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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
f61a2c7d | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a | 20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
39d14dda KC |
21 | ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
22 | ;; 02110-1301, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
9dc62c00 | 28 | ;; c -- Condition code register 33. |
9db1d521 | 29 | ;; d -- Any register from 0 to 15. |
09366c43 AS |
30 | ;; f -- Floating point registers. |
31 | ;; t -- Access registers 36 and 37. | |
d096725d | 32 | ;; G -- Const double zero operand |
9db1d521 HP |
33 | ;; I -- An 8-bit constant (0..255). |
34 | ;; J -- A 12-bit constant (0..4095). | |
35 | ;; K -- A 16-bit constant (-32768..32767). | |
2f7e5a0d | 36 | ;; L -- Value appropriate as displacement. |
f19a9af7 AK |
37 | ;; (0..4095) for short displacement |
38 | ;; (-524288..524287) for long displacement | |
39 | ;; M -- Constant integer with a value of 0x7fffffff. | |
40 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
0dfa6c5e UW |
41 | ;; 0..9,x: number of the part counting from most to least significant |
42 | ;; H,Q: mode of the part | |
43 | ;; D,S,H: mode of the containing operand | |
44 | ;; 0,F: value of the other parts (F - all bits set) | |
2f7e5a0d | 45 | ;; |
f19a9af7 | 46 | ;; The constraint matches if the specified part of a constant |
0dfa6c5e UW |
47 | ;; has a value different from its other parts. If the letter x |
48 | ;; is specified instead of a part number, the constraint matches | |
49 | ;; if there is any single part with non-default value. | |
ec24698e UW |
50 | ;; O -- Multiple letter constraint followed by 1 parameter. |
51 | ;; s: Signed extended immediate value (-2G .. 2G-1). | |
52 | ;; p: Positive extended immediate value (0 .. 4G-1). | |
651a36e3 | 53 | ;; n: Negative extended immediate value (-4G+1 .. -1). |
ec24698e UW |
54 | ;; These constraints do not accept any operand if the machine does |
55 | ;; not provide the extended-immediate facility. | |
11598938 | 56 | ;; P -- Any integer constant that can be loaded without literal pool. |
f19a9af7 AK |
57 | ;; Q -- Memory reference without index register and with short displacement. |
58 | ;; R -- Memory reference with index register and short displacement. | |
59 | ;; S -- Memory reference without index register but with long displacement. | |
60 | ;; T -- Memory reference with index register and long displacement. | |
0dfa6c5e UW |
61 | ;; A -- Multiple letter constraint followed by Q, R, S, or T: |
62 | ;; Offsettable memory reference of type specified by second letter. | |
e221ef54 UW |
63 | ;; B -- Multiple letter constraint followed by Q, R, S, or T: |
64 | ;; Memory reference of the type specified by second letter that | |
65 | ;; does *not* refer to a literal pool entry. | |
f19a9af7 AK |
66 | ;; U -- Pointer with short displacement. |
67 | ;; W -- Pointer with long displacement. | |
68 | ;; Y -- Shift count operand. | |
9db1d521 HP |
69 | ;; |
70 | ;; Special formats used for outputting 390 instructions. | |
71 | ;; | |
f19a9af7 AK |
72 | ;; %C: print opcode suffix for branch condition. |
73 | ;; %D: print opcode suffix for inverse branch condition. | |
74 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 75 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
76 | ;; %O: print only the displacement of a memory reference. |
77 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 78 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
79 | ;; %N: print the second word of a DImode operand. |
80 | ;; %M: print the second word of a TImode operand. | |
da48f5ec AK |
81 | ;; %Y: print shift count operand. |
82 | ;; | |
f19a9af7 | 83 | ;; %b: print integer X as if it's an unsigned byte. |
da48f5ec AK |
84 | ;; %x: print integer X as if it's an unsigned halfword. |
85 | ;; %h: print integer X as if it's a signed halfword. | |
86 | ;; %i: print the first nonzero HImode part of X. | |
87 | ;; %j: print the first HImode part unequal to -1 of X. | |
88 | ;; %k: print the first nonzero SImode part of X. | |
89 | ;; %m: print the first SImode part unequal to -1 of X. | |
90 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
91 | ;; |
92 | ;; We have a special constraint for pattern matching. | |
93 | ;; | |
94 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
95 | ;; | |
9db1d521 | 96 | |
fd3cd001 UW |
97 | ;; |
98 | ;; UNSPEC usage | |
99 | ;; | |
100 | ||
101 | (define_constants | |
10bbf137 UW |
102 | [; Miscellaneous |
103 | (UNSPEC_ROUND 1) | |
5b022de5 | 104 | (UNSPEC_CMPINT 2) |
6fa05db6 | 105 | (UNSPEC_ICM 10) |
10bbf137 UW |
106 | |
107 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
108 | (UNSPEC_LTREL_OFFSET 100) |
109 | (UNSPEC_LTREL_BASE 101) | |
110 | (UNSPEC_GOTENT 110) | |
111 | (UNSPEC_GOT 111) | |
112 | (UNSPEC_GOTOFF 112) | |
113 | (UNSPEC_PLT 113) | |
114 | (UNSPEC_PLTOFF 114) | |
115 | ||
116 | ; Literal pool | |
117 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 118 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 119 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
120 | (UNSPEC_INSN 213) |
121 | (UNSPEC_EXECUTE 214) | |
fd7643fb UW |
122 | |
123 | ; TLS relocation specifiers | |
fd3cd001 UW |
124 | (UNSPEC_TLSGD 500) |
125 | (UNSPEC_TLSLDM 501) | |
126 | (UNSPEC_NTPOFF 502) | |
127 | (UNSPEC_DTPOFF 503) | |
128 | (UNSPEC_GOTNTPOFF 504) | |
129 | (UNSPEC_INDNTPOFF 505) | |
130 | ||
131 | ; TLS support | |
fd3cd001 UW |
132 | (UNSPEC_TLSLDM_NTPOFF 511) |
133 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
134 | |
135 | ; String Functions | |
7b8acc34 | 136 | (UNSPEC_SRST 600) |
742090fc | 137 | (UNSPEC_MVST 601) |
7b8acc34 AK |
138 | |
139 | ; Stack Smashing Protector | |
140 | (UNSPEC_SP_SET 700) | |
141 | (UNSPEC_SP_TEST 701) | |
fd3cd001 UW |
142 | ]) |
143 | ||
144 | ;; | |
145 | ;; UNSPEC_VOLATILE usage | |
146 | ;; | |
147 | ||
148 | (define_constants | |
10bbf137 UW |
149 | [; Blockage |
150 | (UNSPECV_BLOCKAGE 0) | |
151 | ||
2f7e5a0d EC |
152 | ; TPF Support |
153 | (UNSPECV_TPF_PROLOGUE 20) | |
154 | (UNSPECV_TPF_EPILOGUE 21) | |
155 | ||
10bbf137 | 156 | ; Literal pool |
fd7643fb | 157 | (UNSPECV_POOL 200) |
9bb86f41 UW |
158 | (UNSPECV_POOL_SECTION 201) |
159 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 160 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
161 | (UNSPECV_MAIN_POOL 300) |
162 | ||
163 | ; TLS support | |
fd3cd001 | 164 | (UNSPECV_SET_TP 500) |
e0374221 AS |
165 | |
166 | ; Atomic Support | |
167 | (UNSPECV_MB 700) | |
168 | (UNSPECV_CAS 701) | |
fd3cd001 UW |
169 | ]) |
170 | ||
ae156f85 AS |
171 | ;; |
172 | ;; Registers | |
173 | ;; | |
174 | ||
175 | (define_constants | |
176 | [ | |
177 | ; Sibling call register. | |
178 | (SIBCALL_REGNUM 1) | |
179 | ; Literal pool base register. | |
180 | (BASE_REGNUM 13) | |
181 | ; Return address register. | |
182 | (RETURN_REGNUM 14) | |
183 | ; Condition code register. | |
184 | (CC_REGNUM 33) | |
185 | ; Thread local storage pointer register. | |
186 | (TP_REGNUM 36) | |
187 | ]) | |
188 | ||
fd3cd001 | 189 | |
29a74354 UW |
190 | ;; Instruction operand type as used in the Principles of Operation. |
191 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 192 | |
29a74354 UW |
193 | (define_attr "op_type" |
194 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" | |
b628bd8e | 195 | (const_string "NN")) |
9db1d521 | 196 | |
29a74354 | 197 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 198 | |
077dab3b | 199 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 200 | cs,vs,store,sem,idiv, |
ed0e512a | 201 | imulhi,imulsi,imuldi, |
f61a2c7d AK |
202 | branch,jsr,fsimptf,fsimpdf,fsimpsf, |
203 | floadtf,floaddf,floadsf,fstoredf,fstoresf, | |
204 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
205 | ftoi,itof,fsqrttf,fsqrtdf,fsqrtsf, | |
206 | ftrunctf,ftruncdf,other" | |
29a74354 UW |
207 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
208 | (eq_attr "op_type" "SS") (const_string "cs")] | |
209 | (const_string "integer"))) | |
9db1d521 | 210 | |
29a74354 UW |
211 | ;; Another attribute used for scheduling purposes: |
212 | ;; agen: Instruction uses the address generation unit | |
213 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
214 | |
215 | (define_attr "atype" "agen,reg" | |
0101708c AS |
216 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE") |
217 | (const_string "reg") | |
218 | (const_string "agen"))) | |
9db1d521 | 219 | |
9db1d521 HP |
220 | ;; Length in bytes. |
221 | ||
222 | (define_attr "length" "" | |
0101708c AS |
223 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
224 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)] | |
b628bd8e | 225 | (const_int 6))) |
9db1d521 | 226 | |
29a74354 UW |
227 | |
228 | ;; Processor type. This attribute must exactly match the processor_type | |
229 | ;; enumeration in s390.h. The current machine description does not | |
230 | ;; distinguish between g5 and g6, but there are differences between the two | |
231 | ;; CPUs could in theory be modeled. | |
232 | ||
ec24698e | 233 | (define_attr "cpu" "g5,g6,z900,z990,z9_109" |
29a74354 UW |
234 | (const (symbol_ref "s390_tune"))) |
235 | ||
236 | ;; Pipeline description for z900. For lack of anything better, | |
237 | ;; this description is also used for the g5 and g6. | |
238 | (include "2064.md") | |
239 | ||
240 | ;; Pipeline description for z990. | |
241 | (include "2084.md") | |
242 | ||
0bfc3f69 AS |
243 | ;; Predicates |
244 | (include "predicates.md") | |
245 | ||
a8ba31f2 EC |
246 | ;; Other includes |
247 | (include "tpf.md") | |
f52c81dd AS |
248 | |
249 | ;; Macros | |
250 | ||
f61a2c7d | 251 | ;; This mode macro allows floating point patterns to be generated from the |
f5905b37 | 252 | ;; same template. |
f61a2c7d AK |
253 | (define_mode_macro FPR [TF DF SF]) |
254 | (define_mode_macro DSF [DF SF]) | |
f5905b37 | 255 | |
8006eaa6 AS |
256 | ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated |
257 | ;; from the same template. | |
258 | (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI]) | |
259 | ||
9a91a21f | 260 | ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d AS |
261 | ;; from the same template. |
262 | (define_mode_macro GPR [(DI "TARGET_64BIT") SI]) | |
9a91a21f | 263 | (define_mode_macro DSI [DI SI]) |
9db2f16d AS |
264 | |
265 | ;; This mode macro allows :P to be used for patterns that operate on | |
266 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
8006eaa6 | 267 | (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")]) |
9db2f16d AS |
268 | (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
269 | ||
f52c81dd AS |
270 | ;; This mode macro allows the QI and HI patterns to be defined from |
271 | ;; the same template. | |
272 | (define_mode_macro HQI [HI QI]) | |
273 | ||
342cf42b AS |
274 | ;; This mode macro allows the integer patterns to be defined from the |
275 | ;; same template. | |
276 | (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI]) | |
277 | ||
fa77b251 AS |
278 | ;; This macro allows to unify all 'bCOND' expander patterns. |
279 | (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered | |
280 | ordered uneq unlt ungt unle unge ltgt]) | |
281 | ||
9a91a21f AS |
282 | ;; This macro allows to unify all 'sCOND' patterns. |
283 | (define_code_macro SCOND [ltu gtu leu geu]) | |
284 | ||
f337b930 AS |
285 | ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from |
286 | ;; the same template. | |
287 | (define_code_macro SHIFT [ashift lshiftrt]) | |
288 | ||
45d18331 AS |
289 | ;; These macros allow to combine most atomic operations. |
290 | (define_code_macro ATOMIC [and ior xor plus minus mult]) | |
291 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") | |
292 | (plus "add") (minus "sub") (mult "nand")]) | |
293 | ||
f337b930 | 294 | |
f61a2c7d AK |
295 | ;; In FPR templates, a string like "lt<de>br" will expand to "ltxbr" in TFmode, |
296 | ;; "ltdbr" in DFmode, and "ltebr" in SFmode. | |
297 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e")]) | |
f5905b37 | 298 | |
f61a2c7d AK |
299 | ;; In FPR templates, a string like "m<dee>br" will expand to "mxbr" in TFmode, |
300 | ;; "mdbr" in DFmode, and "meebr" in SFmode. | |
301 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee")]) | |
302 | ||
303 | ;; In FPR templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. | |
304 | ;; Likewise for "<RXe>". | |
305 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
306 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
307 | ||
308 | ;; In FPR templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. | |
309 | ;; This is used to disable the memory alternative in TFmode patterns. | |
310 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R")]) | |
f5905b37 | 311 | |
1b48c8cc AS |
312 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
313 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
314 | ;; version only operates on one register. | |
315 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
316 | ||
317 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
318 | ;; version only operates on one register. The DImode version needs an additional | |
319 | ;; register for the assembler output. | |
320 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
321 | ||
f337b930 AS |
322 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in |
323 | ;; 'ashift' and "srdl" in 'lshiftrt'. | |
324 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
325 | ||
326 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
327 | ;; pattern itself and the corresponding function calls. | |
328 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) | |
9a91a21f AS |
329 | |
330 | ;; This attribute handles differences in the instruction 'type' and will result | |
331 | ;; in "RRE" for DImode and "RR" for SImode. | |
332 | (define_mode_attr E [(DI "E") (SI "")]) | |
333 | ||
3298c037 AK |
334 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
335 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
336 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
337 | ||
8006eaa6 AS |
338 | ;; This attribute handles differences in the instruction 'type' and will result |
339 | ;; in "RSE" for TImode and "RS" for DImode. | |
340 | (define_mode_attr TE [(TI "E") (DI "")]) | |
341 | ||
9a91a21f AS |
342 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
343 | ;; and "lcr" in SImode. | |
344 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 345 | |
3298c037 AK |
346 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
347 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
348 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
349 | ;; variant for long displacements. | |
350 | (define_mode_attr y [(DI "g") (SI "y")]) | |
351 | ||
8006eaa6 AS |
352 | ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode |
353 | ;; and "cds" in DImode. | |
354 | (define_mode_attr tg [(TI "g") (DI "")]) | |
355 | ||
2f8f8434 AS |
356 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
357 | ;; and "cfdbr" in SImode. | |
358 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
359 | ||
f52c81dd AS |
360 | ;; ICM mask required to load MODE value into the lowest subreg |
361 | ;; of a SImode register. | |
362 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
363 | ||
f6ee577c AS |
364 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
365 | ;; HImode and "llgc" in QImode. | |
366 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
367 | ||
a1aed706 AS |
368 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
369 | ;; in SImode. | |
370 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
371 | ||
f52c81dd AS |
372 | ;; Maximum unsigned integer that fits in MODE. |
373 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
374 | ||
375 | ||
9db1d521 HP |
376 | ;; |
377 | ;;- Compare instructions. | |
378 | ;; | |
379 | ||
9db2f16d | 380 | (define_expand "cmp<mode>" |
ae156f85 | 381 | [(set (reg:CC CC_REGNUM) |
9db2f16d AS |
382 | (compare:CC (match_operand:GPR 0 "register_operand" "") |
383 | (match_operand:GPR 1 "general_operand" "")))] | |
9db1d521 | 384 | "" |
9db1d521 HP |
385 | { |
386 | s390_compare_op0 = operands[0]; | |
387 | s390_compare_op1 = operands[1]; | |
388 | DONE; | |
10bbf137 | 389 | }) |
9db1d521 | 390 | |
f5905b37 | 391 | (define_expand "cmp<mode>" |
ae156f85 | 392 | [(set (reg:CC CC_REGNUM) |
f5905b37 AS |
393 | (compare:CC (match_operand:FPR 0 "register_operand" "") |
394 | (match_operand:FPR 1 "general_operand" "")))] | |
9db1d521 | 395 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
396 | { |
397 | s390_compare_op0 = operands[0]; | |
398 | s390_compare_op1 = operands[1]; | |
399 | DONE; | |
10bbf137 | 400 | }) |
9db1d521 HP |
401 | |
402 | ||
07893d4f | 403 | ; Test-under-Mask instructions |
9db1d521 | 404 | |
07893d4f | 405 | (define_insn "*tmqi_mem" |
ae156f85 | 406 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
407 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
408 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
409 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 410 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 411 | "@ |
fc0ea003 UW |
412 | tm\t%S0,%b1 |
413 | tmy\t%S0,%b1" | |
d3632d41 | 414 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 415 | |
05b9aaaa | 416 | (define_insn "*tmdi_reg" |
ae156f85 | 417 | [(set (reg CC_REGNUM) |
f19a9af7 | 418 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 419 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
420 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
421 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa | 422 | "TARGET_64BIT |
3ed99cc9 | 423 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
424 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
425 | "@ | |
426 | tmhh\t%0,%i1 | |
427 | tmhl\t%0,%i1 | |
428 | tmlh\t%0,%i1 | |
429 | tmll\t%0,%i1" | |
05b9aaaa UW |
430 | [(set_attr "op_type" "RI")]) |
431 | ||
432 | (define_insn "*tmsi_reg" | |
ae156f85 | 433 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
434 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
435 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
436 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 437 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
438 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
439 | "@ | |
440 | tmh\t%0,%i1 | |
441 | tml\t%0,%i1" | |
05b9aaaa UW |
442 | [(set_attr "op_type" "RI")]) |
443 | ||
f52c81dd | 444 | (define_insn "*tm<mode>_full" |
ae156f85 | 445 | [(set (reg CC_REGNUM) |
f52c81dd AS |
446 | (compare (match_operand:HQI 0 "register_operand" "d") |
447 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 448 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 449 | "tml\t%0,<max_uint>" |
07893d4f | 450 | [(set_attr "op_type" "RI")]) |
9db1d521 | 451 | |
07893d4f | 452 | |
08a5aaa2 | 453 | ; |
07893d4f | 454 | ; Load-and-Test instructions |
08a5aaa2 AS |
455 | ; |
456 | ||
c0220ea4 | 457 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
458 | |
459 | (define_insn "*tstdi_sign" | |
ae156f85 | 460 | [(set (reg CC_REGNUM) |
07893d4f UW |
461 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
462 | (const_int 32)) (const_int 32)) | |
463 | (match_operand:DI 1 "const0_operand" ""))) | |
464 | (set (match_operand:DI 2 "register_operand" "=d") | |
465 | (sign_extend:DI (match_dup 0)))] | |
466 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 467 | "ltgfr\t%2,%0" |
07893d4f UW |
468 | [(set_attr "op_type" "RRE")]) |
469 | ||
43a09b63 | 470 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 471 | (define_insn "*tst<mode>_extimm" |
ec24698e | 472 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
473 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m") |
474 | (match_operand:GPR 1 "const0_operand" ""))) | |
475 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 476 | (match_dup 0))] |
08a5aaa2 | 477 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 478 | "@ |
08a5aaa2 AS |
479 | lt<g>r\t%2,%0 |
480 | lt<g>\t%2,%0" | |
481 | [(set_attr "op_type" "RR<E>,RXY")]) | |
ec24698e | 482 | |
43a09b63 | 483 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 484 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 485 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
486 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,m") |
487 | (match_operand:GPR 1 "const0_operand" ""))) | |
488 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
489 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 490 | "@ |
08a5aaa2 AS |
491 | lt<g>r\t%0,%0 |
492 | lt<g>\t%2,%0" | |
493 | [(set_attr "op_type" "RR<E>,RXY")]) | |
ec24698e | 494 | |
07893d4f | 495 | (define_insn "*tstdi" |
ae156f85 | 496 | [(set (reg CC_REGNUM) |
07893d4f UW |
497 | (compare (match_operand:DI 0 "register_operand" "d") |
498 | (match_operand:DI 1 "const0_operand" ""))) | |
499 | (set (match_operand:DI 2 "register_operand" "=d") | |
500 | (match_dup 0))] | |
ec24698e | 501 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" |
d40c829f | 502 | "ltgr\t%2,%0" |
07893d4f | 503 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 504 | |
07893d4f | 505 | (define_insn "*tstsi" |
ae156f85 | 506 | [(set (reg CC_REGNUM) |
d3632d41 | 507 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 508 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 509 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 510 | (match_dup 0))] |
ec24698e | 511 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 512 | "@ |
d40c829f | 513 | ltr\t%2,%0 |
fc0ea003 UW |
514 | icm\t%2,15,%S0 |
515 | icmy\t%2,15,%S0" | |
d3632d41 | 516 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 517 | |
07893d4f | 518 | (define_insn "*tstsi_cconly" |
ae156f85 | 519 | [(set (reg CC_REGNUM) |
d3632d41 | 520 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 521 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 522 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
523 | "s390_match_ccmode(insn, CCSmode)" |
524 | "@ | |
d40c829f | 525 | ltr\t%0,%0 |
fc0ea003 UW |
526 | icm\t%2,15,%S0 |
527 | icmy\t%2,15,%S0" | |
d3632d41 | 528 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 529 | |
08a5aaa2 AS |
530 | (define_insn "*tstdi_cconly_31" |
531 | [(set (reg CC_REGNUM) | |
532 | (compare (match_operand:DI 0 "register_operand" "d") | |
533 | (match_operand:DI 1 "const0_operand" "")))] | |
534 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
535 | "srda\t%0,0" | |
536 | [(set_attr "op_type" "RS") | |
537 | (set_attr "atype" "reg")]) | |
538 | ||
43a09b63 | 539 | ; ltr, ltgr |
08a5aaa2 | 540 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 541 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
542 | (compare (match_operand:GPR 0 "register_operand" "d") |
543 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 544 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 AS |
545 | "lt<g>r\t%0,%0" |
546 | [(set_attr "op_type" "RR<E>")]) | |
547 | ||
c0220ea4 | 548 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 549 | |
f52c81dd | 550 | (define_insn "*tst<mode>CCT" |
ae156f85 | 551 | [(set (reg CC_REGNUM) |
f52c81dd AS |
552 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
553 | (match_operand:HQI 1 "const0_operand" ""))) | |
554 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
555 | (match_dup 0))] |
556 | "s390_match_ccmode(insn, CCTmode)" | |
557 | "@ | |
f52c81dd AS |
558 | icm\t%2,<icm_lo>,%S0 |
559 | icmy\t%2,<icm_lo>,%S0 | |
560 | tml\t%0,<max_uint>" | |
d3632d41 | 561 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
562 | |
563 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 564 | [(set (reg CC_REGNUM) |
d3632d41 | 565 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 566 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 567 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
568 | "s390_match_ccmode(insn, CCTmode)" |
569 | "@ | |
fc0ea003 UW |
570 | icm\t%2,3,%S0 |
571 | icmy\t%2,3,%S0 | |
d40c829f | 572 | tml\t%0,65535" |
d3632d41 | 573 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 574 | |
3af97654 | 575 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 576 | [(set (reg CC_REGNUM) |
d3632d41 | 577 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
578 | (match_operand:QI 1 "const0_operand" "")))] |
579 | "s390_match_ccmode(insn, CCTmode)" | |
580 | "@ | |
fc0ea003 UW |
581 | cli\t%S0,0 |
582 | cliy\t%S0,0 | |
d40c829f | 583 | tml\t%0,255" |
d3632d41 | 584 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 585 | |
f52c81dd | 586 | (define_insn "*tst<mode>" |
ae156f85 | 587 | [(set (reg CC_REGNUM) |
f52c81dd AS |
588 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
589 | (match_operand:HQI 1 "const0_operand" ""))) | |
590 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
591 | (match_dup 0))] |
592 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 593 | "@ |
f52c81dd AS |
594 | icm\t%2,<icm_lo>,%S0 |
595 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 | 596 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 597 | |
f52c81dd | 598 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 599 | [(set (reg CC_REGNUM) |
f52c81dd AS |
600 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
601 | (match_operand:HQI 1 "const0_operand" ""))) | |
602 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 603 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 604 | "@ |
f52c81dd AS |
605 | icm\t%2,<icm_lo>,%S0 |
606 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 UW |
607 | [(set_attr "op_type" "RS,RSY")]) |
608 | ||
9db1d521 | 609 | |
575f7c2b UW |
610 | ; Compare (equality) instructions |
611 | ||
612 | (define_insn "*cmpdi_cct" | |
ae156f85 | 613 | [(set (reg CC_REGNUM) |
ec24698e UW |
614 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
615 | (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))] | |
e221ef54 | 616 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" |
575f7c2b UW |
617 | "@ |
618 | cgr\t%0,%1 | |
f4f41b4e | 619 | cghi\t%0,%h1 |
ec24698e | 620 | cgfi\t%0,%1 |
575f7c2b | 621 | cg\t%0,%1 |
19b63d8e | 622 | #" |
ec24698e | 623 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")]) |
575f7c2b UW |
624 | |
625 | (define_insn "*cmpsi_cct" | |
ae156f85 | 626 | [(set (reg CC_REGNUM) |
ec24698e UW |
627 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
628 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 629 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
630 | "@ |
631 | cr\t%0,%1 | |
f4f41b4e | 632 | chi\t%0,%h1 |
ec24698e | 633 | cfi\t%0,%1 |
575f7c2b UW |
634 | c\t%0,%1 |
635 | cy\t%0,%1 | |
19b63d8e | 636 | #" |
ec24698e | 637 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")]) |
575f7c2b UW |
638 | |
639 | ||
07893d4f | 640 | ; Compare (signed) instructions |
4023fb28 | 641 | |
07893d4f | 642 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 643 | [(set (reg CC_REGNUM) |
07893d4f UW |
644 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
645 | (match_operand:DI 0 "register_operand" "d,d")))] | |
646 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 647 | "@ |
d40c829f UW |
648 | cgfr\t%0,%1 |
649 | cgf\t%0,%1" | |
d3632d41 | 650 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 651 | |
07893d4f | 652 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 653 | [(set (reg CC_REGNUM) |
d3632d41 UW |
654 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
655 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 656 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 657 | "@ |
d40c829f UW |
658 | ch\t%0,%1 |
659 | chy\t%0,%1" | |
d3632d41 | 660 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 661 | |
43a09b63 | 662 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg |
3298c037 | 663 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 664 | [(set (reg CC_REGNUM) |
3298c037 AK |
665 | (compare (match_operand:GPR 0 "register_operand" "d,d,d,d,d") |
666 | (match_operand:GPR 1 "general_operand" "d,K,Os,R,T")))] | |
9db1d521 | 667 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 668 | "@ |
3298c037 AK |
669 | c<g>r\t%0,%1 |
670 | c<g>hi\t%0,%h1 | |
671 | c<g>fi\t%0,%1 | |
672 | c<g>\t%0,%1 | |
673 | c<y>\t%0,%1" | |
674 | [(set_attr "op_type" "RR<E>,RI,RIL,RX<Y>,RXY")]) | |
c7453384 | 675 | |
07893d4f UW |
676 | |
677 | ; Compare (unsigned) instructions | |
9db1d521 | 678 | |
07893d4f | 679 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 680 | [(set (reg CC_REGNUM) |
07893d4f UW |
681 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
682 | (match_operand:DI 0 "register_operand" "d,d")))] | |
575f7c2b | 683 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 684 | "@ |
d40c829f UW |
685 | clgfr\t%0,%1 |
686 | clgf\t%0,%1" | |
d3632d41 | 687 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 688 | |
07893d4f | 689 | (define_insn "*cmpdi_ccu" |
ae156f85 | 690 | [(set (reg CC_REGNUM) |
ec24698e UW |
691 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ") |
692 | (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))] | |
e221ef54 | 693 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" |
07893d4f | 694 | "@ |
d40c829f | 695 | clgr\t%0,%1 |
ec24698e | 696 | clgfi\t%0,%1 |
575f7c2b | 697 | clg\t%0,%1 |
e221ef54 | 698 | # |
19b63d8e | 699 | #" |
ec24698e | 700 | [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")]) |
9db1d521 | 701 | |
07893d4f | 702 | (define_insn "*cmpsi_ccu" |
ae156f85 | 703 | [(set (reg CC_REGNUM) |
ec24698e UW |
704 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ") |
705 | (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))] | |
e221ef54 | 706 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 707 | "@ |
d40c829f | 708 | clr\t%0,%1 |
ec24698e | 709 | clfi\t%0,%o1 |
d40c829f | 710 | cl\t%0,%1 |
575f7c2b | 711 | cly\t%0,%1 |
e221ef54 | 712 | # |
19b63d8e | 713 | #" |
ec24698e | 714 | [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")]) |
9db1d521 | 715 | |
07893d4f | 716 | (define_insn "*cmphi_ccu" |
ae156f85 | 717 | [(set (reg CC_REGNUM) |
e221ef54 UW |
718 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") |
719 | (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] | |
575f7c2b | 720 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 721 | && !register_operand (operands[1], HImode)" |
d3632d41 | 722 | "@ |
fc0ea003 UW |
723 | clm\t%0,3,%S1 |
724 | clmy\t%0,3,%S1 | |
e221ef54 | 725 | # |
19b63d8e | 726 | #" |
e221ef54 | 727 | [(set_attr "op_type" "RS,RSY,SS,SS")]) |
9db1d521 HP |
728 | |
729 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 730 | [(set (reg CC_REGNUM) |
e221ef54 UW |
731 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
732 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 733 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 734 | && !register_operand (operands[1], QImode)" |
d3632d41 | 735 | "@ |
fc0ea003 UW |
736 | clm\t%0,1,%S1 |
737 | clmy\t%0,1,%S1 | |
738 | cli\t%S0,%b1 | |
739 | cliy\t%S0,%b1 | |
e221ef54 | 740 | # |
19b63d8e | 741 | #" |
e221ef54 | 742 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) |
9db1d521 HP |
743 | |
744 | ||
19b63d8e UW |
745 | ; Block compare (CLC) instruction patterns. |
746 | ||
747 | (define_insn "*clc" | |
ae156f85 | 748 | [(set (reg CC_REGNUM) |
d4f52f0e | 749 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
750 | (match_operand:BLK 1 "memory_operand" "Q"))) |
751 | (use (match_operand 2 "const_int_operand" "n"))] | |
752 | "s390_match_ccmode (insn, CCUmode) | |
753 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 754 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 755 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
756 | |
757 | (define_split | |
ae156f85 | 758 | [(set (reg CC_REGNUM) |
19b63d8e UW |
759 | (compare (match_operand 0 "memory_operand" "") |
760 | (match_operand 1 "memory_operand" "")))] | |
761 | "reload_completed | |
762 | && s390_match_ccmode (insn, CCUmode) | |
763 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
764 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
765 | [(parallel | |
766 | [(set (match_dup 0) (match_dup 1)) | |
767 | (use (match_dup 2))])] | |
768 | { | |
769 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
770 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
771 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
772 | ||
773 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
774 | operands[0], operands[1]); | |
775 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
776 | }) | |
777 | ||
778 | ||
f5905b37 | 779 | ; (DF|SF) instructions |
9db1d521 | 780 | |
43a09b63 | 781 | ; ltxbr, ltdbr, ltebr |
f5905b37 | 782 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 783 | [(set (reg CC_REGNUM) |
f5905b37 AS |
784 | (compare (match_operand:FPR 0 "register_operand" "f") |
785 | (match_operand:FPR 1 "const0_operand" "")))] | |
9db1d521 | 786 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 787 | "lt<xde>br\t%0,%0" |
077dab3b | 788 | [(set_attr "op_type" "RRE") |
f5905b37 | 789 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 790 | |
43a09b63 | 791 | ; ltxr, ltdr, lter |
f5905b37 | 792 | (define_insn "*cmp<mode>_ccs_0_ibm" |
ae156f85 | 793 | [(set (reg CC_REGNUM) |
f5905b37 AS |
794 | (compare (match_operand:FPR 0 "register_operand" "f") |
795 | (match_operand:FPR 1 "const0_operand" "")))] | |
9db1d521 | 796 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f61a2c7d AK |
797 | "lt<xde>r\t%0,%0" |
798 | [(set_attr "op_type" "<RRe>") | |
f5905b37 | 799 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 800 | |
43a09b63 | 801 | ; cxbr, cdbr, cebr, cxb, cdb, ceb |
f5905b37 | 802 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 803 | [(set (reg CC_REGNUM) |
f5905b37 | 804 | (compare (match_operand:FPR 0 "register_operand" "f,f") |
f61a2c7d | 805 | (match_operand:FPR 1 "general_operand" "f,<Rf>")))] |
9db1d521 HP |
806 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
807 | "@ | |
f61a2c7d AK |
808 | c<xde>br\t%0,%1 |
809 | c<xde>b\t%0,%1" | |
077dab3b | 810 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 811 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 812 | |
43a09b63 | 813 | ; cxr, cdr, cer, cx, cd, ce |
f5905b37 | 814 | (define_insn "*cmp<mode>_ccs_ibm" |
ae156f85 | 815 | [(set (reg CC_REGNUM) |
f5905b37 | 816 | (compare (match_operand:FPR 0 "register_operand" "f,f") |
f61a2c7d | 817 | (match_operand:FPR 1 "general_operand" "f,<Rf>")))] |
9db1d521 HP |
818 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
819 | "@ | |
f61a2c7d AK |
820 | c<xde>r\t%0,%1 |
821 | c<xde>\t%0,%1" | |
822 | [(set_attr "op_type" "<RRe>,<RXe>") | |
f5905b37 | 823 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
824 | |
825 | ||
826 | ;; | |
827 | ;;- Move instructions. | |
828 | ;; | |
829 | ||
830 | ; | |
831 | ; movti instruction pattern(s). | |
832 | ; | |
833 | ||
834 | (define_insn "movti" | |
d3632d41 | 835 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
11598938 | 836 | (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))] |
9db1d521 | 837 | "TARGET_64BIT" |
4023fb28 | 838 | "@ |
fc0ea003 UW |
839 | lmg\t%0,%N0,%S1 |
840 | stmg\t%1,%N1,%S0 | |
4023fb28 | 841 | # |
9b7c75b9 | 842 | # |
19b63d8e | 843 | #" |
b628bd8e UW |
844 | [(set_attr "op_type" "RSY,RSY,*,*,SS") |
845 | (set_attr "type" "lm,stm,*,*,*")]) | |
4023fb28 UW |
846 | |
847 | (define_split | |
848 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
849 | (match_operand:TI 1 "general_operand" ""))] | |
850 | "TARGET_64BIT && reload_completed | |
dc65c307 | 851 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
852 | [(set (match_dup 2) (match_dup 4)) |
853 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 854 | { |
dc65c307 UW |
855 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
856 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
857 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
858 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
859 | }) | |
860 | ||
861 | (define_split | |
862 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
863 | (match_operand:TI 1 "general_operand" ""))] | |
864 | "TARGET_64BIT && reload_completed | |
865 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
866 | [(set (match_dup 2) (match_dup 4)) | |
867 | (set (match_dup 3) (match_dup 5))] | |
868 | { | |
869 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
870 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
871 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
872 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
873 | }) | |
4023fb28 UW |
874 | |
875 | (define_split | |
876 | [(set (match_operand:TI 0 "register_operand" "") | |
877 | (match_operand:TI 1 "memory_operand" ""))] | |
878 | "TARGET_64BIT && reload_completed | |
879 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 880 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
881 | { |
882 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
883 | s390_load_address (addr, XEXP (operands[1], 0)); | |
884 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
885 | }) |
886 | ||
887 | (define_expand "reload_outti" | |
9c3c3dcc | 888 | [(parallel [(match_operand:TI 0 "" "") |
dc65c307 UW |
889 | (match_operand:TI 1 "register_operand" "d") |
890 | (match_operand:DI 2 "register_operand" "=&a")])] | |
891 | "TARGET_64BIT" | |
892 | { | |
9c3c3dcc | 893 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 894 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
895 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
896 | emit_move_insn (operands[0], operands[1]); | |
897 | DONE; | |
898 | }) | |
9db1d521 HP |
899 | |
900 | ; | |
901 | ; movdi instruction pattern(s). | |
902 | ; | |
903 | ||
9db1d521 HP |
904 | (define_expand "movdi" |
905 | [(set (match_operand:DI 0 "general_operand" "") | |
906 | (match_operand:DI 1 "general_operand" ""))] | |
907 | "" | |
9db1d521 | 908 | { |
fd3cd001 | 909 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
910 | if (TARGET_64BIT |
911 | && (SYMBOLIC_CONST (operands[1]) | |
912 | || (GET_CODE (operands[1]) == PLUS | |
913 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
914 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 915 | emit_symbolic_move (operands); |
10bbf137 | 916 | }) |
9db1d521 | 917 | |
4023fb28 UW |
918 | (define_insn "*movdi_larl" |
919 | [(set (match_operand:DI 0 "register_operand" "=d") | |
920 | (match_operand:DI 1 "larl_operand" "X"))] | |
921 | "TARGET_64BIT | |
8e509cf9 | 922 | && !FP_REG_P (operands[0])" |
d40c829f | 923 | "larl\t%0,%1" |
4023fb28 | 924 | [(set_attr "op_type" "RIL") |
077dab3b | 925 | (set_attr "type" "larl")]) |
4023fb28 | 926 | |
ec24698e UW |
927 | (define_insn "*movdi_64extimm" |
928 | [(set (match_operand:DI 0 "nonimmediate_operand" | |
929 | "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") | |
930 | (match_operand:DI 1 "general_operand" | |
931 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] | |
932 | "TARGET_64BIT && TARGET_EXTIMM" | |
933 | "@ | |
934 | lghi\t%0,%h1 | |
935 | llihh\t%0,%i1 | |
936 | llihl\t%0,%i1 | |
937 | llilh\t%0,%i1 | |
938 | llill\t%0,%i1 | |
939 | lgfi\t%0,%1 | |
940 | llihf\t%0,%k1 | |
941 | llilf\t%0,%k1 | |
942 | lay\t%0,%a1 | |
943 | lgr\t%0,%1 | |
944 | lg\t%0,%1 | |
945 | stg\t%1,%0 | |
946 | ldr\t%0,%1 | |
947 | ld\t%0,%1 | |
948 | ldy\t%0,%1 | |
949 | std\t%1,%0 | |
950 | stdy\t%1,%0 | |
951 | # | |
952 | # | |
953 | stam\t%1,%N1,%S0 | |
954 | lam\t%0,%N0,%S1 | |
955 | #" | |
956 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY, | |
957 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
958 | (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store, | |
959 | floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")]) | |
960 | ||
9db1d521 | 961 | (define_insn "*movdi_64" |
2f7e5a0d | 962 | [(set (match_operand:DI 0 "nonimmediate_operand" |
c5aa1d12 | 963 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 964 | (match_operand:DI 1 "general_operand" |
c5aa1d12 | 965 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
ec24698e | 966 | "TARGET_64BIT && !TARGET_EXTIMM" |
9db1d521 | 967 | "@ |
f19a9af7 AK |
968 | lghi\t%0,%h1 |
969 | llihh\t%0,%i1 | |
970 | llihl\t%0,%i1 | |
971 | llilh\t%0,%i1 | |
972 | llill\t%0,%i1 | |
973 | lay\t%0,%a1 | |
d40c829f UW |
974 | lgr\t%0,%1 |
975 | lg\t%0,%1 | |
976 | stg\t%1,%0 | |
977 | ldr\t%0,%1 | |
978 | ld\t%0,%1 | |
979 | ldy\t%0,%1 | |
980 | std\t%1,%0 | |
981 | stdy\t%1,%0 | |
c5aa1d12 UW |
982 | # |
983 | # | |
984 | stam\t%1,%N1,%S0 | |
985 | lam\t%0,%N0,%S1 | |
19b63d8e | 986 | #" |
b628bd8e UW |
987 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, |
988 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
989 | (set_attr "type" "*,*,*,*,*,la,lr,load,store, | |
cfdb984b | 990 | floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")]) |
c5aa1d12 UW |
991 | |
992 | (define_split | |
993 | [(set (match_operand:DI 0 "register_operand" "") | |
994 | (match_operand:DI 1 "register_operand" ""))] | |
995 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
996 | [(set (match_dup 2) (match_dup 3)) | |
997 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
998 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
999 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1000 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1001 | ||
1002 | (define_split | |
1003 | [(set (match_operand:DI 0 "register_operand" "") | |
1004 | (match_operand:DI 1 "register_operand" ""))] | |
1005 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1006 | && dead_or_set_p (insn, operands[1])" | |
1007 | [(set (match_dup 3) (match_dup 2)) | |
1008 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1009 | (set (match_dup 4) (match_dup 2))] | |
1010 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1011 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1012 | ||
1013 | (define_split | |
1014 | [(set (match_operand:DI 0 "register_operand" "") | |
1015 | (match_operand:DI 1 "register_operand" ""))] | |
1016 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1017 | && !dead_or_set_p (insn, operands[1])" | |
1018 | [(set (match_dup 3) (match_dup 2)) | |
1019 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1020 | (set (match_dup 4) (match_dup 2)) | |
1021 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1022 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1023 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1024 | |
1025 | (define_insn "*movdi_31" | |
c4d50129 | 1026 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q") |
11598938 | 1027 | (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))] |
9db1d521 | 1028 | "!TARGET_64BIT" |
4023fb28 | 1029 | "@ |
fc0ea003 | 1030 | lm\t%0,%N0,%S1 |
c4d50129 | 1031 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1032 | stm\t%1,%N1,%S0 |
c4d50129 | 1033 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1034 | # |
1035 | # | |
d40c829f UW |
1036 | ldr\t%0,%1 |
1037 | ld\t%0,%1 | |
1038 | ldy\t%0,%1 | |
1039 | std\t%1,%0 | |
1040 | stdy\t%1,%0 | |
19b63d8e | 1041 | #" |
c4d50129 AK |
1042 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS") |
1043 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")]) | |
4023fb28 UW |
1044 | |
1045 | (define_split | |
1046 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1047 | (match_operand:DI 1 "general_operand" ""))] | |
1048 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1049 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1050 | [(set (match_dup 2) (match_dup 4)) |
1051 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1052 | { |
dc65c307 UW |
1053 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1054 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1055 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1056 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1057 | }) | |
1058 | ||
1059 | (define_split | |
1060 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1061 | (match_operand:DI 1 "general_operand" ""))] | |
1062 | "!TARGET_64BIT && reload_completed | |
1063 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1064 | [(set (match_dup 2) (match_dup 4)) | |
1065 | (set (match_dup 3) (match_dup 5))] | |
1066 | { | |
1067 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1068 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1069 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1070 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1071 | }) | |
9db1d521 | 1072 | |
4023fb28 UW |
1073 | (define_split |
1074 | [(set (match_operand:DI 0 "register_operand" "") | |
1075 | (match_operand:DI 1 "memory_operand" ""))] | |
1076 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1077 | && !FP_REG_P (operands[0]) |
4023fb28 | 1078 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1079 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1080 | { |
1081 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1082 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1083 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1084 | }) |
1085 | ||
1086 | (define_expand "reload_outdi" | |
9c3c3dcc | 1087 | [(parallel [(match_operand:DI 0 "" "") |
dc65c307 UW |
1088 | (match_operand:DI 1 "register_operand" "d") |
1089 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1090 | "!TARGET_64BIT" | |
1091 | { | |
9c3c3dcc | 1092 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1093 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1094 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1095 | emit_move_insn (operands[0], operands[1]); | |
1096 | DONE; | |
1097 | }) | |
9db1d521 | 1098 | |
84817c5d UW |
1099 | (define_peephole2 |
1100 | [(set (match_operand:DI 0 "register_operand" "") | |
1101 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1102 | "TARGET_64BIT | |
1103 | && !FP_REG_P (operands[0]) | |
1104 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1105 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1106 | && get_pool_mode (operands[1]) == DImode | |
1107 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1108 | [(set (match_dup 0) (match_dup 2))] | |
1109 | "operands[2] = get_pool_constant (operands[1]);") | |
1110 | ||
7bdff56f UW |
1111 | (define_insn "*la_64" |
1112 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1113 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1114 | "TARGET_64BIT" | |
1115 | "@ | |
1116 | la\t%0,%a1 | |
1117 | lay\t%0,%a1" | |
1118 | [(set_attr "op_type" "RX,RXY") | |
1119 | (set_attr "type" "la")]) | |
1120 | ||
1121 | (define_peephole2 | |
1122 | [(parallel | |
1123 | [(set (match_operand:DI 0 "register_operand" "") | |
1124 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1125 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1126 | "TARGET_64BIT |
e1d5ee28 | 1127 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1128 | [(set (match_dup 0) (match_dup 1))] |
1129 | "") | |
1130 | ||
1131 | (define_peephole2 | |
1132 | [(set (match_operand:DI 0 "register_operand" "") | |
1133 | (match_operand:DI 1 "register_operand" "")) | |
1134 | (parallel | |
1135 | [(set (match_dup 0) | |
1136 | (plus:DI (match_dup 0) | |
1137 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1138 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1139 | "TARGET_64BIT |
1140 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1141 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1142 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1143 | "") | |
1144 | ||
1145 | (define_expand "reload_indi" | |
1146 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1147 | (match_operand:DI 1 "s390_plus_operand" "") | |
1148 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1149 | "TARGET_64BIT" | |
1150 | { | |
1151 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1152 | DONE; | |
1153 | }) | |
1154 | ||
9db1d521 HP |
1155 | ; |
1156 | ; movsi instruction pattern(s). | |
1157 | ; | |
1158 | ||
9db1d521 HP |
1159 | (define_expand "movsi" |
1160 | [(set (match_operand:SI 0 "general_operand" "") | |
1161 | (match_operand:SI 1 "general_operand" ""))] | |
1162 | "" | |
9db1d521 | 1163 | { |
fd3cd001 | 1164 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1165 | if (!TARGET_64BIT |
1166 | && (SYMBOLIC_CONST (operands[1]) | |
1167 | || (GET_CODE (operands[1]) == PLUS | |
1168 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1169 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1170 | emit_symbolic_move (operands); |
10bbf137 | 1171 | }) |
9db1d521 | 1172 | |
9e8327e3 UW |
1173 | (define_insn "*movsi_larl" |
1174 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1175 | (match_operand:SI 1 "larl_operand" "X"))] | |
1176 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1177 | && !FP_REG_P (operands[0])" | |
1178 | "larl\t%0,%1" | |
1179 | [(set_attr "op_type" "RIL") | |
1180 | (set_attr "type" "larl")]) | |
1181 | ||
f19a9af7 | 1182 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1183 | [(set (match_operand:SI 0 "nonimmediate_operand" |
ec24698e | 1184 | "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 1185 | (match_operand:SI 1 "general_operand" |
ec24698e | 1186 | "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
f19a9af7 | 1187 | "TARGET_ZARCH" |
9db1d521 | 1188 | "@ |
f19a9af7 AK |
1189 | lhi\t%0,%h1 |
1190 | llilh\t%0,%i1 | |
1191 | llill\t%0,%i1 | |
ec24698e | 1192 | iilf\t%0,%o1 |
f19a9af7 | 1193 | lay\t%0,%a1 |
d40c829f UW |
1194 | lr\t%0,%1 |
1195 | l\t%0,%1 | |
1196 | ly\t%0,%1 | |
1197 | st\t%1,%0 | |
1198 | sty\t%1,%0 | |
1199 | ler\t%0,%1 | |
1200 | le\t%0,%1 | |
1201 | ley\t%0,%1 | |
1202 | ste\t%1,%0 | |
1203 | stey\t%1,%0 | |
c5aa1d12 UW |
1204 | ear\t%0,%1 |
1205 | sar\t%0,%1 | |
1206 | stam\t%1,%1,%S0 | |
1207 | lam\t%0,%0,%S1 | |
19b63d8e | 1208 | #" |
ec24698e | 1209 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY, |
b628bd8e | 1210 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") |
ec24698e | 1211 | (set_attr "type" "*,*,*,*,la,lr,load,load,store,store, |
cfdb984b | 1212 | floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")]) |
f19a9af7 AK |
1213 | |
1214 | (define_insn "*movsi_esa" | |
c5aa1d12 UW |
1215 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") |
1216 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))] | |
f19a9af7 AK |
1217 | "!TARGET_ZARCH" |
1218 | "@ | |
1219 | lhi\t%0,%h1 | |
1220 | lr\t%0,%1 | |
1221 | l\t%0,%1 | |
1222 | st\t%1,%0 | |
1223 | ler\t%0,%1 | |
1224 | le\t%0,%1 | |
1225 | ste\t%1,%0 | |
c5aa1d12 UW |
1226 | ear\t%0,%1 |
1227 | sar\t%0,%1 | |
1228 | stam\t%1,%1,%S0 | |
1229 | lam\t%0,%0,%S1 | |
19b63d8e | 1230 | #" |
c5aa1d12 | 1231 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") |
cfdb984b | 1232 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")]) |
9db1d521 | 1233 | |
84817c5d UW |
1234 | (define_peephole2 |
1235 | [(set (match_operand:SI 0 "register_operand" "") | |
1236 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1237 | "!FP_REG_P (operands[0]) | |
1238 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1239 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1240 | && get_pool_mode (operands[1]) == SImode | |
1241 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1242 | [(set (match_dup 0) (match_dup 2))] | |
1243 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1244 | |
7bdff56f UW |
1245 | (define_insn "*la_31" |
1246 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1247 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1248 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1249 | "@ | |
1250 | la\t%0,%a1 | |
1251 | lay\t%0,%a1" | |
1252 | [(set_attr "op_type" "RX,RXY") | |
1253 | (set_attr "type" "la")]) | |
1254 | ||
1255 | (define_peephole2 | |
1256 | [(parallel | |
1257 | [(set (match_operand:SI 0 "register_operand" "") | |
1258 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1259 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1260 | "!TARGET_64BIT |
e1d5ee28 | 1261 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1262 | [(set (match_dup 0) (match_dup 1))] |
1263 | "") | |
1264 | ||
1265 | (define_peephole2 | |
1266 | [(set (match_operand:SI 0 "register_operand" "") | |
1267 | (match_operand:SI 1 "register_operand" "")) | |
1268 | (parallel | |
1269 | [(set (match_dup 0) | |
1270 | (plus:SI (match_dup 0) | |
1271 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1272 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1273 | "!TARGET_64BIT |
1274 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1275 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1276 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1277 | "") | |
1278 | ||
1279 | (define_insn "*la_31_and" | |
1280 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1281 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1282 | (const_int 2147483647)))] | |
1283 | "!TARGET_64BIT" | |
1284 | "@ | |
1285 | la\t%0,%a1 | |
1286 | lay\t%0,%a1" | |
1287 | [(set_attr "op_type" "RX,RXY") | |
1288 | (set_attr "type" "la")]) | |
1289 | ||
1290 | (define_insn_and_split "*la_31_and_cc" | |
1291 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1292 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1293 | (const_int 2147483647))) | |
ae156f85 | 1294 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1295 | "!TARGET_64BIT" |
1296 | "#" | |
1297 | "&& reload_completed" | |
1298 | [(set (match_dup 0) | |
1299 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1300 | "" | |
1301 | [(set_attr "op_type" "RX") | |
1302 | (set_attr "type" "la")]) | |
1303 | ||
1304 | (define_insn "force_la_31" | |
1305 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1306 | (match_operand:QI 1 "address_operand" "U,W")) | |
1307 | (use (const_int 0))] | |
1308 | "!TARGET_64BIT" | |
1309 | "@ | |
1310 | la\t%0,%a1 | |
1311 | lay\t%0,%a1" | |
1312 | [(set_attr "op_type" "RX") | |
1313 | (set_attr "type" "la")]) | |
1314 | ||
1315 | (define_expand "reload_insi" | |
1316 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1317 | (match_operand:SI 1 "s390_plus_operand" "") | |
1318 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1319 | "!TARGET_64BIT" | |
1320 | { | |
1321 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1322 | DONE; | |
1323 | }) | |
1324 | ||
9db1d521 HP |
1325 | ; |
1326 | ; movhi instruction pattern(s). | |
1327 | ; | |
1328 | ||
02ed3c5e UW |
1329 | (define_expand "movhi" |
1330 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1331 | (match_operand:HI 1 "general_operand" ""))] | |
1332 | "" | |
1333 | { | |
2f7e5a0d | 1334 | /* Make it explicit that loading a register from memory |
02ed3c5e UW |
1335 | always sign-extends (at least) to SImode. */ |
1336 | if (optimize && !no_new_pseudos | |
1337 | && register_operand (operands[0], VOIDmode) | |
8fff4fc1 | 1338 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1339 | { |
1340 | rtx tmp = gen_reg_rtx (SImode); | |
1341 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1342 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1343 | operands[1] = gen_lowpart (HImode, tmp); | |
1344 | } | |
1345 | }) | |
1346 | ||
1347 | (define_insn "*movhi" | |
d3632d41 UW |
1348 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1349 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1350 | "" |
1351 | "@ | |
d40c829f UW |
1352 | lr\t%0,%1 |
1353 | lhi\t%0,%h1 | |
1354 | lh\t%0,%1 | |
1355 | lhy\t%0,%1 | |
1356 | sth\t%1,%0 | |
1357 | sthy\t%1,%0 | |
19b63d8e | 1358 | #" |
d3632d41 | 1359 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
b628bd8e | 1360 | (set_attr "type" "lr,*,*,*,store,store,*")]) |
9db1d521 | 1361 | |
84817c5d UW |
1362 | (define_peephole2 |
1363 | [(set (match_operand:HI 0 "register_operand" "") | |
1364 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1365 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1366 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1367 | && get_pool_mode (operands[1]) == HImode | |
1368 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1369 | [(set (match_dup 0) (match_dup 2))] | |
1370 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1371 | |
9db1d521 HP |
1372 | ; |
1373 | ; movqi instruction pattern(s). | |
1374 | ; | |
1375 | ||
02ed3c5e UW |
1376 | (define_expand "movqi" |
1377 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1378 | (match_operand:QI 1 "general_operand" ""))] | |
1379 | "" | |
1380 | { | |
c19ec8f9 | 1381 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1382 | is just as fast as a QImode load. */ |
c19ec8f9 | 1383 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1384 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1385 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1386 | { |
c19ec8f9 UW |
1387 | rtx tmp = gen_reg_rtx (word_mode); |
1388 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1389 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1390 | operands[1] = gen_lowpart (QImode, tmp); | |
1391 | } | |
1392 | }) | |
4023fb28 | 1393 | |
02ed3c5e | 1394 | (define_insn "*movqi" |
d3632d41 UW |
1395 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1396 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1397 | "" |
1398 | "@ | |
d40c829f UW |
1399 | lr\t%0,%1 |
1400 | lhi\t%0,%b1 | |
1401 | ic\t%0,%1 | |
1402 | icy\t%0,%1 | |
1403 | stc\t%1,%0 | |
1404 | stcy\t%1,%0 | |
fc0ea003 UW |
1405 | mvi\t%S0,%b1 |
1406 | mviy\t%S0,%b1 | |
19b63d8e | 1407 | #" |
d3632d41 | 1408 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
b628bd8e | 1409 | (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) |
9db1d521 | 1410 | |
84817c5d UW |
1411 | (define_peephole2 |
1412 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1413 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1414 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1415 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1416 | && get_pool_mode (operands[1]) == QImode | |
1417 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1418 | [(set (match_dup 0) (match_dup 2))] | |
1419 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1420 | |
9db1d521 | 1421 | ; |
05b9aaaa | 1422 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1423 | ; |
1424 | ||
1425 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1426 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1427 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1428 | "" |
d3632d41 | 1429 | "@ |
d40c829f UW |
1430 | ic\t%0,%1 |
1431 | icy\t%0,%1" | |
d3632d41 | 1432 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1433 | |
1434 | ; | |
1435 | ; movstricthi instruction pattern(s). | |
1436 | ; | |
1437 | ||
1438 | (define_insn "*movstricthi" | |
d3632d41 | 1439 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1440 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1441 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1442 | "" |
d3632d41 | 1443 | "@ |
fc0ea003 UW |
1444 | icm\t%0,3,%S1 |
1445 | icmy\t%0,3,%S1" | |
d3632d41 | 1446 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1447 | |
1448 | ; | |
1449 | ; movstrictsi instruction pattern(s). | |
1450 | ; | |
1451 | ||
05b9aaaa | 1452 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1453 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1454 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1455 | "TARGET_64BIT" |
1456 | "@ | |
d40c829f UW |
1457 | lr\t%0,%1 |
1458 | l\t%0,%1 | |
c5aa1d12 UW |
1459 | ly\t%0,%1 |
1460 | ear\t%0,%1" | |
1461 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
1462 | (set_attr "type" "lr,load,load,*")]) | |
9db1d521 | 1463 | |
f61a2c7d AK |
1464 | ; |
1465 | ; movtf instruction pattern(s). | |
1466 | ; | |
1467 | ||
1468 | (define_expand "movtf" | |
1469 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
1470 | (match_operand:TF 1 "general_operand" ""))] | |
1471 | "" | |
1472 | "") | |
1473 | ||
1474 | (define_insn "*movtf_64" | |
1475 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,d,QS,d,o,Q") | |
1476 | (match_operand:TF 1 "general_operand" "G,f,o,f,QS,d,dm,d,Q"))] | |
1477 | "TARGET_64BIT" | |
1478 | "@ | |
1479 | lzxr\t%0 | |
1480 | lxr\t%0,%1 | |
1481 | # | |
1482 | # | |
1483 | lmg\t%0,%N0,%S1 | |
1484 | stmg\t%1,%N1,%S0 | |
1485 | # | |
1486 | # | |
1487 | #" | |
1488 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*,*") | |
1489 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*,*")]) | |
1490 | ||
1491 | (define_insn "*movtf_31" | |
1492 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,f,o,Q") | |
1493 | (match_operand:TF 1 "general_operand" "G,f,o,f,Q"))] | |
1494 | "!TARGET_64BIT" | |
1495 | "@ | |
1496 | lzxr\t%0 | |
1497 | lxr\t%0,%1 | |
1498 | # | |
1499 | # | |
1500 | #" | |
1501 | [(set_attr "op_type" "RRE,RRE,*,*,*") | |
1502 | (set_attr "type" "fsimptf,fsimptf,*,*,*")]) | |
1503 | ||
1504 | ; TFmode in GPRs splitters | |
1505 | ||
1506 | (define_split | |
1507 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
1508 | (match_operand:TF 1 "general_operand" ""))] | |
1509 | "TARGET_64BIT && reload_completed | |
1510 | && s390_split_ok_p (operands[0], operands[1], TFmode, 0)" | |
1511 | [(set (match_dup 2) (match_dup 4)) | |
1512 | (set (match_dup 3) (match_dup 5))] | |
1513 | { | |
1514 | operands[2] = operand_subword (operands[0], 0, 0, TFmode); | |
1515 | operands[3] = operand_subword (operands[0], 1, 0, TFmode); | |
1516 | operands[4] = operand_subword (operands[1], 0, 0, TFmode); | |
1517 | operands[5] = operand_subword (operands[1], 1, 0, TFmode); | |
1518 | }) | |
1519 | ||
1520 | (define_split | |
1521 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
1522 | (match_operand:TF 1 "general_operand" ""))] | |
1523 | "TARGET_64BIT && reload_completed | |
1524 | && s390_split_ok_p (operands[0], operands[1], TFmode, 1)" | |
1525 | [(set (match_dup 2) (match_dup 4)) | |
1526 | (set (match_dup 3) (match_dup 5))] | |
1527 | { | |
1528 | operands[2] = operand_subword (operands[0], 1, 0, TFmode); | |
1529 | operands[3] = operand_subword (operands[0], 0, 0, TFmode); | |
1530 | operands[4] = operand_subword (operands[1], 1, 0, TFmode); | |
1531 | operands[5] = operand_subword (operands[1], 0, 0, TFmode); | |
1532 | }) | |
1533 | ||
1534 | (define_split | |
1535 | [(set (match_operand:TF 0 "register_operand" "") | |
1536 | (match_operand:TF 1 "memory_operand" ""))] | |
1537 | "TARGET_64BIT && reload_completed | |
1538 | && !FP_REG_P (operands[0]) | |
1539 | && !s_operand (operands[1], VOIDmode)" | |
1540 | [(set (match_dup 0) (match_dup 1))] | |
1541 | { | |
1542 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1543 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1544 | operands[1] = replace_equiv_address (operands[1], addr); | |
1545 | }) | |
1546 | ||
1547 | ; TFmode in FPRs splitters | |
1548 | ||
1549 | (define_split | |
1550 | [(set (match_operand:TF 0 "register_operand" "") | |
1551 | (match_operand:TF 1 "memory_operand" ""))] | |
1552 | "reload_completed && offsettable_memref_p (operands[1]) | |
1553 | && FP_REG_P (operands[0])" | |
1554 | [(set (match_dup 2) (match_dup 4)) | |
1555 | (set (match_dup 3) (match_dup 5))] | |
1556 | { | |
1557 | operands[2] = simplify_gen_subreg (DFmode, operands[0], TFmode, 0); | |
1558 | operands[3] = simplify_gen_subreg (DFmode, operands[0], TFmode, 8); | |
1559 | operands[4] = adjust_address_nv (operands[1], DFmode, 0); | |
1560 | operands[5] = adjust_address_nv (operands[1], DFmode, 8); | |
1561 | }) | |
1562 | ||
1563 | (define_split | |
1564 | [(set (match_operand:TF 0 "memory_operand" "") | |
1565 | (match_operand:TF 1 "register_operand" ""))] | |
1566 | "reload_completed && offsettable_memref_p (operands[0]) | |
1567 | && FP_REG_P (operands[1])" | |
1568 | [(set (match_dup 2) (match_dup 4)) | |
1569 | (set (match_dup 3) (match_dup 5))] | |
1570 | { | |
1571 | operands[2] = adjust_address_nv (operands[0], DFmode, 0); | |
1572 | operands[3] = adjust_address_nv (operands[0], DFmode, 8); | |
1573 | operands[4] = simplify_gen_subreg (DFmode, operands[1], TFmode, 0); | |
1574 | operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, 8); | |
1575 | }) | |
1576 | ||
1577 | (define_expand "reload_outtf" | |
1578 | [(parallel [(match_operand:TF 0 "" "") | |
1579 | (match_operand:TF 1 "register_operand" "f") | |
1580 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1581 | "" | |
1582 | { | |
1583 | rtx addr = gen_lowpart (Pmode, operands[2]); | |
1584 | ||
1585 | gcc_assert (MEM_P (operands[0])); | |
1586 | s390_load_address (addr, find_replacement (&XEXP (operands[0], 0))); | |
1587 | operands[0] = replace_equiv_address (operands[0], addr); | |
1588 | emit_move_insn (operands[0], operands[1]); | |
1589 | DONE; | |
1590 | }) | |
1591 | ||
1592 | (define_expand "reload_intf" | |
1593 | [(parallel [(match_operand:TF 0 "register_operand" "=f") | |
1594 | (match_operand:TF 1 "" "") | |
1595 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1596 | "" | |
1597 | { | |
1598 | rtx addr = gen_lowpart (Pmode, operands[2]); | |
1599 | ||
1600 | gcc_assert (MEM_P (operands[1])); | |
1601 | s390_load_address (addr, find_replacement (&XEXP (operands[1], 0))); | |
1602 | operands[1] = replace_equiv_address (operands[1], addr); | |
1603 | emit_move_insn (operands[0], operands[1]); | |
1604 | DONE; | |
1605 | }) | |
1606 | ||
9db1d521 HP |
1607 | ; |
1608 | ; movdf instruction pattern(s). | |
1609 | ; | |
1610 | ||
1611 | (define_expand "movdf" | |
1612 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1613 | (match_operand:DF 1 "general_operand" ""))] | |
1614 | "" | |
13c025c1 | 1615 | "") |
9db1d521 HP |
1616 | |
1617 | (define_insn "*movdf_64" | |
d096725d AS |
1618 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q") |
1619 | (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1620 | "TARGET_64BIT" |
9db1d521 | 1621 | "@ |
d096725d | 1622 | lzdr\t%0 |
d40c829f UW |
1623 | ldr\t%0,%1 |
1624 | ld\t%0,%1 | |
1625 | ldy\t%0,%1 | |
1626 | std\t%1,%0 | |
1627 | stdy\t%1,%0 | |
1628 | lgr\t%0,%1 | |
1629 | lg\t%0,%1 | |
1630 | stg\t%1,%0 | |
19b63d8e | 1631 | #" |
d096725d AS |
1632 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
1633 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")]) | |
9db1d521 HP |
1634 | |
1635 | (define_insn "*movdf_31" | |
c4d50129 | 1636 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q") |
11598938 | 1637 | (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))] |
4023fb28 | 1638 | "!TARGET_64BIT" |
9db1d521 | 1639 | "@ |
d096725d | 1640 | lzdr\t%0 |
d40c829f UW |
1641 | ldr\t%0,%1 |
1642 | ld\t%0,%1 | |
1643 | ldy\t%0,%1 | |
1644 | std\t%1,%0 | |
1645 | stdy\t%1,%0 | |
fc0ea003 | 1646 | lm\t%0,%N0,%S1 |
c4d50129 | 1647 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1648 | stm\t%1,%N1,%S0 |
c4d50129 | 1649 | stmy\t%1,%N1,%S0 |
4023fb28 | 1650 | # |
9b7c75b9 | 1651 | # |
19b63d8e | 1652 | #" |
c4d50129 AK |
1653 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS") |
1654 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\ | |
1655 | lm,lm,stm,stm,*,*,*")]) | |
4023fb28 UW |
1656 | |
1657 | (define_split | |
1658 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1659 | (match_operand:DF 1 "general_operand" ""))] | |
1660 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1661 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1662 | [(set (match_dup 2) (match_dup 4)) |
1663 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1664 | { |
dc65c307 UW |
1665 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1666 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1667 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1668 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1669 | }) | |
1670 | ||
1671 | (define_split | |
1672 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1673 | (match_operand:DF 1 "general_operand" ""))] | |
1674 | "!TARGET_64BIT && reload_completed | |
1675 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1676 | [(set (match_dup 2) (match_dup 4)) | |
1677 | (set (match_dup 3) (match_dup 5))] | |
1678 | { | |
1679 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1680 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1681 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1682 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1683 | }) | |
9db1d521 | 1684 | |
4023fb28 UW |
1685 | (define_split |
1686 | [(set (match_operand:DF 0 "register_operand" "") | |
1687 | (match_operand:DF 1 "memory_operand" ""))] | |
1688 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1689 | && !FP_REG_P (operands[0]) |
4023fb28 | 1690 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1691 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1692 | { |
1693 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1694 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1695 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1696 | }) |
1697 | ||
1698 | (define_expand "reload_outdf" | |
9c3c3dcc | 1699 | [(parallel [(match_operand:DF 0 "" "") |
dc65c307 UW |
1700 | (match_operand:DF 1 "register_operand" "d") |
1701 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1702 | "!TARGET_64BIT" | |
1703 | { | |
9c3c3dcc | 1704 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1705 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1706 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1707 | emit_move_insn (operands[0], operands[1]); | |
1708 | DONE; | |
1709 | }) | |
9db1d521 HP |
1710 | |
1711 | ; | |
1712 | ; movsf instruction pattern(s). | |
1713 | ; | |
1714 | ||
13c025c1 | 1715 | (define_insn "movsf" |
d096725d AS |
1716 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q") |
1717 | (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1718 | "" |
9db1d521 | 1719 | "@ |
d096725d | 1720 | lzer\t%0 |
d40c829f UW |
1721 | ler\t%0,%1 |
1722 | le\t%0,%1 | |
1723 | ley\t%0,%1 | |
1724 | ste\t%1,%0 | |
1725 | stey\t%1,%0 | |
1726 | lr\t%0,%1 | |
1727 | l\t%0,%1 | |
1728 | ly\t%0,%1 | |
1729 | st\t%1,%0 | |
1730 | sty\t%1,%0 | |
19b63d8e | 1731 | #" |
d096725d AS |
1732 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1733 | (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf, | |
b628bd8e | 1734 | lr,load,load,store,store,*")]) |
4023fb28 | 1735 | |
9dc62c00 AK |
1736 | ; |
1737 | ; movcc instruction pattern | |
1738 | ; | |
1739 | ||
1740 | (define_insn "movcc" | |
1741 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
1742 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
1743 | "" | |
1744 | "@ | |
1745 | lr\t%0,%1 | |
1746 | tmh\t%1,12288 | |
1747 | ipm\t%0 | |
1748 | st\t%0,%1 | |
1749 | sty\t%0,%1 | |
1750 | l\t%1,%0 | |
1751 | ly\t%1,%0" | |
8dd3b235 AK |
1752 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
1753 | (set_attr "type" "lr,*,*,store,store,load,load")]) | |
9dc62c00 | 1754 | |
19b63d8e UW |
1755 | ; |
1756 | ; Block move (MVC) patterns. | |
1757 | ; | |
1758 | ||
1759 | (define_insn "*mvc" | |
1760 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
1761 | (match_operand:BLK 1 "memory_operand" "Q")) | |
1762 | (use (match_operand 2 "const_int_operand" "n"))] | |
1763 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1764 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 1765 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1766 | |
1767 | (define_split | |
1768 | [(set (match_operand 0 "memory_operand" "") | |
1769 | (match_operand 1 "memory_operand" ""))] | |
1770 | "reload_completed | |
1771 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1772 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1773 | [(parallel | |
1774 | [(set (match_dup 0) (match_dup 1)) | |
1775 | (use (match_dup 2))])] | |
1776 | { | |
1777 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1778 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1779 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1780 | }) | |
1781 | ||
1782 | (define_peephole2 | |
1783 | [(parallel | |
1784 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1785 | (match_operand:BLK 1 "memory_operand" "")) | |
1786 | (use (match_operand 2 "const_int_operand" ""))]) | |
1787 | (parallel | |
1788 | [(set (match_operand:BLK 3 "memory_operand" "") | |
1789 | (match_operand:BLK 4 "memory_operand" "")) | |
1790 | (use (match_operand 5 "const_int_operand" ""))])] | |
1791 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
1792 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
1793 | && !s390_overlap_p (operands[0], operands[1], |
1794 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
1795 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
1796 | [(parallel | |
1797 | [(set (match_dup 6) (match_dup 7)) | |
1798 | (use (match_dup 8))])] | |
1799 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
1800 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
1801 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
1802 | ||
1803 | ||
9db1d521 HP |
1804 | ; |
1805 | ; load_multiple pattern(s). | |
1806 | ; | |
22ea6b4f UW |
1807 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1808 | ; we currently support load_multiple/store_multiple only after reload. | |
1809 | ; | |
9db1d521 HP |
1810 | |
1811 | (define_expand "load_multiple" | |
1812 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1813 | (match_operand 1 "" "")) | |
1814 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1815 | "reload_completed" |
9db1d521 | 1816 | { |
c19ec8f9 | 1817 | enum machine_mode mode; |
9db1d521 HP |
1818 | int regno; |
1819 | int count; | |
1820 | rtx from; | |
4023fb28 | 1821 | int i, off; |
9db1d521 HP |
1822 | |
1823 | /* Support only loading a constant number of fixed-point registers from | |
1824 | memory and only bother with this if more than two */ | |
1825 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1826 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1827 | || INTVAL (operands[2]) > 16 |
1828 | || GET_CODE (operands[1]) != MEM | |
1829 | || GET_CODE (operands[0]) != REG | |
1830 | || REGNO (operands[0]) >= 16) | |
1831 | FAIL; | |
1832 | ||
1833 | count = INTVAL (operands[2]); | |
1834 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1835 | mode = GET_MODE (operands[0]); |
1836 | if (mode != SImode && mode != word_mode) | |
1837 | FAIL; | |
9db1d521 HP |
1838 | |
1839 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1840 | if (no_new_pseudos) |
1841 | { | |
1842 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1843 | { | |
1844 | from = XEXP (operands[1], 0); | |
1845 | off = 0; | |
1846 | } | |
1847 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1848 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1849 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1850 | { | |
1851 | from = XEXP (XEXP (operands[1], 0), 0); | |
1852 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1853 | } | |
1854 | else | |
1855 | FAIL; | |
4023fb28 UW |
1856 | } |
1857 | else | |
1858 | { | |
1859 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1860 | off = 0; | |
1861 | } | |
9db1d521 HP |
1862 | |
1863 | for (i = 0; i < count; i++) | |
1864 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1865 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1866 | change_address (operands[1], mode, | |
1867 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1868 | }) |
9db1d521 HP |
1869 | |
1870 | (define_insn "*load_multiple_di" | |
1871 | [(match_parallel 0 "load_multiple_operation" | |
1872 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1873 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1874 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1875 | { |
1876 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1877 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1878 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 1879 | } |
d3632d41 | 1880 | [(set_attr "op_type" "RSY") |
4023fb28 | 1881 | (set_attr "type" "lm")]) |
9db1d521 HP |
1882 | |
1883 | (define_insn "*load_multiple_si" | |
1884 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1885 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1886 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1887 | "reload_completed" |
9db1d521 HP |
1888 | { |
1889 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1890 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1891 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 1892 | } |
d3632d41 | 1893 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1894 | (set_attr "type" "lm")]) |
9db1d521 HP |
1895 | |
1896 | ; | |
c7453384 | 1897 | ; store multiple pattern(s). |
9db1d521 HP |
1898 | ; |
1899 | ||
1900 | (define_expand "store_multiple" | |
1901 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1902 | (match_operand 1 "" "")) | |
1903 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1904 | "reload_completed" |
9db1d521 | 1905 | { |
c19ec8f9 | 1906 | enum machine_mode mode; |
9db1d521 HP |
1907 | int regno; |
1908 | int count; | |
1909 | rtx to; | |
4023fb28 | 1910 | int i, off; |
9db1d521 HP |
1911 | |
1912 | /* Support only storing a constant number of fixed-point registers to | |
1913 | memory and only bother with this if more than two. */ | |
1914 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1915 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1916 | || INTVAL (operands[2]) > 16 |
1917 | || GET_CODE (operands[0]) != MEM | |
1918 | || GET_CODE (operands[1]) != REG | |
1919 | || REGNO (operands[1]) >= 16) | |
1920 | FAIL; | |
1921 | ||
1922 | count = INTVAL (operands[2]); | |
1923 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1924 | mode = GET_MODE (operands[1]); |
1925 | if (mode != SImode && mode != word_mode) | |
1926 | FAIL; | |
9db1d521 HP |
1927 | |
1928 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1929 | |
1930 | if (no_new_pseudos) | |
1931 | { | |
1932 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1933 | { | |
1934 | to = XEXP (operands[0], 0); | |
1935 | off = 0; | |
1936 | } | |
1937 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1938 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1939 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1940 | { | |
1941 | to = XEXP (XEXP (operands[0], 0), 0); | |
1942 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1943 | } | |
1944 | else | |
1945 | FAIL; | |
4023fb28 | 1946 | } |
c7453384 | 1947 | else |
4023fb28 UW |
1948 | { |
1949 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1950 | off = 0; | |
1951 | } | |
9db1d521 HP |
1952 | |
1953 | for (i = 0; i < count; i++) | |
1954 | XVECEXP (operands[3], 0, i) | |
1955 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1956 | change_address (operands[0], mode, |
1957 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1958 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1959 | }) |
9db1d521 HP |
1960 | |
1961 | (define_insn "*store_multiple_di" | |
1962 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1963 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1964 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1965 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1966 | { |
1967 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1968 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1969 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 1970 | } |
d3632d41 | 1971 | [(set_attr "op_type" "RSY") |
4023fb28 | 1972 | (set_attr "type" "stm")]) |
9db1d521 HP |
1973 | |
1974 | ||
1975 | (define_insn "*store_multiple_si" | |
1976 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1977 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1978 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1979 | "reload_completed" |
9db1d521 HP |
1980 | { |
1981 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1982 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1983 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 1984 | } |
d3632d41 | 1985 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1986 | (set_attr "type" "stm")]) |
9db1d521 HP |
1987 | |
1988 | ;; | |
1989 | ;; String instructions. | |
1990 | ;; | |
1991 | ||
9bb86f41 UW |
1992 | (define_insn "*execute" |
1993 | [(match_parallel 0 "" | |
1994 | [(unspec [(match_operand 1 "register_operand" "a") | |
1995 | (match_operand:BLK 2 "memory_operand" "R") | |
1996 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
1997 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
1998 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
1999 | "ex\t%1,%2" | |
29a74354 UW |
2000 | [(set_attr "op_type" "RX") |
2001 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2002 | |
2003 | ||
91d39d71 UW |
2004 | ; |
2005 | ; strlenM instruction pattern(s). | |
2006 | ; | |
2007 | ||
9db2f16d | 2008 | (define_expand "strlen<mode>" |
ccbdc0d4 | 2009 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2010 | (parallel |
91d39d71 | 2011 | [(set (match_dup 4) |
9db2f16d | 2012 | (unspec:P [(const_int 0) |
91d39d71 | 2013 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2014 | (reg:SI 0) |
91d39d71 | 2015 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2016 | (clobber (scratch:P)) |
ae156f85 | 2017 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2018 | (parallel |
9db2f16d AS |
2019 | [(set (match_operand:P 0 "register_operand" "") |
2020 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2021 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2022 | "" |
91d39d71 | 2023 | { |
9db2f16d AS |
2024 | operands[4] = gen_reg_rtx (Pmode); |
2025 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2026 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2027 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2028 | }) | |
2029 | ||
9db2f16d AS |
2030 | (define_insn "*strlen<mode>" |
2031 | [(set (match_operand:P 0 "register_operand" "=a") | |
2032 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2033 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2034 | (reg:SI 0) |
91d39d71 | 2035 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2036 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2037 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2038 | "" |
91d39d71 | 2039 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2040 | [(set_attr "length" "8") |
2041 | (set_attr "type" "vs")]) | |
91d39d71 | 2042 | |
ccbdc0d4 AS |
2043 | ; |
2044 | ; cmpstrM instruction pattern(s). | |
2045 | ; | |
2046 | ||
2047 | (define_expand "cmpstrsi" | |
2048 | [(set (reg:SI 0) (const_int 0)) | |
2049 | (parallel | |
2050 | [(clobber (match_operand 3 "" "")) | |
2051 | (clobber (match_dup 4)) | |
2052 | (set (reg:CCU CC_REGNUM) | |
2053 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2054 | (match_operand:BLK 2 "memory_operand" ""))) | |
2055 | (use (reg:SI 0))]) | |
2056 | (parallel | |
2057 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2058 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT)) | |
2059 | (clobber (reg:CC CC_REGNUM))])] | |
2060 | "" | |
2061 | { | |
2062 | /* As the result of CMPINT is inverted compared to what we need, | |
2063 | we have to swap the operands. */ | |
2064 | rtx op1 = operands[2]; | |
2065 | rtx op2 = operands[1]; | |
2066 | rtx addr1 = gen_reg_rtx (Pmode); | |
2067 | rtx addr2 = gen_reg_rtx (Pmode); | |
2068 | ||
2069 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2070 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2071 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2072 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2073 | operands[3] = addr1; | |
2074 | operands[4] = addr2; | |
2075 | }) | |
2076 | ||
2077 | (define_insn "*cmpstr<mode>" | |
2078 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2079 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2080 | (set (reg:CCU CC_REGNUM) | |
2081 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2082 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2083 | (use (reg:SI 0))] | |
2084 | "" | |
2085 | "clst\t%0,%1\;jo\t.-4" | |
2086 | [(set_attr "length" "8") | |
2087 | (set_attr "type" "vs")]) | |
2088 | ||
742090fc AS |
2089 | ; |
2090 | ; movstr instruction pattern. | |
2091 | ; | |
2092 | ||
2093 | (define_expand "movstr" | |
2094 | [(set (reg:SI 0) (const_int 0)) | |
2095 | (parallel | |
2096 | [(clobber (match_dup 3)) | |
2097 | (set (match_operand:BLK 1 "memory_operand" "") | |
2098 | (match_operand:BLK 2 "memory_operand" "")) | |
2099 | (set (match_operand 0 "register_operand" "") | |
2100 | (unspec [(match_dup 1) | |
2101 | (match_dup 2) | |
2102 | (reg:SI 0)] UNSPEC_MVST)) | |
2103 | (clobber (reg:CC CC_REGNUM))])] | |
2104 | "" | |
2105 | { | |
2106 | rtx addr1 = gen_reg_rtx (Pmode); | |
2107 | rtx addr2 = gen_reg_rtx (Pmode); | |
2108 | ||
2109 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2110 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2111 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2112 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2113 | operands[3] = addr2; | |
2114 | }) | |
2115 | ||
2116 | (define_insn "*movstr" | |
2117 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2118 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2119 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2120 | (set (match_operand:P 0 "register_operand" "=d") | |
2121 | (unspec [(mem:BLK (match_dup 1)) | |
2122 | (mem:BLK (match_dup 3)) | |
2123 | (reg:SI 0)] UNSPEC_MVST)) | |
2124 | (clobber (reg:CC CC_REGNUM))] | |
2125 | "" | |
2126 | "mvst\t%1,%2\;jo\t.-4" | |
2127 | [(set_attr "length" "8") | |
2128 | (set_attr "type" "vs")]) | |
2129 | ||
2130 | ||
9db1d521 | 2131 | ; |
70128ad9 | 2132 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2133 | ; |
2134 | ||
9db2f16d | 2135 | (define_expand "movmem<mode>" |
a41c6c53 UW |
2136 | [(set (match_operand:BLK 0 "memory_operand" "") |
2137 | (match_operand:BLK 1 "memory_operand" "")) | |
9db2f16d | 2138 | (use (match_operand:GPR 2 "general_operand" "")) |
a41c6c53 UW |
2139 | (match_operand 3 "" "")] |
2140 | "" | |
70128ad9 | 2141 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2142 | |
ecbe845e UW |
2143 | ; Move a block that is up to 256 bytes in length. |
2144 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2145 | |
70128ad9 | 2146 | (define_expand "movmem_short" |
b9404c99 UW |
2147 | [(parallel |
2148 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2149 | (match_operand:BLK 1 "memory_operand" "")) | |
2150 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2151 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2152 | (clobber (match_dup 3))])] |
2153 | "" | |
2154 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2155 | |
70128ad9 | 2156 | (define_insn "*movmem_short" |
9bb86f41 UW |
2157 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
2158 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) | |
2159 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2160 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2161 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2162 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2163 | && GET_MODE (operands[4]) == Pmode" |
2164 | "#" | |
b628bd8e | 2165 | [(set_attr "type" "cs")]) |
ecbe845e | 2166 | |
9bb86f41 UW |
2167 | (define_split |
2168 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2169 | (match_operand:BLK 1 "memory_operand" "")) | |
2170 | (use (match_operand 2 "const_int_operand" "")) | |
2171 | (use (match_operand 3 "immediate_operand" "")) | |
2172 | (clobber (scratch))] | |
2173 | "reload_completed" | |
2174 | [(parallel | |
2175 | [(set (match_dup 0) (match_dup 1)) | |
2176 | (use (match_dup 2))])] | |
2177 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2178 | |
9bb86f41 UW |
2179 | (define_split |
2180 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2181 | (match_operand:BLK 1 "memory_operand" "")) | |
2182 | (use (match_operand 2 "register_operand" "")) | |
2183 | (use (match_operand 3 "memory_operand" "")) | |
2184 | (clobber (scratch))] | |
2185 | "reload_completed" | |
2186 | [(parallel | |
2187 | [(unspec [(match_dup 2) (match_dup 3) | |
2188 | (const_int 0)] UNSPEC_EXECUTE) | |
2189 | (set (match_dup 0) (match_dup 1)) | |
2190 | (use (const_int 1))])] | |
2191 | "") | |
2192 | ||
2193 | (define_split | |
2194 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2195 | (match_operand:BLK 1 "memory_operand" "")) | |
2196 | (use (match_operand 2 "register_operand" "")) | |
2197 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2198 | (clobber (match_operand 3 "register_operand" ""))] | |
2199 | "reload_completed && TARGET_CPU_ZARCH" | |
2200 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2201 | (parallel | |
2202 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2203 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2204 | (set (match_dup 0) (match_dup 1)) | |
2205 | (use (const_int 1))])] | |
2206 | "operands[4] = gen_label_rtx ();") | |
2207 | ||
a41c6c53 | 2208 | ; Move a block of arbitrary length. |
9db1d521 | 2209 | |
70128ad9 | 2210 | (define_expand "movmem_long" |
b9404c99 UW |
2211 | [(parallel |
2212 | [(clobber (match_dup 2)) | |
2213 | (clobber (match_dup 3)) | |
2214 | (set (match_operand:BLK 0 "memory_operand" "") | |
2215 | (match_operand:BLK 1 "memory_operand" "")) | |
2216 | (use (match_operand 2 "general_operand" "")) | |
2217 | (use (match_dup 3)) | |
ae156f85 | 2218 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2219 | "" |
2220 | { | |
2221 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2222 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2223 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2224 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2225 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2226 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2227 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2228 | ||
2229 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2230 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2231 | emit_move_insn (len0, operands[2]); | |
2232 | ||
2233 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2234 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2235 | emit_move_insn (len1, operands[2]); | |
2236 | ||
2237 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2238 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2239 | operands[2] = reg0; | |
2240 | operands[3] = reg1; | |
2241 | }) | |
2242 | ||
a1aed706 AS |
2243 | (define_insn "*movmem_long" |
2244 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2245 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2246 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2247 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2248 | (use (match_dup 2)) |
2249 | (use (match_dup 3)) | |
ae156f85 | 2250 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2251 | "" |
d40c829f | 2252 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2253 | [(set_attr "length" "8") |
2254 | (set_attr "type" "vs")]) | |
9db1d521 HP |
2255 | |
2256 | ; | |
57e84f18 | 2257 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2258 | ; |
2259 | ||
57e84f18 | 2260 | (define_expand "setmem<mode>" |
a41c6c53 | 2261 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2262 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2263 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2264 | (match_operand 3 "" "")] |
a41c6c53 | 2265 | "" |
6d057022 | 2266 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2267 | |
a41c6c53 | 2268 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2269 | ; The block length is taken as (operands[1] % 256) + 1. |
2270 | ||
70128ad9 | 2271 | (define_expand "clrmem_short" |
b9404c99 UW |
2272 | [(parallel |
2273 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2274 | (const_int 0)) | |
2275 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2276 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2277 | (clobber (match_dup 2)) |
ae156f85 | 2278 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2279 | "" |
2280 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2281 | |
70128ad9 | 2282 | (define_insn "*clrmem_short" |
9bb86f41 | 2283 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
a41c6c53 | 2284 | (const_int 0)) |
9bb86f41 UW |
2285 | (use (match_operand 1 "nonmemory_operand" "n,a,a")) |
2286 | (use (match_operand 2 "immediate_operand" "X,R,X")) | |
2287 | (clobber (match_scratch 3 "=X,X,&a")) | |
ae156f85 | 2288 | (clobber (reg:CC CC_REGNUM))] |
b9404c99 | 2289 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
2290 | && GET_MODE (operands[3]) == Pmode" |
2291 | "#" | |
b628bd8e | 2292 | [(set_attr "type" "cs")]) |
9bb86f41 UW |
2293 | |
2294 | (define_split | |
2295 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2296 | (const_int 0)) | |
2297 | (use (match_operand 1 "const_int_operand" "")) | |
2298 | (use (match_operand 2 "immediate_operand" "")) | |
2299 | (clobber (scratch)) | |
ae156f85 | 2300 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2301 | "reload_completed" |
2302 | [(parallel | |
2303 | [(set (match_dup 0) (const_int 0)) | |
2304 | (use (match_dup 1)) | |
ae156f85 | 2305 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2306 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2307 | |
9bb86f41 UW |
2308 | (define_split |
2309 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2310 | (const_int 0)) | |
2311 | (use (match_operand 1 "register_operand" "")) | |
2312 | (use (match_operand 2 "memory_operand" "")) | |
2313 | (clobber (scratch)) | |
ae156f85 | 2314 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2315 | "reload_completed" |
2316 | [(parallel | |
2317 | [(unspec [(match_dup 1) (match_dup 2) | |
2318 | (const_int 0)] UNSPEC_EXECUTE) | |
2319 | (set (match_dup 0) (const_int 0)) | |
2320 | (use (const_int 1)) | |
ae156f85 | 2321 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2322 | "") |
9db1d521 | 2323 | |
9bb86f41 UW |
2324 | (define_split |
2325 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2326 | (const_int 0)) | |
2327 | (use (match_operand 1 "register_operand" "")) | |
2328 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2329 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2330 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2331 | "reload_completed && TARGET_CPU_ZARCH" |
2332 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2333 | (parallel | |
2334 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
2335 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2336 | (set (match_dup 0) (const_int 0)) | |
2337 | (use (const_int 1)) | |
ae156f85 | 2338 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2339 | "operands[3] = gen_label_rtx ();") |
2340 | ||
6d057022 | 2341 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2342 | |
6d057022 | 2343 | (define_expand "setmem_long" |
b9404c99 UW |
2344 | [(parallel |
2345 | [(clobber (match_dup 1)) | |
2346 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 2347 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 2348 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2349 | (use (match_dup 3)) |
ae156f85 | 2350 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2351 | "" |
a41c6c53 | 2352 | { |
b9404c99 UW |
2353 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2354 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2355 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2356 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2357 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2358 | |
b9404c99 UW |
2359 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2360 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2361 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2362 | |
b9404c99 | 2363 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2364 | |
b9404c99 UW |
2365 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2366 | operands[1] = reg0; | |
6d057022 | 2367 | operands[3] = reg1; |
b9404c99 | 2368 | }) |
a41c6c53 | 2369 | |
6d057022 | 2370 | (define_insn "*setmem_long" |
a1aed706 | 2371 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 2372 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 2373 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 2374 | (use (match_dup 3)) |
a1aed706 | 2375 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2376 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2377 | "" |
6d057022 | 2378 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
2379 | [(set_attr "length" "8") |
2380 | (set_attr "type" "vs")]) | |
9db1d521 | 2381 | |
4989e88a AK |
2382 | (define_insn "*setmem_long_and" |
2383 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2384 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
2385 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
2386 | (match_operand 4 "const_int_operand" "n"))) | |
2387 | (use (match_dup 3)) | |
2388 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
2389 | (clobber (reg:CC CC_REGNUM))] | |
2390 | "(INTVAL (operands[4]) & 255) == 255" | |
2391 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
2392 | [(set_attr "length" "8") | |
2393 | (set_attr "type" "vs")]) | |
9db1d521 | 2394 | ; |
358b8f01 | 2395 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2396 | ; |
2397 | ||
358b8f01 | 2398 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2399 | [(set (match_operand:SI 0 "register_operand" "") |
2400 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2401 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2402 | (use (match_operand:SI 3 "general_operand" "")) | |
2403 | (use (match_operand:SI 4 "" ""))] | |
2404 | "" | |
c7453384 | 2405 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2406 | operands[2], operands[3]); DONE;") |
9db1d521 | 2407 | |
a41c6c53 UW |
2408 | ; Compare a block that is up to 256 bytes in length. |
2409 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2410 | |
b9404c99 UW |
2411 | (define_expand "cmpmem_short" |
2412 | [(parallel | |
ae156f85 | 2413 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 2414 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2415 | (match_operand:BLK 1 "memory_operand" ""))) |
2416 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2417 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2418 | (clobber (match_dup 3))])] |
2419 | "" | |
2420 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2421 | |
b9404c99 | 2422 | (define_insn "*cmpmem_short" |
ae156f85 | 2423 | [(set (reg:CCU CC_REGNUM) |
d4f52f0e | 2424 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") |
9bb86f41 UW |
2425 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) |
2426 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2427 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2428 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2429 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2430 | && GET_MODE (operands[4]) == Pmode" |
2431 | "#" | |
b628bd8e | 2432 | [(set_attr "type" "cs")]) |
9db1d521 | 2433 | |
9bb86f41 | 2434 | (define_split |
ae156f85 | 2435 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2436 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2437 | (match_operand:BLK 1 "memory_operand" ""))) | |
2438 | (use (match_operand 2 "const_int_operand" "")) | |
2439 | (use (match_operand 3 "immediate_operand" "")) | |
2440 | (clobber (scratch))] | |
2441 | "reload_completed" | |
2442 | [(parallel | |
ae156f85 | 2443 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2444 | (use (match_dup 2))])] |
2445 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2446 | |
9bb86f41 | 2447 | (define_split |
ae156f85 | 2448 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2449 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2450 | (match_operand:BLK 1 "memory_operand" ""))) | |
2451 | (use (match_operand 2 "register_operand" "")) | |
2452 | (use (match_operand 3 "memory_operand" "")) | |
2453 | (clobber (scratch))] | |
2454 | "reload_completed" | |
2455 | [(parallel | |
2456 | [(unspec [(match_dup 2) (match_dup 3) | |
2457 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 2458 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2459 | (use (const_int 1))])] |
2460 | "") | |
2461 | ||
2462 | (define_split | |
ae156f85 | 2463 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2464 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2465 | (match_operand:BLK 1 "memory_operand" ""))) | |
2466 | (use (match_operand 2 "register_operand" "")) | |
2467 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2468 | (clobber (match_operand 3 "register_operand" ""))] | |
2469 | "reload_completed && TARGET_CPU_ZARCH" | |
2470 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2471 | (parallel | |
2472 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2473 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
ae156f85 | 2474 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2475 | (use (const_int 1))])] |
2476 | "operands[4] = gen_label_rtx ();") | |
2477 | ||
a41c6c53 | 2478 | ; Compare a block of arbitrary length. |
9db1d521 | 2479 | |
b9404c99 UW |
2480 | (define_expand "cmpmem_long" |
2481 | [(parallel | |
2482 | [(clobber (match_dup 2)) | |
2483 | (clobber (match_dup 3)) | |
ae156f85 | 2484 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 2485 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2486 | (match_operand:BLK 1 "memory_operand" ""))) |
2487 | (use (match_operand 2 "general_operand" "")) | |
2488 | (use (match_dup 3))])] | |
2489 | "" | |
2490 | { | |
2491 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2492 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2493 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2494 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2495 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2496 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2497 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2498 | ||
2499 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2500 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2501 | emit_move_insn (len0, operands[2]); | |
2502 | ||
2503 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2504 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2505 | emit_move_insn (len1, operands[2]); | |
2506 | ||
2507 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2508 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2509 | operands[2] = reg0; | |
2510 | operands[3] = reg1; | |
2511 | }) | |
2512 | ||
a1aed706 AS |
2513 | (define_insn "*cmpmem_long" |
2514 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2515 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 2516 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
2517 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
2518 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
2519 | (use (match_dup 2)) |
2520 | (use (match_dup 3))] | |
a1aed706 | 2521 | "" |
287ff198 | 2522 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2523 | [(set_attr "length" "8") |
2524 | (set_attr "type" "vs")]) | |
9db1d521 | 2525 | |
02887425 UW |
2526 | ; Convert CCUmode condition code to integer. |
2527 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 2528 | |
02887425 | 2529 | (define_insn_and_split "cmpint" |
9db1d521 | 2530 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 UW |
2531 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2532 | UNSPEC_CMPINT)) | |
ae156f85 | 2533 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2534 | "" |
02887425 UW |
2535 | "#" |
2536 | "reload_completed" | |
2537 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2538 | (parallel | |
2539 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 2540 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
2541 | |
2542 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 2543 | [(set (reg CC_REGNUM) |
02887425 UW |
2544 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2545 | UNSPEC_CMPINT) | |
2546 | (const_int 0))) | |
2547 | (set (match_operand:SI 0 "register_operand" "=d") | |
2548 | (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))] | |
2549 | "s390_match_ccmode (insn, CCSmode)" | |
2550 | "#" | |
2551 | "&& reload_completed" | |
2552 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2553 | (parallel | |
2554 | [(set (match_dup 2) (match_dup 3)) | |
2555 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 2556 | { |
02887425 UW |
2557 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
2558 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2559 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2560 | }) | |
9db1d521 | 2561 | |
02887425 | 2562 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 2563 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 UW |
2564 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2565 | UNSPEC_CMPINT))) | |
ae156f85 | 2566 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2567 | "TARGET_64BIT" |
02887425 UW |
2568 | "#" |
2569 | "&& reload_completed" | |
2570 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2571 | (parallel | |
2572 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 2573 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
2574 | |
2575 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 2576 | [(set (reg CC_REGNUM) |
02887425 UW |
2577 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
2578 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2579 | UNSPEC_CMPINT) 0) | |
2580 | (const_int 32)) (const_int 32)) | |
2581 | (const_int 0))) | |
2582 | (set (match_operand:DI 0 "register_operand" "=d") | |
2583 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))] | |
2584 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" | |
2585 | "#" | |
2586 | "&& reload_completed" | |
2587 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2588 | (parallel | |
2589 | [(set (match_dup 2) (match_dup 3)) | |
2590 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 2591 | { |
02887425 UW |
2592 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
2593 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2594 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2595 | }) | |
9db1d521 | 2596 | |
4023fb28 | 2597 | |
9db1d521 HP |
2598 | ;; |
2599 | ;;- Conversion instructions. | |
2600 | ;; | |
2601 | ||
6fa05db6 | 2602 | (define_insn "*sethighpartsi" |
d3632d41 | 2603 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
2604 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
2605 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 2606 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2607 | "" |
d3632d41 | 2608 | "@ |
6fa05db6 AS |
2609 | icm\t%0,%2,%S1 |
2610 | icmy\t%0,%2,%S1" | |
d3632d41 | 2611 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2612 | |
6fa05db6 | 2613 | (define_insn "*sethighpartdi_64" |
4023fb28 | 2614 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
2615 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
2616 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 2617 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2618 | "TARGET_64BIT" |
6fa05db6 | 2619 | "icmh\t%0,%2,%S1" |
d3632d41 | 2620 | [(set_attr "op_type" "RSY")]) |
4023fb28 | 2621 | |
6fa05db6 | 2622 | (define_insn "*sethighpartdi_31" |
d3632d41 | 2623 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
2624 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
2625 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 2626 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2627 | "!TARGET_64BIT" |
d3632d41 | 2628 | "@ |
6fa05db6 AS |
2629 | icm\t%0,%2,%S1 |
2630 | icmy\t%0,%2,%S1" | |
d3632d41 | 2631 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2632 | |
6fa05db6 AS |
2633 | (define_insn_and_split "*extzv<mode>" |
2634 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2635 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
2636 | (match_operand 2 "const_int_operand" "n") | |
2637 | (const_int 0))) | |
ae156f85 | 2638 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
2639 | "INTVAL (operands[2]) > 0 |
2640 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
2641 | "#" |
2642 | "&& reload_completed" | |
4023fb28 | 2643 | [(parallel |
6fa05db6 | 2644 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 2645 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 2646 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 2647 | { |
6fa05db6 AS |
2648 | int bitsize = INTVAL (operands[2]); |
2649 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
2650 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
2651 | ||
2652 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2653 | set_mem_size (operands[1], GEN_INT (size)); | |
2654 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
2655 | operands[3] = GEN_INT (mask); | |
b628bd8e | 2656 | }) |
4023fb28 | 2657 | |
6fa05db6 AS |
2658 | (define_insn_and_split "*extv<mode>" |
2659 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2660 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
2661 | (match_operand 2 "const_int_operand" "n") | |
2662 | (const_int 0))) | |
ae156f85 | 2663 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
2664 | "INTVAL (operands[2]) > 0 |
2665 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
2666 | "#" |
2667 | "&& reload_completed" | |
4023fb28 | 2668 | [(parallel |
6fa05db6 | 2669 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 2670 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
2671 | (parallel |
2672 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
2673 | (clobber (reg:CC CC_REGNUM))])] | |
2674 | { | |
2675 | int bitsize = INTVAL (operands[2]); | |
2676 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
2677 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
2678 | ||
2679 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2680 | set_mem_size (operands[1], GEN_INT (size)); | |
2681 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
2682 | operands[3] = GEN_INT (mask); | |
2683 | }) | |
2684 | ||
2685 | ; | |
2686 | ; insv instruction patterns | |
2687 | ; | |
2688 | ||
2689 | (define_expand "insv" | |
2690 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
2691 | (match_operand 1 "const_int_operand" "") | |
2692 | (match_operand 2 "const_int_operand" "")) | |
2693 | (match_operand 3 "general_operand" ""))] | |
2694 | "" | |
4023fb28 | 2695 | { |
6fa05db6 AS |
2696 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
2697 | DONE; | |
2698 | FAIL; | |
b628bd8e | 2699 | }) |
4023fb28 | 2700 | |
6fa05db6 AS |
2701 | (define_insn "*insv<mode>_mem_reg" |
2702 | [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") | |
2703 | (match_operand 1 "const_int_operand" "n,n") | |
2704 | (const_int 0)) | |
2705 | (match_operand:P 2 "register_operand" "d,d"))] | |
2706 | "INTVAL (operands[1]) > 0 | |
2707 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
2708 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
2709 | { | |
2710 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
2711 | ||
2712 | operands[1] = GEN_INT ((1ul << size) - 1); | |
2713 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" | |
2714 | : "stcmy\t%2,%1,%S0"; | |
2715 | } | |
2716 | [(set_attr "op_type" "RS,RSY")]) | |
2717 | ||
2718 | (define_insn "*insvdi_mem_reghigh" | |
2719 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
2720 | (match_operand 1 "const_int_operand" "n") | |
2721 | (const_int 0)) | |
2722 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
2723 | (const_int 32)))] | |
2724 | "TARGET_64BIT | |
2725 | && INTVAL (operands[1]) > 0 | |
2726 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
2727 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
2728 | { | |
2729 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
2730 | ||
2731 | operands[1] = GEN_INT ((1ul << size) - 1); | |
2732 | return "stcmh\t%2,%1,%S0"; | |
2733 | } | |
2734 | [(set_attr "op_type" "RSY")]) | |
2735 | ||
2736 | (define_insn "*insv<mode>_reg_imm" | |
2737 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
2738 | (const_int 16) | |
2739 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 2740 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 AS |
2741 | "TARGET_ZARCH |
2742 | && INTVAL (operands[1]) >= 0 | |
2743 | && INTVAL (operands[1]) < BITS_PER_WORD | |
2744 | && INTVAL (operands[1]) % 16 == 0" | |
2745 | { | |
2746 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
2747 | { | |
2748 | case 64: return "iihh\t%0,%x2"; break; | |
2749 | case 48: return "iihl\t%0,%x2"; break; | |
2750 | case 32: return "iilh\t%0,%x2"; break; | |
2751 | case 16: return "iill\t%0,%x2"; break; | |
2752 | default: gcc_unreachable(); | |
2753 | } | |
2754 | } | |
2755 | [(set_attr "op_type" "RI")]) | |
2756 | ||
2757 | (define_insn "*insv<mode>_reg_extimm" | |
2758 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
2759 | (const_int 32) | |
2760 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 2761 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 AS |
2762 | "TARGET_EXTIMM |
2763 | && INTVAL (operands[1]) >= 0 | |
2764 | && INTVAL (operands[1]) < BITS_PER_WORD | |
2765 | && INTVAL (operands[1]) % 32 == 0" | |
2766 | { | |
2767 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
2768 | { | |
2769 | case 64: return "iihf\t%0,%o2"; break; | |
2770 | case 32: return "iilf\t%0,%o2"; break; | |
2771 | default: gcc_unreachable(); | |
2772 | } | |
2773 | } | |
2774 | [(set_attr "op_type" "RIL")]) | |
2775 | ||
9db1d521 HP |
2776 | ; |
2777 | ; extendsidi2 instruction pattern(s). | |
2778 | ; | |
2779 | ||
4023fb28 UW |
2780 | (define_expand "extendsidi2" |
2781 | [(set (match_operand:DI 0 "register_operand" "") | |
2782 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2783 | "" | |
4023fb28 UW |
2784 | { |
2785 | if (!TARGET_64BIT) | |
2786 | { | |
9f37ccb1 UW |
2787 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2788 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2789 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2790 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2791 | DONE; |
2792 | } | |
ec24698e | 2793 | }) |
4023fb28 UW |
2794 | |
2795 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2796 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2797 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2798 | "TARGET_64BIT" | |
2799 | "@ | |
d40c829f UW |
2800 | lgfr\t%0,%1 |
2801 | lgf\t%0,%1" | |
d3632d41 | 2802 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2803 | |
9db1d521 | 2804 | ; |
56477c21 | 2805 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
2806 | ; |
2807 | ||
56477c21 AS |
2808 | (define_expand "extend<HQI:mode><DSI:mode>2" |
2809 | [(set (match_operand:DSI 0 "register_operand" "") | |
2810 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 2811 | "" |
4023fb28 | 2812 | { |
56477c21 | 2813 | if (<DSI:MODE>mode == DImode && !TARGET_64BIT) |
4023fb28 UW |
2814 | { |
2815 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 2816 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
2817 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
2818 | DONE; | |
2819 | } | |
ec24698e | 2820 | else if (!TARGET_EXTIMM) |
4023fb28 | 2821 | { |
56477c21 AS |
2822 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - |
2823 | GET_MODE_BITSIZE (<HQI:MODE>mode)); | |
2824 | ||
2825 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
2826 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
2827 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2828 | DONE; |
2829 | } | |
ec24698e UW |
2830 | }) |
2831 | ||
56477c21 AS |
2832 | ; |
2833 | ; extendhidi2 instruction pattern(s). | |
2834 | ; | |
2835 | ||
ec24698e UW |
2836 | (define_insn "*extendhidi2_extimm" |
2837 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2838 | (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] | |
2839 | "TARGET_64BIT && TARGET_EXTIMM" | |
2840 | "@ | |
2841 | lghr\t%0,%1 | |
2842 | lgh\t%0,%1" | |
2843 | [(set_attr "op_type" "RRE,RXY")]) | |
4023fb28 UW |
2844 | |
2845 | (define_insn "*extendhidi2" | |
9db1d521 | 2846 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2847 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2848 | "TARGET_64BIT" |
d40c829f | 2849 | "lgh\t%0,%1" |
d3632d41 | 2850 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2851 | |
9db1d521 | 2852 | ; |
56477c21 | 2853 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
2854 | ; |
2855 | ||
ec24698e UW |
2856 | (define_insn "*extendhisi2_extimm" |
2857 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
2858 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))] | |
2859 | "TARGET_EXTIMM" | |
2860 | "@ | |
2861 | lhr\t%0,%1 | |
2862 | lh\t%0,%1 | |
2863 | lhy\t%0,%1" | |
2864 | [(set_attr "op_type" "RRE,RX,RXY")]) | |
9db1d521 | 2865 | |
4023fb28 | 2866 | (define_insn "*extendhisi2" |
d3632d41 UW |
2867 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2868 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 2869 | "!TARGET_EXTIMM" |
d3632d41 | 2870 | "@ |
d40c829f UW |
2871 | lh\t%0,%1 |
2872 | lhy\t%0,%1" | |
d3632d41 | 2873 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 | 2874 | |
56477c21 AS |
2875 | ; |
2876 | ; extendqi(si|di)2 instruction pattern(s). | |
2877 | ; | |
2878 | ||
43a09b63 | 2879 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
2880 | (define_insn "*extendqi<mode>2_extimm" |
2881 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
2882 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))] | |
ec24698e UW |
2883 | "TARGET_EXTIMM" |
2884 | "@ | |
56477c21 AS |
2885 | l<g>br\t%0,%1 |
2886 | l<g>b\t%0,%1" | |
ec24698e UW |
2887 | [(set_attr "op_type" "RRE,RXY")]) |
2888 | ||
43a09b63 | 2889 | ; lb, lgb |
56477c21 AS |
2890 | (define_insn "*extendqi<mode>2" |
2891 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2892 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))] | |
2893 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" | |
2894 | "l<g>b\t%0,%1" | |
d3632d41 UW |
2895 | [(set_attr "op_type" "RXY")]) |
2896 | ||
56477c21 AS |
2897 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
2898 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2899 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 2900 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 2901 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
2902 | "#" |
2903 | "&& reload_completed" | |
4023fb28 | 2904 | [(parallel |
56477c21 | 2905 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 2906 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 2907 | (parallel |
56477c21 | 2908 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 2909 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
2910 | { |
2911 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2912 | set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); | |
56477c21 AS |
2913 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) |
2914 | - GET_MODE_BITSIZE (QImode)); | |
6fa05db6 | 2915 | }) |
9db1d521 | 2916 | |
9db1d521 HP |
2917 | ; |
2918 | ; zero_extendsidi2 instruction pattern(s). | |
2919 | ; | |
2920 | ||
4023fb28 UW |
2921 | (define_expand "zero_extendsidi2" |
2922 | [(set (match_operand:DI 0 "register_operand" "") | |
2923 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2924 | "" | |
4023fb28 UW |
2925 | { |
2926 | if (!TARGET_64BIT) | |
2927 | { | |
9f37ccb1 UW |
2928 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2929 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2930 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2931 | DONE; |
2932 | } | |
ec24698e | 2933 | }) |
4023fb28 UW |
2934 | |
2935 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2936 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2937 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2938 | "TARGET_64BIT" | |
2939 | "@ | |
d40c829f UW |
2940 | llgfr\t%0,%1 |
2941 | llgf\t%0,%1" | |
d3632d41 | 2942 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2943 | |
288e517f AK |
2944 | ; |
2945 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2946 | ; | |
2947 | ||
d6083c7d UW |
2948 | (define_insn "*llgt_sidi" |
2949 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2950 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2951 | (const_int 2147483647)))] | |
2952 | "TARGET_64BIT" | |
2953 | "llgt\t%0,%1" | |
2954 | [(set_attr "op_type" "RXE")]) | |
2955 | ||
2956 | (define_insn_and_split "*llgt_sidi_split" | |
2957 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2958 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2959 | (const_int 2147483647))) | |
ae156f85 | 2960 | (clobber (reg:CC CC_REGNUM))] |
d6083c7d UW |
2961 | "TARGET_64BIT" |
2962 | "#" | |
2963 | "&& reload_completed" | |
2964 | [(set (match_dup 0) | |
2965 | (and:DI (subreg:DI (match_dup 1) 0) | |
2966 | (const_int 2147483647)))] | |
2967 | "") | |
2968 | ||
288e517f AK |
2969 | (define_insn "*llgt_sisi" |
2970 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2971 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2972 | (const_int 2147483647)))] | |
c4d50129 | 2973 | "TARGET_ZARCH" |
288e517f AK |
2974 | "@ |
2975 | llgtr\t%0,%1 | |
2976 | llgt\t%0,%1" | |
2977 | [(set_attr "op_type" "RRE,RXE")]) | |
2978 | ||
288e517f AK |
2979 | (define_insn "*llgt_didi" |
2980 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2981 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2982 | (const_int 2147483647)))] | |
2983 | "TARGET_64BIT" | |
2984 | "@ | |
2985 | llgtr\t%0,%1 | |
2986 | llgt\t%0,%N1" | |
2987 | [(set_attr "op_type" "RRE,RXE")]) | |
2988 | ||
f19a9af7 | 2989 | (define_split |
f6ee577c AS |
2990 | [(set (match_operand:GPR 0 "register_operand" "") |
2991 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
2992 | (const_int 2147483647))) | |
ae156f85 | 2993 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 2994 | "TARGET_ZARCH && reload_completed" |
288e517f | 2995 | [(set (match_dup 0) |
f6ee577c AS |
2996 | (and:GPR (match_dup 1) |
2997 | (const_int 2147483647)))] | |
288e517f AK |
2998 | "") |
2999 | ||
9db1d521 | 3000 | ; |
56477c21 | 3001 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3002 | ; |
3003 | ||
56477c21 AS |
3004 | (define_expand "zero_extend<mode>di2" |
3005 | [(set (match_operand:DI 0 "register_operand" "") | |
3006 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3007 | "" | |
3008 | { | |
3009 | if (!TARGET_64BIT) | |
3010 | { | |
3011 | rtx tmp = gen_reg_rtx (SImode); | |
3012 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3013 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3014 | DONE; | |
3015 | } | |
3016 | else if (!TARGET_EXTIMM) | |
3017 | { | |
3018 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - | |
3019 | GET_MODE_BITSIZE(<MODE>mode)); | |
3020 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3021 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
3022 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
3023 | DONE; | |
3024 | } | |
3025 | }) | |
3026 | ||
f6ee577c | 3027 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 3028 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 3029 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 3030 | "" |
4023fb28 | 3031 | { |
ec24698e UW |
3032 | if (!TARGET_EXTIMM) |
3033 | { | |
3034 | operands[1] = gen_lowpart (SImode, operands[1]); | |
3035 | emit_insn (gen_andsi3 (operands[0], operands[1], | |
3036 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); | |
3037 | DONE; | |
56477c21 | 3038 | } |
ec24698e UW |
3039 | }) |
3040 | ||
43a09b63 | 3041 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
3042 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
3043 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3044 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))] | |
ec24698e UW |
3045 | "TARGET_EXTIMM" |
3046 | "@ | |
56477c21 AS |
3047 | ll<g><hc>r\t%0,%1 |
3048 | ll<g><hc>\t%0,%1" | |
ec24698e | 3049 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3050 | |
43a09b63 | 3051 | ; llgh, llgc |
56477c21 AS |
3052 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
3053 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3054 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))] | |
ec24698e | 3055 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 3056 | "llg<hc>\t%0,%1" |
d3632d41 | 3057 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
3058 | |
3059 | (define_insn_and_split "*zero_extendhisi2_31" | |
3060 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 3061 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 3062 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 3063 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3064 | "#" |
3065 | "&& reload_completed" | |
3066 | [(set (match_dup 0) (const_int 0)) | |
3067 | (parallel | |
3068 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 3069 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 3070 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 3071 | |
cc7ab9b7 UW |
3072 | (define_insn_and_split "*zero_extendqisi2_31" |
3073 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3074 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 3075 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3076 | "#" |
3077 | "&& reload_completed" | |
3078 | [(set (match_dup 0) (const_int 0)) | |
3079 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3080 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 3081 | |
9db1d521 HP |
3082 | ; |
3083 | ; zero_extendqihi2 instruction pattern(s). | |
3084 | ; | |
3085 | ||
9db1d521 HP |
3086 | (define_expand "zero_extendqihi2" |
3087 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 3088 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 3089 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 3090 | { |
4023fb28 UW |
3091 | operands[1] = gen_lowpart (HImode, operands[1]); |
3092 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
3093 | DONE; | |
ec24698e | 3094 | }) |
9db1d521 | 3095 | |
4023fb28 | 3096 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 3097 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 3098 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
ec24698e | 3099 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 3100 | "llgc\t%0,%1" |
d3632d41 | 3101 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 3102 | |
cc7ab9b7 UW |
3103 | (define_insn_and_split "*zero_extendqihi2_31" |
3104 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3105 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 3106 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3107 | "#" |
3108 | "&& reload_completed" | |
3109 | [(set (match_dup 0) (const_int 0)) | |
3110 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3111 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 UW |
3112 | |
3113 | ||
9db1d521 | 3114 | ; |
2f8f8434 | 3115 | ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3116 | ; |
3117 | ||
2f8f8434 AS |
3118 | (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2" |
3119 | [(set (match_operand:GPR 0 "register_operand" "") | |
3120 | (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))] | |
3121 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3122 | { |
3123 | rtx label1 = gen_label_rtx (); | |
3124 | rtx label2 = gen_label_rtx (); | |
2f8f8434 AS |
3125 | rtx temp = gen_reg_rtx (<FPR:MODE>mode); |
3126 | REAL_VALUE_TYPE cmp, sub; | |
3127 | ||
3128 | operands[1] = force_reg (<FPR:MODE>mode, operands[1]); | |
3129 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1); | |
3130 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode)); | |
3131 | ||
3132 | emit_insn (gen_cmp<FPR:mode> (operands[1], | |
3133 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode))); | |
9db1d521 | 3134 | emit_jump_insn (gen_blt (label1)); |
2f8f8434 AS |
3135 | emit_insn (gen_sub<FPR:mode>3 (temp, operands[1], |
3136 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode))); | |
3137 | emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp, | |
3138 | GEN_INT(7))); | |
f314b9b1 | 3139 | emit_jump (label2); |
9db1d521 HP |
3140 | |
3141 | emit_label (label1); | |
2f8f8434 AS |
3142 | emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], |
3143 | operands[1], GEN_INT(5))); | |
9db1d521 HP |
3144 | emit_label (label2); |
3145 | DONE; | |
10bbf137 | 3146 | }) |
9db1d521 | 3147 | |
f61a2c7d | 3148 | (define_expand "fix_trunc<mode>di2" |
9db1d521 | 3149 | [(set (match_operand:DI 0 "register_operand" "") |
f61a2c7d | 3150 | (fix:DI (match_operand:DSF 1 "nonimmediate_operand" "")))] |
9db1d521 | 3151 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
9db1d521 | 3152 | { |
f61a2c7d AK |
3153 | operands[1] = force_reg (<MODE>mode, operands[1]); |
3154 | emit_insn (gen_fix_trunc<mode>di2_ieee (operands[0], operands[1], | |
2f8f8434 | 3155 | GEN_INT(5))); |
9db1d521 | 3156 | DONE; |
10bbf137 | 3157 | }) |
9db1d521 | 3158 | |
43a09b63 | 3159 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
2f8f8434 AS |
3160 | (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee" |
3161 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3162 | (fix:GPR (match_operand:FPR 1 "register_operand" "f"))) | |
3163 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 3164 | (clobber (reg:CC CC_REGNUM))] |
2f8f8434 | 3165 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 3166 | "c<GPR:gf><FPR:xde>br\t%0,%h2,%1" |
9db1d521 | 3167 | [(set_attr "op_type" "RRE") |
077dab3b | 3168 | (set_attr "type" "ftoi")]) |
9db1d521 | 3169 | |
f61a2c7d AK |
3170 | ; |
3171 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
3172 | ; | |
3173 | ||
3174 | (define_expand "fix_trunctf<mode>2" | |
3175 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
3176 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
3177 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
3178 | (clobber (reg:CC CC_REGNUM))])] | |
3179 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3180 | "") | |
3181 | ||
9db1d521 | 3182 | ; |
2f8f8434 | 3183 | ; fix_truncdfsi2 instruction pattern(s). |
9db1d521 HP |
3184 | ; |
3185 | ||
9db1d521 HP |
3186 | (define_expand "fix_truncdfsi2" |
3187 | [(set (match_operand:SI 0 "register_operand" "") | |
3188 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
3189 | "TARGET_HARD_FLOAT" | |
9db1d521 | 3190 | { |
c7453384 | 3191 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3192 | { |
3193 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
3194 | ||
c19ec8f9 | 3195 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
3196 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
3197 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
3198 | |
3199 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 3200 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 3201 | two31r, two32, temp)); |
c7453384 EC |
3202 | } |
3203 | else | |
9db1d521 HP |
3204 | { |
3205 | operands[1] = force_reg (DFmode, operands[1]); | |
3206 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3207 | } | |
3208 | ||
3209 | DONE; | |
10bbf137 | 3210 | }) |
9db1d521 | 3211 | |
9db1d521 HP |
3212 | (define_insn "fix_truncdfsi2_ibm" |
3213 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3214 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
3215 | (use (match_operand:DI 2 "immediate_operand" "m")) |
3216 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 | 3217 | (use (match_operand:BLK 4 "memory_operand" "m")) |
ae156f85 | 3218 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3219 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
9db1d521 | 3220 | { |
d40c829f UW |
3221 | output_asm_insn ("sd\t%1,%2", operands); |
3222 | output_asm_insn ("aw\t%1,%3", operands); | |
3223 | output_asm_insn ("std\t%1,%4", operands); | |
3224 | output_asm_insn ("xi\t%N4,128", operands); | |
3225 | return "l\t%0,%N4"; | |
10bbf137 | 3226 | } |
b628bd8e | 3227 | [(set_attr "length" "20")]) |
9db1d521 HP |
3228 | |
3229 | ; | |
2f8f8434 | 3230 | ; fix_truncsfsi2 instruction pattern(s). |
9db1d521 HP |
3231 | ; |
3232 | ||
9db1d521 HP |
3233 | (define_expand "fix_truncsfsi2" |
3234 | [(set (match_operand:SI 0 "register_operand" "") | |
3235 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3236 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3237 | { |
3238 | if (TARGET_IBM_FLOAT) | |
3239 | { | |
3240 | /* Convert to DFmode and then use the POP algorithm. */ | |
3241 | rtx temp = gen_reg_rtx (DFmode); | |
3242 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
3243 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
3244 | } | |
3245 | else | |
3246 | { | |
3247 | operands[1] = force_reg (SFmode, operands[1]); | |
3248 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3249 | } | |
3250 | ||
3251 | DONE; | |
10bbf137 | 3252 | }) |
9db1d521 | 3253 | |
9db1d521 | 3254 | ; |
f61a2c7d | 3255 | ; float(si|di)(tf|df|sf)2 instruction pattern(s). |
9db1d521 HP |
3256 | ; |
3257 | ||
43a09b63 | 3258 | ; cxgbr, cdgbr, cegbr |
f5905b37 AS |
3259 | (define_insn "floatdi<mode>2" |
3260 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
3261 | (float:FPR (match_operand:DI 1 "register_operand" "d")))] | |
9db1d521 | 3262 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 3263 | "c<xde>gbr\t%0,%1" |
9db1d521 | 3264 | [(set_attr "op_type" "RRE") |
077dab3b | 3265 | (set_attr "type" "itof" )]) |
9db1d521 | 3266 | |
43a09b63 | 3267 | ; cxfbr, cdfbr, cefbr |
f61a2c7d AK |
3268 | (define_insn "floatsi<mode>2_ieee" |
3269 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
3270 | (float:FPR (match_operand:SI 1 "register_operand" "d")))] | |
3271 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3272 | "c<xde>fbr\t%0,%1" | |
3273 | [(set_attr "op_type" "RRE") | |
3274 | (set_attr "type" "itof" )]) | |
3275 | ||
3276 | ||
9db1d521 | 3277 | ; |
f61a2c7d | 3278 | ; floatsi(tf|df)2 instruction pattern(s). |
9db1d521 HP |
3279 | ; |
3280 | ||
f61a2c7d AK |
3281 | (define_expand "floatsitf2" |
3282 | [(set (match_operand:TF 0 "register_operand" "") | |
3283 | (float:TF (match_operand:SI 1 "register_operand" "")))] | |
3284 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3285 | "") | |
3286 | ||
9db1d521 | 3287 | (define_expand "floatsidf2" |
a036c6f7 UW |
3288 | [(set (match_operand:DF 0 "register_operand" "") |
3289 | (float:DF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3290 | "TARGET_HARD_FLOAT" |
9db1d521 | 3291 | { |
c7453384 | 3292 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3293 | { |
3294 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
3295 | ||
c19ec8f9 | 3296 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 3297 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
3298 | |
3299 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
3300 | DONE; | |
3301 | } | |
10bbf137 | 3302 | }) |
9db1d521 | 3303 | |
9db1d521 HP |
3304 | (define_insn "floatsidf2_ibm" |
3305 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3306 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3307 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 | 3308 | (use (match_operand:BLK 3 "memory_operand" "m")) |
ae156f85 | 3309 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3310 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
9db1d521 | 3311 | { |
d40c829f UW |
3312 | output_asm_insn ("st\t%1,%N3", operands); |
3313 | output_asm_insn ("xi\t%N3,128", operands); | |
3314 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3315 | output_asm_insn ("ld\t%0,%3", operands); | |
3316 | return "sd\t%0,%2"; | |
10bbf137 | 3317 | } |
b628bd8e | 3318 | [(set_attr "length" "20")]) |
9db1d521 HP |
3319 | |
3320 | ; | |
3321 | ; floatsisf2 instruction pattern(s). | |
3322 | ; | |
3323 | ||
3324 | (define_expand "floatsisf2" | |
a036c6f7 UW |
3325 | [(set (match_operand:SF 0 "register_operand" "") |
3326 | (float:SF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3327 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3328 | { |
3329 | if (TARGET_IBM_FLOAT) | |
3330 | { | |
3331 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3332 | rtx temp = gen_reg_rtx (DFmode); | |
3333 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3334 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3335 | DONE; | |
3336 | } | |
10bbf137 | 3337 | }) |
9db1d521 | 3338 | |
9db1d521 HP |
3339 | ; |
3340 | ; truncdfsf2 instruction pattern(s). | |
3341 | ; | |
3342 | ||
3343 | (define_expand "truncdfsf2" | |
3344 | [(set (match_operand:SF 0 "register_operand" "") | |
a036c6f7 | 3345 | (float_truncate:SF (match_operand:DF 1 "register_operand" "")))] |
9db1d521 | 3346 | "TARGET_HARD_FLOAT" |
4023fb28 | 3347 | "") |
9db1d521 HP |
3348 | |
3349 | (define_insn "truncdfsf2_ieee" | |
3350 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3351 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
9db1d521 | 3352 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3353 | "ledbr\t%0,%1" |
f61a2c7d AK |
3354 | [(set_attr "op_type" "RRE") |
3355 | (set_attr "type" "ftruncdf")]) | |
9db1d521 HP |
3356 | |
3357 | (define_insn "truncdfsf2_ibm" | |
3358 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
a036c6f7 | 3359 | (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3360 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3361 | "@ | |
a036c6f7 | 3362 | ler\t%0,%1 |
d40c829f | 3363 | le\t%0,%1" |
4023fb28 | 3364 | [(set_attr "op_type" "RR,RX") |
cfdb984b | 3365 | (set_attr "type" "floadsf")]) |
9db1d521 | 3366 | |
f61a2c7d AK |
3367 | ; |
3368 | ; trunctfdf2 instruction pattern(s). | |
3369 | ; | |
3370 | ||
3371 | (define_expand "trunctfdf2" | |
3372 | [(parallel | |
3373 | [(set (match_operand:DF 0 "register_operand" "") | |
3374 | (float_truncate:DF (match_operand:TF 1 "register_operand" ""))) | |
3375 | (clobber (match_scratch:TF 2 "=f"))])] | |
3376 | "TARGET_HARD_FLOAT" | |
3377 | "") | |
3378 | ||
3379 | (define_insn "*trunctfdf2_ieee" | |
3380 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3381 | (float_truncate:DF (match_operand:TF 1 "register_operand" "f"))) | |
3382 | (clobber (match_scratch:TF 2 "=f"))] | |
3383 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3384 | "ldxbr\t%2,%1\;ldr\t%0,%2" | |
3385 | [(set_attr "length" "6") | |
3386 | (set_attr "type" "ftrunctf")]) | |
3387 | ||
3388 | (define_insn "*trunctfdf2_ibm" | |
3389 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3390 | (float_truncate:DF (match_operand:TF 1 "register_operand" "f"))) | |
3391 | (clobber (match_scratch:TF 2 "=f"))] | |
3392 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3393 | "ldxr\t%2,%1\;ldr\t%0,%2" | |
3394 | [(set_attr "length" "4") | |
3395 | (set_attr "type" "ftrunctf")]) | |
3396 | ||
3397 | ; | |
3398 | ; trunctfsf2 instruction pattern(s). | |
3399 | ; | |
3400 | ||
3401 | (define_expand "trunctfsf2" | |
3402 | [(parallel | |
3403 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3404 | (float_truncate:SF (match_operand:TF 1 "register_operand" "f"))) | |
3405 | (clobber (match_scratch:TF 2 "=f"))])] | |
3406 | "TARGET_HARD_FLOAT" | |
3407 | "") | |
3408 | ||
3409 | (define_insn "*trunctfsf2_ieee" | |
3410 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3411 | (float_truncate:SF (match_operand:TF 1 "register_operand" "f"))) | |
3412 | (clobber (match_scratch:TF 2 "=f"))] | |
3413 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3414 | "lexbr\t%2,%1\;ler\t%0,%2" | |
3415 | [(set_attr "length" "6") | |
3416 | (set_attr "type" "ftrunctf")]) | |
3417 | ||
3418 | (define_insn "*trunctfsf2_ibm" | |
3419 | [(set (match_operand:SF 0 "register_operand" "=f") | |
3420 | (float_truncate:SF (match_operand:TF 1 "register_operand" "f"))) | |
3421 | (clobber (match_scratch:TF 2 "=f"))] | |
3422 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3423 | "lexr\t%2,%1\;ler\t%0,%2" | |
3424 | [(set_attr "length" "6") | |
3425 | (set_attr "type" "ftrunctf")]) | |
3426 | ||
9db1d521 HP |
3427 | ; |
3428 | ; extendsfdf2 instruction pattern(s). | |
3429 | ; | |
3430 | ||
3431 | (define_expand "extendsfdf2" | |
3432 | [(set (match_operand:DF 0 "register_operand" "") | |
3433 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3434 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3435 | { |
3436 | if (TARGET_IBM_FLOAT) | |
3437 | { | |
3438 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3439 | DONE; | |
3440 | } | |
10bbf137 | 3441 | }) |
9db1d521 HP |
3442 | |
3443 | (define_insn "extendsfdf2_ieee" | |
3444 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3445 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3446 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3447 | "@ | |
d40c829f UW |
3448 | ldebr\t%0,%1 |
3449 | ldeb\t%0,%1" | |
077dab3b | 3450 | [(set_attr "op_type" "RRE,RXE") |
f61a2c7d | 3451 | (set_attr "type" "fsimpsf, floadsf")]) |
9db1d521 HP |
3452 | |
3453 | (define_insn "extendsfdf2_ibm" | |
3454 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3455 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
ae156f85 | 3456 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3457 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3458 | "@ | |
d40c829f UW |
3459 | sdr\t%0,%0\;ler\t%0,%1 |
3460 | sdr\t%0,%0\;le\t%0,%1" | |
b628bd8e | 3461 | [(set_attr "length" "4,6") |
cfdb984b | 3462 | (set_attr "type" "floadsf")]) |
9db1d521 | 3463 | |
f61a2c7d AK |
3464 | ; |
3465 | ; extenddftf2 instruction pattern(s). | |
3466 | ; | |
3467 | ||
3468 | (define_expand "extenddftf2" | |
3469 | [(set (match_operand:TF 0 "register_operand" "") | |
3470 | (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "")))] | |
3471 | "TARGET_HARD_FLOAT" | |
3472 | "") | |
3473 | ||
3474 | (define_insn "*extenddftf2_ieee" | |
3475 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
3476 | (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] | |
3477 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3478 | "@ | |
3479 | lxdbr\t%0,%1 | |
3480 | lxdb\t%0,%1" | |
3481 | [(set_attr "op_type" "RRE,RXE") | |
3482 | (set_attr "type" "fsimptf, floadtf")]) | |
3483 | ||
3484 | (define_insn "*extenddftf2_ibm" | |
3485 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
3486 | (float_extend:TF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] | |
3487 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3488 | "@ | |
3489 | lxdr\t%0,%1 | |
3490 | lxd\t%0,%1" | |
3491 | [(set_attr "op_type" "RRE,RXE") | |
3492 | (set_attr "type" "fsimptf, floadtf")]) | |
3493 | ||
3494 | ; | |
3495 | ; extendsftf2 instruction pattern(s). | |
3496 | ; | |
3497 | ||
3498 | (define_expand "extendsftf2" | |
3499 | [(set (match_operand:TF 0 "register_operand" "") | |
3500 | (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3501 | "TARGET_HARD_FLOAT" | |
3502 | "") | |
3503 | ||
3504 | (define_insn "*extendsftf2_ieee" | |
3505 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
3506 | (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] | |
3507 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3508 | "@ | |
3509 | lxebr\t%0,%1 | |
3510 | lxeb\t%0,%1" | |
3511 | [(set_attr "op_type" "RRE,RXE") | |
3512 | (set_attr "type" "fsimptf, floadtf")]) | |
3513 | ||
3514 | (define_insn "*extendsftf2_ibm" | |
3515 | [(set (match_operand:TF 0 "register_operand" "=f,f") | |
3516 | (float_extend:TF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] | |
3517 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3518 | "@ | |
3519 | lxer\t%0,%1 | |
3520 | lxe\t%0,%1" | |
3521 | [(set_attr "op_type" "RRE,RXE") | |
3522 | (set_attr "type" "fsimptf, floadtf")]) | |
3523 | ||
9db1d521 HP |
3524 | |
3525 | ;; | |
fae778eb | 3526 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3527 | ;; |
fae778eb | 3528 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3529 | ; because of unpredictable Bits in Register for Halfword and Byte |
3530 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3531 | ||
07893d4f UW |
3532 | ;; |
3533 | ;;- Add instructions. | |
3534 | ;; | |
3535 | ||
1c7b1b7e UW |
3536 | ; |
3537 | ; addti3 instruction pattern(s). | |
3538 | ; | |
3539 | ||
3540 | (define_insn_and_split "addti3" | |
3541 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3542 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
3543 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 3544 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
3545 | "TARGET_64BIT" |
3546 | "#" | |
3547 | "&& reload_completed" | |
3548 | [(parallel | |
ae156f85 | 3549 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
3550 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
3551 | (match_dup 7))) | |
3552 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
3553 | (parallel | |
3554 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3555 | (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)))) |
3556 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
3557 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
3558 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3559 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3560 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3561 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3562 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3563 | |
07893d4f UW |
3564 | ; |
3565 | ; adddi3 instruction pattern(s). | |
3566 | ; | |
3567 | ||
3298c037 AK |
3568 | (define_expand "adddi3" |
3569 | [(parallel | |
3570 | [(set (match_operand:DI 0 "register_operand" "") | |
3571 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
3572 | (match_operand:DI 2 "general_operand" ""))) | |
3573 | (clobber (reg:CC CC_REGNUM))])] | |
3574 | "" | |
3575 | "") | |
3576 | ||
07893d4f UW |
3577 | (define_insn "*adddi3_sign" |
3578 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3579 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3580 | (match_operand:DI 1 "register_operand" "0,0"))) | |
ae156f85 | 3581 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3582 | "TARGET_64BIT" |
3583 | "@ | |
d40c829f UW |
3584 | agfr\t%0,%2 |
3585 | agf\t%0,%2" | |
d3632d41 | 3586 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3587 | |
3588 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 3589 | [(set (reg CC_REGNUM) |
07893d4f UW |
3590 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3591 | (match_operand:DI 1 "register_operand" "0,0")) | |
3592 | (const_int 0))) | |
3593 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3594 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3595 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3596 | "@ | |
d40c829f UW |
3597 | algfr\t%0,%2 |
3598 | algf\t%0,%2" | |
d3632d41 | 3599 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3600 | |
3601 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 3602 | [(set (reg CC_REGNUM) |
07893d4f UW |
3603 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3604 | (match_operand:DI 1 "register_operand" "0,0")) | |
3605 | (const_int 0))) | |
3606 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3607 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3608 | "@ | |
d40c829f UW |
3609 | algfr\t%0,%2 |
3610 | algf\t%0,%2" | |
d3632d41 | 3611 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3612 | |
3613 | (define_insn "*adddi3_zero" | |
3614 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3615 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3616 | (match_operand:DI 1 "register_operand" "0,0"))) | |
ae156f85 | 3617 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3618 | "TARGET_64BIT" |
3619 | "@ | |
d40c829f UW |
3620 | algfr\t%0,%2 |
3621 | algf\t%0,%2" | |
d3632d41 | 3622 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3623 | |
e69166de UW |
3624 | (define_insn_and_split "*adddi3_31z" |
3625 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3626 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3627 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 3628 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
3629 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
3630 | "#" | |
3631 | "&& reload_completed" | |
3632 | [(parallel | |
ae156f85 | 3633 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
3634 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
3635 | (match_dup 7))) | |
3636 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3637 | (parallel | |
3638 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3639 | (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)))) |
3640 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
3641 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3642 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3643 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3644 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3645 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3646 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3647 | |
07893d4f UW |
3648 | (define_insn_and_split "*adddi3_31" |
3649 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3650 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3651 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 3652 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 3653 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3654 | "#" |
3655 | "&& reload_completed" | |
3656 | [(parallel | |
3657 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 3658 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3659 | (parallel |
ae156f85 | 3660 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
3661 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
3662 | (match_dup 7))) | |
3663 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3664 | (set (pc) | |
ae156f85 | 3665 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
3666 | (pc) |
3667 | (label_ref (match_dup 9)))) | |
3668 | (parallel | |
3669 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 3670 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3671 | (match_dup 9)] |
97c6f7ad UW |
3672 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3673 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3674 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3675 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3676 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3677 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3678 | operands[9] = gen_label_rtx ();") |
9db1d521 | 3679 | |
3298c037 AK |
3680 | ; |
3681 | ; addsi3 instruction pattern(s). | |
3682 | ; | |
3683 | ||
3684 | (define_expand "addsi3" | |
07893d4f | 3685 | [(parallel |
3298c037 AK |
3686 | [(set (match_operand:SI 0 "register_operand" "") |
3687 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
3688 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 3689 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 3690 | "" |
07893d4f | 3691 | "") |
9db1d521 | 3692 | |
3298c037 AK |
3693 | (define_insn "*addsi3_sign" |
3694 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3695 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
3696 | (match_operand:SI 1 "register_operand" "0,0"))) | |
3697 | (clobber (reg:CC CC_REGNUM))] | |
3698 | "" | |
3699 | "@ | |
3700 | ah\t%0,%2 | |
3701 | ahy\t%0,%2" | |
3702 | [(set_attr "op_type" "RX,RXY")]) | |
3703 | ||
9db1d521 | 3704 | ; |
3298c037 | 3705 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 3706 | ; |
9db1d521 | 3707 | |
43a09b63 | 3708 | ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag |
3298c037 AK |
3709 | (define_insn "*add<mode>3" |
3710 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d") | |
3711 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
3712 | (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T") ) ) | |
3713 | (clobber (reg:CC CC_REGNUM))] | |
3714 | "" | |
ec24698e | 3715 | "@ |
3298c037 AK |
3716 | a<g>r\t%0,%2 |
3717 | a<g>hi\t%0,%h2 | |
3718 | al<g>fi\t%0,%2 | |
3719 | sl<g>fi\t%0,%n2 | |
3720 | a<g>\t%0,%2 | |
3721 | a<y>\t%0,%2" | |
3722 | [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY")]) | |
0a3bdf9d | 3723 | |
43a09b63 | 3724 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg |
3298c037 | 3725 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 3726 | [(set (reg CC_REGNUM) |
3298c037 AK |
3727 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0") |
3728 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T")) | |
07893d4f | 3729 | (match_dup 1))) |
3298c037 AK |
3730 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") |
3731 | (plus:GPR (match_dup 1) (match_dup 2)))] | |
c7453384 | 3732 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3733 | "@ |
3298c037 AK |
3734 | al<g>r\t%0,%2 |
3735 | al<g>fi\t%0,%2 | |
3736 | sl<g>fi\t%0,%n2 | |
3737 | al<g>\t%0,%2 | |
3738 | al<y>\t%0,%2" | |
3739 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")]) | |
07893d4f | 3740 | |
43a09b63 | 3741 | ; alr, al, aly, algr, alg |
3298c037 | 3742 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 3743 | [(set (reg CC_REGNUM) |
3298c037 AK |
3744 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
3745 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 3746 | (match_dup 1))) |
3298c037 | 3747 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 3748 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3749 | "@ |
3298c037 AK |
3750 | al<g>r\t%0,%2 |
3751 | al<g>\t%0,%2 | |
3752 | al<y>\t%0,%2" | |
3753 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
07893d4f | 3754 | |
43a09b63 | 3755 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg |
3298c037 | 3756 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 3757 | [(set (reg CC_REGNUM) |
3298c037 AK |
3758 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0") |
3759 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T")) | |
07893d4f | 3760 | (match_dup 2))) |
3298c037 AK |
3761 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") |
3762 | (plus:GPR (match_dup 1) (match_dup 2)))] | |
c7453384 | 3763 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3764 | "@ |
3298c037 AK |
3765 | al<g>r\t%0,%2 |
3766 | al<g>fi\t%0,%2 | |
3767 | sl<g>fi\t%0,%n2 | |
3768 | al<g>\t%0,%2 | |
3769 | al<y>\t%0,%2" | |
3770 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")]) | |
07893d4f | 3771 | |
43a09b63 | 3772 | ; alr, al, aly, algr, alg |
3298c037 | 3773 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 3774 | [(set (reg CC_REGNUM) |
3298c037 AK |
3775 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
3776 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 3777 | (match_dup 2))) |
3298c037 | 3778 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 3779 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3780 | "@ |
3298c037 AK |
3781 | al<g>r\t%0,%2 |
3782 | al<g>\t%0,%2 | |
3783 | al<y>\t%0,%2" | |
3784 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
07893d4f | 3785 | |
43a09b63 | 3786 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg |
3298c037 | 3787 | (define_insn "*add<mode>3_cc" |
ae156f85 | 3788 | [(set (reg CC_REGNUM) |
3298c037 AK |
3789 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0") |
3790 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T")) | |
9db1d521 | 3791 | (const_int 0))) |
3298c037 AK |
3792 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d") |
3793 | (plus:GPR (match_dup 1) (match_dup 2)))] | |
c7453384 | 3794 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3795 | "@ |
3298c037 AK |
3796 | al<g>r\t%0,%2 |
3797 | al<g>fi\t%0,%2 | |
3798 | sl<g>fi\t%0,%n2 | |
3799 | al<g>\t%0,%2 | |
3800 | al<y>\t%0,%2" | |
3801 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY")]) | |
9db1d521 | 3802 | |
43a09b63 | 3803 | ; alr, al, aly, algr, alg |
3298c037 | 3804 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 3805 | [(set (reg CC_REGNUM) |
3298c037 AK |
3806 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
3807 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 3808 | (const_int 0))) |
3298c037 | 3809 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 3810 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3811 | "@ |
3298c037 AK |
3812 | al<g>r\t%0,%2 |
3813 | al<g>\t%0,%2 | |
3814 | al<y>\t%0,%2" | |
3815 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
9db1d521 | 3816 | |
43a09b63 | 3817 | ; alr, al, aly, algr, alg |
3298c037 | 3818 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 3819 | [(set (reg CC_REGNUM) |
3298c037 AK |
3820 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
3821 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T")))) | |
3822 | (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
3823 | "s390_match_ccmode(insn, CCLmode)" | |
d3632d41 | 3824 | "@ |
3298c037 AK |
3825 | al<g>r\t%0,%2 |
3826 | al<g>\t%0,%2 | |
3827 | al<y>\t%0,%2" | |
3828 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
07893d4f | 3829 | |
43a09b63 | 3830 | ; ahi, afi, aghi, agfi |
3298c037 AK |
3831 | (define_insn "*add<mode>3_imm_cc" |
3832 | [(set (reg CC_REGNUM) | |
3833 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3834 | (match_operand:GPR 2 "const_int_operand" "K,Os")) | |
3835 | (const_int 0))) | |
3836 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
3837 | (plus:GPR (match_dup 1) (match_dup 2)))] | |
3838 | "s390_match_ccmode (insn, CCAmode) | |
3839 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
3840 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")) | |
3841 | && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" | |
9db1d521 | 3842 | "@ |
3298c037 AK |
3843 | a<g>hi\t%0,%h2 |
3844 | a<g>fi\t%0,%2" | |
3845 | [(set_attr "op_type" "RI,RIL")]) | |
9db1d521 | 3846 | |
9db1d521 | 3847 | ; |
f5905b37 | 3848 | ; add(df|sf)3 instruction pattern(s). |
9db1d521 HP |
3849 | ; |
3850 | ||
f5905b37 | 3851 | (define_expand "add<mode>3" |
9db1d521 | 3852 | [(parallel |
f5905b37 AS |
3853 | [(set (match_operand:FPR 0 "register_operand" "=f,f") |
3854 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
f61a2c7d | 3855 | (match_operand:FPR 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 3856 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
3857 | "TARGET_HARD_FLOAT" |
3858 | "") | |
3859 | ||
43a09b63 | 3860 | ; axbr, adbr, aebr, axb, adb, aeb |
f5905b37 AS |
3861 | (define_insn "*add<mode>3" |
3862 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3863 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
f61a2c7d | 3864 | (match_operand:FPR 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 3865 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3866 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3867 | "@ | |
f61a2c7d AK |
3868 | a<xde>br\t%0,%2 |
3869 | a<xde>b\t%0,%2" | |
ce50cae8 | 3870 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3871 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 3872 | |
43a09b63 | 3873 | ; axbr, adbr, aebr, axb, adb, aeb |
f5905b37 | 3874 | (define_insn "*add<mode>3_cc" |
ae156f85 | 3875 | [(set (reg CC_REGNUM) |
f5905b37 | 3876 | (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") |
f61a2c7d | 3877 | (match_operand:FPR 2 "general_operand" "f,<Rf>")) |
f5905b37 AS |
3878 | (match_operand:FPR 3 "const0_operand" ""))) |
3879 | (set (match_operand:FPR 0 "register_operand" "=f,f") | |
3880 | (plus:FPR (match_dup 1) (match_dup 2)))] | |
3ef093a8 AK |
3881 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3882 | "@ | |
f61a2c7d AK |
3883 | a<xde>br\t%0,%2 |
3884 | a<xde>b\t%0,%2" | |
3ef093a8 | 3885 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3886 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3887 | |
43a09b63 | 3888 | ; axbr, adbr, aebr, axb, adb, aeb |
f5905b37 | 3889 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 3890 | [(set (reg CC_REGNUM) |
f5905b37 | 3891 | (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") |
f61a2c7d | 3892 | (match_operand:FPR 2 "general_operand" "f,<Rf>")) |
f5905b37 AS |
3893 | (match_operand:FPR 3 "const0_operand" ""))) |
3894 | (clobber (match_scratch:FPR 0 "=f,f"))] | |
3ef093a8 AK |
3895 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3896 | "@ | |
f61a2c7d AK |
3897 | a<xde>br\t%0,%2 |
3898 | a<xde>b\t%0,%2" | |
3ef093a8 | 3899 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3900 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3901 | |
43a09b63 | 3902 | ; axr, adr, aer, ax, ad, ae |
f5905b37 AS |
3903 | (define_insn "*add<mode>3_ibm" |
3904 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3905 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
f61a2c7d | 3906 | (match_operand:FPR 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 3907 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3908 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3909 | "@ | |
f61a2c7d AK |
3910 | a<xde>r\t%0,%2 |
3911 | a<xde>\t%0,%2" | |
3912 | [(set_attr "op_type" "<RRe>,<RXe>") | |
f5905b37 | 3913 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
3914 | |
3915 | ||
3916 | ;; | |
3917 | ;;- Subtract instructions. | |
3918 | ;; | |
3919 | ||
1c7b1b7e UW |
3920 | ; |
3921 | ; subti3 instruction pattern(s). | |
3922 | ; | |
3923 | ||
3924 | (define_insn_and_split "subti3" | |
3925 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3926 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3927 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 3928 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
3929 | "TARGET_64BIT" |
3930 | "#" | |
3931 | "&& reload_completed" | |
3932 | [(parallel | |
ae156f85 | 3933 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
3934 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
3935 | (match_dup 7))) | |
3936 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3937 | (parallel | |
3938 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3939 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
3940 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
3941 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
3942 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3943 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3944 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3945 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3946 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3947 | |
9db1d521 HP |
3948 | ; |
3949 | ; subdi3 instruction pattern(s). | |
3950 | ; | |
3951 | ||
3298c037 AK |
3952 | (define_expand "subdi3" |
3953 | [(parallel | |
3954 | [(set (match_operand:DI 0 "register_operand" "") | |
3955 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3956 | (match_operand:DI 2 "general_operand" ""))) | |
3957 | (clobber (reg:CC CC_REGNUM))])] | |
3958 | "" | |
3959 | "") | |
3960 | ||
07893d4f UW |
3961 | (define_insn "*subdi3_sign" |
3962 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3963 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3964 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
ae156f85 | 3965 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3966 | "TARGET_64BIT" |
3967 | "@ | |
d40c829f UW |
3968 | sgfr\t%0,%2 |
3969 | sgf\t%0,%2" | |
d3632d41 | 3970 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3971 | |
3972 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 3973 | [(set (reg CC_REGNUM) |
07893d4f UW |
3974 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3975 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3976 | (const_int 0))) | |
3977 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3978 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3979 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3980 | "@ | |
d40c829f UW |
3981 | slgfr\t%0,%2 |
3982 | slgf\t%0,%2" | |
d3632d41 | 3983 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3984 | |
3985 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 3986 | [(set (reg CC_REGNUM) |
07893d4f UW |
3987 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3988 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3989 | (const_int 0))) | |
3990 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3991 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3992 | "@ | |
d40c829f UW |
3993 | slgfr\t%0,%2 |
3994 | slgf\t%0,%2" | |
d3632d41 | 3995 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3996 | |
3997 | (define_insn "*subdi3_zero" | |
3998 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3999 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
4000 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
ae156f85 | 4001 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4002 | "TARGET_64BIT" |
4003 | "@ | |
d40c829f UW |
4004 | slgfr\t%0,%2 |
4005 | slgf\t%0,%2" | |
d3632d41 | 4006 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 4007 | |
e69166de UW |
4008 | (define_insn_and_split "*subdi3_31z" |
4009 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4010 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4011 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4012 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
4013 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4014 | "#" | |
4015 | "&& reload_completed" | |
4016 | [(parallel | |
ae156f85 | 4017 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
4018 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4019 | (match_dup 7))) | |
4020 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4021 | (parallel | |
4022 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4023 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4024 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
4025 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4026 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4027 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4028 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4029 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4030 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4031 | |
07893d4f UW |
4032 | (define_insn_and_split "*subdi3_31" |
4033 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4034 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 4035 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4036 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4037 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4038 | "#" |
4039 | "&& reload_completed" | |
4040 | [(parallel | |
4041 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4042 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4043 | (parallel |
ae156f85 | 4044 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
4045 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4046 | (match_dup 7))) | |
4047 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4048 | (set (pc) | |
ae156f85 | 4049 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4050 | (pc) |
4051 | (label_ref (match_dup 9)))) | |
4052 | (parallel | |
4053 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 4054 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4055 | (match_dup 9)] |
97c6f7ad UW |
4056 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4057 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4058 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4059 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4060 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4061 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4062 | operands[9] = gen_label_rtx ();") |
07893d4f | 4063 | |
3298c037 AK |
4064 | ; |
4065 | ; subsi3 instruction pattern(s). | |
4066 | ; | |
4067 | ||
4068 | (define_expand "subsi3" | |
07893d4f | 4069 | [(parallel |
3298c037 AK |
4070 | [(set (match_operand:SI 0 "register_operand" "") |
4071 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
4072 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4073 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4074 | "" |
07893d4f | 4075 | "") |
9db1d521 | 4076 | |
3298c037 AK |
4077 | (define_insn "*subsi3_sign" |
4078 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4079 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4080 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
4081 | (clobber (reg:CC CC_REGNUM))] | |
4082 | "" | |
4083 | "@ | |
4084 | sh\t%0,%2 | |
4085 | shy\t%0,%2" | |
4086 | [(set_attr "op_type" "RX,RXY")]) | |
4087 | ||
9db1d521 | 4088 | ; |
3298c037 | 4089 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
4090 | ; |
4091 | ||
43a09b63 | 4092 | ; sr, s, sy, sgr, sg |
3298c037 AK |
4093 | (define_insn "*sub<mode>3" |
4094 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4095 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") | |
4096 | (match_operand:GPR 2 "general_operand" "d,R,T") ) ) | |
4097 | (clobber (reg:CC CC_REGNUM))] | |
4098 | "" | |
4099 | "@ | |
4100 | s<g>r\t%0,%2 | |
4101 | s<g>\t%0,%2 | |
4102 | s<y>\t%0,%2" | |
4103 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
4104 | ||
43a09b63 | 4105 | ; slr, sl, sly, slgr, slg |
3298c037 | 4106 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 4107 | [(set (reg CC_REGNUM) |
3298c037 AK |
4108 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4109 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4110 | (match_dup 1))) |
3298c037 AK |
4111 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") |
4112 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 4113 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4114 | "@ |
3298c037 AK |
4115 | sl<g>r\t%0,%2 |
4116 | sl<g>\t%0,%2 | |
4117 | sl<y>\t%0,%2" | |
4118 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
07893d4f | 4119 | |
43a09b63 | 4120 | ; slr, sl, sly, slgr, slg |
3298c037 | 4121 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 4122 | [(set (reg CC_REGNUM) |
3298c037 AK |
4123 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4124 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4125 | (match_dup 1))) |
3298c037 | 4126 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
b2ba71ca | 4127 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4128 | "@ |
3298c037 AK |
4129 | sl<g>r\t%0,%2 |
4130 | sl<g>\t%0,%2 | |
4131 | sl<y>\t%0,%2" | |
4132 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
07893d4f | 4133 | |
43a09b63 | 4134 | ; slr, sl, sly, slgr, slg |
3298c037 | 4135 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4136 | [(set (reg CC_REGNUM) |
3298c037 AK |
4137 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4138 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 4139 | (const_int 0))) |
3298c037 AK |
4140 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") |
4141 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 4142 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4143 | "@ |
3298c037 AK |
4144 | sl<g>r\t%0,%2 |
4145 | sl<g>\t%0,%2 | |
4146 | sl<y>\t%0,%2" | |
4147 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
9db1d521 | 4148 | |
43a09b63 | 4149 | ; slr, sl, sly, slgr, slg |
3298c037 | 4150 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 4151 | [(set (reg CC_REGNUM) |
3298c037 AK |
4152 | (compare (match_operand:GPR 1 "register_operand" "0,0,0") |
4153 | (match_operand:GPR 2 "general_operand" "d,R,T"))) | |
4154 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4155 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
5d880bd2 UW |
4156 | "s390_match_ccmode (insn, CCL3mode)" |
4157 | "@ | |
3298c037 AK |
4158 | sl<g>r\t%0,%2 |
4159 | sl<g>\t%0,%2 | |
4160 | sl<y>\t%0,%2" | |
4161 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
5d880bd2 | 4162 | |
43a09b63 | 4163 | ; slr, sl, sly, slgr, slg |
3298c037 | 4164 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 4165 | [(set (reg CC_REGNUM) |
3298c037 AK |
4166 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4167 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 4168 | (const_int 0))) |
3298c037 | 4169 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
b2ba71ca | 4170 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4171 | "@ |
3298c037 AK |
4172 | sl<g>r\t%0,%2 |
4173 | sl<g>\t%0,%2 | |
4174 | sl<y>\t%0,%2" | |
4175 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
9db1d521 | 4176 | |
43a09b63 | 4177 | ; slr, sl, sly, slgr, slg |
3298c037 | 4178 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 4179 | [(set (reg CC_REGNUM) |
3298c037 AK |
4180 | (compare (match_operand:GPR 1 "register_operand" "0,0,0") |
4181 | (match_operand:GPR 2 "general_operand" "d,R,T"))) | |
4182 | (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
5d880bd2 UW |
4183 | "s390_match_ccmode (insn, CCL3mode)" |
4184 | "@ | |
3298c037 AK |
4185 | sl<g>r\t%0,%2 |
4186 | sl<g>\t%0,%2 | |
4187 | sl<y>\t%0,%2" | |
4188 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY")]) | |
9db1d521 HP |
4189 | |
4190 | ; | |
f5905b37 | 4191 | ; sub(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4192 | ; |
4193 | ||
f5905b37 | 4194 | (define_expand "sub<mode>3" |
9db1d521 | 4195 | [(parallel |
f5905b37 AS |
4196 | [(set (match_operand:FPR 0 "register_operand" "=f,f") |
4197 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4198 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 4199 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
4200 | "TARGET_HARD_FLOAT" |
4201 | "") | |
4202 | ||
43a09b63 | 4203 | ; sxbr, sdbr, sebr, sxb, sdb, seb |
f5905b37 AS |
4204 | (define_insn "*sub<mode>3" |
4205 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4206 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
f61a2c7d | 4207 | (match_operand:FPR 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 4208 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
4209 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4210 | "@ | |
f61a2c7d AK |
4211 | s<xde>br\t%0,%2 |
4212 | s<xde>b\t%0,%2" | |
ce50cae8 | 4213 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4214 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4215 | |
43a09b63 | 4216 | ; sxbr, sdbr, sebr, sxb, sdb, seb |
f5905b37 | 4217 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4218 | [(set (reg CC_REGNUM) |
f5905b37 | 4219 | (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") |
f61a2c7d | 4220 | (match_operand:FPR 2 "general_operand" "f,<Rf>")) |
f5905b37 AS |
4221 | (match_operand:FPR 3 "const0_operand" ""))) |
4222 | (set (match_operand:FPR 0 "register_operand" "=f,f") | |
4223 | (minus:FPR (match_dup 1) (match_dup 2)))] | |
3ef093a8 AK |
4224 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4225 | "@ | |
f61a2c7d AK |
4226 | s<xde>br\t%0,%2 |
4227 | s<xde>b\t%0,%2" | |
3ef093a8 | 4228 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4229 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4230 | |
43a09b63 | 4231 | ; sxbr, sdbr, sebr, sxb, sdb, seb |
f5905b37 | 4232 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 4233 | [(set (reg CC_REGNUM) |
f5905b37 | 4234 | (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") |
f61a2c7d | 4235 | (match_operand:FPR 2 "general_operand" "f,<Rf>")) |
f5905b37 AS |
4236 | (match_operand:FPR 3 "const0_operand" ""))) |
4237 | (clobber (match_scratch:FPR 0 "=f,f"))] | |
3ef093a8 AK |
4238 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4239 | "@ | |
f61a2c7d AK |
4240 | s<xde>br\t%0,%2 |
4241 | s<xde>b\t%0,%2" | |
3ef093a8 | 4242 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4243 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4244 | |
43a09b63 | 4245 | ; sxr, sdr, ser, sx, sd, se |
f5905b37 AS |
4246 | (define_insn "*sub<mode>3_ibm" |
4247 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4248 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
f61a2c7d | 4249 | (match_operand:FPR 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 4250 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
4251 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4252 | "@ | |
f61a2c7d AK |
4253 | s<xde>r\t%0,%2 |
4254 | s<xde>\t%0,%2" | |
4255 | [(set_attr "op_type" "<RRe>,<RXe>") | |
f5905b37 | 4256 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
4257 | |
4258 | ||
e69166de UW |
4259 | ;; |
4260 | ;;- Conditional add/subtract instructions. | |
4261 | ;; | |
4262 | ||
4263 | ; | |
9a91a21f | 4264 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
4265 | ; |
4266 | ||
43a09b63 | 4267 | ; alcr, alc, alcgr, alcg |
9a91a21f | 4268 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 4269 | [(set (reg CC_REGNUM) |
e69166de | 4270 | (compare |
9a91a21f AS |
4271 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") |
4272 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4273 | (match_operand:GPR 3 "s390_alc_comparison" "")) | |
e69166de | 4274 | (const_int 0))) |
9a91a21f AS |
4275 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
4276 | (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4277 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4278 | "@ |
9a91a21f AS |
4279 | alc<g>r\t%0,%2 |
4280 | alc<g>\t%0,%2" | |
e69166de UW |
4281 | [(set_attr "op_type" "RRE,RXY")]) |
4282 | ||
43a09b63 | 4283 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
4284 | (define_insn "*add<mode>3_alc" |
4285 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
4286 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") | |
4287 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4288 | (match_operand:GPR 3 "s390_alc_comparison" ""))) | |
ae156f85 | 4289 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 4290 | "TARGET_CPU_ZARCH" |
e69166de | 4291 | "@ |
9a91a21f AS |
4292 | alc<g>r\t%0,%2 |
4293 | alc<g>\t%0,%2" | |
e69166de UW |
4294 | [(set_attr "op_type" "RRE,RXY")]) |
4295 | ||
43a09b63 | 4296 | ; slbr, slb, slbgr, slbg |
9a91a21f | 4297 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 4298 | [(set (reg CC_REGNUM) |
e69166de | 4299 | (compare |
9a91a21f AS |
4300 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
4301 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4302 | (match_operand:GPR 3 "s390_slb_comparison" "")) | |
e69166de | 4303 | (const_int 0))) |
9a91a21f AS |
4304 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
4305 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4306 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4307 | "@ |
9a91a21f AS |
4308 | slb<g>r\t%0,%2 |
4309 | slb<g>\t%0,%2" | |
e69166de UW |
4310 | [(set_attr "op_type" "RRE,RXY")]) |
4311 | ||
43a09b63 | 4312 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
4313 | (define_insn "*sub<mode>3_slb" |
4314 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
4315 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
4316 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4317 | (match_operand:GPR 3 "s390_slb_comparison" ""))) | |
ae156f85 | 4318 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 4319 | "TARGET_CPU_ZARCH" |
e69166de | 4320 | "@ |
9a91a21f AS |
4321 | slb<g>r\t%0,%2 |
4322 | slb<g>\t%0,%2" | |
e69166de UW |
4323 | [(set_attr "op_type" "RRE,RXY")]) |
4324 | ||
9a91a21f AS |
4325 | (define_expand "add<mode>cc" |
4326 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 4327 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
4328 | (match_operand:GPR 2 "register_operand" "") |
4329 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 UW |
4330 | "TARGET_CPU_ZARCH" |
4331 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4332 | s390_compare_op0, s390_compare_op1, | |
4333 | operands[0], operands[2], | |
4334 | operands[3])) FAIL; DONE;") | |
4335 | ||
4336 | ; | |
4337 | ; scond instruction pattern(s). | |
4338 | ; | |
4339 | ||
9a91a21f AS |
4340 | (define_insn_and_split "*scond<mode>" |
4341 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
4342 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 4343 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
4344 | "TARGET_CPU_ZARCH" |
4345 | "#" | |
4346 | "&& reload_completed" | |
4347 | [(set (match_dup 0) (const_int 0)) | |
4348 | (parallel | |
9a91a21f | 4349 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0)) |
5d880bd2 | 4350 | (match_dup 1))) |
ae156f85 | 4351 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4352 | "") |
5d880bd2 | 4353 | |
9a91a21f AS |
4354 | (define_insn_and_split "*scond<mode>_neg" |
4355 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
4356 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 4357 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
4358 | "TARGET_CPU_ZARCH" |
4359 | "#" | |
4360 | "&& reload_completed" | |
4361 | [(set (match_dup 0) (const_int 0)) | |
4362 | (parallel | |
9a91a21f AS |
4363 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
4364 | (match_dup 1))) | |
ae156f85 | 4365 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 4366 | (parallel |
9a91a21f | 4367 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 4368 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4369 | "") |
5d880bd2 | 4370 | |
5d880bd2 | 4371 | |
9a91a21f AS |
4372 | (define_expand "s<code>" |
4373 | [(set (match_operand:SI 0 "register_operand" "") | |
4374 | (SCOND (match_dup 0) | |
4375 | (match_dup 0)))] | |
5d880bd2 | 4376 | "TARGET_CPU_ZARCH" |
9a91a21f | 4377 | "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1, |
5d880bd2 UW |
4378 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
4379 | ||
69950452 AS |
4380 | (define_expand "seq" |
4381 | [(parallel | |
4382 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4383 | (match_dup 1)) | |
4384 | (clobber (reg:CC CC_REGNUM))]) | |
4385 | (parallel | |
4386 | [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) | |
4387 | (clobber (reg:CC CC_REGNUM))])] | |
4388 | "" | |
4389 | { | |
4390 | if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) | |
4391 | FAIL; | |
4392 | operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); | |
4393 | PUT_MODE (operands[1], SImode); | |
4394 | }) | |
4395 | ||
4396 | (define_insn_and_split "*sne" | |
4397 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4398 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") | |
4399 | (const_int 0))) | |
4400 | (clobber (reg:CC CC_REGNUM))] | |
4401 | "" | |
4402 | "#" | |
4403 | "reload_completed" | |
4404 | [(parallel | |
4405 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
4406 | (clobber (reg:CC CC_REGNUM))])]) | |
4407 | ||
e69166de | 4408 | |
9db1d521 HP |
4409 | ;; |
4410 | ;;- Multiply instructions. | |
4411 | ;; | |
4412 | ||
4023fb28 UW |
4413 | ; |
4414 | ; muldi3 instruction pattern(s). | |
4415 | ; | |
9db1d521 | 4416 | |
07893d4f UW |
4417 | (define_insn "*muldi3_sign" |
4418 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4419 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4420 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4421 | "TARGET_64BIT" | |
4422 | "@ | |
d40c829f UW |
4423 | msgfr\t%0,%2 |
4424 | msgf\t%0,%2" | |
d3632d41 | 4425 | [(set_attr "op_type" "RRE,RXY") |
ed0e512a | 4426 | (set_attr "type" "imuldi")]) |
07893d4f | 4427 | |
4023fb28 | 4428 | (define_insn "muldi3" |
9db1d521 | 4429 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4430 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4431 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4432 | "TARGET_64BIT" |
4433 | "@ | |
d40c829f UW |
4434 | msgr\t%0,%2 |
4435 | mghi\t%0,%h2 | |
4436 | msg\t%0,%2" | |
d3632d41 | 4437 | [(set_attr "op_type" "RRE,RI,RXY") |
ed0e512a | 4438 | (set_attr "type" "imuldi")]) |
f2d3c02a | 4439 | |
9db1d521 HP |
4440 | ; |
4441 | ; mulsi3 instruction pattern(s). | |
4442 | ; | |
4443 | ||
f1e77d83 UW |
4444 | (define_insn "*mulsi3_sign" |
4445 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4446 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4447 | (match_operand:SI 1 "register_operand" "0")))] | |
4448 | "" | |
4449 | "mh\t%0,%2" | |
4450 | [(set_attr "op_type" "RX") | |
ed0e512a | 4451 | (set_attr "type" "imulhi")]) |
f1e77d83 | 4452 | |
9db1d521 | 4453 | (define_insn "mulsi3" |
d3632d41 UW |
4454 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4455 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4456 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4457 | "" |
4458 | "@ | |
d40c829f UW |
4459 | msr\t%0,%2 |
4460 | mhi\t%0,%h2 | |
4461 | ms\t%0,%2 | |
4462 | msy\t%0,%2" | |
d3632d41 | 4463 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
ed0e512a | 4464 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi")]) |
9db1d521 | 4465 | |
4023fb28 UW |
4466 | ; |
4467 | ; mulsidi3 instruction pattern(s). | |
4468 | ; | |
4469 | ||
f1e77d83 UW |
4470 | (define_insn "mulsidi3" |
4471 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4472 | (mult:DI (sign_extend:DI | |
4473 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4474 | (sign_extend:DI | |
4475 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4476 | "!TARGET_64BIT" |
f1e77d83 UW |
4477 | "@ |
4478 | mr\t%0,%2 | |
4479 | m\t%0,%2" | |
4480 | [(set_attr "op_type" "RR,RX") | |
ed0e512a | 4481 | (set_attr "type" "imulsi")]) |
4023fb28 | 4482 | |
f1e77d83 UW |
4483 | ; |
4484 | ; umulsidi3 instruction pattern(s). | |
4485 | ; | |
c7453384 | 4486 | |
f1e77d83 UW |
4487 | (define_insn "umulsidi3" |
4488 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4489 | (mult:DI (zero_extend:DI | |
4490 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4491 | (zero_extend:DI | |
4492 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4493 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4494 | "@ | |
4495 | mlr\t%0,%2 | |
4496 | ml\t%0,%2" | |
4497 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 4498 | (set_attr "type" "imulsi")]) |
c7453384 | 4499 | |
9db1d521 | 4500 | ; |
f5905b37 | 4501 | ; mul(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4502 | ; |
4503 | ||
f5905b37 AS |
4504 | (define_expand "mul<mode>3" |
4505 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4506 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
f61a2c7d | 4507 | (match_operand:FPR 2 "general_operand" "f,<Rf>")))] |
9db1d521 HP |
4508 | "TARGET_HARD_FLOAT" |
4509 | "") | |
4510 | ||
43a09b63 | 4511 | ; mxbr mdbr, meebr, mxb, mxb, meeb |
f5905b37 AS |
4512 | (define_insn "*mul<mode>3" |
4513 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4514 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
f61a2c7d | 4515 | (match_operand:FPR 2 "general_operand" "f,<Rf>")))] |
9db1d521 HP |
4516 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4517 | "@ | |
f61a2c7d AK |
4518 | m<xdee>br\t%0,%2 |
4519 | m<xdee>b\t%0,%2" | |
ce50cae8 | 4520 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4521 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 4522 | |
43a09b63 | 4523 | ; mxr, mdr, mer, mx, md, me |
f5905b37 AS |
4524 | (define_insn "*mul<mode>3_ibm" |
4525 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4526 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
f61a2c7d | 4527 | (match_operand:FPR 2 "general_operand" "f,<Rf>")))] |
9db1d521 HP |
4528 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4529 | "@ | |
f61a2c7d AK |
4530 | m<xde>r\t%0,%2 |
4531 | m<xde>\t%0,%2" | |
4532 | [(set_attr "op_type" "<RRe>,<RXe>") | |
f5905b37 | 4533 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 4534 | |
43a09b63 | 4535 | ; maxbr, madbr, maebr, maxb, madb, maeb |
f5905b37 | 4536 | (define_insn "*fmadd<mode>" |
f61a2c7d AK |
4537 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
4538 | (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f") | |
4539 | (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
4540 | (match_operand:DSF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4541 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 4542 | "@ |
f61a2c7d AK |
4543 | ma<xde>br\t%0,%1,%2 |
4544 | ma<xde>b\t%0,%1,%2" | |
a1b892b5 | 4545 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4546 | (set_attr "type" "fmul<mode>")]) |
a1b892b5 | 4547 | |
43a09b63 | 4548 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
f5905b37 | 4549 | (define_insn "*fmsub<mode>" |
f61a2c7d AK |
4550 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
4551 | (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f") | |
4552 | (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
4553 | (match_operand:DSF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4554 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 4555 | "@ |
f61a2c7d AK |
4556 | ms<xde>br\t%0,%1,%2 |
4557 | ms<xde>b\t%0,%1,%2" | |
ce50cae8 | 4558 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4559 | (set_attr "type" "fmul<mode>")]) |
9db1d521 HP |
4560 | |
4561 | ;; | |
4562 | ;;- Divide and modulo instructions. | |
4563 | ;; | |
4564 | ||
4565 | ; | |
4023fb28 | 4566 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4567 | ; |
4568 | ||
4023fb28 UW |
4569 | (define_expand "divmoddi4" |
4570 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4571 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4572 | (match_operand:DI 2 "general_operand" ""))) |
4573 | (set (match_operand:DI 3 "general_operand" "") | |
4574 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4575 | (clobber (match_dup 4))] | |
9db1d521 | 4576 | "TARGET_64BIT" |
9db1d521 | 4577 | { |
f1e77d83 | 4578 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4579 | |
4580 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4581 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4582 | |
4583 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4584 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4585 | |
4586 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4587 | REG_NOTES (insn) = | |
4588 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4589 | ||
4590 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4591 | REG_NOTES (insn) = | |
4592 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4593 | |
9db1d521 | 4594 | DONE; |
10bbf137 | 4595 | }) |
9db1d521 HP |
4596 | |
4597 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4598 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4599 | (ior:TI | |
4023fb28 UW |
4600 | (ashift:TI |
4601 | (zero_extend:TI | |
5665e398 UW |
4602 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4603 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4604 | (const_int 64)) | |
4605 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4606 | "TARGET_64BIT" |
4607 | "@ | |
d40c829f UW |
4608 | dsgr\t%0,%2 |
4609 | dsg\t%0,%2" | |
d3632d41 | 4610 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4611 | (set_attr "type" "idiv")]) |
9db1d521 | 4612 | |
4023fb28 UW |
4613 | (define_insn "divmodtisi3" |
4614 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4615 | (ior:TI | |
4023fb28 UW |
4616 | (ashift:TI |
4617 | (zero_extend:TI | |
5665e398 | 4618 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 4619 | (sign_extend:DI |
5665e398 UW |
4620 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4621 | (const_int 64)) | |
4622 | (zero_extend:TI | |
4623 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4624 | "TARGET_64BIT" |
4023fb28 | 4625 | "@ |
d40c829f UW |
4626 | dsgfr\t%0,%2 |
4627 | dsgf\t%0,%2" | |
d3632d41 | 4628 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4629 | (set_attr "type" "idiv")]) |
9db1d521 | 4630 | |
4023fb28 UW |
4631 | ; |
4632 | ; udivmoddi4 instruction pattern(s). | |
4633 | ; | |
9db1d521 | 4634 | |
4023fb28 UW |
4635 | (define_expand "udivmoddi4" |
4636 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4637 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4638 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4639 | (set (match_operand:DI 3 "general_operand" "") | |
4640 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4641 | (clobber (match_dup 4))] | |
9db1d521 | 4642 | "TARGET_64BIT" |
9db1d521 | 4643 | { |
4023fb28 UW |
4644 | rtx insn, div_equal, mod_equal, equal; |
4645 | ||
4646 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4647 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4648 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4649 | gen_rtx_ASHIFT (TImode, |
4650 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4651 | GEN_INT (64)), |
4652 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4653 | |
4654 | operands[4] = gen_reg_rtx(TImode); | |
4655 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4656 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4657 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4658 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4659 | REG_NOTES (insn) = | |
4660 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4661 | ||
4662 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4663 | REG_NOTES (insn) = | |
4664 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4665 | ||
4666 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4667 | REG_NOTES (insn) = | |
4668 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4669 | |
9db1d521 | 4670 | DONE; |
10bbf137 | 4671 | }) |
9db1d521 HP |
4672 | |
4673 | (define_insn "udivmodtidi3" | |
4023fb28 | 4674 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 4675 | (ior:TI |
5665e398 UW |
4676 | (ashift:TI |
4677 | (zero_extend:TI | |
4678 | (truncate:DI | |
2f7e5a0d EC |
4679 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
4680 | (zero_extend:TI | |
5665e398 UW |
4681 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
4682 | (const_int 64)) | |
4683 | (zero_extend:TI | |
4684 | (truncate:DI | |
4685 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4686 | "TARGET_64BIT" |
4687 | "@ | |
d40c829f UW |
4688 | dlgr\t%0,%2 |
4689 | dlg\t%0,%2" | |
d3632d41 | 4690 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4691 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4692 | |
4693 | ; | |
4023fb28 | 4694 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4695 | ; |
4696 | ||
4023fb28 UW |
4697 | (define_expand "divmodsi4" |
4698 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4699 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4700 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4701 | (set (match_operand:SI 3 "general_operand" "") | |
4702 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4703 | (clobber (match_dup 4))] | |
9db1d521 | 4704 | "!TARGET_64BIT" |
9db1d521 | 4705 | { |
4023fb28 UW |
4706 | rtx insn, div_equal, mod_equal, equal; |
4707 | ||
4708 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4709 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4710 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4711 | gen_rtx_ASHIFT (DImode, |
4712 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4713 | GEN_INT (32)), |
4714 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4715 | |
4716 | operands[4] = gen_reg_rtx(DImode); | |
4717 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4718 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4719 | REG_NOTES (insn) = | |
4720 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4721 | ||
4722 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4723 | REG_NOTES (insn) = | |
4724 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4725 | ||
4726 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4727 | REG_NOTES (insn) = | |
4728 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4729 | |
9db1d521 | 4730 | DONE; |
10bbf137 | 4731 | }) |
9db1d521 HP |
4732 | |
4733 | (define_insn "divmoddisi3" | |
4023fb28 | 4734 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 4735 | (ior:DI |
5665e398 UW |
4736 | (ashift:DI |
4737 | (zero_extend:DI | |
4738 | (truncate:SI | |
2f7e5a0d EC |
4739 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4740 | (sign_extend:DI | |
5665e398 UW |
4741 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4742 | (const_int 32)) | |
4743 | (zero_extend:DI | |
4744 | (truncate:SI | |
4745 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4746 | "!TARGET_64BIT" |
4747 | "@ | |
d40c829f UW |
4748 | dr\t%0,%2 |
4749 | d\t%0,%2" | |
9db1d521 | 4750 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4751 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4752 | |
4753 | ; | |
4754 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4755 | ; | |
4756 | ||
f1e77d83 UW |
4757 | (define_expand "udivmodsi4" |
4758 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4759 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4760 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4761 | (set (match_operand:SI 3 "general_operand" "") | |
4762 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4763 | (clobber (match_dup 4))] | |
4764 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4765 | { | |
4766 | rtx insn, div_equal, mod_equal, equal; | |
4767 | ||
4768 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4769 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4770 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4771 | gen_rtx_ASHIFT (DImode, |
4772 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4773 | GEN_INT (32)), |
4774 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4775 | |
4776 | operands[4] = gen_reg_rtx(DImode); | |
4777 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4778 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4779 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4780 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4781 | REG_NOTES (insn) = | |
4782 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4783 | ||
4784 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4785 | REG_NOTES (insn) = | |
4786 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4787 | ||
4788 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4789 | REG_NOTES (insn) = | |
4790 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4791 | ||
4792 | DONE; | |
4793 | }) | |
4794 | ||
4795 | (define_insn "udivmoddisi3" | |
4796 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 4797 | (ior:DI |
5665e398 UW |
4798 | (ashift:DI |
4799 | (zero_extend:DI | |
4800 | (truncate:SI | |
2f7e5a0d EC |
4801 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
4802 | (zero_extend:DI | |
5665e398 UW |
4803 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
4804 | (const_int 32)) | |
4805 | (zero_extend:DI | |
4806 | (truncate:SI | |
4807 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4808 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4809 | "@ | |
4810 | dlr\t%0,%2 | |
4811 | dl\t%0,%2" | |
4812 | [(set_attr "op_type" "RRE,RXY") | |
4813 | (set_attr "type" "idiv")]) | |
4023fb28 | 4814 | |
9db1d521 HP |
4815 | (define_expand "udivsi3" |
4816 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4817 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4818 | (match_operand:SI 2 "general_operand" ""))) |
4819 | (clobber (match_dup 3))] | |
f1e77d83 | 4820 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4821 | { |
4023fb28 UW |
4822 | rtx insn, udiv_equal, umod_equal, equal; |
4823 | ||
4824 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4825 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4826 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4827 | gen_rtx_ASHIFT (DImode, |
4828 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4829 | GEN_INT (32)), |
4830 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4831 | |
4023fb28 | 4832 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4833 | |
4834 | if (CONSTANT_P (operands[2])) | |
4835 | { | |
4836 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4837 | { | |
4838 | rtx label1 = gen_label_rtx (); | |
4839 | ||
4023fb28 UW |
4840 | operands[1] = make_safe_from (operands[1], operands[0]); |
4841 | emit_move_insn (operands[0], const0_rtx); | |
4842 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4843 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4844 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4845 | emit_label (label1); |
4846 | } | |
4847 | else | |
4848 | { | |
c7453384 EC |
4849 | operands[2] = force_reg (SImode, operands[2]); |
4850 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4851 | |
4852 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4853 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4854 | operands[2])); | |
4855 | REG_NOTES (insn) = | |
4856 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4857 | |
4858 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4859 | gen_lowpart (SImode, operands[3])); |
4860 | REG_NOTES (insn) = | |
c7453384 | 4861 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4862 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4863 | } |
4864 | } | |
4865 | else | |
c7453384 | 4866 | { |
9db1d521 HP |
4867 | rtx label1 = gen_label_rtx (); |
4868 | rtx label2 = gen_label_rtx (); | |
4869 | rtx label3 = gen_label_rtx (); | |
4870 | ||
c7453384 EC |
4871 | operands[1] = force_reg (SImode, operands[1]); |
4872 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4873 | operands[2] = force_reg (SImode, operands[2]); | |
4874 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4875 | |
4876 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4877 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4878 | emit_jump_insn (gen_bgtu (label3)); | |
220a826e | 4879 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4880 | emit_jump_insn (gen_blt (label2)); |
4881 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4882 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4883 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4884 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4885 | operands[2])); | |
4886 | REG_NOTES (insn) = | |
4887 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4888 | |
4889 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4890 | gen_lowpart (SImode, operands[3])); |
4891 | REG_NOTES (insn) = | |
c7453384 | 4892 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4893 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4894 | emit_jump (label3); |
9db1d521 | 4895 | emit_label (label1); |
4023fb28 | 4896 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4897 | emit_jump (label3); |
9db1d521 | 4898 | emit_label (label2); |
4023fb28 | 4899 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4900 | emit_label (label3); |
4901 | } | |
c7453384 | 4902 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4903 | DONE; |
10bbf137 | 4904 | }) |
9db1d521 HP |
4905 | |
4906 | (define_expand "umodsi3" | |
4907 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4908 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4909 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4910 | (clobber (match_dup 3))] | |
f1e77d83 | 4911 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4912 | { |
4023fb28 UW |
4913 | rtx insn, udiv_equal, umod_equal, equal; |
4914 | ||
4915 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4916 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4917 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4918 | gen_rtx_ASHIFT (DImode, |
4919 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4920 | GEN_INT (32)), |
4921 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4922 | |
4023fb28 | 4923 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4924 | |
4925 | if (CONSTANT_P (operands[2])) | |
4926 | { | |
4927 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4928 | { | |
4929 | rtx label1 = gen_label_rtx (); | |
4930 | ||
4023fb28 UW |
4931 | operands[1] = make_safe_from (operands[1], operands[0]); |
4932 | emit_move_insn (operands[0], operands[1]); | |
4933 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 4934 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
4935 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4936 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
4937 | emit_label (label1); |
4938 | } | |
4939 | else | |
4940 | { | |
c7453384 EC |
4941 | operands[2] = force_reg (SImode, operands[2]); |
4942 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4943 | |
4944 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4945 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4946 | operands[2])); | |
4947 | REG_NOTES (insn) = | |
4948 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4949 | |
4950 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4951 | gen_highpart (SImode, operands[3])); |
4952 | REG_NOTES (insn) = | |
c7453384 | 4953 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4954 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
4955 | } |
4956 | } | |
4957 | else | |
4958 | { | |
4959 | rtx label1 = gen_label_rtx (); | |
4960 | rtx label2 = gen_label_rtx (); | |
4961 | rtx label3 = gen_label_rtx (); | |
4962 | ||
c7453384 EC |
4963 | operands[1] = force_reg (SImode, operands[1]); |
4964 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4965 | operands[2] = force_reg (SImode, operands[2]); | |
4966 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 4967 | |
c7453384 | 4968 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 4969 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 | 4970 | emit_jump_insn (gen_bgtu (label3)); |
220a826e | 4971 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4972 | emit_jump_insn (gen_blt (label2)); |
4973 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4974 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4975 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4976 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4977 | operands[2])); | |
4978 | REG_NOTES (insn) = | |
4979 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4980 | |
4981 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4982 | gen_highpart (SImode, operands[3])); |
4983 | REG_NOTES (insn) = | |
c7453384 | 4984 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4985 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 4986 | emit_jump (label3); |
9db1d521 | 4987 | emit_label (label1); |
4023fb28 | 4988 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 4989 | emit_jump (label3); |
9db1d521 | 4990 | emit_label (label2); |
4023fb28 | 4991 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
4992 | emit_label (label3); |
4993 | } | |
9db1d521 | 4994 | DONE; |
10bbf137 | 4995 | }) |
9db1d521 HP |
4996 | |
4997 | ; | |
f5905b37 | 4998 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4999 | ; |
5000 | ||
f5905b37 AS |
5001 | (define_expand "div<mode>3" |
5002 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
5003 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
f61a2c7d | 5004 | (match_operand:FPR 2 "general_operand" "f,<Rf>")))] |
9db1d521 HP |
5005 | "TARGET_HARD_FLOAT" |
5006 | "") | |
5007 | ||
43a09b63 | 5008 | ; dxbr, ddbr, debr, dxb, ddb, deb |
f5905b37 AS |
5009 | (define_insn "*div<mode>3" |
5010 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
5011 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
f61a2c7d | 5012 | (match_operand:FPR 2 "general_operand" "f,<Rf>")))] |
9db1d521 HP |
5013 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5014 | "@ | |
f61a2c7d AK |
5015 | d<xde>br\t%0,%2 |
5016 | d<xde>b\t%0,%2" | |
ce50cae8 | 5017 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 5018 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 5019 | |
43a09b63 | 5020 | ; dxr, ddr, der, dx, dd, de |
f5905b37 AS |
5021 | (define_insn "*div<mode>3_ibm" |
5022 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
5023 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
f61a2c7d | 5024 | (match_operand:FPR 2 "general_operand" "f,<Rf>")))] |
9db1d521 HP |
5025 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5026 | "@ | |
f61a2c7d AK |
5027 | d<xde>r\t%0,%2 |
5028 | d<xde>\t%0,%2" | |
5029 | [(set_attr "op_type" "<RRe>,<RXe>") | |
f5905b37 | 5030 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 HP |
5031 | |
5032 | ||
5033 | ;; | |
5034 | ;;- And instructions. | |
5035 | ;; | |
5036 | ||
047d35ed AS |
5037 | (define_expand "and<mode>3" |
5038 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5039 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5040 | (match_operand:INT 2 "general_operand" ""))) | |
5041 | (clobber (reg:CC CC_REGNUM))] | |
5042 | "" | |
5043 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
5044 | ||
9db1d521 HP |
5045 | ; |
5046 | ; anddi3 instruction pattern(s). | |
5047 | ; | |
5048 | ||
5049 | (define_insn "*anddi3_cc" | |
ae156f85 | 5050 | [(set (reg CC_REGNUM) |
96fd3851 | 5051 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5052 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 5053 | (const_int 0))) |
4023fb28 | 5054 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
5055 | (and:DI (match_dup 1) (match_dup 2)))] |
5056 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5057 | "@ | |
d40c829f UW |
5058 | ngr\t%0,%2 |
5059 | ng\t%0,%2" | |
d3632d41 | 5060 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
5061 | |
5062 | (define_insn "*anddi3_cconly" | |
ae156f85 | 5063 | [(set (reg CC_REGNUM) |
96fd3851 | 5064 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5065 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
5066 | (const_int 0))) |
5067 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
5068 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
5069 | /* Do not steal TM patterns. */ | |
5070 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 5071 | "@ |
d40c829f UW |
5072 | ngr\t%0,%2 |
5073 | ng\t%0,%2" | |
d3632d41 | 5074 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 5075 | |
ec24698e UW |
5076 | (define_insn "*anddi3_extimm" |
5077 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") | |
5078 | (and:DI (match_operand:DI 1 "nonimmediate_operand" | |
5079 | "%d,o,0,0,0,0,0,0,0,0,0,0") | |
5080 | (match_operand:DI 2 "general_operand" | |
5081 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q"))) | |
5082 | (clobber (reg:CC CC_REGNUM))] | |
5083 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
5084 | "@ | |
5085 | # | |
5086 | # | |
5087 | nihh\t%0,%j2 | |
5088 | nihl\t%0,%j2 | |
5089 | nilh\t%0,%j2 | |
5090 | nill\t%0,%j2 | |
5091 | nihf\t%0,%m2 | |
5092 | nilf\t%0,%m2 | |
5093 | ngr\t%0,%2 | |
5094 | ng\t%0,%2 | |
5095 | # | |
5096 | #" | |
5097 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")]) | |
5098 | ||
8cb66696 | 5099 | (define_insn "*anddi3" |
0dfa6c5e | 5100 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
8cb66696 | 5101 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
0dfa6c5e | 5102 | "%d,o,0,0,0,0,0,0,0,0") |
8cb66696 | 5103 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5104 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) |
ae156f85 | 5105 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 5106 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
8cb66696 UW |
5107 | "@ |
5108 | # | |
5109 | # | |
5110 | nihh\t%0,%j2 | |
5111 | nihl\t%0,%j2 | |
5112 | nilh\t%0,%j2 | |
5113 | nill\t%0,%j2 | |
5114 | ngr\t%0,%2 | |
5115 | ng\t%0,%2 | |
0dfa6c5e | 5116 | # |
19b63d8e | 5117 | #" |
0dfa6c5e UW |
5118 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5119 | ||
5120 | (define_split | |
5121 | [(set (match_operand:DI 0 "s_operand" "") | |
5122 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5123 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5124 | "reload_completed" |
5125 | [(parallel | |
5126 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5127 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5128 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5129 | |
9db1d521 HP |
5130 | |
5131 | ; | |
5132 | ; andsi3 instruction pattern(s). | |
5133 | ; | |
5134 | ||
5135 | (define_insn "*andsi3_cc" | |
ae156f85 | 5136 | [(set (reg CC_REGNUM) |
ec24698e UW |
5137 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5138 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5139 | (const_int 0))) |
ec24698e | 5140 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
9db1d521 HP |
5141 | (and:SI (match_dup 1) (match_dup 2)))] |
5142 | "s390_match_ccmode(insn, CCTmode)" | |
5143 | "@ | |
ec24698e | 5144 | nilf\t%0,%o2 |
d40c829f UW |
5145 | nr\t%0,%2 |
5146 | n\t%0,%2 | |
5147 | ny\t%0,%2" | |
ec24698e | 5148 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 HP |
5149 | |
5150 | (define_insn "*andsi3_cconly" | |
ae156f85 | 5151 | [(set (reg CC_REGNUM) |
ec24698e UW |
5152 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5153 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5154 | (const_int 0))) |
ec24698e | 5155 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
68f9c5e2 UW |
5156 | "s390_match_ccmode(insn, CCTmode) |
5157 | /* Do not steal TM patterns. */ | |
5158 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 5159 | "@ |
ec24698e | 5160 | nilf\t%0,%o2 |
d40c829f UW |
5161 | nr\t%0,%2 |
5162 | n\t%0,%2 | |
5163 | ny\t%0,%2" | |
ec24698e | 5164 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 | 5165 | |
f19a9af7 | 5166 | (define_insn "*andsi3_zarch" |
ec24698e | 5167 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
0dfa6c5e | 5168 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
ec24698e | 5169 | "%d,o,0,0,0,0,0,0,0,0") |
0dfa6c5e | 5170 | (match_operand:SI 2 "general_operand" |
ec24698e | 5171 | "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q"))) |
ae156f85 | 5172 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5173 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5174 | "@ |
f19a9af7 AK |
5175 | # |
5176 | # | |
5177 | nilh\t%0,%j2 | |
2f7e5a0d | 5178 | nill\t%0,%j2 |
ec24698e | 5179 | nilf\t%0,%o2 |
d40c829f UW |
5180 | nr\t%0,%2 |
5181 | n\t%0,%2 | |
8cb66696 | 5182 | ny\t%0,%2 |
0dfa6c5e | 5183 | # |
19b63d8e | 5184 | #" |
ec24698e | 5185 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")]) |
f19a9af7 AK |
5186 | |
5187 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
5188 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5189 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5190 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
ae156f85 | 5191 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5192 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5193 | "@ |
5194 | nr\t%0,%2 | |
8cb66696 | 5195 | n\t%0,%2 |
0dfa6c5e | 5196 | # |
19b63d8e | 5197 | #" |
0dfa6c5e UW |
5198 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5199 | ||
5200 | (define_split | |
5201 | [(set (match_operand:SI 0 "s_operand" "") | |
5202 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5203 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5204 | "reload_completed" |
5205 | [(parallel | |
5206 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5207 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5208 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5209 | |
9db1d521 HP |
5210 | ; |
5211 | ; andhi3 instruction pattern(s). | |
5212 | ; | |
5213 | ||
8cb66696 | 5214 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
5215 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5216 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5217 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
ae156f85 | 5218 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5219 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5220 | "@ |
d40c829f | 5221 | nr\t%0,%2 |
8cb66696 | 5222 | nill\t%0,%x2 |
0dfa6c5e | 5223 | # |
19b63d8e | 5224 | #" |
0dfa6c5e | 5225 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5226 | |
5227 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
5228 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5229 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5230 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 5231 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5232 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5233 | "@ | |
5234 | nr\t%0,%2 | |
0dfa6c5e | 5235 | # |
19b63d8e | 5236 | #" |
0dfa6c5e UW |
5237 | [(set_attr "op_type" "RR,SI,SS")]) |
5238 | ||
5239 | (define_split | |
5240 | [(set (match_operand:HI 0 "s_operand" "") | |
5241 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5242 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5243 | "reload_completed" |
5244 | [(parallel | |
5245 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5246 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5247 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 5248 | |
9db1d521 HP |
5249 | ; |
5250 | ; andqi3 instruction pattern(s). | |
5251 | ; | |
5252 | ||
8cb66696 UW |
5253 | (define_insn "*andqi3_zarch" |
5254 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5255 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5256 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5257 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5258 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5259 | "@ |
d40c829f | 5260 | nr\t%0,%2 |
8cb66696 | 5261 | nill\t%0,%b2 |
fc0ea003 UW |
5262 | ni\t%S0,%b2 |
5263 | niy\t%S0,%b2 | |
19b63d8e | 5264 | #" |
8cb66696 UW |
5265 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5266 | ||
5267 | (define_insn "*andqi3_esa" | |
5268 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5269 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5270 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5271 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5272 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5273 | "@ |
8cb66696 | 5274 | nr\t%0,%2 |
fc0ea003 | 5275 | ni\t%S0,%b2 |
19b63d8e | 5276 | #" |
8cb66696 | 5277 | [(set_attr "op_type" "RR,SI,SS")]) |
4023fb28 | 5278 | |
19b63d8e UW |
5279 | ; |
5280 | ; Block and (NC) patterns. | |
5281 | ; | |
5282 | ||
5283 | (define_insn "*nc" | |
5284 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5285 | (and:BLK (match_dup 0) | |
5286 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5287 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5288 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5289 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5290 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 5291 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5292 | |
5293 | (define_split | |
5294 | [(set (match_operand 0 "memory_operand" "") | |
5295 | (and (match_dup 0) | |
5296 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5297 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5298 | "reload_completed |
5299 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5300 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5301 | [(parallel | |
5302 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
5303 | (use (match_dup 2)) | |
ae156f85 | 5304 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5305 | { |
5306 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5307 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5308 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5309 | }) | |
5310 | ||
5311 | (define_peephole2 | |
5312 | [(parallel | |
5313 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5314 | (and:BLK (match_dup 0) | |
5315 | (match_operand:BLK 1 "memory_operand" ""))) | |
5316 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5317 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5318 | (parallel |
5319 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5320 | (and:BLK (match_dup 3) | |
5321 | (match_operand:BLK 4 "memory_operand" ""))) | |
5322 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5323 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5324 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5325 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5326 | && !s390_overlap_p (operands[0], operands[1], |
5327 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5328 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5329 | [(parallel | |
5330 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
5331 | (use (match_dup 8)) | |
ae156f85 | 5332 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5333 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5334 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5335 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5336 | ||
9db1d521 HP |
5337 | |
5338 | ;; | |
5339 | ;;- Bit set (inclusive or) instructions. | |
5340 | ;; | |
5341 | ||
047d35ed AS |
5342 | (define_expand "ior<mode>3" |
5343 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5344 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5345 | (match_operand:INT 2 "general_operand" ""))) | |
5346 | (clobber (reg:CC CC_REGNUM))] | |
5347 | "" | |
5348 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
5349 | ||
9db1d521 HP |
5350 | ; |
5351 | ; iordi3 instruction pattern(s). | |
5352 | ; | |
5353 | ||
4023fb28 | 5354 | (define_insn "*iordi3_cc" |
ae156f85 | 5355 | [(set (reg CC_REGNUM) |
96fd3851 | 5356 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5357 | (match_operand:DI 2 "general_operand" "d,m")) |
5358 | (const_int 0))) | |
5359 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5360 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5361 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5362 | "@ | |
d40c829f UW |
5363 | ogr\t%0,%2 |
5364 | og\t%0,%2" | |
d3632d41 | 5365 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5366 | |
5367 | (define_insn "*iordi3_cconly" | |
ae156f85 | 5368 | [(set (reg CC_REGNUM) |
96fd3851 | 5369 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5370 | (match_operand:DI 2 "general_operand" "d,m")) |
5371 | (const_int 0))) | |
5372 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5373 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5374 | "@ | |
d40c829f UW |
5375 | ogr\t%0,%2 |
5376 | og\t%0,%2" | |
d3632d41 | 5377 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5378 | |
ec24698e UW |
5379 | (define_insn "*iordi3_extimm" |
5380 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") | |
5381 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") | |
5382 | (match_operand:DI 2 "general_operand" | |
5383 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q"))) | |
5384 | (clobber (reg:CC CC_REGNUM))] | |
5385 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
5386 | "@ | |
5387 | oihh\t%0,%i2 | |
5388 | oihl\t%0,%i2 | |
5389 | oilh\t%0,%i2 | |
5390 | oill\t%0,%i2 | |
5391 | oihf\t%0,%k2 | |
5392 | oilf\t%0,%k2 | |
5393 | ogr\t%0,%2 | |
5394 | og\t%0,%2 | |
5395 | # | |
5396 | #" | |
5397 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")]) | |
5398 | ||
8cb66696 | 5399 | (define_insn "*iordi3" |
0dfa6c5e | 5400 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
bad82153 | 5401 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") |
8cb66696 | 5402 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5403 | "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) |
ae156f85 | 5404 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 5405 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5406 | "@ |
f19a9af7 AK |
5407 | oihh\t%0,%i2 |
5408 | oihl\t%0,%i2 | |
5409 | oilh\t%0,%i2 | |
5410 | oill\t%0,%i2 | |
d40c829f | 5411 | ogr\t%0,%2 |
8cb66696 | 5412 | og\t%0,%2 |
0dfa6c5e | 5413 | # |
19b63d8e | 5414 | #" |
0dfa6c5e UW |
5415 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5416 | ||
5417 | (define_split | |
5418 | [(set (match_operand:DI 0 "s_operand" "") | |
5419 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5420 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5421 | "reload_completed" |
5422 | [(parallel | |
5423 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5424 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5425 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 5426 | |
9db1d521 HP |
5427 | ; |
5428 | ; iorsi3 instruction pattern(s). | |
5429 | ; | |
5430 | ||
4023fb28 | 5431 | (define_insn "*iorsi3_cc" |
ae156f85 | 5432 | [(set (reg CC_REGNUM) |
ec24698e UW |
5433 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5434 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5435 | (const_int 0))) |
ec24698e | 5436 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
5437 | (ior:SI (match_dup 1) (match_dup 2)))] |
5438 | "s390_match_ccmode(insn, CCTmode)" | |
5439 | "@ | |
ec24698e | 5440 | oilf\t%0,%o2 |
d40c829f UW |
5441 | or\t%0,%2 |
5442 | o\t%0,%2 | |
5443 | oy\t%0,%2" | |
ec24698e | 5444 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 UW |
5445 | |
5446 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 5447 | [(set (reg CC_REGNUM) |
ec24698e UW |
5448 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5449 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5450 | (const_int 0))) |
ec24698e | 5451 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
5452 | "s390_match_ccmode(insn, CCTmode)" |
5453 | "@ | |
ec24698e | 5454 | oilf\t%0,%o2 |
d40c829f UW |
5455 | or\t%0,%2 |
5456 | o\t%0,%2 | |
5457 | oy\t%0,%2" | |
ec24698e | 5458 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 | 5459 | |
8cb66696 | 5460 | (define_insn "*iorsi3_zarch" |
ec24698e UW |
5461 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
5462 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") | |
5463 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 5464 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5465 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5466 | "@ |
f19a9af7 AK |
5467 | oilh\t%0,%i2 |
5468 | oill\t%0,%i2 | |
ec24698e | 5469 | oilf\t%0,%o2 |
d40c829f UW |
5470 | or\t%0,%2 |
5471 | o\t%0,%2 | |
8cb66696 | 5472 | oy\t%0,%2 |
0dfa6c5e | 5473 | # |
19b63d8e | 5474 | #" |
ec24698e | 5475 | [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")]) |
8cb66696 UW |
5476 | |
5477 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 5478 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 5479 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 5480 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 5481 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5482 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5483 | "@ |
5484 | or\t%0,%2 | |
8cb66696 | 5485 | o\t%0,%2 |
0dfa6c5e | 5486 | # |
19b63d8e | 5487 | #" |
0dfa6c5e UW |
5488 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5489 | ||
5490 | (define_split | |
5491 | [(set (match_operand:SI 0 "s_operand" "") | |
5492 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5493 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5494 | "reload_completed" |
5495 | [(parallel | |
5496 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5497 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5498 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 5499 | |
4023fb28 UW |
5500 | ; |
5501 | ; iorhi3 instruction pattern(s). | |
5502 | ; | |
5503 | ||
8cb66696 | 5504 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
5505 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5506 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5507 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
ae156f85 | 5508 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5509 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5510 | "@ |
d40c829f | 5511 | or\t%0,%2 |
8cb66696 | 5512 | oill\t%0,%x2 |
0dfa6c5e | 5513 | # |
19b63d8e | 5514 | #" |
0dfa6c5e | 5515 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5516 | |
5517 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
5518 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5519 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5520 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 5521 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5522 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5523 | "@ | |
5524 | or\t%0,%2 | |
0dfa6c5e | 5525 | # |
19b63d8e | 5526 | #" |
0dfa6c5e UW |
5527 | [(set_attr "op_type" "RR,SI,SS")]) |
5528 | ||
5529 | (define_split | |
5530 | [(set (match_operand:HI 0 "s_operand" "") | |
5531 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5532 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5533 | "reload_completed" |
5534 | [(parallel | |
5535 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5536 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5537 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 5538 | |
9db1d521 | 5539 | ; |
4023fb28 | 5540 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5541 | ; |
5542 | ||
8cb66696 UW |
5543 | (define_insn "*iorqi3_zarch" |
5544 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5545 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5546 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5547 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5548 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5549 | "@ |
d40c829f | 5550 | or\t%0,%2 |
8cb66696 | 5551 | oill\t%0,%b2 |
fc0ea003 UW |
5552 | oi\t%S0,%b2 |
5553 | oiy\t%S0,%b2 | |
19b63d8e | 5554 | #" |
8cb66696 UW |
5555 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5556 | ||
5557 | (define_insn "*iorqi3_esa" | |
5558 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5559 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5560 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5561 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5562 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5563 | "@ |
8cb66696 | 5564 | or\t%0,%2 |
fc0ea003 | 5565 | oi\t%S0,%b2 |
19b63d8e | 5566 | #" |
8cb66696 | 5567 | [(set_attr "op_type" "RR,SI,SS")]) |
9db1d521 | 5568 | |
19b63d8e UW |
5569 | ; |
5570 | ; Block inclusive or (OC) patterns. | |
5571 | ; | |
5572 | ||
5573 | (define_insn "*oc" | |
5574 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5575 | (ior:BLK (match_dup 0) | |
5576 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5577 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5578 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5579 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5580 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 5581 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5582 | |
5583 | (define_split | |
5584 | [(set (match_operand 0 "memory_operand" "") | |
5585 | (ior (match_dup 0) | |
5586 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5587 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5588 | "reload_completed |
5589 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5590 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5591 | [(parallel | |
5592 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
5593 | (use (match_dup 2)) | |
ae156f85 | 5594 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5595 | { |
5596 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5597 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5598 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5599 | }) | |
5600 | ||
5601 | (define_peephole2 | |
5602 | [(parallel | |
5603 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5604 | (ior:BLK (match_dup 0) | |
5605 | (match_operand:BLK 1 "memory_operand" ""))) | |
5606 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5607 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5608 | (parallel |
5609 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5610 | (ior:BLK (match_dup 3) | |
5611 | (match_operand:BLK 4 "memory_operand" ""))) | |
5612 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5613 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5614 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5615 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5616 | && !s390_overlap_p (operands[0], operands[1], |
5617 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5618 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5619 | [(parallel | |
5620 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
5621 | (use (match_dup 8)) | |
ae156f85 | 5622 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5623 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5624 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5625 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5626 | ||
9db1d521 HP |
5627 | |
5628 | ;; | |
5629 | ;;- Xor instructions. | |
5630 | ;; | |
5631 | ||
047d35ed AS |
5632 | (define_expand "xor<mode>3" |
5633 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5634 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5635 | (match_operand:INT 2 "general_operand" ""))) | |
5636 | (clobber (reg:CC CC_REGNUM))] | |
5637 | "" | |
5638 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
5639 | ||
9db1d521 HP |
5640 | ; |
5641 | ; xordi3 instruction pattern(s). | |
5642 | ; | |
5643 | ||
4023fb28 | 5644 | (define_insn "*xordi3_cc" |
ae156f85 | 5645 | [(set (reg CC_REGNUM) |
96fd3851 | 5646 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5647 | (match_operand:DI 2 "general_operand" "d,m")) |
5648 | (const_int 0))) | |
5649 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5650 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5651 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5652 | "@ | |
d40c829f UW |
5653 | xgr\t%0,%2 |
5654 | xg\t%0,%2" | |
d3632d41 | 5655 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5656 | |
5657 | (define_insn "*xordi3_cconly" | |
ae156f85 | 5658 | [(set (reg CC_REGNUM) |
96fd3851 | 5659 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5660 | (match_operand:DI 2 "general_operand" "d,m")) |
5661 | (const_int 0))) | |
5662 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5663 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5664 | "@ | |
d40c829f UW |
5665 | xgr\t%0,%2 |
5666 | xr\t%0,%2" | |
d3632d41 | 5667 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5668 | |
ec24698e UW |
5669 | (define_insn "*xordi3_extimm" |
5670 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") | |
5671 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
5672 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q"))) | |
5673 | (clobber (reg:CC CC_REGNUM))] | |
5674 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
5675 | "@ | |
5676 | xihf\t%0,%k2 | |
5677 | xilf\t%0,%k2 | |
5678 | xgr\t%0,%2 | |
5679 | xg\t%0,%2 | |
5680 | # | |
5681 | #" | |
5682 | [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")]) | |
5683 | ||
8cb66696 | 5684 | (define_insn "*xordi3" |
0dfa6c5e UW |
5685 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5686 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5687 | (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) | |
ae156f85 | 5688 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 5689 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5690 | "@ |
d40c829f | 5691 | xgr\t%0,%2 |
8cb66696 | 5692 | xg\t%0,%2 |
0dfa6c5e | 5693 | # |
19b63d8e | 5694 | #" |
0dfa6c5e UW |
5695 | [(set_attr "op_type" "RRE,RXY,SI,SS")]) |
5696 | ||
5697 | (define_split | |
5698 | [(set (match_operand:DI 0 "s_operand" "") | |
5699 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5700 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5701 | "reload_completed" |
5702 | [(parallel | |
5703 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5704 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5705 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 5706 | |
9db1d521 HP |
5707 | ; |
5708 | ; xorsi3 instruction pattern(s). | |
5709 | ; | |
5710 | ||
4023fb28 | 5711 | (define_insn "*xorsi3_cc" |
ae156f85 | 5712 | [(set (reg CC_REGNUM) |
ec24698e UW |
5713 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5714 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5715 | (const_int 0))) |
ec24698e | 5716 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
5717 | (xor:SI (match_dup 1) (match_dup 2)))] |
5718 | "s390_match_ccmode(insn, CCTmode)" | |
5719 | "@ | |
ec24698e | 5720 | xilf\t%0,%o2 |
d40c829f UW |
5721 | xr\t%0,%2 |
5722 | x\t%0,%2 | |
5723 | xy\t%0,%2" | |
ec24698e | 5724 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 UW |
5725 | |
5726 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 5727 | [(set (reg CC_REGNUM) |
ec24698e UW |
5728 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5729 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5730 | (const_int 0))) |
ec24698e | 5731 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
5732 | "s390_match_ccmode(insn, CCTmode)" |
5733 | "@ | |
ec24698e | 5734 | xilf\t%0,%o2 |
d40c829f UW |
5735 | xr\t%0,%2 |
5736 | x\t%0,%2 | |
5737 | xy\t%0,%2" | |
ec24698e | 5738 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 | 5739 | |
8cb66696 | 5740 | (define_insn "*xorsi3" |
ec24698e UW |
5741 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") |
5742 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
5743 | (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 5744 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5745 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5746 | "@ |
ec24698e | 5747 | xilf\t%0,%o2 |
d40c829f UW |
5748 | xr\t%0,%2 |
5749 | x\t%0,%2 | |
8cb66696 | 5750 | xy\t%0,%2 |
0dfa6c5e | 5751 | # |
19b63d8e | 5752 | #" |
ec24698e | 5753 | [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")]) |
0dfa6c5e UW |
5754 | |
5755 | (define_split | |
5756 | [(set (match_operand:SI 0 "s_operand" "") | |
5757 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5758 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5759 | "reload_completed" |
5760 | [(parallel | |
5761 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5762 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5763 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 5764 | |
9db1d521 HP |
5765 | ; |
5766 | ; xorhi3 instruction pattern(s). | |
5767 | ; | |
5768 | ||
8cb66696 | 5769 | (define_insn "*xorhi3" |
ec24698e UW |
5770 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5771 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5772 | (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q"))) | |
ae156f85 | 5773 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5774 | "s390_logical_operator_ok_p (operands)" |
5775 | "@ | |
ec24698e | 5776 | xilf\t%0,%x2 |
8cb66696 | 5777 | xr\t%0,%2 |
0dfa6c5e | 5778 | # |
19b63d8e | 5779 | #" |
ec24698e | 5780 | [(set_attr "op_type" "RIL,RR,SI,SS")]) |
0dfa6c5e UW |
5781 | |
5782 | (define_split | |
5783 | [(set (match_operand:HI 0 "s_operand" "") | |
5784 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5785 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5786 | "reload_completed" |
5787 | [(parallel | |
5788 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5789 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5790 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 5791 | |
9db1d521 HP |
5792 | ; |
5793 | ; xorqi3 instruction pattern(s). | |
5794 | ; | |
5795 | ||
8cb66696 | 5796 | (define_insn "*xorqi3" |
ec24698e UW |
5797 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") |
5798 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5799 | (match_operand:QI 2 "general_operand" "Os,d,n,n,Q"))) | |
ae156f85 | 5800 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5801 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5802 | "@ |
ec24698e | 5803 | xilf\t%0,%b2 |
8cb66696 | 5804 | xr\t%0,%2 |
fc0ea003 UW |
5805 | xi\t%S0,%b2 |
5806 | xiy\t%S0,%b2 | |
19b63d8e | 5807 | #" |
ec24698e | 5808 | [(set_attr "op_type" "RIL,RR,SI,SIY,SS")]) |
4023fb28 | 5809 | |
19b63d8e UW |
5810 | ; |
5811 | ; Block exclusive or (XC) patterns. | |
5812 | ; | |
5813 | ||
5814 | (define_insn "*xc" | |
5815 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5816 | (xor:BLK (match_dup 0) | |
5817 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5818 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5819 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5820 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5821 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 5822 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5823 | |
5824 | (define_split | |
5825 | [(set (match_operand 0 "memory_operand" "") | |
5826 | (xor (match_dup 0) | |
5827 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5828 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5829 | "reload_completed |
5830 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5831 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5832 | [(parallel | |
5833 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
5834 | (use (match_dup 2)) | |
ae156f85 | 5835 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5836 | { |
5837 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5838 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5839 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5840 | }) | |
5841 | ||
5842 | (define_peephole2 | |
5843 | [(parallel | |
5844 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5845 | (xor:BLK (match_dup 0) | |
5846 | (match_operand:BLK 1 "memory_operand" ""))) | |
5847 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5848 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5849 | (parallel |
5850 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5851 | (xor:BLK (match_dup 3) | |
5852 | (match_operand:BLK 4 "memory_operand" ""))) | |
5853 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5854 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5855 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5856 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5857 | && !s390_overlap_p (operands[0], operands[1], |
5858 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5859 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5860 | [(parallel | |
5861 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
5862 | (use (match_dup 8)) | |
ae156f85 | 5863 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5864 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5865 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5866 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5867 | ||
5868 | ; | |
5869 | ; Block xor (XC) patterns with src == dest. | |
5870 | ; | |
5871 | ||
5872 | (define_insn "*xc_zero" | |
5873 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5874 | (const_int 0)) | |
5875 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 5876 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5877 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 5878 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 5879 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5880 | |
5881 | (define_peephole2 | |
5882 | [(parallel | |
5883 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5884 | (const_int 0)) | |
5885 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 5886 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5887 | (parallel |
5888 | [(set (match_operand:BLK 2 "memory_operand" "") | |
5889 | (const_int 0)) | |
5890 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 5891 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5892 | "s390_offset_p (operands[0], operands[2], operands[1]) |
5893 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
5894 | [(parallel | |
5895 | [(set (match_dup 4) (const_int 0)) | |
5896 | (use (match_dup 5)) | |
ae156f85 | 5897 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5898 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5899 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
5900 | ||
9db1d521 HP |
5901 | |
5902 | ;; | |
5903 | ;;- Negate instructions. | |
5904 | ;; | |
5905 | ||
5906 | ; | |
9a91a21f | 5907 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
5908 | ; |
5909 | ||
9a91a21f | 5910 | (define_expand "neg<mode>2" |
9db1d521 | 5911 | [(parallel |
9a91a21f AS |
5912 | [(set (match_operand:DSI 0 "register_operand" "=d") |
5913 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 5914 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5915 | "" |
5916 | "") | |
5917 | ||
26a89301 | 5918 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 5919 | [(set (reg CC_REGNUM) |
26a89301 UW |
5920 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
5921 | (match_operand:SI 1 "register_operand" "d") 0) | |
5922 | (const_int 32)) (const_int 32))) | |
5923 | (const_int 0))) | |
5924 | (set (match_operand:DI 0 "register_operand" "=d") | |
5925 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
5926 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5927 | "lcgfr\t%0,%1" | |
5928 | [(set_attr "op_type" "RRE")]) | |
5929 | ||
5930 | (define_insn "*negdi2_sign" | |
5931 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5932 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 5933 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
5934 | "TARGET_64BIT" |
5935 | "lcgfr\t%0,%1" | |
5936 | [(set_attr "op_type" "RRE")]) | |
5937 | ||
43a09b63 | 5938 | ; lcr, lcgr |
9a91a21f | 5939 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 5940 | [(set (reg CC_REGNUM) |
9a91a21f | 5941 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5942 | (const_int 0))) |
9a91a21f AS |
5943 | (set (match_operand:GPR 0 "register_operand" "=d") |
5944 | (neg:GPR (match_dup 1)))] | |
5945 | "s390_match_ccmode (insn, CCAmode)" | |
5946 | "lc<g>r\t%0,%1" | |
5947 | [(set_attr "op_type" "RR<E>")]) | |
43a09b63 AK |
5948 | |
5949 | ; lcr, lcgr | |
9a91a21f | 5950 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 5951 | [(set (reg CC_REGNUM) |
9a91a21f | 5952 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5953 | (const_int 0))) |
9a91a21f AS |
5954 | (clobber (match_scratch:GPR 0 "=d"))] |
5955 | "s390_match_ccmode (insn, CCAmode)" | |
5956 | "lc<g>r\t%0,%1" | |
5957 | [(set_attr "op_type" "RR<E>")]) | |
43a09b63 AK |
5958 | |
5959 | ; lcr, lcgr | |
9a91a21f AS |
5960 | (define_insn "*neg<mode>2" |
5961 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5962 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 5963 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
5964 | "" |
5965 | "lc<g>r\t%0,%1" | |
5966 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 5967 | |
26a89301 | 5968 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
5969 | [(set (match_operand:DI 0 "register_operand" "=d") |
5970 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 5971 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5972 | "!TARGET_64BIT" |
26a89301 UW |
5973 | "#" |
5974 | "&& reload_completed" | |
5975 | [(parallel | |
5976 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 5977 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 5978 | (parallel |
ae156f85 | 5979 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
5980 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
5981 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
5982 | (set (pc) | |
ae156f85 | 5983 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
5984 | (pc) |
5985 | (label_ref (match_dup 6)))) | |
5986 | (parallel | |
5987 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 5988 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
5989 | (match_dup 6)] |
5990 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
5991 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
5992 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
5993 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
5994 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 5995 | |
9db1d521 | 5996 | ; |
f5905b37 | 5997 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
5998 | ; |
5999 | ||
f5905b37 | 6000 | (define_expand "neg<mode>2" |
9db1d521 | 6001 | [(parallel |
f5905b37 AS |
6002 | [(set (match_operand:FPR 0 "register_operand" "=f") |
6003 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6004 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6005 | "TARGET_HARD_FLOAT" |
6006 | "") | |
6007 | ||
43a09b63 | 6008 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 6009 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 6010 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6011 | (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) |
6012 | (match_operand:FPR 2 "const0_operand" ""))) | |
6013 | (set (match_operand:FPR 0 "register_operand" "=f") | |
6014 | (neg:FPR (match_dup 1)))] | |
26a89301 | 6015 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6016 | "lc<xde>br\t%0,%1" |
26a89301 | 6017 | [(set_attr "op_type" "RRE") |
f5905b37 | 6018 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6019 | |
6020 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 6021 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 6022 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6023 | (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) |
6024 | (match_operand:FPR 2 "const0_operand" ""))) | |
6025 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 6026 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6027 | "lc<xde>br\t%0,%1" |
26a89301 | 6028 | [(set_attr "op_type" "RRE") |
f5905b37 | 6029 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6030 | |
6031 | ; lcxbr, lcdbr, lcebr | |
f5905b37 AS |
6032 | (define_insn "*neg<mode>2" |
6033 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6034 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6035 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6036 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6037 | "lc<xde>br\t%0,%1" |
077dab3b | 6038 | [(set_attr "op_type" "RRE") |
f5905b37 | 6039 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6040 | |
43a09b63 | 6041 | ; lcxr, lcdr, lcer |
f5905b37 AS |
6042 | (define_insn "*neg<mode>2_ibm" |
6043 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6044 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6045 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6046 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f61a2c7d AK |
6047 | "lc<xde>r\t%0,%1" |
6048 | [(set_attr "op_type" "<RRe>") | |
f5905b37 | 6049 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
6050 | |
6051 | ||
6052 | ;; | |
6053 | ;;- Absolute value instructions. | |
6054 | ;; | |
6055 | ||
6056 | ; | |
9a91a21f | 6057 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
6058 | ; |
6059 | ||
26a89301 | 6060 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 6061 | [(set (reg CC_REGNUM) |
26a89301 UW |
6062 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6063 | (match_operand:SI 1 "register_operand" "d") 0) | |
6064 | (const_int 32)) (const_int 32))) | |
6065 | (const_int 0))) | |
6066 | (set (match_operand:DI 0 "register_operand" "=d") | |
6067 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
6068 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6069 | "lpgfr\t%0,%1" | |
6070 | [(set_attr "op_type" "RRE")]) | |
6071 | ||
6072 | (define_insn "*absdi2_sign" | |
6073 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6074 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 6075 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6076 | "TARGET_64BIT" |
6077 | "lpgfr\t%0,%1" | |
6078 | [(set_attr "op_type" "RRE")]) | |
6079 | ||
43a09b63 | 6080 | ; lpr, lpgr |
9a91a21f | 6081 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 6082 | [(set (reg CC_REGNUM) |
9a91a21f | 6083 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 6084 | (const_int 0))) |
9a91a21f AS |
6085 | (set (match_operand:GPR 0 "register_operand" "=d") |
6086 | (abs:GPR (match_dup 1)))] | |
26a89301 | 6087 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6088 | "lp<g>r\t%0,%1" |
6089 | [(set_attr "op_type" "RR<E>")]) | |
43a09b63 AK |
6090 | |
6091 | ; lpr, lpgr | |
9a91a21f | 6092 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 6093 | [(set (reg CC_REGNUM) |
9a91a21f | 6094 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6095 | (const_int 0))) |
9a91a21f | 6096 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6097 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6098 | "lp<g>r\t%0,%1" |
6099 | [(set_attr "op_type" "RR<E>")]) | |
43a09b63 AK |
6100 | |
6101 | ; lpr, lpgr | |
9a91a21f AS |
6102 | (define_insn "abs<mode>2" |
6103 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6104 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 6105 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6106 | "" |
9a91a21f AS |
6107 | "lp<g>r\t%0,%1" |
6108 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 6109 | |
9db1d521 | 6110 | ; |
f5905b37 | 6111 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
6112 | ; |
6113 | ||
f5905b37 | 6114 | (define_expand "abs<mode>2" |
9db1d521 | 6115 | [(parallel |
f5905b37 AS |
6116 | [(set (match_operand:FPR 0 "register_operand" "=f") |
6117 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6118 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6119 | "TARGET_HARD_FLOAT" |
6120 | "") | |
6121 | ||
43a09b63 | 6122 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 6123 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 6124 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6125 | (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) |
6126 | (match_operand:FPR 2 "const0_operand" ""))) | |
6127 | (set (match_operand:FPR 0 "register_operand" "=f") | |
6128 | (abs:FPR (match_dup 1)))] | |
26a89301 | 6129 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6130 | "lp<xde>br\t%0,%1" |
26a89301 | 6131 | [(set_attr "op_type" "RRE") |
f5905b37 | 6132 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6133 | |
6134 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 6135 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 6136 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6137 | (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) |
6138 | (match_operand:FPR 2 "const0_operand" ""))) | |
6139 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 6140 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6141 | "lp<xde>br\t%0,%1" |
26a89301 | 6142 | [(set_attr "op_type" "RRE") |
f5905b37 | 6143 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6144 | |
6145 | ; lpxbr, lpdbr, lpebr | |
f5905b37 AS |
6146 | (define_insn "*abs<mode>2" |
6147 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6148 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6149 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6150 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6151 | "lp<xde>br\t%0,%1" |
077dab3b | 6152 | [(set_attr "op_type" "RRE") |
f5905b37 | 6153 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6154 | |
43a09b63 | 6155 | ; lpxr, lpdr, lper |
f5905b37 AS |
6156 | (define_insn "*abs<mode>2_ibm" |
6157 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6158 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6159 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6160 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f61a2c7d AK |
6161 | "lp<xde>r\t%0,%1" |
6162 | [(set_attr "op_type" "<RRe>") | |
f5905b37 | 6163 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6164 | |
3ef093a8 AK |
6165 | ;; |
6166 | ;;- Negated absolute value instructions | |
6167 | ;; | |
6168 | ||
6169 | ; | |
6170 | ; Integer | |
6171 | ; | |
6172 | ||
26a89301 | 6173 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 6174 | [(set (reg CC_REGNUM) |
26a89301 UW |
6175 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6176 | (match_operand:SI 1 "register_operand" "d") 0) | |
6177 | (const_int 32)) (const_int 32)))) | |
6178 | (const_int 0))) | |
6179 | (set (match_operand:DI 0 "register_operand" "=d") | |
6180 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6181 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6182 | "lngfr\t%0,%1" | |
6183 | [(set_attr "op_type" "RRE")]) | |
6184 | ||
6185 | (define_insn "*negabsdi2_sign" | |
6186 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6187 | (neg:DI (abs:DI (sign_extend:DI | |
6188 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 6189 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6190 | "TARGET_64BIT" |
6191 | "lngfr\t%0,%1" | |
6192 | [(set_attr "op_type" "RRE")]) | |
3ef093a8 | 6193 | |
43a09b63 | 6194 | ; lnr, lngr |
9a91a21f | 6195 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6196 | [(set (reg CC_REGNUM) |
9a91a21f | 6197 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6198 | (const_int 0))) |
9a91a21f AS |
6199 | (set (match_operand:GPR 0 "register_operand" "=d") |
6200 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 6201 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6202 | "ln<g>r\t%0,%1" |
6203 | [(set_attr "op_type" "RR<E>")]) | |
43a09b63 AK |
6204 | |
6205 | ; lnr, lngr | |
9a91a21f | 6206 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6207 | [(set (reg CC_REGNUM) |
9a91a21f | 6208 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6209 | (const_int 0))) |
9a91a21f | 6210 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6211 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6212 | "ln<g>r\t%0,%1" |
6213 | [(set_attr "op_type" "RR<E>")]) | |
43a09b63 AK |
6214 | |
6215 | ; lnr, lngr | |
9a91a21f AS |
6216 | (define_insn "*negabs<mode>2" |
6217 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6218 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 6219 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 6220 | "" |
9a91a21f AS |
6221 | "ln<g>r\t%0,%1" |
6222 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6223 | |
3ef093a8 AK |
6224 | ; |
6225 | ; Floating point | |
6226 | ; | |
6227 | ||
43a09b63 | 6228 | ; lnxbr, lndbr, lnebr |
f5905b37 | 6229 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6230 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6231 | (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) |
6232 | (match_operand:FPR 2 "const0_operand" ""))) | |
6233 | (set (match_operand:FPR 0 "register_operand" "=f") | |
6234 | (neg:FPR (abs:FPR (match_dup 1))))] | |
26a89301 | 6235 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6236 | "ln<xde>br\t%0,%1" |
26a89301 | 6237 | [(set_attr "op_type" "RRE") |
f5905b37 | 6238 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6239 | |
6240 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 6241 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6242 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6243 | (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) |
6244 | (match_operand:FPR 2 "const0_operand" ""))) | |
6245 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 6246 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6247 | "ln<xde>br\t%0,%1" |
26a89301 | 6248 | [(set_attr "op_type" "RRE") |
f5905b37 | 6249 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6250 | |
6251 | ; lnxbr, lndbr, lnebr | |
f5905b37 AS |
6252 | (define_insn "*negabs<mode>2" |
6253 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6254 | (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))) | |
ae156f85 | 6255 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 6256 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f61a2c7d | 6257 | "ln<xde>br\t%0,%1" |
26a89301 | 6258 | [(set_attr "op_type" "RRE") |
f5905b37 | 6259 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6260 | |
4023fb28 UW |
6261 | ;; |
6262 | ;;- Square root instructions. | |
6263 | ;; | |
6264 | ||
6265 | ; | |
f5905b37 | 6266 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
6267 | ; |
6268 | ||
43a09b63 | 6269 | ; sqxbr, sqdbr, sqebr, sqxb, sqdb, sqeb |
f5905b37 AS |
6270 | (define_insn "sqrt<mode>2" |
6271 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
f61a2c7d | 6272 | (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,<Rf>")))] |
4023fb28 UW |
6273 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6274 | "@ | |
f61a2c7d AK |
6275 | sq<xde>br\t%0,%1 |
6276 | sq<xde>b\t%0,%1" | |
a036c6f7 | 6277 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 6278 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 6279 | |
9db1d521 HP |
6280 | |
6281 | ;; | |
6282 | ;;- One complement instructions. | |
6283 | ;; | |
6284 | ||
6285 | ; | |
342cf42b | 6286 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 6287 | ; |
c7453384 | 6288 | |
342cf42b | 6289 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 6290 | [(parallel |
342cf42b AS |
6291 | [(set (match_operand:INT 0 "register_operand" "") |
6292 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
6293 | (const_int -1))) | |
ae156f85 | 6294 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6295 | "" |
4023fb28 | 6296 | "") |
9db1d521 HP |
6297 | |
6298 | ||
ec24698e UW |
6299 | ;; |
6300 | ;; Find leftmost bit instructions. | |
6301 | ;; | |
6302 | ||
6303 | (define_expand "clzdi2" | |
6304 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6305 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
6306 | "TARGET_EXTIMM && TARGET_64BIT" | |
6307 | { | |
6308 | rtx insn, clz_equal; | |
6309 | rtx wide_reg = gen_reg_rtx (TImode); | |
6310 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
6311 | ||
6312 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
6313 | ||
6314 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
6315 | ||
6316 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); | |
6317 | REG_NOTES (insn) = | |
6318 | gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn)); | |
6319 | ||
6320 | DONE; | |
6321 | }) | |
6322 | ||
6323 | (define_insn "clztidi2" | |
6324 | [(set (match_operand:TI 0 "register_operand" "=d") | |
6325 | (ior:TI | |
6326 | (ashift:TI | |
6327 | (zero_extend:TI | |
6328 | (xor:DI (match_operand:DI 1 "register_operand" "d") | |
6329 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
6330 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
6331 | ||
6332 | (const_int 64)) | |
6333 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
6334 | (clobber (reg:CC CC_REGNUM))] | |
6335 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) | |
6336 | == (unsigned HOST_WIDE_INT) 1 << 63 | |
6337 | && TARGET_EXTIMM && TARGET_64BIT" | |
6338 | "flogr\t%0,%1" | |
6339 | [(set_attr "op_type" "RRE")]) | |
6340 | ||
6341 | ||
9db1d521 HP |
6342 | ;; |
6343 | ;;- Rotate instructions. | |
6344 | ;; | |
6345 | ||
6346 | ; | |
9a91a21f | 6347 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
6348 | ; |
6349 | ||
43a09b63 | 6350 | ; rll, rllg |
9a91a21f AS |
6351 | (define_insn "rotl<mode>3" |
6352 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6353 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 6354 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 6355 | "TARGET_CPU_ZARCH" |
9a91a21f | 6356 | "rll<g>\t%0,%1,%Y2" |
077dab3b HP |
6357 | [(set_attr "op_type" "RSE") |
6358 | (set_attr "atype" "reg")]) | |
9db1d521 | 6359 | |
43a09b63 | 6360 | ; rll, rllg |
4989e88a AK |
6361 | (define_insn "*rotl<mode>3_and" |
6362 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6363 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
6364 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6365 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
6366 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
6367 | "rll<g>\t%0,%1,%Y2" | |
6368 | [(set_attr "op_type" "RSE") | |
6369 | (set_attr "atype" "reg")]) | |
6370 | ||
9db1d521 HP |
6371 | |
6372 | ;; | |
f337b930 | 6373 | ;;- Shift instructions. |
9db1d521 | 6374 | ;; |
9db1d521 HP |
6375 | |
6376 | ; | |
1b48c8cc | 6377 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
9db1d521 HP |
6378 | ; |
6379 | ||
1b48c8cc AS |
6380 | (define_expand "<shift><mode>3" |
6381 | [(set (match_operand:DSI 0 "register_operand" "") | |
6382 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
6383 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
6384 | "" |
6385 | "") | |
6386 | ||
43a09b63 | 6387 | ; sldl, srdl |
f337b930 | 6388 | (define_insn "*<shift>di3_31" |
ac32b25e | 6389 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 6390 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 6391 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9db1d521 | 6392 | "!TARGET_64BIT" |
f337b930 | 6393 | "s<lr>dl\t%0,%Y2" |
077dab3b HP |
6394 | [(set_attr "op_type" "RS") |
6395 | (set_attr "atype" "reg")]) | |
9db1d521 | 6396 | |
43a09b63 | 6397 | ; sll, srl, sllg, srlg |
1b48c8cc AS |
6398 | (define_insn "*<shift><mode>3" |
6399 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6400 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
6401 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] | |
6402 | "" | |
6403 | "s<lr>l<g>\t%0,<1>%Y2" | |
6404 | [(set_attr "op_type" "RS<E>") | |
077dab3b | 6405 | (set_attr "atype" "reg")]) |
9db1d521 | 6406 | |
43a09b63 | 6407 | ; sldl, srdl |
4989e88a AK |
6408 | (define_insn "*<shift>di3_31_and" |
6409 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6410 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
6411 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6412 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
6413 | "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
6414 | "s<lr>dl\t%0,%Y2" | |
6415 | [(set_attr "op_type" "RS") | |
6416 | (set_attr "atype" "reg")]) | |
6417 | ||
43a09b63 | 6418 | ; sll, srl, sllg, srlg |
1b48c8cc AS |
6419 | (define_insn "*<shift><mode>3_and" |
6420 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6421 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
6422 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6423 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
6424 | "(INTVAL (operands[3]) & 63) == 63" | |
6425 | "s<lr>l<g>\t%0,<1>%Y2" | |
6426 | [(set_attr "op_type" "RS<E>") | |
4989e88a AK |
6427 | (set_attr "atype" "reg")]) |
6428 | ||
9db1d521 | 6429 | ; |
1b48c8cc | 6430 | ; ashr(di|si)3 instruction pattern(s). |
9db1d521 HP |
6431 | ; |
6432 | ||
1b48c8cc | 6433 | (define_expand "ashr<mode>3" |
9db1d521 | 6434 | [(parallel |
1b48c8cc AS |
6435 | [(set (match_operand:DSI 0 "register_operand" "") |
6436 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
6437 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 6438 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6439 | "" |
6440 | "") | |
6441 | ||
ecbe845e | 6442 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 6443 | [(set (reg CC_REGNUM) |
ac32b25e | 6444 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 6445 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 6446 | (const_int 0))) |
ac32b25e | 6447 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6448 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6449 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6450 | "srda\t%0,%Y2" |
077dab3b HP |
6451 | [(set_attr "op_type" "RS") |
6452 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6453 | |
6454 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 6455 | [(set (reg CC_REGNUM) |
ac32b25e | 6456 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 6457 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 6458 | (const_int 0))) |
ac32b25e | 6459 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6460 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6461 | "srda\t%0,%Y2" |
077dab3b HP |
6462 | [(set_attr "op_type" "RS") |
6463 | (set_attr "atype" "reg")]) | |
ecbe845e | 6464 | |
9db1d521 | 6465 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6466 | [(set (match_operand:DI 0 "register_operand" "=d") |
6467 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 6468 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 6469 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6470 | "!TARGET_64BIT" |
ac32b25e | 6471 | "srda\t%0,%Y2" |
077dab3b HP |
6472 | [(set_attr "op_type" "RS") |
6473 | (set_attr "atype" "reg")]) | |
c7453384 | 6474 | |
43a09b63 | 6475 | ; sra, srag |
1b48c8cc | 6476 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 6477 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
6478 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
6479 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
ecbe845e | 6480 | (const_int 0))) |
1b48c8cc AS |
6481 | (set (match_operand:GPR 0 "register_operand" "=d") |
6482 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] | |
6483 | "s390_match_ccmode(insn, CCSmode)" | |
6484 | "sra<g>\t%0,<1>%Y2" | |
6485 | [(set_attr "op_type" "RS<E>") | |
077dab3b | 6486 | (set_attr "atype" "reg")]) |
ecbe845e | 6487 | |
43a09b63 | 6488 | ; sra, srag |
1b48c8cc | 6489 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 6490 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
6491 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
6492 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
ecbe845e | 6493 | (const_int 0))) |
1b48c8cc AS |
6494 | (clobber (match_scratch:GPR 0 "=d"))] |
6495 | "s390_match_ccmode(insn, CCSmode)" | |
6496 | "sra<g>\t%0,<1>%Y2" | |
6497 | [(set_attr "op_type" "RS<E>") | |
077dab3b | 6498 | (set_attr "atype" "reg")]) |
ecbe845e | 6499 | |
43a09b63 | 6500 | ; sra, srag |
1b48c8cc AS |
6501 | (define_insn "*ashr<mode>3" |
6502 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6503 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
6504 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) | |
ae156f85 | 6505 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc AS |
6506 | "" |
6507 | "sra<g>\t%0,<1>%Y2" | |
6508 | [(set_attr "op_type" "RS<E>") | |
077dab3b HP |
6509 | (set_attr "atype" "reg")]) |
6510 | ||
9db1d521 | 6511 | |
4989e88a AK |
6512 | ; shift pattern with implicit ANDs |
6513 | ||
6514 | (define_insn "*ashrdi3_cc_31_and" | |
6515 | [(set (reg CC_REGNUM) | |
6516 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6517 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6518 | (match_operand:SI 3 "const_int_operand" "n"))) | |
6519 | (const_int 0))) | |
6520 | (set (match_operand:DI 0 "register_operand" "=d") | |
6521 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
6522 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
6523 | && (INTVAL (operands[3]) & 63) == 63" | |
6524 | "srda\t%0,%Y2" | |
6525 | [(set_attr "op_type" "RS") | |
6526 | (set_attr "atype" "reg")]) | |
6527 | ||
6528 | (define_insn "*ashrdi3_cconly_31_and" | |
6529 | [(set (reg CC_REGNUM) | |
6530 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6531 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6532 | (match_operand:SI 3 "const_int_operand" "n"))) | |
6533 | (const_int 0))) | |
6534 | (clobber (match_scratch:DI 0 "=d"))] | |
6535 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
6536 | && (INTVAL (operands[3]) & 63) == 63" | |
6537 | "srda\t%0,%Y2" | |
6538 | [(set_attr "op_type" "RS") | |
6539 | (set_attr "atype" "reg")]) | |
6540 | ||
6541 | (define_insn "*ashrdi3_31_and" | |
6542 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6543 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6544 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6545 | (match_operand:SI 3 "const_int_operand" "n")))) | |
6546 | (clobber (reg:CC CC_REGNUM))] | |
6547 | "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
6548 | "srda\t%0,%Y2" | |
6549 | [(set_attr "op_type" "RS") | |
6550 | (set_attr "atype" "reg")]) | |
6551 | ||
43a09b63 | 6552 | ; sra, srag |
1b48c8cc | 6553 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 6554 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
6555 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
6556 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6557 | (match_operand:SI 3 "const_int_operand" "n"))) | |
4989e88a | 6558 | (const_int 0))) |
1b48c8cc AS |
6559 | (set (match_operand:GPR 0 "register_operand" "=d") |
6560 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
4989e88a | 6561 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
1b48c8cc AS |
6562 | "sra<g>\t%0,<1>%Y2" |
6563 | [(set_attr "op_type" "RS<E>") | |
4989e88a AK |
6564 | (set_attr "atype" "reg")]) |
6565 | ||
43a09b63 | 6566 | ; sra, srag |
1b48c8cc | 6567 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 6568 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
6569 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
6570 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6571 | (match_operand:SI 3 "const_int_operand" "n"))) | |
4989e88a | 6572 | (const_int 0))) |
1b48c8cc | 6573 | (clobber (match_scratch:GPR 0 "=d"))] |
4989e88a | 6574 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
1b48c8cc AS |
6575 | "sra<g>\t%0,<1>%Y2" |
6576 | [(set_attr "op_type" "RS<E>") | |
4989e88a AK |
6577 | (set_attr "atype" "reg")]) |
6578 | ||
43a09b63 | 6579 | ; sra, srag |
1b48c8cc AS |
6580 | (define_insn "*ashr<mode>3_and" |
6581 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6582 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
6583 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6584 | (match_operand:SI 3 "const_int_operand" "n")))) | |
4989e88a AK |
6585 | (clobber (reg:CC CC_REGNUM))] |
6586 | "(INTVAL (operands[3]) & 63) == 63" | |
1b48c8cc AS |
6587 | "sra<g>\t%0,<1>%Y2" |
6588 | [(set_attr "op_type" "RS<E>") | |
4989e88a AK |
6589 | (set_attr "atype" "reg")]) |
6590 | ||
9db1d521 | 6591 | |
9db1d521 HP |
6592 | ;; |
6593 | ;; Branch instruction patterns. | |
6594 | ;; | |
6595 | ||
fa77b251 AS |
6596 | (define_expand "b<code>" |
6597 | [(set (pc) | |
6598 | (if_then_else (COMPARE (match_operand 0 "" "") | |
6599 | (const_int 0)) | |
6600 | (match_dup 0) | |
6601 | (pc)))] | |
ba956982 | 6602 | "" |
6590e19a | 6603 | "s390_emit_jump (operands[0], |
fa77b251 | 6604 | s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;") |
ba956982 | 6605 | |
9db1d521 HP |
6606 | |
6607 | ;; | |
6608 | ;;- Conditional jump instructions. | |
6609 | ;; | |
6610 | ||
6590e19a UW |
6611 | (define_insn "*cjump_64" |
6612 | [(set (pc) | |
6613 | (if_then_else | |
ae156f85 | 6614 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6615 | (label_ref (match_operand 0 "" "")) |
6616 | (pc)))] | |
6617 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6618 | { |
13e58269 | 6619 | if (get_attr_length (insn) == 4) |
d40c829f | 6620 | return "j%C1\t%l0"; |
6590e19a | 6621 | else |
d40c829f | 6622 | return "jg%C1\t%l0"; |
6590e19a UW |
6623 | } |
6624 | [(set_attr "op_type" "RI") | |
6625 | (set_attr "type" "branch") | |
6626 | (set (attr "length") | |
6627 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6628 | (const_int 4) (const_int 6)))]) | |
6629 | ||
6630 | (define_insn "*cjump_31" | |
6631 | [(set (pc) | |
6632 | (if_then_else | |
ae156f85 | 6633 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6634 | (label_ref (match_operand 0 "" "")) |
6635 | (pc)))] | |
6636 | "!TARGET_CPU_ZARCH" | |
6637 | { | |
8d933e31 AS |
6638 | gcc_assert (get_attr_length (insn) == 4); |
6639 | return "j%C1\t%l0"; | |
10bbf137 | 6640 | } |
9db1d521 | 6641 | [(set_attr "op_type" "RI") |
077dab3b | 6642 | (set_attr "type" "branch") |
13e58269 | 6643 | (set (attr "length") |
6590e19a UW |
6644 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6645 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6646 | (const_int 4) (const_int 6)) | |
6647 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6648 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6649 | |
f314b9b1 | 6650 | (define_insn "*cjump_long" |
6590e19a UW |
6651 | [(set (pc) |
6652 | (if_then_else | |
ae156f85 | 6653 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6654 | (match_operand 0 "address_operand" "U") |
6655 | (pc)))] | |
9db1d521 | 6656 | "" |
f314b9b1 UW |
6657 | { |
6658 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6659 | return "b%C1r\t%0"; |
f314b9b1 | 6660 | else |
d40c829f | 6661 | return "b%C1\t%a0"; |
10bbf137 | 6662 | } |
c7453384 | 6663 | [(set (attr "op_type") |
f314b9b1 UW |
6664 | (if_then_else (match_operand 0 "register_operand" "") |
6665 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 6666 | (set_attr "type" "branch") |
077dab3b | 6667 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6668 | |
6669 | ||
6670 | ;; | |
6671 | ;;- Negated conditional jump instructions. | |
6672 | ;; | |
6673 | ||
6590e19a UW |
6674 | (define_insn "*icjump_64" |
6675 | [(set (pc) | |
6676 | (if_then_else | |
ae156f85 | 6677 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6678 | (pc) |
6679 | (label_ref (match_operand 0 "" ""))))] | |
6680 | "TARGET_CPU_ZARCH" | |
c7453384 | 6681 | { |
13e58269 | 6682 | if (get_attr_length (insn) == 4) |
d40c829f | 6683 | return "j%D1\t%l0"; |
6590e19a | 6684 | else |
d40c829f | 6685 | return "jg%D1\t%l0"; |
6590e19a UW |
6686 | } |
6687 | [(set_attr "op_type" "RI") | |
6688 | (set_attr "type" "branch") | |
6689 | (set (attr "length") | |
6690 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6691 | (const_int 4) (const_int 6)))]) | |
6692 | ||
6693 | (define_insn "*icjump_31" | |
6694 | [(set (pc) | |
6695 | (if_then_else | |
ae156f85 | 6696 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6697 | (pc) |
6698 | (label_ref (match_operand 0 "" ""))))] | |
6699 | "!TARGET_CPU_ZARCH" | |
6700 | { | |
8d933e31 AS |
6701 | gcc_assert (get_attr_length (insn) == 4); |
6702 | return "j%D1\t%l0"; | |
10bbf137 | 6703 | } |
9db1d521 | 6704 | [(set_attr "op_type" "RI") |
077dab3b | 6705 | (set_attr "type" "branch") |
13e58269 | 6706 | (set (attr "length") |
6590e19a UW |
6707 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6708 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6709 | (const_int 4) (const_int 6)) | |
6710 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6711 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6712 | |
f314b9b1 | 6713 | (define_insn "*icjump_long" |
6590e19a UW |
6714 | [(set (pc) |
6715 | (if_then_else | |
ae156f85 | 6716 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6717 | (pc) |
6718 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 6719 | "" |
f314b9b1 UW |
6720 | { |
6721 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6722 | return "b%D1r\t%0"; |
f314b9b1 | 6723 | else |
d40c829f | 6724 | return "b%D1\t%a0"; |
10bbf137 | 6725 | } |
c7453384 | 6726 | [(set (attr "op_type") |
f314b9b1 UW |
6727 | (if_then_else (match_operand 0 "register_operand" "") |
6728 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6729 | (set_attr "type" "branch") |
6730 | (set_attr "atype" "agen")]) | |
9db1d521 | 6731 | |
4456530d HP |
6732 | ;; |
6733 | ;;- Trap instructions. | |
6734 | ;; | |
6735 | ||
6736 | (define_insn "trap" | |
6737 | [(trap_if (const_int 1) (const_int 0))] | |
6738 | "" | |
d40c829f | 6739 | "j\t.+2" |
6590e19a | 6740 | [(set_attr "op_type" "RI") |
077dab3b | 6741 | (set_attr "type" "branch")]) |
4456530d HP |
6742 | |
6743 | (define_expand "conditional_trap" | |
6590e19a UW |
6744 | [(trap_if (match_operand 0 "comparison_operator" "") |
6745 | (match_operand 1 "general_operand" ""))] | |
4456530d | 6746 | "" |
4456530d | 6747 | { |
6590e19a UW |
6748 | if (operands[1] != const0_rtx) FAIL; |
6749 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
6750 | s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6751 | }) |
4456530d HP |
6752 | |
6753 | (define_insn "*trap" | |
ae156f85 | 6754 | [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4456530d HP |
6755 | (const_int 0))] |
6756 | "" | |
d40c829f | 6757 | "j%C0\t.+2"; |
077dab3b HP |
6758 | [(set_attr "op_type" "RI") |
6759 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6760 | |
6761 | ;; | |
0a3bdf9d | 6762 | ;;- Loop instructions. |
9db1d521 | 6763 | ;; |
0a3bdf9d UW |
6764 | ;; This is all complicated by the fact that since this is a jump insn |
6765 | ;; we must handle our own output reloads. | |
c7453384 | 6766 | |
0a3bdf9d UW |
6767 | (define_expand "doloop_end" |
6768 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6769 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6770 | (use (match_operand 2 "" "")) ; max iterations | |
6771 | (use (match_operand 3 "" "")) ; loop level | |
6772 | (use (match_operand 4 "" ""))] ; label | |
6773 | "" | |
0a3bdf9d | 6774 | { |
6590e19a UW |
6775 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
6776 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
6777 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
6778 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
6779 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
6780 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6781 | else | |
6782 | FAIL; | |
6783 | ||
6784 | DONE; | |
10bbf137 | 6785 | }) |
0a3bdf9d | 6786 | |
6590e19a | 6787 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
6788 | [(set (pc) |
6789 | (if_then_else | |
7e665d18 | 6790 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
6791 | (const_int 1)) |
6792 | (label_ref (match_operand 0 "" "")) | |
6793 | (pc))) | |
7e665d18 | 6794 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 6795 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 6796 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 6797 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 6798 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6799 | { |
6800 | if (which_alternative != 0) | |
10bbf137 | 6801 | return "#"; |
0a3bdf9d | 6802 | else if (get_attr_length (insn) == 4) |
d40c829f | 6803 | return "brct\t%1,%l0"; |
6590e19a | 6804 | else |
545d16ff | 6805 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
6806 | } |
6807 | "&& reload_completed | |
6808 | && (! REG_P (operands[2]) | |
6809 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
6810 | [(set (match_dup 3) (match_dup 1)) |
6811 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
6812 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6813 | (const_int 0))) | |
6814 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6815 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6816 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
6817 | (label_ref (match_dup 0)) |
6818 | (pc)))] | |
6819 | "" | |
6820 | [(set_attr "op_type" "RI") | |
6821 | (set_attr "type" "branch") | |
6822 | (set (attr "length") | |
6823 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6824 | (const_int 4) (const_int 10)))]) | |
6825 | ||
6826 | (define_insn_and_split "doloop_si31" | |
6827 | [(set (pc) | |
6828 | (if_then_else | |
7e665d18 | 6829 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
6830 | (const_int 1)) |
6831 | (label_ref (match_operand 0 "" "")) | |
6832 | (pc))) | |
7e665d18 | 6833 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 6834 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 6835 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 6836 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
6837 | "!TARGET_CPU_ZARCH" |
6838 | { | |
6839 | if (which_alternative != 0) | |
6840 | return "#"; | |
6841 | else if (get_attr_length (insn) == 4) | |
6842 | return "brct\t%1,%l0"; | |
0a3bdf9d | 6843 | else |
8d933e31 | 6844 | gcc_unreachable (); |
10bbf137 | 6845 | } |
6590e19a UW |
6846 | "&& reload_completed |
6847 | && (! REG_P (operands[2]) | |
6848 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
6849 | [(set (match_dup 3) (match_dup 1)) |
6850 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
6851 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6852 | (const_int 0))) | |
6853 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6854 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6855 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
6856 | (label_ref (match_dup 0)) |
6857 | (pc)))] | |
6858 | "" | |
0a3bdf9d | 6859 | [(set_attr "op_type" "RI") |
077dab3b | 6860 | (set_attr "type" "branch") |
0a3bdf9d | 6861 | (set (attr "length") |
6590e19a UW |
6862 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6863 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6864 | (const_int 4) (const_int 6)) | |
6865 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6866 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6867 | |
0a3bdf9d UW |
6868 | (define_insn "*doloop_si_long" |
6869 | [(set (pc) | |
6870 | (if_then_else | |
7e665d18 | 6871 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 6872 | (const_int 1)) |
7e665d18 | 6873 | (match_operand 0 "address_operand" "U") |
0a3bdf9d | 6874 | (pc))) |
7e665d18 | 6875 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 6876 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 6877 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 6878 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 6879 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6880 | { |
6881 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6882 | return "bctr\t%1,%0"; |
0a3bdf9d | 6883 | else |
d40c829f | 6884 | return "bct\t%1,%a0"; |
10bbf137 | 6885 | } |
c7453384 | 6886 | [(set (attr "op_type") |
0a3bdf9d UW |
6887 | (if_then_else (match_operand 0 "register_operand" "") |
6888 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6889 | (set_attr "type" "branch") |
6890 | (set_attr "atype" "agen")]) | |
0a3bdf9d | 6891 | |
6590e19a | 6892 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
6893 | [(set (pc) |
6894 | (if_then_else | |
7e665d18 | 6895 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
6896 | (const_int 1)) |
6897 | (label_ref (match_operand 0 "" "")) | |
6898 | (pc))) | |
7e665d18 | 6899 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 6900 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 6901 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 6902 | (clobber (reg:CC CC_REGNUM))] |
0a3bdf9d | 6903 | "TARGET_64BIT" |
0a3bdf9d UW |
6904 | { |
6905 | if (which_alternative != 0) | |
10bbf137 | 6906 | return "#"; |
0a3bdf9d | 6907 | else if (get_attr_length (insn) == 4) |
d40c829f | 6908 | return "brctg\t%1,%l0"; |
0a3bdf9d | 6909 | else |
545d16ff | 6910 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 6911 | } |
6590e19a | 6912 | "&& reload_completed |
0a3bdf9d UW |
6913 | && (! REG_P (operands[2]) |
6914 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
6915 | [(set (match_dup 3) (match_dup 1)) |
6916 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
6917 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
6918 | (const_int 0))) | |
6919 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6920 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6921 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 6922 | (label_ref (match_dup 0)) |
0a3bdf9d | 6923 | (pc)))] |
6590e19a UW |
6924 | "" |
6925 | [(set_attr "op_type" "RI") | |
6926 | (set_attr "type" "branch") | |
6927 | (set (attr "length") | |
6928 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6929 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
6930 | |
6931 | ;; | |
6932 | ;;- Unconditional jump instructions. | |
6933 | ;; | |
6934 | ||
6935 | ; | |
6936 | ; jump instruction pattern(s). | |
6937 | ; | |
6938 | ||
6590e19a UW |
6939 | (define_expand "jump" |
6940 | [(match_operand 0 "" "")] | |
9db1d521 | 6941 | "" |
6590e19a UW |
6942 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
6943 | ||
6944 | (define_insn "*jump64" | |
6945 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6946 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6947 | { |
13e58269 | 6948 | if (get_attr_length (insn) == 4) |
d40c829f | 6949 | return "j\t%l0"; |
6590e19a | 6950 | else |
d40c829f | 6951 | return "jg\t%l0"; |
6590e19a UW |
6952 | } |
6953 | [(set_attr "op_type" "RI") | |
6954 | (set_attr "type" "branch") | |
6955 | (set (attr "length") | |
6956 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6957 | (const_int 4) (const_int 6)))]) | |
6958 | ||
6959 | (define_insn "*jump31" | |
6960 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6961 | "!TARGET_CPU_ZARCH" | |
6962 | { | |
8d933e31 AS |
6963 | gcc_assert (get_attr_length (insn) == 4); |
6964 | return "j\t%l0"; | |
10bbf137 | 6965 | } |
9db1d521 | 6966 | [(set_attr "op_type" "RI") |
077dab3b | 6967 | (set_attr "type" "branch") |
13e58269 | 6968 | (set (attr "length") |
6590e19a UW |
6969 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6970 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6971 | (const_int 4) (const_int 6)) | |
6972 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6973 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
6974 | |
6975 | ; | |
6976 | ; indirect-jump instruction pattern(s). | |
6977 | ; | |
6978 | ||
6979 | (define_insn "indirect_jump" | |
d3632d41 | 6980 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6981 | "" |
f314b9b1 UW |
6982 | { |
6983 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6984 | return "br\t%0"; |
f314b9b1 | 6985 | else |
d40c829f | 6986 | return "b\t%a0"; |
10bbf137 | 6987 | } |
c7453384 | 6988 | [(set (attr "op_type") |
f314b9b1 UW |
6989 | (if_then_else (match_operand 0 "register_operand" "") |
6990 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6991 | (set_attr "type" "branch") |
6992 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6993 | |
6994 | ; | |
f314b9b1 | 6995 | ; casesi instruction pattern(s). |
9db1d521 HP |
6996 | ; |
6997 | ||
f314b9b1 | 6998 | (define_insn "casesi_jump" |
d3632d41 | 6999 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 7000 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 7001 | "" |
9db1d521 | 7002 | { |
f314b9b1 | 7003 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 7004 | return "br\t%0"; |
f314b9b1 | 7005 | else |
d40c829f | 7006 | return "b\t%a0"; |
10bbf137 | 7007 | } |
c7453384 | 7008 | [(set (attr "op_type") |
f314b9b1 UW |
7009 | (if_then_else (match_operand 0 "register_operand" "") |
7010 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7011 | (set_attr "type" "branch") |
7012 | (set_attr "atype" "agen")]) | |
9db1d521 | 7013 | |
f314b9b1 UW |
7014 | (define_expand "casesi" |
7015 | [(match_operand:SI 0 "general_operand" "") | |
7016 | (match_operand:SI 1 "general_operand" "") | |
7017 | (match_operand:SI 2 "general_operand" "") | |
7018 | (label_ref (match_operand 3 "" "")) | |
7019 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 7020 | "" |
f314b9b1 UW |
7021 | { |
7022 | rtx index = gen_reg_rtx (SImode); | |
7023 | rtx base = gen_reg_rtx (Pmode); | |
7024 | rtx target = gen_reg_rtx (Pmode); | |
7025 | ||
7026 | emit_move_insn (index, operands[0]); | |
7027 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
7028 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 7029 | operands[4]); |
f314b9b1 UW |
7030 | |
7031 | if (Pmode != SImode) | |
7032 | index = convert_to_mode (Pmode, index, 1); | |
7033 | if (GET_CODE (index) != REG) | |
7034 | index = copy_to_mode_reg (Pmode, index); | |
7035 | ||
7036 | if (TARGET_64BIT) | |
7037 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
7038 | else | |
a556fd39 | 7039 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 7040 | |
f314b9b1 UW |
7041 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
7042 | ||
542a8afa | 7043 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
7044 | emit_move_insn (target, index); |
7045 | ||
7046 | if (flag_pic) | |
7047 | target = gen_rtx_PLUS (Pmode, base, target); | |
7048 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
7049 | ||
7050 | DONE; | |
10bbf137 | 7051 | }) |
9db1d521 HP |
7052 | |
7053 | ||
7054 | ;; | |
7055 | ;;- Jump to subroutine. | |
7056 | ;; | |
7057 | ;; | |
7058 | ||
7059 | ; | |
7060 | ; untyped call instruction pattern(s). | |
7061 | ; | |
7062 | ||
7063 | ;; Call subroutine returning any type. | |
7064 | (define_expand "untyped_call" | |
7065 | [(parallel [(call (match_operand 0 "" "") | |
7066 | (const_int 0)) | |
7067 | (match_operand 1 "" "") | |
7068 | (match_operand 2 "" "")])] | |
7069 | "" | |
9db1d521 HP |
7070 | { |
7071 | int i; | |
7072 | ||
7073 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
7074 | ||
7075 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7076 | { | |
7077 | rtx set = XVECEXP (operands[2], 0, i); | |
7078 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7079 | } | |
7080 | ||
7081 | /* The optimizer does not know that the call sets the function value | |
7082 | registers we stored in the result block. We avoid problems by | |
7083 | claiming that all hard registers are used and clobbered at this | |
7084 | point. */ | |
7085 | emit_insn (gen_blockage ()); | |
7086 | ||
7087 | DONE; | |
10bbf137 | 7088 | }) |
9db1d521 HP |
7089 | |
7090 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7091 | ;; all of memory. This blocks insns from being moved across this point. | |
7092 | ||
7093 | (define_insn "blockage" | |
10bbf137 | 7094 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 7095 | "" |
4023fb28 | 7096 | "" |
d5869ca0 UW |
7097 | [(set_attr "type" "none") |
7098 | (set_attr "length" "0")]) | |
4023fb28 | 7099 | |
9db1d521 | 7100 | ; |
ed9676cf | 7101 | ; sibcall patterns |
9db1d521 HP |
7102 | ; |
7103 | ||
ed9676cf | 7104 | (define_expand "sibcall" |
44b8152b | 7105 | [(call (match_operand 0 "" "") |
ed9676cf | 7106 | (match_operand 1 "" ""))] |
9db1d521 | 7107 | "" |
9db1d521 | 7108 | { |
ed9676cf AK |
7109 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
7110 | DONE; | |
7111 | }) | |
9db1d521 | 7112 | |
ed9676cf | 7113 | (define_insn "*sibcall_br" |
ae156f85 | 7114 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 7115 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 7116 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7117 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
7118 | "br\t%%r1" | |
7119 | [(set_attr "op_type" "RR") | |
7120 | (set_attr "type" "branch") | |
7121 | (set_attr "atype" "agen")]) | |
9db1d521 | 7122 | |
ed9676cf AK |
7123 | (define_insn "*sibcall_brc" |
7124 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7125 | (match_operand 1 "const_int_operand" "n"))] | |
7126 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7127 | "j\t%0" | |
7128 | [(set_attr "op_type" "RI") | |
7129 | (set_attr "type" "branch")]) | |
9db1d521 | 7130 | |
ed9676cf AK |
7131 | (define_insn "*sibcall_brcl" |
7132 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7133 | (match_operand 1 "const_int_operand" "n"))] | |
7134 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7135 | "jg\t%0" | |
7136 | [(set_attr "op_type" "RIL") | |
7137 | (set_attr "type" "branch")]) | |
44b8152b | 7138 | |
ed9676cf AK |
7139 | ; |
7140 | ; sibcall_value patterns | |
7141 | ; | |
9e8327e3 | 7142 | |
ed9676cf AK |
7143 | (define_expand "sibcall_value" |
7144 | [(set (match_operand 0 "" "") | |
7145 | (call (match_operand 1 "" "") | |
7146 | (match_operand 2 "" "")))] | |
7147 | "" | |
7148 | { | |
7149 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 7150 | DONE; |
10bbf137 | 7151 | }) |
9db1d521 | 7152 | |
ed9676cf AK |
7153 | (define_insn "*sibcall_value_br" |
7154 | [(set (match_operand 0 "" "") | |
ae156f85 | 7155 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 7156 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 7157 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7158 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
7159 | "br\t%%r1" | |
7160 | [(set_attr "op_type" "RR") | |
7161 | (set_attr "type" "branch") | |
7162 | (set_attr "atype" "agen")]) | |
7163 | ||
7164 | (define_insn "*sibcall_value_brc" | |
7165 | [(set (match_operand 0 "" "") | |
7166 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7167 | (match_operand 2 "const_int_operand" "n")))] | |
7168 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7169 | "j\t%1" | |
7170 | [(set_attr "op_type" "RI") | |
7171 | (set_attr "type" "branch")]) | |
7172 | ||
7173 | (define_insn "*sibcall_value_brcl" | |
7174 | [(set (match_operand 0 "" "") | |
7175 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7176 | (match_operand 2 "const_int_operand" "n")))] | |
7177 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7178 | "jg\t%1" | |
7179 | [(set_attr "op_type" "RIL") | |
7180 | (set_attr "type" "branch")]) | |
7181 | ||
7182 | ||
7183 | ; | |
7184 | ; call instruction pattern(s). | |
7185 | ; | |
7186 | ||
7187 | (define_expand "call" | |
7188 | [(call (match_operand 0 "" "") | |
7189 | (match_operand 1 "" "")) | |
7190 | (use (match_operand 2 "" ""))] | |
44b8152b | 7191 | "" |
ed9676cf | 7192 | { |
2f7e5a0d | 7193 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
7194 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
7195 | DONE; | |
7196 | }) | |
44b8152b | 7197 | |
9e8327e3 UW |
7198 | (define_insn "*bras" |
7199 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7200 | (match_operand 1 "const_int_operand" "n")) | |
7201 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7202 | "!SIBLING_CALL_P (insn) |
7203 | && TARGET_SMALL_EXEC | |
ed9676cf | 7204 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 7205 | "bras\t%2,%0" |
9db1d521 | 7206 | [(set_attr "op_type" "RI") |
4023fb28 | 7207 | (set_attr "type" "jsr")]) |
9db1d521 | 7208 | |
9e8327e3 UW |
7209 | (define_insn "*brasl" |
7210 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7211 | (match_operand 1 "const_int_operand" "n")) | |
7212 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7213 | "!SIBLING_CALL_P (insn) |
7214 | && TARGET_CPU_ZARCH | |
ed9676cf | 7215 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7216 | "brasl\t%2,%0" |
7217 | [(set_attr "op_type" "RIL") | |
077dab3b | 7218 | (set_attr "type" "jsr")]) |
9db1d521 | 7219 | |
9e8327e3 UW |
7220 | (define_insn "*basr" |
7221 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
7222 | (match_operand 1 "const_int_operand" "n")) | |
7223 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 7224 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7225 | { |
7226 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7227 | return "basr\t%2,%0"; | |
7228 | else | |
7229 | return "bas\t%2,%a0"; | |
7230 | } | |
7231 | [(set (attr "op_type") | |
7232 | (if_then_else (match_operand 0 "register_operand" "") | |
7233 | (const_string "RR") (const_string "RX"))) | |
7234 | (set_attr "type" "jsr") | |
7235 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7236 | |
7237 | ; | |
7238 | ; call_value instruction pattern(s). | |
7239 | ; | |
7240 | ||
7241 | (define_expand "call_value" | |
44b8152b UW |
7242 | [(set (match_operand 0 "" "") |
7243 | (call (match_operand 1 "" "") | |
7244 | (match_operand 2 "" ""))) | |
7245 | (use (match_operand 3 "" ""))] | |
9db1d521 | 7246 | "" |
9db1d521 | 7247 | { |
2f7e5a0d | 7248 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 7249 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 7250 | DONE; |
10bbf137 | 7251 | }) |
9db1d521 | 7252 | |
9e8327e3 | 7253 | (define_insn "*bras_r" |
c19ec8f9 | 7254 | [(set (match_operand 0 "" "") |
9e8327e3 | 7255 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7256 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 7257 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
7258 | "!SIBLING_CALL_P (insn) |
7259 | && TARGET_SMALL_EXEC | |
ed9676cf | 7260 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7261 | "bras\t%3,%1" |
9db1d521 | 7262 | [(set_attr "op_type" "RI") |
f2d3c02a | 7263 | (set_attr "type" "jsr")]) |
9db1d521 | 7264 | |
9e8327e3 | 7265 | (define_insn "*brasl_r" |
c19ec8f9 | 7266 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7267 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7268 | (match_operand 2 "const_int_operand" "n"))) | |
7269 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
7270 | "!SIBLING_CALL_P (insn) |
7271 | && TARGET_CPU_ZARCH | |
ed9676cf | 7272 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7273 | "brasl\t%3,%1" |
7274 | [(set_attr "op_type" "RIL") | |
077dab3b | 7275 | (set_attr "type" "jsr")]) |
9db1d521 | 7276 | |
9e8327e3 | 7277 | (define_insn "*basr_r" |
c19ec8f9 | 7278 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7279 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7280 | (match_operand 2 "const_int_operand" "n"))) | |
7281 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 7282 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7283 | { |
7284 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7285 | return "basr\t%3,%1"; | |
7286 | else | |
7287 | return "bas\t%3,%a1"; | |
7288 | } | |
7289 | [(set (attr "op_type") | |
7290 | (if_then_else (match_operand 1 "register_operand" "") | |
7291 | (const_string "RR") (const_string "RX"))) | |
7292 | (set_attr "type" "jsr") | |
7293 | (set_attr "atype" "agen")]) | |
9db1d521 | 7294 | |
fd3cd001 UW |
7295 | ;; |
7296 | ;;- Thread-local storage support. | |
7297 | ;; | |
7298 | ||
c5aa1d12 | 7299 | (define_expand "get_tp_64" |
ae156f85 | 7300 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] |
fd3cd001 | 7301 | "TARGET_64BIT" |
c5aa1d12 | 7302 | "") |
fd3cd001 | 7303 | |
c5aa1d12 | 7304 | (define_expand "get_tp_31" |
ae156f85 | 7305 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] |
fd3cd001 | 7306 | "!TARGET_64BIT" |
c5aa1d12 | 7307 | "") |
fd3cd001 | 7308 | |
c5aa1d12 | 7309 | (define_expand "set_tp_64" |
ae156f85 AS |
7310 | [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) |
7311 | (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 7312 | "TARGET_64BIT" |
c5aa1d12 | 7313 | "") |
fd3cd001 | 7314 | |
c5aa1d12 | 7315 | (define_expand "set_tp_31" |
ae156f85 AS |
7316 | [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) |
7317 | (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 7318 | "!TARGET_64BIT" |
c5aa1d12 UW |
7319 | "") |
7320 | ||
7321 | (define_insn "*set_tp" | |
ae156f85 | 7322 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
7323 | "" |
7324 | "" | |
7325 | [(set_attr "type" "none") | |
7326 | (set_attr "length" "0")]) | |
c7453384 | 7327 | |
fd3cd001 UW |
7328 | (define_insn "*tls_load_64" |
7329 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7330 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7331 | (match_operand:DI 2 "" "")] | |
7332 | UNSPEC_TLS_LOAD))] | |
7333 | "TARGET_64BIT" | |
d40c829f | 7334 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7335 | [(set_attr "op_type" "RXE")]) |
7336 | ||
7337 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7338 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7339 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7340 | (match_operand:SI 2 "" "")] |
7341 | UNSPEC_TLS_LOAD))] | |
7342 | "!TARGET_64BIT" | |
d3632d41 | 7343 | "@ |
d40c829f UW |
7344 | l\t%0,%1%J2 |
7345 | ly\t%0,%1%J2" | |
d3632d41 | 7346 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 | 7347 | |
9e8327e3 | 7348 | (define_insn "*bras_tls" |
c19ec8f9 | 7349 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7350 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7351 | (match_operand 2 "const_int_operand" "n"))) | |
7352 | (clobber (match_operand 3 "register_operand" "=r")) | |
7353 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7354 | "!SIBLING_CALL_P (insn) |
7355 | && TARGET_SMALL_EXEC | |
ed9676cf | 7356 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7357 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7358 | [(set_attr "op_type" "RI") |
7359 | (set_attr "type" "jsr")]) | |
7360 | ||
9e8327e3 | 7361 | (define_insn "*brasl_tls" |
c19ec8f9 | 7362 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7363 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7364 | (match_operand 2 "const_int_operand" "n"))) | |
7365 | (clobber (match_operand 3 "register_operand" "=r")) | |
7366 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7367 | "!SIBLING_CALL_P (insn) |
7368 | && TARGET_CPU_ZARCH | |
ed9676cf | 7369 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7370 | "brasl\t%3,%1%J4" |
7371 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7372 | (set_attr "type" "jsr")]) |
7373 | ||
9e8327e3 | 7374 | (define_insn "*basr_tls" |
c19ec8f9 | 7375 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7376 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7377 | (match_operand 2 "const_int_operand" "n"))) | |
7378 | (clobber (match_operand 3 "register_operand" "=r")) | |
7379 | (use (match_operand 4 "" ""))] | |
ed9676cf | 7380 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7381 | { |
7382 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7383 | return "basr\t%3,%1%J4"; | |
7384 | else | |
7385 | return "bas\t%3,%a1%J4"; | |
7386 | } | |
7387 | [(set (attr "op_type") | |
7388 | (if_then_else (match_operand 1 "register_operand" "") | |
7389 | (const_string "RR") (const_string "RX"))) | |
7390 | (set_attr "type" "jsr") | |
7391 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7392 | |
e0374221 AS |
7393 | ;; |
7394 | ;;- Atomic operations | |
7395 | ;; | |
7396 | ||
7397 | ; | |
7398 | ; memory barrier pattern. | |
7399 | ; | |
7400 | ||
7401 | (define_expand "memory_barrier" | |
7402 | [(set (mem:BLK (match_dup 0)) | |
7403 | (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))] | |
7404 | "" | |
7405 | { | |
7406 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
7407 | MEM_VOLATILE_P (operands[0]) = 1; | |
7408 | }) | |
7409 | ||
7410 | (define_insn "*memory_barrier" | |
7411 | [(set (match_operand:BLK 0 "" "") | |
7412 | (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))] | |
7413 | "" | |
7414 | "bcr\t15,0" | |
7415 | [(set_attr "op_type" "RR")]) | |
7416 | ||
7417 | ; | |
7418 | ; compare and swap patterns. | |
7419 | ; | |
7420 | ||
8006eaa6 AS |
7421 | (define_expand "sync_compare_and_swap<mode>" |
7422 | [(parallel | |
7423 | [(set (match_operand:TDSI 0 "register_operand" "") | |
7424 | (match_operand:TDSI 1 "memory_operand" "")) | |
7425 | (set (match_dup 1) | |
7426 | (unspec_volatile:TDSI | |
7427 | [(match_dup 1) | |
7428 | (match_operand:TDSI 2 "register_operand" "") | |
7429 | (match_operand:TDSI 3 "register_operand" "")] | |
7430 | UNSPECV_CAS)) | |
7431 | (set (reg:CCZ1 CC_REGNUM) | |
7432 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
7433 | "") | |
e0374221 | 7434 | |
3093f076 AS |
7435 | (define_expand "sync_compare_and_swap<mode>" |
7436 | [(parallel | |
7437 | [(set (match_operand:HQI 0 "register_operand" "") | |
7438 | (match_operand:HQI 1 "memory_operand" "")) | |
7439 | (set (match_dup 1) | |
7440 | (unspec_volatile:HQI | |
7441 | [(match_dup 1) | |
7442 | (match_operand:HQI 2 "general_operand" "") | |
7443 | (match_operand:HQI 3 "general_operand" "")] | |
7444 | UNSPECV_CAS)) | |
7445 | (set (reg:CCZ1 CC_REGNUM) | |
7446 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
7447 | "" | |
7448 | "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], | |
7449 | operands[2], operands[3]); DONE;") | |
7450 | ||
e0374221 AS |
7451 | (define_expand "sync_compare_and_swap_cc<mode>" |
7452 | [(parallel | |
8006eaa6 AS |
7453 | [(set (match_operand:TDSI 0 "register_operand" "") |
7454 | (match_operand:TDSI 1 "memory_operand" "")) | |
e0374221 | 7455 | (set (match_dup 1) |
8006eaa6 | 7456 | (unspec_volatile:TDSI |
e0374221 | 7457 | [(match_dup 1) |
8006eaa6 AS |
7458 | (match_operand:TDSI 2 "register_operand" "") |
7459 | (match_operand:TDSI 3 "register_operand" "")] | |
e0374221 AS |
7460 | UNSPECV_CAS)) |
7461 | (set (match_dup 4) | |
69950452 | 7462 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] |
e0374221 AS |
7463 | "" |
7464 | { | |
8006eaa6 | 7465 | /* Emulate compare. */ |
69950452 | 7466 | operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
e0374221 AS |
7467 | s390_compare_op0 = operands[1]; |
7468 | s390_compare_op1 = operands[2]; | |
7469 | s390_compare_emitted = operands[4]; | |
7470 | }) | |
7471 | ||
43a09b63 | 7472 | ; cds, cdsg |
8006eaa6 AS |
7473 | (define_insn "*sync_compare_and_swap<mode>" |
7474 | [(set (match_operand:DP 0 "register_operand" "=r") | |
7475 | (match_operand:DP 1 "memory_operand" "+Q")) | |
7476 | (set (match_dup 1) | |
7477 | (unspec_volatile:DP | |
7478 | [(match_dup 1) | |
7479 | (match_operand:DP 2 "register_operand" "0") | |
7480 | (match_operand:DP 3 "register_operand" "r")] | |
7481 | UNSPECV_CAS)) | |
7482 | (set (reg:CCZ1 CC_REGNUM) | |
7483 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
7484 | "" | |
7485 | "cds<tg>\t%0,%3,%S1" | |
7486 | [(set_attr "op_type" "RS<TE>") | |
7487 | (set_attr "type" "sem")]) | |
7488 | ||
43a09b63 | 7489 | ; cs, csg |
8006eaa6 | 7490 | (define_insn "*sync_compare_and_swap<mode>" |
e0374221 AS |
7491 | [(set (match_operand:GPR 0 "register_operand" "=r") |
7492 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
7493 | (set (match_dup 1) | |
7494 | (unspec_volatile:GPR | |
7495 | [(match_dup 1) | |
7496 | (match_operand:GPR 2 "register_operand" "0") | |
7497 | (match_operand:GPR 3 "register_operand" "r")] | |
7498 | UNSPECV_CAS)) | |
69950452 AS |
7499 | (set (reg:CCZ1 CC_REGNUM) |
7500 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
e0374221 AS |
7501 | "" |
7502 | "cs<g>\t%0,%3,%S1" | |
7503 | [(set_attr "op_type" "RS<E>") | |
7504 | (set_attr "type" "sem")]) | |
7505 | ||
7506 | ||
45d18331 AS |
7507 | ; |
7508 | ; Other atomic instruction patterns. | |
7509 | ; | |
7510 | ||
7511 | (define_expand "sync_lock_test_and_set<mode>" | |
7512 | [(match_operand:HQI 0 "register_operand") | |
7513 | (match_operand:HQI 1 "memory_operand") | |
7514 | (match_operand:HQI 2 "general_operand")] | |
7515 | "" | |
7516 | "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
7517 | operands[2], false); DONE;") | |
7518 | ||
7519 | (define_expand "sync_<atomic><mode>" | |
7520 | [(set (match_operand:HQI 0 "memory_operand") | |
7521 | (ATOMIC:HQI (match_dup 0) | |
7522 | (match_operand:HQI 1 "general_operand")))] | |
7523 | "" | |
7524 | "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
7525 | operands[1], false); DONE;") | |
7526 | ||
7527 | (define_expand "sync_old_<atomic><mode>" | |
7528 | [(set (match_operand:HQI 0 "register_operand") | |
7529 | (match_operand:HQI 1 "memory_operand")) | |
7530 | (set (match_dup 1) | |
7531 | (ATOMIC:HQI (match_dup 1) | |
7532 | (match_operand:HQI 2 "general_operand")))] | |
7533 | "" | |
7534 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
7535 | operands[2], false); DONE;") | |
7536 | ||
7537 | (define_expand "sync_new_<atomic><mode>" | |
7538 | [(set (match_operand:HQI 0 "register_operand") | |
7539 | (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") | |
7540 | (match_operand:HQI 2 "general_operand"))) | |
7541 | (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] | |
7542 | "" | |
7543 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
7544 | operands[2], true); DONE;") | |
7545 | ||
9db1d521 HP |
7546 | ;; |
7547 | ;;- Miscellaneous instructions. | |
7548 | ;; | |
7549 | ||
7550 | ; | |
7551 | ; allocate stack instruction pattern(s). | |
7552 | ; | |
7553 | ||
7554 | (define_expand "allocate_stack" | |
ef44a6ff UW |
7555 | [(match_operand 0 "general_operand" "") |
7556 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 7557 | "TARGET_BACKCHAIN" |
9db1d521 | 7558 | { |
ef44a6ff | 7559 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 7560 | |
ef44a6ff UW |
7561 | emit_move_insn (temp, s390_back_chain_rtx ()); |
7562 | anti_adjust_stack (operands[1]); | |
7563 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 7564 | |
ef44a6ff UW |
7565 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
7566 | DONE; | |
10bbf137 | 7567 | }) |
9db1d521 HP |
7568 | |
7569 | ||
7570 | ; | |
43ab026f | 7571 | ; setjmp instruction pattern. |
9db1d521 HP |
7572 | ; |
7573 | ||
9db1d521 | 7574 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7575 | [(match_operand 0 "" "")] |
f314b9b1 | 7576 | "flag_pic" |
9db1d521 | 7577 | { |
585539a1 | 7578 | emit_insn (s390_load_got ()); |
fd7643fb | 7579 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
9db1d521 | 7580 | DONE; |
fd7643fb | 7581 | }) |
9db1d521 | 7582 | |
9db1d521 HP |
7583 | ;; These patterns say how to save and restore the stack pointer. We need not |
7584 | ;; save the stack pointer at function level since we are careful to | |
7585 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7586 | ;; when we restore the stack pointer. | |
7587 | ;; | |
7588 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7589 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7590 | ;; save area is a memory location. | |
7591 | ||
7592 | (define_expand "save_stack_function" | |
7593 | [(match_operand 0 "general_operand" "") | |
7594 | (match_operand 1 "general_operand" "")] | |
7595 | "" | |
7596 | "DONE;") | |
7597 | ||
7598 | (define_expand "restore_stack_function" | |
7599 | [(match_operand 0 "general_operand" "") | |
7600 | (match_operand 1 "general_operand" "")] | |
7601 | "" | |
7602 | "DONE;") | |
7603 | ||
7604 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
7605 | [(match_operand 0 "register_operand" "") |
7606 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 7607 | "TARGET_BACKCHAIN" |
9db1d521 | 7608 | { |
ef44a6ff UW |
7609 | rtx temp = gen_reg_rtx (Pmode); |
7610 | ||
7611 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
7612 | emit_move_insn (operands[0], operands[1]); | |
7613 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7614 | ||
7615 | DONE; | |
10bbf137 | 7616 | }) |
9db1d521 HP |
7617 | |
7618 | (define_expand "save_stack_nonlocal" | |
7619 | [(match_operand 0 "memory_operand" "") | |
7620 | (match_operand 1 "register_operand" "")] | |
7621 | "" | |
9db1d521 | 7622 | { |
ef44a6ff UW |
7623 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
7624 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
7625 | ||
7626 | /* Copy the backchain to the first word, sp to the second and the | |
7627 | literal pool base to the third. */ | |
7628 | ||
b3d31392 | 7629 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7630 | { |
7631 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
7632 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
7633 | } | |
7634 | ||
7635 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
7636 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 7637 | |
9db1d521 | 7638 | DONE; |
10bbf137 | 7639 | }) |
9db1d521 HP |
7640 | |
7641 | (define_expand "restore_stack_nonlocal" | |
7642 | [(match_operand 0 "register_operand" "") | |
7643 | (match_operand 1 "memory_operand" "")] | |
7644 | "" | |
9db1d521 | 7645 | { |
ef44a6ff | 7646 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 7647 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 7648 | rtx temp = NULL_RTX; |
9db1d521 | 7649 | |
43ab026f | 7650 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 7651 | literal pool base from the third. */ |
43ab026f | 7652 | |
b3d31392 | 7653 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7654 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
7655 | ||
7656 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
7657 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
7658 | ||
7659 | if (temp) | |
7660 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7661 | ||
7662 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
9db1d521 | 7663 | DONE; |
10bbf137 | 7664 | }) |
9db1d521 | 7665 | |
7bcebb25 AK |
7666 | (define_expand "exception_receiver" |
7667 | [(const_int 0)] | |
7668 | "" | |
7669 | { | |
7670 | s390_set_has_landing_pad_p (true); | |
7671 | DONE; | |
7672 | }) | |
9db1d521 HP |
7673 | |
7674 | ; | |
7675 | ; nop instruction pattern(s). | |
7676 | ; | |
7677 | ||
7678 | (define_insn "nop" | |
7679 | [(const_int 0)] | |
7680 | "" | |
d40c829f | 7681 | "lr\t0,0" |
9db1d521 HP |
7682 | [(set_attr "op_type" "RR")]) |
7683 | ||
7684 | ||
7685 | ; | |
7686 | ; Special literal pool access instruction pattern(s). | |
7687 | ; | |
7688 | ||
416cf582 UW |
7689 | (define_insn "*pool_entry" |
7690 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7691 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7692 | "" |
9db1d521 | 7693 | { |
416cf582 UW |
7694 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7695 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 7696 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
7697 | return ""; |
7698 | } | |
b628bd8e | 7699 | [(set (attr "length") |
416cf582 | 7700 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 7701 | |
9bb86f41 UW |
7702 | (define_insn "pool_align" |
7703 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
7704 | UNSPECV_POOL_ALIGN)] | |
7705 | "" | |
7706 | ".align\t%0" | |
b628bd8e | 7707 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 7708 | |
9bb86f41 UW |
7709 | (define_insn "pool_section_start" |
7710 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
7711 | "" | |
7712 | ".section\t.rodata" | |
b628bd8e | 7713 | [(set_attr "length" "0")]) |
b2ccb744 | 7714 | |
9bb86f41 UW |
7715 | (define_insn "pool_section_end" |
7716 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
7717 | "" | |
b2ccb744 | 7718 | ".previous" |
b628bd8e | 7719 | [(set_attr "length" "0")]) |
b2ccb744 | 7720 | |
5af2f3d3 | 7721 | (define_insn "main_base_31_small" |
9e8327e3 UW |
7722 | [(set (match_operand 0 "register_operand" "=a") |
7723 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7724 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7725 | "basr\t%0,0" |
7726 | [(set_attr "op_type" "RR") | |
7727 | (set_attr "type" "la")]) | |
7728 | ||
7729 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
7730 | [(set (match_operand 0 "register_operand" "=a") |
7731 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 7732 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 7733 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
7734 | "bras\t%0,%2" |
7735 | [(set_attr "op_type" "RI")]) | |
7736 | ||
7737 | (define_insn "main_base_64" | |
9e8327e3 UW |
7738 | [(set (match_operand 0 "register_operand" "=a") |
7739 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7740 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7741 | "larl\t%0,%1" |
7742 | [(set_attr "op_type" "RIL") | |
7743 | (set_attr "type" "larl")]) | |
7744 | ||
7745 | (define_insn "main_pool" | |
585539a1 UW |
7746 | [(set (match_operand 0 "register_operand" "=a") |
7747 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
7748 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
7749 | { |
7750 | gcc_unreachable (); | |
7751 | } | |
b628bd8e | 7752 | [(set (attr "type") |
ea77e738 UW |
7753 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
7754 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 7755 | |
aee4e0db | 7756 | (define_insn "reload_base_31" |
9e8327e3 UW |
7757 | [(set (match_operand 0 "register_operand" "=a") |
7758 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7759 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7760 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
7761 | [(set_attr "length" "6") |
7762 | (set_attr "type" "la")]) | |
b2ccb744 | 7763 | |
aee4e0db | 7764 | (define_insn "reload_base_64" |
9e8327e3 UW |
7765 | [(set (match_operand 0 "register_operand" "=a") |
7766 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7767 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7768 | "larl\t%0,%1" |
aee4e0db | 7769 | [(set_attr "op_type" "RIL") |
077dab3b | 7770 | (set_attr "type" "larl")]) |
aee4e0db | 7771 | |
aee4e0db | 7772 | (define_insn "pool" |
fd7643fb | 7773 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 7774 | "" |
8d933e31 AS |
7775 | { |
7776 | gcc_unreachable (); | |
7777 | } | |
b628bd8e | 7778 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 7779 | |
4023fb28 UW |
7780 | ;; |
7781 | ;; Insns related to generating the function prologue and epilogue. | |
7782 | ;; | |
7783 | ||
7784 | ||
7785 | (define_expand "prologue" | |
7786 | [(use (const_int 0))] | |
7787 | "" | |
10bbf137 | 7788 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
7789 | |
7790 | (define_expand "epilogue" | |
7791 | [(use (const_int 1))] | |
7792 | "" | |
ed9676cf AK |
7793 | "s390_emit_epilogue (false); DONE;") |
7794 | ||
7795 | (define_expand "sibcall_epilogue" | |
7796 | [(use (const_int 0))] | |
7797 | "" | |
7798 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 7799 | |
9e8327e3 | 7800 | (define_insn "*return" |
4023fb28 | 7801 | [(return) |
9e8327e3 UW |
7802 | (use (match_operand 0 "register_operand" "a"))] |
7803 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7804 | "br\t%0" |
4023fb28 | 7805 | [(set_attr "op_type" "RR") |
c7453384 | 7806 | (set_attr "type" "jsr") |
077dab3b | 7807 | (set_attr "atype" "agen")]) |
4023fb28 | 7808 | |
4023fb28 | 7809 | |
c7453384 | 7810 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 7811 | ;; pointer. This is used for compatibility. |
c7453384 EC |
7812 | |
7813 | (define_expand "ptr_extend" | |
7814 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7815 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7816 | "TARGET_64BIT" |
c7453384 | 7817 | { |
c7453384 EC |
7818 | emit_insn (gen_anddi3 (operands[0], |
7819 | gen_lowpart (DImode, operands[1]), | |
7820 | GEN_INT (0x7fffffff))); | |
c7453384 | 7821 | DONE; |
10bbf137 | 7822 | }) |
4798630c D |
7823 | |
7824 | ;; Instruction definition to expand eh_return macro to support | |
7825 | ;; swapping in special linkage return addresses. | |
7826 | ||
7827 | (define_expand "eh_return" | |
7828 | [(use (match_operand 0 "register_operand" ""))] | |
7829 | "TARGET_TPF" | |
7830 | { | |
7831 | s390_emit_tpf_eh_return (operands[0]); | |
7832 | DONE; | |
7833 | }) | |
7834 | ||
7b8acc34 AK |
7835 | ; |
7836 | ; Stack Protector Patterns | |
7837 | ; | |
7838 | ||
7839 | (define_expand "stack_protect_set" | |
7840 | [(set (match_operand 0 "memory_operand" "") | |
7841 | (match_operand 1 "memory_operand" ""))] | |
7842 | "" | |
7843 | { | |
7844 | #ifdef TARGET_THREAD_SSP_OFFSET | |
7845 | operands[1] | |
7846 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
7847 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
7848 | #endif | |
7849 | if (TARGET_64BIT) | |
7850 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
7851 | else | |
7852 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
7853 | ||
7854 | DONE; | |
7855 | }) | |
7856 | ||
7857 | (define_insn "stack_protect_set<mode>" | |
7858 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
7859 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
7860 | "" | |
7861 | "mvc\t%O0(%G0,%R0),%S1" | |
7862 | [(set_attr "op_type" "SS")]) | |
7863 | ||
7864 | (define_expand "stack_protect_test" | |
7865 | [(set (reg:CC CC_REGNUM) | |
7866 | (compare (match_operand 0 "memory_operand" "") | |
7867 | (match_operand 1 "memory_operand" ""))) | |
7868 | (match_operand 2 "" "")] | |
7869 | "" | |
7870 | { | |
7871 | #ifdef TARGET_THREAD_SSP_OFFSET | |
7872 | operands[1] | |
7873 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
7874 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
7875 | #endif | |
7876 | s390_compare_op0 = operands[0]; | |
7877 | s390_compare_op1 = operands[1]; | |
7878 | s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM); | |
7879 | ||
7880 | if (TARGET_64BIT) | |
7881 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
7882 | else | |
7883 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
7884 | ||
7885 | emit_jump_insn (gen_beq (operands[2])); | |
7886 | ||
7887 | DONE; | |
7888 | }) | |
7889 | ||
7890 | (define_insn "stack_protect_test<mode>" | |
7891 | [(set (reg:CCZ CC_REGNUM) | |
7892 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
7893 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
7894 | "" | |
7895 | "clc\t%O0(%G0,%R0),%S1" | |
7896 | [(set_attr "op_type" "SS")]) |