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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
d1e082c2 | 2 | ;; Copyright (C) 1999-2013 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
10bbf137 | 73 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
74 | UNSPEC_LTREL_OFFSET |
75 | UNSPEC_LTREL_BASE | |
76 | UNSPEC_POOL_OFFSET | |
77 | UNSPEC_GOTENT | |
78 | UNSPEC_GOT | |
79 | UNSPEC_GOTOFF | |
80 | UNSPEC_PLT | |
81 | UNSPEC_PLTOFF | |
fd7643fb UW |
82 | |
83 | ; Literal pool | |
30a49b23 AK |
84 | UNSPEC_RELOAD_BASE |
85 | UNSPEC_MAIN_BASE | |
86 | UNSPEC_LTREF | |
87 | UNSPEC_INSN | |
88 | UNSPEC_EXECUTE | |
fd7643fb | 89 | |
1a8c13b3 | 90 | ; Atomic Support |
30a49b23 | 91 | UNSPEC_MB |
78ce265b | 92 | UNSPEC_MOVA |
1a8c13b3 | 93 | |
fd7643fb | 94 | ; TLS relocation specifiers |
30a49b23 AK |
95 | UNSPEC_TLSGD |
96 | UNSPEC_TLSLDM | |
97 | UNSPEC_NTPOFF | |
98 | UNSPEC_DTPOFF | |
99 | UNSPEC_GOTNTPOFF | |
100 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
101 | |
102 | ; TLS support | |
30a49b23 AK |
103 | UNSPEC_TLSLDM_NTPOFF |
104 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
105 | |
106 | ; String Functions | |
30a49b23 AK |
107 | UNSPEC_SRST |
108 | UNSPEC_MVST | |
638e37c2 | 109 | |
7b8acc34 | 110 | ; Stack Smashing Protector |
30a49b23 AK |
111 | UNSPEC_SP_SET |
112 | UNSPEC_SP_TEST | |
85dae55a | 113 | |
638e37c2 | 114 | ; Test Data Class (TDC) |
30a49b23 | 115 | UNSPEC_TDC_INSN |
65b1d8ea AK |
116 | |
117 | ; Population Count | |
30a49b23 AK |
118 | UNSPEC_POPCNT |
119 | UNSPEC_COPYSIGN | |
fd3cd001 UW |
120 | ]) |
121 | ||
122 | ;; | |
123 | ;; UNSPEC_VOLATILE usage | |
124 | ;; | |
125 | ||
30a49b23 AK |
126 | (define_c_enum "unspecv" [ |
127 | ; Blockage | |
128 | UNSPECV_BLOCKAGE | |
10bbf137 | 129 | |
2f7e5a0d | 130 | ; TPF Support |
30a49b23 AK |
131 | UNSPECV_TPF_PROLOGUE |
132 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 133 | |
10bbf137 | 134 | ; Literal pool |
30a49b23 AK |
135 | UNSPECV_POOL |
136 | UNSPECV_POOL_SECTION | |
137 | UNSPECV_POOL_ALIGN | |
138 | UNSPECV_POOL_ENTRY | |
139 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
140 | |
141 | ; TLS support | |
30a49b23 | 142 | UNSPECV_SET_TP |
e0374221 AS |
143 | |
144 | ; Atomic Support | |
30a49b23 AK |
145 | UNSPECV_CAS |
146 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 AK |
147 | |
148 | ; Transactional Execution support | |
149 | UNSPECV_TBEGIN | |
150 | UNSPECV_TBEGINC | |
151 | UNSPECV_TEND | |
152 | UNSPECV_TABORT | |
153 | UNSPECV_ETND | |
154 | UNSPECV_NTSTG | |
155 | UNSPECV_PPA | |
fd3cd001 UW |
156 | ]) |
157 | ||
ae156f85 AS |
158 | ;; |
159 | ;; Registers | |
160 | ;; | |
161 | ||
35dd9a0e AK |
162 | ; Registers with special meaning |
163 | ||
ae156f85 AS |
164 | (define_constants |
165 | [ | |
166 | ; Sibling call register. | |
167 | (SIBCALL_REGNUM 1) | |
168 | ; Literal pool base register. | |
169 | (BASE_REGNUM 13) | |
170 | ; Return address register. | |
171 | (RETURN_REGNUM 14) | |
172 | ; Condition code register. | |
173 | (CC_REGNUM 33) | |
f4aa3848 | 174 | ; Thread local storage pointer register. |
ae156f85 AS |
175 | (TP_REGNUM 36) |
176 | ]) | |
177 | ||
35dd9a0e AK |
178 | ; Hardware register names |
179 | ||
180 | (define_constants | |
181 | [ | |
182 | ; General purpose registers | |
183 | (GPR0_REGNUM 0) | |
184 | ; Floating point registers. | |
185 | (FPR0_REGNUM 16) | |
186 | (FPR2_REGNUM 18) | |
187 | ]) | |
188 | ||
189 | ;; | |
190 | ;; PFPO GPR0 argument format | |
191 | ;; | |
192 | ||
193 | (define_constants | |
194 | [ | |
195 | ; PFPO operation type | |
196 | (PFPO_CONVERT 0x1000000) | |
197 | ; PFPO operand types | |
198 | (PFPO_OP_TYPE_SF 0x5) | |
199 | (PFPO_OP_TYPE_DF 0x6) | |
200 | (PFPO_OP_TYPE_TF 0x7) | |
201 | (PFPO_OP_TYPE_SD 0x8) | |
202 | (PFPO_OP_TYPE_DD 0x9) | |
203 | (PFPO_OP_TYPE_TD 0xa) | |
204 | ; Bitposition of operand types | |
205 | (PFPO_OP0_TYPE_SHIFT 16) | |
206 | (PFPO_OP1_TYPE_SHIFT 8) | |
207 | ]) | |
208 | ||
5a3fe9b6 AK |
209 | ; Immediate operands for tbegin and tbeginc |
210 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
211 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 212 | |
29a74354 UW |
213 | ;; Instruction operand type as used in the Principles of Operation. |
214 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 215 | |
29a74354 | 216 | (define_attr "op_type" |
963fc8d0 | 217 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" |
b628bd8e | 218 | (const_string "NN")) |
9db1d521 | 219 | |
29a74354 | 220 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 221 | |
077dab3b | 222 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 223 | cs,vs,store,sem,idiv, |
ed0e512a | 224 | imulhi,imulsi,imuldi, |
2cdece44 | 225 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
226 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
227 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 228 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 229 | fmadddf,fmaddsf, |
9381e3f1 WG |
230 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
231 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
232 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
233 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
234 | ftoidfp, other" | |
29a74354 UW |
235 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
236 | (eq_attr "op_type" "SS") (const_string "cs")] | |
237 | (const_string "integer"))) | |
9db1d521 | 238 | |
29a74354 UW |
239 | ;; Another attribute used for scheduling purposes: |
240 | ;; agen: Instruction uses the address generation unit | |
241 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
242 | |
243 | (define_attr "atype" "agen,reg" | |
c68e7b86 | 244 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") |
0101708c AS |
245 | (const_string "reg") |
246 | (const_string "agen"))) | |
9db1d521 | 247 | |
9381e3f1 WG |
248 | ;; Properties concerning Z10 execution grouping and value forwarding. |
249 | ;; z10_super: instruction is superscalar. | |
250 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
251 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
252 | ;; target register. It can forward this value to a second instruction that reads | |
253 | ;; the same register if that second instruction is issued in the same group. | |
254 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
255 | ;; instruction in the S pipe writes to the register, then the T instruction | |
256 | ;; can immediately read the new value. | |
257 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
258 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
259 | ;; |
260 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
261 | ||
262 | ||
263 | (define_attr "z10prop" "none, | |
264 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
265 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
266 | z10_rec, | |
267 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 268 | z10_c" |
9381e3f1 WG |
269 | (const_string "none")) |
270 | ||
65b1d8ea AK |
271 | ;; Properties concerning Z196 decoding |
272 | ;; z196_alone: must group alone | |
273 | ;; z196_end: ends a group | |
274 | ;; z196_cracked: instruction is cracked or expanded | |
275 | (define_attr "z196prop" "none, | |
276 | z196_alone, z196_ends, | |
277 | z196_cracked" | |
278 | (const_string "none")) | |
9381e3f1 | 279 | |
22ac2c2f AK |
280 | (define_attr "mnemonic" "unknown" (const_string "unknown")) |
281 | ||
9db1d521 HP |
282 | ;; Length in bytes. |
283 | ||
284 | (define_attr "length" "" | |
963fc8d0 AK |
285 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
286 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 287 | (const_int 6))) |
9db1d521 | 288 | |
29a74354 UW |
289 | |
290 | ;; Processor type. This attribute must exactly match the processor_type | |
291 | ;; enumeration in s390.h. The current machine description does not | |
292 | ;; distinguish between g5 and g6, but there are differences between the two | |
293 | ;; CPUs could in theory be modeled. | |
294 | ||
22ac2c2f | 295 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12" |
90c6fd8a | 296 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 297 | |
b5e0425c AK |
298 | (define_attr "cpu_facility" |
299 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12" | |
3af8e996 AK |
300 | (const_string "standard")) |
301 | ||
302 | (define_attr "enabled" "" | |
303 | (cond [(eq_attr "cpu_facility" "standard") | |
304 | (const_int 1) | |
305 | ||
306 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 307 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
308 | (const_int 1) |
309 | ||
310 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 311 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
312 | (const_int 1) |
313 | ||
314 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 315 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
316 | (const_int 1) |
317 | ||
318 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 319 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
320 | (const_int 1) |
321 | ||
322 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 323 | (match_test "TARGET_DFP")) |
93538e8e AK |
324 | (const_int 1) |
325 | ||
b5e0425c AK |
326 | (and (eq_attr "cpu_facility" "cpu_zarch") |
327 | (match_test "TARGET_CPU_ZARCH")) | |
328 | (const_int 1) | |
329 | ||
93538e8e | 330 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 331 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
332 | (const_int 1) |
333 | ||
334 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 335 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
336 | (const_int 1) |
337 | ||
338 | (and (eq_attr "cpu_facility" "zEC12") | |
339 | (match_test "TARGET_ZEC12")) | |
3af8e996 AK |
340 | (const_int 1)] |
341 | (const_int 0))) | |
342 | ||
29a74354 UW |
343 | ;; Pipeline description for z900. For lack of anything better, |
344 | ;; this description is also used for the g5 and g6. | |
345 | (include "2064.md") | |
346 | ||
3443392a | 347 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
348 | (include "2084.md") |
349 | ||
9381e3f1 WG |
350 | ;; Pipeline description for z10 |
351 | (include "2097.md") | |
352 | ||
65b1d8ea AK |
353 | ;; Pipeline description for z196 |
354 | (include "2817.md") | |
355 | ||
22ac2c2f AK |
356 | ;; Pipeline description for zEC12 |
357 | (include "2827.md") | |
358 | ||
0bfc3f69 AS |
359 | ;; Predicates |
360 | (include "predicates.md") | |
361 | ||
cd8dc1f9 WG |
362 | ;; Constraint definitions |
363 | (include "constraints.md") | |
364 | ||
a8ba31f2 EC |
365 | ;; Other includes |
366 | (include "tpf.md") | |
f52c81dd | 367 | |
3abcb3a7 | 368 | ;; Iterators |
f52c81dd | 369 | |
3abcb3a7 | 370 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 371 | ;; same template. |
f4aa3848 | 372 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 373 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 | 374 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
963fc8d0 | 375 | (define_mode_iterator FPALL [TF DF SF TD DD SD]) |
3abcb3a7 HPN |
376 | (define_mode_iterator BFP [TF DF SF]) |
377 | (define_mode_iterator DFP [TD DD]) | |
378 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
379 | (define_mode_iterator DSF [DF SF]) | |
380 | (define_mode_iterator SD_SF [SF SD]) | |
381 | (define_mode_iterator DD_DF [DF DD]) | |
382 | (define_mode_iterator TD_TF [TF TD]) | |
383 | ||
3abcb3a7 | 384 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 385 | ;; from the same template. |
9602b6a1 | 386 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 387 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 388 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 389 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 390 | |
3abcb3a7 | 391 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 392 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 393 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 394 | |
78ce265b RH |
395 | ;; These macros refer to the actual word_mode of the configuration. |
396 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
397 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
398 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
399 | ||
6e0d70c9 AK |
400 | ;; Used by the umul pattern to express modes having half the size. |
401 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
402 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
403 | ||
3abcb3a7 | 404 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 405 | ;; the same template. |
3abcb3a7 | 406 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 407 | |
3abcb3a7 | 408 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 409 | ;; same template. |
9602b6a1 | 410 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
963fc8d0 | 411 | (define_mode_iterator INTALL [TI DI SI HI QI]) |
78ce265b | 412 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
342cf42b | 413 | |
3abcb3a7 | 414 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 415 | ;; the same template. |
3abcb3a7 | 416 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 417 | |
571e408a RH |
418 | ;; This iterator allow r[ox]sbg to be defined with the same template |
419 | (define_code_iterator IXOR [ior xor]) | |
420 | ||
3abcb3a7 HPN |
421 | ;; This iterator and attribute allow to combine most atomic operations. |
422 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 423 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
f4aa3848 | 424 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") |
45d18331 | 425 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 426 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 427 | |
f4aa3848 | 428 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
429 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
430 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 431 | |
f4aa3848 AK |
432 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
433 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
434 | ;; SDmode. |
435 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 436 | |
609e7e80 | 437 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
438 | ;; Likewise for "<RXe>". |
439 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
440 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
441 | ||
609e7e80 | 442 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 443 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
444 | ;; dfp variants in a single insn definition. |
445 | ||
3abcb3a7 | 446 | ;; This attribute is used to set op_type accordingly. |
f4aa3848 | 447 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
609e7e80 AK |
448 | (DD "RRR") (SD "RRR")]) |
449 | ||
f4aa3848 | 450 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
451 | ;; first and the second operand match for bfp modes. |
452 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
453 | ||
f4aa3848 | 454 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
455 | ;; additional operand for the dfp instructions. |
456 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
457 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
458 | ||
f5905b37 | 459 | |
85dae55a AK |
460 | ;; This attribute is used in the operand constraint list |
461 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
462 | ;; TFmode values are represented by a fp register pair. Since the | |
463 | ;; sign bit instructions only handle single source and target fp registers | |
464 | ;; these instructions can only be used for TFmode values if the source and | |
465 | ;; target operand uses the same fp register. | |
466 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
467 | ||
609e7e80 AK |
468 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
469 | ;; This is used to disable the memory alternative in TFmode patterns. | |
470 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
471 | ||
3abcb3a7 | 472 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
473 | ;; within instruction mnemonics. |
474 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
475 | ||
0387c142 WG |
476 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
477 | ;; modes and to an empty string for bfp modes. | |
478 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
479 | ||
1b48c8cc AS |
480 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
481 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
482 | ;; version only operates on one register. | |
483 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
484 | ||
485 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
486 | ;; version only operates on one register. The DImode version needs an additional | |
487 | ;; register for the assembler output. | |
488 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
489 | |
490 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
491 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
492 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
493 | ||
494 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 495 | ;; pattern itself and the corresponding function calls. |
f337b930 | 496 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
497 | |
498 | ;; This attribute handles differences in the instruction 'type' and will result | |
499 | ;; in "RRE" for DImode and "RR" for SImode. | |
500 | (define_mode_attr E [(DI "E") (SI "")]) | |
501 | ||
3298c037 AK |
502 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
503 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
504 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
505 | ||
8006eaa6 AS |
506 | ;; This attribute handles differences in the instruction 'type' and will result |
507 | ;; in "RSE" for TImode and "RS" for DImode. | |
508 | (define_mode_attr TE [(TI "E") (DI "")]) | |
509 | ||
9a91a21f AS |
510 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
511 | ;; and "lcr" in SImode. | |
512 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 513 | |
3298c037 AK |
514 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
515 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
516 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
517 | ;; variant for long displacements. | |
518 | (define_mode_attr y [(DI "g") (SI "y")]) | |
519 | ||
9602b6a1 | 520 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
521 | ;; and "cds" in DImode. |
522 | (define_mode_attr tg [(TI "g") (DI "")]) | |
523 | ||
78ce265b RH |
524 | ;; In TDI templates, a string like "c<d>sg". |
525 | (define_mode_attr td [(TI "d") (DI "")]) | |
526 | ||
2f8f8434 AS |
527 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
528 | ;; and "cfdbr" in SImode. | |
529 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
530 | ||
65b1d8ea AK |
531 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
532 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
533 | ;; 3 operands shift instructions into the existing patterns. | |
534 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
535 | ||
f52c81dd AS |
536 | ;; ICM mask required to load MODE value into the lowest subreg |
537 | ;; of a SImode register. | |
538 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
539 | ||
f6ee577c AS |
540 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
541 | ;; HImode and "llgc" in QImode. | |
542 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
543 | ||
a1aed706 AS |
544 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
545 | ;; in SImode. | |
546 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
547 | ||
609e7e80 AK |
548 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
549 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
550 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
551 | ||
f52c81dd AS |
552 | ;; Maximum unsigned integer that fits in MODE. |
553 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
554 | ||
75ca1b39 RH |
555 | ;; Start and end field computations for RISBG et al. |
556 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
557 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
558 | ||
2542ef05 RH |
559 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
560 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
561 | ||
9db1d521 HP |
562 | ;; |
563 | ;;- Compare instructions. | |
564 | ;; | |
565 | ||
07893d4f | 566 | ; Test-under-Mask instructions |
9db1d521 | 567 | |
07893d4f | 568 | (define_insn "*tmqi_mem" |
ae156f85 | 569 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
570 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
571 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
572 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 573 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 574 | "@ |
fc0ea003 UW |
575 | tm\t%S0,%b1 |
576 | tmy\t%S0,%b1" | |
9381e3f1 WG |
577 | [(set_attr "op_type" "SI,SIY") |
578 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 579 | |
05b9aaaa | 580 | (define_insn "*tmdi_reg" |
ae156f85 | 581 | [(set (reg CC_REGNUM) |
f19a9af7 | 582 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 583 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
584 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
585 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 586 | "TARGET_ZARCH |
3ed99cc9 | 587 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
588 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
589 | "@ | |
590 | tmhh\t%0,%i1 | |
591 | tmhl\t%0,%i1 | |
592 | tmlh\t%0,%i1 | |
593 | tmll\t%0,%i1" | |
9381e3f1 WG |
594 | [(set_attr "op_type" "RI") |
595 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
596 | |
597 | (define_insn "*tmsi_reg" | |
ae156f85 | 598 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
599 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
600 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
601 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 602 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
603 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
604 | "@ | |
605 | tmh\t%0,%i1 | |
606 | tml\t%0,%i1" | |
729e750f WG |
607 | [(set_attr "op_type" "RI") |
608 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 609 | |
f52c81dd | 610 | (define_insn "*tm<mode>_full" |
ae156f85 | 611 | [(set (reg CC_REGNUM) |
f52c81dd AS |
612 | (compare (match_operand:HQI 0 "register_operand" "d") |
613 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 614 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 615 | "tml\t%0,<max_uint>" |
729e750f WG |
616 | [(set_attr "op_type" "RI") |
617 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 618 | |
07893d4f | 619 | |
08a5aaa2 | 620 | ; |
07893d4f | 621 | ; Load-and-Test instructions |
08a5aaa2 AS |
622 | ; |
623 | ||
c0220ea4 | 624 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
625 | |
626 | (define_insn "*tstdi_sign" | |
ae156f85 | 627 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
628 | (compare |
629 | (ashiftrt:DI | |
630 | (ashift:DI | |
631 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
632 | (const_int 32)) (const_int 32)) | |
633 | (match_operand:DI 1 "const0_operand" ""))) | |
634 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 635 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 636 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
637 | "ltgfr\t%2,%0 |
638 | ltgf\t%2,%0" | |
639 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
640 | (set_attr "cpu_facility" "*,z10") |
641 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 642 | |
43a09b63 | 643 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 644 | (define_insn "*tst<mode>_extimm" |
ec24698e | 645 | [(set (reg CC_REGNUM) |
fb492564 | 646 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
647 | (match_operand:GPR 1 "const0_operand" ""))) |
648 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 649 | (match_dup 0))] |
08a5aaa2 | 650 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 651 | "@ |
08a5aaa2 AS |
652 | lt<g>r\t%2,%0 |
653 | lt<g>\t%2,%0" | |
9381e3f1 | 654 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 655 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 656 | |
43a09b63 | 657 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 658 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 659 | [(set (reg CC_REGNUM) |
fb492564 | 660 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
661 | (match_operand:GPR 1 "const0_operand" ""))) |
662 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
663 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 664 | "@ |
08a5aaa2 AS |
665 | lt<g>r\t%0,%0 |
666 | lt<g>\t%2,%0" | |
9381e3f1 | 667 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 668 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 669 | |
07893d4f | 670 | (define_insn "*tstdi" |
ae156f85 | 671 | [(set (reg CC_REGNUM) |
07893d4f UW |
672 | (compare (match_operand:DI 0 "register_operand" "d") |
673 | (match_operand:DI 1 "const0_operand" ""))) | |
674 | (set (match_operand:DI 2 "register_operand" "=d") | |
675 | (match_dup 0))] | |
9602b6a1 | 676 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 677 | "ltgr\t%2,%0" |
9381e3f1 WG |
678 | [(set_attr "op_type" "RRE") |
679 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 680 | |
07893d4f | 681 | (define_insn "*tstsi" |
ae156f85 | 682 | [(set (reg CC_REGNUM) |
d3632d41 | 683 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 684 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 685 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 686 | (match_dup 0))] |
ec24698e | 687 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 688 | "@ |
d40c829f | 689 | ltr\t%2,%0 |
fc0ea003 UW |
690 | icm\t%2,15,%S0 |
691 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
692 | [(set_attr "op_type" "RR,RS,RSY") |
693 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 694 | |
07893d4f | 695 | (define_insn "*tstsi_cconly" |
ae156f85 | 696 | [(set (reg CC_REGNUM) |
d3632d41 | 697 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 698 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 699 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
700 | "s390_match_ccmode(insn, CCSmode)" |
701 | "@ | |
d40c829f | 702 | ltr\t%0,%0 |
fc0ea003 UW |
703 | icm\t%2,15,%S0 |
704 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
705 | [(set_attr "op_type" "RR,RS,RSY") |
706 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 707 | |
08a5aaa2 AS |
708 | (define_insn "*tstdi_cconly_31" |
709 | [(set (reg CC_REGNUM) | |
710 | (compare (match_operand:DI 0 "register_operand" "d") | |
711 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 712 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
713 | "srda\t%0,0" |
714 | [(set_attr "op_type" "RS") | |
715 | (set_attr "atype" "reg")]) | |
716 | ||
43a09b63 | 717 | ; ltr, ltgr |
08a5aaa2 | 718 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 719 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
720 | (compare (match_operand:GPR 0 "register_operand" "d") |
721 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 722 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 723 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
724 | [(set_attr "op_type" "RR<E>") |
725 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 726 | |
c0220ea4 | 727 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 728 | |
f52c81dd | 729 | (define_insn "*tst<mode>CCT" |
ae156f85 | 730 | [(set (reg CC_REGNUM) |
f52c81dd AS |
731 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
732 | (match_operand:HQI 1 "const0_operand" ""))) | |
733 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
734 | (match_dup 0))] |
735 | "s390_match_ccmode(insn, CCTmode)" | |
736 | "@ | |
f52c81dd AS |
737 | icm\t%2,<icm_lo>,%S0 |
738 | icmy\t%2,<icm_lo>,%S0 | |
739 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
740 | [(set_attr "op_type" "RS,RSY,RI") |
741 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
742 | |
743 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 744 | [(set (reg CC_REGNUM) |
d3632d41 | 745 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 746 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 747 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
748 | "s390_match_ccmode(insn, CCTmode)" |
749 | "@ | |
fc0ea003 UW |
750 | icm\t%2,3,%S0 |
751 | icmy\t%2,3,%S0 | |
d40c829f | 752 | tml\t%0,65535" |
9381e3f1 WG |
753 | [(set_attr "op_type" "RS,RSY,RI") |
754 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 755 | |
3af97654 | 756 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 757 | [(set (reg CC_REGNUM) |
d3632d41 | 758 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
759 | (match_operand:QI 1 "const0_operand" "")))] |
760 | "s390_match_ccmode(insn, CCTmode)" | |
761 | "@ | |
fc0ea003 UW |
762 | cli\t%S0,0 |
763 | cliy\t%S0,0 | |
d40c829f | 764 | tml\t%0,255" |
9381e3f1 | 765 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 766 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 767 | |
f52c81dd | 768 | (define_insn "*tst<mode>" |
ae156f85 | 769 | [(set (reg CC_REGNUM) |
f52c81dd AS |
770 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
771 | (match_operand:HQI 1 "const0_operand" ""))) | |
772 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
773 | (match_dup 0))] |
774 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 775 | "@ |
f52c81dd AS |
776 | icm\t%2,<icm_lo>,%S0 |
777 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
778 | [(set_attr "op_type" "RS,RSY") |
779 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 780 | |
f52c81dd | 781 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 782 | [(set (reg CC_REGNUM) |
f52c81dd AS |
783 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
784 | (match_operand:HQI 1 "const0_operand" ""))) | |
785 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 786 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 787 | "@ |
f52c81dd AS |
788 | icm\t%2,<icm_lo>,%S0 |
789 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
790 | [(set_attr "op_type" "RS,RSY") |
791 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 792 | |
9db1d521 | 793 | |
575f7c2b UW |
794 | ; Compare (equality) instructions |
795 | ||
796 | (define_insn "*cmpdi_cct" | |
ae156f85 | 797 | [(set (reg CC_REGNUM) |
ec24698e | 798 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 799 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 800 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
801 | "@ |
802 | cgr\t%0,%1 | |
f4f41b4e | 803 | cghi\t%0,%h1 |
ec24698e | 804 | cgfi\t%0,%1 |
575f7c2b | 805 | cg\t%0,%1 |
19b63d8e | 806 | #" |
9381e3f1 WG |
807 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
808 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
809 | |
810 | (define_insn "*cmpsi_cct" | |
ae156f85 | 811 | [(set (reg CC_REGNUM) |
ec24698e UW |
812 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
813 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 814 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
815 | "@ |
816 | cr\t%0,%1 | |
f4f41b4e | 817 | chi\t%0,%h1 |
ec24698e | 818 | cfi\t%0,%1 |
575f7c2b UW |
819 | c\t%0,%1 |
820 | cy\t%0,%1 | |
19b63d8e | 821 | #" |
9381e3f1 | 822 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 823 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 824 | |
07893d4f | 825 | ; Compare (signed) instructions |
4023fb28 | 826 | |
07893d4f | 827 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 828 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
829 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
830 | "d,RT,b")) | |
831 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 832 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 833 | "@ |
d40c829f | 834 | cgfr\t%0,%1 |
963fc8d0 AK |
835 | cgf\t%0,%1 |
836 | cgfrl\t%0,%1" | |
837 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 838 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 839 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 840 | |
9381e3f1 WG |
841 | |
842 | ||
07893d4f | 843 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 844 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
845 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
846 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 847 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 848 | "@ |
d40c829f | 849 | ch\t%0,%1 |
963fc8d0 AK |
850 | chy\t%0,%1 |
851 | chrl\t%0,%1" | |
852 | [(set_attr "op_type" "RX,RXY,RIL") | |
853 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
854 | (set_attr "type" "*,*,larl") |
855 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
856 | |
857 | (define_insn "*cmphi_ccs_z10" | |
858 | [(set (reg CC_REGNUM) | |
859 | (compare (match_operand:HI 0 "s_operand" "Q") | |
860 | (match_operand:HI 1 "immediate_operand" "K")))] | |
861 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
862 | "chhsi\t%0,%1" | |
65b1d8ea AK |
863 | [(set_attr "op_type" "SIL") |
864 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
865 | |
866 | (define_insn "*cmpdi_ccs_signhi_rl" | |
867 | [(set (reg CC_REGNUM) | |
868 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
869 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
870 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
871 | "@ | |
872 | cgh\t%0,%1 | |
873 | cghrl\t%0,%1" | |
874 | [(set_attr "op_type" "RXY,RIL") | |
875 | (set_attr "type" "*,larl")]) | |
4023fb28 | 876 | |
963fc8d0 | 877 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 878 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 879 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
880 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
881 | "d,d,Q, d,d,d,d") | |
882 | (match_operand:GPR 1 "general_operand" | |
883 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 884 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 885 | "@ |
3298c037 AK |
886 | c<g>r\t%0,%1 |
887 | c<g>hi\t%0,%h1 | |
963fc8d0 | 888 | c<g>hsi\t%0,%h1 |
3298c037 AK |
889 | c<g>fi\t%0,%1 |
890 | c<g>\t%0,%1 | |
963fc8d0 AK |
891 | c<y>\t%0,%1 |
892 | c<g>rl\t%0,%1" | |
893 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
894 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
895 | (set_attr "type" "*,*,*,*,*,*,larl") |
896 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 897 | |
07893d4f UW |
898 | |
899 | ; Compare (unsigned) instructions | |
9db1d521 | 900 | |
963fc8d0 AK |
901 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
902 | [(set (reg CC_REGNUM) | |
903 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
904 | "larl_operand" "X"))) | |
905 | (match_operand:SI 0 "register_operand" "d")))] | |
906 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
907 | "clhrl\t%0,%1" | |
908 | [(set_attr "op_type" "RIL") | |
729e750f WG |
909 | (set_attr "type" "larl") |
910 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
911 | |
912 | ; clhrl, clghrl | |
913 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
914 | [(set (reg CC_REGNUM) | |
915 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
916 | "larl_operand" "X"))) | |
917 | (match_operand:GPR 0 "register_operand" "d")))] | |
918 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
919 | "cl<g>hrl\t%0,%1" | |
920 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
921 | (set_attr "type" "larl") |
922 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 923 | |
07893d4f | 924 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 925 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
926 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
927 | "d,RT,b")) | |
928 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 929 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 930 | "@ |
d40c829f | 931 | clgfr\t%0,%1 |
963fc8d0 AK |
932 | clgf\t%0,%1 |
933 | clgfrl\t%0,%1" | |
934 | [(set_attr "op_type" "RRE,RXY,RIL") | |
935 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
936 | (set_attr "type" "*,*,larl") |
937 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 938 | |
07893d4f | 939 | (define_insn "*cmpdi_ccu" |
ae156f85 | 940 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
941 | (compare (match_operand:DI 0 "nonimmediate_operand" |
942 | "d, d,d,Q, d, Q,BQ") | |
943 | (match_operand:DI 1 "general_operand" | |
944 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 945 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 946 | "@ |
d40c829f | 947 | clgr\t%0,%1 |
ec24698e | 948 | clgfi\t%0,%1 |
963fc8d0 AK |
949 | clgrl\t%0,%1 |
950 | clghsi\t%0,%x1 | |
575f7c2b | 951 | clg\t%0,%1 |
e221ef54 | 952 | # |
19b63d8e | 953 | #" |
963fc8d0 AK |
954 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
955 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
956 | (set_attr "type" "*,*,larl,*,*,*,*") |
957 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 958 | |
07893d4f | 959 | (define_insn "*cmpsi_ccu" |
ae156f85 | 960 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
961 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
962 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 963 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 964 | "@ |
d40c829f | 965 | clr\t%0,%1 |
ec24698e | 966 | clfi\t%0,%o1 |
963fc8d0 AK |
967 | clrl\t%0,%1 |
968 | clfhsi\t%0,%x1 | |
d40c829f | 969 | cl\t%0,%1 |
575f7c2b | 970 | cly\t%0,%1 |
e221ef54 | 971 | # |
19b63d8e | 972 | #" |
963fc8d0 AK |
973 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
974 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
975 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
976 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 977 | |
07893d4f | 978 | (define_insn "*cmphi_ccu" |
ae156f85 | 979 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
980 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
981 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 982 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 983 | && !register_operand (operands[1], HImode)" |
d3632d41 | 984 | "@ |
fc0ea003 UW |
985 | clm\t%0,3,%S1 |
986 | clmy\t%0,3,%S1 | |
963fc8d0 | 987 | clhhsi\t%0,%1 |
e221ef54 | 988 | # |
19b63d8e | 989 | #" |
963fc8d0 | 990 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
991 | (set_attr "cpu_facility" "*,*,z10,*,*") |
992 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
993 | |
994 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 995 | [(set (reg CC_REGNUM) |
e221ef54 UW |
996 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
997 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 998 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 999 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1000 | "@ |
fc0ea003 UW |
1001 | clm\t%0,1,%S1 |
1002 | clmy\t%0,1,%S1 | |
1003 | cli\t%S0,%b1 | |
1004 | cliy\t%S0,%b1 | |
e221ef54 | 1005 | # |
19b63d8e | 1006 | #" |
9381e3f1 WG |
1007 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
1008 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
1009 | |
1010 | ||
19b63d8e UW |
1011 | ; Block compare (CLC) instruction patterns. |
1012 | ||
1013 | (define_insn "*clc" | |
ae156f85 | 1014 | [(set (reg CC_REGNUM) |
d4f52f0e | 1015 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1016 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1017 | (use (match_operand 2 "const_int_operand" "n"))] | |
1018 | "s390_match_ccmode (insn, CCUmode) | |
1019 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1020 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1021 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1022 | |
1023 | (define_split | |
ae156f85 | 1024 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1025 | (compare (match_operand 0 "memory_operand" "") |
1026 | (match_operand 1 "memory_operand" "")))] | |
1027 | "reload_completed | |
1028 | && s390_match_ccmode (insn, CCUmode) | |
1029 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1030 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1031 | [(parallel | |
1032 | [(set (match_dup 0) (match_dup 1)) | |
1033 | (use (match_dup 2))])] | |
1034 | { | |
1035 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1036 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1037 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1038 | ||
1039 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1040 | operands[0], operands[1]); | |
1041 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1042 | }) | |
1043 | ||
1044 | ||
609e7e80 | 1045 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1046 | |
609e7e80 | 1047 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1048 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1049 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1050 | (compare (match_operand:FP 0 "register_operand" "f") |
1051 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1052 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1053 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1054 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1055 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1056 | |
be5de7a1 | 1057 | ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb |
f5905b37 | 1058 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1059 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1060 | (compare (match_operand:FP 0 "register_operand" "f,f") |
1061 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 1062 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1063 | "@ |
609e7e80 | 1064 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1065 | c<xde>b\t%0,%1" |
077dab3b | 1066 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 1067 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1068 | |
963fc8d0 AK |
1069 | |
1070 | ; Compare and Branch instructions | |
1071 | ||
1072 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1073 | ; The following instructions do a complementary access of their second |
1074 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1075 | (define_insn "*cmp_and_br_signed_<mode>" |
1076 | [(set (pc) | |
1077 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1078 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1079 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1080 | (label_ref (match_operand 3 "" "")) | |
1081 | (pc))) | |
1082 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1083 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1084 | { |
1085 | if (get_attr_length (insn) == 6) | |
1086 | return which_alternative ? | |
1087 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1088 | else | |
1089 | return which_alternative ? | |
1090 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1091 | } | |
1092 | [(set_attr "op_type" "RIE") | |
1093 | (set_attr "type" "branch") | |
e3cba5e5 | 1094 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1095 | (set (attr "length") |
1096 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1097 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1098 | ; 10 byte for cgr/jg | |
1099 | ||
1100 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1101 | ; The following instructions do a complementary access of their second |
1102 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1103 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1104 | [(set (pc) | |
1105 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1106 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1107 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1108 | (label_ref (match_operand 3 "" "")) | |
1109 | (pc))) | |
1110 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1111 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1112 | { |
1113 | if (get_attr_length (insn) == 6) | |
1114 | return which_alternative ? | |
1115 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1116 | else | |
1117 | return which_alternative ? | |
1118 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1119 | } | |
1120 | [(set_attr "op_type" "RIE") | |
1121 | (set_attr "type" "branch") | |
e3cba5e5 | 1122 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1123 | (set (attr "length") |
1124 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1125 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1126 | ; 10 byte for clgr/jg | |
1127 | ||
b0f86a7e AK |
1128 | ; And now the same two patterns as above but with a negated CC mask. |
1129 | ||
1130 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1131 | ; The following instructions do a complementary access of their second | |
1132 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1133 | (define_insn "*icmp_and_br_signed_<mode>" | |
1134 | [(set (pc) | |
1135 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1136 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1137 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1138 | (pc) | |
1139 | (label_ref (match_operand 3 "" "")))) | |
1140 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1141 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1142 | { |
1143 | if (get_attr_length (insn) == 6) | |
1144 | return which_alternative ? | |
1145 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1146 | else | |
1147 | return which_alternative ? | |
1148 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1149 | } | |
1150 | [(set_attr "op_type" "RIE") | |
1151 | (set_attr "type" "branch") | |
1152 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1153 | (set (attr "length") | |
1154 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1155 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1156 | ; 10 byte for cgr/jg | |
1157 | ||
1158 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1159 | ; The following instructions do a complementary access of their second | |
1160 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1161 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1162 | [(set (pc) | |
1163 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1164 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1165 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1166 | (pc) | |
1167 | (label_ref (match_operand 3 "" "")))) | |
1168 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1169 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1170 | { |
1171 | if (get_attr_length (insn) == 6) | |
1172 | return which_alternative ? | |
1173 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1174 | else | |
1175 | return which_alternative ? | |
1176 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1177 | } | |
1178 | [(set_attr "op_type" "RIE") | |
1179 | (set_attr "type" "branch") | |
1180 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1181 | (set (attr "length") | |
1182 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1183 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1184 | ; 10 byte for clgr/jg | |
1185 | ||
9db1d521 HP |
1186 | ;; |
1187 | ;;- Move instructions. | |
1188 | ;; | |
1189 | ||
1190 | ; | |
1191 | ; movti instruction pattern(s). | |
1192 | ; | |
1193 | ||
1194 | (define_insn "movti" | |
f2dc2f86 AK |
1195 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") |
1196 | (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] | |
9602b6a1 | 1197 | "TARGET_ZARCH" |
4023fb28 | 1198 | "@ |
fc0ea003 UW |
1199 | lmg\t%0,%N0,%S1 |
1200 | stmg\t%1,%N1,%S0 | |
4023fb28 | 1201 | # |
19b63d8e | 1202 | #" |
f2dc2f86 AK |
1203 | [(set_attr "op_type" "RSY,RSY,*,*") |
1204 | (set_attr "type" "lm,stm,*,*")]) | |
4023fb28 UW |
1205 | |
1206 | (define_split | |
1207 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1208 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1209 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1210 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1211 | [(set (match_dup 2) (match_dup 4)) |
1212 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1213 | { |
dc65c307 UW |
1214 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1215 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1216 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1217 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1218 | }) | |
1219 | ||
1220 | (define_split | |
1221 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1222 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1223 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1224 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1225 | [(set (match_dup 2) (match_dup 4)) | |
1226 | (set (match_dup 3) (match_dup 5))] | |
1227 | { | |
1228 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1229 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1230 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1231 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1232 | }) | |
4023fb28 UW |
1233 | |
1234 | (define_split | |
1235 | [(set (match_operand:TI 0 "register_operand" "") | |
1236 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1237 | "TARGET_ZARCH && reload_completed |
4023fb28 | 1238 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1239 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1240 | { |
1241 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1242 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1243 | s390_load_address (addr, XEXP (operands[1], 0)); |
1244 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1245 | }) |
1246 | ||
833cd70a AK |
1247 | |
1248 | ; | |
1249 | ; Patterns used for secondary reloads | |
1250 | ; | |
1251 | ||
963fc8d0 AK |
1252 | ; z10 provides move instructions accepting larl memory operands. |
1253 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1254 | ; These patterns are also used for unaligned SI and DI accesses. | |
1255 | ||
1256 | (define_expand "reload<INTALL:mode><P:mode>_tomem_z10" | |
1257 | [(parallel [(match_operand:INTALL 0 "memory_operand" "") | |
1258 | (match_operand:INTALL 1 "register_operand" "=d") | |
1259 | (match_operand:P 2 "register_operand" "=&a")])] | |
1260 | "TARGET_Z10" | |
1261 | { | |
1262 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1263 | DONE; | |
1264 | }) | |
1265 | ||
1266 | (define_expand "reload<INTALL:mode><P:mode>_toreg_z10" | |
1267 | [(parallel [(match_operand:INTALL 0 "register_operand" "=d") | |
1268 | (match_operand:INTALL 1 "memory_operand" "") | |
1269 | (match_operand:P 2 "register_operand" "=a")])] | |
1270 | "TARGET_Z10" | |
1271 | { | |
1272 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1273 | DONE; | |
1274 | }) | |
1275 | ||
1276 | (define_expand "reload<FPALL:mode><P:mode>_tomem_z10" | |
1277 | [(parallel [(match_operand:FPALL 0 "memory_operand" "") | |
1278 | (match_operand:FPALL 1 "register_operand" "=d") | |
1279 | (match_operand:P 2 "register_operand" "=&a")])] | |
1280 | "TARGET_Z10" | |
1281 | { | |
1282 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1283 | DONE; | |
1284 | }) | |
1285 | ||
1286 | (define_expand "reload<FPALL:mode><P:mode>_toreg_z10" | |
1287 | [(parallel [(match_operand:FPALL 0 "register_operand" "=d") | |
1288 | (match_operand:FPALL 1 "memory_operand" "") | |
1289 | (match_operand:P 2 "register_operand" "=a")])] | |
1290 | "TARGET_Z10" | |
1291 | { | |
1292 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1293 | DONE; | |
1294 | }) | |
1295 | ||
1296 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1297 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1298 | (match_operand:P 1 "larl_operand" "") | |
1299 | (match_operand:P 2 "register_operand" "=a")])] | |
1300 | "TARGET_Z10" | |
1301 | { | |
1302 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1303 | DONE; | |
1304 | }) | |
1305 | ||
833cd70a AK |
1306 | ; Handles loading a PLUS (load address) expression |
1307 | ||
1308 | (define_expand "reload<mode>_plus" | |
1309 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1310 | (match_operand:P 1 "s390_plus_operand" "") | |
1311 | (match_operand:P 2 "register_operand" "=&a")])] | |
1312 | "" | |
1313 | { | |
1314 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1315 | DONE; | |
1316 | }) | |
1317 | ||
1318 | ; Handles assessing a non-offsetable memory address | |
1319 | ||
1320 | (define_expand "reload<mode>_nonoffmem_in" | |
1321 | [(parallel [(match_operand 0 "register_operand" "") | |
1322 | (match_operand 1 "" "") | |
1323 | (match_operand:P 2 "register_operand" "=&a")])] | |
1324 | "" | |
1325 | { | |
1326 | gcc_assert (MEM_P (operands[1])); | |
1327 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1328 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1329 | emit_move_insn (operands[0], operands[1]); | |
1330 | DONE; | |
1331 | }) | |
1332 | ||
1333 | (define_expand "reload<mode>_nonoffmem_out" | |
1334 | [(parallel [(match_operand 0 "" "") | |
1335 | (match_operand 1 "register_operand" "") | |
1336 | (match_operand:P 2 "register_operand" "=&a")])] | |
1337 | "" | |
dc65c307 | 1338 | { |
9c3c3dcc | 1339 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1340 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1341 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1342 | emit_move_insn (operands[0], operands[1]); | |
1343 | DONE; | |
1344 | }) | |
9db1d521 | 1345 | |
1f9e1fc6 AK |
1346 | (define_expand "reload<mode>_PIC_addr" |
1347 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1348 | (match_operand 1 "larl_operand" "") | |
1349 | (match_operand:P 2 "register_operand" "=a")])] | |
1350 | "" | |
1351 | { | |
0a2aaacc KG |
1352 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1353 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1354 | }) |
1355 | ||
9db1d521 HP |
1356 | ; |
1357 | ; movdi instruction pattern(s). | |
1358 | ; | |
1359 | ||
9db1d521 HP |
1360 | (define_expand "movdi" |
1361 | [(set (match_operand:DI 0 "general_operand" "") | |
1362 | (match_operand:DI 1 "general_operand" ""))] | |
1363 | "" | |
9db1d521 | 1364 | { |
fd3cd001 | 1365 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1366 | if (TARGET_64BIT |
1367 | && (SYMBOLIC_CONST (operands[1]) | |
1368 | || (GET_CODE (operands[1]) == PLUS | |
1369 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1370 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1371 | emit_symbolic_move (operands); |
10bbf137 | 1372 | }) |
9db1d521 | 1373 | |
4023fb28 UW |
1374 | (define_insn "*movdi_larl" |
1375 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1376 | (match_operand:DI 1 "larl_operand" "X"))] | |
1377 | "TARGET_64BIT | |
8e509cf9 | 1378 | && !FP_REG_P (operands[0])" |
d40c829f | 1379 | "larl\t%0,%1" |
4023fb28 | 1380 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1381 | (set_attr "type" "larl") |
1382 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1383 | |
3af8e996 | 1384 | (define_insn "*movdi_64" |
85dae55a | 1385 | [(set (match_operand:DI 0 "nonimmediate_operand" |
963fc8d0 | 1386 | "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, |
f2dc2f86 | 1387 | RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") |
85dae55a | 1388 | (match_operand:DI 1 "general_operand" |
963fc8d0 | 1389 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, |
f2dc2f86 | 1390 | d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] |
9602b6a1 | 1391 | "TARGET_ZARCH" |
85dae55a AK |
1392 | "@ |
1393 | lghi\t%0,%h1 | |
1394 | llihh\t%0,%i1 | |
1395 | llihl\t%0,%i1 | |
1396 | llilh\t%0,%i1 | |
1397 | llill\t%0,%i1 | |
1398 | lgfi\t%0,%1 | |
1399 | llihf\t%0,%k1 | |
1400 | llilf\t%0,%k1 | |
1401 | ldgr\t%0,%1 | |
1402 | lgdr\t%0,%1 | |
1403 | lay\t%0,%a1 | |
963fc8d0 | 1404 | lgrl\t%0,%1 |
85dae55a AK |
1405 | lgr\t%0,%1 |
1406 | lg\t%0,%1 | |
1407 | stg\t%1,%0 | |
1408 | ldr\t%0,%1 | |
1409 | ld\t%0,%1 | |
1410 | ldy\t%0,%1 | |
1411 | std\t%1,%0 | |
1412 | stdy\t%1,%0 | |
963fc8d0 AK |
1413 | stgrl\t%1,%0 |
1414 | mvghi\t%0,%1 | |
85dae55a AK |
1415 | # |
1416 | # | |
1417 | stam\t%1,%N1,%S0 | |
f2dc2f86 | 1418 | lam\t%0,%N0,%S1" |
963fc8d0 | 1419 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
f2dc2f86 | 1420 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS") |
963fc8d0 AK |
1421 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
1422 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, | |
f2dc2f86 | 1423 | *,*") |
3af8e996 | 1424 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1425 | z10,*,*,*,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1426 | z10,z10,*,*,*,*") |
9381e3f1 WG |
1427 | (set_attr "z10prop" "z10_fwd_A1, |
1428 | z10_fwd_E1, | |
1429 | z10_fwd_E1, | |
1430 | z10_fwd_E1, | |
1431 | z10_fwd_E1, | |
1432 | z10_fwd_A1, | |
1433 | z10_fwd_E1, | |
1434 | z10_fwd_E1, | |
1435 | *, | |
1436 | *, | |
1437 | z10_fwd_A1, | |
1438 | z10_fwd_A3, | |
1439 | z10_fr_E1, | |
1440 | z10_fwd_A3, | |
1441 | z10_rec, | |
1442 | *, | |
1443 | *, | |
1444 | *, | |
1445 | *, | |
1446 | *, | |
1447 | z10_rec, | |
1448 | z10_super, | |
1449 | *, | |
1450 | *, | |
1451 | *, | |
9381e3f1 WG |
1452 | *") |
1453 | ]) | |
c5aa1d12 UW |
1454 | |
1455 | (define_split | |
1456 | [(set (match_operand:DI 0 "register_operand" "") | |
1457 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1458 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1459 | [(set (match_dup 2) (match_dup 3)) |
1460 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1461 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1462 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1463 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1464 | ||
1465 | (define_split | |
1466 | [(set (match_operand:DI 0 "register_operand" "") | |
1467 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1468 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1469 | && dead_or_set_p (insn, operands[1])" |
1470 | [(set (match_dup 3) (match_dup 2)) | |
1471 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1472 | (set (match_dup 4) (match_dup 2))] | |
1473 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1474 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1475 | ||
1476 | (define_split | |
1477 | [(set (match_operand:DI 0 "register_operand" "") | |
1478 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1479 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1480 | && !dead_or_set_p (insn, operands[1])" |
1481 | [(set (match_dup 3) (match_dup 2)) | |
1482 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1483 | (set (match_dup 4) (match_dup 2)) | |
1484 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1485 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1486 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1487 | |
1488 | (define_insn "*movdi_31" | |
963fc8d0 | 1489 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1490 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1491 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1492 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1493 | "!TARGET_ZARCH" |
4023fb28 | 1494 | "@ |
fc0ea003 | 1495 | lm\t%0,%N0,%S1 |
c4d50129 | 1496 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1497 | stm\t%1,%N1,%S0 |
c4d50129 | 1498 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1499 | # |
1500 | # | |
d40c829f UW |
1501 | ldr\t%0,%1 |
1502 | ld\t%0,%1 | |
1503 | ldy\t%0,%1 | |
1504 | std\t%1,%0 | |
1505 | stdy\t%1,%0 | |
19b63d8e | 1506 | #" |
f2dc2f86 AK |
1507 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1508 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1509 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1510 | |
1511 | ; For a load from a symbol ref we can use one of the target registers | |
1512 | ; together with larl to load the address. | |
1513 | (define_split | |
1514 | [(set (match_operand:DI 0 "register_operand" "") | |
1515 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1516 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1517 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1518 | [(set (match_dup 2) (match_dup 3)) | |
1519 | (set (match_dup 0) (match_dup 1))] | |
1520 | { | |
1521 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1522 | operands[3] = XEXP (operands[1], 0); | |
1523 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1524 | }) | |
4023fb28 UW |
1525 | |
1526 | (define_split | |
1527 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1528 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1529 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1530 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1531 | [(set (match_dup 2) (match_dup 4)) |
1532 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1533 | { |
dc65c307 UW |
1534 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1535 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1536 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1537 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1538 | }) | |
1539 | ||
1540 | (define_split | |
1541 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1542 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1543 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1544 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1545 | [(set (match_dup 2) (match_dup 4)) | |
1546 | (set (match_dup 3) (match_dup 5))] | |
1547 | { | |
1548 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1549 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1550 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1551 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1552 | }) | |
9db1d521 | 1553 | |
4023fb28 UW |
1554 | (define_split |
1555 | [(set (match_operand:DI 0 "register_operand" "") | |
1556 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1557 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1558 | && !FP_REG_P (operands[0]) |
4023fb28 | 1559 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1560 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1561 | { |
1562 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1563 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1564 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1565 | }) |
1566 | ||
84817c5d UW |
1567 | (define_peephole2 |
1568 | [(set (match_operand:DI 0 "register_operand" "") | |
1569 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1570 | "TARGET_ZARCH |
84817c5d UW |
1571 | && !FP_REG_P (operands[0]) |
1572 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1573 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1574 | && get_pool_mode (operands[1]) == DImode | |
1575 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1576 | [(set (match_dup 0) (match_dup 2))] | |
1577 | "operands[2] = get_pool_constant (operands[1]);") | |
1578 | ||
7bdff56f UW |
1579 | (define_insn "*la_64" |
1580 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1581 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1582 | "TARGET_64BIT" |
1583 | "@ | |
1584 | la\t%0,%a1 | |
1585 | lay\t%0,%a1" | |
1586 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1587 | (set_attr "type" "la") |
1588 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1589 | |
1590 | (define_peephole2 | |
1591 | [(parallel | |
1592 | [(set (match_operand:DI 0 "register_operand" "") | |
1593 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1594 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1595 | "TARGET_64BIT |
e1d5ee28 | 1596 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1597 | [(set (match_dup 0) (match_dup 1))] |
1598 | "") | |
1599 | ||
1600 | (define_peephole2 | |
1601 | [(set (match_operand:DI 0 "register_operand" "") | |
1602 | (match_operand:DI 1 "register_operand" "")) | |
1603 | (parallel | |
1604 | [(set (match_dup 0) | |
1605 | (plus:DI (match_dup 0) | |
1606 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1607 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1608 | "TARGET_64BIT |
1609 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1610 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1611 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1612 | "") | |
1613 | ||
9db1d521 HP |
1614 | ; |
1615 | ; movsi instruction pattern(s). | |
1616 | ; | |
1617 | ||
9db1d521 HP |
1618 | (define_expand "movsi" |
1619 | [(set (match_operand:SI 0 "general_operand" "") | |
1620 | (match_operand:SI 1 "general_operand" ""))] | |
1621 | "" | |
9db1d521 | 1622 | { |
fd3cd001 | 1623 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1624 | if (!TARGET_64BIT |
1625 | && (SYMBOLIC_CONST (operands[1]) | |
1626 | || (GET_CODE (operands[1]) == PLUS | |
1627 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1628 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1629 | emit_symbolic_move (operands); |
10bbf137 | 1630 | }) |
9db1d521 | 1631 | |
9e8327e3 UW |
1632 | (define_insn "*movsi_larl" |
1633 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1634 | (match_operand:SI 1 "larl_operand" "X"))] | |
1635 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1636 | && !FP_REG_P (operands[0])" | |
1637 | "larl\t%0,%1" | |
1638 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1639 | (set_attr "type" "larl") |
729e750f | 1640 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1641 | |
f19a9af7 | 1642 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1643 | [(set (match_operand:SI 0 "nonimmediate_operand" |
f2dc2f86 | 1644 | "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t") |
2f7e5a0d | 1645 | (match_operand:SI 1 "general_operand" |
f2dc2f86 | 1646 | "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))] |
f19a9af7 | 1647 | "TARGET_ZARCH" |
9db1d521 | 1648 | "@ |
f19a9af7 AK |
1649 | lhi\t%0,%h1 |
1650 | llilh\t%0,%i1 | |
1651 | llill\t%0,%i1 | |
ec24698e | 1652 | iilf\t%0,%o1 |
f19a9af7 | 1653 | lay\t%0,%a1 |
963fc8d0 | 1654 | lrl\t%0,%1 |
d40c829f UW |
1655 | lr\t%0,%1 |
1656 | l\t%0,%1 | |
1657 | ly\t%0,%1 | |
1658 | st\t%1,%0 | |
1659 | sty\t%1,%0 | |
1660 | ler\t%0,%1 | |
1661 | le\t%0,%1 | |
1662 | ley\t%0,%1 | |
1663 | ste\t%1,%0 | |
1664 | stey\t%1,%0 | |
c5aa1d12 UW |
1665 | ear\t%0,%1 |
1666 | sar\t%0,%1 | |
1667 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1668 | strl\t%1,%0 |
1669 | mvhi\t%0,%1 | |
f2dc2f86 | 1670 | lam\t%0,%0,%S1" |
963fc8d0 | 1671 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
f2dc2f86 | 1672 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS") |
9381e3f1 WG |
1673 | (set_attr "type" "*, |
1674 | *, | |
1675 | *, | |
1676 | *, | |
1677 | la, | |
1678 | larl, | |
1679 | lr, | |
1680 | load, | |
1681 | load, | |
1682 | store, | |
1683 | store, | |
1684 | floadsf, | |
1685 | floadsf, | |
1686 | floadsf, | |
1687 | fstoresf, | |
1688 | fstoresf, | |
1689 | *, | |
1690 | *, | |
1691 | *, | |
1692 | larl, | |
1693 | *, | |
9381e3f1 | 1694 | *") |
963fc8d0 | 1695 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1696 | *,*,longdisp,*,longdisp,*,*,*,z10,z10,*") |
9381e3f1 WG |
1697 | (set_attr "z10prop" "z10_fwd_A1, |
1698 | z10_fwd_E1, | |
1699 | z10_fwd_E1, | |
1700 | z10_fwd_A1, | |
1701 | z10_fwd_A1, | |
1702 | z10_fwd_A3, | |
1703 | z10_fr_E1, | |
1704 | z10_fwd_A3, | |
1705 | z10_fwd_A3, | |
729e750f | 1706 | z10_rec, |
9381e3f1 WG |
1707 | z10_rec, |
1708 | *, | |
1709 | *, | |
1710 | *, | |
1711 | *, | |
1712 | *, | |
1713 | z10_super_E1, | |
1714 | z10_super, | |
1715 | *, | |
1716 | z10_rec, | |
1717 | z10_super, | |
9381e3f1 | 1718 | *")]) |
f19a9af7 AK |
1719 | |
1720 | (define_insn "*movsi_esa" | |
f2dc2f86 AK |
1721 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t") |
1722 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1723 | "!TARGET_ZARCH" |
1724 | "@ | |
1725 | lhi\t%0,%h1 | |
1726 | lr\t%0,%1 | |
1727 | l\t%0,%1 | |
1728 | st\t%1,%0 | |
1729 | ler\t%0,%1 | |
1730 | le\t%0,%1 | |
1731 | ste\t%1,%0 | |
c5aa1d12 UW |
1732 | ear\t%0,%1 |
1733 | sar\t%0,%1 | |
1734 | stam\t%1,%1,%S0 | |
f2dc2f86 AK |
1735 | lam\t%0,%0,%S1" |
1736 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS") | |
1737 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*") | |
9381e3f1 WG |
1738 | (set_attr "z10prop" "z10_fwd_A1, |
1739 | z10_fr_E1, | |
1740 | z10_fwd_A3, | |
729e750f | 1741 | z10_rec, |
9381e3f1 WG |
1742 | *, |
1743 | *, | |
1744 | *, | |
1745 | z10_super_E1, | |
1746 | z10_super, | |
1747 | *, | |
9381e3f1 WG |
1748 | *") |
1749 | ]) | |
9db1d521 | 1750 | |
84817c5d UW |
1751 | (define_peephole2 |
1752 | [(set (match_operand:SI 0 "register_operand" "") | |
1753 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1754 | "!FP_REG_P (operands[0]) | |
1755 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1756 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1757 | && get_pool_mode (operands[1]) == SImode | |
1758 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1759 | [(set (match_dup 0) (match_dup 2))] | |
1760 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1761 | |
7bdff56f UW |
1762 | (define_insn "*la_31" |
1763 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1764 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1765 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1766 | "@ | |
1767 | la\t%0,%a1 | |
1768 | lay\t%0,%a1" | |
1769 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1770 | (set_attr "type" "la") |
1771 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1772 | |
1773 | (define_peephole2 | |
1774 | [(parallel | |
1775 | [(set (match_operand:SI 0 "register_operand" "") | |
1776 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1777 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1778 | "!TARGET_64BIT |
e1d5ee28 | 1779 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1780 | [(set (match_dup 0) (match_dup 1))] |
1781 | "") | |
1782 | ||
1783 | (define_peephole2 | |
1784 | [(set (match_operand:SI 0 "register_operand" "") | |
1785 | (match_operand:SI 1 "register_operand" "")) | |
1786 | (parallel | |
1787 | [(set (match_dup 0) | |
1788 | (plus:SI (match_dup 0) | |
1789 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1790 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1791 | "!TARGET_64BIT |
1792 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1793 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1794 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1795 | "") | |
1796 | ||
1797 | (define_insn "*la_31_and" | |
1798 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1799 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
1800 | (const_int 2147483647)))] |
1801 | "!TARGET_64BIT" | |
1802 | "@ | |
1803 | la\t%0,%a1 | |
1804 | lay\t%0,%a1" | |
1805 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1806 | (set_attr "type" "la") |
1807 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1808 | |
1809 | (define_insn_and_split "*la_31_and_cc" | |
1810 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1811 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1812 | (const_int 2147483647))) | |
ae156f85 | 1813 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1814 | "!TARGET_64BIT" |
1815 | "#" | |
1816 | "&& reload_completed" | |
1817 | [(set (match_dup 0) | |
1818 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1819 | "" | |
1820 | [(set_attr "op_type" "RX") | |
1821 | (set_attr "type" "la")]) | |
1822 | ||
1823 | (define_insn "force_la_31" | |
1824 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1825 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
1826 | (use (const_int 0))] |
1827 | "!TARGET_64BIT" | |
1828 | "@ | |
1829 | la\t%0,%a1 | |
1830 | lay\t%0,%a1" | |
1831 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
1832 | (set_attr "type" "la") |
1833 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 1834 | |
9db1d521 HP |
1835 | ; |
1836 | ; movhi instruction pattern(s). | |
1837 | ; | |
1838 | ||
02ed3c5e UW |
1839 | (define_expand "movhi" |
1840 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1841 | (match_operand:HI 1 "general_operand" ""))] | |
1842 | "" | |
1843 | { | |
2f7e5a0d | 1844 | /* Make it explicit that loading a register from memory |
02ed3c5e | 1845 | always sign-extends (at least) to SImode. */ |
b3a13419 | 1846 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 1847 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1848 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1849 | { |
1850 | rtx tmp = gen_reg_rtx (SImode); | |
1851 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1852 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1853 | operands[1] = gen_lowpart (HImode, tmp); | |
1854 | } | |
1855 | }) | |
1856 | ||
1857 | (define_insn "*movhi" | |
f2dc2f86 AK |
1858 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q") |
1859 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))] | |
9db1d521 HP |
1860 | "" |
1861 | "@ | |
d40c829f UW |
1862 | lr\t%0,%1 |
1863 | lhi\t%0,%h1 | |
1864 | lh\t%0,%1 | |
1865 | lhy\t%0,%1 | |
963fc8d0 | 1866 | lhrl\t%0,%1 |
d40c829f UW |
1867 | sth\t%1,%0 |
1868 | sthy\t%1,%0 | |
963fc8d0 | 1869 | sthrl\t%1,%0 |
f2dc2f86 AK |
1870 | mvhhi\t%0,%1" |
1871 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL") | |
1872 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*") | |
1873 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10") | |
9381e3f1 WG |
1874 | (set_attr "z10prop" "z10_fr_E1, |
1875 | z10_fwd_A1, | |
1876 | z10_super_E1, | |
1877 | z10_super_E1, | |
1878 | z10_super_E1, | |
729e750f | 1879 | z10_rec, |
9381e3f1 WG |
1880 | z10_rec, |
1881 | z10_rec, | |
f2dc2f86 | 1882 | z10_super")]) |
9db1d521 | 1883 | |
84817c5d UW |
1884 | (define_peephole2 |
1885 | [(set (match_operand:HI 0 "register_operand" "") | |
1886 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1887 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1888 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1889 | && get_pool_mode (operands[1]) == HImode | |
1890 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1891 | [(set (match_dup 0) (match_dup 2))] | |
1892 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1893 | |
9db1d521 HP |
1894 | ; |
1895 | ; movqi instruction pattern(s). | |
1896 | ; | |
1897 | ||
02ed3c5e UW |
1898 | (define_expand "movqi" |
1899 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1900 | (match_operand:QI 1 "general_operand" ""))] | |
1901 | "" | |
1902 | { | |
c19ec8f9 | 1903 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1904 | is just as fast as a QImode load. */ |
b3a13419 | 1905 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 1906 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1907 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1908 | { |
9602b6a1 AK |
1909 | rtx tmp = gen_reg_rtx (DImode); |
1910 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
02ed3c5e UW |
1911 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1912 | operands[1] = gen_lowpart (QImode, tmp); | |
1913 | } | |
1914 | }) | |
4023fb28 | 1915 | |
02ed3c5e | 1916 | (define_insn "*movqi" |
0a88561f AK |
1917 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1918 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1919 | "" |
1920 | "@ | |
d40c829f UW |
1921 | lr\t%0,%1 |
1922 | lhi\t%0,%b1 | |
1923 | ic\t%0,%1 | |
1924 | icy\t%0,%1 | |
1925 | stc\t%1,%0 | |
1926 | stcy\t%1,%0 | |
fc0ea003 | 1927 | mvi\t%S0,%b1 |
0a88561f | 1928 | mviy\t%S0,%b1 |
b247e88a | 1929 | #" |
0a88561f AK |
1930 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1931 | (set_attr "type" "lr,*,*,*,store,store,store,store,*") | |
9381e3f1 WG |
1932 | (set_attr "z10prop" "z10_fr_E1, |
1933 | z10_fwd_A1, | |
1934 | z10_super_E1, | |
1935 | z10_super_E1, | |
729e750f | 1936 | z10_rec, |
9381e3f1 WG |
1937 | z10_rec, |
1938 | z10_super, | |
0a88561f AK |
1939 | z10_super, |
1940 | *")]) | |
9db1d521 | 1941 | |
84817c5d UW |
1942 | (define_peephole2 |
1943 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1944 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1945 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1946 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1947 | && get_pool_mode (operands[1]) == QImode | |
1948 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1949 | [(set (match_dup 0) (match_dup 2))] | |
1950 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1951 | |
9db1d521 | 1952 | ; |
05b9aaaa | 1953 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1954 | ; |
1955 | ||
1956 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1957 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1958 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1959 | "" |
d3632d41 | 1960 | "@ |
d40c829f UW |
1961 | ic\t%0,%1 |
1962 | icy\t%0,%1" | |
9381e3f1 | 1963 | [(set_attr "op_type" "RX,RXY") |
729e750f | 1964 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
1965 | |
1966 | ; | |
1967 | ; movstricthi instruction pattern(s). | |
1968 | ; | |
1969 | ||
1970 | (define_insn "*movstricthi" | |
d3632d41 | 1971 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1972 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1973 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1974 | "" |
d3632d41 | 1975 | "@ |
fc0ea003 UW |
1976 | icm\t%0,3,%S1 |
1977 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
1978 | [(set_attr "op_type" "RS,RSY") |
1979 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
1980 | |
1981 | ; | |
1982 | ; movstrictsi instruction pattern(s). | |
1983 | ; | |
1984 | ||
05b9aaaa | 1985 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1986 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1987 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 1988 | "TARGET_ZARCH" |
9db1d521 | 1989 | "@ |
d40c829f UW |
1990 | lr\t%0,%1 |
1991 | l\t%0,%1 | |
c5aa1d12 UW |
1992 | ly\t%0,%1 |
1993 | ear\t%0,%1" | |
1994 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
1995 | (set_attr "type" "lr,load,load,*") |
1996 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 1997 | |
f61a2c7d | 1998 | ; |
609e7e80 | 1999 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2000 | ; |
2001 | ||
609e7e80 AK |
2002 | (define_expand "mov<mode>" |
2003 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2004 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2005 | "" |
2006 | "") | |
2007 | ||
609e7e80 | 2008 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2009 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
2010 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 2011 | "TARGET_ZARCH" |
f61a2c7d | 2012 | "@ |
65b1d8ea | 2013 | lzxr\t%0 |
f61a2c7d AK |
2014 | lxr\t%0,%1 |
2015 | # | |
2016 | # | |
2017 | lmg\t%0,%N0,%S1 | |
2018 | stmg\t%1,%N1,%S0 | |
2019 | # | |
f61a2c7d | 2020 | #" |
65b1d8ea AK |
2021 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2022 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2023 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2024 | |
609e7e80 | 2025 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2026 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2027 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2028 | "!TARGET_ZARCH" |
f61a2c7d | 2029 | "@ |
65b1d8ea | 2030 | lzxr\t%0 |
f61a2c7d AK |
2031 | lxr\t%0,%1 |
2032 | # | |
f61a2c7d | 2033 | #" |
65b1d8ea AK |
2034 | [(set_attr "op_type" "RRE,RRE,*,*") |
2035 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2036 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2037 | |
2038 | ; TFmode in GPRs splitters | |
2039 | ||
2040 | (define_split | |
609e7e80 AK |
2041 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2042 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2043 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2044 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2045 | [(set (match_dup 2) (match_dup 4)) |
2046 | (set (match_dup 3) (match_dup 5))] | |
2047 | { | |
609e7e80 AK |
2048 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2049 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2050 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2051 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2052 | }) |
2053 | ||
2054 | (define_split | |
609e7e80 AK |
2055 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2056 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2057 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2058 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2059 | [(set (match_dup 2) (match_dup 4)) |
2060 | (set (match_dup 3) (match_dup 5))] | |
2061 | { | |
609e7e80 AK |
2062 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2063 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2064 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2065 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2066 | }) |
2067 | ||
2068 | (define_split | |
609e7e80 AK |
2069 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2070 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2071 | "TARGET_ZARCH && reload_completed |
f61a2c7d AK |
2072 | && !FP_REG_P (operands[0]) |
2073 | && !s_operand (operands[1], VOIDmode)" | |
2074 | [(set (match_dup 0) (match_dup 1))] | |
2075 | { | |
609e7e80 | 2076 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2077 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2078 | s390_load_address (addr, XEXP (operands[1], 0)); |
2079 | operands[1] = replace_equiv_address (operands[1], addr); | |
2080 | }) | |
2081 | ||
7b6baae1 | 2082 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2083 | |
2084 | (define_split | |
609e7e80 AK |
2085 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2086 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2087 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2088 | && FP_REG_P (operands[0])" |
2089 | [(set (match_dup 2) (match_dup 4)) | |
2090 | (set (match_dup 3) (match_dup 5))] | |
2091 | { | |
609e7e80 AK |
2092 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2093 | <MODE>mode, 0); | |
2094 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2095 | <MODE>mode, 8); | |
2096 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2097 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2098 | }) |
2099 | ||
2100 | (define_split | |
609e7e80 AK |
2101 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2102 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2103 | "reload_completed && offsettable_memref_p (operands[0]) |
2104 | && FP_REG_P (operands[1])" | |
2105 | [(set (match_dup 2) (match_dup 4)) | |
2106 | (set (match_dup 3) (match_dup 5))] | |
2107 | { | |
609e7e80 AK |
2108 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2109 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2110 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2111 | <MODE>mode, 0); | |
2112 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2113 | <MODE>mode, 8); | |
f61a2c7d AK |
2114 | }) |
2115 | ||
9db1d521 | 2116 | ; |
609e7e80 | 2117 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2118 | ; |
2119 | ||
609e7e80 AK |
2120 | (define_expand "mov<mode>" |
2121 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2122 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2123 | "" |
13c025c1 | 2124 | "") |
9db1d521 | 2125 | |
609e7e80 AK |
2126 | (define_insn "*mov<mode>_64dfp" |
2127 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2128 | "=f,f,f,d,f,f,R,T,d,d, d,RT") |
609e7e80 | 2129 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2130 | " G,f,d,f,R,T,f,f,G,d,RT, d"))] |
9602b6a1 | 2131 | "TARGET_DFP" |
85dae55a | 2132 | "@ |
65b1d8ea | 2133 | lzdr\t%0 |
85dae55a AK |
2134 | ldr\t%0,%1 |
2135 | ldgr\t%0,%1 | |
2136 | lgdr\t%0,%1 | |
2137 | ld\t%0,%1 | |
2138 | ldy\t%0,%1 | |
2139 | std\t%1,%0 | |
2140 | stdy\t%1,%0 | |
45e5214c | 2141 | lghi\t%0,0 |
85dae55a AK |
2142 | lgr\t%0,%1 |
2143 | lg\t%0,%1 | |
f2dc2f86 | 2144 | stg\t%1,%0" |
65b1d8ea AK |
2145 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2146 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, | |
45e5214c | 2147 | fstoredf,fstoredf,*,lr,load,store") |
65b1d8ea AK |
2148 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") |
2149 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
85dae55a | 2150 | |
609e7e80 | 2151 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2152 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT") |
2153 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))] | |
9602b6a1 | 2154 | "TARGET_ZARCH" |
9db1d521 | 2155 | "@ |
65b1d8ea | 2156 | lzdr\t%0 |
d40c829f UW |
2157 | ldr\t%0,%1 |
2158 | ld\t%0,%1 | |
2159 | ldy\t%0,%1 | |
2160 | std\t%1,%0 | |
2161 | stdy\t%1,%0 | |
45e5214c | 2162 | lghi\t%0,0 |
d40c829f UW |
2163 | lgr\t%0,%1 |
2164 | lg\t%0,%1 | |
f2dc2f86 | 2165 | stg\t%1,%0" |
65b1d8ea AK |
2166 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2167 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2168 | fstore<mode>,fstore<mode>,*,lr,load,store") | |
2169 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") | |
2170 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")]) | |
609e7e80 AK |
2171 | |
2172 | (define_insn "*mov<mode>_31" | |
2173 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2174 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2175 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2176 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2177 | "!TARGET_ZARCH" |
9db1d521 | 2178 | "@ |
65b1d8ea | 2179 | lzdr\t%0 |
d40c829f UW |
2180 | ldr\t%0,%1 |
2181 | ld\t%0,%1 | |
2182 | ldy\t%0,%1 | |
2183 | std\t%1,%0 | |
2184 | stdy\t%1,%0 | |
fc0ea003 | 2185 | lm\t%0,%N0,%S1 |
c4d50129 | 2186 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2187 | stm\t%1,%N1,%S0 |
c4d50129 | 2188 | stmy\t%1,%N1,%S0 |
4023fb28 | 2189 | # |
19b63d8e | 2190 | #" |
65b1d8ea AK |
2191 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2192 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2193 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2194 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2195 | |
2196 | (define_split | |
609e7e80 AK |
2197 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2198 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2199 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2200 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2201 | [(set (match_dup 2) (match_dup 4)) |
2202 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2203 | { |
609e7e80 AK |
2204 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2205 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2206 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2207 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2208 | }) |
2209 | ||
2210 | (define_split | |
609e7e80 AK |
2211 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2212 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2213 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2214 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2215 | [(set (match_dup 2) (match_dup 4)) |
2216 | (set (match_dup 3) (match_dup 5))] | |
2217 | { | |
609e7e80 AK |
2218 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2219 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2220 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2221 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2222 | }) |
9db1d521 | 2223 | |
4023fb28 | 2224 | (define_split |
609e7e80 AK |
2225 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2226 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2227 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2228 | && !FP_REG_P (operands[0]) |
4023fb28 | 2229 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2230 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2231 | { |
609e7e80 | 2232 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2233 | s390_load_address (addr, XEXP (operands[1], 0)); |
2234 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2235 | }) |
2236 | ||
9db1d521 | 2237 | ; |
609e7e80 | 2238 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2239 | ; |
2240 | ||
609e7e80 AK |
2241 | (define_insn "mov<mode>" |
2242 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
65b1d8ea | 2243 | "=f,f,f,f,R,T,d,d,d,d,R,T") |
609e7e80 | 2244 | (match_operand:SD_SF 1 "general_operand" |
65b1d8ea | 2245 | " G,f,R,T,f,f,G,d,R,T,d,d"))] |
4023fb28 | 2246 | "" |
9db1d521 | 2247 | "@ |
65b1d8ea | 2248 | lzer\t%0 |
d40c829f UW |
2249 | ler\t%0,%1 |
2250 | le\t%0,%1 | |
2251 | ley\t%0,%1 | |
2252 | ste\t%1,%0 | |
2253 | stey\t%1,%0 | |
45e5214c | 2254 | lhi\t%0,0 |
d40c829f UW |
2255 | lr\t%0,%1 |
2256 | l\t%0,%1 | |
2257 | ly\t%0,%1 | |
2258 | st\t%1,%0 | |
f2dc2f86 | 2259 | sty\t%1,%0" |
65b1d8ea AK |
2260 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY") |
2261 | (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>, | |
2262 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") | |
2263 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2264 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2265 | |
9dc62c00 AK |
2266 | ; |
2267 | ; movcc instruction pattern | |
2268 | ; | |
2269 | ||
2270 | (define_insn "movcc" | |
2271 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2272 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2273 | "" |
2274 | "@ | |
2275 | lr\t%0,%1 | |
2276 | tmh\t%1,12288 | |
2277 | ipm\t%0 | |
2278 | st\t%0,%1 | |
2279 | sty\t%0,%1 | |
2280 | l\t%1,%0 | |
2281 | ly\t%1,%0" | |
8dd3b235 | 2282 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
9381e3f1 | 2283 | (set_attr "type" "lr,*,*,store,store,load,load") |
65b1d8ea AK |
2284 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3") |
2285 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) | |
9dc62c00 | 2286 | |
19b63d8e UW |
2287 | ; |
2288 | ; Block move (MVC) patterns. | |
2289 | ; | |
2290 | ||
2291 | (define_insn "*mvc" | |
2292 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2293 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2294 | (use (match_operand 2 "const_int_operand" "n"))] | |
2295 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2296 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2297 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2298 | |
0a88561f AK |
2299 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2300 | ; order to have it implemented with mvc. | |
2301 | ||
2302 | (define_split | |
2303 | [(set (match_operand:QI 0 "memory_operand" "") | |
2304 | (match_operand:QI 1 "memory_operand" ""))] | |
2305 | "reload_completed" | |
2306 | [(parallel | |
2307 | [(set (match_dup 0) (match_dup 1)) | |
2308 | (use (const_int 1))])] | |
2309 | { | |
2310 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2311 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2312 | }) | |
2313 | ||
2314 | ||
19b63d8e UW |
2315 | (define_peephole2 |
2316 | [(parallel | |
2317 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2318 | (match_operand:BLK 1 "memory_operand" "")) | |
2319 | (use (match_operand 2 "const_int_operand" ""))]) | |
2320 | (parallel | |
2321 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2322 | (match_operand:BLK 4 "memory_operand" "")) | |
2323 | (use (match_operand 5 "const_int_operand" ""))])] | |
2324 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2325 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2326 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2327 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2328 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2329 | [(parallel | |
2330 | [(set (match_dup 6) (match_dup 7)) | |
2331 | (use (match_dup 8))])] | |
2332 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2333 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2334 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2335 | ||
2336 | ||
9db1d521 HP |
2337 | ; |
2338 | ; load_multiple pattern(s). | |
2339 | ; | |
22ea6b4f UW |
2340 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2341 | ; we currently support load_multiple/store_multiple only after reload. | |
2342 | ; | |
9db1d521 HP |
2343 | |
2344 | (define_expand "load_multiple" | |
2345 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2346 | (match_operand 1 "" "")) | |
2347 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2348 | "reload_completed" |
9db1d521 | 2349 | { |
c19ec8f9 | 2350 | enum machine_mode mode; |
9db1d521 HP |
2351 | int regno; |
2352 | int count; | |
2353 | rtx from; | |
4023fb28 | 2354 | int i, off; |
9db1d521 HP |
2355 | |
2356 | /* Support only loading a constant number of fixed-point registers from | |
2357 | memory and only bother with this if more than two */ | |
2358 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2359 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2360 | || INTVAL (operands[2]) > 16 |
2361 | || GET_CODE (operands[1]) != MEM | |
2362 | || GET_CODE (operands[0]) != REG | |
2363 | || REGNO (operands[0]) >= 16) | |
2364 | FAIL; | |
2365 | ||
2366 | count = INTVAL (operands[2]); | |
2367 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2368 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2369 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2370 | FAIL; |
9db1d521 HP |
2371 | |
2372 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2373 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2374 | { |
2375 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2376 | { | |
2377 | from = XEXP (operands[1], 0); | |
2378 | off = 0; | |
2379 | } | |
2380 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2381 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2382 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2383 | { | |
2384 | from = XEXP (XEXP (operands[1], 0), 0); | |
2385 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2386 | } | |
2387 | else | |
2388 | FAIL; | |
4023fb28 UW |
2389 | } |
2390 | else | |
2391 | { | |
2392 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2393 | off = 0; | |
2394 | } | |
9db1d521 HP |
2395 | |
2396 | for (i = 0; i < count; i++) | |
2397 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
2398 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
2399 | change_address (operands[1], mode, | |
0a81f074 RS |
2400 | plus_constant (Pmode, from, |
2401 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2402 | }) |
9db1d521 HP |
2403 | |
2404 | (define_insn "*load_multiple_di" | |
2405 | [(match_parallel 0 "load_multiple_operation" | |
2406 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2407 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2408 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2409 | { |
2410 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2411 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2412 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2413 | } |
d3632d41 | 2414 | [(set_attr "op_type" "RSY") |
4023fb28 | 2415 | (set_attr "type" "lm")]) |
9db1d521 HP |
2416 | |
2417 | (define_insn "*load_multiple_si" | |
2418 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2419 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2420 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2421 | "reload_completed" |
9db1d521 HP |
2422 | { |
2423 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2424 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2425 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2426 | } |
d3632d41 | 2427 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2428 | (set_attr "type" "lm")]) |
9db1d521 HP |
2429 | |
2430 | ; | |
c7453384 | 2431 | ; store multiple pattern(s). |
9db1d521 HP |
2432 | ; |
2433 | ||
2434 | (define_expand "store_multiple" | |
2435 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2436 | (match_operand 1 "" "")) | |
2437 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2438 | "reload_completed" |
9db1d521 | 2439 | { |
c19ec8f9 | 2440 | enum machine_mode mode; |
9db1d521 HP |
2441 | int regno; |
2442 | int count; | |
2443 | rtx to; | |
4023fb28 | 2444 | int i, off; |
9db1d521 HP |
2445 | |
2446 | /* Support only storing a constant number of fixed-point registers to | |
2447 | memory and only bother with this if more than two. */ | |
2448 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2449 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2450 | || INTVAL (operands[2]) > 16 |
2451 | || GET_CODE (operands[0]) != MEM | |
2452 | || GET_CODE (operands[1]) != REG | |
2453 | || REGNO (operands[1]) >= 16) | |
2454 | FAIL; | |
2455 | ||
2456 | count = INTVAL (operands[2]); | |
2457 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2458 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2459 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2460 | FAIL; |
9db1d521 HP |
2461 | |
2462 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2463 | |
b3a13419 | 2464 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2465 | { |
2466 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2467 | { | |
2468 | to = XEXP (operands[0], 0); | |
2469 | off = 0; | |
2470 | } | |
2471 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2472 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2473 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2474 | { | |
2475 | to = XEXP (XEXP (operands[0], 0), 0); | |
2476 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2477 | } | |
2478 | else | |
2479 | FAIL; | |
4023fb28 | 2480 | } |
c7453384 | 2481 | else |
4023fb28 UW |
2482 | { |
2483 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2484 | off = 0; | |
2485 | } | |
9db1d521 HP |
2486 | |
2487 | for (i = 0; i < count; i++) | |
2488 | XVECEXP (operands[3], 0, i) | |
2489 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 | 2490 | change_address (operands[0], mode, |
0a81f074 RS |
2491 | plus_constant (Pmode, to, |
2492 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2493 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2494 | }) |
9db1d521 HP |
2495 | |
2496 | (define_insn "*store_multiple_di" | |
2497 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2498 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2499 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2500 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2501 | { |
2502 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2503 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2504 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2505 | } |
d3632d41 | 2506 | [(set_attr "op_type" "RSY") |
4023fb28 | 2507 | (set_attr "type" "stm")]) |
9db1d521 HP |
2508 | |
2509 | ||
2510 | (define_insn "*store_multiple_si" | |
2511 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2512 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2513 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2514 | "reload_completed" |
9db1d521 HP |
2515 | { |
2516 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2517 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2518 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2519 | } |
d3632d41 | 2520 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2521 | (set_attr "type" "stm")]) |
9db1d521 HP |
2522 | |
2523 | ;; | |
2524 | ;; String instructions. | |
2525 | ;; | |
2526 | ||
963fc8d0 | 2527 | (define_insn "*execute_rl" |
2771c2f9 | 2528 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2529 | [(unspec [(match_operand 1 "register_operand" "a") |
2530 | (match_operand 2 "" "") | |
2531 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2532 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2533 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2534 | "exrl\t%1,%3" | |
2535 | [(set_attr "op_type" "RIL") | |
2536 | (set_attr "type" "cs")]) | |
2537 | ||
9bb86f41 | 2538 | (define_insn "*execute" |
2771c2f9 | 2539 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2540 | [(unspec [(match_operand 1 "register_operand" "a") |
2541 | (match_operand:BLK 2 "memory_operand" "R") | |
2542 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2543 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2544 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2545 | "ex\t%1,%2" | |
29a74354 UW |
2546 | [(set_attr "op_type" "RX") |
2547 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2548 | |
2549 | ||
91d39d71 UW |
2550 | ; |
2551 | ; strlenM instruction pattern(s). | |
2552 | ; | |
2553 | ||
9db2f16d | 2554 | (define_expand "strlen<mode>" |
ccbdc0d4 | 2555 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2556 | (parallel |
91d39d71 | 2557 | [(set (match_dup 4) |
9db2f16d | 2558 | (unspec:P [(const_int 0) |
91d39d71 | 2559 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2560 | (reg:SI 0) |
91d39d71 | 2561 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2562 | (clobber (scratch:P)) |
ae156f85 | 2563 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2564 | (parallel |
9db2f16d AS |
2565 | [(set (match_operand:P 0 "register_operand" "") |
2566 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2567 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2568 | "" |
91d39d71 | 2569 | { |
9db2f16d AS |
2570 | operands[4] = gen_reg_rtx (Pmode); |
2571 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2572 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2573 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2574 | }) | |
2575 | ||
9db2f16d AS |
2576 | (define_insn "*strlen<mode>" |
2577 | [(set (match_operand:P 0 "register_operand" "=a") | |
2578 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2579 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2580 | (reg:SI 0) |
91d39d71 | 2581 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2582 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2583 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2584 | "" |
91d39d71 | 2585 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2586 | [(set_attr "length" "8") |
2587 | (set_attr "type" "vs")]) | |
91d39d71 | 2588 | |
ccbdc0d4 AS |
2589 | ; |
2590 | ; cmpstrM instruction pattern(s). | |
2591 | ; | |
2592 | ||
2593 | (define_expand "cmpstrsi" | |
2594 | [(set (reg:SI 0) (const_int 0)) | |
2595 | (parallel | |
2596 | [(clobber (match_operand 3 "" "")) | |
2597 | (clobber (match_dup 4)) | |
2598 | (set (reg:CCU CC_REGNUM) | |
2599 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2600 | (match_operand:BLK 2 "memory_operand" ""))) | |
2601 | (use (reg:SI 0))]) | |
2602 | (parallel | |
2603 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2604 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
2605 | (clobber (reg:CC CC_REGNUM))])] |
2606 | "" | |
2607 | { | |
2608 | /* As the result of CMPINT is inverted compared to what we need, | |
2609 | we have to swap the operands. */ | |
2610 | rtx op1 = operands[2]; | |
2611 | rtx op2 = operands[1]; | |
2612 | rtx addr1 = gen_reg_rtx (Pmode); | |
2613 | rtx addr2 = gen_reg_rtx (Pmode); | |
2614 | ||
2615 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2616 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2617 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2618 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2619 | operands[3] = addr1; | |
2620 | operands[4] = addr2; | |
2621 | }) | |
2622 | ||
2623 | (define_insn "*cmpstr<mode>" | |
2624 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2625 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2626 | (set (reg:CCU CC_REGNUM) | |
2627 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2628 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2629 | (use (reg:SI 0))] | |
2630 | "" | |
2631 | "clst\t%0,%1\;jo\t.-4" | |
2632 | [(set_attr "length" "8") | |
2633 | (set_attr "type" "vs")]) | |
9381e3f1 | 2634 | |
742090fc AS |
2635 | ; |
2636 | ; movstr instruction pattern. | |
2637 | ; | |
2638 | ||
2639 | (define_expand "movstr" | |
2640 | [(set (reg:SI 0) (const_int 0)) | |
9381e3f1 | 2641 | (parallel |
742090fc AS |
2642 | [(clobber (match_dup 3)) |
2643 | (set (match_operand:BLK 1 "memory_operand" "") | |
2644 | (match_operand:BLK 2 "memory_operand" "")) | |
2645 | (set (match_operand 0 "register_operand" "") | |
9381e3f1 | 2646 | (unspec [(match_dup 1) |
742090fc AS |
2647 | (match_dup 2) |
2648 | (reg:SI 0)] UNSPEC_MVST)) | |
2649 | (clobber (reg:CC CC_REGNUM))])] | |
2650 | "" | |
2651 | { | |
2652 | rtx addr1 = gen_reg_rtx (Pmode); | |
2653 | rtx addr2 = gen_reg_rtx (Pmode); | |
2654 | ||
2655 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2656 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2657 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2658 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2659 | operands[3] = addr2; | |
2660 | }) | |
2661 | ||
2662 | (define_insn "*movstr" | |
2663 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2664 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2665 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2666 | (set (match_operand:P 0 "register_operand" "=d") | |
9381e3f1 | 2667 | (unspec [(mem:BLK (match_dup 1)) |
742090fc AS |
2668 | (mem:BLK (match_dup 3)) |
2669 | (reg:SI 0)] UNSPEC_MVST)) | |
2670 | (clobber (reg:CC CC_REGNUM))] | |
2671 | "" | |
2672 | "mvst\t%1,%2\;jo\t.-4" | |
2673 | [(set_attr "length" "8") | |
2674 | (set_attr "type" "vs")]) | |
9381e3f1 | 2675 | |
742090fc | 2676 | |
9db1d521 | 2677 | ; |
70128ad9 | 2678 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2679 | ; |
2680 | ||
9db2f16d | 2681 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2682 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2683 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2684 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2685 | (match_operand 3 "" "")] |
2686 | "" | |
367d32f3 AK |
2687 | { |
2688 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
2689 | DONE; | |
2690 | else | |
2691 | FAIL; | |
2692 | }) | |
9db1d521 | 2693 | |
ecbe845e UW |
2694 | ; Move a block that is up to 256 bytes in length. |
2695 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2696 | |
70128ad9 | 2697 | (define_expand "movmem_short" |
b9404c99 UW |
2698 | [(parallel |
2699 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2700 | (match_operand:BLK 1 "memory_operand" "")) | |
2701 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2702 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2703 | (clobber (match_dup 3))])] |
2704 | "" | |
2705 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2706 | |
70128ad9 | 2707 | (define_insn "*movmem_short" |
963fc8d0 AK |
2708 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
2709 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2710 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2711 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
2712 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
2713 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 2714 | "#" |
963fc8d0 | 2715 | [(set_attr "type" "cs") |
b5e0425c | 2716 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 2717 | |
9bb86f41 UW |
2718 | (define_split |
2719 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2720 | (match_operand:BLK 1 "memory_operand" "")) | |
2721 | (use (match_operand 2 "const_int_operand" "")) | |
2722 | (use (match_operand 3 "immediate_operand" "")) | |
2723 | (clobber (scratch))] | |
2724 | "reload_completed" | |
2725 | [(parallel | |
2726 | [(set (match_dup 0) (match_dup 1)) | |
2727 | (use (match_dup 2))])] | |
2728 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2729 | |
9bb86f41 UW |
2730 | (define_split |
2731 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2732 | (match_operand:BLK 1 "memory_operand" "")) | |
2733 | (use (match_operand 2 "register_operand" "")) | |
2734 | (use (match_operand 3 "memory_operand" "")) | |
2735 | (clobber (scratch))] | |
2736 | "reload_completed" | |
2737 | [(parallel | |
2738 | [(unspec [(match_dup 2) (match_dup 3) | |
2739 | (const_int 0)] UNSPEC_EXECUTE) | |
2740 | (set (match_dup 0) (match_dup 1)) | |
2741 | (use (const_int 1))])] | |
2742 | "") | |
2743 | ||
963fc8d0 AK |
2744 | (define_split |
2745 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2746 | (match_operand:BLK 1 "memory_operand" "")) | |
2747 | (use (match_operand 2 "register_operand" "")) | |
2748 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2749 | (clobber (scratch))] | |
2750 | "TARGET_Z10 && reload_completed" | |
2751 | [(parallel | |
2752 | [(unspec [(match_dup 2) (const_int 0) | |
2753 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2754 | (set (match_dup 0) (match_dup 1)) | |
2755 | (use (const_int 1))])] | |
2756 | "operands[3] = gen_label_rtx ();") | |
2757 | ||
9bb86f41 UW |
2758 | (define_split |
2759 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2760 | (match_operand:BLK 1 "memory_operand" "")) | |
2761 | (use (match_operand 2 "register_operand" "")) | |
2762 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2763 | (clobber (match_operand 3 "register_operand" ""))] | |
2764 | "reload_completed && TARGET_CPU_ZARCH" | |
2765 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2766 | (parallel | |
9381e3f1 | 2767 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
2768 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
2769 | (set (match_dup 0) (match_dup 1)) | |
2770 | (use (const_int 1))])] | |
2771 | "operands[4] = gen_label_rtx ();") | |
2772 | ||
a41c6c53 | 2773 | ; Move a block of arbitrary length. |
9db1d521 | 2774 | |
70128ad9 | 2775 | (define_expand "movmem_long" |
b9404c99 UW |
2776 | [(parallel |
2777 | [(clobber (match_dup 2)) | |
2778 | (clobber (match_dup 3)) | |
2779 | (set (match_operand:BLK 0 "memory_operand" "") | |
2780 | (match_operand:BLK 1 "memory_operand" "")) | |
2781 | (use (match_operand 2 "general_operand" "")) | |
2782 | (use (match_dup 3)) | |
ae156f85 | 2783 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2784 | "" |
2785 | { | |
9602b6a1 AK |
2786 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
2787 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
2788 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
2789 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
2790 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
2791 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
2792 | rtx len0 = gen_lowpart (Pmode, reg0); |
2793 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2794 | ||
c41c1387 | 2795 | emit_clobber (reg0); |
b9404c99 UW |
2796 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2797 | emit_move_insn (len0, operands[2]); | |
2798 | ||
c41c1387 | 2799 | emit_clobber (reg1); |
b9404c99 UW |
2800 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2801 | emit_move_insn (len1, operands[2]); | |
2802 | ||
2803 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2804 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2805 | operands[2] = reg0; | |
2806 | operands[3] = reg1; | |
2807 | }) | |
2808 | ||
a1aed706 AS |
2809 | (define_insn "*movmem_long" |
2810 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2811 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2812 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2813 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2814 | (use (match_dup 2)) |
2815 | (use (match_dup 3)) | |
ae156f85 | 2816 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
2817 | "TARGET_64BIT || !TARGET_ZARCH" |
2818 | "mvcle\t%0,%1,0\;jo\t.-4" | |
2819 | [(set_attr "length" "8") | |
2820 | (set_attr "type" "vs")]) | |
2821 | ||
2822 | (define_insn "*movmem_long_31z" | |
2823 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2824 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2825 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
2826 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
2827 | (use (match_dup 2)) | |
2828 | (use (match_dup 3)) | |
2829 | (clobber (reg:CC CC_REGNUM))] | |
2830 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 2831 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2832 | [(set_attr "length" "8") |
2833 | (set_attr "type" "vs")]) | |
9db1d521 | 2834 | |
638e37c2 WG |
2835 | |
2836 | ; | |
2837 | ; Test data class. | |
2838 | ; | |
2839 | ||
0f67fa83 WG |
2840 | (define_expand "signbit<mode>2" |
2841 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2842 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2843 | (match_dup 2)] | |
0f67fa83 WG |
2844 | UNSPEC_TDC_INSN)) |
2845 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2846 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
2847 | "TARGET_HARD_FLOAT" |
2848 | { | |
2849 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
2850 | }) | |
2851 | ||
638e37c2 WG |
2852 | (define_expand "isinf<mode>2" |
2853 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2854 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2855 | (match_dup 2)] | |
638e37c2 WG |
2856 | UNSPEC_TDC_INSN)) |
2857 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2858 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 2859 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
2860 | { |
2861 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
2862 | }) | |
2863 | ||
5a3fe9b6 AK |
2864 | (define_insn_and_split "*cc_to_int" |
2865 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2866 | (unspec:SI [(match_operand 1 "register_operand" "0")] | |
2867 | UNSPEC_CC_TO_INT))] | |
2868 | "operands != NULL" | |
2869 | "#" | |
2870 | "reload_completed" | |
2871 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
2872 | ||
638e37c2 WG |
2873 | ; This insn is used to generate all variants of the Test Data Class |
2874 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
2875 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 2876 | ; specifying the required test(s). |
638e37c2 | 2877 | ; |
be5de7a1 | 2878 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
2879 | (define_insn "*TDC_insn_<mode>" |
2880 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 2881 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 2882 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 2883 | "TARGET_HARD_FLOAT" |
0387c142 | 2884 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 2885 | [(set_attr "op_type" "RXE") |
9381e3f1 | 2886 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 2887 | |
638e37c2 WG |
2888 | |
2889 | ||
9db1d521 | 2890 | ; |
57e84f18 | 2891 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2892 | ; |
2893 | ||
57e84f18 | 2894 | (define_expand "setmem<mode>" |
a41c6c53 | 2895 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2896 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2897 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2898 | (match_operand 3 "" "")] |
a41c6c53 | 2899 | "" |
6d057022 | 2900 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2901 | |
a41c6c53 | 2902 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2903 | ; The block length is taken as (operands[1] % 256) + 1. |
2904 | ||
70128ad9 | 2905 | (define_expand "clrmem_short" |
b9404c99 UW |
2906 | [(parallel |
2907 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2908 | (const_int 0)) | |
2909 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2910 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2911 | (clobber (match_dup 2)) |
ae156f85 | 2912 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2913 | "" |
2914 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2915 | |
70128ad9 | 2916 | (define_insn "*clrmem_short" |
963fc8d0 | 2917 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 2918 | (const_int 0)) |
963fc8d0 AK |
2919 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
2920 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 2921 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 2922 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 2923 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 2924 | "#" |
963fc8d0 | 2925 | [(set_attr "type" "cs") |
b5e0425c | 2926 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
2927 | |
2928 | (define_split | |
2929 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2930 | (const_int 0)) | |
2931 | (use (match_operand 1 "const_int_operand" "")) | |
2932 | (use (match_operand 2 "immediate_operand" "")) | |
2933 | (clobber (scratch)) | |
ae156f85 | 2934 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2935 | "reload_completed" |
2936 | [(parallel | |
2937 | [(set (match_dup 0) (const_int 0)) | |
2938 | (use (match_dup 1)) | |
ae156f85 | 2939 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2940 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2941 | |
9bb86f41 UW |
2942 | (define_split |
2943 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2944 | (const_int 0)) | |
2945 | (use (match_operand 1 "register_operand" "")) | |
2946 | (use (match_operand 2 "memory_operand" "")) | |
2947 | (clobber (scratch)) | |
ae156f85 | 2948 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2949 | "reload_completed" |
2950 | [(parallel | |
2951 | [(unspec [(match_dup 1) (match_dup 2) | |
2952 | (const_int 0)] UNSPEC_EXECUTE) | |
2953 | (set (match_dup 0) (const_int 0)) | |
2954 | (use (const_int 1)) | |
ae156f85 | 2955 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2956 | "") |
9db1d521 | 2957 | |
963fc8d0 AK |
2958 | (define_split |
2959 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2960 | (const_int 0)) | |
2961 | (use (match_operand 1 "register_operand" "")) | |
2962 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2963 | (clobber (scratch)) | |
2964 | (clobber (reg:CC CC_REGNUM))] | |
2965 | "TARGET_Z10 && reload_completed" | |
2966 | [(parallel | |
2967 | [(unspec [(match_dup 1) (const_int 0) | |
2968 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2969 | (set (match_dup 0) (const_int 0)) | |
2970 | (use (const_int 1)) | |
2971 | (clobber (reg:CC CC_REGNUM))])] | |
2972 | "operands[3] = gen_label_rtx ();") | |
2973 | ||
9bb86f41 UW |
2974 | (define_split |
2975 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2976 | (const_int 0)) | |
2977 | (use (match_operand 1 "register_operand" "")) | |
2978 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2979 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2980 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2981 | "reload_completed && TARGET_CPU_ZARCH" |
2982 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2983 | (parallel | |
9381e3f1 | 2984 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
2985 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
2986 | (set (match_dup 0) (const_int 0)) | |
2987 | (use (const_int 1)) | |
ae156f85 | 2988 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2989 | "operands[3] = gen_label_rtx ();") |
2990 | ||
9381e3f1 | 2991 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2992 | |
6d057022 | 2993 | (define_expand "setmem_long" |
b9404c99 UW |
2994 | [(parallel |
2995 | [(clobber (match_dup 1)) | |
2996 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 2997 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 2998 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2999 | (use (match_dup 3)) |
ae156f85 | 3000 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3001 | "" |
a41c6c53 | 3002 | { |
9602b6a1 AK |
3003 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3004 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
3005 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
3006 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3007 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3008 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3009 | |
c41c1387 | 3010 | emit_clobber (reg0); |
b9404c99 UW |
3011 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3012 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3013 | |
b9404c99 | 3014 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3015 | |
b9404c99 UW |
3016 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3017 | operands[1] = reg0; | |
6d057022 | 3018 | operands[3] = reg1; |
b9404c99 | 3019 | }) |
a41c6c53 | 3020 | |
6d057022 | 3021 | (define_insn "*setmem_long" |
a1aed706 | 3022 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3023 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 3024 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 3025 | (use (match_dup 3)) |
a1aed706 | 3026 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3027 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3028 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3029 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3030 | [(set_attr "length" "8") |
3031 | (set_attr "type" "vs")]) | |
9db1d521 | 3032 | |
4989e88a AK |
3033 | (define_insn "*setmem_long_and" |
3034 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3035 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
3036 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
3037 | (match_operand 4 "const_int_operand" "n"))) | |
3038 | (use (match_dup 3)) | |
3039 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3040 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 AK |
3041 | "(TARGET_64BIT || !TARGET_ZARCH) && |
3042 | (INTVAL (operands[4]) & 255) == 255" | |
3043 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3044 | [(set_attr "length" "8") | |
3045 | (set_attr "type" "vs")]) | |
3046 | ||
3047 | (define_insn "*setmem_long_31z" | |
3048 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3049 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
3050 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) | |
3051 | (use (match_dup 3)) | |
3052 | (use (match_operand:TI 1 "register_operand" "d")) | |
3053 | (clobber (reg:CC CC_REGNUM))] | |
3054 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3055 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3056 | [(set_attr "length" "8") | |
3057 | (set_attr "type" "vs")]) | |
9602b6a1 | 3058 | |
9db1d521 | 3059 | ; |
358b8f01 | 3060 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3061 | ; |
3062 | ||
358b8f01 | 3063 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3064 | [(set (match_operand:SI 0 "register_operand" "") |
3065 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3066 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3067 | (use (match_operand:SI 3 "general_operand" "")) | |
3068 | (use (match_operand:SI 4 "" ""))] | |
3069 | "" | |
367d32f3 AK |
3070 | { |
3071 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3072 | operands[2], operands[3])) | |
3073 | DONE; | |
3074 | else | |
3075 | FAIL; | |
3076 | }) | |
9db1d521 | 3077 | |
a41c6c53 UW |
3078 | ; Compare a block that is up to 256 bytes in length. |
3079 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3080 | |
b9404c99 UW |
3081 | (define_expand "cmpmem_short" |
3082 | [(parallel | |
ae156f85 | 3083 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3084 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3085 | (match_operand:BLK 1 "memory_operand" ""))) |
3086 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3087 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3088 | (clobber (match_dup 3))])] |
3089 | "" | |
3090 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3091 | |
b9404c99 | 3092 | (define_insn "*cmpmem_short" |
ae156f85 | 3093 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3094 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3095 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3096 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3097 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3098 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3099 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3100 | "#" |
963fc8d0 | 3101 | [(set_attr "type" "cs") |
b5e0425c | 3102 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3103 | |
9bb86f41 | 3104 | (define_split |
ae156f85 | 3105 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3106 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3107 | (match_operand:BLK 1 "memory_operand" ""))) | |
3108 | (use (match_operand 2 "const_int_operand" "")) | |
3109 | (use (match_operand 3 "immediate_operand" "")) | |
3110 | (clobber (scratch))] | |
3111 | "reload_completed" | |
3112 | [(parallel | |
ae156f85 | 3113 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3114 | (use (match_dup 2))])] |
3115 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3116 | |
9bb86f41 | 3117 | (define_split |
ae156f85 | 3118 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3119 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3120 | (match_operand:BLK 1 "memory_operand" ""))) | |
3121 | (use (match_operand 2 "register_operand" "")) | |
3122 | (use (match_operand 3 "memory_operand" "")) | |
3123 | (clobber (scratch))] | |
3124 | "reload_completed" | |
3125 | [(parallel | |
3126 | [(unspec [(match_dup 2) (match_dup 3) | |
3127 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3128 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3129 | (use (const_int 1))])] |
3130 | "") | |
3131 | ||
963fc8d0 AK |
3132 | (define_split |
3133 | [(set (reg:CCU CC_REGNUM) | |
3134 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3135 | (match_operand:BLK 1 "memory_operand" ""))) | |
3136 | (use (match_operand 2 "register_operand" "")) | |
3137 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3138 | (clobber (scratch))] | |
3139 | "TARGET_Z10 && reload_completed" | |
3140 | [(parallel | |
3141 | [(unspec [(match_dup 2) (const_int 0) | |
3142 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3143 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3144 | (use (const_int 1))])] | |
3145 | "operands[4] = gen_label_rtx ();") | |
3146 | ||
9bb86f41 | 3147 | (define_split |
ae156f85 | 3148 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3149 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3150 | (match_operand:BLK 1 "memory_operand" ""))) | |
3151 | (use (match_operand 2 "register_operand" "")) | |
3152 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3153 | (clobber (match_operand 3 "register_operand" ""))] | |
3154 | "reload_completed && TARGET_CPU_ZARCH" | |
3155 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3156 | (parallel | |
9381e3f1 | 3157 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3158 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3159 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3160 | (use (const_int 1))])] |
3161 | "operands[4] = gen_label_rtx ();") | |
3162 | ||
a41c6c53 | 3163 | ; Compare a block of arbitrary length. |
9db1d521 | 3164 | |
b9404c99 UW |
3165 | (define_expand "cmpmem_long" |
3166 | [(parallel | |
3167 | [(clobber (match_dup 2)) | |
3168 | (clobber (match_dup 3)) | |
ae156f85 | 3169 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3170 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3171 | (match_operand:BLK 1 "memory_operand" ""))) |
3172 | (use (match_operand 2 "general_operand" "")) | |
3173 | (use (match_dup 3))])] | |
3174 | "" | |
3175 | { | |
9602b6a1 AK |
3176 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3177 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
3178 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
3179 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3180 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3181 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3182 | rtx len0 = gen_lowpart (Pmode, reg0); |
3183 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3184 | ||
c41c1387 | 3185 | emit_clobber (reg0); |
b9404c99 UW |
3186 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3187 | emit_move_insn (len0, operands[2]); | |
3188 | ||
c41c1387 | 3189 | emit_clobber (reg1); |
b9404c99 UW |
3190 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3191 | emit_move_insn (len1, operands[2]); | |
3192 | ||
3193 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3194 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3195 | operands[2] = reg0; | |
3196 | operands[3] = reg1; | |
3197 | }) | |
3198 | ||
a1aed706 AS |
3199 | (define_insn "*cmpmem_long" |
3200 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3201 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3202 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3203 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3204 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3205 | (use (match_dup 2)) |
3206 | (use (match_dup 3))] | |
9602b6a1 | 3207 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3208 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3209 | [(set_attr "length" "8") |
3210 | (set_attr "type" "vs")]) | |
9db1d521 | 3211 | |
9602b6a1 AK |
3212 | (define_insn "*cmpmem_long_31z" |
3213 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3214 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3215 | (set (reg:CCU CC_REGNUM) | |
3216 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3217 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3218 | (use (match_dup 2)) | |
3219 | (use (match_dup 3))] | |
3220 | "!TARGET_64BIT && TARGET_ZARCH" | |
3221 | "clcle\t%0,%1,0\;jo\t.-4" | |
3222 | [(set_attr "op_type" "NN") | |
3223 | (set_attr "type" "vs") | |
3224 | (set_attr "length" "8")]) | |
3225 | ||
02887425 UW |
3226 | ; Convert CCUmode condition code to integer. |
3227 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3228 | |
02887425 | 3229 | (define_insn_and_split "cmpint" |
9db1d521 | 3230 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3231 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3232 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3233 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3234 | "" |
02887425 UW |
3235 | "#" |
3236 | "reload_completed" | |
3237 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3238 | (parallel | |
3239 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3240 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3241 | |
3242 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3243 | [(set (reg CC_REGNUM) |
02887425 | 3244 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3245 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3246 | (const_int 0))) |
3247 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3248 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3249 | "s390_match_ccmode (insn, CCSmode)" |
3250 | "#" | |
3251 | "&& reload_completed" | |
3252 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3253 | (parallel | |
3254 | [(set (match_dup 2) (match_dup 3)) | |
3255 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3256 | { |
02887425 UW |
3257 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3258 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3259 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3260 | }) | |
9db1d521 | 3261 | |
02887425 | 3262 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3263 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3264 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3265 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3266 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3267 | "TARGET_ZARCH" |
02887425 UW |
3268 | "#" |
3269 | "&& reload_completed" | |
3270 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3271 | (parallel | |
3272 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3273 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3274 | |
3275 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3276 | [(set (reg CC_REGNUM) |
9381e3f1 | 3277 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3278 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3279 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3280 | (const_int 32)) (const_int 32)) |
3281 | (const_int 0))) | |
3282 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3283 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3284 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3285 | "#" |
3286 | "&& reload_completed" | |
3287 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3288 | (parallel | |
3289 | [(set (match_dup 2) (match_dup 3)) | |
3290 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3291 | { |
02887425 UW |
3292 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3293 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3294 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3295 | }) | |
9db1d521 | 3296 | |
4023fb28 | 3297 | |
9db1d521 HP |
3298 | ;; |
3299 | ;;- Conversion instructions. | |
3300 | ;; | |
3301 | ||
6fa05db6 | 3302 | (define_insn "*sethighpartsi" |
d3632d41 | 3303 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3304 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3305 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3306 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3307 | "" |
d3632d41 | 3308 | "@ |
6fa05db6 AS |
3309 | icm\t%0,%2,%S1 |
3310 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3311 | [(set_attr "op_type" "RS,RSY") |
3312 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3313 | |
6fa05db6 | 3314 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3315 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3316 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3317 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3318 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3319 | "TARGET_ZARCH" |
6fa05db6 | 3320 | "icmh\t%0,%2,%S1" |
729e750f WG |
3321 | [(set_attr "op_type" "RSY") |
3322 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3323 | |
6fa05db6 | 3324 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3325 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3326 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3327 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3328 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3329 | "!TARGET_ZARCH" |
d3632d41 | 3330 | "@ |
6fa05db6 AS |
3331 | icm\t%0,%2,%S1 |
3332 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3333 | [(set_attr "op_type" "RS,RSY") |
3334 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3335 | ||
1a2e356e RH |
3336 | ; |
3337 | ; extv instruction patterns | |
3338 | ; | |
3339 | ||
3340 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3341 | ; after resolving some issues with it. | |
3342 | ||
3343 | (define_expand "extzv" | |
3344 | [(parallel | |
3345 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3346 | (zero_extract:DI | |
3347 | (match_operand:DI 1 "register_operand" "d") | |
3348 | (match_operand 2 "const_int_operand" "") ; size | |
3349 | (match_operand 3 "const_int_operand" ""))) ; start | |
3350 | (clobber (reg:CC CC_REGNUM))])] | |
3351 | "TARGET_Z10" | |
3352 | { | |
3353 | /* Starting with zEC12 there is risbgn not clobbering CC. */ | |
3354 | if (TARGET_ZEC12) | |
3355 | { | |
3356 | emit_move_insn (operands[0], | |
3357 | gen_rtx_ZERO_EXTRACT (DImode, | |
3358 | operands[1], | |
3359 | operands[2], | |
3360 | operands[3])); | |
3361 | DONE; | |
3362 | } | |
3363 | }) | |
3364 | ||
3365 | (define_insn "*extzv<mode>_zEC12" | |
3366 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3367 | (zero_extract:GPR | |
3368 | (match_operand:GPR 1 "register_operand" "d") | |
3369 | (match_operand 2 "const_int_operand" "") ; size | |
3370 | (match_operand 3 "const_int_operand" "")))] ; start] | |
3371 | "TARGET_ZEC12" | |
3372 | "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3373 | [(set_attr "op_type" "RIE")]) | |
3374 | ||
3375 | (define_insn "*extzv<mode>_z10" | |
3376 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3377 | (zero_extract:GPR | |
3378 | (match_operand:GPR 1 "register_operand" "d") | |
3379 | (match_operand 2 "const_int_operand" "") ; size | |
3380 | (match_operand 3 "const_int_operand" ""))) ; start | |
3381 | (clobber (reg:CC CC_REGNUM))] | |
3382 | "TARGET_Z10" | |
3383 | "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3384 | [(set_attr "op_type" "RIE") | |
3385 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3386 | |
1a2e356e | 3387 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 AS |
3388 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3389 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3390 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3391 | (const_int 0))) |
ae156f85 | 3392 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3393 | "!TARGET_Z10" |
cc7ab9b7 UW |
3394 | "#" |
3395 | "&& reload_completed" | |
4023fb28 | 3396 | [(parallel |
6fa05db6 | 3397 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3398 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3399 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3400 | { |
6fa05db6 AS |
3401 | int bitsize = INTVAL (operands[2]); |
3402 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3403 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3404 | ||
3405 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3406 | set_mem_size (operands[1], size); |
2542ef05 | 3407 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3408 | operands[3] = GEN_INT (mask); |
b628bd8e | 3409 | }) |
4023fb28 | 3410 | |
1a2e356e | 3411 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 AS |
3412 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3413 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3414 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3415 | (const_int 0))) |
ae156f85 | 3416 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3417 | "" |
cc7ab9b7 UW |
3418 | "#" |
3419 | "&& reload_completed" | |
4023fb28 | 3420 | [(parallel |
6fa05db6 | 3421 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3422 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3423 | (parallel |
3424 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3425 | (clobber (reg:CC CC_REGNUM))])] | |
3426 | { | |
3427 | int bitsize = INTVAL (operands[2]); | |
3428 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3429 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3430 | ||
3431 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3432 | set_mem_size (operands[1], size); |
2542ef05 | 3433 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3434 | operands[3] = GEN_INT (mask); |
3435 | }) | |
3436 | ||
3437 | ; | |
3438 | ; insv instruction patterns | |
3439 | ; | |
3440 | ||
3441 | (define_expand "insv" | |
3442 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3443 | (match_operand 1 "const_int_operand" "") | |
3444 | (match_operand 2 "const_int_operand" "")) | |
3445 | (match_operand 3 "general_operand" ""))] | |
3446 | "" | |
4023fb28 | 3447 | { |
6fa05db6 AS |
3448 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3449 | DONE; | |
3450 | FAIL; | |
b628bd8e | 3451 | }) |
4023fb28 | 3452 | |
2542ef05 RH |
3453 | |
3454 | ; The normal RTL expansion will never generate a zero_extract where | |
3455 | ; the location operand isn't word mode. However, we do this in the | |
3456 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
22ac2c2f AK |
3457 | (define_insn "*insv<mode>_zEC12" |
3458 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3459 | (match_operand 1 "const_int_operand" "I") ; size |
3460 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f AK |
3461 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
3462 | "TARGET_ZEC12 | |
2542ef05 RH |
3463 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3464 | "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
22ac2c2f AK |
3465 | [(set_attr "op_type" "RIE")]) |
3466 | ||
963fc8d0 AK |
3467 | (define_insn "*insv<mode>_z10" |
3468 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3469 | (match_operand 1 "const_int_operand" "I") ; size |
3470 | (match_operand 2 "const_int_operand" "I")) ; pos | |
963fc8d0 AK |
3471 | (match_operand:GPR 3 "nonimmediate_operand" "d")) |
3472 | (clobber (reg:CC CC_REGNUM))] | |
3473 | "TARGET_Z10 | |
2542ef05 RH |
3474 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3475 | "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
9381e3f1 WG |
3476 | [(set_attr "op_type" "RIE") |
3477 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3478 | |
22ac2c2f AK |
3479 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3480 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3481 | (define_insn "*insv<mode>_zEC12_noshift" | |
3482 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3483 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3484 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
22ac2c2f | 3485 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 RH |
3486 | (match_operand:GPR 4 "const_int_operand" ""))))] |
3487 | "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3488 | "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
22ac2c2f AK |
3489 | [(set_attr "op_type" "RIE")]) |
3490 | ||
963fc8d0 AK |
3491 | (define_insn "*insv<mode>_z10_noshift" |
3492 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3493 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3494 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
963fc8d0 | 3495 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 | 3496 | (match_operand:GPR 4 "const_int_operand" "")))) |
963fc8d0 | 3497 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 RH |
3498 | "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3499 | "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
9381e3f1 WG |
3500 | [(set_attr "op_type" "RIE") |
3501 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3502 | |
571e408a | 3503 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 3504 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
3505 | (IXOR:GPR |
3506 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3507 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3508 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 3509 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 3510 | "TARGET_Z10" |
571e408a RH |
3511 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
3512 | [(set_attr "op_type" "RIE")]) | |
3513 | ||
3514 | (define_insn "*r<noxa>sbg_di_rotl" | |
3515 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
3516 | (IXOR:DI | |
3517 | (and:DI | |
3518 | (rotate:DI | |
3519 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
3520 | (match_operand:DI 3 "const_int_operand" "")) | |
3521 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
3522 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
3523 | (clobber (reg:CC CC_REGNUM))] | |
3524 | "TARGET_Z10" | |
3525 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
3526 | [(set_attr "op_type" "RIE")]) | |
3527 | ||
3528 | (define_insn "*r<noxa>sbg_<mode>_srl" | |
3529 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3530 | (IXOR:GPR | |
3531 | (and:GPR | |
3532 | (lshiftrt:GPR | |
3533 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3534 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3535 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3536 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3537 | (clobber (reg:CC CC_REGNUM))] | |
3538 | "TARGET_Z10 | |
3539 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
3540 | INTVAL (operands[2]))" | |
3541 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
3542 | [(set_attr "op_type" "RIE")]) | |
3543 | ||
3544 | (define_insn "*r<noxa>sbg_<mode>_sll" | |
3545 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3546 | (IXOR:GPR | |
3547 | (and:GPR | |
3548 | (ashift:GPR | |
3549 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3550 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3551 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3552 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3553 | (clobber (reg:CC CC_REGNUM))] | |
3554 | "TARGET_Z10 | |
3555 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
3556 | INTVAL (operands[2]))" | |
3557 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
3558 | [(set_attr "op_type" "RIE")]) |
3559 | ||
5bb33936 RH |
3560 | ;; These two are generated by combine for s.bf &= val. |
3561 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
3562 | ;; shifts and ands, which results in some truly awful patterns | |
3563 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
3564 | ;; Instead of | |
3565 | ;; | |
3566 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3567 | ;; (const_int 24 [0x18]) | |
3568 | ;; (const_int 0 [0])) | |
3569 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3570 | ;; (const_int 40 [0x28])) 4) | |
3571 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
3572 | ;; | |
3573 | ;; we should instead generate | |
3574 | ;; | |
3575 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3576 | ;; (const_int 24 [0x18]) | |
3577 | ;; (const_int 0 [0])) | |
3578 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3579 | ;; (const_int 40 [0x28])) | |
3580 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
3581 | ;; | |
3582 | ;; by noticing that we can push down the outer paradoxical subreg | |
3583 | ;; into the operation. | |
3584 | ||
3585 | (define_insn "*insv_rnsbg_noshift" | |
3586 | [(set (zero_extract:DI | |
3587 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3588 | (match_operand 1 "const_int_operand" "") | |
3589 | (match_operand 2 "const_int_operand" "")) | |
3590 | (and:DI | |
3591 | (match_dup 0) | |
3592 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
3593 | (clobber (reg:CC CC_REGNUM))] | |
3594 | "TARGET_Z10 | |
3595 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" | |
3596 | "rnsbg\t%0,%3,%2,63,0" | |
3597 | [(set_attr "op_type" "RIE")]) | |
3598 | ||
3599 | (define_insn "*insv_rnsbg_srl" | |
3600 | [(set (zero_extract:DI | |
3601 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3602 | (match_operand 1 "const_int_operand" "") | |
3603 | (match_operand 2 "const_int_operand" "")) | |
3604 | (and:DI | |
3605 | (lshiftrt:DI | |
3606 | (match_dup 0) | |
3607 | (match_operand 3 "const_int_operand" "")) | |
3608 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
3609 | (clobber (reg:CC CC_REGNUM))] | |
3610 | "TARGET_Z10 | |
3611 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" | |
3612 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
3613 | [(set_attr "op_type" "RIE")]) | |
3614 | ||
6fa05db6 | 3615 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 3616 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
3617 | (match_operand 1 "const_int_operand" "n,n") |
3618 | (const_int 0)) | |
9602b6a1 | 3619 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
3620 | "INTVAL (operands[1]) > 0 |
3621 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3622 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3623 | { | |
3624 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3625 | ||
3626 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 3627 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
3628 | : "stcmy\t%2,%1,%S0"; |
3629 | } | |
9381e3f1 WG |
3630 | [(set_attr "op_type" "RS,RSY") |
3631 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
3632 | |
3633 | (define_insn "*insvdi_mem_reghigh" | |
3634 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3635 | (match_operand 1 "const_int_operand" "n") | |
3636 | (const_int 0)) | |
3637 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3638 | (const_int 32)))] | |
9602b6a1 | 3639 | "TARGET_ZARCH |
6fa05db6 AS |
3640 | && INTVAL (operands[1]) > 0 |
3641 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3642 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3643 | { | |
3644 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3645 | ||
3646 | operands[1] = GEN_INT ((1ul << size) - 1); | |
3647 | return "stcmh\t%2,%1,%S0"; | |
3648 | } | |
9381e3f1 WG |
3649 | [(set_attr "op_type" "RSY") |
3650 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 3651 | |
9602b6a1 AK |
3652 | (define_insn "*insvdi_reg_imm" |
3653 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3654 | (const_int 16) | |
3655 | (match_operand 1 "const_int_operand" "n")) | |
3656 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
3657 | "TARGET_ZARCH |
3658 | && INTVAL (operands[1]) >= 0 | |
3659 | && INTVAL (operands[1]) < BITS_PER_WORD | |
3660 | && INTVAL (operands[1]) % 16 == 0" | |
3661 | { | |
3662 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3663 | { | |
3664 | case 64: return "iihh\t%0,%x2"; break; | |
3665 | case 48: return "iihl\t%0,%x2"; break; | |
3666 | case 32: return "iilh\t%0,%x2"; break; | |
3667 | case 16: return "iill\t%0,%x2"; break; | |
3668 | default: gcc_unreachable(); | |
3669 | } | |
3670 | } | |
9381e3f1 WG |
3671 | [(set_attr "op_type" "RI") |
3672 | (set_attr "z10prop" "z10_super_E1")]) | |
3673 | ||
9fec758d WG |
3674 | ; Update the left-most 32 bit of a DI. |
3675 | (define_insn "*insv_h_di_reg_extimm" | |
3676 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3677 | (const_int 32) | |
3678 | (const_int 0)) | |
3679 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3680 | "TARGET_EXTIMM" | |
3681 | "iihf\t%0,%o1" | |
3682 | [(set_attr "op_type" "RIL") | |
3683 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 3684 | |
d378b983 RH |
3685 | ; Update the right-most 32 bit of a DI. |
3686 | (define_insn "*insv_l_di_reg_extimm" | |
3687 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3688 | (const_int 32) | |
3689 | (const_int 32)) | |
3690 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3691 | "TARGET_EXTIMM" | |
3692 | "iilf\t%0,%o1" | |
9381e3f1 | 3693 | [(set_attr "op_type" "RIL") |
9fec758d | 3694 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 3695 | |
9db1d521 HP |
3696 | ; |
3697 | ; extendsidi2 instruction pattern(s). | |
3698 | ; | |
3699 | ||
4023fb28 UW |
3700 | (define_expand "extendsidi2" |
3701 | [(set (match_operand:DI 0 "register_operand" "") | |
3702 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3703 | "" | |
4023fb28 | 3704 | { |
9602b6a1 | 3705 | if (!TARGET_ZARCH) |
4023fb28 | 3706 | { |
c41c1387 | 3707 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3708 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
3709 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
3710 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
3711 | DONE; |
3712 | } | |
ec24698e | 3713 | }) |
4023fb28 UW |
3714 | |
3715 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
3716 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3717 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3718 | "TARGET_ZARCH" |
9db1d521 | 3719 | "@ |
d40c829f | 3720 | lgfr\t%0,%1 |
963fc8d0 AK |
3721 | lgf\t%0,%1 |
3722 | lgfrl\t%0,%1" | |
3723 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3724 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3725 | (set_attr "cpu_facility" "*,*,z10") |
3726 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3727 | |
9db1d521 | 3728 | ; |
56477c21 | 3729 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3730 | ; |
3731 | ||
56477c21 AS |
3732 | (define_expand "extend<HQI:mode><DSI:mode>2" |
3733 | [(set (match_operand:DSI 0 "register_operand" "") | |
3734 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 3735 | "" |
4023fb28 | 3736 | { |
9602b6a1 | 3737 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
3738 | { |
3739 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 3740 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
3741 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
3742 | DONE; | |
3743 | } | |
ec24698e | 3744 | else if (!TARGET_EXTIMM) |
4023fb28 | 3745 | { |
2542ef05 | 3746 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
3747 | |
3748 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
3749 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
3750 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
3751 | DONE; |
3752 | } | |
ec24698e UW |
3753 | }) |
3754 | ||
56477c21 AS |
3755 | ; |
3756 | ; extendhidi2 instruction pattern(s). | |
3757 | ; | |
3758 | ||
ec24698e | 3759 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
3760 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3761 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 3762 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
3763 | "@ |
3764 | lghr\t%0,%1 | |
963fc8d0 AK |
3765 | lgh\t%0,%1 |
3766 | lghrl\t%0,%1" | |
3767 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3768 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3769 | (set_attr "cpu_facility" "extimm,extimm,z10") |
3770 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
3771 | |
3772 | (define_insn "*extendhidi2" | |
9db1d521 | 3773 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 3774 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 3775 | "TARGET_ZARCH" |
d40c829f | 3776 | "lgh\t%0,%1" |
9381e3f1 WG |
3777 | [(set_attr "op_type" "RXY") |
3778 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 3779 | |
9db1d521 | 3780 | ; |
56477c21 | 3781 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
3782 | ; |
3783 | ||
ec24698e | 3784 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
3785 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3786 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
3787 | "TARGET_EXTIMM" |
3788 | "@ | |
3789 | lhr\t%0,%1 | |
3790 | lh\t%0,%1 | |
963fc8d0 AK |
3791 | lhy\t%0,%1 |
3792 | lhrl\t%0,%1" | |
3793 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
3794 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
3795 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
3796 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3797 | |
4023fb28 | 3798 | (define_insn "*extendhisi2" |
d3632d41 UW |
3799 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3800 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 3801 | "!TARGET_EXTIMM" |
d3632d41 | 3802 | "@ |
d40c829f UW |
3803 | lh\t%0,%1 |
3804 | lhy\t%0,%1" | |
9381e3f1 WG |
3805 | [(set_attr "op_type" "RX,RXY") |
3806 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3807 | |
56477c21 AS |
3808 | ; |
3809 | ; extendqi(si|di)2 instruction pattern(s). | |
3810 | ; | |
3811 | ||
43a09b63 | 3812 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
3813 | (define_insn "*extendqi<mode>2_extimm" |
3814 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3815 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3816 | "TARGET_EXTIMM" |
3817 | "@ | |
56477c21 AS |
3818 | l<g>br\t%0,%1 |
3819 | l<g>b\t%0,%1" | |
9381e3f1 WG |
3820 | [(set_attr "op_type" "RRE,RXY") |
3821 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 3822 | |
43a09b63 | 3823 | ; lb, lgb |
56477c21 AS |
3824 | (define_insn "*extendqi<mode>2" |
3825 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3826 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
3827 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
3828 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
3829 | [(set_attr "op_type" "RXY") |
3830 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 3831 | |
56477c21 AS |
3832 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
3833 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3834 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 3835 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 3836 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
3837 | "#" |
3838 | "&& reload_completed" | |
4023fb28 | 3839 | [(parallel |
56477c21 | 3840 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 3841 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 3842 | (parallel |
56477c21 | 3843 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 3844 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
3845 | { |
3846 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3847 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 3848 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 3849 | }) |
9db1d521 | 3850 | |
9db1d521 HP |
3851 | ; |
3852 | ; zero_extendsidi2 instruction pattern(s). | |
3853 | ; | |
3854 | ||
4023fb28 UW |
3855 | (define_expand "zero_extendsidi2" |
3856 | [(set (match_operand:DI 0 "register_operand" "") | |
3857 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3858 | "" | |
4023fb28 | 3859 | { |
9602b6a1 | 3860 | if (!TARGET_ZARCH) |
4023fb28 | 3861 | { |
c41c1387 | 3862 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3863 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
3864 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
3865 | DONE; |
3866 | } | |
ec24698e | 3867 | }) |
4023fb28 UW |
3868 | |
3869 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
3870 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3871 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3872 | "TARGET_ZARCH" |
9db1d521 | 3873 | "@ |
d40c829f | 3874 | llgfr\t%0,%1 |
963fc8d0 AK |
3875 | llgf\t%0,%1 |
3876 | llgfrl\t%0,%1" | |
3877 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3878 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3879 | (set_attr "cpu_facility" "*,*,z10") |
3880 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 3881 | |
288e517f AK |
3882 | ; |
3883 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
3884 | ; | |
3885 | ||
d6083c7d UW |
3886 | (define_insn "*llgt_sidi" |
3887 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3888 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3889 | (const_int 2147483647)))] |
9602b6a1 | 3890 | "TARGET_ZARCH" |
d6083c7d | 3891 | "llgt\t%0,%1" |
9381e3f1 WG |
3892 | [(set_attr "op_type" "RXE") |
3893 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
3894 | |
3895 | (define_insn_and_split "*llgt_sidi_split" | |
3896 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3897 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3898 | (const_int 2147483647))) |
ae156f85 | 3899 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3900 | "TARGET_ZARCH" |
d6083c7d UW |
3901 | "#" |
3902 | "&& reload_completed" | |
3903 | [(set (match_dup 0) | |
3904 | (and:DI (subreg:DI (match_dup 1) 0) | |
3905 | (const_int 2147483647)))] | |
3906 | "") | |
3907 | ||
288e517f AK |
3908 | (define_insn "*llgt_sisi" |
3909 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 3910 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 3911 | (const_int 2147483647)))] |
c4d50129 | 3912 | "TARGET_ZARCH" |
288e517f AK |
3913 | "@ |
3914 | llgtr\t%0,%1 | |
3915 | llgt\t%0,%1" | |
9381e3f1 WG |
3916 | [(set_attr "op_type" "RRE,RXE") |
3917 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3918 | |
288e517f AK |
3919 | (define_insn "*llgt_didi" |
3920 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3921 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
3922 | (const_int 2147483647)))] | |
9602b6a1 | 3923 | "TARGET_ZARCH" |
288e517f AK |
3924 | "@ |
3925 | llgtr\t%0,%1 | |
3926 | llgt\t%0,%N1" | |
9381e3f1 WG |
3927 | [(set_attr "op_type" "RRE,RXE") |
3928 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3929 | |
f19a9af7 | 3930 | (define_split |
9602b6a1 AK |
3931 | [(set (match_operand:DSI 0 "register_operand" "") |
3932 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 3933 | (const_int 2147483647))) |
ae156f85 | 3934 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 3935 | "TARGET_ZARCH && reload_completed" |
288e517f | 3936 | [(set (match_dup 0) |
9602b6a1 | 3937 | (and:DSI (match_dup 1) |
f6ee577c | 3938 | (const_int 2147483647)))] |
288e517f AK |
3939 | "") |
3940 | ||
9db1d521 | 3941 | ; |
56477c21 | 3942 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3943 | ; |
3944 | ||
56477c21 AS |
3945 | (define_expand "zero_extend<mode>di2" |
3946 | [(set (match_operand:DI 0 "register_operand" "") | |
3947 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3948 | "" | |
3949 | { | |
9602b6a1 | 3950 | if (!TARGET_ZARCH) |
56477c21 AS |
3951 | { |
3952 | rtx tmp = gen_reg_rtx (SImode); | |
3953 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3954 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3955 | DONE; | |
3956 | } | |
3957 | else if (!TARGET_EXTIMM) | |
3958 | { | |
2542ef05 | 3959 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
3960 | operands[1] = gen_lowpart (DImode, operands[1]); |
3961 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
3962 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
3963 | DONE; | |
3964 | } | |
3965 | }) | |
3966 | ||
f6ee577c | 3967 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 3968 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 3969 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 3970 | "" |
4023fb28 | 3971 | { |
ec24698e UW |
3972 | if (!TARGET_EXTIMM) |
3973 | { | |
3974 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 3975 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 3976 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 3977 | DONE; |
56477c21 | 3978 | } |
ec24698e UW |
3979 | }) |
3980 | ||
963fc8d0 AK |
3981 | ; llhrl, llghrl |
3982 | (define_insn "*zero_extendhi<mode>2_z10" | |
3983 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3984 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
3985 | "TARGET_Z10" | |
3986 | "@ | |
3987 | ll<g>hr\t%0,%1 | |
3988 | ll<g>h\t%0,%1 | |
3989 | ll<g>hrl\t%0,%1" | |
3990 | [(set_attr "op_type" "RXY,RRE,RIL") | |
3991 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 3992 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 3993 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 3994 | |
43a09b63 | 3995 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
3996 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
3997 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3998 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3999 | "TARGET_EXTIMM" |
4000 | "@ | |
56477c21 AS |
4001 | ll<g><hc>r\t%0,%1 |
4002 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4003 | [(set_attr "op_type" "RRE,RXY") |
4004 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4005 | |
43a09b63 | 4006 | ; llgh, llgc |
56477c21 AS |
4007 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4008 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4009 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 4010 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4011 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4012 | [(set_attr "op_type" "RXY") |
4013 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4014 | |
4015 | (define_insn_and_split "*zero_extendhisi2_31" | |
4016 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 4017 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 4018 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4019 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4020 | "#" |
4021 | "&& reload_completed" | |
4022 | [(set (match_dup 0) (const_int 0)) | |
4023 | (parallel | |
4024 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4025 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4026 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4027 | |
cc7ab9b7 UW |
4028 | (define_insn_and_split "*zero_extendqisi2_31" |
4029 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 4030 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4031 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4032 | "#" |
4033 | "&& reload_completed" | |
4034 | [(set (match_dup 0) (const_int 0)) | |
4035 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4036 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4037 | |
9db1d521 HP |
4038 | ; |
4039 | ; zero_extendqihi2 instruction pattern(s). | |
4040 | ; | |
4041 | ||
9db1d521 HP |
4042 | (define_expand "zero_extendqihi2" |
4043 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4044 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4045 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4046 | { |
4023fb28 UW |
4047 | operands[1] = gen_lowpart (HImode, operands[1]); |
4048 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4049 | DONE; | |
ec24698e | 4050 | }) |
9db1d521 | 4051 | |
4023fb28 | 4052 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4053 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 4054 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 4055 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4056 | "llgc\t%0,%1" |
9381e3f1 WG |
4057 | [(set_attr "op_type" "RXY") |
4058 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4059 | |
cc7ab9b7 UW |
4060 | (define_insn_and_split "*zero_extendqihi2_31" |
4061 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 4062 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4063 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4064 | "#" |
4065 | "&& reload_completed" | |
4066 | [(set (match_dup 0) (const_int 0)) | |
4067 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4068 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4069 | |
609e7e80 AK |
4070 | ; |
4071 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
4072 | ; | |
4073 | ||
4074 | (define_expand "fixuns_truncdddi2" | |
4075 | [(parallel | |
4076 | [(set (match_operand:DI 0 "register_operand" "") | |
4077 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
65b1d8ea AK |
4078 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) |
4079 | (clobber (reg:CC CC_REGNUM))])] | |
9381e3f1 | 4080 | |
fb068247 | 4081 | "TARGET_HARD_DFP" |
609e7e80 | 4082 | { |
65b1d8ea AK |
4083 | if (!TARGET_Z196) |
4084 | { | |
4085 | rtx label1 = gen_label_rtx (); | |
4086 | rtx label2 = gen_label_rtx (); | |
4087 | rtx temp = gen_reg_rtx (TDmode); | |
4088 | REAL_VALUE_TYPE cmp, sub; | |
4089 | ||
4090 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4091 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4092 | ||
4093 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4094 | solution is doing the check and the subtraction in TD mode and using a | |
4095 | TD -> DI convert afterwards. */ | |
4096 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4097 | temp = force_reg (TDmode, temp); | |
4098 | emit_cmp_and_jump_insns (temp, | |
4099 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
4100 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4101 | emit_insn (gen_subtd3 (temp, temp, | |
4102 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
4103 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
4104 | emit_jump (label2); | |
4105 | ||
4106 | emit_label (label1); | |
4107 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4108 | emit_label (label2); | |
4109 | DONE; | |
4110 | } | |
609e7e80 AK |
4111 | }) |
4112 | ||
4113 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
4114 | [(parallel |
4115 | [(set (match_operand:DI 0 "register_operand" "") | |
4116 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4117 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) | |
4118 | (clobber (reg:CC CC_REGNUM))])] | |
4119 | ||
fb068247 | 4120 | "TARGET_HARD_DFP" |
609e7e80 | 4121 | { |
65b1d8ea AK |
4122 | if (!TARGET_Z196) |
4123 | { | |
4124 | rtx label1 = gen_label_rtx (); | |
4125 | rtx label2 = gen_label_rtx (); | |
4126 | rtx temp = gen_reg_rtx (TDmode); | |
4127 | REAL_VALUE_TYPE cmp, sub; | |
4128 | ||
4129 | operands[1] = force_reg (TDmode, operands[1]); | |
4130 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4131 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4132 | ||
4133 | emit_cmp_and_jump_insns (operands[1], | |
4134 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
4135 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4136 | emit_insn (gen_subtd3 (temp, operands[1], | |
4137 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
4138 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
4139 | emit_jump (label2); | |
4140 | ||
4141 | emit_label (label1); | |
4142 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4143 | emit_label (label2); | |
4144 | DONE; | |
4145 | } | |
609e7e80 | 4146 | }) |
cc7ab9b7 | 4147 | |
9db1d521 | 4148 | ; |
65b1d8ea | 4149 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 4150 | ; instruction pattern(s). |
9db1d521 HP |
4151 | ; |
4152 | ||
7b6baae1 | 4153 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
4154 | [(parallel |
4155 | [(set (match_operand:GPR 0 "register_operand" "") | |
4156 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4157 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4158 | (clobber (reg:CC CC_REGNUM))])] | |
142cd70f | 4159 | "TARGET_HARD_FLOAT" |
9db1d521 | 4160 | { |
65b1d8ea AK |
4161 | if (!TARGET_Z196) |
4162 | { | |
4163 | rtx label1 = gen_label_rtx (); | |
4164 | rtx label2 = gen_label_rtx (); | |
4165 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4166 | REAL_VALUE_TYPE cmp, sub; | |
4167 | ||
4168 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
2542ef05 RH |
4169 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); |
4170 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
65b1d8ea AK |
4171 | |
4172 | emit_cmp_and_jump_insns (operands[1], | |
4173 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), | |
4174 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4175 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4176 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); | |
4177 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4178 | GEN_INT (7))); | |
4179 | emit_jump (label2); | |
4180 | ||
4181 | emit_label (label1); | |
4182 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4183 | operands[1], GEN_INT (5))); | |
4184 | emit_label (label2); | |
4185 | DONE; | |
4186 | } | |
10bbf137 | 4187 | }) |
9db1d521 | 4188 | |
65b1d8ea AK |
4189 | ; fixuns_trunc(td|dd)si2 expander |
4190 | (define_expand "fixuns_trunc<mode>si2" | |
4191 | [(parallel | |
4192 | [(set (match_operand:SI 0 "register_operand" "") | |
4193 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
4194 | (unspec:SI [(const_int 5)] UNSPEC_ROUND) | |
4195 | (clobber (reg:CC CC_REGNUM))])] | |
8540e6e8 | 4196 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4197 | "") |
4198 | ||
4199 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4200 | ||
4201 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr | |
4202 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4203 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
4204 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
4205 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4206 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4207 | (clobber (reg:CC CC_REGNUM))] | |
4208 | "TARGET_Z196" | |
4209 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" | |
4210 | [(set_attr "op_type" "RRF") | |
4211 | (set_attr "type" "ftoi")]) | |
4212 | ||
b60cb710 AK |
4213 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4214 | [(set (match_operand:GPR 0 "register_operand" "") | |
4215 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4216 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4217 | { |
b60cb710 AK |
4218 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
4219 | GEN_INT (5))); | |
9db1d521 | 4220 | DONE; |
10bbf137 | 4221 | }) |
9db1d521 | 4222 | |
43a09b63 | 4223 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
142cd70f | 4224 | (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
2f8f8434 | 4225 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7b6baae1 | 4226 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) |
2f8f8434 | 4227 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) |
ae156f85 | 4228 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4229 | "TARGET_HARD_FLOAT" |
7b6baae1 | 4230 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4231 | [(set_attr "op_type" "RRE") |
077dab3b | 4232 | (set_attr "type" "ftoi")]) |
9db1d521 | 4233 | |
609e7e80 AK |
4234 | |
4235 | ; | |
4236 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4237 | ; | |
4238 | ||
99cd7dd0 AK |
4239 | (define_expand "fix_trunc<mode>di2" |
4240 | [(set (match_operand:DI 0 "register_operand" "") | |
4241 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4242 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4243 | { |
4244 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4245 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
4246 | GEN_INT (9))); | |
4247 | DONE; | |
4248 | }) | |
4249 | ||
609e7e80 | 4250 | ; cgxtr, cgdtr |
99cd7dd0 | 4251 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4252 | [(set (match_operand:DI 0 "register_operand" "=d") |
4253 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4254 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4255 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4256 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4257 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4258 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4259 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4260 | |
4261 | ||
f61a2c7d AK |
4262 | ; |
4263 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4264 | ; | |
4265 | ||
4266 | (define_expand "fix_trunctf<mode>2" | |
4267 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4268 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
4269 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4270 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 4271 | "TARGET_HARD_FLOAT" |
142cd70f | 4272 | "") |
9db1d521 | 4273 | |
9db1d521 | 4274 | |
9db1d521 | 4275 | ; |
142cd70f | 4276 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4277 | ; |
4278 | ||
609e7e80 | 4279 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4280 | (define_insn "floatdi<mode>2" |
609e7e80 AK |
4281 | [(set (match_operand:FP 0 "register_operand" "=f") |
4282 | (float:FP (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 4283 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
609e7e80 | 4284 | "c<xde>g<bt>r\t%0,%1" |
9db1d521 | 4285 | [(set_attr "op_type" "RRE") |
9381e3f1 | 4286 | (set_attr "type" "itof<mode>" )]) |
9db1d521 | 4287 | |
43a09b63 | 4288 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4289 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4290 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4291 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4292 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4293 | "c<xde>fbr\t%0,%1" |
4294 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4295 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4296 | |
65b1d8ea AK |
4297 | ; cxftr, cdftr |
4298 | (define_insn "floatsi<mode>2" | |
4299 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4300 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4301 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4302 | "c<xde>ftr\t%0,0,%1,0" | |
4303 | [(set_attr "op_type" "RRE") | |
4304 | (set_attr "type" "itof<mode>" )]) | |
4305 | ||
4306 | ; | |
4307 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4308 | ; | |
4309 | ||
4310 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr | |
4311 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
4312 | (define_insn "floatuns<GPR:mode><FP:mode>2" | |
4313 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4314 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4315 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4316 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" | |
4317 | [(set_attr "op_type" "RRE") | |
4318 | (set_attr "type" "itof<FP:mode>" )]) | |
f61a2c7d | 4319 | |
9db1d521 HP |
4320 | ; |
4321 | ; truncdfsf2 instruction pattern(s). | |
4322 | ; | |
4323 | ||
142cd70f | 4324 | (define_insn "truncdfsf2" |
9db1d521 | 4325 | [(set (match_operand:SF 0 "register_operand" "=f") |
a036c6f7 | 4326 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
142cd70f | 4327 | "TARGET_HARD_FLOAT" |
d40c829f | 4328 | "ledbr\t%0,%1" |
f61a2c7d AK |
4329 | [(set_attr "op_type" "RRE") |
4330 | (set_attr "type" "ftruncdf")]) | |
9db1d521 | 4331 | |
f61a2c7d | 4332 | ; |
142cd70f | 4333 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4334 | ; |
4335 | ||
142cd70f AK |
4336 | ; ldxbr, lexbr |
4337 | (define_insn "trunctf<mode>2" | |
4338 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4339 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4340 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4341 | "TARGET_HARD_FLOAT" |
4342 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4343 | [(set_attr "length" "6") |
9381e3f1 | 4344 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4345 | |
609e7e80 AK |
4346 | ; |
4347 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4348 | ; | |
4349 | ||
4350 | (define_insn "trunctddd2" | |
4351 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
4352 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4353 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4354 | "TARGET_HARD_DFP" |
bf259a77 AK |
4355 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4356 | [(set_attr "length" "6") | |
9381e3f1 | 4357 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4358 | |
4359 | (define_insn "truncddsd2" | |
4360 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4361 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4362 | "TARGET_HARD_DFP" |
609e7e80 AK |
4363 | "ledtr\t%0,0,%1,0" |
4364 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4365 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4366 | |
9db1d521 | 4367 | ; |
142cd70f | 4368 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4369 | ; |
4370 | ||
142cd70f AK |
4371 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
4372 | (define_insn "extend<DSF:mode><BFP:mode>2" | |
4373 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
4374 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] | |
4375 | "TARGET_HARD_FLOAT | |
4376 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)" | |
f61a2c7d | 4377 | "@ |
142cd70f AK |
4378 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4379 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
f61a2c7d | 4380 | [(set_attr "op_type" "RRE,RXE") |
142cd70f | 4381 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) |
f61a2c7d | 4382 | |
609e7e80 AK |
4383 | ; |
4384 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4385 | ; | |
4386 | ||
4387 | (define_insn "extendddtd2" | |
4388 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4389 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4390 | "TARGET_HARD_DFP" |
609e7e80 AK |
4391 | "lxdtr\t%0,%1,0" |
4392 | [(set_attr "op_type" "RRF") | |
4393 | (set_attr "type" "fsimptf")]) | |
4394 | ||
4395 | (define_insn "extendsddd2" | |
4396 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4397 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4398 | "TARGET_HARD_DFP" |
609e7e80 AK |
4399 | "ldetr\t%0,%1,0" |
4400 | [(set_attr "op_type" "RRF") | |
4401 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4402 | |
35dd9a0e AK |
4403 | ; Binary <-> Decimal floating point trunc patterns |
4404 | ; | |
4405 | ||
4406 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4407 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4408 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4409 | (use (reg:SI GPR0_REGNUM)) | |
4410 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4411 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4412 | "pfpo") |
4413 | ||
4414 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4415 | [(set (reg:BFP FPR0_REGNUM) | |
4416 | (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4417 | (use (reg:SI GPR0_REGNUM)) | |
4418 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4419 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4420 | "pfpo") |
4421 | ||
4422 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
4423 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4424 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4425 | (parallel | |
4426 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4427 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4428 | (use (reg:SI GPR0_REGNUM)) | |
4429 | (clobber (reg:CC CC_REGNUM))]) | |
4430 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4431 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4432 | "TARGET_HARD_DFP |
35dd9a0e AK |
4433 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4434 | { | |
4435 | HOST_WIDE_INT flags; | |
4436 | ||
4437 | flags = (PFPO_CONVERT | | |
4438 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4439 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4440 | ||
4441 | operands[2] = GEN_INT (flags); | |
4442 | }) | |
4443 | ||
4444 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
4445 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4446 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4447 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4448 | (parallel | |
4449 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4450 | (use (reg:SI GPR0_REGNUM)) | |
4451 | (clobber (reg:CC CC_REGNUM))]) | |
4452 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4453 | "TARGET_HARD_DFP |
35dd9a0e AK |
4454 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
4455 | { | |
4456 | HOST_WIDE_INT flags; | |
4457 | ||
4458 | flags = (PFPO_CONVERT | | |
4459 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4460 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4461 | ||
4462 | operands[2] = GEN_INT (flags); | |
4463 | }) | |
4464 | ||
4465 | ; | |
4466 | ; Binary <-> Decimal floating point extend patterns | |
4467 | ; | |
4468 | ||
4469 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
4470 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4471 | (use (reg:SI GPR0_REGNUM)) | |
4472 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4473 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4474 | "pfpo") |
4475 | ||
4476 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
4477 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4478 | (use (reg:SI GPR0_REGNUM)) | |
4479 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4480 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4481 | "pfpo") |
4482 | ||
4483 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
4484 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4485 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4486 | (parallel | |
4487 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4488 | (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4489 | (use (reg:SI GPR0_REGNUM)) | |
4490 | (clobber (reg:CC CC_REGNUM))]) | |
4491 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4492 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4493 | "TARGET_HARD_DFP |
35dd9a0e AK |
4494 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4495 | { | |
4496 | HOST_WIDE_INT flags; | |
4497 | ||
4498 | flags = (PFPO_CONVERT | | |
4499 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4500 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4501 | ||
4502 | operands[2] = GEN_INT (flags); | |
4503 | }) | |
4504 | ||
4505 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
4506 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4507 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4508 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4509 | (parallel | |
4510 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4511 | (use (reg:SI GPR0_REGNUM)) | |
4512 | (clobber (reg:CC CC_REGNUM))]) | |
4513 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4514 | "TARGET_HARD_DFP |
35dd9a0e AK |
4515 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
4516 | { | |
4517 | HOST_WIDE_INT flags; | |
4518 | ||
4519 | flags = (PFPO_CONVERT | | |
4520 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4521 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4522 | ||
4523 | operands[2] = GEN_INT (flags); | |
4524 | }) | |
4525 | ||
4526 | ||
9db1d521 | 4527 | ;; |
fae778eb | 4528 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 4529 | ;; |
fae778eb | 4530 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
4531 | ; because of unpredictable Bits in Register for Halfword and Byte |
4532 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
4533 | ||
07893d4f UW |
4534 | ;; |
4535 | ;;- Add instructions. | |
4536 | ;; | |
4537 | ||
1c7b1b7e UW |
4538 | ; |
4539 | ; addti3 instruction pattern(s). | |
4540 | ; | |
4541 | ||
4542 | (define_insn_and_split "addti3" | |
4543 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4544 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
4545 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4546 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4547 | "TARGET_ZARCH" |
1c7b1b7e UW |
4548 | "#" |
4549 | "&& reload_completed" | |
4550 | [(parallel | |
ae156f85 | 4551 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
4552 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
4553 | (match_dup 7))) | |
4554 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
4555 | (parallel | |
a94a76a7 UW |
4556 | [(set (match_dup 3) (plus:DI |
4557 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4558 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4559 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
4560 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4561 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4562 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4563 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4564 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4565 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4566 | |
07893d4f UW |
4567 | ; |
4568 | ; adddi3 instruction pattern(s). | |
4569 | ; | |
4570 | ||
3298c037 AK |
4571 | (define_expand "adddi3" |
4572 | [(parallel | |
963fc8d0 | 4573 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
4574 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
4575 | (match_operand:DI 2 "general_operand" ""))) | |
4576 | (clobber (reg:CC CC_REGNUM))])] | |
4577 | "" | |
4578 | "") | |
4579 | ||
07893d4f UW |
4580 | (define_insn "*adddi3_sign" |
4581 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4582 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4583 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4584 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4585 | "TARGET_ZARCH" |
07893d4f | 4586 | "@ |
d40c829f UW |
4587 | agfr\t%0,%2 |
4588 | agf\t%0,%2" | |
65b1d8ea AK |
4589 | [(set_attr "op_type" "RRE,RXY") |
4590 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
4591 | |
4592 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 4593 | [(set (reg CC_REGNUM) |
fb492564 | 4594 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4595 | (match_operand:DI 1 "register_operand" "0,0")) |
4596 | (const_int 0))) | |
4597 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4598 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 4599 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4600 | "@ |
d40c829f UW |
4601 | algfr\t%0,%2 |
4602 | algf\t%0,%2" | |
9381e3f1 WG |
4603 | [(set_attr "op_type" "RRE,RXY") |
4604 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4605 | |
4606 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 4607 | [(set (reg CC_REGNUM) |
fb492564 | 4608 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4609 | (match_operand:DI 1 "register_operand" "0,0")) |
4610 | (const_int 0))) | |
4611 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 4612 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4613 | "@ |
d40c829f UW |
4614 | algfr\t%0,%2 |
4615 | algf\t%0,%2" | |
9381e3f1 WG |
4616 | [(set_attr "op_type" "RRE,RXY") |
4617 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4618 | |
4619 | (define_insn "*adddi3_zero" | |
4620 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4621 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4622 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4623 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4624 | "TARGET_ZARCH" |
07893d4f | 4625 | "@ |
d40c829f UW |
4626 | algfr\t%0,%2 |
4627 | algf\t%0,%2" | |
9381e3f1 WG |
4628 | [(set_attr "op_type" "RRE,RXY") |
4629 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 4630 | |
e69166de | 4631 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 4632 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
4633 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
4634 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4635 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4636 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
4637 | "#" |
4638 | "&& reload_completed" | |
4639 | [(parallel | |
ae156f85 | 4640 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
4641 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4642 | (match_dup 7))) | |
4643 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4644 | (parallel | |
a94a76a7 UW |
4645 | [(set (match_dup 3) (plus:SI |
4646 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4647 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4648 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
4649 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4650 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4651 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4652 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4653 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4654 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4655 | |
07893d4f | 4656 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 4657 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 4658 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 4659 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4660 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4661 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4662 | "#" |
4663 | "&& reload_completed" | |
4664 | [(parallel | |
4665 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4666 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4667 | (parallel |
ae156f85 | 4668 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
4669 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4670 | (match_dup 7))) | |
4671 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4672 | (set (pc) | |
ae156f85 | 4673 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4674 | (pc) |
4675 | (label_ref (match_dup 9)))) | |
4676 | (parallel | |
4677 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 4678 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4679 | (match_dup 9)] |
97c6f7ad UW |
4680 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4681 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4682 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4683 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4684 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4685 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4686 | operands[9] = gen_label_rtx ();") |
9db1d521 | 4687 | |
3298c037 AK |
4688 | ; |
4689 | ; addsi3 instruction pattern(s). | |
4690 | ; | |
4691 | ||
4692 | (define_expand "addsi3" | |
07893d4f | 4693 | [(parallel |
963fc8d0 | 4694 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
4695 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
4696 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4697 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4698 | "" |
07893d4f | 4699 | "") |
9db1d521 | 4700 | |
3298c037 AK |
4701 | (define_insn "*addsi3_sign" |
4702 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4703 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
4704 | (match_operand:SI 1 "register_operand" "0,0"))) | |
4705 | (clobber (reg:CC CC_REGNUM))] | |
4706 | "" | |
4707 | "@ | |
4708 | ah\t%0,%2 | |
4709 | ahy\t%0,%2" | |
65b1d8ea AK |
4710 | [(set_attr "op_type" "RX,RXY") |
4711 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 4712 | |
9db1d521 | 4713 | ; |
3298c037 | 4714 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 4715 | ; |
9db1d521 | 4716 | |
65b1d8ea | 4717 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 4718 | (define_insn "*add<mode>3" |
65b1d8ea AK |
4719 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
4720 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
4721 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
4722 | (clobber (reg:CC CC_REGNUM))] |
4723 | "" | |
ec24698e | 4724 | "@ |
3298c037 | 4725 | a<g>r\t%0,%2 |
65b1d8ea | 4726 | a<g>rk\t%0,%1,%2 |
3298c037 | 4727 | a<g>hi\t%0,%h2 |
65b1d8ea | 4728 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
4729 | al<g>fi\t%0,%2 |
4730 | sl<g>fi\t%0,%n2 | |
4731 | a<g>\t%0,%2 | |
963fc8d0 AK |
4732 | a<y>\t%0,%2 |
4733 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4734 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
4735 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
4736 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4737 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 4738 | |
65b1d8ea | 4739 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 4740 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 4741 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4742 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
4743 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 4744 | (match_dup 1))) |
65b1d8ea | 4745 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 4746 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4747 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4748 | "@ |
3298c037 | 4749 | al<g>r\t%0,%2 |
65b1d8ea | 4750 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4751 | al<g>fi\t%0,%2 |
4752 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4753 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4754 | al<g>\t%0,%2 |
963fc8d0 AK |
4755 | al<y>\t%0,%2 |
4756 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4757 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4758 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4759 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4760 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4761 | |
65b1d8ea | 4762 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4763 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 4764 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4765 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4766 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4767 | (match_dup 1))) |
65b1d8ea | 4768 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4769 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4770 | "@ |
3298c037 | 4771 | al<g>r\t%0,%2 |
65b1d8ea | 4772 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4773 | al<g>\t%0,%2 |
4774 | al<y>\t%0,%2" | |
65b1d8ea AK |
4775 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4776 | (set_attr "cpu_facility" "*,z196,*,*") | |
4777 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4778 | |
65b1d8ea | 4779 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4780 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 4781 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4782 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4783 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 4784 | (match_dup 2))) |
65b1d8ea | 4785 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4786 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4787 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4788 | "@ |
3298c037 | 4789 | al<g>r\t%0,%2 |
65b1d8ea | 4790 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4791 | al<g>fi\t%0,%2 |
4792 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4793 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4794 | al<g>\t%0,%2 |
963fc8d0 AK |
4795 | al<y>\t%0,%2 |
4796 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4797 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4798 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4799 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4800 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4801 | |
65b1d8ea | 4802 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4803 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 4804 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4805 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4806 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4807 | (match_dup 2))) |
65b1d8ea | 4808 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4809 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4810 | "@ |
3298c037 | 4811 | al<g>r\t%0,%2 |
65b1d8ea | 4812 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4813 | al<g>\t%0,%2 |
4814 | al<y>\t%0,%2" | |
65b1d8ea AK |
4815 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4816 | (set_attr "cpu_facility" "*,z196,*,*") | |
4817 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4818 | |
65b1d8ea | 4819 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4820 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4821 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4822 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4823 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 4824 | (const_int 0))) |
65b1d8ea | 4825 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4826 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4827 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4828 | "@ |
3298c037 | 4829 | al<g>r\t%0,%2 |
65b1d8ea | 4830 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4831 | al<g>fi\t%0,%2 |
4832 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4833 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4834 | al<g>\t%0,%2 |
963fc8d0 AK |
4835 | al<y>\t%0,%2 |
4836 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4837 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4838 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4839 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4840 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4841 | |
65b1d8ea | 4842 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4843 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4844 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4845 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4846 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 4847 | (const_int 0))) |
65b1d8ea | 4848 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4849 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4850 | "@ |
3298c037 | 4851 | al<g>r\t%0,%2 |
65b1d8ea | 4852 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4853 | al<g>\t%0,%2 |
4854 | al<y>\t%0,%2" | |
65b1d8ea AK |
4855 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4856 | (set_attr "cpu_facility" "*,z196,*,*") | |
4857 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4858 | |
65b1d8ea | 4859 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4860 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 4861 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4862 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4863 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
4864 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 4865 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 4866 | "@ |
3298c037 | 4867 | al<g>r\t%0,%2 |
65b1d8ea | 4868 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4869 | al<g>\t%0,%2 |
4870 | al<y>\t%0,%2" | |
65b1d8ea AK |
4871 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4872 | (set_attr "cpu_facility" "*,z196,*,*") | |
4873 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4874 | |
963fc8d0 | 4875 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
4876 | (define_insn "*add<mode>3_imm_cc" |
4877 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
4878 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
4879 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 4880 | (const_int 0))) |
65b1d8ea | 4881 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
4882 | (plus:GPR (match_dup 1) (match_dup 2)))] |
4883 | "s390_match_ccmode (insn, CCAmode) | |
4884 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
4885 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
4886 | /* Avoid INT32_MIN on 32 bit. */ | |
4887 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 4888 | "@ |
3298c037 | 4889 | a<g>hi\t%0,%h2 |
65b1d8ea | 4890 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
4891 | a<g>fi\t%0,%2 |
4892 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4893 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
4894 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
4895 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4896 | |
9db1d521 | 4897 | ; |
609e7e80 | 4898 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4899 | ; |
4900 | ||
609e7e80 | 4901 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
142cd70f | 4902 | (define_insn "add<mode>3" |
609e7e80 AK |
4903 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4904 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4905 | (match_operand:FP 2 "general_operand" " f,<Rf>"))) | |
ae156f85 | 4906 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4907 | "TARGET_HARD_FLOAT" |
9db1d521 | 4908 | "@ |
609e7e80 | 4909 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4910 | a<xde>b\t%0,%2" |
609e7e80 | 4911 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4912 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4913 | |
609e7e80 | 4914 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4915 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4916 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4917 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4918 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4919 | (match_operand:FP 3 "const0_operand" ""))) | |
4920 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
4921 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 4922 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4923 | "@ |
609e7e80 | 4924 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4925 | a<xde>b\t%0,%2" |
609e7e80 | 4926 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4927 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4928 | |
609e7e80 | 4929 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4930 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4931 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4932 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4933 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4934 | (match_operand:FP 3 "const0_operand" ""))) | |
4935 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 4936 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4937 | "@ |
609e7e80 | 4938 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4939 | a<xde>b\t%0,%2" |
609e7e80 | 4940 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4941 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4942 | |
9db1d521 HP |
4943 | |
4944 | ;; | |
4945 | ;;- Subtract instructions. | |
4946 | ;; | |
4947 | ||
1c7b1b7e UW |
4948 | ; |
4949 | ; subti3 instruction pattern(s). | |
4950 | ; | |
4951 | ||
4952 | (define_insn_and_split "subti3" | |
4953 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4954 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
4955 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4956 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4957 | "TARGET_ZARCH" |
1c7b1b7e UW |
4958 | "#" |
4959 | "&& reload_completed" | |
4960 | [(parallel | |
ae156f85 | 4961 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
4962 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
4963 | (match_dup 7))) | |
4964 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
4965 | (parallel | |
4966 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4967 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4968 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
4969 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4970 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4971 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4972 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4973 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4974 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4975 | |
9db1d521 HP |
4976 | ; |
4977 | ; subdi3 instruction pattern(s). | |
4978 | ; | |
4979 | ||
3298c037 AK |
4980 | (define_expand "subdi3" |
4981 | [(parallel | |
4982 | [(set (match_operand:DI 0 "register_operand" "") | |
4983 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4984 | (match_operand:DI 2 "general_operand" ""))) | |
4985 | (clobber (reg:CC CC_REGNUM))])] | |
4986 | "" | |
4987 | "") | |
4988 | ||
07893d4f UW |
4989 | (define_insn "*subdi3_sign" |
4990 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4991 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4992 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4993 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4994 | "TARGET_ZARCH" |
07893d4f | 4995 | "@ |
d40c829f UW |
4996 | sgfr\t%0,%2 |
4997 | sgf\t%0,%2" | |
9381e3f1 | 4998 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
4999 | (set_attr "z10prop" "z10_c,*") |
5000 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
5001 | |
5002 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 5003 | [(set (reg CC_REGNUM) |
07893d4f | 5004 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5005 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5006 | (const_int 0))) |
5007 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5008 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 5009 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5010 | "@ |
d40c829f UW |
5011 | slgfr\t%0,%2 |
5012 | slgf\t%0,%2" | |
9381e3f1 WG |
5013 | [(set_attr "op_type" "RRE,RXY") |
5014 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5015 | |
5016 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 5017 | [(set (reg CC_REGNUM) |
07893d4f | 5018 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5019 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5020 | (const_int 0))) |
5021 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5022 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5023 | "@ |
d40c829f UW |
5024 | slgfr\t%0,%2 |
5025 | slgf\t%0,%2" | |
9381e3f1 WG |
5026 | [(set_attr "op_type" "RRE,RXY") |
5027 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5028 | |
5029 | (define_insn "*subdi3_zero" | |
5030 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5031 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5032 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5033 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5034 | "TARGET_ZARCH" |
07893d4f | 5035 | "@ |
d40c829f UW |
5036 | slgfr\t%0,%2 |
5037 | slgf\t%0,%2" | |
9381e3f1 WG |
5038 | [(set_attr "op_type" "RRE,RXY") |
5039 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 5040 | |
e69166de UW |
5041 | (define_insn_and_split "*subdi3_31z" |
5042 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5043 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
5044 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5045 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5046 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5047 | "#" |
5048 | "&& reload_completed" | |
5049 | [(parallel | |
ae156f85 | 5050 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
5051 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5052 | (match_dup 7))) | |
5053 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5054 | (parallel | |
5055 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5056 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5057 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
5058 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5059 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5060 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5061 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5062 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5063 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5064 | |
07893d4f UW |
5065 | (define_insn_and_split "*subdi3_31" |
5066 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5067 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 5068 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5069 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5070 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5071 | "#" |
5072 | "&& reload_completed" | |
5073 | [(parallel | |
5074 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5075 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5076 | (parallel |
ae156f85 | 5077 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
5078 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5079 | (match_dup 7))) | |
5080 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5081 | (set (pc) | |
ae156f85 | 5082 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5083 | (pc) |
5084 | (label_ref (match_dup 9)))) | |
5085 | (parallel | |
5086 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 5087 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5088 | (match_dup 9)] |
97c6f7ad UW |
5089 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5090 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5091 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5092 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5093 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5094 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5095 | operands[9] = gen_label_rtx ();") |
07893d4f | 5096 | |
3298c037 AK |
5097 | ; |
5098 | ; subsi3 instruction pattern(s). | |
5099 | ; | |
5100 | ||
5101 | (define_expand "subsi3" | |
07893d4f | 5102 | [(parallel |
3298c037 AK |
5103 | [(set (match_operand:SI 0 "register_operand" "") |
5104 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
5105 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5106 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5107 | "" |
07893d4f | 5108 | "") |
9db1d521 | 5109 | |
3298c037 AK |
5110 | (define_insn "*subsi3_sign" |
5111 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5112 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
5113 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
5114 | (clobber (reg:CC CC_REGNUM))] | |
5115 | "" | |
5116 | "@ | |
5117 | sh\t%0,%2 | |
5118 | shy\t%0,%2" | |
65b1d8ea AK |
5119 | [(set_attr "op_type" "RX,RXY") |
5120 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5121 | |
9db1d521 | 5122 | ; |
3298c037 | 5123 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
5124 | ; |
5125 | ||
65b1d8ea | 5126 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 5127 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
5128 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
5129 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
5130 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
5131 | (clobber (reg:CC CC_REGNUM))] |
5132 | "" | |
5133 | "@ | |
5134 | s<g>r\t%0,%2 | |
65b1d8ea | 5135 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
5136 | s<g>\t%0,%2 |
5137 | s<y>\t%0,%2" | |
65b1d8ea AK |
5138 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5139 | (set_attr "cpu_facility" "*,z196,*,*") | |
5140 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 5141 | |
65b1d8ea | 5142 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5143 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 5144 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5145 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5146 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5147 | (match_dup 1))) |
65b1d8ea | 5148 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5149 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5150 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5151 | "@ |
3298c037 | 5152 | sl<g>r\t%0,%2 |
65b1d8ea | 5153 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5154 | sl<g>\t%0,%2 |
5155 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5156 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5157 | (set_attr "cpu_facility" "*,z196,*,*") | |
5158 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5159 | |
65b1d8ea | 5160 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5161 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 5162 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5163 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5164 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5165 | (match_dup 1))) |
65b1d8ea | 5166 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5167 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5168 | "@ |
3298c037 | 5169 | sl<g>r\t%0,%2 |
65b1d8ea | 5170 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5171 | sl<g>\t%0,%2 |
5172 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5173 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5174 | (set_attr "cpu_facility" "*,z196,*,*") | |
5175 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5176 | |
65b1d8ea | 5177 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5178 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5179 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5180 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5181 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5182 | (const_int 0))) |
65b1d8ea | 5183 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5184 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5185 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5186 | "@ |
3298c037 | 5187 | sl<g>r\t%0,%2 |
65b1d8ea | 5188 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5189 | sl<g>\t%0,%2 |
5190 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5191 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5192 | (set_attr "cpu_facility" "*,z196,*,*") | |
5193 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5194 | |
65b1d8ea | 5195 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5196 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5197 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5198 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5199 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5200 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5201 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5202 | "s390_match_ccmode (insn, CCL3mode)" |
5203 | "@ | |
3298c037 | 5204 | sl<g>r\t%0,%2 |
65b1d8ea | 5205 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5206 | sl<g>\t%0,%2 |
5207 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5208 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5209 | (set_attr "cpu_facility" "*,z196,*,*") | |
5210 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5211 | |
65b1d8ea | 5212 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5213 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5214 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5215 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5216 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5217 | (const_int 0))) |
65b1d8ea | 5218 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5219 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5220 | "@ |
3298c037 | 5221 | sl<g>r\t%0,%2 |
65b1d8ea | 5222 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5223 | sl<g>\t%0,%2 |
5224 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5225 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5226 | (set_attr "cpu_facility" "*,z196,*,*") | |
5227 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5228 | |
9db1d521 | 5229 | |
65b1d8ea | 5230 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5231 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5232 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5233 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5234 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5235 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5236 | "s390_match_ccmode (insn, CCL3mode)" |
5237 | "@ | |
3298c037 | 5238 | sl<g>r\t%0,%2 |
65b1d8ea | 5239 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5240 | sl<g>\t%0,%2 |
5241 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5242 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5243 | (set_attr "cpu_facility" "*,z196,*,*") | |
5244 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5245 | |
9db1d521 HP |
5246 | |
5247 | ; | |
609e7e80 | 5248 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5249 | ; |
5250 | ||
d46f24b6 | 5251 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5252 | (define_insn "sub<mode>3" |
609e7e80 AK |
5253 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
5254 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
142cd70f | 5255 | (match_operand:FP 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 5256 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5257 | "TARGET_HARD_FLOAT" |
9db1d521 | 5258 | "@ |
609e7e80 | 5259 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5260 | s<xde>b\t%0,%2" |
609e7e80 | 5261 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5262 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5263 | |
d46f24b6 | 5264 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5265 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5266 | [(set (reg CC_REGNUM) |
609e7e80 | 5267 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 5268 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
5269 | (match_operand:FP 3 "const0_operand" ""))) |
5270 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5271 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5272 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5273 | "@ |
609e7e80 | 5274 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5275 | s<xde>b\t%0,%2" |
609e7e80 | 5276 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5277 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5278 | |
d46f24b6 | 5279 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5280 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5281 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5282 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
5283 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
5284 | (match_operand:FP 3 "const0_operand" ""))) | |
5285 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5286 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5287 | "@ |
609e7e80 | 5288 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5289 | s<xde>b\t%0,%2" |
609e7e80 | 5290 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5291 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5292 | |
9db1d521 | 5293 | |
e69166de UW |
5294 | ;; |
5295 | ;;- Conditional add/subtract instructions. | |
5296 | ;; | |
5297 | ||
5298 | ; | |
9a91a21f | 5299 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
5300 | ; |
5301 | ||
a996720c UW |
5302 | ; the following 4 patterns are used when the result of an add with |
5303 | ; carry is checked for an overflow condition | |
5304 | ||
5305 | ; op1 + op2 + c < op1 | |
5306 | ||
5307 | ; alcr, alc, alcgr, alcg | |
5308 | (define_insn "*add<mode>3_alc_carry1_cc" | |
5309 | [(set (reg CC_REGNUM) | |
5310 | (compare | |
5311 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5312 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5313 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5314 | (match_dup 1))) |
5315 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5316 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5317 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5318 | "@ | |
5319 | alc<g>r\t%0,%2 | |
5320 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5321 | [(set_attr "op_type" "RRE,RXY") |
5322 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5323 | |
5324 | ; alcr, alc, alcgr, alcg | |
5325 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
5326 | [(set (reg CC_REGNUM) | |
5327 | (compare | |
5328 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5329 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5330 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5331 | (match_dup 1))) |
5332 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5333 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5334 | "@ | |
5335 | alc<g>r\t%0,%2 | |
5336 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5337 | [(set_attr "op_type" "RRE,RXY") |
5338 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5339 | |
5340 | ; op1 + op2 + c < op2 | |
5341 | ||
5342 | ; alcr, alc, alcgr, alcg | |
5343 | (define_insn "*add<mode>3_alc_carry2_cc" | |
5344 | [(set (reg CC_REGNUM) | |
5345 | (compare | |
5346 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5347 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5348 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5349 | (match_dup 2))) |
5350 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5351 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5352 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5353 | "@ | |
5354 | alc<g>r\t%0,%2 | |
5355 | alc<g>\t%0,%2" | |
5356 | [(set_attr "op_type" "RRE,RXY")]) | |
5357 | ||
5358 | ; alcr, alc, alcgr, alcg | |
5359 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
5360 | [(set (reg CC_REGNUM) | |
5361 | (compare | |
5362 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5363 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5364 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5365 | (match_dup 2))) |
5366 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5367 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5368 | "@ | |
5369 | alc<g>r\t%0,%2 | |
5370 | alc<g>\t%0,%2" | |
5371 | [(set_attr "op_type" "RRE,RXY")]) | |
5372 | ||
43a09b63 | 5373 | ; alcr, alc, alcgr, alcg |
9a91a21f | 5374 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 5375 | [(set (reg CC_REGNUM) |
e69166de | 5376 | (compare |
a94a76a7 UW |
5377 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5378 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5379 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 5380 | (const_int 0))) |
9a91a21f | 5381 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 5382 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 5383 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5384 | "@ |
9a91a21f AS |
5385 | alc<g>r\t%0,%2 |
5386 | alc<g>\t%0,%2" | |
e69166de UW |
5387 | [(set_attr "op_type" "RRE,RXY")]) |
5388 | ||
43a09b63 | 5389 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
5390 | (define_insn "*add<mode>3_alc" |
5391 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
5392 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5393 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5394 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 5395 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5396 | "TARGET_CPU_ZARCH" |
e69166de | 5397 | "@ |
9a91a21f AS |
5398 | alc<g>r\t%0,%2 |
5399 | alc<g>\t%0,%2" | |
e69166de UW |
5400 | [(set_attr "op_type" "RRE,RXY")]) |
5401 | ||
43a09b63 | 5402 | ; slbr, slb, slbgr, slbg |
9a91a21f | 5403 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 5404 | [(set (reg CC_REGNUM) |
e69166de | 5405 | (compare |
9a91a21f | 5406 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 5407 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5408 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 5409 | (const_int 0))) |
9a91a21f AS |
5410 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
5411 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 5412 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5413 | "@ |
9a91a21f AS |
5414 | slb<g>r\t%0,%2 |
5415 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5416 | [(set_attr "op_type" "RRE,RXY") |
5417 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5418 | |
43a09b63 | 5419 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
5420 | (define_insn "*sub<mode>3_slb" |
5421 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5422 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 5423 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5424 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 5425 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5426 | "TARGET_CPU_ZARCH" |
e69166de | 5427 | "@ |
9a91a21f AS |
5428 | slb<g>r\t%0,%2 |
5429 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5430 | [(set_attr "op_type" "RRE,RXY") |
5431 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5432 | |
9a91a21f AS |
5433 | (define_expand "add<mode>cc" |
5434 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 5435 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
5436 | (match_operand:GPR 2 "register_operand" "") |
5437 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 5438 | "TARGET_CPU_ZARCH" |
9381e3f1 | 5439 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 5440 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 5441 | operands[0], operands[2], |
5d880bd2 UW |
5442 | operands[3])) FAIL; DONE;") |
5443 | ||
5444 | ; | |
5445 | ; scond instruction pattern(s). | |
5446 | ; | |
5447 | ||
9a91a21f AS |
5448 | (define_insn_and_split "*scond<mode>" |
5449 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5450 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 5451 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5452 | "TARGET_CPU_ZARCH" |
5453 | "#" | |
5454 | "&& reload_completed" | |
5455 | [(set (match_dup 0) (const_int 0)) | |
5456 | (parallel | |
a94a76a7 UW |
5457 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
5458 | (match_dup 0))) | |
ae156f85 | 5459 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5460 | "") |
5d880bd2 | 5461 | |
9a91a21f AS |
5462 | (define_insn_and_split "*scond<mode>_neg" |
5463 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5464 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 5465 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5466 | "TARGET_CPU_ZARCH" |
5467 | "#" | |
5468 | "&& reload_completed" | |
5469 | [(set (match_dup 0) (const_int 0)) | |
5470 | (parallel | |
9a91a21f AS |
5471 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
5472 | (match_dup 1))) | |
ae156f85 | 5473 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 5474 | (parallel |
9a91a21f | 5475 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 5476 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5477 | "") |
5d880bd2 | 5478 | |
5d880bd2 | 5479 | |
f90b7a5a | 5480 | (define_expand "cstore<mode>4" |
9a91a21f | 5481 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
5482 | (match_operator:SI 1 "s390_scond_operator" |
5483 | [(match_operand:GPR 2 "register_operand" "") | |
5484 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 5485 | "TARGET_CPU_ZARCH" |
f90b7a5a | 5486 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
5487 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
5488 | ||
f90b7a5a | 5489 | (define_expand "cstorecc4" |
69950452 | 5490 | [(parallel |
f90b7a5a PB |
5491 | [(set (match_operand:SI 0 "register_operand" "") |
5492 | (match_operator:SI 1 "s390_eqne_operator" | |
5493 | [(match_operand:CCZ1 2 "register_operand") | |
5494 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
5495 | (clobber (reg:CC CC_REGNUM))])] |
5496 | "" | |
f90b7a5a PB |
5497 | "emit_insn (gen_sne (operands[0], operands[2])); |
5498 | if (GET_CODE (operands[1]) == EQ) | |
5499 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
5500 | DONE;") | |
69950452 | 5501 | |
f90b7a5a | 5502 | (define_insn_and_split "sne" |
69950452 | 5503 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 5504 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
5505 | (const_int 0))) |
5506 | (clobber (reg:CC CC_REGNUM))] | |
5507 | "" | |
5508 | "#" | |
5509 | "reload_completed" | |
5510 | [(parallel | |
5511 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
5512 | (clobber (reg:CC CC_REGNUM))])]) | |
5513 | ||
e69166de | 5514 | |
65b1d8ea AK |
5515 | ;; |
5516 | ;; - Conditional move instructions (introduced with z196) | |
5517 | ;; | |
5518 | ||
5519 | (define_expand "mov<mode>cc" | |
5520 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
5521 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
5522 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
5523 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
5524 | "TARGET_Z196" | |
5525 | "operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
5526 | XEXP (operands[1], 0), XEXP (operands[1], 1));") | |
5527 | ||
27037b5f | 5528 | ; locr, loc, stoc, locgr, locg, stocg |
65b1d8ea AK |
5529 | (define_insn_and_split "*mov<mode>cc" |
5530 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
5531 | (if_then_else:GPR | |
5532 | (match_operator 1 "s390_comparison" | |
5533 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5a3fe9b6 | 5534 | (match_operand 5 "const_int_operand" "")]) |
65b1d8ea AK |
5535 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") |
5536 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
5537 | "TARGET_Z196" | |
5538 | "@ | |
5539 | loc<g>r%C1\t%0,%3 | |
5540 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
5541 | loc<g>%C1\t%0,%3 |
5542 | loc<g>%D1\t%0,%4 | |
5543 | stoc<g>%C1\t%3,%0 | |
5544 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
5545 | #" |
5546 | "&& reload_completed | |
5547 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
5548 | [(set (match_dup 0) | |
5549 | (if_then_else:GPR | |
5550 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5551 | (match_dup 3) | |
5552 | (match_dup 0))) | |
5553 | (set (match_dup 0) | |
5554 | (if_then_else:GPR | |
5555 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5556 | (match_dup 0) | |
5557 | (match_dup 4)))] | |
5558 | "" | |
5559 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
5560 | ||
9db1d521 HP |
5561 | ;; |
5562 | ;;- Multiply instructions. | |
5563 | ;; | |
5564 | ||
4023fb28 UW |
5565 | ; |
5566 | ; muldi3 instruction pattern(s). | |
5567 | ; | |
9db1d521 | 5568 | |
07893d4f UW |
5569 | (define_insn "*muldi3_sign" |
5570 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 5571 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5572 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 5573 | "TARGET_ZARCH" |
07893d4f | 5574 | "@ |
d40c829f UW |
5575 | msgfr\t%0,%2 |
5576 | msgf\t%0,%2" | |
963fc8d0 AK |
5577 | [(set_attr "op_type" "RRE,RXY") |
5578 | (set_attr "type" "imuldi")]) | |
07893d4f | 5579 | |
4023fb28 | 5580 | (define_insn "muldi3" |
963fc8d0 AK |
5581 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
5582 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5583 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 5584 | "TARGET_ZARCH" |
9db1d521 | 5585 | "@ |
d40c829f UW |
5586 | msgr\t%0,%2 |
5587 | mghi\t%0,%h2 | |
963fc8d0 AK |
5588 | msg\t%0,%2 |
5589 | msgfi\t%0,%2" | |
5590 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
5591 | (set_attr "type" "imuldi") | |
5592 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 5593 | |
9db1d521 HP |
5594 | ; |
5595 | ; mulsi3 instruction pattern(s). | |
5596 | ; | |
5597 | ||
f1e77d83 | 5598 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
5599 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
5600 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5601 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 5602 | "" |
963fc8d0 AK |
5603 | "@ |
5604 | mh\t%0,%2 | |
5605 | mhy\t%0,%2" | |
5606 | [(set_attr "op_type" "RX,RXY") | |
5607 | (set_attr "type" "imulhi") | |
5608 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 5609 | |
9db1d521 | 5610 | (define_insn "mulsi3" |
963fc8d0 AK |
5611 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
5612 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5613 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
5614 | "" |
5615 | "@ | |
d40c829f UW |
5616 | msr\t%0,%2 |
5617 | mhi\t%0,%h2 | |
5618 | ms\t%0,%2 | |
963fc8d0 AK |
5619 | msy\t%0,%2 |
5620 | msfi\t%0,%2" | |
5621 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
5622 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
5623 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 5624 | |
4023fb28 UW |
5625 | ; |
5626 | ; mulsidi3 instruction pattern(s). | |
5627 | ; | |
5628 | ||
f1e77d83 | 5629 | (define_insn "mulsidi3" |
963fc8d0 | 5630 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 5631 | (mult:DI (sign_extend:DI |
963fc8d0 | 5632 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 5633 | (sign_extend:DI |
963fc8d0 | 5634 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 5635 | "!TARGET_ZARCH" |
f1e77d83 UW |
5636 | "@ |
5637 | mr\t%0,%2 | |
963fc8d0 AK |
5638 | m\t%0,%2 |
5639 | mfy\t%0,%2" | |
5640 | [(set_attr "op_type" "RR,RX,RXY") | |
5641 | (set_attr "type" "imulsi") | |
5642 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 5643 | |
f1e77d83 | 5644 | ; |
6e0d70c9 | 5645 | ; umul instruction pattern(s). |
f1e77d83 | 5646 | ; |
c7453384 | 5647 | |
6e0d70c9 AK |
5648 | ; mlr, ml, mlgr, mlg |
5649 | (define_insn "umul<dwh><mode>3" | |
5650 | [(set (match_operand:DW 0 "register_operand" "=d, d") | |
5651 | (mult:DW (zero_extend:DW | |
5652 | (match_operand:<DWH> 1 "register_operand" "%0, 0")) | |
5653 | (zero_extend:DW | |
5654 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] | |
5655 | "TARGET_CPU_ZARCH" | |
f1e77d83 | 5656 | "@ |
6e0d70c9 AK |
5657 | ml<tg>r\t%0,%2 |
5658 | ml<tg>\t%0,%2" | |
f1e77d83 | 5659 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 5660 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 5661 | |
9db1d521 | 5662 | ; |
609e7e80 | 5663 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5664 | ; |
5665 | ||
9381e3f1 | 5666 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 5667 | (define_insn "mul<mode>3" |
609e7e80 AK |
5668 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5669 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
5670 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5671 | "TARGET_HARD_FLOAT" |
9db1d521 | 5672 | "@ |
609e7e80 | 5673 | m<xdee><bt>r\t%0,<op1>%2 |
f61a2c7d | 5674 | m<xdee>b\t%0,%2" |
609e7e80 | 5675 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5676 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 5677 | |
9381e3f1 | 5678 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 5679 | (define_insn "fma<mode>4" |
f61a2c7d | 5680 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
d7ecb504 RH |
5681 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5682 | (match_operand:DSF 2 "nonimmediate_operand" "f,R") | |
f61a2c7d | 5683 | (match_operand:DSF 3 "register_operand" "0,0")))] |
d7ecb504 | 5684 | "TARGET_HARD_FLOAT" |
a1b892b5 | 5685 | "@ |
f61a2c7d AK |
5686 | ma<xde>br\t%0,%1,%2 |
5687 | ma<xde>b\t%0,%1,%2" | |
a1b892b5 | 5688 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5689 | (set_attr "type" "fmadd<mode>")]) |
a1b892b5 | 5690 | |
43a09b63 | 5691 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 5692 | (define_insn "fms<mode>4" |
f61a2c7d | 5693 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
d7ecb504 RH |
5694 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5695 | (match_operand:DSF 2 "nonimmediate_operand" "f,R") | |
5696 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))] | |
5697 | "TARGET_HARD_FLOAT" | |
a1b892b5 | 5698 | "@ |
f61a2c7d AK |
5699 | ms<xde>br\t%0,%1,%2 |
5700 | ms<xde>b\t%0,%1,%2" | |
ce50cae8 | 5701 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5702 | (set_attr "type" "fmadd<mode>")]) |
9db1d521 HP |
5703 | |
5704 | ;; | |
5705 | ;;- Divide and modulo instructions. | |
5706 | ;; | |
5707 | ||
5708 | ; | |
4023fb28 | 5709 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
5710 | ; |
5711 | ||
4023fb28 UW |
5712 | (define_expand "divmoddi4" |
5713 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 5714 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
5715 | (match_operand:DI 2 "general_operand" ""))) |
5716 | (set (match_operand:DI 3 "general_operand" "") | |
5717 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
5718 | (clobber (match_dup 4))] | |
9602b6a1 | 5719 | "TARGET_ZARCH" |
9db1d521 | 5720 | { |
f1e77d83 | 5721 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
5722 | |
5723 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
5724 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
5725 | |
5726 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 5727 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
5728 | |
5729 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5730 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5731 | |
5732 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5733 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5734 | |
9db1d521 | 5735 | DONE; |
10bbf137 | 5736 | }) |
9db1d521 HP |
5737 | |
5738 | (define_insn "divmodtidi3" | |
4023fb28 UW |
5739 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
5740 | (ior:TI | |
4023fb28 UW |
5741 | (ashift:TI |
5742 | (zero_extend:TI | |
5665e398 | 5743 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5744 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
5745 | (const_int 64)) |
5746 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 5747 | "TARGET_ZARCH" |
9db1d521 | 5748 | "@ |
d40c829f UW |
5749 | dsgr\t%0,%2 |
5750 | dsg\t%0,%2" | |
d3632d41 | 5751 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5752 | (set_attr "type" "idiv")]) |
9db1d521 | 5753 | |
4023fb28 UW |
5754 | (define_insn "divmodtisi3" |
5755 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5756 | (ior:TI | |
4023fb28 UW |
5757 | (ashift:TI |
5758 | (zero_extend:TI | |
5665e398 | 5759 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 5760 | (sign_extend:DI |
fb492564 | 5761 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
5762 | (const_int 64)) |
5763 | (zero_extend:TI | |
5764 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 5765 | "TARGET_ZARCH" |
4023fb28 | 5766 | "@ |
d40c829f UW |
5767 | dsgfr\t%0,%2 |
5768 | dsgf\t%0,%2" | |
d3632d41 | 5769 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5770 | (set_attr "type" "idiv")]) |
9db1d521 | 5771 | |
4023fb28 UW |
5772 | ; |
5773 | ; udivmoddi4 instruction pattern(s). | |
5774 | ; | |
9db1d521 | 5775 | |
4023fb28 UW |
5776 | (define_expand "udivmoddi4" |
5777 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5778 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
5779 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
5780 | (set (match_operand:DI 3 "general_operand" "") | |
5781 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
5782 | (clobber (match_dup 4))] | |
9602b6a1 | 5783 | "TARGET_ZARCH" |
9db1d521 | 5784 | { |
4023fb28 UW |
5785 | rtx insn, div_equal, mod_equal, equal; |
5786 | ||
5787 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
5788 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
5789 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
5790 | gen_rtx_ASHIFT (TImode, |
5791 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
5792 | GEN_INT (64)), |
5793 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
5794 | |
5795 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 5796 | emit_clobber (operands[4]); |
4023fb28 UW |
5797 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
5798 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 5799 | |
4023fb28 | 5800 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5801 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5802 | |
5803 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5804 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5805 | |
5806 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5807 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5808 | |
9db1d521 | 5809 | DONE; |
10bbf137 | 5810 | }) |
9db1d521 HP |
5811 | |
5812 | (define_insn "udivmodtidi3" | |
4023fb28 | 5813 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 5814 | (ior:TI |
5665e398 UW |
5815 | (ashift:TI |
5816 | (zero_extend:TI | |
5817 | (truncate:DI | |
2f7e5a0d EC |
5818 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
5819 | (zero_extend:TI | |
fb492564 | 5820 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5821 | (const_int 64)) |
5822 | (zero_extend:TI | |
5823 | (truncate:DI | |
5824 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 5825 | "TARGET_ZARCH" |
9db1d521 | 5826 | "@ |
d40c829f UW |
5827 | dlgr\t%0,%2 |
5828 | dlg\t%0,%2" | |
d3632d41 | 5829 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5830 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5831 | |
5832 | ; | |
4023fb28 | 5833 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
5834 | ; |
5835 | ||
4023fb28 UW |
5836 | (define_expand "divmodsi4" |
5837 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5838 | (div:SI (match_operand:SI 1 "general_operand" "") | |
5839 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5840 | (set (match_operand:SI 3 "general_operand" "") | |
5841 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
5842 | (clobber (match_dup 4))] | |
9602b6a1 | 5843 | "!TARGET_ZARCH" |
9db1d521 | 5844 | { |
4023fb28 UW |
5845 | rtx insn, div_equal, mod_equal, equal; |
5846 | ||
5847 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
5848 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
5849 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5850 | gen_rtx_ASHIFT (DImode, |
5851 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5852 | GEN_INT (32)), |
5853 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
5854 | |
5855 | operands[4] = gen_reg_rtx(DImode); | |
5856 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 5857 | |
4023fb28 | 5858 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5859 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5860 | |
5861 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5862 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5863 | |
5864 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5865 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5866 | |
9db1d521 | 5867 | DONE; |
10bbf137 | 5868 | }) |
9db1d521 HP |
5869 | |
5870 | (define_insn "divmoddisi3" | |
4023fb28 | 5871 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 5872 | (ior:DI |
5665e398 UW |
5873 | (ashift:DI |
5874 | (zero_extend:DI | |
5875 | (truncate:SI | |
2f7e5a0d EC |
5876 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
5877 | (sign_extend:DI | |
5665e398 UW |
5878 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
5879 | (const_int 32)) | |
5880 | (zero_extend:DI | |
5881 | (truncate:SI | |
5882 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5883 | "!TARGET_ZARCH" |
9db1d521 | 5884 | "@ |
d40c829f UW |
5885 | dr\t%0,%2 |
5886 | d\t%0,%2" | |
9db1d521 | 5887 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5888 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5889 | |
5890 | ; | |
5891 | ; udivsi3 and umodsi3 instruction pattern(s). | |
5892 | ; | |
5893 | ||
f1e77d83 UW |
5894 | (define_expand "udivmodsi4" |
5895 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5896 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5897 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5898 | (set (match_operand:SI 3 "general_operand" "") | |
5899 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
5900 | (clobber (match_dup 4))] | |
9602b6a1 | 5901 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5902 | { |
5903 | rtx insn, div_equal, mod_equal, equal; | |
5904 | ||
5905 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5906 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5907 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
5908 | gen_rtx_ASHIFT (DImode, |
5909 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5910 | GEN_INT (32)), |
5911 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
5912 | |
5913 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 5914 | emit_clobber (operands[4]); |
f1e77d83 UW |
5915 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
5916 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 5917 | |
f1e77d83 | 5918 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5919 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
5920 | |
5921 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5922 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
5923 | |
5924 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5925 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
5926 | |
5927 | DONE; | |
5928 | }) | |
5929 | ||
5930 | (define_insn "udivmoddisi3" | |
5931 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 5932 | (ior:DI |
5665e398 UW |
5933 | (ashift:DI |
5934 | (zero_extend:DI | |
5935 | (truncate:SI | |
2f7e5a0d EC |
5936 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
5937 | (zero_extend:DI | |
fb492564 | 5938 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5939 | (const_int 32)) |
5940 | (zero_extend:DI | |
5941 | (truncate:SI | |
5942 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5943 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5944 | "@ |
5945 | dlr\t%0,%2 | |
5946 | dl\t%0,%2" | |
5947 | [(set_attr "op_type" "RRE,RXY") | |
5948 | (set_attr "type" "idiv")]) | |
4023fb28 | 5949 | |
9db1d521 HP |
5950 | (define_expand "udivsi3" |
5951 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5952 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
5953 | (match_operand:SI 2 "general_operand" ""))) |
5954 | (clobber (match_dup 3))] | |
9602b6a1 | 5955 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 5956 | { |
4023fb28 UW |
5957 | rtx insn, udiv_equal, umod_equal, equal; |
5958 | ||
5959 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5960 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5961 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5962 | gen_rtx_ASHIFT (DImode, |
5963 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5964 | GEN_INT (32)), |
5965 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5966 | |
4023fb28 | 5967 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5968 | |
5969 | if (CONSTANT_P (operands[2])) | |
5970 | { | |
5971 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
5972 | { | |
5973 | rtx label1 = gen_label_rtx (); | |
5974 | ||
4023fb28 UW |
5975 | operands[1] = make_safe_from (operands[1], operands[0]); |
5976 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5977 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
5978 | SImode, 1, label1); | |
4023fb28 | 5979 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5980 | emit_label (label1); |
5981 | } | |
5982 | else | |
5983 | { | |
c7453384 EC |
5984 | operands[2] = force_reg (SImode, operands[2]); |
5985 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5986 | |
5987 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5988 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5989 | operands[2])); | |
bd94cb6e | 5990 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5991 | |
5992 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5993 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 5994 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
5995 | } |
5996 | } | |
5997 | else | |
c7453384 | 5998 | { |
9db1d521 HP |
5999 | rtx label1 = gen_label_rtx (); |
6000 | rtx label2 = gen_label_rtx (); | |
6001 | rtx label3 = gen_label_rtx (); | |
6002 | ||
c7453384 EC |
6003 | operands[1] = force_reg (SImode, operands[1]); |
6004 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6005 | operands[2] = force_reg (SImode, operands[2]); | |
6006 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6007 | |
6008 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6009 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6010 | SImode, 1, label3); | |
6011 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6012 | SImode, 0, label2); | |
6013 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6014 | SImode, 0, label1); | |
4023fb28 UW |
6015 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6016 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6017 | operands[2])); | |
bd94cb6e | 6018 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6019 | |
6020 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6021 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
6022 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
6023 | ||
f314b9b1 | 6024 | emit_jump (label3); |
9db1d521 | 6025 | emit_label (label1); |
4023fb28 | 6026 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 6027 | emit_jump (label3); |
9db1d521 | 6028 | emit_label (label2); |
4023fb28 | 6029 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6030 | emit_label (label3); |
6031 | } | |
c7453384 | 6032 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 6033 | DONE; |
10bbf137 | 6034 | }) |
9db1d521 HP |
6035 | |
6036 | (define_expand "umodsi3" | |
6037 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6038 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
6039 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
6040 | (clobber (match_dup 3))] | |
9602b6a1 | 6041 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6042 | { |
4023fb28 UW |
6043 | rtx insn, udiv_equal, umod_equal, equal; |
6044 | ||
6045 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6046 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6047 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6048 | gen_rtx_ASHIFT (DImode, |
6049 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6050 | GEN_INT (32)), |
6051 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6052 | |
4023fb28 | 6053 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6054 | |
6055 | if (CONSTANT_P (operands[2])) | |
6056 | { | |
6057 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
6058 | { | |
6059 | rtx label1 = gen_label_rtx (); | |
6060 | ||
4023fb28 UW |
6061 | operands[1] = make_safe_from (operands[1], operands[0]); |
6062 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
6063 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
6064 | SImode, 1, label1); | |
4023fb28 UW |
6065 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
6066 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
6067 | emit_label (label1); |
6068 | } | |
6069 | else | |
6070 | { | |
c7453384 EC |
6071 | operands[2] = force_reg (SImode, operands[2]); |
6072 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6073 | |
6074 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6075 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6076 | operands[2])); | |
bd94cb6e | 6077 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6078 | |
6079 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6080 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 6081 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
6082 | } |
6083 | } | |
6084 | else | |
6085 | { | |
6086 | rtx label1 = gen_label_rtx (); | |
6087 | rtx label2 = gen_label_rtx (); | |
6088 | rtx label3 = gen_label_rtx (); | |
6089 | ||
c7453384 EC |
6090 | operands[1] = force_reg (SImode, operands[1]); |
6091 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6092 | operands[2] = force_reg (SImode, operands[2]); | |
6093 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 6094 | |
c7453384 | 6095 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
6096 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6097 | SImode, 1, label3); | |
6098 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6099 | SImode, 0, label2); | |
6100 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6101 | SImode, 0, label1); | |
4023fb28 UW |
6102 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6103 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6104 | operands[2])); | |
bd94cb6e | 6105 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6106 | |
6107 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6108 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
6109 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
6110 | ||
f314b9b1 | 6111 | emit_jump (label3); |
9db1d521 | 6112 | emit_label (label1); |
4023fb28 | 6113 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 6114 | emit_jump (label3); |
9db1d521 | 6115 | emit_label (label2); |
4023fb28 | 6116 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
6117 | emit_label (label3); |
6118 | } | |
9db1d521 | 6119 | DONE; |
10bbf137 | 6120 | }) |
9db1d521 HP |
6121 | |
6122 | ; | |
f5905b37 | 6123 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
6124 | ; |
6125 | ||
609e7e80 | 6126 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 6127 | (define_insn "div<mode>3" |
609e7e80 AK |
6128 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
6129 | (div:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
6130 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 6131 | "TARGET_HARD_FLOAT" |
9db1d521 | 6132 | "@ |
609e7e80 | 6133 | d<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 6134 | d<xde>b\t%0,%2" |
609e7e80 | 6135 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 6136 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 6137 | |
9db1d521 HP |
6138 | |
6139 | ;; | |
6140 | ;;- And instructions. | |
6141 | ;; | |
6142 | ||
047d35ed AS |
6143 | (define_expand "and<mode>3" |
6144 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6145 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6146 | (match_operand:INT 2 "general_operand" ""))) | |
6147 | (clobber (reg:CC CC_REGNUM))] | |
6148 | "" | |
6149 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
6150 | ||
9db1d521 HP |
6151 | ; |
6152 | ; anddi3 instruction pattern(s). | |
6153 | ; | |
6154 | ||
6155 | (define_insn "*anddi3_cc" | |
ae156f85 | 6156 | [(set (reg CC_REGNUM) |
e3140518 RH |
6157 | (compare |
6158 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6159 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
6160 | (const_int 0))) | |
6161 | (set (match_operand:DI 0 "register_operand" "=d,d, d, d") | |
9db1d521 | 6162 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 6163 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 6164 | "@ |
d40c829f | 6165 | ngr\t%0,%2 |
65b1d8ea | 6166 | ngrk\t%0,%1,%2 |
e3140518 RH |
6167 | ng\t%0,%2 |
6168 | risbg\t%0,%1,%s2,128+%e2,0" | |
6169 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6170 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6171 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6172 | |
6173 | (define_insn "*anddi3_cconly" | |
ae156f85 | 6174 | [(set (reg CC_REGNUM) |
e3140518 RH |
6175 | (compare |
6176 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6177 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
9db1d521 | 6178 | (const_int 0))) |
e3140518 RH |
6179 | (clobber (match_scratch:DI 0 "=d,d, d, d"))] |
6180 | "TARGET_ZARCH | |
6181 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
6182 | /* Do not steal TM patterns. */ |
6183 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 6184 | "@ |
d40c829f | 6185 | ngr\t%0,%2 |
65b1d8ea | 6186 | ngrk\t%0,%1,%2 |
e3140518 RH |
6187 | ng\t%0,%2 |
6188 | risbg\t%0,%1,%s2,128+%e2,0" | |
6189 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6190 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6191 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6192 | |
3af8e996 | 6193 | (define_insn "*anddi3" |
65b1d8ea | 6194 | [(set (match_operand:DI 0 "nonimmediate_operand" |
e3140518 RH |
6195 | "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") |
6196 | (and:DI | |
6197 | (match_operand:DI 1 "nonimmediate_operand" | |
6198 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") | |
6199 | (match_operand:DI 2 "general_operand" | |
6200 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) | |
ec24698e | 6201 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6202 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6203 | "@ |
6204 | # | |
6205 | # | |
6206 | nihh\t%0,%j2 | |
6207 | nihl\t%0,%j2 | |
6208 | nilh\t%0,%j2 | |
6209 | nill\t%0,%j2 | |
6210 | nihf\t%0,%m2 | |
6211 | nilf\t%0,%m2 | |
6212 | ngr\t%0,%2 | |
65b1d8ea | 6213 | ngrk\t%0,%1,%2 |
ec24698e | 6214 | ng\t%0,%2 |
e3140518 | 6215 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
6216 | # |
6217 | #" | |
e3140518 RH |
6218 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
6219 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
6220 | (set_attr "z10prop" "*, |
6221 | *, | |
6222 | z10_super_E1, | |
6223 | z10_super_E1, | |
6224 | z10_super_E1, | |
6225 | z10_super_E1, | |
6226 | z10_super_E1, | |
6227 | z10_super_E1, | |
6228 | z10_super_E1, | |
65b1d8ea | 6229 | *, |
9381e3f1 | 6230 | z10_super_E1, |
e3140518 | 6231 | z10_super_E1, |
9381e3f1 WG |
6232 | *, |
6233 | *")]) | |
0dfa6c5e UW |
6234 | |
6235 | (define_split | |
6236 | [(set (match_operand:DI 0 "s_operand" "") | |
6237 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6238 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6239 | "reload_completed" |
6240 | [(parallel | |
6241 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6242 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6243 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6244 | |
1a2e356e RH |
6245 | ;; These two are what combine generates for (ashift (zero_extract)). |
6246 | (define_insn "*extzv_<mode>_srl" | |
6247 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6248 | (and:GPR (lshiftrt:GPR | |
6249 | (match_operand:GPR 1 "register_operand" "d") | |
6250 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6251 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6252 | (clobber (reg:CC CC_REGNUM))] | |
6253 | "TARGET_Z10 | |
6254 | /* Note that even for the SImode pattern, the rotate is always DImode. */ | |
6255 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
6256 | INTVAL (operands[3]))" | |
6257 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" | |
6258 | [(set_attr "op_type" "RIE") | |
6259 | (set_attr "z10prop" "z10_super_E1")]) | |
6260 | ||
6261 | (define_insn "*extzv_<mode>_sll" | |
6262 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6263 | (and:GPR (ashift:GPR | |
6264 | (match_operand:GPR 1 "register_operand" "d") | |
6265 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6266 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6267 | (clobber (reg:CC CC_REGNUM))] | |
6268 | "TARGET_Z10 | |
6269 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), | |
6270 | INTVAL (operands[3]))" | |
6271 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" | |
6272 | [(set_attr "op_type" "RIE") | |
6273 | (set_attr "z10prop" "z10_super_E1")]) | |
6274 | ||
9db1d521 HP |
6275 | |
6276 | ; | |
6277 | ; andsi3 instruction pattern(s). | |
6278 | ; | |
6279 | ||
6280 | (define_insn "*andsi3_cc" | |
ae156f85 | 6281 | [(set (reg CC_REGNUM) |
e3140518 RH |
6282 | (compare |
6283 | (and:SI | |
6284 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6285 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6286 | (const_int 0))) | |
6287 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
6288 | (and:SI (match_dup 1) (match_dup 2)))] |
6289 | "s390_match_ccmode(insn, CCTmode)" | |
6290 | "@ | |
ec24698e | 6291 | nilf\t%0,%o2 |
d40c829f | 6292 | nr\t%0,%2 |
65b1d8ea | 6293 | nrk\t%0,%1,%2 |
d40c829f | 6294 | n\t%0,%2 |
e3140518 RH |
6295 | ny\t%0,%2 |
6296 | risbg\t%0,%1,%t2,128+%f2,0" | |
6297 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6298 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
6299 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6300 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6301 | |
6302 | (define_insn "*andsi3_cconly" | |
ae156f85 | 6303 | [(set (reg CC_REGNUM) |
e3140518 RH |
6304 | (compare |
6305 | (and:SI | |
6306 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6307 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6308 | (const_int 0))) | |
6309 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
6310 | "s390_match_ccmode(insn, CCTmode) |
6311 | /* Do not steal TM patterns. */ | |
6312 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 6313 | "@ |
ec24698e | 6314 | nilf\t%0,%o2 |
d40c829f | 6315 | nr\t%0,%2 |
65b1d8ea | 6316 | nrk\t%0,%1,%2 |
d40c829f | 6317 | n\t%0,%2 |
e3140518 RH |
6318 | ny\t%0,%2 |
6319 | risbg\t%0,%1,%t2,128+%f2,0" | |
6320 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6321 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
65b1d8ea | 6322 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 6323 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6324 | |
f19a9af7 | 6325 | (define_insn "*andsi3_zarch" |
65b1d8ea | 6326 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 6327 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 6328 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 6329 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 6330 | (match_operand:SI 2 "general_operand" |
e3140518 | 6331 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q"))) |
ae156f85 | 6332 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6333 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6334 | "@ |
f19a9af7 AK |
6335 | # |
6336 | # | |
6337 | nilh\t%0,%j2 | |
2f7e5a0d | 6338 | nill\t%0,%j2 |
ec24698e | 6339 | nilf\t%0,%o2 |
d40c829f | 6340 | nr\t%0,%2 |
65b1d8ea | 6341 | nrk\t%0,%1,%2 |
d40c829f | 6342 | n\t%0,%2 |
8cb66696 | 6343 | ny\t%0,%2 |
e3140518 | 6344 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 6345 | # |
19b63d8e | 6346 | #" |
e3140518 RH |
6347 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
6348 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") | |
9381e3f1 WG |
6349 | (set_attr "z10prop" "*, |
6350 | *, | |
6351 | z10_super_E1, | |
6352 | z10_super_E1, | |
6353 | z10_super_E1, | |
6354 | z10_super_E1, | |
65b1d8ea | 6355 | *, |
9381e3f1 WG |
6356 | z10_super_E1, |
6357 | z10_super_E1, | |
e3140518 | 6358 | z10_super_E1, |
9381e3f1 WG |
6359 | *, |
6360 | *")]) | |
f19a9af7 AK |
6361 | |
6362 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
6363 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
6364 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
6365 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 6366 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6367 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6368 | "@ |
6369 | nr\t%0,%2 | |
8cb66696 | 6370 | n\t%0,%2 |
0dfa6c5e | 6371 | # |
19b63d8e | 6372 | #" |
9381e3f1 WG |
6373 | [(set_attr "op_type" "RR,RX,SI,SS") |
6374 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6375 | ||
0dfa6c5e UW |
6376 | |
6377 | (define_split | |
6378 | [(set (match_operand:SI 0 "s_operand" "") | |
6379 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6380 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6381 | "reload_completed" |
6382 | [(parallel | |
6383 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6384 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6385 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6386 | |
9db1d521 HP |
6387 | ; |
6388 | ; andhi3 instruction pattern(s). | |
6389 | ; | |
6390 | ||
8cb66696 | 6391 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
6392 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6393 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6394 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 6395 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6396 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6397 | "@ |
d40c829f | 6398 | nr\t%0,%2 |
65b1d8ea | 6399 | nrk\t%0,%1,%2 |
8cb66696 | 6400 | nill\t%0,%x2 |
0dfa6c5e | 6401 | # |
19b63d8e | 6402 | #" |
65b1d8ea AK |
6403 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6404 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6405 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 6406 | ]) |
8cb66696 UW |
6407 | |
6408 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
6409 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6410 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6411 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 6412 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6413 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6414 | "@ | |
6415 | nr\t%0,%2 | |
0dfa6c5e | 6416 | # |
19b63d8e | 6417 | #" |
9381e3f1 WG |
6418 | [(set_attr "op_type" "RR,SI,SS") |
6419 | (set_attr "z10prop" "z10_super_E1,*,*") | |
6420 | ]) | |
0dfa6c5e UW |
6421 | |
6422 | (define_split | |
6423 | [(set (match_operand:HI 0 "s_operand" "") | |
6424 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6425 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6426 | "reload_completed" |
6427 | [(parallel | |
6428 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6429 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6430 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 6431 | |
9db1d521 HP |
6432 | ; |
6433 | ; andqi3 instruction pattern(s). | |
6434 | ; | |
6435 | ||
8cb66696 | 6436 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
6437 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6438 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6439 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6440 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6441 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6442 | "@ |
d40c829f | 6443 | nr\t%0,%2 |
65b1d8ea | 6444 | nrk\t%0,%1,%2 |
8cb66696 | 6445 | nill\t%0,%b2 |
fc0ea003 UW |
6446 | ni\t%S0,%b2 |
6447 | niy\t%S0,%b2 | |
19b63d8e | 6448 | #" |
65b1d8ea AK |
6449 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6450 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6451 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
6452 | |
6453 | (define_insn "*andqi3_esa" | |
6454 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6455 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6456 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6457 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6458 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6459 | "@ |
8cb66696 | 6460 | nr\t%0,%2 |
fc0ea003 | 6461 | ni\t%S0,%b2 |
19b63d8e | 6462 | #" |
9381e3f1 WG |
6463 | [(set_attr "op_type" "RR,SI,SS") |
6464 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 6465 | |
19b63d8e UW |
6466 | ; |
6467 | ; Block and (NC) patterns. | |
6468 | ; | |
6469 | ||
6470 | (define_insn "*nc" | |
6471 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6472 | (and:BLK (match_dup 0) | |
6473 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6474 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6475 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6476 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6477 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6478 | [(set_attr "op_type" "SS") |
6479 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6480 | |
6481 | (define_split | |
6482 | [(set (match_operand 0 "memory_operand" "") | |
6483 | (and (match_dup 0) | |
6484 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6485 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6486 | "reload_completed |
6487 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6488 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6489 | [(parallel | |
6490 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
6491 | (use (match_dup 2)) | |
ae156f85 | 6492 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6493 | { |
6494 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6495 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6496 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6497 | }) | |
6498 | ||
6499 | (define_peephole2 | |
6500 | [(parallel | |
6501 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6502 | (and:BLK (match_dup 0) | |
6503 | (match_operand:BLK 1 "memory_operand" ""))) | |
6504 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6505 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6506 | (parallel |
6507 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6508 | (and:BLK (match_dup 3) | |
6509 | (match_operand:BLK 4 "memory_operand" ""))) | |
6510 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6511 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6512 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6513 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6514 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6515 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6516 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6517 | [(parallel | |
6518 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
6519 | (use (match_dup 8)) | |
ae156f85 | 6520 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6521 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6522 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6523 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6524 | ||
9db1d521 HP |
6525 | |
6526 | ;; | |
6527 | ;;- Bit set (inclusive or) instructions. | |
6528 | ;; | |
6529 | ||
047d35ed AS |
6530 | (define_expand "ior<mode>3" |
6531 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6532 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6533 | (match_operand:INT 2 "general_operand" ""))) | |
6534 | (clobber (reg:CC CC_REGNUM))] | |
6535 | "" | |
6536 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
6537 | ||
9db1d521 HP |
6538 | ; |
6539 | ; iordi3 instruction pattern(s). | |
6540 | ; | |
6541 | ||
4023fb28 | 6542 | (define_insn "*iordi3_cc" |
ae156f85 | 6543 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6544 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6545 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6546 | (const_int 0))) |
65b1d8ea | 6547 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6548 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6549 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6550 | "@ |
d40c829f | 6551 | ogr\t%0,%2 |
65b1d8ea | 6552 | ogrk\t%0,%1,%2 |
d40c829f | 6553 | og\t%0,%2" |
65b1d8ea AK |
6554 | [(set_attr "op_type" "RRE,RRF,RXY") |
6555 | (set_attr "cpu_facility" "*,z196,*") | |
6556 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
6557 | |
6558 | (define_insn "*iordi3_cconly" | |
ae156f85 | 6559 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6560 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
6561 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6562 | (const_int 0))) |
65b1d8ea | 6563 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 6564 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6565 | "@ |
d40c829f | 6566 | ogr\t%0,%2 |
65b1d8ea | 6567 | ogrk\t%0,%1,%2 |
d40c829f | 6568 | og\t%0,%2" |
65b1d8ea AK |
6569 | [(set_attr "op_type" "RRE,RRF,RXY") |
6570 | (set_attr "cpu_facility" "*,z196,*") | |
6571 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6572 | |
3af8e996 | 6573 | (define_insn "*iordi3" |
65b1d8ea AK |
6574 | [(set (match_operand:DI 0 "nonimmediate_operand" |
6575 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
6576 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
6577 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 6578 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 6579 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 6580 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6581 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6582 | "@ |
6583 | oihh\t%0,%i2 | |
6584 | oihl\t%0,%i2 | |
6585 | oilh\t%0,%i2 | |
6586 | oill\t%0,%i2 | |
6587 | oihf\t%0,%k2 | |
6588 | oilf\t%0,%k2 | |
6589 | ogr\t%0,%2 | |
65b1d8ea | 6590 | ogrk\t%0,%1,%2 |
ec24698e UW |
6591 | og\t%0,%2 |
6592 | # | |
6593 | #" | |
65b1d8ea AK |
6594 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
6595 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
6596 | (set_attr "z10prop" "z10_super_E1, |
6597 | z10_super_E1, | |
6598 | z10_super_E1, | |
6599 | z10_super_E1, | |
6600 | z10_super_E1, | |
6601 | z10_super_E1, | |
6602 | z10_super_E1, | |
65b1d8ea | 6603 | *, |
9381e3f1 WG |
6604 | z10_super_E1, |
6605 | *, | |
6606 | *")]) | |
0dfa6c5e UW |
6607 | |
6608 | (define_split | |
6609 | [(set (match_operand:DI 0 "s_operand" "") | |
6610 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6611 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6612 | "reload_completed" |
6613 | [(parallel | |
6614 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6615 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6616 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6617 | |
9db1d521 HP |
6618 | ; |
6619 | ; iorsi3 instruction pattern(s). | |
6620 | ; | |
6621 | ||
4023fb28 | 6622 | (define_insn "*iorsi3_cc" |
ae156f85 | 6623 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6624 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6625 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6626 | (const_int 0))) |
65b1d8ea | 6627 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6628 | (ior:SI (match_dup 1) (match_dup 2)))] |
6629 | "s390_match_ccmode(insn, CCTmode)" | |
6630 | "@ | |
ec24698e | 6631 | oilf\t%0,%o2 |
d40c829f | 6632 | or\t%0,%2 |
65b1d8ea | 6633 | ork\t%0,%1,%2 |
d40c829f UW |
6634 | o\t%0,%2 |
6635 | oy\t%0,%2" | |
65b1d8ea AK |
6636 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6637 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6638 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6639 | |
6640 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 6641 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6642 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6643 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6644 | (const_int 0))) |
65b1d8ea | 6645 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6646 | "s390_match_ccmode(insn, CCTmode)" |
6647 | "@ | |
ec24698e | 6648 | oilf\t%0,%o2 |
d40c829f | 6649 | or\t%0,%2 |
65b1d8ea | 6650 | ork\t%0,%1,%2 |
d40c829f UW |
6651 | o\t%0,%2 |
6652 | oy\t%0,%2" | |
65b1d8ea AK |
6653 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6654 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6655 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6656 | |
8cb66696 | 6657 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
6658 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
6659 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
6660 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6661 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6662 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6663 | "@ |
f19a9af7 AK |
6664 | oilh\t%0,%i2 |
6665 | oill\t%0,%i2 | |
ec24698e | 6666 | oilf\t%0,%o2 |
d40c829f | 6667 | or\t%0,%2 |
65b1d8ea | 6668 | ork\t%0,%1,%2 |
d40c829f | 6669 | o\t%0,%2 |
8cb66696 | 6670 | oy\t%0,%2 |
0dfa6c5e | 6671 | # |
19b63d8e | 6672 | #" |
65b1d8ea AK |
6673 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
6674 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
6675 | (set_attr "z10prop" "z10_super_E1, |
6676 | z10_super_E1, | |
6677 | z10_super_E1, | |
6678 | z10_super_E1, | |
65b1d8ea | 6679 | *, |
9381e3f1 WG |
6680 | z10_super_E1, |
6681 | z10_super_E1, | |
6682 | *, | |
6683 | *")]) | |
8cb66696 UW |
6684 | |
6685 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 6686 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 6687 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 6688 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 6689 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6690 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6691 | "@ |
6692 | or\t%0,%2 | |
8cb66696 | 6693 | o\t%0,%2 |
0dfa6c5e | 6694 | # |
19b63d8e | 6695 | #" |
9381e3f1 WG |
6696 | [(set_attr "op_type" "RR,RX,SI,SS") |
6697 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6698 | |
6699 | (define_split | |
6700 | [(set (match_operand:SI 0 "s_operand" "") | |
6701 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6702 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6703 | "reload_completed" |
6704 | [(parallel | |
6705 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6706 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6707 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6708 | |
4023fb28 UW |
6709 | ; |
6710 | ; iorhi3 instruction pattern(s). | |
6711 | ; | |
6712 | ||
8cb66696 | 6713 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
6714 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6715 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6716 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 6717 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6718 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6719 | "@ |
d40c829f | 6720 | or\t%0,%2 |
65b1d8ea | 6721 | ork\t%0,%1,%2 |
8cb66696 | 6722 | oill\t%0,%x2 |
0dfa6c5e | 6723 | # |
19b63d8e | 6724 | #" |
65b1d8ea AK |
6725 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6726 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6727 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
6728 | |
6729 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
6730 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6731 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6732 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 6733 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6734 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6735 | "@ | |
6736 | or\t%0,%2 | |
0dfa6c5e | 6737 | # |
19b63d8e | 6738 | #" |
9381e3f1 WG |
6739 | [(set_attr "op_type" "RR,SI,SS") |
6740 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6741 | |
6742 | (define_split | |
6743 | [(set (match_operand:HI 0 "s_operand" "") | |
6744 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6745 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6746 | "reload_completed" |
6747 | [(parallel | |
6748 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6749 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6750 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 6751 | |
9db1d521 | 6752 | ; |
4023fb28 | 6753 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
6754 | ; |
6755 | ||
8cb66696 | 6756 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
6757 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6758 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6759 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6760 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6761 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6762 | "@ |
d40c829f | 6763 | or\t%0,%2 |
65b1d8ea | 6764 | ork\t%0,%1,%2 |
8cb66696 | 6765 | oill\t%0,%b2 |
fc0ea003 UW |
6766 | oi\t%S0,%b2 |
6767 | oiy\t%S0,%b2 | |
19b63d8e | 6768 | #" |
65b1d8ea AK |
6769 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6770 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6771 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
6772 | z10_super,z10_super,*")]) | |
8cb66696 UW |
6773 | |
6774 | (define_insn "*iorqi3_esa" | |
6775 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6776 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6777 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6778 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6779 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6780 | "@ |
8cb66696 | 6781 | or\t%0,%2 |
fc0ea003 | 6782 | oi\t%S0,%b2 |
19b63d8e | 6783 | #" |
9381e3f1 WG |
6784 | [(set_attr "op_type" "RR,SI,SS") |
6785 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 6786 | |
19b63d8e UW |
6787 | ; |
6788 | ; Block inclusive or (OC) patterns. | |
6789 | ; | |
6790 | ||
6791 | (define_insn "*oc" | |
6792 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6793 | (ior:BLK (match_dup 0) | |
6794 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6795 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6796 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6797 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6798 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6799 | [(set_attr "op_type" "SS") |
6800 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6801 | |
6802 | (define_split | |
6803 | [(set (match_operand 0 "memory_operand" "") | |
6804 | (ior (match_dup 0) | |
6805 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6806 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6807 | "reload_completed |
6808 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6809 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6810 | [(parallel | |
6811 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
6812 | (use (match_dup 2)) | |
ae156f85 | 6813 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6814 | { |
6815 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6816 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6817 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6818 | }) | |
6819 | ||
6820 | (define_peephole2 | |
6821 | [(parallel | |
6822 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6823 | (ior:BLK (match_dup 0) | |
6824 | (match_operand:BLK 1 "memory_operand" ""))) | |
6825 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6826 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6827 | (parallel |
6828 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6829 | (ior:BLK (match_dup 3) | |
6830 | (match_operand:BLK 4 "memory_operand" ""))) | |
6831 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6832 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6833 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6834 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6835 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6836 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6837 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6838 | [(parallel | |
6839 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
6840 | (use (match_dup 8)) | |
ae156f85 | 6841 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6842 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6843 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6844 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6845 | ||
9db1d521 HP |
6846 | |
6847 | ;; | |
6848 | ;;- Xor instructions. | |
6849 | ;; | |
6850 | ||
047d35ed AS |
6851 | (define_expand "xor<mode>3" |
6852 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6853 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6854 | (match_operand:INT 2 "general_operand" ""))) | |
6855 | (clobber (reg:CC CC_REGNUM))] | |
6856 | "" | |
6857 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
6858 | ||
9db1d521 HP |
6859 | ; |
6860 | ; xordi3 instruction pattern(s). | |
6861 | ; | |
6862 | ||
4023fb28 | 6863 | (define_insn "*xordi3_cc" |
ae156f85 | 6864 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6865 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6866 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6867 | (const_int 0))) |
65b1d8ea | 6868 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6869 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6870 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6871 | "@ |
d40c829f | 6872 | xgr\t%0,%2 |
65b1d8ea | 6873 | xgrk\t%0,%1,%2 |
d40c829f | 6874 | xg\t%0,%2" |
65b1d8ea | 6875 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 6876 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 6877 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
6878 | |
6879 | (define_insn "*xordi3_cconly" | |
ae156f85 | 6880 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6881 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6882 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6883 | (const_int 0))) |
65b1d8ea | 6884 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 6885 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6886 | "@ |
d40c829f | 6887 | xgr\t%0,%2 |
65b1d8ea | 6888 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 6889 | xg\t%0,%2" |
65b1d8ea AK |
6890 | [(set_attr "op_type" "RRE,RRF,RXY") |
6891 | (set_attr "cpu_facility" "*,z196,*") | |
6892 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6893 | |
3af8e996 | 6894 | (define_insn "*xordi3" |
65b1d8ea AK |
6895 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
6896 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
6897 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 6898 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6899 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6900 | "@ |
6901 | xihf\t%0,%k2 | |
6902 | xilf\t%0,%k2 | |
6903 | xgr\t%0,%2 | |
65b1d8ea | 6904 | xgrk\t%0,%1,%2 |
ec24698e UW |
6905 | xg\t%0,%2 |
6906 | # | |
6907 | #" | |
65b1d8ea AK |
6908 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
6909 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
6910 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
6911 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6912 | |
6913 | (define_split | |
6914 | [(set (match_operand:DI 0 "s_operand" "") | |
6915 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6916 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6917 | "reload_completed" |
6918 | [(parallel | |
6919 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6920 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6921 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 6922 | |
9db1d521 HP |
6923 | ; |
6924 | ; xorsi3 instruction pattern(s). | |
6925 | ; | |
6926 | ||
4023fb28 | 6927 | (define_insn "*xorsi3_cc" |
ae156f85 | 6928 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6929 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6930 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6931 | (const_int 0))) |
65b1d8ea | 6932 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6933 | (xor:SI (match_dup 1) (match_dup 2)))] |
6934 | "s390_match_ccmode(insn, CCTmode)" | |
6935 | "@ | |
ec24698e | 6936 | xilf\t%0,%o2 |
d40c829f | 6937 | xr\t%0,%2 |
65b1d8ea | 6938 | xrk\t%0,%1,%2 |
d40c829f UW |
6939 | x\t%0,%2 |
6940 | xy\t%0,%2" | |
65b1d8ea AK |
6941 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6942 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6943 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6944 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6945 | |
6946 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 6947 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6948 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6949 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6950 | (const_int 0))) |
65b1d8ea | 6951 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6952 | "s390_match_ccmode(insn, CCTmode)" |
6953 | "@ | |
ec24698e | 6954 | xilf\t%0,%o2 |
d40c829f | 6955 | xr\t%0,%2 |
65b1d8ea | 6956 | xrk\t%0,%1,%2 |
d40c829f UW |
6957 | x\t%0,%2 |
6958 | xy\t%0,%2" | |
65b1d8ea AK |
6959 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6960 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6961 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6962 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6963 | |
8cb66696 | 6964 | (define_insn "*xorsi3" |
65b1d8ea AK |
6965 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
6966 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
6967 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6968 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6969 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6970 | "@ |
ec24698e | 6971 | xilf\t%0,%o2 |
d40c829f | 6972 | xr\t%0,%2 |
65b1d8ea | 6973 | xrk\t%0,%1,%2 |
d40c829f | 6974 | x\t%0,%2 |
8cb66696 | 6975 | xy\t%0,%2 |
0dfa6c5e | 6976 | # |
19b63d8e | 6977 | #" |
65b1d8ea AK |
6978 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
6979 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
6980 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6981 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6982 | |
6983 | (define_split | |
6984 | [(set (match_operand:SI 0 "s_operand" "") | |
6985 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6986 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6987 | "reload_completed" |
6988 | [(parallel | |
6989 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6990 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6991 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 6992 | |
9db1d521 HP |
6993 | ; |
6994 | ; xorhi3 instruction pattern(s). | |
6995 | ; | |
6996 | ||
8cb66696 | 6997 | (define_insn "*xorhi3" |
65b1d8ea AK |
6998 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6999 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
7000 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 7001 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7002 | "s390_logical_operator_ok_p (operands)" |
7003 | "@ | |
ec24698e | 7004 | xilf\t%0,%x2 |
8cb66696 | 7005 | xr\t%0,%2 |
65b1d8ea | 7006 | xrk\t%0,%1,%2 |
0dfa6c5e | 7007 | # |
19b63d8e | 7008 | #" |
65b1d8ea AK |
7009 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
7010 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7011 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
7012 | |
7013 | (define_split | |
7014 | [(set (match_operand:HI 0 "s_operand" "") | |
7015 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7016 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7017 | "reload_completed" |
7018 | [(parallel | |
7019 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7020 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7021 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 7022 | |
9db1d521 HP |
7023 | ; |
7024 | ; xorqi3 instruction pattern(s). | |
7025 | ; | |
7026 | ||
8cb66696 | 7027 | (define_insn "*xorqi3" |
65b1d8ea AK |
7028 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7029 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
7030 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 7031 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7032 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7033 | "@ |
ec24698e | 7034 | xilf\t%0,%b2 |
8cb66696 | 7035 | xr\t%0,%2 |
65b1d8ea | 7036 | xrk\t%0,%1,%2 |
fc0ea003 UW |
7037 | xi\t%S0,%b2 |
7038 | xiy\t%S0,%b2 | |
19b63d8e | 7039 | #" |
65b1d8ea AK |
7040 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
7041 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
7042 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 7043 | |
4023fb28 | 7044 | |
19b63d8e UW |
7045 | ; |
7046 | ; Block exclusive or (XC) patterns. | |
7047 | ; | |
7048 | ||
7049 | (define_insn "*xc" | |
7050 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7051 | (xor:BLK (match_dup 0) | |
7052 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7053 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7054 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7055 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7056 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 7057 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
7058 | |
7059 | (define_split | |
7060 | [(set (match_operand 0 "memory_operand" "") | |
7061 | (xor (match_dup 0) | |
7062 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7063 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7064 | "reload_completed |
7065 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7066 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7067 | [(parallel | |
7068 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
7069 | (use (match_dup 2)) | |
ae156f85 | 7070 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7071 | { |
7072 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7073 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7074 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7075 | }) | |
7076 | ||
7077 | (define_peephole2 | |
7078 | [(parallel | |
7079 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7080 | (xor:BLK (match_dup 0) | |
7081 | (match_operand:BLK 1 "memory_operand" ""))) | |
7082 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7083 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7084 | (parallel |
7085 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7086 | (xor:BLK (match_dup 3) | |
7087 | (match_operand:BLK 4 "memory_operand" ""))) | |
7088 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7089 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7090 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7091 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7092 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7093 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7094 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7095 | [(parallel | |
7096 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
7097 | (use (match_dup 8)) | |
ae156f85 | 7098 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7099 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7100 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7101 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7102 | ||
7103 | ; | |
7104 | ; Block xor (XC) patterns with src == dest. | |
7105 | ; | |
7106 | ||
7107 | (define_insn "*xc_zero" | |
7108 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7109 | (const_int 0)) | |
7110 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 7111 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7112 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 7113 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
7114 | [(set_attr "op_type" "SS") |
7115 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7116 | |
7117 | (define_peephole2 | |
7118 | [(parallel | |
7119 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7120 | (const_int 0)) | |
7121 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 7122 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7123 | (parallel |
7124 | [(set (match_operand:BLK 2 "memory_operand" "") | |
7125 | (const_int 0)) | |
7126 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 7127 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7128 | "s390_offset_p (operands[0], operands[2], operands[1]) |
7129 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
7130 | [(parallel | |
7131 | [(set (match_dup 4) (const_int 0)) | |
7132 | (use (match_dup 5)) | |
ae156f85 | 7133 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7134 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7135 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
7136 | ||
9db1d521 HP |
7137 | |
7138 | ;; | |
7139 | ;;- Negate instructions. | |
7140 | ;; | |
7141 | ||
7142 | ; | |
9a91a21f | 7143 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
7144 | ; |
7145 | ||
9a91a21f | 7146 | (define_expand "neg<mode>2" |
9db1d521 | 7147 | [(parallel |
9a91a21f AS |
7148 | [(set (match_operand:DSI 0 "register_operand" "=d") |
7149 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 7150 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7151 | "" |
7152 | "") | |
7153 | ||
26a89301 | 7154 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 7155 | [(set (reg CC_REGNUM) |
26a89301 UW |
7156 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7157 | (match_operand:SI 1 "register_operand" "d") 0) | |
7158 | (const_int 32)) (const_int 32))) | |
7159 | (const_int 0))) | |
7160 | (set (match_operand:DI 0 "register_operand" "=d") | |
7161 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7162 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7163 | "lcgfr\t%0,%1" |
729e750f WG |
7164 | [(set_attr "op_type" "RRE") |
7165 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7166 | |
26a89301 UW |
7167 | (define_insn "*negdi2_sign" |
7168 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7169 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7170 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7171 | "TARGET_ZARCH" |
26a89301 | 7172 | "lcgfr\t%0,%1" |
729e750f WG |
7173 | [(set_attr "op_type" "RRE") |
7174 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7175 | |
43a09b63 | 7176 | ; lcr, lcgr |
9a91a21f | 7177 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7178 | [(set (reg CC_REGNUM) |
9a91a21f | 7179 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7180 | (const_int 0))) |
9a91a21f AS |
7181 | (set (match_operand:GPR 0 "register_operand" "=d") |
7182 | (neg:GPR (match_dup 1)))] | |
7183 | "s390_match_ccmode (insn, CCAmode)" | |
7184 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7185 | [(set_attr "op_type" "RR<E>") |
7186 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7187 | |
7188 | ; lcr, lcgr | |
9a91a21f | 7189 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7190 | [(set (reg CC_REGNUM) |
9a91a21f | 7191 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7192 | (const_int 0))) |
9a91a21f AS |
7193 | (clobber (match_scratch:GPR 0 "=d"))] |
7194 | "s390_match_ccmode (insn, CCAmode)" | |
7195 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7196 | [(set_attr "op_type" "RR<E>") |
7197 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7198 | |
7199 | ; lcr, lcgr | |
9a91a21f AS |
7200 | (define_insn "*neg<mode>2" |
7201 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7202 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7203 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
7204 | "" |
7205 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7206 | [(set_attr "op_type" "RR<E>") |
7207 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 7208 | |
26a89301 | 7209 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
7210 | [(set (match_operand:DI 0 "register_operand" "=d") |
7211 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 7212 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7213 | "!TARGET_ZARCH" |
26a89301 UW |
7214 | "#" |
7215 | "&& reload_completed" | |
7216 | [(parallel | |
7217 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 7218 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 7219 | (parallel |
ae156f85 | 7220 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
7221 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
7222 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
7223 | (set (pc) | |
ae156f85 | 7224 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
7225 | (pc) |
7226 | (label_ref (match_dup 6)))) | |
7227 | (parallel | |
7228 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 7229 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
7230 | (match_dup 6)] |
7231 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7232 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7233 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7234 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7235 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 7236 | |
9db1d521 | 7237 | ; |
f5905b37 | 7238 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7239 | ; |
7240 | ||
f5905b37 | 7241 | (define_expand "neg<mode>2" |
9db1d521 | 7242 | [(parallel |
7b6baae1 AK |
7243 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7244 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7245 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7246 | "TARGET_HARD_FLOAT" |
7247 | "") | |
7248 | ||
43a09b63 | 7249 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7250 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7251 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7252 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7253 | (match_operand:BFP 2 "const0_operand" ""))) | |
7254 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7255 | (neg:BFP (match_dup 1)))] | |
142cd70f | 7256 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7257 | "lc<xde>br\t%0,%1" |
26a89301 | 7258 | [(set_attr "op_type" "RRE") |
f5905b37 | 7259 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7260 | |
7261 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 7262 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7263 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7264 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7265 | (match_operand:BFP 2 "const0_operand" ""))) | |
7266 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7267 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7268 | "lc<xde>br\t%0,%1" |
26a89301 | 7269 | [(set_attr "op_type" "RRE") |
f5905b37 | 7270 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7271 | |
85dae55a AK |
7272 | ; lcdfr |
7273 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
7274 | [(set (match_operand:FP 0 "register_operand" "=f") |
7275 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7276 | "TARGET_DFP" |
85dae55a AK |
7277 | "lcdfr\t%0,%1" |
7278 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7279 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7280 | |
43a09b63 | 7281 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7282 | (define_insn "*neg<mode>2" |
7b6baae1 AK |
7283 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7284 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7285 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7286 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7287 | "lc<xde>br\t%0,%1" |
077dab3b | 7288 | [(set_attr "op_type" "RRE") |
f5905b37 | 7289 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7290 | |
9db1d521 HP |
7291 | |
7292 | ;; | |
7293 | ;;- Absolute value instructions. | |
7294 | ;; | |
7295 | ||
7296 | ; | |
9a91a21f | 7297 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
7298 | ; |
7299 | ||
26a89301 | 7300 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 7301 | [(set (reg CC_REGNUM) |
26a89301 UW |
7302 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7303 | (match_operand:SI 1 "register_operand" "d") 0) | |
7304 | (const_int 32)) (const_int 32))) | |
7305 | (const_int 0))) | |
7306 | (set (match_operand:DI 0 "register_operand" "=d") | |
7307 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7308 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7309 | "lpgfr\t%0,%1" |
729e750f WG |
7310 | [(set_attr "op_type" "RRE") |
7311 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
7312 | |
7313 | (define_insn "*absdi2_sign" | |
7314 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7315 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7316 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7317 | "TARGET_ZARCH" |
26a89301 | 7318 | "lpgfr\t%0,%1" |
729e750f WG |
7319 | [(set_attr "op_type" "RRE") |
7320 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7321 | |
43a09b63 | 7322 | ; lpr, lpgr |
9a91a21f | 7323 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7324 | [(set (reg CC_REGNUM) |
9a91a21f | 7325 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 7326 | (const_int 0))) |
9a91a21f AS |
7327 | (set (match_operand:GPR 0 "register_operand" "=d") |
7328 | (abs:GPR (match_dup 1)))] | |
26a89301 | 7329 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7330 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7331 | [(set_attr "op_type" "RR<E>") |
7332 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 7333 | |
9381e3f1 | 7334 | ; lpr, lpgr |
9a91a21f | 7335 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7336 | [(set (reg CC_REGNUM) |
9a91a21f | 7337 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7338 | (const_int 0))) |
9a91a21f | 7339 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7340 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7341 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7342 | [(set_attr "op_type" "RR<E>") |
7343 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7344 | |
7345 | ; lpr, lpgr | |
9a91a21f AS |
7346 | (define_insn "abs<mode>2" |
7347 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7348 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7349 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 7350 | "" |
9a91a21f | 7351 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7352 | [(set_attr "op_type" "RR<E>") |
7353 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 7354 | |
9db1d521 | 7355 | ; |
f5905b37 | 7356 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7357 | ; |
7358 | ||
f5905b37 | 7359 | (define_expand "abs<mode>2" |
9db1d521 | 7360 | [(parallel |
7b6baae1 AK |
7361 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7362 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7363 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7364 | "TARGET_HARD_FLOAT" |
7365 | "") | |
7366 | ||
43a09b63 | 7367 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7368 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7369 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7370 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7371 | (match_operand:BFP 2 "const0_operand" ""))) | |
7372 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7373 | (abs:BFP (match_dup 1)))] | |
142cd70f | 7374 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7375 | "lp<xde>br\t%0,%1" |
26a89301 | 7376 | [(set_attr "op_type" "RRE") |
f5905b37 | 7377 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7378 | |
7379 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 7380 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7381 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7382 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7383 | (match_operand:BFP 2 "const0_operand" ""))) | |
7384 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7385 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7386 | "lp<xde>br\t%0,%1" |
26a89301 | 7387 | [(set_attr "op_type" "RRE") |
f5905b37 | 7388 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7389 | |
85dae55a AK |
7390 | ; lpdfr |
7391 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
7392 | [(set (match_operand:FP 0 "register_operand" "=f") |
7393 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7394 | "TARGET_DFP" |
85dae55a AK |
7395 | "lpdfr\t%0,%1" |
7396 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7397 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7398 | |
43a09b63 | 7399 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7400 | (define_insn "*abs<mode>2" |
7b6baae1 AK |
7401 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7402 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7403 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7404 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7405 | "lp<xde>br\t%0,%1" |
077dab3b | 7406 | [(set_attr "op_type" "RRE") |
f5905b37 | 7407 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7408 | |
9db1d521 | 7409 | |
3ef093a8 AK |
7410 | ;; |
7411 | ;;- Negated absolute value instructions | |
7412 | ;; | |
7413 | ||
7414 | ; | |
7415 | ; Integer | |
7416 | ; | |
7417 | ||
26a89301 | 7418 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 7419 | [(set (reg CC_REGNUM) |
26a89301 UW |
7420 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7421 | (match_operand:SI 1 "register_operand" "d") 0) | |
7422 | (const_int 32)) (const_int 32)))) | |
7423 | (const_int 0))) | |
7424 | (set (match_operand:DI 0 "register_operand" "=d") | |
7425 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 7426 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7427 | "lngfr\t%0,%1" |
729e750f WG |
7428 | [(set_attr "op_type" "RRE") |
7429 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7430 | |
26a89301 UW |
7431 | (define_insn "*negabsdi2_sign" |
7432 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7433 | (neg:DI (abs:DI (sign_extend:DI | |
7434 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 7435 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7436 | "TARGET_ZARCH" |
26a89301 | 7437 | "lngfr\t%0,%1" |
729e750f WG |
7438 | [(set_attr "op_type" "RRE") |
7439 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 7440 | |
43a09b63 | 7441 | ; lnr, lngr |
9a91a21f | 7442 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7443 | [(set (reg CC_REGNUM) |
9a91a21f | 7444 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7445 | (const_int 0))) |
9a91a21f AS |
7446 | (set (match_operand:GPR 0 "register_operand" "=d") |
7447 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 7448 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7449 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7450 | [(set_attr "op_type" "RR<E>") |
7451 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7452 | |
7453 | ; lnr, lngr | |
9a91a21f | 7454 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7455 | [(set (reg CC_REGNUM) |
9a91a21f | 7456 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7457 | (const_int 0))) |
9a91a21f | 7458 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7459 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7460 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7461 | [(set_attr "op_type" "RR<E>") |
7462 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7463 | |
7464 | ; lnr, lngr | |
9a91a21f AS |
7465 | (define_insn "*negabs<mode>2" |
7466 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7467 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 7468 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 7469 | "" |
9a91a21f | 7470 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7471 | [(set_attr "op_type" "RR<E>") |
7472 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7473 | |
3ef093a8 AK |
7474 | ; |
7475 | ; Floating point | |
7476 | ; | |
7477 | ||
43a09b63 | 7478 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7479 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7480 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7481 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7482 | (match_operand:BFP 2 "const0_operand" ""))) | |
7483 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7484 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 7485 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7486 | "ln<xde>br\t%0,%1" |
26a89301 | 7487 | [(set_attr "op_type" "RRE") |
f5905b37 | 7488 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7489 | |
7490 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 7491 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7492 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7493 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7494 | (match_operand:BFP 2 "const0_operand" ""))) | |
7495 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7496 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7497 | "ln<xde>br\t%0,%1" |
26a89301 | 7498 | [(set_attr "op_type" "RRE") |
f5905b37 | 7499 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7500 | |
85dae55a AK |
7501 | ; lndfr |
7502 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
7503 | [(set (match_operand:FP 0 "register_operand" "=f") |
7504 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 7505 | "TARGET_DFP" |
85dae55a AK |
7506 | "lndfr\t%0,%1" |
7507 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7508 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7509 | |
43a09b63 | 7510 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7511 | (define_insn "*negabs<mode>2" |
7b6baae1 AK |
7512 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7513 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))) | |
ae156f85 | 7514 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7515 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7516 | "ln<xde>br\t%0,%1" |
26a89301 | 7517 | [(set_attr "op_type" "RRE") |
f5905b37 | 7518 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 7519 | |
4023fb28 UW |
7520 | ;; |
7521 | ;;- Square root instructions. | |
7522 | ;; | |
7523 | ||
7524 | ; | |
f5905b37 | 7525 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
7526 | ; |
7527 | ||
9381e3f1 | 7528 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 7529 | (define_insn "sqrt<mode>2" |
7b6baae1 AK |
7530 | [(set (match_operand:BFP 0 "register_operand" "=f,f") |
7531 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 7532 | "TARGET_HARD_FLOAT" |
4023fb28 | 7533 | "@ |
f61a2c7d AK |
7534 | sq<xde>br\t%0,%1 |
7535 | sq<xde>b\t%0,%1" | |
a036c6f7 | 7536 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 7537 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 7538 | |
9db1d521 HP |
7539 | |
7540 | ;; | |
7541 | ;;- One complement instructions. | |
7542 | ;; | |
7543 | ||
7544 | ; | |
342cf42b | 7545 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 7546 | ; |
c7453384 | 7547 | |
342cf42b | 7548 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 7549 | [(parallel |
342cf42b AS |
7550 | [(set (match_operand:INT 0 "register_operand" "") |
7551 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
7552 | (const_int -1))) | |
ae156f85 | 7553 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 7554 | "" |
4023fb28 | 7555 | "") |
9db1d521 HP |
7556 | |
7557 | ||
ec24698e UW |
7558 | ;; |
7559 | ;; Find leftmost bit instructions. | |
7560 | ;; | |
7561 | ||
7562 | (define_expand "clzdi2" | |
7563 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7564 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 7565 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7566 | { |
7567 | rtx insn, clz_equal; | |
7568 | rtx wide_reg = gen_reg_rtx (TImode); | |
7569 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
7570 | ||
7571 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
7572 | ||
7573 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
7574 | ||
9381e3f1 | 7575 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 7576 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
7577 | |
7578 | DONE; | |
7579 | }) | |
7580 | ||
7581 | (define_insn "clztidi2" | |
7582 | [(set (match_operand:TI 0 "register_operand" "=d") | |
7583 | (ior:TI | |
9381e3f1 WG |
7584 | (ashift:TI |
7585 | (zero_extend:TI | |
ec24698e UW |
7586 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
7587 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
7588 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 7589 | |
ec24698e UW |
7590 | (const_int 64)) |
7591 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
7592 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 7593 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 7594 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 7595 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7596 | "flogr\t%0,%1" |
7597 | [(set_attr "op_type" "RRE")]) | |
7598 | ||
7599 | ||
9db1d521 HP |
7600 | ;; |
7601 | ;;- Rotate instructions. | |
7602 | ;; | |
7603 | ||
7604 | ; | |
9a91a21f | 7605 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
7606 | ; |
7607 | ||
43a09b63 | 7608 | ; rll, rllg |
9a91a21f AS |
7609 | (define_insn "rotl<mode>3" |
7610 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7611 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 7612 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 7613 | "TARGET_CPU_ZARCH" |
9a91a21f | 7614 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 7615 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
7616 | (set_attr "atype" "reg") |
7617 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7618 | |
43a09b63 | 7619 | ; rll, rllg |
4989e88a AK |
7620 | (define_insn "*rotl<mode>3_and" |
7621 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7622 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7623 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7624 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7625 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
7626 | "rll<g>\t%0,%1,%Y2" | |
7627 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
7628 | (set_attr "atype" "reg") |
7629 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7630 | |
9db1d521 HP |
7631 | |
7632 | ;; | |
f337b930 | 7633 | ;;- Shift instructions. |
9db1d521 | 7634 | ;; |
9db1d521 HP |
7635 | |
7636 | ; | |
1b48c8cc | 7637 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 7638 | ; Left shifts and logical right shifts |
9db1d521 | 7639 | |
1b48c8cc AS |
7640 | (define_expand "<shift><mode>3" |
7641 | [(set (match_operand:DSI 0 "register_operand" "") | |
7642 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
7643 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
7644 | "" |
7645 | "") | |
7646 | ||
43a09b63 | 7647 | ; sldl, srdl |
f337b930 | 7648 | (define_insn "*<shift>di3_31" |
ac32b25e | 7649 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 7650 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7651 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9602b6a1 | 7652 | "!TARGET_ZARCH" |
f337b930 | 7653 | "s<lr>dl\t%0,%Y2" |
077dab3b | 7654 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
7655 | (set_attr "atype" "reg") |
7656 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 7657 | |
65b1d8ea | 7658 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7659 | (define_insn "*<shift><mode>3" |
65b1d8ea AK |
7660 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7661 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7662 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] | |
1b48c8cc | 7663 | "" |
65b1d8ea AK |
7664 | "@ |
7665 | s<lr>l<g>\t%0,<1>%Y2 | |
7666 | s<lr>l<gk>\t%0,%1,%Y2" | |
7667 | [(set_attr "op_type" "RS<E>,RSY") | |
7668 | (set_attr "atype" "reg,reg") | |
7669 | (set_attr "cpu_facility" "*,z196") | |
7670 | (set_attr "z10prop" "z10_super_E1,*")]) | |
9db1d521 | 7671 | |
43a09b63 | 7672 | ; sldl, srdl |
4989e88a AK |
7673 | (define_insn "*<shift>di3_31_and" |
7674 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7675 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7676 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7677 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
9602b6a1 | 7678 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7679 | "s<lr>dl\t%0,%Y2" |
7680 | [(set_attr "op_type" "RS") | |
7681 | (set_attr "atype" "reg")]) | |
7682 | ||
65b1d8ea | 7683 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7684 | (define_insn "*<shift><mode>3_and" |
65b1d8ea AK |
7685 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7686 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7687 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7688 | (match_operand:SI 3 "const_int_operand" "n,n"))))] | |
1b48c8cc | 7689 | "(INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7690 | "@ |
7691 | s<lr>l<g>\t%0,<1>%Y2 | |
7692 | s<lr>l<gk>\t%0,%1,%Y2" | |
7693 | [(set_attr "op_type" "RS<E>,RSY") | |
7694 | (set_attr "atype" "reg,reg") | |
7695 | (set_attr "cpu_facility" "*,z196") | |
7696 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7697 | |
9db1d521 | 7698 | ; |
1b48c8cc | 7699 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 7700 | ; Arithmetic right shifts |
9db1d521 | 7701 | |
1b48c8cc | 7702 | (define_expand "ashr<mode>3" |
9db1d521 | 7703 | [(parallel |
1b48c8cc AS |
7704 | [(set (match_operand:DSI 0 "register_operand" "") |
7705 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
7706 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 7707 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7708 | "" |
7709 | "") | |
7710 | ||
ecbe845e | 7711 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 7712 | [(set (reg CC_REGNUM) |
ac32b25e | 7713 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7714 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7715 | (const_int 0))) |
ac32b25e | 7716 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e | 7717 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7718 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7719 | "srda\t%0,%Y2" |
077dab3b HP |
7720 | [(set_attr "op_type" "RS") |
7721 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
7722 | |
7723 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 7724 | [(set (reg CC_REGNUM) |
ac32b25e | 7725 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7726 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7727 | (const_int 0))) |
ac32b25e | 7728 | (clobber (match_scratch:DI 0 "=d"))] |
9602b6a1 | 7729 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7730 | "srda\t%0,%Y2" |
077dab3b HP |
7731 | [(set_attr "op_type" "RS") |
7732 | (set_attr "atype" "reg")]) | |
ecbe845e | 7733 | |
9db1d521 | 7734 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
7735 | [(set (match_operand:DI 0 "register_operand" "=d") |
7736 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 7737 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 7738 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7739 | "!TARGET_ZARCH" |
ac32b25e | 7740 | "srda\t%0,%Y2" |
077dab3b HP |
7741 | [(set_attr "op_type" "RS") |
7742 | (set_attr "atype" "reg")]) | |
c7453384 | 7743 | |
65b1d8ea | 7744 | ; sra, srag, srak |
1b48c8cc | 7745 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 7746 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7747 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7748 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7749 | (const_int 0))) |
65b1d8ea | 7750 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc AS |
7751 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] |
7752 | "s390_match_ccmode(insn, CCSmode)" | |
65b1d8ea AK |
7753 | "@ |
7754 | sra<g>\t%0,<1>%Y2 | |
7755 | sra<gk>\t%0,%1,%Y2" | |
7756 | [(set_attr "op_type" "RS<E>,RSY") | |
7757 | (set_attr "atype" "reg,reg") | |
7758 | (set_attr "cpu_facility" "*,z196") | |
7759 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7760 | |
65b1d8ea | 7761 | ; sra, srag, srak |
1b48c8cc | 7762 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 7763 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7764 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7765 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7766 | (const_int 0))) |
65b1d8ea | 7767 | (clobber (match_scratch:GPR 0 "=d,d"))] |
1b48c8cc | 7768 | "s390_match_ccmode(insn, CCSmode)" |
65b1d8ea AK |
7769 | "@ |
7770 | sra<g>\t%0,<1>%Y2 | |
7771 | sra<gk>\t%0,%1,%Y2" | |
7772 | [(set_attr "op_type" "RS<E>,RSY") | |
7773 | (set_attr "atype" "reg,reg") | |
7774 | (set_attr "cpu_facility" "*,z196") | |
7775 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7776 | |
43a09b63 | 7777 | ; sra, srag |
1b48c8cc | 7778 | (define_insn "*ashr<mode>3" |
65b1d8ea AK |
7779 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7780 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7781 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) | |
ae156f85 | 7782 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 7783 | "" |
65b1d8ea AK |
7784 | "@ |
7785 | sra<g>\t%0,<1>%Y2 | |
7786 | sra<gk>\t%0,%1,%Y2" | |
7787 | [(set_attr "op_type" "RS<E>,RSY") | |
7788 | (set_attr "atype" "reg,reg") | |
7789 | (set_attr "cpu_facility" "*,z196") | |
7790 | (set_attr "z10prop" "z10_super_E1,*")]) | |
077dab3b | 7791 | |
9db1d521 | 7792 | |
4989e88a AK |
7793 | ; shift pattern with implicit ANDs |
7794 | ||
7795 | (define_insn "*ashrdi3_cc_31_and" | |
7796 | [(set (reg CC_REGNUM) | |
7797 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7798 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7799 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7800 | (const_int 0))) | |
7801 | (set (match_operand:DI 0 "register_operand" "=d") | |
7802 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
9602b6a1 | 7803 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7804 | && (INTVAL (operands[3]) & 63) == 63" |
7805 | "srda\t%0,%Y2" | |
7806 | [(set_attr "op_type" "RS") | |
7807 | (set_attr "atype" "reg")]) | |
7808 | ||
7809 | (define_insn "*ashrdi3_cconly_31_and" | |
7810 | [(set (reg CC_REGNUM) | |
7811 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7812 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7813 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7814 | (const_int 0))) | |
7815 | (clobber (match_scratch:DI 0 "=d"))] | |
9602b6a1 | 7816 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7817 | && (INTVAL (operands[3]) & 63) == 63" |
7818 | "srda\t%0,%Y2" | |
7819 | [(set_attr "op_type" "RS") | |
7820 | (set_attr "atype" "reg")]) | |
7821 | ||
7822 | (define_insn "*ashrdi3_31_and" | |
7823 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7824 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7825 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7826 | (match_operand:SI 3 "const_int_operand" "n")))) | |
7827 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 7828 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7829 | "srda\t%0,%Y2" |
7830 | [(set_attr "op_type" "RS") | |
7831 | (set_attr "atype" "reg")]) | |
7832 | ||
65b1d8ea | 7833 | ; sra, srag, srak |
1b48c8cc | 7834 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 7835 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7836 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7837 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7838 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7839 | (const_int 0))) |
65b1d8ea | 7840 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc | 7841 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] |
4989e88a | 7842 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7843 | "@ |
7844 | sra<g>\t%0,<1>%Y2 | |
7845 | sra<gk>\t%0,%1,%Y2" | |
7846 | [(set_attr "op_type" "RS<E>,RSY") | |
7847 | (set_attr "atype" "reg,reg") | |
7848 | (set_attr "cpu_facility" "*,z196") | |
7849 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7850 | |
65b1d8ea | 7851 | ; sra, srag, srak |
1b48c8cc | 7852 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 7853 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7854 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7855 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7856 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7857 | (const_int 0))) |
65b1d8ea | 7858 | (clobber (match_scratch:GPR 0 "=d,d"))] |
4989e88a | 7859 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7860 | "@ |
7861 | sra<g>\t%0,<1>%Y2 | |
7862 | sra<gk>\t%0,%1,%Y2" | |
7863 | [(set_attr "op_type" "RS<E>,RSY") | |
7864 | (set_attr "atype" "reg,reg") | |
7865 | (set_attr "cpu_facility" "*,z196") | |
7866 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7867 | |
65b1d8ea | 7868 | ; sra, srag, srak |
1b48c8cc | 7869 | (define_insn "*ashr<mode>3_and" |
65b1d8ea AK |
7870 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7871 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7872 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7873 | (match_operand:SI 3 "const_int_operand" "n,n")))) | |
4989e88a AK |
7874 | (clobber (reg:CC CC_REGNUM))] |
7875 | "(INTVAL (operands[3]) & 63) == 63" | |
65b1d8ea AK |
7876 | "@ |
7877 | sra<g>\t%0,<1>%Y2 | |
7878 | sra<gk>\t%0,%1,%Y2" | |
7879 | [(set_attr "op_type" "RS<E>,RSY") | |
7880 | (set_attr "atype" "reg,reg") | |
01496eca | 7881 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 7882 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 7883 | |
9db1d521 | 7884 | |
9db1d521 HP |
7885 | ;; |
7886 | ;; Branch instruction patterns. | |
7887 | ;; | |
7888 | ||
f90b7a5a | 7889 | (define_expand "cbranch<mode>4" |
fa77b251 | 7890 | [(set (pc) |
f90b7a5a PB |
7891 | (if_then_else (match_operator 0 "comparison_operator" |
7892 | [(match_operand:GPR 1 "register_operand" "") | |
7893 | (match_operand:GPR 2 "general_operand" "")]) | |
7894 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 7895 | (pc)))] |
ba956982 | 7896 | "" |
f90b7a5a PB |
7897 | "s390_emit_jump (operands[3], |
7898 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7899 | DONE;") | |
7900 | ||
7901 | (define_expand "cbranch<mode>4" | |
7902 | [(set (pc) | |
7903 | (if_then_else (match_operator 0 "comparison_operator" | |
7904 | [(match_operand:FP 1 "register_operand" "") | |
7905 | (match_operand:FP 2 "general_operand" "")]) | |
7906 | (label_ref (match_operand 3 "" "")) | |
7907 | (pc)))] | |
7908 | "TARGET_HARD_FLOAT" | |
7909 | "s390_emit_jump (operands[3], | |
7910 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7911 | DONE;") | |
7912 | ||
7913 | (define_expand "cbranchcc4" | |
7914 | [(set (pc) | |
7915 | (if_then_else (match_operator 0 "s390_eqne_operator" | |
7916 | [(match_operand 1 "cc_reg_operand" "") | |
7917 | (match_operand 2 "const0_operand" "")]) | |
7918 | (label_ref (match_operand 3 "" "")) | |
7919 | (pc)))] | |
7920 | "TARGET_HARD_FLOAT" | |
7921 | "s390_emit_jump (operands[3], | |
7922 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7923 | DONE;") | |
7924 | ||
ba956982 | 7925 | |
9db1d521 HP |
7926 | |
7927 | ;; | |
7928 | ;;- Conditional jump instructions. | |
7929 | ;; | |
7930 | ||
6590e19a UW |
7931 | (define_insn "*cjump_64" |
7932 | [(set (pc) | |
7933 | (if_then_else | |
5a3fe9b6 AK |
7934 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
7935 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
7936 | (label_ref (match_operand 0 "" "")) |
7937 | (pc)))] | |
7938 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7939 | { |
13e58269 | 7940 | if (get_attr_length (insn) == 4) |
d40c829f | 7941 | return "j%C1\t%l0"; |
6590e19a | 7942 | else |
d40c829f | 7943 | return "jg%C1\t%l0"; |
6590e19a UW |
7944 | } |
7945 | [(set_attr "op_type" "RI") | |
7946 | (set_attr "type" "branch") | |
7947 | (set (attr "length") | |
7948 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7949 | (const_int 4) (const_int 6)))]) | |
7950 | ||
7951 | (define_insn "*cjump_31" | |
7952 | [(set (pc) | |
7953 | (if_then_else | |
5a3fe9b6 AK |
7954 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
7955 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
7956 | (label_ref (match_operand 0 "" "")) |
7957 | (pc)))] | |
7958 | "!TARGET_CPU_ZARCH" | |
7959 | { | |
8d933e31 AS |
7960 | gcc_assert (get_attr_length (insn) == 4); |
7961 | return "j%C1\t%l0"; | |
10bbf137 | 7962 | } |
9db1d521 | 7963 | [(set_attr "op_type" "RI") |
077dab3b | 7964 | (set_attr "type" "branch") |
13e58269 | 7965 | (set (attr "length") |
d7f99b2c | 7966 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
7967 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
7968 | (const_int 4) (const_int 6)) | |
7969 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7970 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7971 | |
f314b9b1 | 7972 | (define_insn "*cjump_long" |
6590e19a UW |
7973 | [(set (pc) |
7974 | (if_then_else | |
ae156f85 | 7975 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 7976 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 7977 | (pc)))] |
9db1d521 | 7978 | "" |
f314b9b1 UW |
7979 | { |
7980 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7981 | return "b%C1r\t%0"; |
f314b9b1 | 7982 | else |
d40c829f | 7983 | return "b%C1\t%a0"; |
10bbf137 | 7984 | } |
c7453384 | 7985 | [(set (attr "op_type") |
f314b9b1 UW |
7986 | (if_then_else (match_operand 0 "register_operand" "") |
7987 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 7988 | (set_attr "type" "branch") |
077dab3b | 7989 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7990 | |
7991 | ||
7992 | ;; | |
7993 | ;;- Negated conditional jump instructions. | |
7994 | ;; | |
7995 | ||
6590e19a UW |
7996 | (define_insn "*icjump_64" |
7997 | [(set (pc) | |
7998 | (if_then_else | |
ae156f85 | 7999 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8000 | (pc) |
8001 | (label_ref (match_operand 0 "" ""))))] | |
8002 | "TARGET_CPU_ZARCH" | |
c7453384 | 8003 | { |
13e58269 | 8004 | if (get_attr_length (insn) == 4) |
d40c829f | 8005 | return "j%D1\t%l0"; |
6590e19a | 8006 | else |
d40c829f | 8007 | return "jg%D1\t%l0"; |
6590e19a UW |
8008 | } |
8009 | [(set_attr "op_type" "RI") | |
8010 | (set_attr "type" "branch") | |
8011 | (set (attr "length") | |
8012 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8013 | (const_int 4) (const_int 6)))]) | |
8014 | ||
8015 | (define_insn "*icjump_31" | |
8016 | [(set (pc) | |
8017 | (if_then_else | |
ae156f85 | 8018 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8019 | (pc) |
8020 | (label_ref (match_operand 0 "" ""))))] | |
8021 | "!TARGET_CPU_ZARCH" | |
8022 | { | |
8d933e31 AS |
8023 | gcc_assert (get_attr_length (insn) == 4); |
8024 | return "j%D1\t%l0"; | |
10bbf137 | 8025 | } |
9db1d521 | 8026 | [(set_attr "op_type" "RI") |
077dab3b | 8027 | (set_attr "type" "branch") |
13e58269 | 8028 | (set (attr "length") |
d7f99b2c | 8029 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8030 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8031 | (const_int 4) (const_int 6)) | |
8032 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8033 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8034 | |
f314b9b1 | 8035 | (define_insn "*icjump_long" |
6590e19a UW |
8036 | [(set (pc) |
8037 | (if_then_else | |
ae156f85 | 8038 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 8039 | (pc) |
4fe6dea8 | 8040 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 8041 | "" |
f314b9b1 UW |
8042 | { |
8043 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8044 | return "b%D1r\t%0"; |
f314b9b1 | 8045 | else |
d40c829f | 8046 | return "b%D1\t%a0"; |
10bbf137 | 8047 | } |
c7453384 | 8048 | [(set (attr "op_type") |
f314b9b1 UW |
8049 | (if_then_else (match_operand 0 "register_operand" "") |
8050 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8051 | (set_attr "type" "branch") |
8052 | (set_attr "atype" "agen")]) | |
9db1d521 | 8053 | |
4456530d HP |
8054 | ;; |
8055 | ;;- Trap instructions. | |
8056 | ;; | |
8057 | ||
8058 | (define_insn "trap" | |
8059 | [(trap_if (const_int 1) (const_int 0))] | |
8060 | "" | |
d40c829f | 8061 | "j\t.+2" |
6590e19a | 8062 | [(set_attr "op_type" "RI") |
077dab3b | 8063 | (set_attr "type" "branch")]) |
4456530d | 8064 | |
f90b7a5a PB |
8065 | (define_expand "ctrap<mode>4" |
8066 | [(trap_if (match_operator 0 "comparison_operator" | |
8067 | [(match_operand:GPR 1 "register_operand" "") | |
8068 | (match_operand:GPR 2 "general_operand" "")]) | |
8069 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 8070 | "" |
f90b7a5a PB |
8071 | { |
8072 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8073 | operands[1], operands[2]); | |
8074 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8075 | DONE; | |
8076 | }) | |
8077 | ||
8078 | (define_expand "ctrap<mode>4" | |
8079 | [(trap_if (match_operator 0 "comparison_operator" | |
8080 | [(match_operand:FP 1 "register_operand" "") | |
8081 | (match_operand:FP 2 "general_operand" "")]) | |
8082 | (match_operand 3 "const0_operand" ""))] | |
8083 | "" | |
8084 | { | |
8085 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8086 | operands[1], operands[2]); | |
8087 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8088 | DONE; | |
8089 | }) | |
4456530d | 8090 | |
f90b7a5a PB |
8091 | (define_insn "condtrap" |
8092 | [(trap_if (match_operator 0 "s390_comparison" | |
8093 | [(match_operand 1 "cc_reg_operand" "c") | |
8094 | (const_int 0)]) | |
4456530d HP |
8095 | (const_int 0))] |
8096 | "" | |
d40c829f | 8097 | "j%C0\t.+2"; |
077dab3b HP |
8098 | [(set_attr "op_type" "RI") |
8099 | (set_attr "type" "branch")]) | |
9db1d521 | 8100 | |
963fc8d0 AK |
8101 | ; crt, cgrt, cit, cgit |
8102 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
8103 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
8104 | [(match_operand:GPR 1 "register_operand" "d,d") | |
8105 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
8106 | (const_int 0))] | |
8107 | "TARGET_Z10" | |
8108 | "@ | |
8109 | c<g>rt%C0\t%1,%2 | |
8110 | c<g>it%C0\t%1,%h2" | |
8111 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 8112 | (set_attr "type" "branch") |
729e750f | 8113 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 8114 | |
22ac2c2f | 8115 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
8116 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
8117 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
22ac2c2f AK |
8118 | [(match_operand:GPR 1 "register_operand" "d,d, d") |
8119 | (match_operand:GPR 2 "general_operand" "d,D,RT")]) | |
963fc8d0 AK |
8120 | (const_int 0))] |
8121 | "TARGET_Z10" | |
8122 | "@ | |
8123 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
8124 | cl<gf>it%C0\t%1,%x2 |
8125 | cl<g>t%C0\t%1,%2" | |
8126 | [(set_attr "op_type" "RRF,RIE,RSY") | |
8127 | (set_attr "type" "branch") | |
8128 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
8129 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
8130 | ||
8131 | ; lat, lgat | |
8132 | (define_insn "*load_and_trap<mode>" | |
8133 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") | |
8134 | (const_int 0)) | |
8135 | (const_int 0)) | |
8136 | (set (match_operand:GPR 1 "register_operand" "=d") | |
8137 | (match_dup 0))] | |
8138 | "TARGET_ZEC12" | |
8139 | "l<g>at\t%1,%0" | |
8140 | [(set_attr "op_type" "RXY")]) | |
8141 | ||
963fc8d0 | 8142 | |
9db1d521 | 8143 | ;; |
0a3bdf9d | 8144 | ;;- Loop instructions. |
9db1d521 | 8145 | ;; |
0a3bdf9d UW |
8146 | ;; This is all complicated by the fact that since this is a jump insn |
8147 | ;; we must handle our own output reloads. | |
c7453384 | 8148 | |
f1149235 AK |
8149 | ;; branch on index |
8150 | ||
8151 | ; This splitter will be matched by combine and has to add the 2 moves | |
8152 | ; necessary to load the compare and the increment values into a | |
8153 | ; register pair as needed by brxle. | |
8154 | ||
8155 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
8156 | [(set (pc) | |
8157 | (if_then_else | |
8158 | (match_operator 6 "s390_brx_operator" | |
8159 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
8160 | (match_operand:GPR 2 "general_operand" "")) | |
8161 | (match_operand:GPR 3 "register_operand" "")]) | |
8162 | (label_ref (match_operand 0 "" "")) | |
8163 | (pc))) | |
8164 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
8165 | (plus:GPR (match_dup 1) (match_dup 2))) | |
8166 | (clobber (match_scratch:GPR 5 ""))] | |
8167 | "TARGET_CPU_ZARCH" | |
8168 | "#" | |
8169 | "!reload_completed && !reload_in_progress" | |
8170 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
8171 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
8172 | (parallel [(set (pc) | |
8173 | (if_then_else | |
8174 | (match_op_dup 6 | |
8175 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
8176 | (match_dup 8)]) | |
8177 | (label_ref (match_dup 0)) | |
8178 | (pc))) | |
8179 | (set (match_dup 4) | |
8180 | (plus:GPR (match_dup 1) (match_dup 7))) | |
8181 | (clobber (match_dup 5)) | |
8182 | (clobber (reg:CC CC_REGNUM))])] | |
8183 | { | |
8184 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
8185 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
8186 | gen_highpart (word_mode, dreg)); | |
8187 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
8188 | gen_lowpart (word_mode, dreg)); | |
8189 | }) | |
8190 | ||
8191 | ; brxlg, brxhg | |
8192 | ||
8193 | (define_insn_and_split "*brxg_64bit" | |
8194 | [(set (pc) | |
8195 | (if_then_else | |
8196 | (match_operator 5 "s390_brx_operator" | |
8197 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
8198 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
8199 | (subreg:DI (match_dup 2) 8)]) | |
8200 | (label_ref (match_operand 0 "" "")) | |
8201 | (pc))) | |
8202 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
8203 | (plus:DI (match_dup 1) | |
8204 | (subreg:DI (match_dup 2) 0))) | |
8205 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
8206 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8207 | "TARGET_ZARCH" |
f1149235 AK |
8208 | { |
8209 | if (which_alternative != 0) | |
8210 | return "#"; | |
8211 | else if (get_attr_length (insn) == 6) | |
8212 | return "brx%E5g\t%1,%2,%l0"; | |
8213 | else | |
8214 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
8215 | } | |
8216 | "&& reload_completed | |
8217 | && (!REG_P (operands[3]) | |
8218 | || !rtx_equal_p (operands[1], operands[3]))" | |
8219 | [(set (match_dup 4) (match_dup 1)) | |
8220 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
8221 | (clobber (reg:CC CC_REGNUM))]) | |
8222 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
8223 | (set (match_dup 3) (match_dup 4)) | |
8224 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8225 | (label_ref (match_dup 0)) | |
8226 | (pc)))] | |
8227 | "" | |
8228 | [(set_attr "op_type" "RIE") | |
8229 | (set_attr "type" "branch") | |
8230 | (set (attr "length") | |
8231 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8232 | (const_int 6) (const_int 16)))]) | |
8233 | ||
8234 | ; brxle, brxh | |
8235 | ||
8236 | (define_insn_and_split "*brx_64bit" | |
8237 | [(set (pc) | |
8238 | (if_then_else | |
8239 | (match_operator 5 "s390_brx_operator" | |
8240 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8241 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
8242 | (subreg:SI (match_dup 2) 12)]) | |
8243 | (label_ref (match_operand 0 "" "")) | |
8244 | (pc))) | |
8245 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8246 | (plus:SI (match_dup 1) | |
8247 | (subreg:SI (match_dup 2) 4))) | |
8248 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8249 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8250 | "TARGET_ZARCH" |
f1149235 AK |
8251 | { |
8252 | if (which_alternative != 0) | |
8253 | return "#"; | |
8254 | else if (get_attr_length (insn) == 6) | |
8255 | return "brx%C5\t%1,%2,%l0"; | |
8256 | else | |
8257 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8258 | } | |
8259 | "&& reload_completed | |
8260 | && (!REG_P (operands[3]) | |
8261 | || !rtx_equal_p (operands[1], operands[3]))" | |
8262 | [(set (match_dup 4) (match_dup 1)) | |
8263 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8264 | (clobber (reg:CC CC_REGNUM))]) | |
8265 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
8266 | (set (match_dup 3) (match_dup 4)) | |
8267 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8268 | (label_ref (match_dup 0)) | |
8269 | (pc)))] | |
8270 | "" | |
8271 | [(set_attr "op_type" "RSI") | |
8272 | (set_attr "type" "branch") | |
8273 | (set (attr "length") | |
8274 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8275 | (const_int 6) (const_int 14)))]) | |
8276 | ||
8277 | ; brxle, brxh | |
8278 | ||
8279 | (define_insn_and_split "*brx_31bit" | |
8280 | [(set (pc) | |
8281 | (if_then_else | |
8282 | (match_operator 5 "s390_brx_operator" | |
8283 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8284 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
8285 | (subreg:SI (match_dup 2) 4)]) | |
8286 | (label_ref (match_operand 0 "" "")) | |
8287 | (pc))) | |
8288 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8289 | (plus:SI (match_dup 1) | |
8290 | (subreg:SI (match_dup 2) 0))) | |
8291 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8292 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8293 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
8294 | { |
8295 | if (which_alternative != 0) | |
8296 | return "#"; | |
8297 | else if (get_attr_length (insn) == 6) | |
8298 | return "brx%C5\t%1,%2,%l0"; | |
8299 | else | |
8300 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8301 | } | |
8302 | "&& reload_completed | |
8303 | && (!REG_P (operands[3]) | |
8304 | || !rtx_equal_p (operands[1], operands[3]))" | |
8305 | [(set (match_dup 4) (match_dup 1)) | |
8306 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
8307 | (clobber (reg:CC CC_REGNUM))]) | |
8308 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8309 | (set (match_dup 3) (match_dup 4)) | |
8310 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8311 | (label_ref (match_dup 0)) | |
8312 | (pc)))] | |
8313 | "" | |
8314 | [(set_attr "op_type" "RSI") | |
8315 | (set_attr "type" "branch") | |
8316 | (set (attr "length") | |
8317 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8318 | (const_int 6) (const_int 14)))]) | |
8319 | ||
8320 | ||
8321 | ;; branch on count | |
8322 | ||
0a3bdf9d UW |
8323 | (define_expand "doloop_end" |
8324 | [(use (match_operand 0 "" "")) ; loop pseudo | |
8325 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
8326 | (use (match_operand 2 "" "")) ; max iterations | |
8327 | (use (match_operand 3 "" "")) ; loop level | |
2407343c JR |
8328 | (use (match_operand 4 "" "")) ; label |
8329 | (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0 | |
0a3bdf9d | 8330 | "" |
0a3bdf9d | 8331 | { |
6590e19a UW |
8332 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
8333 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
8334 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
8335 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
9602b6a1 | 8336 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
0a3bdf9d UW |
8337 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); |
8338 | else | |
8339 | FAIL; | |
8340 | ||
8341 | DONE; | |
10bbf137 | 8342 | }) |
0a3bdf9d | 8343 | |
6590e19a | 8344 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
8345 | [(set (pc) |
8346 | (if_then_else | |
7e665d18 | 8347 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8348 | (const_int 1)) |
8349 | (label_ref (match_operand 0 "" "")) | |
8350 | (pc))) | |
7e665d18 | 8351 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8352 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8353 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8354 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8355 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8356 | { |
8357 | if (which_alternative != 0) | |
10bbf137 | 8358 | return "#"; |
0a3bdf9d | 8359 | else if (get_attr_length (insn) == 4) |
d40c829f | 8360 | return "brct\t%1,%l0"; |
6590e19a | 8361 | else |
545d16ff | 8362 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
8363 | } |
8364 | "&& reload_completed | |
8365 | && (! REG_P (operands[2]) | |
8366 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8367 | [(set (match_dup 3) (match_dup 1)) |
8368 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8369 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8370 | (const_int 0))) | |
8371 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8372 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8373 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8374 | (label_ref (match_dup 0)) |
8375 | (pc)))] | |
8376 | "" | |
8377 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8378 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8379 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8380 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8381 | (set_attr "type" "branch") |
8382 | (set (attr "length") | |
8383 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8384 | (const_int 4) (const_int 10)))]) | |
8385 | ||
8386 | (define_insn_and_split "doloop_si31" | |
8387 | [(set (pc) | |
8388 | (if_then_else | |
7e665d18 | 8389 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
8390 | (const_int 1)) |
8391 | (label_ref (match_operand 0 "" "")) | |
8392 | (pc))) | |
7e665d18 | 8393 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 8394 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8395 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8396 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
8397 | "!TARGET_CPU_ZARCH" |
8398 | { | |
8399 | if (which_alternative != 0) | |
8400 | return "#"; | |
8401 | else if (get_attr_length (insn) == 4) | |
8402 | return "brct\t%1,%l0"; | |
0a3bdf9d | 8403 | else |
8d933e31 | 8404 | gcc_unreachable (); |
10bbf137 | 8405 | } |
6590e19a UW |
8406 | "&& reload_completed |
8407 | && (! REG_P (operands[2]) | |
8408 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8409 | [(set (match_dup 3) (match_dup 1)) |
8410 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8411 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8412 | (const_int 0))) | |
8413 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8414 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8415 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8416 | (label_ref (match_dup 0)) |
8417 | (pc)))] | |
8418 | "" | |
0a3bdf9d | 8419 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
8420 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8421 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8422 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 8423 | (set_attr "type" "branch") |
0a3bdf9d | 8424 | (set (attr "length") |
d7f99b2c | 8425 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8426 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8427 | (const_int 4) (const_int 6)) | |
8428 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8429 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8430 | |
0a3bdf9d UW |
8431 | (define_insn "*doloop_si_long" |
8432 | [(set (pc) | |
8433 | (if_then_else | |
7e665d18 | 8434 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 8435 | (const_int 1)) |
4fe6dea8 | 8436 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 8437 | (pc))) |
7e665d18 | 8438 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 8439 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8440 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 8441 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8442 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8443 | { |
8444 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8445 | return "bctr\t%1,%0"; |
0a3bdf9d | 8446 | else |
d40c829f | 8447 | return "bct\t%1,%a0"; |
10bbf137 | 8448 | } |
c7453384 | 8449 | [(set (attr "op_type") |
0a3bdf9d UW |
8450 | (if_then_else (match_operand 0 "register_operand" "") |
8451 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8452 | (set_attr "type" "branch") |
729e750f | 8453 | (set_attr "atype" "agen") |
65b1d8ea AK |
8454 | (set_attr "z10prop" "z10_c") |
8455 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 8456 | |
6590e19a | 8457 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
8458 | [(set (pc) |
8459 | (if_then_else | |
7e665d18 | 8460 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8461 | (const_int 1)) |
8462 | (label_ref (match_operand 0 "" "")) | |
8463 | (pc))) | |
7e665d18 | 8464 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8465 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 8466 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 8467 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8468 | "TARGET_ZARCH" |
0a3bdf9d UW |
8469 | { |
8470 | if (which_alternative != 0) | |
10bbf137 | 8471 | return "#"; |
0a3bdf9d | 8472 | else if (get_attr_length (insn) == 4) |
d40c829f | 8473 | return "brctg\t%1,%l0"; |
0a3bdf9d | 8474 | else |
545d16ff | 8475 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 8476 | } |
6590e19a | 8477 | "&& reload_completed |
0a3bdf9d UW |
8478 | && (! REG_P (operands[2]) |
8479 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8480 | [(set (match_dup 3) (match_dup 1)) |
8481 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
8482 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
8483 | (const_int 0))) | |
8484 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
8485 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8486 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 8487 | (label_ref (match_dup 0)) |
0a3bdf9d | 8488 | (pc)))] |
6590e19a UW |
8489 | "" |
8490 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8491 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8492 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8493 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8494 | (set_attr "type" "branch") |
8495 | (set (attr "length") | |
8496 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8497 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
8498 | |
8499 | ;; | |
8500 | ;;- Unconditional jump instructions. | |
8501 | ;; | |
8502 | ||
8503 | ; | |
8504 | ; jump instruction pattern(s). | |
8505 | ; | |
8506 | ||
6590e19a UW |
8507 | (define_expand "jump" |
8508 | [(match_operand 0 "" "")] | |
9db1d521 | 8509 | "" |
6590e19a UW |
8510 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
8511 | ||
8512 | (define_insn "*jump64" | |
8513 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8514 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8515 | { |
13e58269 | 8516 | if (get_attr_length (insn) == 4) |
d40c829f | 8517 | return "j\t%l0"; |
6590e19a | 8518 | else |
d40c829f | 8519 | return "jg\t%l0"; |
6590e19a UW |
8520 | } |
8521 | [(set_attr "op_type" "RI") | |
8522 | (set_attr "type" "branch") | |
8523 | (set (attr "length") | |
8524 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8525 | (const_int 4) (const_int 6)))]) | |
8526 | ||
8527 | (define_insn "*jump31" | |
8528 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8529 | "!TARGET_CPU_ZARCH" | |
8530 | { | |
8d933e31 AS |
8531 | gcc_assert (get_attr_length (insn) == 4); |
8532 | return "j\t%l0"; | |
10bbf137 | 8533 | } |
9db1d521 | 8534 | [(set_attr "op_type" "RI") |
077dab3b | 8535 | (set_attr "type" "branch") |
13e58269 | 8536 | (set (attr "length") |
d7f99b2c | 8537 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8538 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8539 | (const_int 4) (const_int 6)) | |
8540 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8541 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
8542 | |
8543 | ; | |
8544 | ; indirect-jump instruction pattern(s). | |
8545 | ; | |
8546 | ||
8547 | (define_insn "indirect_jump" | |
4fe6dea8 | 8548 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 8549 | "" |
f314b9b1 UW |
8550 | { |
8551 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8552 | return "br\t%0"; |
f314b9b1 | 8553 | else |
d40c829f | 8554 | return "b\t%a0"; |
10bbf137 | 8555 | } |
c7453384 | 8556 | [(set (attr "op_type") |
f314b9b1 UW |
8557 | (if_then_else (match_operand 0 "register_operand" "") |
8558 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8559 | (set_attr "type" "branch") |
729e750f | 8560 | (set_attr "atype" "agen")]) |
9db1d521 HP |
8561 | |
8562 | ; | |
f314b9b1 | 8563 | ; casesi instruction pattern(s). |
9db1d521 HP |
8564 | ; |
8565 | ||
f314b9b1 | 8566 | (define_insn "casesi_jump" |
4fe6dea8 | 8567 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 8568 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 8569 | "" |
9db1d521 | 8570 | { |
f314b9b1 | 8571 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 8572 | return "br\t%0"; |
f314b9b1 | 8573 | else |
d40c829f | 8574 | return "b\t%a0"; |
10bbf137 | 8575 | } |
c7453384 | 8576 | [(set (attr "op_type") |
f314b9b1 UW |
8577 | (if_then_else (match_operand 0 "register_operand" "") |
8578 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8579 | (set_attr "type" "branch") |
8580 | (set_attr "atype" "agen")]) | |
9db1d521 | 8581 | |
f314b9b1 UW |
8582 | (define_expand "casesi" |
8583 | [(match_operand:SI 0 "general_operand" "") | |
8584 | (match_operand:SI 1 "general_operand" "") | |
8585 | (match_operand:SI 2 "general_operand" "") | |
8586 | (label_ref (match_operand 3 "" "")) | |
8587 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 8588 | "" |
f314b9b1 UW |
8589 | { |
8590 | rtx index = gen_reg_rtx (SImode); | |
8591 | rtx base = gen_reg_rtx (Pmode); | |
8592 | rtx target = gen_reg_rtx (Pmode); | |
8593 | ||
8594 | emit_move_insn (index, operands[0]); | |
8595 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
8596 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 8597 | operands[4]); |
f314b9b1 UW |
8598 | |
8599 | if (Pmode != SImode) | |
8600 | index = convert_to_mode (Pmode, index, 1); | |
8601 | if (GET_CODE (index) != REG) | |
8602 | index = copy_to_mode_reg (Pmode, index); | |
8603 | ||
8604 | if (TARGET_64BIT) | |
8605 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
8606 | else | |
a556fd39 | 8607 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 8608 | |
f314b9b1 UW |
8609 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
8610 | ||
542a8afa | 8611 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
8612 | emit_move_insn (target, index); |
8613 | ||
8614 | if (flag_pic) | |
8615 | target = gen_rtx_PLUS (Pmode, base, target); | |
8616 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
8617 | ||
8618 | DONE; | |
10bbf137 | 8619 | }) |
9db1d521 HP |
8620 | |
8621 | ||
8622 | ;; | |
8623 | ;;- Jump to subroutine. | |
8624 | ;; | |
8625 | ;; | |
8626 | ||
8627 | ; | |
8628 | ; untyped call instruction pattern(s). | |
8629 | ; | |
8630 | ||
8631 | ;; Call subroutine returning any type. | |
8632 | (define_expand "untyped_call" | |
8633 | [(parallel [(call (match_operand 0 "" "") | |
8634 | (const_int 0)) | |
8635 | (match_operand 1 "" "") | |
8636 | (match_operand 2 "" "")])] | |
8637 | "" | |
9db1d521 HP |
8638 | { |
8639 | int i; | |
8640 | ||
8641 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
8642 | ||
8643 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
8644 | { | |
8645 | rtx set = XVECEXP (operands[2], 0, i); | |
8646 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
8647 | } | |
8648 | ||
8649 | /* The optimizer does not know that the call sets the function value | |
8650 | registers we stored in the result block. We avoid problems by | |
8651 | claiming that all hard registers are used and clobbered at this | |
8652 | point. */ | |
8653 | emit_insn (gen_blockage ()); | |
8654 | ||
8655 | DONE; | |
10bbf137 | 8656 | }) |
9db1d521 HP |
8657 | |
8658 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
8659 | ;; all of memory. This blocks insns from being moved across this point. | |
8660 | ||
8661 | (define_insn "blockage" | |
10bbf137 | 8662 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 8663 | "" |
4023fb28 | 8664 | "" |
d5869ca0 UW |
8665 | [(set_attr "type" "none") |
8666 | (set_attr "length" "0")]) | |
4023fb28 | 8667 | |
9db1d521 | 8668 | ; |
ed9676cf | 8669 | ; sibcall patterns |
9db1d521 HP |
8670 | ; |
8671 | ||
ed9676cf | 8672 | (define_expand "sibcall" |
44b8152b | 8673 | [(call (match_operand 0 "" "") |
ed9676cf | 8674 | (match_operand 1 "" ""))] |
9db1d521 | 8675 | "" |
9db1d521 | 8676 | { |
ed9676cf AK |
8677 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
8678 | DONE; | |
8679 | }) | |
9db1d521 | 8680 | |
ed9676cf | 8681 | (define_insn "*sibcall_br" |
ae156f85 | 8682 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8683 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 8684 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8685 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
8686 | "br\t%%r1" | |
8687 | [(set_attr "op_type" "RR") | |
8688 | (set_attr "type" "branch") | |
8689 | (set_attr "atype" "agen")]) | |
9db1d521 | 8690 | |
ed9676cf AK |
8691 | (define_insn "*sibcall_brc" |
8692 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8693 | (match_operand 1 "const_int_operand" "n"))] | |
8694 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8695 | "j\t%0" | |
8696 | [(set_attr "op_type" "RI") | |
8697 | (set_attr "type" "branch")]) | |
9db1d521 | 8698 | |
ed9676cf AK |
8699 | (define_insn "*sibcall_brcl" |
8700 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8701 | (match_operand 1 "const_int_operand" "n"))] | |
8702 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8703 | "jg\t%0" | |
8704 | [(set_attr "op_type" "RIL") | |
8705 | (set_attr "type" "branch")]) | |
44b8152b | 8706 | |
ed9676cf AK |
8707 | ; |
8708 | ; sibcall_value patterns | |
8709 | ; | |
9e8327e3 | 8710 | |
ed9676cf AK |
8711 | (define_expand "sibcall_value" |
8712 | [(set (match_operand 0 "" "") | |
8713 | (call (match_operand 1 "" "") | |
8714 | (match_operand 2 "" "")))] | |
8715 | "" | |
8716 | { | |
8717 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 8718 | DONE; |
10bbf137 | 8719 | }) |
9db1d521 | 8720 | |
ed9676cf AK |
8721 | (define_insn "*sibcall_value_br" |
8722 | [(set (match_operand 0 "" "") | |
ae156f85 | 8723 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8724 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 8725 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8726 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
8727 | "br\t%%r1" | |
8728 | [(set_attr "op_type" "RR") | |
8729 | (set_attr "type" "branch") | |
8730 | (set_attr "atype" "agen")]) | |
8731 | ||
8732 | (define_insn "*sibcall_value_brc" | |
8733 | [(set (match_operand 0 "" "") | |
8734 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8735 | (match_operand 2 "const_int_operand" "n")))] | |
8736 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8737 | "j\t%1" | |
8738 | [(set_attr "op_type" "RI") | |
8739 | (set_attr "type" "branch")]) | |
8740 | ||
8741 | (define_insn "*sibcall_value_brcl" | |
8742 | [(set (match_operand 0 "" "") | |
8743 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8744 | (match_operand 2 "const_int_operand" "n")))] | |
8745 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8746 | "jg\t%1" | |
8747 | [(set_attr "op_type" "RIL") | |
8748 | (set_attr "type" "branch")]) | |
8749 | ||
8750 | ||
8751 | ; | |
8752 | ; call instruction pattern(s). | |
8753 | ; | |
8754 | ||
8755 | (define_expand "call" | |
8756 | [(call (match_operand 0 "" "") | |
8757 | (match_operand 1 "" "")) | |
8758 | (use (match_operand 2 "" ""))] | |
44b8152b | 8759 | "" |
ed9676cf | 8760 | { |
2f7e5a0d | 8761 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
8762 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
8763 | DONE; | |
8764 | }) | |
44b8152b | 8765 | |
9e8327e3 UW |
8766 | (define_insn "*bras" |
8767 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8768 | (match_operand 1 "const_int_operand" "n")) | |
8769 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8770 | "!SIBLING_CALL_P (insn) |
8771 | && TARGET_SMALL_EXEC | |
ed9676cf | 8772 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 8773 | "bras\t%2,%0" |
9db1d521 | 8774 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8775 | (set_attr "type" "jsr") |
8776 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8777 | |
9e8327e3 UW |
8778 | (define_insn "*brasl" |
8779 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8780 | (match_operand 1 "const_int_operand" "n")) | |
8781 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8782 | "!SIBLING_CALL_P (insn) |
8783 | && TARGET_CPU_ZARCH | |
ed9676cf | 8784 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8785 | "brasl\t%2,%0" |
8786 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8787 | (set_attr "type" "jsr") |
8788 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8789 | |
9e8327e3 | 8790 | (define_insn "*basr" |
4fe6dea8 | 8791 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
8792 | (match_operand 1 "const_int_operand" "n")) |
8793 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 8794 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8795 | { |
8796 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8797 | return "basr\t%2,%0"; | |
8798 | else | |
8799 | return "bas\t%2,%a0"; | |
8800 | } | |
8801 | [(set (attr "op_type") | |
8802 | (if_then_else (match_operand 0 "register_operand" "") | |
8803 | (const_string "RR") (const_string "RX"))) | |
8804 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8805 | (set_attr "atype" "agen") |
8806 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
8807 | |
8808 | ; | |
8809 | ; call_value instruction pattern(s). | |
8810 | ; | |
8811 | ||
8812 | (define_expand "call_value" | |
44b8152b UW |
8813 | [(set (match_operand 0 "" "") |
8814 | (call (match_operand 1 "" "") | |
8815 | (match_operand 2 "" ""))) | |
8816 | (use (match_operand 3 "" ""))] | |
9db1d521 | 8817 | "" |
9db1d521 | 8818 | { |
2f7e5a0d | 8819 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 8820 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 8821 | DONE; |
10bbf137 | 8822 | }) |
9db1d521 | 8823 | |
9e8327e3 | 8824 | (define_insn "*bras_r" |
c19ec8f9 | 8825 | [(set (match_operand 0 "" "") |
9e8327e3 | 8826 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 8827 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 8828 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
8829 | "!SIBLING_CALL_P (insn) |
8830 | && TARGET_SMALL_EXEC | |
ed9676cf | 8831 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8832 | "bras\t%3,%1" |
9db1d521 | 8833 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8834 | (set_attr "type" "jsr") |
8835 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8836 | |
9e8327e3 | 8837 | (define_insn "*brasl_r" |
c19ec8f9 | 8838 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8839 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8840 | (match_operand 2 "const_int_operand" "n"))) | |
8841 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
8842 | "!SIBLING_CALL_P (insn) |
8843 | && TARGET_CPU_ZARCH | |
ed9676cf | 8844 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8845 | "brasl\t%3,%1" |
8846 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8847 | (set_attr "type" "jsr") |
8848 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8849 | |
9e8327e3 | 8850 | (define_insn "*basr_r" |
c19ec8f9 | 8851 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8852 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8853 | (match_operand 2 "const_int_operand" "n"))) |
8854 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 8855 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8856 | { |
8857 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8858 | return "basr\t%3,%1"; | |
8859 | else | |
8860 | return "bas\t%3,%a1"; | |
8861 | } | |
8862 | [(set (attr "op_type") | |
8863 | (if_then_else (match_operand 1 "register_operand" "") | |
8864 | (const_string "RR") (const_string "RX"))) | |
8865 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8866 | (set_attr "atype" "agen") |
8867 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8868 | |
fd3cd001 UW |
8869 | ;; |
8870 | ;;- Thread-local storage support. | |
8871 | ;; | |
8872 | ||
f959607b CLT |
8873 | (define_expand "get_thread_pointer<mode>" |
8874 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
8875 | "" | |
c5aa1d12 | 8876 | "") |
fd3cd001 | 8877 | |
f959607b CLT |
8878 | (define_expand "set_thread_pointer<mode>" |
8879 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
8880 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
8881 | "" | |
c5aa1d12 UW |
8882 | "") |
8883 | ||
8884 | (define_insn "*set_tp" | |
ae156f85 | 8885 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
8886 | "" |
8887 | "" | |
8888 | [(set_attr "type" "none") | |
8889 | (set_attr "length" "0")]) | |
c7453384 | 8890 | |
fd3cd001 UW |
8891 | (define_insn "*tls_load_64" |
8892 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 8893 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
8894 | (match_operand:DI 2 "" "")] |
8895 | UNSPEC_TLS_LOAD))] | |
8896 | "TARGET_64BIT" | |
d40c829f | 8897 | "lg\t%0,%1%J2" |
9381e3f1 WG |
8898 | [(set_attr "op_type" "RXE") |
8899 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
8900 | |
8901 | (define_insn "*tls_load_31" | |
d3632d41 UW |
8902 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
8903 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
8904 | (match_operand:SI 2 "" "")] |
8905 | UNSPEC_TLS_LOAD))] | |
8906 | "!TARGET_64BIT" | |
d3632d41 | 8907 | "@ |
d40c829f UW |
8908 | l\t%0,%1%J2 |
8909 | ly\t%0,%1%J2" | |
9381e3f1 | 8910 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 8911 | (set_attr "type" "load") |
9381e3f1 | 8912 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 8913 | |
9e8327e3 | 8914 | (define_insn "*bras_tls" |
c19ec8f9 | 8915 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8916 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8917 | (match_operand 2 "const_int_operand" "n"))) | |
8918 | (clobber (match_operand 3 "register_operand" "=r")) | |
8919 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8920 | "!SIBLING_CALL_P (insn) |
8921 | && TARGET_SMALL_EXEC | |
ed9676cf | 8922 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8923 | "bras\t%3,%1%J4" |
fd3cd001 | 8924 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8925 | (set_attr "type" "jsr") |
8926 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8927 | |
9e8327e3 | 8928 | (define_insn "*brasl_tls" |
c19ec8f9 | 8929 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8930 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8931 | (match_operand 2 "const_int_operand" "n"))) | |
8932 | (clobber (match_operand 3 "register_operand" "=r")) | |
8933 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8934 | "!SIBLING_CALL_P (insn) |
8935 | && TARGET_CPU_ZARCH | |
ed9676cf | 8936 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8937 | "brasl\t%3,%1%J4" |
8938 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8939 | (set_attr "type" "jsr") |
8940 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8941 | |
9e8327e3 | 8942 | (define_insn "*basr_tls" |
c19ec8f9 | 8943 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8944 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8945 | (match_operand 2 "const_int_operand" "n"))) |
8946 | (clobber (match_operand 3 "register_operand" "=r")) | |
8947 | (use (match_operand 4 "" ""))] | |
ed9676cf | 8948 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8949 | { |
8950 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8951 | return "basr\t%3,%1%J4"; | |
8952 | else | |
8953 | return "bas\t%3,%a1%J4"; | |
8954 | } | |
8955 | [(set (attr "op_type") | |
8956 | (if_then_else (match_operand 1 "register_operand" "") | |
8957 | (const_string "RR") (const_string "RX"))) | |
8958 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8959 | (set_attr "atype" "agen") |
8960 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8961 | |
e0374221 AS |
8962 | ;; |
8963 | ;;- Atomic operations | |
8964 | ;; | |
8965 | ||
8966 | ; | |
78ce265b | 8967 | ; memory barrier patterns. |
e0374221 AS |
8968 | ; |
8969 | ||
78ce265b RH |
8970 | (define_expand "mem_signal_fence" |
8971 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
8972 | "" |
8973 | { | |
78ce265b RH |
8974 | /* The s390 memory model is strong enough not to require any |
8975 | barrier in order to synchronize a thread with itself. */ | |
8976 | DONE; | |
8977 | }) | |
8978 | ||
8979 | (define_expand "mem_thread_fence" | |
8980 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
8981 | "" | |
8982 | { | |
8983 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
8984 | enough not to require barriers of any kind. */ | |
8985 | if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST) | |
8986 | { | |
8987 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
8988 | MEM_VOLATILE_P (mem) = 1; | |
8989 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
8990 | } | |
8991 | DONE; | |
e0374221 AS |
8992 | }) |
8993 | ||
78ce265b RH |
8994 | ; Although bcr is superscalar on Z10, this variant will never |
8995 | ; become part of an execution group. | |
8996 | (define_insn "mem_thread_fence_1" | |
e0374221 | 8997 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 8998 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 AS |
8999 | "" |
9000 | "bcr\t15,0" | |
9001 | [(set_attr "op_type" "RR")]) | |
1a8c13b3 | 9002 | |
78ce265b RH |
9003 | ; |
9004 | ; atomic load/store operations | |
9005 | ; | |
9006 | ||
9007 | ; Atomic loads need not examine the memory model at all. | |
9008 | (define_expand "atomic_load<mode>" | |
9009 | [(match_operand:DINT 0 "register_operand") ;; output | |
9010 | (match_operand:DINT 1 "memory_operand") ;; memory | |
9011 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9012 | "" | |
9013 | { | |
9014 | if (<MODE>mode == TImode) | |
9015 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
9016 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9017 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
9018 | else | |
9019 | emit_move_insn (operands[0], operands[1]); | |
9020 | DONE; | |
9021 | }) | |
9022 | ||
9023 | ; Different from movdi_31 in that we want no splitters. | |
9024 | (define_insn "atomic_loaddi_1" | |
9025 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
9026 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
9027 | UNSPEC_MOVA))] | |
9028 | "!TARGET_ZARCH" | |
9029 | "@ | |
9030 | lm\t%0,%M0,%S1 | |
9031 | lmy\t%0,%M0,%S1 | |
9032 | ld\t%0,%1 | |
9033 | ldy\t%0,%1" | |
9034 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9035 | (set_attr "type" "lm,lm,floaddf,floaddf")]) | |
9036 | ||
9037 | (define_insn "atomic_loadti_1" | |
9038 | [(set (match_operand:TI 0 "register_operand" "=r") | |
9039 | (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] | |
9040 | UNSPEC_MOVA))] | |
9041 | "TARGET_ZARCH" | |
9042 | "lpq\t%0,%1" | |
9043 | [(set_attr "op_type" "RXY") | |
9044 | (set_attr "type" "other")]) | |
9045 | ||
9046 | ; Atomic stores must(?) enforce sequential consistency. | |
9047 | (define_expand "atomic_store<mode>" | |
9048 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
9049 | (match_operand:DINT 1 "register_operand") ;; input | |
9050 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9051 | "" | |
9052 | { | |
9053 | enum memmodel model = (enum memmodel) INTVAL (operands[2]); | |
9054 | ||
9055 | if (<MODE>mode == TImode) | |
9056 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
9057 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9058 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
9059 | else | |
9060 | emit_move_insn (operands[0], operands[1]); | |
9061 | if (model == MEMMODEL_SEQ_CST) | |
9062 | emit_insn (gen_mem_thread_fence (operands[2])); | |
9063 | DONE; | |
9064 | }) | |
9065 | ||
9066 | ; Different from movdi_31 in that we want no splitters. | |
9067 | (define_insn "atomic_storedi_1" | |
9068 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
9069 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
9070 | UNSPEC_MOVA))] | |
9071 | "!TARGET_ZARCH" | |
9072 | "@ | |
9073 | stm\t%1,%N1,%S0 | |
9074 | stmy\t%1,%N1,%S0 | |
9075 | std %1,%0 | |
9076 | stdy %1,%0" | |
9077 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9078 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) | |
9079 | ||
9080 | (define_insn "atomic_storeti_1" | |
9081 | [(set (match_operand:TI 0 "memory_operand" "=RT") | |
9082 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] | |
9083 | UNSPEC_MOVA))] | |
9084 | "TARGET_ZARCH" | |
9085 | "stpq\t%1,%0" | |
9086 | [(set_attr "op_type" "RXY") | |
9087 | (set_attr "type" "other")]) | |
e0374221 AS |
9088 | |
9089 | ; | |
9090 | ; compare and swap patterns. | |
9091 | ; | |
9092 | ||
78ce265b RH |
9093 | (define_expand "atomic_compare_and_swap<mode>" |
9094 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9095 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
9096 | (match_operand:DGPR 2 "memory_operand") ;; memory |
9097 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
9098 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
9099 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9100 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9101 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
9102 | "" | |
9103 | { | |
215770ad UW |
9104 | rtx cc, cmp, output = operands[1]; |
9105 | ||
9106 | if (!register_operand (output, <MODE>mode)) | |
9107 | output = gen_reg_rtx (<MODE>mode); | |
9108 | ||
78ce265b | 9109 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
9110 | (output, operands[2], operands[3], operands[4])); |
9111 | ||
9112 | /* We deliberately accept non-register operands in the predicate | |
9113 | to ensure the write back to the output operand happens *before* | |
9114 | the store-flags code below. This makes it easier for combine | |
9115 | to merge the store-flags code with a potential test-and-branch | |
9116 | pattern following (immediately!) afterwards. */ | |
9117 | if (output != operands[1]) | |
9118 | emit_move_insn (operands[1], output); | |
9119 | ||
78ce265b RH |
9120 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
9121 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
9122 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
9123 | DONE; | |
9124 | }) | |
e0374221 | 9125 | |
78ce265b RH |
9126 | (define_expand "atomic_compare_and_swap<mode>" |
9127 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9128 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
9129 | (match_operand:HQI 2 "memory_operand") ;; memory |
9130 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
9131 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
9132 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9133 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9134 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 9135 | "" |
78ce265b RH |
9136 | { |
9137 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
9138 | operands[3], operands[4], INTVAL (operands[5])); | |
9139 | DONE; | |
9140 | }) | |
3093f076 | 9141 | |
78ce265b RH |
9142 | (define_expand "atomic_compare_and_swap<mode>_internal" |
9143 | [(parallel | |
9144 | [(set (match_operand:DGPR 0 "register_operand") | |
9145 | (match_operand:DGPR 1 "memory_operand")) | |
9146 | (set (match_dup 1) | |
9147 | (unspec_volatile:DGPR | |
9148 | [(match_dup 1) | |
9149 | (match_operand:DGPR 2 "register_operand") | |
9150 | (match_operand:DGPR 3 "register_operand")] | |
9151 | UNSPECV_CAS)) | |
9152 | (set (reg:CCZ1 CC_REGNUM) | |
9153 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
9154 | "") | |
9155 | ||
9156 | ; cdsg, csg | |
9157 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
9158 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
9159 | (match_operand:TDI 1 "memory_operand" "+QS")) | |
8006eaa6 | 9160 | (set (match_dup 1) |
78ce265b | 9161 | (unspec_volatile:TDI |
8006eaa6 | 9162 | [(match_dup 1) |
78ce265b RH |
9163 | (match_operand:TDI 2 "register_operand" "0") |
9164 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
9165 | UNSPECV_CAS)) |
9166 | (set (reg:CCZ1 CC_REGNUM) | |
9167 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
9168 | "TARGET_ZARCH" |
9169 | "c<td>sg\t%0,%3,%S1" | |
9170 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
9171 | (set_attr "type" "sem")]) |
9172 | ||
78ce265b RH |
9173 | ; cds, cdsy |
9174 | (define_insn "*atomic_compare_and_swapdi_2" | |
9175 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
9176 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 9177 | (set (match_dup 1) |
78ce265b RH |
9178 | (unspec_volatile:DI |
9179 | [(match_dup 1) | |
9180 | (match_operand:DI 2 "register_operand" "0,0") | |
9181 | (match_operand:DI 3 "register_operand" "r,r")] | |
9182 | UNSPECV_CAS)) | |
9183 | (set (reg:CCZ1 CC_REGNUM) | |
9184 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9185 | "!TARGET_ZARCH" | |
9186 | "@ | |
9187 | cds\t%0,%3,%S1 | |
9188 | cdsy\t%0,%3,%S1" | |
9189 | [(set_attr "op_type" "RS,RSY") | |
9190 | (set_attr "type" "sem")]) | |
9191 | ||
9192 | ; cs, csy | |
9193 | (define_insn "*atomic_compare_and_swapsi_3" | |
9194 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
9195 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
9196 | (set (match_dup 1) | |
9197 | (unspec_volatile:SI | |
e0374221 | 9198 | [(match_dup 1) |
78ce265b RH |
9199 | (match_operand:SI 2 "register_operand" "0,0") |
9200 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 9201 | UNSPECV_CAS)) |
69950452 AS |
9202 | (set (reg:CCZ1 CC_REGNUM) |
9203 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 9204 | "" |
78ce265b RH |
9205 | "@ |
9206 | cs\t%0,%3,%S1 | |
9207 | csy\t%0,%3,%S1" | |
9208 | [(set_attr "op_type" "RS,RSY") | |
e0374221 AS |
9209 | (set_attr "type" "sem")]) |
9210 | ||
45d18331 AS |
9211 | ; |
9212 | ; Other atomic instruction patterns. | |
9213 | ; | |
9214 | ||
65b1d8ea AK |
9215 | ; z196 load and add, xor, or and and instructions |
9216 | ||
78ce265b RH |
9217 | (define_expand "atomic_fetch_<atomic><mode>" |
9218 | [(match_operand:GPR 0 "register_operand") ;; val out | |
9219 | (ATOMIC_Z196:GPR | |
9220 | (match_operand:GPR 1 "memory_operand") ;; memory | |
9221 | (match_operand:GPR 2 "register_operand")) ;; val in | |
9222 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 9223 | "TARGET_Z196" |
78ce265b RH |
9224 | { |
9225 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf | |
9226 | (operands[0], operands[1], operands[2])); | |
9227 | DONE; | |
9228 | }) | |
65b1d8ea AK |
9229 | |
9230 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
9231 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
9232 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
9233 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
9234 | (set (match_dup 1) | |
9235 | (unspec_volatile:GPR | |
9236 | [(ATOMIC_Z196:GPR (match_dup 1) | |
9237 | (match_operand:GPR 2 "general_operand" "d"))] | |
9238 | UNSPECV_ATOMIC_OP)) | |
9239 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 9240 | "TARGET_Z196" |
78ce265b RH |
9241 | "la<noxa><g>\t%0,%2,%1" |
9242 | [(set_attr "op_type" "RSY") | |
9243 | (set_attr "type" "sem")]) | |
65b1d8ea | 9244 | |
78ce265b RH |
9245 | ;; For SImode and larger, the optabs.c code will do just fine in |
9246 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
9247 | ;; better by expanding our own loop. | |
65b1d8ea | 9248 | |
78ce265b RH |
9249 | (define_expand "atomic_<atomic><mode>" |
9250 | [(ATOMIC:HQI | |
9251 | (match_operand:HQI 0 "memory_operand") ;; memory | |
9252 | (match_operand:HQI 1 "general_operand")) ;; val in | |
9253 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 9254 | "" |
78ce265b RH |
9255 | { |
9256 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
9257 | operands[1], false); | |
9258 | DONE; | |
9259 | }) | |
45d18331 | 9260 | |
78ce265b RH |
9261 | (define_expand "atomic_fetch_<atomic><mode>" |
9262 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9263 | (ATOMIC:HQI | |
9264 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9265 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9266 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9267 | "" |
78ce265b RH |
9268 | { |
9269 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9270 | operands[2], false); | |
9271 | DONE; | |
9272 | }) | |
9273 | ||
9274 | (define_expand "atomic_<atomic>_fetch<mode>" | |
9275 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9276 | (ATOMIC:HQI | |
9277 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9278 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9279 | (match_operand:SI 3 "const_int_operand")] ;; model | |
9280 | "" | |
9281 | { | |
9282 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9283 | operands[2], true); | |
9284 | DONE; | |
9285 | }) | |
9286 | ||
9287 | (define_expand "atomic_exchange<mode>" | |
9288 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9289 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9290 | (match_operand:HQI 2 "general_operand") ;; val in | |
9291 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9292 | "" |
78ce265b RH |
9293 | { |
9294 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
9295 | operands[2], false); | |
9296 | DONE; | |
9297 | }) | |
45d18331 | 9298 | |
9db1d521 HP |
9299 | ;; |
9300 | ;;- Miscellaneous instructions. | |
9301 | ;; | |
9302 | ||
9303 | ; | |
9304 | ; allocate stack instruction pattern(s). | |
9305 | ; | |
9306 | ||
9307 | (define_expand "allocate_stack" | |
ef44a6ff UW |
9308 | [(match_operand 0 "general_operand" "") |
9309 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 9310 | "TARGET_BACKCHAIN" |
9db1d521 | 9311 | { |
ef44a6ff | 9312 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 9313 | |
ef44a6ff UW |
9314 | emit_move_insn (temp, s390_back_chain_rtx ()); |
9315 | anti_adjust_stack (operands[1]); | |
9316 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 9317 | |
ef44a6ff UW |
9318 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
9319 | DONE; | |
10bbf137 | 9320 | }) |
9db1d521 HP |
9321 | |
9322 | ||
9323 | ; | |
43ab026f | 9324 | ; setjmp instruction pattern. |
9db1d521 HP |
9325 | ; |
9326 | ||
9db1d521 | 9327 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 9328 | [(match_operand 0 "" "")] |
f314b9b1 | 9329 | "flag_pic" |
9db1d521 | 9330 | { |
585539a1 | 9331 | emit_insn (s390_load_got ()); |
c41c1387 | 9332 | emit_use (pic_offset_table_rtx); |
9db1d521 | 9333 | DONE; |
fd7643fb | 9334 | }) |
9db1d521 | 9335 | |
9db1d521 HP |
9336 | ;; These patterns say how to save and restore the stack pointer. We need not |
9337 | ;; save the stack pointer at function level since we are careful to | |
9338 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9339 | ;; when we restore the stack pointer. | |
9340 | ;; | |
9341 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9342 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9343 | ;; save area is a memory location. | |
9344 | ||
9345 | (define_expand "save_stack_function" | |
9346 | [(match_operand 0 "general_operand" "") | |
9347 | (match_operand 1 "general_operand" "")] | |
9348 | "" | |
9349 | "DONE;") | |
9350 | ||
9351 | (define_expand "restore_stack_function" | |
9352 | [(match_operand 0 "general_operand" "") | |
9353 | (match_operand 1 "general_operand" "")] | |
9354 | "" | |
9355 | "DONE;") | |
9356 | ||
9357 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
9358 | [(match_operand 0 "register_operand" "") |
9359 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 9360 | "TARGET_BACKCHAIN" |
9db1d521 | 9361 | { |
ef44a6ff UW |
9362 | rtx temp = gen_reg_rtx (Pmode); |
9363 | ||
9364 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
9365 | emit_move_insn (operands[0], operands[1]); | |
9366 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9367 | ||
9368 | DONE; | |
10bbf137 | 9369 | }) |
9db1d521 HP |
9370 | |
9371 | (define_expand "save_stack_nonlocal" | |
9372 | [(match_operand 0 "memory_operand" "") | |
9373 | (match_operand 1 "register_operand" "")] | |
9374 | "" | |
9db1d521 | 9375 | { |
ef44a6ff UW |
9376 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
9377 | ||
9378 | /* Copy the backchain to the first word, sp to the second and the | |
9379 | literal pool base to the third. */ | |
9380 | ||
9602b6a1 AK |
9381 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
9382 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
9383 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
9384 | ||
b3d31392 | 9385 | if (TARGET_BACKCHAIN) |
9602b6a1 | 9386 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 9387 | |
9602b6a1 AK |
9388 | emit_move_insn (save_sp, operands[1]); |
9389 | emit_move_insn (save_bp, base); | |
9db1d521 | 9390 | |
9db1d521 | 9391 | DONE; |
10bbf137 | 9392 | }) |
9db1d521 HP |
9393 | |
9394 | (define_expand "restore_stack_nonlocal" | |
9395 | [(match_operand 0 "register_operand" "") | |
9396 | (match_operand 1 "memory_operand" "")] | |
9397 | "" | |
9db1d521 | 9398 | { |
490ceeb4 | 9399 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 9400 | rtx temp = NULL_RTX; |
9db1d521 | 9401 | |
43ab026f | 9402 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 9403 | literal pool base from the third. */ |
43ab026f | 9404 | |
9602b6a1 AK |
9405 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
9406 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
9407 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
9408 | ||
b3d31392 | 9409 | if (TARGET_BACKCHAIN) |
9602b6a1 | 9410 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 9411 | |
9602b6a1 AK |
9412 | emit_move_insn (base, save_bp); |
9413 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
9414 | |
9415 | if (temp) | |
9416 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9417 | ||
c41c1387 | 9418 | emit_use (base); |
9db1d521 | 9419 | DONE; |
10bbf137 | 9420 | }) |
9db1d521 | 9421 | |
7bcebb25 AK |
9422 | (define_expand "exception_receiver" |
9423 | [(const_int 0)] | |
9424 | "" | |
9425 | { | |
9426 | s390_set_has_landing_pad_p (true); | |
9427 | DONE; | |
9428 | }) | |
9db1d521 HP |
9429 | |
9430 | ; | |
9431 | ; nop instruction pattern(s). | |
9432 | ; | |
9433 | ||
9434 | (define_insn "nop" | |
9435 | [(const_int 0)] | |
9436 | "" | |
d40c829f | 9437 | "lr\t0,0" |
729e750f WG |
9438 | [(set_attr "op_type" "RR") |
9439 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 9440 | |
d277db6b WG |
9441 | (define_insn "nop1" |
9442 | [(const_int 1)] | |
9443 | "" | |
9444 | "lr\t1,1" | |
9445 | [(set_attr "op_type" "RR")]) | |
9446 | ||
9db1d521 HP |
9447 | |
9448 | ; | |
9449 | ; Special literal pool access instruction pattern(s). | |
9450 | ; | |
9451 | ||
416cf582 UW |
9452 | (define_insn "*pool_entry" |
9453 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
9454 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 9455 | "" |
9db1d521 | 9456 | { |
416cf582 UW |
9457 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
9458 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 9459 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
9460 | return ""; |
9461 | } | |
b628bd8e | 9462 | [(set (attr "length") |
416cf582 | 9463 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 9464 | |
9bb86f41 UW |
9465 | (define_insn "pool_align" |
9466 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
9467 | UNSPECV_POOL_ALIGN)] | |
9468 | "" | |
9469 | ".align\t%0" | |
b628bd8e | 9470 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 9471 | |
9bb86f41 UW |
9472 | (define_insn "pool_section_start" |
9473 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
9474 | "" | |
9475 | ".section\t.rodata" | |
b628bd8e | 9476 | [(set_attr "length" "0")]) |
b2ccb744 | 9477 | |
9bb86f41 UW |
9478 | (define_insn "pool_section_end" |
9479 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
9480 | "" | |
b2ccb744 | 9481 | ".previous" |
b628bd8e | 9482 | [(set_attr "length" "0")]) |
b2ccb744 | 9483 | |
5af2f3d3 | 9484 | (define_insn "main_base_31_small" |
9e8327e3 UW |
9485 | [(set (match_operand 0 "register_operand" "=a") |
9486 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9487 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9488 | "basr\t%0,0" |
9489 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
9490 | (set_attr "type" "la") |
9491 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9492 | |
9493 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
9494 | [(set (match_operand 0 "register_operand" "=a") |
9495 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 9496 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 9497 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 9498 | "bras\t%0,%2" |
65b1d8ea AK |
9499 | [(set_attr "op_type" "RI") |
9500 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9501 | |
9502 | (define_insn "main_base_64" | |
9e8327e3 UW |
9503 | [(set (match_operand 0 "register_operand" "=a") |
9504 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9505 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9506 | "larl\t%0,%1" |
9507 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 9508 | (set_attr "type" "larl") |
729e750f | 9509 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
9510 | |
9511 | (define_insn "main_pool" | |
585539a1 UW |
9512 | [(set (match_operand 0 "register_operand" "=a") |
9513 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
9514 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
9515 | { |
9516 | gcc_unreachable (); | |
9517 | } | |
9381e3f1 | 9518 | [(set (attr "type") |
d7f99b2c | 9519 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 9520 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 9521 | |
aee4e0db | 9522 | (define_insn "reload_base_31" |
9e8327e3 UW |
9523 | [(set (match_operand 0 "register_operand" "=a") |
9524 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9525 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9526 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 9527 | [(set_attr "length" "6") |
65b1d8ea AK |
9528 | (set_attr "type" "la") |
9529 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 9530 | |
aee4e0db | 9531 | (define_insn "reload_base_64" |
9e8327e3 UW |
9532 | [(set (match_operand 0 "register_operand" "=a") |
9533 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9534 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9535 | "larl\t%0,%1" |
aee4e0db | 9536 | [(set_attr "op_type" "RIL") |
9381e3f1 | 9537 | (set_attr "type" "larl") |
729e750f | 9538 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 9539 | |
aee4e0db | 9540 | (define_insn "pool" |
fd7643fb | 9541 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 9542 | "" |
8d933e31 AS |
9543 | { |
9544 | gcc_unreachable (); | |
9545 | } | |
b628bd8e | 9546 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 9547 | |
4023fb28 UW |
9548 | ;; |
9549 | ;; Insns related to generating the function prologue and epilogue. | |
9550 | ;; | |
9551 | ||
9552 | ||
9553 | (define_expand "prologue" | |
9554 | [(use (const_int 0))] | |
9555 | "" | |
10bbf137 | 9556 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
9557 | |
9558 | (define_expand "epilogue" | |
9559 | [(use (const_int 1))] | |
9560 | "" | |
ed9676cf AK |
9561 | "s390_emit_epilogue (false); DONE;") |
9562 | ||
9563 | (define_expand "sibcall_epilogue" | |
9564 | [(use (const_int 0))] | |
9565 | "" | |
9566 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 9567 | |
9e8327e3 | 9568 | (define_insn "*return" |
4023fb28 | 9569 | [(return) |
9e8327e3 UW |
9570 | (use (match_operand 0 "register_operand" "a"))] |
9571 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9572 | "br\t%0" |
4023fb28 | 9573 | [(set_attr "op_type" "RR") |
c7453384 | 9574 | (set_attr "type" "jsr") |
077dab3b | 9575 | (set_attr "atype" "agen")]) |
4023fb28 | 9576 | |
4023fb28 | 9577 | |
c7453384 | 9578 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 9579 | ;; pointer. This is used for compatibility. |
c7453384 EC |
9580 | |
9581 | (define_expand "ptr_extend" | |
9582 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9583 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 9584 | "TARGET_64BIT" |
c7453384 | 9585 | { |
c7453384 EC |
9586 | emit_insn (gen_anddi3 (operands[0], |
9587 | gen_lowpart (DImode, operands[1]), | |
9588 | GEN_INT (0x7fffffff))); | |
c7453384 | 9589 | DONE; |
10bbf137 | 9590 | }) |
4798630c D |
9591 | |
9592 | ;; Instruction definition to expand eh_return macro to support | |
9593 | ;; swapping in special linkage return addresses. | |
9594 | ||
9595 | (define_expand "eh_return" | |
9596 | [(use (match_operand 0 "register_operand" ""))] | |
9597 | "TARGET_TPF" | |
9598 | { | |
9599 | s390_emit_tpf_eh_return (operands[0]); | |
9600 | DONE; | |
9601 | }) | |
9602 | ||
7b8acc34 AK |
9603 | ; |
9604 | ; Stack Protector Patterns | |
9605 | ; | |
9606 | ||
9607 | (define_expand "stack_protect_set" | |
9608 | [(set (match_operand 0 "memory_operand" "") | |
9609 | (match_operand 1 "memory_operand" ""))] | |
9610 | "" | |
9611 | { | |
9612 | #ifdef TARGET_THREAD_SSP_OFFSET | |
9613 | operands[1] | |
9614 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9615 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9616 | #endif | |
9617 | if (TARGET_64BIT) | |
9618 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
9619 | else | |
9620 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
9621 | ||
9622 | DONE; | |
9623 | }) | |
9624 | ||
9625 | (define_insn "stack_protect_set<mode>" | |
9626 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
9627 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
9628 | "" | |
9629 | "mvc\t%O0(%G0,%R0),%S1" | |
9630 | [(set_attr "op_type" "SS")]) | |
9631 | ||
9632 | (define_expand "stack_protect_test" | |
9633 | [(set (reg:CC CC_REGNUM) | |
9634 | (compare (match_operand 0 "memory_operand" "") | |
9635 | (match_operand 1 "memory_operand" ""))) | |
9636 | (match_operand 2 "" "")] | |
9637 | "" | |
9638 | { | |
f90b7a5a | 9639 | rtx cc_reg, test; |
7b8acc34 AK |
9640 | #ifdef TARGET_THREAD_SSP_OFFSET |
9641 | operands[1] | |
9642 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9643 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9644 | #endif | |
7b8acc34 AK |
9645 | if (TARGET_64BIT) |
9646 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
9647 | else | |
9648 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
9649 | ||
f90b7a5a PB |
9650 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
9651 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
9652 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
9653 | DONE; |
9654 | }) | |
9655 | ||
9656 | (define_insn "stack_protect_test<mode>" | |
9657 | [(set (reg:CCZ CC_REGNUM) | |
9658 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
9659 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
9660 | "" | |
9661 | "clc\t%O0(%G0,%R0),%S1" | |
9662 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
9663 | |
9664 | ; This is used in s390_emit_prologue in order to prevent insns | |
9665 | ; adjusting the stack pointer to be moved over insns writing stack | |
9666 | ; slots using a copy of the stack pointer in a different register. | |
9667 | (define_insn "stack_tie" | |
9668 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
9669 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
9670 | "" | |
9671 | "" | |
9672 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
9673 | |
9674 | ||
9675 | ; | |
9676 | ; Data prefetch patterns | |
9677 | ; | |
9678 | ||
9679 | (define_insn "prefetch" | |
22d72dbc AK |
9680 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
9681 | (match_operand:SI 1 "const_int_operand" " n,n") | |
9682 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
9683 | "TARGET_Z10" | |
963fc8d0 | 9684 | { |
4fe6dea8 AK |
9685 | switch (which_alternative) |
9686 | { | |
9687 | case 0: | |
4fe6dea8 | 9688 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 9689 | case 1: |
4fe6dea8 AK |
9690 | if (larl_operand (operands[0], Pmode)) |
9691 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
9692 | default: | |
9693 | ||
9694 | /* This might be reached for symbolic operands with an odd | |
9695 | addend. We simply omit the prefetch for such rare cases. */ | |
9696 | ||
9697 | return ""; | |
9698 | } | |
9381e3f1 | 9699 | } |
22d72dbc AK |
9700 | [(set_attr "type" "load,larl") |
9701 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
9702 | (set_attr "z10prop" "z10_super") |
9703 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
9704 | |
9705 | ||
9706 | ; | |
9707 | ; Byte swap instructions | |
9708 | ; | |
9709 | ||
9710 | (define_insn "bswap<mode>2" | |
9711 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
9712 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] | |
677fbff4 | 9713 | "TARGET_CPU_ZARCH" |
07da44ab AK |
9714 | "@ |
9715 | lrv<g>r\t%0,%1 | |
9716 | lrv<g>\t%0,%1" | |
9717 | [(set_attr "type" "*,load") | |
9718 | (set_attr "op_type" "RRE,RXY") | |
9719 | (set_attr "z10prop" "z10_super")]) | |
65b1d8ea AK |
9720 | |
9721 | ||
9722 | ; | |
9723 | ; Population count instruction | |
9724 | ; | |
9725 | ||
9726 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
9727 | ; portions and stores the result in the corresponding bytes in op0. | |
9728 | (define_insn "*popcount<mode>" | |
9729 | [(set (match_operand:INT 0 "register_operand" "=d") | |
9730 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
9731 | (clobber (reg:CC CC_REGNUM))] | |
9732 | "TARGET_Z196" | |
9733 | "popcnt\t%0,%1" | |
9734 | [(set_attr "op_type" "RRE")]) | |
9735 | ||
9736 | (define_expand "popcountdi2" | |
9737 | [; popcnt op0, op1 | |
9738 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
9739 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
9740 | UNSPEC_POPCNT)) | |
9741 | (clobber (reg:CC CC_REGNUM))]) | |
9742 | ; sllg op2, op0, 32 | |
9743 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
9744 | ; agr op0, op2 | |
9745 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9746 | (clobber (reg:CC CC_REGNUM))]) | |
9747 | ; sllg op2, op0, 16 | |
17465c6e | 9748 | (set (match_dup 2) |
65b1d8ea AK |
9749 | (ashift:DI (match_dup 0) (const_int 16))) |
9750 | ; agr op0, op2 | |
9751 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9752 | (clobber (reg:CC CC_REGNUM))]) | |
9753 | ; sllg op2, op0, 8 | |
9754 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
9755 | ; agr op0, op2 | |
9756 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9757 | (clobber (reg:CC CC_REGNUM))]) | |
9758 | ; srlg op0, op0, 56 | |
9759 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
9760 | "TARGET_Z196 && TARGET_64BIT" | |
9761 | "operands[2] = gen_reg_rtx (DImode);") | |
9762 | ||
9763 | (define_expand "popcountsi2" | |
9764 | [; popcnt op0, op1 | |
9765 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
9766 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
9767 | UNSPEC_POPCNT)) | |
9768 | (clobber (reg:CC CC_REGNUM))]) | |
9769 | ; sllk op2, op0, 16 | |
17465c6e | 9770 | (set (match_dup 2) |
65b1d8ea AK |
9771 | (ashift:SI (match_dup 0) (const_int 16))) |
9772 | ; ar op0, op2 | |
9773 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9774 | (clobber (reg:CC CC_REGNUM))]) | |
9775 | ; sllk op2, op0, 8 | |
9776 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
9777 | ; ar op0, op2 | |
9778 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9779 | (clobber (reg:CC CC_REGNUM))]) | |
9780 | ; srl op0, op0, 24 | |
9781 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
9782 | "TARGET_Z196" | |
9783 | "operands[2] = gen_reg_rtx (SImode);") | |
9784 | ||
9785 | (define_expand "popcounthi2" | |
9786 | [; popcnt op0, op1 | |
9787 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
9788 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
9789 | UNSPEC_POPCNT)) | |
9790 | (clobber (reg:CC CC_REGNUM))]) | |
9791 | ; sllk op2, op0, 8 | |
17465c6e | 9792 | (set (match_dup 2) |
65b1d8ea AK |
9793 | (ashift:SI (match_dup 0) (const_int 8))) |
9794 | ; ar op0, op2 | |
9795 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9796 | (clobber (reg:CC CC_REGNUM))]) | |
9797 | ; srl op0, op0, 8 | |
9798 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
9799 | "TARGET_Z196" | |
9800 | "operands[2] = gen_reg_rtx (SImode);") | |
9801 | ||
9802 | (define_expand "popcountqi2" | |
9803 | [; popcnt op0, op1 | |
9804 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
9805 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
9806 | UNSPEC_POPCNT)) | |
9807 | (clobber (reg:CC CC_REGNUM))])] | |
9808 | "TARGET_Z196" | |
9809 | "") | |
9810 | ||
9811 | ;; | |
9812 | ;;- Copy sign instructions | |
9813 | ;; | |
9814 | ||
9815 | (define_insn "copysign<mode>3" | |
9816 | [(set (match_operand:FP 0 "register_operand" "=f") | |
9817 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
9818 | (match_operand:FP 2 "register_operand" "f")] | |
9819 | UNSPEC_COPYSIGN))] | |
9820 | "TARGET_Z196" | |
9821 | "cpsdr\t%0,%2,%1" | |
9822 | [(set_attr "op_type" "RRF") | |
9823 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
9824 | |
9825 | ||
9826 | ;; | |
9827 | ;;- Transactional execution instructions | |
9828 | ;; | |
9829 | ||
9830 | ; This splitter helps combine to make use of CC directly when | |
9831 | ; comparing the integer result of a tbegin builtin with a constant. | |
9832 | ; The unspec is already removed by canonicalize_comparison. So this | |
9833 | ; splitters only job is to turn the PARALLEL into separate insns | |
9834 | ; again. Unfortunately this only works with the very first cc/int | |
9835 | ; compare since combine is not able to deal with data flow across | |
9836 | ; basic block boundaries. | |
9837 | ||
9838 | ; It needs to be an insn pattern as well since combine does not apply | |
9839 | ; the splitter directly. Combine would only use it if it actually | |
9840 | ; would reduce the number of instructions. | |
9841 | (define_insn_and_split "*ccraw_to_int" | |
9842 | [(set (pc) | |
9843 | (if_then_else | |
9844 | (match_operator 0 "s390_eqne_operator" | |
9845 | [(reg:CCRAW CC_REGNUM) | |
9846 | (match_operand 1 "const_int_operand" "")]) | |
9847 | (label_ref (match_operand 2 "" "")) | |
9848 | (pc))) | |
9849 | (set (match_operand:SI 3 "register_operand" "=d") | |
9850 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
9851 | "" | |
9852 | "#" | |
9853 | "" | |
9854 | [(set (match_dup 3) | |
9855 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
9856 | (set (pc) | |
9857 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
9858 | (label_ref (match_dup 2)) | |
9859 | (pc)))] | |
9860 | "") | |
9861 | ||
9862 | ; Non-constrained transaction begin | |
9863 | ||
9864 | (define_expand "tbegin" | |
9865 | [(match_operand:SI 0 "register_operand" "=d") | |
9866 | (match_operand:BLK 1 "memory_operand" "=Q")] | |
9867 | "TARGET_HTM" | |
9868 | { | |
9869 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
9870 | DONE; | |
9871 | }) | |
9872 | ||
9873 | (define_expand "tbegin_nofloat" | |
9874 | [(match_operand:SI 0 "register_operand" "=d") | |
9875 | (match_operand:BLK 1 "memory_operand" "=Q")] | |
9876 | "TARGET_HTM" | |
9877 | { | |
9878 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
9879 | DONE; | |
9880 | }) | |
9881 | ||
9882 | (define_expand "tbegin_retry" | |
9883 | [(match_operand:SI 0 "register_operand" "=d") | |
9884 | (match_operand:BLK 1 "memory_operand" "=Q") | |
9885 | (match_operand 2 "const_int_operand")] | |
9886 | "TARGET_HTM" | |
9887 | { | |
9888 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
9889 | DONE; | |
9890 | }) | |
9891 | ||
9892 | (define_expand "tbegin_retry_nofloat" | |
9893 | [(match_operand:SI 0 "register_operand" "=d") | |
9894 | (match_operand:BLK 1 "memory_operand" "=Q") | |
9895 | (match_operand 2 "const_int_operand")] | |
9896 | "TARGET_HTM" | |
9897 | { | |
9898 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
9899 | DONE; | |
9900 | }) | |
9901 | ||
9902 | (define_insn "tbegin_1" | |
9903 | [(set (reg:CCRAW CC_REGNUM) | |
9904 | (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q") | |
9905 | (match_operand 1 "const_int_operand" " D")] | |
9906 | UNSPECV_TBEGIN)) | |
9907 | (clobber (reg:DF 16)) | |
9908 | (clobber (reg:DF 17)) | |
9909 | (clobber (reg:DF 18)) | |
9910 | (clobber (reg:DF 19)) | |
9911 | (clobber (reg:DF 20)) | |
9912 | (clobber (reg:DF 21)) | |
9913 | (clobber (reg:DF 22)) | |
9914 | (clobber (reg:DF 23)) | |
9915 | (clobber (reg:DF 24)) | |
9916 | (clobber (reg:DF 25)) | |
9917 | (clobber (reg:DF 26)) | |
9918 | (clobber (reg:DF 27)) | |
9919 | (clobber (reg:DF 28)) | |
9920 | (clobber (reg:DF 29)) | |
9921 | (clobber (reg:DF 30)) | |
9922 | (clobber (reg:DF 31))] | |
9923 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
9924 | ; not supposed to be used for immediates (see genpreds.c). | |
9925 | "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff" | |
9926 | "tbegin\t%0,%x1" | |
9927 | [(set_attr "op_type" "SIL")]) | |
9928 | ||
9929 | ; Same as above but without the FPR clobbers | |
9930 | (define_insn "tbegin_nofloat_1" | |
9931 | [(set (reg:CCRAW CC_REGNUM) | |
9932 | (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q") | |
9933 | (match_operand 1 "const_int_operand" " D")] | |
9934 | UNSPECV_TBEGIN))] | |
9935 | "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff" | |
9936 | "tbegin\t%0,%x1" | |
9937 | [(set_attr "op_type" "SIL")]) | |
9938 | ||
9939 | ||
9940 | ; Constrained transaction begin | |
9941 | ||
9942 | (define_expand "tbeginc" | |
9943 | [(set (reg:CCRAW CC_REGNUM) | |
9944 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
9945 | UNSPECV_TBEGINC))] | |
9946 | "TARGET_HTM" | |
9947 | "") | |
9948 | ||
9949 | (define_insn "*tbeginc_1" | |
9950 | [(set (reg:CCRAW CC_REGNUM) | |
9951 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
9952 | UNSPECV_TBEGINC))] | |
9953 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
9954 | "tbeginc\t0,%x0" | |
9955 | [(set_attr "op_type" "SIL")]) | |
9956 | ||
9957 | ; Transaction end | |
9958 | ||
9959 | (define_expand "tend" | |
9960 | [(set (reg:CCRAW CC_REGNUM) | |
9961 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
9962 | (set (match_operand:SI 0 "register_operand" "=d") | |
9963 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
9964 | "TARGET_HTM" | |
9965 | "") | |
9966 | ||
9967 | (define_insn "*tend_1" | |
9968 | [(set (reg:CCRAW CC_REGNUM) | |
9969 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
9970 | "TARGET_HTM" | |
9971 | "tend" | |
9972 | [(set_attr "op_type" "S")]) | |
9973 | ||
9974 | ; Transaction abort | |
9975 | ||
9976 | (define_expand "tabort" | |
9977 | [(unspec_volatile [(match_operand 0 "shift_count_or_setmem_operand" "")] | |
9978 | UNSPECV_TABORT)] | |
9979 | "TARGET_HTM && operands != NULL" | |
9980 | { | |
9981 | if (CONST_INT_P (operands[0]) | |
9982 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
9983 | { | |
9984 | error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC | |
9985 | ". Values in range 0 through 255 are reserved.", | |
9986 | INTVAL (operands[0])); | |
9987 | FAIL; | |
9988 | } | |
9989 | }) | |
9990 | ||
9991 | (define_insn "*tabort_1" | |
9992 | [(unspec_volatile [(match_operand 0 "shift_count_or_setmem_operand" "")] | |
9993 | UNSPECV_TABORT)] | |
9994 | "TARGET_HTM && operands != NULL" | |
9995 | "tabort\t%Y0" | |
9996 | [(set_attr "op_type" "S")]) | |
9997 | ||
9998 | ; Transaction extract nesting depth | |
9999 | ||
10000 | (define_insn "etnd" | |
10001 | [(set (match_operand:SI 0 "register_operand" "=d") | |
10002 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
10003 | "TARGET_HTM" | |
10004 | "etnd\t%0" | |
10005 | [(set_attr "op_type" "RRE")]) | |
10006 | ||
10007 | ; Non-transactional store | |
10008 | ||
10009 | (define_insn "ntstg" | |
10010 | [(set (match_operand:DI 0 "memory_operand" "=RT") | |
10011 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] | |
10012 | UNSPECV_NTSTG))] | |
10013 | "TARGET_HTM" | |
10014 | "ntstg\t%1,%0" | |
10015 | [(set_attr "op_type" "RXY")]) | |
10016 | ||
10017 | ; Transaction perform processor assist | |
10018 | ||
10019 | (define_expand "tx_assist" | |
10020 | [(set (match_dup 1) (const_int 0)) | |
10021 | (unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
10022 | (match_dup 1) | |
10023 | (const_int 1)] | |
10024 | UNSPECV_PPA)] | |
10025 | "TARGET_HTM" | |
10026 | { | |
10027 | operands[1] = gen_reg_rtx (SImode); | |
10028 | }) | |
10029 | ||
10030 | (define_insn "*ppa" | |
10031 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
10032 | (match_operand:SI 1 "register_operand" "d") | |
10033 | (match_operand 2 "const_int_operand" "I")] | |
10034 | UNSPECV_PPA)] | |
10035 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
10036 | "ppa\t%0,%1,1" | |
10037 | [(set_attr "op_type" "RRF")]) |