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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
66647d44 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
c75c517d | 3 | ;; 2009, 2010 Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
5 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
6 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 7 | |
58add37a UW |
8 | ;; This file is part of GCC. |
9 | ||
10 | ;; GCC is free software; you can redistribute it and/or modify it under | |
11 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
13 | ;; version. |
14 | ||
15 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | ;; for more details. | |
9db1d521 HP |
19 | |
20 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | ;; along with GCC; see the file COPYING3. If not see |
22 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
23 | |
24 | ;; | |
cd8dc1f9 | 25 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 26 | ;; |
cd8dc1f9 | 27 | |
9db1d521 HP |
28 | ;; Special formats used for outputting 390 instructions. |
29 | ;; | |
f19a9af7 AK |
30 | ;; %C: print opcode suffix for branch condition. |
31 | ;; %D: print opcode suffix for inverse branch condition. | |
32 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 33 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
34 | ;; %O: print only the displacement of a memory reference. |
35 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 36 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
37 | ;; %N: print the second word of a DImode operand. |
38 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 39 | ;; %Y: print shift count operand. |
f4aa3848 | 40 | ;; |
f19a9af7 | 41 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 42 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
43 | ;; %x: print integer X as if it's an unsigned halfword. |
44 | ;; %h: print integer X as if it's a signed halfword. | |
45 | ;; %i: print the first nonzero HImode part of X. | |
46 | ;; %j: print the first HImode part unequal to -1 of X. | |
47 | ;; %k: print the first nonzero SImode part of X. | |
48 | ;; %m: print the first SImode part unequal to -1 of X. | |
49 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
50 | ;; |
51 | ;; We have a special constraint for pattern matching. | |
52 | ;; | |
53 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
54 | ;; | |
9db1d521 | 55 | |
fd3cd001 UW |
56 | ;; |
57 | ;; UNSPEC usage | |
58 | ;; | |
59 | ||
30a49b23 AK |
60 | (define_c_enum "unspec" [ |
61 | ; Miscellaneous | |
62 | UNSPEC_ROUND | |
63 | UNSPEC_CCU_TO_INT | |
64 | UNSPEC_CCZ_TO_INT | |
65 | UNSPEC_ICM | |
66 | UNSPEC_TIE | |
10bbf137 UW |
67 | |
68 | ; GOT/PLT and lt-relative accesses | |
30a49b23 AK |
69 | UNSPEC_LTREL_OFFSET |
70 | UNSPEC_LTREL_BASE | |
71 | UNSPEC_POOL_OFFSET | |
72 | UNSPEC_GOTENT | |
73 | UNSPEC_GOT | |
74 | UNSPEC_GOTOFF | |
75 | UNSPEC_PLT | |
76 | UNSPEC_PLTOFF | |
fd7643fb UW |
77 | |
78 | ; Literal pool | |
30a49b23 AK |
79 | UNSPEC_RELOAD_BASE |
80 | UNSPEC_MAIN_BASE | |
81 | UNSPEC_LTREF | |
82 | UNSPEC_INSN | |
83 | UNSPEC_EXECUTE | |
fd7643fb | 84 | |
1a8c13b3 | 85 | ; Atomic Support |
30a49b23 | 86 | UNSPEC_MB |
1a8c13b3 | 87 | |
fd7643fb | 88 | ; TLS relocation specifiers |
30a49b23 AK |
89 | UNSPEC_TLSGD |
90 | UNSPEC_TLSLDM | |
91 | UNSPEC_NTPOFF | |
92 | UNSPEC_DTPOFF | |
93 | UNSPEC_GOTNTPOFF | |
94 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
95 | |
96 | ; TLS support | |
30a49b23 AK |
97 | UNSPEC_TLSLDM_NTPOFF |
98 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
99 | |
100 | ; String Functions | |
30a49b23 AK |
101 | UNSPEC_SRST |
102 | UNSPEC_MVST | |
638e37c2 | 103 | |
7b8acc34 | 104 | ; Stack Smashing Protector |
30a49b23 AK |
105 | UNSPEC_SP_SET |
106 | UNSPEC_SP_TEST | |
85dae55a | 107 | |
638e37c2 | 108 | ; Test Data Class (TDC) |
30a49b23 | 109 | UNSPEC_TDC_INSN |
65b1d8ea AK |
110 | |
111 | ; Population Count | |
30a49b23 AK |
112 | UNSPEC_POPCNT |
113 | UNSPEC_COPYSIGN | |
fd3cd001 UW |
114 | ]) |
115 | ||
116 | ;; | |
117 | ;; UNSPEC_VOLATILE usage | |
118 | ;; | |
119 | ||
30a49b23 AK |
120 | (define_c_enum "unspecv" [ |
121 | ; Blockage | |
122 | UNSPECV_BLOCKAGE | |
10bbf137 | 123 | |
2f7e5a0d | 124 | ; TPF Support |
30a49b23 AK |
125 | UNSPECV_TPF_PROLOGUE |
126 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 127 | |
10bbf137 | 128 | ; Literal pool |
30a49b23 AK |
129 | UNSPECV_POOL |
130 | UNSPECV_POOL_SECTION | |
131 | UNSPECV_POOL_ALIGN | |
132 | UNSPECV_POOL_ENTRY | |
133 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
134 | |
135 | ; TLS support | |
30a49b23 | 136 | UNSPECV_SET_TP |
e0374221 AS |
137 | |
138 | ; Atomic Support | |
30a49b23 AK |
139 | UNSPECV_CAS |
140 | UNSPECV_ATOMIC_OP | |
fd3cd001 UW |
141 | ]) |
142 | ||
ae156f85 AS |
143 | ;; |
144 | ;; Registers | |
145 | ;; | |
146 | ||
35dd9a0e AK |
147 | ; Registers with special meaning |
148 | ||
ae156f85 AS |
149 | (define_constants |
150 | [ | |
151 | ; Sibling call register. | |
152 | (SIBCALL_REGNUM 1) | |
153 | ; Literal pool base register. | |
154 | (BASE_REGNUM 13) | |
155 | ; Return address register. | |
156 | (RETURN_REGNUM 14) | |
157 | ; Condition code register. | |
158 | (CC_REGNUM 33) | |
f4aa3848 | 159 | ; Thread local storage pointer register. |
ae156f85 AS |
160 | (TP_REGNUM 36) |
161 | ]) | |
162 | ||
35dd9a0e AK |
163 | ; Hardware register names |
164 | ||
165 | (define_constants | |
166 | [ | |
167 | ; General purpose registers | |
168 | (GPR0_REGNUM 0) | |
169 | ; Floating point registers. | |
170 | (FPR0_REGNUM 16) | |
171 | (FPR2_REGNUM 18) | |
172 | ]) | |
173 | ||
174 | ;; | |
175 | ;; PFPO GPR0 argument format | |
176 | ;; | |
177 | ||
178 | (define_constants | |
179 | [ | |
180 | ; PFPO operation type | |
181 | (PFPO_CONVERT 0x1000000) | |
182 | ; PFPO operand types | |
183 | (PFPO_OP_TYPE_SF 0x5) | |
184 | (PFPO_OP_TYPE_DF 0x6) | |
185 | (PFPO_OP_TYPE_TF 0x7) | |
186 | (PFPO_OP_TYPE_SD 0x8) | |
187 | (PFPO_OP_TYPE_DD 0x9) | |
188 | (PFPO_OP_TYPE_TD 0xa) | |
189 | ; Bitposition of operand types | |
190 | (PFPO_OP0_TYPE_SHIFT 16) | |
191 | (PFPO_OP1_TYPE_SHIFT 8) | |
192 | ]) | |
193 | ||
fd3cd001 | 194 | |
29a74354 UW |
195 | ;; Instruction operand type as used in the Principles of Operation. |
196 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 197 | |
29a74354 | 198 | (define_attr "op_type" |
963fc8d0 | 199 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" |
b628bd8e | 200 | (const_string "NN")) |
9db1d521 | 201 | |
29a74354 | 202 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 203 | |
077dab3b | 204 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 205 | cs,vs,store,sem,idiv, |
ed0e512a | 206 | imulhi,imulsi,imuldi, |
2cdece44 | 207 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
208 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
209 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 210 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 211 | fmadddf,fmaddsf, |
9381e3f1 WG |
212 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
213 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
214 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
215 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
216 | ftoidfp, other" | |
29a74354 UW |
217 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
218 | (eq_attr "op_type" "SS") (const_string "cs")] | |
219 | (const_string "integer"))) | |
9db1d521 | 220 | |
29a74354 UW |
221 | ;; Another attribute used for scheduling purposes: |
222 | ;; agen: Instruction uses the address generation unit | |
223 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
224 | |
225 | (define_attr "atype" "agen,reg" | |
c68e7b86 | 226 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") |
0101708c AS |
227 | (const_string "reg") |
228 | (const_string "agen"))) | |
9db1d521 | 229 | |
9381e3f1 WG |
230 | ;; Properties concerning Z10 execution grouping and value forwarding. |
231 | ;; z10_super: instruction is superscalar. | |
232 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
233 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
234 | ;; target register. It can forward this value to a second instruction that reads | |
235 | ;; the same register if that second instruction is issued in the same group. | |
236 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
237 | ;; instruction in the S pipe writes to the register, then the T instruction | |
238 | ;; can immediately read the new value. | |
239 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
240 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
241 | ;; |
242 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
243 | ||
244 | ||
245 | (define_attr "z10prop" "none, | |
246 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
247 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
248 | z10_rec, | |
249 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 250 | z10_c" |
9381e3f1 WG |
251 | (const_string "none")) |
252 | ||
65b1d8ea AK |
253 | ;; Properties concerning Z196 decoding |
254 | ;; z196_alone: must group alone | |
255 | ;; z196_end: ends a group | |
256 | ;; z196_cracked: instruction is cracked or expanded | |
257 | (define_attr "z196prop" "none, | |
258 | z196_alone, z196_ends, | |
259 | z196_cracked" | |
260 | (const_string "none")) | |
9381e3f1 | 261 | |
9db1d521 HP |
262 | ;; Length in bytes. |
263 | ||
264 | (define_attr "length" "" | |
963fc8d0 AK |
265 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
266 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 267 | (const_int 6))) |
9db1d521 | 268 | |
29a74354 UW |
269 | |
270 | ;; Processor type. This attribute must exactly match the processor_type | |
271 | ;; enumeration in s390.h. The current machine description does not | |
272 | ;; distinguish between g5 and g6, but there are differences between the two | |
273 | ;; CPUs could in theory be modeled. | |
274 | ||
f137aa63 | 275 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196" |
90c6fd8a | 276 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 277 | |
65b1d8ea | 278 | (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196" |
3af8e996 AK |
279 | (const_string "standard")) |
280 | ||
281 | (define_attr "enabled" "" | |
282 | (cond [(eq_attr "cpu_facility" "standard") | |
283 | (const_int 1) | |
284 | ||
285 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 286 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
287 | (const_int 1) |
288 | ||
289 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 290 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
291 | (const_int 1) |
292 | ||
293 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 294 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
295 | (const_int 1) |
296 | ||
297 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 298 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
299 | (const_int 1) |
300 | ||
301 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 302 | (match_test "TARGET_DFP")) |
93538e8e AK |
303 | (const_int 1) |
304 | ||
305 | (and (eq_attr "cpu_facility" "z10") | |
d7f99b2c | 306 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
307 | (const_int 1) |
308 | ||
309 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 310 | (match_test "TARGET_Z196")) |
3af8e996 AK |
311 | (const_int 1)] |
312 | (const_int 0))) | |
313 | ||
29a74354 UW |
314 | ;; Pipeline description for z900. For lack of anything better, |
315 | ;; this description is also used for the g5 and g6. | |
316 | (include "2064.md") | |
317 | ||
3443392a | 318 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
319 | (include "2084.md") |
320 | ||
9381e3f1 WG |
321 | ;; Pipeline description for z10 |
322 | (include "2097.md") | |
323 | ||
65b1d8ea AK |
324 | ;; Pipeline description for z196 |
325 | (include "2817.md") | |
326 | ||
0bfc3f69 AS |
327 | ;; Predicates |
328 | (include "predicates.md") | |
329 | ||
cd8dc1f9 WG |
330 | ;; Constraint definitions |
331 | (include "constraints.md") | |
332 | ||
a8ba31f2 EC |
333 | ;; Other includes |
334 | (include "tpf.md") | |
f52c81dd | 335 | |
3abcb3a7 | 336 | ;; Iterators |
f52c81dd | 337 | |
3abcb3a7 | 338 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 339 | ;; same template. |
f4aa3848 | 340 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 341 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 | 342 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
963fc8d0 | 343 | (define_mode_iterator FPALL [TF DF SF TD DD SD]) |
3abcb3a7 HPN |
344 | (define_mode_iterator BFP [TF DF SF]) |
345 | (define_mode_iterator DFP [TD DD]) | |
346 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
347 | (define_mode_iterator DSF [DF SF]) | |
348 | (define_mode_iterator SD_SF [SF SD]) | |
349 | (define_mode_iterator DD_DF [DF DD]) | |
350 | (define_mode_iterator TD_TF [TF TD]) | |
351 | ||
352 | ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated | |
8006eaa6 | 353 | ;; from the same template. |
3abcb3a7 | 354 | (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI]) |
8006eaa6 | 355 | |
3abcb3a7 | 356 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 357 | ;; from the same template. |
9602b6a1 | 358 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
3abcb3a7 | 359 | (define_mode_iterator DSI [DI SI]) |
9db2f16d | 360 | |
3abcb3a7 | 361 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 362 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 363 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 364 | |
9602b6a1 AK |
365 | ;; These macros refer to the actual word_mode of the configuration. This is equal |
366 | ;; to Pmode except on 31-bit machines in zarch mode. | |
367 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) | |
368 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
369 | ||
6e0d70c9 AK |
370 | ;; Used by the umul pattern to express modes having half the size. |
371 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
372 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
373 | ||
3abcb3a7 | 374 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 375 | ;; the same template. |
3abcb3a7 | 376 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 377 | |
3abcb3a7 | 378 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 379 | ;; same template. |
9602b6a1 | 380 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
963fc8d0 | 381 | (define_mode_iterator INTALL [TI DI SI HI QI]) |
342cf42b | 382 | |
3abcb3a7 | 383 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 384 | ;; the same template. |
3abcb3a7 | 385 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 386 | |
3abcb3a7 HPN |
387 | ;; This iterator and attribute allow to combine most atomic operations. |
388 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 389 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
f4aa3848 | 390 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") |
45d18331 | 391 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 392 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 393 | |
f4aa3848 | 394 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
395 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
396 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 397 | |
f4aa3848 AK |
398 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
399 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
400 | ;; SDmode. |
401 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 402 | |
609e7e80 | 403 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
404 | ;; Likewise for "<RXe>". |
405 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
406 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
407 | ||
609e7e80 | 408 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 409 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
410 | ;; dfp variants in a single insn definition. |
411 | ||
3abcb3a7 | 412 | ;; This attribute is used to set op_type accordingly. |
f4aa3848 | 413 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
609e7e80 AK |
414 | (DD "RRR") (SD "RRR")]) |
415 | ||
f4aa3848 | 416 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
417 | ;; first and the second operand match for bfp modes. |
418 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
419 | ||
f4aa3848 | 420 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
421 | ;; additional operand for the dfp instructions. |
422 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
423 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
424 | ||
f5905b37 | 425 | |
85dae55a AK |
426 | ;; This attribute is used in the operand constraint list |
427 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
428 | ;; TFmode values are represented by a fp register pair. Since the | |
429 | ;; sign bit instructions only handle single source and target fp registers | |
430 | ;; these instructions can only be used for TFmode values if the source and | |
431 | ;; target operand uses the same fp register. | |
432 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
433 | ||
609e7e80 AK |
434 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
435 | ;; This is used to disable the memory alternative in TFmode patterns. | |
436 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
437 | ||
3abcb3a7 | 438 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
439 | ;; within instruction mnemonics. |
440 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
441 | ||
0387c142 WG |
442 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
443 | ;; modes and to an empty string for bfp modes. | |
444 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
445 | ||
1b48c8cc AS |
446 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
447 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
448 | ;; version only operates on one register. | |
449 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
450 | ||
451 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
452 | ;; version only operates on one register. The DImode version needs an additional | |
453 | ;; register for the assembler output. | |
454 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
455 | |
456 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
457 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
458 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
459 | ||
460 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 461 | ;; pattern itself and the corresponding function calls. |
f337b930 | 462 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
463 | |
464 | ;; This attribute handles differences in the instruction 'type' and will result | |
465 | ;; in "RRE" for DImode and "RR" for SImode. | |
466 | (define_mode_attr E [(DI "E") (SI "")]) | |
467 | ||
3298c037 AK |
468 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
469 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
470 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
471 | ||
8006eaa6 AS |
472 | ;; This attribute handles differences in the instruction 'type' and will result |
473 | ;; in "RSE" for TImode and "RS" for DImode. | |
474 | (define_mode_attr TE [(TI "E") (DI "")]) | |
475 | ||
9a91a21f AS |
476 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
477 | ;; and "lcr" in SImode. | |
478 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 479 | |
3298c037 AK |
480 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
481 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
482 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
483 | ;; variant for long displacements. | |
484 | (define_mode_attr y [(DI "g") (SI "y")]) | |
485 | ||
9602b6a1 | 486 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
487 | ;; and "cds" in DImode. |
488 | (define_mode_attr tg [(TI "g") (DI "")]) | |
489 | ||
2f8f8434 AS |
490 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
491 | ;; and "cfdbr" in SImode. | |
492 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
493 | ||
65b1d8ea AK |
494 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
495 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
496 | ;; 3 operands shift instructions into the existing patterns. | |
497 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
498 | ||
f52c81dd AS |
499 | ;; ICM mask required to load MODE value into the lowest subreg |
500 | ;; of a SImode register. | |
501 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
502 | ||
f6ee577c AS |
503 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
504 | ;; HImode and "llgc" in QImode. | |
505 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
506 | ||
a1aed706 AS |
507 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
508 | ;; in SImode. | |
509 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
510 | ||
609e7e80 AK |
511 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
512 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
513 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
514 | ||
f52c81dd AS |
515 | ;; Maximum unsigned integer that fits in MODE. |
516 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
517 | ||
9db1d521 HP |
518 | ;; |
519 | ;;- Compare instructions. | |
520 | ;; | |
521 | ||
07893d4f | 522 | ; Test-under-Mask instructions |
9db1d521 | 523 | |
07893d4f | 524 | (define_insn "*tmqi_mem" |
ae156f85 | 525 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
526 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
527 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
528 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 529 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 530 | "@ |
fc0ea003 UW |
531 | tm\t%S0,%b1 |
532 | tmy\t%S0,%b1" | |
9381e3f1 WG |
533 | [(set_attr "op_type" "SI,SIY") |
534 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 535 | |
05b9aaaa | 536 | (define_insn "*tmdi_reg" |
ae156f85 | 537 | [(set (reg CC_REGNUM) |
f19a9af7 | 538 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 539 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
540 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
541 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 542 | "TARGET_ZARCH |
3ed99cc9 | 543 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
544 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
545 | "@ | |
546 | tmhh\t%0,%i1 | |
547 | tmhl\t%0,%i1 | |
548 | tmlh\t%0,%i1 | |
549 | tmll\t%0,%i1" | |
9381e3f1 WG |
550 | [(set_attr "op_type" "RI") |
551 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
552 | |
553 | (define_insn "*tmsi_reg" | |
ae156f85 | 554 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
555 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
556 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
557 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 558 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
559 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
560 | "@ | |
561 | tmh\t%0,%i1 | |
562 | tml\t%0,%i1" | |
729e750f WG |
563 | [(set_attr "op_type" "RI") |
564 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 565 | |
f52c81dd | 566 | (define_insn "*tm<mode>_full" |
ae156f85 | 567 | [(set (reg CC_REGNUM) |
f52c81dd AS |
568 | (compare (match_operand:HQI 0 "register_operand" "d") |
569 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 570 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 571 | "tml\t%0,<max_uint>" |
729e750f WG |
572 | [(set_attr "op_type" "RI") |
573 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 574 | |
07893d4f | 575 | |
08a5aaa2 | 576 | ; |
07893d4f | 577 | ; Load-and-Test instructions |
08a5aaa2 AS |
578 | ; |
579 | ||
c0220ea4 | 580 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
581 | |
582 | (define_insn "*tstdi_sign" | |
ae156f85 | 583 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
584 | (compare |
585 | (ashiftrt:DI | |
586 | (ashift:DI | |
587 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
588 | (const_int 32)) (const_int 32)) | |
589 | (match_operand:DI 1 "const0_operand" ""))) | |
590 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 591 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 592 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
593 | "ltgfr\t%2,%0 |
594 | ltgf\t%2,%0" | |
595 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
596 | (set_attr "cpu_facility" "*,z10") |
597 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 598 | |
43a09b63 | 599 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 600 | (define_insn "*tst<mode>_extimm" |
ec24698e | 601 | [(set (reg CC_REGNUM) |
fb492564 | 602 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
603 | (match_operand:GPR 1 "const0_operand" ""))) |
604 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 605 | (match_dup 0))] |
08a5aaa2 | 606 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 607 | "@ |
08a5aaa2 AS |
608 | lt<g>r\t%2,%0 |
609 | lt<g>\t%2,%0" | |
9381e3f1 | 610 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 611 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 612 | |
43a09b63 | 613 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 614 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 615 | [(set (reg CC_REGNUM) |
fb492564 | 616 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
617 | (match_operand:GPR 1 "const0_operand" ""))) |
618 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
619 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 620 | "@ |
08a5aaa2 AS |
621 | lt<g>r\t%0,%0 |
622 | lt<g>\t%2,%0" | |
9381e3f1 | 623 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 624 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 625 | |
07893d4f | 626 | (define_insn "*tstdi" |
ae156f85 | 627 | [(set (reg CC_REGNUM) |
07893d4f UW |
628 | (compare (match_operand:DI 0 "register_operand" "d") |
629 | (match_operand:DI 1 "const0_operand" ""))) | |
630 | (set (match_operand:DI 2 "register_operand" "=d") | |
631 | (match_dup 0))] | |
9602b6a1 | 632 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 633 | "ltgr\t%2,%0" |
9381e3f1 WG |
634 | [(set_attr "op_type" "RRE") |
635 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 636 | |
07893d4f | 637 | (define_insn "*tstsi" |
ae156f85 | 638 | [(set (reg CC_REGNUM) |
d3632d41 | 639 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 640 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 641 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 642 | (match_dup 0))] |
ec24698e | 643 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 644 | "@ |
d40c829f | 645 | ltr\t%2,%0 |
fc0ea003 UW |
646 | icm\t%2,15,%S0 |
647 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
648 | [(set_attr "op_type" "RR,RS,RSY") |
649 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 650 | |
07893d4f | 651 | (define_insn "*tstsi_cconly" |
ae156f85 | 652 | [(set (reg CC_REGNUM) |
d3632d41 | 653 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 654 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 655 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
656 | "s390_match_ccmode(insn, CCSmode)" |
657 | "@ | |
d40c829f | 658 | ltr\t%0,%0 |
fc0ea003 UW |
659 | icm\t%2,15,%S0 |
660 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
661 | [(set_attr "op_type" "RR,RS,RSY") |
662 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 663 | |
08a5aaa2 AS |
664 | (define_insn "*tstdi_cconly_31" |
665 | [(set (reg CC_REGNUM) | |
666 | (compare (match_operand:DI 0 "register_operand" "d") | |
667 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 668 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
669 | "srda\t%0,0" |
670 | [(set_attr "op_type" "RS") | |
671 | (set_attr "atype" "reg")]) | |
672 | ||
43a09b63 | 673 | ; ltr, ltgr |
08a5aaa2 | 674 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 675 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
676 | (compare (match_operand:GPR 0 "register_operand" "d") |
677 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 678 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 679 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
680 | [(set_attr "op_type" "RR<E>") |
681 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 682 | |
c0220ea4 | 683 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 684 | |
f52c81dd | 685 | (define_insn "*tst<mode>CCT" |
ae156f85 | 686 | [(set (reg CC_REGNUM) |
f52c81dd AS |
687 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
688 | (match_operand:HQI 1 "const0_operand" ""))) | |
689 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
690 | (match_dup 0))] |
691 | "s390_match_ccmode(insn, CCTmode)" | |
692 | "@ | |
f52c81dd AS |
693 | icm\t%2,<icm_lo>,%S0 |
694 | icmy\t%2,<icm_lo>,%S0 | |
695 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
696 | [(set_attr "op_type" "RS,RSY,RI") |
697 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
698 | |
699 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 700 | [(set (reg CC_REGNUM) |
d3632d41 | 701 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 702 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 703 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
704 | "s390_match_ccmode(insn, CCTmode)" |
705 | "@ | |
fc0ea003 UW |
706 | icm\t%2,3,%S0 |
707 | icmy\t%2,3,%S0 | |
d40c829f | 708 | tml\t%0,65535" |
9381e3f1 WG |
709 | [(set_attr "op_type" "RS,RSY,RI") |
710 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 711 | |
3af97654 | 712 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 713 | [(set (reg CC_REGNUM) |
d3632d41 | 714 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
715 | (match_operand:QI 1 "const0_operand" "")))] |
716 | "s390_match_ccmode(insn, CCTmode)" | |
717 | "@ | |
fc0ea003 UW |
718 | cli\t%S0,0 |
719 | cliy\t%S0,0 | |
d40c829f | 720 | tml\t%0,255" |
9381e3f1 | 721 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 722 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 723 | |
f52c81dd | 724 | (define_insn "*tst<mode>" |
ae156f85 | 725 | [(set (reg CC_REGNUM) |
f52c81dd AS |
726 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
727 | (match_operand:HQI 1 "const0_operand" ""))) | |
728 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
729 | (match_dup 0))] |
730 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 731 | "@ |
f52c81dd AS |
732 | icm\t%2,<icm_lo>,%S0 |
733 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
734 | [(set_attr "op_type" "RS,RSY") |
735 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 736 | |
f52c81dd | 737 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 738 | [(set (reg CC_REGNUM) |
f52c81dd AS |
739 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
740 | (match_operand:HQI 1 "const0_operand" ""))) | |
741 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 742 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 743 | "@ |
f52c81dd AS |
744 | icm\t%2,<icm_lo>,%S0 |
745 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
746 | [(set_attr "op_type" "RS,RSY") |
747 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 748 | |
9db1d521 | 749 | |
575f7c2b UW |
750 | ; Compare (equality) instructions |
751 | ||
752 | (define_insn "*cmpdi_cct" | |
ae156f85 | 753 | [(set (reg CC_REGNUM) |
ec24698e | 754 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 755 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 756 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
757 | "@ |
758 | cgr\t%0,%1 | |
f4f41b4e | 759 | cghi\t%0,%h1 |
ec24698e | 760 | cgfi\t%0,%1 |
575f7c2b | 761 | cg\t%0,%1 |
19b63d8e | 762 | #" |
9381e3f1 WG |
763 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
764 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
765 | |
766 | (define_insn "*cmpsi_cct" | |
ae156f85 | 767 | [(set (reg CC_REGNUM) |
ec24698e UW |
768 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
769 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 770 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
771 | "@ |
772 | cr\t%0,%1 | |
f4f41b4e | 773 | chi\t%0,%h1 |
ec24698e | 774 | cfi\t%0,%1 |
575f7c2b UW |
775 | c\t%0,%1 |
776 | cy\t%0,%1 | |
19b63d8e | 777 | #" |
9381e3f1 | 778 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 779 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 780 | |
07893d4f | 781 | ; Compare (signed) instructions |
4023fb28 | 782 | |
07893d4f | 783 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 784 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
785 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
786 | "d,RT,b")) | |
787 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 788 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 789 | "@ |
d40c829f | 790 | cgfr\t%0,%1 |
963fc8d0 AK |
791 | cgf\t%0,%1 |
792 | cgfrl\t%0,%1" | |
793 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 794 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 795 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 796 | |
9381e3f1 WG |
797 | |
798 | ||
07893d4f | 799 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 800 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
801 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
802 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 803 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 804 | "@ |
d40c829f | 805 | ch\t%0,%1 |
963fc8d0 AK |
806 | chy\t%0,%1 |
807 | chrl\t%0,%1" | |
808 | [(set_attr "op_type" "RX,RXY,RIL") | |
809 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
810 | (set_attr "type" "*,*,larl") |
811 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
812 | |
813 | (define_insn "*cmphi_ccs_z10" | |
814 | [(set (reg CC_REGNUM) | |
815 | (compare (match_operand:HI 0 "s_operand" "Q") | |
816 | (match_operand:HI 1 "immediate_operand" "K")))] | |
817 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
818 | "chhsi\t%0,%1" | |
65b1d8ea AK |
819 | [(set_attr "op_type" "SIL") |
820 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
821 | |
822 | (define_insn "*cmpdi_ccs_signhi_rl" | |
823 | [(set (reg CC_REGNUM) | |
824 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
825 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
826 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
827 | "@ | |
828 | cgh\t%0,%1 | |
829 | cghrl\t%0,%1" | |
830 | [(set_attr "op_type" "RXY,RIL") | |
831 | (set_attr "type" "*,larl")]) | |
4023fb28 | 832 | |
963fc8d0 | 833 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 834 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 835 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
836 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
837 | "d,d,Q, d,d,d,d") | |
838 | (match_operand:GPR 1 "general_operand" | |
839 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 840 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 841 | "@ |
3298c037 AK |
842 | c<g>r\t%0,%1 |
843 | c<g>hi\t%0,%h1 | |
963fc8d0 | 844 | c<g>hsi\t%0,%h1 |
3298c037 AK |
845 | c<g>fi\t%0,%1 |
846 | c<g>\t%0,%1 | |
963fc8d0 AK |
847 | c<y>\t%0,%1 |
848 | c<g>rl\t%0,%1" | |
849 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
850 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
851 | (set_attr "type" "*,*,*,*,*,*,larl") |
852 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 853 | |
07893d4f UW |
854 | |
855 | ; Compare (unsigned) instructions | |
9db1d521 | 856 | |
963fc8d0 AK |
857 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
858 | [(set (reg CC_REGNUM) | |
859 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
860 | "larl_operand" "X"))) | |
861 | (match_operand:SI 0 "register_operand" "d")))] | |
862 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
863 | "clhrl\t%0,%1" | |
864 | [(set_attr "op_type" "RIL") | |
729e750f WG |
865 | (set_attr "type" "larl") |
866 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
867 | |
868 | ; clhrl, clghrl | |
869 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
870 | [(set (reg CC_REGNUM) | |
871 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
872 | "larl_operand" "X"))) | |
873 | (match_operand:GPR 0 "register_operand" "d")))] | |
874 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
875 | "cl<g>hrl\t%0,%1" | |
876 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
877 | (set_attr "type" "larl") |
878 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 879 | |
07893d4f | 880 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 881 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
882 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
883 | "d,RT,b")) | |
884 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 885 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 886 | "@ |
d40c829f | 887 | clgfr\t%0,%1 |
963fc8d0 AK |
888 | clgf\t%0,%1 |
889 | clgfrl\t%0,%1" | |
890 | [(set_attr "op_type" "RRE,RXY,RIL") | |
891 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
892 | (set_attr "type" "*,*,larl") |
893 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 894 | |
07893d4f | 895 | (define_insn "*cmpdi_ccu" |
ae156f85 | 896 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
897 | (compare (match_operand:DI 0 "nonimmediate_operand" |
898 | "d, d,d,Q, d, Q,BQ") | |
899 | (match_operand:DI 1 "general_operand" | |
900 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 901 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 902 | "@ |
d40c829f | 903 | clgr\t%0,%1 |
ec24698e | 904 | clgfi\t%0,%1 |
963fc8d0 AK |
905 | clgrl\t%0,%1 |
906 | clghsi\t%0,%x1 | |
575f7c2b | 907 | clg\t%0,%1 |
e221ef54 | 908 | # |
19b63d8e | 909 | #" |
963fc8d0 AK |
910 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
911 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
912 | (set_attr "type" "*,*,larl,*,*,*,*") |
913 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 914 | |
07893d4f | 915 | (define_insn "*cmpsi_ccu" |
ae156f85 | 916 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
917 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
918 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 919 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 920 | "@ |
d40c829f | 921 | clr\t%0,%1 |
ec24698e | 922 | clfi\t%0,%o1 |
963fc8d0 AK |
923 | clrl\t%0,%1 |
924 | clfhsi\t%0,%x1 | |
d40c829f | 925 | cl\t%0,%1 |
575f7c2b | 926 | cly\t%0,%1 |
e221ef54 | 927 | # |
19b63d8e | 928 | #" |
963fc8d0 AK |
929 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
930 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
931 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
932 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 933 | |
07893d4f | 934 | (define_insn "*cmphi_ccu" |
ae156f85 | 935 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
936 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
937 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 938 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 939 | && !register_operand (operands[1], HImode)" |
d3632d41 | 940 | "@ |
fc0ea003 UW |
941 | clm\t%0,3,%S1 |
942 | clmy\t%0,3,%S1 | |
963fc8d0 | 943 | clhhsi\t%0,%1 |
e221ef54 | 944 | # |
19b63d8e | 945 | #" |
963fc8d0 | 946 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
947 | (set_attr "cpu_facility" "*,*,z10,*,*") |
948 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
949 | |
950 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 951 | [(set (reg CC_REGNUM) |
e221ef54 UW |
952 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
953 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 954 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 955 | && !register_operand (operands[1], QImode)" |
d3632d41 | 956 | "@ |
fc0ea003 UW |
957 | clm\t%0,1,%S1 |
958 | clmy\t%0,1,%S1 | |
959 | cli\t%S0,%b1 | |
960 | cliy\t%S0,%b1 | |
e221ef54 | 961 | # |
19b63d8e | 962 | #" |
9381e3f1 WG |
963 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
964 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
965 | |
966 | ||
19b63d8e UW |
967 | ; Block compare (CLC) instruction patterns. |
968 | ||
969 | (define_insn "*clc" | |
ae156f85 | 970 | [(set (reg CC_REGNUM) |
d4f52f0e | 971 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
972 | (match_operand:BLK 1 "memory_operand" "Q"))) |
973 | (use (match_operand 2 "const_int_operand" "n"))] | |
974 | "s390_match_ccmode (insn, CCUmode) | |
975 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 976 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 977 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
978 | |
979 | (define_split | |
ae156f85 | 980 | [(set (reg CC_REGNUM) |
19b63d8e UW |
981 | (compare (match_operand 0 "memory_operand" "") |
982 | (match_operand 1 "memory_operand" "")))] | |
983 | "reload_completed | |
984 | && s390_match_ccmode (insn, CCUmode) | |
985 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
986 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
987 | [(parallel | |
988 | [(set (match_dup 0) (match_dup 1)) | |
989 | (use (match_dup 2))])] | |
990 | { | |
991 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
992 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
993 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
994 | ||
995 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
996 | operands[0], operands[1]); | |
997 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
998 | }) | |
999 | ||
1000 | ||
609e7e80 | 1001 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1002 | |
609e7e80 | 1003 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1004 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1005 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1006 | (compare (match_operand:FP 0 "register_operand" "f") |
1007 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1008 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1009 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1010 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1011 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1012 | |
be5de7a1 | 1013 | ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb |
f5905b37 | 1014 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1015 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1016 | (compare (match_operand:FP 0 "register_operand" "f,f") |
1017 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 1018 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1019 | "@ |
609e7e80 | 1020 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1021 | c<xde>b\t%0,%1" |
077dab3b | 1022 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 1023 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1024 | |
963fc8d0 AK |
1025 | |
1026 | ; Compare and Branch instructions | |
1027 | ||
1028 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1029 | ; The following instructions do a complementary access of their second |
1030 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1031 | (define_insn "*cmp_and_br_signed_<mode>" |
1032 | [(set (pc) | |
1033 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1034 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1035 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1036 | (label_ref (match_operand 3 "" "")) | |
1037 | (pc))) | |
1038 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1039 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1040 | { |
1041 | if (get_attr_length (insn) == 6) | |
1042 | return which_alternative ? | |
1043 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1044 | else | |
1045 | return which_alternative ? | |
1046 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1047 | } | |
1048 | [(set_attr "op_type" "RIE") | |
1049 | (set_attr "type" "branch") | |
e3cba5e5 | 1050 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1051 | (set (attr "length") |
1052 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1053 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1054 | ; 10 byte for cgr/jg | |
1055 | ||
1056 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1057 | ; The following instructions do a complementary access of their second |
1058 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1059 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1060 | [(set (pc) | |
1061 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1062 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1063 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1064 | (label_ref (match_operand 3 "" "")) | |
1065 | (pc))) | |
1066 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1067 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1068 | { |
1069 | if (get_attr_length (insn) == 6) | |
1070 | return which_alternative ? | |
1071 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1072 | else | |
1073 | return which_alternative ? | |
1074 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1075 | } | |
1076 | [(set_attr "op_type" "RIE") | |
1077 | (set_attr "type" "branch") | |
e3cba5e5 | 1078 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1079 | (set (attr "length") |
1080 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1081 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1082 | ; 10 byte for clgr/jg | |
1083 | ||
b0f86a7e AK |
1084 | ; And now the same two patterns as above but with a negated CC mask. |
1085 | ||
1086 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1087 | ; The following instructions do a complementary access of their second | |
1088 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1089 | (define_insn "*icmp_and_br_signed_<mode>" | |
1090 | [(set (pc) | |
1091 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1092 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1093 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1094 | (pc) | |
1095 | (label_ref (match_operand 3 "" "")))) | |
1096 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1097 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1098 | { |
1099 | if (get_attr_length (insn) == 6) | |
1100 | return which_alternative ? | |
1101 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1102 | else | |
1103 | return which_alternative ? | |
1104 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1105 | } | |
1106 | [(set_attr "op_type" "RIE") | |
1107 | (set_attr "type" "branch") | |
1108 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1109 | (set (attr "length") | |
1110 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1111 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1112 | ; 10 byte for cgr/jg | |
1113 | ||
1114 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1115 | ; The following instructions do a complementary access of their second | |
1116 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1117 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1118 | [(set (pc) | |
1119 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1120 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1121 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1122 | (pc) | |
1123 | (label_ref (match_operand 3 "" "")))) | |
1124 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1125 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1126 | { |
1127 | if (get_attr_length (insn) == 6) | |
1128 | return which_alternative ? | |
1129 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1130 | else | |
1131 | return which_alternative ? | |
1132 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1133 | } | |
1134 | [(set_attr "op_type" "RIE") | |
1135 | (set_attr "type" "branch") | |
1136 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1137 | (set (attr "length") | |
1138 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1139 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1140 | ; 10 byte for clgr/jg | |
1141 | ||
9db1d521 HP |
1142 | ;; |
1143 | ;;- Move instructions. | |
1144 | ;; | |
1145 | ||
1146 | ; | |
1147 | ; movti instruction pattern(s). | |
1148 | ; | |
1149 | ||
1150 | (define_insn "movti" | |
f2dc2f86 AK |
1151 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") |
1152 | (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] | |
9602b6a1 | 1153 | "TARGET_ZARCH" |
4023fb28 | 1154 | "@ |
fc0ea003 UW |
1155 | lmg\t%0,%N0,%S1 |
1156 | stmg\t%1,%N1,%S0 | |
4023fb28 | 1157 | # |
19b63d8e | 1158 | #" |
f2dc2f86 AK |
1159 | [(set_attr "op_type" "RSY,RSY,*,*") |
1160 | (set_attr "type" "lm,stm,*,*")]) | |
4023fb28 UW |
1161 | |
1162 | (define_split | |
1163 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1164 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1165 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1166 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1167 | [(set (match_dup 2) (match_dup 4)) |
1168 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1169 | { |
dc65c307 UW |
1170 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1171 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1172 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1173 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1174 | }) | |
1175 | ||
1176 | (define_split | |
1177 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1178 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1179 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1180 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1181 | [(set (match_dup 2) (match_dup 4)) | |
1182 | (set (match_dup 3) (match_dup 5))] | |
1183 | { | |
1184 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1185 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1186 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1187 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1188 | }) | |
4023fb28 UW |
1189 | |
1190 | (define_split | |
1191 | [(set (match_operand:TI 0 "register_operand" "") | |
1192 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1193 | "TARGET_ZARCH && reload_completed |
4023fb28 | 1194 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1195 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1196 | { |
1197 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1198 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1199 | s390_load_address (addr, XEXP (operands[1], 0)); |
1200 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1201 | }) |
1202 | ||
833cd70a AK |
1203 | |
1204 | ; | |
1205 | ; Patterns used for secondary reloads | |
1206 | ; | |
1207 | ||
963fc8d0 AK |
1208 | ; z10 provides move instructions accepting larl memory operands. |
1209 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1210 | ; These patterns are also used for unaligned SI and DI accesses. | |
1211 | ||
1212 | (define_expand "reload<INTALL:mode><P:mode>_tomem_z10" | |
1213 | [(parallel [(match_operand:INTALL 0 "memory_operand" "") | |
1214 | (match_operand:INTALL 1 "register_operand" "=d") | |
1215 | (match_operand:P 2 "register_operand" "=&a")])] | |
1216 | "TARGET_Z10" | |
1217 | { | |
1218 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1219 | DONE; | |
1220 | }) | |
1221 | ||
1222 | (define_expand "reload<INTALL:mode><P:mode>_toreg_z10" | |
1223 | [(parallel [(match_operand:INTALL 0 "register_operand" "=d") | |
1224 | (match_operand:INTALL 1 "memory_operand" "") | |
1225 | (match_operand:P 2 "register_operand" "=a")])] | |
1226 | "TARGET_Z10" | |
1227 | { | |
1228 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1229 | DONE; | |
1230 | }) | |
1231 | ||
1232 | (define_expand "reload<FPALL:mode><P:mode>_tomem_z10" | |
1233 | [(parallel [(match_operand:FPALL 0 "memory_operand" "") | |
1234 | (match_operand:FPALL 1 "register_operand" "=d") | |
1235 | (match_operand:P 2 "register_operand" "=&a")])] | |
1236 | "TARGET_Z10" | |
1237 | { | |
1238 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1239 | DONE; | |
1240 | }) | |
1241 | ||
1242 | (define_expand "reload<FPALL:mode><P:mode>_toreg_z10" | |
1243 | [(parallel [(match_operand:FPALL 0 "register_operand" "=d") | |
1244 | (match_operand:FPALL 1 "memory_operand" "") | |
1245 | (match_operand:P 2 "register_operand" "=a")])] | |
1246 | "TARGET_Z10" | |
1247 | { | |
1248 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1249 | DONE; | |
1250 | }) | |
1251 | ||
1252 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1253 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1254 | (match_operand:P 1 "larl_operand" "") | |
1255 | (match_operand:P 2 "register_operand" "=a")])] | |
1256 | "TARGET_Z10" | |
1257 | { | |
1258 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1259 | DONE; | |
1260 | }) | |
1261 | ||
833cd70a AK |
1262 | ; Handles loading a PLUS (load address) expression |
1263 | ||
1264 | (define_expand "reload<mode>_plus" | |
1265 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1266 | (match_operand:P 1 "s390_plus_operand" "") | |
1267 | (match_operand:P 2 "register_operand" "=&a")])] | |
1268 | "" | |
1269 | { | |
1270 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1271 | DONE; | |
1272 | }) | |
1273 | ||
1274 | ; Handles assessing a non-offsetable memory address | |
1275 | ||
1276 | (define_expand "reload<mode>_nonoffmem_in" | |
1277 | [(parallel [(match_operand 0 "register_operand" "") | |
1278 | (match_operand 1 "" "") | |
1279 | (match_operand:P 2 "register_operand" "=&a")])] | |
1280 | "" | |
1281 | { | |
1282 | gcc_assert (MEM_P (operands[1])); | |
1283 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1284 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1285 | emit_move_insn (operands[0], operands[1]); | |
1286 | DONE; | |
1287 | }) | |
1288 | ||
1289 | (define_expand "reload<mode>_nonoffmem_out" | |
1290 | [(parallel [(match_operand 0 "" "") | |
1291 | (match_operand 1 "register_operand" "") | |
1292 | (match_operand:P 2 "register_operand" "=&a")])] | |
1293 | "" | |
dc65c307 | 1294 | { |
9c3c3dcc | 1295 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1296 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1297 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1298 | emit_move_insn (operands[0], operands[1]); | |
1299 | DONE; | |
1300 | }) | |
9db1d521 | 1301 | |
1f9e1fc6 AK |
1302 | (define_expand "reload<mode>_PIC_addr" |
1303 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1304 | (match_operand 1 "larl_operand" "") | |
1305 | (match_operand:P 2 "register_operand" "=a")])] | |
1306 | "" | |
1307 | { | |
0a2aaacc KG |
1308 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1309 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1310 | }) |
1311 | ||
9db1d521 HP |
1312 | ; |
1313 | ; movdi instruction pattern(s). | |
1314 | ; | |
1315 | ||
9db1d521 HP |
1316 | (define_expand "movdi" |
1317 | [(set (match_operand:DI 0 "general_operand" "") | |
1318 | (match_operand:DI 1 "general_operand" ""))] | |
1319 | "" | |
9db1d521 | 1320 | { |
fd3cd001 | 1321 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1322 | if (TARGET_64BIT |
1323 | && (SYMBOLIC_CONST (operands[1]) | |
1324 | || (GET_CODE (operands[1]) == PLUS | |
1325 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1326 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1327 | emit_symbolic_move (operands); |
10bbf137 | 1328 | }) |
9db1d521 | 1329 | |
4023fb28 UW |
1330 | (define_insn "*movdi_larl" |
1331 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1332 | (match_operand:DI 1 "larl_operand" "X"))] | |
1333 | "TARGET_64BIT | |
8e509cf9 | 1334 | && !FP_REG_P (operands[0])" |
d40c829f | 1335 | "larl\t%0,%1" |
4023fb28 | 1336 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1337 | (set_attr "type" "larl") |
1338 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1339 | |
3af8e996 | 1340 | (define_insn "*movdi_64" |
85dae55a | 1341 | [(set (match_operand:DI 0 "nonimmediate_operand" |
963fc8d0 | 1342 | "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, |
f2dc2f86 | 1343 | RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") |
85dae55a | 1344 | (match_operand:DI 1 "general_operand" |
963fc8d0 | 1345 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, |
f2dc2f86 | 1346 | d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] |
9602b6a1 | 1347 | "TARGET_ZARCH" |
85dae55a AK |
1348 | "@ |
1349 | lghi\t%0,%h1 | |
1350 | llihh\t%0,%i1 | |
1351 | llihl\t%0,%i1 | |
1352 | llilh\t%0,%i1 | |
1353 | llill\t%0,%i1 | |
1354 | lgfi\t%0,%1 | |
1355 | llihf\t%0,%k1 | |
1356 | llilf\t%0,%k1 | |
1357 | ldgr\t%0,%1 | |
1358 | lgdr\t%0,%1 | |
1359 | lay\t%0,%a1 | |
963fc8d0 | 1360 | lgrl\t%0,%1 |
85dae55a AK |
1361 | lgr\t%0,%1 |
1362 | lg\t%0,%1 | |
1363 | stg\t%1,%0 | |
1364 | ldr\t%0,%1 | |
1365 | ld\t%0,%1 | |
1366 | ldy\t%0,%1 | |
1367 | std\t%1,%0 | |
1368 | stdy\t%1,%0 | |
963fc8d0 AK |
1369 | stgrl\t%1,%0 |
1370 | mvghi\t%0,%1 | |
85dae55a AK |
1371 | # |
1372 | # | |
1373 | stam\t%1,%N1,%S0 | |
f2dc2f86 | 1374 | lam\t%0,%N0,%S1" |
963fc8d0 | 1375 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
f2dc2f86 | 1376 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS") |
963fc8d0 AK |
1377 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
1378 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, | |
f2dc2f86 | 1379 | *,*") |
3af8e996 | 1380 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1381 | z10,*,*,*,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1382 | z10,z10,*,*,*,*") |
9381e3f1 WG |
1383 | (set_attr "z10prop" "z10_fwd_A1, |
1384 | z10_fwd_E1, | |
1385 | z10_fwd_E1, | |
1386 | z10_fwd_E1, | |
1387 | z10_fwd_E1, | |
1388 | z10_fwd_A1, | |
1389 | z10_fwd_E1, | |
1390 | z10_fwd_E1, | |
1391 | *, | |
1392 | *, | |
1393 | z10_fwd_A1, | |
1394 | z10_fwd_A3, | |
1395 | z10_fr_E1, | |
1396 | z10_fwd_A3, | |
1397 | z10_rec, | |
1398 | *, | |
1399 | *, | |
1400 | *, | |
1401 | *, | |
1402 | *, | |
1403 | z10_rec, | |
1404 | z10_super, | |
1405 | *, | |
1406 | *, | |
1407 | *, | |
9381e3f1 WG |
1408 | *") |
1409 | ]) | |
c5aa1d12 UW |
1410 | |
1411 | (define_split | |
1412 | [(set (match_operand:DI 0 "register_operand" "") | |
1413 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1414 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1415 | [(set (match_dup 2) (match_dup 3)) |
1416 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1417 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1418 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1419 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1420 | ||
1421 | (define_split | |
1422 | [(set (match_operand:DI 0 "register_operand" "") | |
1423 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1424 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1425 | && dead_or_set_p (insn, operands[1])" |
1426 | [(set (match_dup 3) (match_dup 2)) | |
1427 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1428 | (set (match_dup 4) (match_dup 2))] | |
1429 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1430 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1431 | ||
1432 | (define_split | |
1433 | [(set (match_operand:DI 0 "register_operand" "") | |
1434 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1435 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1436 | && !dead_or_set_p (insn, operands[1])" |
1437 | [(set (match_dup 3) (match_dup 2)) | |
1438 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1439 | (set (match_dup 4) (match_dup 2)) | |
1440 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1441 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1442 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1443 | |
1444 | (define_insn "*movdi_31" | |
963fc8d0 | 1445 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1446 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1447 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1448 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1449 | "!TARGET_ZARCH" |
4023fb28 | 1450 | "@ |
fc0ea003 | 1451 | lm\t%0,%N0,%S1 |
c4d50129 | 1452 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1453 | stm\t%1,%N1,%S0 |
c4d50129 | 1454 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1455 | # |
1456 | # | |
d40c829f UW |
1457 | ldr\t%0,%1 |
1458 | ld\t%0,%1 | |
1459 | ldy\t%0,%1 | |
1460 | std\t%1,%0 | |
1461 | stdy\t%1,%0 | |
19b63d8e | 1462 | #" |
f2dc2f86 AK |
1463 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1464 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1465 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1466 | |
1467 | ; For a load from a symbol ref we can use one of the target registers | |
1468 | ; together with larl to load the address. | |
1469 | (define_split | |
1470 | [(set (match_operand:DI 0 "register_operand" "") | |
1471 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1472 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1473 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1474 | [(set (match_dup 2) (match_dup 3)) | |
1475 | (set (match_dup 0) (match_dup 1))] | |
1476 | { | |
1477 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1478 | operands[3] = XEXP (operands[1], 0); | |
1479 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1480 | }) | |
4023fb28 UW |
1481 | |
1482 | (define_split | |
1483 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1484 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1485 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1486 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1487 | [(set (match_dup 2) (match_dup 4)) |
1488 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1489 | { |
dc65c307 UW |
1490 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1491 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1492 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1493 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1494 | }) | |
1495 | ||
1496 | (define_split | |
1497 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1498 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1499 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1500 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1501 | [(set (match_dup 2) (match_dup 4)) | |
1502 | (set (match_dup 3) (match_dup 5))] | |
1503 | { | |
1504 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1505 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1506 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1507 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1508 | }) | |
9db1d521 | 1509 | |
4023fb28 UW |
1510 | (define_split |
1511 | [(set (match_operand:DI 0 "register_operand" "") | |
1512 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1513 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1514 | && !FP_REG_P (operands[0]) |
4023fb28 | 1515 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1516 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1517 | { |
1518 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1519 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1520 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1521 | }) |
1522 | ||
84817c5d UW |
1523 | (define_peephole2 |
1524 | [(set (match_operand:DI 0 "register_operand" "") | |
1525 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1526 | "TARGET_ZARCH |
84817c5d UW |
1527 | && !FP_REG_P (operands[0]) |
1528 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1529 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1530 | && get_pool_mode (operands[1]) == DImode | |
1531 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1532 | [(set (match_dup 0) (match_dup 2))] | |
1533 | "operands[2] = get_pool_constant (operands[1]);") | |
1534 | ||
7bdff56f UW |
1535 | (define_insn "*la_64" |
1536 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1537 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1538 | "TARGET_64BIT" |
1539 | "@ | |
1540 | la\t%0,%a1 | |
1541 | lay\t%0,%a1" | |
1542 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1543 | (set_attr "type" "la") |
1544 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1545 | |
1546 | (define_peephole2 | |
1547 | [(parallel | |
1548 | [(set (match_operand:DI 0 "register_operand" "") | |
1549 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1550 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1551 | "TARGET_64BIT |
e1d5ee28 | 1552 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1553 | [(set (match_dup 0) (match_dup 1))] |
1554 | "") | |
1555 | ||
1556 | (define_peephole2 | |
1557 | [(set (match_operand:DI 0 "register_operand" "") | |
1558 | (match_operand:DI 1 "register_operand" "")) | |
1559 | (parallel | |
1560 | [(set (match_dup 0) | |
1561 | (plus:DI (match_dup 0) | |
1562 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1563 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1564 | "TARGET_64BIT |
1565 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1566 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1567 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1568 | "") | |
1569 | ||
9db1d521 HP |
1570 | ; |
1571 | ; movsi instruction pattern(s). | |
1572 | ; | |
1573 | ||
9db1d521 HP |
1574 | (define_expand "movsi" |
1575 | [(set (match_operand:SI 0 "general_operand" "") | |
1576 | (match_operand:SI 1 "general_operand" ""))] | |
1577 | "" | |
9db1d521 | 1578 | { |
fd3cd001 | 1579 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1580 | if (!TARGET_64BIT |
1581 | && (SYMBOLIC_CONST (operands[1]) | |
1582 | || (GET_CODE (operands[1]) == PLUS | |
1583 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1584 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1585 | emit_symbolic_move (operands); |
10bbf137 | 1586 | }) |
9db1d521 | 1587 | |
9e8327e3 UW |
1588 | (define_insn "*movsi_larl" |
1589 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1590 | (match_operand:SI 1 "larl_operand" "X"))] | |
1591 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1592 | && !FP_REG_P (operands[0])" | |
1593 | "larl\t%0,%1" | |
1594 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1595 | (set_attr "type" "larl") |
729e750f | 1596 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1597 | |
f19a9af7 | 1598 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1599 | [(set (match_operand:SI 0 "nonimmediate_operand" |
f2dc2f86 | 1600 | "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t") |
2f7e5a0d | 1601 | (match_operand:SI 1 "general_operand" |
f2dc2f86 | 1602 | "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))] |
f19a9af7 | 1603 | "TARGET_ZARCH" |
9db1d521 | 1604 | "@ |
f19a9af7 AK |
1605 | lhi\t%0,%h1 |
1606 | llilh\t%0,%i1 | |
1607 | llill\t%0,%i1 | |
ec24698e | 1608 | iilf\t%0,%o1 |
f19a9af7 | 1609 | lay\t%0,%a1 |
963fc8d0 | 1610 | lrl\t%0,%1 |
d40c829f UW |
1611 | lr\t%0,%1 |
1612 | l\t%0,%1 | |
1613 | ly\t%0,%1 | |
1614 | st\t%1,%0 | |
1615 | sty\t%1,%0 | |
1616 | ler\t%0,%1 | |
1617 | le\t%0,%1 | |
1618 | ley\t%0,%1 | |
1619 | ste\t%1,%0 | |
1620 | stey\t%1,%0 | |
c5aa1d12 UW |
1621 | ear\t%0,%1 |
1622 | sar\t%0,%1 | |
1623 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1624 | strl\t%1,%0 |
1625 | mvhi\t%0,%1 | |
f2dc2f86 | 1626 | lam\t%0,%0,%S1" |
963fc8d0 | 1627 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
f2dc2f86 | 1628 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS") |
9381e3f1 WG |
1629 | (set_attr "type" "*, |
1630 | *, | |
1631 | *, | |
1632 | *, | |
1633 | la, | |
1634 | larl, | |
1635 | lr, | |
1636 | load, | |
1637 | load, | |
1638 | store, | |
1639 | store, | |
1640 | floadsf, | |
1641 | floadsf, | |
1642 | floadsf, | |
1643 | fstoresf, | |
1644 | fstoresf, | |
1645 | *, | |
1646 | *, | |
1647 | *, | |
1648 | larl, | |
1649 | *, | |
9381e3f1 | 1650 | *") |
963fc8d0 | 1651 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1652 | *,*,longdisp,*,longdisp,*,*,*,z10,z10,*") |
9381e3f1 WG |
1653 | (set_attr "z10prop" "z10_fwd_A1, |
1654 | z10_fwd_E1, | |
1655 | z10_fwd_E1, | |
1656 | z10_fwd_A1, | |
1657 | z10_fwd_A1, | |
1658 | z10_fwd_A3, | |
1659 | z10_fr_E1, | |
1660 | z10_fwd_A3, | |
1661 | z10_fwd_A3, | |
729e750f | 1662 | z10_rec, |
9381e3f1 WG |
1663 | z10_rec, |
1664 | *, | |
1665 | *, | |
1666 | *, | |
1667 | *, | |
1668 | *, | |
1669 | z10_super_E1, | |
1670 | z10_super, | |
1671 | *, | |
1672 | z10_rec, | |
1673 | z10_super, | |
9381e3f1 | 1674 | *")]) |
f19a9af7 AK |
1675 | |
1676 | (define_insn "*movsi_esa" | |
f2dc2f86 AK |
1677 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t") |
1678 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1679 | "!TARGET_ZARCH" |
1680 | "@ | |
1681 | lhi\t%0,%h1 | |
1682 | lr\t%0,%1 | |
1683 | l\t%0,%1 | |
1684 | st\t%1,%0 | |
1685 | ler\t%0,%1 | |
1686 | le\t%0,%1 | |
1687 | ste\t%1,%0 | |
c5aa1d12 UW |
1688 | ear\t%0,%1 |
1689 | sar\t%0,%1 | |
1690 | stam\t%1,%1,%S0 | |
f2dc2f86 AK |
1691 | lam\t%0,%0,%S1" |
1692 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS") | |
1693 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*") | |
9381e3f1 WG |
1694 | (set_attr "z10prop" "z10_fwd_A1, |
1695 | z10_fr_E1, | |
1696 | z10_fwd_A3, | |
729e750f | 1697 | z10_rec, |
9381e3f1 WG |
1698 | *, |
1699 | *, | |
1700 | *, | |
1701 | z10_super_E1, | |
1702 | z10_super, | |
1703 | *, | |
9381e3f1 WG |
1704 | *") |
1705 | ]) | |
9db1d521 | 1706 | |
84817c5d UW |
1707 | (define_peephole2 |
1708 | [(set (match_operand:SI 0 "register_operand" "") | |
1709 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1710 | "!FP_REG_P (operands[0]) | |
1711 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1712 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1713 | && get_pool_mode (operands[1]) == SImode | |
1714 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1715 | [(set (match_dup 0) (match_dup 2))] | |
1716 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1717 | |
7bdff56f UW |
1718 | (define_insn "*la_31" |
1719 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1720 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1721 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1722 | "@ | |
1723 | la\t%0,%a1 | |
1724 | lay\t%0,%a1" | |
1725 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1726 | (set_attr "type" "la") |
1727 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1728 | |
1729 | (define_peephole2 | |
1730 | [(parallel | |
1731 | [(set (match_operand:SI 0 "register_operand" "") | |
1732 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1733 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1734 | "!TARGET_64BIT |
e1d5ee28 | 1735 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1736 | [(set (match_dup 0) (match_dup 1))] |
1737 | "") | |
1738 | ||
1739 | (define_peephole2 | |
1740 | [(set (match_operand:SI 0 "register_operand" "") | |
1741 | (match_operand:SI 1 "register_operand" "")) | |
1742 | (parallel | |
1743 | [(set (match_dup 0) | |
1744 | (plus:SI (match_dup 0) | |
1745 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1746 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1747 | "!TARGET_64BIT |
1748 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1749 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1750 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1751 | "") | |
1752 | ||
1753 | (define_insn "*la_31_and" | |
1754 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1755 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
1756 | (const_int 2147483647)))] |
1757 | "!TARGET_64BIT" | |
1758 | "@ | |
1759 | la\t%0,%a1 | |
1760 | lay\t%0,%a1" | |
1761 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1762 | (set_attr "type" "la") |
1763 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1764 | |
1765 | (define_insn_and_split "*la_31_and_cc" | |
1766 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1767 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1768 | (const_int 2147483647))) | |
ae156f85 | 1769 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1770 | "!TARGET_64BIT" |
1771 | "#" | |
1772 | "&& reload_completed" | |
1773 | [(set (match_dup 0) | |
1774 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1775 | "" | |
1776 | [(set_attr "op_type" "RX") | |
1777 | (set_attr "type" "la")]) | |
1778 | ||
1779 | (define_insn "force_la_31" | |
1780 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1781 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
1782 | (use (const_int 0))] |
1783 | "!TARGET_64BIT" | |
1784 | "@ | |
1785 | la\t%0,%a1 | |
1786 | lay\t%0,%a1" | |
1787 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
1788 | (set_attr "type" "la") |
1789 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 1790 | |
9db1d521 HP |
1791 | ; |
1792 | ; movhi instruction pattern(s). | |
1793 | ; | |
1794 | ||
02ed3c5e UW |
1795 | (define_expand "movhi" |
1796 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1797 | (match_operand:HI 1 "general_operand" ""))] | |
1798 | "" | |
1799 | { | |
2f7e5a0d | 1800 | /* Make it explicit that loading a register from memory |
02ed3c5e | 1801 | always sign-extends (at least) to SImode. */ |
b3a13419 | 1802 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 1803 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1804 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1805 | { |
1806 | rtx tmp = gen_reg_rtx (SImode); | |
1807 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1808 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1809 | operands[1] = gen_lowpart (HImode, tmp); | |
1810 | } | |
1811 | }) | |
1812 | ||
1813 | (define_insn "*movhi" | |
f2dc2f86 AK |
1814 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q") |
1815 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))] | |
9db1d521 HP |
1816 | "" |
1817 | "@ | |
d40c829f UW |
1818 | lr\t%0,%1 |
1819 | lhi\t%0,%h1 | |
1820 | lh\t%0,%1 | |
1821 | lhy\t%0,%1 | |
963fc8d0 | 1822 | lhrl\t%0,%1 |
d40c829f UW |
1823 | sth\t%1,%0 |
1824 | sthy\t%1,%0 | |
963fc8d0 | 1825 | sthrl\t%1,%0 |
f2dc2f86 AK |
1826 | mvhhi\t%0,%1" |
1827 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL") | |
1828 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*") | |
1829 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10") | |
9381e3f1 WG |
1830 | (set_attr "z10prop" "z10_fr_E1, |
1831 | z10_fwd_A1, | |
1832 | z10_super_E1, | |
1833 | z10_super_E1, | |
1834 | z10_super_E1, | |
729e750f | 1835 | z10_rec, |
9381e3f1 WG |
1836 | z10_rec, |
1837 | z10_rec, | |
f2dc2f86 | 1838 | z10_super")]) |
9db1d521 | 1839 | |
84817c5d UW |
1840 | (define_peephole2 |
1841 | [(set (match_operand:HI 0 "register_operand" "") | |
1842 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1843 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1844 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1845 | && get_pool_mode (operands[1]) == HImode | |
1846 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1847 | [(set (match_dup 0) (match_dup 2))] | |
1848 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1849 | |
9db1d521 HP |
1850 | ; |
1851 | ; movqi instruction pattern(s). | |
1852 | ; | |
1853 | ||
02ed3c5e UW |
1854 | (define_expand "movqi" |
1855 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1856 | (match_operand:QI 1 "general_operand" ""))] | |
1857 | "" | |
1858 | { | |
c19ec8f9 | 1859 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1860 | is just as fast as a QImode load. */ |
b3a13419 | 1861 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 1862 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1863 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1864 | { |
9602b6a1 AK |
1865 | rtx tmp = gen_reg_rtx (DImode); |
1866 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
02ed3c5e UW |
1867 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1868 | operands[1] = gen_lowpart (QImode, tmp); | |
1869 | } | |
1870 | }) | |
4023fb28 | 1871 | |
02ed3c5e | 1872 | (define_insn "*movqi" |
0a88561f AK |
1873 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1874 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1875 | "" |
1876 | "@ | |
d40c829f UW |
1877 | lr\t%0,%1 |
1878 | lhi\t%0,%b1 | |
1879 | ic\t%0,%1 | |
1880 | icy\t%0,%1 | |
1881 | stc\t%1,%0 | |
1882 | stcy\t%1,%0 | |
fc0ea003 | 1883 | mvi\t%S0,%b1 |
0a88561f | 1884 | mviy\t%S0,%b1 |
b247e88a | 1885 | #" |
0a88561f AK |
1886 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1887 | (set_attr "type" "lr,*,*,*,store,store,store,store,*") | |
9381e3f1 WG |
1888 | (set_attr "z10prop" "z10_fr_E1, |
1889 | z10_fwd_A1, | |
1890 | z10_super_E1, | |
1891 | z10_super_E1, | |
729e750f | 1892 | z10_rec, |
9381e3f1 WG |
1893 | z10_rec, |
1894 | z10_super, | |
0a88561f AK |
1895 | z10_super, |
1896 | *")]) | |
9db1d521 | 1897 | |
84817c5d UW |
1898 | (define_peephole2 |
1899 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1900 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1901 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1902 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1903 | && get_pool_mode (operands[1]) == QImode | |
1904 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1905 | [(set (match_dup 0) (match_dup 2))] | |
1906 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1907 | |
9db1d521 | 1908 | ; |
05b9aaaa | 1909 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1910 | ; |
1911 | ||
1912 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1913 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1914 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1915 | "" |
d3632d41 | 1916 | "@ |
d40c829f UW |
1917 | ic\t%0,%1 |
1918 | icy\t%0,%1" | |
9381e3f1 | 1919 | [(set_attr "op_type" "RX,RXY") |
729e750f | 1920 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
1921 | |
1922 | ; | |
1923 | ; movstricthi instruction pattern(s). | |
1924 | ; | |
1925 | ||
1926 | (define_insn "*movstricthi" | |
d3632d41 | 1927 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1928 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1929 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1930 | "" |
d3632d41 | 1931 | "@ |
fc0ea003 UW |
1932 | icm\t%0,3,%S1 |
1933 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
1934 | [(set_attr "op_type" "RS,RSY") |
1935 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
1936 | |
1937 | ; | |
1938 | ; movstrictsi instruction pattern(s). | |
1939 | ; | |
1940 | ||
05b9aaaa | 1941 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1942 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1943 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 1944 | "TARGET_ZARCH" |
9db1d521 | 1945 | "@ |
d40c829f UW |
1946 | lr\t%0,%1 |
1947 | l\t%0,%1 | |
c5aa1d12 UW |
1948 | ly\t%0,%1 |
1949 | ear\t%0,%1" | |
1950 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
1951 | (set_attr "type" "lr,load,load,*") |
1952 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 1953 | |
f61a2c7d | 1954 | ; |
609e7e80 | 1955 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
1956 | ; |
1957 | ||
609e7e80 AK |
1958 | (define_expand "mov<mode>" |
1959 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
1960 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
1961 | "" |
1962 | "") | |
1963 | ||
609e7e80 | 1964 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
1965 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
1966 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 1967 | "TARGET_ZARCH" |
f61a2c7d | 1968 | "@ |
65b1d8ea | 1969 | lzxr\t%0 |
f61a2c7d AK |
1970 | lxr\t%0,%1 |
1971 | # | |
1972 | # | |
1973 | lmg\t%0,%N0,%S1 | |
1974 | stmg\t%1,%N1,%S0 | |
1975 | # | |
f61a2c7d | 1976 | #" |
65b1d8ea AK |
1977 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
1978 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
1979 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 1980 | |
609e7e80 | 1981 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
1982 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
1983 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 1984 | "!TARGET_ZARCH" |
f61a2c7d | 1985 | "@ |
65b1d8ea | 1986 | lzxr\t%0 |
f61a2c7d AK |
1987 | lxr\t%0,%1 |
1988 | # | |
f61a2c7d | 1989 | #" |
65b1d8ea AK |
1990 | [(set_attr "op_type" "RRE,RRE,*,*") |
1991 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
1992 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
1993 | |
1994 | ; TFmode in GPRs splitters | |
1995 | ||
1996 | (define_split | |
609e7e80 AK |
1997 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
1998 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 1999 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2000 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2001 | [(set (match_dup 2) (match_dup 4)) |
2002 | (set (match_dup 3) (match_dup 5))] | |
2003 | { | |
609e7e80 AK |
2004 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2005 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2006 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2007 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2008 | }) |
2009 | ||
2010 | (define_split | |
609e7e80 AK |
2011 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2012 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2013 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2014 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2015 | [(set (match_dup 2) (match_dup 4)) |
2016 | (set (match_dup 3) (match_dup 5))] | |
2017 | { | |
609e7e80 AK |
2018 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2019 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2020 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2021 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2022 | }) |
2023 | ||
2024 | (define_split | |
609e7e80 AK |
2025 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2026 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2027 | "TARGET_ZARCH && reload_completed |
f61a2c7d AK |
2028 | && !FP_REG_P (operands[0]) |
2029 | && !s_operand (operands[1], VOIDmode)" | |
2030 | [(set (match_dup 0) (match_dup 1))] | |
2031 | { | |
609e7e80 | 2032 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2033 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2034 | s390_load_address (addr, XEXP (operands[1], 0)); |
2035 | operands[1] = replace_equiv_address (operands[1], addr); | |
2036 | }) | |
2037 | ||
7b6baae1 | 2038 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2039 | |
2040 | (define_split | |
609e7e80 AK |
2041 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2042 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2043 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2044 | && FP_REG_P (operands[0])" |
2045 | [(set (match_dup 2) (match_dup 4)) | |
2046 | (set (match_dup 3) (match_dup 5))] | |
2047 | { | |
609e7e80 AK |
2048 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2049 | <MODE>mode, 0); | |
2050 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2051 | <MODE>mode, 8); | |
2052 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2053 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2054 | }) |
2055 | ||
2056 | (define_split | |
609e7e80 AK |
2057 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2058 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2059 | "reload_completed && offsettable_memref_p (operands[0]) |
2060 | && FP_REG_P (operands[1])" | |
2061 | [(set (match_dup 2) (match_dup 4)) | |
2062 | (set (match_dup 3) (match_dup 5))] | |
2063 | { | |
609e7e80 AK |
2064 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2065 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2066 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2067 | <MODE>mode, 0); | |
2068 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2069 | <MODE>mode, 8); | |
f61a2c7d AK |
2070 | }) |
2071 | ||
9db1d521 | 2072 | ; |
609e7e80 | 2073 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2074 | ; |
2075 | ||
609e7e80 AK |
2076 | (define_expand "mov<mode>" |
2077 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2078 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2079 | "" |
13c025c1 | 2080 | "") |
9db1d521 | 2081 | |
609e7e80 AK |
2082 | (define_insn "*mov<mode>_64dfp" |
2083 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2084 | "=f,f,f,d,f,f,R,T,d,d, d,RT") |
609e7e80 | 2085 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2086 | " G,f,d,f,R,T,f,f,G,d,RT, d"))] |
9602b6a1 | 2087 | "TARGET_DFP" |
85dae55a | 2088 | "@ |
65b1d8ea | 2089 | lzdr\t%0 |
85dae55a AK |
2090 | ldr\t%0,%1 |
2091 | ldgr\t%0,%1 | |
2092 | lgdr\t%0,%1 | |
2093 | ld\t%0,%1 | |
2094 | ldy\t%0,%1 | |
2095 | std\t%1,%0 | |
2096 | stdy\t%1,%0 | |
45e5214c | 2097 | lghi\t%0,0 |
85dae55a AK |
2098 | lgr\t%0,%1 |
2099 | lg\t%0,%1 | |
f2dc2f86 | 2100 | stg\t%1,%0" |
65b1d8ea AK |
2101 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2102 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, | |
45e5214c | 2103 | fstoredf,fstoredf,*,lr,load,store") |
65b1d8ea AK |
2104 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") |
2105 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
85dae55a | 2106 | |
609e7e80 | 2107 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2108 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT") |
2109 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))] | |
9602b6a1 | 2110 | "TARGET_ZARCH" |
9db1d521 | 2111 | "@ |
65b1d8ea | 2112 | lzdr\t%0 |
d40c829f UW |
2113 | ldr\t%0,%1 |
2114 | ld\t%0,%1 | |
2115 | ldy\t%0,%1 | |
2116 | std\t%1,%0 | |
2117 | stdy\t%1,%0 | |
45e5214c | 2118 | lghi\t%0,0 |
d40c829f UW |
2119 | lgr\t%0,%1 |
2120 | lg\t%0,%1 | |
f2dc2f86 | 2121 | stg\t%1,%0" |
65b1d8ea AK |
2122 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2123 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2124 | fstore<mode>,fstore<mode>,*,lr,load,store") | |
2125 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") | |
2126 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")]) | |
609e7e80 AK |
2127 | |
2128 | (define_insn "*mov<mode>_31" | |
2129 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2130 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2131 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2132 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2133 | "!TARGET_ZARCH" |
9db1d521 | 2134 | "@ |
65b1d8ea | 2135 | lzdr\t%0 |
d40c829f UW |
2136 | ldr\t%0,%1 |
2137 | ld\t%0,%1 | |
2138 | ldy\t%0,%1 | |
2139 | std\t%1,%0 | |
2140 | stdy\t%1,%0 | |
fc0ea003 | 2141 | lm\t%0,%N0,%S1 |
c4d50129 | 2142 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2143 | stm\t%1,%N1,%S0 |
c4d50129 | 2144 | stmy\t%1,%N1,%S0 |
4023fb28 | 2145 | # |
19b63d8e | 2146 | #" |
65b1d8ea AK |
2147 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2148 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2149 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2150 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2151 | |
2152 | (define_split | |
609e7e80 AK |
2153 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2154 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2155 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2156 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2157 | [(set (match_dup 2) (match_dup 4)) |
2158 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2159 | { |
609e7e80 AK |
2160 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2161 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2162 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2163 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2164 | }) |
2165 | ||
2166 | (define_split | |
609e7e80 AK |
2167 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2168 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2169 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2170 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2171 | [(set (match_dup 2) (match_dup 4)) |
2172 | (set (match_dup 3) (match_dup 5))] | |
2173 | { | |
609e7e80 AK |
2174 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2175 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2176 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2177 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2178 | }) |
9db1d521 | 2179 | |
4023fb28 | 2180 | (define_split |
609e7e80 AK |
2181 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2182 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2183 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2184 | && !FP_REG_P (operands[0]) |
4023fb28 | 2185 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2186 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2187 | { |
609e7e80 | 2188 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2189 | s390_load_address (addr, XEXP (operands[1], 0)); |
2190 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2191 | }) |
2192 | ||
9db1d521 | 2193 | ; |
609e7e80 | 2194 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2195 | ; |
2196 | ||
609e7e80 AK |
2197 | (define_insn "mov<mode>" |
2198 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
65b1d8ea | 2199 | "=f,f,f,f,R,T,d,d,d,d,R,T") |
609e7e80 | 2200 | (match_operand:SD_SF 1 "general_operand" |
65b1d8ea | 2201 | " G,f,R,T,f,f,G,d,R,T,d,d"))] |
4023fb28 | 2202 | "" |
9db1d521 | 2203 | "@ |
65b1d8ea | 2204 | lzer\t%0 |
d40c829f UW |
2205 | ler\t%0,%1 |
2206 | le\t%0,%1 | |
2207 | ley\t%0,%1 | |
2208 | ste\t%1,%0 | |
2209 | stey\t%1,%0 | |
45e5214c | 2210 | lhi\t%0,0 |
d40c829f UW |
2211 | lr\t%0,%1 |
2212 | l\t%0,%1 | |
2213 | ly\t%0,%1 | |
2214 | st\t%1,%0 | |
f2dc2f86 | 2215 | sty\t%1,%0" |
65b1d8ea AK |
2216 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY") |
2217 | (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>, | |
2218 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") | |
2219 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2220 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2221 | |
9dc62c00 AK |
2222 | ; |
2223 | ; movcc instruction pattern | |
2224 | ; | |
2225 | ||
2226 | (define_insn "movcc" | |
2227 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
2228 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
2229 | "" | |
2230 | "@ | |
2231 | lr\t%0,%1 | |
2232 | tmh\t%1,12288 | |
2233 | ipm\t%0 | |
2234 | st\t%0,%1 | |
2235 | sty\t%0,%1 | |
2236 | l\t%1,%0 | |
2237 | ly\t%1,%0" | |
8dd3b235 | 2238 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
9381e3f1 | 2239 | (set_attr "type" "lr,*,*,store,store,load,load") |
65b1d8ea AK |
2240 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3") |
2241 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) | |
9dc62c00 | 2242 | |
19b63d8e UW |
2243 | ; |
2244 | ; Block move (MVC) patterns. | |
2245 | ; | |
2246 | ||
2247 | (define_insn "*mvc" | |
2248 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2249 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2250 | (use (match_operand 2 "const_int_operand" "n"))] | |
2251 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2252 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2253 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2254 | |
0a88561f AK |
2255 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2256 | ; order to have it implemented with mvc. | |
2257 | ||
2258 | (define_split | |
2259 | [(set (match_operand:QI 0 "memory_operand" "") | |
2260 | (match_operand:QI 1 "memory_operand" ""))] | |
2261 | "reload_completed" | |
2262 | [(parallel | |
2263 | [(set (match_dup 0) (match_dup 1)) | |
2264 | (use (const_int 1))])] | |
2265 | { | |
2266 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2267 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2268 | }) | |
2269 | ||
2270 | ||
19b63d8e UW |
2271 | (define_peephole2 |
2272 | [(parallel | |
2273 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2274 | (match_operand:BLK 1 "memory_operand" "")) | |
2275 | (use (match_operand 2 "const_int_operand" ""))]) | |
2276 | (parallel | |
2277 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2278 | (match_operand:BLK 4 "memory_operand" "")) | |
2279 | (use (match_operand 5 "const_int_operand" ""))])] | |
2280 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2281 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2282 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2283 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2284 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2285 | [(parallel | |
2286 | [(set (match_dup 6) (match_dup 7)) | |
2287 | (use (match_dup 8))])] | |
2288 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2289 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2290 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2291 | ||
2292 | ||
9db1d521 HP |
2293 | ; |
2294 | ; load_multiple pattern(s). | |
2295 | ; | |
22ea6b4f UW |
2296 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2297 | ; we currently support load_multiple/store_multiple only after reload. | |
2298 | ; | |
9db1d521 HP |
2299 | |
2300 | (define_expand "load_multiple" | |
2301 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2302 | (match_operand 1 "" "")) | |
2303 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2304 | "reload_completed" |
9db1d521 | 2305 | { |
c19ec8f9 | 2306 | enum machine_mode mode; |
9db1d521 HP |
2307 | int regno; |
2308 | int count; | |
2309 | rtx from; | |
4023fb28 | 2310 | int i, off; |
9db1d521 HP |
2311 | |
2312 | /* Support only loading a constant number of fixed-point registers from | |
2313 | memory and only bother with this if more than two */ | |
2314 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2315 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2316 | || INTVAL (operands[2]) > 16 |
2317 | || GET_CODE (operands[1]) != MEM | |
2318 | || GET_CODE (operands[0]) != REG | |
2319 | || REGNO (operands[0]) >= 16) | |
2320 | FAIL; | |
2321 | ||
2322 | count = INTVAL (operands[2]); | |
2323 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2324 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2325 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2326 | FAIL; |
9db1d521 HP |
2327 | |
2328 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2329 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2330 | { |
2331 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2332 | { | |
2333 | from = XEXP (operands[1], 0); | |
2334 | off = 0; | |
2335 | } | |
2336 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2337 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2338 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2339 | { | |
2340 | from = XEXP (XEXP (operands[1], 0), 0); | |
2341 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2342 | } | |
2343 | else | |
2344 | FAIL; | |
4023fb28 UW |
2345 | } |
2346 | else | |
2347 | { | |
2348 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2349 | off = 0; | |
2350 | } | |
9db1d521 HP |
2351 | |
2352 | for (i = 0; i < count; i++) | |
2353 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
2354 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
2355 | change_address (operands[1], mode, | |
0a81f074 RS |
2356 | plus_constant (Pmode, from, |
2357 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2358 | }) |
9db1d521 HP |
2359 | |
2360 | (define_insn "*load_multiple_di" | |
2361 | [(match_parallel 0 "load_multiple_operation" | |
2362 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2363 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2364 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2365 | { |
2366 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2367 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2368 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2369 | } |
d3632d41 | 2370 | [(set_attr "op_type" "RSY") |
4023fb28 | 2371 | (set_attr "type" "lm")]) |
9db1d521 HP |
2372 | |
2373 | (define_insn "*load_multiple_si" | |
2374 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2375 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2376 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2377 | "reload_completed" |
9db1d521 HP |
2378 | { |
2379 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2380 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2381 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2382 | } |
d3632d41 | 2383 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2384 | (set_attr "type" "lm")]) |
9db1d521 HP |
2385 | |
2386 | ; | |
c7453384 | 2387 | ; store multiple pattern(s). |
9db1d521 HP |
2388 | ; |
2389 | ||
2390 | (define_expand "store_multiple" | |
2391 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2392 | (match_operand 1 "" "")) | |
2393 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2394 | "reload_completed" |
9db1d521 | 2395 | { |
c19ec8f9 | 2396 | enum machine_mode mode; |
9db1d521 HP |
2397 | int regno; |
2398 | int count; | |
2399 | rtx to; | |
4023fb28 | 2400 | int i, off; |
9db1d521 HP |
2401 | |
2402 | /* Support only storing a constant number of fixed-point registers to | |
2403 | memory and only bother with this if more than two. */ | |
2404 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2405 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2406 | || INTVAL (operands[2]) > 16 |
2407 | || GET_CODE (operands[0]) != MEM | |
2408 | || GET_CODE (operands[1]) != REG | |
2409 | || REGNO (operands[1]) >= 16) | |
2410 | FAIL; | |
2411 | ||
2412 | count = INTVAL (operands[2]); | |
2413 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2414 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2415 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2416 | FAIL; |
9db1d521 HP |
2417 | |
2418 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2419 | |
b3a13419 | 2420 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2421 | { |
2422 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2423 | { | |
2424 | to = XEXP (operands[0], 0); | |
2425 | off = 0; | |
2426 | } | |
2427 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2428 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2429 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2430 | { | |
2431 | to = XEXP (XEXP (operands[0], 0), 0); | |
2432 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2433 | } | |
2434 | else | |
2435 | FAIL; | |
4023fb28 | 2436 | } |
c7453384 | 2437 | else |
4023fb28 UW |
2438 | { |
2439 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2440 | off = 0; | |
2441 | } | |
9db1d521 HP |
2442 | |
2443 | for (i = 0; i < count; i++) | |
2444 | XVECEXP (operands[3], 0, i) | |
2445 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 | 2446 | change_address (operands[0], mode, |
0a81f074 RS |
2447 | plus_constant (Pmode, to, |
2448 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2449 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2450 | }) |
9db1d521 HP |
2451 | |
2452 | (define_insn "*store_multiple_di" | |
2453 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2454 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2455 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2456 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2457 | { |
2458 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2459 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2460 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2461 | } |
d3632d41 | 2462 | [(set_attr "op_type" "RSY") |
4023fb28 | 2463 | (set_attr "type" "stm")]) |
9db1d521 HP |
2464 | |
2465 | ||
2466 | (define_insn "*store_multiple_si" | |
2467 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2468 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2469 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2470 | "reload_completed" |
9db1d521 HP |
2471 | { |
2472 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2473 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2474 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2475 | } |
d3632d41 | 2476 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2477 | (set_attr "type" "stm")]) |
9db1d521 HP |
2478 | |
2479 | ;; | |
2480 | ;; String instructions. | |
2481 | ;; | |
2482 | ||
963fc8d0 AK |
2483 | (define_insn "*execute_rl" |
2484 | [(match_parallel 0 "" | |
2485 | [(unspec [(match_operand 1 "register_operand" "a") | |
2486 | (match_operand 2 "" "") | |
2487 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2488 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2489 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2490 | "exrl\t%1,%3" | |
2491 | [(set_attr "op_type" "RIL") | |
2492 | (set_attr "type" "cs")]) | |
2493 | ||
9bb86f41 UW |
2494 | (define_insn "*execute" |
2495 | [(match_parallel 0 "" | |
2496 | [(unspec [(match_operand 1 "register_operand" "a") | |
2497 | (match_operand:BLK 2 "memory_operand" "R") | |
2498 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2499 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2500 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2501 | "ex\t%1,%2" | |
29a74354 UW |
2502 | [(set_attr "op_type" "RX") |
2503 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2504 | |
2505 | ||
91d39d71 UW |
2506 | ; |
2507 | ; strlenM instruction pattern(s). | |
2508 | ; | |
2509 | ||
9db2f16d | 2510 | (define_expand "strlen<mode>" |
ccbdc0d4 | 2511 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2512 | (parallel |
91d39d71 | 2513 | [(set (match_dup 4) |
9db2f16d | 2514 | (unspec:P [(const_int 0) |
91d39d71 | 2515 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2516 | (reg:SI 0) |
91d39d71 | 2517 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2518 | (clobber (scratch:P)) |
ae156f85 | 2519 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2520 | (parallel |
9db2f16d AS |
2521 | [(set (match_operand:P 0 "register_operand" "") |
2522 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2523 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2524 | "" |
91d39d71 | 2525 | { |
9db2f16d AS |
2526 | operands[4] = gen_reg_rtx (Pmode); |
2527 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2528 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2529 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2530 | }) | |
2531 | ||
9db2f16d AS |
2532 | (define_insn "*strlen<mode>" |
2533 | [(set (match_operand:P 0 "register_operand" "=a") | |
2534 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2535 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2536 | (reg:SI 0) |
91d39d71 | 2537 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2538 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2539 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2540 | "" |
91d39d71 | 2541 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2542 | [(set_attr "length" "8") |
2543 | (set_attr "type" "vs")]) | |
91d39d71 | 2544 | |
ccbdc0d4 AS |
2545 | ; |
2546 | ; cmpstrM instruction pattern(s). | |
2547 | ; | |
2548 | ||
2549 | (define_expand "cmpstrsi" | |
2550 | [(set (reg:SI 0) (const_int 0)) | |
2551 | (parallel | |
2552 | [(clobber (match_operand 3 "" "")) | |
2553 | (clobber (match_dup 4)) | |
2554 | (set (reg:CCU CC_REGNUM) | |
2555 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2556 | (match_operand:BLK 2 "memory_operand" ""))) | |
2557 | (use (reg:SI 0))]) | |
2558 | (parallel | |
2559 | [(set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 2560 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT)) |
ccbdc0d4 AS |
2561 | (clobber (reg:CC CC_REGNUM))])] |
2562 | "" | |
2563 | { | |
2564 | /* As the result of CMPINT is inverted compared to what we need, | |
2565 | we have to swap the operands. */ | |
2566 | rtx op1 = operands[2]; | |
2567 | rtx op2 = operands[1]; | |
2568 | rtx addr1 = gen_reg_rtx (Pmode); | |
2569 | rtx addr2 = gen_reg_rtx (Pmode); | |
2570 | ||
2571 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2572 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2573 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2574 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2575 | operands[3] = addr1; | |
2576 | operands[4] = addr2; | |
2577 | }) | |
2578 | ||
2579 | (define_insn "*cmpstr<mode>" | |
2580 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2581 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2582 | (set (reg:CCU CC_REGNUM) | |
2583 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2584 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2585 | (use (reg:SI 0))] | |
2586 | "" | |
2587 | "clst\t%0,%1\;jo\t.-4" | |
2588 | [(set_attr "length" "8") | |
2589 | (set_attr "type" "vs")]) | |
9381e3f1 | 2590 | |
742090fc AS |
2591 | ; |
2592 | ; movstr instruction pattern. | |
2593 | ; | |
2594 | ||
2595 | (define_expand "movstr" | |
2596 | [(set (reg:SI 0) (const_int 0)) | |
9381e3f1 | 2597 | (parallel |
742090fc AS |
2598 | [(clobber (match_dup 3)) |
2599 | (set (match_operand:BLK 1 "memory_operand" "") | |
2600 | (match_operand:BLK 2 "memory_operand" "")) | |
2601 | (set (match_operand 0 "register_operand" "") | |
9381e3f1 | 2602 | (unspec [(match_dup 1) |
742090fc AS |
2603 | (match_dup 2) |
2604 | (reg:SI 0)] UNSPEC_MVST)) | |
2605 | (clobber (reg:CC CC_REGNUM))])] | |
2606 | "" | |
2607 | { | |
2608 | rtx addr1 = gen_reg_rtx (Pmode); | |
2609 | rtx addr2 = gen_reg_rtx (Pmode); | |
2610 | ||
2611 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2612 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2613 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2614 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2615 | operands[3] = addr2; | |
2616 | }) | |
2617 | ||
2618 | (define_insn "*movstr" | |
2619 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2620 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2621 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2622 | (set (match_operand:P 0 "register_operand" "=d") | |
9381e3f1 | 2623 | (unspec [(mem:BLK (match_dup 1)) |
742090fc AS |
2624 | (mem:BLK (match_dup 3)) |
2625 | (reg:SI 0)] UNSPEC_MVST)) | |
2626 | (clobber (reg:CC CC_REGNUM))] | |
2627 | "" | |
2628 | "mvst\t%1,%2\;jo\t.-4" | |
2629 | [(set_attr "length" "8") | |
2630 | (set_attr "type" "vs")]) | |
9381e3f1 | 2631 | |
742090fc | 2632 | |
9db1d521 | 2633 | ; |
70128ad9 | 2634 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2635 | ; |
2636 | ||
9db2f16d | 2637 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2638 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2639 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2640 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2641 | (match_operand 3 "" "")] |
2642 | "" | |
70128ad9 | 2643 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2644 | |
ecbe845e UW |
2645 | ; Move a block that is up to 256 bytes in length. |
2646 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2647 | |
70128ad9 | 2648 | (define_expand "movmem_short" |
b9404c99 UW |
2649 | [(parallel |
2650 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2651 | (match_operand:BLK 1 "memory_operand" "")) | |
2652 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2653 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2654 | (clobber (match_dup 3))])] |
2655 | "" | |
2656 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2657 | |
70128ad9 | 2658 | (define_insn "*movmem_short" |
963fc8d0 AK |
2659 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
2660 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2661 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2662 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
2663 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
2664 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 2665 | "#" |
963fc8d0 AK |
2666 | [(set_attr "type" "cs") |
2667 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
ecbe845e | 2668 | |
9bb86f41 UW |
2669 | (define_split |
2670 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2671 | (match_operand:BLK 1 "memory_operand" "")) | |
2672 | (use (match_operand 2 "const_int_operand" "")) | |
2673 | (use (match_operand 3 "immediate_operand" "")) | |
2674 | (clobber (scratch))] | |
2675 | "reload_completed" | |
2676 | [(parallel | |
2677 | [(set (match_dup 0) (match_dup 1)) | |
2678 | (use (match_dup 2))])] | |
2679 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2680 | |
9bb86f41 UW |
2681 | (define_split |
2682 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2683 | (match_operand:BLK 1 "memory_operand" "")) | |
2684 | (use (match_operand 2 "register_operand" "")) | |
2685 | (use (match_operand 3 "memory_operand" "")) | |
2686 | (clobber (scratch))] | |
2687 | "reload_completed" | |
2688 | [(parallel | |
2689 | [(unspec [(match_dup 2) (match_dup 3) | |
2690 | (const_int 0)] UNSPEC_EXECUTE) | |
2691 | (set (match_dup 0) (match_dup 1)) | |
2692 | (use (const_int 1))])] | |
2693 | "") | |
2694 | ||
963fc8d0 AK |
2695 | (define_split |
2696 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2697 | (match_operand:BLK 1 "memory_operand" "")) | |
2698 | (use (match_operand 2 "register_operand" "")) | |
2699 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2700 | (clobber (scratch))] | |
2701 | "TARGET_Z10 && reload_completed" | |
2702 | [(parallel | |
2703 | [(unspec [(match_dup 2) (const_int 0) | |
2704 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2705 | (set (match_dup 0) (match_dup 1)) | |
2706 | (use (const_int 1))])] | |
2707 | "operands[3] = gen_label_rtx ();") | |
2708 | ||
9bb86f41 UW |
2709 | (define_split |
2710 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2711 | (match_operand:BLK 1 "memory_operand" "")) | |
2712 | (use (match_operand 2 "register_operand" "")) | |
2713 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2714 | (clobber (match_operand 3 "register_operand" ""))] | |
2715 | "reload_completed && TARGET_CPU_ZARCH" | |
2716 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2717 | (parallel | |
9381e3f1 | 2718 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
2719 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
2720 | (set (match_dup 0) (match_dup 1)) | |
2721 | (use (const_int 1))])] | |
2722 | "operands[4] = gen_label_rtx ();") | |
2723 | ||
a41c6c53 | 2724 | ; Move a block of arbitrary length. |
9db1d521 | 2725 | |
70128ad9 | 2726 | (define_expand "movmem_long" |
b9404c99 UW |
2727 | [(parallel |
2728 | [(clobber (match_dup 2)) | |
2729 | (clobber (match_dup 3)) | |
2730 | (set (match_operand:BLK 0 "memory_operand" "") | |
2731 | (match_operand:BLK 1 "memory_operand" "")) | |
2732 | (use (match_operand 2 "general_operand" "")) | |
2733 | (use (match_dup 3)) | |
ae156f85 | 2734 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2735 | "" |
2736 | { | |
9602b6a1 AK |
2737 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
2738 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
2739 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
2740 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
2741 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
2742 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
2743 | rtx len0 = gen_lowpart (Pmode, reg0); |
2744 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2745 | ||
c41c1387 | 2746 | emit_clobber (reg0); |
b9404c99 UW |
2747 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2748 | emit_move_insn (len0, operands[2]); | |
2749 | ||
c41c1387 | 2750 | emit_clobber (reg1); |
b9404c99 UW |
2751 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2752 | emit_move_insn (len1, operands[2]); | |
2753 | ||
2754 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2755 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2756 | operands[2] = reg0; | |
2757 | operands[3] = reg1; | |
2758 | }) | |
2759 | ||
a1aed706 AS |
2760 | (define_insn "*movmem_long" |
2761 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2762 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2763 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2764 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2765 | (use (match_dup 2)) |
2766 | (use (match_dup 3)) | |
ae156f85 | 2767 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
2768 | "TARGET_64BIT || !TARGET_ZARCH" |
2769 | "mvcle\t%0,%1,0\;jo\t.-4" | |
2770 | [(set_attr "length" "8") | |
2771 | (set_attr "type" "vs")]) | |
2772 | ||
2773 | (define_insn "*movmem_long_31z" | |
2774 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2775 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2776 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
2777 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
2778 | (use (match_dup 2)) | |
2779 | (use (match_dup 3)) | |
2780 | (clobber (reg:CC CC_REGNUM))] | |
2781 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 2782 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2783 | [(set_attr "length" "8") |
2784 | (set_attr "type" "vs")]) | |
9db1d521 | 2785 | |
638e37c2 WG |
2786 | |
2787 | ; | |
2788 | ; Test data class. | |
2789 | ; | |
2790 | ||
0f67fa83 WG |
2791 | (define_expand "signbit<mode>2" |
2792 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2793 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2794 | (match_dup 2)] | |
0f67fa83 WG |
2795 | UNSPEC_TDC_INSN)) |
2796 | (set (match_operand:SI 0 "register_operand" "=d") | |
2797 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
2798 | "TARGET_HARD_FLOAT" | |
2799 | { | |
2800 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
2801 | }) | |
2802 | ||
638e37c2 WG |
2803 | (define_expand "isinf<mode>2" |
2804 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2805 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2806 | (match_dup 2)] | |
638e37c2 WG |
2807 | UNSPEC_TDC_INSN)) |
2808 | (set (match_operand:SI 0 "register_operand" "=d") | |
2809 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
142cd70f | 2810 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
2811 | { |
2812 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
2813 | }) | |
2814 | ||
2815 | ; This insn is used to generate all variants of the Test Data Class | |
2816 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
2817 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 2818 | ; specifying the required test(s). |
638e37c2 | 2819 | ; |
be5de7a1 | 2820 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
2821 | (define_insn "*TDC_insn_<mode>" |
2822 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 2823 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 2824 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 2825 | "TARGET_HARD_FLOAT" |
0387c142 | 2826 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 2827 | [(set_attr "op_type" "RXE") |
9381e3f1 | 2828 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 WG |
2829 | |
2830 | (define_insn_and_split "*ccz_to_int" | |
2831 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2832 | (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")] | |
2833 | UNSPEC_CCZ_TO_INT))] | |
2834 | "" | |
2835 | "#" | |
2836 | "reload_completed" | |
2837 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
2838 | ||
2839 | ||
9db1d521 | 2840 | ; |
57e84f18 | 2841 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2842 | ; |
2843 | ||
57e84f18 | 2844 | (define_expand "setmem<mode>" |
a41c6c53 | 2845 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2846 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2847 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2848 | (match_operand 3 "" "")] |
a41c6c53 | 2849 | "" |
6d057022 | 2850 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2851 | |
a41c6c53 | 2852 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2853 | ; The block length is taken as (operands[1] % 256) + 1. |
2854 | ||
70128ad9 | 2855 | (define_expand "clrmem_short" |
b9404c99 UW |
2856 | [(parallel |
2857 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2858 | (const_int 0)) | |
2859 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2860 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2861 | (clobber (match_dup 2)) |
ae156f85 | 2862 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2863 | "" |
2864 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2865 | |
70128ad9 | 2866 | (define_insn "*clrmem_short" |
963fc8d0 | 2867 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 2868 | (const_int 0)) |
963fc8d0 AK |
2869 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
2870 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 2871 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 2872 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 2873 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 2874 | "#" |
963fc8d0 AK |
2875 | [(set_attr "type" "cs") |
2876 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9bb86f41 UW |
2877 | |
2878 | (define_split | |
2879 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2880 | (const_int 0)) | |
2881 | (use (match_operand 1 "const_int_operand" "")) | |
2882 | (use (match_operand 2 "immediate_operand" "")) | |
2883 | (clobber (scratch)) | |
ae156f85 | 2884 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2885 | "reload_completed" |
2886 | [(parallel | |
2887 | [(set (match_dup 0) (const_int 0)) | |
2888 | (use (match_dup 1)) | |
ae156f85 | 2889 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2890 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2891 | |
9bb86f41 UW |
2892 | (define_split |
2893 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2894 | (const_int 0)) | |
2895 | (use (match_operand 1 "register_operand" "")) | |
2896 | (use (match_operand 2 "memory_operand" "")) | |
2897 | (clobber (scratch)) | |
ae156f85 | 2898 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2899 | "reload_completed" |
2900 | [(parallel | |
2901 | [(unspec [(match_dup 1) (match_dup 2) | |
2902 | (const_int 0)] UNSPEC_EXECUTE) | |
2903 | (set (match_dup 0) (const_int 0)) | |
2904 | (use (const_int 1)) | |
ae156f85 | 2905 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2906 | "") |
9db1d521 | 2907 | |
963fc8d0 AK |
2908 | (define_split |
2909 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2910 | (const_int 0)) | |
2911 | (use (match_operand 1 "register_operand" "")) | |
2912 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2913 | (clobber (scratch)) | |
2914 | (clobber (reg:CC CC_REGNUM))] | |
2915 | "TARGET_Z10 && reload_completed" | |
2916 | [(parallel | |
2917 | [(unspec [(match_dup 1) (const_int 0) | |
2918 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2919 | (set (match_dup 0) (const_int 0)) | |
2920 | (use (const_int 1)) | |
2921 | (clobber (reg:CC CC_REGNUM))])] | |
2922 | "operands[3] = gen_label_rtx ();") | |
2923 | ||
9bb86f41 UW |
2924 | (define_split |
2925 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2926 | (const_int 0)) | |
2927 | (use (match_operand 1 "register_operand" "")) | |
2928 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2929 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2930 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2931 | "reload_completed && TARGET_CPU_ZARCH" |
2932 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2933 | (parallel | |
9381e3f1 | 2934 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
2935 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
2936 | (set (match_dup 0) (const_int 0)) | |
2937 | (use (const_int 1)) | |
ae156f85 | 2938 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2939 | "operands[3] = gen_label_rtx ();") |
2940 | ||
9381e3f1 | 2941 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2942 | |
6d057022 | 2943 | (define_expand "setmem_long" |
b9404c99 UW |
2944 | [(parallel |
2945 | [(clobber (match_dup 1)) | |
2946 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 2947 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 2948 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2949 | (use (match_dup 3)) |
ae156f85 | 2950 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2951 | "" |
a41c6c53 | 2952 | { |
9602b6a1 AK |
2953 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
2954 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
2955 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
2956 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
2957 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 2958 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 2959 | |
c41c1387 | 2960 | emit_clobber (reg0); |
b9404c99 UW |
2961 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2962 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2963 | |
b9404c99 | 2964 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2965 | |
b9404c99 UW |
2966 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2967 | operands[1] = reg0; | |
6d057022 | 2968 | operands[3] = reg1; |
b9404c99 | 2969 | }) |
a41c6c53 | 2970 | |
6d057022 | 2971 | (define_insn "*setmem_long" |
a1aed706 | 2972 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 2973 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 2974 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 2975 | (use (match_dup 3)) |
a1aed706 | 2976 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2977 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 2978 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 2979 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
2980 | [(set_attr "length" "8") |
2981 | (set_attr "type" "vs")]) | |
9db1d521 | 2982 | |
4989e88a AK |
2983 | (define_insn "*setmem_long_and" |
2984 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2985 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
2986 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
2987 | (match_operand 4 "const_int_operand" "n"))) | |
2988 | (use (match_dup 3)) | |
2989 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
2990 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 AK |
2991 | "(TARGET_64BIT || !TARGET_ZARCH) && |
2992 | (INTVAL (operands[4]) & 255) == 255" | |
2993 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
2994 | [(set_attr "length" "8") | |
2995 | (set_attr "type" "vs")]) | |
2996 | ||
2997 | (define_insn "*setmem_long_31z" | |
2998 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2999 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
3000 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) | |
3001 | (use (match_dup 3)) | |
3002 | (use (match_operand:TI 1 "register_operand" "d")) | |
3003 | (clobber (reg:CC CC_REGNUM))] | |
3004 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3005 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3006 | [(set_attr "length" "8") | |
3007 | (set_attr "type" "vs")]) | |
9602b6a1 | 3008 | |
9db1d521 | 3009 | ; |
358b8f01 | 3010 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3011 | ; |
3012 | ||
358b8f01 | 3013 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3014 | [(set (match_operand:SI 0 "register_operand" "") |
3015 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3016 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3017 | (use (match_operand:SI 3 "general_operand" "")) | |
3018 | (use (match_operand:SI 4 "" ""))] | |
3019 | "" | |
c7453384 | 3020 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 3021 | operands[2], operands[3]); DONE;") |
9db1d521 | 3022 | |
a41c6c53 UW |
3023 | ; Compare a block that is up to 256 bytes in length. |
3024 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3025 | |
b9404c99 UW |
3026 | (define_expand "cmpmem_short" |
3027 | [(parallel | |
ae156f85 | 3028 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3029 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3030 | (match_operand:BLK 1 "memory_operand" ""))) |
3031 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3032 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3033 | (clobber (match_dup 3))])] |
3034 | "" | |
3035 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3036 | |
b9404c99 | 3037 | (define_insn "*cmpmem_short" |
ae156f85 | 3038 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3039 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3040 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3041 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3042 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3043 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3044 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3045 | "#" |
963fc8d0 AK |
3046 | [(set_attr "type" "cs") |
3047 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9db1d521 | 3048 | |
9bb86f41 | 3049 | (define_split |
ae156f85 | 3050 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3051 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3052 | (match_operand:BLK 1 "memory_operand" ""))) | |
3053 | (use (match_operand 2 "const_int_operand" "")) | |
3054 | (use (match_operand 3 "immediate_operand" "")) | |
3055 | (clobber (scratch))] | |
3056 | "reload_completed" | |
3057 | [(parallel | |
ae156f85 | 3058 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3059 | (use (match_dup 2))])] |
3060 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3061 | |
9bb86f41 | 3062 | (define_split |
ae156f85 | 3063 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3064 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3065 | (match_operand:BLK 1 "memory_operand" ""))) | |
3066 | (use (match_operand 2 "register_operand" "")) | |
3067 | (use (match_operand 3 "memory_operand" "")) | |
3068 | (clobber (scratch))] | |
3069 | "reload_completed" | |
3070 | [(parallel | |
3071 | [(unspec [(match_dup 2) (match_dup 3) | |
3072 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3073 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3074 | (use (const_int 1))])] |
3075 | "") | |
3076 | ||
963fc8d0 AK |
3077 | (define_split |
3078 | [(set (reg:CCU CC_REGNUM) | |
3079 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3080 | (match_operand:BLK 1 "memory_operand" ""))) | |
3081 | (use (match_operand 2 "register_operand" "")) | |
3082 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3083 | (clobber (scratch))] | |
3084 | "TARGET_Z10 && reload_completed" | |
3085 | [(parallel | |
3086 | [(unspec [(match_dup 2) (const_int 0) | |
3087 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3088 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3089 | (use (const_int 1))])] | |
3090 | "operands[4] = gen_label_rtx ();") | |
3091 | ||
9bb86f41 | 3092 | (define_split |
ae156f85 | 3093 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3094 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3095 | (match_operand:BLK 1 "memory_operand" ""))) | |
3096 | (use (match_operand 2 "register_operand" "")) | |
3097 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3098 | (clobber (match_operand 3 "register_operand" ""))] | |
3099 | "reload_completed && TARGET_CPU_ZARCH" | |
3100 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3101 | (parallel | |
9381e3f1 | 3102 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3103 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3104 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3105 | (use (const_int 1))])] |
3106 | "operands[4] = gen_label_rtx ();") | |
3107 | ||
a41c6c53 | 3108 | ; Compare a block of arbitrary length. |
9db1d521 | 3109 | |
b9404c99 UW |
3110 | (define_expand "cmpmem_long" |
3111 | [(parallel | |
3112 | [(clobber (match_dup 2)) | |
3113 | (clobber (match_dup 3)) | |
ae156f85 | 3114 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3115 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3116 | (match_operand:BLK 1 "memory_operand" ""))) |
3117 | (use (match_operand 2 "general_operand" "")) | |
3118 | (use (match_dup 3))])] | |
3119 | "" | |
3120 | { | |
9602b6a1 AK |
3121 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3122 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
3123 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
3124 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3125 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3126 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3127 | rtx len0 = gen_lowpart (Pmode, reg0); |
3128 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3129 | ||
c41c1387 | 3130 | emit_clobber (reg0); |
b9404c99 UW |
3131 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3132 | emit_move_insn (len0, operands[2]); | |
3133 | ||
c41c1387 | 3134 | emit_clobber (reg1); |
b9404c99 UW |
3135 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3136 | emit_move_insn (len1, operands[2]); | |
3137 | ||
3138 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3139 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3140 | operands[2] = reg0; | |
3141 | operands[3] = reg1; | |
3142 | }) | |
3143 | ||
a1aed706 AS |
3144 | (define_insn "*cmpmem_long" |
3145 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3146 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3147 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3148 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3149 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3150 | (use (match_dup 2)) |
3151 | (use (match_dup 3))] | |
9602b6a1 | 3152 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3153 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3154 | [(set_attr "length" "8") |
3155 | (set_attr "type" "vs")]) | |
9db1d521 | 3156 | |
9602b6a1 AK |
3157 | (define_insn "*cmpmem_long_31z" |
3158 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3159 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3160 | (set (reg:CCU CC_REGNUM) | |
3161 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3162 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3163 | (use (match_dup 2)) | |
3164 | (use (match_dup 3))] | |
3165 | "!TARGET_64BIT && TARGET_ZARCH" | |
3166 | "clcle\t%0,%1,0\;jo\t.-4" | |
3167 | [(set_attr "op_type" "NN") | |
3168 | (set_attr "type" "vs") | |
3169 | (set_attr "length" "8")]) | |
3170 | ||
02887425 UW |
3171 | ; Convert CCUmode condition code to integer. |
3172 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3173 | |
02887425 | 3174 | (define_insn_and_split "cmpint" |
9db1d521 | 3175 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3176 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3177 | UNSPEC_CCU_TO_INT)) |
ae156f85 | 3178 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3179 | "" |
02887425 UW |
3180 | "#" |
3181 | "reload_completed" | |
3182 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3183 | (parallel | |
3184 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3185 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3186 | |
3187 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3188 | [(set (reg CC_REGNUM) |
02887425 | 3189 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3190 | UNSPEC_CCU_TO_INT) |
02887425 UW |
3191 | (const_int 0))) |
3192 | (set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 3193 | (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))] |
02887425 UW |
3194 | "s390_match_ccmode (insn, CCSmode)" |
3195 | "#" | |
3196 | "&& reload_completed" | |
3197 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3198 | (parallel | |
3199 | [(set (match_dup 2) (match_dup 3)) | |
3200 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3201 | { |
02887425 UW |
3202 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3203 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3204 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3205 | }) | |
9db1d521 | 3206 | |
02887425 | 3207 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3208 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3209 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3210 | UNSPEC_CCU_TO_INT))) |
ae156f85 | 3211 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3212 | "TARGET_ZARCH" |
02887425 UW |
3213 | "#" |
3214 | "&& reload_completed" | |
3215 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3216 | (parallel | |
3217 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3218 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3219 | |
3220 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3221 | [(set (reg CC_REGNUM) |
9381e3f1 | 3222 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3223 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3224 | UNSPEC_CCU_TO_INT) 0) |
02887425 UW |
3225 | (const_int 32)) (const_int 32)) |
3226 | (const_int 0))) | |
3227 | (set (match_operand:DI 0 "register_operand" "=d") | |
638e37c2 | 3228 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] |
9602b6a1 | 3229 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3230 | "#" |
3231 | "&& reload_completed" | |
3232 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3233 | (parallel | |
3234 | [(set (match_dup 2) (match_dup 3)) | |
3235 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3236 | { |
02887425 UW |
3237 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3238 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3239 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3240 | }) | |
9db1d521 | 3241 | |
4023fb28 | 3242 | |
9db1d521 HP |
3243 | ;; |
3244 | ;;- Conversion instructions. | |
3245 | ;; | |
3246 | ||
6fa05db6 | 3247 | (define_insn "*sethighpartsi" |
d3632d41 | 3248 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3249 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3250 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3251 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3252 | "" |
d3632d41 | 3253 | "@ |
6fa05db6 AS |
3254 | icm\t%0,%2,%S1 |
3255 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3256 | [(set_attr "op_type" "RS,RSY") |
3257 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3258 | |
6fa05db6 | 3259 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3260 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3261 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3262 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3263 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3264 | "TARGET_ZARCH" |
6fa05db6 | 3265 | "icmh\t%0,%2,%S1" |
729e750f WG |
3266 | [(set_attr "op_type" "RSY") |
3267 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3268 | |
6fa05db6 | 3269 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3270 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3271 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3272 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3273 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3274 | "!TARGET_ZARCH" |
d3632d41 | 3275 | "@ |
6fa05db6 AS |
3276 | icm\t%0,%2,%S1 |
3277 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3278 | [(set_attr "op_type" "RS,RSY") |
3279 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3280 | ||
4023fb28 | 3281 | |
6fa05db6 AS |
3282 | (define_insn_and_split "*extzv<mode>" |
3283 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3284 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3285 | (match_operand 2 "const_int_operand" "n") | |
3286 | (const_int 0))) | |
ae156f85 | 3287 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3288 | "INTVAL (operands[2]) > 0 |
3289 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3290 | "#" |
3291 | "&& reload_completed" | |
4023fb28 | 3292 | [(parallel |
6fa05db6 | 3293 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3294 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3295 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3296 | { |
6fa05db6 AS |
3297 | int bitsize = INTVAL (operands[2]); |
3298 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3299 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3300 | ||
3301 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3302 | set_mem_size (operands[1], size); |
6fa05db6 AS |
3303 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); |
3304 | operands[3] = GEN_INT (mask); | |
b628bd8e | 3305 | }) |
4023fb28 | 3306 | |
6fa05db6 AS |
3307 | (define_insn_and_split "*extv<mode>" |
3308 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3309 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3310 | (match_operand 2 "const_int_operand" "n") | |
3311 | (const_int 0))) | |
ae156f85 | 3312 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3313 | "INTVAL (operands[2]) > 0 |
3314 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3315 | "#" |
3316 | "&& reload_completed" | |
4023fb28 | 3317 | [(parallel |
6fa05db6 | 3318 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3319 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3320 | (parallel |
3321 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3322 | (clobber (reg:CC CC_REGNUM))])] | |
3323 | { | |
3324 | int bitsize = INTVAL (operands[2]); | |
3325 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3326 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3327 | ||
3328 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3329 | set_mem_size (operands[1], size); |
6fa05db6 AS |
3330 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); |
3331 | operands[3] = GEN_INT (mask); | |
3332 | }) | |
3333 | ||
3334 | ; | |
3335 | ; insv instruction patterns | |
3336 | ; | |
3337 | ||
3338 | (define_expand "insv" | |
3339 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3340 | (match_operand 1 "const_int_operand" "") | |
3341 | (match_operand 2 "const_int_operand" "")) | |
3342 | (match_operand 3 "general_operand" ""))] | |
3343 | "" | |
4023fb28 | 3344 | { |
6fa05db6 AS |
3345 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3346 | DONE; | |
3347 | FAIL; | |
b628bd8e | 3348 | }) |
4023fb28 | 3349 | |
963fc8d0 AK |
3350 | (define_insn "*insv<mode>_z10" |
3351 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
3352 | (match_operand 1 "const_int_operand" "I") | |
3353 | (match_operand 2 "const_int_operand" "I")) | |
3354 | (match_operand:GPR 3 "nonimmediate_operand" "d")) | |
3355 | (clobber (reg:CC CC_REGNUM))] | |
3356 | "TARGET_Z10 | |
3357 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= | |
3358 | GET_MODE_BITSIZE (<MODE>mode)" | |
3359 | { | |
3360 | int start = INTVAL (operands[2]); | |
3361 | int size = INTVAL (operands[1]); | |
3362 | int offset = 64 - GET_MODE_BITSIZE (<MODE>mode); | |
3363 | ||
3364 | operands[2] = GEN_INT (offset + start); /* start bit position */ | |
3365 | operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ | |
3366 | operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - | |
3367 | start - size); /* left shift count */ | |
3368 | ||
3369 | return "risbg\t%0,%3,%b2,%b1,%b4"; | |
3370 | } | |
9381e3f1 WG |
3371 | [(set_attr "op_type" "RIE") |
3372 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3373 | |
3374 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3375 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3376 | (define_insn "*insv<mode>_z10_noshift" | |
3377 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3378 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3379 | (match_operand 2 "const_int_operand" "n")) | |
3380 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") | |
3381 | (match_operand 4 "const_int_operand" "n")))) | |
3382 | (clobber (reg:CC CC_REGNUM))] | |
3383 | "TARGET_Z10 | |
3384 | && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3385 | GET_MODE_BITSIZE (<MODE>mode), NULL, NULL) | |
3386 | && INTVAL (operands[2]) == ~(INTVAL (operands[4]))" | |
3387 | ||
3388 | { | |
3389 | int start; | |
3390 | int size; | |
3391 | ||
3392 | s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3393 | GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3394 | ||
3395 | operands[5] = GEN_INT (64 - start - size); /* start bit position */ | |
3396 | operands[6] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3397 | operands[7] = const0_rtx; /* left shift count */ | |
3398 | ||
3399 | return "risbg\t%0,%1,%b5,%b6,%b7"; | |
3400 | } | |
9381e3f1 WG |
3401 | [(set_attr "op_type" "RIE") |
3402 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3403 | |
3404 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3405 | (define_insn "*insv<mode>_or_z10_noshift" | |
3406 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3407 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3408 | (match_operand 2 "const_int_operand" "n")) | |
3409 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
3410 | (clobber (reg:CC CC_REGNUM))] | |
3411 | "TARGET_Z10 | |
3412 | && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3413 | GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)" | |
3414 | { | |
3415 | int start; | |
3416 | int size; | |
3417 | ||
3418 | s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3419 | GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3420 | ||
3421 | operands[4] = GEN_INT (64 - start - size); /* start bit position */ | |
3422 | operands[5] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3423 | operands[6] = const0_rtx; /* left shift count */ | |
3424 | ||
3425 | return "rosbg\t%0,%1,%b4,%b5,%b6"; | |
3426 | } | |
3427 | [(set_attr "op_type" "RIE")]) | |
3428 | ||
6fa05db6 | 3429 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 3430 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
3431 | (match_operand 1 "const_int_operand" "n,n") |
3432 | (const_int 0)) | |
9602b6a1 | 3433 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
3434 | "INTVAL (operands[1]) > 0 |
3435 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3436 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3437 | { | |
3438 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3439 | ||
3440 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 3441 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
3442 | : "stcmy\t%2,%1,%S0"; |
3443 | } | |
9381e3f1 WG |
3444 | [(set_attr "op_type" "RS,RSY") |
3445 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
3446 | |
3447 | (define_insn "*insvdi_mem_reghigh" | |
3448 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3449 | (match_operand 1 "const_int_operand" "n") | |
3450 | (const_int 0)) | |
3451 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3452 | (const_int 32)))] | |
9602b6a1 | 3453 | "TARGET_ZARCH |
6fa05db6 AS |
3454 | && INTVAL (operands[1]) > 0 |
3455 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3456 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3457 | { | |
3458 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3459 | ||
3460 | operands[1] = GEN_INT ((1ul << size) - 1); | |
3461 | return "stcmh\t%2,%1,%S0"; | |
3462 | } | |
9381e3f1 WG |
3463 | [(set_attr "op_type" "RSY") |
3464 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 3465 | |
9602b6a1 AK |
3466 | (define_insn "*insvdi_reg_imm" |
3467 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3468 | (const_int 16) | |
3469 | (match_operand 1 "const_int_operand" "n")) | |
3470 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
3471 | "TARGET_ZARCH |
3472 | && INTVAL (operands[1]) >= 0 | |
3473 | && INTVAL (operands[1]) < BITS_PER_WORD | |
3474 | && INTVAL (operands[1]) % 16 == 0" | |
3475 | { | |
3476 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3477 | { | |
3478 | case 64: return "iihh\t%0,%x2"; break; | |
3479 | case 48: return "iihl\t%0,%x2"; break; | |
3480 | case 32: return "iilh\t%0,%x2"; break; | |
3481 | case 16: return "iill\t%0,%x2"; break; | |
3482 | default: gcc_unreachable(); | |
3483 | } | |
3484 | } | |
9381e3f1 WG |
3485 | [(set_attr "op_type" "RI") |
3486 | (set_attr "z10prop" "z10_super_E1")]) | |
3487 | ||
9fec758d WG |
3488 | ; Update the left-most 32 bit of a DI. |
3489 | (define_insn "*insv_h_di_reg_extimm" | |
3490 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3491 | (const_int 32) | |
3492 | (const_int 0)) | |
3493 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3494 | "TARGET_EXTIMM" | |
3495 | "iihf\t%0,%o1" | |
3496 | [(set_attr "op_type" "RIL") | |
3497 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 3498 | |
9fec758d WG |
3499 | ; Update the right-most 32 bit of a DI, or the whole of a SI. |
3500 | (define_insn "*insv_l<mode>_reg_extimm" | |
6fa05db6 AS |
3501 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") |
3502 | (const_int 32) | |
3503 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 3504 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 | 3505 | "TARGET_EXTIMM |
9fec758d WG |
3506 | && BITS_PER_WORD - INTVAL (operands[1]) == 32" |
3507 | "iilf\t%0,%o2" | |
9381e3f1 | 3508 | [(set_attr "op_type" "RIL") |
9fec758d | 3509 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 3510 | |
9db1d521 HP |
3511 | ; |
3512 | ; extendsidi2 instruction pattern(s). | |
3513 | ; | |
3514 | ||
4023fb28 UW |
3515 | (define_expand "extendsidi2" |
3516 | [(set (match_operand:DI 0 "register_operand" "") | |
3517 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3518 | "" | |
4023fb28 | 3519 | { |
9602b6a1 | 3520 | if (!TARGET_ZARCH) |
4023fb28 | 3521 | { |
c41c1387 | 3522 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3523 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
3524 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
3525 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
3526 | DONE; |
3527 | } | |
ec24698e | 3528 | }) |
4023fb28 UW |
3529 | |
3530 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
3531 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3532 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3533 | "TARGET_ZARCH" |
9db1d521 | 3534 | "@ |
d40c829f | 3535 | lgfr\t%0,%1 |
963fc8d0 AK |
3536 | lgf\t%0,%1 |
3537 | lgfrl\t%0,%1" | |
3538 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3539 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3540 | (set_attr "cpu_facility" "*,*,z10") |
3541 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3542 | |
9db1d521 | 3543 | ; |
56477c21 | 3544 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3545 | ; |
3546 | ||
56477c21 AS |
3547 | (define_expand "extend<HQI:mode><DSI:mode>2" |
3548 | [(set (match_operand:DSI 0 "register_operand" "") | |
3549 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 3550 | "" |
4023fb28 | 3551 | { |
9602b6a1 | 3552 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
3553 | { |
3554 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 3555 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
3556 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
3557 | DONE; | |
3558 | } | |
ec24698e | 3559 | else if (!TARGET_EXTIMM) |
4023fb28 | 3560 | { |
56477c21 AS |
3561 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - |
3562 | GET_MODE_BITSIZE (<HQI:MODE>mode)); | |
3563 | ||
3564 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
3565 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
3566 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
3567 | DONE; |
3568 | } | |
ec24698e UW |
3569 | }) |
3570 | ||
56477c21 AS |
3571 | ; |
3572 | ; extendhidi2 instruction pattern(s). | |
3573 | ; | |
3574 | ||
ec24698e | 3575 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
3576 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3577 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 3578 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
3579 | "@ |
3580 | lghr\t%0,%1 | |
963fc8d0 AK |
3581 | lgh\t%0,%1 |
3582 | lghrl\t%0,%1" | |
3583 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3584 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3585 | (set_attr "cpu_facility" "extimm,extimm,z10") |
3586 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
3587 | |
3588 | (define_insn "*extendhidi2" | |
9db1d521 | 3589 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 3590 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 3591 | "TARGET_ZARCH" |
d40c829f | 3592 | "lgh\t%0,%1" |
9381e3f1 WG |
3593 | [(set_attr "op_type" "RXY") |
3594 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 3595 | |
9db1d521 | 3596 | ; |
56477c21 | 3597 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
3598 | ; |
3599 | ||
ec24698e | 3600 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
3601 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3602 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
3603 | "TARGET_EXTIMM" |
3604 | "@ | |
3605 | lhr\t%0,%1 | |
3606 | lh\t%0,%1 | |
963fc8d0 AK |
3607 | lhy\t%0,%1 |
3608 | lhrl\t%0,%1" | |
3609 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
3610 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
3611 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
3612 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3613 | |
4023fb28 | 3614 | (define_insn "*extendhisi2" |
d3632d41 UW |
3615 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3616 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 3617 | "!TARGET_EXTIMM" |
d3632d41 | 3618 | "@ |
d40c829f UW |
3619 | lh\t%0,%1 |
3620 | lhy\t%0,%1" | |
9381e3f1 WG |
3621 | [(set_attr "op_type" "RX,RXY") |
3622 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3623 | |
56477c21 AS |
3624 | ; |
3625 | ; extendqi(si|di)2 instruction pattern(s). | |
3626 | ; | |
3627 | ||
43a09b63 | 3628 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
3629 | (define_insn "*extendqi<mode>2_extimm" |
3630 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3631 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3632 | "TARGET_EXTIMM" |
3633 | "@ | |
56477c21 AS |
3634 | l<g>br\t%0,%1 |
3635 | l<g>b\t%0,%1" | |
9381e3f1 WG |
3636 | [(set_attr "op_type" "RRE,RXY") |
3637 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 3638 | |
43a09b63 | 3639 | ; lb, lgb |
56477c21 AS |
3640 | (define_insn "*extendqi<mode>2" |
3641 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3642 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
3643 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
3644 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
3645 | [(set_attr "op_type" "RXY") |
3646 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 3647 | |
56477c21 AS |
3648 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
3649 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3650 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 3651 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 3652 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
3653 | "#" |
3654 | "&& reload_completed" | |
4023fb28 | 3655 | [(parallel |
56477c21 | 3656 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 3657 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 3658 | (parallel |
56477c21 | 3659 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 3660 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
3661 | { |
3662 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3663 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
56477c21 AS |
3664 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) |
3665 | - GET_MODE_BITSIZE (QImode)); | |
6fa05db6 | 3666 | }) |
9db1d521 | 3667 | |
9db1d521 HP |
3668 | ; |
3669 | ; zero_extendsidi2 instruction pattern(s). | |
3670 | ; | |
3671 | ||
4023fb28 UW |
3672 | (define_expand "zero_extendsidi2" |
3673 | [(set (match_operand:DI 0 "register_operand" "") | |
3674 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3675 | "" | |
4023fb28 | 3676 | { |
9602b6a1 | 3677 | if (!TARGET_ZARCH) |
4023fb28 | 3678 | { |
c41c1387 | 3679 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3680 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
3681 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
3682 | DONE; |
3683 | } | |
ec24698e | 3684 | }) |
4023fb28 UW |
3685 | |
3686 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
3687 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3688 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3689 | "TARGET_ZARCH" |
9db1d521 | 3690 | "@ |
d40c829f | 3691 | llgfr\t%0,%1 |
963fc8d0 AK |
3692 | llgf\t%0,%1 |
3693 | llgfrl\t%0,%1" | |
3694 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3695 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3696 | (set_attr "cpu_facility" "*,*,z10") |
3697 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 3698 | |
288e517f AK |
3699 | ; |
3700 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
3701 | ; | |
3702 | ||
d6083c7d UW |
3703 | (define_insn "*llgt_sidi" |
3704 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3705 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3706 | (const_int 2147483647)))] |
9602b6a1 | 3707 | "TARGET_ZARCH" |
d6083c7d | 3708 | "llgt\t%0,%1" |
9381e3f1 WG |
3709 | [(set_attr "op_type" "RXE") |
3710 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
3711 | |
3712 | (define_insn_and_split "*llgt_sidi_split" | |
3713 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3714 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3715 | (const_int 2147483647))) |
ae156f85 | 3716 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3717 | "TARGET_ZARCH" |
d6083c7d UW |
3718 | "#" |
3719 | "&& reload_completed" | |
3720 | [(set (match_dup 0) | |
3721 | (and:DI (subreg:DI (match_dup 1) 0) | |
3722 | (const_int 2147483647)))] | |
3723 | "") | |
3724 | ||
288e517f AK |
3725 | (define_insn "*llgt_sisi" |
3726 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 3727 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 3728 | (const_int 2147483647)))] |
c4d50129 | 3729 | "TARGET_ZARCH" |
288e517f AK |
3730 | "@ |
3731 | llgtr\t%0,%1 | |
3732 | llgt\t%0,%1" | |
9381e3f1 WG |
3733 | [(set_attr "op_type" "RRE,RXE") |
3734 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3735 | |
288e517f AK |
3736 | (define_insn "*llgt_didi" |
3737 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3738 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
3739 | (const_int 2147483647)))] | |
9602b6a1 | 3740 | "TARGET_ZARCH" |
288e517f AK |
3741 | "@ |
3742 | llgtr\t%0,%1 | |
3743 | llgt\t%0,%N1" | |
9381e3f1 WG |
3744 | [(set_attr "op_type" "RRE,RXE") |
3745 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3746 | |
f19a9af7 | 3747 | (define_split |
9602b6a1 AK |
3748 | [(set (match_operand:DSI 0 "register_operand" "") |
3749 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 3750 | (const_int 2147483647))) |
ae156f85 | 3751 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 3752 | "TARGET_ZARCH && reload_completed" |
288e517f | 3753 | [(set (match_dup 0) |
9602b6a1 | 3754 | (and:DSI (match_dup 1) |
f6ee577c | 3755 | (const_int 2147483647)))] |
288e517f AK |
3756 | "") |
3757 | ||
9db1d521 | 3758 | ; |
56477c21 | 3759 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3760 | ; |
3761 | ||
56477c21 AS |
3762 | (define_expand "zero_extend<mode>di2" |
3763 | [(set (match_operand:DI 0 "register_operand" "") | |
3764 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3765 | "" | |
3766 | { | |
9602b6a1 | 3767 | if (!TARGET_ZARCH) |
56477c21 AS |
3768 | { |
3769 | rtx tmp = gen_reg_rtx (SImode); | |
3770 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3771 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3772 | DONE; | |
3773 | } | |
3774 | else if (!TARGET_EXTIMM) | |
3775 | { | |
9381e3f1 | 3776 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - |
56477c21 AS |
3777 | GET_MODE_BITSIZE(<MODE>mode)); |
3778 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3779 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
3780 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
3781 | DONE; | |
3782 | } | |
3783 | }) | |
3784 | ||
f6ee577c | 3785 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 3786 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 3787 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 3788 | "" |
4023fb28 | 3789 | { |
ec24698e UW |
3790 | if (!TARGET_EXTIMM) |
3791 | { | |
3792 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 3793 | emit_insn (gen_andsi3 (operands[0], operands[1], |
ec24698e UW |
3794 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); |
3795 | DONE; | |
56477c21 | 3796 | } |
ec24698e UW |
3797 | }) |
3798 | ||
963fc8d0 AK |
3799 | ; llhrl, llghrl |
3800 | (define_insn "*zero_extendhi<mode>2_z10" | |
3801 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3802 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
3803 | "TARGET_Z10" | |
3804 | "@ | |
3805 | ll<g>hr\t%0,%1 | |
3806 | ll<g>h\t%0,%1 | |
3807 | ll<g>hrl\t%0,%1" | |
3808 | [(set_attr "op_type" "RXY,RRE,RIL") | |
3809 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 3810 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 3811 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 3812 | |
43a09b63 | 3813 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
3814 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
3815 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3816 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3817 | "TARGET_EXTIMM" |
3818 | "@ | |
56477c21 AS |
3819 | ll<g><hc>r\t%0,%1 |
3820 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
3821 | [(set_attr "op_type" "RRE,RXY") |
3822 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 3823 | |
43a09b63 | 3824 | ; llgh, llgc |
56477c21 AS |
3825 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
3826 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3827 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 3828 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 3829 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
3830 | [(set_attr "op_type" "RXY") |
3831 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
3832 | |
3833 | (define_insn_and_split "*zero_extendhisi2_31" | |
3834 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 3835 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 3836 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 3837 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3838 | "#" |
3839 | "&& reload_completed" | |
3840 | [(set (match_dup 0) (const_int 0)) | |
3841 | (parallel | |
3842 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 3843 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 3844 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 3845 | |
cc7ab9b7 UW |
3846 | (define_insn_and_split "*zero_extendqisi2_31" |
3847 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 3848 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3849 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3850 | "#" |
3851 | "&& reload_completed" | |
3852 | [(set (match_dup 0) (const_int 0)) | |
3853 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3854 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 3855 | |
9db1d521 HP |
3856 | ; |
3857 | ; zero_extendqihi2 instruction pattern(s). | |
3858 | ; | |
3859 | ||
9db1d521 HP |
3860 | (define_expand "zero_extendqihi2" |
3861 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 3862 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 3863 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 3864 | { |
4023fb28 UW |
3865 | operands[1] = gen_lowpart (HImode, operands[1]); |
3866 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
3867 | DONE; | |
ec24698e | 3868 | }) |
9db1d521 | 3869 | |
4023fb28 | 3870 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 3871 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 3872 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 3873 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 3874 | "llgc\t%0,%1" |
9381e3f1 WG |
3875 | [(set_attr "op_type" "RXY") |
3876 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 3877 | |
cc7ab9b7 UW |
3878 | (define_insn_and_split "*zero_extendqihi2_31" |
3879 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 3880 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3881 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3882 | "#" |
3883 | "&& reload_completed" | |
3884 | [(set (match_dup 0) (const_int 0)) | |
3885 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3886 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 3887 | |
609e7e80 AK |
3888 | ; |
3889 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
3890 | ; | |
3891 | ||
3892 | (define_expand "fixuns_truncdddi2" | |
3893 | [(parallel | |
3894 | [(set (match_operand:DI 0 "register_operand" "") | |
3895 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
65b1d8ea AK |
3896 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) |
3897 | (clobber (reg:CC CC_REGNUM))])] | |
9381e3f1 | 3898 | |
fb068247 | 3899 | "TARGET_HARD_DFP" |
609e7e80 | 3900 | { |
65b1d8ea AK |
3901 | if (!TARGET_Z196) |
3902 | { | |
3903 | rtx label1 = gen_label_rtx (); | |
3904 | rtx label2 = gen_label_rtx (); | |
3905 | rtx temp = gen_reg_rtx (TDmode); | |
3906 | REAL_VALUE_TYPE cmp, sub; | |
3907 | ||
3908 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3909 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3910 | ||
3911 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
3912 | solution is doing the check and the subtraction in TD mode and using a | |
3913 | TD -> DI convert afterwards. */ | |
3914 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
3915 | temp = force_reg (TDmode, temp); | |
3916 | emit_cmp_and_jump_insns (temp, | |
3917 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
3918 | LT, NULL_RTX, VOIDmode, 0, label1); | |
3919 | emit_insn (gen_subtd3 (temp, temp, | |
3920 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
3921 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
3922 | emit_jump (label2); | |
3923 | ||
3924 | emit_label (label1); | |
3925 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
3926 | emit_label (label2); | |
3927 | DONE; | |
3928 | } | |
609e7e80 AK |
3929 | }) |
3930 | ||
3931 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
3932 | [(parallel |
3933 | [(set (match_operand:DI 0 "register_operand" "") | |
3934 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
3935 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) | |
3936 | (clobber (reg:CC CC_REGNUM))])] | |
3937 | ||
fb068247 | 3938 | "TARGET_HARD_DFP" |
609e7e80 | 3939 | { |
65b1d8ea AK |
3940 | if (!TARGET_Z196) |
3941 | { | |
3942 | rtx label1 = gen_label_rtx (); | |
3943 | rtx label2 = gen_label_rtx (); | |
3944 | rtx temp = gen_reg_rtx (TDmode); | |
3945 | REAL_VALUE_TYPE cmp, sub; | |
3946 | ||
3947 | operands[1] = force_reg (TDmode, operands[1]); | |
3948 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3949 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3950 | ||
3951 | emit_cmp_and_jump_insns (operands[1], | |
3952 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
3953 | LT, NULL_RTX, VOIDmode, 0, label1); | |
3954 | emit_insn (gen_subtd3 (temp, operands[1], | |
3955 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
3956 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
3957 | emit_jump (label2); | |
3958 | ||
3959 | emit_label (label1); | |
3960 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
3961 | emit_label (label2); | |
3962 | DONE; | |
3963 | } | |
609e7e80 | 3964 | }) |
cc7ab9b7 | 3965 | |
9db1d521 | 3966 | ; |
65b1d8ea | 3967 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 3968 | ; instruction pattern(s). |
9db1d521 HP |
3969 | ; |
3970 | ||
7b6baae1 | 3971 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
3972 | [(parallel |
3973 | [(set (match_operand:GPR 0 "register_operand" "") | |
3974 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
3975 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
3976 | (clobber (reg:CC CC_REGNUM))])] | |
142cd70f | 3977 | "TARGET_HARD_FLOAT" |
9db1d521 | 3978 | { |
65b1d8ea AK |
3979 | if (!TARGET_Z196) |
3980 | { | |
3981 | rtx label1 = gen_label_rtx (); | |
3982 | rtx label2 = gen_label_rtx (); | |
3983 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
3984 | REAL_VALUE_TYPE cmp, sub; | |
3985 | ||
3986 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
3987 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); | |
3988 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); | |
3989 | ||
3990 | emit_cmp_and_jump_insns (operands[1], | |
3991 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), | |
3992 | LT, NULL_RTX, VOIDmode, 0, label1); | |
3993 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
3994 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); | |
3995 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
3996 | GEN_INT (7))); | |
3997 | emit_jump (label2); | |
3998 | ||
3999 | emit_label (label1); | |
4000 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4001 | operands[1], GEN_INT (5))); | |
4002 | emit_label (label2); | |
4003 | DONE; | |
4004 | } | |
10bbf137 | 4005 | }) |
9db1d521 | 4006 | |
65b1d8ea AK |
4007 | ; fixuns_trunc(td|dd)si2 expander |
4008 | (define_expand "fixuns_trunc<mode>si2" | |
4009 | [(parallel | |
4010 | [(set (match_operand:SI 0 "register_operand" "") | |
4011 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
4012 | (unspec:SI [(const_int 5)] UNSPEC_ROUND) | |
4013 | (clobber (reg:CC CC_REGNUM))])] | |
8540e6e8 | 4014 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4015 | "") |
4016 | ||
4017 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4018 | ||
4019 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr | |
4020 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4021 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
4022 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
4023 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4024 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4025 | (clobber (reg:CC CC_REGNUM))] | |
4026 | "TARGET_Z196" | |
4027 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" | |
4028 | [(set_attr "op_type" "RRF") | |
4029 | (set_attr "type" "ftoi")]) | |
4030 | ||
b60cb710 AK |
4031 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4032 | [(set (match_operand:GPR 0 "register_operand" "") | |
4033 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4034 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4035 | { |
b60cb710 AK |
4036 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
4037 | GEN_INT (5))); | |
9db1d521 | 4038 | DONE; |
10bbf137 | 4039 | }) |
9db1d521 | 4040 | |
43a09b63 | 4041 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
142cd70f | 4042 | (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
2f8f8434 | 4043 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7b6baae1 | 4044 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) |
2f8f8434 | 4045 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) |
ae156f85 | 4046 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4047 | "TARGET_HARD_FLOAT" |
7b6baae1 | 4048 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4049 | [(set_attr "op_type" "RRE") |
077dab3b | 4050 | (set_attr "type" "ftoi")]) |
9db1d521 | 4051 | |
609e7e80 AK |
4052 | |
4053 | ; | |
4054 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4055 | ; | |
4056 | ||
99cd7dd0 AK |
4057 | (define_expand "fix_trunc<mode>di2" |
4058 | [(set (match_operand:DI 0 "register_operand" "") | |
4059 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4060 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4061 | { |
4062 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4063 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
4064 | GEN_INT (9))); | |
4065 | DONE; | |
4066 | }) | |
4067 | ||
609e7e80 | 4068 | ; cgxtr, cgdtr |
99cd7dd0 | 4069 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4070 | [(set (match_operand:DI 0 "register_operand" "=d") |
4071 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4072 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4073 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4074 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4075 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4076 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4077 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4078 | |
4079 | ||
f61a2c7d AK |
4080 | ; |
4081 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4082 | ; | |
4083 | ||
4084 | (define_expand "fix_trunctf<mode>2" | |
4085 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4086 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
4087 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4088 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 4089 | "TARGET_HARD_FLOAT" |
142cd70f | 4090 | "") |
9db1d521 | 4091 | |
9db1d521 | 4092 | |
9db1d521 | 4093 | ; |
142cd70f | 4094 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4095 | ; |
4096 | ||
609e7e80 | 4097 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4098 | (define_insn "floatdi<mode>2" |
609e7e80 AK |
4099 | [(set (match_operand:FP 0 "register_operand" "=f") |
4100 | (float:FP (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 4101 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
609e7e80 | 4102 | "c<xde>g<bt>r\t%0,%1" |
9db1d521 | 4103 | [(set_attr "op_type" "RRE") |
9381e3f1 | 4104 | (set_attr "type" "itof<mode>" )]) |
9db1d521 | 4105 | |
43a09b63 | 4106 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4107 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4108 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4109 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4110 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4111 | "c<xde>fbr\t%0,%1" |
4112 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4113 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4114 | |
65b1d8ea AK |
4115 | ; cxftr, cdftr |
4116 | (define_insn "floatsi<mode>2" | |
4117 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4118 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4119 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4120 | "c<xde>ftr\t%0,0,%1,0" | |
4121 | [(set_attr "op_type" "RRE") | |
4122 | (set_attr "type" "itof<mode>" )]) | |
4123 | ||
4124 | ; | |
4125 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4126 | ; | |
4127 | ||
4128 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr | |
4129 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
4130 | (define_insn "floatuns<GPR:mode><FP:mode>2" | |
4131 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4132 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4133 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4134 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" | |
4135 | [(set_attr "op_type" "RRE") | |
4136 | (set_attr "type" "itof<FP:mode>" )]) | |
f61a2c7d | 4137 | |
9db1d521 HP |
4138 | ; |
4139 | ; truncdfsf2 instruction pattern(s). | |
4140 | ; | |
4141 | ||
142cd70f | 4142 | (define_insn "truncdfsf2" |
9db1d521 | 4143 | [(set (match_operand:SF 0 "register_operand" "=f") |
a036c6f7 | 4144 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
142cd70f | 4145 | "TARGET_HARD_FLOAT" |
d40c829f | 4146 | "ledbr\t%0,%1" |
f61a2c7d AK |
4147 | [(set_attr "op_type" "RRE") |
4148 | (set_attr "type" "ftruncdf")]) | |
9db1d521 | 4149 | |
f61a2c7d | 4150 | ; |
142cd70f | 4151 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4152 | ; |
4153 | ||
142cd70f AK |
4154 | ; ldxbr, lexbr |
4155 | (define_insn "trunctf<mode>2" | |
4156 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4157 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4158 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4159 | "TARGET_HARD_FLOAT" |
4160 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4161 | [(set_attr "length" "6") |
9381e3f1 | 4162 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4163 | |
609e7e80 AK |
4164 | ; |
4165 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4166 | ; | |
4167 | ||
4168 | (define_insn "trunctddd2" | |
4169 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
4170 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4171 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4172 | "TARGET_HARD_DFP" |
bf259a77 AK |
4173 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4174 | [(set_attr "length" "6") | |
9381e3f1 | 4175 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4176 | |
4177 | (define_insn "truncddsd2" | |
4178 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4179 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4180 | "TARGET_HARD_DFP" |
609e7e80 AK |
4181 | "ledtr\t%0,0,%1,0" |
4182 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4183 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4184 | |
9db1d521 | 4185 | ; |
142cd70f | 4186 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4187 | ; |
4188 | ||
142cd70f AK |
4189 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
4190 | (define_insn "extend<DSF:mode><BFP:mode>2" | |
4191 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
4192 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] | |
4193 | "TARGET_HARD_FLOAT | |
4194 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)" | |
f61a2c7d | 4195 | "@ |
142cd70f AK |
4196 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4197 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
f61a2c7d | 4198 | [(set_attr "op_type" "RRE,RXE") |
142cd70f | 4199 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) |
f61a2c7d | 4200 | |
609e7e80 AK |
4201 | ; |
4202 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4203 | ; | |
4204 | ||
4205 | (define_insn "extendddtd2" | |
4206 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4207 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4208 | "TARGET_HARD_DFP" |
609e7e80 AK |
4209 | "lxdtr\t%0,%1,0" |
4210 | [(set_attr "op_type" "RRF") | |
4211 | (set_attr "type" "fsimptf")]) | |
4212 | ||
4213 | (define_insn "extendsddd2" | |
4214 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4215 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4216 | "TARGET_HARD_DFP" |
609e7e80 AK |
4217 | "ldetr\t%0,%1,0" |
4218 | [(set_attr "op_type" "RRF") | |
4219 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4220 | |
35dd9a0e AK |
4221 | ; Binary <-> Decimal floating point trunc patterns |
4222 | ; | |
4223 | ||
4224 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4225 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4226 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4227 | (use (reg:SI GPR0_REGNUM)) | |
4228 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4229 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4230 | "pfpo") |
4231 | ||
4232 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4233 | [(set (reg:BFP FPR0_REGNUM) | |
4234 | (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4235 | (use (reg:SI GPR0_REGNUM)) | |
4236 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4237 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4238 | "pfpo") |
4239 | ||
4240 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
4241 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4242 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4243 | (parallel | |
4244 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4245 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4246 | (use (reg:SI GPR0_REGNUM)) | |
4247 | (clobber (reg:CC CC_REGNUM))]) | |
4248 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4249 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4250 | "TARGET_HARD_DFP |
35dd9a0e AK |
4251 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4252 | { | |
4253 | HOST_WIDE_INT flags; | |
4254 | ||
4255 | flags = (PFPO_CONVERT | | |
4256 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4257 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4258 | ||
4259 | operands[2] = GEN_INT (flags); | |
4260 | }) | |
4261 | ||
4262 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
4263 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4264 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4265 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4266 | (parallel | |
4267 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4268 | (use (reg:SI GPR0_REGNUM)) | |
4269 | (clobber (reg:CC CC_REGNUM))]) | |
4270 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4271 | "TARGET_HARD_DFP |
35dd9a0e AK |
4272 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
4273 | { | |
4274 | HOST_WIDE_INT flags; | |
4275 | ||
4276 | flags = (PFPO_CONVERT | | |
4277 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4278 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4279 | ||
4280 | operands[2] = GEN_INT (flags); | |
4281 | }) | |
4282 | ||
4283 | ; | |
4284 | ; Binary <-> Decimal floating point extend patterns | |
4285 | ; | |
4286 | ||
4287 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
4288 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4289 | (use (reg:SI GPR0_REGNUM)) | |
4290 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4291 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4292 | "pfpo") |
4293 | ||
4294 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
4295 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4296 | (use (reg:SI GPR0_REGNUM)) | |
4297 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4298 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4299 | "pfpo") |
4300 | ||
4301 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
4302 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4303 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4304 | (parallel | |
4305 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4306 | (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4307 | (use (reg:SI GPR0_REGNUM)) | |
4308 | (clobber (reg:CC CC_REGNUM))]) | |
4309 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4310 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4311 | "TARGET_HARD_DFP |
35dd9a0e AK |
4312 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4313 | { | |
4314 | HOST_WIDE_INT flags; | |
4315 | ||
4316 | flags = (PFPO_CONVERT | | |
4317 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4318 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4319 | ||
4320 | operands[2] = GEN_INT (flags); | |
4321 | }) | |
4322 | ||
4323 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
4324 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4325 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4326 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4327 | (parallel | |
4328 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4329 | (use (reg:SI GPR0_REGNUM)) | |
4330 | (clobber (reg:CC CC_REGNUM))]) | |
4331 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4332 | "TARGET_HARD_DFP |
35dd9a0e AK |
4333 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
4334 | { | |
4335 | HOST_WIDE_INT flags; | |
4336 | ||
4337 | flags = (PFPO_CONVERT | | |
4338 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4339 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4340 | ||
4341 | operands[2] = GEN_INT (flags); | |
4342 | }) | |
4343 | ||
4344 | ||
9db1d521 | 4345 | ;; |
fae778eb | 4346 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 4347 | ;; |
fae778eb | 4348 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
4349 | ; because of unpredictable Bits in Register for Halfword and Byte |
4350 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
4351 | ||
07893d4f UW |
4352 | ;; |
4353 | ;;- Add instructions. | |
4354 | ;; | |
4355 | ||
1c7b1b7e UW |
4356 | ; |
4357 | ; addti3 instruction pattern(s). | |
4358 | ; | |
4359 | ||
4360 | (define_insn_and_split "addti3" | |
4361 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4362 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
4363 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4364 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4365 | "TARGET_ZARCH" |
1c7b1b7e UW |
4366 | "#" |
4367 | "&& reload_completed" | |
4368 | [(parallel | |
ae156f85 | 4369 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
4370 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
4371 | (match_dup 7))) | |
4372 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
4373 | (parallel | |
a94a76a7 UW |
4374 | [(set (match_dup 3) (plus:DI |
4375 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4376 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4377 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
4378 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4379 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4380 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4381 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4382 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4383 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4384 | |
07893d4f UW |
4385 | ; |
4386 | ; adddi3 instruction pattern(s). | |
4387 | ; | |
4388 | ||
3298c037 AK |
4389 | (define_expand "adddi3" |
4390 | [(parallel | |
963fc8d0 | 4391 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
4392 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
4393 | (match_operand:DI 2 "general_operand" ""))) | |
4394 | (clobber (reg:CC CC_REGNUM))])] | |
4395 | "" | |
4396 | "") | |
4397 | ||
07893d4f UW |
4398 | (define_insn "*adddi3_sign" |
4399 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4400 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4401 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4402 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4403 | "TARGET_ZARCH" |
07893d4f | 4404 | "@ |
d40c829f UW |
4405 | agfr\t%0,%2 |
4406 | agf\t%0,%2" | |
65b1d8ea AK |
4407 | [(set_attr "op_type" "RRE,RXY") |
4408 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
4409 | |
4410 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 4411 | [(set (reg CC_REGNUM) |
fb492564 | 4412 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4413 | (match_operand:DI 1 "register_operand" "0,0")) |
4414 | (const_int 0))) | |
4415 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4416 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 4417 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4418 | "@ |
d40c829f UW |
4419 | algfr\t%0,%2 |
4420 | algf\t%0,%2" | |
9381e3f1 WG |
4421 | [(set_attr "op_type" "RRE,RXY") |
4422 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4423 | |
4424 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 4425 | [(set (reg CC_REGNUM) |
fb492564 | 4426 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4427 | (match_operand:DI 1 "register_operand" "0,0")) |
4428 | (const_int 0))) | |
4429 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 4430 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4431 | "@ |
d40c829f UW |
4432 | algfr\t%0,%2 |
4433 | algf\t%0,%2" | |
9381e3f1 WG |
4434 | [(set_attr "op_type" "RRE,RXY") |
4435 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4436 | |
4437 | (define_insn "*adddi3_zero" | |
4438 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4439 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4440 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4441 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4442 | "TARGET_ZARCH" |
07893d4f | 4443 | "@ |
d40c829f UW |
4444 | algfr\t%0,%2 |
4445 | algf\t%0,%2" | |
9381e3f1 WG |
4446 | [(set_attr "op_type" "RRE,RXY") |
4447 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 4448 | |
e69166de | 4449 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 4450 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
4451 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
4452 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4453 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4454 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
4455 | "#" |
4456 | "&& reload_completed" | |
4457 | [(parallel | |
ae156f85 | 4458 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
4459 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4460 | (match_dup 7))) | |
4461 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4462 | (parallel | |
a94a76a7 UW |
4463 | [(set (match_dup 3) (plus:SI |
4464 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4465 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4466 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
4467 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4468 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4469 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4470 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4471 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4472 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4473 | |
07893d4f | 4474 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 4475 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 4476 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 4477 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4478 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4479 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4480 | "#" |
4481 | "&& reload_completed" | |
4482 | [(parallel | |
4483 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4484 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4485 | (parallel |
ae156f85 | 4486 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
4487 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4488 | (match_dup 7))) | |
4489 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4490 | (set (pc) | |
ae156f85 | 4491 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4492 | (pc) |
4493 | (label_ref (match_dup 9)))) | |
4494 | (parallel | |
4495 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 4496 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4497 | (match_dup 9)] |
97c6f7ad UW |
4498 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4499 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4500 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4501 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4502 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4503 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4504 | operands[9] = gen_label_rtx ();") |
9db1d521 | 4505 | |
3298c037 AK |
4506 | ; |
4507 | ; addsi3 instruction pattern(s). | |
4508 | ; | |
4509 | ||
4510 | (define_expand "addsi3" | |
07893d4f | 4511 | [(parallel |
963fc8d0 | 4512 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
4513 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
4514 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4515 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4516 | "" |
07893d4f | 4517 | "") |
9db1d521 | 4518 | |
3298c037 AK |
4519 | (define_insn "*addsi3_sign" |
4520 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4521 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
4522 | (match_operand:SI 1 "register_operand" "0,0"))) | |
4523 | (clobber (reg:CC CC_REGNUM))] | |
4524 | "" | |
4525 | "@ | |
4526 | ah\t%0,%2 | |
4527 | ahy\t%0,%2" | |
65b1d8ea AK |
4528 | [(set_attr "op_type" "RX,RXY") |
4529 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 4530 | |
9db1d521 | 4531 | ; |
3298c037 | 4532 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 4533 | ; |
9db1d521 | 4534 | |
65b1d8ea | 4535 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 4536 | (define_insn "*add<mode>3" |
65b1d8ea AK |
4537 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
4538 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
4539 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
4540 | (clobber (reg:CC CC_REGNUM))] |
4541 | "" | |
ec24698e | 4542 | "@ |
3298c037 | 4543 | a<g>r\t%0,%2 |
65b1d8ea | 4544 | a<g>rk\t%0,%1,%2 |
3298c037 | 4545 | a<g>hi\t%0,%h2 |
65b1d8ea | 4546 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
4547 | al<g>fi\t%0,%2 |
4548 | sl<g>fi\t%0,%n2 | |
4549 | a<g>\t%0,%2 | |
963fc8d0 AK |
4550 | a<y>\t%0,%2 |
4551 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4552 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
4553 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
4554 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4555 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 4556 | |
65b1d8ea | 4557 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 4558 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 4559 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4560 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
4561 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 4562 | (match_dup 1))) |
65b1d8ea | 4563 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 4564 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4565 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4566 | "@ |
3298c037 | 4567 | al<g>r\t%0,%2 |
65b1d8ea | 4568 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4569 | al<g>fi\t%0,%2 |
4570 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4571 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4572 | al<g>\t%0,%2 |
963fc8d0 AK |
4573 | al<y>\t%0,%2 |
4574 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4575 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4576 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4577 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4578 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4579 | |
65b1d8ea | 4580 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4581 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 4582 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4583 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4584 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4585 | (match_dup 1))) |
65b1d8ea | 4586 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4587 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4588 | "@ |
3298c037 | 4589 | al<g>r\t%0,%2 |
65b1d8ea | 4590 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4591 | al<g>\t%0,%2 |
4592 | al<y>\t%0,%2" | |
65b1d8ea AK |
4593 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4594 | (set_attr "cpu_facility" "*,z196,*,*") | |
4595 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4596 | |
65b1d8ea | 4597 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4598 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 4599 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4600 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4601 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 4602 | (match_dup 2))) |
65b1d8ea | 4603 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4604 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4605 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4606 | "@ |
3298c037 | 4607 | al<g>r\t%0,%2 |
65b1d8ea | 4608 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4609 | al<g>fi\t%0,%2 |
4610 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4611 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4612 | al<g>\t%0,%2 |
963fc8d0 AK |
4613 | al<y>\t%0,%2 |
4614 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4615 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4616 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4617 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4618 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4619 | |
65b1d8ea | 4620 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4621 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 4622 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4623 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4624 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4625 | (match_dup 2))) |
65b1d8ea | 4626 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4627 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4628 | "@ |
3298c037 | 4629 | al<g>r\t%0,%2 |
65b1d8ea | 4630 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4631 | al<g>\t%0,%2 |
4632 | al<y>\t%0,%2" | |
65b1d8ea AK |
4633 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4634 | (set_attr "cpu_facility" "*,z196,*,*") | |
4635 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4636 | |
65b1d8ea | 4637 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4638 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4639 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4640 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4641 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 4642 | (const_int 0))) |
65b1d8ea | 4643 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4644 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4645 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4646 | "@ |
3298c037 | 4647 | al<g>r\t%0,%2 |
65b1d8ea | 4648 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4649 | al<g>fi\t%0,%2 |
4650 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4651 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4652 | al<g>\t%0,%2 |
963fc8d0 AK |
4653 | al<y>\t%0,%2 |
4654 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4655 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4656 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4657 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4658 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4659 | |
65b1d8ea | 4660 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4661 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4662 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4663 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4664 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 4665 | (const_int 0))) |
65b1d8ea | 4666 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4667 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4668 | "@ |
3298c037 | 4669 | al<g>r\t%0,%2 |
65b1d8ea | 4670 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4671 | al<g>\t%0,%2 |
4672 | al<y>\t%0,%2" | |
65b1d8ea AK |
4673 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4674 | (set_attr "cpu_facility" "*,z196,*,*") | |
4675 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4676 | |
65b1d8ea | 4677 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4678 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 4679 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4680 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4681 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
4682 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 4683 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 4684 | "@ |
3298c037 | 4685 | al<g>r\t%0,%2 |
65b1d8ea | 4686 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4687 | al<g>\t%0,%2 |
4688 | al<y>\t%0,%2" | |
65b1d8ea AK |
4689 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4690 | (set_attr "cpu_facility" "*,z196,*,*") | |
4691 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4692 | |
963fc8d0 | 4693 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
4694 | (define_insn "*add<mode>3_imm_cc" |
4695 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
4696 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
4697 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 4698 | (const_int 0))) |
65b1d8ea | 4699 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
4700 | (plus:GPR (match_dup 1) (match_dup 2)))] |
4701 | "s390_match_ccmode (insn, CCAmode) | |
4702 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
963fc8d0 AK |
4703 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
4704 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) | |
3298c037 | 4705 | && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" |
9db1d521 | 4706 | "@ |
3298c037 | 4707 | a<g>hi\t%0,%h2 |
65b1d8ea | 4708 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
4709 | a<g>fi\t%0,%2 |
4710 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4711 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
4712 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
4713 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4714 | |
9db1d521 | 4715 | ; |
609e7e80 | 4716 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4717 | ; |
4718 | ||
609e7e80 | 4719 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
142cd70f | 4720 | (define_insn "add<mode>3" |
609e7e80 AK |
4721 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4722 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4723 | (match_operand:FP 2 "general_operand" " f,<Rf>"))) | |
ae156f85 | 4724 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4725 | "TARGET_HARD_FLOAT" |
9db1d521 | 4726 | "@ |
609e7e80 | 4727 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4728 | a<xde>b\t%0,%2" |
609e7e80 | 4729 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4730 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4731 | |
609e7e80 | 4732 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4733 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4734 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4735 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4736 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4737 | (match_operand:FP 3 "const0_operand" ""))) | |
4738 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
4739 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 4740 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4741 | "@ |
609e7e80 | 4742 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4743 | a<xde>b\t%0,%2" |
609e7e80 | 4744 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4745 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4746 | |
609e7e80 | 4747 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4748 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4749 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4750 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4751 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4752 | (match_operand:FP 3 "const0_operand" ""))) | |
4753 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 4754 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4755 | "@ |
609e7e80 | 4756 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4757 | a<xde>b\t%0,%2" |
609e7e80 | 4758 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4759 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4760 | |
9db1d521 HP |
4761 | |
4762 | ;; | |
4763 | ;;- Subtract instructions. | |
4764 | ;; | |
4765 | ||
1c7b1b7e UW |
4766 | ; |
4767 | ; subti3 instruction pattern(s). | |
4768 | ; | |
4769 | ||
4770 | (define_insn_and_split "subti3" | |
4771 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4772 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
4773 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4774 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4775 | "TARGET_ZARCH" |
1c7b1b7e UW |
4776 | "#" |
4777 | "&& reload_completed" | |
4778 | [(parallel | |
ae156f85 | 4779 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
4780 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
4781 | (match_dup 7))) | |
4782 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
4783 | (parallel | |
4784 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4785 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4786 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
4787 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4788 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4789 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4790 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4791 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4792 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4793 | |
9db1d521 HP |
4794 | ; |
4795 | ; subdi3 instruction pattern(s). | |
4796 | ; | |
4797 | ||
3298c037 AK |
4798 | (define_expand "subdi3" |
4799 | [(parallel | |
4800 | [(set (match_operand:DI 0 "register_operand" "") | |
4801 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4802 | (match_operand:DI 2 "general_operand" ""))) | |
4803 | (clobber (reg:CC CC_REGNUM))])] | |
4804 | "" | |
4805 | "") | |
4806 | ||
07893d4f UW |
4807 | (define_insn "*subdi3_sign" |
4808 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4809 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4810 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4811 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4812 | "TARGET_ZARCH" |
07893d4f | 4813 | "@ |
d40c829f UW |
4814 | sgfr\t%0,%2 |
4815 | sgf\t%0,%2" | |
9381e3f1 | 4816 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
4817 | (set_attr "z10prop" "z10_c,*") |
4818 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
4819 | |
4820 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 4821 | [(set (reg CC_REGNUM) |
07893d4f | 4822 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4823 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4824 | (const_int 0))) |
4825 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4826 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 4827 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4828 | "@ |
d40c829f UW |
4829 | slgfr\t%0,%2 |
4830 | slgf\t%0,%2" | |
9381e3f1 WG |
4831 | [(set_attr "op_type" "RRE,RXY") |
4832 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4833 | |
4834 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 4835 | [(set (reg CC_REGNUM) |
07893d4f | 4836 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4837 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4838 | (const_int 0))) |
4839 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 4840 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4841 | "@ |
d40c829f UW |
4842 | slgfr\t%0,%2 |
4843 | slgf\t%0,%2" | |
9381e3f1 WG |
4844 | [(set_attr "op_type" "RRE,RXY") |
4845 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4846 | |
4847 | (define_insn "*subdi3_zero" | |
4848 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4849 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4850 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4851 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4852 | "TARGET_ZARCH" |
07893d4f | 4853 | "@ |
d40c829f UW |
4854 | slgfr\t%0,%2 |
4855 | slgf\t%0,%2" | |
9381e3f1 WG |
4856 | [(set_attr "op_type" "RRE,RXY") |
4857 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 4858 | |
e69166de UW |
4859 | (define_insn_and_split "*subdi3_31z" |
4860 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4861 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4862 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4863 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4864 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
4865 | "#" |
4866 | "&& reload_completed" | |
4867 | [(parallel | |
ae156f85 | 4868 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
4869 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4870 | (match_dup 7))) | |
4871 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4872 | (parallel | |
4873 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4874 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4875 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
4876 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4877 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4878 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4879 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4880 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4881 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4882 | |
07893d4f UW |
4883 | (define_insn_and_split "*subdi3_31" |
4884 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4885 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 4886 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4887 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4888 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4889 | "#" |
4890 | "&& reload_completed" | |
4891 | [(parallel | |
4892 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4893 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4894 | (parallel |
ae156f85 | 4895 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
4896 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4897 | (match_dup 7))) | |
4898 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4899 | (set (pc) | |
ae156f85 | 4900 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4901 | (pc) |
4902 | (label_ref (match_dup 9)))) | |
4903 | (parallel | |
4904 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 4905 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4906 | (match_dup 9)] |
97c6f7ad UW |
4907 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4908 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4909 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4910 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4911 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4912 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4913 | operands[9] = gen_label_rtx ();") |
07893d4f | 4914 | |
3298c037 AK |
4915 | ; |
4916 | ; subsi3 instruction pattern(s). | |
4917 | ; | |
4918 | ||
4919 | (define_expand "subsi3" | |
07893d4f | 4920 | [(parallel |
3298c037 AK |
4921 | [(set (match_operand:SI 0 "register_operand" "") |
4922 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
4923 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4924 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4925 | "" |
07893d4f | 4926 | "") |
9db1d521 | 4927 | |
3298c037 AK |
4928 | (define_insn "*subsi3_sign" |
4929 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4930 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4931 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
4932 | (clobber (reg:CC CC_REGNUM))] | |
4933 | "" | |
4934 | "@ | |
4935 | sh\t%0,%2 | |
4936 | shy\t%0,%2" | |
65b1d8ea AK |
4937 | [(set_attr "op_type" "RX,RXY") |
4938 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 4939 | |
9db1d521 | 4940 | ; |
3298c037 | 4941 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
4942 | ; |
4943 | ||
65b1d8ea | 4944 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 4945 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
4946 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
4947 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
4948 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
4949 | (clobber (reg:CC CC_REGNUM))] |
4950 | "" | |
4951 | "@ | |
4952 | s<g>r\t%0,%2 | |
65b1d8ea | 4953 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
4954 | s<g>\t%0,%2 |
4955 | s<y>\t%0,%2" | |
65b1d8ea AK |
4956 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4957 | (set_attr "cpu_facility" "*,z196,*,*") | |
4958 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 4959 | |
65b1d8ea | 4960 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 4961 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 4962 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4963 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
4964 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4965 | (match_dup 1))) |
65b1d8ea | 4966 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 4967 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4968 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4969 | "@ |
3298c037 | 4970 | sl<g>r\t%0,%2 |
65b1d8ea | 4971 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
4972 | sl<g>\t%0,%2 |
4973 | sl<y>\t%0,%2" | |
65b1d8ea AK |
4974 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4975 | (set_attr "cpu_facility" "*,z196,*,*") | |
4976 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4977 | |
65b1d8ea | 4978 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 4979 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 4980 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4981 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
4982 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4983 | (match_dup 1))) |
65b1d8ea | 4984 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 4985 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4986 | "@ |
3298c037 | 4987 | sl<g>r\t%0,%2 |
65b1d8ea | 4988 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
4989 | sl<g>\t%0,%2 |
4990 | sl<y>\t%0,%2" | |
65b1d8ea AK |
4991 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4992 | (set_attr "cpu_facility" "*,z196,*,*") | |
4993 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4994 | |
65b1d8ea | 4995 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 4996 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4997 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4998 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
4999 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5000 | (const_int 0))) |
65b1d8ea | 5001 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5002 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5003 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5004 | "@ |
3298c037 | 5005 | sl<g>r\t%0,%2 |
65b1d8ea | 5006 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5007 | sl<g>\t%0,%2 |
5008 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5009 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5010 | (set_attr "cpu_facility" "*,z196,*,*") | |
5011 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5012 | |
65b1d8ea | 5013 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5014 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5015 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5016 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5017 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5018 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5019 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5020 | "s390_match_ccmode (insn, CCL3mode)" |
5021 | "@ | |
3298c037 | 5022 | sl<g>r\t%0,%2 |
65b1d8ea | 5023 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5024 | sl<g>\t%0,%2 |
5025 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5026 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5027 | (set_attr "cpu_facility" "*,z196,*,*") | |
5028 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5029 | |
65b1d8ea | 5030 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5031 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5032 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5033 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5034 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5035 | (const_int 0))) |
65b1d8ea | 5036 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5037 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5038 | "@ |
3298c037 | 5039 | sl<g>r\t%0,%2 |
65b1d8ea | 5040 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5041 | sl<g>\t%0,%2 |
5042 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5043 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5044 | (set_attr "cpu_facility" "*,z196,*,*") | |
5045 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5046 | |
9db1d521 | 5047 | |
65b1d8ea | 5048 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5049 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5050 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5051 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5052 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5053 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5054 | "s390_match_ccmode (insn, CCL3mode)" |
5055 | "@ | |
3298c037 | 5056 | sl<g>r\t%0,%2 |
65b1d8ea | 5057 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5058 | sl<g>\t%0,%2 |
5059 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5060 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5061 | (set_attr "cpu_facility" "*,z196,*,*") | |
5062 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5063 | |
9db1d521 HP |
5064 | |
5065 | ; | |
609e7e80 | 5066 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5067 | ; |
5068 | ||
d46f24b6 | 5069 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5070 | (define_insn "sub<mode>3" |
609e7e80 AK |
5071 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
5072 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
142cd70f | 5073 | (match_operand:FP 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 5074 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5075 | "TARGET_HARD_FLOAT" |
9db1d521 | 5076 | "@ |
609e7e80 | 5077 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5078 | s<xde>b\t%0,%2" |
609e7e80 | 5079 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5080 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5081 | |
d46f24b6 | 5082 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5083 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5084 | [(set (reg CC_REGNUM) |
609e7e80 | 5085 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 5086 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
5087 | (match_operand:FP 3 "const0_operand" ""))) |
5088 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5089 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5090 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5091 | "@ |
609e7e80 | 5092 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5093 | s<xde>b\t%0,%2" |
609e7e80 | 5094 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5095 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5096 | |
d46f24b6 | 5097 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5098 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5099 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5100 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
5101 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
5102 | (match_operand:FP 3 "const0_operand" ""))) | |
5103 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5104 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5105 | "@ |
609e7e80 | 5106 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5107 | s<xde>b\t%0,%2" |
609e7e80 | 5108 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5109 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5110 | |
9db1d521 | 5111 | |
e69166de UW |
5112 | ;; |
5113 | ;;- Conditional add/subtract instructions. | |
5114 | ;; | |
5115 | ||
5116 | ; | |
9a91a21f | 5117 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
5118 | ; |
5119 | ||
a996720c UW |
5120 | ; the following 4 patterns are used when the result of an add with |
5121 | ; carry is checked for an overflow condition | |
5122 | ||
5123 | ; op1 + op2 + c < op1 | |
5124 | ||
5125 | ; alcr, alc, alcgr, alcg | |
5126 | (define_insn "*add<mode>3_alc_carry1_cc" | |
5127 | [(set (reg CC_REGNUM) | |
5128 | (compare | |
5129 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5130 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5131 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5132 | (match_dup 1))) |
5133 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5134 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5135 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5136 | "@ | |
5137 | alc<g>r\t%0,%2 | |
5138 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5139 | [(set_attr "op_type" "RRE,RXY") |
5140 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5141 | |
5142 | ; alcr, alc, alcgr, alcg | |
5143 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
5144 | [(set (reg CC_REGNUM) | |
5145 | (compare | |
5146 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5147 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5148 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5149 | (match_dup 1))) |
5150 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5151 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5152 | "@ | |
5153 | alc<g>r\t%0,%2 | |
5154 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5155 | [(set_attr "op_type" "RRE,RXY") |
5156 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5157 | |
5158 | ; op1 + op2 + c < op2 | |
5159 | ||
5160 | ; alcr, alc, alcgr, alcg | |
5161 | (define_insn "*add<mode>3_alc_carry2_cc" | |
5162 | [(set (reg CC_REGNUM) | |
5163 | (compare | |
5164 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5165 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5166 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5167 | (match_dup 2))) |
5168 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5169 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5170 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5171 | "@ | |
5172 | alc<g>r\t%0,%2 | |
5173 | alc<g>\t%0,%2" | |
5174 | [(set_attr "op_type" "RRE,RXY")]) | |
5175 | ||
5176 | ; alcr, alc, alcgr, alcg | |
5177 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
5178 | [(set (reg CC_REGNUM) | |
5179 | (compare | |
5180 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5181 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5182 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5183 | (match_dup 2))) |
5184 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5185 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5186 | "@ | |
5187 | alc<g>r\t%0,%2 | |
5188 | alc<g>\t%0,%2" | |
5189 | [(set_attr "op_type" "RRE,RXY")]) | |
5190 | ||
43a09b63 | 5191 | ; alcr, alc, alcgr, alcg |
9a91a21f | 5192 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 5193 | [(set (reg CC_REGNUM) |
e69166de | 5194 | (compare |
a94a76a7 UW |
5195 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5196 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5197 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 5198 | (const_int 0))) |
9a91a21f | 5199 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 5200 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 5201 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5202 | "@ |
9a91a21f AS |
5203 | alc<g>r\t%0,%2 |
5204 | alc<g>\t%0,%2" | |
e69166de UW |
5205 | [(set_attr "op_type" "RRE,RXY")]) |
5206 | ||
43a09b63 | 5207 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
5208 | (define_insn "*add<mode>3_alc" |
5209 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
5210 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5211 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5212 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 5213 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5214 | "TARGET_CPU_ZARCH" |
e69166de | 5215 | "@ |
9a91a21f AS |
5216 | alc<g>r\t%0,%2 |
5217 | alc<g>\t%0,%2" | |
e69166de UW |
5218 | [(set_attr "op_type" "RRE,RXY")]) |
5219 | ||
43a09b63 | 5220 | ; slbr, slb, slbgr, slbg |
9a91a21f | 5221 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 5222 | [(set (reg CC_REGNUM) |
e69166de | 5223 | (compare |
9a91a21f | 5224 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 5225 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5226 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 5227 | (const_int 0))) |
9a91a21f AS |
5228 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
5229 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 5230 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5231 | "@ |
9a91a21f AS |
5232 | slb<g>r\t%0,%2 |
5233 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5234 | [(set_attr "op_type" "RRE,RXY") |
5235 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5236 | |
43a09b63 | 5237 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
5238 | (define_insn "*sub<mode>3_slb" |
5239 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5240 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 5241 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5242 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 5243 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5244 | "TARGET_CPU_ZARCH" |
e69166de | 5245 | "@ |
9a91a21f AS |
5246 | slb<g>r\t%0,%2 |
5247 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5248 | [(set_attr "op_type" "RRE,RXY") |
5249 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5250 | |
9a91a21f AS |
5251 | (define_expand "add<mode>cc" |
5252 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 5253 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
5254 | (match_operand:GPR 2 "register_operand" "") |
5255 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 5256 | "TARGET_CPU_ZARCH" |
9381e3f1 | 5257 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 5258 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 5259 | operands[0], operands[2], |
5d880bd2 UW |
5260 | operands[3])) FAIL; DONE;") |
5261 | ||
5262 | ; | |
5263 | ; scond instruction pattern(s). | |
5264 | ; | |
5265 | ||
9a91a21f AS |
5266 | (define_insn_and_split "*scond<mode>" |
5267 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5268 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 5269 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5270 | "TARGET_CPU_ZARCH" |
5271 | "#" | |
5272 | "&& reload_completed" | |
5273 | [(set (match_dup 0) (const_int 0)) | |
5274 | (parallel | |
a94a76a7 UW |
5275 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
5276 | (match_dup 0))) | |
ae156f85 | 5277 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5278 | "") |
5d880bd2 | 5279 | |
9a91a21f AS |
5280 | (define_insn_and_split "*scond<mode>_neg" |
5281 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5282 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 5283 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5284 | "TARGET_CPU_ZARCH" |
5285 | "#" | |
5286 | "&& reload_completed" | |
5287 | [(set (match_dup 0) (const_int 0)) | |
5288 | (parallel | |
9a91a21f AS |
5289 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
5290 | (match_dup 1))) | |
ae156f85 | 5291 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 5292 | (parallel |
9a91a21f | 5293 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 5294 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5295 | "") |
5d880bd2 | 5296 | |
5d880bd2 | 5297 | |
f90b7a5a | 5298 | (define_expand "cstore<mode>4" |
9a91a21f | 5299 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
5300 | (match_operator:SI 1 "s390_scond_operator" |
5301 | [(match_operand:GPR 2 "register_operand" "") | |
5302 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 5303 | "TARGET_CPU_ZARCH" |
f90b7a5a | 5304 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
5305 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
5306 | ||
f90b7a5a | 5307 | (define_expand "cstorecc4" |
69950452 | 5308 | [(parallel |
f90b7a5a PB |
5309 | [(set (match_operand:SI 0 "register_operand" "") |
5310 | (match_operator:SI 1 "s390_eqne_operator" | |
5311 | [(match_operand:CCZ1 2 "register_operand") | |
5312 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
5313 | (clobber (reg:CC CC_REGNUM))])] |
5314 | "" | |
f90b7a5a PB |
5315 | "emit_insn (gen_sne (operands[0], operands[2])); |
5316 | if (GET_CODE (operands[1]) == EQ) | |
5317 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
5318 | DONE;") | |
69950452 | 5319 | |
f90b7a5a | 5320 | (define_insn_and_split "sne" |
69950452 | 5321 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 5322 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
5323 | (const_int 0))) |
5324 | (clobber (reg:CC CC_REGNUM))] | |
5325 | "" | |
5326 | "#" | |
5327 | "reload_completed" | |
5328 | [(parallel | |
5329 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
5330 | (clobber (reg:CC CC_REGNUM))])]) | |
5331 | ||
e69166de | 5332 | |
65b1d8ea AK |
5333 | ;; |
5334 | ;; - Conditional move instructions (introduced with z196) | |
5335 | ;; | |
5336 | ||
5337 | (define_expand "mov<mode>cc" | |
5338 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
5339 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
5340 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
5341 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
5342 | "TARGET_Z196" | |
5343 | "operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
5344 | XEXP (operands[1], 0), XEXP (operands[1], 1));") | |
5345 | ||
27037b5f | 5346 | ; locr, loc, stoc, locgr, locg, stocg |
65b1d8ea AK |
5347 | (define_insn_and_split "*mov<mode>cc" |
5348 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
5349 | (if_then_else:GPR | |
5350 | (match_operator 1 "s390_comparison" | |
5351 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5352 | (const_int 0)]) | |
5353 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") | |
5354 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
5355 | "TARGET_Z196" | |
5356 | "@ | |
5357 | loc<g>r%C1\t%0,%3 | |
5358 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
5359 | loc<g>%C1\t%0,%3 |
5360 | loc<g>%D1\t%0,%4 | |
5361 | stoc<g>%C1\t%3,%0 | |
5362 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
5363 | #" |
5364 | "&& reload_completed | |
5365 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
5366 | [(set (match_dup 0) | |
5367 | (if_then_else:GPR | |
5368 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5369 | (match_dup 3) | |
5370 | (match_dup 0))) | |
5371 | (set (match_dup 0) | |
5372 | (if_then_else:GPR | |
5373 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5374 | (match_dup 0) | |
5375 | (match_dup 4)))] | |
5376 | "" | |
5377 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
5378 | ||
9db1d521 HP |
5379 | ;; |
5380 | ;;- Multiply instructions. | |
5381 | ;; | |
5382 | ||
4023fb28 UW |
5383 | ; |
5384 | ; muldi3 instruction pattern(s). | |
5385 | ; | |
9db1d521 | 5386 | |
07893d4f UW |
5387 | (define_insn "*muldi3_sign" |
5388 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 5389 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5390 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 5391 | "TARGET_ZARCH" |
07893d4f | 5392 | "@ |
d40c829f UW |
5393 | msgfr\t%0,%2 |
5394 | msgf\t%0,%2" | |
963fc8d0 AK |
5395 | [(set_attr "op_type" "RRE,RXY") |
5396 | (set_attr "type" "imuldi")]) | |
07893d4f | 5397 | |
4023fb28 | 5398 | (define_insn "muldi3" |
963fc8d0 AK |
5399 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
5400 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5401 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 5402 | "TARGET_ZARCH" |
9db1d521 | 5403 | "@ |
d40c829f UW |
5404 | msgr\t%0,%2 |
5405 | mghi\t%0,%h2 | |
963fc8d0 AK |
5406 | msg\t%0,%2 |
5407 | msgfi\t%0,%2" | |
5408 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
5409 | (set_attr "type" "imuldi") | |
5410 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 5411 | |
9db1d521 HP |
5412 | ; |
5413 | ; mulsi3 instruction pattern(s). | |
5414 | ; | |
5415 | ||
f1e77d83 | 5416 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
5417 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
5418 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5419 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 5420 | "" |
963fc8d0 AK |
5421 | "@ |
5422 | mh\t%0,%2 | |
5423 | mhy\t%0,%2" | |
5424 | [(set_attr "op_type" "RX,RXY") | |
5425 | (set_attr "type" "imulhi") | |
5426 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 5427 | |
9db1d521 | 5428 | (define_insn "mulsi3" |
963fc8d0 AK |
5429 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
5430 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5431 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
5432 | "" |
5433 | "@ | |
d40c829f UW |
5434 | msr\t%0,%2 |
5435 | mhi\t%0,%h2 | |
5436 | ms\t%0,%2 | |
963fc8d0 AK |
5437 | msy\t%0,%2 |
5438 | msfi\t%0,%2" | |
5439 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
5440 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
5441 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 5442 | |
4023fb28 UW |
5443 | ; |
5444 | ; mulsidi3 instruction pattern(s). | |
5445 | ; | |
5446 | ||
f1e77d83 | 5447 | (define_insn "mulsidi3" |
963fc8d0 | 5448 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 5449 | (mult:DI (sign_extend:DI |
963fc8d0 | 5450 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 5451 | (sign_extend:DI |
963fc8d0 | 5452 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 5453 | "!TARGET_ZARCH" |
f1e77d83 UW |
5454 | "@ |
5455 | mr\t%0,%2 | |
963fc8d0 AK |
5456 | m\t%0,%2 |
5457 | mfy\t%0,%2" | |
5458 | [(set_attr "op_type" "RR,RX,RXY") | |
5459 | (set_attr "type" "imulsi") | |
5460 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 5461 | |
f1e77d83 | 5462 | ; |
6e0d70c9 | 5463 | ; umul instruction pattern(s). |
f1e77d83 | 5464 | ; |
c7453384 | 5465 | |
6e0d70c9 AK |
5466 | ; mlr, ml, mlgr, mlg |
5467 | (define_insn "umul<dwh><mode>3" | |
5468 | [(set (match_operand:DW 0 "register_operand" "=d, d") | |
5469 | (mult:DW (zero_extend:DW | |
5470 | (match_operand:<DWH> 1 "register_operand" "%0, 0")) | |
5471 | (zero_extend:DW | |
5472 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] | |
5473 | "TARGET_CPU_ZARCH" | |
f1e77d83 | 5474 | "@ |
6e0d70c9 AK |
5475 | ml<tg>r\t%0,%2 |
5476 | ml<tg>\t%0,%2" | |
f1e77d83 | 5477 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 5478 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 5479 | |
9db1d521 | 5480 | ; |
609e7e80 | 5481 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5482 | ; |
5483 | ||
9381e3f1 | 5484 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 5485 | (define_insn "mul<mode>3" |
609e7e80 AK |
5486 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5487 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
5488 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5489 | "TARGET_HARD_FLOAT" |
9db1d521 | 5490 | "@ |
609e7e80 | 5491 | m<xdee><bt>r\t%0,<op1>%2 |
f61a2c7d | 5492 | m<xdee>b\t%0,%2" |
609e7e80 | 5493 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5494 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 5495 | |
9381e3f1 | 5496 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 5497 | (define_insn "fma<mode>4" |
f61a2c7d | 5498 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
d7ecb504 RH |
5499 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5500 | (match_operand:DSF 2 "nonimmediate_operand" "f,R") | |
f61a2c7d | 5501 | (match_operand:DSF 3 "register_operand" "0,0")))] |
d7ecb504 | 5502 | "TARGET_HARD_FLOAT" |
a1b892b5 | 5503 | "@ |
f61a2c7d AK |
5504 | ma<xde>br\t%0,%1,%2 |
5505 | ma<xde>b\t%0,%1,%2" | |
a1b892b5 | 5506 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5507 | (set_attr "type" "fmadd<mode>")]) |
a1b892b5 | 5508 | |
43a09b63 | 5509 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 5510 | (define_insn "fms<mode>4" |
f61a2c7d | 5511 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
d7ecb504 RH |
5512 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5513 | (match_operand:DSF 2 "nonimmediate_operand" "f,R") | |
5514 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))] | |
5515 | "TARGET_HARD_FLOAT" | |
a1b892b5 | 5516 | "@ |
f61a2c7d AK |
5517 | ms<xde>br\t%0,%1,%2 |
5518 | ms<xde>b\t%0,%1,%2" | |
ce50cae8 | 5519 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5520 | (set_attr "type" "fmadd<mode>")]) |
9db1d521 HP |
5521 | |
5522 | ;; | |
5523 | ;;- Divide and modulo instructions. | |
5524 | ;; | |
5525 | ||
5526 | ; | |
4023fb28 | 5527 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
5528 | ; |
5529 | ||
4023fb28 UW |
5530 | (define_expand "divmoddi4" |
5531 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 5532 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
5533 | (match_operand:DI 2 "general_operand" ""))) |
5534 | (set (match_operand:DI 3 "general_operand" "") | |
5535 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
5536 | (clobber (match_dup 4))] | |
9602b6a1 | 5537 | "TARGET_ZARCH" |
9db1d521 | 5538 | { |
f1e77d83 | 5539 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
5540 | |
5541 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
5542 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
5543 | |
5544 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 5545 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
5546 | |
5547 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5548 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5549 | |
5550 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5551 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5552 | |
9db1d521 | 5553 | DONE; |
10bbf137 | 5554 | }) |
9db1d521 HP |
5555 | |
5556 | (define_insn "divmodtidi3" | |
4023fb28 UW |
5557 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
5558 | (ior:TI | |
4023fb28 UW |
5559 | (ashift:TI |
5560 | (zero_extend:TI | |
5665e398 | 5561 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5562 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
5563 | (const_int 64)) |
5564 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 5565 | "TARGET_ZARCH" |
9db1d521 | 5566 | "@ |
d40c829f UW |
5567 | dsgr\t%0,%2 |
5568 | dsg\t%0,%2" | |
d3632d41 | 5569 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5570 | (set_attr "type" "idiv")]) |
9db1d521 | 5571 | |
4023fb28 UW |
5572 | (define_insn "divmodtisi3" |
5573 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5574 | (ior:TI | |
4023fb28 UW |
5575 | (ashift:TI |
5576 | (zero_extend:TI | |
5665e398 | 5577 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 5578 | (sign_extend:DI |
fb492564 | 5579 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
5580 | (const_int 64)) |
5581 | (zero_extend:TI | |
5582 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 5583 | "TARGET_ZARCH" |
4023fb28 | 5584 | "@ |
d40c829f UW |
5585 | dsgfr\t%0,%2 |
5586 | dsgf\t%0,%2" | |
d3632d41 | 5587 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5588 | (set_attr "type" "idiv")]) |
9db1d521 | 5589 | |
4023fb28 UW |
5590 | ; |
5591 | ; udivmoddi4 instruction pattern(s). | |
5592 | ; | |
9db1d521 | 5593 | |
4023fb28 UW |
5594 | (define_expand "udivmoddi4" |
5595 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5596 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
5597 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
5598 | (set (match_operand:DI 3 "general_operand" "") | |
5599 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
5600 | (clobber (match_dup 4))] | |
9602b6a1 | 5601 | "TARGET_ZARCH" |
9db1d521 | 5602 | { |
4023fb28 UW |
5603 | rtx insn, div_equal, mod_equal, equal; |
5604 | ||
5605 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
5606 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
5607 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
5608 | gen_rtx_ASHIFT (TImode, |
5609 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
5610 | GEN_INT (64)), |
5611 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
5612 | |
5613 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 5614 | emit_clobber (operands[4]); |
4023fb28 UW |
5615 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
5616 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 5617 | |
4023fb28 | 5618 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5619 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5620 | |
5621 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5622 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5623 | |
5624 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5625 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5626 | |
9db1d521 | 5627 | DONE; |
10bbf137 | 5628 | }) |
9db1d521 HP |
5629 | |
5630 | (define_insn "udivmodtidi3" | |
4023fb28 | 5631 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 5632 | (ior:TI |
5665e398 UW |
5633 | (ashift:TI |
5634 | (zero_extend:TI | |
5635 | (truncate:DI | |
2f7e5a0d EC |
5636 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
5637 | (zero_extend:TI | |
fb492564 | 5638 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5639 | (const_int 64)) |
5640 | (zero_extend:TI | |
5641 | (truncate:DI | |
5642 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 5643 | "TARGET_ZARCH" |
9db1d521 | 5644 | "@ |
d40c829f UW |
5645 | dlgr\t%0,%2 |
5646 | dlg\t%0,%2" | |
d3632d41 | 5647 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5648 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5649 | |
5650 | ; | |
4023fb28 | 5651 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
5652 | ; |
5653 | ||
4023fb28 UW |
5654 | (define_expand "divmodsi4" |
5655 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5656 | (div:SI (match_operand:SI 1 "general_operand" "") | |
5657 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5658 | (set (match_operand:SI 3 "general_operand" "") | |
5659 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
5660 | (clobber (match_dup 4))] | |
9602b6a1 | 5661 | "!TARGET_ZARCH" |
9db1d521 | 5662 | { |
4023fb28 UW |
5663 | rtx insn, div_equal, mod_equal, equal; |
5664 | ||
5665 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
5666 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
5667 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5668 | gen_rtx_ASHIFT (DImode, |
5669 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5670 | GEN_INT (32)), |
5671 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
5672 | |
5673 | operands[4] = gen_reg_rtx(DImode); | |
5674 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 5675 | |
4023fb28 | 5676 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5677 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5678 | |
5679 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5680 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5681 | |
5682 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5683 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5684 | |
9db1d521 | 5685 | DONE; |
10bbf137 | 5686 | }) |
9db1d521 HP |
5687 | |
5688 | (define_insn "divmoddisi3" | |
4023fb28 | 5689 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 5690 | (ior:DI |
5665e398 UW |
5691 | (ashift:DI |
5692 | (zero_extend:DI | |
5693 | (truncate:SI | |
2f7e5a0d EC |
5694 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
5695 | (sign_extend:DI | |
5665e398 UW |
5696 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
5697 | (const_int 32)) | |
5698 | (zero_extend:DI | |
5699 | (truncate:SI | |
5700 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5701 | "!TARGET_ZARCH" |
9db1d521 | 5702 | "@ |
d40c829f UW |
5703 | dr\t%0,%2 |
5704 | d\t%0,%2" | |
9db1d521 | 5705 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5706 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5707 | |
5708 | ; | |
5709 | ; udivsi3 and umodsi3 instruction pattern(s). | |
5710 | ; | |
5711 | ||
f1e77d83 UW |
5712 | (define_expand "udivmodsi4" |
5713 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5714 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5715 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5716 | (set (match_operand:SI 3 "general_operand" "") | |
5717 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
5718 | (clobber (match_dup 4))] | |
9602b6a1 | 5719 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5720 | { |
5721 | rtx insn, div_equal, mod_equal, equal; | |
5722 | ||
5723 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5724 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5725 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
5726 | gen_rtx_ASHIFT (DImode, |
5727 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5728 | GEN_INT (32)), |
5729 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
5730 | |
5731 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 5732 | emit_clobber (operands[4]); |
f1e77d83 UW |
5733 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
5734 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 5735 | |
f1e77d83 | 5736 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5737 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
5738 | |
5739 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5740 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
5741 | |
5742 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5743 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
5744 | |
5745 | DONE; | |
5746 | }) | |
5747 | ||
5748 | (define_insn "udivmoddisi3" | |
5749 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 5750 | (ior:DI |
5665e398 UW |
5751 | (ashift:DI |
5752 | (zero_extend:DI | |
5753 | (truncate:SI | |
2f7e5a0d EC |
5754 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
5755 | (zero_extend:DI | |
fb492564 | 5756 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5757 | (const_int 32)) |
5758 | (zero_extend:DI | |
5759 | (truncate:SI | |
5760 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5761 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5762 | "@ |
5763 | dlr\t%0,%2 | |
5764 | dl\t%0,%2" | |
5765 | [(set_attr "op_type" "RRE,RXY") | |
5766 | (set_attr "type" "idiv")]) | |
4023fb28 | 5767 | |
9db1d521 HP |
5768 | (define_expand "udivsi3" |
5769 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5770 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
5771 | (match_operand:SI 2 "general_operand" ""))) |
5772 | (clobber (match_dup 3))] | |
9602b6a1 | 5773 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 5774 | { |
4023fb28 UW |
5775 | rtx insn, udiv_equal, umod_equal, equal; |
5776 | ||
5777 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5778 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5779 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5780 | gen_rtx_ASHIFT (DImode, |
5781 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5782 | GEN_INT (32)), |
5783 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5784 | |
4023fb28 | 5785 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5786 | |
5787 | if (CONSTANT_P (operands[2])) | |
5788 | { | |
5789 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
5790 | { | |
5791 | rtx label1 = gen_label_rtx (); | |
5792 | ||
4023fb28 UW |
5793 | operands[1] = make_safe_from (operands[1], operands[0]); |
5794 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5795 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
5796 | SImode, 1, label1); | |
4023fb28 | 5797 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5798 | emit_label (label1); |
5799 | } | |
5800 | else | |
5801 | { | |
c7453384 EC |
5802 | operands[2] = force_reg (SImode, operands[2]); |
5803 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5804 | |
5805 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5806 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5807 | operands[2])); | |
bd94cb6e | 5808 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5809 | |
5810 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5811 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 5812 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
5813 | } |
5814 | } | |
5815 | else | |
c7453384 | 5816 | { |
9db1d521 HP |
5817 | rtx label1 = gen_label_rtx (); |
5818 | rtx label2 = gen_label_rtx (); | |
5819 | rtx label3 = gen_label_rtx (); | |
5820 | ||
c7453384 EC |
5821 | operands[1] = force_reg (SImode, operands[1]); |
5822 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5823 | operands[2] = force_reg (SImode, operands[2]); | |
5824 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5825 | |
5826 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5827 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
5828 | SImode, 1, label3); | |
5829 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
5830 | SImode, 0, label2); | |
5831 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
5832 | SImode, 0, label1); | |
4023fb28 UW |
5833 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5834 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5835 | operands[2])); | |
bd94cb6e | 5836 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5837 | |
5838 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5839 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
5840 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
5841 | ||
f314b9b1 | 5842 | emit_jump (label3); |
9db1d521 | 5843 | emit_label (label1); |
4023fb28 | 5844 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 5845 | emit_jump (label3); |
9db1d521 | 5846 | emit_label (label2); |
4023fb28 | 5847 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5848 | emit_label (label3); |
5849 | } | |
c7453384 | 5850 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 5851 | DONE; |
10bbf137 | 5852 | }) |
9db1d521 HP |
5853 | |
5854 | (define_expand "umodsi3" | |
5855 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5856 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
5857 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
5858 | (clobber (match_dup 3))] | |
9602b6a1 | 5859 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 5860 | { |
4023fb28 UW |
5861 | rtx insn, udiv_equal, umod_equal, equal; |
5862 | ||
5863 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5864 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5865 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5866 | gen_rtx_ASHIFT (DImode, |
5867 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5868 | GEN_INT (32)), |
5869 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5870 | |
4023fb28 | 5871 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5872 | |
5873 | if (CONSTANT_P (operands[2])) | |
5874 | { | |
5875 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
5876 | { | |
5877 | rtx label1 = gen_label_rtx (); | |
5878 | ||
4023fb28 UW |
5879 | operands[1] = make_safe_from (operands[1], operands[0]); |
5880 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
5881 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
5882 | SImode, 1, label1); | |
4023fb28 UW |
5883 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
5884 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
5885 | emit_label (label1); |
5886 | } | |
5887 | else | |
5888 | { | |
c7453384 EC |
5889 | operands[2] = force_reg (SImode, operands[2]); |
5890 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5891 | |
5892 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5893 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5894 | operands[2])); | |
bd94cb6e | 5895 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5896 | |
5897 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5898 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 5899 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
5900 | } |
5901 | } | |
5902 | else | |
5903 | { | |
5904 | rtx label1 = gen_label_rtx (); | |
5905 | rtx label2 = gen_label_rtx (); | |
5906 | rtx label3 = gen_label_rtx (); | |
5907 | ||
c7453384 EC |
5908 | operands[1] = force_reg (SImode, operands[1]); |
5909 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5910 | operands[2] = force_reg (SImode, operands[2]); | |
5911 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5912 | |
c7453384 | 5913 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
5914 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
5915 | SImode, 1, label3); | |
5916 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
5917 | SImode, 0, label2); | |
5918 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
5919 | SImode, 0, label1); | |
4023fb28 UW |
5920 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5921 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5922 | operands[2])); | |
bd94cb6e | 5923 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5924 | |
5925 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5926 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
5927 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
5928 | ||
f314b9b1 | 5929 | emit_jump (label3); |
9db1d521 | 5930 | emit_label (label1); |
4023fb28 | 5931 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5932 | emit_jump (label3); |
9db1d521 | 5933 | emit_label (label2); |
4023fb28 | 5934 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5935 | emit_label (label3); |
5936 | } | |
9db1d521 | 5937 | DONE; |
10bbf137 | 5938 | }) |
9db1d521 HP |
5939 | |
5940 | ; | |
f5905b37 | 5941 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
5942 | ; |
5943 | ||
609e7e80 | 5944 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 5945 | (define_insn "div<mode>3" |
609e7e80 AK |
5946 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5947 | (div:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
5948 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5949 | "TARGET_HARD_FLOAT" |
9db1d521 | 5950 | "@ |
609e7e80 | 5951 | d<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5952 | d<xde>b\t%0,%2" |
609e7e80 | 5953 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5954 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 5955 | |
9db1d521 HP |
5956 | |
5957 | ;; | |
5958 | ;;- And instructions. | |
5959 | ;; | |
5960 | ||
047d35ed AS |
5961 | (define_expand "and<mode>3" |
5962 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5963 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5964 | (match_operand:INT 2 "general_operand" ""))) | |
5965 | (clobber (reg:CC CC_REGNUM))] | |
5966 | "" | |
5967 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
5968 | ||
9db1d521 HP |
5969 | ; |
5970 | ; anddi3 instruction pattern(s). | |
5971 | ; | |
5972 | ||
5973 | (define_insn "*anddi3_cc" | |
ae156f85 | 5974 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5975 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
5976 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
9db1d521 | 5977 | (const_int 0))) |
65b1d8ea | 5978 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
9db1d521 | 5979 | (and:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 5980 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
9db1d521 | 5981 | "@ |
d40c829f | 5982 | ngr\t%0,%2 |
65b1d8ea | 5983 | ngrk\t%0,%1,%2 |
d40c829f | 5984 | ng\t%0,%2" |
65b1d8ea AK |
5985 | [(set_attr "op_type" "RRE,RRF,RXY") |
5986 | (set_attr "cpu_facility" "*,z196,*") | |
5987 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
9db1d521 HP |
5988 | |
5989 | (define_insn "*anddi3_cconly" | |
ae156f85 | 5990 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5991 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
5992 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
9db1d521 | 5993 | (const_int 0))) |
65b1d8ea | 5994 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 5995 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH |
68f9c5e2 UW |
5996 | /* Do not steal TM patterns. */ |
5997 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 5998 | "@ |
d40c829f | 5999 | ngr\t%0,%2 |
65b1d8ea | 6000 | ngrk\t%0,%1,%2 |
d40c829f | 6001 | ng\t%0,%2" |
65b1d8ea AK |
6002 | [(set_attr "op_type" "RRE,RRF,RXY") |
6003 | (set_attr "cpu_facility" "*,z196,*") | |
6004 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
9db1d521 | 6005 | |
3af8e996 | 6006 | (define_insn "*anddi3" |
65b1d8ea AK |
6007 | [(set (match_operand:DI 0 "nonimmediate_operand" |
6008 | "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q") | |
ec24698e | 6009 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
65b1d8ea | 6010 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0") |
ec24698e | 6011 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 6012 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q"))) |
ec24698e | 6013 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6014 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6015 | "@ |
6016 | # | |
6017 | # | |
6018 | nihh\t%0,%j2 | |
6019 | nihl\t%0,%j2 | |
6020 | nilh\t%0,%j2 | |
6021 | nill\t%0,%j2 | |
6022 | nihf\t%0,%m2 | |
6023 | nilf\t%0,%m2 | |
6024 | ngr\t%0,%2 | |
65b1d8ea | 6025 | ngrk\t%0,%1,%2 |
ec24698e UW |
6026 | ng\t%0,%2 |
6027 | # | |
6028 | #" | |
65b1d8ea AK |
6029 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
6030 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
6031 | (set_attr "z10prop" "*, |
6032 | *, | |
6033 | z10_super_E1, | |
6034 | z10_super_E1, | |
6035 | z10_super_E1, | |
6036 | z10_super_E1, | |
6037 | z10_super_E1, | |
6038 | z10_super_E1, | |
6039 | z10_super_E1, | |
65b1d8ea | 6040 | *, |
9381e3f1 WG |
6041 | z10_super_E1, |
6042 | *, | |
6043 | *")]) | |
0dfa6c5e UW |
6044 | |
6045 | (define_split | |
6046 | [(set (match_operand:DI 0 "s_operand" "") | |
6047 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6048 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6049 | "reload_completed" |
6050 | [(parallel | |
6051 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6052 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6053 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6054 | |
9db1d521 HP |
6055 | |
6056 | ; | |
6057 | ; andsi3 instruction pattern(s). | |
6058 | ; | |
6059 | ||
6060 | (define_insn "*andsi3_cc" | |
ae156f85 | 6061 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6062 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6063 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
9db1d521 | 6064 | (const_int 0))) |
65b1d8ea | 6065 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
9db1d521 HP |
6066 | (and:SI (match_dup 1) (match_dup 2)))] |
6067 | "s390_match_ccmode(insn, CCTmode)" | |
6068 | "@ | |
ec24698e | 6069 | nilf\t%0,%o2 |
d40c829f | 6070 | nr\t%0,%2 |
65b1d8ea | 6071 | nrk\t%0,%1,%2 |
d40c829f UW |
6072 | n\t%0,%2 |
6073 | ny\t%0,%2" | |
65b1d8ea AK |
6074 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6075 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6076 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6077 | |
6078 | (define_insn "*andsi3_cconly" | |
ae156f85 | 6079 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6080 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6081 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
9db1d521 | 6082 | (const_int 0))) |
65b1d8ea | 6083 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
68f9c5e2 UW |
6084 | "s390_match_ccmode(insn, CCTmode) |
6085 | /* Do not steal TM patterns. */ | |
6086 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 6087 | "@ |
ec24698e | 6088 | nilf\t%0,%o2 |
d40c829f | 6089 | nr\t%0,%2 |
65b1d8ea | 6090 | nrk\t%0,%1,%2 |
d40c829f UW |
6091 | n\t%0,%2 |
6092 | ny\t%0,%2" | |
65b1d8ea AK |
6093 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6094 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6095 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6096 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6097 | |
f19a9af7 | 6098 | (define_insn "*andsi3_zarch" |
65b1d8ea AK |
6099 | [(set (match_operand:SI 0 "nonimmediate_operand" |
6100 | "=d,d, d, d, d,d,d,d,d, AQ,Q") | |
0dfa6c5e | 6101 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
65b1d8ea | 6102 | "%d,o, 0, 0, 0,0,d,0,0, 0,0") |
0dfa6c5e | 6103 | (match_operand:SI 2 "general_operand" |
65b1d8ea | 6104 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q"))) |
ae156f85 | 6105 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6106 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6107 | "@ |
f19a9af7 AK |
6108 | # |
6109 | # | |
6110 | nilh\t%0,%j2 | |
2f7e5a0d | 6111 | nill\t%0,%j2 |
ec24698e | 6112 | nilf\t%0,%o2 |
d40c829f | 6113 | nr\t%0,%2 |
65b1d8ea | 6114 | nrk\t%0,%1,%2 |
d40c829f | 6115 | n\t%0,%2 |
8cb66696 | 6116 | ny\t%0,%2 |
0dfa6c5e | 6117 | # |
19b63d8e | 6118 | #" |
65b1d8ea AK |
6119 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
6120 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
6121 | (set_attr "z10prop" "*, |
6122 | *, | |
6123 | z10_super_E1, | |
6124 | z10_super_E1, | |
6125 | z10_super_E1, | |
6126 | z10_super_E1, | |
65b1d8ea | 6127 | *, |
9381e3f1 WG |
6128 | z10_super_E1, |
6129 | z10_super_E1, | |
6130 | *, | |
6131 | *")]) | |
f19a9af7 AK |
6132 | |
6133 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
6134 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
6135 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
6136 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 6137 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6138 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6139 | "@ |
6140 | nr\t%0,%2 | |
8cb66696 | 6141 | n\t%0,%2 |
0dfa6c5e | 6142 | # |
19b63d8e | 6143 | #" |
9381e3f1 WG |
6144 | [(set_attr "op_type" "RR,RX,SI,SS") |
6145 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6146 | ||
0dfa6c5e UW |
6147 | |
6148 | (define_split | |
6149 | [(set (match_operand:SI 0 "s_operand" "") | |
6150 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6151 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6152 | "reload_completed" |
6153 | [(parallel | |
6154 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6155 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6156 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6157 | |
9db1d521 HP |
6158 | ; |
6159 | ; andhi3 instruction pattern(s). | |
6160 | ; | |
6161 | ||
8cb66696 | 6162 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
6163 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6164 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6165 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 6166 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6167 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6168 | "@ |
d40c829f | 6169 | nr\t%0,%2 |
65b1d8ea | 6170 | nrk\t%0,%1,%2 |
8cb66696 | 6171 | nill\t%0,%x2 |
0dfa6c5e | 6172 | # |
19b63d8e | 6173 | #" |
65b1d8ea AK |
6174 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6175 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6176 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 6177 | ]) |
8cb66696 UW |
6178 | |
6179 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
6180 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6181 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6182 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 6183 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6184 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6185 | "@ | |
6186 | nr\t%0,%2 | |
0dfa6c5e | 6187 | # |
19b63d8e | 6188 | #" |
9381e3f1 WG |
6189 | [(set_attr "op_type" "RR,SI,SS") |
6190 | (set_attr "z10prop" "z10_super_E1,*,*") | |
6191 | ]) | |
0dfa6c5e UW |
6192 | |
6193 | (define_split | |
6194 | [(set (match_operand:HI 0 "s_operand" "") | |
6195 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6196 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6197 | "reload_completed" |
6198 | [(parallel | |
6199 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6200 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6201 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 6202 | |
9db1d521 HP |
6203 | ; |
6204 | ; andqi3 instruction pattern(s). | |
6205 | ; | |
6206 | ||
8cb66696 | 6207 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
6208 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6209 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6210 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6211 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6212 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6213 | "@ |
d40c829f | 6214 | nr\t%0,%2 |
65b1d8ea | 6215 | nrk\t%0,%1,%2 |
8cb66696 | 6216 | nill\t%0,%b2 |
fc0ea003 UW |
6217 | ni\t%S0,%b2 |
6218 | niy\t%S0,%b2 | |
19b63d8e | 6219 | #" |
65b1d8ea AK |
6220 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6221 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6222 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
6223 | |
6224 | (define_insn "*andqi3_esa" | |
6225 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6226 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6227 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6228 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6229 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6230 | "@ |
8cb66696 | 6231 | nr\t%0,%2 |
fc0ea003 | 6232 | ni\t%S0,%b2 |
19b63d8e | 6233 | #" |
9381e3f1 WG |
6234 | [(set_attr "op_type" "RR,SI,SS") |
6235 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 6236 | |
19b63d8e UW |
6237 | ; |
6238 | ; Block and (NC) patterns. | |
6239 | ; | |
6240 | ||
6241 | (define_insn "*nc" | |
6242 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6243 | (and:BLK (match_dup 0) | |
6244 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6245 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6246 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6247 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6248 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6249 | [(set_attr "op_type" "SS") |
6250 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6251 | |
6252 | (define_split | |
6253 | [(set (match_operand 0 "memory_operand" "") | |
6254 | (and (match_dup 0) | |
6255 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6256 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6257 | "reload_completed |
6258 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6259 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6260 | [(parallel | |
6261 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
6262 | (use (match_dup 2)) | |
ae156f85 | 6263 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6264 | { |
6265 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6266 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6267 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6268 | }) | |
6269 | ||
6270 | (define_peephole2 | |
6271 | [(parallel | |
6272 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6273 | (and:BLK (match_dup 0) | |
6274 | (match_operand:BLK 1 "memory_operand" ""))) | |
6275 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6276 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6277 | (parallel |
6278 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6279 | (and:BLK (match_dup 3) | |
6280 | (match_operand:BLK 4 "memory_operand" ""))) | |
6281 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6282 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6283 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6284 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6285 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6286 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6287 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6288 | [(parallel | |
6289 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
6290 | (use (match_dup 8)) | |
ae156f85 | 6291 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6292 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6293 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6294 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6295 | ||
9db1d521 HP |
6296 | |
6297 | ;; | |
6298 | ;;- Bit set (inclusive or) instructions. | |
6299 | ;; | |
6300 | ||
047d35ed AS |
6301 | (define_expand "ior<mode>3" |
6302 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6303 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6304 | (match_operand:INT 2 "general_operand" ""))) | |
6305 | (clobber (reg:CC CC_REGNUM))] | |
6306 | "" | |
6307 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
6308 | ||
9db1d521 HP |
6309 | ; |
6310 | ; iordi3 instruction pattern(s). | |
6311 | ; | |
6312 | ||
4023fb28 | 6313 | (define_insn "*iordi3_cc" |
ae156f85 | 6314 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6315 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6316 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6317 | (const_int 0))) |
65b1d8ea | 6318 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6319 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6320 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6321 | "@ |
d40c829f | 6322 | ogr\t%0,%2 |
65b1d8ea | 6323 | ogrk\t%0,%1,%2 |
d40c829f | 6324 | og\t%0,%2" |
65b1d8ea AK |
6325 | [(set_attr "op_type" "RRE,RRF,RXY") |
6326 | (set_attr "cpu_facility" "*,z196,*") | |
6327 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
6328 | |
6329 | (define_insn "*iordi3_cconly" | |
ae156f85 | 6330 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6331 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
6332 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6333 | (const_int 0))) |
65b1d8ea | 6334 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 6335 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6336 | "@ |
d40c829f | 6337 | ogr\t%0,%2 |
65b1d8ea | 6338 | ogrk\t%0,%1,%2 |
d40c829f | 6339 | og\t%0,%2" |
65b1d8ea AK |
6340 | [(set_attr "op_type" "RRE,RRF,RXY") |
6341 | (set_attr "cpu_facility" "*,z196,*") | |
6342 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6343 | |
3af8e996 | 6344 | (define_insn "*iordi3" |
65b1d8ea AK |
6345 | [(set (match_operand:DI 0 "nonimmediate_operand" |
6346 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
6347 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
6348 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 6349 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 6350 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 6351 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6352 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6353 | "@ |
6354 | oihh\t%0,%i2 | |
6355 | oihl\t%0,%i2 | |
6356 | oilh\t%0,%i2 | |
6357 | oill\t%0,%i2 | |
6358 | oihf\t%0,%k2 | |
6359 | oilf\t%0,%k2 | |
6360 | ogr\t%0,%2 | |
65b1d8ea | 6361 | ogrk\t%0,%1,%2 |
ec24698e UW |
6362 | og\t%0,%2 |
6363 | # | |
6364 | #" | |
65b1d8ea AK |
6365 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
6366 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
6367 | (set_attr "z10prop" "z10_super_E1, |
6368 | z10_super_E1, | |
6369 | z10_super_E1, | |
6370 | z10_super_E1, | |
6371 | z10_super_E1, | |
6372 | z10_super_E1, | |
6373 | z10_super_E1, | |
65b1d8ea | 6374 | *, |
9381e3f1 WG |
6375 | z10_super_E1, |
6376 | *, | |
6377 | *")]) | |
0dfa6c5e UW |
6378 | |
6379 | (define_split | |
6380 | [(set (match_operand:DI 0 "s_operand" "") | |
6381 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6382 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6383 | "reload_completed" |
6384 | [(parallel | |
6385 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6386 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6387 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6388 | |
9db1d521 HP |
6389 | ; |
6390 | ; iorsi3 instruction pattern(s). | |
6391 | ; | |
6392 | ||
4023fb28 | 6393 | (define_insn "*iorsi3_cc" |
ae156f85 | 6394 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6395 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6396 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6397 | (const_int 0))) |
65b1d8ea | 6398 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6399 | (ior:SI (match_dup 1) (match_dup 2)))] |
6400 | "s390_match_ccmode(insn, CCTmode)" | |
6401 | "@ | |
ec24698e | 6402 | oilf\t%0,%o2 |
d40c829f | 6403 | or\t%0,%2 |
65b1d8ea | 6404 | ork\t%0,%1,%2 |
d40c829f UW |
6405 | o\t%0,%2 |
6406 | oy\t%0,%2" | |
65b1d8ea AK |
6407 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6408 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6409 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6410 | |
6411 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 6412 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6413 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6414 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6415 | (const_int 0))) |
65b1d8ea | 6416 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6417 | "s390_match_ccmode(insn, CCTmode)" |
6418 | "@ | |
ec24698e | 6419 | oilf\t%0,%o2 |
d40c829f | 6420 | or\t%0,%2 |
65b1d8ea | 6421 | ork\t%0,%1,%2 |
d40c829f UW |
6422 | o\t%0,%2 |
6423 | oy\t%0,%2" | |
65b1d8ea AK |
6424 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6425 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6426 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6427 | |
8cb66696 | 6428 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
6429 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
6430 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
6431 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6432 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6433 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6434 | "@ |
f19a9af7 AK |
6435 | oilh\t%0,%i2 |
6436 | oill\t%0,%i2 | |
ec24698e | 6437 | oilf\t%0,%o2 |
d40c829f | 6438 | or\t%0,%2 |
65b1d8ea | 6439 | ork\t%0,%1,%2 |
d40c829f | 6440 | o\t%0,%2 |
8cb66696 | 6441 | oy\t%0,%2 |
0dfa6c5e | 6442 | # |
19b63d8e | 6443 | #" |
65b1d8ea AK |
6444 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
6445 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
6446 | (set_attr "z10prop" "z10_super_E1, |
6447 | z10_super_E1, | |
6448 | z10_super_E1, | |
6449 | z10_super_E1, | |
65b1d8ea | 6450 | *, |
9381e3f1 WG |
6451 | z10_super_E1, |
6452 | z10_super_E1, | |
6453 | *, | |
6454 | *")]) | |
8cb66696 UW |
6455 | |
6456 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 6457 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 6458 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 6459 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 6460 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6461 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6462 | "@ |
6463 | or\t%0,%2 | |
8cb66696 | 6464 | o\t%0,%2 |
0dfa6c5e | 6465 | # |
19b63d8e | 6466 | #" |
9381e3f1 WG |
6467 | [(set_attr "op_type" "RR,RX,SI,SS") |
6468 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6469 | |
6470 | (define_split | |
6471 | [(set (match_operand:SI 0 "s_operand" "") | |
6472 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6473 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6474 | "reload_completed" |
6475 | [(parallel | |
6476 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6477 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6478 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6479 | |
4023fb28 UW |
6480 | ; |
6481 | ; iorhi3 instruction pattern(s). | |
6482 | ; | |
6483 | ||
8cb66696 | 6484 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
6485 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6486 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6487 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 6488 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6489 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6490 | "@ |
d40c829f | 6491 | or\t%0,%2 |
65b1d8ea | 6492 | ork\t%0,%1,%2 |
8cb66696 | 6493 | oill\t%0,%x2 |
0dfa6c5e | 6494 | # |
19b63d8e | 6495 | #" |
65b1d8ea AK |
6496 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6497 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6498 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
6499 | |
6500 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
6501 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6502 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6503 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 6504 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6505 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6506 | "@ | |
6507 | or\t%0,%2 | |
0dfa6c5e | 6508 | # |
19b63d8e | 6509 | #" |
9381e3f1 WG |
6510 | [(set_attr "op_type" "RR,SI,SS") |
6511 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6512 | |
6513 | (define_split | |
6514 | [(set (match_operand:HI 0 "s_operand" "") | |
6515 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6516 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6517 | "reload_completed" |
6518 | [(parallel | |
6519 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6520 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6521 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 6522 | |
9db1d521 | 6523 | ; |
4023fb28 | 6524 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
6525 | ; |
6526 | ||
8cb66696 | 6527 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
6528 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6529 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6530 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6531 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6532 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6533 | "@ |
d40c829f | 6534 | or\t%0,%2 |
65b1d8ea | 6535 | ork\t%0,%1,%2 |
8cb66696 | 6536 | oill\t%0,%b2 |
fc0ea003 UW |
6537 | oi\t%S0,%b2 |
6538 | oiy\t%S0,%b2 | |
19b63d8e | 6539 | #" |
65b1d8ea AK |
6540 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6541 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6542 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
6543 | z10_super,z10_super,*")]) | |
8cb66696 UW |
6544 | |
6545 | (define_insn "*iorqi3_esa" | |
6546 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6547 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6548 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6549 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6550 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6551 | "@ |
8cb66696 | 6552 | or\t%0,%2 |
fc0ea003 | 6553 | oi\t%S0,%b2 |
19b63d8e | 6554 | #" |
9381e3f1 WG |
6555 | [(set_attr "op_type" "RR,SI,SS") |
6556 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 6557 | |
19b63d8e UW |
6558 | ; |
6559 | ; Block inclusive or (OC) patterns. | |
6560 | ; | |
6561 | ||
6562 | (define_insn "*oc" | |
6563 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6564 | (ior:BLK (match_dup 0) | |
6565 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6566 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6567 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6568 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6569 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6570 | [(set_attr "op_type" "SS") |
6571 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6572 | |
6573 | (define_split | |
6574 | [(set (match_operand 0 "memory_operand" "") | |
6575 | (ior (match_dup 0) | |
6576 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6577 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6578 | "reload_completed |
6579 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6580 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6581 | [(parallel | |
6582 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
6583 | (use (match_dup 2)) | |
ae156f85 | 6584 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6585 | { |
6586 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6587 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6588 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6589 | }) | |
6590 | ||
6591 | (define_peephole2 | |
6592 | [(parallel | |
6593 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6594 | (ior:BLK (match_dup 0) | |
6595 | (match_operand:BLK 1 "memory_operand" ""))) | |
6596 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6597 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6598 | (parallel |
6599 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6600 | (ior:BLK (match_dup 3) | |
6601 | (match_operand:BLK 4 "memory_operand" ""))) | |
6602 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6603 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6604 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6605 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6606 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6607 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6608 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6609 | [(parallel | |
6610 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
6611 | (use (match_dup 8)) | |
ae156f85 | 6612 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6613 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6614 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6615 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6616 | ||
9db1d521 HP |
6617 | |
6618 | ;; | |
6619 | ;;- Xor instructions. | |
6620 | ;; | |
6621 | ||
047d35ed AS |
6622 | (define_expand "xor<mode>3" |
6623 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6624 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6625 | (match_operand:INT 2 "general_operand" ""))) | |
6626 | (clobber (reg:CC CC_REGNUM))] | |
6627 | "" | |
6628 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
6629 | ||
9db1d521 HP |
6630 | ; |
6631 | ; xordi3 instruction pattern(s). | |
6632 | ; | |
6633 | ||
4023fb28 | 6634 | (define_insn "*xordi3_cc" |
ae156f85 | 6635 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6636 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6637 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6638 | (const_int 0))) |
65b1d8ea | 6639 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6640 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6641 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6642 | "@ |
d40c829f | 6643 | xgr\t%0,%2 |
65b1d8ea | 6644 | xgrk\t%0,%1,%2 |
d40c829f | 6645 | xg\t%0,%2" |
65b1d8ea | 6646 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 6647 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 6648 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
6649 | |
6650 | (define_insn "*xordi3_cconly" | |
ae156f85 | 6651 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6652 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6653 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6654 | (const_int 0))) |
65b1d8ea | 6655 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 6656 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6657 | "@ |
d40c829f | 6658 | xgr\t%0,%2 |
65b1d8ea | 6659 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 6660 | xg\t%0,%2" |
65b1d8ea AK |
6661 | [(set_attr "op_type" "RRE,RRF,RXY") |
6662 | (set_attr "cpu_facility" "*,z196,*") | |
6663 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6664 | |
3af8e996 | 6665 | (define_insn "*xordi3" |
65b1d8ea AK |
6666 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
6667 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
6668 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 6669 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6670 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6671 | "@ |
6672 | xihf\t%0,%k2 | |
6673 | xilf\t%0,%k2 | |
6674 | xgr\t%0,%2 | |
65b1d8ea | 6675 | xgrk\t%0,%1,%2 |
ec24698e UW |
6676 | xg\t%0,%2 |
6677 | # | |
6678 | #" | |
65b1d8ea AK |
6679 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
6680 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
6681 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
6682 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6683 | |
6684 | (define_split | |
6685 | [(set (match_operand:DI 0 "s_operand" "") | |
6686 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6687 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6688 | "reload_completed" |
6689 | [(parallel | |
6690 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6691 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6692 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 6693 | |
9db1d521 HP |
6694 | ; |
6695 | ; xorsi3 instruction pattern(s). | |
6696 | ; | |
6697 | ||
4023fb28 | 6698 | (define_insn "*xorsi3_cc" |
ae156f85 | 6699 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6700 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6701 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6702 | (const_int 0))) |
65b1d8ea | 6703 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6704 | (xor:SI (match_dup 1) (match_dup 2)))] |
6705 | "s390_match_ccmode(insn, CCTmode)" | |
6706 | "@ | |
ec24698e | 6707 | xilf\t%0,%o2 |
d40c829f | 6708 | xr\t%0,%2 |
65b1d8ea | 6709 | xrk\t%0,%1,%2 |
d40c829f UW |
6710 | x\t%0,%2 |
6711 | xy\t%0,%2" | |
65b1d8ea AK |
6712 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6713 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6714 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6715 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6716 | |
6717 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 6718 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6719 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6720 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6721 | (const_int 0))) |
65b1d8ea | 6722 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6723 | "s390_match_ccmode(insn, CCTmode)" |
6724 | "@ | |
ec24698e | 6725 | xilf\t%0,%o2 |
d40c829f | 6726 | xr\t%0,%2 |
65b1d8ea | 6727 | xrk\t%0,%1,%2 |
d40c829f UW |
6728 | x\t%0,%2 |
6729 | xy\t%0,%2" | |
65b1d8ea AK |
6730 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6731 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6732 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6733 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6734 | |
8cb66696 | 6735 | (define_insn "*xorsi3" |
65b1d8ea AK |
6736 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
6737 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
6738 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6739 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6740 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6741 | "@ |
ec24698e | 6742 | xilf\t%0,%o2 |
d40c829f | 6743 | xr\t%0,%2 |
65b1d8ea | 6744 | xrk\t%0,%1,%2 |
d40c829f | 6745 | x\t%0,%2 |
8cb66696 | 6746 | xy\t%0,%2 |
0dfa6c5e | 6747 | # |
19b63d8e | 6748 | #" |
65b1d8ea AK |
6749 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
6750 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
6751 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6752 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6753 | |
6754 | (define_split | |
6755 | [(set (match_operand:SI 0 "s_operand" "") | |
6756 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6757 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6758 | "reload_completed" |
6759 | [(parallel | |
6760 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6761 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6762 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 6763 | |
9db1d521 HP |
6764 | ; |
6765 | ; xorhi3 instruction pattern(s). | |
6766 | ; | |
6767 | ||
8cb66696 | 6768 | (define_insn "*xorhi3" |
65b1d8ea AK |
6769 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6770 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
6771 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 6772 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6773 | "s390_logical_operator_ok_p (operands)" |
6774 | "@ | |
ec24698e | 6775 | xilf\t%0,%x2 |
8cb66696 | 6776 | xr\t%0,%2 |
65b1d8ea | 6777 | xrk\t%0,%1,%2 |
0dfa6c5e | 6778 | # |
19b63d8e | 6779 | #" |
65b1d8ea AK |
6780 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
6781 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6782 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
6783 | |
6784 | (define_split | |
6785 | [(set (match_operand:HI 0 "s_operand" "") | |
6786 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6787 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6788 | "reload_completed" |
6789 | [(parallel | |
6790 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6791 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6792 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 6793 | |
9db1d521 HP |
6794 | ; |
6795 | ; xorqi3 instruction pattern(s). | |
6796 | ; | |
6797 | ||
8cb66696 | 6798 | (define_insn "*xorqi3" |
65b1d8ea AK |
6799 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6800 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
6801 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 6802 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6803 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6804 | "@ |
ec24698e | 6805 | xilf\t%0,%b2 |
8cb66696 | 6806 | xr\t%0,%2 |
65b1d8ea | 6807 | xrk\t%0,%1,%2 |
fc0ea003 UW |
6808 | xi\t%S0,%b2 |
6809 | xiy\t%S0,%b2 | |
19b63d8e | 6810 | #" |
65b1d8ea AK |
6811 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
6812 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
6813 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 6814 | |
4023fb28 | 6815 | |
19b63d8e UW |
6816 | ; |
6817 | ; Block exclusive or (XC) patterns. | |
6818 | ; | |
6819 | ||
6820 | (define_insn "*xc" | |
6821 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6822 | (xor:BLK (match_dup 0) | |
6823 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6824 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6825 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6826 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6827 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 6828 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6829 | |
6830 | (define_split | |
6831 | [(set (match_operand 0 "memory_operand" "") | |
6832 | (xor (match_dup 0) | |
6833 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6834 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6835 | "reload_completed |
6836 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6837 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6838 | [(parallel | |
6839 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
6840 | (use (match_dup 2)) | |
ae156f85 | 6841 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6842 | { |
6843 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6844 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6845 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6846 | }) | |
6847 | ||
6848 | (define_peephole2 | |
6849 | [(parallel | |
6850 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6851 | (xor:BLK (match_dup 0) | |
6852 | (match_operand:BLK 1 "memory_operand" ""))) | |
6853 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6854 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6855 | (parallel |
6856 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6857 | (xor:BLK (match_dup 3) | |
6858 | (match_operand:BLK 4 "memory_operand" ""))) | |
6859 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6860 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6861 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6862 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6863 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6864 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6865 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6866 | [(parallel | |
6867 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
6868 | (use (match_dup 8)) | |
ae156f85 | 6869 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6870 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6871 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6872 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6873 | ||
6874 | ; | |
6875 | ; Block xor (XC) patterns with src == dest. | |
6876 | ; | |
6877 | ||
6878 | (define_insn "*xc_zero" | |
6879 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6880 | (const_int 0)) | |
6881 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 6882 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6883 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 6884 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
6885 | [(set_attr "op_type" "SS") |
6886 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6887 | |
6888 | (define_peephole2 | |
6889 | [(parallel | |
6890 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6891 | (const_int 0)) | |
6892 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 6893 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6894 | (parallel |
6895 | [(set (match_operand:BLK 2 "memory_operand" "") | |
6896 | (const_int 0)) | |
6897 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 6898 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6899 | "s390_offset_p (operands[0], operands[2], operands[1]) |
6900 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
6901 | [(parallel | |
6902 | [(set (match_dup 4) (const_int 0)) | |
6903 | (use (match_dup 5)) | |
ae156f85 | 6904 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6905 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6906 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
6907 | ||
9db1d521 HP |
6908 | |
6909 | ;; | |
6910 | ;;- Negate instructions. | |
6911 | ;; | |
6912 | ||
6913 | ; | |
9a91a21f | 6914 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
6915 | ; |
6916 | ||
9a91a21f | 6917 | (define_expand "neg<mode>2" |
9db1d521 | 6918 | [(parallel |
9a91a21f AS |
6919 | [(set (match_operand:DSI 0 "register_operand" "=d") |
6920 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 6921 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6922 | "" |
6923 | "") | |
6924 | ||
26a89301 | 6925 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 6926 | [(set (reg CC_REGNUM) |
26a89301 UW |
6927 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6928 | (match_operand:SI 1 "register_operand" "d") 0) | |
6929 | (const_int 32)) (const_int 32))) | |
6930 | (const_int 0))) | |
6931 | (set (match_operand:DI 0 "register_operand" "=d") | |
6932 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 6933 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 6934 | "lcgfr\t%0,%1" |
729e750f WG |
6935 | [(set_attr "op_type" "RRE") |
6936 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 6937 | |
26a89301 UW |
6938 | (define_insn "*negdi2_sign" |
6939 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6940 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 6941 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6942 | "TARGET_ZARCH" |
26a89301 | 6943 | "lcgfr\t%0,%1" |
729e750f WG |
6944 | [(set_attr "op_type" "RRE") |
6945 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6946 | |
43a09b63 | 6947 | ; lcr, lcgr |
9a91a21f | 6948 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 6949 | [(set (reg CC_REGNUM) |
9a91a21f | 6950 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6951 | (const_int 0))) |
9a91a21f AS |
6952 | (set (match_operand:GPR 0 "register_operand" "=d") |
6953 | (neg:GPR (match_dup 1)))] | |
6954 | "s390_match_ccmode (insn, CCAmode)" | |
6955 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6956 | [(set_attr "op_type" "RR<E>") |
6957 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6958 | |
6959 | ; lcr, lcgr | |
9a91a21f | 6960 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 6961 | [(set (reg CC_REGNUM) |
9a91a21f | 6962 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6963 | (const_int 0))) |
9a91a21f AS |
6964 | (clobber (match_scratch:GPR 0 "=d"))] |
6965 | "s390_match_ccmode (insn, CCAmode)" | |
6966 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6967 | [(set_attr "op_type" "RR<E>") |
6968 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6969 | |
6970 | ; lcr, lcgr | |
9a91a21f AS |
6971 | (define_insn "*neg<mode>2" |
6972 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6973 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 6974 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
6975 | "" |
6976 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6977 | [(set_attr "op_type" "RR<E>") |
6978 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 6979 | |
26a89301 | 6980 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
6981 | [(set (match_operand:DI 0 "register_operand" "=d") |
6982 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 6983 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6984 | "!TARGET_ZARCH" |
26a89301 UW |
6985 | "#" |
6986 | "&& reload_completed" | |
6987 | [(parallel | |
6988 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 6989 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 6990 | (parallel |
ae156f85 | 6991 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
6992 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
6993 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
6994 | (set (pc) | |
ae156f85 | 6995 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
6996 | (pc) |
6997 | (label_ref (match_dup 6)))) | |
6998 | (parallel | |
6999 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 7000 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
7001 | (match_dup 6)] |
7002 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7003 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7004 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7005 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7006 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 7007 | |
9db1d521 | 7008 | ; |
f5905b37 | 7009 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7010 | ; |
7011 | ||
f5905b37 | 7012 | (define_expand "neg<mode>2" |
9db1d521 | 7013 | [(parallel |
7b6baae1 AK |
7014 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7015 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7016 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7017 | "TARGET_HARD_FLOAT" |
7018 | "") | |
7019 | ||
43a09b63 | 7020 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7021 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7022 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7023 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7024 | (match_operand:BFP 2 "const0_operand" ""))) | |
7025 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7026 | (neg:BFP (match_dup 1)))] | |
142cd70f | 7027 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7028 | "lc<xde>br\t%0,%1" |
26a89301 | 7029 | [(set_attr "op_type" "RRE") |
f5905b37 | 7030 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7031 | |
7032 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 7033 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7034 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7035 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7036 | (match_operand:BFP 2 "const0_operand" ""))) | |
7037 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7038 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7039 | "lc<xde>br\t%0,%1" |
26a89301 | 7040 | [(set_attr "op_type" "RRE") |
f5905b37 | 7041 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7042 | |
85dae55a AK |
7043 | ; lcdfr |
7044 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
7045 | [(set (match_operand:FP 0 "register_operand" "=f") |
7046 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7047 | "TARGET_DFP" |
85dae55a AK |
7048 | "lcdfr\t%0,%1" |
7049 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7050 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7051 | |
43a09b63 | 7052 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7053 | (define_insn "*neg<mode>2" |
7b6baae1 AK |
7054 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7055 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7056 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7057 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7058 | "lc<xde>br\t%0,%1" |
077dab3b | 7059 | [(set_attr "op_type" "RRE") |
f5905b37 | 7060 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7061 | |
9db1d521 HP |
7062 | |
7063 | ;; | |
7064 | ;;- Absolute value instructions. | |
7065 | ;; | |
7066 | ||
7067 | ; | |
9a91a21f | 7068 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
7069 | ; |
7070 | ||
26a89301 | 7071 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 7072 | [(set (reg CC_REGNUM) |
26a89301 UW |
7073 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7074 | (match_operand:SI 1 "register_operand" "d") 0) | |
7075 | (const_int 32)) (const_int 32))) | |
7076 | (const_int 0))) | |
7077 | (set (match_operand:DI 0 "register_operand" "=d") | |
7078 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7079 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7080 | "lpgfr\t%0,%1" |
729e750f WG |
7081 | [(set_attr "op_type" "RRE") |
7082 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
7083 | |
7084 | (define_insn "*absdi2_sign" | |
7085 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7086 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7087 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7088 | "TARGET_ZARCH" |
26a89301 | 7089 | "lpgfr\t%0,%1" |
729e750f WG |
7090 | [(set_attr "op_type" "RRE") |
7091 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7092 | |
43a09b63 | 7093 | ; lpr, lpgr |
9a91a21f | 7094 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7095 | [(set (reg CC_REGNUM) |
9a91a21f | 7096 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 7097 | (const_int 0))) |
9a91a21f AS |
7098 | (set (match_operand:GPR 0 "register_operand" "=d") |
7099 | (abs:GPR (match_dup 1)))] | |
26a89301 | 7100 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7101 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7102 | [(set_attr "op_type" "RR<E>") |
7103 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 7104 | |
9381e3f1 | 7105 | ; lpr, lpgr |
9a91a21f | 7106 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7107 | [(set (reg CC_REGNUM) |
9a91a21f | 7108 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7109 | (const_int 0))) |
9a91a21f | 7110 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7111 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7112 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7113 | [(set_attr "op_type" "RR<E>") |
7114 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7115 | |
7116 | ; lpr, lpgr | |
9a91a21f AS |
7117 | (define_insn "abs<mode>2" |
7118 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7119 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7120 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 7121 | "" |
9a91a21f | 7122 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7123 | [(set_attr "op_type" "RR<E>") |
7124 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 7125 | |
9db1d521 | 7126 | ; |
f5905b37 | 7127 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7128 | ; |
7129 | ||
f5905b37 | 7130 | (define_expand "abs<mode>2" |
9db1d521 | 7131 | [(parallel |
7b6baae1 AK |
7132 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7133 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7134 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7135 | "TARGET_HARD_FLOAT" |
7136 | "") | |
7137 | ||
43a09b63 | 7138 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7139 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7140 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7141 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7142 | (match_operand:BFP 2 "const0_operand" ""))) | |
7143 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7144 | (abs:BFP (match_dup 1)))] | |
142cd70f | 7145 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7146 | "lp<xde>br\t%0,%1" |
26a89301 | 7147 | [(set_attr "op_type" "RRE") |
f5905b37 | 7148 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7149 | |
7150 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 7151 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7152 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7153 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7154 | (match_operand:BFP 2 "const0_operand" ""))) | |
7155 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7156 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7157 | "lp<xde>br\t%0,%1" |
26a89301 | 7158 | [(set_attr "op_type" "RRE") |
f5905b37 | 7159 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7160 | |
85dae55a AK |
7161 | ; lpdfr |
7162 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
7163 | [(set (match_operand:FP 0 "register_operand" "=f") |
7164 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7165 | "TARGET_DFP" |
85dae55a AK |
7166 | "lpdfr\t%0,%1" |
7167 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7168 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7169 | |
43a09b63 | 7170 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7171 | (define_insn "*abs<mode>2" |
7b6baae1 AK |
7172 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7173 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7174 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7175 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7176 | "lp<xde>br\t%0,%1" |
077dab3b | 7177 | [(set_attr "op_type" "RRE") |
f5905b37 | 7178 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7179 | |
9db1d521 | 7180 | |
3ef093a8 AK |
7181 | ;; |
7182 | ;;- Negated absolute value instructions | |
7183 | ;; | |
7184 | ||
7185 | ; | |
7186 | ; Integer | |
7187 | ; | |
7188 | ||
26a89301 | 7189 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 7190 | [(set (reg CC_REGNUM) |
26a89301 UW |
7191 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7192 | (match_operand:SI 1 "register_operand" "d") 0) | |
7193 | (const_int 32)) (const_int 32)))) | |
7194 | (const_int 0))) | |
7195 | (set (match_operand:DI 0 "register_operand" "=d") | |
7196 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 7197 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7198 | "lngfr\t%0,%1" |
729e750f WG |
7199 | [(set_attr "op_type" "RRE") |
7200 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7201 | |
26a89301 UW |
7202 | (define_insn "*negabsdi2_sign" |
7203 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7204 | (neg:DI (abs:DI (sign_extend:DI | |
7205 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 7206 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7207 | "TARGET_ZARCH" |
26a89301 | 7208 | "lngfr\t%0,%1" |
729e750f WG |
7209 | [(set_attr "op_type" "RRE") |
7210 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 7211 | |
43a09b63 | 7212 | ; lnr, lngr |
9a91a21f | 7213 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7214 | [(set (reg CC_REGNUM) |
9a91a21f | 7215 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7216 | (const_int 0))) |
9a91a21f AS |
7217 | (set (match_operand:GPR 0 "register_operand" "=d") |
7218 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 7219 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7220 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7221 | [(set_attr "op_type" "RR<E>") |
7222 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7223 | |
7224 | ; lnr, lngr | |
9a91a21f | 7225 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7226 | [(set (reg CC_REGNUM) |
9a91a21f | 7227 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7228 | (const_int 0))) |
9a91a21f | 7229 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7230 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7231 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7232 | [(set_attr "op_type" "RR<E>") |
7233 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7234 | |
7235 | ; lnr, lngr | |
9a91a21f AS |
7236 | (define_insn "*negabs<mode>2" |
7237 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7238 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 7239 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 7240 | "" |
9a91a21f | 7241 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7242 | [(set_attr "op_type" "RR<E>") |
7243 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7244 | |
3ef093a8 AK |
7245 | ; |
7246 | ; Floating point | |
7247 | ; | |
7248 | ||
43a09b63 | 7249 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7250 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7251 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7252 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7253 | (match_operand:BFP 2 "const0_operand" ""))) | |
7254 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7255 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 7256 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7257 | "ln<xde>br\t%0,%1" |
26a89301 | 7258 | [(set_attr "op_type" "RRE") |
f5905b37 | 7259 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7260 | |
7261 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 7262 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7263 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7264 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7265 | (match_operand:BFP 2 "const0_operand" ""))) | |
7266 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7267 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7268 | "ln<xde>br\t%0,%1" |
26a89301 | 7269 | [(set_attr "op_type" "RRE") |
f5905b37 | 7270 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7271 | |
85dae55a AK |
7272 | ; lndfr |
7273 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
7274 | [(set (match_operand:FP 0 "register_operand" "=f") |
7275 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 7276 | "TARGET_DFP" |
85dae55a AK |
7277 | "lndfr\t%0,%1" |
7278 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7279 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7280 | |
43a09b63 | 7281 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7282 | (define_insn "*negabs<mode>2" |
7b6baae1 AK |
7283 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7284 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))) | |
ae156f85 | 7285 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7286 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7287 | "ln<xde>br\t%0,%1" |
26a89301 | 7288 | [(set_attr "op_type" "RRE") |
f5905b37 | 7289 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 7290 | |
4023fb28 UW |
7291 | ;; |
7292 | ;;- Square root instructions. | |
7293 | ;; | |
7294 | ||
7295 | ; | |
f5905b37 | 7296 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
7297 | ; |
7298 | ||
9381e3f1 | 7299 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 7300 | (define_insn "sqrt<mode>2" |
7b6baae1 AK |
7301 | [(set (match_operand:BFP 0 "register_operand" "=f,f") |
7302 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 7303 | "TARGET_HARD_FLOAT" |
4023fb28 | 7304 | "@ |
f61a2c7d AK |
7305 | sq<xde>br\t%0,%1 |
7306 | sq<xde>b\t%0,%1" | |
a036c6f7 | 7307 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 7308 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 7309 | |
9db1d521 HP |
7310 | |
7311 | ;; | |
7312 | ;;- One complement instructions. | |
7313 | ;; | |
7314 | ||
7315 | ; | |
342cf42b | 7316 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 7317 | ; |
c7453384 | 7318 | |
342cf42b | 7319 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 7320 | [(parallel |
342cf42b AS |
7321 | [(set (match_operand:INT 0 "register_operand" "") |
7322 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
7323 | (const_int -1))) | |
ae156f85 | 7324 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 7325 | "" |
4023fb28 | 7326 | "") |
9db1d521 HP |
7327 | |
7328 | ||
ec24698e UW |
7329 | ;; |
7330 | ;; Find leftmost bit instructions. | |
7331 | ;; | |
7332 | ||
7333 | (define_expand "clzdi2" | |
7334 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7335 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 7336 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7337 | { |
7338 | rtx insn, clz_equal; | |
7339 | rtx wide_reg = gen_reg_rtx (TImode); | |
7340 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
7341 | ||
7342 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
7343 | ||
7344 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
7345 | ||
9381e3f1 | 7346 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 7347 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
7348 | |
7349 | DONE; | |
7350 | }) | |
7351 | ||
7352 | (define_insn "clztidi2" | |
7353 | [(set (match_operand:TI 0 "register_operand" "=d") | |
7354 | (ior:TI | |
9381e3f1 WG |
7355 | (ashift:TI |
7356 | (zero_extend:TI | |
ec24698e UW |
7357 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
7358 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
7359 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 7360 | |
ec24698e UW |
7361 | (const_int 64)) |
7362 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
7363 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 7364 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 7365 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 7366 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7367 | "flogr\t%0,%1" |
7368 | [(set_attr "op_type" "RRE")]) | |
7369 | ||
7370 | ||
9db1d521 HP |
7371 | ;; |
7372 | ;;- Rotate instructions. | |
7373 | ;; | |
7374 | ||
7375 | ; | |
9a91a21f | 7376 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
7377 | ; |
7378 | ||
43a09b63 | 7379 | ; rll, rllg |
9a91a21f AS |
7380 | (define_insn "rotl<mode>3" |
7381 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7382 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 7383 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 7384 | "TARGET_CPU_ZARCH" |
9a91a21f | 7385 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 7386 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
7387 | (set_attr "atype" "reg") |
7388 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7389 | |
43a09b63 | 7390 | ; rll, rllg |
4989e88a AK |
7391 | (define_insn "*rotl<mode>3_and" |
7392 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7393 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7394 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7395 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7396 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
7397 | "rll<g>\t%0,%1,%Y2" | |
7398 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
7399 | (set_attr "atype" "reg") |
7400 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7401 | |
9db1d521 HP |
7402 | |
7403 | ;; | |
f337b930 | 7404 | ;;- Shift instructions. |
9db1d521 | 7405 | ;; |
9db1d521 HP |
7406 | |
7407 | ; | |
1b48c8cc | 7408 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 7409 | ; Left shifts and logical right shifts |
9db1d521 | 7410 | |
1b48c8cc AS |
7411 | (define_expand "<shift><mode>3" |
7412 | [(set (match_operand:DSI 0 "register_operand" "") | |
7413 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
7414 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
7415 | "" |
7416 | "") | |
7417 | ||
43a09b63 | 7418 | ; sldl, srdl |
f337b930 | 7419 | (define_insn "*<shift>di3_31" |
ac32b25e | 7420 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 7421 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7422 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9602b6a1 | 7423 | "!TARGET_ZARCH" |
f337b930 | 7424 | "s<lr>dl\t%0,%Y2" |
077dab3b | 7425 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
7426 | (set_attr "atype" "reg") |
7427 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 7428 | |
65b1d8ea | 7429 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7430 | (define_insn "*<shift><mode>3" |
65b1d8ea AK |
7431 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7432 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7433 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] | |
1b48c8cc | 7434 | "" |
65b1d8ea AK |
7435 | "@ |
7436 | s<lr>l<g>\t%0,<1>%Y2 | |
7437 | s<lr>l<gk>\t%0,%1,%Y2" | |
7438 | [(set_attr "op_type" "RS<E>,RSY") | |
7439 | (set_attr "atype" "reg,reg") | |
7440 | (set_attr "cpu_facility" "*,z196") | |
7441 | (set_attr "z10prop" "z10_super_E1,*")]) | |
9db1d521 | 7442 | |
43a09b63 | 7443 | ; sldl, srdl |
4989e88a AK |
7444 | (define_insn "*<shift>di3_31_and" |
7445 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7446 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7447 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7448 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
9602b6a1 | 7449 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7450 | "s<lr>dl\t%0,%Y2" |
7451 | [(set_attr "op_type" "RS") | |
7452 | (set_attr "atype" "reg")]) | |
7453 | ||
65b1d8ea | 7454 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7455 | (define_insn "*<shift><mode>3_and" |
65b1d8ea AK |
7456 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7457 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7458 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7459 | (match_operand:SI 3 "const_int_operand" "n,n"))))] | |
1b48c8cc | 7460 | "(INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7461 | "@ |
7462 | s<lr>l<g>\t%0,<1>%Y2 | |
7463 | s<lr>l<gk>\t%0,%1,%Y2" | |
7464 | [(set_attr "op_type" "RS<E>,RSY") | |
7465 | (set_attr "atype" "reg,reg") | |
7466 | (set_attr "cpu_facility" "*,z196") | |
7467 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7468 | |
9db1d521 | 7469 | ; |
1b48c8cc | 7470 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 7471 | ; Arithmetic right shifts |
9db1d521 | 7472 | |
1b48c8cc | 7473 | (define_expand "ashr<mode>3" |
9db1d521 | 7474 | [(parallel |
1b48c8cc AS |
7475 | [(set (match_operand:DSI 0 "register_operand" "") |
7476 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
7477 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 7478 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7479 | "" |
7480 | "") | |
7481 | ||
ecbe845e | 7482 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 7483 | [(set (reg CC_REGNUM) |
ac32b25e | 7484 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7485 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7486 | (const_int 0))) |
ac32b25e | 7487 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e | 7488 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7489 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7490 | "srda\t%0,%Y2" |
077dab3b HP |
7491 | [(set_attr "op_type" "RS") |
7492 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
7493 | |
7494 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 7495 | [(set (reg CC_REGNUM) |
ac32b25e | 7496 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7497 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7498 | (const_int 0))) |
ac32b25e | 7499 | (clobber (match_scratch:DI 0 "=d"))] |
9602b6a1 | 7500 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7501 | "srda\t%0,%Y2" |
077dab3b HP |
7502 | [(set_attr "op_type" "RS") |
7503 | (set_attr "atype" "reg")]) | |
ecbe845e | 7504 | |
9db1d521 | 7505 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
7506 | [(set (match_operand:DI 0 "register_operand" "=d") |
7507 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 7508 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 7509 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7510 | "!TARGET_ZARCH" |
ac32b25e | 7511 | "srda\t%0,%Y2" |
077dab3b HP |
7512 | [(set_attr "op_type" "RS") |
7513 | (set_attr "atype" "reg")]) | |
c7453384 | 7514 | |
65b1d8ea | 7515 | ; sra, srag, srak |
1b48c8cc | 7516 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 7517 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7518 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7519 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7520 | (const_int 0))) |
65b1d8ea | 7521 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc AS |
7522 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] |
7523 | "s390_match_ccmode(insn, CCSmode)" | |
65b1d8ea AK |
7524 | "@ |
7525 | sra<g>\t%0,<1>%Y2 | |
7526 | sra<gk>\t%0,%1,%Y2" | |
7527 | [(set_attr "op_type" "RS<E>,RSY") | |
7528 | (set_attr "atype" "reg,reg") | |
7529 | (set_attr "cpu_facility" "*,z196") | |
7530 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7531 | |
65b1d8ea | 7532 | ; sra, srag, srak |
1b48c8cc | 7533 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 7534 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7535 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7536 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7537 | (const_int 0))) |
65b1d8ea | 7538 | (clobber (match_scratch:GPR 0 "=d,d"))] |
1b48c8cc | 7539 | "s390_match_ccmode(insn, CCSmode)" |
65b1d8ea AK |
7540 | "@ |
7541 | sra<g>\t%0,<1>%Y2 | |
7542 | sra<gk>\t%0,%1,%Y2" | |
7543 | [(set_attr "op_type" "RS<E>,RSY") | |
7544 | (set_attr "atype" "reg,reg") | |
7545 | (set_attr "cpu_facility" "*,z196") | |
7546 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7547 | |
43a09b63 | 7548 | ; sra, srag |
1b48c8cc | 7549 | (define_insn "*ashr<mode>3" |
65b1d8ea AK |
7550 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7551 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7552 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) | |
ae156f85 | 7553 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 7554 | "" |
65b1d8ea AK |
7555 | "@ |
7556 | sra<g>\t%0,<1>%Y2 | |
7557 | sra<gk>\t%0,%1,%Y2" | |
7558 | [(set_attr "op_type" "RS<E>,RSY") | |
7559 | (set_attr "atype" "reg,reg") | |
7560 | (set_attr "cpu_facility" "*,z196") | |
7561 | (set_attr "z10prop" "z10_super_E1,*")]) | |
077dab3b | 7562 | |
9db1d521 | 7563 | |
4989e88a AK |
7564 | ; shift pattern with implicit ANDs |
7565 | ||
7566 | (define_insn "*ashrdi3_cc_31_and" | |
7567 | [(set (reg CC_REGNUM) | |
7568 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7569 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7570 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7571 | (const_int 0))) | |
7572 | (set (match_operand:DI 0 "register_operand" "=d") | |
7573 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
9602b6a1 | 7574 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7575 | && (INTVAL (operands[3]) & 63) == 63" |
7576 | "srda\t%0,%Y2" | |
7577 | [(set_attr "op_type" "RS") | |
7578 | (set_attr "atype" "reg")]) | |
7579 | ||
7580 | (define_insn "*ashrdi3_cconly_31_and" | |
7581 | [(set (reg CC_REGNUM) | |
7582 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7583 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7584 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7585 | (const_int 0))) | |
7586 | (clobber (match_scratch:DI 0 "=d"))] | |
9602b6a1 | 7587 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7588 | && (INTVAL (operands[3]) & 63) == 63" |
7589 | "srda\t%0,%Y2" | |
7590 | [(set_attr "op_type" "RS") | |
7591 | (set_attr "atype" "reg")]) | |
7592 | ||
7593 | (define_insn "*ashrdi3_31_and" | |
7594 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7595 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7596 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7597 | (match_operand:SI 3 "const_int_operand" "n")))) | |
7598 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 7599 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7600 | "srda\t%0,%Y2" |
7601 | [(set_attr "op_type" "RS") | |
7602 | (set_attr "atype" "reg")]) | |
7603 | ||
65b1d8ea | 7604 | ; sra, srag, srak |
1b48c8cc | 7605 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 7606 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7607 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7608 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7609 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7610 | (const_int 0))) |
65b1d8ea | 7611 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc | 7612 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] |
4989e88a | 7613 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7614 | "@ |
7615 | sra<g>\t%0,<1>%Y2 | |
7616 | sra<gk>\t%0,%1,%Y2" | |
7617 | [(set_attr "op_type" "RS<E>,RSY") | |
7618 | (set_attr "atype" "reg,reg") | |
7619 | (set_attr "cpu_facility" "*,z196") | |
7620 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7621 | |
65b1d8ea | 7622 | ; sra, srag, srak |
1b48c8cc | 7623 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 7624 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7625 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7626 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7627 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7628 | (const_int 0))) |
65b1d8ea | 7629 | (clobber (match_scratch:GPR 0 "=d,d"))] |
4989e88a | 7630 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7631 | "@ |
7632 | sra<g>\t%0,<1>%Y2 | |
7633 | sra<gk>\t%0,%1,%Y2" | |
7634 | [(set_attr "op_type" "RS<E>,RSY") | |
7635 | (set_attr "atype" "reg,reg") | |
7636 | (set_attr "cpu_facility" "*,z196") | |
7637 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7638 | |
65b1d8ea | 7639 | ; sra, srag, srak |
1b48c8cc | 7640 | (define_insn "*ashr<mode>3_and" |
65b1d8ea AK |
7641 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7642 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7643 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7644 | (match_operand:SI 3 "const_int_operand" "n,n")))) | |
4989e88a AK |
7645 | (clobber (reg:CC CC_REGNUM))] |
7646 | "(INTVAL (operands[3]) & 63) == 63" | |
65b1d8ea AK |
7647 | "@ |
7648 | sra<g>\t%0,<1>%Y2 | |
7649 | sra<gk>\t%0,%1,%Y2" | |
7650 | [(set_attr "op_type" "RS<E>,RSY") | |
7651 | (set_attr "atype" "reg,reg") | |
01496eca | 7652 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 7653 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 7654 | |
9db1d521 | 7655 | |
9db1d521 HP |
7656 | ;; |
7657 | ;; Branch instruction patterns. | |
7658 | ;; | |
7659 | ||
f90b7a5a | 7660 | (define_expand "cbranch<mode>4" |
fa77b251 | 7661 | [(set (pc) |
f90b7a5a PB |
7662 | (if_then_else (match_operator 0 "comparison_operator" |
7663 | [(match_operand:GPR 1 "register_operand" "") | |
7664 | (match_operand:GPR 2 "general_operand" "")]) | |
7665 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 7666 | (pc)))] |
ba956982 | 7667 | "" |
f90b7a5a PB |
7668 | "s390_emit_jump (operands[3], |
7669 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7670 | DONE;") | |
7671 | ||
7672 | (define_expand "cbranch<mode>4" | |
7673 | [(set (pc) | |
7674 | (if_then_else (match_operator 0 "comparison_operator" | |
7675 | [(match_operand:FP 1 "register_operand" "") | |
7676 | (match_operand:FP 2 "general_operand" "")]) | |
7677 | (label_ref (match_operand 3 "" "")) | |
7678 | (pc)))] | |
7679 | "TARGET_HARD_FLOAT" | |
7680 | "s390_emit_jump (operands[3], | |
7681 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7682 | DONE;") | |
7683 | ||
7684 | (define_expand "cbranchcc4" | |
7685 | [(set (pc) | |
7686 | (if_then_else (match_operator 0 "s390_eqne_operator" | |
7687 | [(match_operand 1 "cc_reg_operand" "") | |
7688 | (match_operand 2 "const0_operand" "")]) | |
7689 | (label_ref (match_operand 3 "" "")) | |
7690 | (pc)))] | |
7691 | "TARGET_HARD_FLOAT" | |
7692 | "s390_emit_jump (operands[3], | |
7693 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7694 | DONE;") | |
7695 | ||
ba956982 | 7696 | |
9db1d521 HP |
7697 | |
7698 | ;; | |
7699 | ;;- Conditional jump instructions. | |
7700 | ;; | |
7701 | ||
6590e19a UW |
7702 | (define_insn "*cjump_64" |
7703 | [(set (pc) | |
7704 | (if_then_else | |
ae156f85 | 7705 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7706 | (label_ref (match_operand 0 "" "")) |
7707 | (pc)))] | |
7708 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7709 | { |
13e58269 | 7710 | if (get_attr_length (insn) == 4) |
d40c829f | 7711 | return "j%C1\t%l0"; |
6590e19a | 7712 | else |
d40c829f | 7713 | return "jg%C1\t%l0"; |
6590e19a UW |
7714 | } |
7715 | [(set_attr "op_type" "RI") | |
7716 | (set_attr "type" "branch") | |
7717 | (set (attr "length") | |
7718 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7719 | (const_int 4) (const_int 6)))]) | |
7720 | ||
7721 | (define_insn "*cjump_31" | |
7722 | [(set (pc) | |
7723 | (if_then_else | |
ae156f85 | 7724 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7725 | (label_ref (match_operand 0 "" "")) |
7726 | (pc)))] | |
7727 | "!TARGET_CPU_ZARCH" | |
7728 | { | |
8d933e31 AS |
7729 | gcc_assert (get_attr_length (insn) == 4); |
7730 | return "j%C1\t%l0"; | |
10bbf137 | 7731 | } |
9db1d521 | 7732 | [(set_attr "op_type" "RI") |
077dab3b | 7733 | (set_attr "type" "branch") |
13e58269 | 7734 | (set (attr "length") |
d7f99b2c | 7735 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
7736 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
7737 | (const_int 4) (const_int 6)) | |
7738 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7739 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7740 | |
f314b9b1 | 7741 | (define_insn "*cjump_long" |
6590e19a UW |
7742 | [(set (pc) |
7743 | (if_then_else | |
ae156f85 | 7744 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 7745 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 7746 | (pc)))] |
9db1d521 | 7747 | "" |
f314b9b1 UW |
7748 | { |
7749 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7750 | return "b%C1r\t%0"; |
f314b9b1 | 7751 | else |
d40c829f | 7752 | return "b%C1\t%a0"; |
10bbf137 | 7753 | } |
c7453384 | 7754 | [(set (attr "op_type") |
f314b9b1 UW |
7755 | (if_then_else (match_operand 0 "register_operand" "") |
7756 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 7757 | (set_attr "type" "branch") |
077dab3b | 7758 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7759 | |
7760 | ||
7761 | ;; | |
7762 | ;;- Negated conditional jump instructions. | |
7763 | ;; | |
7764 | ||
6590e19a UW |
7765 | (define_insn "*icjump_64" |
7766 | [(set (pc) | |
7767 | (if_then_else | |
ae156f85 | 7768 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7769 | (pc) |
7770 | (label_ref (match_operand 0 "" ""))))] | |
7771 | "TARGET_CPU_ZARCH" | |
c7453384 | 7772 | { |
13e58269 | 7773 | if (get_attr_length (insn) == 4) |
d40c829f | 7774 | return "j%D1\t%l0"; |
6590e19a | 7775 | else |
d40c829f | 7776 | return "jg%D1\t%l0"; |
6590e19a UW |
7777 | } |
7778 | [(set_attr "op_type" "RI") | |
7779 | (set_attr "type" "branch") | |
7780 | (set (attr "length") | |
7781 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7782 | (const_int 4) (const_int 6)))]) | |
7783 | ||
7784 | (define_insn "*icjump_31" | |
7785 | [(set (pc) | |
7786 | (if_then_else | |
ae156f85 | 7787 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7788 | (pc) |
7789 | (label_ref (match_operand 0 "" ""))))] | |
7790 | "!TARGET_CPU_ZARCH" | |
7791 | { | |
8d933e31 AS |
7792 | gcc_assert (get_attr_length (insn) == 4); |
7793 | return "j%D1\t%l0"; | |
10bbf137 | 7794 | } |
9db1d521 | 7795 | [(set_attr "op_type" "RI") |
077dab3b | 7796 | (set_attr "type" "branch") |
13e58269 | 7797 | (set (attr "length") |
d7f99b2c | 7798 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
7799 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
7800 | (const_int 4) (const_int 6)) | |
7801 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7802 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7803 | |
f314b9b1 | 7804 | (define_insn "*icjump_long" |
6590e19a UW |
7805 | [(set (pc) |
7806 | (if_then_else | |
ae156f85 | 7807 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 7808 | (pc) |
4fe6dea8 | 7809 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 7810 | "" |
f314b9b1 UW |
7811 | { |
7812 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7813 | return "b%D1r\t%0"; |
f314b9b1 | 7814 | else |
d40c829f | 7815 | return "b%D1\t%a0"; |
10bbf137 | 7816 | } |
c7453384 | 7817 | [(set (attr "op_type") |
f314b9b1 UW |
7818 | (if_then_else (match_operand 0 "register_operand" "") |
7819 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7820 | (set_attr "type" "branch") |
7821 | (set_attr "atype" "agen")]) | |
9db1d521 | 7822 | |
4456530d HP |
7823 | ;; |
7824 | ;;- Trap instructions. | |
7825 | ;; | |
7826 | ||
7827 | (define_insn "trap" | |
7828 | [(trap_if (const_int 1) (const_int 0))] | |
7829 | "" | |
d40c829f | 7830 | "j\t.+2" |
6590e19a | 7831 | [(set_attr "op_type" "RI") |
077dab3b | 7832 | (set_attr "type" "branch")]) |
4456530d | 7833 | |
f90b7a5a PB |
7834 | (define_expand "ctrap<mode>4" |
7835 | [(trap_if (match_operator 0 "comparison_operator" | |
7836 | [(match_operand:GPR 1 "register_operand" "") | |
7837 | (match_operand:GPR 2 "general_operand" "")]) | |
7838 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 7839 | "" |
f90b7a5a PB |
7840 | { |
7841 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
7842 | operands[1], operands[2]); | |
7843 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
7844 | DONE; | |
7845 | }) | |
7846 | ||
7847 | (define_expand "ctrap<mode>4" | |
7848 | [(trap_if (match_operator 0 "comparison_operator" | |
7849 | [(match_operand:FP 1 "register_operand" "") | |
7850 | (match_operand:FP 2 "general_operand" "")]) | |
7851 | (match_operand 3 "const0_operand" ""))] | |
7852 | "" | |
7853 | { | |
7854 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
7855 | operands[1], operands[2]); | |
7856 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
7857 | DONE; | |
7858 | }) | |
4456530d | 7859 | |
f90b7a5a PB |
7860 | (define_insn "condtrap" |
7861 | [(trap_if (match_operator 0 "s390_comparison" | |
7862 | [(match_operand 1 "cc_reg_operand" "c") | |
7863 | (const_int 0)]) | |
4456530d HP |
7864 | (const_int 0))] |
7865 | "" | |
d40c829f | 7866 | "j%C0\t.+2"; |
077dab3b HP |
7867 | [(set_attr "op_type" "RI") |
7868 | (set_attr "type" "branch")]) | |
9db1d521 | 7869 | |
963fc8d0 AK |
7870 | ; crt, cgrt, cit, cgit |
7871 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
7872 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
7873 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7874 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
7875 | (const_int 0))] | |
7876 | "TARGET_Z10" | |
7877 | "@ | |
7878 | c<g>rt%C0\t%1,%2 | |
7879 | c<g>it%C0\t%1,%h2" | |
7880 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7881 | (set_attr "type" "branch") |
729e750f | 7882 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 AK |
7883 | |
7884 | ; clrt, clgrt, clfit, clgit | |
7885 | (define_insn "*cmp_and_trap_unsigned_int<mode>" | |
7886 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
7887 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7888 | (match_operand:GPR 2 "nonmemory_operand" "d,D")]) | |
7889 | (const_int 0))] | |
7890 | "TARGET_Z10" | |
7891 | "@ | |
7892 | cl<g>rt%C0\t%1,%2 | |
7893 | cl<gf>it%C0\t%1,%x2" | |
7894 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7895 | (set_attr "type" "branch") |
729e750f | 7896 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 7897 | |
9db1d521 | 7898 | ;; |
0a3bdf9d | 7899 | ;;- Loop instructions. |
9db1d521 | 7900 | ;; |
0a3bdf9d UW |
7901 | ;; This is all complicated by the fact that since this is a jump insn |
7902 | ;; we must handle our own output reloads. | |
c7453384 | 7903 | |
f1149235 AK |
7904 | ;; branch on index |
7905 | ||
7906 | ; This splitter will be matched by combine and has to add the 2 moves | |
7907 | ; necessary to load the compare and the increment values into a | |
7908 | ; register pair as needed by brxle. | |
7909 | ||
7910 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
7911 | [(set (pc) | |
7912 | (if_then_else | |
7913 | (match_operator 6 "s390_brx_operator" | |
7914 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
7915 | (match_operand:GPR 2 "general_operand" "")) | |
7916 | (match_operand:GPR 3 "register_operand" "")]) | |
7917 | (label_ref (match_operand 0 "" "")) | |
7918 | (pc))) | |
7919 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
7920 | (plus:GPR (match_dup 1) (match_dup 2))) | |
7921 | (clobber (match_scratch:GPR 5 ""))] | |
7922 | "TARGET_CPU_ZARCH" | |
7923 | "#" | |
7924 | "!reload_completed && !reload_in_progress" | |
7925 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
7926 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
7927 | (parallel [(set (pc) | |
7928 | (if_then_else | |
7929 | (match_op_dup 6 | |
7930 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
7931 | (match_dup 8)]) | |
7932 | (label_ref (match_dup 0)) | |
7933 | (pc))) | |
7934 | (set (match_dup 4) | |
7935 | (plus:GPR (match_dup 1) (match_dup 7))) | |
7936 | (clobber (match_dup 5)) | |
7937 | (clobber (reg:CC CC_REGNUM))])] | |
7938 | { | |
7939 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
7940 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
7941 | gen_highpart (word_mode, dreg)); | |
7942 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
7943 | gen_lowpart (word_mode, dreg)); | |
7944 | }) | |
7945 | ||
7946 | ; brxlg, brxhg | |
7947 | ||
7948 | (define_insn_and_split "*brxg_64bit" | |
7949 | [(set (pc) | |
7950 | (if_then_else | |
7951 | (match_operator 5 "s390_brx_operator" | |
7952 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
7953 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
7954 | (subreg:DI (match_dup 2) 8)]) | |
7955 | (label_ref (match_operand 0 "" "")) | |
7956 | (pc))) | |
7957 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
7958 | (plus:DI (match_dup 1) | |
7959 | (subreg:DI (match_dup 2) 0))) | |
7960 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
7961 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 7962 | "TARGET_ZARCH" |
f1149235 AK |
7963 | { |
7964 | if (which_alternative != 0) | |
7965 | return "#"; | |
7966 | else if (get_attr_length (insn) == 6) | |
7967 | return "brx%E5g\t%1,%2,%l0"; | |
7968 | else | |
7969 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
7970 | } | |
7971 | "&& reload_completed | |
7972 | && (!REG_P (operands[3]) | |
7973 | || !rtx_equal_p (operands[1], operands[3]))" | |
7974 | [(set (match_dup 4) (match_dup 1)) | |
7975 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
7976 | (clobber (reg:CC CC_REGNUM))]) | |
7977 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
7978 | (set (match_dup 3) (match_dup 4)) | |
7979 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
7980 | (label_ref (match_dup 0)) | |
7981 | (pc)))] | |
7982 | "" | |
7983 | [(set_attr "op_type" "RIE") | |
7984 | (set_attr "type" "branch") | |
7985 | (set (attr "length") | |
7986 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7987 | (const_int 6) (const_int 16)))]) | |
7988 | ||
7989 | ; brxle, brxh | |
7990 | ||
7991 | (define_insn_and_split "*brx_64bit" | |
7992 | [(set (pc) | |
7993 | (if_then_else | |
7994 | (match_operator 5 "s390_brx_operator" | |
7995 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
7996 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
7997 | (subreg:SI (match_dup 2) 12)]) | |
7998 | (label_ref (match_operand 0 "" "")) | |
7999 | (pc))) | |
8000 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8001 | (plus:SI (match_dup 1) | |
8002 | (subreg:SI (match_dup 2) 4))) | |
8003 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8004 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8005 | "TARGET_ZARCH" |
f1149235 AK |
8006 | { |
8007 | if (which_alternative != 0) | |
8008 | return "#"; | |
8009 | else if (get_attr_length (insn) == 6) | |
8010 | return "brx%C5\t%1,%2,%l0"; | |
8011 | else | |
8012 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8013 | } | |
8014 | "&& reload_completed | |
8015 | && (!REG_P (operands[3]) | |
8016 | || !rtx_equal_p (operands[1], operands[3]))" | |
8017 | [(set (match_dup 4) (match_dup 1)) | |
8018 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8019 | (clobber (reg:CC CC_REGNUM))]) | |
8020 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
8021 | (set (match_dup 3) (match_dup 4)) | |
8022 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8023 | (label_ref (match_dup 0)) | |
8024 | (pc)))] | |
8025 | "" | |
8026 | [(set_attr "op_type" "RSI") | |
8027 | (set_attr "type" "branch") | |
8028 | (set (attr "length") | |
8029 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8030 | (const_int 6) (const_int 14)))]) | |
8031 | ||
8032 | ; brxle, brxh | |
8033 | ||
8034 | (define_insn_and_split "*brx_31bit" | |
8035 | [(set (pc) | |
8036 | (if_then_else | |
8037 | (match_operator 5 "s390_brx_operator" | |
8038 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8039 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
8040 | (subreg:SI (match_dup 2) 4)]) | |
8041 | (label_ref (match_operand 0 "" "")) | |
8042 | (pc))) | |
8043 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8044 | (plus:SI (match_dup 1) | |
8045 | (subreg:SI (match_dup 2) 0))) | |
8046 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8047 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8048 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
8049 | { |
8050 | if (which_alternative != 0) | |
8051 | return "#"; | |
8052 | else if (get_attr_length (insn) == 6) | |
8053 | return "brx%C5\t%1,%2,%l0"; | |
8054 | else | |
8055 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8056 | } | |
8057 | "&& reload_completed | |
8058 | && (!REG_P (operands[3]) | |
8059 | || !rtx_equal_p (operands[1], operands[3]))" | |
8060 | [(set (match_dup 4) (match_dup 1)) | |
8061 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
8062 | (clobber (reg:CC CC_REGNUM))]) | |
8063 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8064 | (set (match_dup 3) (match_dup 4)) | |
8065 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8066 | (label_ref (match_dup 0)) | |
8067 | (pc)))] | |
8068 | "" | |
8069 | [(set_attr "op_type" "RSI") | |
8070 | (set_attr "type" "branch") | |
8071 | (set (attr "length") | |
8072 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8073 | (const_int 6) (const_int 14)))]) | |
8074 | ||
8075 | ||
8076 | ;; branch on count | |
8077 | ||
0a3bdf9d UW |
8078 | (define_expand "doloop_end" |
8079 | [(use (match_operand 0 "" "")) ; loop pseudo | |
8080 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
8081 | (use (match_operand 2 "" "")) ; max iterations | |
8082 | (use (match_operand 3 "" "")) ; loop level | |
8083 | (use (match_operand 4 "" ""))] ; label | |
8084 | "" | |
0a3bdf9d | 8085 | { |
6590e19a UW |
8086 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
8087 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
8088 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
8089 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
9602b6a1 | 8090 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
0a3bdf9d UW |
8091 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); |
8092 | else | |
8093 | FAIL; | |
8094 | ||
8095 | DONE; | |
10bbf137 | 8096 | }) |
0a3bdf9d | 8097 | |
6590e19a | 8098 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
8099 | [(set (pc) |
8100 | (if_then_else | |
7e665d18 | 8101 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8102 | (const_int 1)) |
8103 | (label_ref (match_operand 0 "" "")) | |
8104 | (pc))) | |
7e665d18 | 8105 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8106 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8107 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8108 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8109 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8110 | { |
8111 | if (which_alternative != 0) | |
10bbf137 | 8112 | return "#"; |
0a3bdf9d | 8113 | else if (get_attr_length (insn) == 4) |
d40c829f | 8114 | return "brct\t%1,%l0"; |
6590e19a | 8115 | else |
545d16ff | 8116 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
8117 | } |
8118 | "&& reload_completed | |
8119 | && (! REG_P (operands[2]) | |
8120 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8121 | [(set (match_dup 3) (match_dup 1)) |
8122 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8123 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8124 | (const_int 0))) | |
8125 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8126 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8127 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8128 | (label_ref (match_dup 0)) |
8129 | (pc)))] | |
8130 | "" | |
8131 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8132 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8133 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8134 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8135 | (set_attr "type" "branch") |
8136 | (set (attr "length") | |
8137 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8138 | (const_int 4) (const_int 10)))]) | |
8139 | ||
8140 | (define_insn_and_split "doloop_si31" | |
8141 | [(set (pc) | |
8142 | (if_then_else | |
7e665d18 | 8143 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
8144 | (const_int 1)) |
8145 | (label_ref (match_operand 0 "" "")) | |
8146 | (pc))) | |
7e665d18 | 8147 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 8148 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8149 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8150 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
8151 | "!TARGET_CPU_ZARCH" |
8152 | { | |
8153 | if (which_alternative != 0) | |
8154 | return "#"; | |
8155 | else if (get_attr_length (insn) == 4) | |
8156 | return "brct\t%1,%l0"; | |
0a3bdf9d | 8157 | else |
8d933e31 | 8158 | gcc_unreachable (); |
10bbf137 | 8159 | } |
6590e19a UW |
8160 | "&& reload_completed |
8161 | && (! REG_P (operands[2]) | |
8162 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8163 | [(set (match_dup 3) (match_dup 1)) |
8164 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8165 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8166 | (const_int 0))) | |
8167 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8168 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8169 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8170 | (label_ref (match_dup 0)) |
8171 | (pc)))] | |
8172 | "" | |
0a3bdf9d | 8173 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
8174 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8175 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8176 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 8177 | (set_attr "type" "branch") |
0a3bdf9d | 8178 | (set (attr "length") |
d7f99b2c | 8179 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8180 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8181 | (const_int 4) (const_int 6)) | |
8182 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8183 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8184 | |
0a3bdf9d UW |
8185 | (define_insn "*doloop_si_long" |
8186 | [(set (pc) | |
8187 | (if_then_else | |
7e665d18 | 8188 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 8189 | (const_int 1)) |
4fe6dea8 | 8190 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 8191 | (pc))) |
7e665d18 | 8192 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 8193 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8194 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 8195 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8196 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8197 | { |
8198 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8199 | return "bctr\t%1,%0"; |
0a3bdf9d | 8200 | else |
d40c829f | 8201 | return "bct\t%1,%a0"; |
10bbf137 | 8202 | } |
c7453384 | 8203 | [(set (attr "op_type") |
0a3bdf9d UW |
8204 | (if_then_else (match_operand 0 "register_operand" "") |
8205 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8206 | (set_attr "type" "branch") |
729e750f | 8207 | (set_attr "atype" "agen") |
65b1d8ea AK |
8208 | (set_attr "z10prop" "z10_c") |
8209 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 8210 | |
6590e19a | 8211 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
8212 | [(set (pc) |
8213 | (if_then_else | |
7e665d18 | 8214 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8215 | (const_int 1)) |
8216 | (label_ref (match_operand 0 "" "")) | |
8217 | (pc))) | |
7e665d18 | 8218 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8219 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 8220 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 8221 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8222 | "TARGET_ZARCH" |
0a3bdf9d UW |
8223 | { |
8224 | if (which_alternative != 0) | |
10bbf137 | 8225 | return "#"; |
0a3bdf9d | 8226 | else if (get_attr_length (insn) == 4) |
d40c829f | 8227 | return "brctg\t%1,%l0"; |
0a3bdf9d | 8228 | else |
545d16ff | 8229 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 8230 | } |
6590e19a | 8231 | "&& reload_completed |
0a3bdf9d UW |
8232 | && (! REG_P (operands[2]) |
8233 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8234 | [(set (match_dup 3) (match_dup 1)) |
8235 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
8236 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
8237 | (const_int 0))) | |
8238 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
8239 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8240 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 8241 | (label_ref (match_dup 0)) |
0a3bdf9d | 8242 | (pc)))] |
6590e19a UW |
8243 | "" |
8244 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8245 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8246 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8247 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8248 | (set_attr "type" "branch") |
8249 | (set (attr "length") | |
8250 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8251 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
8252 | |
8253 | ;; | |
8254 | ;;- Unconditional jump instructions. | |
8255 | ;; | |
8256 | ||
8257 | ; | |
8258 | ; jump instruction pattern(s). | |
8259 | ; | |
8260 | ||
6590e19a UW |
8261 | (define_expand "jump" |
8262 | [(match_operand 0 "" "")] | |
9db1d521 | 8263 | "" |
6590e19a UW |
8264 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
8265 | ||
8266 | (define_insn "*jump64" | |
8267 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8268 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8269 | { |
13e58269 | 8270 | if (get_attr_length (insn) == 4) |
d40c829f | 8271 | return "j\t%l0"; |
6590e19a | 8272 | else |
d40c829f | 8273 | return "jg\t%l0"; |
6590e19a UW |
8274 | } |
8275 | [(set_attr "op_type" "RI") | |
8276 | (set_attr "type" "branch") | |
8277 | (set (attr "length") | |
8278 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8279 | (const_int 4) (const_int 6)))]) | |
8280 | ||
8281 | (define_insn "*jump31" | |
8282 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8283 | "!TARGET_CPU_ZARCH" | |
8284 | { | |
8d933e31 AS |
8285 | gcc_assert (get_attr_length (insn) == 4); |
8286 | return "j\t%l0"; | |
10bbf137 | 8287 | } |
9db1d521 | 8288 | [(set_attr "op_type" "RI") |
077dab3b | 8289 | (set_attr "type" "branch") |
13e58269 | 8290 | (set (attr "length") |
d7f99b2c | 8291 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8292 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8293 | (const_int 4) (const_int 6)) | |
8294 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8295 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
8296 | |
8297 | ; | |
8298 | ; indirect-jump instruction pattern(s). | |
8299 | ; | |
8300 | ||
8301 | (define_insn "indirect_jump" | |
4fe6dea8 | 8302 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 8303 | "" |
f314b9b1 UW |
8304 | { |
8305 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8306 | return "br\t%0"; |
f314b9b1 | 8307 | else |
d40c829f | 8308 | return "b\t%a0"; |
10bbf137 | 8309 | } |
c7453384 | 8310 | [(set (attr "op_type") |
f314b9b1 UW |
8311 | (if_then_else (match_operand 0 "register_operand" "") |
8312 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8313 | (set_attr "type" "branch") |
729e750f | 8314 | (set_attr "atype" "agen")]) |
9db1d521 HP |
8315 | |
8316 | ; | |
f314b9b1 | 8317 | ; casesi instruction pattern(s). |
9db1d521 HP |
8318 | ; |
8319 | ||
f314b9b1 | 8320 | (define_insn "casesi_jump" |
4fe6dea8 | 8321 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 8322 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 8323 | "" |
9db1d521 | 8324 | { |
f314b9b1 | 8325 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 8326 | return "br\t%0"; |
f314b9b1 | 8327 | else |
d40c829f | 8328 | return "b\t%a0"; |
10bbf137 | 8329 | } |
c7453384 | 8330 | [(set (attr "op_type") |
f314b9b1 UW |
8331 | (if_then_else (match_operand 0 "register_operand" "") |
8332 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8333 | (set_attr "type" "branch") |
8334 | (set_attr "atype" "agen")]) | |
9db1d521 | 8335 | |
f314b9b1 UW |
8336 | (define_expand "casesi" |
8337 | [(match_operand:SI 0 "general_operand" "") | |
8338 | (match_operand:SI 1 "general_operand" "") | |
8339 | (match_operand:SI 2 "general_operand" "") | |
8340 | (label_ref (match_operand 3 "" "")) | |
8341 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 8342 | "" |
f314b9b1 UW |
8343 | { |
8344 | rtx index = gen_reg_rtx (SImode); | |
8345 | rtx base = gen_reg_rtx (Pmode); | |
8346 | rtx target = gen_reg_rtx (Pmode); | |
8347 | ||
8348 | emit_move_insn (index, operands[0]); | |
8349 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
8350 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 8351 | operands[4]); |
f314b9b1 UW |
8352 | |
8353 | if (Pmode != SImode) | |
8354 | index = convert_to_mode (Pmode, index, 1); | |
8355 | if (GET_CODE (index) != REG) | |
8356 | index = copy_to_mode_reg (Pmode, index); | |
8357 | ||
8358 | if (TARGET_64BIT) | |
8359 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
8360 | else | |
a556fd39 | 8361 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 8362 | |
f314b9b1 UW |
8363 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
8364 | ||
542a8afa | 8365 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
8366 | emit_move_insn (target, index); |
8367 | ||
8368 | if (flag_pic) | |
8369 | target = gen_rtx_PLUS (Pmode, base, target); | |
8370 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
8371 | ||
8372 | DONE; | |
10bbf137 | 8373 | }) |
9db1d521 HP |
8374 | |
8375 | ||
8376 | ;; | |
8377 | ;;- Jump to subroutine. | |
8378 | ;; | |
8379 | ;; | |
8380 | ||
8381 | ; | |
8382 | ; untyped call instruction pattern(s). | |
8383 | ; | |
8384 | ||
8385 | ;; Call subroutine returning any type. | |
8386 | (define_expand "untyped_call" | |
8387 | [(parallel [(call (match_operand 0 "" "") | |
8388 | (const_int 0)) | |
8389 | (match_operand 1 "" "") | |
8390 | (match_operand 2 "" "")])] | |
8391 | "" | |
9db1d521 HP |
8392 | { |
8393 | int i; | |
8394 | ||
8395 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
8396 | ||
8397 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
8398 | { | |
8399 | rtx set = XVECEXP (operands[2], 0, i); | |
8400 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
8401 | } | |
8402 | ||
8403 | /* The optimizer does not know that the call sets the function value | |
8404 | registers we stored in the result block. We avoid problems by | |
8405 | claiming that all hard registers are used and clobbered at this | |
8406 | point. */ | |
8407 | emit_insn (gen_blockage ()); | |
8408 | ||
8409 | DONE; | |
10bbf137 | 8410 | }) |
9db1d521 HP |
8411 | |
8412 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
8413 | ;; all of memory. This blocks insns from being moved across this point. | |
8414 | ||
8415 | (define_insn "blockage" | |
10bbf137 | 8416 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 8417 | "" |
4023fb28 | 8418 | "" |
d5869ca0 UW |
8419 | [(set_attr "type" "none") |
8420 | (set_attr "length" "0")]) | |
4023fb28 | 8421 | |
9db1d521 | 8422 | ; |
ed9676cf | 8423 | ; sibcall patterns |
9db1d521 HP |
8424 | ; |
8425 | ||
ed9676cf | 8426 | (define_expand "sibcall" |
44b8152b | 8427 | [(call (match_operand 0 "" "") |
ed9676cf | 8428 | (match_operand 1 "" ""))] |
9db1d521 | 8429 | "" |
9db1d521 | 8430 | { |
ed9676cf AK |
8431 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
8432 | DONE; | |
8433 | }) | |
9db1d521 | 8434 | |
ed9676cf | 8435 | (define_insn "*sibcall_br" |
ae156f85 | 8436 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8437 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 8438 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8439 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
8440 | "br\t%%r1" | |
8441 | [(set_attr "op_type" "RR") | |
8442 | (set_attr "type" "branch") | |
8443 | (set_attr "atype" "agen")]) | |
9db1d521 | 8444 | |
ed9676cf AK |
8445 | (define_insn "*sibcall_brc" |
8446 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8447 | (match_operand 1 "const_int_operand" "n"))] | |
8448 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8449 | "j\t%0" | |
8450 | [(set_attr "op_type" "RI") | |
8451 | (set_attr "type" "branch")]) | |
9db1d521 | 8452 | |
ed9676cf AK |
8453 | (define_insn "*sibcall_brcl" |
8454 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8455 | (match_operand 1 "const_int_operand" "n"))] | |
8456 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8457 | "jg\t%0" | |
8458 | [(set_attr "op_type" "RIL") | |
8459 | (set_attr "type" "branch")]) | |
44b8152b | 8460 | |
ed9676cf AK |
8461 | ; |
8462 | ; sibcall_value patterns | |
8463 | ; | |
9e8327e3 | 8464 | |
ed9676cf AK |
8465 | (define_expand "sibcall_value" |
8466 | [(set (match_operand 0 "" "") | |
8467 | (call (match_operand 1 "" "") | |
8468 | (match_operand 2 "" "")))] | |
8469 | "" | |
8470 | { | |
8471 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 8472 | DONE; |
10bbf137 | 8473 | }) |
9db1d521 | 8474 | |
ed9676cf AK |
8475 | (define_insn "*sibcall_value_br" |
8476 | [(set (match_operand 0 "" "") | |
ae156f85 | 8477 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8478 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 8479 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8480 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
8481 | "br\t%%r1" | |
8482 | [(set_attr "op_type" "RR") | |
8483 | (set_attr "type" "branch") | |
8484 | (set_attr "atype" "agen")]) | |
8485 | ||
8486 | (define_insn "*sibcall_value_brc" | |
8487 | [(set (match_operand 0 "" "") | |
8488 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8489 | (match_operand 2 "const_int_operand" "n")))] | |
8490 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8491 | "j\t%1" | |
8492 | [(set_attr "op_type" "RI") | |
8493 | (set_attr "type" "branch")]) | |
8494 | ||
8495 | (define_insn "*sibcall_value_brcl" | |
8496 | [(set (match_operand 0 "" "") | |
8497 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8498 | (match_operand 2 "const_int_operand" "n")))] | |
8499 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8500 | "jg\t%1" | |
8501 | [(set_attr "op_type" "RIL") | |
8502 | (set_attr "type" "branch")]) | |
8503 | ||
8504 | ||
8505 | ; | |
8506 | ; call instruction pattern(s). | |
8507 | ; | |
8508 | ||
8509 | (define_expand "call" | |
8510 | [(call (match_operand 0 "" "") | |
8511 | (match_operand 1 "" "")) | |
8512 | (use (match_operand 2 "" ""))] | |
44b8152b | 8513 | "" |
ed9676cf | 8514 | { |
2f7e5a0d | 8515 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
8516 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
8517 | DONE; | |
8518 | }) | |
44b8152b | 8519 | |
9e8327e3 UW |
8520 | (define_insn "*bras" |
8521 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8522 | (match_operand 1 "const_int_operand" "n")) | |
8523 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8524 | "!SIBLING_CALL_P (insn) |
8525 | && TARGET_SMALL_EXEC | |
ed9676cf | 8526 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 8527 | "bras\t%2,%0" |
9db1d521 | 8528 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8529 | (set_attr "type" "jsr") |
8530 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8531 | |
9e8327e3 UW |
8532 | (define_insn "*brasl" |
8533 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8534 | (match_operand 1 "const_int_operand" "n")) | |
8535 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8536 | "!SIBLING_CALL_P (insn) |
8537 | && TARGET_CPU_ZARCH | |
ed9676cf | 8538 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8539 | "brasl\t%2,%0" |
8540 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8541 | (set_attr "type" "jsr") |
8542 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8543 | |
9e8327e3 | 8544 | (define_insn "*basr" |
4fe6dea8 | 8545 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
8546 | (match_operand 1 "const_int_operand" "n")) |
8547 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 8548 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8549 | { |
8550 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8551 | return "basr\t%2,%0"; | |
8552 | else | |
8553 | return "bas\t%2,%a0"; | |
8554 | } | |
8555 | [(set (attr "op_type") | |
8556 | (if_then_else (match_operand 0 "register_operand" "") | |
8557 | (const_string "RR") (const_string "RX"))) | |
8558 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8559 | (set_attr "atype" "agen") |
8560 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
8561 | |
8562 | ; | |
8563 | ; call_value instruction pattern(s). | |
8564 | ; | |
8565 | ||
8566 | (define_expand "call_value" | |
44b8152b UW |
8567 | [(set (match_operand 0 "" "") |
8568 | (call (match_operand 1 "" "") | |
8569 | (match_operand 2 "" ""))) | |
8570 | (use (match_operand 3 "" ""))] | |
9db1d521 | 8571 | "" |
9db1d521 | 8572 | { |
2f7e5a0d | 8573 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 8574 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 8575 | DONE; |
10bbf137 | 8576 | }) |
9db1d521 | 8577 | |
9e8327e3 | 8578 | (define_insn "*bras_r" |
c19ec8f9 | 8579 | [(set (match_operand 0 "" "") |
9e8327e3 | 8580 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 8581 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 8582 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
8583 | "!SIBLING_CALL_P (insn) |
8584 | && TARGET_SMALL_EXEC | |
ed9676cf | 8585 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8586 | "bras\t%3,%1" |
9db1d521 | 8587 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8588 | (set_attr "type" "jsr") |
8589 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8590 | |
9e8327e3 | 8591 | (define_insn "*brasl_r" |
c19ec8f9 | 8592 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8593 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8594 | (match_operand 2 "const_int_operand" "n"))) | |
8595 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
8596 | "!SIBLING_CALL_P (insn) |
8597 | && TARGET_CPU_ZARCH | |
ed9676cf | 8598 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8599 | "brasl\t%3,%1" |
8600 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8601 | (set_attr "type" "jsr") |
8602 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8603 | |
9e8327e3 | 8604 | (define_insn "*basr_r" |
c19ec8f9 | 8605 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8606 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8607 | (match_operand 2 "const_int_operand" "n"))) |
8608 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 8609 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8610 | { |
8611 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8612 | return "basr\t%3,%1"; | |
8613 | else | |
8614 | return "bas\t%3,%a1"; | |
8615 | } | |
8616 | [(set (attr "op_type") | |
8617 | (if_then_else (match_operand 1 "register_operand" "") | |
8618 | (const_string "RR") (const_string "RX"))) | |
8619 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8620 | (set_attr "atype" "agen") |
8621 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8622 | |
fd3cd001 UW |
8623 | ;; |
8624 | ;;- Thread-local storage support. | |
8625 | ;; | |
8626 | ||
c5aa1d12 | 8627 | (define_expand "get_tp_64" |
ae156f85 | 8628 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] |
fd3cd001 | 8629 | "TARGET_64BIT" |
c5aa1d12 | 8630 | "") |
fd3cd001 | 8631 | |
c5aa1d12 | 8632 | (define_expand "get_tp_31" |
ae156f85 | 8633 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] |
fd3cd001 | 8634 | "!TARGET_64BIT" |
c5aa1d12 | 8635 | "") |
fd3cd001 | 8636 | |
c5aa1d12 | 8637 | (define_expand "set_tp_64" |
ae156f85 AS |
8638 | [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) |
8639 | (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 8640 | "TARGET_64BIT" |
c5aa1d12 | 8641 | "") |
fd3cd001 | 8642 | |
c5aa1d12 | 8643 | (define_expand "set_tp_31" |
ae156f85 AS |
8644 | [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) |
8645 | (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 8646 | "!TARGET_64BIT" |
c5aa1d12 UW |
8647 | "") |
8648 | ||
8649 | (define_insn "*set_tp" | |
ae156f85 | 8650 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
8651 | "" |
8652 | "" | |
8653 | [(set_attr "type" "none") | |
8654 | (set_attr "length" "0")]) | |
c7453384 | 8655 | |
fd3cd001 UW |
8656 | (define_insn "*tls_load_64" |
8657 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 8658 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
8659 | (match_operand:DI 2 "" "")] |
8660 | UNSPEC_TLS_LOAD))] | |
8661 | "TARGET_64BIT" | |
d40c829f | 8662 | "lg\t%0,%1%J2" |
9381e3f1 WG |
8663 | [(set_attr "op_type" "RXE") |
8664 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
8665 | |
8666 | (define_insn "*tls_load_31" | |
d3632d41 UW |
8667 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
8668 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
8669 | (match_operand:SI 2 "" "")] |
8670 | UNSPEC_TLS_LOAD))] | |
8671 | "!TARGET_64BIT" | |
d3632d41 | 8672 | "@ |
d40c829f UW |
8673 | l\t%0,%1%J2 |
8674 | ly\t%0,%1%J2" | |
9381e3f1 | 8675 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 8676 | (set_attr "type" "load") |
9381e3f1 | 8677 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 8678 | |
9e8327e3 | 8679 | (define_insn "*bras_tls" |
c19ec8f9 | 8680 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8681 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8682 | (match_operand 2 "const_int_operand" "n"))) | |
8683 | (clobber (match_operand 3 "register_operand" "=r")) | |
8684 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8685 | "!SIBLING_CALL_P (insn) |
8686 | && TARGET_SMALL_EXEC | |
ed9676cf | 8687 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8688 | "bras\t%3,%1%J4" |
fd3cd001 | 8689 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8690 | (set_attr "type" "jsr") |
8691 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8692 | |
9e8327e3 | 8693 | (define_insn "*brasl_tls" |
c19ec8f9 | 8694 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8695 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8696 | (match_operand 2 "const_int_operand" "n"))) | |
8697 | (clobber (match_operand 3 "register_operand" "=r")) | |
8698 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8699 | "!SIBLING_CALL_P (insn) |
8700 | && TARGET_CPU_ZARCH | |
ed9676cf | 8701 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8702 | "brasl\t%3,%1%J4" |
8703 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8704 | (set_attr "type" "jsr") |
8705 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8706 | |
9e8327e3 | 8707 | (define_insn "*basr_tls" |
c19ec8f9 | 8708 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8709 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8710 | (match_operand 2 "const_int_operand" "n"))) |
8711 | (clobber (match_operand 3 "register_operand" "=r")) | |
8712 | (use (match_operand 4 "" ""))] | |
ed9676cf | 8713 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8714 | { |
8715 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8716 | return "basr\t%3,%1%J4"; | |
8717 | else | |
8718 | return "bas\t%3,%a1%J4"; | |
8719 | } | |
8720 | [(set (attr "op_type") | |
8721 | (if_then_else (match_operand 1 "register_operand" "") | |
8722 | (const_string "RR") (const_string "RX"))) | |
8723 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8724 | (set_attr "atype" "agen") |
8725 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8726 | |
e0374221 AS |
8727 | ;; |
8728 | ;;- Atomic operations | |
8729 | ;; | |
8730 | ||
8731 | ; | |
8732 | ; memory barrier pattern. | |
8733 | ; | |
8734 | ||
8735 | (define_expand "memory_barrier" | |
1a8c13b3 UB |
8736 | [(set (match_dup 0) |
8737 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] | |
e0374221 AS |
8738 | "" |
8739 | { | |
1a8c13b3 | 8740 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); |
e0374221 AS |
8741 | MEM_VOLATILE_P (operands[0]) = 1; |
8742 | }) | |
8743 | ||
8744 | (define_insn "*memory_barrier" | |
8745 | [(set (match_operand:BLK 0 "" "") | |
1a8c13b3 | 8746 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 AS |
8747 | "" |
8748 | "bcr\t15,0" | |
8749 | [(set_attr "op_type" "RR")]) | |
1a8c13b3 | 8750 | |
9381e3f1 WG |
8751 | ; Although bcr is superscalar on Z10, this variant will never become part of |
8752 | ; an execution group. | |
e0374221 AS |
8753 | |
8754 | ; | |
8755 | ; compare and swap patterns. | |
8756 | ; | |
8757 | ||
8006eaa6 AS |
8758 | (define_expand "sync_compare_and_swap<mode>" |
8759 | [(parallel | |
8760 | [(set (match_operand:TDSI 0 "register_operand" "") | |
8761 | (match_operand:TDSI 1 "memory_operand" "")) | |
8762 | (set (match_dup 1) | |
8763 | (unspec_volatile:TDSI | |
8764 | [(match_dup 1) | |
8765 | (match_operand:TDSI 2 "register_operand" "") | |
8766 | (match_operand:TDSI 3 "register_operand" "")] | |
8767 | UNSPECV_CAS)) | |
8768 | (set (reg:CCZ1 CC_REGNUM) | |
8769 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8770 | "") | |
e0374221 | 8771 | |
3093f076 AS |
8772 | (define_expand "sync_compare_and_swap<mode>" |
8773 | [(parallel | |
8774 | [(set (match_operand:HQI 0 "register_operand" "") | |
8775 | (match_operand:HQI 1 "memory_operand" "")) | |
8776 | (set (match_dup 1) | |
8777 | (unspec_volatile:HQI | |
8778 | [(match_dup 1) | |
8779 | (match_operand:HQI 2 "general_operand" "") | |
8780 | (match_operand:HQI 3 "general_operand" "")] | |
8781 | UNSPECV_CAS)) | |
4a77c72b | 8782 | (clobber (reg:CC CC_REGNUM))])] |
3093f076 | 8783 | "" |
9381e3f1 | 8784 | "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], |
3093f076 AS |
8785 | operands[2], operands[3]); DONE;") |
8786 | ||
43a09b63 | 8787 | ; cds, cdsg |
8006eaa6 | 8788 | (define_insn "*sync_compare_and_swap<mode>" |
9602b6a1 AK |
8789 | [(set (match_operand:DW 0 "register_operand" "=r") |
8790 | (match_operand:DW 1 "memory_operand" "+Q")) | |
8006eaa6 | 8791 | (set (match_dup 1) |
9602b6a1 | 8792 | (unspec_volatile:DW |
8006eaa6 | 8793 | [(match_dup 1) |
9602b6a1 AK |
8794 | (match_operand:DW 2 "register_operand" "0") |
8795 | (match_operand:DW 3 "register_operand" "r")] | |
8006eaa6 AS |
8796 | UNSPECV_CAS)) |
8797 | (set (reg:CCZ1 CC_REGNUM) | |
8798 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
8799 | "" | |
8800 | "cds<tg>\t%0,%3,%S1" | |
8801 | [(set_attr "op_type" "RS<TE>") | |
8802 | (set_attr "type" "sem")]) | |
8803 | ||
43a09b63 | 8804 | ; cs, csg |
8006eaa6 | 8805 | (define_insn "*sync_compare_and_swap<mode>" |
e0374221 AS |
8806 | [(set (match_operand:GPR 0 "register_operand" "=r") |
8807 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
8808 | (set (match_dup 1) | |
8809 | (unspec_volatile:GPR | |
8810 | [(match_dup 1) | |
8811 | (match_operand:GPR 2 "register_operand" "0") | |
8812 | (match_operand:GPR 3 "register_operand" "r")] | |
8813 | UNSPECV_CAS)) | |
69950452 AS |
8814 | (set (reg:CCZ1 CC_REGNUM) |
8815 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 8816 | "" |
e0374221 AS |
8817 | "cs<g>\t%0,%3,%S1" |
8818 | [(set_attr "op_type" "RS<E>") | |
8819 | (set_attr "type" "sem")]) | |
8820 | ||
8821 | ||
45d18331 AS |
8822 | ; |
8823 | ; Other atomic instruction patterns. | |
8824 | ; | |
8825 | ||
8826 | (define_expand "sync_lock_test_and_set<mode>" | |
8827 | [(match_operand:HQI 0 "register_operand") | |
8828 | (match_operand:HQI 1 "memory_operand") | |
8829 | (match_operand:HQI 2 "general_operand")] | |
8830 | "" | |
9381e3f1 | 8831 | "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], |
45d18331 AS |
8832 | operands[2], false); DONE;") |
8833 | ||
65b1d8ea AK |
8834 | ; z196 load and add, xor, or and and instructions |
8835 | ||
8836 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
8837 | (define_insn "sync_<atomic><mode>" | |
8838 | [(parallel | |
8839 | [(set (match_operand:GPR 0 "memory_operand" "+QS") | |
8840 | (unspec_volatile:GPR | |
8841 | [(ATOMIC_Z196:GPR (match_dup 0) | |
8842 | (match_operand:GPR 1 "general_operand" "d"))] | |
8843 | UNSPECV_ATOMIC_OP)) | |
8844 | (clobber (match_scratch:GPR 2 "=d")) | |
8845 | (clobber (reg:CC CC_REGNUM))])] | |
8846 | "TARGET_Z196" | |
8847 | "la<noxa><g>\t%2,%1,%0") | |
8848 | ||
8849 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
8850 | (define_insn "sync_old_<atomic><mode>" | |
8851 | [(parallel | |
8852 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8853 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
8854 | (set (match_dup 1) | |
27037b5f | 8855 | (unspec_volatile:GPR |
65b1d8ea AK |
8856 | [(ATOMIC_Z196:GPR (match_dup 1) |
8857 | (match_operand:GPR 2 "general_operand" "d"))] | |
8858 | UNSPECV_ATOMIC_OP)) | |
8859 | (clobber (reg:CC CC_REGNUM))])] | |
8860 | "TARGET_Z196" | |
8861 | "la<noxa><g>\t%0,%2,%1") | |
8862 | ||
8863 | ||
45d18331 AS |
8864 | (define_expand "sync_<atomic><mode>" |
8865 | [(set (match_operand:HQI 0 "memory_operand") | |
8866 | (ATOMIC:HQI (match_dup 0) | |
8867 | (match_operand:HQI 1 "general_operand")))] | |
8868 | "" | |
9381e3f1 | 8869 | "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], |
45d18331 AS |
8870 | operands[1], false); DONE;") |
8871 | ||
8872 | (define_expand "sync_old_<atomic><mode>" | |
8873 | [(set (match_operand:HQI 0 "register_operand") | |
8874 | (match_operand:HQI 1 "memory_operand")) | |
8875 | (set (match_dup 1) | |
8876 | (ATOMIC:HQI (match_dup 1) | |
8877 | (match_operand:HQI 2 "general_operand")))] | |
8878 | "" | |
9381e3f1 | 8879 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], |
45d18331 AS |
8880 | operands[2], false); DONE;") |
8881 | ||
8882 | (define_expand "sync_new_<atomic><mode>" | |
8883 | [(set (match_operand:HQI 0 "register_operand") | |
8884 | (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") | |
9381e3f1 | 8885 | (match_operand:HQI 2 "general_operand"))) |
45d18331 AS |
8886 | (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] |
8887 | "" | |
9381e3f1 | 8888 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], |
45d18331 AS |
8889 | operands[2], true); DONE;") |
8890 | ||
9db1d521 HP |
8891 | ;; |
8892 | ;;- Miscellaneous instructions. | |
8893 | ;; | |
8894 | ||
8895 | ; | |
8896 | ; allocate stack instruction pattern(s). | |
8897 | ; | |
8898 | ||
8899 | (define_expand "allocate_stack" | |
ef44a6ff UW |
8900 | [(match_operand 0 "general_operand" "") |
8901 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 8902 | "TARGET_BACKCHAIN" |
9db1d521 | 8903 | { |
ef44a6ff | 8904 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 8905 | |
ef44a6ff UW |
8906 | emit_move_insn (temp, s390_back_chain_rtx ()); |
8907 | anti_adjust_stack (operands[1]); | |
8908 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 8909 | |
ef44a6ff UW |
8910 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
8911 | DONE; | |
10bbf137 | 8912 | }) |
9db1d521 HP |
8913 | |
8914 | ||
8915 | ; | |
43ab026f | 8916 | ; setjmp instruction pattern. |
9db1d521 HP |
8917 | ; |
8918 | ||
9db1d521 | 8919 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 8920 | [(match_operand 0 "" "")] |
f314b9b1 | 8921 | "flag_pic" |
9db1d521 | 8922 | { |
585539a1 | 8923 | emit_insn (s390_load_got ()); |
c41c1387 | 8924 | emit_use (pic_offset_table_rtx); |
9db1d521 | 8925 | DONE; |
fd7643fb | 8926 | }) |
9db1d521 | 8927 | |
9db1d521 HP |
8928 | ;; These patterns say how to save and restore the stack pointer. We need not |
8929 | ;; save the stack pointer at function level since we are careful to | |
8930 | ;; preserve the backchain. At block level, we have to restore the backchain | |
8931 | ;; when we restore the stack pointer. | |
8932 | ;; | |
8933 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
8934 | ;; backchain and restore both. Note that in the nonlocal case, the | |
8935 | ;; save area is a memory location. | |
8936 | ||
8937 | (define_expand "save_stack_function" | |
8938 | [(match_operand 0 "general_operand" "") | |
8939 | (match_operand 1 "general_operand" "")] | |
8940 | "" | |
8941 | "DONE;") | |
8942 | ||
8943 | (define_expand "restore_stack_function" | |
8944 | [(match_operand 0 "general_operand" "") | |
8945 | (match_operand 1 "general_operand" "")] | |
8946 | "" | |
8947 | "DONE;") | |
8948 | ||
8949 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
8950 | [(match_operand 0 "register_operand" "") |
8951 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 8952 | "TARGET_BACKCHAIN" |
9db1d521 | 8953 | { |
ef44a6ff UW |
8954 | rtx temp = gen_reg_rtx (Pmode); |
8955 | ||
8956 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
8957 | emit_move_insn (operands[0], operands[1]); | |
8958 | emit_move_insn (s390_back_chain_rtx (), temp); | |
8959 | ||
8960 | DONE; | |
10bbf137 | 8961 | }) |
9db1d521 HP |
8962 | |
8963 | (define_expand "save_stack_nonlocal" | |
8964 | [(match_operand 0 "memory_operand" "") | |
8965 | (match_operand 1 "register_operand" "")] | |
8966 | "" | |
9db1d521 | 8967 | { |
ef44a6ff UW |
8968 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
8969 | ||
8970 | /* Copy the backchain to the first word, sp to the second and the | |
8971 | literal pool base to the third. */ | |
8972 | ||
9602b6a1 AK |
8973 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
8974 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
8975 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
8976 | ||
b3d31392 | 8977 | if (TARGET_BACKCHAIN) |
9602b6a1 | 8978 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 8979 | |
9602b6a1 AK |
8980 | emit_move_insn (save_sp, operands[1]); |
8981 | emit_move_insn (save_bp, base); | |
9db1d521 | 8982 | |
9db1d521 | 8983 | DONE; |
10bbf137 | 8984 | }) |
9db1d521 HP |
8985 | |
8986 | (define_expand "restore_stack_nonlocal" | |
8987 | [(match_operand 0 "register_operand" "") | |
8988 | (match_operand 1 "memory_operand" "")] | |
8989 | "" | |
9db1d521 | 8990 | { |
490ceeb4 | 8991 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 8992 | rtx temp = NULL_RTX; |
9db1d521 | 8993 | |
43ab026f | 8994 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 8995 | literal pool base from the third. */ |
43ab026f | 8996 | |
9602b6a1 AK |
8997 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
8998 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
8999 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
9000 | ||
b3d31392 | 9001 | if (TARGET_BACKCHAIN) |
9602b6a1 | 9002 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 9003 | |
9602b6a1 AK |
9004 | emit_move_insn (base, save_bp); |
9005 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
9006 | |
9007 | if (temp) | |
9008 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9009 | ||
c41c1387 | 9010 | emit_use (base); |
9db1d521 | 9011 | DONE; |
10bbf137 | 9012 | }) |
9db1d521 | 9013 | |
7bcebb25 AK |
9014 | (define_expand "exception_receiver" |
9015 | [(const_int 0)] | |
9016 | "" | |
9017 | { | |
9018 | s390_set_has_landing_pad_p (true); | |
9019 | DONE; | |
9020 | }) | |
9db1d521 HP |
9021 | |
9022 | ; | |
9023 | ; nop instruction pattern(s). | |
9024 | ; | |
9025 | ||
9026 | (define_insn "nop" | |
9027 | [(const_int 0)] | |
9028 | "" | |
d40c829f | 9029 | "lr\t0,0" |
729e750f WG |
9030 | [(set_attr "op_type" "RR") |
9031 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 9032 | |
d277db6b WG |
9033 | (define_insn "nop1" |
9034 | [(const_int 1)] | |
9035 | "" | |
9036 | "lr\t1,1" | |
9037 | [(set_attr "op_type" "RR")]) | |
9038 | ||
9db1d521 HP |
9039 | |
9040 | ; | |
9041 | ; Special literal pool access instruction pattern(s). | |
9042 | ; | |
9043 | ||
416cf582 UW |
9044 | (define_insn "*pool_entry" |
9045 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
9046 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 9047 | "" |
9db1d521 | 9048 | { |
416cf582 UW |
9049 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
9050 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 9051 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
9052 | return ""; |
9053 | } | |
b628bd8e | 9054 | [(set (attr "length") |
416cf582 | 9055 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 9056 | |
9bb86f41 UW |
9057 | (define_insn "pool_align" |
9058 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
9059 | UNSPECV_POOL_ALIGN)] | |
9060 | "" | |
9061 | ".align\t%0" | |
b628bd8e | 9062 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 9063 | |
9bb86f41 UW |
9064 | (define_insn "pool_section_start" |
9065 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
9066 | "" | |
9067 | ".section\t.rodata" | |
b628bd8e | 9068 | [(set_attr "length" "0")]) |
b2ccb744 | 9069 | |
9bb86f41 UW |
9070 | (define_insn "pool_section_end" |
9071 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
9072 | "" | |
b2ccb744 | 9073 | ".previous" |
b628bd8e | 9074 | [(set_attr "length" "0")]) |
b2ccb744 | 9075 | |
5af2f3d3 | 9076 | (define_insn "main_base_31_small" |
9e8327e3 UW |
9077 | [(set (match_operand 0 "register_operand" "=a") |
9078 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9079 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9080 | "basr\t%0,0" |
9081 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
9082 | (set_attr "type" "la") |
9083 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9084 | |
9085 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
9086 | [(set (match_operand 0 "register_operand" "=a") |
9087 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 9088 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 9089 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 9090 | "bras\t%0,%2" |
65b1d8ea AK |
9091 | [(set_attr "op_type" "RI") |
9092 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9093 | |
9094 | (define_insn "main_base_64" | |
9e8327e3 UW |
9095 | [(set (match_operand 0 "register_operand" "=a") |
9096 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9097 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9098 | "larl\t%0,%1" |
9099 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 9100 | (set_attr "type" "larl") |
729e750f | 9101 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
9102 | |
9103 | (define_insn "main_pool" | |
585539a1 UW |
9104 | [(set (match_operand 0 "register_operand" "=a") |
9105 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
9106 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
9107 | { |
9108 | gcc_unreachable (); | |
9109 | } | |
9381e3f1 | 9110 | [(set (attr "type") |
d7f99b2c | 9111 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 9112 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 9113 | |
aee4e0db | 9114 | (define_insn "reload_base_31" |
9e8327e3 UW |
9115 | [(set (match_operand 0 "register_operand" "=a") |
9116 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9117 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9118 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 9119 | [(set_attr "length" "6") |
65b1d8ea AK |
9120 | (set_attr "type" "la") |
9121 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 9122 | |
aee4e0db | 9123 | (define_insn "reload_base_64" |
9e8327e3 UW |
9124 | [(set (match_operand 0 "register_operand" "=a") |
9125 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9126 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9127 | "larl\t%0,%1" |
aee4e0db | 9128 | [(set_attr "op_type" "RIL") |
9381e3f1 | 9129 | (set_attr "type" "larl") |
729e750f | 9130 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 9131 | |
aee4e0db | 9132 | (define_insn "pool" |
fd7643fb | 9133 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 9134 | "" |
8d933e31 AS |
9135 | { |
9136 | gcc_unreachable (); | |
9137 | } | |
b628bd8e | 9138 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 9139 | |
4023fb28 UW |
9140 | ;; |
9141 | ;; Insns related to generating the function prologue and epilogue. | |
9142 | ;; | |
9143 | ||
9144 | ||
9145 | (define_expand "prologue" | |
9146 | [(use (const_int 0))] | |
9147 | "" | |
10bbf137 | 9148 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
9149 | |
9150 | (define_expand "epilogue" | |
9151 | [(use (const_int 1))] | |
9152 | "" | |
ed9676cf AK |
9153 | "s390_emit_epilogue (false); DONE;") |
9154 | ||
9155 | (define_expand "sibcall_epilogue" | |
9156 | [(use (const_int 0))] | |
9157 | "" | |
9158 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 9159 | |
9e8327e3 | 9160 | (define_insn "*return" |
4023fb28 | 9161 | [(return) |
9e8327e3 UW |
9162 | (use (match_operand 0 "register_operand" "a"))] |
9163 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9164 | "br\t%0" |
4023fb28 | 9165 | [(set_attr "op_type" "RR") |
c7453384 | 9166 | (set_attr "type" "jsr") |
077dab3b | 9167 | (set_attr "atype" "agen")]) |
4023fb28 | 9168 | |
4023fb28 | 9169 | |
c7453384 | 9170 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 9171 | ;; pointer. This is used for compatibility. |
c7453384 EC |
9172 | |
9173 | (define_expand "ptr_extend" | |
9174 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9175 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 9176 | "TARGET_64BIT" |
c7453384 | 9177 | { |
c7453384 EC |
9178 | emit_insn (gen_anddi3 (operands[0], |
9179 | gen_lowpart (DImode, operands[1]), | |
9180 | GEN_INT (0x7fffffff))); | |
c7453384 | 9181 | DONE; |
10bbf137 | 9182 | }) |
4798630c D |
9183 | |
9184 | ;; Instruction definition to expand eh_return macro to support | |
9185 | ;; swapping in special linkage return addresses. | |
9186 | ||
9187 | (define_expand "eh_return" | |
9188 | [(use (match_operand 0 "register_operand" ""))] | |
9189 | "TARGET_TPF" | |
9190 | { | |
9191 | s390_emit_tpf_eh_return (operands[0]); | |
9192 | DONE; | |
9193 | }) | |
9194 | ||
7b8acc34 AK |
9195 | ; |
9196 | ; Stack Protector Patterns | |
9197 | ; | |
9198 | ||
9199 | (define_expand "stack_protect_set" | |
9200 | [(set (match_operand 0 "memory_operand" "") | |
9201 | (match_operand 1 "memory_operand" ""))] | |
9202 | "" | |
9203 | { | |
9204 | #ifdef TARGET_THREAD_SSP_OFFSET | |
9205 | operands[1] | |
9206 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9207 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9208 | #endif | |
9209 | if (TARGET_64BIT) | |
9210 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
9211 | else | |
9212 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
9213 | ||
9214 | DONE; | |
9215 | }) | |
9216 | ||
9217 | (define_insn "stack_protect_set<mode>" | |
9218 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
9219 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
9220 | "" | |
9221 | "mvc\t%O0(%G0,%R0),%S1" | |
9222 | [(set_attr "op_type" "SS")]) | |
9223 | ||
9224 | (define_expand "stack_protect_test" | |
9225 | [(set (reg:CC CC_REGNUM) | |
9226 | (compare (match_operand 0 "memory_operand" "") | |
9227 | (match_operand 1 "memory_operand" ""))) | |
9228 | (match_operand 2 "" "")] | |
9229 | "" | |
9230 | { | |
f90b7a5a | 9231 | rtx cc_reg, test; |
7b8acc34 AK |
9232 | #ifdef TARGET_THREAD_SSP_OFFSET |
9233 | operands[1] | |
9234 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9235 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9236 | #endif | |
7b8acc34 AK |
9237 | if (TARGET_64BIT) |
9238 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
9239 | else | |
9240 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
9241 | ||
f90b7a5a PB |
9242 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
9243 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
9244 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
9245 | DONE; |
9246 | }) | |
9247 | ||
9248 | (define_insn "stack_protect_test<mode>" | |
9249 | [(set (reg:CCZ CC_REGNUM) | |
9250 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
9251 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
9252 | "" | |
9253 | "clc\t%O0(%G0,%R0),%S1" | |
9254 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
9255 | |
9256 | ; This is used in s390_emit_prologue in order to prevent insns | |
9257 | ; adjusting the stack pointer to be moved over insns writing stack | |
9258 | ; slots using a copy of the stack pointer in a different register. | |
9259 | (define_insn "stack_tie" | |
9260 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
9261 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
9262 | "" | |
9263 | "" | |
9264 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
9265 | |
9266 | ||
9267 | ; | |
9268 | ; Data prefetch patterns | |
9269 | ; | |
9270 | ||
9271 | (define_insn "prefetch" | |
22d72dbc AK |
9272 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
9273 | (match_operand:SI 1 "const_int_operand" " n,n") | |
9274 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
9275 | "TARGET_Z10" | |
963fc8d0 | 9276 | { |
4fe6dea8 AK |
9277 | switch (which_alternative) |
9278 | { | |
9279 | case 0: | |
4fe6dea8 | 9280 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 9281 | case 1: |
4fe6dea8 AK |
9282 | if (larl_operand (operands[0], Pmode)) |
9283 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
9284 | default: | |
9285 | ||
9286 | /* This might be reached for symbolic operands with an odd | |
9287 | addend. We simply omit the prefetch for such rare cases. */ | |
9288 | ||
9289 | return ""; | |
9290 | } | |
9381e3f1 | 9291 | } |
22d72dbc AK |
9292 | [(set_attr "type" "load,larl") |
9293 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
9294 | (set_attr "z10prop" "z10_super") |
9295 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
9296 | |
9297 | ||
9298 | ; | |
9299 | ; Byte swap instructions | |
9300 | ; | |
9301 | ||
9302 | (define_insn "bswap<mode>2" | |
9303 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
9304 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] | |
677fbff4 | 9305 | "TARGET_CPU_ZARCH" |
07da44ab AK |
9306 | "@ |
9307 | lrv<g>r\t%0,%1 | |
9308 | lrv<g>\t%0,%1" | |
9309 | [(set_attr "type" "*,load") | |
9310 | (set_attr "op_type" "RRE,RXY") | |
9311 | (set_attr "z10prop" "z10_super")]) | |
65b1d8ea AK |
9312 | |
9313 | ||
9314 | ; | |
9315 | ; Population count instruction | |
9316 | ; | |
9317 | ||
9318 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
9319 | ; portions and stores the result in the corresponding bytes in op0. | |
9320 | (define_insn "*popcount<mode>" | |
9321 | [(set (match_operand:INT 0 "register_operand" "=d") | |
9322 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
9323 | (clobber (reg:CC CC_REGNUM))] | |
9324 | "TARGET_Z196" | |
9325 | "popcnt\t%0,%1" | |
9326 | [(set_attr "op_type" "RRE")]) | |
9327 | ||
9328 | (define_expand "popcountdi2" | |
9329 | [; popcnt op0, op1 | |
9330 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
9331 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
9332 | UNSPEC_POPCNT)) | |
9333 | (clobber (reg:CC CC_REGNUM))]) | |
9334 | ; sllg op2, op0, 32 | |
9335 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
9336 | ; agr op0, op2 | |
9337 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9338 | (clobber (reg:CC CC_REGNUM))]) | |
9339 | ; sllg op2, op0, 16 | |
17465c6e | 9340 | (set (match_dup 2) |
65b1d8ea AK |
9341 | (ashift:DI (match_dup 0) (const_int 16))) |
9342 | ; agr op0, op2 | |
9343 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9344 | (clobber (reg:CC CC_REGNUM))]) | |
9345 | ; sllg op2, op0, 8 | |
9346 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
9347 | ; agr op0, op2 | |
9348 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9349 | (clobber (reg:CC CC_REGNUM))]) | |
9350 | ; srlg op0, op0, 56 | |
9351 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
9352 | "TARGET_Z196 && TARGET_64BIT" | |
9353 | "operands[2] = gen_reg_rtx (DImode);") | |
9354 | ||
9355 | (define_expand "popcountsi2" | |
9356 | [; popcnt op0, op1 | |
9357 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
9358 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
9359 | UNSPEC_POPCNT)) | |
9360 | (clobber (reg:CC CC_REGNUM))]) | |
9361 | ; sllk op2, op0, 16 | |
17465c6e | 9362 | (set (match_dup 2) |
65b1d8ea AK |
9363 | (ashift:SI (match_dup 0) (const_int 16))) |
9364 | ; ar op0, op2 | |
9365 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9366 | (clobber (reg:CC CC_REGNUM))]) | |
9367 | ; sllk op2, op0, 8 | |
9368 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
9369 | ; ar op0, op2 | |
9370 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9371 | (clobber (reg:CC CC_REGNUM))]) | |
9372 | ; srl op0, op0, 24 | |
9373 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
9374 | "TARGET_Z196" | |
9375 | "operands[2] = gen_reg_rtx (SImode);") | |
9376 | ||
9377 | (define_expand "popcounthi2" | |
9378 | [; popcnt op0, op1 | |
9379 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
9380 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
9381 | UNSPEC_POPCNT)) | |
9382 | (clobber (reg:CC CC_REGNUM))]) | |
9383 | ; sllk op2, op0, 8 | |
17465c6e | 9384 | (set (match_dup 2) |
65b1d8ea AK |
9385 | (ashift:SI (match_dup 0) (const_int 8))) |
9386 | ; ar op0, op2 | |
9387 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9388 | (clobber (reg:CC CC_REGNUM))]) | |
9389 | ; srl op0, op0, 8 | |
9390 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
9391 | "TARGET_Z196" | |
9392 | "operands[2] = gen_reg_rtx (SImode);") | |
9393 | ||
9394 | (define_expand "popcountqi2" | |
9395 | [; popcnt op0, op1 | |
9396 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
9397 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
9398 | UNSPEC_POPCNT)) | |
9399 | (clobber (reg:CC CC_REGNUM))])] | |
9400 | "TARGET_Z196" | |
9401 | "") | |
9402 | ||
9403 | ;; | |
9404 | ;;- Copy sign instructions | |
9405 | ;; | |
9406 | ||
9407 | (define_insn "copysign<mode>3" | |
9408 | [(set (match_operand:FP 0 "register_operand" "=f") | |
9409 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
9410 | (match_operand:FP 2 "register_operand" "f")] | |
9411 | UNSPEC_COPYSIGN))] | |
9412 | "TARGET_Z196" | |
9413 | "cpsdr\t%0,%2,%1" | |
9414 | [(set_attr "op_type" "RRF") | |
9415 | (set_attr "type" "fsimp<mode>")]) |