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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
818ab71a | 2 | ;; Copyright (C) 1999-2016 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
77 | UNSPEC_LTREL_OFFSET |
78 | UNSPEC_LTREL_BASE | |
79 | UNSPEC_POOL_OFFSET | |
80 | UNSPEC_GOTENT | |
81 | UNSPEC_GOT | |
82 | UNSPEC_GOTOFF | |
83 | UNSPEC_PLT | |
84 | UNSPEC_PLTOFF | |
fd7643fb UW |
85 | |
86 | ; Literal pool | |
30a49b23 AK |
87 | UNSPEC_RELOAD_BASE |
88 | UNSPEC_MAIN_BASE | |
89 | UNSPEC_LTREF | |
90 | UNSPEC_INSN | |
91 | UNSPEC_EXECUTE | |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
3af82a61 AK |
159 | UNSPEC_VEC_MERGEH |
160 | UNSPEC_VEC_MERGEL | |
161 | UNSPEC_VEC_PACK | |
162 | UNSPEC_VEC_PACK_SATURATE | |
163 | UNSPEC_VEC_PACK_SATURATE_CC | |
164 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
165 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
168 | UNSPEC_VEC_PERM | |
169 | UNSPEC_VEC_PERMI | |
170 | UNSPEC_VEC_EXTEND | |
171 | UNSPEC_VEC_STORE_LEN | |
172 | UNSPEC_VEC_UNPACKH | |
173 | UNSPEC_VEC_UNPACKH_L | |
174 | UNSPEC_VEC_UNPACKL | |
175 | UNSPEC_VEC_UNPACKL_L | |
176 | UNSPEC_VEC_ADDC | |
177 | UNSPEC_VEC_ADDC_U128 | |
178 | UNSPEC_VEC_ADDE_U128 | |
179 | UNSPEC_VEC_ADDEC_U128 | |
180 | UNSPEC_VEC_AVG | |
181 | UNSPEC_VEC_AVGU | |
182 | UNSPEC_VEC_CHECKSUM | |
183 | UNSPEC_VEC_GFMSUM | |
184 | UNSPEC_VEC_GFMSUM_128 | |
185 | UNSPEC_VEC_GFMSUM_ACCUM | |
186 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
187 | UNSPEC_VEC_SET | |
188 | ||
189 | UNSPEC_VEC_VSUMG | |
190 | UNSPEC_VEC_VSUMQ | |
191 | UNSPEC_VEC_VSUM | |
192 | UNSPEC_VEC_RL_MASK | |
193 | UNSPEC_VEC_SLL | |
194 | UNSPEC_VEC_SLB | |
195 | UNSPEC_VEC_SLDB | |
196 | UNSPEC_VEC_SRAL | |
197 | UNSPEC_VEC_SRAB | |
198 | UNSPEC_VEC_SRL | |
199 | UNSPEC_VEC_SRLB | |
200 | ||
201 | UNSPEC_VEC_SUB_U128 | |
202 | UNSPEC_VEC_SUBC | |
203 | UNSPEC_VEC_SUBC_U128 | |
204 | UNSPEC_VEC_SUBE_U128 | |
205 | UNSPEC_VEC_SUBEC_U128 | |
206 | ||
207 | UNSPEC_VEC_TEST_MASK | |
208 | ||
209 | UNSPEC_VEC_VFAE | |
210 | UNSPEC_VEC_VFAECC | |
211 | ||
212 | UNSPEC_VEC_VFEE | |
213 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
214 | UNSPEC_VEC_VFENE |
215 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
216 | |
217 | UNSPEC_VEC_VISTR | |
218 | UNSPEC_VEC_VISTRCC | |
219 | ||
220 | UNSPEC_VEC_VSTRC | |
221 | UNSPEC_VEC_VSTRCCC | |
222 | ||
223 | UNSPEC_VEC_VCDGB | |
224 | UNSPEC_VEC_VCDLGB | |
225 | ||
226 | UNSPEC_VEC_VCGDB | |
227 | UNSPEC_VEC_VCLGDB | |
228 | ||
229 | UNSPEC_VEC_VFIDB | |
230 | ||
231 | UNSPEC_VEC_VLDEB | |
232 | UNSPEC_VEC_VLEDB | |
233 | ||
234 | UNSPEC_VEC_VFTCIDB | |
235 | UNSPEC_VEC_VFTCIDBCC | |
085261c8 | 236 | ]) |
fd3cd001 UW |
237 | |
238 | ;; | |
239 | ;; UNSPEC_VOLATILE usage | |
240 | ;; | |
241 | ||
30a49b23 AK |
242 | (define_c_enum "unspecv" [ |
243 | ; Blockage | |
244 | UNSPECV_BLOCKAGE | |
10bbf137 | 245 | |
2f7e5a0d | 246 | ; TPF Support |
30a49b23 AK |
247 | UNSPECV_TPF_PROLOGUE |
248 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 249 | |
10bbf137 | 250 | ; Literal pool |
30a49b23 AK |
251 | UNSPECV_POOL |
252 | UNSPECV_POOL_SECTION | |
253 | UNSPECV_POOL_ALIGN | |
254 | UNSPECV_POOL_ENTRY | |
255 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
256 | |
257 | ; TLS support | |
30a49b23 | 258 | UNSPECV_SET_TP |
e0374221 AS |
259 | |
260 | ; Atomic Support | |
30a49b23 AK |
261 | UNSPECV_CAS |
262 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 263 | |
f8af0e30 DV |
264 | ; Hotpatching (unremovable NOPs) |
265 | UNSPECV_NOP_2_BYTE | |
266 | UNSPECV_NOP_4_BYTE | |
267 | UNSPECV_NOP_6_BYTE | |
268 | ||
5a3fe9b6 AK |
269 | ; Transactional Execution support |
270 | UNSPECV_TBEGIN | |
2561451d | 271 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
272 | UNSPECV_TBEGINC |
273 | UNSPECV_TEND | |
274 | UNSPECV_TABORT | |
275 | UNSPECV_ETND | |
276 | UNSPECV_NTSTG | |
277 | UNSPECV_PPA | |
004f64e1 AK |
278 | |
279 | ; Set and get floating point control register | |
280 | UNSPECV_SFPC | |
281 | UNSPECV_EFPC | |
4cb4721f MK |
282 | |
283 | ; Split stack support | |
284 | UNSPECV_SPLIT_STACK_CALL | |
285 | UNSPECV_SPLIT_STACK_DATA | |
fd3cd001 UW |
286 | ]) |
287 | ||
ae156f85 AS |
288 | ;; |
289 | ;; Registers | |
290 | ;; | |
291 | ||
35dd9a0e AK |
292 | ; Registers with special meaning |
293 | ||
ae156f85 AS |
294 | (define_constants |
295 | [ | |
296 | ; Sibling call register. | |
297 | (SIBCALL_REGNUM 1) | |
298 | ; Literal pool base register. | |
299 | (BASE_REGNUM 13) | |
300 | ; Return address register. | |
301 | (RETURN_REGNUM 14) | |
302 | ; Condition code register. | |
303 | (CC_REGNUM 33) | |
f4aa3848 | 304 | ; Thread local storage pointer register. |
ae156f85 AS |
305 | (TP_REGNUM 36) |
306 | ]) | |
307 | ||
35dd9a0e AK |
308 | ; Hardware register names |
309 | ||
310 | (define_constants | |
311 | [ | |
312 | ; General purpose registers | |
313 | (GPR0_REGNUM 0) | |
af344a30 | 314 | (GPR1_REGNUM 1) |
82379bdf AK |
315 | (GPR2_REGNUM 2) |
316 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
317 | ; Floating point registers. |
318 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
319 | (FPR1_REGNUM 20) |
320 | (FPR2_REGNUM 17) | |
321 | (FPR3_REGNUM 21) | |
322 | (FPR4_REGNUM 18) | |
323 | (FPR5_REGNUM 22) | |
324 | (FPR6_REGNUM 19) | |
325 | (FPR7_REGNUM 23) | |
326 | (FPR8_REGNUM 24) | |
327 | (FPR9_REGNUM 28) | |
328 | (FPR10_REGNUM 25) | |
329 | (FPR11_REGNUM 29) | |
330 | (FPR12_REGNUM 26) | |
331 | (FPR13_REGNUM 30) | |
332 | (FPR14_REGNUM 27) | |
333 | (FPR15_REGNUM 31) | |
085261c8 AK |
334 | (VR0_REGNUM 16) |
335 | (VR16_REGNUM 38) | |
336 | (VR23_REGNUM 45) | |
337 | (VR24_REGNUM 46) | |
338 | (VR31_REGNUM 53) | |
35dd9a0e AK |
339 | ]) |
340 | ||
341 | ;; | |
342 | ;; PFPO GPR0 argument format | |
343 | ;; | |
344 | ||
345 | (define_constants | |
346 | [ | |
347 | ; PFPO operation type | |
348 | (PFPO_CONVERT 0x1000000) | |
349 | ; PFPO operand types | |
350 | (PFPO_OP_TYPE_SF 0x5) | |
351 | (PFPO_OP_TYPE_DF 0x6) | |
352 | (PFPO_OP_TYPE_TF 0x7) | |
353 | (PFPO_OP_TYPE_SD 0x8) | |
354 | (PFPO_OP_TYPE_DD 0x9) | |
355 | (PFPO_OP_TYPE_TD 0xa) | |
356 | ; Bitposition of operand types | |
357 | (PFPO_OP0_TYPE_SHIFT 16) | |
358 | (PFPO_OP1_TYPE_SHIFT 8) | |
359 | ]) | |
360 | ||
5a3fe9b6 AK |
361 | ; Immediate operands for tbegin and tbeginc |
362 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
363 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 364 | |
29a74354 UW |
365 | ;; Instruction operand type as used in the Principles of Operation. |
366 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 367 | |
29a74354 | 368 | (define_attr "op_type" |
62d3f261 | 369 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" |
b628bd8e | 370 | (const_string "NN")) |
9db1d521 | 371 | |
29a74354 | 372 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 373 | |
077dab3b | 374 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 375 | cs,vs,store,sem,idiv, |
ed0e512a | 376 | imulhi,imulsi,imuldi, |
2cdece44 | 377 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
378 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
379 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 380 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 381 | fmadddf,fmaddsf, |
9381e3f1 WG |
382 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
383 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
384 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
385 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
386 | ftoidfp, other" | |
29a74354 UW |
387 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
388 | (eq_attr "op_type" "SS") (const_string "cs")] | |
389 | (const_string "integer"))) | |
9db1d521 | 390 | |
29a74354 UW |
391 | ;; Another attribute used for scheduling purposes: |
392 | ;; agen: Instruction uses the address generation unit | |
393 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
394 | |
395 | (define_attr "atype" "agen,reg" | |
62d3f261 | 396 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
397 | (const_string "reg") |
398 | (const_string "agen"))) | |
9db1d521 | 399 | |
9381e3f1 WG |
400 | ;; Properties concerning Z10 execution grouping and value forwarding. |
401 | ;; z10_super: instruction is superscalar. | |
402 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
403 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
404 | ;; target register. It can forward this value to a second instruction that reads | |
405 | ;; the same register if that second instruction is issued in the same group. | |
406 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
407 | ;; instruction in the S pipe writes to the register, then the T instruction | |
408 | ;; can immediately read the new value. | |
409 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
410 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
411 | ;; |
412 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
413 | ||
414 | ||
415 | (define_attr "z10prop" "none, | |
416 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
417 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
418 | z10_rec, | |
419 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 420 | z10_c" |
9381e3f1 WG |
421 | (const_string "none")) |
422 | ||
65b1d8ea AK |
423 | ;; Properties concerning Z196 decoding |
424 | ;; z196_alone: must group alone | |
425 | ;; z196_end: ends a group | |
426 | ;; z196_cracked: instruction is cracked or expanded | |
427 | (define_attr "z196prop" "none, | |
428 | z196_alone, z196_ends, | |
429 | z196_cracked" | |
430 | (const_string "none")) | |
9381e3f1 | 431 | |
a9cc3f58 | 432 | (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 433 | |
9db1d521 HP |
434 | ;; Length in bytes. |
435 | ||
436 | (define_attr "length" "" | |
62d3f261 AK |
437 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
438 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 439 | (const_int 6))) |
9db1d521 | 440 | |
29a74354 UW |
441 | |
442 | ;; Processor type. This attribute must exactly match the processor_type | |
443 | ;; enumeration in s390.h. The current machine description does not | |
444 | ;; distinguish between g5 and g6, but there are differences between the two | |
445 | ;; CPUs could in theory be modeled. | |
446 | ||
55ac540c | 447 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13" |
90c6fd8a | 448 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 449 | |
b5e0425c | 450 | (define_attr "cpu_facility" |
55ac540c | 451 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec" |
3af8e996 AK |
452 | (const_string "standard")) |
453 | ||
454 | (define_attr "enabled" "" | |
455 | (cond [(eq_attr "cpu_facility" "standard") | |
456 | (const_int 1) | |
457 | ||
458 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 459 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
460 | (const_int 1) |
461 | ||
462 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 463 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
464 | (const_int 1) |
465 | ||
466 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 467 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
468 | (const_int 1) |
469 | ||
470 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 471 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
472 | (const_int 1) |
473 | ||
474 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 475 | (match_test "TARGET_DFP")) |
93538e8e AK |
476 | (const_int 1) |
477 | ||
b5e0425c AK |
478 | (and (eq_attr "cpu_facility" "cpu_zarch") |
479 | (match_test "TARGET_CPU_ZARCH")) | |
480 | (const_int 1) | |
481 | ||
93538e8e | 482 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 483 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
484 | (const_int 1) |
485 | ||
486 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 487 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
488 | (const_int 1) |
489 | ||
490 | (and (eq_attr "cpu_facility" "zEC12") | |
491 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
492 | (const_int 1) |
493 | ||
494 | (and (eq_attr "cpu_facility" "vec") | |
495 | (match_test "TARGET_VX")) | |
3af8e996 AK |
496 | (const_int 1)] |
497 | (const_int 0))) | |
498 | ||
29a74354 UW |
499 | ;; Pipeline description for z900. For lack of anything better, |
500 | ;; this description is also used for the g5 and g6. | |
501 | (include "2064.md") | |
502 | ||
3443392a | 503 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
504 | (include "2084.md") |
505 | ||
9381e3f1 WG |
506 | ;; Pipeline description for z10 |
507 | (include "2097.md") | |
508 | ||
65b1d8ea AK |
509 | ;; Pipeline description for z196 |
510 | (include "2817.md") | |
511 | ||
22ac2c2f AK |
512 | ;; Pipeline description for zEC12 |
513 | (include "2827.md") | |
514 | ||
23902021 AK |
515 | ;; Pipeline description for z13 |
516 | (include "2964.md") | |
517 | ||
0bfc3f69 AS |
518 | ;; Predicates |
519 | (include "predicates.md") | |
520 | ||
cd8dc1f9 WG |
521 | ;; Constraint definitions |
522 | (include "constraints.md") | |
523 | ||
a8ba31f2 EC |
524 | ;; Other includes |
525 | (include "tpf.md") | |
f52c81dd | 526 | |
3abcb3a7 | 527 | ;; Iterators |
f52c81dd | 528 | |
085261c8 AK |
529 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
530 | ||
3abcb3a7 | 531 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 532 | ;; same template. |
f4aa3848 | 533 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 534 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
535 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
536 | (define_mode_iterator BFP [TF DF SF]) | |
537 | (define_mode_iterator DFP [TD DD]) | |
538 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
539 | (define_mode_iterator DSF [DF SF]) | |
540 | (define_mode_iterator SD_SF [SF SD]) | |
541 | (define_mode_iterator DD_DF [DF DD]) | |
542 | (define_mode_iterator TD_TF [TF TD]) | |
543 | ||
3abcb3a7 | 544 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 545 | ;; from the same template. |
9602b6a1 | 546 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 547 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 548 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 549 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 550 | |
3abcb3a7 | 551 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 552 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 553 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 554 | |
78ce265b RH |
555 | ;; These macros refer to the actual word_mode of the configuration. |
556 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
557 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
558 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
559 | ||
6e0d70c9 AK |
560 | ;; Used by the umul pattern to express modes having half the size. |
561 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
562 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
563 | ||
3abcb3a7 | 564 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 565 | ;; the same template. |
3abcb3a7 | 566 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 567 | |
3abcb3a7 | 568 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 569 | ;; same template. |
9602b6a1 | 570 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 571 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
342cf42b | 572 | |
3abcb3a7 | 573 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 574 | ;; the same template. |
3abcb3a7 | 575 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 576 | |
d12a76f3 | 577 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
578 | (define_code_iterator IXOR [ior xor]) |
579 | ||
d12a76f3 AK |
580 | ;; This iterator is used to expand the patterns for the nearest |
581 | ;; integer functions. | |
582 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
583 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
584 | UNSPEC_FPINT_NEARBYINT]) | |
585 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
586 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
587 | (UNSPEC_FPINT_ROUND "round") | |
588 | (UNSPEC_FPINT_CEIL "ceil") | |
589 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
590 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
591 | (UNSPEC_FPINT_BTRUNC "5") | |
592 | (UNSPEC_FPINT_ROUND "1") | |
593 | (UNSPEC_FPINT_CEIL "6") | |
594 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
595 | ||
3abcb3a7 HPN |
596 | ;; This iterator and attribute allow to combine most atomic operations. |
597 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 598 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 599 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 600 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 601 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 602 | |
f4aa3848 | 603 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
604 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
605 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 606 | |
f4aa3848 AK |
607 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
608 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
609 | ;; SDmode. |
610 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 611 | |
609e7e80 | 612 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
613 | ;; Likewise for "<RXe>". |
614 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
615 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
616 | ||
609e7e80 | 617 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 618 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
619 | ;; dfp variants in a single insn definition. |
620 | ||
62d3f261 AK |
621 | ;; These mode attributes are supposed to be used in the `enabled' insn |
622 | ;; attribute to disable certain alternatives for certain modes. | |
623 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
624 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
625 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
626 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
627 | (TD "0") (DD "0") (DD "0") | |
628 | (TI "0") (DI "*") (SI "0")]) | |
f5905b37 | 629 | |
85dae55a AK |
630 | ;; This attribute is used in the operand constraint list |
631 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
632 | ;; TFmode values are represented by a fp register pair. Since the | |
633 | ;; sign bit instructions only handle single source and target fp registers | |
634 | ;; these instructions can only be used for TFmode values if the source and | |
635 | ;; target operand uses the same fp register. | |
636 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
637 | ||
3abcb3a7 | 638 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
639 | ;; within instruction mnemonics. |
640 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
641 | ||
0387c142 WG |
642 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
643 | ;; modes and to an empty string for bfp modes. | |
644 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
645 | ||
1b48c8cc AS |
646 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
647 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
648 | ;; version only operates on one register. | |
649 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
650 | ||
651 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
652 | ;; version only operates on one register. The DImode version needs an additional | |
653 | ;; register for the assembler output. | |
654 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
655 | |
656 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
657 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
658 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
659 | ||
660 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 661 | ;; pattern itself and the corresponding function calls. |
f337b930 | 662 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
663 | |
664 | ;; This attribute handles differences in the instruction 'type' and will result | |
665 | ;; in "RRE" for DImode and "RR" for SImode. | |
666 | (define_mode_attr E [(DI "E") (SI "")]) | |
667 | ||
3298c037 AK |
668 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
669 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
670 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
671 | ||
8006eaa6 AS |
672 | ;; This attribute handles differences in the instruction 'type' and will result |
673 | ;; in "RSE" for TImode and "RS" for DImode. | |
674 | (define_mode_attr TE [(TI "E") (DI "")]) | |
675 | ||
9a91a21f AS |
676 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
677 | ;; and "lcr" in SImode. | |
678 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 679 | |
3298c037 AK |
680 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
681 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
682 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
683 | ;; variant for long displacements. | |
684 | (define_mode_attr y [(DI "g") (SI "y")]) | |
685 | ||
9602b6a1 | 686 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
687 | ;; and "cds" in DImode. |
688 | (define_mode_attr tg [(TI "g") (DI "")]) | |
689 | ||
78ce265b RH |
690 | ;; In TDI templates, a string like "c<d>sg". |
691 | (define_mode_attr td [(TI "d") (DI "")]) | |
692 | ||
2f8f8434 AS |
693 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
694 | ;; and "cfdbr" in SImode. | |
695 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
696 | ||
65b1d8ea AK |
697 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
698 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
699 | ;; 3 operands shift instructions into the existing patterns. | |
700 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
701 | ||
f52c81dd AS |
702 | ;; ICM mask required to load MODE value into the lowest subreg |
703 | ;; of a SImode register. | |
704 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
705 | ||
f6ee577c AS |
706 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
707 | ;; HImode and "llgc" in QImode. | |
708 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
709 | ||
a1aed706 AS |
710 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
711 | ;; in SImode. | |
712 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
713 | ||
609e7e80 AK |
714 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
715 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
716 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
717 | ||
f52c81dd AS |
718 | ;; Maximum unsigned integer that fits in MODE. |
719 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
720 | ||
75ca1b39 RH |
721 | ;; Start and end field computations for RISBG et al. |
722 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
723 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
724 | ||
2542ef05 RH |
725 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
726 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
727 | ||
da0dcab1 DV |
728 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
729 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
730 | ||
177bc204 RS |
731 | ;; Allow return and simple_return to be defined from a single template. |
732 | (define_code_iterator ANY_RETURN [return simple_return]) | |
733 | ||
6e5b5de8 AK |
734 | |
735 | ||
736 | ; Condition code modes generated by vector fp comparisons. These will | |
737 | ; be used also in single element mode. | |
738 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
739 | ; Used with VFCMP to expand part of the mnemonic | |
740 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
741 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
3af82a61 | 742 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 AK |
743 | |
744 | ||
085261c8 AK |
745 | (include "vector.md") |
746 | ||
9db1d521 HP |
747 | ;; |
748 | ;;- Compare instructions. | |
749 | ;; | |
750 | ||
07893d4f | 751 | ; Test-under-Mask instructions |
9db1d521 | 752 | |
07893d4f | 753 | (define_insn "*tmqi_mem" |
ae156f85 | 754 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
755 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
756 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
757 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 758 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 759 | "@ |
fc0ea003 UW |
760 | tm\t%S0,%b1 |
761 | tmy\t%S0,%b1" | |
9381e3f1 WG |
762 | [(set_attr "op_type" "SI,SIY") |
763 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 764 | |
05b9aaaa | 765 | (define_insn "*tmdi_reg" |
ae156f85 | 766 | [(set (reg CC_REGNUM) |
f19a9af7 | 767 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 768 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
769 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
770 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 771 | "TARGET_ZARCH |
3ed99cc9 | 772 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
773 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
774 | "@ | |
775 | tmhh\t%0,%i1 | |
776 | tmhl\t%0,%i1 | |
777 | tmlh\t%0,%i1 | |
778 | tmll\t%0,%i1" | |
9381e3f1 WG |
779 | [(set_attr "op_type" "RI") |
780 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
781 | |
782 | (define_insn "*tmsi_reg" | |
ae156f85 | 783 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
784 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
785 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
786 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 787 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
788 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
789 | "@ | |
790 | tmh\t%0,%i1 | |
791 | tml\t%0,%i1" | |
729e750f WG |
792 | [(set_attr "op_type" "RI") |
793 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 794 | |
f52c81dd | 795 | (define_insn "*tm<mode>_full" |
ae156f85 | 796 | [(set (reg CC_REGNUM) |
f52c81dd AS |
797 | (compare (match_operand:HQI 0 "register_operand" "d") |
798 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 799 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 800 | "tml\t%0,<max_uint>" |
729e750f WG |
801 | [(set_attr "op_type" "RI") |
802 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 803 | |
07893d4f | 804 | |
08a5aaa2 | 805 | ; |
07893d4f | 806 | ; Load-and-Test instructions |
08a5aaa2 AS |
807 | ; |
808 | ||
c0220ea4 | 809 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
810 | |
811 | (define_insn "*tstdi_sign" | |
ae156f85 | 812 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
813 | (compare |
814 | (ashiftrt:DI | |
815 | (ashift:DI | |
816 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
817 | (const_int 32)) (const_int 32)) | |
818 | (match_operand:DI 1 "const0_operand" ""))) | |
819 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 820 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 821 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
822 | "ltgfr\t%2,%0 |
823 | ltgf\t%2,%0" | |
824 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
825 | (set_attr "cpu_facility" "*,z10") |
826 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 827 | |
43a09b63 | 828 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 829 | (define_insn "*tst<mode>_extimm" |
ec24698e | 830 | [(set (reg CC_REGNUM) |
fb492564 | 831 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
832 | (match_operand:GPR 1 "const0_operand" ""))) |
833 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 834 | (match_dup 0))] |
08a5aaa2 | 835 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 836 | "@ |
08a5aaa2 AS |
837 | lt<g>r\t%2,%0 |
838 | lt<g>\t%2,%0" | |
9381e3f1 | 839 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 840 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 841 | |
43a09b63 | 842 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 843 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 844 | [(set (reg CC_REGNUM) |
fb492564 | 845 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
846 | (match_operand:GPR 1 "const0_operand" ""))) |
847 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
848 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 849 | "@ |
08a5aaa2 AS |
850 | lt<g>r\t%0,%0 |
851 | lt<g>\t%2,%0" | |
9381e3f1 | 852 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 853 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 854 | |
07893d4f | 855 | (define_insn "*tstdi" |
ae156f85 | 856 | [(set (reg CC_REGNUM) |
07893d4f UW |
857 | (compare (match_operand:DI 0 "register_operand" "d") |
858 | (match_operand:DI 1 "const0_operand" ""))) | |
859 | (set (match_operand:DI 2 "register_operand" "=d") | |
860 | (match_dup 0))] | |
9602b6a1 | 861 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 862 | "ltgr\t%2,%0" |
9381e3f1 WG |
863 | [(set_attr "op_type" "RRE") |
864 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 865 | |
07893d4f | 866 | (define_insn "*tstsi" |
ae156f85 | 867 | [(set (reg CC_REGNUM) |
d3632d41 | 868 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 869 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 870 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 871 | (match_dup 0))] |
ec24698e | 872 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 873 | "@ |
d40c829f | 874 | ltr\t%2,%0 |
fc0ea003 UW |
875 | icm\t%2,15,%S0 |
876 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
877 | [(set_attr "op_type" "RR,RS,RSY") |
878 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 879 | |
07893d4f | 880 | (define_insn "*tstsi_cconly" |
ae156f85 | 881 | [(set (reg CC_REGNUM) |
d3632d41 | 882 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 883 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 884 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
885 | "s390_match_ccmode(insn, CCSmode)" |
886 | "@ | |
d40c829f | 887 | ltr\t%0,%0 |
fc0ea003 UW |
888 | icm\t%2,15,%S0 |
889 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
890 | [(set_attr "op_type" "RR,RS,RSY") |
891 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 892 | |
08a5aaa2 AS |
893 | (define_insn "*tstdi_cconly_31" |
894 | [(set (reg CC_REGNUM) | |
895 | (compare (match_operand:DI 0 "register_operand" "d") | |
896 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 897 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
898 | "srda\t%0,0" |
899 | [(set_attr "op_type" "RS") | |
900 | (set_attr "atype" "reg")]) | |
901 | ||
43a09b63 | 902 | ; ltr, ltgr |
08a5aaa2 | 903 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 904 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
905 | (compare (match_operand:GPR 0 "register_operand" "d") |
906 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 907 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 908 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
909 | [(set_attr "op_type" "RR<E>") |
910 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 911 | |
c0220ea4 | 912 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 913 | |
f52c81dd | 914 | (define_insn "*tst<mode>CCT" |
ae156f85 | 915 | [(set (reg CC_REGNUM) |
f52c81dd AS |
916 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
917 | (match_operand:HQI 1 "const0_operand" ""))) | |
918 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
919 | (match_dup 0))] |
920 | "s390_match_ccmode(insn, CCTmode)" | |
921 | "@ | |
f52c81dd AS |
922 | icm\t%2,<icm_lo>,%S0 |
923 | icmy\t%2,<icm_lo>,%S0 | |
924 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
925 | [(set_attr "op_type" "RS,RSY,RI") |
926 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
927 | |
928 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 929 | [(set (reg CC_REGNUM) |
d3632d41 | 930 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 931 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 932 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
933 | "s390_match_ccmode(insn, CCTmode)" |
934 | "@ | |
fc0ea003 UW |
935 | icm\t%2,3,%S0 |
936 | icmy\t%2,3,%S0 | |
d40c829f | 937 | tml\t%0,65535" |
9381e3f1 WG |
938 | [(set_attr "op_type" "RS,RSY,RI") |
939 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 940 | |
3af97654 | 941 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 942 | [(set (reg CC_REGNUM) |
d3632d41 | 943 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
944 | (match_operand:QI 1 "const0_operand" "")))] |
945 | "s390_match_ccmode(insn, CCTmode)" | |
946 | "@ | |
fc0ea003 UW |
947 | cli\t%S0,0 |
948 | cliy\t%S0,0 | |
d40c829f | 949 | tml\t%0,255" |
9381e3f1 | 950 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 951 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 952 | |
f52c81dd | 953 | (define_insn "*tst<mode>" |
ae156f85 | 954 | [(set (reg CC_REGNUM) |
f52c81dd AS |
955 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
956 | (match_operand:HQI 1 "const0_operand" ""))) | |
957 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
958 | (match_dup 0))] |
959 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 960 | "@ |
f52c81dd AS |
961 | icm\t%2,<icm_lo>,%S0 |
962 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
963 | [(set_attr "op_type" "RS,RSY") |
964 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 965 | |
f52c81dd | 966 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 967 | [(set (reg CC_REGNUM) |
f52c81dd AS |
968 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
969 | (match_operand:HQI 1 "const0_operand" ""))) | |
970 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 971 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 972 | "@ |
f52c81dd AS |
973 | icm\t%2,<icm_lo>,%S0 |
974 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
975 | [(set_attr "op_type" "RS,RSY") |
976 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 977 | |
9db1d521 | 978 | |
575f7c2b UW |
979 | ; Compare (equality) instructions |
980 | ||
981 | (define_insn "*cmpdi_cct" | |
ae156f85 | 982 | [(set (reg CC_REGNUM) |
ec24698e | 983 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 984 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 985 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
986 | "@ |
987 | cgr\t%0,%1 | |
f4f41b4e | 988 | cghi\t%0,%h1 |
ec24698e | 989 | cgfi\t%0,%1 |
575f7c2b | 990 | cg\t%0,%1 |
19b63d8e | 991 | #" |
9381e3f1 WG |
992 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
993 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
994 | |
995 | (define_insn "*cmpsi_cct" | |
ae156f85 | 996 | [(set (reg CC_REGNUM) |
ec24698e UW |
997 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
998 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 999 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1000 | "@ |
1001 | cr\t%0,%1 | |
f4f41b4e | 1002 | chi\t%0,%h1 |
ec24698e | 1003 | cfi\t%0,%1 |
575f7c2b UW |
1004 | c\t%0,%1 |
1005 | cy\t%0,%1 | |
19b63d8e | 1006 | #" |
9381e3f1 | 1007 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 1008 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1009 | |
07893d4f | 1010 | ; Compare (signed) instructions |
4023fb28 | 1011 | |
07893d4f | 1012 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1013 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1014 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
1015 | "d,RT,b")) | |
1016 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 1017 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1018 | "@ |
d40c829f | 1019 | cgfr\t%0,%1 |
963fc8d0 AK |
1020 | cgf\t%0,%1 |
1021 | cgfrl\t%0,%1" | |
1022 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1023 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1024 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1025 | |
9381e3f1 WG |
1026 | |
1027 | ||
07893d4f | 1028 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1029 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1030 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1031 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1032 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1033 | "@ |
d40c829f | 1034 | ch\t%0,%1 |
963fc8d0 AK |
1035 | chy\t%0,%1 |
1036 | chrl\t%0,%1" | |
1037 | [(set_attr "op_type" "RX,RXY,RIL") | |
1038 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
1039 | (set_attr "type" "*,*,larl") |
1040 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1041 | |
1042 | (define_insn "*cmphi_ccs_z10" | |
1043 | [(set (reg CC_REGNUM) | |
1044 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1045 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1046 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1047 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1048 | [(set_attr "op_type" "SIL") |
1049 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1050 | |
1051 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1052 | [(set (reg CC_REGNUM) | |
1053 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
1054 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
1055 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1056 | "@ | |
1057 | cgh\t%0,%1 | |
1058 | cghrl\t%0,%1" | |
1059 | [(set_attr "op_type" "RXY,RIL") | |
1060 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1061 | |
963fc8d0 | 1062 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1063 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1064 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1065 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1066 | "d,d,Q, d,d,d,d") | |
1067 | (match_operand:GPR 1 "general_operand" | |
1068 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1069 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1070 | "@ |
3298c037 AK |
1071 | c<g>r\t%0,%1 |
1072 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1073 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1074 | c<g>fi\t%0,%1 |
1075 | c<g>\t%0,%1 | |
963fc8d0 AK |
1076 | c<y>\t%0,%1 |
1077 | c<g>rl\t%0,%1" | |
1078 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
1079 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
1080 | (set_attr "type" "*,*,*,*,*,*,larl") |
1081 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1082 | |
07893d4f UW |
1083 | |
1084 | ; Compare (unsigned) instructions | |
9db1d521 | 1085 | |
963fc8d0 AK |
1086 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1087 | [(set (reg CC_REGNUM) | |
1088 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1089 | "larl_operand" "X"))) | |
1090 | (match_operand:SI 0 "register_operand" "d")))] | |
1091 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1092 | "clhrl\t%0,%1" | |
1093 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1094 | (set_attr "type" "larl") |
1095 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1096 | |
1097 | ; clhrl, clghrl | |
1098 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1099 | [(set (reg CC_REGNUM) | |
1100 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1101 | "larl_operand" "X"))) | |
1102 | (match_operand:GPR 0 "register_operand" "d")))] | |
1103 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1104 | "cl<g>hrl\t%0,%1" | |
1105 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1106 | (set_attr "type" "larl") |
1107 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1108 | |
07893d4f | 1109 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1110 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1111 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
1112 | "d,RT,b")) | |
1113 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 1114 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1115 | "@ |
d40c829f | 1116 | clgfr\t%0,%1 |
963fc8d0 AK |
1117 | clgf\t%0,%1 |
1118 | clgfrl\t%0,%1" | |
1119 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1120 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1121 | (set_attr "type" "*,*,larl") |
1122 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1123 | |
07893d4f | 1124 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1125 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1126 | (compare (match_operand:DI 0 "nonimmediate_operand" |
1127 | "d, d,d,Q, d, Q,BQ") | |
1128 | (match_operand:DI 1 "general_operand" | |
1129 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 1130 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1131 | "@ |
d40c829f | 1132 | clgr\t%0,%1 |
ec24698e | 1133 | clgfi\t%0,%1 |
963fc8d0 AK |
1134 | clgrl\t%0,%1 |
1135 | clghsi\t%0,%x1 | |
575f7c2b | 1136 | clg\t%0,%1 |
e221ef54 | 1137 | # |
19b63d8e | 1138 | #" |
963fc8d0 AK |
1139 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1140 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1141 | (set_attr "type" "*,*,larl,*,*,*,*") |
1142 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1143 | |
07893d4f | 1144 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1145 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1146 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1147 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1148 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1149 | "@ |
d40c829f | 1150 | clr\t%0,%1 |
ec24698e | 1151 | clfi\t%0,%o1 |
963fc8d0 AK |
1152 | clrl\t%0,%1 |
1153 | clfhsi\t%0,%x1 | |
d40c829f | 1154 | cl\t%0,%1 |
575f7c2b | 1155 | cly\t%0,%1 |
e221ef54 | 1156 | # |
19b63d8e | 1157 | #" |
963fc8d0 AK |
1158 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
1159 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
1160 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1161 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1162 | |
07893d4f | 1163 | (define_insn "*cmphi_ccu" |
ae156f85 | 1164 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1165 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1166 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1167 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1168 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1169 | "@ |
fc0ea003 UW |
1170 | clm\t%0,3,%S1 |
1171 | clmy\t%0,3,%S1 | |
963fc8d0 | 1172 | clhhsi\t%0,%1 |
e221ef54 | 1173 | # |
19b63d8e | 1174 | #" |
963fc8d0 | 1175 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
1176 | (set_attr "cpu_facility" "*,*,z10,*,*") |
1177 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
1178 | |
1179 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1180 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1181 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1182 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1183 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1184 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1185 | "@ |
fc0ea003 UW |
1186 | clm\t%0,1,%S1 |
1187 | clmy\t%0,1,%S1 | |
1188 | cli\t%S0,%b1 | |
1189 | cliy\t%S0,%b1 | |
e221ef54 | 1190 | # |
19b63d8e | 1191 | #" |
9381e3f1 WG |
1192 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
1193 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
1194 | |
1195 | ||
19b63d8e UW |
1196 | ; Block compare (CLC) instruction patterns. |
1197 | ||
1198 | (define_insn "*clc" | |
ae156f85 | 1199 | [(set (reg CC_REGNUM) |
d4f52f0e | 1200 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1201 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1202 | (use (match_operand 2 "const_int_operand" "n"))] | |
1203 | "s390_match_ccmode (insn, CCUmode) | |
1204 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1205 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1206 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1207 | |
1208 | (define_split | |
ae156f85 | 1209 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1210 | (compare (match_operand 0 "memory_operand" "") |
1211 | (match_operand 1 "memory_operand" "")))] | |
1212 | "reload_completed | |
1213 | && s390_match_ccmode (insn, CCUmode) | |
1214 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1215 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1216 | [(parallel | |
1217 | [(set (match_dup 0) (match_dup 1)) | |
1218 | (use (match_dup 2))])] | |
1219 | { | |
1220 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1221 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1222 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1223 | ||
1224 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1225 | operands[0], operands[1]); | |
1226 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1227 | }) | |
1228 | ||
1229 | ||
609e7e80 | 1230 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1231 | |
609e7e80 | 1232 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1233 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1234 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1235 | (compare (match_operand:FP 0 "register_operand" "f") |
1236 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1237 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1238 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1239 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1240 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1241 | |
be5de7a1 | 1242 | ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb |
f5905b37 | 1243 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1244 | [(set (reg CC_REGNUM) |
609e7e80 | 1245 | (compare (match_operand:FP 0 "register_operand" "f,f") |
62d3f261 | 1246 | (match_operand:FP 1 "general_operand" "f,R")))] |
142cd70f | 1247 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1248 | "@ |
609e7e80 | 1249 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1250 | c<xde>b\t%0,%1" |
077dab3b | 1251 | [(set_attr "op_type" "RRE,RXE") |
62d3f261 AK |
1252 | (set_attr "type" "fsimp<mode>") |
1253 | (set_attr "enabled" "*,<DSF>")]) | |
9db1d521 | 1254 | |
6e5b5de8 AK |
1255 | ; wfcedbs, wfchdbs, wfchedbs |
1256 | (define_insn "*vec_cmp<insn_cmp>df_cconly" | |
1257 | [(set (reg:VFCMP CC_REGNUM) | |
1258 | (compare:VFCMP (match_operand:DF 0 "register_operand" "v") | |
1259 | (match_operand:DF 1 "register_operand" "v"))) | |
1260 | (clobber (match_scratch:V2DI 2 "=v"))] | |
1261 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
1262 | "wfc<asm_fcmp>dbs\t%v2,%v0,%v1" | |
1263 | [(set_attr "op_type" "VRR")]) | |
963fc8d0 AK |
1264 | |
1265 | ; Compare and Branch instructions | |
1266 | ||
1267 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1268 | ; The following instructions do a complementary access of their second |
1269 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1270 | (define_insn "*cmp_and_br_signed_<mode>" |
1271 | [(set (pc) | |
1272 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1273 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1274 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1275 | (label_ref (match_operand 3 "" "")) | |
1276 | (pc))) | |
1277 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1278 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1279 | { |
1280 | if (get_attr_length (insn) == 6) | |
1281 | return which_alternative ? | |
1282 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1283 | else | |
1284 | return which_alternative ? | |
1285 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1286 | } | |
1287 | [(set_attr "op_type" "RIE") | |
1288 | (set_attr "type" "branch") | |
e3cba5e5 | 1289 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1290 | (set (attr "length") |
1291 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1292 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1293 | ; 10 byte for cgr/jg | |
1294 | ||
1295 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1296 | ; The following instructions do a complementary access of their second |
1297 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1298 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1299 | [(set (pc) | |
1300 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1301 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1302 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1303 | (label_ref (match_operand 3 "" "")) | |
1304 | (pc))) | |
1305 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1306 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1307 | { |
1308 | if (get_attr_length (insn) == 6) | |
1309 | return which_alternative ? | |
1310 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1311 | else | |
1312 | return which_alternative ? | |
1313 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1314 | } | |
1315 | [(set_attr "op_type" "RIE") | |
1316 | (set_attr "type" "branch") | |
e3cba5e5 | 1317 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1318 | (set (attr "length") |
1319 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1320 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1321 | ; 10 byte for clgr/jg | |
1322 | ||
b0f86a7e AK |
1323 | ; And now the same two patterns as above but with a negated CC mask. |
1324 | ||
1325 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1326 | ; The following instructions do a complementary access of their second | |
1327 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1328 | (define_insn "*icmp_and_br_signed_<mode>" | |
1329 | [(set (pc) | |
1330 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1331 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1332 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1333 | (pc) | |
1334 | (label_ref (match_operand 3 "" "")))) | |
1335 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1336 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1337 | { |
1338 | if (get_attr_length (insn) == 6) | |
1339 | return which_alternative ? | |
1340 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1341 | else | |
1342 | return which_alternative ? | |
1343 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1344 | } | |
1345 | [(set_attr "op_type" "RIE") | |
1346 | (set_attr "type" "branch") | |
1347 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1348 | (set (attr "length") | |
1349 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1350 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1351 | ; 10 byte for cgr/jg | |
1352 | ||
1353 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1354 | ; The following instructions do a complementary access of their second | |
1355 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1356 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1357 | [(set (pc) | |
1358 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1359 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1360 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1361 | (pc) | |
1362 | (label_ref (match_operand 3 "" "")))) | |
1363 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1364 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1365 | { |
1366 | if (get_attr_length (insn) == 6) | |
1367 | return which_alternative ? | |
1368 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1369 | else | |
1370 | return which_alternative ? | |
1371 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1372 | } | |
1373 | [(set_attr "op_type" "RIE") | |
1374 | (set_attr "type" "branch") | |
1375 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1376 | (set (attr "length") | |
1377 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1378 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1379 | ; 10 byte for clgr/jg | |
1380 | ||
9db1d521 HP |
1381 | ;; |
1382 | ;;- Move instructions. | |
1383 | ;; | |
1384 | ||
1385 | ; | |
1386 | ; movti instruction pattern(s). | |
1387 | ; | |
1388 | ||
085261c8 AK |
1389 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1390 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1391 | (define_insn "movti" |
085261c8 AK |
1392 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o") |
1393 | (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))] | |
9602b6a1 | 1394 | "TARGET_ZARCH" |
4023fb28 | 1395 | "@ |
fc0ea003 UW |
1396 | lmg\t%0,%N0,%S1 |
1397 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1398 | vlr\t%v0,%v1 |
1399 | vzero\t%v0 | |
1400 | vone\t%v0 | |
1401 | vlvgp\t%v0,%1,%N1 | |
1402 | # | |
1403 | vl\t%v0,%1 | |
1404 | vst\t%v1,%0 | |
4023fb28 | 1405 | # |
19b63d8e | 1406 | #" |
085261c8 AK |
1407 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1408 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
1409 | (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")]) | |
4023fb28 UW |
1410 | |
1411 | (define_split | |
1412 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1413 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1414 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1415 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1416 | [(set (match_dup 2) (match_dup 4)) |
1417 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1418 | { |
dc65c307 UW |
1419 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1420 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1421 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1422 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1423 | }) | |
1424 | ||
1425 | (define_split | |
1426 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1427 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1428 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1429 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1430 | [(set (match_dup 2) (match_dup 4)) | |
1431 | (set (match_dup 3) (match_dup 5))] | |
1432 | { | |
1433 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1434 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1435 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1436 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1437 | }) | |
4023fb28 | 1438 | |
085261c8 AK |
1439 | ; Use part of the TImode target reg to perform the address |
1440 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1441 | ; this splitter is not necessary. | |
4023fb28 UW |
1442 | (define_split |
1443 | [(set (match_operand:TI 0 "register_operand" "") | |
1444 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1445 | "TARGET_ZARCH && reload_completed |
085261c8 | 1446 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1447 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1448 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1449 | { |
1450 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1451 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1452 | s390_load_address (addr, XEXP (operands[1], 0)); |
1453 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1454 | }) |
1455 | ||
833cd70a | 1456 | |
085261c8 AK |
1457 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1458 | ; For the higher order bits we do simply a DImode move while the | |
1459 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1460 | (define_split | |
1461 | [(set (match_operand:TI 0 "register_operand" "") | |
1462 | (match_operand:TI 1 "register_operand" ""))] | |
1463 | "TARGET_VX && reload_completed | |
1464 | && GENERAL_REG_P (operands[0]) | |
1465 | && VECTOR_REG_P (operands[1])" | |
1466 | [(set (match_dup 2) (match_dup 4)) | |
1467 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1468 | UNSPEC_VEC_EXTRACT))] | |
1469 | { | |
1470 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1471 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1472 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1473 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1474 | }) | |
1475 | ||
833cd70a AK |
1476 | ; |
1477 | ; Patterns used for secondary reloads | |
1478 | ; | |
1479 | ||
963fc8d0 AK |
1480 | ; z10 provides move instructions accepting larl memory operands. |
1481 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1482 | ; These patterns are also used for unaligned SI and DI accesses. | |
1483 | ||
085261c8 AK |
1484 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1485 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1486 | (match_operand:ALL 1 "register_operand" "=d") | |
1487 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1488 | "TARGET_Z10" |
1489 | { | |
1490 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1491 | DONE; | |
1492 | }) | |
1493 | ||
085261c8 AK |
1494 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1495 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1496 | (match_operand:ALL 1 "memory_operand" "") | |
1497 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1498 | "TARGET_Z10" |
1499 | { | |
1500 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1501 | DONE; | |
1502 | }) | |
1503 | ||
1504 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1505 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1506 | (match_operand:P 1 "larl_operand" "") | |
1507 | (match_operand:P 2 "register_operand" "=a")])] | |
1508 | "TARGET_Z10" | |
1509 | { | |
1510 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1511 | DONE; | |
1512 | }) | |
1513 | ||
833cd70a AK |
1514 | ; Handles loading a PLUS (load address) expression |
1515 | ||
1516 | (define_expand "reload<mode>_plus" | |
1517 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1518 | (match_operand:P 1 "s390_plus_operand" "") | |
1519 | (match_operand:P 2 "register_operand" "=&a")])] | |
1520 | "" | |
1521 | { | |
1522 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1523 | DONE; | |
1524 | }) | |
1525 | ||
085261c8 AK |
1526 | ; Not all the indirect memory access instructions support the full |
1527 | ; format (long disp + index + base). So whenever a move from/to such | |
1528 | ; an address is required and the instruction cannot deal with it we do | |
1529 | ; a load address into a scratch register first and use this as the new | |
1530 | ; base register. | |
1531 | ; This in particular is used for: | |
1532 | ; - non-offsetable memory accesses for multiword moves | |
1533 | ; - full vector reg moves with long displacements | |
833cd70a | 1534 | |
085261c8 | 1535 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1536 | [(parallel [(match_operand 0 "register_operand" "") |
1537 | (match_operand 1 "" "") | |
1538 | (match_operand:P 2 "register_operand" "=&a")])] | |
1539 | "" | |
1540 | { | |
1541 | gcc_assert (MEM_P (operands[1])); | |
1542 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1543 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1544 | emit_move_insn (operands[0], operands[1]); | |
1545 | DONE; | |
1546 | }) | |
1547 | ||
085261c8 | 1548 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1549 | [(parallel [(match_operand 0 "" "") |
1550 | (match_operand 1 "register_operand" "") | |
1551 | (match_operand:P 2 "register_operand" "=&a")])] | |
1552 | "" | |
dc65c307 | 1553 | { |
9c3c3dcc | 1554 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1555 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1556 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1557 | emit_move_insn (operands[0], operands[1]); | |
1558 | DONE; | |
1559 | }) | |
9db1d521 | 1560 | |
1f9e1fc6 AK |
1561 | (define_expand "reload<mode>_PIC_addr" |
1562 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1563 | (match_operand 1 "larl_operand" "") | |
1564 | (match_operand:P 2 "register_operand" "=a")])] | |
1565 | "" | |
1566 | { | |
0a2aaacc KG |
1567 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1568 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1569 | }) |
1570 | ||
9db1d521 HP |
1571 | ; |
1572 | ; movdi instruction pattern(s). | |
1573 | ; | |
1574 | ||
9db1d521 HP |
1575 | (define_expand "movdi" |
1576 | [(set (match_operand:DI 0 "general_operand" "") | |
1577 | (match_operand:DI 1 "general_operand" ""))] | |
1578 | "" | |
9db1d521 | 1579 | { |
fd3cd001 | 1580 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1581 | if (TARGET_64BIT |
1582 | && (SYMBOLIC_CONST (operands[1]) | |
1583 | || (GET_CODE (operands[1]) == PLUS | |
1584 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1585 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1586 | emit_symbolic_move (operands); |
10bbf137 | 1587 | }) |
9db1d521 | 1588 | |
4023fb28 UW |
1589 | (define_insn "*movdi_larl" |
1590 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1591 | (match_operand:DI 1 "larl_operand" "X"))] | |
1592 | "TARGET_64BIT | |
8e509cf9 | 1593 | && !FP_REG_P (operands[0])" |
d40c829f | 1594 | "larl\t%0,%1" |
4023fb28 | 1595 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1596 | (set_attr "type" "larl") |
1597 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1598 | |
3af8e996 | 1599 | (define_insn "*movdi_64" |
85dae55a | 1600 | [(set (match_operand:DI 0 "nonimmediate_operand" |
085261c8 | 1601 | "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR") |
85dae55a | 1602 | (match_operand:DI 1 "general_operand" |
085261c8 | 1603 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))] |
9602b6a1 | 1604 | "TARGET_ZARCH" |
85dae55a AK |
1605 | "@ |
1606 | lghi\t%0,%h1 | |
1607 | llihh\t%0,%i1 | |
1608 | llihl\t%0,%i1 | |
1609 | llilh\t%0,%i1 | |
1610 | llill\t%0,%i1 | |
1611 | lgfi\t%0,%1 | |
1612 | llihf\t%0,%k1 | |
1613 | llilf\t%0,%k1 | |
1614 | ldgr\t%0,%1 | |
1615 | lgdr\t%0,%1 | |
1616 | lay\t%0,%a1 | |
963fc8d0 | 1617 | lgrl\t%0,%1 |
85dae55a AK |
1618 | lgr\t%0,%1 |
1619 | lg\t%0,%1 | |
1620 | stg\t%1,%0 | |
1621 | ldr\t%0,%1 | |
1622 | ld\t%0,%1 | |
1623 | ldy\t%0,%1 | |
1624 | std\t%1,%0 | |
1625 | stdy\t%1,%0 | |
963fc8d0 AK |
1626 | stgrl\t%1,%0 |
1627 | mvghi\t%0,%1 | |
85dae55a AK |
1628 | # |
1629 | # | |
1630 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1631 | lam\t%0,%N0,%S1 |
1632 | vleig\t%v0,%h1,0 | |
1633 | vlr\t%v0,%v1 | |
1634 | vlvgg\t%v0,%1,0 | |
1635 | vlgvg\t%0,%v1,0 | |
1636 | vleg\t%v0,%1,0 | |
1637 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1638 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1639 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1640 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1641 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1642 | *,*,*,*,*,*,*") | |
3af8e996 | 1643 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1644 | z10,*,*,*,*,*,longdisp,*,longdisp, |
085261c8 | 1645 | z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec") |
9381e3f1 WG |
1646 | (set_attr "z10prop" "z10_fwd_A1, |
1647 | z10_fwd_E1, | |
1648 | z10_fwd_E1, | |
1649 | z10_fwd_E1, | |
1650 | z10_fwd_E1, | |
1651 | z10_fwd_A1, | |
1652 | z10_fwd_E1, | |
1653 | z10_fwd_E1, | |
1654 | *, | |
1655 | *, | |
1656 | z10_fwd_A1, | |
1657 | z10_fwd_A3, | |
1658 | z10_fr_E1, | |
1659 | z10_fwd_A3, | |
1660 | z10_rec, | |
1661 | *, | |
1662 | *, | |
1663 | *, | |
1664 | *, | |
1665 | *, | |
1666 | z10_rec, | |
1667 | z10_super, | |
1668 | *, | |
1669 | *, | |
1670 | *, | |
085261c8 | 1671 | *,*,*,*,*,*,*") |
9381e3f1 | 1672 | ]) |
c5aa1d12 UW |
1673 | |
1674 | (define_split | |
1675 | [(set (match_operand:DI 0 "register_operand" "") | |
1676 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1677 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1678 | [(set (match_dup 2) (match_dup 3)) |
1679 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1680 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1681 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1682 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1683 | ||
1684 | (define_split | |
1685 | [(set (match_operand:DI 0 "register_operand" "") | |
1686 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1687 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1688 | && dead_or_set_p (insn, operands[1])" |
1689 | [(set (match_dup 3) (match_dup 2)) | |
1690 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1691 | (set (match_dup 4) (match_dup 2))] | |
1692 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1693 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1694 | ||
1695 | (define_split | |
1696 | [(set (match_operand:DI 0 "register_operand" "") | |
1697 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1698 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1699 | && !dead_or_set_p (insn, operands[1])" |
1700 | [(set (match_dup 3) (match_dup 2)) | |
1701 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1702 | (set (match_dup 4) (match_dup 2)) | |
1703 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1704 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1705 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1706 | |
1707 | (define_insn "*movdi_31" | |
963fc8d0 | 1708 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1709 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1710 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1711 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1712 | "!TARGET_ZARCH" |
4023fb28 | 1713 | "@ |
fc0ea003 | 1714 | lm\t%0,%N0,%S1 |
c4d50129 | 1715 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1716 | stm\t%1,%N1,%S0 |
c4d50129 | 1717 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1718 | # |
1719 | # | |
d40c829f UW |
1720 | ldr\t%0,%1 |
1721 | ld\t%0,%1 | |
1722 | ldy\t%0,%1 | |
1723 | std\t%1,%0 | |
1724 | stdy\t%1,%0 | |
19b63d8e | 1725 | #" |
f2dc2f86 AK |
1726 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1727 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1728 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1729 | |
1730 | ; For a load from a symbol ref we can use one of the target registers | |
1731 | ; together with larl to load the address. | |
1732 | (define_split | |
1733 | [(set (match_operand:DI 0 "register_operand" "") | |
1734 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1735 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1736 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1737 | [(set (match_dup 2) (match_dup 3)) | |
1738 | (set (match_dup 0) (match_dup 1))] | |
1739 | { | |
1740 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1741 | operands[3] = XEXP (operands[1], 0); | |
1742 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1743 | }) | |
4023fb28 UW |
1744 | |
1745 | (define_split | |
1746 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1747 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1748 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1749 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1750 | [(set (match_dup 2) (match_dup 4)) |
1751 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1752 | { |
dc65c307 UW |
1753 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1754 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1755 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1756 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1757 | }) | |
1758 | ||
1759 | (define_split | |
1760 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1761 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1762 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1763 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1764 | [(set (match_dup 2) (match_dup 4)) | |
1765 | (set (match_dup 3) (match_dup 5))] | |
1766 | { | |
1767 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1768 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1769 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1770 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1771 | }) | |
9db1d521 | 1772 | |
4023fb28 UW |
1773 | (define_split |
1774 | [(set (match_operand:DI 0 "register_operand" "") | |
1775 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1776 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1777 | && !FP_REG_P (operands[0]) |
4023fb28 | 1778 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1779 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1780 | { |
1781 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1782 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1783 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1784 | }) |
1785 | ||
84817c5d UW |
1786 | (define_peephole2 |
1787 | [(set (match_operand:DI 0 "register_operand" "") | |
1788 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1789 | "TARGET_ZARCH |
84817c5d UW |
1790 | && !FP_REG_P (operands[0]) |
1791 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1792 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1793 | && get_pool_mode (operands[1]) == DImode | |
1794 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1795 | [(set (match_dup 0) (match_dup 2))] | |
1796 | "operands[2] = get_pool_constant (operands[1]);") | |
1797 | ||
7bdff56f UW |
1798 | (define_insn "*la_64" |
1799 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1800 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1801 | "TARGET_64BIT" |
1802 | "@ | |
1803 | la\t%0,%a1 | |
1804 | lay\t%0,%a1" | |
1805 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1806 | (set_attr "type" "la") |
1807 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1808 | |
1809 | (define_peephole2 | |
1810 | [(parallel | |
1811 | [(set (match_operand:DI 0 "register_operand" "") | |
1812 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1813 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1814 | "TARGET_64BIT |
e1d5ee28 | 1815 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1816 | [(set (match_dup 0) (match_dup 1))] |
1817 | "") | |
1818 | ||
1819 | (define_peephole2 | |
1820 | [(set (match_operand:DI 0 "register_operand" "") | |
1821 | (match_operand:DI 1 "register_operand" "")) | |
1822 | (parallel | |
1823 | [(set (match_dup 0) | |
1824 | (plus:DI (match_dup 0) | |
1825 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1826 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1827 | "TARGET_64BIT |
1828 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1829 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1830 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1831 | "") | |
1832 | ||
9db1d521 HP |
1833 | ; |
1834 | ; movsi instruction pattern(s). | |
1835 | ; | |
1836 | ||
9db1d521 HP |
1837 | (define_expand "movsi" |
1838 | [(set (match_operand:SI 0 "general_operand" "") | |
1839 | (match_operand:SI 1 "general_operand" ""))] | |
1840 | "" | |
9db1d521 | 1841 | { |
fd3cd001 | 1842 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1843 | if (!TARGET_64BIT |
1844 | && (SYMBOLIC_CONST (operands[1]) | |
1845 | || (GET_CODE (operands[1]) == PLUS | |
1846 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1847 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1848 | emit_symbolic_move (operands); |
10bbf137 | 1849 | }) |
9db1d521 | 1850 | |
9e8327e3 UW |
1851 | (define_insn "*movsi_larl" |
1852 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1853 | (match_operand:SI 1 "larl_operand" "X"))] | |
1854 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1855 | && !FP_REG_P (operands[0])" | |
1856 | "larl\t%0,%1" | |
1857 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1858 | (set_attr "type" "larl") |
729e750f | 1859 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1860 | |
f19a9af7 | 1861 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1862 | [(set (match_operand:SI 0 "nonimmediate_operand" |
085261c8 | 1863 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR") |
2f7e5a0d | 1864 | (match_operand:SI 1 "general_operand" |
085261c8 | 1865 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))] |
f19a9af7 | 1866 | "TARGET_ZARCH" |
9db1d521 | 1867 | "@ |
f19a9af7 AK |
1868 | lhi\t%0,%h1 |
1869 | llilh\t%0,%i1 | |
1870 | llill\t%0,%i1 | |
ec24698e | 1871 | iilf\t%0,%o1 |
f19a9af7 | 1872 | lay\t%0,%a1 |
963fc8d0 | 1873 | lrl\t%0,%1 |
d40c829f UW |
1874 | lr\t%0,%1 |
1875 | l\t%0,%1 | |
1876 | ly\t%0,%1 | |
1877 | st\t%1,%0 | |
1878 | sty\t%1,%0 | |
085261c8 | 1879 | lder\t%0,%1 |
d40c829f | 1880 | ler\t%0,%1 |
085261c8 | 1881 | lde\t%0,%1 |
d40c829f UW |
1882 | le\t%0,%1 |
1883 | ley\t%0,%1 | |
1884 | ste\t%1,%0 | |
1885 | stey\t%1,%0 | |
c5aa1d12 UW |
1886 | ear\t%0,%1 |
1887 | sar\t%0,%1 | |
1888 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1889 | strl\t%1,%0 |
1890 | mvhi\t%0,%1 | |
085261c8 AK |
1891 | lam\t%0,%0,%S1 |
1892 | vleif\t%v0,%h1,0 | |
1893 | vlr\t%v0,%v1 | |
1894 | vlvgf\t%v0,%1,0 | |
1895 | vlgvf\t%0,%v1,0 | |
1896 | vlef\t%v0,%1,0 | |
1897 | vstef\t%v1,%0,0" | |
963fc8d0 | 1898 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
085261c8 | 1899 | RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
1900 | (set_attr "type" "*, |
1901 | *, | |
1902 | *, | |
1903 | *, | |
1904 | la, | |
1905 | larl, | |
1906 | lr, | |
1907 | load, | |
1908 | load, | |
1909 | store, | |
1910 | store, | |
1911 | floadsf, | |
1912 | floadsf, | |
1913 | floadsf, | |
085261c8 AK |
1914 | floadsf, |
1915 | floadsf, | |
9381e3f1 WG |
1916 | fstoresf, |
1917 | fstoresf, | |
1918 | *, | |
1919 | *, | |
1920 | *, | |
1921 | larl, | |
1922 | *, | |
085261c8 | 1923 | *,*,*,*,*,*,*") |
963fc8d0 | 1924 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
085261c8 | 1925 | vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec") |
9381e3f1 WG |
1926 | (set_attr "z10prop" "z10_fwd_A1, |
1927 | z10_fwd_E1, | |
1928 | z10_fwd_E1, | |
1929 | z10_fwd_A1, | |
1930 | z10_fwd_A1, | |
1931 | z10_fwd_A3, | |
1932 | z10_fr_E1, | |
1933 | z10_fwd_A3, | |
1934 | z10_fwd_A3, | |
729e750f | 1935 | z10_rec, |
9381e3f1 WG |
1936 | z10_rec, |
1937 | *, | |
1938 | *, | |
1939 | *, | |
1940 | *, | |
1941 | *, | |
085261c8 AK |
1942 | *, |
1943 | *, | |
9381e3f1 WG |
1944 | z10_super_E1, |
1945 | z10_super, | |
1946 | *, | |
1947 | z10_rec, | |
1948 | z10_super, | |
085261c8 | 1949 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
1950 | |
1951 | (define_insn "*movsi_esa" | |
085261c8 AK |
1952 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
1953 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1954 | "!TARGET_ZARCH" |
1955 | "@ | |
1956 | lhi\t%0,%h1 | |
1957 | lr\t%0,%1 | |
1958 | l\t%0,%1 | |
1959 | st\t%1,%0 | |
085261c8 | 1960 | lder\t%0,%1 |
f19a9af7 | 1961 | ler\t%0,%1 |
085261c8 | 1962 | lde\t%0,%1 |
f19a9af7 AK |
1963 | le\t%0,%1 |
1964 | ste\t%1,%0 | |
c5aa1d12 UW |
1965 | ear\t%0,%1 |
1966 | sar\t%0,%1 | |
1967 | stam\t%1,%1,%S0 | |
f2dc2f86 | 1968 | lam\t%0,%0,%S1" |
085261c8 AK |
1969 | [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
1970 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") | |
1971 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
1972 | z10_super,*,*") | |
1973 | (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*") | |
9381e3f1 | 1974 | ]) |
9db1d521 | 1975 | |
84817c5d UW |
1976 | (define_peephole2 |
1977 | [(set (match_operand:SI 0 "register_operand" "") | |
1978 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1979 | "!FP_REG_P (operands[0]) | |
1980 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1981 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1982 | && get_pool_mode (operands[1]) == SImode | |
1983 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1984 | [(set (match_dup 0) (match_dup 2))] | |
1985 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1986 | |
7bdff56f UW |
1987 | (define_insn "*la_31" |
1988 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1989 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1990 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1991 | "@ | |
1992 | la\t%0,%a1 | |
1993 | lay\t%0,%a1" | |
1994 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1995 | (set_attr "type" "la") |
1996 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1997 | |
1998 | (define_peephole2 | |
1999 | [(parallel | |
2000 | [(set (match_operand:SI 0 "register_operand" "") | |
2001 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2002 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2003 | "!TARGET_64BIT |
e1d5ee28 | 2004 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2005 | [(set (match_dup 0) (match_dup 1))] |
2006 | "") | |
2007 | ||
2008 | (define_peephole2 | |
2009 | [(set (match_operand:SI 0 "register_operand" "") | |
2010 | (match_operand:SI 1 "register_operand" "")) | |
2011 | (parallel | |
2012 | [(set (match_dup 0) | |
2013 | (plus:SI (match_dup 0) | |
2014 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2015 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2016 | "!TARGET_64BIT |
2017 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2018 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2019 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2020 | "") | |
2021 | ||
2022 | (define_insn "*la_31_and" | |
2023 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2024 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
2025 | (const_int 2147483647)))] |
2026 | "!TARGET_64BIT" | |
2027 | "@ | |
2028 | la\t%0,%a1 | |
2029 | lay\t%0,%a1" | |
2030 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
2031 | (set_attr "type" "la") |
2032 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
2033 | |
2034 | (define_insn_and_split "*la_31_and_cc" | |
2035 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2036 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2037 | (const_int 2147483647))) | |
ae156f85 | 2038 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2039 | "!TARGET_64BIT" |
2040 | "#" | |
2041 | "&& reload_completed" | |
2042 | [(set (match_dup 0) | |
2043 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2044 | "" | |
2045 | [(set_attr "op_type" "RX") | |
2046 | (set_attr "type" "la")]) | |
2047 | ||
2048 | (define_insn "force_la_31" | |
2049 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2050 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
2051 | (use (const_int 0))] |
2052 | "!TARGET_64BIT" | |
2053 | "@ | |
2054 | la\t%0,%a1 | |
2055 | lay\t%0,%a1" | |
2056 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
2057 | (set_attr "type" "la") |
2058 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 2059 | |
9db1d521 HP |
2060 | ; |
2061 | ; movhi instruction pattern(s). | |
2062 | ; | |
2063 | ||
02ed3c5e UW |
2064 | (define_expand "movhi" |
2065 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2066 | (match_operand:HI 1 "general_operand" ""))] | |
2067 | "" | |
2068 | { | |
2f7e5a0d | 2069 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2070 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2071 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2072 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2073 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2074 | { |
2075 | rtx tmp = gen_reg_rtx (SImode); | |
2076 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2077 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2078 | operands[1] = gen_lowpart (HImode, tmp); |
2079 | } | |
2080 | }) | |
2081 | ||
2082 | (define_insn "*movhi" | |
085261c8 AK |
2083 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR") |
2084 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))] | |
9db1d521 HP |
2085 | "" |
2086 | "@ | |
d40c829f UW |
2087 | lr\t%0,%1 |
2088 | lhi\t%0,%h1 | |
2089 | lh\t%0,%1 | |
2090 | lhy\t%0,%1 | |
963fc8d0 | 2091 | lhrl\t%0,%1 |
d40c829f UW |
2092 | sth\t%1,%0 |
2093 | sthy\t%1,%0 | |
963fc8d0 | 2094 | sthrl\t%1,%0 |
085261c8 AK |
2095 | mvhhi\t%0,%1 |
2096 | vleih\t%v0,%h1,0 | |
2097 | vlr\t%v0,%v1 | |
2098 | vlvgh\t%v0,%1,0 | |
2099 | vlgvh\t%0,%v1,0 | |
2100 | vleh\t%v0,%1,0 | |
2101 | vsteh\t%v1,%0,0" | |
2102 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2103 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
2104 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec") | |
9381e3f1 WG |
2105 | (set_attr "z10prop" "z10_fr_E1, |
2106 | z10_fwd_A1, | |
2107 | z10_super_E1, | |
2108 | z10_super_E1, | |
2109 | z10_super_E1, | |
729e750f | 2110 | z10_rec, |
9381e3f1 WG |
2111 | z10_rec, |
2112 | z10_rec, | |
085261c8 | 2113 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2114 | |
84817c5d UW |
2115 | (define_peephole2 |
2116 | [(set (match_operand:HI 0 "register_operand" "") | |
2117 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2118 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2119 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2120 | && get_pool_mode (operands[1]) == HImode | |
2121 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2122 | [(set (match_dup 0) (match_dup 2))] | |
2123 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2124 | |
9db1d521 HP |
2125 | ; |
2126 | ; movqi instruction pattern(s). | |
2127 | ; | |
2128 | ||
02ed3c5e UW |
2129 | (define_expand "movqi" |
2130 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2131 | (match_operand:QI 1 "general_operand" ""))] | |
2132 | "" | |
2133 | { | |
c19ec8f9 | 2134 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2135 | is just as fast as a QImode load. */ |
b3a13419 | 2136 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2137 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2138 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2139 | { |
9602b6a1 AK |
2140 | rtx tmp = gen_reg_rtx (DImode); |
2141 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2142 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2143 | operands[1] = gen_lowpart (QImode, tmp); |
2144 | } | |
2145 | }) | |
4023fb28 | 2146 | |
02ed3c5e | 2147 | (define_insn "*movqi" |
085261c8 AK |
2148 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR") |
2149 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))] | |
9db1d521 HP |
2150 | "" |
2151 | "@ | |
d40c829f UW |
2152 | lr\t%0,%1 |
2153 | lhi\t%0,%b1 | |
2154 | ic\t%0,%1 | |
2155 | icy\t%0,%1 | |
2156 | stc\t%1,%0 | |
2157 | stcy\t%1,%0 | |
fc0ea003 | 2158 | mvi\t%S0,%b1 |
0a88561f | 2159 | mviy\t%S0,%b1 |
085261c8 AK |
2160 | # |
2161 | vleib\t%v0,%b1,0 | |
2162 | vlr\t%v0,%v1 | |
2163 | vlvgb\t%v0,%1,0 | |
2164 | vlgvb\t%0,%v1,0 | |
2165 | vleb\t%v0,%1,0 | |
2166 | vsteb\t%v1,%0,0" | |
2167 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2168 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
2169 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec") | |
9381e3f1 WG |
2170 | (set_attr "z10prop" "z10_fr_E1, |
2171 | z10_fwd_A1, | |
2172 | z10_super_E1, | |
2173 | z10_super_E1, | |
729e750f | 2174 | z10_rec, |
9381e3f1 WG |
2175 | z10_rec, |
2176 | z10_super, | |
0a88561f | 2177 | z10_super, |
085261c8 | 2178 | *,*,*,*,*,*,*")]) |
9db1d521 | 2179 | |
84817c5d UW |
2180 | (define_peephole2 |
2181 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2182 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2183 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2184 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2185 | && get_pool_mode (operands[1]) == QImode | |
2186 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2187 | [(set (match_dup 0) (match_dup 2))] | |
2188 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2189 | |
9db1d521 | 2190 | ; |
05b9aaaa | 2191 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2192 | ; |
2193 | ||
2194 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2195 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2196 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2197 | "" |
d3632d41 | 2198 | "@ |
d40c829f UW |
2199 | ic\t%0,%1 |
2200 | icy\t%0,%1" | |
9381e3f1 | 2201 | [(set_attr "op_type" "RX,RXY") |
729e750f | 2202 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2203 | |
2204 | ; | |
2205 | ; movstricthi instruction pattern(s). | |
2206 | ; | |
2207 | ||
2208 | (define_insn "*movstricthi" | |
d3632d41 | 2209 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2210 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2211 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2212 | "" |
d3632d41 | 2213 | "@ |
fc0ea003 UW |
2214 | icm\t%0,3,%S1 |
2215 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
2216 | [(set_attr "op_type" "RS,RSY") |
2217 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
2218 | |
2219 | ; | |
2220 | ; movstrictsi instruction pattern(s). | |
2221 | ; | |
2222 | ||
05b9aaaa | 2223 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2224 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2225 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2226 | "TARGET_ZARCH" |
9db1d521 | 2227 | "@ |
d40c829f UW |
2228 | lr\t%0,%1 |
2229 | l\t%0,%1 | |
c5aa1d12 UW |
2230 | ly\t%0,%1 |
2231 | ear\t%0,%1" | |
2232 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
2233 | (set_attr "type" "lr,load,load,*") |
2234 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 2235 | |
f61a2c7d | 2236 | ; |
609e7e80 | 2237 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2238 | ; |
2239 | ||
609e7e80 AK |
2240 | (define_expand "mov<mode>" |
2241 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2242 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2243 | "" |
2244 | "") | |
2245 | ||
609e7e80 | 2246 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2247 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
2248 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 2249 | "TARGET_ZARCH" |
f61a2c7d | 2250 | "@ |
65b1d8ea | 2251 | lzxr\t%0 |
f61a2c7d AK |
2252 | lxr\t%0,%1 |
2253 | # | |
2254 | # | |
2255 | lmg\t%0,%N0,%S1 | |
2256 | stmg\t%1,%N1,%S0 | |
2257 | # | |
f61a2c7d | 2258 | #" |
65b1d8ea AK |
2259 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2260 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2261 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2262 | |
609e7e80 | 2263 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2264 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2265 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2266 | "!TARGET_ZARCH" |
f61a2c7d | 2267 | "@ |
65b1d8ea | 2268 | lzxr\t%0 |
f61a2c7d AK |
2269 | lxr\t%0,%1 |
2270 | # | |
f61a2c7d | 2271 | #" |
65b1d8ea AK |
2272 | [(set_attr "op_type" "RRE,RRE,*,*") |
2273 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2274 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2275 | |
2276 | ; TFmode in GPRs splitters | |
2277 | ||
2278 | (define_split | |
609e7e80 AK |
2279 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2280 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2281 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2282 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2283 | [(set (match_dup 2) (match_dup 4)) |
2284 | (set (match_dup 3) (match_dup 5))] | |
2285 | { | |
609e7e80 AK |
2286 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2287 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2288 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2289 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2290 | }) |
2291 | ||
2292 | (define_split | |
609e7e80 AK |
2293 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2294 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2295 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2296 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2297 | [(set (match_dup 2) (match_dup 4)) |
2298 | (set (match_dup 3) (match_dup 5))] | |
2299 | { | |
609e7e80 AK |
2300 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2301 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2302 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2303 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2304 | }) |
2305 | ||
2306 | (define_split | |
609e7e80 AK |
2307 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2308 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2309 | "TARGET_ZARCH && reload_completed |
085261c8 | 2310 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2311 | && !s_operand (operands[1], VOIDmode)" |
2312 | [(set (match_dup 0) (match_dup 1))] | |
2313 | { | |
609e7e80 | 2314 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2315 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2316 | s390_load_address (addr, XEXP (operands[1], 0)); |
2317 | operands[1] = replace_equiv_address (operands[1], addr); | |
2318 | }) | |
2319 | ||
7b6baae1 | 2320 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2321 | |
2322 | (define_split | |
609e7e80 AK |
2323 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2324 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2325 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2326 | && FP_REG_P (operands[0])" |
2327 | [(set (match_dup 2) (match_dup 4)) | |
2328 | (set (match_dup 3) (match_dup 5))] | |
2329 | { | |
609e7e80 AK |
2330 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2331 | <MODE>mode, 0); | |
2332 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2333 | <MODE>mode, 8); | |
2334 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2335 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2336 | }) |
2337 | ||
2338 | (define_split | |
609e7e80 AK |
2339 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2340 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2341 | "reload_completed && offsettable_memref_p (operands[0]) |
2342 | && FP_REG_P (operands[1])" | |
2343 | [(set (match_dup 2) (match_dup 4)) | |
2344 | (set (match_dup 3) (match_dup 5))] | |
2345 | { | |
609e7e80 AK |
2346 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2347 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2348 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2349 | <MODE>mode, 0); | |
2350 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2351 | <MODE>mode, 8); | |
f61a2c7d AK |
2352 | }) |
2353 | ||
9db1d521 | 2354 | ; |
609e7e80 | 2355 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2356 | ; |
2357 | ||
609e7e80 AK |
2358 | (define_expand "mov<mode>" |
2359 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2360 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2361 | "" |
13c025c1 | 2362 | "") |
9db1d521 | 2363 | |
609e7e80 AK |
2364 | (define_insn "*mov<mode>_64dfp" |
2365 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
085261c8 | 2366 | "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR") |
609e7e80 | 2367 | (match_operand:DD_DF 1 "general_operand" |
085261c8 | 2368 | " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))] |
9602b6a1 | 2369 | "TARGET_DFP" |
85dae55a | 2370 | "@ |
65b1d8ea | 2371 | lzdr\t%0 |
85dae55a AK |
2372 | ldr\t%0,%1 |
2373 | ldgr\t%0,%1 | |
2374 | lgdr\t%0,%1 | |
2375 | ld\t%0,%1 | |
2376 | ldy\t%0,%1 | |
2377 | std\t%1,%0 | |
2378 | stdy\t%1,%0 | |
45e5214c | 2379 | lghi\t%0,0 |
85dae55a | 2380 | lgr\t%0,%1 |
085261c8 | 2381 | lgrl\t%0,%1 |
85dae55a | 2382 | lg\t%0,%1 |
085261c8 AK |
2383 | stgrl\t%1,%0 |
2384 | stg\t%1,%0 | |
2385 | vlr\t%v0,%v1 | |
2386 | vlvgg\t%v0,%1,0 | |
2387 | vlgvg\t%0,%v1,0 | |
2388 | vleg\t%0,%1,0 | |
2389 | vsteg\t%1,%0,0" | |
2390 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX") | |
65b1d8ea | 2391 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
085261c8 AK |
2392 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store") |
2393 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*") | |
2394 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")]) | |
85dae55a | 2395 | |
609e7e80 | 2396 | (define_insn "*mov<mode>_64" |
085261c8 AK |
2397 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR") |
2398 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))] | |
9602b6a1 | 2399 | "TARGET_ZARCH" |
9db1d521 | 2400 | "@ |
65b1d8ea | 2401 | lzdr\t%0 |
d40c829f UW |
2402 | ldr\t%0,%1 |
2403 | ld\t%0,%1 | |
2404 | ldy\t%0,%1 | |
2405 | std\t%1,%0 | |
2406 | stdy\t%1,%0 | |
45e5214c | 2407 | lghi\t%0,0 |
d40c829f | 2408 | lgr\t%0,%1 |
085261c8 | 2409 | lgrl\t%0,%1 |
d40c829f | 2410 | lg\t%0,%1 |
085261c8 AK |
2411 | stgrl\t%1,%0 |
2412 | stg\t%1,%0 | |
2413 | vlr\t%v0,%v1 | |
2414 | vleg\t%v0,%1,0 | |
2415 | vsteg\t%v1,%0,0" | |
2416 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX") | |
65b1d8ea | 2417 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
085261c8 AK |
2418 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store") |
2419 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*") | |
2420 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")]) | |
609e7e80 AK |
2421 | |
2422 | (define_insn "*mov<mode>_31" | |
2423 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2424 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2425 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2426 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2427 | "!TARGET_ZARCH" |
9db1d521 | 2428 | "@ |
65b1d8ea | 2429 | lzdr\t%0 |
d40c829f UW |
2430 | ldr\t%0,%1 |
2431 | ld\t%0,%1 | |
2432 | ldy\t%0,%1 | |
2433 | std\t%1,%0 | |
2434 | stdy\t%1,%0 | |
fc0ea003 | 2435 | lm\t%0,%N0,%S1 |
c4d50129 | 2436 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2437 | stm\t%1,%N1,%S0 |
c4d50129 | 2438 | stmy\t%1,%N1,%S0 |
4023fb28 | 2439 | # |
19b63d8e | 2440 | #" |
65b1d8ea AK |
2441 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2442 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2443 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2444 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2445 | |
2446 | (define_split | |
609e7e80 AK |
2447 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2448 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2449 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2450 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2451 | [(set (match_dup 2) (match_dup 4)) |
2452 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2453 | { |
609e7e80 AK |
2454 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2455 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2456 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2457 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2458 | }) |
2459 | ||
2460 | (define_split | |
609e7e80 AK |
2461 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2462 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2463 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2464 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2465 | [(set (match_dup 2) (match_dup 4)) |
2466 | (set (match_dup 3) (match_dup 5))] | |
2467 | { | |
609e7e80 AK |
2468 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2469 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2470 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2471 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2472 | }) |
9db1d521 | 2473 | |
4023fb28 | 2474 | (define_split |
609e7e80 AK |
2475 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2476 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2477 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2478 | && !FP_REG_P (operands[0]) |
4023fb28 | 2479 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2480 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2481 | { |
609e7e80 | 2482 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2483 | s390_load_address (addr, XEXP (operands[1], 0)); |
2484 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2485 | }) |
2486 | ||
9db1d521 | 2487 | ; |
609e7e80 | 2488 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2489 | ; |
2490 | ||
609e7e80 AK |
2491 | (define_insn "mov<mode>" |
2492 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
085261c8 | 2493 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR") |
609e7e80 | 2494 | (match_operand:SD_SF 1 "general_operand" |
085261c8 | 2495 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))] |
4023fb28 | 2496 | "" |
9db1d521 | 2497 | "@ |
65b1d8ea | 2498 | lzer\t%0 |
085261c8 | 2499 | lder\t%0,%1 |
d40c829f | 2500 | ler\t%0,%1 |
085261c8 | 2501 | lde\t%0,%1 |
d40c829f UW |
2502 | le\t%0,%1 |
2503 | ley\t%0,%1 | |
2504 | ste\t%1,%0 | |
2505 | stey\t%1,%0 | |
45e5214c | 2506 | lhi\t%0,0 |
d40c829f | 2507 | lr\t%0,%1 |
085261c8 | 2508 | lrl\t%0,%1 |
d40c829f UW |
2509 | l\t%0,%1 |
2510 | ly\t%0,%1 | |
085261c8 | 2511 | strl\t%1,%0 |
d40c829f | 2512 | st\t%1,%0 |
085261c8 AK |
2513 | sty\t%1,%0 |
2514 | vlr\t%v0,%v1 | |
2515 | vleif\t%v0,0 | |
2516 | vlvgf\t%v0,%1,0 | |
2517 | vlgvf\t%0,%v1,0 | |
2518 | vleg\t%0,%1,0 | |
2519 | vsteg\t%1,%0,0" | |
2520 | [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") | |
2521 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, | |
2522 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2523 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
2524 | (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")]) | |
4023fb28 | 2525 | |
9dc62c00 AK |
2526 | ; |
2527 | ; movcc instruction pattern | |
2528 | ; | |
2529 | ||
2530 | (define_insn "movcc" | |
2531 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2532 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2533 | "" |
2534 | "@ | |
2535 | lr\t%0,%1 | |
2536 | tmh\t%1,12288 | |
2537 | ipm\t%0 | |
a71f0749 DV |
2538 | l\t%0,%1 |
2539 | ly\t%0,%1 | |
2540 | st\t%1,%0 | |
2541 | sty\t%1,%0" | |
8dd3b235 | 2542 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 DV |
2543 | (set_attr "type" "lr,*,*,load,load,store,store") |
2544 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
65b1d8ea | 2545 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2546 | |
19b63d8e UW |
2547 | ; |
2548 | ; Block move (MVC) patterns. | |
2549 | ; | |
2550 | ||
2551 | (define_insn "*mvc" | |
2552 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2553 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2554 | (use (match_operand 2 "const_int_operand" "n"))] | |
2555 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2556 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2557 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2558 | |
0a88561f AK |
2559 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2560 | ; order to have it implemented with mvc. | |
2561 | ||
2562 | (define_split | |
2563 | [(set (match_operand:QI 0 "memory_operand" "") | |
2564 | (match_operand:QI 1 "memory_operand" ""))] | |
2565 | "reload_completed" | |
2566 | [(parallel | |
2567 | [(set (match_dup 0) (match_dup 1)) | |
2568 | (use (const_int 1))])] | |
2569 | { | |
2570 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2571 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2572 | }) | |
2573 | ||
2574 | ||
19b63d8e UW |
2575 | (define_peephole2 |
2576 | [(parallel | |
2577 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2578 | (match_operand:BLK 1 "memory_operand" "")) | |
2579 | (use (match_operand 2 "const_int_operand" ""))]) | |
2580 | (parallel | |
2581 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2582 | (match_operand:BLK 4 "memory_operand" "")) | |
2583 | (use (match_operand 5 "const_int_operand" ""))])] | |
2584 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2585 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2586 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2587 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2588 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2589 | [(parallel | |
2590 | [(set (match_dup 6) (match_dup 7)) | |
2591 | (use (match_dup 8))])] | |
2592 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2593 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2594 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2595 | ||
2596 | ||
9db1d521 HP |
2597 | ; |
2598 | ; load_multiple pattern(s). | |
2599 | ; | |
22ea6b4f UW |
2600 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2601 | ; we currently support load_multiple/store_multiple only after reload. | |
2602 | ; | |
9db1d521 HP |
2603 | |
2604 | (define_expand "load_multiple" | |
2605 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2606 | (match_operand 1 "" "")) | |
2607 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2608 | "reload_completed" |
9db1d521 | 2609 | { |
ef4bddc2 | 2610 | machine_mode mode; |
9db1d521 HP |
2611 | int regno; |
2612 | int count; | |
2613 | rtx from; | |
4023fb28 | 2614 | int i, off; |
9db1d521 HP |
2615 | |
2616 | /* Support only loading a constant number of fixed-point registers from | |
2617 | memory and only bother with this if more than two */ | |
2618 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2619 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2620 | || INTVAL (operands[2]) > 16 |
2621 | || GET_CODE (operands[1]) != MEM | |
2622 | || GET_CODE (operands[0]) != REG | |
2623 | || REGNO (operands[0]) >= 16) | |
2624 | FAIL; | |
2625 | ||
2626 | count = INTVAL (operands[2]); | |
2627 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2628 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2629 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2630 | FAIL; |
9db1d521 HP |
2631 | |
2632 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2633 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2634 | { |
2635 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2636 | { | |
2637 | from = XEXP (operands[1], 0); | |
2638 | off = 0; | |
2639 | } | |
2640 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2641 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2642 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2643 | { | |
2644 | from = XEXP (XEXP (operands[1], 0), 0); | |
2645 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2646 | } | |
2647 | else | |
2648 | FAIL; | |
4023fb28 UW |
2649 | } |
2650 | else | |
2651 | { | |
2652 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2653 | off = 0; | |
2654 | } | |
9db1d521 HP |
2655 | |
2656 | for (i = 0; i < count; i++) | |
2657 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2658 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2659 | change_address (operands[1], mode, |
0a81f074 RS |
2660 | plus_constant (Pmode, from, |
2661 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2662 | }) |
9db1d521 HP |
2663 | |
2664 | (define_insn "*load_multiple_di" | |
2665 | [(match_parallel 0 "load_multiple_operation" | |
2666 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2667 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2668 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2669 | { |
2670 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2671 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2672 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2673 | } |
d3632d41 | 2674 | [(set_attr "op_type" "RSY") |
4023fb28 | 2675 | (set_attr "type" "lm")]) |
9db1d521 HP |
2676 | |
2677 | (define_insn "*load_multiple_si" | |
2678 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2679 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2680 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2681 | "reload_completed" |
9db1d521 HP |
2682 | { |
2683 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2684 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2685 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2686 | } |
d3632d41 | 2687 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2688 | (set_attr "type" "lm")]) |
9db1d521 HP |
2689 | |
2690 | ; | |
c7453384 | 2691 | ; store multiple pattern(s). |
9db1d521 HP |
2692 | ; |
2693 | ||
2694 | (define_expand "store_multiple" | |
2695 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2696 | (match_operand 1 "" "")) | |
2697 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2698 | "reload_completed" |
9db1d521 | 2699 | { |
ef4bddc2 | 2700 | machine_mode mode; |
9db1d521 HP |
2701 | int regno; |
2702 | int count; | |
2703 | rtx to; | |
4023fb28 | 2704 | int i, off; |
9db1d521 HP |
2705 | |
2706 | /* Support only storing a constant number of fixed-point registers to | |
2707 | memory and only bother with this if more than two. */ | |
2708 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2709 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2710 | || INTVAL (operands[2]) > 16 |
2711 | || GET_CODE (operands[0]) != MEM | |
2712 | || GET_CODE (operands[1]) != REG | |
2713 | || REGNO (operands[1]) >= 16) | |
2714 | FAIL; | |
2715 | ||
2716 | count = INTVAL (operands[2]); | |
2717 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2718 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2719 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2720 | FAIL; |
9db1d521 HP |
2721 | |
2722 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2723 | |
b3a13419 | 2724 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2725 | { |
2726 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2727 | { | |
2728 | to = XEXP (operands[0], 0); | |
2729 | off = 0; | |
2730 | } | |
2731 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2732 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2733 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2734 | { | |
2735 | to = XEXP (XEXP (operands[0], 0), 0); | |
2736 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2737 | } | |
2738 | else | |
2739 | FAIL; | |
4023fb28 | 2740 | } |
c7453384 | 2741 | else |
4023fb28 UW |
2742 | { |
2743 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2744 | off = 0; | |
2745 | } | |
9db1d521 HP |
2746 | |
2747 | for (i = 0; i < count; i++) | |
2748 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2749 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2750 | plus_constant (Pmode, to, |
2751 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2752 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2753 | }) |
9db1d521 HP |
2754 | |
2755 | (define_insn "*store_multiple_di" | |
2756 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2757 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2758 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2759 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2760 | { |
2761 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2762 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2763 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2764 | } |
d3632d41 | 2765 | [(set_attr "op_type" "RSY") |
4023fb28 | 2766 | (set_attr "type" "stm")]) |
9db1d521 HP |
2767 | |
2768 | ||
2769 | (define_insn "*store_multiple_si" | |
2770 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2771 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2772 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2773 | "reload_completed" |
9db1d521 HP |
2774 | { |
2775 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2776 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2777 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2778 | } |
d3632d41 | 2779 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2780 | (set_attr "type" "stm")]) |
9db1d521 HP |
2781 | |
2782 | ;; | |
2783 | ;; String instructions. | |
2784 | ;; | |
2785 | ||
963fc8d0 | 2786 | (define_insn "*execute_rl" |
2771c2f9 | 2787 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2788 | [(unspec [(match_operand 1 "register_operand" "a") |
2789 | (match_operand 2 "" "") | |
2790 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2791 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2792 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2793 | "exrl\t%1,%3" | |
2794 | [(set_attr "op_type" "RIL") | |
2795 | (set_attr "type" "cs")]) | |
2796 | ||
9bb86f41 | 2797 | (define_insn "*execute" |
2771c2f9 | 2798 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2799 | [(unspec [(match_operand 1 "register_operand" "a") |
2800 | (match_operand:BLK 2 "memory_operand" "R") | |
2801 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2802 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2803 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2804 | "ex\t%1,%2" | |
29a74354 UW |
2805 | [(set_attr "op_type" "RX") |
2806 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2807 | |
2808 | ||
91d39d71 UW |
2809 | ; |
2810 | ; strlenM instruction pattern(s). | |
2811 | ; | |
2812 | ||
9db2f16d | 2813 | (define_expand "strlen<mode>" |
085261c8 AK |
2814 | [(match_operand:P 0 "register_operand" "") ; result |
2815 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2816 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2817 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2818 | "" | |
2819 | { | |
2820 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2821 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2822 | operands[2], operands[3])); | |
2823 | else | |
2824 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2825 | ||
2826 | DONE; | |
2827 | }) | |
2828 | ||
2829 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 2830 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2831 | (parallel |
91d39d71 | 2832 | [(set (match_dup 4) |
9db2f16d | 2833 | (unspec:P [(const_int 0) |
91d39d71 | 2834 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2835 | (reg:SI 0) |
91d39d71 | 2836 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2837 | (clobber (scratch:P)) |
ae156f85 | 2838 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2839 | (parallel |
9db2f16d AS |
2840 | [(set (match_operand:P 0 "register_operand" "") |
2841 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2842 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2843 | "" |
91d39d71 | 2844 | { |
9db2f16d AS |
2845 | operands[4] = gen_reg_rtx (Pmode); |
2846 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2847 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2848 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2849 | }) | |
2850 | ||
9db2f16d AS |
2851 | (define_insn "*strlen<mode>" |
2852 | [(set (match_operand:P 0 "register_operand" "=a") | |
2853 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2854 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2855 | (reg:SI 0) |
91d39d71 | 2856 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2857 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2858 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2859 | "" |
91d39d71 | 2860 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2861 | [(set_attr "length" "8") |
2862 | (set_attr "type" "vs")]) | |
91d39d71 | 2863 | |
ccbdc0d4 AS |
2864 | ; |
2865 | ; cmpstrM instruction pattern(s). | |
2866 | ; | |
2867 | ||
2868 | (define_expand "cmpstrsi" | |
2869 | [(set (reg:SI 0) (const_int 0)) | |
2870 | (parallel | |
2871 | [(clobber (match_operand 3 "" "")) | |
2872 | (clobber (match_dup 4)) | |
2873 | (set (reg:CCU CC_REGNUM) | |
2874 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2875 | (match_operand:BLK 2 "memory_operand" ""))) | |
2876 | (use (reg:SI 0))]) | |
2877 | (parallel | |
2878 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2879 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
2880 | (clobber (reg:CC CC_REGNUM))])] |
2881 | "" | |
2882 | { | |
2883 | /* As the result of CMPINT is inverted compared to what we need, | |
2884 | we have to swap the operands. */ | |
2885 | rtx op1 = operands[2]; | |
2886 | rtx op2 = operands[1]; | |
2887 | rtx addr1 = gen_reg_rtx (Pmode); | |
2888 | rtx addr2 = gen_reg_rtx (Pmode); | |
2889 | ||
2890 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2891 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2892 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2893 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2894 | operands[3] = addr1; | |
2895 | operands[4] = addr2; | |
2896 | }) | |
2897 | ||
2898 | (define_insn "*cmpstr<mode>" | |
2899 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2900 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2901 | (set (reg:CCU CC_REGNUM) | |
2902 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2903 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2904 | (use (reg:SI 0))] | |
2905 | "" | |
2906 | "clst\t%0,%1\;jo\t.-4" | |
2907 | [(set_attr "length" "8") | |
2908 | (set_attr "type" "vs")]) | |
9381e3f1 | 2909 | |
742090fc AS |
2910 | ; |
2911 | ; movstr instruction pattern. | |
2912 | ; | |
2913 | ||
2914 | (define_expand "movstr" | |
4a7dec25 DV |
2915 | [(match_operand 0 "register_operand" "") |
2916 | (match_operand 1 "memory_operand" "") | |
2917 | (match_operand 2 "memory_operand" "")] | |
2918 | "" | |
2919 | { | |
2920 | if (TARGET_64BIT) | |
2921 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
2922 | else | |
2923 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
2924 | DONE; | |
2925 | }) | |
2926 | ||
2927 | (define_expand "movstr<P:mode>" | |
742090fc | 2928 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 2929 | (parallel |
742090fc AS |
2930 | [(clobber (match_dup 3)) |
2931 | (set (match_operand:BLK 1 "memory_operand" "") | |
2932 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
2933 | (set (match_operand:P 0 "register_operand" "") |
2934 | (unspec:P [(match_dup 1) | |
742090fc AS |
2935 | (match_dup 2) |
2936 | (reg:SI 0)] UNSPEC_MVST)) | |
2937 | (clobber (reg:CC CC_REGNUM))])] | |
2938 | "" | |
2939 | { | |
859a4c0e AK |
2940 | rtx addr1, addr2; |
2941 | ||
2942 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
2943 | { | |
2944 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
2945 | DONE; | |
2946 | } | |
2947 | ||
2948 | addr1 = gen_reg_rtx (Pmode); | |
2949 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
2950 | |
2951 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2952 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2953 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2954 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2955 | operands[3] = addr2; | |
2956 | }) | |
2957 | ||
2958 | (define_insn "*movstr" | |
2959 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2960 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2961 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2962 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 2963 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
2964 | (mem:BLK (match_dup 3)) |
2965 | (reg:SI 0)] UNSPEC_MVST)) | |
2966 | (clobber (reg:CC CC_REGNUM))] | |
2967 | "" | |
2968 | "mvst\t%1,%2\;jo\t.-4" | |
2969 | [(set_attr "length" "8") | |
2970 | (set_attr "type" "vs")]) | |
9381e3f1 | 2971 | |
742090fc | 2972 | |
9db1d521 | 2973 | ; |
70128ad9 | 2974 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2975 | ; |
2976 | ||
9db2f16d | 2977 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2978 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2979 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2980 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2981 | (match_operand 3 "" "")] |
2982 | "" | |
367d32f3 AK |
2983 | { |
2984 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
2985 | DONE; | |
2986 | else | |
2987 | FAIL; | |
2988 | }) | |
9db1d521 | 2989 | |
ecbe845e UW |
2990 | ; Move a block that is up to 256 bytes in length. |
2991 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2992 | |
70128ad9 | 2993 | (define_expand "movmem_short" |
b9404c99 UW |
2994 | [(parallel |
2995 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2996 | (match_operand:BLK 1 "memory_operand" "")) | |
2997 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2998 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2999 | (clobber (match_dup 3))])] |
3000 | "" | |
3001 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3002 | |
70128ad9 | 3003 | (define_insn "*movmem_short" |
963fc8d0 AK |
3004 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3005 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3006 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3007 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3008 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3009 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3010 | "#" |
963fc8d0 | 3011 | [(set_attr "type" "cs") |
b5e0425c | 3012 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3013 | |
9bb86f41 UW |
3014 | (define_split |
3015 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3016 | (match_operand:BLK 1 "memory_operand" "")) | |
3017 | (use (match_operand 2 "const_int_operand" "")) | |
3018 | (use (match_operand 3 "immediate_operand" "")) | |
3019 | (clobber (scratch))] | |
3020 | "reload_completed" | |
3021 | [(parallel | |
3022 | [(set (match_dup 0) (match_dup 1)) | |
3023 | (use (match_dup 2))])] | |
3024 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3025 | |
9bb86f41 UW |
3026 | (define_split |
3027 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3028 | (match_operand:BLK 1 "memory_operand" "")) | |
3029 | (use (match_operand 2 "register_operand" "")) | |
3030 | (use (match_operand 3 "memory_operand" "")) | |
3031 | (clobber (scratch))] | |
3032 | "reload_completed" | |
3033 | [(parallel | |
3034 | [(unspec [(match_dup 2) (match_dup 3) | |
3035 | (const_int 0)] UNSPEC_EXECUTE) | |
3036 | (set (match_dup 0) (match_dup 1)) | |
3037 | (use (const_int 1))])] | |
3038 | "") | |
3039 | ||
963fc8d0 AK |
3040 | (define_split |
3041 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3042 | (match_operand:BLK 1 "memory_operand" "")) | |
3043 | (use (match_operand 2 "register_operand" "")) | |
3044 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3045 | (clobber (scratch))] | |
3046 | "TARGET_Z10 && reload_completed" | |
3047 | [(parallel | |
3048 | [(unspec [(match_dup 2) (const_int 0) | |
3049 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3050 | (set (match_dup 0) (match_dup 1)) | |
3051 | (use (const_int 1))])] | |
3052 | "operands[3] = gen_label_rtx ();") | |
3053 | ||
9bb86f41 UW |
3054 | (define_split |
3055 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3056 | (match_operand:BLK 1 "memory_operand" "")) | |
3057 | (use (match_operand 2 "register_operand" "")) | |
3058 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3059 | (clobber (match_operand 3 "register_operand" ""))] | |
3060 | "reload_completed && TARGET_CPU_ZARCH" | |
3061 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3062 | (parallel | |
9381e3f1 | 3063 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3064 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3065 | (set (match_dup 0) (match_dup 1)) | |
3066 | (use (const_int 1))])] | |
3067 | "operands[4] = gen_label_rtx ();") | |
3068 | ||
a41c6c53 | 3069 | ; Move a block of arbitrary length. |
9db1d521 | 3070 | |
70128ad9 | 3071 | (define_expand "movmem_long" |
b9404c99 UW |
3072 | [(parallel |
3073 | [(clobber (match_dup 2)) | |
3074 | (clobber (match_dup 3)) | |
3075 | (set (match_operand:BLK 0 "memory_operand" "") | |
3076 | (match_operand:BLK 1 "memory_operand" "")) | |
3077 | (use (match_operand 2 "general_operand" "")) | |
3078 | (use (match_dup 3)) | |
ae156f85 | 3079 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3080 | "" |
3081 | { | |
ef4bddc2 RS |
3082 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3083 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3084 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3085 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3086 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3087 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3088 | rtx len0 = gen_lowpart (Pmode, reg0); |
3089 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3090 | ||
c41c1387 | 3091 | emit_clobber (reg0); |
b9404c99 UW |
3092 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3093 | emit_move_insn (len0, operands[2]); | |
3094 | ||
c41c1387 | 3095 | emit_clobber (reg1); |
b9404c99 UW |
3096 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3097 | emit_move_insn (len1, operands[2]); | |
3098 | ||
3099 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3100 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3101 | operands[2] = reg0; | |
3102 | operands[3] = reg1; | |
3103 | }) | |
3104 | ||
a1aed706 AS |
3105 | (define_insn "*movmem_long" |
3106 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3107 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3108 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3109 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3110 | (use (match_dup 2)) |
3111 | (use (match_dup 3)) | |
ae156f85 | 3112 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3113 | "TARGET_64BIT || !TARGET_ZARCH" |
3114 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3115 | [(set_attr "length" "8") | |
3116 | (set_attr "type" "vs")]) | |
3117 | ||
3118 | (define_insn "*movmem_long_31z" | |
3119 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3120 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3121 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3122 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3123 | (use (match_dup 2)) | |
3124 | (use (match_dup 3)) | |
3125 | (clobber (reg:CC CC_REGNUM))] | |
3126 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3127 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3128 | [(set_attr "length" "8") |
3129 | (set_attr "type" "vs")]) | |
9db1d521 | 3130 | |
638e37c2 WG |
3131 | |
3132 | ; | |
3133 | ; Test data class. | |
3134 | ; | |
3135 | ||
0f67fa83 WG |
3136 | (define_expand "signbit<mode>2" |
3137 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3138 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3139 | (match_dup 2)] | |
0f67fa83 WG |
3140 | UNSPEC_TDC_INSN)) |
3141 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3142 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3143 | "TARGET_HARD_FLOAT" |
3144 | { | |
3145 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3146 | }) | |
3147 | ||
638e37c2 WG |
3148 | (define_expand "isinf<mode>2" |
3149 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3150 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3151 | (match_dup 2)] | |
638e37c2 WG |
3152 | UNSPEC_TDC_INSN)) |
3153 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3154 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3155 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3156 | { |
3157 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3158 | }) | |
3159 | ||
085261c8 AK |
3160 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3161 | ; instruction will be issued by reload. The constraint of operand 1 | |
3162 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3163 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3164 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3165 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3166 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3167 | UNSPEC_CC_TO_INT))] | |
3168 | "operands != NULL" | |
3169 | "#" | |
3170 | "reload_completed" | |
3171 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3172 | ||
638e37c2 WG |
3173 | ; This insn is used to generate all variants of the Test Data Class |
3174 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3175 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3176 | ; specifying the required test(s). |
638e37c2 | 3177 | ; |
be5de7a1 | 3178 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3179 | (define_insn "*TDC_insn_<mode>" |
3180 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3181 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3182 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3183 | "TARGET_HARD_FLOAT" |
0387c142 | 3184 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3185 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3186 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3187 | |
638e37c2 WG |
3188 | |
3189 | ||
9db1d521 | 3190 | ; |
57e84f18 | 3191 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3192 | ; |
3193 | ||
57e84f18 | 3194 | (define_expand "setmem<mode>" |
a41c6c53 | 3195 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3196 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3197 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3198 | (match_operand 3 "" "")] |
a41c6c53 | 3199 | "" |
6d057022 | 3200 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3201 | |
a41c6c53 | 3202 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3203 | ; The block length is taken as (operands[1] % 256) + 1. |
3204 | ||
70128ad9 | 3205 | (define_expand "clrmem_short" |
b9404c99 UW |
3206 | [(parallel |
3207 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3208 | (const_int 0)) | |
3209 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3210 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3211 | (clobber (match_dup 2)) |
ae156f85 | 3212 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3213 | "" |
3214 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3215 | |
70128ad9 | 3216 | (define_insn "*clrmem_short" |
963fc8d0 | 3217 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3218 | (const_int 0)) |
963fc8d0 AK |
3219 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3220 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3221 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3222 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3223 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3224 | "#" |
963fc8d0 | 3225 | [(set_attr "type" "cs") |
b5e0425c | 3226 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3227 | |
3228 | (define_split | |
3229 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3230 | (const_int 0)) | |
3231 | (use (match_operand 1 "const_int_operand" "")) | |
3232 | (use (match_operand 2 "immediate_operand" "")) | |
3233 | (clobber (scratch)) | |
ae156f85 | 3234 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3235 | "reload_completed" |
3236 | [(parallel | |
3237 | [(set (match_dup 0) (const_int 0)) | |
3238 | (use (match_dup 1)) | |
ae156f85 | 3239 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3240 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3241 | |
9bb86f41 UW |
3242 | (define_split |
3243 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3244 | (const_int 0)) | |
3245 | (use (match_operand 1 "register_operand" "")) | |
3246 | (use (match_operand 2 "memory_operand" "")) | |
3247 | (clobber (scratch)) | |
ae156f85 | 3248 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3249 | "reload_completed" |
3250 | [(parallel | |
3251 | [(unspec [(match_dup 1) (match_dup 2) | |
3252 | (const_int 0)] UNSPEC_EXECUTE) | |
3253 | (set (match_dup 0) (const_int 0)) | |
3254 | (use (const_int 1)) | |
ae156f85 | 3255 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3256 | "") |
9db1d521 | 3257 | |
963fc8d0 AK |
3258 | (define_split |
3259 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3260 | (const_int 0)) | |
3261 | (use (match_operand 1 "register_operand" "")) | |
3262 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3263 | (clobber (scratch)) | |
3264 | (clobber (reg:CC CC_REGNUM))] | |
3265 | "TARGET_Z10 && reload_completed" | |
3266 | [(parallel | |
3267 | [(unspec [(match_dup 1) (const_int 0) | |
3268 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3269 | (set (match_dup 0) (const_int 0)) | |
3270 | (use (const_int 1)) | |
3271 | (clobber (reg:CC CC_REGNUM))])] | |
3272 | "operands[3] = gen_label_rtx ();") | |
3273 | ||
9bb86f41 UW |
3274 | (define_split |
3275 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3276 | (const_int 0)) | |
3277 | (use (match_operand 1 "register_operand" "")) | |
3278 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3279 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3280 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3281 | "reload_completed && TARGET_CPU_ZARCH" |
3282 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3283 | (parallel | |
9381e3f1 | 3284 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3285 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3286 | (set (match_dup 0) (const_int 0)) | |
3287 | (use (const_int 1)) | |
ae156f85 | 3288 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3289 | "operands[3] = gen_label_rtx ();") |
3290 | ||
9381e3f1 | 3291 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3292 | |
da0dcab1 | 3293 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3294 | [(parallel |
3295 | [(clobber (match_dup 1)) | |
3296 | (set (match_operand:BLK 0 "memory_operand" "") | |
da0dcab1 DV |
3297 | (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "") |
3298 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) | |
6d057022 | 3299 | (use (match_dup 3)) |
ae156f85 | 3300 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3301 | "" |
a41c6c53 | 3302 | { |
ef4bddc2 RS |
3303 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3304 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3305 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3306 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3307 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3308 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3309 | |
c41c1387 | 3310 | emit_clobber (reg0); |
b9404c99 UW |
3311 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3312 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3313 | |
b9404c99 | 3314 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3315 | |
b9404c99 UW |
3316 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3317 | operands[1] = reg0; | |
6d057022 | 3318 | operands[3] = reg1; |
da0dcab1 | 3319 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3320 | }) |
a41c6c53 | 3321 | |
da0dcab1 DV |
3322 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3323 | ||
6d057022 | 3324 | (define_insn "*setmem_long" |
a1aed706 | 3325 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3326 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
da0dcab1 DV |
3327 | (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y") |
3328 | (subreg:P (match_dup 3) <modesize>)] | |
3329 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3330 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3331 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3332 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3333 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3334 | [(set_attr "length" "8") |
3335 | (set_attr "type" "vs")]) | |
9db1d521 | 3336 | |
4989e88a AK |
3337 | (define_insn "*setmem_long_and" |
3338 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3339 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
da0dcab1 DV |
3340 | (unspec:BLK [(and:P |
3341 | (match_operand:P 2 "shift_count_or_setmem_operand" "Y") | |
3342 | (match_operand:P 4 "const_int_operand" "n")) | |
3343 | (subreg:P (match_dup 3) <modesize>)] | |
3344 | UNSPEC_REPLICATE_BYTE)) | |
4989e88a AK |
3345 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
3346 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 AK |
3347 | "(TARGET_64BIT || !TARGET_ZARCH) && |
3348 | (INTVAL (operands[4]) & 255) == 255" | |
3349 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3350 | [(set_attr "length" "8") | |
3351 | (set_attr "type" "vs")]) | |
3352 | ||
da0dcab1 DV |
3353 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3354 | ; of the SImode subregs. | |
3355 | ||
9602b6a1 AK |
3356 | (define_insn "*setmem_long_31z" |
3357 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3358 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
da0dcab1 DV |
3359 | (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y") |
3360 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) | |
9602b6a1 AK |
3361 | (use (match_operand:TI 1 "register_operand" "d")) |
3362 | (clobber (reg:CC CC_REGNUM))] | |
3363 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3364 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3365 | [(set_attr "length" "8") | |
3366 | (set_attr "type" "vs")]) | |
9602b6a1 | 3367 | |
da0dcab1 DV |
3368 | (define_insn "*setmem_long_and_31z" |
3369 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3370 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
3371 | (unspec:BLK [(and:SI | |
3372 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
3373 | (match_operand:SI 4 "const_int_operand" "n")) | |
3374 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) | |
3375 | (use (match_operand:TI 1 "register_operand" "d")) | |
3376 | (clobber (reg:CC CC_REGNUM))] | |
3377 | "(!TARGET_64BIT && TARGET_ZARCH) && | |
3378 | (INTVAL (operands[4]) & 255) == 255" | |
3379 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3380 | [(set_attr "length" "8") | |
3381 | (set_attr "type" "vs")]) | |
3382 | ||
9db1d521 | 3383 | ; |
358b8f01 | 3384 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3385 | ; |
3386 | ||
358b8f01 | 3387 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3388 | [(set (match_operand:SI 0 "register_operand" "") |
3389 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3390 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3391 | (use (match_operand:SI 3 "general_operand" "")) | |
3392 | (use (match_operand:SI 4 "" ""))] | |
3393 | "" | |
367d32f3 AK |
3394 | { |
3395 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3396 | operands[2], operands[3])) | |
3397 | DONE; | |
3398 | else | |
3399 | FAIL; | |
3400 | }) | |
9db1d521 | 3401 | |
a41c6c53 UW |
3402 | ; Compare a block that is up to 256 bytes in length. |
3403 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3404 | |
b9404c99 UW |
3405 | (define_expand "cmpmem_short" |
3406 | [(parallel | |
ae156f85 | 3407 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3408 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3409 | (match_operand:BLK 1 "memory_operand" ""))) |
3410 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3411 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3412 | (clobber (match_dup 3))])] |
3413 | "" | |
3414 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3415 | |
b9404c99 | 3416 | (define_insn "*cmpmem_short" |
ae156f85 | 3417 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3418 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3419 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3420 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3421 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3422 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3423 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3424 | "#" |
963fc8d0 | 3425 | [(set_attr "type" "cs") |
b5e0425c | 3426 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3427 | |
9bb86f41 | 3428 | (define_split |
ae156f85 | 3429 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3430 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3431 | (match_operand:BLK 1 "memory_operand" ""))) | |
3432 | (use (match_operand 2 "const_int_operand" "")) | |
3433 | (use (match_operand 3 "immediate_operand" "")) | |
3434 | (clobber (scratch))] | |
3435 | "reload_completed" | |
3436 | [(parallel | |
ae156f85 | 3437 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3438 | (use (match_dup 2))])] |
3439 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3440 | |
9bb86f41 | 3441 | (define_split |
ae156f85 | 3442 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3443 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3444 | (match_operand:BLK 1 "memory_operand" ""))) | |
3445 | (use (match_operand 2 "register_operand" "")) | |
3446 | (use (match_operand 3 "memory_operand" "")) | |
3447 | (clobber (scratch))] | |
3448 | "reload_completed" | |
3449 | [(parallel | |
3450 | [(unspec [(match_dup 2) (match_dup 3) | |
3451 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3452 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3453 | (use (const_int 1))])] |
3454 | "") | |
3455 | ||
963fc8d0 AK |
3456 | (define_split |
3457 | [(set (reg:CCU CC_REGNUM) | |
3458 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3459 | (match_operand:BLK 1 "memory_operand" ""))) | |
3460 | (use (match_operand 2 "register_operand" "")) | |
3461 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3462 | (clobber (scratch))] | |
3463 | "TARGET_Z10 && reload_completed" | |
3464 | [(parallel | |
3465 | [(unspec [(match_dup 2) (const_int 0) | |
3466 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3467 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3468 | (use (const_int 1))])] | |
3469 | "operands[4] = gen_label_rtx ();") | |
3470 | ||
9bb86f41 | 3471 | (define_split |
ae156f85 | 3472 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3473 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3474 | (match_operand:BLK 1 "memory_operand" ""))) | |
3475 | (use (match_operand 2 "register_operand" "")) | |
3476 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3477 | (clobber (match_operand 3 "register_operand" ""))] | |
3478 | "reload_completed && TARGET_CPU_ZARCH" | |
3479 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3480 | (parallel | |
9381e3f1 | 3481 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3482 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3483 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3484 | (use (const_int 1))])] |
3485 | "operands[4] = gen_label_rtx ();") | |
3486 | ||
a41c6c53 | 3487 | ; Compare a block of arbitrary length. |
9db1d521 | 3488 | |
b9404c99 UW |
3489 | (define_expand "cmpmem_long" |
3490 | [(parallel | |
3491 | [(clobber (match_dup 2)) | |
3492 | (clobber (match_dup 3)) | |
ae156f85 | 3493 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3494 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3495 | (match_operand:BLK 1 "memory_operand" ""))) |
3496 | (use (match_operand 2 "general_operand" "")) | |
3497 | (use (match_dup 3))])] | |
3498 | "" | |
3499 | { | |
ef4bddc2 RS |
3500 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3501 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3502 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3503 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3504 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3505 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3506 | rtx len0 = gen_lowpart (Pmode, reg0); |
3507 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3508 | ||
c41c1387 | 3509 | emit_clobber (reg0); |
b9404c99 UW |
3510 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3511 | emit_move_insn (len0, operands[2]); | |
3512 | ||
c41c1387 | 3513 | emit_clobber (reg1); |
b9404c99 UW |
3514 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3515 | emit_move_insn (len1, operands[2]); | |
3516 | ||
3517 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3518 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3519 | operands[2] = reg0; | |
3520 | operands[3] = reg1; | |
3521 | }) | |
3522 | ||
a1aed706 AS |
3523 | (define_insn "*cmpmem_long" |
3524 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3525 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3526 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3527 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3528 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3529 | (use (match_dup 2)) |
3530 | (use (match_dup 3))] | |
9602b6a1 | 3531 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3532 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3533 | [(set_attr "length" "8") |
3534 | (set_attr "type" "vs")]) | |
9db1d521 | 3535 | |
9602b6a1 AK |
3536 | (define_insn "*cmpmem_long_31z" |
3537 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3538 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3539 | (set (reg:CCU CC_REGNUM) | |
3540 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3541 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3542 | (use (match_dup 2)) | |
3543 | (use (match_dup 3))] | |
3544 | "!TARGET_64BIT && TARGET_ZARCH" | |
3545 | "clcle\t%0,%1,0\;jo\t.-4" | |
3546 | [(set_attr "op_type" "NN") | |
3547 | (set_attr "type" "vs") | |
3548 | (set_attr "length" "8")]) | |
3549 | ||
02887425 UW |
3550 | ; Convert CCUmode condition code to integer. |
3551 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3552 | |
02887425 | 3553 | (define_insn_and_split "cmpint" |
9db1d521 | 3554 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3555 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3556 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3557 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3558 | "" |
02887425 UW |
3559 | "#" |
3560 | "reload_completed" | |
3561 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3562 | (parallel | |
3563 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3564 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3565 | |
3566 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3567 | [(set (reg CC_REGNUM) |
02887425 | 3568 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3569 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3570 | (const_int 0))) |
3571 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3572 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3573 | "s390_match_ccmode (insn, CCSmode)" |
3574 | "#" | |
3575 | "&& reload_completed" | |
3576 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3577 | (parallel | |
3578 | [(set (match_dup 2) (match_dup 3)) | |
3579 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3580 | { |
02887425 UW |
3581 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3582 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3583 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3584 | }) | |
9db1d521 | 3585 | |
02887425 | 3586 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3587 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3588 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3589 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3590 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3591 | "TARGET_ZARCH" |
02887425 UW |
3592 | "#" |
3593 | "&& reload_completed" | |
3594 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3595 | (parallel | |
3596 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3597 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3598 | |
3599 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3600 | [(set (reg CC_REGNUM) |
9381e3f1 | 3601 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3602 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3603 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3604 | (const_int 32)) (const_int 32)) |
3605 | (const_int 0))) | |
3606 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3607 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3608 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3609 | "#" |
3610 | "&& reload_completed" | |
3611 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3612 | (parallel | |
3613 | [(set (match_dup 2) (match_dup 3)) | |
3614 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3615 | { |
02887425 UW |
3616 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3617 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3618 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3619 | }) | |
9db1d521 | 3620 | |
4023fb28 | 3621 | |
9db1d521 HP |
3622 | ;; |
3623 | ;;- Conversion instructions. | |
3624 | ;; | |
3625 | ||
6fa05db6 | 3626 | (define_insn "*sethighpartsi" |
d3632d41 | 3627 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3628 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3629 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3630 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3631 | "" |
d3632d41 | 3632 | "@ |
6fa05db6 AS |
3633 | icm\t%0,%2,%S1 |
3634 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3635 | [(set_attr "op_type" "RS,RSY") |
3636 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3637 | |
6fa05db6 | 3638 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3639 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3640 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3641 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3642 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3643 | "TARGET_ZARCH" |
6fa05db6 | 3644 | "icmh\t%0,%2,%S1" |
729e750f WG |
3645 | [(set_attr "op_type" "RSY") |
3646 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3647 | |
6fa05db6 | 3648 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3649 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3650 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3651 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3652 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3653 | "!TARGET_ZARCH" |
d3632d41 | 3654 | "@ |
6fa05db6 AS |
3655 | icm\t%0,%2,%S1 |
3656 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3657 | [(set_attr "op_type" "RS,RSY") |
3658 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3659 | ||
1a2e356e RH |
3660 | ; |
3661 | ; extv instruction patterns | |
3662 | ; | |
3663 | ||
3664 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3665 | ; after resolving some issues with it. | |
3666 | ||
3667 | (define_expand "extzv" | |
3668 | [(parallel | |
3669 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3670 | (zero_extract:DI | |
3671 | (match_operand:DI 1 "register_operand" "d") | |
3672 | (match_operand 2 "const_int_operand" "") ; size | |
3673 | (match_operand 3 "const_int_operand" ""))) ; start | |
3674 | (clobber (reg:CC CC_REGNUM))])] | |
3675 | "TARGET_Z10" | |
3676 | { | |
3677 | /* Starting with zEC12 there is risbgn not clobbering CC. */ | |
3678 | if (TARGET_ZEC12) | |
3679 | { | |
3680 | emit_move_insn (operands[0], | |
3681 | gen_rtx_ZERO_EXTRACT (DImode, | |
3682 | operands[1], | |
3683 | operands[2], | |
3684 | operands[3])); | |
3685 | DONE; | |
3686 | } | |
3687 | }) | |
3688 | ||
3689 | (define_insn "*extzv<mode>_zEC12" | |
3690 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3691 | (zero_extract:GPR | |
3692 | (match_operand:GPR 1 "register_operand" "d") | |
3693 | (match_operand 2 "const_int_operand" "") ; size | |
3694 | (match_operand 3 "const_int_operand" "")))] ; start] | |
3695 | "TARGET_ZEC12" | |
3696 | "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3697 | [(set_attr "op_type" "RIE")]) | |
3698 | ||
3699 | (define_insn "*extzv<mode>_z10" | |
3700 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3701 | (zero_extract:GPR | |
3702 | (match_operand:GPR 1 "register_operand" "d") | |
3703 | (match_operand 2 "const_int_operand" "") ; size | |
3704 | (match_operand 3 "const_int_operand" ""))) ; start | |
3705 | (clobber (reg:CC CC_REGNUM))] | |
3706 | "TARGET_Z10" | |
3707 | "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3708 | [(set_attr "op_type" "RIE") | |
3709 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3710 | |
1a2e356e | 3711 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 AS |
3712 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3713 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3714 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3715 | (const_int 0))) |
ae156f85 | 3716 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3717 | "!TARGET_Z10" |
cc7ab9b7 UW |
3718 | "#" |
3719 | "&& reload_completed" | |
4023fb28 | 3720 | [(parallel |
6fa05db6 | 3721 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3722 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3723 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3724 | { |
6fa05db6 AS |
3725 | int bitsize = INTVAL (operands[2]); |
3726 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3727 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3728 | ||
3729 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3730 | set_mem_size (operands[1], size); |
2542ef05 | 3731 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3732 | operands[3] = GEN_INT (mask); |
b628bd8e | 3733 | }) |
4023fb28 | 3734 | |
1a2e356e | 3735 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 AS |
3736 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3737 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3738 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3739 | (const_int 0))) |
ae156f85 | 3740 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3741 | "" |
cc7ab9b7 UW |
3742 | "#" |
3743 | "&& reload_completed" | |
4023fb28 | 3744 | [(parallel |
6fa05db6 | 3745 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3746 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3747 | (parallel |
3748 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3749 | (clobber (reg:CC CC_REGNUM))])] | |
3750 | { | |
3751 | int bitsize = INTVAL (operands[2]); | |
3752 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3753 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3754 | ||
3755 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3756 | set_mem_size (operands[1], size); |
2542ef05 | 3757 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3758 | operands[3] = GEN_INT (mask); |
3759 | }) | |
3760 | ||
3761 | ; | |
3762 | ; insv instruction patterns | |
3763 | ; | |
3764 | ||
3765 | (define_expand "insv" | |
3766 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3767 | (match_operand 1 "const_int_operand" "") | |
3768 | (match_operand 2 "const_int_operand" "")) | |
3769 | (match_operand 3 "general_operand" ""))] | |
3770 | "" | |
4023fb28 | 3771 | { |
6fa05db6 AS |
3772 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3773 | DONE; | |
3774 | FAIL; | |
b628bd8e | 3775 | }) |
4023fb28 | 3776 | |
2542ef05 RH |
3777 | |
3778 | ; The normal RTL expansion will never generate a zero_extract where | |
3779 | ; the location operand isn't word mode. However, we do this in the | |
3780 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
22ac2c2f AK |
3781 | (define_insn "*insv<mode>_zEC12" |
3782 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3783 | (match_operand 1 "const_int_operand" "I") ; size |
3784 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f AK |
3785 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
3786 | "TARGET_ZEC12 | |
2542ef05 RH |
3787 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3788 | "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
22ac2c2f AK |
3789 | [(set_attr "op_type" "RIE")]) |
3790 | ||
963fc8d0 AK |
3791 | (define_insn "*insv<mode>_z10" |
3792 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3793 | (match_operand 1 "const_int_operand" "I") ; size |
3794 | (match_operand 2 "const_int_operand" "I")) ; pos | |
963fc8d0 AK |
3795 | (match_operand:GPR 3 "nonimmediate_operand" "d")) |
3796 | (clobber (reg:CC CC_REGNUM))] | |
3797 | "TARGET_Z10 | |
2542ef05 RH |
3798 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3799 | "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
9381e3f1 WG |
3800 | [(set_attr "op_type" "RIE") |
3801 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3802 | |
22ac2c2f AK |
3803 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3804 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3805 | (define_insn "*insv<mode>_zEC12_noshift" | |
3806 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3807 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3808 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
22ac2c2f | 3809 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 RH |
3810 | (match_operand:GPR 4 "const_int_operand" ""))))] |
3811 | "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3812 | "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
22ac2c2f AK |
3813 | [(set_attr "op_type" "RIE")]) |
3814 | ||
963fc8d0 AK |
3815 | (define_insn "*insv<mode>_z10_noshift" |
3816 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3817 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3818 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
963fc8d0 | 3819 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 | 3820 | (match_operand:GPR 4 "const_int_operand" "")))) |
963fc8d0 | 3821 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 RH |
3822 | "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3823 | "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
9381e3f1 WG |
3824 | [(set_attr "op_type" "RIE") |
3825 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3826 | |
3d44ff99 AK |
3827 | ; Implement appending Y on the left of S bits of X |
3828 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
3829 | (define_insn "*insv<mode>_zEC12_appendbitsleft" | |
3830 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3831 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
3832 | (match_operand:GPR 2 "immediate_operand" "")) | |
3833 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
3834 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
3835 | "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
3836 | "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4" | |
3837 | [(set_attr "op_type" "RIE") | |
3838 | (set_attr "z10prop" "z10_super_E1")]) | |
3839 | ||
3840 | (define_insn "*insv<mode>_z10_appendbitsleft" | |
3841 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3842 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
3843 | (match_operand:GPR 2 "immediate_operand" "")) | |
3844 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
3845 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
3846 | (clobber (reg:CC CC_REGNUM))] | |
3847 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
3848 | "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4" | |
3849 | [(set_attr "op_type" "RIE") | |
3850 | (set_attr "z10prop" "z10_super_E1")]) | |
3851 | ||
3852 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
3853 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
3854 | ; -> z = y >> d; z = risbg; | |
3855 | ||
3856 | (define_split | |
3857 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
3858 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3859 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
3860 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
3861 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
3862 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 3863 | [(set (match_dup 6) |
3d44ff99 AK |
3864 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
3865 | (set (match_dup 0) | |
1d11f7ce | 3866 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
3867 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
3868 | { | |
3869 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
1d11f7ce AK |
3870 | if (rtx_equal_p (operands[0], operands[3])) |
3871 | { | |
3872 | if (!can_create_pseudo_p ()) | |
3873 | FAIL; | |
3874 | operands[6] = gen_reg_rtx (<MODE>mode); | |
3875 | } | |
3876 | else | |
3877 | operands[6] = operands[0]; | |
3d44ff99 AK |
3878 | }) |
3879 | ||
3880 | (define_split | |
3881 | [(parallel | |
3882 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
3883 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3884 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
3885 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
3886 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
3887 | (clobber (reg:CC CC_REGNUM))])] | |
3888 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 3889 | [(set (match_dup 6) |
3d44ff99 AK |
3890 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
3891 | (parallel | |
3892 | [(set (match_dup 0) | |
1d11f7ce | 3893 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
3894 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
3895 | (clobber (reg:CC CC_REGNUM))])] | |
3896 | { | |
3897 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
1d11f7ce AK |
3898 | if (rtx_equal_p (operands[0], operands[3])) |
3899 | { | |
3900 | if (!can_create_pseudo_p ()) | |
3901 | FAIL; | |
3902 | operands[6] = gen_reg_rtx (<MODE>mode); | |
3903 | } | |
3904 | else | |
3905 | operands[6] = operands[0]; | |
3d44ff99 AK |
3906 | }) |
3907 | ||
571e408a | 3908 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 3909 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
3910 | (IXOR:GPR |
3911 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3912 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3913 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 3914 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 3915 | "TARGET_Z10" |
571e408a RH |
3916 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
3917 | [(set_attr "op_type" "RIE")]) | |
3918 | ||
3919 | (define_insn "*r<noxa>sbg_di_rotl" | |
3920 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
3921 | (IXOR:DI | |
3922 | (and:DI | |
3923 | (rotate:DI | |
3924 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
3925 | (match_operand:DI 3 "const_int_operand" "")) | |
3926 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
3927 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
3928 | (clobber (reg:CC CC_REGNUM))] | |
3929 | "TARGET_Z10" | |
3930 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
3931 | [(set_attr "op_type" "RIE")]) | |
3932 | ||
3933 | (define_insn "*r<noxa>sbg_<mode>_srl" | |
3934 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3935 | (IXOR:GPR | |
3936 | (and:GPR | |
3937 | (lshiftrt:GPR | |
3938 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3939 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3940 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3941 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3942 | (clobber (reg:CC CC_REGNUM))] | |
3943 | "TARGET_Z10 | |
3944 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
3945 | INTVAL (operands[2]))" | |
3946 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
3947 | [(set_attr "op_type" "RIE")]) | |
3948 | ||
3949 | (define_insn "*r<noxa>sbg_<mode>_sll" | |
3950 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3951 | (IXOR:GPR | |
3952 | (and:GPR | |
3953 | (ashift:GPR | |
3954 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3955 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3956 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3957 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3958 | (clobber (reg:CC CC_REGNUM))] | |
3959 | "TARGET_Z10 | |
3960 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
3961 | INTVAL (operands[2]))" | |
3962 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
3963 | [(set_attr "op_type" "RIE")]) |
3964 | ||
5bb33936 RH |
3965 | ;; These two are generated by combine for s.bf &= val. |
3966 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
3967 | ;; shifts and ands, which results in some truly awful patterns | |
3968 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
3969 | ;; Instead of | |
3970 | ;; | |
3971 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3972 | ;; (const_int 24 [0x18]) | |
3973 | ;; (const_int 0 [0])) | |
3974 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3975 | ;; (const_int 40 [0x28])) 4) | |
3976 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
3977 | ;; | |
3978 | ;; we should instead generate | |
3979 | ;; | |
3980 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3981 | ;; (const_int 24 [0x18]) | |
3982 | ;; (const_int 0 [0])) | |
3983 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3984 | ;; (const_int 40 [0x28])) | |
3985 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
3986 | ;; | |
3987 | ;; by noticing that we can push down the outer paradoxical subreg | |
3988 | ;; into the operation. | |
3989 | ||
3990 | (define_insn "*insv_rnsbg_noshift" | |
3991 | [(set (zero_extract:DI | |
3992 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3993 | (match_operand 1 "const_int_operand" "") | |
3994 | (match_operand 2 "const_int_operand" "")) | |
3995 | (and:DI | |
3996 | (match_dup 0) | |
3997 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
3998 | (clobber (reg:CC CC_REGNUM))] | |
3999 | "TARGET_Z10 | |
4000 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" | |
4001 | "rnsbg\t%0,%3,%2,63,0" | |
4002 | [(set_attr "op_type" "RIE")]) | |
4003 | ||
4004 | (define_insn "*insv_rnsbg_srl" | |
4005 | [(set (zero_extract:DI | |
4006 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4007 | (match_operand 1 "const_int_operand" "") | |
4008 | (match_operand 2 "const_int_operand" "")) | |
4009 | (and:DI | |
4010 | (lshiftrt:DI | |
4011 | (match_dup 0) | |
4012 | (match_operand 3 "const_int_operand" "")) | |
4013 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4014 | (clobber (reg:CC CC_REGNUM))] | |
4015 | "TARGET_Z10 | |
4016 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" | |
4017 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4018 | [(set_attr "op_type" "RIE")]) | |
4019 | ||
6fa05db6 | 4020 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4021 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4022 | (match_operand 1 "const_int_operand" "n,n") |
4023 | (const_int 0)) | |
9602b6a1 | 4024 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
4025 | "INTVAL (operands[1]) > 0 |
4026 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4027 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4028 | { | |
4029 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4030 | ||
4031 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4032 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4033 | : "stcmy\t%2,%1,%S0"; |
4034 | } | |
9381e3f1 WG |
4035 | [(set_attr "op_type" "RS,RSY") |
4036 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
4037 | |
4038 | (define_insn "*insvdi_mem_reghigh" | |
4039 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
4040 | (match_operand 1 "const_int_operand" "n") | |
4041 | (const_int 0)) | |
4042 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4043 | (const_int 32)))] | |
9602b6a1 | 4044 | "TARGET_ZARCH |
6fa05db6 AS |
4045 | && INTVAL (operands[1]) > 0 |
4046 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4047 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4048 | { | |
4049 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4050 | ||
4051 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4052 | return "stcmh\t%2,%1,%S0"; | |
4053 | } | |
9381e3f1 WG |
4054 | [(set_attr "op_type" "RSY") |
4055 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4056 | |
9602b6a1 AK |
4057 | (define_insn "*insvdi_reg_imm" |
4058 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4059 | (const_int 16) | |
4060 | (match_operand 1 "const_int_operand" "n")) | |
4061 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
4062 | "TARGET_ZARCH |
4063 | && INTVAL (operands[1]) >= 0 | |
4064 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4065 | && INTVAL (operands[1]) % 16 == 0" | |
4066 | { | |
4067 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4068 | { | |
4069 | case 64: return "iihh\t%0,%x2"; break; | |
4070 | case 48: return "iihl\t%0,%x2"; break; | |
4071 | case 32: return "iilh\t%0,%x2"; break; | |
4072 | case 16: return "iill\t%0,%x2"; break; | |
4073 | default: gcc_unreachable(); | |
4074 | } | |
4075 | } | |
9381e3f1 WG |
4076 | [(set_attr "op_type" "RI") |
4077 | (set_attr "z10prop" "z10_super_E1")]) | |
4078 | ||
9fec758d WG |
4079 | ; Update the left-most 32 bit of a DI. |
4080 | (define_insn "*insv_h_di_reg_extimm" | |
4081 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4082 | (const_int 32) | |
4083 | (const_int 0)) | |
4084 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4085 | "TARGET_EXTIMM" | |
4086 | "iihf\t%0,%o1" | |
4087 | [(set_attr "op_type" "RIL") | |
4088 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4089 | |
d378b983 RH |
4090 | ; Update the right-most 32 bit of a DI. |
4091 | (define_insn "*insv_l_di_reg_extimm" | |
4092 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4093 | (const_int 32) | |
4094 | (const_int 32)) | |
4095 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4096 | "TARGET_EXTIMM" | |
4097 | "iilf\t%0,%o1" | |
9381e3f1 | 4098 | [(set_attr "op_type" "RIL") |
9fec758d | 4099 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4100 | |
9db1d521 HP |
4101 | ; |
4102 | ; extendsidi2 instruction pattern(s). | |
4103 | ; | |
4104 | ||
4023fb28 UW |
4105 | (define_expand "extendsidi2" |
4106 | [(set (match_operand:DI 0 "register_operand" "") | |
4107 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4108 | "" | |
4023fb28 | 4109 | { |
9602b6a1 | 4110 | if (!TARGET_ZARCH) |
4023fb28 | 4111 | { |
c41c1387 | 4112 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4113 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4114 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4115 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4116 | DONE; |
4117 | } | |
ec24698e | 4118 | }) |
4023fb28 UW |
4119 | |
4120 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
4121 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4122 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 4123 | "TARGET_ZARCH" |
9db1d521 | 4124 | "@ |
d40c829f | 4125 | lgfr\t%0,%1 |
963fc8d0 AK |
4126 | lgf\t%0,%1 |
4127 | lgfrl\t%0,%1" | |
4128 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4129 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4130 | (set_attr "cpu_facility" "*,*,z10") |
4131 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4132 | |
9db1d521 | 4133 | ; |
56477c21 | 4134 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4135 | ; |
4136 | ||
56477c21 AS |
4137 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4138 | [(set (match_operand:DSI 0 "register_operand" "") | |
4139 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4140 | "" |
4023fb28 | 4141 | { |
9602b6a1 | 4142 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4143 | { |
4144 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4145 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4146 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4147 | DONE; | |
4148 | } | |
ec24698e | 4149 | else if (!TARGET_EXTIMM) |
4023fb28 | 4150 | { |
2542ef05 | 4151 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4152 | |
4153 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4154 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4155 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4156 | DONE; |
4157 | } | |
ec24698e UW |
4158 | }) |
4159 | ||
56477c21 AS |
4160 | ; |
4161 | ; extendhidi2 instruction pattern(s). | |
4162 | ; | |
4163 | ||
ec24698e | 4164 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
4165 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4166 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 4167 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4168 | "@ |
4169 | lghr\t%0,%1 | |
963fc8d0 AK |
4170 | lgh\t%0,%1 |
4171 | lghrl\t%0,%1" | |
4172 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4173 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4174 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4175 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4176 | |
4177 | (define_insn "*extendhidi2" | |
9db1d521 | 4178 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 4179 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 4180 | "TARGET_ZARCH" |
d40c829f | 4181 | "lgh\t%0,%1" |
9381e3f1 WG |
4182 | [(set_attr "op_type" "RXY") |
4183 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4184 | |
9db1d521 | 4185 | ; |
56477c21 | 4186 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4187 | ; |
4188 | ||
ec24698e | 4189 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4190 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4191 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4192 | "TARGET_EXTIMM" |
4193 | "@ | |
4194 | lhr\t%0,%1 | |
4195 | lh\t%0,%1 | |
963fc8d0 AK |
4196 | lhy\t%0,%1 |
4197 | lhrl\t%0,%1" | |
4198 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4199 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4200 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4201 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4202 | |
4023fb28 | 4203 | (define_insn "*extendhisi2" |
d3632d41 UW |
4204 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4205 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4206 | "!TARGET_EXTIMM" |
d3632d41 | 4207 | "@ |
d40c829f UW |
4208 | lh\t%0,%1 |
4209 | lhy\t%0,%1" | |
9381e3f1 WG |
4210 | [(set_attr "op_type" "RX,RXY") |
4211 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4212 | |
56477c21 AS |
4213 | ; |
4214 | ; extendqi(si|di)2 instruction pattern(s). | |
4215 | ; | |
4216 | ||
43a09b63 | 4217 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4218 | (define_insn "*extendqi<mode>2_extimm" |
4219 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4220 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4221 | "TARGET_EXTIMM" |
4222 | "@ | |
56477c21 AS |
4223 | l<g>br\t%0,%1 |
4224 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4225 | [(set_attr "op_type" "RRE,RXY") |
4226 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4227 | |
43a09b63 | 4228 | ; lb, lgb |
56477c21 AS |
4229 | (define_insn "*extendqi<mode>2" |
4230 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4231 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
4232 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4233 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4234 | [(set_attr "op_type" "RXY") |
4235 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4236 | |
56477c21 AS |
4237 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4238 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4239 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4240 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4241 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4242 | "#" |
4243 | "&& reload_completed" | |
4023fb28 | 4244 | [(parallel |
56477c21 | 4245 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4246 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4247 | (parallel |
56477c21 | 4248 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4249 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4250 | { |
4251 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4252 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4253 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4254 | }) |
9db1d521 | 4255 | |
9db1d521 HP |
4256 | ; |
4257 | ; zero_extendsidi2 instruction pattern(s). | |
4258 | ; | |
4259 | ||
4023fb28 UW |
4260 | (define_expand "zero_extendsidi2" |
4261 | [(set (match_operand:DI 0 "register_operand" "") | |
4262 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4263 | "" | |
4023fb28 | 4264 | { |
9602b6a1 | 4265 | if (!TARGET_ZARCH) |
4023fb28 | 4266 | { |
c41c1387 | 4267 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4268 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4269 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4270 | DONE; |
4271 | } | |
ec24698e | 4272 | }) |
4023fb28 UW |
4273 | |
4274 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
4275 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4276 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 4277 | "TARGET_ZARCH" |
9db1d521 | 4278 | "@ |
d40c829f | 4279 | llgfr\t%0,%1 |
963fc8d0 AK |
4280 | llgf\t%0,%1 |
4281 | llgfrl\t%0,%1" | |
4282 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4283 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4284 | (set_attr "cpu_facility" "*,*,z10") |
4285 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4286 | |
288e517f AK |
4287 | ; |
4288 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4289 | ; | |
4290 | ||
d6083c7d UW |
4291 | (define_insn "*llgt_sidi" |
4292 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 4293 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 4294 | (const_int 2147483647)))] |
9602b6a1 | 4295 | "TARGET_ZARCH" |
d6083c7d | 4296 | "llgt\t%0,%1" |
9381e3f1 WG |
4297 | [(set_attr "op_type" "RXE") |
4298 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4299 | |
4300 | (define_insn_and_split "*llgt_sidi_split" | |
4301 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 4302 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 4303 | (const_int 2147483647))) |
ae156f85 | 4304 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4305 | "TARGET_ZARCH" |
d6083c7d UW |
4306 | "#" |
4307 | "&& reload_completed" | |
4308 | [(set (match_dup 0) | |
4309 | (and:DI (subreg:DI (match_dup 1) 0) | |
4310 | (const_int 2147483647)))] | |
4311 | "") | |
4312 | ||
288e517f AK |
4313 | (define_insn "*llgt_sisi" |
4314 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 4315 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 4316 | (const_int 2147483647)))] |
c4d50129 | 4317 | "TARGET_ZARCH" |
288e517f AK |
4318 | "@ |
4319 | llgtr\t%0,%1 | |
4320 | llgt\t%0,%1" | |
9381e3f1 WG |
4321 | [(set_attr "op_type" "RRE,RXE") |
4322 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4323 | |
288e517f AK |
4324 | (define_insn "*llgt_didi" |
4325 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4326 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4327 | (const_int 2147483647)))] | |
9602b6a1 | 4328 | "TARGET_ZARCH" |
288e517f AK |
4329 | "@ |
4330 | llgtr\t%0,%1 | |
4331 | llgt\t%0,%N1" | |
9381e3f1 WG |
4332 | [(set_attr "op_type" "RRE,RXE") |
4333 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4334 | |
f19a9af7 | 4335 | (define_split |
9602b6a1 AK |
4336 | [(set (match_operand:DSI 0 "register_operand" "") |
4337 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4338 | (const_int 2147483647))) |
ae156f85 | 4339 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4340 | "TARGET_ZARCH && reload_completed" |
288e517f | 4341 | [(set (match_dup 0) |
9602b6a1 | 4342 | (and:DSI (match_dup 1) |
f6ee577c | 4343 | (const_int 2147483647)))] |
288e517f AK |
4344 | "") |
4345 | ||
9db1d521 | 4346 | ; |
56477c21 | 4347 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4348 | ; |
4349 | ||
56477c21 AS |
4350 | (define_expand "zero_extend<mode>di2" |
4351 | [(set (match_operand:DI 0 "register_operand" "") | |
4352 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4353 | "" | |
4354 | { | |
9602b6a1 | 4355 | if (!TARGET_ZARCH) |
56477c21 AS |
4356 | { |
4357 | rtx tmp = gen_reg_rtx (SImode); | |
4358 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4359 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4360 | DONE; | |
4361 | } | |
4362 | else if (!TARGET_EXTIMM) | |
4363 | { | |
2542ef05 | 4364 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4365 | operands[1] = gen_lowpart (DImode, operands[1]); |
4366 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4367 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4368 | DONE; | |
4369 | } | |
4370 | }) | |
4371 | ||
f6ee577c | 4372 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4373 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4374 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4375 | "" |
4023fb28 | 4376 | { |
ec24698e UW |
4377 | if (!TARGET_EXTIMM) |
4378 | { | |
4379 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4380 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4381 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4382 | DONE; |
56477c21 | 4383 | } |
ec24698e UW |
4384 | }) |
4385 | ||
963fc8d0 AK |
4386 | ; llhrl, llghrl |
4387 | (define_insn "*zero_extendhi<mode>2_z10" | |
4388 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4389 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
4390 | "TARGET_Z10" | |
4391 | "@ | |
4392 | ll<g>hr\t%0,%1 | |
4393 | ll<g>h\t%0,%1 | |
4394 | ll<g>hrl\t%0,%1" | |
4395 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4396 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4397 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4398 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4399 | |
43a09b63 | 4400 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4401 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4402 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4403 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4404 | "TARGET_EXTIMM" |
4405 | "@ | |
56477c21 AS |
4406 | ll<g><hc>r\t%0,%1 |
4407 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4408 | [(set_attr "op_type" "RRE,RXY") |
4409 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4410 | |
43a09b63 | 4411 | ; llgh, llgc |
56477c21 AS |
4412 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4413 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4414 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 4415 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4416 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4417 | [(set_attr "op_type" "RXY") |
4418 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4419 | |
4420 | (define_insn_and_split "*zero_extendhisi2_31" | |
4421 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 4422 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 4423 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4424 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4425 | "#" |
4426 | "&& reload_completed" | |
4427 | [(set (match_dup 0) (const_int 0)) | |
4428 | (parallel | |
4429 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4430 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4431 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4432 | |
cc7ab9b7 UW |
4433 | (define_insn_and_split "*zero_extendqisi2_31" |
4434 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 4435 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4436 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4437 | "#" |
4438 | "&& reload_completed" | |
4439 | [(set (match_dup 0) (const_int 0)) | |
4440 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4441 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4442 | |
9db1d521 HP |
4443 | ; |
4444 | ; zero_extendqihi2 instruction pattern(s). | |
4445 | ; | |
4446 | ||
9db1d521 HP |
4447 | (define_expand "zero_extendqihi2" |
4448 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4449 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4450 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4451 | { |
4023fb28 UW |
4452 | operands[1] = gen_lowpart (HImode, operands[1]); |
4453 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4454 | DONE; | |
ec24698e | 4455 | }) |
9db1d521 | 4456 | |
4023fb28 | 4457 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4458 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 4459 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 4460 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4461 | "llgc\t%0,%1" |
9381e3f1 WG |
4462 | [(set_attr "op_type" "RXY") |
4463 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4464 | |
cc7ab9b7 UW |
4465 | (define_insn_and_split "*zero_extendqihi2_31" |
4466 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 4467 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4468 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4469 | "#" |
4470 | "&& reload_completed" | |
4471 | [(set (match_dup 0) (const_int 0)) | |
4472 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4473 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4474 | |
609e7e80 AK |
4475 | ; |
4476 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
4477 | ; | |
4478 | ||
4479 | (define_expand "fixuns_truncdddi2" | |
4480 | [(parallel | |
4481 | [(set (match_operand:DI 0 "register_operand" "") | |
4482 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
65b1d8ea AK |
4483 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) |
4484 | (clobber (reg:CC CC_REGNUM))])] | |
9381e3f1 | 4485 | |
fb068247 | 4486 | "TARGET_HARD_DFP" |
609e7e80 | 4487 | { |
65b1d8ea AK |
4488 | if (!TARGET_Z196) |
4489 | { | |
19f8b229 TS |
4490 | rtx_code_label *label1 = gen_label_rtx (); |
4491 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4492 | rtx temp = gen_reg_rtx (TDmode); |
4493 | REAL_VALUE_TYPE cmp, sub; | |
4494 | ||
4495 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4496 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4497 | ||
4498 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4499 | solution is doing the check and the subtraction in TD mode and using a | |
4500 | TD -> DI convert afterwards. */ | |
4501 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4502 | temp = force_reg (TDmode, temp); | |
4503 | emit_cmp_and_jump_insns (temp, | |
555affd7 | 4504 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4505 | LT, NULL_RTX, VOIDmode, 0, label1); |
4506 | emit_insn (gen_subtd3 (temp, temp, | |
555affd7 | 4507 | const_double_from_real_value (sub, TDmode))); |
65b1d8ea AK |
4508 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
4509 | emit_jump (label2); | |
4510 | ||
4511 | emit_label (label1); | |
4512 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4513 | emit_label (label2); | |
4514 | DONE; | |
4515 | } | |
609e7e80 AK |
4516 | }) |
4517 | ||
4518 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
4519 | [(parallel |
4520 | [(set (match_operand:DI 0 "register_operand" "") | |
4521 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4522 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) | |
4523 | (clobber (reg:CC CC_REGNUM))])] | |
4524 | ||
fb068247 | 4525 | "TARGET_HARD_DFP" |
609e7e80 | 4526 | { |
65b1d8ea AK |
4527 | if (!TARGET_Z196) |
4528 | { | |
19f8b229 TS |
4529 | rtx_code_label *label1 = gen_label_rtx (); |
4530 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4531 | rtx temp = gen_reg_rtx (TDmode); |
4532 | REAL_VALUE_TYPE cmp, sub; | |
4533 | ||
4534 | operands[1] = force_reg (TDmode, operands[1]); | |
4535 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4536 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4537 | ||
4538 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4539 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4540 | LT, NULL_RTX, VOIDmode, 0, label1); |
4541 | emit_insn (gen_subtd3 (temp, operands[1], | |
555affd7 | 4542 | const_double_from_real_value (sub, TDmode))); |
65b1d8ea AK |
4543 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
4544 | emit_jump (label2); | |
4545 | ||
4546 | emit_label (label1); | |
4547 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4548 | emit_label (label2); | |
4549 | DONE; | |
4550 | } | |
609e7e80 | 4551 | }) |
cc7ab9b7 | 4552 | |
9db1d521 | 4553 | ; |
65b1d8ea | 4554 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 4555 | ; instruction pattern(s). |
9db1d521 HP |
4556 | ; |
4557 | ||
7b6baae1 | 4558 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
4559 | [(parallel |
4560 | [(set (match_operand:GPR 0 "register_operand" "") | |
4561 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4562 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4563 | (clobber (reg:CC CC_REGNUM))])] | |
142cd70f | 4564 | "TARGET_HARD_FLOAT" |
9db1d521 | 4565 | { |
65b1d8ea AK |
4566 | if (!TARGET_Z196) |
4567 | { | |
19f8b229 TS |
4568 | rtx_code_label *label1 = gen_label_rtx (); |
4569 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4570 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); |
4571 | REAL_VALUE_TYPE cmp, sub; | |
4572 | ||
4573 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
2542ef05 RH |
4574 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); |
4575 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
65b1d8ea AK |
4576 | |
4577 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4578 | const_double_from_real_value (cmp, <BFP:MODE>mode), |
65b1d8ea AK |
4579 | LT, NULL_RTX, VOIDmode, 0, label1); |
4580 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
555affd7 | 4581 | const_double_from_real_value (sub, <BFP:MODE>mode))); |
65b1d8ea AK |
4582 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, |
4583 | GEN_INT (7))); | |
4584 | emit_jump (label2); | |
4585 | ||
4586 | emit_label (label1); | |
4587 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4588 | operands[1], GEN_INT (5))); | |
4589 | emit_label (label2); | |
4590 | DONE; | |
4591 | } | |
10bbf137 | 4592 | }) |
9db1d521 | 4593 | |
65b1d8ea AK |
4594 | ; fixuns_trunc(td|dd)si2 expander |
4595 | (define_expand "fixuns_trunc<mode>si2" | |
4596 | [(parallel | |
4597 | [(set (match_operand:SI 0 "register_operand" "") | |
4598 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
4599 | (unspec:SI [(const_int 5)] UNSPEC_ROUND) | |
4600 | (clobber (reg:CC CC_REGNUM))])] | |
8540e6e8 | 4601 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4602 | "") |
4603 | ||
4604 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4605 | ||
6e5b5de8 AK |
4606 | (define_insn "*fixuns_truncdfdi2_z13" |
4607 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4608 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4609 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4610 | (clobber (reg:CC CC_REGNUM))] | |
4611 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4612 | "@ | |
4613 | clgdbr\t%0,%h2,%1,0 | |
4614 | wclgdb\t%v0,%v1,0,%h2" | |
4615 | [(set_attr "op_type" "RRF,VRR") | |
4616 | (set_attr "type" "ftoi")]) | |
4617 | ||
65b1d8ea AK |
4618 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4619 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4620 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4621 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4622 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4623 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 4624 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4625 | "TARGET_Z196 && TARGET_HARD_FLOAT |
4626 | && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" | |
65b1d8ea AK |
4627 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
4628 | [(set_attr "op_type" "RRF") | |
4629 | (set_attr "type" "ftoi")]) | |
4630 | ||
b60cb710 AK |
4631 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4632 | [(set (match_operand:GPR 0 "register_operand" "") | |
4633 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4634 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4635 | { |
b60cb710 AK |
4636 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
4637 | GEN_INT (5))); | |
9db1d521 | 4638 | DONE; |
10bbf137 | 4639 | }) |
9db1d521 | 4640 | |
6e5b5de8 AK |
4641 | (define_insn "*fix_truncdfdi2_bfp_z13" |
4642 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4643 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4644 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4645 | (clobber (reg:CC CC_REGNUM))] | |
4646 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4647 | "@ | |
4648 | cgdbr\t%0,%h2,%1 | |
4649 | wcgdb\t%v0,%v1,0,%h2" | |
4650 | [(set_attr "op_type" "RRE,VRR") | |
4651 | (set_attr "type" "ftoi")]) | |
4652 | ||
43a09b63 | 4653 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
4654 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4655 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4656 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4657 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 4658 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4659 | "TARGET_HARD_FLOAT |
4660 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 4661 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4662 | [(set_attr "op_type" "RRE") |
077dab3b | 4663 | (set_attr "type" "ftoi")]) |
9db1d521 | 4664 | |
6e5b5de8 AK |
4665 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4666 | [(parallel | |
4667 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4668 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4669 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4670 | (clobber (reg:CC CC_REGNUM))])] | |
4671 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
4672 | ; |
4673 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4674 | ; | |
4675 | ||
99cd7dd0 AK |
4676 | (define_expand "fix_trunc<mode>di2" |
4677 | [(set (match_operand:DI 0 "register_operand" "") | |
4678 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4679 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4680 | { |
4681 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4682 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
4683 | GEN_INT (9))); | |
4684 | DONE; | |
4685 | }) | |
4686 | ||
609e7e80 | 4687 | ; cgxtr, cgdtr |
99cd7dd0 | 4688 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4689 | [(set (match_operand:DI 0 "register_operand" "=d") |
4690 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4691 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4692 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4693 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4694 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4695 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4696 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4697 | |
4698 | ||
f61a2c7d AK |
4699 | ; |
4700 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4701 | ; | |
4702 | ||
4703 | (define_expand "fix_trunctf<mode>2" | |
4704 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4705 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
4706 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4707 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 4708 | "TARGET_HARD_FLOAT" |
142cd70f | 4709 | "") |
9db1d521 | 4710 | |
9db1d521 | 4711 | |
9db1d521 | 4712 | ; |
142cd70f | 4713 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4714 | ; |
4715 | ||
609e7e80 | 4716 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4717 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
4718 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
4719 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 4720 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4721 | "@ |
4722 | c<xde>g<bt>r\t%0,%1 | |
4723 | wcdgb\t%v0,%v1,0,0" | |
4724 | [(set_attr "op_type" "RRE,VRR") | |
4725 | (set_attr "type" "itof<mode>" ) | |
62d3f261 AK |
4726 | (set_attr "cpu_facility" "*,vec") |
4727 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 4728 | |
43a09b63 | 4729 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4730 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4731 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4732 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4733 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4734 | "c<xde>fbr\t%0,%1" |
4735 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4736 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4737 | |
65b1d8ea AK |
4738 | ; cxftr, cdftr |
4739 | (define_insn "floatsi<mode>2" | |
4740 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4741 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4742 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4743 | "c<xde>ftr\t%0,0,%1,0" | |
4744 | [(set_attr "op_type" "RRE") | |
4745 | (set_attr "type" "itof<mode>" )]) | |
4746 | ||
4747 | ; | |
4748 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4749 | ; | |
4750 | ||
6e5b5de8 AK |
4751 | (define_insn "*floatunsdidf2_z13" |
4752 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
4753 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
4754 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4755 | "@ | |
4756 | cdlgbr\t%0,0,%1,0 | |
4757 | wcdlgb\t%v0,%v1,0,0" | |
4758 | [(set_attr "op_type" "RRE,VRR") | |
4759 | (set_attr "type" "itofdf")]) | |
4760 | ||
65b1d8ea AK |
4761 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
4762 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
4763 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
4764 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4765 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4766 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
4767 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
4768 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
4769 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
4770 | (set_attr "type" "itof<FP:mode>")]) |
4771 | ||
4772 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
4773 | [(set (match_operand:FP 0 "register_operand" "") | |
4774 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
4775 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 4776 | |
9db1d521 HP |
4777 | ; |
4778 | ; truncdfsf2 instruction pattern(s). | |
4779 | ; | |
4780 | ||
142cd70f | 4781 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
4782 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
4783 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 4784 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4785 | "@ |
4786 | ledbr\t%0,%1 | |
4787 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
4788 | ; According to BFP rounding mode | |
4789 | [(set_attr "op_type" "RRE,VRR") | |
4790 | (set_attr "type" "ftruncdf") | |
4791 | (set_attr "cpu_facility" "*,vec")]) | |
9db1d521 | 4792 | |
f61a2c7d | 4793 | ; |
142cd70f | 4794 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4795 | ; |
4796 | ||
142cd70f AK |
4797 | ; ldxbr, lexbr |
4798 | (define_insn "trunctf<mode>2" | |
4799 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4800 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4801 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4802 | "TARGET_HARD_FLOAT" |
4803 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4804 | [(set_attr "length" "6") |
9381e3f1 | 4805 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4806 | |
609e7e80 AK |
4807 | ; |
4808 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4809 | ; | |
4810 | ||
4811 | (define_insn "trunctddd2" | |
4812 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
4813 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4814 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4815 | "TARGET_HARD_DFP" |
bf259a77 AK |
4816 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4817 | [(set_attr "length" "6") | |
9381e3f1 | 4818 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4819 | |
4820 | (define_insn "truncddsd2" | |
4821 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4822 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4823 | "TARGET_HARD_DFP" |
609e7e80 AK |
4824 | "ledtr\t%0,0,%1,0" |
4825 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4826 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4827 | |
feade5a8 AK |
4828 | (define_expand "trunctdsd2" |
4829 | [(parallel | |
4830 | [(set (match_dup 3) | |
4831 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
4832 | (clobber (match_scratch:TD 2 ""))]) | |
4833 | (set (match_operand:SD 0 "register_operand" "") | |
4834 | (float_truncate:SD (match_dup 3)))] | |
4835 | "TARGET_HARD_DFP" | |
4836 | { | |
4837 | operands[3] = gen_reg_rtx (DDmode); | |
4838 | }) | |
4839 | ||
9db1d521 | 4840 | ; |
142cd70f | 4841 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4842 | ; |
4843 | ||
6e5b5de8 AK |
4844 | (define_insn "*extendsfdf2_z13" |
4845 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
4846 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
4847 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4848 | "@ | |
4849 | ldebr\t%0,%1 | |
4850 | ldeb\t%0,%1 | |
4851 | wldeb\t%v0,%v1" | |
4852 | [(set_attr "op_type" "RRE,RXE,VRR") | |
4853 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
4854 | ||
142cd70f | 4855 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
4856 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
4857 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
4858 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
4859 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
4860 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
4861 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 4862 | "@ |
142cd70f AK |
4863 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4864 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
4865 | [(set_attr "op_type" "RRE,RXE") |
4866 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
4867 | ||
4868 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
4869 | [(set (match_operand:BFP 0 "register_operand" "") | |
4870 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
4871 | "TARGET_HARD_FLOAT | |
4872 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 4873 | |
609e7e80 AK |
4874 | ; |
4875 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4876 | ; | |
4877 | ||
4878 | (define_insn "extendddtd2" | |
4879 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4880 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4881 | "TARGET_HARD_DFP" |
609e7e80 AK |
4882 | "lxdtr\t%0,%1,0" |
4883 | [(set_attr "op_type" "RRF") | |
4884 | (set_attr "type" "fsimptf")]) | |
4885 | ||
4886 | (define_insn "extendsddd2" | |
4887 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4888 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4889 | "TARGET_HARD_DFP" |
609e7e80 AK |
4890 | "ldetr\t%0,%1,0" |
4891 | [(set_attr "op_type" "RRF") | |
4892 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4893 | |
feade5a8 AK |
4894 | (define_expand "extendsdtd2" |
4895 | [(set (match_dup 2) | |
4896 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
4897 | (set (match_operand:TD 0 "register_operand" "") | |
4898 | (float_extend:TD (match_dup 2)))] | |
4899 | "TARGET_HARD_DFP" | |
4900 | { | |
4901 | operands[2] = gen_reg_rtx (DDmode); | |
4902 | }) | |
4903 | ||
d12a76f3 AK |
4904 | ; Binary Floating Point - load fp integer |
4905 | ||
4906 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
4907 | ; For all of them the inexact exceptions are suppressed. | |
4908 | ||
4909 | ; fiebra, fidbra, fixbra | |
4910 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
4911 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4912 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4913 | FPINT))] | |
4914 | "TARGET_Z196" | |
4915 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4916 | [(set_attr "op_type" "RRF") | |
4917 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4918 | ||
4919 | ; rint is supposed to raise an inexact exception so we can use the | |
4920 | ; older instructions. | |
4921 | ||
4922 | ; fiebr, fidbr, fixbr | |
4923 | (define_insn "rint<BFP:mode>2" | |
4924 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4925 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4926 | UNSPEC_FPINT_RINT))] | |
4927 | "" | |
4928 | "fi<BFP:xde>br\t%0,0,%1" | |
4929 | [(set_attr "op_type" "RRF") | |
4930 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4931 | ||
4932 | ||
4933 | ; Decimal Floating Point - load fp integer | |
4934 | ||
4935 | ; fidtr, fixtr | |
4936 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
4937 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4938 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4939 | FPINT))] | |
4940 | "TARGET_HARD_DFP" | |
4941 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4942 | [(set_attr "op_type" "RRF") | |
4943 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4944 | ||
4945 | ; fidtr, fixtr | |
4946 | (define_insn "rint<DFP:mode>2" | |
4947 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4948 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4949 | UNSPEC_FPINT_RINT))] | |
4950 | "TARGET_HARD_DFP" | |
4951 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
4952 | [(set_attr "op_type" "RRF") | |
4953 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4954 | ||
4955 | ; | |
35dd9a0e AK |
4956 | ; Binary <-> Decimal floating point trunc patterns |
4957 | ; | |
4958 | ||
4959 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4960 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4961 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 4962 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4963 | (clobber (reg:CC CC_REGNUM)) |
4964 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 4965 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4966 | "pfpo") |
4967 | ||
4968 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4969 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 4970 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 4971 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4972 | (clobber (reg:CC CC_REGNUM)) |
4973 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 4974 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4975 | "pfpo") |
4976 | ||
4977 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 4978 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
4979 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
4980 | (parallel | |
4981 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4982 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 4983 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4984 | (clobber (reg:CC CC_REGNUM)) |
4985 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
4986 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
4987 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4988 | "TARGET_HARD_DFP |
35dd9a0e AK |
4989 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4990 | { | |
4991 | HOST_WIDE_INT flags; | |
4992 | ||
4993 | flags = (PFPO_CONVERT | | |
4994 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4995 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4996 | ||
4997 | operands[2] = GEN_INT (flags); | |
4998 | }) | |
4999 | ||
5000 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5001 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5002 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5003 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5004 | (parallel | |
2cf4c39e | 5005 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5006 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5007 | (clobber (reg:CC CC_REGNUM)) |
5008 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5009 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5010 | "TARGET_HARD_DFP |
35dd9a0e AK |
5011 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5012 | { | |
5013 | HOST_WIDE_INT flags; | |
5014 | ||
5015 | flags = (PFPO_CONVERT | | |
5016 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5017 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5018 | ||
5019 | operands[2] = GEN_INT (flags); | |
5020 | }) | |
5021 | ||
5022 | ; | |
5023 | ; Binary <-> Decimal floating point extend patterns | |
5024 | ; | |
5025 | ||
5026 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5027 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5028 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5029 | (clobber (reg:CC CC_REGNUM)) |
5030 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5031 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5032 | "pfpo") |
5033 | ||
5034 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5035 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5036 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5037 | (clobber (reg:CC CC_REGNUM)) |
5038 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5039 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5040 | "pfpo") |
5041 | ||
5042 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5043 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5044 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5045 | (parallel | |
5046 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5047 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5048 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5049 | (clobber (reg:CC CC_REGNUM)) |
5050 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5051 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5052 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5053 | "TARGET_HARD_DFP |
35dd9a0e AK |
5054 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5055 | { | |
5056 | HOST_WIDE_INT flags; | |
5057 | ||
5058 | flags = (PFPO_CONVERT | | |
5059 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5060 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5061 | ||
5062 | operands[2] = GEN_INT (flags); | |
5063 | }) | |
5064 | ||
5065 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5066 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5067 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5068 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5069 | (parallel | |
2cf4c39e | 5070 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5071 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5072 | (clobber (reg:CC CC_REGNUM)) |
5073 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5074 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5075 | "TARGET_HARD_DFP |
35dd9a0e AK |
5076 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5077 | { | |
5078 | HOST_WIDE_INT flags; | |
5079 | ||
5080 | flags = (PFPO_CONVERT | | |
5081 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5082 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5083 | ||
5084 | operands[2] = GEN_INT (flags); | |
5085 | }) | |
5086 | ||
5087 | ||
9db1d521 | 5088 | ;; |
fae778eb | 5089 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5090 | ;; |
fae778eb | 5091 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5092 | ; because of unpredictable Bits in Register for Halfword and Byte |
5093 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5094 | ||
07893d4f UW |
5095 | ;; |
5096 | ;;- Add instructions. | |
5097 | ;; | |
5098 | ||
1c7b1b7e UW |
5099 | ; |
5100 | ; addti3 instruction pattern(s). | |
5101 | ; | |
5102 | ||
085261c8 AK |
5103 | (define_expand "addti3" |
5104 | [(parallel | |
5105 | [(set (match_operand:TI 0 "register_operand" "") | |
5106 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5107 | (match_operand:TI 2 "general_operand" "") ) ) | |
5108 | (clobber (reg:CC CC_REGNUM))])] | |
5109 | "TARGET_ZARCH" | |
5110 | { | |
5111 | /* For z13 we have vaq which doesn't set CC. */ | |
5112 | if (TARGET_VX) | |
5113 | { | |
5114 | emit_insn (gen_rtx_SET (operands[0], | |
5115 | gen_rtx_PLUS (TImode, | |
5116 | copy_to_mode_reg (TImode, operands[1]), | |
5117 | copy_to_mode_reg (TImode, operands[2])))); | |
5118 | DONE; | |
5119 | } | |
5120 | }) | |
5121 | ||
5122 | (define_insn_and_split "*addti3" | |
5123 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5124 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5125 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5126 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5127 | "TARGET_ZARCH" |
1c7b1b7e UW |
5128 | "#" |
5129 | "&& reload_completed" | |
5130 | [(parallel | |
ae156f85 | 5131 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5132 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5133 | (match_dup 7))) | |
5134 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5135 | (parallel | |
a94a76a7 UW |
5136 | [(set (match_dup 3) (plus:DI |
5137 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5138 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5139 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5140 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5141 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5142 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5143 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5144 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5145 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5146 | [(set_attr "op_type" "*") | |
5147 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5148 | |
07893d4f UW |
5149 | ; |
5150 | ; adddi3 instruction pattern(s). | |
5151 | ; | |
5152 | ||
3298c037 AK |
5153 | (define_expand "adddi3" |
5154 | [(parallel | |
963fc8d0 | 5155 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5156 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5157 | (match_operand:DI 2 "general_operand" ""))) | |
5158 | (clobber (reg:CC CC_REGNUM))])] | |
5159 | "" | |
5160 | "") | |
5161 | ||
07893d4f UW |
5162 | (define_insn "*adddi3_sign" |
5163 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 5164 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5165 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5166 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5167 | "TARGET_ZARCH" |
07893d4f | 5168 | "@ |
d40c829f UW |
5169 | agfr\t%0,%2 |
5170 | agf\t%0,%2" | |
65b1d8ea AK |
5171 | [(set_attr "op_type" "RRE,RXY") |
5172 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5173 | |
5174 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5175 | [(set (reg CC_REGNUM) |
fb492564 | 5176 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5177 | (match_operand:DI 1 "register_operand" "0,0")) |
5178 | (const_int 0))) | |
5179 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5180 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5181 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5182 | "@ |
d40c829f UW |
5183 | algfr\t%0,%2 |
5184 | algf\t%0,%2" | |
9381e3f1 WG |
5185 | [(set_attr "op_type" "RRE,RXY") |
5186 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5187 | |
5188 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5189 | [(set (reg CC_REGNUM) |
fb492564 | 5190 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5191 | (match_operand:DI 1 "register_operand" "0,0")) |
5192 | (const_int 0))) | |
5193 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5194 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5195 | "@ |
d40c829f UW |
5196 | algfr\t%0,%2 |
5197 | algf\t%0,%2" | |
9381e3f1 WG |
5198 | [(set_attr "op_type" "RRE,RXY") |
5199 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5200 | |
5201 | (define_insn "*adddi3_zero" | |
5202 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 5203 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5204 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5205 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5206 | "TARGET_ZARCH" |
07893d4f | 5207 | "@ |
d40c829f UW |
5208 | algfr\t%0,%2 |
5209 | algf\t%0,%2" | |
9381e3f1 WG |
5210 | [(set_attr "op_type" "RRE,RXY") |
5211 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5212 | |
e69166de | 5213 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5214 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5215 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5216 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5217 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5218 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5219 | "#" |
5220 | "&& reload_completed" | |
5221 | [(parallel | |
ae156f85 | 5222 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5223 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5224 | (match_dup 7))) | |
5225 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5226 | (parallel | |
a94a76a7 UW |
5227 | [(set (match_dup 3) (plus:SI |
5228 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5229 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5230 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5231 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5232 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5233 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5234 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5235 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5236 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5237 | |
07893d4f | 5238 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 5239 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 5240 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 5241 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5242 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5243 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5244 | "#" |
5245 | "&& reload_completed" | |
5246 | [(parallel | |
5247 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5248 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5249 | (parallel |
ae156f85 | 5250 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
5251 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5252 | (match_dup 7))) | |
5253 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5254 | (set (pc) | |
ae156f85 | 5255 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5256 | (pc) |
5257 | (label_ref (match_dup 9)))) | |
5258 | (parallel | |
5259 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 5260 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5261 | (match_dup 9)] |
97c6f7ad UW |
5262 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5263 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5264 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5265 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5266 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5267 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5268 | operands[9] = gen_label_rtx ();") |
9db1d521 | 5269 | |
3298c037 AK |
5270 | ; |
5271 | ; addsi3 instruction pattern(s). | |
5272 | ; | |
5273 | ||
5274 | (define_expand "addsi3" | |
07893d4f | 5275 | [(parallel |
963fc8d0 | 5276 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5277 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5278 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5279 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5280 | "" |
07893d4f | 5281 | "") |
9db1d521 | 5282 | |
3298c037 AK |
5283 | (define_insn "*addsi3_sign" |
5284 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5285 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5286 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5287 | (clobber (reg:CC CC_REGNUM))] | |
5288 | "" | |
5289 | "@ | |
5290 | ah\t%0,%2 | |
5291 | ahy\t%0,%2" | |
65b1d8ea AK |
5292 | [(set_attr "op_type" "RX,RXY") |
5293 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5294 | |
9db1d521 | 5295 | ; |
3298c037 | 5296 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5297 | ; |
9db1d521 | 5298 | |
65b1d8ea | 5299 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5300 | (define_insn "*add<mode>3" |
65b1d8ea AK |
5301 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
5302 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
5303 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
5304 | (clobber (reg:CC CC_REGNUM))] |
5305 | "" | |
ec24698e | 5306 | "@ |
3298c037 | 5307 | a<g>r\t%0,%2 |
65b1d8ea | 5308 | a<g>rk\t%0,%1,%2 |
3298c037 | 5309 | a<g>hi\t%0,%h2 |
65b1d8ea | 5310 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5311 | al<g>fi\t%0,%2 |
5312 | sl<g>fi\t%0,%n2 | |
5313 | a<g>\t%0,%2 | |
963fc8d0 AK |
5314 | a<y>\t%0,%2 |
5315 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5316 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
5317 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
5318 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
5319 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5320 | |
65b1d8ea | 5321 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5322 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5323 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5324 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5325 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5326 | (match_dup 1))) |
65b1d8ea | 5327 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5328 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5329 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5330 | "@ |
3298c037 | 5331 | al<g>r\t%0,%2 |
65b1d8ea | 5332 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5333 | al<g>fi\t%0,%2 |
5334 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5335 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5336 | al<g>\t%0,%2 |
963fc8d0 AK |
5337 | al<y>\t%0,%2 |
5338 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5339 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5340 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5341 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
5342 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5343 | |
65b1d8ea | 5344 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5345 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5346 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5347 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5348 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5349 | (match_dup 1))) |
65b1d8ea | 5350 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5351 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5352 | "@ |
3298c037 | 5353 | al<g>r\t%0,%2 |
65b1d8ea | 5354 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5355 | al<g>\t%0,%2 |
5356 | al<y>\t%0,%2" | |
65b1d8ea AK |
5357 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5358 | (set_attr "cpu_facility" "*,z196,*,*") | |
5359 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5360 | |
65b1d8ea | 5361 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5362 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5363 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5364 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
5365 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 5366 | (match_dup 2))) |
65b1d8ea | 5367 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 5368 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5369 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5370 | "@ |
3298c037 | 5371 | al<g>r\t%0,%2 |
65b1d8ea | 5372 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5373 | al<g>fi\t%0,%2 |
5374 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5375 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5376 | al<g>\t%0,%2 |
963fc8d0 AK |
5377 | al<y>\t%0,%2 |
5378 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5379 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5380 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5381 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
5382 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5383 | |
65b1d8ea | 5384 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5385 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5386 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5387 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5388 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5389 | (match_dup 2))) |
65b1d8ea | 5390 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5391 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5392 | "@ |
3298c037 | 5393 | al<g>r\t%0,%2 |
65b1d8ea | 5394 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5395 | al<g>\t%0,%2 |
5396 | al<y>\t%0,%2" | |
65b1d8ea AK |
5397 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5398 | (set_attr "cpu_facility" "*,z196,*,*") | |
5399 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5400 | |
65b1d8ea | 5401 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5402 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5403 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5404 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
5405 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 5406 | (const_int 0))) |
65b1d8ea | 5407 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 5408 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5409 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5410 | "@ |
3298c037 | 5411 | al<g>r\t%0,%2 |
65b1d8ea | 5412 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5413 | al<g>fi\t%0,%2 |
5414 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5415 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5416 | al<g>\t%0,%2 |
963fc8d0 AK |
5417 | al<y>\t%0,%2 |
5418 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5419 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5420 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5421 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
5422 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5423 | |
65b1d8ea | 5424 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5425 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5426 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5427 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5428 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5429 | (const_int 0))) |
65b1d8ea | 5430 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5431 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5432 | "@ |
3298c037 | 5433 | al<g>r\t%0,%2 |
65b1d8ea | 5434 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5435 | al<g>\t%0,%2 |
5436 | al<y>\t%0,%2" | |
65b1d8ea AK |
5437 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5438 | (set_attr "cpu_facility" "*,z196,*,*") | |
5439 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5440 | |
65b1d8ea | 5441 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5442 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5443 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5444 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5445 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5446 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5447 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5448 | "@ |
3298c037 | 5449 | al<g>r\t%0,%2 |
65b1d8ea | 5450 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5451 | al<g>\t%0,%2 |
5452 | al<y>\t%0,%2" | |
65b1d8ea AK |
5453 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5454 | (set_attr "cpu_facility" "*,z196,*,*") | |
5455 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5456 | |
963fc8d0 | 5457 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5458 | (define_insn "*add<mode>3_imm_cc" |
5459 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
5460 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
5461 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 5462 | (const_int 0))) |
65b1d8ea | 5463 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
5464 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5465 | "s390_match_ccmode (insn, CCAmode) | |
5466 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5467 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5468 | /* Avoid INT32_MIN on 32 bit. */ | |
5469 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5470 | "@ |
3298c037 | 5471 | a<g>hi\t%0,%h2 |
65b1d8ea | 5472 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5473 | a<g>fi\t%0,%2 |
5474 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5475 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5476 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5477 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5478 | |
9db1d521 | 5479 | ; |
609e7e80 | 5480 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5481 | ; |
5482 | ||
609e7e80 | 5483 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5484 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5485 | (define_insn "add<mode>3" |
62d3f261 AK |
5486 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
5487 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") | |
5488 | (match_operand:FP 2 "general_operand" "f,f,R,v"))) | |
ae156f85 | 5489 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5490 | "TARGET_HARD_FLOAT" |
9db1d521 | 5491 | "@ |
62d3f261 AK |
5492 | a<xde>tr\t%0,%1,%2 |
5493 | a<xde>br\t%0,%2 | |
6e5b5de8 AK |
5494 | a<xde>b\t%0,%2 |
5495 | wfadb\t%v0,%v1,%v2" | |
62d3f261 | 5496 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 5497 | (set_attr "type" "fsimp<mode>") |
62d3f261 AK |
5498 | (set_attr "cpu_facility" "*,*,*,vec") |
5499 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) | |
9db1d521 | 5500 | |
609e7e80 | 5501 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5502 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5503 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5504 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5505 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5506 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5507 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5508 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5509 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5510 | "@ |
62d3f261 AK |
5511 | a<xde>tr\t%0,%1,%2 |
5512 | a<xde>br\t%0,%2 | |
f61a2c7d | 5513 | a<xde>b\t%0,%2" |
62d3f261 AK |
5514 | [(set_attr "op_type" "RRF,RRE,RXE") |
5515 | (set_attr "type" "fsimp<mode>") | |
5516 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5517 | |
609e7e80 | 5518 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5519 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5520 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5521 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5522 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5523 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5524 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5525 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5526 | "@ |
62d3f261 AK |
5527 | a<xde>tr\t%0,%1,%2 |
5528 | a<xde>br\t%0,%2 | |
f61a2c7d | 5529 | a<xde>b\t%0,%2" |
62d3f261 AK |
5530 | [(set_attr "op_type" "RRF,RRE,RXE") |
5531 | (set_attr "type" "fsimp<mode>") | |
5532 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5533 | |
72a4ddf2 AK |
5534 | ; |
5535 | ; Pointer add instruction patterns | |
5536 | ; | |
5537 | ||
5538 | ; This will match "*la_64" | |
5539 | (define_expand "addptrdi3" | |
5540 | [(set (match_operand:DI 0 "register_operand" "") | |
5541 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5542 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5543 | "TARGET_64BIT" | |
5544 | { | |
72a4ddf2 AK |
5545 | if (GET_CODE (operands[2]) == CONST_INT) |
5546 | { | |
357ddc7d TV |
5547 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5548 | ||
72a4ddf2 AK |
5549 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5550 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5551 | { | |
5552 | operands[2] = force_const_mem (DImode, operands[2]); | |
5553 | operands[2] = force_reg (DImode, operands[2]); | |
5554 | } | |
5555 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5556 | operands[2] = force_reg (DImode, operands[2]); | |
5557 | } | |
5558 | }) | |
5559 | ||
5560 | ; For 31 bit we have to prevent the generated pattern from matching | |
5561 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5562 | ; match "force_la_31". | |
5563 | (define_expand "addptrsi3" | |
5564 | [(parallel | |
5565 | [(set (match_operand:SI 0 "register_operand" "") | |
5566 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5567 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5568 | (use (const_int 0))])] | |
5569 | "!TARGET_64BIT" | |
5570 | { | |
72a4ddf2 AK |
5571 | if (GET_CODE (operands[2]) == CONST_INT) |
5572 | { | |
357ddc7d TV |
5573 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5574 | ||
72a4ddf2 AK |
5575 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5576 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5577 | { | |
5578 | operands[2] = force_const_mem (SImode, operands[2]); | |
5579 | operands[2] = force_reg (SImode, operands[2]); | |
5580 | } | |
5581 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5582 | operands[2] = force_reg (SImode, operands[2]); | |
5583 | } | |
5584 | }) | |
9db1d521 HP |
5585 | |
5586 | ;; | |
5587 | ;;- Subtract instructions. | |
5588 | ;; | |
5589 | ||
1c7b1b7e UW |
5590 | ; |
5591 | ; subti3 instruction pattern(s). | |
5592 | ; | |
5593 | ||
085261c8 AK |
5594 | (define_expand "subti3" |
5595 | [(parallel | |
5596 | [(set (match_operand:TI 0 "register_operand" "") | |
5597 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5598 | (match_operand:TI 2 "general_operand" "") ) ) | |
5599 | (clobber (reg:CC CC_REGNUM))])] | |
5600 | "TARGET_ZARCH" | |
5601 | { | |
5602 | /* For z13 we have vaq which doesn't set CC. */ | |
5603 | if (TARGET_VX) | |
5604 | { | |
5605 | emit_insn (gen_rtx_SET (operands[0], | |
5606 | gen_rtx_MINUS (TImode, | |
5607 | operands[1], | |
5608 | copy_to_mode_reg (TImode, operands[2])))); | |
5609 | DONE; | |
5610 | } | |
5611 | }) | |
5612 | ||
5613 | (define_insn_and_split "*subti3" | |
5614 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
5615 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
5616 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 5617 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5618 | "TARGET_ZARCH" |
1c7b1b7e UW |
5619 | "#" |
5620 | "&& reload_completed" | |
5621 | [(parallel | |
ae156f85 | 5622 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
5623 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
5624 | (match_dup 7))) | |
5625 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
5626 | (parallel | |
5627 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5628 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5629 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
5630 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5631 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5632 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5633 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5634 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5635 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5636 | [(set_attr "op_type" "*") | |
5637 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5638 | |
9db1d521 HP |
5639 | ; |
5640 | ; subdi3 instruction pattern(s). | |
5641 | ; | |
5642 | ||
3298c037 AK |
5643 | (define_expand "subdi3" |
5644 | [(parallel | |
5645 | [(set (match_operand:DI 0 "register_operand" "") | |
5646 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
5647 | (match_operand:DI 2 "general_operand" ""))) | |
5648 | (clobber (reg:CC CC_REGNUM))])] | |
5649 | "" | |
5650 | "") | |
5651 | ||
07893d4f UW |
5652 | (define_insn "*subdi3_sign" |
5653 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5654 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5655 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5656 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5657 | "TARGET_ZARCH" |
07893d4f | 5658 | "@ |
d40c829f UW |
5659 | sgfr\t%0,%2 |
5660 | sgf\t%0,%2" | |
9381e3f1 | 5661 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
5662 | (set_attr "z10prop" "z10_c,*") |
5663 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
5664 | |
5665 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 5666 | [(set (reg CC_REGNUM) |
07893d4f | 5667 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5668 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5669 | (const_int 0))) |
5670 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5671 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 5672 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5673 | "@ |
d40c829f UW |
5674 | slgfr\t%0,%2 |
5675 | slgf\t%0,%2" | |
9381e3f1 WG |
5676 | [(set_attr "op_type" "RRE,RXY") |
5677 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5678 | |
5679 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 5680 | [(set (reg CC_REGNUM) |
07893d4f | 5681 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5682 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5683 | (const_int 0))) |
5684 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5685 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5686 | "@ |
d40c829f UW |
5687 | slgfr\t%0,%2 |
5688 | slgf\t%0,%2" | |
9381e3f1 WG |
5689 | [(set_attr "op_type" "RRE,RXY") |
5690 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5691 | |
5692 | (define_insn "*subdi3_zero" | |
5693 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5694 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5695 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5696 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5697 | "TARGET_ZARCH" |
07893d4f | 5698 | "@ |
d40c829f UW |
5699 | slgfr\t%0,%2 |
5700 | slgf\t%0,%2" | |
9381e3f1 WG |
5701 | [(set_attr "op_type" "RRE,RXY") |
5702 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 5703 | |
e69166de UW |
5704 | (define_insn_and_split "*subdi3_31z" |
5705 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5706 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
5707 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5708 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5709 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5710 | "#" |
5711 | "&& reload_completed" | |
5712 | [(parallel | |
ae156f85 | 5713 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
5714 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5715 | (match_dup 7))) | |
5716 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5717 | (parallel | |
5718 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5719 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5720 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
5721 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5722 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5723 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5724 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5725 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5726 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5727 | |
07893d4f UW |
5728 | (define_insn_and_split "*subdi3_31" |
5729 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5730 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 5731 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5732 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5733 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5734 | "#" |
5735 | "&& reload_completed" | |
5736 | [(parallel | |
5737 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5738 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5739 | (parallel |
ae156f85 | 5740 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
5741 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5742 | (match_dup 7))) | |
5743 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5744 | (set (pc) | |
ae156f85 | 5745 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5746 | (pc) |
5747 | (label_ref (match_dup 9)))) | |
5748 | (parallel | |
5749 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 5750 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5751 | (match_dup 9)] |
97c6f7ad UW |
5752 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5753 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5754 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5755 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5756 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5757 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5758 | operands[9] = gen_label_rtx ();") |
07893d4f | 5759 | |
3298c037 AK |
5760 | ; |
5761 | ; subsi3 instruction pattern(s). | |
5762 | ; | |
5763 | ||
5764 | (define_expand "subsi3" | |
07893d4f | 5765 | [(parallel |
3298c037 AK |
5766 | [(set (match_operand:SI 0 "register_operand" "") |
5767 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
5768 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5769 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5770 | "" |
07893d4f | 5771 | "") |
9db1d521 | 5772 | |
3298c037 AK |
5773 | (define_insn "*subsi3_sign" |
5774 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5775 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
5776 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
5777 | (clobber (reg:CC CC_REGNUM))] | |
5778 | "" | |
5779 | "@ | |
5780 | sh\t%0,%2 | |
5781 | shy\t%0,%2" | |
65b1d8ea AK |
5782 | [(set_attr "op_type" "RX,RXY") |
5783 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5784 | |
9db1d521 | 5785 | ; |
3298c037 | 5786 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
5787 | ; |
5788 | ||
65b1d8ea | 5789 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 5790 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
5791 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
5792 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
5793 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
5794 | (clobber (reg:CC CC_REGNUM))] |
5795 | "" | |
5796 | "@ | |
5797 | s<g>r\t%0,%2 | |
65b1d8ea | 5798 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
5799 | s<g>\t%0,%2 |
5800 | s<y>\t%0,%2" | |
65b1d8ea AK |
5801 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5802 | (set_attr "cpu_facility" "*,z196,*,*") | |
5803 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 5804 | |
65b1d8ea | 5805 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5806 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 5807 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5808 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5809 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5810 | (match_dup 1))) |
65b1d8ea | 5811 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5812 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5813 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5814 | "@ |
3298c037 | 5815 | sl<g>r\t%0,%2 |
65b1d8ea | 5816 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5817 | sl<g>\t%0,%2 |
5818 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5819 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5820 | (set_attr "cpu_facility" "*,z196,*,*") | |
5821 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5822 | |
65b1d8ea | 5823 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5824 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 5825 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5826 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5827 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5828 | (match_dup 1))) |
65b1d8ea | 5829 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5830 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5831 | "@ |
3298c037 | 5832 | sl<g>r\t%0,%2 |
65b1d8ea | 5833 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5834 | sl<g>\t%0,%2 |
5835 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5836 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5837 | (set_attr "cpu_facility" "*,z196,*,*") | |
5838 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5839 | |
65b1d8ea | 5840 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5841 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5842 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5843 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5844 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5845 | (const_int 0))) |
65b1d8ea | 5846 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5847 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5848 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5849 | "@ |
3298c037 | 5850 | sl<g>r\t%0,%2 |
65b1d8ea | 5851 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5852 | sl<g>\t%0,%2 |
5853 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5854 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5855 | (set_attr "cpu_facility" "*,z196,*,*") | |
5856 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5857 | |
65b1d8ea | 5858 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5859 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5860 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5861 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5862 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5863 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5864 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5865 | "s390_match_ccmode (insn, CCL3mode)" |
5866 | "@ | |
3298c037 | 5867 | sl<g>r\t%0,%2 |
65b1d8ea | 5868 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5869 | sl<g>\t%0,%2 |
5870 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5871 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5872 | (set_attr "cpu_facility" "*,z196,*,*") | |
5873 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5874 | |
65b1d8ea | 5875 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5876 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5877 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5878 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5879 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5880 | (const_int 0))) |
65b1d8ea | 5881 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5882 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5883 | "@ |
3298c037 | 5884 | sl<g>r\t%0,%2 |
65b1d8ea | 5885 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5886 | sl<g>\t%0,%2 |
5887 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5888 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5889 | (set_attr "cpu_facility" "*,z196,*,*") | |
5890 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5891 | |
9db1d521 | 5892 | |
65b1d8ea | 5893 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5894 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5895 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5896 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5897 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5898 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5899 | "s390_match_ccmode (insn, CCL3mode)" |
5900 | "@ | |
3298c037 | 5901 | sl<g>r\t%0,%2 |
65b1d8ea | 5902 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5903 | sl<g>\t%0,%2 |
5904 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5905 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5906 | (set_attr "cpu_facility" "*,z196,*,*") | |
5907 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5908 | |
9db1d521 HP |
5909 | |
5910 | ; | |
609e7e80 | 5911 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5912 | ; |
5913 | ||
d46f24b6 | 5914 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5915 | (define_insn "sub<mode>3" |
62d3f261 AK |
5916 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
5917 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v") | |
5918 | (match_operand:FP 2 "general_operand" "f,f,R,v"))) | |
ae156f85 | 5919 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5920 | "TARGET_HARD_FLOAT" |
9db1d521 | 5921 | "@ |
62d3f261 AK |
5922 | s<xde>tr\t%0,%1,%2 |
5923 | s<xde>br\t%0,%2 | |
6e5b5de8 AK |
5924 | s<xde>b\t%0,%2 |
5925 | wfsdb\t%v0,%v1,%v2" | |
62d3f261 | 5926 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 5927 | (set_attr "type" "fsimp<mode>") |
62d3f261 AK |
5928 | (set_attr "cpu_facility" "*,*,*,vec") |
5929 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) | |
9db1d521 | 5930 | |
d46f24b6 | 5931 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5932 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5933 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5934 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
5935 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5936 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5937 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5938 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5939 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5940 | "@ |
62d3f261 AK |
5941 | s<xde>tr\t%0,%1,%2 |
5942 | s<xde>br\t%0,%2 | |
f61a2c7d | 5943 | s<xde>b\t%0,%2" |
62d3f261 AK |
5944 | [(set_attr "op_type" "RRF,RRE,RXE") |
5945 | (set_attr "type" "fsimp<mode>") | |
5946 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5947 | |
d46f24b6 | 5948 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5949 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5950 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5951 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
5952 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5953 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5954 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5955 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5956 | "@ |
62d3f261 AK |
5957 | s<xde>tr\t%0,%1,%2 |
5958 | s<xde>br\t%0,%2 | |
f61a2c7d | 5959 | s<xde>b\t%0,%2" |
62d3f261 AK |
5960 | [(set_attr "op_type" "RRF,RRE,RXE") |
5961 | (set_attr "type" "fsimp<mode>") | |
5962 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5963 | |
9db1d521 | 5964 | |
e69166de UW |
5965 | ;; |
5966 | ;;- Conditional add/subtract instructions. | |
5967 | ;; | |
5968 | ||
5969 | ; | |
9a91a21f | 5970 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
5971 | ; |
5972 | ||
a996720c UW |
5973 | ; the following 4 patterns are used when the result of an add with |
5974 | ; carry is checked for an overflow condition | |
5975 | ||
5976 | ; op1 + op2 + c < op1 | |
5977 | ||
5978 | ; alcr, alc, alcgr, alcg | |
5979 | (define_insn "*add<mode>3_alc_carry1_cc" | |
5980 | [(set (reg CC_REGNUM) | |
5981 | (compare | |
5982 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5983 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5984 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5985 | (match_dup 1))) |
5986 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5987 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5988 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5989 | "@ | |
5990 | alc<g>r\t%0,%2 | |
5991 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5992 | [(set_attr "op_type" "RRE,RXY") |
5993 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5994 | |
5995 | ; alcr, alc, alcgr, alcg | |
5996 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
5997 | [(set (reg CC_REGNUM) | |
5998 | (compare | |
5999 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6000 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6001 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
6002 | (match_dup 1))) |
6003 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6004 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6005 | "@ | |
6006 | alc<g>r\t%0,%2 | |
6007 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6008 | [(set_attr "op_type" "RRE,RXY") |
6009 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6010 | |
6011 | ; op1 + op2 + c < op2 | |
6012 | ||
6013 | ; alcr, alc, alcgr, alcg | |
6014 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6015 | [(set (reg CC_REGNUM) | |
6016 | (compare | |
6017 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6018 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6019 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
6020 | (match_dup 2))) |
6021 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6022 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6023 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6024 | "@ | |
6025 | alc<g>r\t%0,%2 | |
6026 | alc<g>\t%0,%2" | |
6027 | [(set_attr "op_type" "RRE,RXY")]) | |
6028 | ||
6029 | ; alcr, alc, alcgr, alcg | |
6030 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6031 | [(set (reg CC_REGNUM) | |
6032 | (compare | |
6033 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6034 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6035 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
6036 | (match_dup 2))) |
6037 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6038 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6039 | "@ | |
6040 | alc<g>r\t%0,%2 | |
6041 | alc<g>\t%0,%2" | |
6042 | [(set_attr "op_type" "RRE,RXY")]) | |
6043 | ||
43a09b63 | 6044 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6045 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6046 | [(set (reg CC_REGNUM) |
e69166de | 6047 | (compare |
a94a76a7 UW |
6048 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6049 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6050 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 6051 | (const_int 0))) |
9a91a21f | 6052 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6053 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 6054 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6055 | "@ |
9a91a21f AS |
6056 | alc<g>r\t%0,%2 |
6057 | alc<g>\t%0,%2" | |
e69166de UW |
6058 | [(set_attr "op_type" "RRE,RXY")]) |
6059 | ||
43a09b63 | 6060 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6061 | (define_insn "*add<mode>3_alc" |
6062 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6063 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6064 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6065 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 6066 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6067 | "TARGET_CPU_ZARCH" |
e69166de | 6068 | "@ |
9a91a21f AS |
6069 | alc<g>r\t%0,%2 |
6070 | alc<g>\t%0,%2" | |
e69166de UW |
6071 | [(set_attr "op_type" "RRE,RXY")]) |
6072 | ||
43a09b63 | 6073 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6074 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6075 | [(set (reg CC_REGNUM) |
e69166de | 6076 | (compare |
9a91a21f | 6077 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 6078 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 6079 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6080 | (const_int 0))) |
9a91a21f AS |
6081 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6082 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 6083 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6084 | "@ |
9a91a21f AS |
6085 | slb<g>r\t%0,%2 |
6086 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6087 | [(set_attr "op_type" "RRE,RXY") |
6088 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6089 | |
43a09b63 | 6090 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6091 | (define_insn "*sub<mode>3_slb" |
6092 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6093 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 6094 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 6095 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6096 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6097 | "TARGET_CPU_ZARCH" |
e69166de | 6098 | "@ |
9a91a21f AS |
6099 | slb<g>r\t%0,%2 |
6100 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6101 | [(set_attr "op_type" "RRE,RXY") |
6102 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6103 | |
9a91a21f AS |
6104 | (define_expand "add<mode>cc" |
6105 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6106 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6107 | (match_operand:GPR 2 "register_operand" "") |
6108 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 6109 | "TARGET_CPU_ZARCH" |
9381e3f1 | 6110 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6111 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6112 | operands[0], operands[2], |
5d880bd2 UW |
6113 | operands[3])) FAIL; DONE;") |
6114 | ||
6115 | ; | |
6116 | ; scond instruction pattern(s). | |
6117 | ; | |
6118 | ||
9a91a21f AS |
6119 | (define_insn_and_split "*scond<mode>" |
6120 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6121 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6122 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6123 | "TARGET_CPU_ZARCH" |
6124 | "#" | |
6125 | "&& reload_completed" | |
6126 | [(set (match_dup 0) (const_int 0)) | |
6127 | (parallel | |
a94a76a7 UW |
6128 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6129 | (match_dup 0))) | |
ae156f85 | 6130 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6131 | "") |
5d880bd2 | 6132 | |
9a91a21f AS |
6133 | (define_insn_and_split "*scond<mode>_neg" |
6134 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6135 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6136 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6137 | "TARGET_CPU_ZARCH" |
6138 | "#" | |
6139 | "&& reload_completed" | |
6140 | [(set (match_dup 0) (const_int 0)) | |
6141 | (parallel | |
9a91a21f AS |
6142 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6143 | (match_dup 1))) | |
ae156f85 | 6144 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6145 | (parallel |
9a91a21f | 6146 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6147 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6148 | "") |
5d880bd2 | 6149 | |
5d880bd2 | 6150 | |
f90b7a5a | 6151 | (define_expand "cstore<mode>4" |
9a91a21f | 6152 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6153 | (match_operator:SI 1 "s390_scond_operator" |
6154 | [(match_operand:GPR 2 "register_operand" "") | |
6155 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 6156 | "TARGET_CPU_ZARCH" |
f90b7a5a | 6157 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6158 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6159 | ||
f90b7a5a | 6160 | (define_expand "cstorecc4" |
69950452 | 6161 | [(parallel |
f90b7a5a PB |
6162 | [(set (match_operand:SI 0 "register_operand" "") |
6163 | (match_operator:SI 1 "s390_eqne_operator" | |
6164 | [(match_operand:CCZ1 2 "register_operand") | |
6165 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
6166 | (clobber (reg:CC CC_REGNUM))])] |
6167 | "" | |
f90b7a5a PB |
6168 | "emit_insn (gen_sne (operands[0], operands[2])); |
6169 | if (GET_CODE (operands[1]) == EQ) | |
6170 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6171 | DONE;") | |
69950452 | 6172 | |
f90b7a5a | 6173 | (define_insn_and_split "sne" |
69950452 | 6174 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6175 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6176 | (const_int 0))) |
6177 | (clobber (reg:CC CC_REGNUM))] | |
6178 | "" | |
6179 | "#" | |
6180 | "reload_completed" | |
6181 | [(parallel | |
6182 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6183 | (clobber (reg:CC CC_REGNUM))])]) | |
6184 | ||
e69166de | 6185 | |
65b1d8ea AK |
6186 | ;; |
6187 | ;; - Conditional move instructions (introduced with z196) | |
6188 | ;; | |
6189 | ||
6190 | (define_expand "mov<mode>cc" | |
6191 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6192 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6193 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6194 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6195 | "TARGET_Z196" | |
7477de01 AK |
6196 | { |
6197 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6198 | if (!s390_comparison (operands[1], VOIDmode)) | |
6199 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6200 | XEXP (operands[1], 0), | |
6201 | XEXP (operands[1], 1)); | |
6202 | }) | |
65b1d8ea | 6203 | |
27037b5f | 6204 | ; locr, loc, stoc, locgr, locg, stocg |
65b1d8ea AK |
6205 | (define_insn_and_split "*mov<mode>cc" |
6206 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
6207 | (if_then_else:GPR | |
6208 | (match_operator 1 "s390_comparison" | |
6209 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5a3fe9b6 | 6210 | (match_operand 5 "const_int_operand" "")]) |
65b1d8ea AK |
6211 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") |
6212 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
6213 | "TARGET_Z196" | |
6214 | "@ | |
6215 | loc<g>r%C1\t%0,%3 | |
6216 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6217 | loc<g>%C1\t%0,%3 |
6218 | loc<g>%D1\t%0,%4 | |
6219 | stoc<g>%C1\t%3,%0 | |
6220 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
6221 | #" |
6222 | "&& reload_completed | |
6223 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
6224 | [(set (match_dup 0) | |
6225 | (if_then_else:GPR | |
6226 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6227 | (match_dup 3) | |
6228 | (match_dup 0))) | |
6229 | (set (match_dup 0) | |
6230 | (if_then_else:GPR | |
6231 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6232 | (match_dup 0) | |
6233 | (match_dup 4)))] | |
6234 | "" | |
6235 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
6236 | ||
9db1d521 HP |
6237 | ;; |
6238 | ;;- Multiply instructions. | |
6239 | ;; | |
6240 | ||
4023fb28 UW |
6241 | ; |
6242 | ; muldi3 instruction pattern(s). | |
6243 | ; | |
9db1d521 | 6244 | |
07893d4f UW |
6245 | (define_insn "*muldi3_sign" |
6246 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 6247 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 6248 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6249 | "TARGET_ZARCH" |
07893d4f | 6250 | "@ |
d40c829f UW |
6251 | msgfr\t%0,%2 |
6252 | msgf\t%0,%2" | |
963fc8d0 AK |
6253 | [(set_attr "op_type" "RRE,RXY") |
6254 | (set_attr "type" "imuldi")]) | |
07893d4f | 6255 | |
4023fb28 | 6256 | (define_insn "muldi3" |
963fc8d0 AK |
6257 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
6258 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
6259 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 6260 | "TARGET_ZARCH" |
9db1d521 | 6261 | "@ |
d40c829f UW |
6262 | msgr\t%0,%2 |
6263 | mghi\t%0,%h2 | |
963fc8d0 AK |
6264 | msg\t%0,%2 |
6265 | msgfi\t%0,%2" | |
6266 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
6267 | (set_attr "type" "imuldi") | |
6268 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 6269 | |
9db1d521 HP |
6270 | ; |
6271 | ; mulsi3 instruction pattern(s). | |
6272 | ; | |
6273 | ||
f1e77d83 | 6274 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6275 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6276 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6277 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6278 | "" |
963fc8d0 AK |
6279 | "@ |
6280 | mh\t%0,%2 | |
6281 | mhy\t%0,%2" | |
6282 | [(set_attr "op_type" "RX,RXY") | |
6283 | (set_attr "type" "imulhi") | |
6284 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6285 | |
9db1d521 | 6286 | (define_insn "mulsi3" |
963fc8d0 AK |
6287 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
6288 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6289 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
6290 | "" |
6291 | "@ | |
d40c829f UW |
6292 | msr\t%0,%2 |
6293 | mhi\t%0,%h2 | |
6294 | ms\t%0,%2 | |
963fc8d0 AK |
6295 | msy\t%0,%2 |
6296 | msfi\t%0,%2" | |
6297 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
6298 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
6299 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 6300 | |
4023fb28 UW |
6301 | ; |
6302 | ; mulsidi3 instruction pattern(s). | |
6303 | ; | |
6304 | ||
f1e77d83 | 6305 | (define_insn "mulsidi3" |
963fc8d0 | 6306 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6307 | (mult:DI (sign_extend:DI |
963fc8d0 | 6308 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6309 | (sign_extend:DI |
963fc8d0 | 6310 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6311 | "!TARGET_ZARCH" |
f1e77d83 UW |
6312 | "@ |
6313 | mr\t%0,%2 | |
963fc8d0 AK |
6314 | m\t%0,%2 |
6315 | mfy\t%0,%2" | |
6316 | [(set_attr "op_type" "RR,RX,RXY") | |
6317 | (set_attr "type" "imulsi") | |
6318 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6319 | |
f1e77d83 | 6320 | ; |
6e0d70c9 | 6321 | ; umul instruction pattern(s). |
f1e77d83 | 6322 | ; |
c7453384 | 6323 | |
6e0d70c9 AK |
6324 | ; mlr, ml, mlgr, mlg |
6325 | (define_insn "umul<dwh><mode>3" | |
6326 | [(set (match_operand:DW 0 "register_operand" "=d, d") | |
6327 | (mult:DW (zero_extend:DW | |
6328 | (match_operand:<DWH> 1 "register_operand" "%0, 0")) | |
6329 | (zero_extend:DW | |
6330 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] | |
6331 | "TARGET_CPU_ZARCH" | |
f1e77d83 | 6332 | "@ |
6e0d70c9 AK |
6333 | ml<tg>r\t%0,%2 |
6334 | ml<tg>\t%0,%2" | |
f1e77d83 | 6335 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6336 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6337 | |
9db1d521 | 6338 | ; |
609e7e80 | 6339 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6340 | ; |
6341 | ||
9381e3f1 | 6342 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6343 | (define_insn "mul<mode>3" |
62d3f261 AK |
6344 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
6345 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") | |
6346 | (match_operand:FP 2 "general_operand" "f,f,R,v")))] | |
142cd70f | 6347 | "TARGET_HARD_FLOAT" |
9db1d521 | 6348 | "@ |
62d3f261 AK |
6349 | m<xdee>tr\t%0,%1,%2 |
6350 | m<xdee>br\t%0,%2 | |
6e5b5de8 AK |
6351 | m<xdee>b\t%0,%2 |
6352 | wfmdb\t%v0,%v1,%v2" | |
62d3f261 | 6353 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 6354 | (set_attr "type" "fmul<mode>") |
62d3f261 AK |
6355 | (set_attr "cpu_facility" "*,*,*,vec") |
6356 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) | |
9db1d521 | 6357 | |
9381e3f1 | 6358 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6359 | (define_insn "fma<mode>4" |
62d3f261 AK |
6360 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v") |
6361 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") | |
6362 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") | |
6363 | (match_operand:DSF 3 "register_operand" "0,0,v")))] | |
d7ecb504 | 6364 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6365 | "@ |
f61a2c7d | 6366 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6367 | ma<xde>b\t%0,%1,%2 |
6368 | wfmadb\t%v0,%v1,%v2,%v3" | |
6369 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6370 | (set_attr "type" "fmadd<mode>") | |
62d3f261 AK |
6371 | (set_attr "cpu_facility" "*,*,vec") |
6372 | (set_attr "enabled" "*,*,<DFDI>")]) | |
a1b892b5 | 6373 | |
43a09b63 | 6374 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6375 | (define_insn "fms<mode>4" |
62d3f261 AK |
6376 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v") |
6377 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") | |
6378 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") | |
6379 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))] | |
d7ecb504 | 6380 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6381 | "@ |
f61a2c7d | 6382 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6383 | ms<xde>b\t%0,%1,%2 |
6384 | wfmsdb\t%v0,%v1,%v2,%v3" | |
6385 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6386 | (set_attr "type" "fmadd<mode>") | |
62d3f261 AK |
6387 | (set_attr "cpu_facility" "*,*,vec") |
6388 | (set_attr "enabled" "*,*,<DFDI>")]) | |
9db1d521 HP |
6389 | |
6390 | ;; | |
6391 | ;;- Divide and modulo instructions. | |
6392 | ;; | |
6393 | ||
6394 | ; | |
4023fb28 | 6395 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6396 | ; |
6397 | ||
4023fb28 UW |
6398 | (define_expand "divmoddi4" |
6399 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6400 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6401 | (match_operand:DI 2 "general_operand" ""))) |
6402 | (set (match_operand:DI 3 "general_operand" "") | |
6403 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6404 | (clobber (match_dup 4))] | |
9602b6a1 | 6405 | "TARGET_ZARCH" |
9db1d521 | 6406 | { |
f1e77d83 | 6407 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
6408 | |
6409 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6410 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6411 | |
6412 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6413 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6414 | |
6415 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6416 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6417 | |
6418 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6419 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6420 | |
9db1d521 | 6421 | DONE; |
10bbf137 | 6422 | }) |
9db1d521 HP |
6423 | |
6424 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6425 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6426 | (ior:TI | |
4023fb28 UW |
6427 | (ashift:TI |
6428 | (zero_extend:TI | |
5665e398 | 6429 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 6430 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
6431 | (const_int 64)) |
6432 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6433 | "TARGET_ZARCH" |
9db1d521 | 6434 | "@ |
d40c829f UW |
6435 | dsgr\t%0,%2 |
6436 | dsg\t%0,%2" | |
d3632d41 | 6437 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6438 | (set_attr "type" "idiv")]) |
9db1d521 | 6439 | |
4023fb28 UW |
6440 | (define_insn "divmodtisi3" |
6441 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6442 | (ior:TI | |
4023fb28 UW |
6443 | (ashift:TI |
6444 | (zero_extend:TI | |
5665e398 | 6445 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6446 | (sign_extend:DI |
fb492564 | 6447 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
6448 | (const_int 64)) |
6449 | (zero_extend:TI | |
6450 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6451 | "TARGET_ZARCH" |
4023fb28 | 6452 | "@ |
d40c829f UW |
6453 | dsgfr\t%0,%2 |
6454 | dsgf\t%0,%2" | |
d3632d41 | 6455 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6456 | (set_attr "type" "idiv")]) |
9db1d521 | 6457 | |
4023fb28 UW |
6458 | ; |
6459 | ; udivmoddi4 instruction pattern(s). | |
6460 | ; | |
9db1d521 | 6461 | |
4023fb28 UW |
6462 | (define_expand "udivmoddi4" |
6463 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6464 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6465 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6466 | (set (match_operand:DI 3 "general_operand" "") | |
6467 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6468 | (clobber (match_dup 4))] | |
9602b6a1 | 6469 | "TARGET_ZARCH" |
9db1d521 | 6470 | { |
4023fb28 UW |
6471 | rtx insn, div_equal, mod_equal, equal; |
6472 | ||
6473 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6474 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6475 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6476 | gen_rtx_ASHIFT (TImode, |
6477 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6478 | GEN_INT (64)), |
6479 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6480 | |
6481 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6482 | emit_clobber (operands[4]); |
4023fb28 UW |
6483 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6484 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6485 | |
4023fb28 | 6486 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6487 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6488 | |
6489 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6490 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6491 | |
6492 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6493 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6494 | |
9db1d521 | 6495 | DONE; |
10bbf137 | 6496 | }) |
9db1d521 HP |
6497 | |
6498 | (define_insn "udivmodtidi3" | |
4023fb28 | 6499 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6500 | (ior:TI |
5665e398 UW |
6501 | (ashift:TI |
6502 | (zero_extend:TI | |
6503 | (truncate:DI | |
2f7e5a0d EC |
6504 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6505 | (zero_extend:TI | |
fb492564 | 6506 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6507 | (const_int 64)) |
6508 | (zero_extend:TI | |
6509 | (truncate:DI | |
6510 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6511 | "TARGET_ZARCH" |
9db1d521 | 6512 | "@ |
d40c829f UW |
6513 | dlgr\t%0,%2 |
6514 | dlg\t%0,%2" | |
d3632d41 | 6515 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6516 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6517 | |
6518 | ; | |
4023fb28 | 6519 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6520 | ; |
6521 | ||
4023fb28 UW |
6522 | (define_expand "divmodsi4" |
6523 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6524 | (div:SI (match_operand:SI 1 "general_operand" "") | |
6525 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6526 | (set (match_operand:SI 3 "general_operand" "") | |
6527 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
6528 | (clobber (match_dup 4))] | |
9602b6a1 | 6529 | "!TARGET_ZARCH" |
9db1d521 | 6530 | { |
4023fb28 UW |
6531 | rtx insn, div_equal, mod_equal, equal; |
6532 | ||
6533 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
6534 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
6535 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6536 | gen_rtx_ASHIFT (DImode, |
6537 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6538 | GEN_INT (32)), |
6539 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
6540 | |
6541 | operands[4] = gen_reg_rtx(DImode); | |
6542 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 6543 | |
4023fb28 | 6544 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6545 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6546 | |
6547 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6548 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6549 | |
6550 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6551 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6552 | |
9db1d521 | 6553 | DONE; |
10bbf137 | 6554 | }) |
9db1d521 HP |
6555 | |
6556 | (define_insn "divmoddisi3" | |
4023fb28 | 6557 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 6558 | (ior:DI |
5665e398 UW |
6559 | (ashift:DI |
6560 | (zero_extend:DI | |
6561 | (truncate:SI | |
2f7e5a0d EC |
6562 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
6563 | (sign_extend:DI | |
5665e398 UW |
6564 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
6565 | (const_int 32)) | |
6566 | (zero_extend:DI | |
6567 | (truncate:SI | |
6568 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6569 | "!TARGET_ZARCH" |
9db1d521 | 6570 | "@ |
d40c829f UW |
6571 | dr\t%0,%2 |
6572 | d\t%0,%2" | |
9db1d521 | 6573 | [(set_attr "op_type" "RR,RX") |
077dab3b | 6574 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6575 | |
6576 | ; | |
6577 | ; udivsi3 and umodsi3 instruction pattern(s). | |
6578 | ; | |
6579 | ||
f1e77d83 UW |
6580 | (define_expand "udivmodsi4" |
6581 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6582 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
6583 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6584 | (set (match_operand:SI 3 "general_operand" "") | |
6585 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
6586 | (clobber (match_dup 4))] | |
9602b6a1 | 6587 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6588 | { |
6589 | rtx insn, div_equal, mod_equal, equal; | |
6590 | ||
6591 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6592 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6593 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
6594 | gen_rtx_ASHIFT (DImode, |
6595 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6596 | GEN_INT (32)), |
6597 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
6598 | |
6599 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 6600 | emit_clobber (operands[4]); |
f1e77d83 UW |
6601 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
6602 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 6603 | |
f1e77d83 | 6604 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6605 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
6606 | |
6607 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6608 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
6609 | |
6610 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6611 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
6612 | |
6613 | DONE; | |
6614 | }) | |
6615 | ||
6616 | (define_insn "udivmoddisi3" | |
6617 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 6618 | (ior:DI |
5665e398 UW |
6619 | (ashift:DI |
6620 | (zero_extend:DI | |
6621 | (truncate:SI | |
2f7e5a0d EC |
6622 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
6623 | (zero_extend:DI | |
fb492564 | 6624 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6625 | (const_int 32)) |
6626 | (zero_extend:DI | |
6627 | (truncate:SI | |
6628 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6629 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6630 | "@ |
6631 | dlr\t%0,%2 | |
6632 | dl\t%0,%2" | |
6633 | [(set_attr "op_type" "RRE,RXY") | |
6634 | (set_attr "type" "idiv")]) | |
4023fb28 | 6635 | |
9db1d521 HP |
6636 | (define_expand "udivsi3" |
6637 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6638 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
6639 | (match_operand:SI 2 "general_operand" ""))) |
6640 | (clobber (match_dup 3))] | |
9602b6a1 | 6641 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6642 | { |
4023fb28 UW |
6643 | rtx insn, udiv_equal, umod_equal, equal; |
6644 | ||
6645 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6646 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6647 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6648 | gen_rtx_ASHIFT (DImode, |
6649 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6650 | GEN_INT (32)), |
6651 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6652 | |
4023fb28 | 6653 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6654 | |
6655 | if (CONSTANT_P (operands[2])) | |
6656 | { | |
6657 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
6658 | { | |
19f8b229 | 6659 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6660 | |
4023fb28 UW |
6661 | operands[1] = make_safe_from (operands[1], operands[0]); |
6662 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6663 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
6664 | SImode, 1, label1); | |
4023fb28 | 6665 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6666 | emit_label (label1); |
6667 | } | |
6668 | else | |
6669 | { | |
c7453384 EC |
6670 | operands[2] = force_reg (SImode, operands[2]); |
6671 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6672 | |
6673 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6674 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6675 | operands[2])); | |
bd94cb6e | 6676 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6677 | |
6678 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6679 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 6680 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
6681 | } |
6682 | } | |
6683 | else | |
c7453384 | 6684 | { |
19f8b229 TS |
6685 | rtx_code_label *label1 = gen_label_rtx (); |
6686 | rtx_code_label *label2 = gen_label_rtx (); | |
6687 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6688 | |
c7453384 EC |
6689 | operands[1] = force_reg (SImode, operands[1]); |
6690 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6691 | operands[2] = force_reg (SImode, operands[2]); | |
6692 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6693 | |
6694 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6695 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6696 | SImode, 1, label3); | |
6697 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6698 | SImode, 0, label2); | |
6699 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6700 | SImode, 0, label1); | |
4023fb28 UW |
6701 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6702 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6703 | operands[2])); | |
bd94cb6e | 6704 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6705 | |
6706 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6707 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
6708 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
6709 | ||
f314b9b1 | 6710 | emit_jump (label3); |
9db1d521 | 6711 | emit_label (label1); |
4023fb28 | 6712 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 6713 | emit_jump (label3); |
9db1d521 | 6714 | emit_label (label2); |
4023fb28 | 6715 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6716 | emit_label (label3); |
6717 | } | |
c7453384 | 6718 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 6719 | DONE; |
10bbf137 | 6720 | }) |
9db1d521 HP |
6721 | |
6722 | (define_expand "umodsi3" | |
6723 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6724 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
6725 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
6726 | (clobber (match_dup 3))] | |
9602b6a1 | 6727 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6728 | { |
4023fb28 UW |
6729 | rtx insn, udiv_equal, umod_equal, equal; |
6730 | ||
6731 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6732 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6733 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6734 | gen_rtx_ASHIFT (DImode, |
6735 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6736 | GEN_INT (32)), |
6737 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6738 | |
4023fb28 | 6739 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6740 | |
6741 | if (CONSTANT_P (operands[2])) | |
6742 | { | |
6743 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
6744 | { | |
19f8b229 | 6745 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6746 | |
4023fb28 UW |
6747 | operands[1] = make_safe_from (operands[1], operands[0]); |
6748 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
6749 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
6750 | SImode, 1, label1); | |
4023fb28 UW |
6751 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
6752 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
6753 | emit_label (label1); |
6754 | } | |
6755 | else | |
6756 | { | |
c7453384 EC |
6757 | operands[2] = force_reg (SImode, operands[2]); |
6758 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6759 | |
6760 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6761 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6762 | operands[2])); | |
bd94cb6e | 6763 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6764 | |
6765 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6766 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 6767 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
6768 | } |
6769 | } | |
6770 | else | |
6771 | { | |
19f8b229 TS |
6772 | rtx_code_label *label1 = gen_label_rtx (); |
6773 | rtx_code_label *label2 = gen_label_rtx (); | |
6774 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6775 | |
c7453384 EC |
6776 | operands[1] = force_reg (SImode, operands[1]); |
6777 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6778 | operands[2] = force_reg (SImode, operands[2]); | |
6779 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 6780 | |
c7453384 | 6781 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
6782 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6783 | SImode, 1, label3); | |
6784 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6785 | SImode, 0, label2); | |
6786 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6787 | SImode, 0, label1); | |
4023fb28 UW |
6788 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6789 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6790 | operands[2])); | |
bd94cb6e | 6791 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6792 | |
6793 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6794 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
6795 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
6796 | ||
f314b9b1 | 6797 | emit_jump (label3); |
9db1d521 | 6798 | emit_label (label1); |
4023fb28 | 6799 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 6800 | emit_jump (label3); |
9db1d521 | 6801 | emit_label (label2); |
4023fb28 | 6802 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
6803 | emit_label (label3); |
6804 | } | |
9db1d521 | 6805 | DONE; |
10bbf137 | 6806 | }) |
9db1d521 HP |
6807 | |
6808 | ; | |
f5905b37 | 6809 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
6810 | ; |
6811 | ||
609e7e80 | 6812 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 6813 | (define_insn "div<mode>3" |
62d3f261 AK |
6814 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
6815 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v") | |
6816 | (match_operand:FP 2 "general_operand" "f,f,R,v")))] | |
142cd70f | 6817 | "TARGET_HARD_FLOAT" |
9db1d521 | 6818 | "@ |
62d3f261 AK |
6819 | d<xde>tr\t%0,%1,%2 |
6820 | d<xde>br\t%0,%2 | |
6e5b5de8 AK |
6821 | d<xde>b\t%0,%2 |
6822 | wfddb\t%v0,%v1,%v2" | |
62d3f261 | 6823 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 6824 | (set_attr "type" "fdiv<mode>") |
62d3f261 AK |
6825 | (set_attr "cpu_facility" "*,*,*,vec") |
6826 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) | |
9db1d521 | 6827 | |
9db1d521 HP |
6828 | |
6829 | ;; | |
6830 | ;;- And instructions. | |
6831 | ;; | |
6832 | ||
047d35ed AS |
6833 | (define_expand "and<mode>3" |
6834 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6835 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6836 | (match_operand:INT 2 "general_operand" ""))) | |
6837 | (clobber (reg:CC CC_REGNUM))] | |
6838 | "" | |
6839 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
6840 | ||
9db1d521 HP |
6841 | ; |
6842 | ; anddi3 instruction pattern(s). | |
6843 | ; | |
6844 | ||
6845 | (define_insn "*anddi3_cc" | |
ae156f85 | 6846 | [(set (reg CC_REGNUM) |
e3140518 RH |
6847 | (compare |
6848 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6849 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
6850 | (const_int 0))) | |
6851 | (set (match_operand:DI 0 "register_operand" "=d,d, d, d") | |
9db1d521 | 6852 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 6853 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 6854 | "@ |
d40c829f | 6855 | ngr\t%0,%2 |
65b1d8ea | 6856 | ngrk\t%0,%1,%2 |
e3140518 RH |
6857 | ng\t%0,%2 |
6858 | risbg\t%0,%1,%s2,128+%e2,0" | |
6859 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6860 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6861 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6862 | |
6863 | (define_insn "*anddi3_cconly" | |
ae156f85 | 6864 | [(set (reg CC_REGNUM) |
e3140518 RH |
6865 | (compare |
6866 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6867 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
9db1d521 | 6868 | (const_int 0))) |
e3140518 RH |
6869 | (clobber (match_scratch:DI 0 "=d,d, d, d"))] |
6870 | "TARGET_ZARCH | |
6871 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
6872 | /* Do not steal TM patterns. */ |
6873 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 6874 | "@ |
d40c829f | 6875 | ngr\t%0,%2 |
65b1d8ea | 6876 | ngrk\t%0,%1,%2 |
e3140518 RH |
6877 | ng\t%0,%2 |
6878 | risbg\t%0,%1,%s2,128+%e2,0" | |
6879 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6880 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6881 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6882 | |
3af8e996 | 6883 | (define_insn "*anddi3" |
65b1d8ea | 6884 | [(set (match_operand:DI 0 "nonimmediate_operand" |
e3140518 RH |
6885 | "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") |
6886 | (and:DI | |
6887 | (match_operand:DI 1 "nonimmediate_operand" | |
6888 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") | |
6889 | (match_operand:DI 2 "general_operand" | |
6890 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) | |
ec24698e | 6891 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6892 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6893 | "@ |
6894 | # | |
6895 | # | |
6896 | nihh\t%0,%j2 | |
6897 | nihl\t%0,%j2 | |
6898 | nilh\t%0,%j2 | |
6899 | nill\t%0,%j2 | |
6900 | nihf\t%0,%m2 | |
6901 | nilf\t%0,%m2 | |
6902 | ngr\t%0,%2 | |
65b1d8ea | 6903 | ngrk\t%0,%1,%2 |
ec24698e | 6904 | ng\t%0,%2 |
e3140518 | 6905 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
6906 | # |
6907 | #" | |
e3140518 RH |
6908 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
6909 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
6910 | (set_attr "z10prop" "*, |
6911 | *, | |
6912 | z10_super_E1, | |
6913 | z10_super_E1, | |
6914 | z10_super_E1, | |
6915 | z10_super_E1, | |
6916 | z10_super_E1, | |
6917 | z10_super_E1, | |
6918 | z10_super_E1, | |
65b1d8ea | 6919 | *, |
9381e3f1 | 6920 | z10_super_E1, |
e3140518 | 6921 | z10_super_E1, |
9381e3f1 WG |
6922 | *, |
6923 | *")]) | |
0dfa6c5e UW |
6924 | |
6925 | (define_split | |
6926 | [(set (match_operand:DI 0 "s_operand" "") | |
6927 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6928 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6929 | "reload_completed" |
6930 | [(parallel | |
6931 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6932 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6933 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6934 | |
1a2e356e RH |
6935 | ;; These two are what combine generates for (ashift (zero_extract)). |
6936 | (define_insn "*extzv_<mode>_srl" | |
6937 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6938 | (and:GPR (lshiftrt:GPR | |
6939 | (match_operand:GPR 1 "register_operand" "d") | |
6940 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6941 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6942 | (clobber (reg:CC CC_REGNUM))] | |
6943 | "TARGET_Z10 | |
6944 | /* Note that even for the SImode pattern, the rotate is always DImode. */ | |
6945 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
6946 | INTVAL (operands[3]))" | |
6947 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" | |
6948 | [(set_attr "op_type" "RIE") | |
6949 | (set_attr "z10prop" "z10_super_E1")]) | |
6950 | ||
6951 | (define_insn "*extzv_<mode>_sll" | |
6952 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6953 | (and:GPR (ashift:GPR | |
6954 | (match_operand:GPR 1 "register_operand" "d") | |
6955 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6956 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6957 | (clobber (reg:CC CC_REGNUM))] | |
6958 | "TARGET_Z10 | |
6959 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), | |
6960 | INTVAL (operands[3]))" | |
6961 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" | |
6962 | [(set_attr "op_type" "RIE") | |
6963 | (set_attr "z10prop" "z10_super_E1")]) | |
6964 | ||
9db1d521 HP |
6965 | |
6966 | ; | |
6967 | ; andsi3 instruction pattern(s). | |
6968 | ; | |
6969 | ||
6970 | (define_insn "*andsi3_cc" | |
ae156f85 | 6971 | [(set (reg CC_REGNUM) |
e3140518 RH |
6972 | (compare |
6973 | (and:SI | |
6974 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6975 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6976 | (const_int 0))) | |
6977 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
6978 | (and:SI (match_dup 1) (match_dup 2)))] |
6979 | "s390_match_ccmode(insn, CCTmode)" | |
6980 | "@ | |
ec24698e | 6981 | nilf\t%0,%o2 |
d40c829f | 6982 | nr\t%0,%2 |
65b1d8ea | 6983 | nrk\t%0,%1,%2 |
d40c829f | 6984 | n\t%0,%2 |
e3140518 RH |
6985 | ny\t%0,%2 |
6986 | risbg\t%0,%1,%t2,128+%f2,0" | |
6987 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6988 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
6989 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6990 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6991 | |
6992 | (define_insn "*andsi3_cconly" | |
ae156f85 | 6993 | [(set (reg CC_REGNUM) |
e3140518 RH |
6994 | (compare |
6995 | (and:SI | |
6996 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6997 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6998 | (const_int 0))) | |
6999 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7000 | "s390_match_ccmode(insn, CCTmode) |
7001 | /* Do not steal TM patterns. */ | |
7002 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7003 | "@ |
ec24698e | 7004 | nilf\t%0,%o2 |
d40c829f | 7005 | nr\t%0,%2 |
65b1d8ea | 7006 | nrk\t%0,%1,%2 |
d40c829f | 7007 | n\t%0,%2 |
e3140518 RH |
7008 | ny\t%0,%2 |
7009 | risbg\t%0,%1,%t2,128+%f2,0" | |
7010 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
7011 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
65b1d8ea | 7012 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7013 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7014 | |
f19a9af7 | 7015 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7016 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7017 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7018 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7019 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7020 | (match_operand:SI 2 "general_operand" |
e3140518 | 7021 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q"))) |
ae156f85 | 7022 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7023 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7024 | "@ |
f19a9af7 AK |
7025 | # |
7026 | # | |
7027 | nilh\t%0,%j2 | |
2f7e5a0d | 7028 | nill\t%0,%j2 |
ec24698e | 7029 | nilf\t%0,%o2 |
d40c829f | 7030 | nr\t%0,%2 |
65b1d8ea | 7031 | nrk\t%0,%1,%2 |
d40c829f | 7032 | n\t%0,%2 |
8cb66696 | 7033 | ny\t%0,%2 |
e3140518 | 7034 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7035 | # |
19b63d8e | 7036 | #" |
e3140518 RH |
7037 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
7038 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") | |
9381e3f1 WG |
7039 | (set_attr "z10prop" "*, |
7040 | *, | |
7041 | z10_super_E1, | |
7042 | z10_super_E1, | |
7043 | z10_super_E1, | |
7044 | z10_super_E1, | |
65b1d8ea | 7045 | *, |
9381e3f1 WG |
7046 | z10_super_E1, |
7047 | z10_super_E1, | |
e3140518 | 7048 | z10_super_E1, |
9381e3f1 WG |
7049 | *, |
7050 | *")]) | |
f19a9af7 AK |
7051 | |
7052 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7053 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7054 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7055 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7056 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7057 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7058 | "@ |
7059 | nr\t%0,%2 | |
8cb66696 | 7060 | n\t%0,%2 |
0dfa6c5e | 7061 | # |
19b63d8e | 7062 | #" |
9381e3f1 WG |
7063 | [(set_attr "op_type" "RR,RX,SI,SS") |
7064 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7065 | ||
0dfa6c5e UW |
7066 | |
7067 | (define_split | |
7068 | [(set (match_operand:SI 0 "s_operand" "") | |
7069 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7070 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7071 | "reload_completed" |
7072 | [(parallel | |
7073 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7074 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7075 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7076 | |
9db1d521 HP |
7077 | ; |
7078 | ; andhi3 instruction pattern(s). | |
7079 | ; | |
7080 | ||
8cb66696 | 7081 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7082 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7083 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7084 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7085 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7086 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7087 | "@ |
d40c829f | 7088 | nr\t%0,%2 |
65b1d8ea | 7089 | nrk\t%0,%1,%2 |
8cb66696 | 7090 | nill\t%0,%x2 |
0dfa6c5e | 7091 | # |
19b63d8e | 7092 | #" |
65b1d8ea AK |
7093 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7094 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7095 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7096 | ]) |
8cb66696 UW |
7097 | |
7098 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7099 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7100 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7101 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7102 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7103 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7104 | "@ | |
7105 | nr\t%0,%2 | |
0dfa6c5e | 7106 | # |
19b63d8e | 7107 | #" |
9381e3f1 WG |
7108 | [(set_attr "op_type" "RR,SI,SS") |
7109 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7110 | ]) | |
0dfa6c5e UW |
7111 | |
7112 | (define_split | |
7113 | [(set (match_operand:HI 0 "s_operand" "") | |
7114 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7115 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7116 | "reload_completed" |
7117 | [(parallel | |
7118 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7119 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7120 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7121 | |
9db1d521 HP |
7122 | ; |
7123 | ; andqi3 instruction pattern(s). | |
7124 | ; | |
7125 | ||
8cb66696 | 7126 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7127 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7128 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7129 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7130 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7131 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7132 | "@ |
d40c829f | 7133 | nr\t%0,%2 |
65b1d8ea | 7134 | nrk\t%0,%1,%2 |
8cb66696 | 7135 | nill\t%0,%b2 |
fc0ea003 UW |
7136 | ni\t%S0,%b2 |
7137 | niy\t%S0,%b2 | |
19b63d8e | 7138 | #" |
65b1d8ea AK |
7139 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
7140 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
7141 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
7142 | |
7143 | (define_insn "*andqi3_esa" | |
7144 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7145 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7146 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7147 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7148 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7149 | "@ |
8cb66696 | 7150 | nr\t%0,%2 |
fc0ea003 | 7151 | ni\t%S0,%b2 |
19b63d8e | 7152 | #" |
9381e3f1 WG |
7153 | [(set_attr "op_type" "RR,SI,SS") |
7154 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7155 | |
19b63d8e UW |
7156 | ; |
7157 | ; Block and (NC) patterns. | |
7158 | ; | |
7159 | ||
7160 | (define_insn "*nc" | |
7161 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7162 | (and:BLK (match_dup 0) | |
7163 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7164 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7165 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7166 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7167 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7168 | [(set_attr "op_type" "SS") |
7169 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7170 | |
7171 | (define_split | |
7172 | [(set (match_operand 0 "memory_operand" "") | |
7173 | (and (match_dup 0) | |
7174 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7175 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7176 | "reload_completed |
7177 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7178 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7179 | [(parallel | |
7180 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7181 | (use (match_dup 2)) | |
ae156f85 | 7182 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7183 | { |
7184 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7185 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7186 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7187 | }) | |
7188 | ||
7189 | (define_peephole2 | |
7190 | [(parallel | |
7191 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7192 | (and:BLK (match_dup 0) | |
7193 | (match_operand:BLK 1 "memory_operand" ""))) | |
7194 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7195 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7196 | (parallel |
7197 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7198 | (and:BLK (match_dup 3) | |
7199 | (match_operand:BLK 4 "memory_operand" ""))) | |
7200 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7201 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7202 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7203 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7204 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7205 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7206 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7207 | [(parallel | |
7208 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7209 | (use (match_dup 8)) | |
ae156f85 | 7210 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7211 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7212 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7213 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7214 | ||
9db1d521 HP |
7215 | |
7216 | ;; | |
7217 | ;;- Bit set (inclusive or) instructions. | |
7218 | ;; | |
7219 | ||
047d35ed AS |
7220 | (define_expand "ior<mode>3" |
7221 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7222 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7223 | (match_operand:INT 2 "general_operand" ""))) | |
7224 | (clobber (reg:CC CC_REGNUM))] | |
7225 | "" | |
7226 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7227 | ||
9db1d521 HP |
7228 | ; |
7229 | ; iordi3 instruction pattern(s). | |
7230 | ; | |
7231 | ||
4023fb28 | 7232 | (define_insn "*iordi3_cc" |
ae156f85 | 7233 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7234 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7235 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7236 | (const_int 0))) |
65b1d8ea | 7237 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 7238 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7239 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7240 | "@ |
d40c829f | 7241 | ogr\t%0,%2 |
65b1d8ea | 7242 | ogrk\t%0,%1,%2 |
d40c829f | 7243 | og\t%0,%2" |
65b1d8ea AK |
7244 | [(set_attr "op_type" "RRE,RRF,RXY") |
7245 | (set_attr "cpu_facility" "*,z196,*") | |
7246 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7247 | |
7248 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7249 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7250 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7251 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7252 | (const_int 0))) |
65b1d8ea | 7253 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7254 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7255 | "@ |
d40c829f | 7256 | ogr\t%0,%2 |
65b1d8ea | 7257 | ogrk\t%0,%1,%2 |
d40c829f | 7258 | og\t%0,%2" |
65b1d8ea AK |
7259 | [(set_attr "op_type" "RRE,RRF,RXY") |
7260 | (set_attr "cpu_facility" "*,z196,*") | |
7261 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7262 | |
3af8e996 | 7263 | (define_insn "*iordi3" |
65b1d8ea AK |
7264 | [(set (match_operand:DI 0 "nonimmediate_operand" |
7265 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
7266 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
7267 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 7268 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 7269 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 7270 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7271 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7272 | "@ |
7273 | oihh\t%0,%i2 | |
7274 | oihl\t%0,%i2 | |
7275 | oilh\t%0,%i2 | |
7276 | oill\t%0,%i2 | |
7277 | oihf\t%0,%k2 | |
7278 | oilf\t%0,%k2 | |
7279 | ogr\t%0,%2 | |
65b1d8ea | 7280 | ogrk\t%0,%1,%2 |
ec24698e UW |
7281 | og\t%0,%2 |
7282 | # | |
7283 | #" | |
65b1d8ea AK |
7284 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7285 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7286 | (set_attr "z10prop" "z10_super_E1, |
7287 | z10_super_E1, | |
7288 | z10_super_E1, | |
7289 | z10_super_E1, | |
7290 | z10_super_E1, | |
7291 | z10_super_E1, | |
7292 | z10_super_E1, | |
65b1d8ea | 7293 | *, |
9381e3f1 WG |
7294 | z10_super_E1, |
7295 | *, | |
7296 | *")]) | |
0dfa6c5e UW |
7297 | |
7298 | (define_split | |
7299 | [(set (match_operand:DI 0 "s_operand" "") | |
7300 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7301 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7302 | "reload_completed" |
7303 | [(parallel | |
7304 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7305 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7306 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7307 | |
9db1d521 HP |
7308 | ; |
7309 | ; iorsi3 instruction pattern(s). | |
7310 | ; | |
7311 | ||
4023fb28 | 7312 | (define_insn "*iorsi3_cc" |
ae156f85 | 7313 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7314 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7315 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7316 | (const_int 0))) |
65b1d8ea | 7317 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7318 | (ior:SI (match_dup 1) (match_dup 2)))] |
7319 | "s390_match_ccmode(insn, CCTmode)" | |
7320 | "@ | |
ec24698e | 7321 | oilf\t%0,%o2 |
d40c829f | 7322 | or\t%0,%2 |
65b1d8ea | 7323 | ork\t%0,%1,%2 |
d40c829f UW |
7324 | o\t%0,%2 |
7325 | oy\t%0,%2" | |
65b1d8ea AK |
7326 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7327 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7328 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7329 | |
7330 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7331 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7332 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7333 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7334 | (const_int 0))) |
65b1d8ea | 7335 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7336 | "s390_match_ccmode(insn, CCTmode)" |
7337 | "@ | |
ec24698e | 7338 | oilf\t%0,%o2 |
d40c829f | 7339 | or\t%0,%2 |
65b1d8ea | 7340 | ork\t%0,%1,%2 |
d40c829f UW |
7341 | o\t%0,%2 |
7342 | oy\t%0,%2" | |
65b1d8ea AK |
7343 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7344 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7345 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 7346 | |
8cb66696 | 7347 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7348 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7349 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7350 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7351 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7352 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7353 | "@ |
f19a9af7 AK |
7354 | oilh\t%0,%i2 |
7355 | oill\t%0,%i2 | |
ec24698e | 7356 | oilf\t%0,%o2 |
d40c829f | 7357 | or\t%0,%2 |
65b1d8ea | 7358 | ork\t%0,%1,%2 |
d40c829f | 7359 | o\t%0,%2 |
8cb66696 | 7360 | oy\t%0,%2 |
0dfa6c5e | 7361 | # |
19b63d8e | 7362 | #" |
65b1d8ea AK |
7363 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
7364 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
7365 | (set_attr "z10prop" "z10_super_E1, |
7366 | z10_super_E1, | |
7367 | z10_super_E1, | |
7368 | z10_super_E1, | |
65b1d8ea | 7369 | *, |
9381e3f1 WG |
7370 | z10_super_E1, |
7371 | z10_super_E1, | |
7372 | *, | |
7373 | *")]) | |
8cb66696 UW |
7374 | |
7375 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7376 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7377 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7378 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7379 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7380 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7381 | "@ |
7382 | or\t%0,%2 | |
8cb66696 | 7383 | o\t%0,%2 |
0dfa6c5e | 7384 | # |
19b63d8e | 7385 | #" |
9381e3f1 WG |
7386 | [(set_attr "op_type" "RR,RX,SI,SS") |
7387 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7388 | |
7389 | (define_split | |
7390 | [(set (match_operand:SI 0 "s_operand" "") | |
7391 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7392 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7393 | "reload_completed" |
7394 | [(parallel | |
7395 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7396 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7397 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7398 | |
4023fb28 UW |
7399 | ; |
7400 | ; iorhi3 instruction pattern(s). | |
7401 | ; | |
7402 | ||
8cb66696 | 7403 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7404 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7405 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7406 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7407 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7408 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7409 | "@ |
d40c829f | 7410 | or\t%0,%2 |
65b1d8ea | 7411 | ork\t%0,%1,%2 |
8cb66696 | 7412 | oill\t%0,%x2 |
0dfa6c5e | 7413 | # |
19b63d8e | 7414 | #" |
65b1d8ea AK |
7415 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7416 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7417 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7418 | |
7419 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7420 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7421 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7422 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7423 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7424 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7425 | "@ | |
7426 | or\t%0,%2 | |
0dfa6c5e | 7427 | # |
19b63d8e | 7428 | #" |
9381e3f1 WG |
7429 | [(set_attr "op_type" "RR,SI,SS") |
7430 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7431 | |
7432 | (define_split | |
7433 | [(set (match_operand:HI 0 "s_operand" "") | |
7434 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7435 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7436 | "reload_completed" |
7437 | [(parallel | |
7438 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7439 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7440 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7441 | |
9db1d521 | 7442 | ; |
4023fb28 | 7443 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7444 | ; |
7445 | ||
8cb66696 | 7446 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7447 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7448 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7449 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7450 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7451 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7452 | "@ |
d40c829f | 7453 | or\t%0,%2 |
65b1d8ea | 7454 | ork\t%0,%1,%2 |
8cb66696 | 7455 | oill\t%0,%b2 |
fc0ea003 UW |
7456 | oi\t%S0,%b2 |
7457 | oiy\t%S0,%b2 | |
19b63d8e | 7458 | #" |
65b1d8ea AK |
7459 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
7460 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
7461 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
7462 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7463 | |
7464 | (define_insn "*iorqi3_esa" | |
7465 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7466 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7467 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7468 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7469 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7470 | "@ |
8cb66696 | 7471 | or\t%0,%2 |
fc0ea003 | 7472 | oi\t%S0,%b2 |
19b63d8e | 7473 | #" |
9381e3f1 WG |
7474 | [(set_attr "op_type" "RR,SI,SS") |
7475 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7476 | |
19b63d8e UW |
7477 | ; |
7478 | ; Block inclusive or (OC) patterns. | |
7479 | ; | |
7480 | ||
7481 | (define_insn "*oc" | |
7482 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7483 | (ior:BLK (match_dup 0) | |
7484 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7485 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7486 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7487 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7488 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7489 | [(set_attr "op_type" "SS") |
7490 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7491 | |
7492 | (define_split | |
7493 | [(set (match_operand 0 "memory_operand" "") | |
7494 | (ior (match_dup 0) | |
7495 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7496 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7497 | "reload_completed |
7498 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7499 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7500 | [(parallel | |
7501 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7502 | (use (match_dup 2)) | |
ae156f85 | 7503 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7504 | { |
7505 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7506 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7507 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7508 | }) | |
7509 | ||
7510 | (define_peephole2 | |
7511 | [(parallel | |
7512 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7513 | (ior:BLK (match_dup 0) | |
7514 | (match_operand:BLK 1 "memory_operand" ""))) | |
7515 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7516 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7517 | (parallel |
7518 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7519 | (ior:BLK (match_dup 3) | |
7520 | (match_operand:BLK 4 "memory_operand" ""))) | |
7521 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7522 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7523 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7524 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7525 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7526 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7527 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7528 | [(parallel | |
7529 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7530 | (use (match_dup 8)) | |
ae156f85 | 7531 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7532 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7533 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7534 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7535 | ||
9db1d521 HP |
7536 | |
7537 | ;; | |
7538 | ;;- Xor instructions. | |
7539 | ;; | |
7540 | ||
047d35ed AS |
7541 | (define_expand "xor<mode>3" |
7542 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7543 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7544 | (match_operand:INT 2 "general_operand" ""))) | |
7545 | (clobber (reg:CC CC_REGNUM))] | |
7546 | "" | |
7547 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7548 | ||
3c91f126 AK |
7549 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7550 | ; simplifications. So its better to have something matching. | |
7551 | (define_split | |
7552 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7553 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7554 | "" | |
7555 | [(parallel | |
7556 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7557 | (clobber (reg:CC CC_REGNUM))])] | |
7558 | { | |
7559 | operands[2] = constm1_rtx; | |
7560 | if (!s390_logical_operator_ok_p (operands)) | |
7561 | FAIL; | |
7562 | }) | |
7563 | ||
9db1d521 HP |
7564 | ; |
7565 | ; xordi3 instruction pattern(s). | |
7566 | ; | |
7567 | ||
4023fb28 | 7568 | (define_insn "*xordi3_cc" |
ae156f85 | 7569 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7570 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7571 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7572 | (const_int 0))) |
65b1d8ea | 7573 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 7574 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7575 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7576 | "@ |
d40c829f | 7577 | xgr\t%0,%2 |
65b1d8ea | 7578 | xgrk\t%0,%1,%2 |
d40c829f | 7579 | xg\t%0,%2" |
65b1d8ea | 7580 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7581 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7582 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7583 | |
7584 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7585 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7586 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7587 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7588 | (const_int 0))) |
65b1d8ea | 7589 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 7590 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7591 | "@ |
d40c829f | 7592 | xgr\t%0,%2 |
65b1d8ea | 7593 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 7594 | xg\t%0,%2" |
65b1d8ea AK |
7595 | [(set_attr "op_type" "RRE,RRF,RXY") |
7596 | (set_attr "cpu_facility" "*,z196,*") | |
7597 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7598 | |
3af8e996 | 7599 | (define_insn "*xordi3" |
65b1d8ea AK |
7600 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
7601 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
7602 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 7603 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7604 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7605 | "@ |
7606 | xihf\t%0,%k2 | |
7607 | xilf\t%0,%k2 | |
7608 | xgr\t%0,%2 | |
65b1d8ea | 7609 | xgrk\t%0,%1,%2 |
ec24698e UW |
7610 | xg\t%0,%2 |
7611 | # | |
7612 | #" | |
65b1d8ea AK |
7613 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
7614 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
7615 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
7616 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7617 | |
7618 | (define_split | |
7619 | [(set (match_operand:DI 0 "s_operand" "") | |
7620 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7621 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7622 | "reload_completed" |
7623 | [(parallel | |
7624 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7625 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7626 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 7627 | |
9db1d521 HP |
7628 | ; |
7629 | ; xorsi3 instruction pattern(s). | |
7630 | ; | |
7631 | ||
4023fb28 | 7632 | (define_insn "*xorsi3_cc" |
ae156f85 | 7633 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7634 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7635 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7636 | (const_int 0))) |
65b1d8ea | 7637 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7638 | (xor:SI (match_dup 1) (match_dup 2)))] |
7639 | "s390_match_ccmode(insn, CCTmode)" | |
7640 | "@ | |
ec24698e | 7641 | xilf\t%0,%o2 |
d40c829f | 7642 | xr\t%0,%2 |
65b1d8ea | 7643 | xrk\t%0,%1,%2 |
d40c829f UW |
7644 | x\t%0,%2 |
7645 | xy\t%0,%2" | |
65b1d8ea AK |
7646 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7647 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7648 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7649 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7650 | |
7651 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 7652 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7653 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7654 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7655 | (const_int 0))) |
65b1d8ea | 7656 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7657 | "s390_match_ccmode(insn, CCTmode)" |
7658 | "@ | |
ec24698e | 7659 | xilf\t%0,%o2 |
d40c829f | 7660 | xr\t%0,%2 |
65b1d8ea | 7661 | xrk\t%0,%1,%2 |
d40c829f UW |
7662 | x\t%0,%2 |
7663 | xy\t%0,%2" | |
65b1d8ea AK |
7664 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7665 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7666 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7667 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7668 | |
8cb66696 | 7669 | (define_insn "*xorsi3" |
65b1d8ea AK |
7670 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
7671 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
7672 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7673 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7674 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7675 | "@ |
ec24698e | 7676 | xilf\t%0,%o2 |
d40c829f | 7677 | xr\t%0,%2 |
65b1d8ea | 7678 | xrk\t%0,%1,%2 |
d40c829f | 7679 | x\t%0,%2 |
8cb66696 | 7680 | xy\t%0,%2 |
0dfa6c5e | 7681 | # |
19b63d8e | 7682 | #" |
65b1d8ea AK |
7683 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
7684 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
7685 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7686 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7687 | |
7688 | (define_split | |
7689 | [(set (match_operand:SI 0 "s_operand" "") | |
7690 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7691 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7692 | "reload_completed" |
7693 | [(parallel | |
7694 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7695 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7696 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 7697 | |
9db1d521 HP |
7698 | ; |
7699 | ; xorhi3 instruction pattern(s). | |
7700 | ; | |
7701 | ||
8cb66696 | 7702 | (define_insn "*xorhi3" |
65b1d8ea AK |
7703 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7704 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
7705 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 7706 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7707 | "s390_logical_operator_ok_p (operands)" |
7708 | "@ | |
ec24698e | 7709 | xilf\t%0,%x2 |
8cb66696 | 7710 | xr\t%0,%2 |
65b1d8ea | 7711 | xrk\t%0,%1,%2 |
0dfa6c5e | 7712 | # |
19b63d8e | 7713 | #" |
65b1d8ea AK |
7714 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
7715 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7716 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
7717 | |
7718 | (define_split | |
7719 | [(set (match_operand:HI 0 "s_operand" "") | |
7720 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7721 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7722 | "reload_completed" |
7723 | [(parallel | |
7724 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7725 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7726 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 7727 | |
9db1d521 HP |
7728 | ; |
7729 | ; xorqi3 instruction pattern(s). | |
7730 | ; | |
7731 | ||
8cb66696 | 7732 | (define_insn "*xorqi3" |
65b1d8ea AK |
7733 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7734 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
7735 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 7736 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7737 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7738 | "@ |
ec24698e | 7739 | xilf\t%0,%b2 |
8cb66696 | 7740 | xr\t%0,%2 |
65b1d8ea | 7741 | xrk\t%0,%1,%2 |
fc0ea003 UW |
7742 | xi\t%S0,%b2 |
7743 | xiy\t%S0,%b2 | |
19b63d8e | 7744 | #" |
65b1d8ea AK |
7745 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
7746 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
7747 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 7748 | |
4023fb28 | 7749 | |
19b63d8e UW |
7750 | ; |
7751 | ; Block exclusive or (XC) patterns. | |
7752 | ; | |
7753 | ||
7754 | (define_insn "*xc" | |
7755 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7756 | (xor:BLK (match_dup 0) | |
7757 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7758 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7759 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7760 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7761 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 7762 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
7763 | |
7764 | (define_split | |
7765 | [(set (match_operand 0 "memory_operand" "") | |
7766 | (xor (match_dup 0) | |
7767 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7768 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7769 | "reload_completed |
7770 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7771 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7772 | [(parallel | |
7773 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
7774 | (use (match_dup 2)) | |
ae156f85 | 7775 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7776 | { |
7777 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7778 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7779 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7780 | }) | |
7781 | ||
7782 | (define_peephole2 | |
7783 | [(parallel | |
7784 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7785 | (xor:BLK (match_dup 0) | |
7786 | (match_operand:BLK 1 "memory_operand" ""))) | |
7787 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7788 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7789 | (parallel |
7790 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7791 | (xor:BLK (match_dup 3) | |
7792 | (match_operand:BLK 4 "memory_operand" ""))) | |
7793 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7794 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7795 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7796 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7797 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7798 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7799 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7800 | [(parallel | |
7801 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
7802 | (use (match_dup 8)) | |
ae156f85 | 7803 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7804 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7805 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7806 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7807 | ||
7808 | ; | |
7809 | ; Block xor (XC) patterns with src == dest. | |
7810 | ; | |
7811 | ||
7812 | (define_insn "*xc_zero" | |
7813 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7814 | (const_int 0)) | |
7815 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 7816 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7817 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 7818 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
7819 | [(set_attr "op_type" "SS") |
7820 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7821 | |
7822 | (define_peephole2 | |
7823 | [(parallel | |
7824 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7825 | (const_int 0)) | |
7826 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 7827 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7828 | (parallel |
7829 | [(set (match_operand:BLK 2 "memory_operand" "") | |
7830 | (const_int 0)) | |
7831 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 7832 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7833 | "s390_offset_p (operands[0], operands[2], operands[1]) |
7834 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
7835 | [(parallel | |
7836 | [(set (match_dup 4) (const_int 0)) | |
7837 | (use (match_dup 5)) | |
ae156f85 | 7838 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7839 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7840 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
7841 | ||
9db1d521 HP |
7842 | |
7843 | ;; | |
7844 | ;;- Negate instructions. | |
7845 | ;; | |
7846 | ||
7847 | ; | |
9a91a21f | 7848 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
7849 | ; |
7850 | ||
9a91a21f | 7851 | (define_expand "neg<mode>2" |
9db1d521 | 7852 | [(parallel |
9a91a21f AS |
7853 | [(set (match_operand:DSI 0 "register_operand" "=d") |
7854 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 7855 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7856 | "" |
7857 | "") | |
7858 | ||
26a89301 | 7859 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 7860 | [(set (reg CC_REGNUM) |
26a89301 UW |
7861 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7862 | (match_operand:SI 1 "register_operand" "d") 0) | |
7863 | (const_int 32)) (const_int 32))) | |
7864 | (const_int 0))) | |
7865 | (set (match_operand:DI 0 "register_operand" "=d") | |
7866 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7867 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7868 | "lcgfr\t%0,%1" |
729e750f WG |
7869 | [(set_attr "op_type" "RRE") |
7870 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7871 | |
26a89301 UW |
7872 | (define_insn "*negdi2_sign" |
7873 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7874 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7875 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7876 | "TARGET_ZARCH" |
26a89301 | 7877 | "lcgfr\t%0,%1" |
729e750f WG |
7878 | [(set_attr "op_type" "RRE") |
7879 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7880 | |
43a09b63 | 7881 | ; lcr, lcgr |
9a91a21f | 7882 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7883 | [(set (reg CC_REGNUM) |
9a91a21f | 7884 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7885 | (const_int 0))) |
9a91a21f AS |
7886 | (set (match_operand:GPR 0 "register_operand" "=d") |
7887 | (neg:GPR (match_dup 1)))] | |
7888 | "s390_match_ccmode (insn, CCAmode)" | |
7889 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7890 | [(set_attr "op_type" "RR<E>") |
7891 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7892 | |
7893 | ; lcr, lcgr | |
9a91a21f | 7894 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7895 | [(set (reg CC_REGNUM) |
9a91a21f | 7896 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7897 | (const_int 0))) |
9a91a21f AS |
7898 | (clobber (match_scratch:GPR 0 "=d"))] |
7899 | "s390_match_ccmode (insn, CCAmode)" | |
7900 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7901 | [(set_attr "op_type" "RR<E>") |
7902 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7903 | |
7904 | ; lcr, lcgr | |
9a91a21f AS |
7905 | (define_insn "*neg<mode>2" |
7906 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7907 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7908 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
7909 | "" |
7910 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7911 | [(set_attr "op_type" "RR<E>") |
7912 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 7913 | |
b7d19263 | 7914 | (define_insn "*negdi2_31" |
9db1d521 HP |
7915 | [(set (match_operand:DI 0 "register_operand" "=d") |
7916 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 7917 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7918 | "!TARGET_ZARCH" |
b7d19263 AK |
7919 | "#") |
7920 | ||
7921 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
7922 | ||
7923 | ; Doing the twos complement separately on the SImode parts does an | |
7924 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
7925 | ; ... unless the +1 on the low part created an overflow. | |
7926 | ||
7927 | (define_split | |
7928 | [(set (match_operand:DI 0 "register_operand" "") | |
7929 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
7930 | (clobber (reg:CC CC_REGNUM))] | |
7931 | "!TARGET_ZARCH | |
7932 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
7933 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
7934 | && reload_completed" | |
26a89301 UW |
7935 | [(parallel |
7936 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 7937 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 7938 | (parallel |
ae156f85 | 7939 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
7940 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
7941 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
7942 | (set (pc) | |
ae156f85 | 7943 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
7944 | (pc) |
7945 | (label_ref (match_dup 6)))) | |
7946 | (parallel | |
7947 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 7948 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
7949 | (match_dup 6)] |
7950 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7951 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7952 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7953 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7954 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 7955 | |
b7d19263 AK |
7956 | ; Like above but first make a copy of the low part of the src operand |
7957 | ; since it might overlap with the high part of the destination. | |
7958 | ||
7959 | (define_split | |
7960 | [(set (match_operand:DI 0 "register_operand" "") | |
7961 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
7962 | (clobber (reg:CC CC_REGNUM))] | |
7963 | "!TARGET_ZARCH | |
7964 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
7965 | && reload_completed" | |
7966 | [; Make a backup of op5 first | |
7967 | (set (match_dup 4) (match_dup 5)) | |
7968 | ; Setting op2 here might clobber op5 | |
7969 | (parallel | |
7970 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
7971 | (clobber (reg:CC CC_REGNUM))]) | |
7972 | (parallel | |
7973 | [(set (reg:CCAP CC_REGNUM) | |
7974 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
7975 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
7976 | (set (pc) | |
7977 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
7978 | (pc) | |
7979 | (label_ref (match_dup 6)))) | |
7980 | (parallel | |
7981 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
7982 | (clobber (reg:CC CC_REGNUM))]) | |
7983 | (match_dup 6)] | |
7984 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7985 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7986 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7987 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7988 | operands[6] = gen_label_rtx ();") | |
7989 | ||
9db1d521 | 7990 | ; |
f5905b37 | 7991 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7992 | ; |
7993 | ||
f5905b37 | 7994 | (define_expand "neg<mode>2" |
9db1d521 | 7995 | [(parallel |
7b6baae1 AK |
7996 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7997 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7998 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7999 | "TARGET_HARD_FLOAT" |
8000 | "") | |
8001 | ||
43a09b63 | 8002 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8003 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8004 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8005 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8006 | (match_operand:BFP 2 "const0_operand" ""))) | |
8007 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8008 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8009 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8010 | "lc<xde>br\t%0,%1" |
26a89301 | 8011 | [(set_attr "op_type" "RRE") |
f5905b37 | 8012 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8013 | |
8014 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8015 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8016 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8017 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8018 | (match_operand:BFP 2 "const0_operand" ""))) | |
8019 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8020 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8021 | "lc<xde>br\t%0,%1" |
26a89301 | 8022 | [(set_attr "op_type" "RRE") |
f5905b37 | 8023 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8024 | |
85dae55a AK |
8025 | ; lcdfr |
8026 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8027 | [(set (match_operand:FP 0 "register_operand" "=f") |
8028 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8029 | "TARGET_DFP" |
85dae55a AK |
8030 | "lcdfr\t%0,%1" |
8031 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8032 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8033 | |
43a09b63 | 8034 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8035 | ; FIXME: wflcdb does not clobber cc |
f5905b37 | 8036 | (define_insn "*neg<mode>2" |
62d3f261 AK |
8037 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8038 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8039 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8040 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8041 | "@ |
8042 | lc<xde>br\t%0,%1 | |
8043 | wflcdb\t%0,%1" | |
8044 | [(set_attr "op_type" "RRE,VRR") | |
8045 | (set_attr "cpu_facility" "*,vec") | |
62d3f261 AK |
8046 | (set_attr "type" "fsimp<mode>,*") |
8047 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8048 | |
9db1d521 HP |
8049 | |
8050 | ;; | |
8051 | ;;- Absolute value instructions. | |
8052 | ;; | |
8053 | ||
8054 | ; | |
9a91a21f | 8055 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8056 | ; |
8057 | ||
26a89301 | 8058 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8059 | [(set (reg CC_REGNUM) |
26a89301 UW |
8060 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8061 | (match_operand:SI 1 "register_operand" "d") 0) | |
8062 | (const_int 32)) (const_int 32))) | |
8063 | (const_int 0))) | |
8064 | (set (match_operand:DI 0 "register_operand" "=d") | |
8065 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8066 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8067 | "lpgfr\t%0,%1" |
729e750f WG |
8068 | [(set_attr "op_type" "RRE") |
8069 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8070 | |
8071 | (define_insn "*absdi2_sign" | |
8072 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8073 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8074 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8075 | "TARGET_ZARCH" |
26a89301 | 8076 | "lpgfr\t%0,%1" |
729e750f WG |
8077 | [(set_attr "op_type" "RRE") |
8078 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8079 | |
43a09b63 | 8080 | ; lpr, lpgr |
9a91a21f | 8081 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8082 | [(set (reg CC_REGNUM) |
9a91a21f | 8083 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8084 | (const_int 0))) |
9a91a21f AS |
8085 | (set (match_operand:GPR 0 "register_operand" "=d") |
8086 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8087 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8088 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8089 | [(set_attr "op_type" "RR<E>") |
8090 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8091 | |
9381e3f1 | 8092 | ; lpr, lpgr |
9a91a21f | 8093 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8094 | [(set (reg CC_REGNUM) |
9a91a21f | 8095 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8096 | (const_int 0))) |
9a91a21f | 8097 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8098 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8099 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8100 | [(set_attr "op_type" "RR<E>") |
8101 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8102 | |
8103 | ; lpr, lpgr | |
9a91a21f AS |
8104 | (define_insn "abs<mode>2" |
8105 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8106 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8107 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8108 | "" |
9a91a21f | 8109 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8110 | [(set_attr "op_type" "RR<E>") |
8111 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8112 | |
9db1d521 | 8113 | ; |
f5905b37 | 8114 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8115 | ; |
8116 | ||
f5905b37 | 8117 | (define_expand "abs<mode>2" |
9db1d521 | 8118 | [(parallel |
7b6baae1 AK |
8119 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8120 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8121 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8122 | "TARGET_HARD_FLOAT" |
8123 | "") | |
8124 | ||
43a09b63 | 8125 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8126 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8127 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8128 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8129 | (match_operand:BFP 2 "const0_operand" ""))) | |
8130 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8131 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8132 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8133 | "lp<xde>br\t%0,%1" |
26a89301 | 8134 | [(set_attr "op_type" "RRE") |
f5905b37 | 8135 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8136 | |
8137 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8138 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8139 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8140 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8141 | (match_operand:BFP 2 "const0_operand" ""))) | |
8142 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8143 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8144 | "lp<xde>br\t%0,%1" |
26a89301 | 8145 | [(set_attr "op_type" "RRE") |
f5905b37 | 8146 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8147 | |
85dae55a AK |
8148 | ; lpdfr |
8149 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8150 | [(set (match_operand:FP 0 "register_operand" "=f") |
8151 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8152 | "TARGET_DFP" |
85dae55a AK |
8153 | "lpdfr\t%0,%1" |
8154 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8155 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8156 | |
43a09b63 | 8157 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8158 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8159 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8160 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8161 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8162 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8163 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8164 | "@ |
8165 | lp<xde>br\t%0,%1 | |
8166 | wflpdb\t%0,%1" | |
8167 | [(set_attr "op_type" "RRE,VRR") | |
8168 | (set_attr "cpu_facility" "*,vec") | |
62d3f261 AK |
8169 | (set_attr "type" "fsimp<mode>,*") |
8170 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8171 | |
9db1d521 | 8172 | |
3ef093a8 AK |
8173 | ;; |
8174 | ;;- Negated absolute value instructions | |
8175 | ;; | |
8176 | ||
8177 | ; | |
8178 | ; Integer | |
8179 | ; | |
8180 | ||
26a89301 | 8181 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8182 | [(set (reg CC_REGNUM) |
26a89301 UW |
8183 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8184 | (match_operand:SI 1 "register_operand" "d") 0) | |
8185 | (const_int 32)) (const_int 32)))) | |
8186 | (const_int 0))) | |
8187 | (set (match_operand:DI 0 "register_operand" "=d") | |
8188 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8189 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8190 | "lngfr\t%0,%1" |
729e750f WG |
8191 | [(set_attr "op_type" "RRE") |
8192 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8193 | |
26a89301 UW |
8194 | (define_insn "*negabsdi2_sign" |
8195 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8196 | (neg:DI (abs:DI (sign_extend:DI | |
8197 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8198 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8199 | "TARGET_ZARCH" |
26a89301 | 8200 | "lngfr\t%0,%1" |
729e750f WG |
8201 | [(set_attr "op_type" "RRE") |
8202 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8203 | |
43a09b63 | 8204 | ; lnr, lngr |
9a91a21f | 8205 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8206 | [(set (reg CC_REGNUM) |
9a91a21f | 8207 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8208 | (const_int 0))) |
9a91a21f AS |
8209 | (set (match_operand:GPR 0 "register_operand" "=d") |
8210 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8211 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8212 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8213 | [(set_attr "op_type" "RR<E>") |
8214 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8215 | |
8216 | ; lnr, lngr | |
9a91a21f | 8217 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8218 | [(set (reg CC_REGNUM) |
9a91a21f | 8219 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8220 | (const_int 0))) |
9a91a21f | 8221 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8222 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8223 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8224 | [(set_attr "op_type" "RR<E>") |
8225 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8226 | |
8227 | ; lnr, lngr | |
9a91a21f AS |
8228 | (define_insn "*negabs<mode>2" |
8229 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8230 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8231 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8232 | "" |
9a91a21f | 8233 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8234 | [(set_attr "op_type" "RR<E>") |
8235 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8236 | |
3ef093a8 AK |
8237 | ; |
8238 | ; Floating point | |
8239 | ; | |
8240 | ||
43a09b63 | 8241 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8242 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8243 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8244 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8245 | (match_operand:BFP 2 "const0_operand" ""))) | |
8246 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8247 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8248 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8249 | "ln<xde>br\t%0,%1" |
26a89301 | 8250 | [(set_attr "op_type" "RRE") |
f5905b37 | 8251 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8252 | |
8253 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8254 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8255 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8256 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8257 | (match_operand:BFP 2 "const0_operand" ""))) | |
8258 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8259 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8260 | "ln<xde>br\t%0,%1" |
26a89301 | 8261 | [(set_attr "op_type" "RRE") |
f5905b37 | 8262 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8263 | |
85dae55a AK |
8264 | ; lndfr |
8265 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8266 | [(set (match_operand:FP 0 "register_operand" "=f") |
8267 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8268 | "TARGET_DFP" |
85dae55a AK |
8269 | "lndfr\t%0,%1" |
8270 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8271 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8272 | |
43a09b63 | 8273 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8274 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8275 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8276 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8277 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8278 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8279 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8280 | "@ |
8281 | ln<xde>br\t%0,%1 | |
8282 | wflndb\t%0,%1" | |
8283 | [(set_attr "op_type" "RRE,VRR") | |
8284 | (set_attr "cpu_facility" "*,vec") | |
62d3f261 AK |
8285 | (set_attr "type" "fsimp<mode>,*") |
8286 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8287 | |
4023fb28 UW |
8288 | ;; |
8289 | ;;- Square root instructions. | |
8290 | ;; | |
8291 | ||
8292 | ; | |
f5905b37 | 8293 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8294 | ; |
8295 | ||
9381e3f1 | 8296 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8297 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8298 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8299 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8300 | "TARGET_HARD_FLOAT" |
4023fb28 | 8301 | "@ |
f61a2c7d | 8302 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8303 | sq<xde>b\t%0,%1 |
8304 | wfsqdb\t%v0,%v1" | |
8305 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8306 | (set_attr "type" "fsqrt<mode>") | |
62d3f261 AK |
8307 | (set_attr "cpu_facility" "*,*,vec") |
8308 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) | |
4023fb28 | 8309 | |
9db1d521 HP |
8310 | |
8311 | ;; | |
8312 | ;;- One complement instructions. | |
8313 | ;; | |
8314 | ||
8315 | ; | |
342cf42b | 8316 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8317 | ; |
c7453384 | 8318 | |
342cf42b | 8319 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8320 | [(parallel |
342cf42b AS |
8321 | [(set (match_operand:INT 0 "register_operand" "") |
8322 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8323 | (const_int -1))) | |
ae156f85 | 8324 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8325 | "" |
4023fb28 | 8326 | "") |
9db1d521 HP |
8327 | |
8328 | ||
ec24698e UW |
8329 | ;; |
8330 | ;; Find leftmost bit instructions. | |
8331 | ;; | |
8332 | ||
8333 | (define_expand "clzdi2" | |
8334 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8335 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8336 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8337 | { |
8338 | rtx insn, clz_equal; | |
8339 | rtx wide_reg = gen_reg_rtx (TImode); | |
8340 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
8341 | ||
8342 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8343 | ||
8344 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8345 | ||
9381e3f1 | 8346 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8347 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8348 | |
8349 | DONE; | |
8350 | }) | |
8351 | ||
8352 | (define_insn "clztidi2" | |
8353 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8354 | (ior:TI | |
9381e3f1 WG |
8355 | (ashift:TI |
8356 | (zero_extend:TI | |
ec24698e UW |
8357 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8358 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8359 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8360 | |
ec24698e UW |
8361 | (const_int 64)) |
8362 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8363 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 8364 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 8365 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 8366 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8367 | "flogr\t%0,%1" |
8368 | [(set_attr "op_type" "RRE")]) | |
8369 | ||
8370 | ||
9db1d521 HP |
8371 | ;; |
8372 | ;;- Rotate instructions. | |
8373 | ;; | |
8374 | ||
8375 | ; | |
9a91a21f | 8376 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8377 | ; |
8378 | ||
43a09b63 | 8379 | ; rll, rllg |
9a91a21f AS |
8380 | (define_insn "rotl<mode>3" |
8381 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8382 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 8383 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 8384 | "TARGET_CPU_ZARCH" |
9a91a21f | 8385 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 8386 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
8387 | (set_attr "atype" "reg") |
8388 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 8389 | |
43a09b63 | 8390 | ; rll, rllg |
4989e88a AK |
8391 | (define_insn "*rotl<mode>3_and" |
8392 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8393 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8394 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8395 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
8396 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
8397 | "rll<g>\t%0,%1,%Y2" | |
8398 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
8399 | (set_attr "atype" "reg") |
8400 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 8401 | |
9db1d521 HP |
8402 | |
8403 | ;; | |
f337b930 | 8404 | ;;- Shift instructions. |
9db1d521 | 8405 | ;; |
9db1d521 HP |
8406 | |
8407 | ; | |
1b48c8cc | 8408 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8409 | ; Left shifts and logical right shifts |
9db1d521 | 8410 | |
1b48c8cc AS |
8411 | (define_expand "<shift><mode>3" |
8412 | [(set (match_operand:DSI 0 "register_operand" "") | |
8413 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
8414 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
8415 | "" |
8416 | "") | |
8417 | ||
43a09b63 | 8418 | ; sldl, srdl |
f337b930 | 8419 | (define_insn "*<shift>di3_31" |
ac32b25e | 8420 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 8421 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8422 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9602b6a1 | 8423 | "!TARGET_ZARCH" |
f337b930 | 8424 | "s<lr>dl\t%0,%Y2" |
077dab3b | 8425 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8426 | (set_attr "atype" "reg") |
8427 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8428 | |
65b1d8ea | 8429 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 8430 | (define_insn "*<shift><mode>3" |
65b1d8ea AK |
8431 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8432 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8433 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] | |
1b48c8cc | 8434 | "" |
65b1d8ea AK |
8435 | "@ |
8436 | s<lr>l<g>\t%0,<1>%Y2 | |
8437 | s<lr>l<gk>\t%0,%1,%Y2" | |
8438 | [(set_attr "op_type" "RS<E>,RSY") | |
8439 | (set_attr "atype" "reg,reg") | |
8440 | (set_attr "cpu_facility" "*,z196") | |
8441 | (set_attr "z10prop" "z10_super_E1,*")]) | |
9db1d521 | 8442 | |
43a09b63 | 8443 | ; sldl, srdl |
4989e88a AK |
8444 | (define_insn "*<shift>di3_31_and" |
8445 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8446 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8447 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8448 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
9602b6a1 | 8449 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
8450 | "s<lr>dl\t%0,%Y2" |
8451 | [(set_attr "op_type" "RS") | |
8452 | (set_attr "atype" "reg")]) | |
8453 | ||
65b1d8ea | 8454 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 8455 | (define_insn "*<shift><mode>3_and" |
65b1d8ea AK |
8456 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8457 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8458 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8459 | (match_operand:SI 3 "const_int_operand" "n,n"))))] | |
1b48c8cc | 8460 | "(INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8461 | "@ |
8462 | s<lr>l<g>\t%0,<1>%Y2 | |
8463 | s<lr>l<gk>\t%0,%1,%Y2" | |
8464 | [(set_attr "op_type" "RS<E>,RSY") | |
8465 | (set_attr "atype" "reg,reg") | |
8466 | (set_attr "cpu_facility" "*,z196") | |
8467 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8468 | |
9db1d521 | 8469 | ; |
1b48c8cc | 8470 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8471 | ; Arithmetic right shifts |
9db1d521 | 8472 | |
1b48c8cc | 8473 | (define_expand "ashr<mode>3" |
9db1d521 | 8474 | [(parallel |
1b48c8cc AS |
8475 | [(set (match_operand:DSI 0 "register_operand" "") |
8476 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
8477 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 8478 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8479 | "" |
8480 | "") | |
8481 | ||
ecbe845e | 8482 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 8483 | [(set (reg CC_REGNUM) |
ac32b25e | 8484 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8485 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 8486 | (const_int 0))) |
ac32b25e | 8487 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e | 8488 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 8489 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 8490 | "srda\t%0,%Y2" |
077dab3b HP |
8491 | [(set_attr "op_type" "RS") |
8492 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
8493 | |
8494 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 8495 | [(set (reg CC_REGNUM) |
ac32b25e | 8496 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8497 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 8498 | (const_int 0))) |
ac32b25e | 8499 | (clobber (match_scratch:DI 0 "=d"))] |
9602b6a1 | 8500 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 8501 | "srda\t%0,%Y2" |
077dab3b HP |
8502 | [(set_attr "op_type" "RS") |
8503 | (set_attr "atype" "reg")]) | |
ecbe845e | 8504 | |
9db1d521 | 8505 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
8506 | [(set (match_operand:DI 0 "register_operand" "=d") |
8507 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 8508 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 8509 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8510 | "!TARGET_ZARCH" |
ac32b25e | 8511 | "srda\t%0,%Y2" |
077dab3b HP |
8512 | [(set_attr "op_type" "RS") |
8513 | (set_attr "atype" "reg")]) | |
c7453384 | 8514 | |
65b1d8ea | 8515 | ; sra, srag, srak |
1b48c8cc | 8516 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 8517 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8518 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8519 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 8520 | (const_int 0))) |
65b1d8ea | 8521 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc AS |
8522 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] |
8523 | "s390_match_ccmode(insn, CCSmode)" | |
65b1d8ea AK |
8524 | "@ |
8525 | sra<g>\t%0,<1>%Y2 | |
8526 | sra<gk>\t%0,%1,%Y2" | |
8527 | [(set_attr "op_type" "RS<E>,RSY") | |
8528 | (set_attr "atype" "reg,reg") | |
8529 | (set_attr "cpu_facility" "*,z196") | |
8530 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 8531 | |
65b1d8ea | 8532 | ; sra, srag, srak |
1b48c8cc | 8533 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 8534 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8535 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8536 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 8537 | (const_int 0))) |
65b1d8ea | 8538 | (clobber (match_scratch:GPR 0 "=d,d"))] |
1b48c8cc | 8539 | "s390_match_ccmode(insn, CCSmode)" |
65b1d8ea AK |
8540 | "@ |
8541 | sra<g>\t%0,<1>%Y2 | |
8542 | sra<gk>\t%0,%1,%Y2" | |
8543 | [(set_attr "op_type" "RS<E>,RSY") | |
8544 | (set_attr "atype" "reg,reg") | |
8545 | (set_attr "cpu_facility" "*,z196") | |
8546 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 8547 | |
43a09b63 | 8548 | ; sra, srag |
1b48c8cc | 8549 | (define_insn "*ashr<mode>3" |
65b1d8ea AK |
8550 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8551 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8552 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) | |
ae156f85 | 8553 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8554 | "" |
65b1d8ea AK |
8555 | "@ |
8556 | sra<g>\t%0,<1>%Y2 | |
8557 | sra<gk>\t%0,%1,%Y2" | |
8558 | [(set_attr "op_type" "RS<E>,RSY") | |
8559 | (set_attr "atype" "reg,reg") | |
8560 | (set_attr "cpu_facility" "*,z196") | |
8561 | (set_attr "z10prop" "z10_super_E1,*")]) | |
077dab3b | 8562 | |
9db1d521 | 8563 | |
4989e88a AK |
8564 | ; shift pattern with implicit ANDs |
8565 | ||
8566 | (define_insn "*ashrdi3_cc_31_and" | |
8567 | [(set (reg CC_REGNUM) | |
8568 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8569 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8570 | (match_operand:SI 3 "const_int_operand" "n"))) | |
8571 | (const_int 0))) | |
8572 | (set (match_operand:DI 0 "register_operand" "=d") | |
8573 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
9602b6a1 | 8574 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
8575 | && (INTVAL (operands[3]) & 63) == 63" |
8576 | "srda\t%0,%Y2" | |
8577 | [(set_attr "op_type" "RS") | |
8578 | (set_attr "atype" "reg")]) | |
8579 | ||
8580 | (define_insn "*ashrdi3_cconly_31_and" | |
8581 | [(set (reg CC_REGNUM) | |
8582 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8583 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8584 | (match_operand:SI 3 "const_int_operand" "n"))) | |
8585 | (const_int 0))) | |
8586 | (clobber (match_scratch:DI 0 "=d"))] | |
9602b6a1 | 8587 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
8588 | && (INTVAL (operands[3]) & 63) == 63" |
8589 | "srda\t%0,%Y2" | |
8590 | [(set_attr "op_type" "RS") | |
8591 | (set_attr "atype" "reg")]) | |
8592 | ||
8593 | (define_insn "*ashrdi3_31_and" | |
8594 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8595 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8596 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8597 | (match_operand:SI 3 "const_int_operand" "n")))) | |
8598 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8599 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
8600 | "srda\t%0,%Y2" |
8601 | [(set_attr "op_type" "RS") | |
8602 | (set_attr "atype" "reg")]) | |
8603 | ||
65b1d8ea | 8604 | ; sra, srag, srak |
1b48c8cc | 8605 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 8606 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8607 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8608 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8609 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 8610 | (const_int 0))) |
65b1d8ea | 8611 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc | 8612 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] |
4989e88a | 8613 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8614 | "@ |
8615 | sra<g>\t%0,<1>%Y2 | |
8616 | sra<gk>\t%0,%1,%Y2" | |
8617 | [(set_attr "op_type" "RS<E>,RSY") | |
8618 | (set_attr "atype" "reg,reg") | |
8619 | (set_attr "cpu_facility" "*,z196") | |
8620 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8621 | |
65b1d8ea | 8622 | ; sra, srag, srak |
1b48c8cc | 8623 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 8624 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8625 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8626 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8627 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 8628 | (const_int 0))) |
65b1d8ea | 8629 | (clobber (match_scratch:GPR 0 "=d,d"))] |
4989e88a | 8630 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8631 | "@ |
8632 | sra<g>\t%0,<1>%Y2 | |
8633 | sra<gk>\t%0,%1,%Y2" | |
8634 | [(set_attr "op_type" "RS<E>,RSY") | |
8635 | (set_attr "atype" "reg,reg") | |
8636 | (set_attr "cpu_facility" "*,z196") | |
8637 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8638 | |
65b1d8ea | 8639 | ; sra, srag, srak |
1b48c8cc | 8640 | (define_insn "*ashr<mode>3_and" |
65b1d8ea AK |
8641 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8642 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8643 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8644 | (match_operand:SI 3 "const_int_operand" "n,n")))) | |
4989e88a AK |
8645 | (clobber (reg:CC CC_REGNUM))] |
8646 | "(INTVAL (operands[3]) & 63) == 63" | |
65b1d8ea AK |
8647 | "@ |
8648 | sra<g>\t%0,<1>%Y2 | |
8649 | sra<gk>\t%0,%1,%Y2" | |
8650 | [(set_attr "op_type" "RS<E>,RSY") | |
8651 | (set_attr "atype" "reg,reg") | |
01496eca | 8652 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8653 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8654 | |
9db1d521 | 8655 | |
9db1d521 HP |
8656 | ;; |
8657 | ;; Branch instruction patterns. | |
8658 | ;; | |
8659 | ||
f90b7a5a | 8660 | (define_expand "cbranch<mode>4" |
fa77b251 | 8661 | [(set (pc) |
f90b7a5a PB |
8662 | (if_then_else (match_operator 0 "comparison_operator" |
8663 | [(match_operand:GPR 1 "register_operand" "") | |
8664 | (match_operand:GPR 2 "general_operand" "")]) | |
8665 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8666 | (pc)))] |
ba956982 | 8667 | "" |
f90b7a5a PB |
8668 | "s390_emit_jump (operands[3], |
8669 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8670 | DONE;") | |
8671 | ||
8672 | (define_expand "cbranch<mode>4" | |
8673 | [(set (pc) | |
8674 | (if_then_else (match_operator 0 "comparison_operator" | |
8675 | [(match_operand:FP 1 "register_operand" "") | |
8676 | (match_operand:FP 2 "general_operand" "")]) | |
8677 | (label_ref (match_operand 3 "" "")) | |
8678 | (pc)))] | |
8679 | "TARGET_HARD_FLOAT" | |
8680 | "s390_emit_jump (operands[3], | |
8681 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8682 | DONE;") | |
8683 | ||
8684 | (define_expand "cbranchcc4" | |
8685 | [(set (pc) | |
de6fba39 | 8686 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8687 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8688 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8689 | (label_ref (match_operand 3 "" "")) |
8690 | (pc)))] | |
de6fba39 UW |
8691 | "" |
8692 | "") | |
ba956982 | 8693 | |
9db1d521 HP |
8694 | |
8695 | ;; | |
8696 | ;;- Conditional jump instructions. | |
8697 | ;; | |
8698 | ||
6590e19a UW |
8699 | (define_insn "*cjump_64" |
8700 | [(set (pc) | |
8701 | (if_then_else | |
5a3fe9b6 AK |
8702 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8703 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8704 | (label_ref (match_operand 0 "" "")) |
8705 | (pc)))] | |
8706 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8707 | { |
13e58269 | 8708 | if (get_attr_length (insn) == 4) |
d40c829f | 8709 | return "j%C1\t%l0"; |
6590e19a | 8710 | else |
d40c829f | 8711 | return "jg%C1\t%l0"; |
6590e19a UW |
8712 | } |
8713 | [(set_attr "op_type" "RI") | |
8714 | (set_attr "type" "branch") | |
8715 | (set (attr "length") | |
8716 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8717 | (const_int 4) (const_int 6)))]) | |
8718 | ||
8719 | (define_insn "*cjump_31" | |
8720 | [(set (pc) | |
8721 | (if_then_else | |
5a3fe9b6 AK |
8722 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8723 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8724 | (label_ref (match_operand 0 "" "")) |
8725 | (pc)))] | |
8726 | "!TARGET_CPU_ZARCH" | |
8727 | { | |
8d933e31 AS |
8728 | gcc_assert (get_attr_length (insn) == 4); |
8729 | return "j%C1\t%l0"; | |
10bbf137 | 8730 | } |
9db1d521 | 8731 | [(set_attr "op_type" "RI") |
077dab3b | 8732 | (set_attr "type" "branch") |
13e58269 | 8733 | (set (attr "length") |
d7f99b2c | 8734 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8735 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8736 | (const_int 4) (const_int 6)) | |
8737 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8738 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8739 | |
f314b9b1 | 8740 | (define_insn "*cjump_long" |
6590e19a UW |
8741 | [(set (pc) |
8742 | (if_then_else | |
ae156f85 | 8743 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8744 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8745 | (pc)))] |
9db1d521 | 8746 | "" |
f314b9b1 UW |
8747 | { |
8748 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8749 | return "b%C1r\t%0"; |
f314b9b1 | 8750 | else |
d40c829f | 8751 | return "b%C1\t%a0"; |
10bbf137 | 8752 | } |
c7453384 | 8753 | [(set (attr "op_type") |
f314b9b1 UW |
8754 | (if_then_else (match_operand 0 "register_operand" "") |
8755 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 8756 | (set_attr "type" "branch") |
077dab3b | 8757 | (set_attr "atype" "agen")]) |
9db1d521 | 8758 | |
177bc204 RS |
8759 | ;; A conditional return instruction. |
8760 | (define_insn "*c<code>" | |
8761 | [(set (pc) | |
8762 | (if_then_else | |
8763 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8764 | (ANY_RETURN) | |
8765 | (pc)))] | |
8766 | "s390_can_use_<code>_insn ()" | |
8767 | "b%C0r\t%%r14" | |
8768 | [(set_attr "op_type" "RR") | |
8769 | (set_attr "type" "jsr") | |
8770 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8771 | |
8772 | ;; | |
8773 | ;;- Negated conditional jump instructions. | |
8774 | ;; | |
8775 | ||
6590e19a UW |
8776 | (define_insn "*icjump_64" |
8777 | [(set (pc) | |
8778 | (if_then_else | |
ae156f85 | 8779 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8780 | (pc) |
8781 | (label_ref (match_operand 0 "" ""))))] | |
8782 | "TARGET_CPU_ZARCH" | |
c7453384 | 8783 | { |
13e58269 | 8784 | if (get_attr_length (insn) == 4) |
d40c829f | 8785 | return "j%D1\t%l0"; |
6590e19a | 8786 | else |
d40c829f | 8787 | return "jg%D1\t%l0"; |
6590e19a UW |
8788 | } |
8789 | [(set_attr "op_type" "RI") | |
8790 | (set_attr "type" "branch") | |
8791 | (set (attr "length") | |
8792 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8793 | (const_int 4) (const_int 6)))]) | |
8794 | ||
8795 | (define_insn "*icjump_31" | |
8796 | [(set (pc) | |
8797 | (if_then_else | |
ae156f85 | 8798 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8799 | (pc) |
8800 | (label_ref (match_operand 0 "" ""))))] | |
8801 | "!TARGET_CPU_ZARCH" | |
8802 | { | |
8d933e31 AS |
8803 | gcc_assert (get_attr_length (insn) == 4); |
8804 | return "j%D1\t%l0"; | |
10bbf137 | 8805 | } |
9db1d521 | 8806 | [(set_attr "op_type" "RI") |
077dab3b | 8807 | (set_attr "type" "branch") |
13e58269 | 8808 | (set (attr "length") |
d7f99b2c | 8809 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8810 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8811 | (const_int 4) (const_int 6)) | |
8812 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8813 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8814 | |
f314b9b1 | 8815 | (define_insn "*icjump_long" |
6590e19a UW |
8816 | [(set (pc) |
8817 | (if_then_else | |
ae156f85 | 8818 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 8819 | (pc) |
4fe6dea8 | 8820 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 8821 | "" |
f314b9b1 UW |
8822 | { |
8823 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8824 | return "b%D1r\t%0"; |
f314b9b1 | 8825 | else |
d40c829f | 8826 | return "b%D1\t%a0"; |
10bbf137 | 8827 | } |
c7453384 | 8828 | [(set (attr "op_type") |
f314b9b1 UW |
8829 | (if_then_else (match_operand 0 "register_operand" "") |
8830 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8831 | (set_attr "type" "branch") |
8832 | (set_attr "atype" "agen")]) | |
9db1d521 | 8833 | |
4456530d HP |
8834 | ;; |
8835 | ;;- Trap instructions. | |
8836 | ;; | |
8837 | ||
8838 | (define_insn "trap" | |
8839 | [(trap_if (const_int 1) (const_int 0))] | |
8840 | "" | |
d40c829f | 8841 | "j\t.+2" |
6590e19a | 8842 | [(set_attr "op_type" "RI") |
077dab3b | 8843 | (set_attr "type" "branch")]) |
4456530d | 8844 | |
f90b7a5a PB |
8845 | (define_expand "ctrap<mode>4" |
8846 | [(trap_if (match_operator 0 "comparison_operator" | |
8847 | [(match_operand:GPR 1 "register_operand" "") | |
8848 | (match_operand:GPR 2 "general_operand" "")]) | |
8849 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 8850 | "" |
f90b7a5a PB |
8851 | { |
8852 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8853 | operands[1], operands[2]); | |
8854 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8855 | DONE; | |
8856 | }) | |
8857 | ||
8858 | (define_expand "ctrap<mode>4" | |
8859 | [(trap_if (match_operator 0 "comparison_operator" | |
8860 | [(match_operand:FP 1 "register_operand" "") | |
8861 | (match_operand:FP 2 "general_operand" "")]) | |
8862 | (match_operand 3 "const0_operand" ""))] | |
8863 | "" | |
8864 | { | |
8865 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8866 | operands[1], operands[2]); | |
8867 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8868 | DONE; | |
8869 | }) | |
4456530d | 8870 | |
f90b7a5a PB |
8871 | (define_insn "condtrap" |
8872 | [(trap_if (match_operator 0 "s390_comparison" | |
8873 | [(match_operand 1 "cc_reg_operand" "c") | |
8874 | (const_int 0)]) | |
4456530d HP |
8875 | (const_int 0))] |
8876 | "" | |
d40c829f | 8877 | "j%C0\t.+2"; |
077dab3b HP |
8878 | [(set_attr "op_type" "RI") |
8879 | (set_attr "type" "branch")]) | |
9db1d521 | 8880 | |
963fc8d0 AK |
8881 | ; crt, cgrt, cit, cgit |
8882 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
8883 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
8884 | [(match_operand:GPR 1 "register_operand" "d,d") | |
8885 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
8886 | (const_int 0))] | |
8887 | "TARGET_Z10" | |
8888 | "@ | |
8889 | c<g>rt%C0\t%1,%2 | |
8890 | c<g>it%C0\t%1,%h2" | |
8891 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 8892 | (set_attr "type" "branch") |
729e750f | 8893 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 8894 | |
22ac2c2f | 8895 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
8896 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
8897 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
22ac2c2f AK |
8898 | [(match_operand:GPR 1 "register_operand" "d,d, d") |
8899 | (match_operand:GPR 2 "general_operand" "d,D,RT")]) | |
963fc8d0 AK |
8900 | (const_int 0))] |
8901 | "TARGET_Z10" | |
8902 | "@ | |
8903 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
8904 | cl<gf>it%C0\t%1,%x2 |
8905 | cl<g>t%C0\t%1,%2" | |
8906 | [(set_attr "op_type" "RRF,RIE,RSY") | |
8907 | (set_attr "type" "branch") | |
8908 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
8909 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
8910 | ||
8911 | ; lat, lgat | |
8912 | (define_insn "*load_and_trap<mode>" | |
8913 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") | |
8914 | (const_int 0)) | |
8915 | (const_int 0)) | |
8916 | (set (match_operand:GPR 1 "register_operand" "=d") | |
8917 | (match_dup 0))] | |
8918 | "TARGET_ZEC12" | |
8919 | "l<g>at\t%1,%0" | |
8920 | [(set_attr "op_type" "RXY")]) | |
8921 | ||
963fc8d0 | 8922 | |
9db1d521 | 8923 | ;; |
0a3bdf9d | 8924 | ;;- Loop instructions. |
9db1d521 | 8925 | ;; |
0a3bdf9d UW |
8926 | ;; This is all complicated by the fact that since this is a jump insn |
8927 | ;; we must handle our own output reloads. | |
c7453384 | 8928 | |
f1149235 AK |
8929 | ;; branch on index |
8930 | ||
8931 | ; This splitter will be matched by combine and has to add the 2 moves | |
8932 | ; necessary to load the compare and the increment values into a | |
8933 | ; register pair as needed by brxle. | |
8934 | ||
8935 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
8936 | [(set (pc) | |
8937 | (if_then_else | |
8938 | (match_operator 6 "s390_brx_operator" | |
8939 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
8940 | (match_operand:GPR 2 "general_operand" "")) | |
8941 | (match_operand:GPR 3 "register_operand" "")]) | |
8942 | (label_ref (match_operand 0 "" "")) | |
8943 | (pc))) | |
8944 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
8945 | (plus:GPR (match_dup 1) (match_dup 2))) | |
8946 | (clobber (match_scratch:GPR 5 ""))] | |
8947 | "TARGET_CPU_ZARCH" | |
8948 | "#" | |
8949 | "!reload_completed && !reload_in_progress" | |
8950 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
8951 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
8952 | (parallel [(set (pc) | |
8953 | (if_then_else | |
8954 | (match_op_dup 6 | |
8955 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
8956 | (match_dup 8)]) | |
8957 | (label_ref (match_dup 0)) | |
8958 | (pc))) | |
8959 | (set (match_dup 4) | |
8960 | (plus:GPR (match_dup 1) (match_dup 7))) | |
8961 | (clobber (match_dup 5)) | |
8962 | (clobber (reg:CC CC_REGNUM))])] | |
8963 | { | |
8964 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
8965 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
8966 | gen_highpart (word_mode, dreg)); | |
8967 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
8968 | gen_lowpart (word_mode, dreg)); | |
8969 | }) | |
8970 | ||
8971 | ; brxlg, brxhg | |
8972 | ||
8973 | (define_insn_and_split "*brxg_64bit" | |
8974 | [(set (pc) | |
8975 | (if_then_else | |
8976 | (match_operator 5 "s390_brx_operator" | |
8977 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
8978 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
8979 | (subreg:DI (match_dup 2) 8)]) | |
8980 | (label_ref (match_operand 0 "" "")) | |
8981 | (pc))) | |
8982 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
8983 | (plus:DI (match_dup 1) | |
8984 | (subreg:DI (match_dup 2) 0))) | |
8985 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
8986 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8987 | "TARGET_ZARCH" |
f1149235 AK |
8988 | { |
8989 | if (which_alternative != 0) | |
8990 | return "#"; | |
8991 | else if (get_attr_length (insn) == 6) | |
8992 | return "brx%E5g\t%1,%2,%l0"; | |
8993 | else | |
8994 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
8995 | } | |
8996 | "&& reload_completed | |
8997 | && (!REG_P (operands[3]) | |
8998 | || !rtx_equal_p (operands[1], operands[3]))" | |
8999 | [(set (match_dup 4) (match_dup 1)) | |
9000 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9001 | (clobber (reg:CC CC_REGNUM))]) | |
9002 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9003 | (set (match_dup 3) (match_dup 4)) | |
9004 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9005 | (label_ref (match_dup 0)) | |
9006 | (pc)))] | |
9007 | "" | |
9008 | [(set_attr "op_type" "RIE") | |
9009 | (set_attr "type" "branch") | |
9010 | (set (attr "length") | |
9011 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9012 | (const_int 6) (const_int 16)))]) | |
9013 | ||
9014 | ; brxle, brxh | |
9015 | ||
9016 | (define_insn_and_split "*brx_64bit" | |
9017 | [(set (pc) | |
9018 | (if_then_else | |
9019 | (match_operator 5 "s390_brx_operator" | |
9020 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9021 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9022 | (subreg:SI (match_dup 2) 12)]) | |
9023 | (label_ref (match_operand 0 "" "")) | |
9024 | (pc))) | |
9025 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9026 | (plus:SI (match_dup 1) | |
9027 | (subreg:SI (match_dup 2) 4))) | |
9028 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9029 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9030 | "TARGET_ZARCH" |
f1149235 AK |
9031 | { |
9032 | if (which_alternative != 0) | |
9033 | return "#"; | |
9034 | else if (get_attr_length (insn) == 6) | |
9035 | return "brx%C5\t%1,%2,%l0"; | |
9036 | else | |
9037 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9038 | } | |
9039 | "&& reload_completed | |
9040 | && (!REG_P (operands[3]) | |
9041 | || !rtx_equal_p (operands[1], operands[3]))" | |
9042 | [(set (match_dup 4) (match_dup 1)) | |
9043 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9044 | (clobber (reg:CC CC_REGNUM))]) | |
9045 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9046 | (set (match_dup 3) (match_dup 4)) | |
9047 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9048 | (label_ref (match_dup 0)) | |
9049 | (pc)))] | |
9050 | "" | |
9051 | [(set_attr "op_type" "RSI") | |
9052 | (set_attr "type" "branch") | |
9053 | (set (attr "length") | |
9054 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9055 | (const_int 6) (const_int 14)))]) | |
9056 | ||
9057 | ; brxle, brxh | |
9058 | ||
9059 | (define_insn_and_split "*brx_31bit" | |
9060 | [(set (pc) | |
9061 | (if_then_else | |
9062 | (match_operator 5 "s390_brx_operator" | |
9063 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9064 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9065 | (subreg:SI (match_dup 2) 4)]) | |
9066 | (label_ref (match_operand 0 "" "")) | |
9067 | (pc))) | |
9068 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9069 | (plus:SI (match_dup 1) | |
9070 | (subreg:SI (match_dup 2) 0))) | |
9071 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9072 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9073 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
9074 | { |
9075 | if (which_alternative != 0) | |
9076 | return "#"; | |
9077 | else if (get_attr_length (insn) == 6) | |
9078 | return "brx%C5\t%1,%2,%l0"; | |
9079 | else | |
9080 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9081 | } | |
9082 | "&& reload_completed | |
9083 | && (!REG_P (operands[3]) | |
9084 | || !rtx_equal_p (operands[1], operands[3]))" | |
9085 | [(set (match_dup 4) (match_dup 1)) | |
9086 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9087 | (clobber (reg:CC CC_REGNUM))]) | |
9088 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9089 | (set (match_dup 3) (match_dup 4)) | |
9090 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9091 | (label_ref (match_dup 0)) | |
9092 | (pc)))] | |
9093 | "" | |
9094 | [(set_attr "op_type" "RSI") | |
9095 | (set_attr "type" "branch") | |
9096 | (set (attr "length") | |
9097 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9098 | (const_int 6) (const_int 14)))]) | |
9099 | ||
9100 | ||
9101 | ;; branch on count | |
9102 | ||
0a3bdf9d UW |
9103 | (define_expand "doloop_end" |
9104 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9105 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9106 | "" |
0a3bdf9d | 9107 | { |
6590e19a | 9108 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 9109 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 9110 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 9111 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9112 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9113 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9114 | else |
9115 | FAIL; | |
9116 | ||
9117 | DONE; | |
10bbf137 | 9118 | }) |
0a3bdf9d | 9119 | |
6590e19a | 9120 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9121 | [(set (pc) |
9122 | (if_then_else | |
7e665d18 | 9123 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9124 | (const_int 1)) |
9125 | (label_ref (match_operand 0 "" "")) | |
9126 | (pc))) | |
7e665d18 | 9127 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9128 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9129 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9130 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9131 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9132 | { |
9133 | if (which_alternative != 0) | |
10bbf137 | 9134 | return "#"; |
0a3bdf9d | 9135 | else if (get_attr_length (insn) == 4) |
d40c829f | 9136 | return "brct\t%1,%l0"; |
6590e19a | 9137 | else |
545d16ff | 9138 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9139 | } |
9140 | "&& reload_completed | |
9141 | && (! REG_P (operands[2]) | |
9142 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9143 | [(set (match_dup 3) (match_dup 1)) |
9144 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9145 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9146 | (const_int 0))) | |
9147 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9148 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9149 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9150 | (label_ref (match_dup 0)) |
9151 | (pc)))] | |
9152 | "" | |
9153 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9154 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9155 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9156 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9157 | (set_attr "type" "branch") |
9158 | (set (attr "length") | |
9159 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9160 | (const_int 4) (const_int 10)))]) | |
9161 | ||
9162 | (define_insn_and_split "doloop_si31" | |
9163 | [(set (pc) | |
9164 | (if_then_else | |
7e665d18 | 9165 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
9166 | (const_int 1)) |
9167 | (label_ref (match_operand 0 "" "")) | |
9168 | (pc))) | |
7e665d18 | 9169 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 9170 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9171 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9172 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
9173 | "!TARGET_CPU_ZARCH" |
9174 | { | |
9175 | if (which_alternative != 0) | |
9176 | return "#"; | |
9177 | else if (get_attr_length (insn) == 4) | |
9178 | return "brct\t%1,%l0"; | |
0a3bdf9d | 9179 | else |
8d933e31 | 9180 | gcc_unreachable (); |
10bbf137 | 9181 | } |
6590e19a UW |
9182 | "&& reload_completed |
9183 | && (! REG_P (operands[2]) | |
9184 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9185 | [(set (match_dup 3) (match_dup 1)) |
9186 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9187 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9188 | (const_int 0))) | |
9189 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9190 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9191 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9192 | (label_ref (match_dup 0)) |
9193 | (pc)))] | |
9194 | "" | |
0a3bdf9d | 9195 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
9196 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9197 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9198 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 9199 | (set_attr "type" "branch") |
0a3bdf9d | 9200 | (set (attr "length") |
d7f99b2c | 9201 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9202 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9203 | (const_int 4) (const_int 6)) | |
9204 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9205 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9206 | |
0a3bdf9d UW |
9207 | (define_insn "*doloop_si_long" |
9208 | [(set (pc) | |
9209 | (if_then_else | |
7e665d18 | 9210 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 9211 | (const_int 1)) |
4fe6dea8 | 9212 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 9213 | (pc))) |
7e665d18 | 9214 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 9215 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9216 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 9217 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9218 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9219 | { |
9220 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9221 | return "bctr\t%1,%0"; |
0a3bdf9d | 9222 | else |
d40c829f | 9223 | return "bct\t%1,%a0"; |
10bbf137 | 9224 | } |
c7453384 | 9225 | [(set (attr "op_type") |
0a3bdf9d UW |
9226 | (if_then_else (match_operand 0 "register_operand" "") |
9227 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9228 | (set_attr "type" "branch") |
729e750f | 9229 | (set_attr "atype" "agen") |
65b1d8ea AK |
9230 | (set_attr "z10prop" "z10_c") |
9231 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 9232 | |
6590e19a | 9233 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9234 | [(set (pc) |
9235 | (if_then_else | |
7e665d18 | 9236 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9237 | (const_int 1)) |
9238 | (label_ref (match_operand 0 "" "")) | |
9239 | (pc))) | |
7e665d18 | 9240 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9241 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9242 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9243 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9244 | "TARGET_ZARCH" |
0a3bdf9d UW |
9245 | { |
9246 | if (which_alternative != 0) | |
10bbf137 | 9247 | return "#"; |
0a3bdf9d | 9248 | else if (get_attr_length (insn) == 4) |
d40c829f | 9249 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9250 | else |
545d16ff | 9251 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9252 | } |
6590e19a | 9253 | "&& reload_completed |
0a3bdf9d UW |
9254 | && (! REG_P (operands[2]) |
9255 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9256 | [(set (match_dup 3) (match_dup 1)) |
9257 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9258 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9259 | (const_int 0))) | |
9260 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9261 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9262 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9263 | (label_ref (match_dup 0)) |
0a3bdf9d | 9264 | (pc)))] |
6590e19a UW |
9265 | "" |
9266 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9267 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9268 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9269 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9270 | (set_attr "type" "branch") |
9271 | (set (attr "length") | |
9272 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9273 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9274 | |
9275 | ;; | |
9276 | ;;- Unconditional jump instructions. | |
9277 | ;; | |
9278 | ||
9279 | ; | |
9280 | ; jump instruction pattern(s). | |
9281 | ; | |
9282 | ||
6590e19a UW |
9283 | (define_expand "jump" |
9284 | [(match_operand 0 "" "")] | |
9db1d521 | 9285 | "" |
6590e19a UW |
9286 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9287 | ||
9288 | (define_insn "*jump64" | |
9289 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9290 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9291 | { |
13e58269 | 9292 | if (get_attr_length (insn) == 4) |
d40c829f | 9293 | return "j\t%l0"; |
6590e19a | 9294 | else |
d40c829f | 9295 | return "jg\t%l0"; |
6590e19a UW |
9296 | } |
9297 | [(set_attr "op_type" "RI") | |
9298 | (set_attr "type" "branch") | |
9299 | (set (attr "length") | |
9300 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9301 | (const_int 4) (const_int 6)))]) | |
9302 | ||
9303 | (define_insn "*jump31" | |
9304 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9305 | "!TARGET_CPU_ZARCH" | |
9306 | { | |
8d933e31 AS |
9307 | gcc_assert (get_attr_length (insn) == 4); |
9308 | return "j\t%l0"; | |
10bbf137 | 9309 | } |
9db1d521 | 9310 | [(set_attr "op_type" "RI") |
077dab3b | 9311 | (set_attr "type" "branch") |
13e58269 | 9312 | (set (attr "length") |
d7f99b2c | 9313 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9314 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9315 | (const_int 4) (const_int 6)) | |
9316 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9317 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
9318 | |
9319 | ; | |
9320 | ; indirect-jump instruction pattern(s). | |
9321 | ; | |
9322 | ||
9323 | (define_insn "indirect_jump" | |
4fe6dea8 | 9324 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 9325 | "" |
f314b9b1 UW |
9326 | { |
9327 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9328 | return "br\t%0"; |
f314b9b1 | 9329 | else |
d40c829f | 9330 | return "b\t%a0"; |
10bbf137 | 9331 | } |
c7453384 | 9332 | [(set (attr "op_type") |
f314b9b1 UW |
9333 | (if_then_else (match_operand 0 "register_operand" "") |
9334 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9335 | (set_attr "type" "branch") |
729e750f | 9336 | (set_attr "atype" "agen")]) |
9db1d521 HP |
9337 | |
9338 | ; | |
f314b9b1 | 9339 | ; casesi instruction pattern(s). |
9db1d521 HP |
9340 | ; |
9341 | ||
f314b9b1 | 9342 | (define_insn "casesi_jump" |
4fe6dea8 | 9343 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 9344 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 9345 | "" |
9db1d521 | 9346 | { |
f314b9b1 | 9347 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9348 | return "br\t%0"; |
f314b9b1 | 9349 | else |
d40c829f | 9350 | return "b\t%a0"; |
10bbf137 | 9351 | } |
c7453384 | 9352 | [(set (attr "op_type") |
f314b9b1 UW |
9353 | (if_then_else (match_operand 0 "register_operand" "") |
9354 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9355 | (set_attr "type" "branch") |
9356 | (set_attr "atype" "agen")]) | |
9db1d521 | 9357 | |
f314b9b1 UW |
9358 | (define_expand "casesi" |
9359 | [(match_operand:SI 0 "general_operand" "") | |
9360 | (match_operand:SI 1 "general_operand" "") | |
9361 | (match_operand:SI 2 "general_operand" "") | |
9362 | (label_ref (match_operand 3 "" "")) | |
9363 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9364 | "" |
f314b9b1 UW |
9365 | { |
9366 | rtx index = gen_reg_rtx (SImode); | |
9367 | rtx base = gen_reg_rtx (Pmode); | |
9368 | rtx target = gen_reg_rtx (Pmode); | |
9369 | ||
9370 | emit_move_insn (index, operands[0]); | |
9371 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9372 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9373 | operands[4]); |
f314b9b1 UW |
9374 | |
9375 | if (Pmode != SImode) | |
9376 | index = convert_to_mode (Pmode, index, 1); | |
9377 | if (GET_CODE (index) != REG) | |
9378 | index = copy_to_mode_reg (Pmode, index); | |
9379 | ||
9380 | if (TARGET_64BIT) | |
9381 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9382 | else | |
a556fd39 | 9383 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9384 | |
f314b9b1 UW |
9385 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9386 | ||
542a8afa | 9387 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9388 | emit_move_insn (target, index); |
9389 | ||
9390 | if (flag_pic) | |
9391 | target = gen_rtx_PLUS (Pmode, base, target); | |
9392 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9393 | ||
9394 | DONE; | |
10bbf137 | 9395 | }) |
9db1d521 HP |
9396 | |
9397 | ||
9398 | ;; | |
9399 | ;;- Jump to subroutine. | |
9400 | ;; | |
9401 | ;; | |
9402 | ||
9403 | ; | |
9404 | ; untyped call instruction pattern(s). | |
9405 | ; | |
9406 | ||
9407 | ;; Call subroutine returning any type. | |
9408 | (define_expand "untyped_call" | |
9409 | [(parallel [(call (match_operand 0 "" "") | |
9410 | (const_int 0)) | |
9411 | (match_operand 1 "" "") | |
9412 | (match_operand 2 "" "")])] | |
9413 | "" | |
9db1d521 HP |
9414 | { |
9415 | int i; | |
9416 | ||
9417 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9418 | ||
9419 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9420 | { | |
9421 | rtx set = XVECEXP (operands[2], 0, i); | |
9422 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9423 | } | |
9424 | ||
9425 | /* The optimizer does not know that the call sets the function value | |
9426 | registers we stored in the result block. We avoid problems by | |
9427 | claiming that all hard registers are used and clobbered at this | |
9428 | point. */ | |
9429 | emit_insn (gen_blockage ()); | |
9430 | ||
9431 | DONE; | |
10bbf137 | 9432 | }) |
9db1d521 HP |
9433 | |
9434 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9435 | ;; all of memory. This blocks insns from being moved across this point. | |
9436 | ||
9437 | (define_insn "blockage" | |
10bbf137 | 9438 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9439 | "" |
4023fb28 | 9440 | "" |
d5869ca0 UW |
9441 | [(set_attr "type" "none") |
9442 | (set_attr "length" "0")]) | |
4023fb28 | 9443 | |
9db1d521 | 9444 | ; |
ed9676cf | 9445 | ; sibcall patterns |
9db1d521 HP |
9446 | ; |
9447 | ||
ed9676cf | 9448 | (define_expand "sibcall" |
44b8152b | 9449 | [(call (match_operand 0 "" "") |
ed9676cf | 9450 | (match_operand 1 "" ""))] |
9db1d521 | 9451 | "" |
9db1d521 | 9452 | { |
ed9676cf AK |
9453 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9454 | DONE; | |
9455 | }) | |
9db1d521 | 9456 | |
ed9676cf | 9457 | (define_insn "*sibcall_br" |
ae156f85 | 9458 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9459 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9460 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9461 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
9462 | "br\t%%r1" | |
9463 | [(set_attr "op_type" "RR") | |
9464 | (set_attr "type" "branch") | |
9465 | (set_attr "atype" "agen")]) | |
9db1d521 | 9466 | |
ed9676cf AK |
9467 | (define_insn "*sibcall_brc" |
9468 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9469 | (match_operand 1 "const_int_operand" "n"))] | |
9470 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9471 | "j\t%0" | |
9472 | [(set_attr "op_type" "RI") | |
9473 | (set_attr "type" "branch")]) | |
9db1d521 | 9474 | |
ed9676cf AK |
9475 | (define_insn "*sibcall_brcl" |
9476 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9477 | (match_operand 1 "const_int_operand" "n"))] | |
9478 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9479 | "jg\t%0" | |
9480 | [(set_attr "op_type" "RIL") | |
9481 | (set_attr "type" "branch")]) | |
44b8152b | 9482 | |
ed9676cf AK |
9483 | ; |
9484 | ; sibcall_value patterns | |
9485 | ; | |
9e8327e3 | 9486 | |
ed9676cf AK |
9487 | (define_expand "sibcall_value" |
9488 | [(set (match_operand 0 "" "") | |
9489 | (call (match_operand 1 "" "") | |
9490 | (match_operand 2 "" "")))] | |
9491 | "" | |
9492 | { | |
9493 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9494 | DONE; |
10bbf137 | 9495 | }) |
9db1d521 | 9496 | |
ed9676cf AK |
9497 | (define_insn "*sibcall_value_br" |
9498 | [(set (match_operand 0 "" "") | |
ae156f85 | 9499 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9500 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9501 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9502 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
9503 | "br\t%%r1" | |
9504 | [(set_attr "op_type" "RR") | |
9505 | (set_attr "type" "branch") | |
9506 | (set_attr "atype" "agen")]) | |
9507 | ||
9508 | (define_insn "*sibcall_value_brc" | |
9509 | [(set (match_operand 0 "" "") | |
9510 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9511 | (match_operand 2 "const_int_operand" "n")))] | |
9512 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9513 | "j\t%1" | |
9514 | [(set_attr "op_type" "RI") | |
9515 | (set_attr "type" "branch")]) | |
9516 | ||
9517 | (define_insn "*sibcall_value_brcl" | |
9518 | [(set (match_operand 0 "" "") | |
9519 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9520 | (match_operand 2 "const_int_operand" "n")))] | |
9521 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9522 | "jg\t%1" | |
9523 | [(set_attr "op_type" "RIL") | |
9524 | (set_attr "type" "branch")]) | |
9525 | ||
9526 | ||
9527 | ; | |
9528 | ; call instruction pattern(s). | |
9529 | ; | |
9530 | ||
9531 | (define_expand "call" | |
9532 | [(call (match_operand 0 "" "") | |
9533 | (match_operand 1 "" "")) | |
9534 | (use (match_operand 2 "" ""))] | |
44b8152b | 9535 | "" |
ed9676cf | 9536 | { |
2f7e5a0d | 9537 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9538 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9539 | DONE; | |
9540 | }) | |
44b8152b | 9541 | |
9e8327e3 UW |
9542 | (define_insn "*bras" |
9543 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9544 | (match_operand 1 "const_int_operand" "n")) | |
9545 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9546 | "!SIBLING_CALL_P (insn) |
9547 | && TARGET_SMALL_EXEC | |
ed9676cf | 9548 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9549 | "bras\t%2,%0" |
9db1d521 | 9550 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9551 | (set_attr "type" "jsr") |
9552 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9553 | |
9e8327e3 UW |
9554 | (define_insn "*brasl" |
9555 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9556 | (match_operand 1 "const_int_operand" "n")) | |
9557 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9558 | "!SIBLING_CALL_P (insn) |
9559 | && TARGET_CPU_ZARCH | |
ed9676cf | 9560 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9561 | "brasl\t%2,%0" |
9562 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9563 | (set_attr "type" "jsr") |
9564 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9565 | |
9e8327e3 | 9566 | (define_insn "*basr" |
4fe6dea8 | 9567 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
9568 | (match_operand 1 "const_int_operand" "n")) |
9569 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 9570 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9571 | { |
9572 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9573 | return "basr\t%2,%0"; | |
9574 | else | |
9575 | return "bas\t%2,%a0"; | |
9576 | } | |
9577 | [(set (attr "op_type") | |
9578 | (if_then_else (match_operand 0 "register_operand" "") | |
9579 | (const_string "RR") (const_string "RX"))) | |
9580 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9581 | (set_attr "atype" "agen") |
9582 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
9583 | |
9584 | ; | |
9585 | ; call_value instruction pattern(s). | |
9586 | ; | |
9587 | ||
9588 | (define_expand "call_value" | |
44b8152b UW |
9589 | [(set (match_operand 0 "" "") |
9590 | (call (match_operand 1 "" "") | |
9591 | (match_operand 2 "" ""))) | |
9592 | (use (match_operand 3 "" ""))] | |
9db1d521 | 9593 | "" |
9db1d521 | 9594 | { |
2f7e5a0d | 9595 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 9596 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 9597 | DONE; |
10bbf137 | 9598 | }) |
9db1d521 | 9599 | |
9e8327e3 | 9600 | (define_insn "*bras_r" |
c19ec8f9 | 9601 | [(set (match_operand 0 "" "") |
9e8327e3 | 9602 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 9603 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 9604 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
9605 | "!SIBLING_CALL_P (insn) |
9606 | && TARGET_SMALL_EXEC | |
ed9676cf | 9607 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9608 | "bras\t%3,%1" |
9db1d521 | 9609 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9610 | (set_attr "type" "jsr") |
9611 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9612 | |
9e8327e3 | 9613 | (define_insn "*brasl_r" |
c19ec8f9 | 9614 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9615 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9616 | (match_operand 2 "const_int_operand" "n"))) | |
9617 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
9618 | "!SIBLING_CALL_P (insn) |
9619 | && TARGET_CPU_ZARCH | |
ed9676cf | 9620 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9621 | "brasl\t%3,%1" |
9622 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9623 | (set_attr "type" "jsr") |
9624 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9625 | |
9e8327e3 | 9626 | (define_insn "*basr_r" |
c19ec8f9 | 9627 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9628 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9629 | (match_operand 2 "const_int_operand" "n"))) |
9630 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 9631 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9632 | { |
9633 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9634 | return "basr\t%3,%1"; | |
9635 | else | |
9636 | return "bas\t%3,%a1"; | |
9637 | } | |
9638 | [(set (attr "op_type") | |
9639 | (if_then_else (match_operand 1 "register_operand" "") | |
9640 | (const_string "RR") (const_string "RX"))) | |
9641 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9642 | (set_attr "atype" "agen") |
9643 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9644 | |
fd3cd001 UW |
9645 | ;; |
9646 | ;;- Thread-local storage support. | |
9647 | ;; | |
9648 | ||
f959607b CLT |
9649 | (define_expand "get_thread_pointer<mode>" |
9650 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
9651 | "" | |
c5aa1d12 | 9652 | "") |
fd3cd001 | 9653 | |
f959607b CLT |
9654 | (define_expand "set_thread_pointer<mode>" |
9655 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
9656 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
9657 | "" | |
c5aa1d12 UW |
9658 | "") |
9659 | ||
9660 | (define_insn "*set_tp" | |
ae156f85 | 9661 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
9662 | "" |
9663 | "" | |
9664 | [(set_attr "type" "none") | |
9665 | (set_attr "length" "0")]) | |
c7453384 | 9666 | |
fd3cd001 UW |
9667 | (define_insn "*tls_load_64" |
9668 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 9669 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
9670 | (match_operand:DI 2 "" "")] |
9671 | UNSPEC_TLS_LOAD))] | |
9672 | "TARGET_64BIT" | |
d40c829f | 9673 | "lg\t%0,%1%J2" |
9381e3f1 WG |
9674 | [(set_attr "op_type" "RXE") |
9675 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
9676 | |
9677 | (define_insn "*tls_load_31" | |
d3632d41 UW |
9678 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
9679 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
9680 | (match_operand:SI 2 "" "")] |
9681 | UNSPEC_TLS_LOAD))] | |
9682 | "!TARGET_64BIT" | |
d3632d41 | 9683 | "@ |
d40c829f UW |
9684 | l\t%0,%1%J2 |
9685 | ly\t%0,%1%J2" | |
9381e3f1 | 9686 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 9687 | (set_attr "type" "load") |
9381e3f1 | 9688 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 9689 | |
9e8327e3 | 9690 | (define_insn "*bras_tls" |
c19ec8f9 | 9691 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9692 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9693 | (match_operand 2 "const_int_operand" "n"))) | |
9694 | (clobber (match_operand 3 "register_operand" "=r")) | |
9695 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9696 | "!SIBLING_CALL_P (insn) |
9697 | && TARGET_SMALL_EXEC | |
ed9676cf | 9698 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9699 | "bras\t%3,%1%J4" |
fd3cd001 | 9700 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9701 | (set_attr "type" "jsr") |
9702 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9703 | |
9e8327e3 | 9704 | (define_insn "*brasl_tls" |
c19ec8f9 | 9705 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9706 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9707 | (match_operand 2 "const_int_operand" "n"))) | |
9708 | (clobber (match_operand 3 "register_operand" "=r")) | |
9709 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9710 | "!SIBLING_CALL_P (insn) |
9711 | && TARGET_CPU_ZARCH | |
ed9676cf | 9712 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9713 | "brasl\t%3,%1%J4" |
9714 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9715 | (set_attr "type" "jsr") |
9716 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9717 | |
9e8327e3 | 9718 | (define_insn "*basr_tls" |
c19ec8f9 | 9719 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9720 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9721 | (match_operand 2 "const_int_operand" "n"))) |
9722 | (clobber (match_operand 3 "register_operand" "=r")) | |
9723 | (use (match_operand 4 "" ""))] | |
ed9676cf | 9724 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9725 | { |
9726 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9727 | return "basr\t%3,%1%J4"; | |
9728 | else | |
9729 | return "bas\t%3,%a1%J4"; | |
9730 | } | |
9731 | [(set (attr "op_type") | |
9732 | (if_then_else (match_operand 1 "register_operand" "") | |
9733 | (const_string "RR") (const_string "RX"))) | |
9734 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9735 | (set_attr "atype" "agen") |
9736 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9737 | |
e0374221 AS |
9738 | ;; |
9739 | ;;- Atomic operations | |
9740 | ;; | |
9741 | ||
9742 | ; | |
78ce265b | 9743 | ; memory barrier patterns. |
e0374221 AS |
9744 | ; |
9745 | ||
78ce265b RH |
9746 | (define_expand "mem_signal_fence" |
9747 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
9748 | "" |
9749 | { | |
78ce265b RH |
9750 | /* The s390 memory model is strong enough not to require any |
9751 | barrier in order to synchronize a thread with itself. */ | |
9752 | DONE; | |
9753 | }) | |
9754 | ||
9755 | (define_expand "mem_thread_fence" | |
9756 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
9757 | "" | |
9758 | { | |
9759 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
9760 | enough not to require barriers of any kind. */ | |
46b35980 | 9761 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
9762 | { |
9763 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
9764 | MEM_VOLATILE_P (mem) = 1; | |
9765 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
9766 | } | |
9767 | DONE; | |
e0374221 AS |
9768 | }) |
9769 | ||
78ce265b RH |
9770 | ; Although bcr is superscalar on Z10, this variant will never |
9771 | ; become part of an execution group. | |
a9cc3f58 AK |
9772 | ; With z196 we can make use of the fast-BCR-serialization facility. |
9773 | ; This allows for a slightly faster sync which is sufficient for our | |
9774 | ; purposes. | |
78ce265b | 9775 | (define_insn "mem_thread_fence_1" |
e0374221 | 9776 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 9777 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 9778 | "" |
a9cc3f58 AK |
9779 | { |
9780 | if (TARGET_Z196) | |
9781 | return "bcr\t14,0"; | |
9782 | else | |
9783 | return "bcr\t15,0"; | |
9784 | } | |
9785 | [(set_attr "op_type" "RR") | |
9786 | (set_attr "mnemonic" "bcr_flush") | |
9787 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 9788 | |
78ce265b RH |
9789 | ; |
9790 | ; atomic load/store operations | |
9791 | ; | |
9792 | ||
9793 | ; Atomic loads need not examine the memory model at all. | |
9794 | (define_expand "atomic_load<mode>" | |
9795 | [(match_operand:DINT 0 "register_operand") ;; output | |
9796 | (match_operand:DINT 1 "memory_operand") ;; memory | |
9797 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9798 | "" | |
9799 | { | |
75cc21e2 AK |
9800 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
9801 | FAIL; | |
9802 | ||
78ce265b RH |
9803 | if (<MODE>mode == TImode) |
9804 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
9805 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9806 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
9807 | else | |
9808 | emit_move_insn (operands[0], operands[1]); | |
9809 | DONE; | |
9810 | }) | |
9811 | ||
9812 | ; Different from movdi_31 in that we want no splitters. | |
9813 | (define_insn "atomic_loaddi_1" | |
9814 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
9815 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
9816 | UNSPEC_MOVA))] | |
9817 | "!TARGET_ZARCH" | |
9818 | "@ | |
9819 | lm\t%0,%M0,%S1 | |
9820 | lmy\t%0,%M0,%S1 | |
9821 | ld\t%0,%1 | |
9822 | ldy\t%0,%1" | |
9823 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9824 | (set_attr "type" "lm,lm,floaddf,floaddf")]) | |
9825 | ||
9826 | (define_insn "atomic_loadti_1" | |
9827 | [(set (match_operand:TI 0 "register_operand" "=r") | |
9828 | (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] | |
9829 | UNSPEC_MOVA))] | |
9830 | "TARGET_ZARCH" | |
9831 | "lpq\t%0,%1" | |
9832 | [(set_attr "op_type" "RXY") | |
9833 | (set_attr "type" "other")]) | |
9834 | ||
9835 | ; Atomic stores must(?) enforce sequential consistency. | |
9836 | (define_expand "atomic_store<mode>" | |
9837 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
9838 | (match_operand:DINT 1 "register_operand") ;; input | |
9839 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9840 | "" | |
9841 | { | |
46b35980 | 9842 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 9843 | |
75cc21e2 AK |
9844 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
9845 | FAIL; | |
9846 | ||
78ce265b RH |
9847 | if (<MODE>mode == TImode) |
9848 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
9849 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9850 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
9851 | else | |
9852 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 9853 | if (is_mm_seq_cst (model)) |
78ce265b RH |
9854 | emit_insn (gen_mem_thread_fence (operands[2])); |
9855 | DONE; | |
9856 | }) | |
9857 | ||
9858 | ; Different from movdi_31 in that we want no splitters. | |
9859 | (define_insn "atomic_storedi_1" | |
9860 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
9861 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
9862 | UNSPEC_MOVA))] | |
9863 | "!TARGET_ZARCH" | |
9864 | "@ | |
9865 | stm\t%1,%N1,%S0 | |
9866 | stmy\t%1,%N1,%S0 | |
9867 | std %1,%0 | |
9868 | stdy %1,%0" | |
9869 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9870 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) | |
9871 | ||
9872 | (define_insn "atomic_storeti_1" | |
9873 | [(set (match_operand:TI 0 "memory_operand" "=RT") | |
9874 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] | |
9875 | UNSPEC_MOVA))] | |
9876 | "TARGET_ZARCH" | |
9877 | "stpq\t%1,%0" | |
9878 | [(set_attr "op_type" "RXY") | |
9879 | (set_attr "type" "other")]) | |
e0374221 AS |
9880 | |
9881 | ; | |
9882 | ; compare and swap patterns. | |
9883 | ; | |
9884 | ||
78ce265b RH |
9885 | (define_expand "atomic_compare_and_swap<mode>" |
9886 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9887 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
9888 | (match_operand:DGPR 2 "memory_operand") ;; memory |
9889 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
9890 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
9891 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9892 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9893 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
9894 | "" | |
9895 | { | |
215770ad UW |
9896 | rtx cc, cmp, output = operands[1]; |
9897 | ||
9898 | if (!register_operand (output, <MODE>mode)) | |
9899 | output = gen_reg_rtx (<MODE>mode); | |
9900 | ||
75cc21e2 AK |
9901 | if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2]))) |
9902 | FAIL; | |
9903 | ||
78ce265b | 9904 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
9905 | (output, operands[2], operands[3], operands[4])); |
9906 | ||
9907 | /* We deliberately accept non-register operands in the predicate | |
9908 | to ensure the write back to the output operand happens *before* | |
9909 | the store-flags code below. This makes it easier for combine | |
9910 | to merge the store-flags code with a potential test-and-branch | |
9911 | pattern following (immediately!) afterwards. */ | |
9912 | if (output != operands[1]) | |
9913 | emit_move_insn (operands[1], output); | |
9914 | ||
78ce265b RH |
9915 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
9916 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
9917 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
9918 | DONE; | |
9919 | }) | |
e0374221 | 9920 | |
78ce265b RH |
9921 | (define_expand "atomic_compare_and_swap<mode>" |
9922 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9923 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
9924 | (match_operand:HQI 2 "memory_operand") ;; memory |
9925 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
9926 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
9927 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9928 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9929 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 9930 | "" |
78ce265b RH |
9931 | { |
9932 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
9933 | operands[3], operands[4], INTVAL (operands[5])); | |
9934 | DONE; | |
9935 | }) | |
3093f076 | 9936 | |
78ce265b RH |
9937 | (define_expand "atomic_compare_and_swap<mode>_internal" |
9938 | [(parallel | |
9939 | [(set (match_operand:DGPR 0 "register_operand") | |
9940 | (match_operand:DGPR 1 "memory_operand")) | |
9941 | (set (match_dup 1) | |
9942 | (unspec_volatile:DGPR | |
9943 | [(match_dup 1) | |
9944 | (match_operand:DGPR 2 "register_operand") | |
9945 | (match_operand:DGPR 3 "register_operand")] | |
9946 | UNSPECV_CAS)) | |
9947 | (set (reg:CCZ1 CC_REGNUM) | |
9948 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
9949 | "") | |
9950 | ||
9951 | ; cdsg, csg | |
9952 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
9953 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
9954 | (match_operand:TDI 1 "memory_operand" "+QS")) | |
8006eaa6 | 9955 | (set (match_dup 1) |
78ce265b | 9956 | (unspec_volatile:TDI |
8006eaa6 | 9957 | [(match_dup 1) |
78ce265b RH |
9958 | (match_operand:TDI 2 "register_operand" "0") |
9959 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
9960 | UNSPECV_CAS)) |
9961 | (set (reg:CCZ1 CC_REGNUM) | |
9962 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
9963 | "TARGET_ZARCH" |
9964 | "c<td>sg\t%0,%3,%S1" | |
9965 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
9966 | (set_attr "type" "sem")]) |
9967 | ||
78ce265b RH |
9968 | ; cds, cdsy |
9969 | (define_insn "*atomic_compare_and_swapdi_2" | |
9970 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
9971 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 9972 | (set (match_dup 1) |
78ce265b RH |
9973 | (unspec_volatile:DI |
9974 | [(match_dup 1) | |
9975 | (match_operand:DI 2 "register_operand" "0,0") | |
9976 | (match_operand:DI 3 "register_operand" "r,r")] | |
9977 | UNSPECV_CAS)) | |
9978 | (set (reg:CCZ1 CC_REGNUM) | |
9979 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9980 | "!TARGET_ZARCH" | |
9981 | "@ | |
9982 | cds\t%0,%3,%S1 | |
9983 | cdsy\t%0,%3,%S1" | |
9984 | [(set_attr "op_type" "RS,RSY") | |
9985 | (set_attr "type" "sem")]) | |
9986 | ||
9987 | ; cs, csy | |
9988 | (define_insn "*atomic_compare_and_swapsi_3" | |
9989 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
9990 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
9991 | (set (match_dup 1) | |
9992 | (unspec_volatile:SI | |
e0374221 | 9993 | [(match_dup 1) |
78ce265b RH |
9994 | (match_operand:SI 2 "register_operand" "0,0") |
9995 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 9996 | UNSPECV_CAS)) |
69950452 AS |
9997 | (set (reg:CCZ1 CC_REGNUM) |
9998 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 9999 | "" |
78ce265b RH |
10000 | "@ |
10001 | cs\t%0,%3,%S1 | |
10002 | csy\t%0,%3,%S1" | |
10003 | [(set_attr "op_type" "RS,RSY") | |
e0374221 AS |
10004 | (set_attr "type" "sem")]) |
10005 | ||
45d18331 AS |
10006 | ; |
10007 | ; Other atomic instruction patterns. | |
10008 | ; | |
10009 | ||
65b1d8ea AK |
10010 | ; z196 load and add, xor, or and and instructions |
10011 | ||
78ce265b RH |
10012 | (define_expand "atomic_fetch_<atomic><mode>" |
10013 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10014 | (ATOMIC_Z196:GPR | |
10015 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10016 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10017 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10018 | "TARGET_Z196" |
78ce265b | 10019 | { |
75cc21e2 AK |
10020 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10021 | FAIL; | |
10022 | ||
78ce265b RH |
10023 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10024 | (operands[0], operands[1], operands[2])); | |
10025 | DONE; | |
10026 | }) | |
65b1d8ea AK |
10027 | |
10028 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10029 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10030 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
10031 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
10032 | (set (match_dup 1) | |
10033 | (unspec_volatile:GPR | |
10034 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10035 | (match_operand:GPR 2 "general_operand" "d"))] | |
10036 | UNSPECV_ATOMIC_OP)) | |
10037 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10038 | "TARGET_Z196" |
78ce265b RH |
10039 | "la<noxa><g>\t%0,%2,%1" |
10040 | [(set_attr "op_type" "RSY") | |
10041 | (set_attr "type" "sem")]) | |
65b1d8ea | 10042 | |
78ce265b RH |
10043 | ;; For SImode and larger, the optabs.c code will do just fine in |
10044 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10045 | ;; better by expanding our own loop. | |
65b1d8ea | 10046 | |
78ce265b RH |
10047 | (define_expand "atomic_<atomic><mode>" |
10048 | [(ATOMIC:HQI | |
10049 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10050 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10051 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10052 | "" |
78ce265b RH |
10053 | { |
10054 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10055 | operands[1], false); | |
10056 | DONE; | |
10057 | }) | |
45d18331 | 10058 | |
78ce265b RH |
10059 | (define_expand "atomic_fetch_<atomic><mode>" |
10060 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10061 | (ATOMIC:HQI | |
10062 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10063 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10064 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10065 | "" |
78ce265b RH |
10066 | { |
10067 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10068 | operands[2], false); | |
10069 | DONE; | |
10070 | }) | |
10071 | ||
10072 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10073 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10074 | (ATOMIC:HQI | |
10075 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10076 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10077 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10078 | "" | |
10079 | { | |
10080 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10081 | operands[2], true); | |
10082 | DONE; | |
10083 | }) | |
10084 | ||
10085 | (define_expand "atomic_exchange<mode>" | |
10086 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10087 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10088 | (match_operand:HQI 2 "general_operand") ;; val in | |
10089 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10090 | "" |
78ce265b RH |
10091 | { |
10092 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
10093 | operands[2], false); | |
10094 | DONE; | |
10095 | }) | |
45d18331 | 10096 | |
9db1d521 HP |
10097 | ;; |
10098 | ;;- Miscellaneous instructions. | |
10099 | ;; | |
10100 | ||
10101 | ; | |
10102 | ; allocate stack instruction pattern(s). | |
10103 | ; | |
10104 | ||
10105 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10106 | [(match_operand 0 "general_operand" "") |
10107 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10108 | "TARGET_BACKCHAIN" |
9db1d521 | 10109 | { |
ef44a6ff | 10110 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10111 | |
ef44a6ff UW |
10112 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10113 | anti_adjust_stack (operands[1]); | |
10114 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10115 | |
ef44a6ff UW |
10116 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10117 | DONE; | |
10bbf137 | 10118 | }) |
9db1d521 HP |
10119 | |
10120 | ||
10121 | ; | |
43ab026f | 10122 | ; setjmp instruction pattern. |
9db1d521 HP |
10123 | ; |
10124 | ||
9db1d521 | 10125 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10126 | [(match_operand 0 "" "")] |
f314b9b1 | 10127 | "flag_pic" |
9db1d521 | 10128 | { |
585539a1 | 10129 | emit_insn (s390_load_got ()); |
c41c1387 | 10130 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10131 | DONE; |
fd7643fb | 10132 | }) |
9db1d521 | 10133 | |
9db1d521 HP |
10134 | ;; These patterns say how to save and restore the stack pointer. We need not |
10135 | ;; save the stack pointer at function level since we are careful to | |
10136 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10137 | ;; when we restore the stack pointer. | |
10138 | ;; | |
10139 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10140 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10141 | ;; save area is a memory location. | |
10142 | ||
10143 | (define_expand "save_stack_function" | |
10144 | [(match_operand 0 "general_operand" "") | |
10145 | (match_operand 1 "general_operand" "")] | |
10146 | "" | |
10147 | "DONE;") | |
10148 | ||
10149 | (define_expand "restore_stack_function" | |
10150 | [(match_operand 0 "general_operand" "") | |
10151 | (match_operand 1 "general_operand" "")] | |
10152 | "" | |
10153 | "DONE;") | |
10154 | ||
10155 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10156 | [(match_operand 0 "register_operand" "") |
10157 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10158 | "TARGET_BACKCHAIN" |
9db1d521 | 10159 | { |
ef44a6ff UW |
10160 | rtx temp = gen_reg_rtx (Pmode); |
10161 | ||
10162 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10163 | emit_move_insn (operands[0], operands[1]); | |
10164 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10165 | ||
10166 | DONE; | |
10bbf137 | 10167 | }) |
9db1d521 HP |
10168 | |
10169 | (define_expand "save_stack_nonlocal" | |
10170 | [(match_operand 0 "memory_operand" "") | |
10171 | (match_operand 1 "register_operand" "")] | |
10172 | "" | |
9db1d521 | 10173 | { |
ef44a6ff UW |
10174 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10175 | ||
10176 | /* Copy the backchain to the first word, sp to the second and the | |
10177 | literal pool base to the third. */ | |
10178 | ||
9602b6a1 AK |
10179 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10180 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10181 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10182 | ||
b3d31392 | 10183 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10184 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10185 | |
9602b6a1 AK |
10186 | emit_move_insn (save_sp, operands[1]); |
10187 | emit_move_insn (save_bp, base); | |
9db1d521 | 10188 | |
9db1d521 | 10189 | DONE; |
10bbf137 | 10190 | }) |
9db1d521 HP |
10191 | |
10192 | (define_expand "restore_stack_nonlocal" | |
10193 | [(match_operand 0 "register_operand" "") | |
10194 | (match_operand 1 "memory_operand" "")] | |
10195 | "" | |
9db1d521 | 10196 | { |
490ceeb4 | 10197 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10198 | rtx temp = NULL_RTX; |
9db1d521 | 10199 | |
43ab026f | 10200 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10201 | literal pool base from the third. */ |
43ab026f | 10202 | |
9602b6a1 AK |
10203 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10204 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10205 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10206 | ||
b3d31392 | 10207 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10208 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10209 | |
9602b6a1 AK |
10210 | emit_move_insn (base, save_bp); |
10211 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10212 | |
10213 | if (temp) | |
10214 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10215 | ||
c41c1387 | 10216 | emit_use (base); |
9db1d521 | 10217 | DONE; |
10bbf137 | 10218 | }) |
9db1d521 | 10219 | |
7bcebb25 AK |
10220 | (define_expand "exception_receiver" |
10221 | [(const_int 0)] | |
10222 | "" | |
10223 | { | |
10224 | s390_set_has_landing_pad_p (true); | |
10225 | DONE; | |
10226 | }) | |
9db1d521 HP |
10227 | |
10228 | ; | |
10229 | ; nop instruction pattern(s). | |
10230 | ; | |
10231 | ||
10232 | (define_insn "nop" | |
10233 | [(const_int 0)] | |
10234 | "" | |
d40c829f | 10235 | "lr\t0,0" |
729e750f WG |
10236 | [(set_attr "op_type" "RR") |
10237 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10238 | |
d277db6b WG |
10239 | (define_insn "nop1" |
10240 | [(const_int 1)] | |
10241 | "" | |
10242 | "lr\t1,1" | |
10243 | [(set_attr "op_type" "RR")]) | |
10244 | ||
f8af0e30 DV |
10245 | ;;- Undeletable nops (used for hotpatching) |
10246 | ||
10247 | (define_insn "nop_2_byte" | |
10248 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10249 | "" | |
10250 | "nopr\t%%r7" | |
10251 | [(set_attr "op_type" "RR")]) | |
10252 | ||
10253 | (define_insn "nop_4_byte" | |
10254 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10255 | "" | |
10256 | "nop\t0" | |
10257 | [(set_attr "op_type" "RX")]) | |
10258 | ||
10259 | (define_insn "nop_6_byte" | |
10260 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
10261 | "TARGET_CPU_ZARCH" | |
10262 | "brcl\t0, 0" | |
10263 | [(set_attr "op_type" "RIL")]) | |
10264 | ||
9db1d521 HP |
10265 | |
10266 | ; | |
10267 | ; Special literal pool access instruction pattern(s). | |
10268 | ; | |
10269 | ||
416cf582 UW |
10270 | (define_insn "*pool_entry" |
10271 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10272 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10273 | "" |
9db1d521 | 10274 | { |
ef4bddc2 | 10275 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10276 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10277 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10278 | return ""; |
10279 | } | |
b628bd8e | 10280 | [(set (attr "length") |
416cf582 | 10281 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10282 | |
9bb86f41 UW |
10283 | (define_insn "pool_align" |
10284 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10285 | UNSPECV_POOL_ALIGN)] | |
10286 | "" | |
10287 | ".align\t%0" | |
b628bd8e | 10288 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10289 | |
9bb86f41 UW |
10290 | (define_insn "pool_section_start" |
10291 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10292 | "" | |
b929b470 MK |
10293 | { |
10294 | switch_to_section (targetm.asm_out.function_rodata_section | |
10295 | (current_function_decl)); | |
10296 | return ""; | |
10297 | } | |
b628bd8e | 10298 | [(set_attr "length" "0")]) |
b2ccb744 | 10299 | |
9bb86f41 UW |
10300 | (define_insn "pool_section_end" |
10301 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10302 | "" | |
b929b470 MK |
10303 | { |
10304 | switch_to_section (current_function_section ()); | |
10305 | return ""; | |
10306 | } | |
b628bd8e | 10307 | [(set_attr "length" "0")]) |
b2ccb744 | 10308 | |
5af2f3d3 | 10309 | (define_insn "main_base_31_small" |
9e8327e3 UW |
10310 | [(set (match_operand 0 "register_operand" "=a") |
10311 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10312 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10313 | "basr\t%0,0" |
10314 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
10315 | (set_attr "type" "la") |
10316 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10317 | |
10318 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
10319 | [(set (match_operand 0 "register_operand" "=a") |
10320 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 10321 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 10322 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 10323 | "bras\t%0,%2" |
65b1d8ea AK |
10324 | [(set_attr "op_type" "RI") |
10325 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10326 | |
10327 | (define_insn "main_base_64" | |
9e8327e3 UW |
10328 | [(set (match_operand 0 "register_operand" "=a") |
10329 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10330 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10331 | "larl\t%0,%1" |
10332 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10333 | (set_attr "type" "larl") |
729e750f | 10334 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
10335 | |
10336 | (define_insn "main_pool" | |
585539a1 UW |
10337 | [(set (match_operand 0 "register_operand" "=a") |
10338 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10339 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10340 | { |
10341 | gcc_unreachable (); | |
10342 | } | |
9381e3f1 | 10343 | [(set (attr "type") |
d7f99b2c | 10344 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 10345 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 10346 | |
aee4e0db | 10347 | (define_insn "reload_base_31" |
9e8327e3 UW |
10348 | [(set (match_operand 0 "register_operand" "=a") |
10349 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10350 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10351 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 10352 | [(set_attr "length" "6") |
65b1d8ea AK |
10353 | (set_attr "type" "la") |
10354 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 10355 | |
aee4e0db | 10356 | (define_insn "reload_base_64" |
9e8327e3 UW |
10357 | [(set (match_operand 0 "register_operand" "=a") |
10358 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10359 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10360 | "larl\t%0,%1" |
aee4e0db | 10361 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10362 | (set_attr "type" "larl") |
729e750f | 10363 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10364 | |
aee4e0db | 10365 | (define_insn "pool" |
fd7643fb | 10366 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10367 | "" |
8d933e31 AS |
10368 | { |
10369 | gcc_unreachable (); | |
10370 | } | |
b628bd8e | 10371 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10372 | |
4023fb28 UW |
10373 | ;; |
10374 | ;; Insns related to generating the function prologue and epilogue. | |
10375 | ;; | |
10376 | ||
10377 | ||
10378 | (define_expand "prologue" | |
10379 | [(use (const_int 0))] | |
10380 | "" | |
10bbf137 | 10381 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10382 | |
10383 | (define_expand "epilogue" | |
10384 | [(use (const_int 1))] | |
10385 | "" | |
ed9676cf AK |
10386 | "s390_emit_epilogue (false); DONE;") |
10387 | ||
10388 | (define_expand "sibcall_epilogue" | |
10389 | [(use (const_int 0))] | |
10390 | "" | |
10391 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10392 | |
177bc204 RS |
10393 | ;; A direct return instruction, without using an epilogue. |
10394 | (define_insn "<code>" | |
10395 | [(ANY_RETURN)] | |
10396 | "s390_can_use_<code>_insn ()" | |
10397 | "br\t%%r14" | |
10398 | [(set_attr "op_type" "RR") | |
10399 | (set_attr "type" "jsr") | |
10400 | (set_attr "atype" "agen")]) | |
10401 | ||
9e8327e3 | 10402 | (define_insn "*return" |
4023fb28 | 10403 | [(return) |
9e8327e3 UW |
10404 | (use (match_operand 0 "register_operand" "a"))] |
10405 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10406 | "br\t%0" |
4023fb28 | 10407 | [(set_attr "op_type" "RR") |
c7453384 | 10408 | (set_attr "type" "jsr") |
077dab3b | 10409 | (set_attr "atype" "agen")]) |
4023fb28 | 10410 | |
4023fb28 | 10411 | |
c7453384 | 10412 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 10413 | ;; pointer. This is used for compatibility. |
c7453384 EC |
10414 | |
10415 | (define_expand "ptr_extend" | |
10416 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10417 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 10418 | "TARGET_64BIT" |
c7453384 | 10419 | { |
c7453384 EC |
10420 | emit_insn (gen_anddi3 (operands[0], |
10421 | gen_lowpart (DImode, operands[1]), | |
10422 | GEN_INT (0x7fffffff))); | |
c7453384 | 10423 | DONE; |
10bbf137 | 10424 | }) |
4798630c D |
10425 | |
10426 | ;; Instruction definition to expand eh_return macro to support | |
10427 | ;; swapping in special linkage return addresses. | |
10428 | ||
10429 | (define_expand "eh_return" | |
10430 | [(use (match_operand 0 "register_operand" ""))] | |
10431 | "TARGET_TPF" | |
10432 | { | |
10433 | s390_emit_tpf_eh_return (operands[0]); | |
10434 | DONE; | |
10435 | }) | |
10436 | ||
7b8acc34 AK |
10437 | ; |
10438 | ; Stack Protector Patterns | |
10439 | ; | |
10440 | ||
10441 | (define_expand "stack_protect_set" | |
10442 | [(set (match_operand 0 "memory_operand" "") | |
10443 | (match_operand 1 "memory_operand" ""))] | |
10444 | "" | |
10445 | { | |
10446 | #ifdef TARGET_THREAD_SSP_OFFSET | |
10447 | operands[1] | |
10448 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10449 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10450 | #endif | |
10451 | if (TARGET_64BIT) | |
10452 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10453 | else | |
10454 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10455 | ||
10456 | DONE; | |
10457 | }) | |
10458 | ||
10459 | (define_insn "stack_protect_set<mode>" | |
10460 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
10461 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
10462 | "" | |
10463 | "mvc\t%O0(%G0,%R0),%S1" | |
10464 | [(set_attr "op_type" "SS")]) | |
10465 | ||
10466 | (define_expand "stack_protect_test" | |
10467 | [(set (reg:CC CC_REGNUM) | |
10468 | (compare (match_operand 0 "memory_operand" "") | |
10469 | (match_operand 1 "memory_operand" ""))) | |
10470 | (match_operand 2 "" "")] | |
10471 | "" | |
10472 | { | |
f90b7a5a | 10473 | rtx cc_reg, test; |
7b8acc34 AK |
10474 | #ifdef TARGET_THREAD_SSP_OFFSET |
10475 | operands[1] | |
10476 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10477 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10478 | #endif | |
7b8acc34 AK |
10479 | if (TARGET_64BIT) |
10480 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
10481 | else | |
10482 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
10483 | ||
f90b7a5a PB |
10484 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
10485 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
10486 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
10487 | DONE; |
10488 | }) | |
10489 | ||
10490 | (define_insn "stack_protect_test<mode>" | |
10491 | [(set (reg:CCZ CC_REGNUM) | |
10492 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
10493 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
10494 | "" | |
10495 | "clc\t%O0(%G0,%R0),%S1" | |
10496 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
10497 | |
10498 | ; This is used in s390_emit_prologue in order to prevent insns | |
10499 | ; adjusting the stack pointer to be moved over insns writing stack | |
10500 | ; slots using a copy of the stack pointer in a different register. | |
10501 | (define_insn "stack_tie" | |
10502 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
10503 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
10504 | "" | |
10505 | "" | |
10506 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
10507 | |
10508 | ||
10509 | ; | |
10510 | ; Data prefetch patterns | |
10511 | ; | |
10512 | ||
10513 | (define_insn "prefetch" | |
22d72dbc AK |
10514 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
10515 | (match_operand:SI 1 "const_int_operand" " n,n") | |
10516 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
10517 | "TARGET_Z10" | |
963fc8d0 | 10518 | { |
4fe6dea8 AK |
10519 | switch (which_alternative) |
10520 | { | |
10521 | case 0: | |
4fe6dea8 | 10522 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 10523 | case 1: |
4fe6dea8 AK |
10524 | if (larl_operand (operands[0], Pmode)) |
10525 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
10526 | default: | |
10527 | ||
10528 | /* This might be reached for symbolic operands with an odd | |
10529 | addend. We simply omit the prefetch for such rare cases. */ | |
10530 | ||
10531 | return ""; | |
10532 | } | |
9381e3f1 | 10533 | } |
22d72dbc AK |
10534 | [(set_attr "type" "load,larl") |
10535 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
10536 | (set_attr "z10prop" "z10_super") |
10537 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
10538 | |
10539 | ||
10540 | ; | |
10541 | ; Byte swap instructions | |
10542 | ; | |
10543 | ||
511f5bb1 AK |
10544 | ; FIXME: There is also mvcin but we cannot use it since src and target |
10545 | ; may overlap. | |
07da44ab | 10546 | (define_insn "bswap<mode>2" |
6f5a59d1 AK |
10547 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,RT") |
10548 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))] | |
677fbff4 | 10549 | "TARGET_CPU_ZARCH" |
07da44ab AK |
10550 | "@ |
10551 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
10552 | lrv<g>\t%0,%1 |
10553 | strv<g>\t%1,%0" | |
10554 | [(set_attr "type" "*,load,store") | |
10555 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 10556 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10557 | |
511f5bb1 | 10558 | (define_insn "bswaphi2" |
6f5a59d1 AK |
10559 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d, d,RT") |
10560 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))] | |
511f5bb1 | 10561 | "TARGET_CPU_ZARCH" |
6f5a59d1 AK |
10562 | "@ |
10563 | # | |
10564 | lrvh\t%0,%1 | |
10565 | strvh\t%1,%0" | |
10566 | [(set_attr "type" "*,load,store") | |
10567 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 10568 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10569 | |
6f5a59d1 AK |
10570 | (define_split |
10571 | [(set (match_operand:HI 0 "register_operand" "") | |
10572 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
10573 | "TARGET_CPU_ZARCH" | |
10574 | [(set (match_dup 2) (bswap:SI (match_dup 3))) | |
9060e335 | 10575 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 10576 | { |
9060e335 | 10577 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
10578 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
10579 | }) | |
10580 | ||
10581 | ||
65b1d8ea AK |
10582 | ; |
10583 | ; Population count instruction | |
10584 | ; | |
10585 | ||
10586 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
10587 | ; portions and stores the result in the corresponding bytes in op0. | |
10588 | (define_insn "*popcount<mode>" | |
10589 | [(set (match_operand:INT 0 "register_operand" "=d") | |
10590 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
10591 | (clobber (reg:CC CC_REGNUM))] | |
10592 | "TARGET_Z196" | |
10593 | "popcnt\t%0,%1" | |
10594 | [(set_attr "op_type" "RRE")]) | |
10595 | ||
10596 | (define_expand "popcountdi2" | |
10597 | [; popcnt op0, op1 | |
10598 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
10599 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
10600 | UNSPEC_POPCNT)) | |
10601 | (clobber (reg:CC CC_REGNUM))]) | |
10602 | ; sllg op2, op0, 32 | |
10603 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
10604 | ; agr op0, op2 | |
10605 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10606 | (clobber (reg:CC CC_REGNUM))]) | |
10607 | ; sllg op2, op0, 16 | |
17465c6e | 10608 | (set (match_dup 2) |
65b1d8ea AK |
10609 | (ashift:DI (match_dup 0) (const_int 16))) |
10610 | ; agr op0, op2 | |
10611 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10612 | (clobber (reg:CC CC_REGNUM))]) | |
10613 | ; sllg op2, op0, 8 | |
10614 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
10615 | ; agr op0, op2 | |
10616 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10617 | (clobber (reg:CC CC_REGNUM))]) | |
10618 | ; srlg op0, op0, 56 | |
10619 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
10620 | "TARGET_Z196 && TARGET_64BIT" | |
10621 | "operands[2] = gen_reg_rtx (DImode);") | |
10622 | ||
10623 | (define_expand "popcountsi2" | |
10624 | [; popcnt op0, op1 | |
10625 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
10626 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
10627 | UNSPEC_POPCNT)) | |
10628 | (clobber (reg:CC CC_REGNUM))]) | |
10629 | ; sllk op2, op0, 16 | |
17465c6e | 10630 | (set (match_dup 2) |
65b1d8ea AK |
10631 | (ashift:SI (match_dup 0) (const_int 16))) |
10632 | ; ar op0, op2 | |
10633 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10634 | (clobber (reg:CC CC_REGNUM))]) | |
10635 | ; sllk op2, op0, 8 | |
10636 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
10637 | ; ar op0, op2 | |
10638 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10639 | (clobber (reg:CC CC_REGNUM))]) | |
10640 | ; srl op0, op0, 24 | |
10641 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
10642 | "TARGET_Z196" | |
10643 | "operands[2] = gen_reg_rtx (SImode);") | |
10644 | ||
10645 | (define_expand "popcounthi2" | |
10646 | [; popcnt op0, op1 | |
10647 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
10648 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
10649 | UNSPEC_POPCNT)) | |
10650 | (clobber (reg:CC CC_REGNUM))]) | |
10651 | ; sllk op2, op0, 8 | |
17465c6e | 10652 | (set (match_dup 2) |
65b1d8ea AK |
10653 | (ashift:SI (match_dup 0) (const_int 8))) |
10654 | ; ar op0, op2 | |
10655 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10656 | (clobber (reg:CC CC_REGNUM))]) | |
10657 | ; srl op0, op0, 8 | |
10658 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
10659 | "TARGET_Z196" | |
10660 | "operands[2] = gen_reg_rtx (SImode);") | |
10661 | ||
10662 | (define_expand "popcountqi2" | |
10663 | [; popcnt op0, op1 | |
10664 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
10665 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
10666 | UNSPEC_POPCNT)) | |
10667 | (clobber (reg:CC CC_REGNUM))])] | |
10668 | "TARGET_Z196" | |
10669 | "") | |
10670 | ||
10671 | ;; | |
10672 | ;;- Copy sign instructions | |
10673 | ;; | |
10674 | ||
10675 | (define_insn "copysign<mode>3" | |
10676 | [(set (match_operand:FP 0 "register_operand" "=f") | |
10677 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
10678 | (match_operand:FP 2 "register_operand" "f")] | |
10679 | UNSPEC_COPYSIGN))] | |
10680 | "TARGET_Z196" | |
10681 | "cpsdr\t%0,%2,%1" | |
10682 | [(set_attr "op_type" "RRF") | |
10683 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
10684 | |
10685 | ||
10686 | ;; | |
10687 | ;;- Transactional execution instructions | |
10688 | ;; | |
10689 | ||
10690 | ; This splitter helps combine to make use of CC directly when | |
10691 | ; comparing the integer result of a tbegin builtin with a constant. | |
10692 | ; The unspec is already removed by canonicalize_comparison. So this | |
10693 | ; splitters only job is to turn the PARALLEL into separate insns | |
10694 | ; again. Unfortunately this only works with the very first cc/int | |
10695 | ; compare since combine is not able to deal with data flow across | |
10696 | ; basic block boundaries. | |
10697 | ||
10698 | ; It needs to be an insn pattern as well since combine does not apply | |
10699 | ; the splitter directly. Combine would only use it if it actually | |
10700 | ; would reduce the number of instructions. | |
10701 | (define_insn_and_split "*ccraw_to_int" | |
10702 | [(set (pc) | |
10703 | (if_then_else | |
10704 | (match_operator 0 "s390_eqne_operator" | |
10705 | [(reg:CCRAW CC_REGNUM) | |
10706 | (match_operand 1 "const_int_operand" "")]) | |
10707 | (label_ref (match_operand 2 "" "")) | |
10708 | (pc))) | |
10709 | (set (match_operand:SI 3 "register_operand" "=d") | |
10710 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
10711 | "" | |
10712 | "#" | |
10713 | "" | |
10714 | [(set (match_dup 3) | |
10715 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
10716 | (set (pc) | |
10717 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
10718 | (label_ref (match_dup 2)) | |
10719 | (pc)))] | |
10720 | "") | |
10721 | ||
10722 | ; Non-constrained transaction begin | |
10723 | ||
10724 | (define_expand "tbegin" | |
ee163e72 AK |
10725 | [(match_operand:SI 0 "register_operand" "") |
10726 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10727 | "TARGET_HTM" |
10728 | { | |
10729 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
10730 | DONE; | |
10731 | }) | |
10732 | ||
10733 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
10734 | [(match_operand:SI 0 "register_operand" "") |
10735 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10736 | "TARGET_HTM" |
10737 | { | |
10738 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
10739 | DONE; | |
10740 | }) | |
10741 | ||
10742 | (define_expand "tbegin_retry" | |
ee163e72 AK |
10743 | [(match_operand:SI 0 "register_operand" "") |
10744 | (match_operand:BLK 1 "memory_operand" "") | |
10745 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10746 | "TARGET_HTM" |
10747 | { | |
10748 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
10749 | DONE; | |
10750 | }) | |
10751 | ||
10752 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
10753 | [(match_operand:SI 0 "register_operand" "") |
10754 | (match_operand:BLK 1 "memory_operand" "") | |
10755 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10756 | "TARGET_HTM" |
10757 | { | |
10758 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
10759 | DONE; | |
10760 | }) | |
10761 | ||
c914ac45 AK |
10762 | ; Clobber VRs since they don't get restored |
10763 | (define_insn "tbegin_1_z13" | |
10764 | [(set (reg:CCRAW CC_REGNUM) | |
10765 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
10766 | UNSPECV_TBEGIN)) | |
10767 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10768 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
10769 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
10770 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
10771 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
10772 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
10773 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
10774 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
10775 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
10776 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
10777 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
10778 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
10779 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
10780 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
10781 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
10782 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
10783 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
10784 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
10785 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10786 | ; not supposed to be used for immediates (see genpreds.c). | |
10787 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10788 | "tbegin\t%1,%x0" | |
10789 | [(set_attr "op_type" "SIL")]) | |
10790 | ||
5a3fe9b6 AK |
10791 | (define_insn "tbegin_1" |
10792 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 10793 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 10794 | UNSPECV_TBEGIN)) |
2561451d AK |
10795 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
10796 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
10797 | (clobber (reg:DF 16)) |
10798 | (clobber (reg:DF 17)) | |
10799 | (clobber (reg:DF 18)) | |
10800 | (clobber (reg:DF 19)) | |
10801 | (clobber (reg:DF 20)) | |
10802 | (clobber (reg:DF 21)) | |
10803 | (clobber (reg:DF 22)) | |
10804 | (clobber (reg:DF 23)) | |
10805 | (clobber (reg:DF 24)) | |
10806 | (clobber (reg:DF 25)) | |
10807 | (clobber (reg:DF 26)) | |
10808 | (clobber (reg:DF 27)) | |
10809 | (clobber (reg:DF 28)) | |
10810 | (clobber (reg:DF 29)) | |
10811 | (clobber (reg:DF 30)) | |
10812 | (clobber (reg:DF 31))] | |
10813 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10814 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
10815 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
10816 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10817 | [(set_attr "op_type" "SIL")]) |
10818 | ||
10819 | ; Same as above but without the FPR clobbers | |
10820 | (define_insn "tbegin_nofloat_1" | |
10821 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
10822 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
10823 | UNSPECV_TBEGIN)) | |
10824 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10825 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
10826 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10827 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10828 | [(set_attr "op_type" "SIL")]) |
10829 | ||
10830 | ||
10831 | ; Constrained transaction begin | |
10832 | ||
10833 | (define_expand "tbeginc" | |
10834 | [(set (reg:CCRAW CC_REGNUM) | |
10835 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
10836 | UNSPECV_TBEGINC))] | |
10837 | "TARGET_HTM" | |
10838 | "") | |
10839 | ||
10840 | (define_insn "*tbeginc_1" | |
10841 | [(set (reg:CCRAW CC_REGNUM) | |
10842 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
10843 | UNSPECV_TBEGINC))] | |
10844 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10845 | "tbeginc\t0,%x0" | |
10846 | [(set_attr "op_type" "SIL")]) | |
10847 | ||
10848 | ; Transaction end | |
10849 | ||
10850 | (define_expand "tend" | |
10851 | [(set (reg:CCRAW CC_REGNUM) | |
10852 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 10853 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
10854 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
10855 | "TARGET_HTM" | |
10856 | "") | |
10857 | ||
10858 | (define_insn "*tend_1" | |
10859 | [(set (reg:CCRAW CC_REGNUM) | |
10860 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
10861 | "TARGET_HTM" | |
10862 | "tend" | |
10863 | [(set_attr "op_type" "S")]) | |
10864 | ||
10865 | ; Transaction abort | |
10866 | ||
10867 | (define_expand "tabort" | |
ee163e72 | 10868 | [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")] |
5a3fe9b6 AK |
10869 | UNSPECV_TABORT)] |
10870 | "TARGET_HTM && operands != NULL" | |
10871 | { | |
10872 | if (CONST_INT_P (operands[0]) | |
10873 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
10874 | { | |
10875 | error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC | |
10876 | ". Values in range 0 through 255 are reserved.", | |
10877 | INTVAL (operands[0])); | |
10878 | FAIL; | |
10879 | } | |
10880 | }) | |
10881 | ||
10882 | (define_insn "*tabort_1" | |
ee163e72 | 10883 | [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")] |
5a3fe9b6 AK |
10884 | UNSPECV_TABORT)] |
10885 | "TARGET_HTM && operands != NULL" | |
10886 | "tabort\t%Y0" | |
10887 | [(set_attr "op_type" "S")]) | |
10888 | ||
10889 | ; Transaction extract nesting depth | |
10890 | ||
10891 | (define_insn "etnd" | |
10892 | [(set (match_operand:SI 0 "register_operand" "=d") | |
10893 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
10894 | "TARGET_HTM" | |
10895 | "etnd\t%0" | |
10896 | [(set_attr "op_type" "RRE")]) | |
10897 | ||
10898 | ; Non-transactional store | |
10899 | ||
10900 | (define_insn "ntstg" | |
10901 | [(set (match_operand:DI 0 "memory_operand" "=RT") | |
10902 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] | |
10903 | UNSPECV_NTSTG))] | |
10904 | "TARGET_HTM" | |
10905 | "ntstg\t%1,%0" | |
10906 | [(set_attr "op_type" "RXY")]) | |
10907 | ||
10908 | ; Transaction perform processor assist | |
10909 | ||
10910 | (define_expand "tx_assist" | |
2561451d AK |
10911 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
10912 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
10913 | (const_int 1)] |
10914 | UNSPECV_PPA)] | |
10915 | "TARGET_HTM" | |
2561451d | 10916 | "") |
5a3fe9b6 AK |
10917 | |
10918 | (define_insn "*ppa" | |
10919 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
10920 | (match_operand:SI 1 "register_operand" "d") | |
10921 | (match_operand 2 "const_int_operand" "I")] | |
10922 | UNSPECV_PPA)] | |
10923 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 10924 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 10925 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
10926 | |
10927 | ||
10928 | ; Set and get floating point control register | |
10929 | ||
3af82a61 | 10930 | (define_insn "sfpc" |
004f64e1 AK |
10931 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
10932 | UNSPECV_SFPC)] | |
10933 | "TARGET_HARD_FLOAT" | |
10934 | "sfpc\t%0") | |
10935 | ||
3af82a61 | 10936 | (define_insn "efpc" |
004f64e1 AK |
10937 | [(set (match_operand:SI 0 "register_operand" "=d") |
10938 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
10939 | "TARGET_HARD_FLOAT" | |
10940 | "efpc\t%0") | |
3af82a61 AK |
10941 | |
10942 | ||
10943 | ; Load count to block boundary | |
10944 | ||
10945 | (define_insn "lcbb" | |
10946 | [(set (match_operand:SI 0 "register_operand" "=d") | |
9a36359e | 10947 | (unspec:SI [(match_operand 1 "address_operand" "ZQZR") |
3af82a61 AK |
10948 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
10949 | (clobber (reg:CC CC_REGNUM))] | |
10950 | "TARGET_Z13" | |
9a36359e | 10951 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 10952 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
10953 | |
10954 | ; Handle -fsplit-stack. | |
10955 | ||
10956 | (define_expand "split_stack_prologue" | |
10957 | [(const_int 0)] | |
10958 | "" | |
10959 | { | |
10960 | s390_expand_split_stack_prologue (); | |
10961 | DONE; | |
10962 | }) | |
10963 | ||
10964 | ;; If there are operand 0 bytes available on the stack, jump to | |
10965 | ;; operand 1. | |
10966 | ||
10967 | (define_expand "split_stack_space_check" | |
10968 | [(set (pc) (if_then_else | |
10969 | (ltu (minus (reg 15) | |
10970 | (match_operand 0 "register_operand")) | |
10971 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
10972 | (label_ref (match_operand 1)) | |
10973 | (pc)))] | |
10974 | "" | |
10975 | { | |
10976 | /* Offset from thread pointer to __private_ss. */ | |
10977 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
10978 | rtx tp = s390_get_thread_pointer (); | |
10979 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
10980 | rtx reg = gen_reg_rtx (Pmode); | |
10981 | rtx cc; | |
10982 | if (TARGET_64BIT) | |
10983 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
10984 | else | |
10985 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
10986 | cc = s390_emit_compare (GT, reg, guard); | |
10987 | s390_emit_jump (operands[1], cc); | |
10988 | ||
10989 | DONE; | |
10990 | }) | |
10991 | ||
10992 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
10993 | ;; parameter block label, label to be called by __morestack, frame size, | |
10994 | ;; stack parameter size. | |
10995 | ||
10996 | (define_insn "split_stack_data" | |
10997 | [(unspec_volatile [(match_operand 0 "" "X") | |
10998 | (match_operand 1 "" "X") | |
10999 | (match_operand 2 "const_int_operand" "X") | |
11000 | (match_operand 3 "const_int_operand" "X")] | |
11001 | UNSPECV_SPLIT_STACK_DATA)] | |
11002 | "TARGET_CPU_ZARCH" | |
11003 | { | |
11004 | switch_to_section (targetm.asm_out.function_rodata_section | |
11005 | (current_function_decl)); | |
11006 | ||
11007 | if (TARGET_64BIT) | |
11008 | output_asm_insn (".align\t8", operands); | |
11009 | else | |
11010 | output_asm_insn (".align\t4", operands); | |
11011 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11012 | CODE_LABEL_NUMBER (operands[0])); | |
11013 | if (TARGET_64BIT) | |
11014 | { | |
11015 | output_asm_insn (".quad\t%2", operands); | |
11016 | output_asm_insn (".quad\t%3", operands); | |
11017 | output_asm_insn (".quad\t%1-%0", operands); | |
11018 | } | |
11019 | else | |
11020 | { | |
11021 | output_asm_insn (".long\t%2", operands); | |
11022 | output_asm_insn (".long\t%3", operands); | |
11023 | output_asm_insn (".long\t%1-%0", operands); | |
11024 | } | |
11025 | ||
11026 | switch_to_section (current_function_section ()); | |
11027 | return ""; | |
11028 | } | |
11029 | [(set_attr "length" "0")]) | |
11030 | ||
11031 | ||
11032 | ;; A jg with minimal fuss for use in split stack prologue. | |
11033 | ||
11034 | (define_expand "split_stack_call" | |
11035 | [(match_operand 0 "bras_sym_operand" "X") | |
11036 | (match_operand 1 "" "")] | |
11037 | "TARGET_CPU_ZARCH" | |
11038 | { | |
11039 | if (TARGET_64BIT) | |
11040 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11041 | else | |
11042 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11043 | DONE; | |
11044 | }) | |
11045 | ||
11046 | (define_insn "split_stack_call_<mode>" | |
11047 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11048 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11049 | (reg:P 1)] | |
11050 | UNSPECV_SPLIT_STACK_CALL))] | |
11051 | "TARGET_CPU_ZARCH" | |
11052 | "jg\t%0" | |
11053 | [(set_attr "op_type" "RIL") | |
11054 | (set_attr "type" "branch")]) | |
11055 | ||
11056 | ;; Also a conditional one. | |
11057 | ||
11058 | (define_expand "split_stack_cond_call" | |
11059 | [(match_operand 0 "bras_sym_operand" "X") | |
11060 | (match_operand 1 "" "") | |
11061 | (match_operand 2 "" "")] | |
11062 | "TARGET_CPU_ZARCH" | |
11063 | { | |
11064 | if (TARGET_64BIT) | |
11065 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11066 | else | |
11067 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11068 | DONE; | |
11069 | }) | |
11070 | ||
11071 | (define_insn "split_stack_cond_call_<mode>" | |
11072 | [(set (pc) | |
11073 | (if_then_else | |
11074 | (match_operand 1 "" "") | |
11075 | (label_ref (match_operand 2 "" "")) | |
11076 | (pc))) | |
11077 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11078 | (reg:P 1)] | |
11079 | UNSPECV_SPLIT_STACK_CALL))] | |
11080 | "TARGET_CPU_ZARCH" | |
11081 | "jg%C1\t%0" | |
11082 | [(set_attr "op_type" "RIL") | |
11083 | (set_attr "type" "branch")]) |