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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
9c3c3dcc | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a | 20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
39d14dda KC |
21 | ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
22 | ;; 02110-1301, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
9dc62c00 | 28 | ;; c -- Condition code register 33. |
9db1d521 | 29 | ;; d -- Any register from 0 to 15. |
09366c43 AS |
30 | ;; f -- Floating point registers. |
31 | ;; t -- Access registers 36 and 37. | |
d096725d | 32 | ;; G -- Const double zero operand |
9db1d521 HP |
33 | ;; I -- An 8-bit constant (0..255). |
34 | ;; J -- A 12-bit constant (0..4095). | |
35 | ;; K -- A 16-bit constant (-32768..32767). | |
2f7e5a0d | 36 | ;; L -- Value appropriate as displacement. |
f19a9af7 AK |
37 | ;; (0..4095) for short displacement |
38 | ;; (-524288..524287) for long displacement | |
39 | ;; M -- Constant integer with a value of 0x7fffffff. | |
40 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
0dfa6c5e UW |
41 | ;; 0..9,x: number of the part counting from most to least significant |
42 | ;; H,Q: mode of the part | |
43 | ;; D,S,H: mode of the containing operand | |
44 | ;; 0,F: value of the other parts (F - all bits set) | |
2f7e5a0d | 45 | ;; |
f19a9af7 | 46 | ;; The constraint matches if the specified part of a constant |
0dfa6c5e UW |
47 | ;; has a value different from its other parts. If the letter x |
48 | ;; is specified instead of a part number, the constraint matches | |
49 | ;; if there is any single part with non-default value. | |
ec24698e UW |
50 | ;; O -- Multiple letter constraint followed by 1 parameter. |
51 | ;; s: Signed extended immediate value (-2G .. 2G-1). | |
52 | ;; p: Positive extended immediate value (0 .. 4G-1). | |
53 | ;; n: Negative extended immediate value (-4G .. -1). | |
54 | ;; These constraints do not accept any operand if the machine does | |
55 | ;; not provide the extended-immediate facility. | |
11598938 | 56 | ;; P -- Any integer constant that can be loaded without literal pool. |
f19a9af7 AK |
57 | ;; Q -- Memory reference without index register and with short displacement. |
58 | ;; R -- Memory reference with index register and short displacement. | |
59 | ;; S -- Memory reference without index register but with long displacement. | |
60 | ;; T -- Memory reference with index register and long displacement. | |
0dfa6c5e UW |
61 | ;; A -- Multiple letter constraint followed by Q, R, S, or T: |
62 | ;; Offsettable memory reference of type specified by second letter. | |
e221ef54 UW |
63 | ;; B -- Multiple letter constraint followed by Q, R, S, or T: |
64 | ;; Memory reference of the type specified by second letter that | |
65 | ;; does *not* refer to a literal pool entry. | |
f19a9af7 AK |
66 | ;; U -- Pointer with short displacement. |
67 | ;; W -- Pointer with long displacement. | |
68 | ;; Y -- Shift count operand. | |
9db1d521 HP |
69 | ;; |
70 | ;; Special formats used for outputting 390 instructions. | |
71 | ;; | |
f19a9af7 AK |
72 | ;; %C: print opcode suffix for branch condition. |
73 | ;; %D: print opcode suffix for inverse branch condition. | |
74 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 75 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
76 | ;; %O: print only the displacement of a memory reference. |
77 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 78 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
79 | ;; %N: print the second word of a DImode operand. |
80 | ;; %M: print the second word of a TImode operand. | |
da48f5ec AK |
81 | ;; %Y: print shift count operand. |
82 | ;; | |
f19a9af7 | 83 | ;; %b: print integer X as if it's an unsigned byte. |
da48f5ec AK |
84 | ;; %x: print integer X as if it's an unsigned halfword. |
85 | ;; %h: print integer X as if it's a signed halfword. | |
86 | ;; %i: print the first nonzero HImode part of X. | |
87 | ;; %j: print the first HImode part unequal to -1 of X. | |
88 | ;; %k: print the first nonzero SImode part of X. | |
89 | ;; %m: print the first SImode part unequal to -1 of X. | |
90 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
91 | ;; |
92 | ;; We have a special constraint for pattern matching. | |
93 | ;; | |
94 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
95 | ;; | |
9db1d521 | 96 | |
fd3cd001 UW |
97 | ;; |
98 | ;; UNSPEC usage | |
99 | ;; | |
100 | ||
101 | (define_constants | |
10bbf137 UW |
102 | [; Miscellaneous |
103 | (UNSPEC_ROUND 1) | |
5b022de5 | 104 | (UNSPEC_CMPINT 2) |
6fa05db6 | 105 | (UNSPEC_ICM 10) |
10bbf137 UW |
106 | |
107 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
108 | (UNSPEC_LTREL_OFFSET 100) |
109 | (UNSPEC_LTREL_BASE 101) | |
110 | (UNSPEC_GOTENT 110) | |
111 | (UNSPEC_GOT 111) | |
112 | (UNSPEC_GOTOFF 112) | |
113 | (UNSPEC_PLT 113) | |
114 | (UNSPEC_PLTOFF 114) | |
115 | ||
116 | ; Literal pool | |
117 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 118 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 119 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
120 | (UNSPEC_INSN 213) |
121 | (UNSPEC_EXECUTE 214) | |
fd7643fb UW |
122 | |
123 | ; TLS relocation specifiers | |
fd3cd001 UW |
124 | (UNSPEC_TLSGD 500) |
125 | (UNSPEC_TLSLDM 501) | |
126 | (UNSPEC_NTPOFF 502) | |
127 | (UNSPEC_DTPOFF 503) | |
128 | (UNSPEC_GOTNTPOFF 504) | |
129 | (UNSPEC_INDNTPOFF 505) | |
130 | ||
131 | ; TLS support | |
fd3cd001 UW |
132 | (UNSPEC_TLSLDM_NTPOFF 511) |
133 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
134 | |
135 | ; String Functions | |
7b8acc34 | 136 | (UNSPEC_SRST 600) |
742090fc | 137 | (UNSPEC_MVST 601) |
7b8acc34 AK |
138 | |
139 | ; Stack Smashing Protector | |
140 | (UNSPEC_SP_SET 700) | |
141 | (UNSPEC_SP_TEST 701) | |
fd3cd001 UW |
142 | ]) |
143 | ||
144 | ;; | |
145 | ;; UNSPEC_VOLATILE usage | |
146 | ;; | |
147 | ||
148 | (define_constants | |
10bbf137 UW |
149 | [; Blockage |
150 | (UNSPECV_BLOCKAGE 0) | |
151 | ||
2f7e5a0d EC |
152 | ; TPF Support |
153 | (UNSPECV_TPF_PROLOGUE 20) | |
154 | (UNSPECV_TPF_EPILOGUE 21) | |
155 | ||
10bbf137 | 156 | ; Literal pool |
fd7643fb | 157 | (UNSPECV_POOL 200) |
9bb86f41 UW |
158 | (UNSPECV_POOL_SECTION 201) |
159 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 160 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
161 | (UNSPECV_MAIN_POOL 300) |
162 | ||
163 | ; TLS support | |
fd3cd001 | 164 | (UNSPECV_SET_TP 500) |
e0374221 AS |
165 | |
166 | ; Atomic Support | |
167 | (UNSPECV_MB 700) | |
168 | (UNSPECV_CAS 701) | |
fd3cd001 UW |
169 | ]) |
170 | ||
ae156f85 AS |
171 | ;; |
172 | ;; Registers | |
173 | ;; | |
174 | ||
175 | (define_constants | |
176 | [ | |
177 | ; Sibling call register. | |
178 | (SIBCALL_REGNUM 1) | |
179 | ; Literal pool base register. | |
180 | (BASE_REGNUM 13) | |
181 | ; Return address register. | |
182 | (RETURN_REGNUM 14) | |
183 | ; Condition code register. | |
184 | (CC_REGNUM 33) | |
185 | ; Thread local storage pointer register. | |
186 | (TP_REGNUM 36) | |
187 | ]) | |
188 | ||
fd3cd001 | 189 | |
29a74354 UW |
190 | ;; Instruction operand type as used in the Principles of Operation. |
191 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 192 | |
29a74354 UW |
193 | (define_attr "op_type" |
194 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" | |
b628bd8e | 195 | (const_string "NN")) |
9db1d521 | 196 | |
29a74354 | 197 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 198 | |
077dab3b | 199 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 200 | cs,vs,store,sem,idiv, |
ed0e512a | 201 | imulhi,imulsi,imuldi, |
cfdb984b AS |
202 | branch,jsr,fsimpdf,fsimpsf, |
203 | floaddf,floadsf,fstoredf,fstoresf, | |
204 | fmuldf,fmulsf,fdivdf,fdivsf, | |
205 | ftoi,itof,fsqrtdf,fsqrtsf, | |
a036c6f7 | 206 | other" |
29a74354 UW |
207 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
208 | (eq_attr "op_type" "SS") (const_string "cs")] | |
209 | (const_string "integer"))) | |
9db1d521 | 210 | |
29a74354 UW |
211 | ;; Another attribute used for scheduling purposes: |
212 | ;; agen: Instruction uses the address generation unit | |
213 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
214 | |
215 | (define_attr "atype" "agen,reg" | |
b628bd8e | 216 | (cond [(eq_attr "op_type" "E") (const_string "reg") |
077dab3b HP |
217 | (eq_attr "op_type" "RR") (const_string "reg") |
218 | (eq_attr "op_type" "RX") (const_string "agen") | |
219 | (eq_attr "op_type" "RI") (const_string "reg") | |
220 | (eq_attr "op_type" "RRE") (const_string "reg") | |
221 | (eq_attr "op_type" "RS") (const_string "agen") | |
222 | (eq_attr "op_type" "RSI") (const_string "agen") | |
223 | (eq_attr "op_type" "S") (const_string "agen") | |
224 | (eq_attr "op_type" "SI") (const_string "agen") | |
225 | (eq_attr "op_type" "SS") (const_string "agen") | |
226 | (eq_attr "op_type" "SSE") (const_string "agen") | |
227 | (eq_attr "op_type" "RXE") (const_string "agen") | |
228 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
229 | (eq_attr "op_type" "RIL") (const_string "agen") |
230 | (eq_attr "op_type" "RXY") (const_string "agen") | |
231 | (eq_attr "op_type" "RSY") (const_string "agen") | |
232 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
b628bd8e | 233 | (const_string "agen"))) |
9db1d521 | 234 | |
9db1d521 HP |
235 | ;; Length in bytes. |
236 | ||
237 | (define_attr "length" "" | |
b628bd8e | 238 | (cond [(eq_attr "op_type" "E") (const_int 2) |
9db1d521 HP |
239 | (eq_attr "op_type" "RR") (const_int 2) |
240 | (eq_attr "op_type" "RX") (const_int 4) | |
241 | (eq_attr "op_type" "RI") (const_int 4) | |
242 | (eq_attr "op_type" "RRE") (const_int 4) | |
243 | (eq_attr "op_type" "RS") (const_int 4) | |
244 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
245 | (eq_attr "op_type" "S") (const_int 4) |
246 | (eq_attr "op_type" "SI") (const_int 4) | |
247 | (eq_attr "op_type" "SS") (const_int 6) | |
248 | (eq_attr "op_type" "SSE") (const_int 6) | |
249 | (eq_attr "op_type" "RXE") (const_int 6) | |
250 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
251 | (eq_attr "op_type" "RIL") (const_int 6) |
252 | (eq_attr "op_type" "RXY") (const_int 6) | |
253 | (eq_attr "op_type" "RSY") (const_int 6) | |
254 | (eq_attr "op_type" "SIY") (const_int 6)] | |
b628bd8e | 255 | (const_int 6))) |
9db1d521 | 256 | |
29a74354 UW |
257 | |
258 | ;; Processor type. This attribute must exactly match the processor_type | |
259 | ;; enumeration in s390.h. The current machine description does not | |
260 | ;; distinguish between g5 and g6, but there are differences between the two | |
261 | ;; CPUs could in theory be modeled. | |
262 | ||
ec24698e | 263 | (define_attr "cpu" "g5,g6,z900,z990,z9_109" |
29a74354 UW |
264 | (const (symbol_ref "s390_tune"))) |
265 | ||
266 | ;; Pipeline description for z900. For lack of anything better, | |
267 | ;; this description is also used for the g5 and g6. | |
268 | (include "2064.md") | |
269 | ||
270 | ;; Pipeline description for z990. | |
271 | (include "2084.md") | |
272 | ||
0bfc3f69 AS |
273 | ;; Predicates |
274 | (include "predicates.md") | |
275 | ||
a8ba31f2 EC |
276 | ;; Other includes |
277 | (include "tpf.md") | |
f52c81dd AS |
278 | |
279 | ;; Macros | |
280 | ||
f5905b37 AS |
281 | ;; This mode macro allows DF and SF patterns to be generated from the |
282 | ;; same template. | |
283 | (define_mode_macro FPR [DF SF]) | |
284 | ||
8006eaa6 AS |
285 | ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated |
286 | ;; from the same template. | |
287 | (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI]) | |
288 | ||
9a91a21f | 289 | ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d AS |
290 | ;; from the same template. |
291 | (define_mode_macro GPR [(DI "TARGET_64BIT") SI]) | |
9a91a21f | 292 | (define_mode_macro DSI [DI SI]) |
9db2f16d AS |
293 | |
294 | ;; This mode macro allows :P to be used for patterns that operate on | |
295 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
8006eaa6 | 296 | (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")]) |
9db2f16d AS |
297 | (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
298 | ||
f52c81dd AS |
299 | ;; This mode macro allows the QI and HI patterns to be defined from |
300 | ;; the same template. | |
301 | (define_mode_macro HQI [HI QI]) | |
302 | ||
342cf42b AS |
303 | ;; This mode macro allows the integer patterns to be defined from the |
304 | ;; same template. | |
305 | (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI]) | |
306 | ||
fa77b251 AS |
307 | ;; This macro allows to unify all 'bCOND' expander patterns. |
308 | (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered | |
309 | ordered uneq unlt ungt unle unge ltgt]) | |
310 | ||
9a91a21f AS |
311 | ;; This macro allows to unify all 'sCOND' patterns. |
312 | (define_code_macro SCOND [ltu gtu leu geu]) | |
313 | ||
f337b930 AS |
314 | ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from |
315 | ;; the same template. | |
316 | (define_code_macro SHIFT [ashift lshiftrt]) | |
317 | ||
318 | ||
f5905b37 AS |
319 | ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode |
320 | ;; and "ltebr" in SFmode. | |
321 | (define_mode_attr de [(DF "d") (SF "e")]) | |
322 | ||
323 | ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode | |
324 | ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern. | |
325 | (define_mode_attr dee [(DF "d") (SF "ee")]) | |
326 | ||
f337b930 AS |
327 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in |
328 | ;; 'ashift' and "srdl" in 'lshiftrt'. | |
329 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
330 | ||
331 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
332 | ;; pattern itself and the corresponding function calls. | |
333 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) | |
9a91a21f AS |
334 | |
335 | ;; This attribute handles differences in the instruction 'type' and will result | |
336 | ;; in "RRE" for DImode and "RR" for SImode. | |
337 | (define_mode_attr E [(DI "E") (SI "")]) | |
338 | ||
8006eaa6 AS |
339 | ;; This attribute handles differences in the instruction 'type' and will result |
340 | ;; in "RSE" for TImode and "RS" for DImode. | |
341 | (define_mode_attr TE [(TI "E") (DI "")]) | |
342 | ||
9a91a21f AS |
343 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
344 | ;; and "lcr" in SImode. | |
345 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 346 | |
8006eaa6 AS |
347 | ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode |
348 | ;; and "cds" in DImode. | |
349 | (define_mode_attr tg [(TI "g") (DI "")]) | |
350 | ||
2f8f8434 AS |
351 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
352 | ;; and "cfdbr" in SImode. | |
353 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
354 | ||
f52c81dd AS |
355 | ;; ICM mask required to load MODE value into the lowest subreg |
356 | ;; of a SImode register. | |
357 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
358 | ||
f6ee577c AS |
359 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
360 | ;; HImode and "llgc" in QImode. | |
361 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
362 | ||
a1aed706 AS |
363 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
364 | ;; in SImode. | |
365 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
366 | ||
f52c81dd AS |
367 | ;; Maximum unsigned integer that fits in MODE. |
368 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
369 | ||
370 | ||
9db1d521 HP |
371 | ;; |
372 | ;;- Compare instructions. | |
373 | ;; | |
374 | ||
9db2f16d | 375 | (define_expand "cmp<mode>" |
ae156f85 | 376 | [(set (reg:CC CC_REGNUM) |
9db2f16d AS |
377 | (compare:CC (match_operand:GPR 0 "register_operand" "") |
378 | (match_operand:GPR 1 "general_operand" "")))] | |
9db1d521 | 379 | "" |
9db1d521 HP |
380 | { |
381 | s390_compare_op0 = operands[0]; | |
382 | s390_compare_op1 = operands[1]; | |
383 | DONE; | |
10bbf137 | 384 | }) |
9db1d521 | 385 | |
f5905b37 | 386 | (define_expand "cmp<mode>" |
ae156f85 | 387 | [(set (reg:CC CC_REGNUM) |
f5905b37 AS |
388 | (compare:CC (match_operand:FPR 0 "register_operand" "") |
389 | (match_operand:FPR 1 "general_operand" "")))] | |
9db1d521 | 390 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
391 | { |
392 | s390_compare_op0 = operands[0]; | |
393 | s390_compare_op1 = operands[1]; | |
394 | DONE; | |
10bbf137 | 395 | }) |
9db1d521 HP |
396 | |
397 | ||
07893d4f | 398 | ; Test-under-Mask instructions |
9db1d521 | 399 | |
07893d4f | 400 | (define_insn "*tmqi_mem" |
ae156f85 | 401 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
402 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
403 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
404 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 405 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 406 | "@ |
fc0ea003 UW |
407 | tm\t%S0,%b1 |
408 | tmy\t%S0,%b1" | |
d3632d41 | 409 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 410 | |
05b9aaaa | 411 | (define_insn "*tmdi_reg" |
ae156f85 | 412 | [(set (reg CC_REGNUM) |
f19a9af7 | 413 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 414 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
415 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
416 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa | 417 | "TARGET_64BIT |
3ed99cc9 | 418 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
419 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
420 | "@ | |
421 | tmhh\t%0,%i1 | |
422 | tmhl\t%0,%i1 | |
423 | tmlh\t%0,%i1 | |
424 | tmll\t%0,%i1" | |
05b9aaaa UW |
425 | [(set_attr "op_type" "RI")]) |
426 | ||
427 | (define_insn "*tmsi_reg" | |
ae156f85 | 428 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
429 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
430 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
431 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 432 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
433 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
434 | "@ | |
435 | tmh\t%0,%i1 | |
436 | tml\t%0,%i1" | |
05b9aaaa UW |
437 | [(set_attr "op_type" "RI")]) |
438 | ||
f52c81dd | 439 | (define_insn "*tm<mode>_full" |
ae156f85 | 440 | [(set (reg CC_REGNUM) |
f52c81dd AS |
441 | (compare (match_operand:HQI 0 "register_operand" "d") |
442 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 443 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 444 | "tml\t%0,<max_uint>" |
07893d4f | 445 | [(set_attr "op_type" "RI")]) |
9db1d521 | 446 | |
07893d4f UW |
447 | |
448 | ; Load-and-Test instructions | |
449 | ||
450 | (define_insn "*tstdi_sign" | |
ae156f85 | 451 | [(set (reg CC_REGNUM) |
07893d4f UW |
452 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
453 | (const_int 32)) (const_int 32)) | |
454 | (match_operand:DI 1 "const0_operand" ""))) | |
455 | (set (match_operand:DI 2 "register_operand" "=d") | |
456 | (sign_extend:DI (match_dup 0)))] | |
457 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 458 | "ltgfr\t%2,%0" |
07893d4f UW |
459 | [(set_attr "op_type" "RRE")]) |
460 | ||
ec24698e UW |
461 | (define_insn "*tstdi_extimm" |
462 | [(set (reg CC_REGNUM) | |
463 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,m") | |
464 | (match_operand:DI 1 "const0_operand" ""))) | |
465 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
466 | (match_dup 0))] | |
467 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM" | |
468 | "@ | |
469 | ltgr\t%2,%0 | |
470 | ltg\t%2,%0" | |
471 | [(set_attr "op_type" "RRE,RXY")]) | |
472 | ||
473 | (define_insn "*tstdi_cconly_extimm" | |
474 | [(set (reg CC_REGNUM) | |
475 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,m") | |
476 | (match_operand:DI 1 "const0_operand" ""))) | |
477 | (clobber (match_scratch:DI 2 "=X,d"))] | |
478 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM" | |
479 | "@ | |
480 | ltgr\t%0,%0 | |
481 | ltg\t%2,%0" | |
482 | [(set_attr "op_type" "RRE,RXY")]) | |
483 | ||
07893d4f | 484 | (define_insn "*tstdi" |
ae156f85 | 485 | [(set (reg CC_REGNUM) |
07893d4f UW |
486 | (compare (match_operand:DI 0 "register_operand" "d") |
487 | (match_operand:DI 1 "const0_operand" ""))) | |
488 | (set (match_operand:DI 2 "register_operand" "=d") | |
489 | (match_dup 0))] | |
ec24698e | 490 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" |
d40c829f | 491 | "ltgr\t%2,%0" |
07893d4f | 492 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 493 | |
07893d4f | 494 | (define_insn "*tstdi_cconly" |
ae156f85 | 495 | [(set (reg CC_REGNUM) |
07893d4f UW |
496 | (compare (match_operand:DI 0 "register_operand" "d") |
497 | (match_operand:DI 1 "const0_operand" "")))] | |
498 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 499 | "ltgr\t%0,%0" |
07893d4f | 500 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 501 | |
07893d4f | 502 | (define_insn "*tstdi_cconly_31" |
ae156f85 | 503 | [(set (reg CC_REGNUM) |
07893d4f UW |
504 | (compare (match_operand:DI 0 "register_operand" "d") |
505 | (match_operand:DI 1 "const0_operand" "")))] | |
506 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 507 | "srda\t%0,0" |
077dab3b HP |
508 | [(set_attr "op_type" "RS") |
509 | (set_attr "atype" "reg")]) | |
510 | ||
ec24698e UW |
511 | (define_insn "*tstsi_extimm" |
512 | [(set (reg CC_REGNUM) | |
513 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,m") | |
514 | (match_operand:SI 1 "const0_operand" ""))) | |
515 | (set (match_operand:SI 2 "register_operand" "=d,d") | |
516 | (match_dup 0))] | |
517 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
518 | "@ | |
519 | ltr\t%2,%0 | |
520 | lt\t%2,%0" | |
521 | [(set_attr "op_type" "RR,RXY")]) | |
522 | ||
523 | (define_insn "*tstsi_cconly_extimm" | |
524 | [(set (reg CC_REGNUM) | |
525 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,m") | |
526 | (match_operand:SI 1 "const0_operand" ""))) | |
527 | (clobber (match_scratch:SI 2 "=X,d"))] | |
528 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
529 | "@ | |
530 | ltr\t%0,%0 | |
531 | lt\t%2,%0" | |
532 | [(set_attr "op_type" "RR,RXY")]) | |
4023fb28 | 533 | |
07893d4f | 534 | (define_insn "*tstsi" |
ae156f85 | 535 | [(set (reg CC_REGNUM) |
d3632d41 | 536 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 537 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 538 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 539 | (match_dup 0))] |
ec24698e | 540 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 541 | "@ |
d40c829f | 542 | ltr\t%2,%0 |
fc0ea003 UW |
543 | icm\t%2,15,%S0 |
544 | icmy\t%2,15,%S0" | |
d3632d41 | 545 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 546 | |
07893d4f | 547 | (define_insn "*tstsi_cconly" |
ae156f85 | 548 | [(set (reg CC_REGNUM) |
d3632d41 | 549 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 550 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 551 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
552 | "s390_match_ccmode(insn, CCSmode)" |
553 | "@ | |
d40c829f | 554 | ltr\t%0,%0 |
fc0ea003 UW |
555 | icm\t%2,15,%S0 |
556 | icmy\t%2,15,%S0" | |
d3632d41 | 557 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 558 | |
07893d4f | 559 | (define_insn "*tstsi_cconly2" |
ae156f85 | 560 | [(set (reg CC_REGNUM) |
07893d4f UW |
561 | (compare (match_operand:SI 0 "register_operand" "d") |
562 | (match_operand:SI 1 "const0_operand" "")))] | |
563 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 564 | "ltr\t%0,%0" |
07893d4f | 565 | [(set_attr "op_type" "RR")]) |
4023fb28 | 566 | |
f52c81dd | 567 | (define_insn "*tst<mode>CCT" |
ae156f85 | 568 | [(set (reg CC_REGNUM) |
f52c81dd AS |
569 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
570 | (match_operand:HQI 1 "const0_operand" ""))) | |
571 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
572 | (match_dup 0))] |
573 | "s390_match_ccmode(insn, CCTmode)" | |
574 | "@ | |
f52c81dd AS |
575 | icm\t%2,<icm_lo>,%S0 |
576 | icmy\t%2,<icm_lo>,%S0 | |
577 | tml\t%0,<max_uint>" | |
d3632d41 | 578 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
579 | |
580 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 581 | [(set (reg CC_REGNUM) |
d3632d41 | 582 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 583 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 584 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
585 | "s390_match_ccmode(insn, CCTmode)" |
586 | "@ | |
fc0ea003 UW |
587 | icm\t%2,3,%S0 |
588 | icmy\t%2,3,%S0 | |
d40c829f | 589 | tml\t%0,65535" |
d3632d41 | 590 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 591 | |
3af97654 | 592 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 593 | [(set (reg CC_REGNUM) |
d3632d41 | 594 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
595 | (match_operand:QI 1 "const0_operand" "")))] |
596 | "s390_match_ccmode(insn, CCTmode)" | |
597 | "@ | |
fc0ea003 UW |
598 | cli\t%S0,0 |
599 | cliy\t%S0,0 | |
d40c829f | 600 | tml\t%0,255" |
d3632d41 | 601 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 602 | |
f52c81dd | 603 | (define_insn "*tst<mode>" |
ae156f85 | 604 | [(set (reg CC_REGNUM) |
f52c81dd AS |
605 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
606 | (match_operand:HQI 1 "const0_operand" ""))) | |
607 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
608 | (match_dup 0))] |
609 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 610 | "@ |
f52c81dd AS |
611 | icm\t%2,<icm_lo>,%S0 |
612 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 | 613 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 614 | |
f52c81dd | 615 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 616 | [(set (reg CC_REGNUM) |
f52c81dd AS |
617 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
618 | (match_operand:HQI 1 "const0_operand" ""))) | |
619 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 620 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 621 | "@ |
f52c81dd AS |
622 | icm\t%2,<icm_lo>,%S0 |
623 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 UW |
624 | [(set_attr "op_type" "RS,RSY")]) |
625 | ||
9db1d521 | 626 | |
575f7c2b UW |
627 | ; Compare (equality) instructions |
628 | ||
629 | (define_insn "*cmpdi_cct" | |
ae156f85 | 630 | [(set (reg CC_REGNUM) |
ec24698e UW |
631 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
632 | (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))] | |
e221ef54 | 633 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" |
575f7c2b UW |
634 | "@ |
635 | cgr\t%0,%1 | |
f4f41b4e | 636 | cghi\t%0,%h1 |
ec24698e | 637 | cgfi\t%0,%1 |
575f7c2b | 638 | cg\t%0,%1 |
19b63d8e | 639 | #" |
ec24698e | 640 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")]) |
575f7c2b UW |
641 | |
642 | (define_insn "*cmpsi_cct" | |
ae156f85 | 643 | [(set (reg CC_REGNUM) |
ec24698e UW |
644 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
645 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 646 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
647 | "@ |
648 | cr\t%0,%1 | |
f4f41b4e | 649 | chi\t%0,%h1 |
ec24698e | 650 | cfi\t%0,%1 |
575f7c2b UW |
651 | c\t%0,%1 |
652 | cy\t%0,%1 | |
19b63d8e | 653 | #" |
ec24698e | 654 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")]) |
575f7c2b UW |
655 | |
656 | ||
07893d4f | 657 | ; Compare (signed) instructions |
4023fb28 | 658 | |
07893d4f | 659 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 660 | [(set (reg CC_REGNUM) |
07893d4f UW |
661 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
662 | (match_operand:DI 0 "register_operand" "d,d")))] | |
663 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 664 | "@ |
d40c829f UW |
665 | cgfr\t%0,%1 |
666 | cgf\t%0,%1" | |
d3632d41 | 667 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 668 | |
07893d4f | 669 | (define_insn "*cmpdi_ccs" |
ae156f85 | 670 | [(set (reg CC_REGNUM) |
ec24698e UW |
671 | (compare (match_operand:DI 0 "register_operand" "d,d,d,d") |
672 | (match_operand:DI 1 "general_operand" "d,K,Os,m")))] | |
07893d4f UW |
673 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
674 | "@ | |
d40c829f | 675 | cgr\t%0,%1 |
f4f41b4e | 676 | cghi\t%0,%h1 |
ec24698e | 677 | cgfi\t%0,%1 |
d40c829f | 678 | cg\t%0,%1" |
ec24698e | 679 | [(set_attr "op_type" "RRE,RI,RIL,RXY")]) |
c7453384 | 680 | |
07893d4f | 681 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 682 | [(set (reg CC_REGNUM) |
d3632d41 UW |
683 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
684 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 685 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 686 | "@ |
d40c829f UW |
687 | ch\t%0,%1 |
688 | chy\t%0,%1" | |
d3632d41 | 689 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 690 | |
07893d4f | 691 | (define_insn "*cmpsi_ccs" |
ae156f85 | 692 | [(set (reg CC_REGNUM) |
ec24698e UW |
693 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d") |
694 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))] | |
9db1d521 | 695 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 696 | "@ |
d40c829f | 697 | cr\t%0,%1 |
f4f41b4e | 698 | chi\t%0,%h1 |
ec24698e | 699 | cfi\t%0,%1 |
d40c829f UW |
700 | c\t%0,%1 |
701 | cy\t%0,%1" | |
ec24698e | 702 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY")]) |
c7453384 | 703 | |
07893d4f UW |
704 | |
705 | ; Compare (unsigned) instructions | |
9db1d521 | 706 | |
07893d4f | 707 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 708 | [(set (reg CC_REGNUM) |
07893d4f UW |
709 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
710 | (match_operand:DI 0 "register_operand" "d,d")))] | |
575f7c2b | 711 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 712 | "@ |
d40c829f UW |
713 | clgfr\t%0,%1 |
714 | clgf\t%0,%1" | |
d3632d41 | 715 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 716 | |
07893d4f | 717 | (define_insn "*cmpdi_ccu" |
ae156f85 | 718 | [(set (reg CC_REGNUM) |
ec24698e UW |
719 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ") |
720 | (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))] | |
e221ef54 | 721 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" |
07893d4f | 722 | "@ |
d40c829f | 723 | clgr\t%0,%1 |
ec24698e | 724 | clgfi\t%0,%1 |
575f7c2b | 725 | clg\t%0,%1 |
e221ef54 | 726 | # |
19b63d8e | 727 | #" |
ec24698e | 728 | [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")]) |
9db1d521 | 729 | |
07893d4f | 730 | (define_insn "*cmpsi_ccu" |
ae156f85 | 731 | [(set (reg CC_REGNUM) |
ec24698e UW |
732 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ") |
733 | (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))] | |
e221ef54 | 734 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 735 | "@ |
d40c829f | 736 | clr\t%0,%1 |
ec24698e | 737 | clfi\t%0,%o1 |
d40c829f | 738 | cl\t%0,%1 |
575f7c2b | 739 | cly\t%0,%1 |
e221ef54 | 740 | # |
19b63d8e | 741 | #" |
ec24698e | 742 | [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")]) |
9db1d521 | 743 | |
07893d4f | 744 | (define_insn "*cmphi_ccu" |
ae156f85 | 745 | [(set (reg CC_REGNUM) |
e221ef54 UW |
746 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") |
747 | (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] | |
575f7c2b | 748 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 749 | && !register_operand (operands[1], HImode)" |
d3632d41 | 750 | "@ |
fc0ea003 UW |
751 | clm\t%0,3,%S1 |
752 | clmy\t%0,3,%S1 | |
e221ef54 | 753 | # |
19b63d8e | 754 | #" |
e221ef54 | 755 | [(set_attr "op_type" "RS,RSY,SS,SS")]) |
9db1d521 HP |
756 | |
757 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 758 | [(set (reg CC_REGNUM) |
e221ef54 UW |
759 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
760 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 761 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 762 | && !register_operand (operands[1], QImode)" |
d3632d41 | 763 | "@ |
fc0ea003 UW |
764 | clm\t%0,1,%S1 |
765 | clmy\t%0,1,%S1 | |
766 | cli\t%S0,%b1 | |
767 | cliy\t%S0,%b1 | |
e221ef54 | 768 | # |
19b63d8e | 769 | #" |
e221ef54 | 770 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) |
9db1d521 HP |
771 | |
772 | ||
19b63d8e UW |
773 | ; Block compare (CLC) instruction patterns. |
774 | ||
775 | (define_insn "*clc" | |
ae156f85 | 776 | [(set (reg CC_REGNUM) |
d4f52f0e | 777 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
778 | (match_operand:BLK 1 "memory_operand" "Q"))) |
779 | (use (match_operand 2 "const_int_operand" "n"))] | |
780 | "s390_match_ccmode (insn, CCUmode) | |
781 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 782 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 783 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
784 | |
785 | (define_split | |
ae156f85 | 786 | [(set (reg CC_REGNUM) |
19b63d8e UW |
787 | (compare (match_operand 0 "memory_operand" "") |
788 | (match_operand 1 "memory_operand" "")))] | |
789 | "reload_completed | |
790 | && s390_match_ccmode (insn, CCUmode) | |
791 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
792 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
793 | [(parallel | |
794 | [(set (match_dup 0) (match_dup 1)) | |
795 | (use (match_dup 2))])] | |
796 | { | |
797 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
798 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
799 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
800 | ||
801 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
802 | operands[0], operands[1]); | |
803 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
804 | }) | |
805 | ||
806 | ||
f5905b37 | 807 | ; (DF|SF) instructions |
9db1d521 | 808 | |
f5905b37 | 809 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 810 | [(set (reg CC_REGNUM) |
f5905b37 AS |
811 | (compare (match_operand:FPR 0 "register_operand" "f") |
812 | (match_operand:FPR 1 "const0_operand" "")))] | |
9db1d521 | 813 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 814 | "lt<de>br\t%0,%0" |
077dab3b | 815 | [(set_attr "op_type" "RRE") |
f5905b37 | 816 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 817 | |
f5905b37 | 818 | (define_insn "*cmp<mode>_ccs_0_ibm" |
ae156f85 | 819 | [(set (reg CC_REGNUM) |
f5905b37 AS |
820 | (compare (match_operand:FPR 0 "register_operand" "f") |
821 | (match_operand:FPR 1 "const0_operand" "")))] | |
9db1d521 | 822 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 823 | "lt<de>r\t%0,%0" |
077dab3b | 824 | [(set_attr "op_type" "RR") |
f5905b37 | 825 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 826 | |
f5905b37 | 827 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 828 | [(set (reg CC_REGNUM) |
f5905b37 AS |
829 | (compare (match_operand:FPR 0 "register_operand" "f,f") |
830 | (match_operand:FPR 1 "general_operand" "f,R")))] | |
9db1d521 HP |
831 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
832 | "@ | |
f5905b37 AS |
833 | c<de>br\t%0,%1 |
834 | c<de>b\t%0,%1" | |
077dab3b | 835 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 836 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 837 | |
f5905b37 | 838 | (define_insn "*cmp<mode>_ccs_ibm" |
ae156f85 | 839 | [(set (reg CC_REGNUM) |
f5905b37 AS |
840 | (compare (match_operand:FPR 0 "register_operand" "f,f") |
841 | (match_operand:FPR 1 "general_operand" "f,R")))] | |
9db1d521 HP |
842 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
843 | "@ | |
f5905b37 AS |
844 | c<de>r\t%0,%1 |
845 | c<de>\t%0,%1" | |
077dab3b | 846 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 847 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
848 | |
849 | ||
850 | ;; | |
851 | ;;- Move instructions. | |
852 | ;; | |
853 | ||
854 | ; | |
855 | ; movti instruction pattern(s). | |
856 | ; | |
857 | ||
858 | (define_insn "movti" | |
d3632d41 | 859 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
11598938 | 860 | (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))] |
9db1d521 | 861 | "TARGET_64BIT" |
4023fb28 | 862 | "@ |
fc0ea003 UW |
863 | lmg\t%0,%N0,%S1 |
864 | stmg\t%1,%N1,%S0 | |
4023fb28 | 865 | # |
9b7c75b9 | 866 | # |
19b63d8e | 867 | #" |
b628bd8e UW |
868 | [(set_attr "op_type" "RSY,RSY,*,*,SS") |
869 | (set_attr "type" "lm,stm,*,*,*")]) | |
4023fb28 UW |
870 | |
871 | (define_split | |
872 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
873 | (match_operand:TI 1 "general_operand" ""))] | |
874 | "TARGET_64BIT && reload_completed | |
dc65c307 | 875 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
876 | [(set (match_dup 2) (match_dup 4)) |
877 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 878 | { |
dc65c307 UW |
879 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
880 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
881 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
882 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
883 | }) | |
884 | ||
885 | (define_split | |
886 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
887 | (match_operand:TI 1 "general_operand" ""))] | |
888 | "TARGET_64BIT && reload_completed | |
889 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
890 | [(set (match_dup 2) (match_dup 4)) | |
891 | (set (match_dup 3) (match_dup 5))] | |
892 | { | |
893 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
894 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
895 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
896 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
897 | }) | |
4023fb28 UW |
898 | |
899 | (define_split | |
900 | [(set (match_operand:TI 0 "register_operand" "") | |
901 | (match_operand:TI 1 "memory_operand" ""))] | |
902 | "TARGET_64BIT && reload_completed | |
903 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 904 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
905 | { |
906 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
907 | s390_load_address (addr, XEXP (operands[1], 0)); | |
908 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
909 | }) |
910 | ||
911 | (define_expand "reload_outti" | |
9c3c3dcc | 912 | [(parallel [(match_operand:TI 0 "" "") |
dc65c307 UW |
913 | (match_operand:TI 1 "register_operand" "d") |
914 | (match_operand:DI 2 "register_operand" "=&a")])] | |
915 | "TARGET_64BIT" | |
916 | { | |
9c3c3dcc | 917 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 918 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
919 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
920 | emit_move_insn (operands[0], operands[1]); | |
921 | DONE; | |
922 | }) | |
9db1d521 HP |
923 | |
924 | ; | |
925 | ; movdi instruction pattern(s). | |
926 | ; | |
927 | ||
9db1d521 HP |
928 | (define_expand "movdi" |
929 | [(set (match_operand:DI 0 "general_operand" "") | |
930 | (match_operand:DI 1 "general_operand" ""))] | |
931 | "" | |
9db1d521 | 932 | { |
fd3cd001 UW |
933 | /* Handle symbolic constants. */ |
934 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
935 | emit_symbolic_move (operands); | |
10bbf137 | 936 | }) |
9db1d521 | 937 | |
4023fb28 UW |
938 | (define_insn "*movdi_larl" |
939 | [(set (match_operand:DI 0 "register_operand" "=d") | |
940 | (match_operand:DI 1 "larl_operand" "X"))] | |
941 | "TARGET_64BIT | |
8e509cf9 | 942 | && !FP_REG_P (operands[0])" |
d40c829f | 943 | "larl\t%0,%1" |
4023fb28 | 944 | [(set_attr "op_type" "RIL") |
077dab3b | 945 | (set_attr "type" "larl")]) |
4023fb28 | 946 | |
ec24698e UW |
947 | (define_insn "*movdi_64extimm" |
948 | [(set (match_operand:DI 0 "nonimmediate_operand" | |
949 | "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") | |
950 | (match_operand:DI 1 "general_operand" | |
951 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] | |
952 | "TARGET_64BIT && TARGET_EXTIMM" | |
953 | "@ | |
954 | lghi\t%0,%h1 | |
955 | llihh\t%0,%i1 | |
956 | llihl\t%0,%i1 | |
957 | llilh\t%0,%i1 | |
958 | llill\t%0,%i1 | |
959 | lgfi\t%0,%1 | |
960 | llihf\t%0,%k1 | |
961 | llilf\t%0,%k1 | |
962 | lay\t%0,%a1 | |
963 | lgr\t%0,%1 | |
964 | lg\t%0,%1 | |
965 | stg\t%1,%0 | |
966 | ldr\t%0,%1 | |
967 | ld\t%0,%1 | |
968 | ldy\t%0,%1 | |
969 | std\t%1,%0 | |
970 | stdy\t%1,%0 | |
971 | # | |
972 | # | |
973 | stam\t%1,%N1,%S0 | |
974 | lam\t%0,%N0,%S1 | |
975 | #" | |
976 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY, | |
977 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
978 | (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store, | |
979 | floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")]) | |
980 | ||
9db1d521 | 981 | (define_insn "*movdi_64" |
2f7e5a0d | 982 | [(set (match_operand:DI 0 "nonimmediate_operand" |
c5aa1d12 | 983 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 984 | (match_operand:DI 1 "general_operand" |
c5aa1d12 | 985 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
ec24698e | 986 | "TARGET_64BIT && !TARGET_EXTIMM" |
9db1d521 | 987 | "@ |
f19a9af7 AK |
988 | lghi\t%0,%h1 |
989 | llihh\t%0,%i1 | |
990 | llihl\t%0,%i1 | |
991 | llilh\t%0,%i1 | |
992 | llill\t%0,%i1 | |
993 | lay\t%0,%a1 | |
d40c829f UW |
994 | lgr\t%0,%1 |
995 | lg\t%0,%1 | |
996 | stg\t%1,%0 | |
997 | ldr\t%0,%1 | |
998 | ld\t%0,%1 | |
999 | ldy\t%0,%1 | |
1000 | std\t%1,%0 | |
1001 | stdy\t%1,%0 | |
c5aa1d12 UW |
1002 | # |
1003 | # | |
1004 | stam\t%1,%N1,%S0 | |
1005 | lam\t%0,%N0,%S1 | |
19b63d8e | 1006 | #" |
b628bd8e UW |
1007 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, |
1008 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
1009 | (set_attr "type" "*,*,*,*,*,la,lr,load,store, | |
cfdb984b | 1010 | floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")]) |
c5aa1d12 UW |
1011 | |
1012 | (define_split | |
1013 | [(set (match_operand:DI 0 "register_operand" "") | |
1014 | (match_operand:DI 1 "register_operand" ""))] | |
1015 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
1016 | [(set (match_dup 2) (match_dup 3)) | |
1017 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1018 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1019 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1020 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1021 | ||
1022 | (define_split | |
1023 | [(set (match_operand:DI 0 "register_operand" "") | |
1024 | (match_operand:DI 1 "register_operand" ""))] | |
1025 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1026 | && dead_or_set_p (insn, operands[1])" | |
1027 | [(set (match_dup 3) (match_dup 2)) | |
1028 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1029 | (set (match_dup 4) (match_dup 2))] | |
1030 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1031 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1032 | ||
1033 | (define_split | |
1034 | [(set (match_operand:DI 0 "register_operand" "") | |
1035 | (match_operand:DI 1 "register_operand" ""))] | |
1036 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1037 | && !dead_or_set_p (insn, operands[1])" | |
1038 | [(set (match_dup 3) (match_dup 2)) | |
1039 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1040 | (set (match_dup 4) (match_dup 2)) | |
1041 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1042 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1043 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1044 | |
1045 | (define_insn "*movdi_31" | |
c4d50129 | 1046 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q") |
11598938 | 1047 | (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))] |
9db1d521 | 1048 | "!TARGET_64BIT" |
4023fb28 | 1049 | "@ |
fc0ea003 | 1050 | lm\t%0,%N0,%S1 |
c4d50129 | 1051 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1052 | stm\t%1,%N1,%S0 |
c4d50129 | 1053 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1054 | # |
1055 | # | |
d40c829f UW |
1056 | ldr\t%0,%1 |
1057 | ld\t%0,%1 | |
1058 | ldy\t%0,%1 | |
1059 | std\t%1,%0 | |
1060 | stdy\t%1,%0 | |
19b63d8e | 1061 | #" |
c4d50129 AK |
1062 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS") |
1063 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")]) | |
4023fb28 UW |
1064 | |
1065 | (define_split | |
1066 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1067 | (match_operand:DI 1 "general_operand" ""))] | |
1068 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1069 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1070 | [(set (match_dup 2) (match_dup 4)) |
1071 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1072 | { |
dc65c307 UW |
1073 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1074 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1075 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1076 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1077 | }) | |
1078 | ||
1079 | (define_split | |
1080 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1081 | (match_operand:DI 1 "general_operand" ""))] | |
1082 | "!TARGET_64BIT && reload_completed | |
1083 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1084 | [(set (match_dup 2) (match_dup 4)) | |
1085 | (set (match_dup 3) (match_dup 5))] | |
1086 | { | |
1087 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1088 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1089 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1090 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1091 | }) | |
9db1d521 | 1092 | |
4023fb28 UW |
1093 | (define_split |
1094 | [(set (match_operand:DI 0 "register_operand" "") | |
1095 | (match_operand:DI 1 "memory_operand" ""))] | |
1096 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1097 | && !FP_REG_P (operands[0]) |
4023fb28 | 1098 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1099 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1100 | { |
1101 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1102 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1103 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1104 | }) |
1105 | ||
1106 | (define_expand "reload_outdi" | |
9c3c3dcc | 1107 | [(parallel [(match_operand:DI 0 "" "") |
dc65c307 UW |
1108 | (match_operand:DI 1 "register_operand" "d") |
1109 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1110 | "!TARGET_64BIT" | |
1111 | { | |
9c3c3dcc | 1112 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1113 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1114 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1115 | emit_move_insn (operands[0], operands[1]); | |
1116 | DONE; | |
1117 | }) | |
9db1d521 | 1118 | |
84817c5d UW |
1119 | (define_peephole2 |
1120 | [(set (match_operand:DI 0 "register_operand" "") | |
1121 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1122 | "TARGET_64BIT | |
1123 | && !FP_REG_P (operands[0]) | |
1124 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1125 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1126 | && get_pool_mode (operands[1]) == DImode | |
1127 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1128 | [(set (match_dup 0) (match_dup 2))] | |
1129 | "operands[2] = get_pool_constant (operands[1]);") | |
1130 | ||
7bdff56f UW |
1131 | (define_insn "*la_64" |
1132 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1133 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1134 | "TARGET_64BIT" | |
1135 | "@ | |
1136 | la\t%0,%a1 | |
1137 | lay\t%0,%a1" | |
1138 | [(set_attr "op_type" "RX,RXY") | |
1139 | (set_attr "type" "la")]) | |
1140 | ||
1141 | (define_peephole2 | |
1142 | [(parallel | |
1143 | [(set (match_operand:DI 0 "register_operand" "") | |
1144 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1145 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1146 | "TARGET_64BIT |
e1d5ee28 | 1147 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1148 | [(set (match_dup 0) (match_dup 1))] |
1149 | "") | |
1150 | ||
1151 | (define_peephole2 | |
1152 | [(set (match_operand:DI 0 "register_operand" "") | |
1153 | (match_operand:DI 1 "register_operand" "")) | |
1154 | (parallel | |
1155 | [(set (match_dup 0) | |
1156 | (plus:DI (match_dup 0) | |
1157 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1158 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1159 | "TARGET_64BIT |
1160 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1161 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1162 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1163 | "") | |
1164 | ||
1165 | (define_expand "reload_indi" | |
1166 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1167 | (match_operand:DI 1 "s390_plus_operand" "") | |
1168 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1169 | "TARGET_64BIT" | |
1170 | { | |
1171 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1172 | DONE; | |
1173 | }) | |
1174 | ||
9db1d521 HP |
1175 | ; |
1176 | ; movsi instruction pattern(s). | |
1177 | ; | |
1178 | ||
9db1d521 HP |
1179 | (define_expand "movsi" |
1180 | [(set (match_operand:SI 0 "general_operand" "") | |
1181 | (match_operand:SI 1 "general_operand" ""))] | |
1182 | "" | |
9db1d521 | 1183 | { |
fd3cd001 UW |
1184 | /* Handle symbolic constants. */ |
1185 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1186 | emit_symbolic_move (operands); | |
10bbf137 | 1187 | }) |
9db1d521 | 1188 | |
9e8327e3 UW |
1189 | (define_insn "*movsi_larl" |
1190 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1191 | (match_operand:SI 1 "larl_operand" "X"))] | |
1192 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1193 | && !FP_REG_P (operands[0])" | |
1194 | "larl\t%0,%1" | |
1195 | [(set_attr "op_type" "RIL") | |
1196 | (set_attr "type" "larl")]) | |
1197 | ||
f19a9af7 | 1198 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1199 | [(set (match_operand:SI 0 "nonimmediate_operand" |
ec24698e | 1200 | "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 1201 | (match_operand:SI 1 "general_operand" |
ec24698e | 1202 | "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
f19a9af7 | 1203 | "TARGET_ZARCH" |
9db1d521 | 1204 | "@ |
f19a9af7 AK |
1205 | lhi\t%0,%h1 |
1206 | llilh\t%0,%i1 | |
1207 | llill\t%0,%i1 | |
ec24698e | 1208 | iilf\t%0,%o1 |
f19a9af7 | 1209 | lay\t%0,%a1 |
d40c829f UW |
1210 | lr\t%0,%1 |
1211 | l\t%0,%1 | |
1212 | ly\t%0,%1 | |
1213 | st\t%1,%0 | |
1214 | sty\t%1,%0 | |
1215 | ler\t%0,%1 | |
1216 | le\t%0,%1 | |
1217 | ley\t%0,%1 | |
1218 | ste\t%1,%0 | |
1219 | stey\t%1,%0 | |
c5aa1d12 UW |
1220 | ear\t%0,%1 |
1221 | sar\t%0,%1 | |
1222 | stam\t%1,%1,%S0 | |
1223 | lam\t%0,%0,%S1 | |
19b63d8e | 1224 | #" |
ec24698e | 1225 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY, |
b628bd8e | 1226 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") |
ec24698e | 1227 | (set_attr "type" "*,*,*,*,la,lr,load,load,store,store, |
cfdb984b | 1228 | floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")]) |
f19a9af7 AK |
1229 | |
1230 | (define_insn "*movsi_esa" | |
c5aa1d12 UW |
1231 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") |
1232 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))] | |
f19a9af7 AK |
1233 | "!TARGET_ZARCH" |
1234 | "@ | |
1235 | lhi\t%0,%h1 | |
1236 | lr\t%0,%1 | |
1237 | l\t%0,%1 | |
1238 | st\t%1,%0 | |
1239 | ler\t%0,%1 | |
1240 | le\t%0,%1 | |
1241 | ste\t%1,%0 | |
c5aa1d12 UW |
1242 | ear\t%0,%1 |
1243 | sar\t%0,%1 | |
1244 | stam\t%1,%1,%S0 | |
1245 | lam\t%0,%0,%S1 | |
19b63d8e | 1246 | #" |
c5aa1d12 | 1247 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") |
cfdb984b | 1248 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")]) |
9db1d521 | 1249 | |
84817c5d UW |
1250 | (define_peephole2 |
1251 | [(set (match_operand:SI 0 "register_operand" "") | |
1252 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1253 | "!FP_REG_P (operands[0]) | |
1254 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1255 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1256 | && get_pool_mode (operands[1]) == SImode | |
1257 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1258 | [(set (match_dup 0) (match_dup 2))] | |
1259 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1260 | |
7bdff56f UW |
1261 | (define_insn "*la_31" |
1262 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1263 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1264 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1265 | "@ | |
1266 | la\t%0,%a1 | |
1267 | lay\t%0,%a1" | |
1268 | [(set_attr "op_type" "RX,RXY") | |
1269 | (set_attr "type" "la")]) | |
1270 | ||
1271 | (define_peephole2 | |
1272 | [(parallel | |
1273 | [(set (match_operand:SI 0 "register_operand" "") | |
1274 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1275 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1276 | "!TARGET_64BIT |
e1d5ee28 | 1277 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1278 | [(set (match_dup 0) (match_dup 1))] |
1279 | "") | |
1280 | ||
1281 | (define_peephole2 | |
1282 | [(set (match_operand:SI 0 "register_operand" "") | |
1283 | (match_operand:SI 1 "register_operand" "")) | |
1284 | (parallel | |
1285 | [(set (match_dup 0) | |
1286 | (plus:SI (match_dup 0) | |
1287 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1288 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1289 | "!TARGET_64BIT |
1290 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1291 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1292 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1293 | "") | |
1294 | ||
1295 | (define_insn "*la_31_and" | |
1296 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1297 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1298 | (const_int 2147483647)))] | |
1299 | "!TARGET_64BIT" | |
1300 | "@ | |
1301 | la\t%0,%a1 | |
1302 | lay\t%0,%a1" | |
1303 | [(set_attr "op_type" "RX,RXY") | |
1304 | (set_attr "type" "la")]) | |
1305 | ||
1306 | (define_insn_and_split "*la_31_and_cc" | |
1307 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1308 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1309 | (const_int 2147483647))) | |
ae156f85 | 1310 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1311 | "!TARGET_64BIT" |
1312 | "#" | |
1313 | "&& reload_completed" | |
1314 | [(set (match_dup 0) | |
1315 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1316 | "" | |
1317 | [(set_attr "op_type" "RX") | |
1318 | (set_attr "type" "la")]) | |
1319 | ||
1320 | (define_insn "force_la_31" | |
1321 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1322 | (match_operand:QI 1 "address_operand" "U,W")) | |
1323 | (use (const_int 0))] | |
1324 | "!TARGET_64BIT" | |
1325 | "@ | |
1326 | la\t%0,%a1 | |
1327 | lay\t%0,%a1" | |
1328 | [(set_attr "op_type" "RX") | |
1329 | (set_attr "type" "la")]) | |
1330 | ||
1331 | (define_expand "reload_insi" | |
1332 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1333 | (match_operand:SI 1 "s390_plus_operand" "") | |
1334 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1335 | "!TARGET_64BIT" | |
1336 | { | |
1337 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1338 | DONE; | |
1339 | }) | |
1340 | ||
9db1d521 HP |
1341 | ; |
1342 | ; movhi instruction pattern(s). | |
1343 | ; | |
1344 | ||
02ed3c5e UW |
1345 | (define_expand "movhi" |
1346 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1347 | (match_operand:HI 1 "general_operand" ""))] | |
1348 | "" | |
1349 | { | |
2f7e5a0d | 1350 | /* Make it explicit that loading a register from memory |
02ed3c5e UW |
1351 | always sign-extends (at least) to SImode. */ |
1352 | if (optimize && !no_new_pseudos | |
1353 | && register_operand (operands[0], VOIDmode) | |
8fff4fc1 | 1354 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1355 | { |
1356 | rtx tmp = gen_reg_rtx (SImode); | |
1357 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1358 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1359 | operands[1] = gen_lowpart (HImode, tmp); | |
1360 | } | |
1361 | }) | |
1362 | ||
1363 | (define_insn "*movhi" | |
d3632d41 UW |
1364 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1365 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1366 | "" |
1367 | "@ | |
d40c829f UW |
1368 | lr\t%0,%1 |
1369 | lhi\t%0,%h1 | |
1370 | lh\t%0,%1 | |
1371 | lhy\t%0,%1 | |
1372 | sth\t%1,%0 | |
1373 | sthy\t%1,%0 | |
19b63d8e | 1374 | #" |
d3632d41 | 1375 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
b628bd8e | 1376 | (set_attr "type" "lr,*,*,*,store,store,*")]) |
9db1d521 | 1377 | |
84817c5d UW |
1378 | (define_peephole2 |
1379 | [(set (match_operand:HI 0 "register_operand" "") | |
1380 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1381 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1382 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1383 | && get_pool_mode (operands[1]) == HImode | |
1384 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1385 | [(set (match_dup 0) (match_dup 2))] | |
1386 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1387 | |
9db1d521 HP |
1388 | ; |
1389 | ; movqi instruction pattern(s). | |
1390 | ; | |
1391 | ||
02ed3c5e UW |
1392 | (define_expand "movqi" |
1393 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1394 | (match_operand:QI 1 "general_operand" ""))] | |
1395 | "" | |
1396 | { | |
c19ec8f9 | 1397 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1398 | is just as fast as a QImode load. */ |
c19ec8f9 | 1399 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1400 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1401 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1402 | { |
c19ec8f9 UW |
1403 | rtx tmp = gen_reg_rtx (word_mode); |
1404 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1405 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1406 | operands[1] = gen_lowpart (QImode, tmp); | |
1407 | } | |
1408 | }) | |
4023fb28 | 1409 | |
02ed3c5e | 1410 | (define_insn "*movqi" |
d3632d41 UW |
1411 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1412 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1413 | "" |
1414 | "@ | |
d40c829f UW |
1415 | lr\t%0,%1 |
1416 | lhi\t%0,%b1 | |
1417 | ic\t%0,%1 | |
1418 | icy\t%0,%1 | |
1419 | stc\t%1,%0 | |
1420 | stcy\t%1,%0 | |
fc0ea003 UW |
1421 | mvi\t%S0,%b1 |
1422 | mviy\t%S0,%b1 | |
19b63d8e | 1423 | #" |
d3632d41 | 1424 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
b628bd8e | 1425 | (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) |
9db1d521 | 1426 | |
84817c5d UW |
1427 | (define_peephole2 |
1428 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1429 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1430 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1431 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1432 | && get_pool_mode (operands[1]) == QImode | |
1433 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1434 | [(set (match_dup 0) (match_dup 2))] | |
1435 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1436 | |
9db1d521 | 1437 | ; |
05b9aaaa | 1438 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1439 | ; |
1440 | ||
1441 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1442 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1443 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1444 | "" |
d3632d41 | 1445 | "@ |
d40c829f UW |
1446 | ic\t%0,%1 |
1447 | icy\t%0,%1" | |
d3632d41 | 1448 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1449 | |
1450 | ; | |
1451 | ; movstricthi instruction pattern(s). | |
1452 | ; | |
1453 | ||
1454 | (define_insn "*movstricthi" | |
d3632d41 | 1455 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1456 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1457 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1458 | "" |
d3632d41 | 1459 | "@ |
fc0ea003 UW |
1460 | icm\t%0,3,%S1 |
1461 | icmy\t%0,3,%S1" | |
d3632d41 | 1462 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1463 | |
1464 | ; | |
1465 | ; movstrictsi instruction pattern(s). | |
1466 | ; | |
1467 | ||
05b9aaaa | 1468 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1469 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1470 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1471 | "TARGET_64BIT" |
1472 | "@ | |
d40c829f UW |
1473 | lr\t%0,%1 |
1474 | l\t%0,%1 | |
c5aa1d12 UW |
1475 | ly\t%0,%1 |
1476 | ear\t%0,%1" | |
1477 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
1478 | (set_attr "type" "lr,load,load,*")]) | |
9db1d521 HP |
1479 | |
1480 | ; | |
1481 | ; movdf instruction pattern(s). | |
1482 | ; | |
1483 | ||
1484 | (define_expand "movdf" | |
1485 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1486 | (match_operand:DF 1 "general_operand" ""))] | |
1487 | "" | |
13c025c1 | 1488 | "") |
9db1d521 HP |
1489 | |
1490 | (define_insn "*movdf_64" | |
d096725d AS |
1491 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q") |
1492 | (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1493 | "TARGET_64BIT" |
9db1d521 | 1494 | "@ |
d096725d | 1495 | lzdr\t%0 |
d40c829f UW |
1496 | ldr\t%0,%1 |
1497 | ld\t%0,%1 | |
1498 | ldy\t%0,%1 | |
1499 | std\t%1,%0 | |
1500 | stdy\t%1,%0 | |
1501 | lgr\t%0,%1 | |
1502 | lg\t%0,%1 | |
1503 | stg\t%1,%0 | |
19b63d8e | 1504 | #" |
d096725d AS |
1505 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
1506 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")]) | |
9db1d521 HP |
1507 | |
1508 | (define_insn "*movdf_31" | |
c4d50129 | 1509 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q") |
11598938 | 1510 | (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))] |
4023fb28 | 1511 | "!TARGET_64BIT" |
9db1d521 | 1512 | "@ |
d096725d | 1513 | lzdr\t%0 |
d40c829f UW |
1514 | ldr\t%0,%1 |
1515 | ld\t%0,%1 | |
1516 | ldy\t%0,%1 | |
1517 | std\t%1,%0 | |
1518 | stdy\t%1,%0 | |
fc0ea003 | 1519 | lm\t%0,%N0,%S1 |
c4d50129 | 1520 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1521 | stm\t%1,%N1,%S0 |
c4d50129 | 1522 | stmy\t%1,%N1,%S0 |
4023fb28 | 1523 | # |
9b7c75b9 | 1524 | # |
19b63d8e | 1525 | #" |
c4d50129 AK |
1526 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS") |
1527 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\ | |
1528 | lm,lm,stm,stm,*,*,*")]) | |
4023fb28 UW |
1529 | |
1530 | (define_split | |
1531 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1532 | (match_operand:DF 1 "general_operand" ""))] | |
1533 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1534 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1535 | [(set (match_dup 2) (match_dup 4)) |
1536 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1537 | { |
dc65c307 UW |
1538 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1539 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1540 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1541 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1542 | }) | |
1543 | ||
1544 | (define_split | |
1545 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1546 | (match_operand:DF 1 "general_operand" ""))] | |
1547 | "!TARGET_64BIT && reload_completed | |
1548 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1549 | [(set (match_dup 2) (match_dup 4)) | |
1550 | (set (match_dup 3) (match_dup 5))] | |
1551 | { | |
1552 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1553 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1554 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1555 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1556 | }) | |
9db1d521 | 1557 | |
4023fb28 UW |
1558 | (define_split |
1559 | [(set (match_operand:DF 0 "register_operand" "") | |
1560 | (match_operand:DF 1 "memory_operand" ""))] | |
1561 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1562 | && !FP_REG_P (operands[0]) |
4023fb28 | 1563 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1564 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1565 | { |
1566 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1567 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1568 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1569 | }) |
1570 | ||
1571 | (define_expand "reload_outdf" | |
9c3c3dcc | 1572 | [(parallel [(match_operand:DF 0 "" "") |
dc65c307 UW |
1573 | (match_operand:DF 1 "register_operand" "d") |
1574 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1575 | "!TARGET_64BIT" | |
1576 | { | |
9c3c3dcc | 1577 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1578 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1579 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1580 | emit_move_insn (operands[0], operands[1]); | |
1581 | DONE; | |
1582 | }) | |
9db1d521 HP |
1583 | |
1584 | ; | |
1585 | ; movsf instruction pattern(s). | |
1586 | ; | |
1587 | ||
13c025c1 | 1588 | (define_insn "movsf" |
d096725d AS |
1589 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q") |
1590 | (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1591 | "" |
9db1d521 | 1592 | "@ |
d096725d | 1593 | lzer\t%0 |
d40c829f UW |
1594 | ler\t%0,%1 |
1595 | le\t%0,%1 | |
1596 | ley\t%0,%1 | |
1597 | ste\t%1,%0 | |
1598 | stey\t%1,%0 | |
1599 | lr\t%0,%1 | |
1600 | l\t%0,%1 | |
1601 | ly\t%0,%1 | |
1602 | st\t%1,%0 | |
1603 | sty\t%1,%0 | |
19b63d8e | 1604 | #" |
d096725d AS |
1605 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1606 | (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf, | |
b628bd8e | 1607 | lr,load,load,store,store,*")]) |
4023fb28 | 1608 | |
9dc62c00 AK |
1609 | ; |
1610 | ; movcc instruction pattern | |
1611 | ; | |
1612 | ||
1613 | (define_insn "movcc" | |
1614 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
1615 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
1616 | "" | |
1617 | "@ | |
1618 | lr\t%0,%1 | |
1619 | tmh\t%1,12288 | |
1620 | ipm\t%0 | |
1621 | st\t%0,%1 | |
1622 | sty\t%0,%1 | |
1623 | l\t%1,%0 | |
1624 | ly\t%1,%0" | |
8dd3b235 AK |
1625 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
1626 | (set_attr "type" "lr,*,*,store,store,load,load")]) | |
9dc62c00 | 1627 | |
19b63d8e UW |
1628 | ; |
1629 | ; Block move (MVC) patterns. | |
1630 | ; | |
1631 | ||
1632 | (define_insn "*mvc" | |
1633 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
1634 | (match_operand:BLK 1 "memory_operand" "Q")) | |
1635 | (use (match_operand 2 "const_int_operand" "n"))] | |
1636 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1637 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 1638 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1639 | |
1640 | (define_split | |
1641 | [(set (match_operand 0 "memory_operand" "") | |
1642 | (match_operand 1 "memory_operand" ""))] | |
1643 | "reload_completed | |
1644 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1645 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1646 | [(parallel | |
1647 | [(set (match_dup 0) (match_dup 1)) | |
1648 | (use (match_dup 2))])] | |
1649 | { | |
1650 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1651 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1652 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1653 | }) | |
1654 | ||
1655 | (define_peephole2 | |
1656 | [(parallel | |
1657 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1658 | (match_operand:BLK 1 "memory_operand" "")) | |
1659 | (use (match_operand 2 "const_int_operand" ""))]) | |
1660 | (parallel | |
1661 | [(set (match_operand:BLK 3 "memory_operand" "") | |
1662 | (match_operand:BLK 4 "memory_operand" "")) | |
1663 | (use (match_operand 5 "const_int_operand" ""))])] | |
1664 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
1665 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
1666 | && !s390_overlap_p (operands[0], operands[1], |
1667 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
1668 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
1669 | [(parallel | |
1670 | [(set (match_dup 6) (match_dup 7)) | |
1671 | (use (match_dup 8))])] | |
1672 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
1673 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
1674 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
1675 | ||
1676 | ||
9db1d521 HP |
1677 | ; |
1678 | ; load_multiple pattern(s). | |
1679 | ; | |
22ea6b4f UW |
1680 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1681 | ; we currently support load_multiple/store_multiple only after reload. | |
1682 | ; | |
9db1d521 HP |
1683 | |
1684 | (define_expand "load_multiple" | |
1685 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1686 | (match_operand 1 "" "")) | |
1687 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1688 | "reload_completed" |
9db1d521 | 1689 | { |
c19ec8f9 | 1690 | enum machine_mode mode; |
9db1d521 HP |
1691 | int regno; |
1692 | int count; | |
1693 | rtx from; | |
4023fb28 | 1694 | int i, off; |
9db1d521 HP |
1695 | |
1696 | /* Support only loading a constant number of fixed-point registers from | |
1697 | memory and only bother with this if more than two */ | |
1698 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1699 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1700 | || INTVAL (operands[2]) > 16 |
1701 | || GET_CODE (operands[1]) != MEM | |
1702 | || GET_CODE (operands[0]) != REG | |
1703 | || REGNO (operands[0]) >= 16) | |
1704 | FAIL; | |
1705 | ||
1706 | count = INTVAL (operands[2]); | |
1707 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1708 | mode = GET_MODE (operands[0]); |
1709 | if (mode != SImode && mode != word_mode) | |
1710 | FAIL; | |
9db1d521 HP |
1711 | |
1712 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1713 | if (no_new_pseudos) |
1714 | { | |
1715 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1716 | { | |
1717 | from = XEXP (operands[1], 0); | |
1718 | off = 0; | |
1719 | } | |
1720 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1721 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1722 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1723 | { | |
1724 | from = XEXP (XEXP (operands[1], 0), 0); | |
1725 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1726 | } | |
1727 | else | |
1728 | FAIL; | |
4023fb28 UW |
1729 | } |
1730 | else | |
1731 | { | |
1732 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1733 | off = 0; | |
1734 | } | |
9db1d521 HP |
1735 | |
1736 | for (i = 0; i < count; i++) | |
1737 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1738 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1739 | change_address (operands[1], mode, | |
1740 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1741 | }) |
9db1d521 HP |
1742 | |
1743 | (define_insn "*load_multiple_di" | |
1744 | [(match_parallel 0 "load_multiple_operation" | |
1745 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1746 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1747 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1748 | { |
1749 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1750 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1751 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 1752 | } |
d3632d41 | 1753 | [(set_attr "op_type" "RSY") |
4023fb28 | 1754 | (set_attr "type" "lm")]) |
9db1d521 HP |
1755 | |
1756 | (define_insn "*load_multiple_si" | |
1757 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1758 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1759 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1760 | "reload_completed" |
9db1d521 HP |
1761 | { |
1762 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1763 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1764 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 1765 | } |
d3632d41 | 1766 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1767 | (set_attr "type" "lm")]) |
9db1d521 HP |
1768 | |
1769 | ; | |
c7453384 | 1770 | ; store multiple pattern(s). |
9db1d521 HP |
1771 | ; |
1772 | ||
1773 | (define_expand "store_multiple" | |
1774 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1775 | (match_operand 1 "" "")) | |
1776 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1777 | "reload_completed" |
9db1d521 | 1778 | { |
c19ec8f9 | 1779 | enum machine_mode mode; |
9db1d521 HP |
1780 | int regno; |
1781 | int count; | |
1782 | rtx to; | |
4023fb28 | 1783 | int i, off; |
9db1d521 HP |
1784 | |
1785 | /* Support only storing a constant number of fixed-point registers to | |
1786 | memory and only bother with this if more than two. */ | |
1787 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1788 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1789 | || INTVAL (operands[2]) > 16 |
1790 | || GET_CODE (operands[0]) != MEM | |
1791 | || GET_CODE (operands[1]) != REG | |
1792 | || REGNO (operands[1]) >= 16) | |
1793 | FAIL; | |
1794 | ||
1795 | count = INTVAL (operands[2]); | |
1796 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1797 | mode = GET_MODE (operands[1]); |
1798 | if (mode != SImode && mode != word_mode) | |
1799 | FAIL; | |
9db1d521 HP |
1800 | |
1801 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1802 | |
1803 | if (no_new_pseudos) | |
1804 | { | |
1805 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1806 | { | |
1807 | to = XEXP (operands[0], 0); | |
1808 | off = 0; | |
1809 | } | |
1810 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1811 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1812 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1813 | { | |
1814 | to = XEXP (XEXP (operands[0], 0), 0); | |
1815 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1816 | } | |
1817 | else | |
1818 | FAIL; | |
4023fb28 | 1819 | } |
c7453384 | 1820 | else |
4023fb28 UW |
1821 | { |
1822 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1823 | off = 0; | |
1824 | } | |
9db1d521 HP |
1825 | |
1826 | for (i = 0; i < count; i++) | |
1827 | XVECEXP (operands[3], 0, i) | |
1828 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1829 | change_address (operands[0], mode, |
1830 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1831 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1832 | }) |
9db1d521 HP |
1833 | |
1834 | (define_insn "*store_multiple_di" | |
1835 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1836 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1837 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1838 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1839 | { |
1840 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1841 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1842 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 1843 | } |
d3632d41 | 1844 | [(set_attr "op_type" "RSY") |
4023fb28 | 1845 | (set_attr "type" "stm")]) |
9db1d521 HP |
1846 | |
1847 | ||
1848 | (define_insn "*store_multiple_si" | |
1849 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1850 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1851 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1852 | "reload_completed" |
9db1d521 HP |
1853 | { |
1854 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1855 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1856 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 1857 | } |
d3632d41 | 1858 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1859 | (set_attr "type" "stm")]) |
9db1d521 HP |
1860 | |
1861 | ;; | |
1862 | ;; String instructions. | |
1863 | ;; | |
1864 | ||
9bb86f41 UW |
1865 | (define_insn "*execute" |
1866 | [(match_parallel 0 "" | |
1867 | [(unspec [(match_operand 1 "register_operand" "a") | |
1868 | (match_operand:BLK 2 "memory_operand" "R") | |
1869 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
1870 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
1871 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
1872 | "ex\t%1,%2" | |
29a74354 UW |
1873 | [(set_attr "op_type" "RX") |
1874 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
1875 | |
1876 | ||
91d39d71 UW |
1877 | ; |
1878 | ; strlenM instruction pattern(s). | |
1879 | ; | |
1880 | ||
9db2f16d | 1881 | (define_expand "strlen<mode>" |
ccbdc0d4 | 1882 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 1883 | (parallel |
91d39d71 | 1884 | [(set (match_dup 4) |
9db2f16d | 1885 | (unspec:P [(const_int 0) |
91d39d71 | 1886 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 1887 | (reg:SI 0) |
91d39d71 | 1888 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 1889 | (clobber (scratch:P)) |
ae156f85 | 1890 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 1891 | (parallel |
9db2f16d AS |
1892 | [(set (match_operand:P 0 "register_operand" "") |
1893 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 1894 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 1895 | "" |
91d39d71 | 1896 | { |
9db2f16d AS |
1897 | operands[4] = gen_reg_rtx (Pmode); |
1898 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
1899 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
1900 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1901 | }) | |
1902 | ||
9db2f16d AS |
1903 | (define_insn "*strlen<mode>" |
1904 | [(set (match_operand:P 0 "register_operand" "=a") | |
1905 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
1906 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 1907 | (reg:SI 0) |
91d39d71 | 1908 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 1909 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 1910 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 1911 | "" |
91d39d71 | 1912 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
1913 | [(set_attr "length" "8") |
1914 | (set_attr "type" "vs")]) | |
91d39d71 | 1915 | |
ccbdc0d4 AS |
1916 | ; |
1917 | ; cmpstrM instruction pattern(s). | |
1918 | ; | |
1919 | ||
1920 | (define_expand "cmpstrsi" | |
1921 | [(set (reg:SI 0) (const_int 0)) | |
1922 | (parallel | |
1923 | [(clobber (match_operand 3 "" "")) | |
1924 | (clobber (match_dup 4)) | |
1925 | (set (reg:CCU CC_REGNUM) | |
1926 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
1927 | (match_operand:BLK 2 "memory_operand" ""))) | |
1928 | (use (reg:SI 0))]) | |
1929 | (parallel | |
1930 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1931 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT)) | |
1932 | (clobber (reg:CC CC_REGNUM))])] | |
1933 | "" | |
1934 | { | |
1935 | /* As the result of CMPINT is inverted compared to what we need, | |
1936 | we have to swap the operands. */ | |
1937 | rtx op1 = operands[2]; | |
1938 | rtx op2 = operands[1]; | |
1939 | rtx addr1 = gen_reg_rtx (Pmode); | |
1940 | rtx addr2 = gen_reg_rtx (Pmode); | |
1941 | ||
1942 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
1943 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
1944 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
1945 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
1946 | operands[3] = addr1; | |
1947 | operands[4] = addr2; | |
1948 | }) | |
1949 | ||
1950 | (define_insn "*cmpstr<mode>" | |
1951 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
1952 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
1953 | (set (reg:CCU CC_REGNUM) | |
1954 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
1955 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
1956 | (use (reg:SI 0))] | |
1957 | "" | |
1958 | "clst\t%0,%1\;jo\t.-4" | |
1959 | [(set_attr "length" "8") | |
1960 | (set_attr "type" "vs")]) | |
1961 | ||
742090fc AS |
1962 | ; |
1963 | ; movstr instruction pattern. | |
1964 | ; | |
1965 | ||
1966 | (define_expand "movstr" | |
1967 | [(set (reg:SI 0) (const_int 0)) | |
1968 | (parallel | |
1969 | [(clobber (match_dup 3)) | |
1970 | (set (match_operand:BLK 1 "memory_operand" "") | |
1971 | (match_operand:BLK 2 "memory_operand" "")) | |
1972 | (set (match_operand 0 "register_operand" "") | |
1973 | (unspec [(match_dup 1) | |
1974 | (match_dup 2) | |
1975 | (reg:SI 0)] UNSPEC_MVST)) | |
1976 | (clobber (reg:CC CC_REGNUM))])] | |
1977 | "" | |
1978 | { | |
1979 | rtx addr1 = gen_reg_rtx (Pmode); | |
1980 | rtx addr2 = gen_reg_rtx (Pmode); | |
1981 | ||
1982 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1983 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
1984 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
1985 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
1986 | operands[3] = addr2; | |
1987 | }) | |
1988 | ||
1989 | (define_insn "*movstr" | |
1990 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
1991 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
1992 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
1993 | (set (match_operand:P 0 "register_operand" "=d") | |
1994 | (unspec [(mem:BLK (match_dup 1)) | |
1995 | (mem:BLK (match_dup 3)) | |
1996 | (reg:SI 0)] UNSPEC_MVST)) | |
1997 | (clobber (reg:CC CC_REGNUM))] | |
1998 | "" | |
1999 | "mvst\t%1,%2\;jo\t.-4" | |
2000 | [(set_attr "length" "8") | |
2001 | (set_attr "type" "vs")]) | |
2002 | ||
2003 | ||
9db1d521 | 2004 | ; |
70128ad9 | 2005 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2006 | ; |
2007 | ||
9db2f16d | 2008 | (define_expand "movmem<mode>" |
a41c6c53 UW |
2009 | [(set (match_operand:BLK 0 "memory_operand" "") |
2010 | (match_operand:BLK 1 "memory_operand" "")) | |
9db2f16d | 2011 | (use (match_operand:GPR 2 "general_operand" "")) |
a41c6c53 UW |
2012 | (match_operand 3 "" "")] |
2013 | "" | |
70128ad9 | 2014 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2015 | |
ecbe845e UW |
2016 | ; Move a block that is up to 256 bytes in length. |
2017 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2018 | |
70128ad9 | 2019 | (define_expand "movmem_short" |
b9404c99 UW |
2020 | [(parallel |
2021 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2022 | (match_operand:BLK 1 "memory_operand" "")) | |
2023 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2024 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2025 | (clobber (match_dup 3))])] |
2026 | "" | |
2027 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2028 | |
70128ad9 | 2029 | (define_insn "*movmem_short" |
9bb86f41 UW |
2030 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
2031 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) | |
2032 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2033 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2034 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2035 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2036 | && GET_MODE (operands[4]) == Pmode" |
2037 | "#" | |
b628bd8e | 2038 | [(set_attr "type" "cs")]) |
ecbe845e | 2039 | |
9bb86f41 UW |
2040 | (define_split |
2041 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2042 | (match_operand:BLK 1 "memory_operand" "")) | |
2043 | (use (match_operand 2 "const_int_operand" "")) | |
2044 | (use (match_operand 3 "immediate_operand" "")) | |
2045 | (clobber (scratch))] | |
2046 | "reload_completed" | |
2047 | [(parallel | |
2048 | [(set (match_dup 0) (match_dup 1)) | |
2049 | (use (match_dup 2))])] | |
2050 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2051 | |
9bb86f41 UW |
2052 | (define_split |
2053 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2054 | (match_operand:BLK 1 "memory_operand" "")) | |
2055 | (use (match_operand 2 "register_operand" "")) | |
2056 | (use (match_operand 3 "memory_operand" "")) | |
2057 | (clobber (scratch))] | |
2058 | "reload_completed" | |
2059 | [(parallel | |
2060 | [(unspec [(match_dup 2) (match_dup 3) | |
2061 | (const_int 0)] UNSPEC_EXECUTE) | |
2062 | (set (match_dup 0) (match_dup 1)) | |
2063 | (use (const_int 1))])] | |
2064 | "") | |
2065 | ||
2066 | (define_split | |
2067 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2068 | (match_operand:BLK 1 "memory_operand" "")) | |
2069 | (use (match_operand 2 "register_operand" "")) | |
2070 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2071 | (clobber (match_operand 3 "register_operand" ""))] | |
2072 | "reload_completed && TARGET_CPU_ZARCH" | |
2073 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2074 | (parallel | |
2075 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2076 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2077 | (set (match_dup 0) (match_dup 1)) | |
2078 | (use (const_int 1))])] | |
2079 | "operands[4] = gen_label_rtx ();") | |
2080 | ||
a41c6c53 | 2081 | ; Move a block of arbitrary length. |
9db1d521 | 2082 | |
70128ad9 | 2083 | (define_expand "movmem_long" |
b9404c99 UW |
2084 | [(parallel |
2085 | [(clobber (match_dup 2)) | |
2086 | (clobber (match_dup 3)) | |
2087 | (set (match_operand:BLK 0 "memory_operand" "") | |
2088 | (match_operand:BLK 1 "memory_operand" "")) | |
2089 | (use (match_operand 2 "general_operand" "")) | |
2090 | (use (match_dup 3)) | |
ae156f85 | 2091 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2092 | "" |
2093 | { | |
2094 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2095 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2096 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2097 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2098 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2099 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2100 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2101 | ||
2102 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2103 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2104 | emit_move_insn (len0, operands[2]); | |
2105 | ||
2106 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2107 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2108 | emit_move_insn (len1, operands[2]); | |
2109 | ||
2110 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2111 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2112 | operands[2] = reg0; | |
2113 | operands[3] = reg1; | |
2114 | }) | |
2115 | ||
a1aed706 AS |
2116 | (define_insn "*movmem_long" |
2117 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2118 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2119 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2120 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2121 | (use (match_dup 2)) |
2122 | (use (match_dup 3)) | |
ae156f85 | 2123 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2124 | "" |
d40c829f | 2125 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2126 | [(set_attr "length" "8") |
2127 | (set_attr "type" "vs")]) | |
9db1d521 HP |
2128 | |
2129 | ; | |
57e84f18 | 2130 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2131 | ; |
2132 | ||
57e84f18 | 2133 | (define_expand "setmem<mode>" |
a41c6c53 | 2134 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2135 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2136 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2137 | (match_operand 3 "" "")] |
a41c6c53 | 2138 | "" |
6d057022 | 2139 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2140 | |
a41c6c53 | 2141 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2142 | ; The block length is taken as (operands[1] % 256) + 1. |
2143 | ||
70128ad9 | 2144 | (define_expand "clrmem_short" |
b9404c99 UW |
2145 | [(parallel |
2146 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2147 | (const_int 0)) | |
2148 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2149 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2150 | (clobber (match_dup 2)) |
ae156f85 | 2151 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2152 | "" |
2153 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2154 | |
70128ad9 | 2155 | (define_insn "*clrmem_short" |
9bb86f41 | 2156 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
a41c6c53 | 2157 | (const_int 0)) |
9bb86f41 UW |
2158 | (use (match_operand 1 "nonmemory_operand" "n,a,a")) |
2159 | (use (match_operand 2 "immediate_operand" "X,R,X")) | |
2160 | (clobber (match_scratch 3 "=X,X,&a")) | |
ae156f85 | 2161 | (clobber (reg:CC CC_REGNUM))] |
b9404c99 | 2162 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
2163 | && GET_MODE (operands[3]) == Pmode" |
2164 | "#" | |
b628bd8e | 2165 | [(set_attr "type" "cs")]) |
9bb86f41 UW |
2166 | |
2167 | (define_split | |
2168 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2169 | (const_int 0)) | |
2170 | (use (match_operand 1 "const_int_operand" "")) | |
2171 | (use (match_operand 2 "immediate_operand" "")) | |
2172 | (clobber (scratch)) | |
ae156f85 | 2173 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2174 | "reload_completed" |
2175 | [(parallel | |
2176 | [(set (match_dup 0) (const_int 0)) | |
2177 | (use (match_dup 1)) | |
ae156f85 | 2178 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2179 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2180 | |
9bb86f41 UW |
2181 | (define_split |
2182 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2183 | (const_int 0)) | |
2184 | (use (match_operand 1 "register_operand" "")) | |
2185 | (use (match_operand 2 "memory_operand" "")) | |
2186 | (clobber (scratch)) | |
ae156f85 | 2187 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2188 | "reload_completed" |
2189 | [(parallel | |
2190 | [(unspec [(match_dup 1) (match_dup 2) | |
2191 | (const_int 0)] UNSPEC_EXECUTE) | |
2192 | (set (match_dup 0) (const_int 0)) | |
2193 | (use (const_int 1)) | |
ae156f85 | 2194 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2195 | "") |
9db1d521 | 2196 | |
9bb86f41 UW |
2197 | (define_split |
2198 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2199 | (const_int 0)) | |
2200 | (use (match_operand 1 "register_operand" "")) | |
2201 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2202 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2203 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2204 | "reload_completed && TARGET_CPU_ZARCH" |
2205 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2206 | (parallel | |
2207 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
2208 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2209 | (set (match_dup 0) (const_int 0)) | |
2210 | (use (const_int 1)) | |
ae156f85 | 2211 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2212 | "operands[3] = gen_label_rtx ();") |
2213 | ||
6d057022 | 2214 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2215 | |
6d057022 | 2216 | (define_expand "setmem_long" |
b9404c99 UW |
2217 | [(parallel |
2218 | [(clobber (match_dup 1)) | |
2219 | (set (match_operand:BLK 0 "memory_operand" "") | |
f83a336d | 2220 | (match_operand 2 "setmem_operand" "")) |
b9404c99 | 2221 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2222 | (use (match_dup 3)) |
ae156f85 | 2223 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2224 | "" |
a41c6c53 | 2225 | { |
b9404c99 UW |
2226 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2227 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2228 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2229 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2230 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2231 | |
b9404c99 UW |
2232 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2233 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2234 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2235 | |
b9404c99 | 2236 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2237 | |
b9404c99 UW |
2238 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2239 | operands[1] = reg0; | |
6d057022 | 2240 | operands[3] = reg1; |
b9404c99 | 2241 | }) |
a41c6c53 | 2242 | |
6d057022 | 2243 | (define_insn "*setmem_long" |
a1aed706 | 2244 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 2245 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
f83a336d | 2246 | (match_operand 2 "setmem_operand" "Y")) |
6d057022 | 2247 | (use (match_dup 3)) |
a1aed706 | 2248 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2249 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2250 | "" |
6d057022 | 2251 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
2252 | [(set_attr "length" "8") |
2253 | (set_attr "type" "vs")]) | |
9db1d521 HP |
2254 | |
2255 | ; | |
358b8f01 | 2256 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2257 | ; |
2258 | ||
358b8f01 | 2259 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2260 | [(set (match_operand:SI 0 "register_operand" "") |
2261 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2262 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2263 | (use (match_operand:SI 3 "general_operand" "")) | |
2264 | (use (match_operand:SI 4 "" ""))] | |
2265 | "" | |
c7453384 | 2266 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2267 | operands[2], operands[3]); DONE;") |
9db1d521 | 2268 | |
a41c6c53 UW |
2269 | ; Compare a block that is up to 256 bytes in length. |
2270 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2271 | |
b9404c99 UW |
2272 | (define_expand "cmpmem_short" |
2273 | [(parallel | |
ae156f85 | 2274 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 2275 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2276 | (match_operand:BLK 1 "memory_operand" ""))) |
2277 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2278 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2279 | (clobber (match_dup 3))])] |
2280 | "" | |
2281 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2282 | |
b9404c99 | 2283 | (define_insn "*cmpmem_short" |
ae156f85 | 2284 | [(set (reg:CCU CC_REGNUM) |
d4f52f0e | 2285 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") |
9bb86f41 UW |
2286 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) |
2287 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2288 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2289 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2290 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2291 | && GET_MODE (operands[4]) == Pmode" |
2292 | "#" | |
b628bd8e | 2293 | [(set_attr "type" "cs")]) |
9db1d521 | 2294 | |
9bb86f41 | 2295 | (define_split |
ae156f85 | 2296 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2297 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2298 | (match_operand:BLK 1 "memory_operand" ""))) | |
2299 | (use (match_operand 2 "const_int_operand" "")) | |
2300 | (use (match_operand 3 "immediate_operand" "")) | |
2301 | (clobber (scratch))] | |
2302 | "reload_completed" | |
2303 | [(parallel | |
ae156f85 | 2304 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2305 | (use (match_dup 2))])] |
2306 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2307 | |
9bb86f41 | 2308 | (define_split |
ae156f85 | 2309 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2310 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2311 | (match_operand:BLK 1 "memory_operand" ""))) | |
2312 | (use (match_operand 2 "register_operand" "")) | |
2313 | (use (match_operand 3 "memory_operand" "")) | |
2314 | (clobber (scratch))] | |
2315 | "reload_completed" | |
2316 | [(parallel | |
2317 | [(unspec [(match_dup 2) (match_dup 3) | |
2318 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 2319 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2320 | (use (const_int 1))])] |
2321 | "") | |
2322 | ||
2323 | (define_split | |
ae156f85 | 2324 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2325 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2326 | (match_operand:BLK 1 "memory_operand" ""))) | |
2327 | (use (match_operand 2 "register_operand" "")) | |
2328 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2329 | (clobber (match_operand 3 "register_operand" ""))] | |
2330 | "reload_completed && TARGET_CPU_ZARCH" | |
2331 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2332 | (parallel | |
2333 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2334 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
ae156f85 | 2335 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2336 | (use (const_int 1))])] |
2337 | "operands[4] = gen_label_rtx ();") | |
2338 | ||
a41c6c53 | 2339 | ; Compare a block of arbitrary length. |
9db1d521 | 2340 | |
b9404c99 UW |
2341 | (define_expand "cmpmem_long" |
2342 | [(parallel | |
2343 | [(clobber (match_dup 2)) | |
2344 | (clobber (match_dup 3)) | |
ae156f85 | 2345 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 2346 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2347 | (match_operand:BLK 1 "memory_operand" ""))) |
2348 | (use (match_operand 2 "general_operand" "")) | |
2349 | (use (match_dup 3))])] | |
2350 | "" | |
2351 | { | |
2352 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2353 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2354 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2355 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2356 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2357 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2358 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2359 | ||
2360 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2361 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2362 | emit_move_insn (len0, operands[2]); | |
2363 | ||
2364 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2365 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2366 | emit_move_insn (len1, operands[2]); | |
2367 | ||
2368 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2369 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2370 | operands[2] = reg0; | |
2371 | operands[3] = reg1; | |
2372 | }) | |
2373 | ||
a1aed706 AS |
2374 | (define_insn "*cmpmem_long" |
2375 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2376 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 2377 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
2378 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
2379 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
2380 | (use (match_dup 2)) |
2381 | (use (match_dup 3))] | |
a1aed706 | 2382 | "" |
287ff198 | 2383 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2384 | [(set_attr "length" "8") |
2385 | (set_attr "type" "vs")]) | |
9db1d521 | 2386 | |
02887425 UW |
2387 | ; Convert CCUmode condition code to integer. |
2388 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 2389 | |
02887425 | 2390 | (define_insn_and_split "cmpint" |
9db1d521 | 2391 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 UW |
2392 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2393 | UNSPEC_CMPINT)) | |
ae156f85 | 2394 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2395 | "" |
02887425 UW |
2396 | "#" |
2397 | "reload_completed" | |
2398 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2399 | (parallel | |
2400 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 2401 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
2402 | |
2403 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 2404 | [(set (reg CC_REGNUM) |
02887425 UW |
2405 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2406 | UNSPEC_CMPINT) | |
2407 | (const_int 0))) | |
2408 | (set (match_operand:SI 0 "register_operand" "=d") | |
2409 | (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))] | |
2410 | "s390_match_ccmode (insn, CCSmode)" | |
2411 | "#" | |
2412 | "&& reload_completed" | |
2413 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2414 | (parallel | |
2415 | [(set (match_dup 2) (match_dup 3)) | |
2416 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 2417 | { |
02887425 UW |
2418 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
2419 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2420 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2421 | }) | |
9db1d521 | 2422 | |
02887425 | 2423 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 2424 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 UW |
2425 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2426 | UNSPEC_CMPINT))) | |
ae156f85 | 2427 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2428 | "TARGET_64BIT" |
02887425 UW |
2429 | "#" |
2430 | "&& reload_completed" | |
2431 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2432 | (parallel | |
2433 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 2434 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
2435 | |
2436 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 2437 | [(set (reg CC_REGNUM) |
02887425 UW |
2438 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
2439 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2440 | UNSPEC_CMPINT) 0) | |
2441 | (const_int 32)) (const_int 32)) | |
2442 | (const_int 0))) | |
2443 | (set (match_operand:DI 0 "register_operand" "=d") | |
2444 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))] | |
2445 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" | |
2446 | "#" | |
2447 | "&& reload_completed" | |
2448 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2449 | (parallel | |
2450 | [(set (match_dup 2) (match_dup 3)) | |
2451 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 2452 | { |
02887425 UW |
2453 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
2454 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2455 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2456 | }) | |
9db1d521 | 2457 | |
4023fb28 | 2458 | |
9db1d521 HP |
2459 | ;; |
2460 | ;;- Conversion instructions. | |
2461 | ;; | |
2462 | ||
6fa05db6 | 2463 | (define_insn "*sethighpartsi" |
d3632d41 | 2464 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
2465 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
2466 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 2467 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2468 | "" |
d3632d41 | 2469 | "@ |
6fa05db6 AS |
2470 | icm\t%0,%2,%S1 |
2471 | icmy\t%0,%2,%S1" | |
d3632d41 | 2472 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2473 | |
6fa05db6 | 2474 | (define_insn "*sethighpartdi_64" |
4023fb28 | 2475 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
2476 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
2477 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 2478 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2479 | "TARGET_64BIT" |
6fa05db6 | 2480 | "icmh\t%0,%2,%S1" |
d3632d41 | 2481 | [(set_attr "op_type" "RSY")]) |
4023fb28 | 2482 | |
6fa05db6 | 2483 | (define_insn "*sethighpartdi_31" |
d3632d41 | 2484 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
2485 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
2486 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 2487 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2488 | "!TARGET_64BIT" |
d3632d41 | 2489 | "@ |
6fa05db6 AS |
2490 | icm\t%0,%2,%S1 |
2491 | icmy\t%0,%2,%S1" | |
d3632d41 | 2492 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2493 | |
6fa05db6 AS |
2494 | (define_insn_and_split "*extzv<mode>" |
2495 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2496 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
2497 | (match_operand 2 "const_int_operand" "n") | |
2498 | (const_int 0))) | |
ae156f85 | 2499 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
2500 | "INTVAL (operands[2]) > 0 |
2501 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
2502 | "#" |
2503 | "&& reload_completed" | |
4023fb28 | 2504 | [(parallel |
6fa05db6 | 2505 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 2506 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 2507 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 2508 | { |
6fa05db6 AS |
2509 | int bitsize = INTVAL (operands[2]); |
2510 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
2511 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
2512 | ||
2513 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2514 | set_mem_size (operands[1], GEN_INT (size)); | |
2515 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
2516 | operands[3] = GEN_INT (mask); | |
b628bd8e | 2517 | }) |
4023fb28 | 2518 | |
6fa05db6 AS |
2519 | (define_insn_and_split "*extv<mode>" |
2520 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2521 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
2522 | (match_operand 2 "const_int_operand" "n") | |
2523 | (const_int 0))) | |
ae156f85 | 2524 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
2525 | "INTVAL (operands[2]) > 0 |
2526 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
2527 | "#" |
2528 | "&& reload_completed" | |
4023fb28 | 2529 | [(parallel |
6fa05db6 | 2530 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 2531 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
2532 | (parallel |
2533 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
2534 | (clobber (reg:CC CC_REGNUM))])] | |
2535 | { | |
2536 | int bitsize = INTVAL (operands[2]); | |
2537 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
2538 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
2539 | ||
2540 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2541 | set_mem_size (operands[1], GEN_INT (size)); | |
2542 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
2543 | operands[3] = GEN_INT (mask); | |
2544 | }) | |
2545 | ||
2546 | ; | |
2547 | ; insv instruction patterns | |
2548 | ; | |
2549 | ||
2550 | (define_expand "insv" | |
2551 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
2552 | (match_operand 1 "const_int_operand" "") | |
2553 | (match_operand 2 "const_int_operand" "")) | |
2554 | (match_operand 3 "general_operand" ""))] | |
2555 | "" | |
4023fb28 | 2556 | { |
6fa05db6 AS |
2557 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
2558 | DONE; | |
2559 | FAIL; | |
b628bd8e | 2560 | }) |
4023fb28 | 2561 | |
6fa05db6 AS |
2562 | (define_insn "*insv<mode>_mem_reg" |
2563 | [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") | |
2564 | (match_operand 1 "const_int_operand" "n,n") | |
2565 | (const_int 0)) | |
2566 | (match_operand:P 2 "register_operand" "d,d"))] | |
2567 | "INTVAL (operands[1]) > 0 | |
2568 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
2569 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
2570 | { | |
2571 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
2572 | ||
2573 | operands[1] = GEN_INT ((1ul << size) - 1); | |
2574 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" | |
2575 | : "stcmy\t%2,%1,%S0"; | |
2576 | } | |
2577 | [(set_attr "op_type" "RS,RSY")]) | |
2578 | ||
2579 | (define_insn "*insvdi_mem_reghigh" | |
2580 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
2581 | (match_operand 1 "const_int_operand" "n") | |
2582 | (const_int 0)) | |
2583 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
2584 | (const_int 32)))] | |
2585 | "TARGET_64BIT | |
2586 | && INTVAL (operands[1]) > 0 | |
2587 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
2588 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
2589 | { | |
2590 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
2591 | ||
2592 | operands[1] = GEN_INT ((1ul << size) - 1); | |
2593 | return "stcmh\t%2,%1,%S0"; | |
2594 | } | |
2595 | [(set_attr "op_type" "RSY")]) | |
2596 | ||
2597 | (define_insn "*insv<mode>_reg_imm" | |
2598 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
2599 | (const_int 16) | |
2600 | (match_operand 1 "const_int_operand" "n")) | |
ac746a73 | 2601 | (match_operand 2 "const_int_operand" "n"))] |
6fa05db6 AS |
2602 | "TARGET_ZARCH |
2603 | && INTVAL (operands[1]) >= 0 | |
2604 | && INTVAL (operands[1]) < BITS_PER_WORD | |
2605 | && INTVAL (operands[1]) % 16 == 0" | |
2606 | { | |
2607 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
2608 | { | |
2609 | case 64: return "iihh\t%0,%x2"; break; | |
2610 | case 48: return "iihl\t%0,%x2"; break; | |
2611 | case 32: return "iilh\t%0,%x2"; break; | |
2612 | case 16: return "iill\t%0,%x2"; break; | |
2613 | default: gcc_unreachable(); | |
2614 | } | |
2615 | } | |
2616 | [(set_attr "op_type" "RI")]) | |
2617 | ||
2618 | (define_insn "*insv<mode>_reg_extimm" | |
2619 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
2620 | (const_int 32) | |
2621 | (match_operand 1 "const_int_operand" "n")) | |
ac746a73 | 2622 | (match_operand 2 "const_int_operand" "n"))] |
6fa05db6 AS |
2623 | "TARGET_EXTIMM |
2624 | && INTVAL (operands[1]) >= 0 | |
2625 | && INTVAL (operands[1]) < BITS_PER_WORD | |
2626 | && INTVAL (operands[1]) % 32 == 0" | |
2627 | { | |
2628 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
2629 | { | |
2630 | case 64: return "iihf\t%0,%o2"; break; | |
2631 | case 32: return "iilf\t%0,%o2"; break; | |
2632 | default: gcc_unreachable(); | |
2633 | } | |
2634 | } | |
2635 | [(set_attr "op_type" "RIL")]) | |
2636 | ||
9db1d521 HP |
2637 | ; |
2638 | ; extendsidi2 instruction pattern(s). | |
2639 | ; | |
2640 | ||
4023fb28 UW |
2641 | (define_expand "extendsidi2" |
2642 | [(set (match_operand:DI 0 "register_operand" "") | |
2643 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2644 | "" | |
4023fb28 UW |
2645 | { |
2646 | if (!TARGET_64BIT) | |
2647 | { | |
9f37ccb1 UW |
2648 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2649 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2650 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2651 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2652 | DONE; |
2653 | } | |
ec24698e | 2654 | }) |
4023fb28 UW |
2655 | |
2656 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2657 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2658 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2659 | "TARGET_64BIT" | |
2660 | "@ | |
d40c829f UW |
2661 | lgfr\t%0,%1 |
2662 | lgf\t%0,%1" | |
d3632d41 | 2663 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2664 | |
9db1d521 | 2665 | ; |
f6ee577c | 2666 | ; extend(hi|qi)di2 instruction pattern(s). |
9db1d521 HP |
2667 | ; |
2668 | ||
f6ee577c | 2669 | (define_expand "extend<mode>di2" |
4023fb28 | 2670 | [(set (match_operand:DI 0 "register_operand" "") |
ec24698e | 2671 | (sign_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
4023fb28 | 2672 | "" |
4023fb28 UW |
2673 | { |
2674 | if (!TARGET_64BIT) | |
2675 | { | |
2676 | rtx tmp = gen_reg_rtx (SImode); | |
f6ee577c | 2677 | emit_insn (gen_extend<mode>si2 (tmp, operands[1])); |
4023fb28 UW |
2678 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
2679 | DONE; | |
2680 | } | |
ec24698e | 2681 | else if (!TARGET_EXTIMM) |
4023fb28 | 2682 | { |
f6ee577c AS |
2683 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) - |
2684 | GET_MODE_BITSIZE (<MODE>mode)); | |
4023fb28 | 2685 | operands[1] = gen_lowpart (DImode, operands[1]); |
f6ee577c AS |
2686 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); |
2687 | emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2688 | DONE; |
2689 | } | |
ec24698e UW |
2690 | }) |
2691 | ||
2692 | (define_insn "*extendhidi2_extimm" | |
2693 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2694 | (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] | |
2695 | "TARGET_64BIT && TARGET_EXTIMM" | |
2696 | "@ | |
2697 | lghr\t%0,%1 | |
2698 | lgh\t%0,%1" | |
2699 | [(set_attr "op_type" "RRE,RXY")]) | |
4023fb28 UW |
2700 | |
2701 | (define_insn "*extendhidi2" | |
9db1d521 | 2702 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2703 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2704 | "TARGET_64BIT" |
d40c829f | 2705 | "lgh\t%0,%1" |
d3632d41 | 2706 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2707 | |
ec24698e UW |
2708 | (define_insn "*extendqidi2_extimm" |
2709 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2710 | (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] | |
2711 | "TARGET_64BIT && TARGET_EXTIMM" | |
2712 | "@ | |
2713 | lgbr\t%0,%1 | |
2714 | lgb\t%0,%1" | |
2715 | [(set_attr "op_type" "RRE,RXY")]) | |
2716 | ||
d3632d41 UW |
2717 | (define_insn "*extendqidi2" |
2718 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2719 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2720 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2721 | "lgb\t%0,%1" |
d3632d41 UW |
2722 | [(set_attr "op_type" "RXY")]) |
2723 | ||
19796784 AK |
2724 | (define_insn_and_split "*extendqidi2_short_displ" |
2725 | [(set (match_operand:DI 0 "register_operand" "=d") | |
59f8a8be | 2726 | (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) |
ae156f85 | 2727 | (clobber (reg:CC CC_REGNUM))] |
19796784 AK |
2728 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" |
2729 | "#" | |
2730 | "&& reload_completed" | |
4023fb28 | 2731 | [(parallel |
6fa05db6 | 2732 | [(set (match_dup 0) (unspec:DI [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 2733 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 UW |
2734 | (parallel |
2735 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
ae156f85 | 2736 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
2737 | { |
2738 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2739 | set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); | |
2740 | }) | |
9db1d521 HP |
2741 | |
2742 | ; | |
f6ee577c | 2743 | ; extend(hi|qi)si2 instruction pattern(s). |
9db1d521 HP |
2744 | ; |
2745 | ||
f6ee577c | 2746 | (define_expand "extend<mode>si2" |
4023fb28 | 2747 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 2748 | (sign_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 2749 | "" |
4023fb28 | 2750 | { |
ec24698e UW |
2751 | if (!TARGET_EXTIMM) |
2752 | { | |
2753 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) - | |
2754 | GET_MODE_BITSIZE(<MODE>mode)); | |
2755 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2756 | emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount)); | |
2757 | emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount)); | |
2758 | DONE; | |
2759 | } | |
2760 | }) | |
2761 | ||
2762 | (define_insn "*extendhisi2_extimm" | |
2763 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
2764 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))] | |
2765 | "TARGET_EXTIMM" | |
2766 | "@ | |
2767 | lhr\t%0,%1 | |
2768 | lh\t%0,%1 | |
2769 | lhy\t%0,%1" | |
2770 | [(set_attr "op_type" "RRE,RX,RXY")]) | |
9db1d521 | 2771 | |
4023fb28 | 2772 | (define_insn "*extendhisi2" |
d3632d41 UW |
2773 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2774 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 2775 | "!TARGET_EXTIMM" |
d3632d41 | 2776 | "@ |
d40c829f UW |
2777 | lh\t%0,%1 |
2778 | lhy\t%0,%1" | |
d3632d41 | 2779 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 | 2780 | |
ec24698e UW |
2781 | (define_insn "*extendqisi2_extimm" |
2782 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2783 | (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] | |
2784 | "TARGET_EXTIMM" | |
2785 | "@ | |
2786 | lbr\t%0,%1 | |
2787 | lb\t%0,%1" | |
2788 | [(set_attr "op_type" "RRE,RXY")]) | |
2789 | ||
d3632d41 UW |
2790 | (define_insn "*extendqisi2" |
2791 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2792 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
ec24698e | 2793 | "TARGET_LONG_DISPLACEMENT && !TARGET_EXTIMM" |
d40c829f | 2794 | "lb\t%0,%1" |
d3632d41 UW |
2795 | [(set_attr "op_type" "RXY")]) |
2796 | ||
eb457a7a | 2797 | (define_insn_and_split "*extendqisi2_short_displ" |
19796784 | 2798 | [(set (match_operand:SI 0 "register_operand" "=d") |
59f8a8be | 2799 | (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) |
ae156f85 | 2800 | (clobber (reg:CC CC_REGNUM))] |
19796784 AK |
2801 | "!TARGET_LONG_DISPLACEMENT" |
2802 | "#" | |
2803 | "&& reload_completed" | |
4023fb28 | 2804 | [(parallel |
6fa05db6 | 2805 | [(set (match_dup 0) (unspec:SI [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 2806 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 UW |
2807 | (parallel |
2808 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
ae156f85 | 2809 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
2810 | { |
2811 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2812 | set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); | |
2813 | }) | |
9db1d521 HP |
2814 | |
2815 | ; | |
2816 | ; extendqihi2 instruction pattern(s). | |
2817 | ; | |
2818 | ||
9db1d521 HP |
2819 | |
2820 | ; | |
2821 | ; zero_extendsidi2 instruction pattern(s). | |
2822 | ; | |
2823 | ||
4023fb28 UW |
2824 | (define_expand "zero_extendsidi2" |
2825 | [(set (match_operand:DI 0 "register_operand" "") | |
2826 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2827 | "" | |
4023fb28 UW |
2828 | { |
2829 | if (!TARGET_64BIT) | |
2830 | { | |
9f37ccb1 UW |
2831 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2832 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2833 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2834 | DONE; |
2835 | } | |
ec24698e | 2836 | }) |
4023fb28 UW |
2837 | |
2838 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2839 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2840 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2841 | "TARGET_64BIT" | |
2842 | "@ | |
d40c829f UW |
2843 | llgfr\t%0,%1 |
2844 | llgf\t%0,%1" | |
d3632d41 | 2845 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2846 | |
9db1d521 | 2847 | ; |
f6ee577c | 2848 | ; zero_extend(hi|qi)di2 instruction pattern(s). |
9db1d521 HP |
2849 | ; |
2850 | ||
f6ee577c | 2851 | (define_expand "zero_extend<mode>di2" |
4023fb28 | 2852 | [(set (match_operand:DI 0 "register_operand" "") |
ec24698e | 2853 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
4023fb28 | 2854 | "" |
4023fb28 UW |
2855 | { |
2856 | if (!TARGET_64BIT) | |
2857 | { | |
2858 | rtx tmp = gen_reg_rtx (SImode); | |
f6ee577c | 2859 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); |
4023fb28 UW |
2860 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); |
2861 | DONE; | |
2862 | } | |
ec24698e | 2863 | else if (!TARGET_EXTIMM) |
4023fb28 | 2864 | { |
f6ee577c AS |
2865 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - |
2866 | GET_MODE_BITSIZE(<MODE>mode)); | |
4023fb28 | 2867 | operands[1] = gen_lowpart (DImode, operands[1]); |
f6ee577c AS |
2868 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); |
2869 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2870 | DONE; |
2871 | } | |
ec24698e UW |
2872 | }) |
2873 | ||
2874 | (define_insn "*zero_extend<mode>di2_extimm" | |
2875 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2876 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))] | |
2877 | "TARGET_64BIT && TARGET_EXTIMM" | |
2878 | "@ | |
2879 | llg<hc>r\t%0,%1 | |
2880 | llg<hc>\t%0,%1" | |
2881 | [(set_attr "op_type" "RRE,RXY")]) | |
9db1d521 | 2882 | |
f6ee577c | 2883 | (define_insn "*zero_extend<mode>di2" |
4023fb28 | 2884 | [(set (match_operand:DI 0 "register_operand" "=d") |
f6ee577c | 2885 | (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))] |
ec24698e | 2886 | "TARGET_64BIT && !TARGET_EXTIMM" |
f6ee577c | 2887 | "llg<hc>\t%0,%1" |
d3632d41 | 2888 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2889 | |
288e517f AK |
2890 | ; |
2891 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2892 | ; | |
2893 | ||
d6083c7d UW |
2894 | (define_insn "*llgt_sidi" |
2895 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2896 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2897 | (const_int 2147483647)))] | |
2898 | "TARGET_64BIT" | |
2899 | "llgt\t%0,%1" | |
2900 | [(set_attr "op_type" "RXE")]) | |
2901 | ||
2902 | (define_insn_and_split "*llgt_sidi_split" | |
2903 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2904 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2905 | (const_int 2147483647))) | |
ae156f85 | 2906 | (clobber (reg:CC CC_REGNUM))] |
d6083c7d UW |
2907 | "TARGET_64BIT" |
2908 | "#" | |
2909 | "&& reload_completed" | |
2910 | [(set (match_dup 0) | |
2911 | (and:DI (subreg:DI (match_dup 1) 0) | |
2912 | (const_int 2147483647)))] | |
2913 | "") | |
2914 | ||
288e517f AK |
2915 | (define_insn "*llgt_sisi" |
2916 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2917 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2918 | (const_int 2147483647)))] | |
c4d50129 | 2919 | "TARGET_ZARCH" |
288e517f AK |
2920 | "@ |
2921 | llgtr\t%0,%1 | |
2922 | llgt\t%0,%1" | |
2923 | [(set_attr "op_type" "RRE,RXE")]) | |
2924 | ||
288e517f AK |
2925 | (define_insn "*llgt_didi" |
2926 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2927 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2928 | (const_int 2147483647)))] | |
2929 | "TARGET_64BIT" | |
2930 | "@ | |
2931 | llgtr\t%0,%1 | |
2932 | llgt\t%0,%N1" | |
2933 | [(set_attr "op_type" "RRE,RXE")]) | |
2934 | ||
f19a9af7 | 2935 | (define_split |
f6ee577c AS |
2936 | [(set (match_operand:GPR 0 "register_operand" "") |
2937 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
2938 | (const_int 2147483647))) | |
ae156f85 | 2939 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 2940 | "TARGET_ZARCH && reload_completed" |
288e517f | 2941 | [(set (match_dup 0) |
f6ee577c AS |
2942 | (and:GPR (match_dup 1) |
2943 | (const_int 2147483647)))] | |
288e517f AK |
2944 | "") |
2945 | ||
9db1d521 | 2946 | ; |
f6ee577c | 2947 | ; zero_extend(hi|qi)si2 instruction pattern(s). |
9db1d521 HP |
2948 | ; |
2949 | ||
f6ee577c | 2950 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 2951 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 2952 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 2953 | "" |
4023fb28 | 2954 | { |
ec24698e UW |
2955 | if (!TARGET_EXTIMM) |
2956 | { | |
2957 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2958 | emit_insn (gen_andsi3 (operands[0], operands[1], | |
2959 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); | |
2960 | DONE; | |
4023fb28 | 2961 | } |
ec24698e UW |
2962 | }) |
2963 | ||
2964 | (define_insn "*zero_extend<mode>si2_extimm" | |
2965 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2966 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "d,m")))] | |
2967 | "TARGET_EXTIMM" | |
2968 | "@ | |
2969 | ll<hc>r\t%0,%1 | |
2970 | ll<hc>\t%0,%1" | |
2971 | [(set_attr "op_type" "RRE,RXY")]) | |
9db1d521 | 2972 | |
f6ee577c | 2973 | (define_insn "*zero_extend<mode>si2_64" |
9db1d521 | 2974 | [(set (match_operand:SI 0 "register_operand" "=d") |
f6ee577c | 2975 | (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))] |
ec24698e | 2976 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 2977 | "llg<hc>\t%0,%1" |
d3632d41 | 2978 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2979 | |
2980 | (define_insn_and_split "*zero_extendhisi2_31" | |
2981 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2982 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 2983 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 2984 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2985 | "#" |
2986 | "&& reload_completed" | |
2987 | [(set (match_dup 0) (const_int 0)) | |
2988 | (parallel | |
2989 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 2990 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 2991 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 2992 | |
cc7ab9b7 UW |
2993 | (define_insn_and_split "*zero_extendqisi2_31" |
2994 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2995 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2996 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2997 | "#" |
2998 | "&& reload_completed" | |
2999 | [(set (match_dup 0) (const_int 0)) | |
3000 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3001 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 3002 | |
9db1d521 HP |
3003 | ; |
3004 | ; zero_extendqihi2 instruction pattern(s). | |
3005 | ; | |
3006 | ||
9db1d521 HP |
3007 | (define_expand "zero_extendqihi2" |
3008 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 3009 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 3010 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 3011 | { |
4023fb28 UW |
3012 | operands[1] = gen_lowpart (HImode, operands[1]); |
3013 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
3014 | DONE; | |
ec24698e | 3015 | }) |
9db1d521 | 3016 | |
4023fb28 | 3017 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 3018 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 3019 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
ec24698e | 3020 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 3021 | "llgc\t%0,%1" |
d3632d41 | 3022 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 3023 | |
cc7ab9b7 UW |
3024 | (define_insn_and_split "*zero_extendqihi2_31" |
3025 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3026 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 3027 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3028 | "#" |
3029 | "&& reload_completed" | |
3030 | [(set (match_dup 0) (const_int 0)) | |
3031 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3032 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 UW |
3033 | |
3034 | ||
9db1d521 | 3035 | ; |
2f8f8434 | 3036 | ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3037 | ; |
3038 | ||
2f8f8434 AS |
3039 | (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2" |
3040 | [(set (match_operand:GPR 0 "register_operand" "") | |
3041 | (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))] | |
3042 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3043 | { |
3044 | rtx label1 = gen_label_rtx (); | |
3045 | rtx label2 = gen_label_rtx (); | |
2f8f8434 AS |
3046 | rtx temp = gen_reg_rtx (<FPR:MODE>mode); |
3047 | REAL_VALUE_TYPE cmp, sub; | |
3048 | ||
3049 | operands[1] = force_reg (<FPR:MODE>mode, operands[1]); | |
3050 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1); | |
3051 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode)); | |
3052 | ||
3053 | emit_insn (gen_cmp<FPR:mode> (operands[1], | |
3054 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode))); | |
9db1d521 | 3055 | emit_jump_insn (gen_blt (label1)); |
2f8f8434 AS |
3056 | emit_insn (gen_sub<FPR:mode>3 (temp, operands[1], |
3057 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode))); | |
3058 | emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp, | |
3059 | GEN_INT(7))); | |
f314b9b1 | 3060 | emit_jump (label2); |
9db1d521 HP |
3061 | |
3062 | emit_label (label1); | |
2f8f8434 AS |
3063 | emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], |
3064 | operands[1], GEN_INT(5))); | |
9db1d521 HP |
3065 | emit_label (label2); |
3066 | DONE; | |
10bbf137 | 3067 | }) |
9db1d521 | 3068 | |
2f8f8434 | 3069 | (define_expand "fix_trunc<FPR:mode>di2" |
9db1d521 | 3070 | [(set (match_operand:DI 0 "register_operand" "") |
2f8f8434 | 3071 | (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))] |
9db1d521 | 3072 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
9db1d521 | 3073 | { |
2f8f8434 AS |
3074 | operands[1] = force_reg (<FPR:MODE>mode, operands[1]); |
3075 | emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1], | |
3076 | GEN_INT(5))); | |
9db1d521 | 3077 | DONE; |
10bbf137 | 3078 | }) |
9db1d521 | 3079 | |
2f8f8434 AS |
3080 | (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee" |
3081 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3082 | (fix:GPR (match_operand:FPR 1 "register_operand" "f"))) | |
3083 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 3084 | (clobber (reg:CC CC_REGNUM))] |
2f8f8434 AS |
3085 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3086 | "c<GPR:gf><FPR:de>br\t%0,%h2,%1" | |
9db1d521 | 3087 | [(set_attr "op_type" "RRE") |
077dab3b | 3088 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
3089 | |
3090 | ; | |
2f8f8434 | 3091 | ; fix_truncdfsi2 instruction pattern(s). |
9db1d521 HP |
3092 | ; |
3093 | ||
9db1d521 HP |
3094 | (define_expand "fix_truncdfsi2" |
3095 | [(set (match_operand:SI 0 "register_operand" "") | |
3096 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
3097 | "TARGET_HARD_FLOAT" | |
9db1d521 | 3098 | { |
c7453384 | 3099 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3100 | { |
3101 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
3102 | ||
c19ec8f9 | 3103 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
3104 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
3105 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
3106 | |
3107 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 3108 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 3109 | two31r, two32, temp)); |
c7453384 EC |
3110 | } |
3111 | else | |
9db1d521 HP |
3112 | { |
3113 | operands[1] = force_reg (DFmode, operands[1]); | |
3114 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3115 | } | |
3116 | ||
3117 | DONE; | |
10bbf137 | 3118 | }) |
9db1d521 | 3119 | |
9db1d521 HP |
3120 | (define_insn "fix_truncdfsi2_ibm" |
3121 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3122 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
3123 | (use (match_operand:DI 2 "immediate_operand" "m")) |
3124 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 | 3125 | (use (match_operand:BLK 4 "memory_operand" "m")) |
ae156f85 | 3126 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3127 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
9db1d521 | 3128 | { |
d40c829f UW |
3129 | output_asm_insn ("sd\t%1,%2", operands); |
3130 | output_asm_insn ("aw\t%1,%3", operands); | |
3131 | output_asm_insn ("std\t%1,%4", operands); | |
3132 | output_asm_insn ("xi\t%N4,128", operands); | |
3133 | return "l\t%0,%N4"; | |
10bbf137 | 3134 | } |
b628bd8e | 3135 | [(set_attr "length" "20")]) |
9db1d521 HP |
3136 | |
3137 | ; | |
2f8f8434 | 3138 | ; fix_truncsfsi2 instruction pattern(s). |
9db1d521 HP |
3139 | ; |
3140 | ||
9db1d521 HP |
3141 | (define_expand "fix_truncsfsi2" |
3142 | [(set (match_operand:SI 0 "register_operand" "") | |
3143 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3144 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3145 | { |
3146 | if (TARGET_IBM_FLOAT) | |
3147 | { | |
3148 | /* Convert to DFmode and then use the POP algorithm. */ | |
3149 | rtx temp = gen_reg_rtx (DFmode); | |
3150 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
3151 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
3152 | } | |
3153 | else | |
3154 | { | |
3155 | operands[1] = force_reg (SFmode, operands[1]); | |
3156 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3157 | } | |
3158 | ||
3159 | DONE; | |
10bbf137 | 3160 | }) |
9db1d521 | 3161 | |
9db1d521 | 3162 | ; |
f5905b37 | 3163 | ; floatdi(df|sf)2 instruction pattern(s). |
9db1d521 HP |
3164 | ; |
3165 | ||
f5905b37 AS |
3166 | (define_insn "floatdi<mode>2" |
3167 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
3168 | (float:FPR (match_operand:DI 1 "register_operand" "d")))] | |
9db1d521 | 3169 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 3170 | "c<de>gbr\t%0,%1" |
9db1d521 | 3171 | [(set_attr "op_type" "RRE") |
077dab3b | 3172 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3173 | |
3174 | ; | |
3175 | ; floatsidf2 instruction pattern(s). | |
3176 | ; | |
3177 | ||
3178 | (define_expand "floatsidf2" | |
a036c6f7 UW |
3179 | [(set (match_operand:DF 0 "register_operand" "") |
3180 | (float:DF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3181 | "TARGET_HARD_FLOAT" |
9db1d521 | 3182 | { |
c7453384 | 3183 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3184 | { |
3185 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
3186 | ||
c19ec8f9 | 3187 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 3188 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
3189 | |
3190 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
3191 | DONE; | |
3192 | } | |
10bbf137 | 3193 | }) |
9db1d521 HP |
3194 | |
3195 | (define_insn "floatsidf2_ieee" | |
3196 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 3197 | (float:DF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3198 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3199 | "cdfbr\t%0,%1" |
9db1d521 | 3200 | [(set_attr "op_type" "RRE") |
077dab3b | 3201 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3202 | |
3203 | (define_insn "floatsidf2_ibm" | |
3204 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3205 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3206 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 | 3207 | (use (match_operand:BLK 3 "memory_operand" "m")) |
ae156f85 | 3208 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3209 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
9db1d521 | 3210 | { |
d40c829f UW |
3211 | output_asm_insn ("st\t%1,%N3", operands); |
3212 | output_asm_insn ("xi\t%N3,128", operands); | |
3213 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3214 | output_asm_insn ("ld\t%0,%3", operands); | |
3215 | return "sd\t%0,%2"; | |
10bbf137 | 3216 | } |
b628bd8e | 3217 | [(set_attr "length" "20")]) |
9db1d521 HP |
3218 | |
3219 | ; | |
3220 | ; floatsisf2 instruction pattern(s). | |
3221 | ; | |
3222 | ||
3223 | (define_expand "floatsisf2" | |
a036c6f7 UW |
3224 | [(set (match_operand:SF 0 "register_operand" "") |
3225 | (float:SF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3226 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3227 | { |
3228 | if (TARGET_IBM_FLOAT) | |
3229 | { | |
3230 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3231 | rtx temp = gen_reg_rtx (DFmode); | |
3232 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3233 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3234 | DONE; | |
3235 | } | |
10bbf137 | 3236 | }) |
9db1d521 HP |
3237 | |
3238 | (define_insn "floatsisf2_ieee" | |
3239 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3240 | (float:SF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3241 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3242 | "cefbr\t%0,%1" |
9db1d521 | 3243 | [(set_attr "op_type" "RRE") |
077dab3b | 3244 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3245 | |
3246 | ; | |
3247 | ; truncdfsf2 instruction pattern(s). | |
3248 | ; | |
3249 | ||
3250 | (define_expand "truncdfsf2" | |
3251 | [(set (match_operand:SF 0 "register_operand" "") | |
a036c6f7 | 3252 | (float_truncate:SF (match_operand:DF 1 "register_operand" "")))] |
9db1d521 | 3253 | "TARGET_HARD_FLOAT" |
4023fb28 | 3254 | "") |
9db1d521 HP |
3255 | |
3256 | (define_insn "truncdfsf2_ieee" | |
3257 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3258 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
9db1d521 | 3259 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3260 | "ledbr\t%0,%1" |
ce50cae8 | 3261 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
3262 | |
3263 | (define_insn "truncdfsf2_ibm" | |
3264 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
a036c6f7 | 3265 | (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3266 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3267 | "@ | |
a036c6f7 | 3268 | ler\t%0,%1 |
d40c829f | 3269 | le\t%0,%1" |
4023fb28 | 3270 | [(set_attr "op_type" "RR,RX") |
cfdb984b | 3271 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
3272 | |
3273 | ; | |
3274 | ; extendsfdf2 instruction pattern(s). | |
3275 | ; | |
3276 | ||
3277 | (define_expand "extendsfdf2" | |
3278 | [(set (match_operand:DF 0 "register_operand" "") | |
3279 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3280 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3281 | { |
3282 | if (TARGET_IBM_FLOAT) | |
3283 | { | |
3284 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3285 | DONE; | |
3286 | } | |
10bbf137 | 3287 | }) |
9db1d521 HP |
3288 | |
3289 | (define_insn "extendsfdf2_ieee" | |
3290 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3291 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3292 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3293 | "@ | |
d40c829f UW |
3294 | ldebr\t%0,%1 |
3295 | ldeb\t%0,%1" | |
077dab3b | 3296 | [(set_attr "op_type" "RRE,RXE") |
cfdb984b | 3297 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
3298 | |
3299 | (define_insn "extendsfdf2_ibm" | |
3300 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3301 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
ae156f85 | 3302 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3303 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3304 | "@ | |
d40c829f UW |
3305 | sdr\t%0,%0\;ler\t%0,%1 |
3306 | sdr\t%0,%0\;le\t%0,%1" | |
b628bd8e | 3307 | [(set_attr "length" "4,6") |
cfdb984b | 3308 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
3309 | |
3310 | ||
3311 | ;; | |
fae778eb | 3312 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3313 | ;; |
fae778eb | 3314 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3315 | ; because of unpredictable Bits in Register for Halfword and Byte |
3316 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3317 | ||
07893d4f UW |
3318 | ;; |
3319 | ;;- Add instructions. | |
3320 | ;; | |
3321 | ||
1c7b1b7e UW |
3322 | ; |
3323 | ; addti3 instruction pattern(s). | |
3324 | ; | |
3325 | ||
3326 | (define_insn_and_split "addti3" | |
3327 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3328 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
3329 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 3330 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
3331 | "TARGET_64BIT" |
3332 | "#" | |
3333 | "&& reload_completed" | |
3334 | [(parallel | |
ae156f85 | 3335 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
3336 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
3337 | (match_dup 7))) | |
3338 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
3339 | (parallel | |
3340 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3341 | (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)))) |
3342 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
3343 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
3344 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3345 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3346 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3347 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3348 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3349 | |
07893d4f UW |
3350 | ; |
3351 | ; adddi3 instruction pattern(s). | |
3352 | ; | |
3353 | ||
07893d4f UW |
3354 | (define_insn "*adddi3_sign" |
3355 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3356 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3357 | (match_operand:DI 1 "register_operand" "0,0"))) | |
ae156f85 | 3358 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3359 | "TARGET_64BIT" |
3360 | "@ | |
d40c829f UW |
3361 | agfr\t%0,%2 |
3362 | agf\t%0,%2" | |
d3632d41 | 3363 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3364 | |
3365 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 3366 | [(set (reg CC_REGNUM) |
07893d4f UW |
3367 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3368 | (match_operand:DI 1 "register_operand" "0,0")) | |
3369 | (const_int 0))) | |
3370 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3371 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3372 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3373 | "@ | |
d40c829f UW |
3374 | algfr\t%0,%2 |
3375 | algf\t%0,%2" | |
d3632d41 | 3376 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3377 | |
3378 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 3379 | [(set (reg CC_REGNUM) |
07893d4f UW |
3380 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3381 | (match_operand:DI 1 "register_operand" "0,0")) | |
3382 | (const_int 0))) | |
3383 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3384 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3385 | "@ | |
d40c829f UW |
3386 | algfr\t%0,%2 |
3387 | algf\t%0,%2" | |
d3632d41 | 3388 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3389 | |
3390 | (define_insn "*adddi3_zero" | |
3391 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3392 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3393 | (match_operand:DI 1 "register_operand" "0,0"))) | |
ae156f85 | 3394 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3395 | "TARGET_64BIT" |
3396 | "@ | |
d40c829f UW |
3397 | algfr\t%0,%2 |
3398 | algf\t%0,%2" | |
d3632d41 | 3399 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3400 | |
0a3bdf9d | 3401 | (define_insn "*adddi3_imm_cc" |
ae156f85 | 3402 | [(set (reg CC_REGNUM) |
ec24698e UW |
3403 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") |
3404 | (match_operand:DI 2 "const_int_operand" "K,Os")) | |
0a3bdf9d | 3405 | (const_int 0))) |
ec24698e | 3406 | (set (match_operand:DI 0 "register_operand" "=d,d") |
0a3bdf9d | 3407 | (plus:DI (match_dup 1) (match_dup 2)))] |
c7453384 EC |
3408 | "TARGET_64BIT |
3409 | && s390_match_ccmode (insn, CCAmode) | |
ec24698e UW |
3410 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") |
3411 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))" | |
3412 | "@ | |
3413 | aghi\t%0,%h2 | |
3414 | agfi\t%0,%2" | |
3415 | [(set_attr "op_type" "RI,RIL")]) | |
0a3bdf9d | 3416 | |
b2ba71ca | 3417 | (define_insn "*adddi3_carry1_cc" |
ae156f85 | 3418 | [(set (reg CC_REGNUM) |
ec24698e UW |
3419 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") |
3420 | (match_operand:DI 2 "general_operand" "d,Op,On,m")) | |
b2ba71ca | 3421 | (match_dup 1))) |
ec24698e | 3422 | (set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
b2ba71ca UW |
3423 | (plus:DI (match_dup 1) (match_dup 2)))] |
3424 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3425 | "@ | |
3426 | algr\t%0,%2 | |
ec24698e UW |
3427 | algfi\t%0,%2 |
3428 | slgfi\t%0,%n2 | |
b2ba71ca | 3429 | alg\t%0,%2" |
ec24698e | 3430 | [(set_attr "op_type" "RRE,RIL,RIL,RXY")]) |
b2ba71ca UW |
3431 | |
3432 | (define_insn "*adddi3_carry1_cconly" | |
ae156f85 | 3433 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3434 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
3435 | (match_operand:DI 2 "general_operand" "d,m")) | |
3436 | (match_dup 1))) | |
3437 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3438 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3439 | "@ | |
3440 | algr\t%0,%2 | |
3441 | alg\t%0,%2" | |
3442 | [(set_attr "op_type" "RRE,RXY")]) | |
3443 | ||
3444 | (define_insn "*adddi3_carry2_cc" | |
ae156f85 | 3445 | [(set (reg CC_REGNUM) |
ec24698e UW |
3446 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") |
3447 | (match_operand:DI 2 "general_operand" "d,Op,On,m")) | |
b2ba71ca | 3448 | (match_dup 2))) |
ec24698e | 3449 | (set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
b2ba71ca UW |
3450 | (plus:DI (match_dup 1) (match_dup 2)))] |
3451 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3452 | "@ | |
3453 | algr\t%0,%2 | |
ec24698e UW |
3454 | algfi\t%0,%2 |
3455 | slgfi\t%0,%n2 | |
b2ba71ca | 3456 | alg\t%0,%2" |
ec24698e | 3457 | [(set_attr "op_type" "RRE,RIL,RIL,RXY")]) |
b2ba71ca UW |
3458 | |
3459 | (define_insn "*adddi3_carry2_cconly" | |
ae156f85 | 3460 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3461 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
3462 | (match_operand:DI 2 "general_operand" "d,m")) | |
3463 | (match_dup 2))) | |
3464 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3465 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3466 | "@ | |
3467 | algr\t%0,%2 | |
3468 | alg\t%0,%2" | |
3469 | [(set_attr "op_type" "RRE,RXY")]) | |
3470 | ||
07893d4f | 3471 | (define_insn "*adddi3_cc" |
ae156f85 | 3472 | [(set (reg CC_REGNUM) |
ec24698e UW |
3473 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") |
3474 | (match_operand:DI 2 "general_operand" "d,Op,On,m")) | |
07893d4f | 3475 | (const_int 0))) |
ec24698e | 3476 | (set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
07893d4f UW |
3477 | (plus:DI (match_dup 1) (match_dup 2)))] |
3478 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3479 | "@ | |
d40c829f | 3480 | algr\t%0,%2 |
ec24698e UW |
3481 | algfi\t%0,%2 |
3482 | slgfi\t%0,%n2 | |
d40c829f | 3483 | alg\t%0,%2" |
ec24698e | 3484 | [(set_attr "op_type" "RRE,RIL,RIL,RXY")]) |
9db1d521 | 3485 | |
07893d4f | 3486 | (define_insn "*adddi3_cconly" |
ae156f85 | 3487 | [(set (reg CC_REGNUM) |
96fd3851 | 3488 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3489 | (match_operand:DI 2 "general_operand" "d,m")) |
3490 | (const_int 0))) | |
3491 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3492 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3493 | "@ | |
d40c829f UW |
3494 | algr\t%0,%2 |
3495 | alg\t%0,%2" | |
d3632d41 | 3496 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3497 | |
07893d4f | 3498 | (define_insn "*adddi3_cconly2" |
ae156f85 | 3499 | [(set (reg CC_REGNUM) |
96fd3851 | 3500 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3501 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3502 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3503 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3504 | "@ |
d40c829f UW |
3505 | algr\t%0,%2 |
3506 | alg\t%0,%2" | |
d3632d41 | 3507 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3508 | |
07893d4f | 3509 | (define_insn "*adddi3_64" |
ec24698e UW |
3510 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") |
3511 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
3512 | (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) ) | |
ae156f85 | 3513 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3514 | "TARGET_64BIT" |
3515 | "@ | |
d40c829f UW |
3516 | agr\t%0,%2 |
3517 | aghi\t%0,%h2 | |
ec24698e UW |
3518 | algfi\t%0,%2 |
3519 | slgfi\t%0,%n2 | |
d40c829f | 3520 | ag\t%0,%2" |
ec24698e | 3521 | [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")]) |
9db1d521 | 3522 | |
e69166de UW |
3523 | (define_insn_and_split "*adddi3_31z" |
3524 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3525 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3526 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 3527 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
3528 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
3529 | "#" | |
3530 | "&& reload_completed" | |
3531 | [(parallel | |
ae156f85 | 3532 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
3533 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
3534 | (match_dup 7))) | |
3535 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3536 | (parallel | |
3537 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3538 | (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)))) |
3539 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
3540 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3541 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3542 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3543 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3544 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3545 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3546 | |
07893d4f UW |
3547 | (define_insn_and_split "*adddi3_31" |
3548 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3549 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3550 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 3551 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 3552 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3553 | "#" |
3554 | "&& reload_completed" | |
3555 | [(parallel | |
3556 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 3557 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3558 | (parallel |
ae156f85 | 3559 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
3560 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
3561 | (match_dup 7))) | |
3562 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3563 | (set (pc) | |
ae156f85 | 3564 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
3565 | (pc) |
3566 | (label_ref (match_dup 9)))) | |
3567 | (parallel | |
3568 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 3569 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3570 | (match_dup 9)] |
97c6f7ad UW |
3571 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3572 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3573 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3574 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3575 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3576 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3577 | operands[9] = gen_label_rtx ();") |
9db1d521 HP |
3578 | |
3579 | (define_expand "adddi3" | |
07893d4f UW |
3580 | [(parallel |
3581 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3582 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f | 3583 | (match_operand:DI 2 "general_operand" ""))) |
ae156f85 | 3584 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 3585 | "" |
07893d4f | 3586 | "") |
9db1d521 | 3587 | |
9db1d521 HP |
3588 | ; |
3589 | ; addsi3 instruction pattern(s). | |
3590 | ; | |
9db1d521 | 3591 | |
0a3bdf9d | 3592 | (define_insn "*addsi3_imm_cc" |
ae156f85 | 3593 | [(set (reg CC_REGNUM) |
ec24698e UW |
3594 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") |
3595 | (match_operand:SI 2 "const_int_operand" "K,Os")) | |
0a3bdf9d | 3596 | (const_int 0))) |
ec24698e | 3597 | (set (match_operand:SI 0 "register_operand" "=d,d") |
0a3bdf9d UW |
3598 | (plus:SI (match_dup 1) (match_dup 2)))] |
3599 | "s390_match_ccmode (insn, CCAmode) | |
ec24698e UW |
3600 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") |
3601 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")) | |
3602 | && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)" | |
3603 | "@ | |
3604 | ahi\t%0,%h2 | |
3605 | afi\t%0,%2" | |
3606 | [(set_attr "op_type" "RI,RIL")]) | |
0a3bdf9d | 3607 | |
07893d4f | 3608 | (define_insn "*addsi3_carry1_cc" |
ae156f85 | 3609 | [(set (reg CC_REGNUM) |
ec24698e UW |
3610 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
3611 | (match_operand:SI 2 "general_operand" "d,Os,R,T")) | |
07893d4f | 3612 | (match_dup 1))) |
ec24698e | 3613 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
07893d4f | 3614 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3615 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3616 | "@ |
d40c829f | 3617 | alr\t%0,%2 |
ec24698e | 3618 | alfi\t%0,%o2 |
d40c829f UW |
3619 | al\t%0,%2 |
3620 | aly\t%0,%2" | |
ec24698e | 3621 | [(set_attr "op_type" "RR,RIL,RX,RXY")]) |
07893d4f UW |
3622 | |
3623 | (define_insn "*addsi3_carry1_cconly" | |
ae156f85 | 3624 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3625 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3626 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3627 | (match_dup 1))) |
d3632d41 | 3628 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3629 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3630 | "@ |
d40c829f UW |
3631 | alr\t%0,%2 |
3632 | al\t%0,%2 | |
3633 | aly\t%0,%2" | |
d3632d41 | 3634 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3635 | |
3636 | (define_insn "*addsi3_carry2_cc" | |
ae156f85 | 3637 | [(set (reg CC_REGNUM) |
ec24698e UW |
3638 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
3639 | (match_operand:SI 2 "general_operand" "d,Os,R,T")) | |
07893d4f | 3640 | (match_dup 2))) |
ec24698e | 3641 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
07893d4f | 3642 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3643 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3644 | "@ |
d40c829f | 3645 | alr\t%0,%2 |
ec24698e | 3646 | alfi\t%0,%o2 |
d40c829f UW |
3647 | al\t%0,%2 |
3648 | aly\t%0,%2" | |
ec24698e | 3649 | [(set_attr "op_type" "RR,RIL,RX,RXY")]) |
07893d4f UW |
3650 | |
3651 | (define_insn "*addsi3_carry2_cconly" | |
ae156f85 | 3652 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3653 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3654 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3655 | (match_dup 2))) |
d3632d41 | 3656 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3657 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3658 | "@ |
d40c829f UW |
3659 | alr\t%0,%2 |
3660 | al\t%0,%2 | |
3661 | aly\t%0,%2" | |
d3632d41 | 3662 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3663 | |
9db1d521 | 3664 | (define_insn "*addsi3_cc" |
ae156f85 | 3665 | [(set (reg CC_REGNUM) |
ec24698e UW |
3666 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
3667 | (match_operand:SI 2 "general_operand" "d,Os,R,T")) | |
9db1d521 | 3668 | (const_int 0))) |
ec24698e | 3669 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
9db1d521 | 3670 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3671 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3672 | "@ |
d40c829f | 3673 | alr\t%0,%2 |
ec24698e | 3674 | alfi\t%0,%o2 |
d40c829f UW |
3675 | al\t%0,%2 |
3676 | aly\t%0,%2" | |
ec24698e | 3677 | [(set_attr "op_type" "RR,RIL,RX,RXY")]) |
9db1d521 HP |
3678 | |
3679 | (define_insn "*addsi3_cconly" | |
ae156f85 | 3680 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3681 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3682 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3683 | (const_int 0))) |
d3632d41 | 3684 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3685 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3686 | "@ |
d40c829f UW |
3687 | alr\t%0,%2 |
3688 | al\t%0,%2 | |
3689 | aly\t%0,%2" | |
d3632d41 | 3690 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3691 | |
3692 | (define_insn "*addsi3_cconly2" | |
ae156f85 | 3693 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3694 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3695 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3696 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3697 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3698 | "@ |
d40c829f UW |
3699 | alr\t%0,%2 |
3700 | al\t%0,%2 | |
3701 | aly\t%0,%2" | |
d3632d41 | 3702 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3703 | |
07893d4f | 3704 | (define_insn "*addsi3_sign" |
d3632d41 | 3705 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f0ad121f UW |
3706 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) |
3707 | (match_operand:SI 1 "register_operand" "0,0"))) | |
ae156f85 | 3708 | (clobber (reg:CC CC_REGNUM))] |
07893d4f | 3709 | "" |
d3632d41 | 3710 | "@ |
d40c829f UW |
3711 | ah\t%0,%2 |
3712 | ahy\t%0,%2" | |
d3632d41 | 3713 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3714 | |
9db1d521 | 3715 | (define_insn "addsi3" |
ec24698e UW |
3716 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
3717 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
3718 | (match_operand:SI 2 "general_operand" "d,K,Os,R,T"))) | |
ae156f85 | 3719 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3720 | "" |
3721 | "@ | |
d40c829f UW |
3722 | ar\t%0,%2 |
3723 | ahi\t%0,%h2 | |
ec24698e | 3724 | afi\t%0,%2 |
d40c829f UW |
3725 | a\t%0,%2 |
3726 | ay\t%0,%2" | |
ec24698e | 3727 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY")]) |
9db1d521 | 3728 | |
9db1d521 | 3729 | ; |
f5905b37 | 3730 | ; add(df|sf)3 instruction pattern(s). |
9db1d521 HP |
3731 | ; |
3732 | ||
f5905b37 | 3733 | (define_expand "add<mode>3" |
9db1d521 | 3734 | [(parallel |
f5905b37 AS |
3735 | [(set (match_operand:FPR 0 "register_operand" "=f,f") |
3736 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3737 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3738 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
3739 | "TARGET_HARD_FLOAT" |
3740 | "") | |
3741 | ||
f5905b37 AS |
3742 | (define_insn "*add<mode>3" |
3743 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3744 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3745 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3746 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3747 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3748 | "@ | |
f5905b37 AS |
3749 | a<de>br\t%0,%2 |
3750 | a<de>b\t%0,%2" | |
ce50cae8 | 3751 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3752 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 3753 | |
f5905b37 | 3754 | (define_insn "*add<mode>3_cc" |
ae156f85 | 3755 | [(set (reg CC_REGNUM) |
f5905b37 AS |
3756 | (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") |
3757 | (match_operand:FPR 2 "general_operand" "f,R")) | |
3758 | (match_operand:FPR 3 "const0_operand" ""))) | |
3759 | (set (match_operand:FPR 0 "register_operand" "=f,f") | |
3760 | (plus:FPR (match_dup 1) (match_dup 2)))] | |
3ef093a8 AK |
3761 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3762 | "@ | |
f5905b37 AS |
3763 | a<de>br\t%0,%2 |
3764 | a<de>b\t%0,%2" | |
3ef093a8 | 3765 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3766 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3767 | |
f5905b37 | 3768 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 3769 | [(set (reg CC_REGNUM) |
f5905b37 AS |
3770 | (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") |
3771 | (match_operand:FPR 2 "general_operand" "f,R")) | |
3772 | (match_operand:FPR 3 "const0_operand" ""))) | |
3773 | (clobber (match_scratch:FPR 0 "=f,f"))] | |
3ef093a8 AK |
3774 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3775 | "@ | |
f5905b37 AS |
3776 | a<de>br\t%0,%2 |
3777 | a<de>b\t%0,%2" | |
3ef093a8 | 3778 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3779 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3780 | |
f5905b37 AS |
3781 | (define_insn "*add<mode>3_ibm" |
3782 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3783 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3784 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3785 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3786 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3787 | "@ | |
f5905b37 AS |
3788 | a<de>r\t%0,%2 |
3789 | a<de>\t%0,%2" | |
9db1d521 | 3790 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 3791 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
3792 | |
3793 | ||
3794 | ;; | |
3795 | ;;- Subtract instructions. | |
3796 | ;; | |
3797 | ||
1c7b1b7e UW |
3798 | ; |
3799 | ; subti3 instruction pattern(s). | |
3800 | ; | |
3801 | ||
3802 | (define_insn_and_split "subti3" | |
3803 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3804 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3805 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 3806 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
3807 | "TARGET_64BIT" |
3808 | "#" | |
3809 | "&& reload_completed" | |
3810 | [(parallel | |
ae156f85 | 3811 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
3812 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
3813 | (match_dup 7))) | |
3814 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3815 | (parallel | |
3816 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3817 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
3818 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
3819 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
3820 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3821 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3822 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3823 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3824 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3825 | |
9db1d521 HP |
3826 | ; |
3827 | ; subdi3 instruction pattern(s). | |
3828 | ; | |
3829 | ||
07893d4f UW |
3830 | (define_insn "*subdi3_sign" |
3831 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3832 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3833 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
ae156f85 | 3834 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3835 | "TARGET_64BIT" |
3836 | "@ | |
d40c829f UW |
3837 | sgfr\t%0,%2 |
3838 | sgf\t%0,%2" | |
d3632d41 | 3839 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3840 | |
3841 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 3842 | [(set (reg CC_REGNUM) |
07893d4f UW |
3843 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3844 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3845 | (const_int 0))) | |
3846 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3847 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3848 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3849 | "@ | |
d40c829f UW |
3850 | slgfr\t%0,%2 |
3851 | slgf\t%0,%2" | |
d3632d41 | 3852 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3853 | |
3854 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 3855 | [(set (reg CC_REGNUM) |
07893d4f UW |
3856 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3857 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3858 | (const_int 0))) | |
3859 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3860 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3861 | "@ | |
d40c829f UW |
3862 | slgfr\t%0,%2 |
3863 | slgf\t%0,%2" | |
d3632d41 | 3864 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3865 | |
3866 | (define_insn "*subdi3_zero" | |
3867 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3868 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3869 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
ae156f85 | 3870 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3871 | "TARGET_64BIT" |
3872 | "@ | |
d40c829f UW |
3873 | slgfr\t%0,%2 |
3874 | slgf\t%0,%2" | |
d3632d41 | 3875 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3876 | |
b2ba71ca | 3877 | (define_insn "*subdi3_borrow_cc" |
ae156f85 | 3878 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3879 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3880 | (match_operand:DI 2 "general_operand" "d,m")) | |
3881 | (match_dup 1))) | |
3882 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3883 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3884 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3885 | "@ | |
3886 | slgr\t%0,%2 | |
3887 | slg\t%0,%2" | |
3888 | [(set_attr "op_type" "RRE,RXY")]) | |
3889 | ||
3890 | (define_insn "*subdi3_borrow_cconly" | |
ae156f85 | 3891 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3892 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3893 | (match_operand:DI 2 "general_operand" "d,m")) | |
3894 | (match_dup 1))) | |
3895 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3896 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3897 | "@ | |
3898 | slgr\t%0,%2 | |
3899 | slg\t%0,%2" | |
3900 | [(set_attr "op_type" "RRE,RXY")]) | |
3901 | ||
07893d4f | 3902 | (define_insn "*subdi3_cc" |
ae156f85 | 3903 | [(set (reg CC_REGNUM) |
07893d4f UW |
3904 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3905 | (match_operand:DI 2 "general_operand" "d,m")) | |
3906 | (const_int 0))) | |
3907 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3908 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3909 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3910 | "@ |
d40c829f UW |
3911 | slgr\t%0,%2 |
3912 | slg\t%0,%2" | |
d3632d41 | 3913 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3914 | |
5d880bd2 | 3915 | (define_insn "*subdi3_cc2" |
ae156f85 | 3916 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
3917 | (compare (match_operand:DI 1 "register_operand" "0,0") |
3918 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3919 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3920 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3921 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3922 | "@ | |
3923 | slgr\t%0,%2 | |
3924 | slg\t%0,%2" | |
3925 | [(set_attr "op_type" "RRE,RXY")]) | |
3926 | ||
07893d4f | 3927 | (define_insn "*subdi3_cconly" |
ae156f85 | 3928 | [(set (reg CC_REGNUM) |
07893d4f UW |
3929 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3930 | (match_operand:DI 2 "general_operand" "d,m")) | |
3931 | (const_int 0))) | |
3932 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3933 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3934 | "@ |
d40c829f UW |
3935 | slgr\t%0,%2 |
3936 | slg\t%0,%2" | |
d3632d41 | 3937 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3938 | |
5d880bd2 | 3939 | (define_insn "*subdi3_cconly2" |
ae156f85 | 3940 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
3941 | (compare (match_operand:DI 1 "register_operand" "0,0") |
3942 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3943 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3944 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3945 | "@ | |
3946 | slgr\t%0,%2 | |
3947 | slg\t%0,%2" | |
3948 | [(set_attr "op_type" "RRE,RXY")]) | |
3949 | ||
9db1d521 HP |
3950 | (define_insn "*subdi3_64" |
3951 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3952 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3953 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
ae156f85 | 3954 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3955 | "TARGET_64BIT" |
3956 | "@ | |
d40c829f UW |
3957 | sgr\t%0,%2 |
3958 | sg\t%0,%2" | |
077dab3b | 3959 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3960 | |
e69166de UW |
3961 | (define_insn_and_split "*subdi3_31z" |
3962 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3963 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3964 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 3965 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
3966 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
3967 | "#" | |
3968 | "&& reload_completed" | |
3969 | [(parallel | |
ae156f85 | 3970 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
3971 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
3972 | (match_dup 7))) | |
3973 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3974 | (parallel | |
3975 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3976 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
3977 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
3978 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3979 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3980 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3981 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3982 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3983 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3984 | |
07893d4f UW |
3985 | (define_insn_and_split "*subdi3_31" |
3986 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3987 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3988 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 3989 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 3990 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3991 | "#" |
3992 | "&& reload_completed" | |
3993 | [(parallel | |
3994 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 3995 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3996 | (parallel |
ae156f85 | 3997 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
3998 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
3999 | (match_dup 7))) | |
4000 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4001 | (set (pc) | |
ae156f85 | 4002 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4003 | (pc) |
4004 | (label_ref (match_dup 9)))) | |
4005 | (parallel | |
4006 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 4007 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4008 | (match_dup 9)] |
97c6f7ad UW |
4009 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4010 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4011 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4012 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4013 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4014 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4015 | operands[9] = gen_label_rtx ();") |
07893d4f UW |
4016 | |
4017 | (define_expand "subdi3" | |
4018 | [(parallel | |
4019 | [(set (match_operand:DI 0 "register_operand" "") | |
4020 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4021 | (match_operand:DI 2 "general_operand" ""))) | |
ae156f85 | 4022 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4023 | "" |
07893d4f | 4024 | "") |
9db1d521 HP |
4025 | |
4026 | ; | |
4027 | ; subsi3 instruction pattern(s). | |
4028 | ; | |
4029 | ||
07893d4f | 4030 | (define_insn "*subsi3_borrow_cc" |
ae156f85 | 4031 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4032 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4033 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 4034 | (match_dup 1))) |
d3632d41 | 4035 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 4036 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4037 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4038 | "@ |
d40c829f UW |
4039 | slr\t%0,%2 |
4040 | sl\t%0,%2 | |
4041 | sly\t%0,%2" | |
d3632d41 | 4042 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
4043 | |
4044 | (define_insn "*subsi3_borrow_cconly" | |
ae156f85 | 4045 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4046 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4047 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 4048 | (match_dup 1))) |
d3632d41 | 4049 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4050 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4051 | "@ |
d40c829f UW |
4052 | slr\t%0,%2 |
4053 | sl\t%0,%2 | |
4054 | sly\t%0,%2" | |
b2ba71ca | 4055 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 4056 | |
9db1d521 | 4057 | (define_insn "*subsi3_cc" |
ae156f85 | 4058 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4059 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4060 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4061 | (const_int 0))) |
d3632d41 | 4062 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 4063 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4064 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4065 | "@ |
d40c829f UW |
4066 | slr\t%0,%2 |
4067 | sl\t%0,%2 | |
4068 | sly\t%0,%2" | |
d3632d41 | 4069 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4070 | |
5d880bd2 | 4071 | (define_insn "*subsi3_cc2" |
ae156f85 | 4072 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
4073 | (compare (match_operand:SI 1 "register_operand" "0,0,0") |
4074 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4075 | (set (match_operand:SI 0 "register_operand" "=d,d,d") | |
4076 | (minus:SI (match_dup 1) (match_dup 2)))] | |
4077 | "s390_match_ccmode (insn, CCL3mode)" | |
4078 | "@ | |
4079 | slr\t%0,%2 | |
4080 | sl\t%0,%2 | |
4081 | sly\t%0,%2" | |
4082 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4083 | ||
9db1d521 | 4084 | (define_insn "*subsi3_cconly" |
ae156f85 | 4085 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4086 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4087 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4088 | (const_int 0))) |
d3632d41 | 4089 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4090 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4091 | "@ |
d40c829f UW |
4092 | slr\t%0,%2 |
4093 | sl\t%0,%2 | |
4094 | sly\t%0,%2" | |
d3632d41 | 4095 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4096 | |
5d880bd2 | 4097 | (define_insn "*subsi3_cconly2" |
ae156f85 | 4098 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
4099 | (compare (match_operand:SI 1 "register_operand" "0,0,0") |
4100 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4101 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
4102 | "s390_match_ccmode (insn, CCL3mode)" | |
4103 | "@ | |
4104 | slr\t%0,%2 | |
4105 | sl\t%0,%2 | |
4106 | sly\t%0,%2" | |
4107 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4108 | ||
07893d4f | 4109 | (define_insn "*subsi3_sign" |
d3632d41 UW |
4110 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4111 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4112 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
ae156f85 | 4113 | (clobber (reg:CC CC_REGNUM))] |
07893d4f | 4114 | "" |
d3632d41 | 4115 | "@ |
d40c829f UW |
4116 | sh\t%0,%2 |
4117 | shy\t%0,%2" | |
d3632d41 | 4118 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 4119 | |
9db1d521 | 4120 | (define_insn "subsi3" |
d3632d41 UW |
4121 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4122 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
4123 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
ae156f85 | 4124 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
4125 | "" |
4126 | "@ | |
d40c829f UW |
4127 | sr\t%0,%2 |
4128 | s\t%0,%2 | |
4129 | sy\t%0,%2" | |
d3632d41 | 4130 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4131 | |
9db1d521 HP |
4132 | |
4133 | ; | |
f5905b37 | 4134 | ; sub(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4135 | ; |
4136 | ||
f5905b37 | 4137 | (define_expand "sub<mode>3" |
9db1d521 | 4138 | [(parallel |
f5905b37 AS |
4139 | [(set (match_operand:FPR 0 "register_operand" "=f,f") |
4140 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4141 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 4142 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
4143 | "TARGET_HARD_FLOAT" |
4144 | "") | |
4145 | ||
f5905b37 AS |
4146 | (define_insn "*sub<mode>3" |
4147 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4148 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4149 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 4150 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
4151 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4152 | "@ | |
f5905b37 AS |
4153 | s<de>br\t%0,%2 |
4154 | s<de>b\t%0,%2" | |
ce50cae8 | 4155 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4156 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4157 | |
f5905b37 | 4158 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4159 | [(set (reg CC_REGNUM) |
f5905b37 AS |
4160 | (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") |
4161 | (match_operand:FPR 2 "general_operand" "f,R")) | |
4162 | (match_operand:FPR 3 "const0_operand" ""))) | |
4163 | (set (match_operand:FPR 0 "register_operand" "=f,f") | |
4164 | (minus:FPR (match_dup 1) (match_dup 2)))] | |
3ef093a8 AK |
4165 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4166 | "@ | |
f5905b37 AS |
4167 | s<de>br\t%0,%2 |
4168 | s<de>b\t%0,%2" | |
3ef093a8 | 4169 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4170 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4171 | |
f5905b37 | 4172 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 4173 | [(set (reg CC_REGNUM) |
f5905b37 AS |
4174 | (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") |
4175 | (match_operand:FPR 2 "general_operand" "f,R")) | |
4176 | (match_operand:FPR 3 "const0_operand" ""))) | |
4177 | (clobber (match_scratch:FPR 0 "=f,f"))] | |
3ef093a8 AK |
4178 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4179 | "@ | |
f5905b37 AS |
4180 | s<de>br\t%0,%2 |
4181 | s<de>b\t%0,%2" | |
3ef093a8 | 4182 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4183 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4184 | |
f5905b37 AS |
4185 | (define_insn "*sub<mode>3_ibm" |
4186 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4187 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4188 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 4189 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
4190 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4191 | "@ | |
f5905b37 AS |
4192 | s<de>r\t%0,%2 |
4193 | s<de>\t%0,%2" | |
9db1d521 | 4194 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 4195 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
4196 | |
4197 | ||
e69166de UW |
4198 | ;; |
4199 | ;;- Conditional add/subtract instructions. | |
4200 | ;; | |
4201 | ||
4202 | ; | |
9a91a21f | 4203 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
4204 | ; |
4205 | ||
9a91a21f | 4206 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 4207 | [(set (reg CC_REGNUM) |
e69166de | 4208 | (compare |
9a91a21f AS |
4209 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") |
4210 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4211 | (match_operand:GPR 3 "s390_alc_comparison" "")) | |
e69166de | 4212 | (const_int 0))) |
9a91a21f AS |
4213 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
4214 | (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4215 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4216 | "@ |
9a91a21f AS |
4217 | alc<g>r\t%0,%2 |
4218 | alc<g>\t%0,%2" | |
e69166de UW |
4219 | [(set_attr "op_type" "RRE,RXY")]) |
4220 | ||
9a91a21f AS |
4221 | (define_insn "*add<mode>3_alc" |
4222 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
4223 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") | |
4224 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4225 | (match_operand:GPR 3 "s390_alc_comparison" ""))) | |
ae156f85 | 4226 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 4227 | "TARGET_CPU_ZARCH" |
e69166de | 4228 | "@ |
9a91a21f AS |
4229 | alc<g>r\t%0,%2 |
4230 | alc<g>\t%0,%2" | |
e69166de UW |
4231 | [(set_attr "op_type" "RRE,RXY")]) |
4232 | ||
9a91a21f | 4233 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 4234 | [(set (reg CC_REGNUM) |
e69166de | 4235 | (compare |
9a91a21f AS |
4236 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
4237 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4238 | (match_operand:GPR 3 "s390_slb_comparison" "")) | |
e69166de | 4239 | (const_int 0))) |
9a91a21f AS |
4240 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
4241 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4242 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4243 | "@ |
9a91a21f AS |
4244 | slb<g>r\t%0,%2 |
4245 | slb<g>\t%0,%2" | |
e69166de UW |
4246 | [(set_attr "op_type" "RRE,RXY")]) |
4247 | ||
9a91a21f AS |
4248 | (define_insn "*sub<mode>3_slb" |
4249 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
4250 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
4251 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4252 | (match_operand:GPR 3 "s390_slb_comparison" ""))) | |
ae156f85 | 4253 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 4254 | "TARGET_CPU_ZARCH" |
e69166de | 4255 | "@ |
9a91a21f AS |
4256 | slb<g>r\t%0,%2 |
4257 | slb<g>\t%0,%2" | |
e69166de UW |
4258 | [(set_attr "op_type" "RRE,RXY")]) |
4259 | ||
9a91a21f AS |
4260 | (define_expand "add<mode>cc" |
4261 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 4262 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
4263 | (match_operand:GPR 2 "register_operand" "") |
4264 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 UW |
4265 | "TARGET_CPU_ZARCH" |
4266 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4267 | s390_compare_op0, s390_compare_op1, | |
4268 | operands[0], operands[2], | |
4269 | operands[3])) FAIL; DONE;") | |
4270 | ||
4271 | ; | |
4272 | ; scond instruction pattern(s). | |
4273 | ; | |
4274 | ||
9a91a21f AS |
4275 | (define_insn_and_split "*scond<mode>" |
4276 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
4277 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 4278 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
4279 | "TARGET_CPU_ZARCH" |
4280 | "#" | |
4281 | "&& reload_completed" | |
4282 | [(set (match_dup 0) (const_int 0)) | |
4283 | (parallel | |
9a91a21f | 4284 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0)) |
5d880bd2 | 4285 | (match_dup 1))) |
ae156f85 | 4286 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4287 | "") |
5d880bd2 | 4288 | |
9a91a21f AS |
4289 | (define_insn_and_split "*scond<mode>_neg" |
4290 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
4291 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 4292 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
4293 | "TARGET_CPU_ZARCH" |
4294 | "#" | |
4295 | "&& reload_completed" | |
4296 | [(set (match_dup 0) (const_int 0)) | |
4297 | (parallel | |
9a91a21f AS |
4298 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
4299 | (match_dup 1))) | |
ae156f85 | 4300 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 4301 | (parallel |
9a91a21f | 4302 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 4303 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4304 | "") |
5d880bd2 | 4305 | |
5d880bd2 | 4306 | |
9a91a21f AS |
4307 | (define_expand "s<code>" |
4308 | [(set (match_operand:SI 0 "register_operand" "") | |
4309 | (SCOND (match_dup 0) | |
4310 | (match_dup 0)))] | |
5d880bd2 | 4311 | "TARGET_CPU_ZARCH" |
9a91a21f | 4312 | "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1, |
5d880bd2 UW |
4313 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
4314 | ||
69950452 AS |
4315 | (define_expand "seq" |
4316 | [(parallel | |
4317 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4318 | (match_dup 1)) | |
4319 | (clobber (reg:CC CC_REGNUM))]) | |
4320 | (parallel | |
4321 | [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) | |
4322 | (clobber (reg:CC CC_REGNUM))])] | |
4323 | "" | |
4324 | { | |
4325 | if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) | |
4326 | FAIL; | |
4327 | operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); | |
4328 | PUT_MODE (operands[1], SImode); | |
4329 | }) | |
4330 | ||
4331 | (define_insn_and_split "*sne" | |
4332 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4333 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") | |
4334 | (const_int 0))) | |
4335 | (clobber (reg:CC CC_REGNUM))] | |
4336 | "" | |
4337 | "#" | |
4338 | "reload_completed" | |
4339 | [(parallel | |
4340 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
4341 | (clobber (reg:CC CC_REGNUM))])]) | |
4342 | ||
e69166de | 4343 | |
9db1d521 HP |
4344 | ;; |
4345 | ;;- Multiply instructions. | |
4346 | ;; | |
4347 | ||
4023fb28 UW |
4348 | ; |
4349 | ; muldi3 instruction pattern(s). | |
4350 | ; | |
9db1d521 | 4351 | |
07893d4f UW |
4352 | (define_insn "*muldi3_sign" |
4353 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4354 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4355 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4356 | "TARGET_64BIT" | |
4357 | "@ | |
d40c829f UW |
4358 | msgfr\t%0,%2 |
4359 | msgf\t%0,%2" | |
d3632d41 | 4360 | [(set_attr "op_type" "RRE,RXY") |
ed0e512a | 4361 | (set_attr "type" "imuldi")]) |
07893d4f | 4362 | |
4023fb28 | 4363 | (define_insn "muldi3" |
9db1d521 | 4364 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4365 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4366 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4367 | "TARGET_64BIT" |
4368 | "@ | |
d40c829f UW |
4369 | msgr\t%0,%2 |
4370 | mghi\t%0,%h2 | |
4371 | msg\t%0,%2" | |
d3632d41 | 4372 | [(set_attr "op_type" "RRE,RI,RXY") |
ed0e512a | 4373 | (set_attr "type" "imuldi")]) |
f2d3c02a | 4374 | |
9db1d521 HP |
4375 | ; |
4376 | ; mulsi3 instruction pattern(s). | |
4377 | ; | |
4378 | ||
f1e77d83 UW |
4379 | (define_insn "*mulsi3_sign" |
4380 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4381 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4382 | (match_operand:SI 1 "register_operand" "0")))] | |
4383 | "" | |
4384 | "mh\t%0,%2" | |
4385 | [(set_attr "op_type" "RX") | |
ed0e512a | 4386 | (set_attr "type" "imulhi")]) |
f1e77d83 | 4387 | |
9db1d521 | 4388 | (define_insn "mulsi3" |
d3632d41 UW |
4389 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4390 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4391 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4392 | "" |
4393 | "@ | |
d40c829f UW |
4394 | msr\t%0,%2 |
4395 | mhi\t%0,%h2 | |
4396 | ms\t%0,%2 | |
4397 | msy\t%0,%2" | |
d3632d41 | 4398 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
ed0e512a | 4399 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi")]) |
9db1d521 | 4400 | |
4023fb28 UW |
4401 | ; |
4402 | ; mulsidi3 instruction pattern(s). | |
4403 | ; | |
4404 | ||
f1e77d83 UW |
4405 | (define_insn "mulsidi3" |
4406 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4407 | (mult:DI (sign_extend:DI | |
4408 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4409 | (sign_extend:DI | |
4410 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4411 | "!TARGET_64BIT" |
f1e77d83 UW |
4412 | "@ |
4413 | mr\t%0,%2 | |
4414 | m\t%0,%2" | |
4415 | [(set_attr "op_type" "RR,RX") | |
ed0e512a | 4416 | (set_attr "type" "imulsi")]) |
4023fb28 | 4417 | |
f1e77d83 UW |
4418 | ; |
4419 | ; umulsidi3 instruction pattern(s). | |
4420 | ; | |
c7453384 | 4421 | |
f1e77d83 UW |
4422 | (define_insn "umulsidi3" |
4423 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4424 | (mult:DI (zero_extend:DI | |
4425 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4426 | (zero_extend:DI | |
4427 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4428 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4429 | "@ | |
4430 | mlr\t%0,%2 | |
4431 | ml\t%0,%2" | |
4432 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 4433 | (set_attr "type" "imulsi")]) |
c7453384 | 4434 | |
9db1d521 | 4435 | ; |
f5905b37 | 4436 | ; mul(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4437 | ; |
4438 | ||
f5905b37 AS |
4439 | (define_expand "mul<mode>3" |
4440 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4441 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4442 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4443 | "TARGET_HARD_FLOAT" |
4444 | "") | |
4445 | ||
f5905b37 AS |
4446 | (define_insn "*mul<mode>3" |
4447 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4448 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4449 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4450 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4451 | "@ | |
f5905b37 AS |
4452 | m<dee>br\t%0,%2 |
4453 | m<dee>b\t%0,%2" | |
ce50cae8 | 4454 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4455 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 4456 | |
f5905b37 AS |
4457 | (define_insn "*mul<mode>3_ibm" |
4458 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4459 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4460 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4461 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4462 | "@ | |
f5905b37 AS |
4463 | m<de>r\t%0,%2 |
4464 | m<de>\t%0,%2" | |
9db1d521 | 4465 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 4466 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 4467 | |
f5905b37 AS |
4468 | (define_insn "*fmadd<mode>" |
4469 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4470 | (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f") | |
4471 | (match_operand:FPR 2 "nonimmediate_operand" "f,R")) | |
4472 | (match_operand:FPR 3 "register_operand" "0,0")))] | |
f2d226e1 | 4473 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 4474 | "@ |
f5905b37 AS |
4475 | ma<de>br\t%0,%1,%2 |
4476 | ma<de>b\t%0,%1,%2" | |
a1b892b5 | 4477 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4478 | (set_attr "type" "fmul<mode>")]) |
a1b892b5 | 4479 | |
f5905b37 AS |
4480 | (define_insn "*fmsub<mode>" |
4481 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4482 | (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f") | |
4483 | (match_operand:FPR 2 "nonimmediate_operand" "f,R")) | |
4484 | (match_operand:FPR 3 "register_operand" "0,0")))] | |
f2d226e1 | 4485 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 4486 | "@ |
f5905b37 AS |
4487 | ms<de>br\t%0,%1,%2 |
4488 | ms<de>b\t%0,%1,%2" | |
ce50cae8 | 4489 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4490 | (set_attr "type" "fmul<mode>")]) |
9db1d521 HP |
4491 | |
4492 | ;; | |
4493 | ;;- Divide and modulo instructions. | |
4494 | ;; | |
4495 | ||
4496 | ; | |
4023fb28 | 4497 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4498 | ; |
4499 | ||
4023fb28 UW |
4500 | (define_expand "divmoddi4" |
4501 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4502 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4503 | (match_operand:DI 2 "general_operand" ""))) |
4504 | (set (match_operand:DI 3 "general_operand" "") | |
4505 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4506 | (clobber (match_dup 4))] | |
9db1d521 | 4507 | "TARGET_64BIT" |
9db1d521 | 4508 | { |
f1e77d83 | 4509 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4510 | |
4511 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4512 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4513 | |
4514 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4515 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4516 | |
4517 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4518 | REG_NOTES (insn) = | |
4519 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4520 | ||
4521 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4522 | REG_NOTES (insn) = | |
4523 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4524 | |
9db1d521 | 4525 | DONE; |
10bbf137 | 4526 | }) |
9db1d521 HP |
4527 | |
4528 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4529 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4530 | (ior:TI | |
4023fb28 UW |
4531 | (ashift:TI |
4532 | (zero_extend:TI | |
5665e398 UW |
4533 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4534 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4535 | (const_int 64)) | |
4536 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4537 | "TARGET_64BIT" |
4538 | "@ | |
d40c829f UW |
4539 | dsgr\t%0,%2 |
4540 | dsg\t%0,%2" | |
d3632d41 | 4541 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4542 | (set_attr "type" "idiv")]) |
9db1d521 | 4543 | |
4023fb28 UW |
4544 | (define_insn "divmodtisi3" |
4545 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4546 | (ior:TI | |
4023fb28 UW |
4547 | (ashift:TI |
4548 | (zero_extend:TI | |
5665e398 | 4549 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 4550 | (sign_extend:DI |
5665e398 UW |
4551 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4552 | (const_int 64)) | |
4553 | (zero_extend:TI | |
4554 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4555 | "TARGET_64BIT" |
4023fb28 | 4556 | "@ |
d40c829f UW |
4557 | dsgfr\t%0,%2 |
4558 | dsgf\t%0,%2" | |
d3632d41 | 4559 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4560 | (set_attr "type" "idiv")]) |
9db1d521 | 4561 | |
4023fb28 UW |
4562 | ; |
4563 | ; udivmoddi4 instruction pattern(s). | |
4564 | ; | |
9db1d521 | 4565 | |
4023fb28 UW |
4566 | (define_expand "udivmoddi4" |
4567 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4568 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4569 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4570 | (set (match_operand:DI 3 "general_operand" "") | |
4571 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4572 | (clobber (match_dup 4))] | |
9db1d521 | 4573 | "TARGET_64BIT" |
9db1d521 | 4574 | { |
4023fb28 UW |
4575 | rtx insn, div_equal, mod_equal, equal; |
4576 | ||
4577 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4578 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4579 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4580 | gen_rtx_ASHIFT (TImode, |
4581 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4582 | GEN_INT (64)), |
4583 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4584 | |
4585 | operands[4] = gen_reg_rtx(TImode); | |
4586 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4587 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4588 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4589 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4590 | REG_NOTES (insn) = | |
4591 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4592 | ||
4593 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4594 | REG_NOTES (insn) = | |
4595 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4596 | ||
4597 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4598 | REG_NOTES (insn) = | |
4599 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4600 | |
9db1d521 | 4601 | DONE; |
10bbf137 | 4602 | }) |
9db1d521 HP |
4603 | |
4604 | (define_insn "udivmodtidi3" | |
4023fb28 | 4605 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 4606 | (ior:TI |
5665e398 UW |
4607 | (ashift:TI |
4608 | (zero_extend:TI | |
4609 | (truncate:DI | |
2f7e5a0d EC |
4610 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
4611 | (zero_extend:TI | |
5665e398 UW |
4612 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
4613 | (const_int 64)) | |
4614 | (zero_extend:TI | |
4615 | (truncate:DI | |
4616 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4617 | "TARGET_64BIT" |
4618 | "@ | |
d40c829f UW |
4619 | dlgr\t%0,%2 |
4620 | dlg\t%0,%2" | |
d3632d41 | 4621 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4622 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4623 | |
4624 | ; | |
4023fb28 | 4625 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4626 | ; |
4627 | ||
4023fb28 UW |
4628 | (define_expand "divmodsi4" |
4629 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4630 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4631 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4632 | (set (match_operand:SI 3 "general_operand" "") | |
4633 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4634 | (clobber (match_dup 4))] | |
9db1d521 | 4635 | "!TARGET_64BIT" |
9db1d521 | 4636 | { |
4023fb28 UW |
4637 | rtx insn, div_equal, mod_equal, equal; |
4638 | ||
4639 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4640 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4641 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4642 | gen_rtx_ASHIFT (DImode, |
4643 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4644 | GEN_INT (32)), |
4645 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4646 | |
4647 | operands[4] = gen_reg_rtx(DImode); | |
4648 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4649 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4650 | REG_NOTES (insn) = | |
4651 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4652 | ||
4653 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4654 | REG_NOTES (insn) = | |
4655 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4656 | ||
4657 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4658 | REG_NOTES (insn) = | |
4659 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4660 | |
9db1d521 | 4661 | DONE; |
10bbf137 | 4662 | }) |
9db1d521 HP |
4663 | |
4664 | (define_insn "divmoddisi3" | |
4023fb28 | 4665 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 4666 | (ior:DI |
5665e398 UW |
4667 | (ashift:DI |
4668 | (zero_extend:DI | |
4669 | (truncate:SI | |
2f7e5a0d EC |
4670 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4671 | (sign_extend:DI | |
5665e398 UW |
4672 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4673 | (const_int 32)) | |
4674 | (zero_extend:DI | |
4675 | (truncate:SI | |
4676 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4677 | "!TARGET_64BIT" |
4678 | "@ | |
d40c829f UW |
4679 | dr\t%0,%2 |
4680 | d\t%0,%2" | |
9db1d521 | 4681 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4682 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4683 | |
4684 | ; | |
4685 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4686 | ; | |
4687 | ||
f1e77d83 UW |
4688 | (define_expand "udivmodsi4" |
4689 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4690 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4691 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4692 | (set (match_operand:SI 3 "general_operand" "") | |
4693 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4694 | (clobber (match_dup 4))] | |
4695 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4696 | { | |
4697 | rtx insn, div_equal, mod_equal, equal; | |
4698 | ||
4699 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4700 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4701 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4702 | gen_rtx_ASHIFT (DImode, |
4703 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4704 | GEN_INT (32)), |
4705 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4706 | |
4707 | operands[4] = gen_reg_rtx(DImode); | |
4708 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4709 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4710 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4711 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4712 | REG_NOTES (insn) = | |
4713 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4714 | ||
4715 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4716 | REG_NOTES (insn) = | |
4717 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4718 | ||
4719 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4720 | REG_NOTES (insn) = | |
4721 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4722 | ||
4723 | DONE; | |
4724 | }) | |
4725 | ||
4726 | (define_insn "udivmoddisi3" | |
4727 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 4728 | (ior:DI |
5665e398 UW |
4729 | (ashift:DI |
4730 | (zero_extend:DI | |
4731 | (truncate:SI | |
2f7e5a0d EC |
4732 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
4733 | (zero_extend:DI | |
5665e398 UW |
4734 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
4735 | (const_int 32)) | |
4736 | (zero_extend:DI | |
4737 | (truncate:SI | |
4738 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4739 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4740 | "@ | |
4741 | dlr\t%0,%2 | |
4742 | dl\t%0,%2" | |
4743 | [(set_attr "op_type" "RRE,RXY") | |
4744 | (set_attr "type" "idiv")]) | |
4023fb28 | 4745 | |
9db1d521 HP |
4746 | (define_expand "udivsi3" |
4747 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4748 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4749 | (match_operand:SI 2 "general_operand" ""))) |
4750 | (clobber (match_dup 3))] | |
f1e77d83 | 4751 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4752 | { |
4023fb28 UW |
4753 | rtx insn, udiv_equal, umod_equal, equal; |
4754 | ||
4755 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4756 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4757 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4758 | gen_rtx_ASHIFT (DImode, |
4759 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4760 | GEN_INT (32)), |
4761 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4762 | |
4023fb28 | 4763 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4764 | |
4765 | if (CONSTANT_P (operands[2])) | |
4766 | { | |
4767 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4768 | { | |
4769 | rtx label1 = gen_label_rtx (); | |
4770 | ||
4023fb28 UW |
4771 | operands[1] = make_safe_from (operands[1], operands[0]); |
4772 | emit_move_insn (operands[0], const0_rtx); | |
4773 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4774 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4775 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4776 | emit_label (label1); |
4777 | } | |
4778 | else | |
4779 | { | |
c7453384 EC |
4780 | operands[2] = force_reg (SImode, operands[2]); |
4781 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4782 | |
4783 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4784 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4785 | operands[2])); | |
4786 | REG_NOTES (insn) = | |
4787 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4788 | |
4789 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4790 | gen_lowpart (SImode, operands[3])); |
4791 | REG_NOTES (insn) = | |
c7453384 | 4792 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4793 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4794 | } |
4795 | } | |
4796 | else | |
c7453384 | 4797 | { |
9db1d521 HP |
4798 | rtx label1 = gen_label_rtx (); |
4799 | rtx label2 = gen_label_rtx (); | |
4800 | rtx label3 = gen_label_rtx (); | |
4801 | ||
c7453384 EC |
4802 | operands[1] = force_reg (SImode, operands[1]); |
4803 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4804 | operands[2] = force_reg (SImode, operands[2]); | |
4805 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4806 | |
4807 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4808 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4809 | emit_jump_insn (gen_bgtu (label3)); | |
220a826e | 4810 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4811 | emit_jump_insn (gen_blt (label2)); |
4812 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4813 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4814 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4815 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4816 | operands[2])); | |
4817 | REG_NOTES (insn) = | |
4818 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4819 | |
4820 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4821 | gen_lowpart (SImode, operands[3])); |
4822 | REG_NOTES (insn) = | |
c7453384 | 4823 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4824 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4825 | emit_jump (label3); |
9db1d521 | 4826 | emit_label (label1); |
4023fb28 | 4827 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4828 | emit_jump (label3); |
9db1d521 | 4829 | emit_label (label2); |
4023fb28 | 4830 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4831 | emit_label (label3); |
4832 | } | |
c7453384 | 4833 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4834 | DONE; |
10bbf137 | 4835 | }) |
9db1d521 HP |
4836 | |
4837 | (define_expand "umodsi3" | |
4838 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4839 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4840 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4841 | (clobber (match_dup 3))] | |
f1e77d83 | 4842 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4843 | { |
4023fb28 UW |
4844 | rtx insn, udiv_equal, umod_equal, equal; |
4845 | ||
4846 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4847 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4848 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4849 | gen_rtx_ASHIFT (DImode, |
4850 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4851 | GEN_INT (32)), |
4852 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4853 | |
4023fb28 | 4854 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4855 | |
4856 | if (CONSTANT_P (operands[2])) | |
4857 | { | |
4858 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4859 | { | |
4860 | rtx label1 = gen_label_rtx (); | |
4861 | ||
4023fb28 UW |
4862 | operands[1] = make_safe_from (operands[1], operands[0]); |
4863 | emit_move_insn (operands[0], operands[1]); | |
4864 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 4865 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
4866 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4867 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
4868 | emit_label (label1); |
4869 | } | |
4870 | else | |
4871 | { | |
c7453384 EC |
4872 | operands[2] = force_reg (SImode, operands[2]); |
4873 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4874 | |
4875 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4876 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4877 | operands[2])); | |
4878 | REG_NOTES (insn) = | |
4879 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4880 | |
4881 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4882 | gen_highpart (SImode, operands[3])); |
4883 | REG_NOTES (insn) = | |
c7453384 | 4884 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4885 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
4886 | } |
4887 | } | |
4888 | else | |
4889 | { | |
4890 | rtx label1 = gen_label_rtx (); | |
4891 | rtx label2 = gen_label_rtx (); | |
4892 | rtx label3 = gen_label_rtx (); | |
4893 | ||
c7453384 EC |
4894 | operands[1] = force_reg (SImode, operands[1]); |
4895 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4896 | operands[2] = force_reg (SImode, operands[2]); | |
4897 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 4898 | |
c7453384 | 4899 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 4900 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 | 4901 | emit_jump_insn (gen_bgtu (label3)); |
220a826e | 4902 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4903 | emit_jump_insn (gen_blt (label2)); |
4904 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4905 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4906 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4907 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4908 | operands[2])); | |
4909 | REG_NOTES (insn) = | |
4910 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4911 | |
4912 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4913 | gen_highpart (SImode, operands[3])); |
4914 | REG_NOTES (insn) = | |
c7453384 | 4915 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4916 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 4917 | emit_jump (label3); |
9db1d521 | 4918 | emit_label (label1); |
4023fb28 | 4919 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 4920 | emit_jump (label3); |
9db1d521 | 4921 | emit_label (label2); |
4023fb28 | 4922 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
4923 | emit_label (label3); |
4924 | } | |
9db1d521 | 4925 | DONE; |
10bbf137 | 4926 | }) |
9db1d521 HP |
4927 | |
4928 | ; | |
f5905b37 | 4929 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4930 | ; |
4931 | ||
f5905b37 AS |
4932 | (define_expand "div<mode>3" |
4933 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4934 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4935 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4936 | "TARGET_HARD_FLOAT" |
4937 | "") | |
4938 | ||
f5905b37 AS |
4939 | (define_insn "*div<mode>3" |
4940 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4941 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4942 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4943 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4944 | "@ | |
f5905b37 AS |
4945 | d<de>br\t%0,%2 |
4946 | d<de>b\t%0,%2" | |
ce50cae8 | 4947 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4948 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 4949 | |
f5905b37 AS |
4950 | (define_insn "*div<mode>3_ibm" |
4951 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4952 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4953 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4954 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4955 | "@ | |
f5905b37 AS |
4956 | d<de>r\t%0,%2 |
4957 | d<de>\t%0,%2" | |
9db1d521 | 4958 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 4959 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 HP |
4960 | |
4961 | ||
4962 | ;; | |
4963 | ;;- And instructions. | |
4964 | ;; | |
4965 | ||
047d35ed AS |
4966 | (define_expand "and<mode>3" |
4967 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
4968 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
4969 | (match_operand:INT 2 "general_operand" ""))) | |
4970 | (clobber (reg:CC CC_REGNUM))] | |
4971 | "" | |
4972 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
4973 | ||
9db1d521 HP |
4974 | ; |
4975 | ; anddi3 instruction pattern(s). | |
4976 | ; | |
4977 | ||
4978 | (define_insn "*anddi3_cc" | |
ae156f85 | 4979 | [(set (reg CC_REGNUM) |
96fd3851 | 4980 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4981 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 4982 | (const_int 0))) |
4023fb28 | 4983 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
4984 | (and:DI (match_dup 1) (match_dup 2)))] |
4985 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4986 | "@ | |
d40c829f UW |
4987 | ngr\t%0,%2 |
4988 | ng\t%0,%2" | |
d3632d41 | 4989 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
4990 | |
4991 | (define_insn "*anddi3_cconly" | |
ae156f85 | 4992 | [(set (reg CC_REGNUM) |
96fd3851 | 4993 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4994 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
4995 | (const_int 0))) |
4996 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
4997 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
4998 | /* Do not steal TM patterns. */ | |
4999 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 5000 | "@ |
d40c829f UW |
5001 | ngr\t%0,%2 |
5002 | ng\t%0,%2" | |
d3632d41 | 5003 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 5004 | |
ec24698e UW |
5005 | (define_insn "*anddi3_extimm" |
5006 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") | |
5007 | (and:DI (match_operand:DI 1 "nonimmediate_operand" | |
5008 | "%d,o,0,0,0,0,0,0,0,0,0,0") | |
5009 | (match_operand:DI 2 "general_operand" | |
5010 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q"))) | |
5011 | (clobber (reg:CC CC_REGNUM))] | |
5012 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
5013 | "@ | |
5014 | # | |
5015 | # | |
5016 | nihh\t%0,%j2 | |
5017 | nihl\t%0,%j2 | |
5018 | nilh\t%0,%j2 | |
5019 | nill\t%0,%j2 | |
5020 | nihf\t%0,%m2 | |
5021 | nilf\t%0,%m2 | |
5022 | ngr\t%0,%2 | |
5023 | ng\t%0,%2 | |
5024 | # | |
5025 | #" | |
5026 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")]) | |
5027 | ||
8cb66696 | 5028 | (define_insn "*anddi3" |
0dfa6c5e | 5029 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
8cb66696 | 5030 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
0dfa6c5e | 5031 | "%d,o,0,0,0,0,0,0,0,0") |
8cb66696 | 5032 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5033 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) |
ae156f85 | 5034 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 5035 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
8cb66696 UW |
5036 | "@ |
5037 | # | |
5038 | # | |
5039 | nihh\t%0,%j2 | |
5040 | nihl\t%0,%j2 | |
5041 | nilh\t%0,%j2 | |
5042 | nill\t%0,%j2 | |
5043 | ngr\t%0,%2 | |
5044 | ng\t%0,%2 | |
0dfa6c5e | 5045 | # |
19b63d8e | 5046 | #" |
0dfa6c5e UW |
5047 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5048 | ||
5049 | (define_split | |
5050 | [(set (match_operand:DI 0 "s_operand" "") | |
5051 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5052 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5053 | "reload_completed" |
5054 | [(parallel | |
5055 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5056 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5057 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5058 | |
9db1d521 HP |
5059 | |
5060 | ; | |
5061 | ; andsi3 instruction pattern(s). | |
5062 | ; | |
5063 | ||
5064 | (define_insn "*andsi3_cc" | |
ae156f85 | 5065 | [(set (reg CC_REGNUM) |
ec24698e UW |
5066 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5067 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5068 | (const_int 0))) |
ec24698e | 5069 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
9db1d521 HP |
5070 | (and:SI (match_dup 1) (match_dup 2)))] |
5071 | "s390_match_ccmode(insn, CCTmode)" | |
5072 | "@ | |
ec24698e | 5073 | nilf\t%0,%o2 |
d40c829f UW |
5074 | nr\t%0,%2 |
5075 | n\t%0,%2 | |
5076 | ny\t%0,%2" | |
ec24698e | 5077 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 HP |
5078 | |
5079 | (define_insn "*andsi3_cconly" | |
ae156f85 | 5080 | [(set (reg CC_REGNUM) |
ec24698e UW |
5081 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5082 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5083 | (const_int 0))) |
ec24698e | 5084 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
68f9c5e2 UW |
5085 | "s390_match_ccmode(insn, CCTmode) |
5086 | /* Do not steal TM patterns. */ | |
5087 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 5088 | "@ |
ec24698e | 5089 | nilf\t%0,%o2 |
d40c829f UW |
5090 | nr\t%0,%2 |
5091 | n\t%0,%2 | |
5092 | ny\t%0,%2" | |
ec24698e | 5093 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 | 5094 | |
f19a9af7 | 5095 | (define_insn "*andsi3_zarch" |
ec24698e | 5096 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
0dfa6c5e | 5097 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
ec24698e | 5098 | "%d,o,0,0,0,0,0,0,0,0") |
0dfa6c5e | 5099 | (match_operand:SI 2 "general_operand" |
ec24698e | 5100 | "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q"))) |
ae156f85 | 5101 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5102 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5103 | "@ |
f19a9af7 AK |
5104 | # |
5105 | # | |
5106 | nilh\t%0,%j2 | |
2f7e5a0d | 5107 | nill\t%0,%j2 |
ec24698e | 5108 | nilf\t%0,%o2 |
d40c829f UW |
5109 | nr\t%0,%2 |
5110 | n\t%0,%2 | |
8cb66696 | 5111 | ny\t%0,%2 |
0dfa6c5e | 5112 | # |
19b63d8e | 5113 | #" |
ec24698e | 5114 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")]) |
f19a9af7 AK |
5115 | |
5116 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
5117 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5118 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5119 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
ae156f85 | 5120 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5121 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5122 | "@ |
5123 | nr\t%0,%2 | |
8cb66696 | 5124 | n\t%0,%2 |
0dfa6c5e | 5125 | # |
19b63d8e | 5126 | #" |
0dfa6c5e UW |
5127 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5128 | ||
5129 | (define_split | |
5130 | [(set (match_operand:SI 0 "s_operand" "") | |
5131 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5132 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5133 | "reload_completed" |
5134 | [(parallel | |
5135 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5136 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5137 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5138 | |
9db1d521 HP |
5139 | ; |
5140 | ; andhi3 instruction pattern(s). | |
5141 | ; | |
5142 | ||
8cb66696 | 5143 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
5144 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5145 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5146 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
ae156f85 | 5147 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5148 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5149 | "@ |
d40c829f | 5150 | nr\t%0,%2 |
8cb66696 | 5151 | nill\t%0,%x2 |
0dfa6c5e | 5152 | # |
19b63d8e | 5153 | #" |
0dfa6c5e | 5154 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5155 | |
5156 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
5157 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5158 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5159 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 5160 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5161 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5162 | "@ | |
5163 | nr\t%0,%2 | |
0dfa6c5e | 5164 | # |
19b63d8e | 5165 | #" |
0dfa6c5e UW |
5166 | [(set_attr "op_type" "RR,SI,SS")]) |
5167 | ||
5168 | (define_split | |
5169 | [(set (match_operand:HI 0 "s_operand" "") | |
5170 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5171 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5172 | "reload_completed" |
5173 | [(parallel | |
5174 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5175 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5176 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 5177 | |
9db1d521 HP |
5178 | ; |
5179 | ; andqi3 instruction pattern(s). | |
5180 | ; | |
5181 | ||
8cb66696 UW |
5182 | (define_insn "*andqi3_zarch" |
5183 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5184 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5185 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5186 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5187 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5188 | "@ |
d40c829f | 5189 | nr\t%0,%2 |
8cb66696 | 5190 | nill\t%0,%b2 |
fc0ea003 UW |
5191 | ni\t%S0,%b2 |
5192 | niy\t%S0,%b2 | |
19b63d8e | 5193 | #" |
8cb66696 UW |
5194 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5195 | ||
5196 | (define_insn "*andqi3_esa" | |
5197 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5198 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5199 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5200 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5201 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5202 | "@ |
8cb66696 | 5203 | nr\t%0,%2 |
fc0ea003 | 5204 | ni\t%S0,%b2 |
19b63d8e | 5205 | #" |
8cb66696 | 5206 | [(set_attr "op_type" "RR,SI,SS")]) |
4023fb28 | 5207 | |
19b63d8e UW |
5208 | ; |
5209 | ; Block and (NC) patterns. | |
5210 | ; | |
5211 | ||
5212 | (define_insn "*nc" | |
5213 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5214 | (and:BLK (match_dup 0) | |
5215 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5216 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5217 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5218 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5219 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 5220 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5221 | |
5222 | (define_split | |
5223 | [(set (match_operand 0 "memory_operand" "") | |
5224 | (and (match_dup 0) | |
5225 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5226 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5227 | "reload_completed |
5228 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5229 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5230 | [(parallel | |
5231 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
5232 | (use (match_dup 2)) | |
ae156f85 | 5233 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5234 | { |
5235 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5236 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5237 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5238 | }) | |
5239 | ||
5240 | (define_peephole2 | |
5241 | [(parallel | |
5242 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5243 | (and:BLK (match_dup 0) | |
5244 | (match_operand:BLK 1 "memory_operand" ""))) | |
5245 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5246 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5247 | (parallel |
5248 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5249 | (and:BLK (match_dup 3) | |
5250 | (match_operand:BLK 4 "memory_operand" ""))) | |
5251 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5252 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5253 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5254 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5255 | && !s390_overlap_p (operands[0], operands[1], |
5256 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5257 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5258 | [(parallel | |
5259 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
5260 | (use (match_dup 8)) | |
ae156f85 | 5261 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5262 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5263 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5264 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5265 | ||
9db1d521 HP |
5266 | |
5267 | ;; | |
5268 | ;;- Bit set (inclusive or) instructions. | |
5269 | ;; | |
5270 | ||
047d35ed AS |
5271 | (define_expand "ior<mode>3" |
5272 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5273 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5274 | (match_operand:INT 2 "general_operand" ""))) | |
5275 | (clobber (reg:CC CC_REGNUM))] | |
5276 | "" | |
5277 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
5278 | ||
9db1d521 HP |
5279 | ; |
5280 | ; iordi3 instruction pattern(s). | |
5281 | ; | |
5282 | ||
4023fb28 | 5283 | (define_insn "*iordi3_cc" |
ae156f85 | 5284 | [(set (reg CC_REGNUM) |
96fd3851 | 5285 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5286 | (match_operand:DI 2 "general_operand" "d,m")) |
5287 | (const_int 0))) | |
5288 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5289 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5290 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5291 | "@ | |
d40c829f UW |
5292 | ogr\t%0,%2 |
5293 | og\t%0,%2" | |
d3632d41 | 5294 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5295 | |
5296 | (define_insn "*iordi3_cconly" | |
ae156f85 | 5297 | [(set (reg CC_REGNUM) |
96fd3851 | 5298 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5299 | (match_operand:DI 2 "general_operand" "d,m")) |
5300 | (const_int 0))) | |
5301 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5302 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5303 | "@ | |
d40c829f UW |
5304 | ogr\t%0,%2 |
5305 | og\t%0,%2" | |
d3632d41 | 5306 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5307 | |
ec24698e UW |
5308 | (define_insn "*iordi3_extimm" |
5309 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") | |
5310 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") | |
5311 | (match_operand:DI 2 "general_operand" | |
5312 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q"))) | |
5313 | (clobber (reg:CC CC_REGNUM))] | |
5314 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
5315 | "@ | |
5316 | oihh\t%0,%i2 | |
5317 | oihl\t%0,%i2 | |
5318 | oilh\t%0,%i2 | |
5319 | oill\t%0,%i2 | |
5320 | oihf\t%0,%k2 | |
5321 | oilf\t%0,%k2 | |
5322 | ogr\t%0,%2 | |
5323 | og\t%0,%2 | |
5324 | # | |
5325 | #" | |
5326 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")]) | |
5327 | ||
8cb66696 | 5328 | (define_insn "*iordi3" |
0dfa6c5e | 5329 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
bad82153 | 5330 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") |
8cb66696 | 5331 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5332 | "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) |
ae156f85 | 5333 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 5334 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5335 | "@ |
f19a9af7 AK |
5336 | oihh\t%0,%i2 |
5337 | oihl\t%0,%i2 | |
5338 | oilh\t%0,%i2 | |
5339 | oill\t%0,%i2 | |
d40c829f | 5340 | ogr\t%0,%2 |
8cb66696 | 5341 | og\t%0,%2 |
0dfa6c5e | 5342 | # |
19b63d8e | 5343 | #" |
0dfa6c5e UW |
5344 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5345 | ||
5346 | (define_split | |
5347 | [(set (match_operand:DI 0 "s_operand" "") | |
5348 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5349 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5350 | "reload_completed" |
5351 | [(parallel | |
5352 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5353 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5354 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 5355 | |
9db1d521 HP |
5356 | ; |
5357 | ; iorsi3 instruction pattern(s). | |
5358 | ; | |
5359 | ||
4023fb28 | 5360 | (define_insn "*iorsi3_cc" |
ae156f85 | 5361 | [(set (reg CC_REGNUM) |
ec24698e UW |
5362 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5363 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5364 | (const_int 0))) |
ec24698e | 5365 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
5366 | (ior:SI (match_dup 1) (match_dup 2)))] |
5367 | "s390_match_ccmode(insn, CCTmode)" | |
5368 | "@ | |
ec24698e | 5369 | oilf\t%0,%o2 |
d40c829f UW |
5370 | or\t%0,%2 |
5371 | o\t%0,%2 | |
5372 | oy\t%0,%2" | |
ec24698e | 5373 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 UW |
5374 | |
5375 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 5376 | [(set (reg CC_REGNUM) |
ec24698e UW |
5377 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5378 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5379 | (const_int 0))) |
ec24698e | 5380 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
5381 | "s390_match_ccmode(insn, CCTmode)" |
5382 | "@ | |
ec24698e | 5383 | oilf\t%0,%o2 |
d40c829f UW |
5384 | or\t%0,%2 |
5385 | o\t%0,%2 | |
5386 | oy\t%0,%2" | |
ec24698e | 5387 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 | 5388 | |
8cb66696 | 5389 | (define_insn "*iorsi3_zarch" |
ec24698e UW |
5390 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
5391 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") | |
5392 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 5393 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5394 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5395 | "@ |
f19a9af7 AK |
5396 | oilh\t%0,%i2 |
5397 | oill\t%0,%i2 | |
ec24698e | 5398 | oilf\t%0,%o2 |
d40c829f UW |
5399 | or\t%0,%2 |
5400 | o\t%0,%2 | |
8cb66696 | 5401 | oy\t%0,%2 |
0dfa6c5e | 5402 | # |
19b63d8e | 5403 | #" |
ec24698e | 5404 | [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")]) |
8cb66696 UW |
5405 | |
5406 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 5407 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 5408 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 5409 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 5410 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5411 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5412 | "@ |
5413 | or\t%0,%2 | |
8cb66696 | 5414 | o\t%0,%2 |
0dfa6c5e | 5415 | # |
19b63d8e | 5416 | #" |
0dfa6c5e UW |
5417 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5418 | ||
5419 | (define_split | |
5420 | [(set (match_operand:SI 0 "s_operand" "") | |
5421 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5422 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5423 | "reload_completed" |
5424 | [(parallel | |
5425 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5426 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5427 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 5428 | |
4023fb28 UW |
5429 | ; |
5430 | ; iorhi3 instruction pattern(s). | |
5431 | ; | |
5432 | ||
8cb66696 | 5433 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
5434 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5435 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5436 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
ae156f85 | 5437 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5438 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5439 | "@ |
d40c829f | 5440 | or\t%0,%2 |
8cb66696 | 5441 | oill\t%0,%x2 |
0dfa6c5e | 5442 | # |
19b63d8e | 5443 | #" |
0dfa6c5e | 5444 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5445 | |
5446 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
5447 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5448 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5449 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 5450 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5451 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5452 | "@ | |
5453 | or\t%0,%2 | |
0dfa6c5e | 5454 | # |
19b63d8e | 5455 | #" |
0dfa6c5e UW |
5456 | [(set_attr "op_type" "RR,SI,SS")]) |
5457 | ||
5458 | (define_split | |
5459 | [(set (match_operand:HI 0 "s_operand" "") | |
5460 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5461 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5462 | "reload_completed" |
5463 | [(parallel | |
5464 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5465 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5466 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 5467 | |
9db1d521 | 5468 | ; |
4023fb28 | 5469 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5470 | ; |
5471 | ||
8cb66696 UW |
5472 | (define_insn "*iorqi3_zarch" |
5473 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5474 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5475 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5476 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5477 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5478 | "@ |
d40c829f | 5479 | or\t%0,%2 |
8cb66696 | 5480 | oill\t%0,%b2 |
fc0ea003 UW |
5481 | oi\t%S0,%b2 |
5482 | oiy\t%S0,%b2 | |
19b63d8e | 5483 | #" |
8cb66696 UW |
5484 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5485 | ||
5486 | (define_insn "*iorqi3_esa" | |
5487 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5488 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5489 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5490 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5491 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5492 | "@ |
8cb66696 | 5493 | or\t%0,%2 |
fc0ea003 | 5494 | oi\t%S0,%b2 |
19b63d8e | 5495 | #" |
8cb66696 | 5496 | [(set_attr "op_type" "RR,SI,SS")]) |
9db1d521 | 5497 | |
19b63d8e UW |
5498 | ; |
5499 | ; Block inclusive or (OC) patterns. | |
5500 | ; | |
5501 | ||
5502 | (define_insn "*oc" | |
5503 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5504 | (ior:BLK (match_dup 0) | |
5505 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5506 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5507 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5508 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5509 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 5510 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5511 | |
5512 | (define_split | |
5513 | [(set (match_operand 0 "memory_operand" "") | |
5514 | (ior (match_dup 0) | |
5515 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5516 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5517 | "reload_completed |
5518 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5519 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5520 | [(parallel | |
5521 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
5522 | (use (match_dup 2)) | |
ae156f85 | 5523 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5524 | { |
5525 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5526 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5527 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5528 | }) | |
5529 | ||
5530 | (define_peephole2 | |
5531 | [(parallel | |
5532 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5533 | (ior:BLK (match_dup 0) | |
5534 | (match_operand:BLK 1 "memory_operand" ""))) | |
5535 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5536 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5537 | (parallel |
5538 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5539 | (ior:BLK (match_dup 3) | |
5540 | (match_operand:BLK 4 "memory_operand" ""))) | |
5541 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5542 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5543 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5544 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5545 | && !s390_overlap_p (operands[0], operands[1], |
5546 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5547 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5548 | [(parallel | |
5549 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
5550 | (use (match_dup 8)) | |
ae156f85 | 5551 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5552 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5553 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5554 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5555 | ||
9db1d521 HP |
5556 | |
5557 | ;; | |
5558 | ;;- Xor instructions. | |
5559 | ;; | |
5560 | ||
047d35ed AS |
5561 | (define_expand "xor<mode>3" |
5562 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5563 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5564 | (match_operand:INT 2 "general_operand" ""))) | |
5565 | (clobber (reg:CC CC_REGNUM))] | |
5566 | "" | |
5567 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
5568 | ||
9db1d521 HP |
5569 | ; |
5570 | ; xordi3 instruction pattern(s). | |
5571 | ; | |
5572 | ||
4023fb28 | 5573 | (define_insn "*xordi3_cc" |
ae156f85 | 5574 | [(set (reg CC_REGNUM) |
96fd3851 | 5575 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5576 | (match_operand:DI 2 "general_operand" "d,m")) |
5577 | (const_int 0))) | |
5578 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5579 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5580 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5581 | "@ | |
d40c829f UW |
5582 | xgr\t%0,%2 |
5583 | xg\t%0,%2" | |
d3632d41 | 5584 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5585 | |
5586 | (define_insn "*xordi3_cconly" | |
ae156f85 | 5587 | [(set (reg CC_REGNUM) |
96fd3851 | 5588 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5589 | (match_operand:DI 2 "general_operand" "d,m")) |
5590 | (const_int 0))) | |
5591 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5592 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5593 | "@ | |
d40c829f UW |
5594 | xgr\t%0,%2 |
5595 | xr\t%0,%2" | |
d3632d41 | 5596 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5597 | |
ec24698e UW |
5598 | (define_insn "*xordi3_extimm" |
5599 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") | |
5600 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
5601 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q"))) | |
5602 | (clobber (reg:CC CC_REGNUM))] | |
5603 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
5604 | "@ | |
5605 | xihf\t%0,%k2 | |
5606 | xilf\t%0,%k2 | |
5607 | xgr\t%0,%2 | |
5608 | xg\t%0,%2 | |
5609 | # | |
5610 | #" | |
5611 | [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")]) | |
5612 | ||
8cb66696 | 5613 | (define_insn "*xordi3" |
0dfa6c5e UW |
5614 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5615 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5616 | (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) | |
ae156f85 | 5617 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 5618 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5619 | "@ |
d40c829f | 5620 | xgr\t%0,%2 |
8cb66696 | 5621 | xg\t%0,%2 |
0dfa6c5e | 5622 | # |
19b63d8e | 5623 | #" |
0dfa6c5e UW |
5624 | [(set_attr "op_type" "RRE,RXY,SI,SS")]) |
5625 | ||
5626 | (define_split | |
5627 | [(set (match_operand:DI 0 "s_operand" "") | |
5628 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5629 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5630 | "reload_completed" |
5631 | [(parallel | |
5632 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5633 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5634 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 5635 | |
9db1d521 HP |
5636 | ; |
5637 | ; xorsi3 instruction pattern(s). | |
5638 | ; | |
5639 | ||
4023fb28 | 5640 | (define_insn "*xorsi3_cc" |
ae156f85 | 5641 | [(set (reg CC_REGNUM) |
ec24698e UW |
5642 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5643 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5644 | (const_int 0))) |
ec24698e | 5645 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
5646 | (xor:SI (match_dup 1) (match_dup 2)))] |
5647 | "s390_match_ccmode(insn, CCTmode)" | |
5648 | "@ | |
ec24698e | 5649 | xilf\t%0,%o2 |
d40c829f UW |
5650 | xr\t%0,%2 |
5651 | x\t%0,%2 | |
5652 | xy\t%0,%2" | |
ec24698e | 5653 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 UW |
5654 | |
5655 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 5656 | [(set (reg CC_REGNUM) |
ec24698e UW |
5657 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5658 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5659 | (const_int 0))) |
ec24698e | 5660 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
5661 | "s390_match_ccmode(insn, CCTmode)" |
5662 | "@ | |
ec24698e | 5663 | xilf\t%0,%o2 |
d40c829f UW |
5664 | xr\t%0,%2 |
5665 | x\t%0,%2 | |
5666 | xy\t%0,%2" | |
ec24698e | 5667 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 | 5668 | |
8cb66696 | 5669 | (define_insn "*xorsi3" |
ec24698e UW |
5670 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") |
5671 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
5672 | (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 5673 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5674 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5675 | "@ |
ec24698e | 5676 | xilf\t%0,%o2 |
d40c829f UW |
5677 | xr\t%0,%2 |
5678 | x\t%0,%2 | |
8cb66696 | 5679 | xy\t%0,%2 |
0dfa6c5e | 5680 | # |
19b63d8e | 5681 | #" |
ec24698e | 5682 | [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")]) |
0dfa6c5e UW |
5683 | |
5684 | (define_split | |
5685 | [(set (match_operand:SI 0 "s_operand" "") | |
5686 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5687 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5688 | "reload_completed" |
5689 | [(parallel | |
5690 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5691 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5692 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 5693 | |
9db1d521 HP |
5694 | ; |
5695 | ; xorhi3 instruction pattern(s). | |
5696 | ; | |
5697 | ||
8cb66696 | 5698 | (define_insn "*xorhi3" |
ec24698e UW |
5699 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5700 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5701 | (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q"))) | |
ae156f85 | 5702 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5703 | "s390_logical_operator_ok_p (operands)" |
5704 | "@ | |
ec24698e | 5705 | xilf\t%0,%x2 |
8cb66696 | 5706 | xr\t%0,%2 |
0dfa6c5e | 5707 | # |
19b63d8e | 5708 | #" |
ec24698e | 5709 | [(set_attr "op_type" "RIL,RR,SI,SS")]) |
0dfa6c5e UW |
5710 | |
5711 | (define_split | |
5712 | [(set (match_operand:HI 0 "s_operand" "") | |
5713 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5714 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5715 | "reload_completed" |
5716 | [(parallel | |
5717 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5718 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5719 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 5720 | |
9db1d521 HP |
5721 | ; |
5722 | ; xorqi3 instruction pattern(s). | |
5723 | ; | |
5724 | ||
8cb66696 | 5725 | (define_insn "*xorqi3" |
ec24698e UW |
5726 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") |
5727 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5728 | (match_operand:QI 2 "general_operand" "Os,d,n,n,Q"))) | |
ae156f85 | 5729 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5730 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5731 | "@ |
ec24698e | 5732 | xilf\t%0,%b2 |
8cb66696 | 5733 | xr\t%0,%2 |
fc0ea003 UW |
5734 | xi\t%S0,%b2 |
5735 | xiy\t%S0,%b2 | |
19b63d8e | 5736 | #" |
ec24698e | 5737 | [(set_attr "op_type" "RIL,RR,SI,SIY,SS")]) |
4023fb28 | 5738 | |
19b63d8e UW |
5739 | ; |
5740 | ; Block exclusive or (XC) patterns. | |
5741 | ; | |
5742 | ||
5743 | (define_insn "*xc" | |
5744 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5745 | (xor:BLK (match_dup 0) | |
5746 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5747 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5748 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5749 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5750 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 5751 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5752 | |
5753 | (define_split | |
5754 | [(set (match_operand 0 "memory_operand" "") | |
5755 | (xor (match_dup 0) | |
5756 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5757 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5758 | "reload_completed |
5759 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5760 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5761 | [(parallel | |
5762 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
5763 | (use (match_dup 2)) | |
ae156f85 | 5764 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5765 | { |
5766 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5767 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5768 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5769 | }) | |
5770 | ||
5771 | (define_peephole2 | |
5772 | [(parallel | |
5773 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5774 | (xor:BLK (match_dup 0) | |
5775 | (match_operand:BLK 1 "memory_operand" ""))) | |
5776 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5777 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5778 | (parallel |
5779 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5780 | (xor:BLK (match_dup 3) | |
5781 | (match_operand:BLK 4 "memory_operand" ""))) | |
5782 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5783 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5784 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5785 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5786 | && !s390_overlap_p (operands[0], operands[1], |
5787 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5788 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5789 | [(parallel | |
5790 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
5791 | (use (match_dup 8)) | |
ae156f85 | 5792 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5793 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5794 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5795 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5796 | ||
5797 | ; | |
5798 | ; Block xor (XC) patterns with src == dest. | |
5799 | ; | |
5800 | ||
5801 | (define_insn "*xc_zero" | |
5802 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5803 | (const_int 0)) | |
5804 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 5805 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5806 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 5807 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 5808 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5809 | |
5810 | (define_peephole2 | |
5811 | [(parallel | |
5812 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5813 | (const_int 0)) | |
5814 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 5815 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5816 | (parallel |
5817 | [(set (match_operand:BLK 2 "memory_operand" "") | |
5818 | (const_int 0)) | |
5819 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 5820 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5821 | "s390_offset_p (operands[0], operands[2], operands[1]) |
5822 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
5823 | [(parallel | |
5824 | [(set (match_dup 4) (const_int 0)) | |
5825 | (use (match_dup 5)) | |
ae156f85 | 5826 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5827 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5828 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
5829 | ||
9db1d521 HP |
5830 | |
5831 | ;; | |
5832 | ;;- Negate instructions. | |
5833 | ;; | |
5834 | ||
5835 | ; | |
9a91a21f | 5836 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
5837 | ; |
5838 | ||
9a91a21f | 5839 | (define_expand "neg<mode>2" |
9db1d521 | 5840 | [(parallel |
9a91a21f AS |
5841 | [(set (match_operand:DSI 0 "register_operand" "=d") |
5842 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 5843 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5844 | "" |
5845 | "") | |
5846 | ||
26a89301 | 5847 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 5848 | [(set (reg CC_REGNUM) |
26a89301 UW |
5849 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
5850 | (match_operand:SI 1 "register_operand" "d") 0) | |
5851 | (const_int 32)) (const_int 32))) | |
5852 | (const_int 0))) | |
5853 | (set (match_operand:DI 0 "register_operand" "=d") | |
5854 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
5855 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5856 | "lcgfr\t%0,%1" | |
5857 | [(set_attr "op_type" "RRE")]) | |
5858 | ||
5859 | (define_insn "*negdi2_sign" | |
5860 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5861 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 5862 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
5863 | "TARGET_64BIT" |
5864 | "lcgfr\t%0,%1" | |
5865 | [(set_attr "op_type" "RRE")]) | |
5866 | ||
9a91a21f | 5867 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 5868 | [(set (reg CC_REGNUM) |
9a91a21f | 5869 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5870 | (const_int 0))) |
9a91a21f AS |
5871 | (set (match_operand:GPR 0 "register_operand" "=d") |
5872 | (neg:GPR (match_dup 1)))] | |
5873 | "s390_match_ccmode (insn, CCAmode)" | |
5874 | "lc<g>r\t%0,%1" | |
5875 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5876 | |
9a91a21f | 5877 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 5878 | [(set (reg CC_REGNUM) |
9a91a21f | 5879 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5880 | (const_int 0))) |
9a91a21f AS |
5881 | (clobber (match_scratch:GPR 0 "=d"))] |
5882 | "s390_match_ccmode (insn, CCAmode)" | |
5883 | "lc<g>r\t%0,%1" | |
5884 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5885 | |
9a91a21f AS |
5886 | (define_insn "*neg<mode>2" |
5887 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5888 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 5889 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
5890 | "" |
5891 | "lc<g>r\t%0,%1" | |
5892 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 5893 | |
26a89301 | 5894 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
5895 | [(set (match_operand:DI 0 "register_operand" "=d") |
5896 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 5897 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5898 | "!TARGET_64BIT" |
26a89301 UW |
5899 | "#" |
5900 | "&& reload_completed" | |
5901 | [(parallel | |
5902 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 5903 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 5904 | (parallel |
ae156f85 | 5905 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
5906 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
5907 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
5908 | (set (pc) | |
ae156f85 | 5909 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
5910 | (pc) |
5911 | (label_ref (match_dup 6)))) | |
5912 | (parallel | |
5913 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 5914 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
5915 | (match_dup 6)] |
5916 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
5917 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
5918 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
5919 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
5920 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 5921 | |
9db1d521 | 5922 | ; |
f5905b37 | 5923 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
5924 | ; |
5925 | ||
f5905b37 | 5926 | (define_expand "neg<mode>2" |
9db1d521 | 5927 | [(parallel |
f5905b37 AS |
5928 | [(set (match_operand:FPR 0 "register_operand" "=f") |
5929 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5930 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5931 | "TARGET_HARD_FLOAT" |
5932 | "") | |
5933 | ||
f5905b37 | 5934 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 5935 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5936 | (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) |
5937 | (match_operand:FPR 2 "const0_operand" ""))) | |
5938 | (set (match_operand:FPR 0 "register_operand" "=f") | |
5939 | (neg:FPR (match_dup 1)))] | |
26a89301 | 5940 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5941 | "lc<de>br\t%0,%1" |
26a89301 | 5942 | [(set_attr "op_type" "RRE") |
f5905b37 | 5943 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5944 | |
f5905b37 | 5945 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 5946 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5947 | (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) |
5948 | (match_operand:FPR 2 "const0_operand" ""))) | |
5949 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 5950 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5951 | "lc<de>br\t%0,%1" |
26a89301 | 5952 | [(set_attr "op_type" "RRE") |
f5905b37 | 5953 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5954 | |
f5905b37 AS |
5955 | (define_insn "*neg<mode>2" |
5956 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5957 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5958 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5959 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5960 | "lc<de>br\t%0,%1" |
077dab3b | 5961 | [(set_attr "op_type" "RRE") |
f5905b37 | 5962 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5963 | |
f5905b37 AS |
5964 | (define_insn "*neg<mode>2_ibm" |
5965 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5966 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5967 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5968 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 5969 | "lc<de>r\t%0,%1" |
077dab3b | 5970 | [(set_attr "op_type" "RR") |
f5905b37 | 5971 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
5972 | |
5973 | ||
5974 | ;; | |
5975 | ;;- Absolute value instructions. | |
5976 | ;; | |
5977 | ||
5978 | ; | |
9a91a21f | 5979 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
5980 | ; |
5981 | ||
26a89301 | 5982 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 5983 | [(set (reg CC_REGNUM) |
26a89301 UW |
5984 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
5985 | (match_operand:SI 1 "register_operand" "d") 0) | |
5986 | (const_int 32)) (const_int 32))) | |
5987 | (const_int 0))) | |
5988 | (set (match_operand:DI 0 "register_operand" "=d") | |
5989 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
5990 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5991 | "lpgfr\t%0,%1" | |
5992 | [(set_attr "op_type" "RRE")]) | |
5993 | ||
5994 | (define_insn "*absdi2_sign" | |
5995 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5996 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 5997 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
5998 | "TARGET_64BIT" |
5999 | "lpgfr\t%0,%1" | |
6000 | [(set_attr "op_type" "RRE")]) | |
6001 | ||
9a91a21f | 6002 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 6003 | [(set (reg CC_REGNUM) |
9a91a21f | 6004 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 6005 | (const_int 0))) |
9a91a21f AS |
6006 | (set (match_operand:GPR 0 "register_operand" "=d") |
6007 | (abs:GPR (match_dup 1)))] | |
26a89301 | 6008 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6009 | "lp<g>r\t%0,%1" |
6010 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6011 | |
9a91a21f | 6012 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 6013 | [(set (reg CC_REGNUM) |
9a91a21f | 6014 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6015 | (const_int 0))) |
9a91a21f | 6016 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6017 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6018 | "lp<g>r\t%0,%1" |
6019 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6020 | |
9a91a21f AS |
6021 | (define_insn "abs<mode>2" |
6022 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6023 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 6024 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6025 | "" |
9a91a21f AS |
6026 | "lp<g>r\t%0,%1" |
6027 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 6028 | |
9db1d521 | 6029 | ; |
f5905b37 | 6030 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
6031 | ; |
6032 | ||
f5905b37 | 6033 | (define_expand "abs<mode>2" |
9db1d521 | 6034 | [(parallel |
f5905b37 AS |
6035 | [(set (match_operand:FPR 0 "register_operand" "=f") |
6036 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6037 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6038 | "TARGET_HARD_FLOAT" |
6039 | "") | |
6040 | ||
f5905b37 | 6041 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 6042 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6043 | (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) |
6044 | (match_operand:FPR 2 "const0_operand" ""))) | |
6045 | (set (match_operand:FPR 0 "register_operand" "=f") | |
6046 | (abs:FPR (match_dup 1)))] | |
26a89301 | 6047 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6048 | "lp<de>br\t%0,%1" |
26a89301 | 6049 | [(set_attr "op_type" "RRE") |
f5905b37 | 6050 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6051 | |
f5905b37 | 6052 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 6053 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6054 | (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) |
6055 | (match_operand:FPR 2 "const0_operand" ""))) | |
6056 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 6057 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6058 | "lp<de>br\t%0,%1" |
26a89301 | 6059 | [(set_attr "op_type" "RRE") |
f5905b37 | 6060 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6061 | |
f5905b37 AS |
6062 | (define_insn "*abs<mode>2" |
6063 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6064 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6065 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6066 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6067 | "lp<de>br\t%0,%1" |
077dab3b | 6068 | [(set_attr "op_type" "RRE") |
f5905b37 | 6069 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6070 | |
f5905b37 AS |
6071 | (define_insn "*abs<mode>2_ibm" |
6072 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6073 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6074 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6075 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 6076 | "lp<de>r\t%0,%1" |
077dab3b | 6077 | [(set_attr "op_type" "RR") |
f5905b37 | 6078 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6079 | |
3ef093a8 AK |
6080 | ;; |
6081 | ;;- Negated absolute value instructions | |
6082 | ;; | |
6083 | ||
6084 | ; | |
6085 | ; Integer | |
6086 | ; | |
6087 | ||
26a89301 | 6088 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 6089 | [(set (reg CC_REGNUM) |
26a89301 UW |
6090 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6091 | (match_operand:SI 1 "register_operand" "d") 0) | |
6092 | (const_int 32)) (const_int 32)))) | |
6093 | (const_int 0))) | |
6094 | (set (match_operand:DI 0 "register_operand" "=d") | |
6095 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6096 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6097 | "lngfr\t%0,%1" | |
6098 | [(set_attr "op_type" "RRE")]) | |
6099 | ||
6100 | (define_insn "*negabsdi2_sign" | |
6101 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6102 | (neg:DI (abs:DI (sign_extend:DI | |
6103 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 6104 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6105 | "TARGET_64BIT" |
6106 | "lngfr\t%0,%1" | |
6107 | [(set_attr "op_type" "RRE")]) | |
3ef093a8 | 6108 | |
9a91a21f | 6109 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6110 | [(set (reg CC_REGNUM) |
9a91a21f | 6111 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6112 | (const_int 0))) |
9a91a21f AS |
6113 | (set (match_operand:GPR 0 "register_operand" "=d") |
6114 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 6115 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6116 | "ln<g>r\t%0,%1" |
6117 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6118 | |
9a91a21f | 6119 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6120 | [(set (reg CC_REGNUM) |
9a91a21f | 6121 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6122 | (const_int 0))) |
9a91a21f | 6123 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6124 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6125 | "ln<g>r\t%0,%1" |
6126 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6127 | |
9a91a21f AS |
6128 | (define_insn "*negabs<mode>2" |
6129 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6130 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 6131 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 6132 | "" |
9a91a21f AS |
6133 | "ln<g>r\t%0,%1" |
6134 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6135 | |
3ef093a8 AK |
6136 | ; |
6137 | ; Floating point | |
6138 | ; | |
6139 | ||
f5905b37 | 6140 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6141 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6142 | (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) |
6143 | (match_operand:FPR 2 "const0_operand" ""))) | |
6144 | (set (match_operand:FPR 0 "register_operand" "=f") | |
6145 | (neg:FPR (abs:FPR (match_dup 1))))] | |
26a89301 | 6146 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6147 | "ln<de>br\t%0,%1" |
26a89301 | 6148 | [(set_attr "op_type" "RRE") |
f5905b37 | 6149 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6150 | |
f5905b37 | 6151 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6152 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6153 | (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) |
6154 | (match_operand:FPR 2 "const0_operand" ""))) | |
6155 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 6156 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6157 | "ln<de>br\t%0,%1" |
26a89301 | 6158 | [(set_attr "op_type" "RRE") |
f5905b37 | 6159 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6160 | |
f5905b37 AS |
6161 | (define_insn "*negabs<mode>2" |
6162 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6163 | (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))) | |
ae156f85 | 6164 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 6165 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6166 | "ln<de>br\t%0,%1" |
26a89301 | 6167 | [(set_attr "op_type" "RRE") |
f5905b37 | 6168 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6169 | |
4023fb28 UW |
6170 | ;; |
6171 | ;;- Square root instructions. | |
6172 | ;; | |
6173 | ||
6174 | ; | |
f5905b37 | 6175 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
6176 | ; |
6177 | ||
f5905b37 AS |
6178 | (define_insn "sqrt<mode>2" |
6179 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
6180 | (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))] | |
4023fb28 UW |
6181 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6182 | "@ | |
f5905b37 AS |
6183 | sq<de>br\t%0,%1 |
6184 | sq<de>b\t%0,%1" | |
a036c6f7 | 6185 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 6186 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 6187 | |
9db1d521 HP |
6188 | |
6189 | ;; | |
6190 | ;;- One complement instructions. | |
6191 | ;; | |
6192 | ||
6193 | ; | |
342cf42b | 6194 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 6195 | ; |
c7453384 | 6196 | |
342cf42b | 6197 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 6198 | [(parallel |
342cf42b AS |
6199 | [(set (match_operand:INT 0 "register_operand" "") |
6200 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
6201 | (const_int -1))) | |
ae156f85 | 6202 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6203 | "" |
4023fb28 | 6204 | "") |
9db1d521 HP |
6205 | |
6206 | ||
ec24698e UW |
6207 | ;; |
6208 | ;; Find leftmost bit instructions. | |
6209 | ;; | |
6210 | ||
6211 | (define_expand "clzdi2" | |
6212 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6213 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
6214 | "TARGET_EXTIMM && TARGET_64BIT" | |
6215 | { | |
6216 | rtx insn, clz_equal; | |
6217 | rtx wide_reg = gen_reg_rtx (TImode); | |
6218 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
6219 | ||
6220 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
6221 | ||
6222 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
6223 | ||
6224 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); | |
6225 | REG_NOTES (insn) = | |
6226 | gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn)); | |
6227 | ||
6228 | DONE; | |
6229 | }) | |
6230 | ||
6231 | (define_insn "clztidi2" | |
6232 | [(set (match_operand:TI 0 "register_operand" "=d") | |
6233 | (ior:TI | |
6234 | (ashift:TI | |
6235 | (zero_extend:TI | |
6236 | (xor:DI (match_operand:DI 1 "register_operand" "d") | |
6237 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
6238 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
6239 | ||
6240 | (const_int 64)) | |
6241 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
6242 | (clobber (reg:CC CC_REGNUM))] | |
6243 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) | |
6244 | == (unsigned HOST_WIDE_INT) 1 << 63 | |
6245 | && TARGET_EXTIMM && TARGET_64BIT" | |
6246 | "flogr\t%0,%1" | |
6247 | [(set_attr "op_type" "RRE")]) | |
6248 | ||
6249 | ||
9db1d521 HP |
6250 | ;; |
6251 | ;;- Rotate instructions. | |
6252 | ;; | |
6253 | ||
6254 | ; | |
9a91a21f | 6255 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
6256 | ; |
6257 | ||
9a91a21f AS |
6258 | (define_insn "rotl<mode>3" |
6259 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6260 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
6261 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9e8327e3 | 6262 | "TARGET_CPU_ZARCH" |
9a91a21f | 6263 | "rll<g>\t%0,%1,%Y2" |
077dab3b HP |
6264 | [(set_attr "op_type" "RSE") |
6265 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6266 | |
6267 | ||
6268 | ;; | |
f337b930 | 6269 | ;;- Shift instructions. |
9db1d521 | 6270 | ;; |
9db1d521 HP |
6271 | |
6272 | ; | |
f337b930 | 6273 | ; (ashl|lshr)di3 instruction pattern(s). |
9db1d521 HP |
6274 | ; |
6275 | ||
f337b930 | 6276 | (define_expand "<shift>di3" |
ecbe845e | 6277 | [(set (match_operand:DI 0 "register_operand" "") |
f337b930 AS |
6278 | (SHIFT:DI (match_operand:DI 1 "register_operand" "") |
6279 | (match_operand:SI 2 "shift_count_operand" "")))] | |
9db1d521 HP |
6280 | "" |
6281 | "") | |
6282 | ||
f337b930 | 6283 | (define_insn "*<shift>di3_31" |
ac32b25e | 6284 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 AS |
6285 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
6286 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6287 | "!TARGET_64BIT" |
f337b930 | 6288 | "s<lr>dl\t%0,%Y2" |
077dab3b HP |
6289 | [(set_attr "op_type" "RS") |
6290 | (set_attr "atype" "reg")]) | |
9db1d521 | 6291 | |
f337b930 | 6292 | (define_insn "*<shift>di3_64" |
ac32b25e | 6293 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 AS |
6294 | (SHIFT:DI (match_operand:DI 1 "register_operand" "d") |
6295 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6296 | "TARGET_64BIT" |
f337b930 | 6297 | "s<lr>lg\t%0,%1,%Y2" |
077dab3b HP |
6298 | [(set_attr "op_type" "RSE") |
6299 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6300 | |
6301 | ; | |
6302 | ; ashrdi3 instruction pattern(s). | |
6303 | ; | |
6304 | ||
6305 | (define_expand "ashrdi3" | |
6306 | [(parallel | |
6307 | [(set (match_operand:DI 0 "register_operand" "") | |
6308 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6309 | (match_operand:SI 2 "shift_count_operand" ""))) |
ae156f85 | 6310 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6311 | "" |
6312 | "") | |
6313 | ||
ecbe845e | 6314 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 6315 | [(set (reg CC_REGNUM) |
ac32b25e UW |
6316 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6317 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6318 | (const_int 0))) |
ac32b25e | 6319 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6320 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6321 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6322 | "srda\t%0,%Y2" |
077dab3b HP |
6323 | [(set_attr "op_type" "RS") |
6324 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6325 | |
6326 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 6327 | [(set (reg CC_REGNUM) |
ac32b25e UW |
6328 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6329 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6330 | (const_int 0))) |
ac32b25e | 6331 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6332 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6333 | "srda\t%0,%Y2" |
077dab3b HP |
6334 | [(set_attr "op_type" "RS") |
6335 | (set_attr "atype" "reg")]) | |
ecbe845e | 6336 | |
9db1d521 | 6337 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6338 | [(set (match_operand:DI 0 "register_operand" "=d") |
6339 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6340 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
ae156f85 | 6341 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6342 | "!TARGET_64BIT" |
ac32b25e | 6343 | "srda\t%0,%Y2" |
077dab3b HP |
6344 | [(set_attr "op_type" "RS") |
6345 | (set_attr "atype" "reg")]) | |
c7453384 | 6346 | |
ecbe845e | 6347 | (define_insn "*ashrdi3_cc_64" |
ae156f85 | 6348 | [(set (reg CC_REGNUM) |
ac32b25e UW |
6349 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6350 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6351 | (const_int 0))) |
ac32b25e | 6352 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6353 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6354 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
ac32b25e | 6355 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6356 | [(set_attr "op_type" "RSE") |
6357 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6358 | |
6359 | (define_insn "*ashrdi3_cconly_64" | |
ae156f85 | 6360 | [(set (reg CC_REGNUM) |
ac32b25e UW |
6361 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6362 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6363 | (const_int 0))) |
ac32b25e | 6364 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6365 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
ac32b25e | 6366 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6367 | [(set_attr "op_type" "RSE") |
6368 | (set_attr "atype" "reg")]) | |
ecbe845e | 6369 | |
9db1d521 | 6370 | (define_insn "*ashrdi3_64" |
ac32b25e UW |
6371 | [(set (match_operand:DI 0 "register_operand" "=d") |
6372 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6373 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
ae156f85 | 6374 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6375 | "TARGET_64BIT" |
ac32b25e | 6376 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6377 | [(set_attr "op_type" "RSE") |
6378 | (set_attr "atype" "reg")]) | |
6379 | ||
9db1d521 HP |
6380 | |
6381 | ; | |
f337b930 | 6382 | ; (ashl|lshr)si3 instruction pattern(s). |
9db1d521 | 6383 | ; |
9db1d521 | 6384 | |
f337b930 | 6385 | (define_insn "<shift>si3" |
ac32b25e | 6386 | [(set (match_operand:SI 0 "register_operand" "=d") |
f337b930 AS |
6387 | (SHIFT:SI (match_operand:SI 1 "register_operand" "0") |
6388 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6389 | "" |
f337b930 | 6390 | "s<lr>l\t%0,%Y2" |
077dab3b HP |
6391 | [(set_attr "op_type" "RS") |
6392 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6393 | |
6394 | ; | |
6395 | ; ashrsi3 instruction pattern(s). | |
6396 | ; | |
6397 | ||
ecbe845e | 6398 | (define_insn "*ashrsi3_cc" |
ae156f85 | 6399 | [(set (reg CC_REGNUM) |
ac32b25e UW |
6400 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6401 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6402 | (const_int 0))) |
ac32b25e | 6403 | (set (match_operand:SI 0 "register_operand" "=d") |
ecbe845e UW |
6404 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
6405 | "s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6406 | "sra\t%0,%Y2" |
077dab3b HP |
6407 | [(set_attr "op_type" "RS") |
6408 | (set_attr "atype" "reg")]) | |
6409 | ||
ecbe845e UW |
6410 | |
6411 | (define_insn "*ashrsi3_cconly" | |
ae156f85 | 6412 | [(set (reg CC_REGNUM) |
ac32b25e UW |
6413 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6414 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6415 | (const_int 0))) |
ac32b25e | 6416 | (clobber (match_scratch:SI 0 "=d"))] |
ecbe845e | 6417 | "s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6418 | "sra\t%0,%Y2" |
077dab3b HP |
6419 | [(set_attr "op_type" "RS") |
6420 | (set_attr "atype" "reg")]) | |
ecbe845e | 6421 | |
9db1d521 | 6422 | (define_insn "ashrsi3" |
ac32b25e UW |
6423 | [(set (match_operand:SI 0 "register_operand" "=d") |
6424 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6425 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
ae156f85 | 6426 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6427 | "" |
ac32b25e | 6428 | "sra\t%0,%Y2" |
077dab3b HP |
6429 | [(set_attr "op_type" "RS") |
6430 | (set_attr "atype" "reg")]) | |
9db1d521 | 6431 | |
9db1d521 | 6432 | |
9db1d521 HP |
6433 | ;; |
6434 | ;; Branch instruction patterns. | |
6435 | ;; | |
6436 | ||
fa77b251 AS |
6437 | (define_expand "b<code>" |
6438 | [(set (pc) | |
6439 | (if_then_else (COMPARE (match_operand 0 "" "") | |
6440 | (const_int 0)) | |
6441 | (match_dup 0) | |
6442 | (pc)))] | |
ba956982 | 6443 | "" |
6590e19a | 6444 | "s390_emit_jump (operands[0], |
fa77b251 | 6445 | s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;") |
ba956982 | 6446 | |
9db1d521 HP |
6447 | |
6448 | ;; | |
6449 | ;;- Conditional jump instructions. | |
6450 | ;; | |
6451 | ||
6590e19a UW |
6452 | (define_insn "*cjump_64" |
6453 | [(set (pc) | |
6454 | (if_then_else | |
ae156f85 | 6455 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6456 | (label_ref (match_operand 0 "" "")) |
6457 | (pc)))] | |
6458 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6459 | { |
13e58269 | 6460 | if (get_attr_length (insn) == 4) |
d40c829f | 6461 | return "j%C1\t%l0"; |
6590e19a | 6462 | else |
d40c829f | 6463 | return "jg%C1\t%l0"; |
6590e19a UW |
6464 | } |
6465 | [(set_attr "op_type" "RI") | |
6466 | (set_attr "type" "branch") | |
6467 | (set (attr "length") | |
6468 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6469 | (const_int 4) (const_int 6)))]) | |
6470 | ||
6471 | (define_insn "*cjump_31" | |
6472 | [(set (pc) | |
6473 | (if_then_else | |
ae156f85 | 6474 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6475 | (label_ref (match_operand 0 "" "")) |
6476 | (pc)))] | |
6477 | "!TARGET_CPU_ZARCH" | |
6478 | { | |
8d933e31 AS |
6479 | gcc_assert (get_attr_length (insn) == 4); |
6480 | return "j%C1\t%l0"; | |
10bbf137 | 6481 | } |
9db1d521 | 6482 | [(set_attr "op_type" "RI") |
077dab3b | 6483 | (set_attr "type" "branch") |
13e58269 | 6484 | (set (attr "length") |
6590e19a UW |
6485 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6486 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6487 | (const_int 4) (const_int 6)) | |
6488 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6489 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6490 | |
f314b9b1 | 6491 | (define_insn "*cjump_long" |
6590e19a UW |
6492 | [(set (pc) |
6493 | (if_then_else | |
ae156f85 | 6494 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6495 | (match_operand 0 "address_operand" "U") |
6496 | (pc)))] | |
9db1d521 | 6497 | "" |
f314b9b1 UW |
6498 | { |
6499 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6500 | return "b%C1r\t%0"; |
f314b9b1 | 6501 | else |
d40c829f | 6502 | return "b%C1\t%a0"; |
10bbf137 | 6503 | } |
c7453384 | 6504 | [(set (attr "op_type") |
f314b9b1 UW |
6505 | (if_then_else (match_operand 0 "register_operand" "") |
6506 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 6507 | (set_attr "type" "branch") |
077dab3b | 6508 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6509 | |
6510 | ||
6511 | ;; | |
6512 | ;;- Negated conditional jump instructions. | |
6513 | ;; | |
6514 | ||
6590e19a UW |
6515 | (define_insn "*icjump_64" |
6516 | [(set (pc) | |
6517 | (if_then_else | |
ae156f85 | 6518 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6519 | (pc) |
6520 | (label_ref (match_operand 0 "" ""))))] | |
6521 | "TARGET_CPU_ZARCH" | |
c7453384 | 6522 | { |
13e58269 | 6523 | if (get_attr_length (insn) == 4) |
d40c829f | 6524 | return "j%D1\t%l0"; |
6590e19a | 6525 | else |
d40c829f | 6526 | return "jg%D1\t%l0"; |
6590e19a UW |
6527 | } |
6528 | [(set_attr "op_type" "RI") | |
6529 | (set_attr "type" "branch") | |
6530 | (set (attr "length") | |
6531 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6532 | (const_int 4) (const_int 6)))]) | |
6533 | ||
6534 | (define_insn "*icjump_31" | |
6535 | [(set (pc) | |
6536 | (if_then_else | |
ae156f85 | 6537 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6538 | (pc) |
6539 | (label_ref (match_operand 0 "" ""))))] | |
6540 | "!TARGET_CPU_ZARCH" | |
6541 | { | |
8d933e31 AS |
6542 | gcc_assert (get_attr_length (insn) == 4); |
6543 | return "j%D1\t%l0"; | |
10bbf137 | 6544 | } |
9db1d521 | 6545 | [(set_attr "op_type" "RI") |
077dab3b | 6546 | (set_attr "type" "branch") |
13e58269 | 6547 | (set (attr "length") |
6590e19a UW |
6548 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6549 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6550 | (const_int 4) (const_int 6)) | |
6551 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6552 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6553 | |
f314b9b1 | 6554 | (define_insn "*icjump_long" |
6590e19a UW |
6555 | [(set (pc) |
6556 | (if_then_else | |
ae156f85 | 6557 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6558 | (pc) |
6559 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 6560 | "" |
f314b9b1 UW |
6561 | { |
6562 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6563 | return "b%D1r\t%0"; |
f314b9b1 | 6564 | else |
d40c829f | 6565 | return "b%D1\t%a0"; |
10bbf137 | 6566 | } |
c7453384 | 6567 | [(set (attr "op_type") |
f314b9b1 UW |
6568 | (if_then_else (match_operand 0 "register_operand" "") |
6569 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6570 | (set_attr "type" "branch") |
6571 | (set_attr "atype" "agen")]) | |
9db1d521 | 6572 | |
4456530d HP |
6573 | ;; |
6574 | ;;- Trap instructions. | |
6575 | ;; | |
6576 | ||
6577 | (define_insn "trap" | |
6578 | [(trap_if (const_int 1) (const_int 0))] | |
6579 | "" | |
d40c829f | 6580 | "j\t.+2" |
6590e19a | 6581 | [(set_attr "op_type" "RI") |
077dab3b | 6582 | (set_attr "type" "branch")]) |
4456530d HP |
6583 | |
6584 | (define_expand "conditional_trap" | |
6590e19a UW |
6585 | [(trap_if (match_operand 0 "comparison_operator" "") |
6586 | (match_operand 1 "general_operand" ""))] | |
4456530d | 6587 | "" |
4456530d | 6588 | { |
6590e19a UW |
6589 | if (operands[1] != const0_rtx) FAIL; |
6590 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
6591 | s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6592 | }) |
4456530d HP |
6593 | |
6594 | (define_insn "*trap" | |
ae156f85 | 6595 | [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4456530d HP |
6596 | (const_int 0))] |
6597 | "" | |
d40c829f | 6598 | "j%C0\t.+2"; |
077dab3b HP |
6599 | [(set_attr "op_type" "RI") |
6600 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6601 | |
6602 | ;; | |
0a3bdf9d | 6603 | ;;- Loop instructions. |
9db1d521 | 6604 | ;; |
0a3bdf9d UW |
6605 | ;; This is all complicated by the fact that since this is a jump insn |
6606 | ;; we must handle our own output reloads. | |
c7453384 | 6607 | |
0a3bdf9d UW |
6608 | (define_expand "doloop_end" |
6609 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6610 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6611 | (use (match_operand 2 "" "")) ; max iterations | |
6612 | (use (match_operand 3 "" "")) ; loop level | |
6613 | (use (match_operand 4 "" ""))] ; label | |
6614 | "" | |
0a3bdf9d | 6615 | { |
6590e19a UW |
6616 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
6617 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
6618 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
6619 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
6620 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
6621 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6622 | else | |
6623 | FAIL; | |
6624 | ||
6625 | DONE; | |
10bbf137 | 6626 | }) |
0a3bdf9d | 6627 | |
6590e19a | 6628 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
6629 | [(set (pc) |
6630 | (if_then_else | |
6631 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6632 | (const_int 1)) | |
6633 | (label_ref (match_operand 0 "" "")) | |
6634 | (pc))) | |
bd446804 | 6635 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 6636 | (plus:SI (match_dup 1) (const_int -1))) |
eb862a88 | 6637 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6638 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 6639 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6640 | { |
6641 | if (which_alternative != 0) | |
10bbf137 | 6642 | return "#"; |
0a3bdf9d | 6643 | else if (get_attr_length (insn) == 4) |
d40c829f | 6644 | return "brct\t%1,%l0"; |
6590e19a | 6645 | else |
545d16ff | 6646 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
6647 | } |
6648 | "&& reload_completed | |
6649 | && (! REG_P (operands[2]) | |
6650 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6651 | [(parallel [(set (reg:CCAN CC_REGNUM) |
6590e19a UW |
6652 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6653 | (const_int 0))) | |
6654 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6655 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6656 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
6657 | (label_ref (match_dup 0)) |
6658 | (pc)))] | |
6659 | "" | |
6660 | [(set_attr "op_type" "RI") | |
6661 | (set_attr "type" "branch") | |
6662 | (set (attr "length") | |
6663 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6664 | (const_int 4) (const_int 10)))]) | |
6665 | ||
6666 | (define_insn_and_split "doloop_si31" | |
6667 | [(set (pc) | |
6668 | (if_then_else | |
6669 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6670 | (const_int 1)) | |
6671 | (label_ref (match_operand 0 "" "")) | |
6672 | (pc))) | |
6673 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") | |
6674 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 6675 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6676 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
6677 | "!TARGET_CPU_ZARCH" |
6678 | { | |
6679 | if (which_alternative != 0) | |
6680 | return "#"; | |
6681 | else if (get_attr_length (insn) == 4) | |
6682 | return "brct\t%1,%l0"; | |
0a3bdf9d | 6683 | else |
8d933e31 | 6684 | gcc_unreachable (); |
10bbf137 | 6685 | } |
6590e19a UW |
6686 | "&& reload_completed |
6687 | && (! REG_P (operands[2]) | |
6688 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6689 | [(parallel [(set (reg:CCAN CC_REGNUM) |
6590e19a UW |
6690 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6691 | (const_int 0))) | |
6692 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6693 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6694 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
6695 | (label_ref (match_dup 0)) |
6696 | (pc)))] | |
6697 | "" | |
0a3bdf9d | 6698 | [(set_attr "op_type" "RI") |
077dab3b | 6699 | (set_attr "type" "branch") |
0a3bdf9d | 6700 | (set (attr "length") |
6590e19a UW |
6701 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6702 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6703 | (const_int 4) (const_int 6)) | |
6704 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6705 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6706 | |
0a3bdf9d UW |
6707 | (define_insn "*doloop_si_long" |
6708 | [(set (pc) | |
6709 | (if_then_else | |
6710 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6711 | (const_int 1)) | |
d3632d41 | 6712 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6713 | (pc))) |
6714 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6715 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 6716 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6717 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 6718 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6719 | { |
6720 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6721 | return "bctr\t%1,%0"; |
0a3bdf9d | 6722 | else |
d40c829f | 6723 | return "bct\t%1,%a0"; |
10bbf137 | 6724 | } |
c7453384 | 6725 | [(set (attr "op_type") |
0a3bdf9d UW |
6726 | (if_then_else (match_operand 0 "register_operand" "") |
6727 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6728 | (set_attr "type" "branch") |
6729 | (set_attr "atype" "agen")]) | |
0a3bdf9d | 6730 | |
6590e19a | 6731 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
6732 | [(set (pc) |
6733 | (if_then_else | |
6734 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6735 | (const_int 1)) | |
6736 | (label_ref (match_operand 0 "" "")) | |
6737 | (pc))) | |
eb862a88 | 6738 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 6739 | (plus:DI (match_dup 1) (const_int -1))) |
eb862a88 | 6740 | (clobber (match_scratch:DI 3 "=X,&1")) |
ae156f85 | 6741 | (clobber (reg:CC CC_REGNUM))] |
0a3bdf9d | 6742 | "TARGET_64BIT" |
0a3bdf9d UW |
6743 | { |
6744 | if (which_alternative != 0) | |
10bbf137 | 6745 | return "#"; |
0a3bdf9d | 6746 | else if (get_attr_length (insn) == 4) |
d40c829f | 6747 | return "brctg\t%1,%l0"; |
0a3bdf9d | 6748 | else |
545d16ff | 6749 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 6750 | } |
6590e19a | 6751 | "&& reload_completed |
0a3bdf9d UW |
6752 | && (! REG_P (operands[2]) |
6753 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6754 | [(parallel [(set (reg:CCAN CC_REGNUM) |
0a3bdf9d UW |
6755 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
6756 | (const_int 0))) | |
6757 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6758 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6759 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 6760 | (label_ref (match_dup 0)) |
0a3bdf9d | 6761 | (pc)))] |
6590e19a UW |
6762 | "" |
6763 | [(set_attr "op_type" "RI") | |
6764 | (set_attr "type" "branch") | |
6765 | (set (attr "length") | |
6766 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6767 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
6768 | |
6769 | ;; | |
6770 | ;;- Unconditional jump instructions. | |
6771 | ;; | |
6772 | ||
6773 | ; | |
6774 | ; jump instruction pattern(s). | |
6775 | ; | |
6776 | ||
6590e19a UW |
6777 | (define_expand "jump" |
6778 | [(match_operand 0 "" "")] | |
9db1d521 | 6779 | "" |
6590e19a UW |
6780 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
6781 | ||
6782 | (define_insn "*jump64" | |
6783 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6784 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6785 | { |
13e58269 | 6786 | if (get_attr_length (insn) == 4) |
d40c829f | 6787 | return "j\t%l0"; |
6590e19a | 6788 | else |
d40c829f | 6789 | return "jg\t%l0"; |
6590e19a UW |
6790 | } |
6791 | [(set_attr "op_type" "RI") | |
6792 | (set_attr "type" "branch") | |
6793 | (set (attr "length") | |
6794 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6795 | (const_int 4) (const_int 6)))]) | |
6796 | ||
6797 | (define_insn "*jump31" | |
6798 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6799 | "!TARGET_CPU_ZARCH" | |
6800 | { | |
8d933e31 AS |
6801 | gcc_assert (get_attr_length (insn) == 4); |
6802 | return "j\t%l0"; | |
10bbf137 | 6803 | } |
9db1d521 | 6804 | [(set_attr "op_type" "RI") |
077dab3b | 6805 | (set_attr "type" "branch") |
13e58269 | 6806 | (set (attr "length") |
6590e19a UW |
6807 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6808 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6809 | (const_int 4) (const_int 6)) | |
6810 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6811 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
6812 | |
6813 | ; | |
6814 | ; indirect-jump instruction pattern(s). | |
6815 | ; | |
6816 | ||
6817 | (define_insn "indirect_jump" | |
d3632d41 | 6818 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6819 | "" |
f314b9b1 UW |
6820 | { |
6821 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6822 | return "br\t%0"; |
f314b9b1 | 6823 | else |
d40c829f | 6824 | return "b\t%a0"; |
10bbf137 | 6825 | } |
c7453384 | 6826 | [(set (attr "op_type") |
f314b9b1 UW |
6827 | (if_then_else (match_operand 0 "register_operand" "") |
6828 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6829 | (set_attr "type" "branch") |
6830 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6831 | |
6832 | ; | |
f314b9b1 | 6833 | ; casesi instruction pattern(s). |
9db1d521 HP |
6834 | ; |
6835 | ||
f314b9b1 | 6836 | (define_insn "casesi_jump" |
d3632d41 | 6837 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 6838 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 6839 | "" |
9db1d521 | 6840 | { |
f314b9b1 | 6841 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 6842 | return "br\t%0"; |
f314b9b1 | 6843 | else |
d40c829f | 6844 | return "b\t%a0"; |
10bbf137 | 6845 | } |
c7453384 | 6846 | [(set (attr "op_type") |
f314b9b1 UW |
6847 | (if_then_else (match_operand 0 "register_operand" "") |
6848 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6849 | (set_attr "type" "branch") |
6850 | (set_attr "atype" "agen")]) | |
9db1d521 | 6851 | |
f314b9b1 UW |
6852 | (define_expand "casesi" |
6853 | [(match_operand:SI 0 "general_operand" "") | |
6854 | (match_operand:SI 1 "general_operand" "") | |
6855 | (match_operand:SI 2 "general_operand" "") | |
6856 | (label_ref (match_operand 3 "" "")) | |
6857 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 6858 | "" |
f314b9b1 UW |
6859 | { |
6860 | rtx index = gen_reg_rtx (SImode); | |
6861 | rtx base = gen_reg_rtx (Pmode); | |
6862 | rtx target = gen_reg_rtx (Pmode); | |
6863 | ||
6864 | emit_move_insn (index, operands[0]); | |
6865 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6866 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 6867 | operands[4]); |
f314b9b1 UW |
6868 | |
6869 | if (Pmode != SImode) | |
6870 | index = convert_to_mode (Pmode, index, 1); | |
6871 | if (GET_CODE (index) != REG) | |
6872 | index = copy_to_mode_reg (Pmode, index); | |
6873 | ||
6874 | if (TARGET_64BIT) | |
6875 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6876 | else | |
a556fd39 | 6877 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 6878 | |
f314b9b1 UW |
6879 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6880 | ||
542a8afa | 6881 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
6882 | emit_move_insn (target, index); |
6883 | ||
6884 | if (flag_pic) | |
6885 | target = gen_rtx_PLUS (Pmode, base, target); | |
6886 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
6887 | ||
6888 | DONE; | |
10bbf137 | 6889 | }) |
9db1d521 HP |
6890 | |
6891 | ||
6892 | ;; | |
6893 | ;;- Jump to subroutine. | |
6894 | ;; | |
6895 | ;; | |
6896 | ||
6897 | ; | |
6898 | ; untyped call instruction pattern(s). | |
6899 | ; | |
6900 | ||
6901 | ;; Call subroutine returning any type. | |
6902 | (define_expand "untyped_call" | |
6903 | [(parallel [(call (match_operand 0 "" "") | |
6904 | (const_int 0)) | |
6905 | (match_operand 1 "" "") | |
6906 | (match_operand 2 "" "")])] | |
6907 | "" | |
9db1d521 HP |
6908 | { |
6909 | int i; | |
6910 | ||
6911 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
6912 | ||
6913 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
6914 | { | |
6915 | rtx set = XVECEXP (operands[2], 0, i); | |
6916 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
6917 | } | |
6918 | ||
6919 | /* The optimizer does not know that the call sets the function value | |
6920 | registers we stored in the result block. We avoid problems by | |
6921 | claiming that all hard registers are used and clobbered at this | |
6922 | point. */ | |
6923 | emit_insn (gen_blockage ()); | |
6924 | ||
6925 | DONE; | |
10bbf137 | 6926 | }) |
9db1d521 HP |
6927 | |
6928 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
6929 | ;; all of memory. This blocks insns from being moved across this point. | |
6930 | ||
6931 | (define_insn "blockage" | |
10bbf137 | 6932 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 6933 | "" |
4023fb28 | 6934 | "" |
d5869ca0 UW |
6935 | [(set_attr "type" "none") |
6936 | (set_attr "length" "0")]) | |
4023fb28 | 6937 | |
9db1d521 | 6938 | ; |
ed9676cf | 6939 | ; sibcall patterns |
9db1d521 HP |
6940 | ; |
6941 | ||
ed9676cf | 6942 | (define_expand "sibcall" |
44b8152b | 6943 | [(call (match_operand 0 "" "") |
ed9676cf | 6944 | (match_operand 1 "" ""))] |
9db1d521 | 6945 | "" |
9db1d521 | 6946 | { |
ed9676cf AK |
6947 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
6948 | DONE; | |
6949 | }) | |
9db1d521 | 6950 | |
ed9676cf | 6951 | (define_insn "*sibcall_br" |
ae156f85 | 6952 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 6953 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 6954 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
6955 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
6956 | "br\t%%r1" | |
6957 | [(set_attr "op_type" "RR") | |
6958 | (set_attr "type" "branch") | |
6959 | (set_attr "atype" "agen")]) | |
9db1d521 | 6960 | |
ed9676cf AK |
6961 | (define_insn "*sibcall_brc" |
6962 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6963 | (match_operand 1 "const_int_operand" "n"))] | |
6964 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
6965 | "j\t%0" | |
6966 | [(set_attr "op_type" "RI") | |
6967 | (set_attr "type" "branch")]) | |
9db1d521 | 6968 | |
ed9676cf AK |
6969 | (define_insn "*sibcall_brcl" |
6970 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6971 | (match_operand 1 "const_int_operand" "n"))] | |
6972 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
6973 | "jg\t%0" | |
6974 | [(set_attr "op_type" "RIL") | |
6975 | (set_attr "type" "branch")]) | |
44b8152b | 6976 | |
ed9676cf AK |
6977 | ; |
6978 | ; sibcall_value patterns | |
6979 | ; | |
9e8327e3 | 6980 | |
ed9676cf AK |
6981 | (define_expand "sibcall_value" |
6982 | [(set (match_operand 0 "" "") | |
6983 | (call (match_operand 1 "" "") | |
6984 | (match_operand 2 "" "")))] | |
6985 | "" | |
6986 | { | |
6987 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 6988 | DONE; |
10bbf137 | 6989 | }) |
9db1d521 | 6990 | |
ed9676cf AK |
6991 | (define_insn "*sibcall_value_br" |
6992 | [(set (match_operand 0 "" "") | |
ae156f85 | 6993 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 6994 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 6995 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
6996 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
6997 | "br\t%%r1" | |
6998 | [(set_attr "op_type" "RR") | |
6999 | (set_attr "type" "branch") | |
7000 | (set_attr "atype" "agen")]) | |
7001 | ||
7002 | (define_insn "*sibcall_value_brc" | |
7003 | [(set (match_operand 0 "" "") | |
7004 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7005 | (match_operand 2 "const_int_operand" "n")))] | |
7006 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7007 | "j\t%1" | |
7008 | [(set_attr "op_type" "RI") | |
7009 | (set_attr "type" "branch")]) | |
7010 | ||
7011 | (define_insn "*sibcall_value_brcl" | |
7012 | [(set (match_operand 0 "" "") | |
7013 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7014 | (match_operand 2 "const_int_operand" "n")))] | |
7015 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7016 | "jg\t%1" | |
7017 | [(set_attr "op_type" "RIL") | |
7018 | (set_attr "type" "branch")]) | |
7019 | ||
7020 | ||
7021 | ; | |
7022 | ; call instruction pattern(s). | |
7023 | ; | |
7024 | ||
7025 | (define_expand "call" | |
7026 | [(call (match_operand 0 "" "") | |
7027 | (match_operand 1 "" "")) | |
7028 | (use (match_operand 2 "" ""))] | |
44b8152b | 7029 | "" |
ed9676cf | 7030 | { |
2f7e5a0d | 7031 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
7032 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
7033 | DONE; | |
7034 | }) | |
44b8152b | 7035 | |
9e8327e3 UW |
7036 | (define_insn "*bras" |
7037 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7038 | (match_operand 1 "const_int_operand" "n")) | |
7039 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7040 | "!SIBLING_CALL_P (insn) |
7041 | && TARGET_SMALL_EXEC | |
ed9676cf | 7042 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 7043 | "bras\t%2,%0" |
9db1d521 | 7044 | [(set_attr "op_type" "RI") |
4023fb28 | 7045 | (set_attr "type" "jsr")]) |
9db1d521 | 7046 | |
9e8327e3 UW |
7047 | (define_insn "*brasl" |
7048 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7049 | (match_operand 1 "const_int_operand" "n")) | |
7050 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7051 | "!SIBLING_CALL_P (insn) |
7052 | && TARGET_CPU_ZARCH | |
ed9676cf | 7053 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7054 | "brasl\t%2,%0" |
7055 | [(set_attr "op_type" "RIL") | |
077dab3b | 7056 | (set_attr "type" "jsr")]) |
9db1d521 | 7057 | |
9e8327e3 UW |
7058 | (define_insn "*basr" |
7059 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
7060 | (match_operand 1 "const_int_operand" "n")) | |
7061 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 7062 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7063 | { |
7064 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7065 | return "basr\t%2,%0"; | |
7066 | else | |
7067 | return "bas\t%2,%a0"; | |
7068 | } | |
7069 | [(set (attr "op_type") | |
7070 | (if_then_else (match_operand 0 "register_operand" "") | |
7071 | (const_string "RR") (const_string "RX"))) | |
7072 | (set_attr "type" "jsr") | |
7073 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7074 | |
7075 | ; | |
7076 | ; call_value instruction pattern(s). | |
7077 | ; | |
7078 | ||
7079 | (define_expand "call_value" | |
44b8152b UW |
7080 | [(set (match_operand 0 "" "") |
7081 | (call (match_operand 1 "" "") | |
7082 | (match_operand 2 "" ""))) | |
7083 | (use (match_operand 3 "" ""))] | |
9db1d521 | 7084 | "" |
9db1d521 | 7085 | { |
2f7e5a0d | 7086 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 7087 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 7088 | DONE; |
10bbf137 | 7089 | }) |
9db1d521 | 7090 | |
9e8327e3 | 7091 | (define_insn "*bras_r" |
c19ec8f9 | 7092 | [(set (match_operand 0 "" "") |
9e8327e3 | 7093 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7094 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 7095 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
7096 | "!SIBLING_CALL_P (insn) |
7097 | && TARGET_SMALL_EXEC | |
ed9676cf | 7098 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7099 | "bras\t%3,%1" |
9db1d521 | 7100 | [(set_attr "op_type" "RI") |
f2d3c02a | 7101 | (set_attr "type" "jsr")]) |
9db1d521 | 7102 | |
9e8327e3 | 7103 | (define_insn "*brasl_r" |
c19ec8f9 | 7104 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7105 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7106 | (match_operand 2 "const_int_operand" "n"))) | |
7107 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
7108 | "!SIBLING_CALL_P (insn) |
7109 | && TARGET_CPU_ZARCH | |
ed9676cf | 7110 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7111 | "brasl\t%3,%1" |
7112 | [(set_attr "op_type" "RIL") | |
077dab3b | 7113 | (set_attr "type" "jsr")]) |
9db1d521 | 7114 | |
9e8327e3 | 7115 | (define_insn "*basr_r" |
c19ec8f9 | 7116 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7117 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7118 | (match_operand 2 "const_int_operand" "n"))) | |
7119 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 7120 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7121 | { |
7122 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7123 | return "basr\t%3,%1"; | |
7124 | else | |
7125 | return "bas\t%3,%a1"; | |
7126 | } | |
7127 | [(set (attr "op_type") | |
7128 | (if_then_else (match_operand 1 "register_operand" "") | |
7129 | (const_string "RR") (const_string "RX"))) | |
7130 | (set_attr "type" "jsr") | |
7131 | (set_attr "atype" "agen")]) | |
9db1d521 | 7132 | |
fd3cd001 UW |
7133 | ;; |
7134 | ;;- Thread-local storage support. | |
7135 | ;; | |
7136 | ||
c5aa1d12 | 7137 | (define_expand "get_tp_64" |
ae156f85 | 7138 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] |
fd3cd001 | 7139 | "TARGET_64BIT" |
c5aa1d12 | 7140 | "") |
fd3cd001 | 7141 | |
c5aa1d12 | 7142 | (define_expand "get_tp_31" |
ae156f85 | 7143 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] |
fd3cd001 | 7144 | "!TARGET_64BIT" |
c5aa1d12 | 7145 | "") |
fd3cd001 | 7146 | |
c5aa1d12 | 7147 | (define_expand "set_tp_64" |
ae156f85 AS |
7148 | [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) |
7149 | (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 7150 | "TARGET_64BIT" |
c5aa1d12 | 7151 | "") |
fd3cd001 | 7152 | |
c5aa1d12 | 7153 | (define_expand "set_tp_31" |
ae156f85 AS |
7154 | [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) |
7155 | (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 7156 | "!TARGET_64BIT" |
c5aa1d12 UW |
7157 | "") |
7158 | ||
7159 | (define_insn "*set_tp" | |
ae156f85 | 7160 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
7161 | "" |
7162 | "" | |
7163 | [(set_attr "type" "none") | |
7164 | (set_attr "length" "0")]) | |
c7453384 | 7165 | |
fd3cd001 UW |
7166 | (define_insn "*tls_load_64" |
7167 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7168 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7169 | (match_operand:DI 2 "" "")] | |
7170 | UNSPEC_TLS_LOAD))] | |
7171 | "TARGET_64BIT" | |
d40c829f | 7172 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7173 | [(set_attr "op_type" "RXE")]) |
7174 | ||
7175 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7176 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7177 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7178 | (match_operand:SI 2 "" "")] |
7179 | UNSPEC_TLS_LOAD))] | |
7180 | "!TARGET_64BIT" | |
d3632d41 | 7181 | "@ |
d40c829f UW |
7182 | l\t%0,%1%J2 |
7183 | ly\t%0,%1%J2" | |
d3632d41 | 7184 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 | 7185 | |
9e8327e3 | 7186 | (define_insn "*bras_tls" |
c19ec8f9 | 7187 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7188 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7189 | (match_operand 2 "const_int_operand" "n"))) | |
7190 | (clobber (match_operand 3 "register_operand" "=r")) | |
7191 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7192 | "!SIBLING_CALL_P (insn) |
7193 | && TARGET_SMALL_EXEC | |
ed9676cf | 7194 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7195 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7196 | [(set_attr "op_type" "RI") |
7197 | (set_attr "type" "jsr")]) | |
7198 | ||
9e8327e3 | 7199 | (define_insn "*brasl_tls" |
c19ec8f9 | 7200 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7201 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7202 | (match_operand 2 "const_int_operand" "n"))) | |
7203 | (clobber (match_operand 3 "register_operand" "=r")) | |
7204 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7205 | "!SIBLING_CALL_P (insn) |
7206 | && TARGET_CPU_ZARCH | |
ed9676cf | 7207 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7208 | "brasl\t%3,%1%J4" |
7209 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7210 | (set_attr "type" "jsr")]) |
7211 | ||
9e8327e3 | 7212 | (define_insn "*basr_tls" |
c19ec8f9 | 7213 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7214 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7215 | (match_operand 2 "const_int_operand" "n"))) | |
7216 | (clobber (match_operand 3 "register_operand" "=r")) | |
7217 | (use (match_operand 4 "" ""))] | |
ed9676cf | 7218 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7219 | { |
7220 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7221 | return "basr\t%3,%1%J4"; | |
7222 | else | |
7223 | return "bas\t%3,%a1%J4"; | |
7224 | } | |
7225 | [(set (attr "op_type") | |
7226 | (if_then_else (match_operand 1 "register_operand" "") | |
7227 | (const_string "RR") (const_string "RX"))) | |
7228 | (set_attr "type" "jsr") | |
7229 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7230 | |
e0374221 AS |
7231 | ;; |
7232 | ;;- Atomic operations | |
7233 | ;; | |
7234 | ||
7235 | ; | |
7236 | ; memory barrier pattern. | |
7237 | ; | |
7238 | ||
7239 | (define_expand "memory_barrier" | |
7240 | [(set (mem:BLK (match_dup 0)) | |
7241 | (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))] | |
7242 | "" | |
7243 | { | |
7244 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
7245 | MEM_VOLATILE_P (operands[0]) = 1; | |
7246 | }) | |
7247 | ||
7248 | (define_insn "*memory_barrier" | |
7249 | [(set (match_operand:BLK 0 "" "") | |
7250 | (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))] | |
7251 | "" | |
7252 | "bcr\t15,0" | |
7253 | [(set_attr "op_type" "RR")]) | |
7254 | ||
7255 | ; | |
7256 | ; compare and swap patterns. | |
7257 | ; | |
7258 | ||
8006eaa6 AS |
7259 | (define_expand "sync_compare_and_swap<mode>" |
7260 | [(parallel | |
7261 | [(set (match_operand:TDSI 0 "register_operand" "") | |
7262 | (match_operand:TDSI 1 "memory_operand" "")) | |
7263 | (set (match_dup 1) | |
7264 | (unspec_volatile:TDSI | |
7265 | [(match_dup 1) | |
7266 | (match_operand:TDSI 2 "register_operand" "") | |
7267 | (match_operand:TDSI 3 "register_operand" "")] | |
7268 | UNSPECV_CAS)) | |
7269 | (set (reg:CCZ1 CC_REGNUM) | |
7270 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
7271 | "") | |
e0374221 AS |
7272 | |
7273 | (define_expand "sync_compare_and_swap_cc<mode>" | |
7274 | [(parallel | |
8006eaa6 AS |
7275 | [(set (match_operand:TDSI 0 "register_operand" "") |
7276 | (match_operand:TDSI 1 "memory_operand" "")) | |
e0374221 | 7277 | (set (match_dup 1) |
8006eaa6 | 7278 | (unspec_volatile:TDSI |
e0374221 | 7279 | [(match_dup 1) |
8006eaa6 AS |
7280 | (match_operand:TDSI 2 "register_operand" "") |
7281 | (match_operand:TDSI 3 "register_operand" "")] | |
e0374221 AS |
7282 | UNSPECV_CAS)) |
7283 | (set (match_dup 4) | |
69950452 | 7284 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] |
e0374221 AS |
7285 | "" |
7286 | { | |
8006eaa6 | 7287 | /* Emulate compare. */ |
69950452 | 7288 | operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
e0374221 AS |
7289 | s390_compare_op0 = operands[1]; |
7290 | s390_compare_op1 = operands[2]; | |
7291 | s390_compare_emitted = operands[4]; | |
7292 | }) | |
7293 | ||
8006eaa6 AS |
7294 | (define_insn "*sync_compare_and_swap<mode>" |
7295 | [(set (match_operand:DP 0 "register_operand" "=r") | |
7296 | (match_operand:DP 1 "memory_operand" "+Q")) | |
7297 | (set (match_dup 1) | |
7298 | (unspec_volatile:DP | |
7299 | [(match_dup 1) | |
7300 | (match_operand:DP 2 "register_operand" "0") | |
7301 | (match_operand:DP 3 "register_operand" "r")] | |
7302 | UNSPECV_CAS)) | |
7303 | (set (reg:CCZ1 CC_REGNUM) | |
7304 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
7305 | "" | |
7306 | "cds<tg>\t%0,%3,%S1" | |
7307 | [(set_attr "op_type" "RS<TE>") | |
7308 | (set_attr "type" "sem")]) | |
7309 | ||
7310 | (define_insn "*sync_compare_and_swap<mode>" | |
e0374221 AS |
7311 | [(set (match_operand:GPR 0 "register_operand" "=r") |
7312 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
7313 | (set (match_dup 1) | |
7314 | (unspec_volatile:GPR | |
7315 | [(match_dup 1) | |
7316 | (match_operand:GPR 2 "register_operand" "0") | |
7317 | (match_operand:GPR 3 "register_operand" "r")] | |
7318 | UNSPECV_CAS)) | |
69950452 AS |
7319 | (set (reg:CCZ1 CC_REGNUM) |
7320 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
e0374221 AS |
7321 | "" |
7322 | "cs<g>\t%0,%3,%S1" | |
7323 | [(set_attr "op_type" "RS<E>") | |
7324 | (set_attr "type" "sem")]) | |
7325 | ||
7326 | ||
9db1d521 HP |
7327 | ;; |
7328 | ;;- Miscellaneous instructions. | |
7329 | ;; | |
7330 | ||
7331 | ; | |
7332 | ; allocate stack instruction pattern(s). | |
7333 | ; | |
7334 | ||
7335 | (define_expand "allocate_stack" | |
ef44a6ff UW |
7336 | [(match_operand 0 "general_operand" "") |
7337 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 7338 | "TARGET_BACKCHAIN" |
9db1d521 | 7339 | { |
ef44a6ff | 7340 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 7341 | |
ef44a6ff UW |
7342 | emit_move_insn (temp, s390_back_chain_rtx ()); |
7343 | anti_adjust_stack (operands[1]); | |
7344 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 7345 | |
ef44a6ff UW |
7346 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
7347 | DONE; | |
10bbf137 | 7348 | }) |
9db1d521 HP |
7349 | |
7350 | ||
7351 | ; | |
43ab026f | 7352 | ; setjmp instruction pattern. |
9db1d521 HP |
7353 | ; |
7354 | ||
9db1d521 | 7355 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7356 | [(match_operand 0 "" "")] |
f314b9b1 | 7357 | "flag_pic" |
9db1d521 | 7358 | { |
585539a1 | 7359 | emit_insn (s390_load_got ()); |
fd7643fb | 7360 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
9db1d521 | 7361 | DONE; |
fd7643fb | 7362 | }) |
9db1d521 | 7363 | |
9db1d521 HP |
7364 | ;; These patterns say how to save and restore the stack pointer. We need not |
7365 | ;; save the stack pointer at function level since we are careful to | |
7366 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7367 | ;; when we restore the stack pointer. | |
7368 | ;; | |
7369 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7370 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7371 | ;; save area is a memory location. | |
7372 | ||
7373 | (define_expand "save_stack_function" | |
7374 | [(match_operand 0 "general_operand" "") | |
7375 | (match_operand 1 "general_operand" "")] | |
7376 | "" | |
7377 | "DONE;") | |
7378 | ||
7379 | (define_expand "restore_stack_function" | |
7380 | [(match_operand 0 "general_operand" "") | |
7381 | (match_operand 1 "general_operand" "")] | |
7382 | "" | |
7383 | "DONE;") | |
7384 | ||
7385 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
7386 | [(match_operand 0 "register_operand" "") |
7387 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 7388 | "TARGET_BACKCHAIN" |
9db1d521 | 7389 | { |
ef44a6ff UW |
7390 | rtx temp = gen_reg_rtx (Pmode); |
7391 | ||
7392 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
7393 | emit_move_insn (operands[0], operands[1]); | |
7394 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7395 | ||
7396 | DONE; | |
10bbf137 | 7397 | }) |
9db1d521 HP |
7398 | |
7399 | (define_expand "save_stack_nonlocal" | |
7400 | [(match_operand 0 "memory_operand" "") | |
7401 | (match_operand 1 "register_operand" "")] | |
7402 | "" | |
9db1d521 | 7403 | { |
ef44a6ff UW |
7404 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
7405 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
7406 | ||
7407 | /* Copy the backchain to the first word, sp to the second and the | |
7408 | literal pool base to the third. */ | |
7409 | ||
b3d31392 | 7410 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7411 | { |
7412 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
7413 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
7414 | } | |
7415 | ||
7416 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
7417 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 7418 | |
9db1d521 | 7419 | DONE; |
10bbf137 | 7420 | }) |
9db1d521 HP |
7421 | |
7422 | (define_expand "restore_stack_nonlocal" | |
7423 | [(match_operand 0 "register_operand" "") | |
7424 | (match_operand 1 "memory_operand" "")] | |
7425 | "" | |
9db1d521 | 7426 | { |
ef44a6ff | 7427 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 7428 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 7429 | rtx temp = NULL_RTX; |
9db1d521 | 7430 | |
43ab026f | 7431 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 7432 | literal pool base from the third. */ |
43ab026f | 7433 | |
b3d31392 | 7434 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7435 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
7436 | ||
7437 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
7438 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
7439 | ||
7440 | if (temp) | |
7441 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7442 | ||
7443 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
9db1d521 | 7444 | DONE; |
10bbf137 | 7445 | }) |
9db1d521 | 7446 | |
7bcebb25 AK |
7447 | (define_expand "exception_receiver" |
7448 | [(const_int 0)] | |
7449 | "" | |
7450 | { | |
7451 | s390_set_has_landing_pad_p (true); | |
7452 | DONE; | |
7453 | }) | |
9db1d521 HP |
7454 | |
7455 | ; | |
7456 | ; nop instruction pattern(s). | |
7457 | ; | |
7458 | ||
7459 | (define_insn "nop" | |
7460 | [(const_int 0)] | |
7461 | "" | |
d40c829f | 7462 | "lr\t0,0" |
9db1d521 HP |
7463 | [(set_attr "op_type" "RR")]) |
7464 | ||
7465 | ||
7466 | ; | |
7467 | ; Special literal pool access instruction pattern(s). | |
7468 | ; | |
7469 | ||
416cf582 UW |
7470 | (define_insn "*pool_entry" |
7471 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7472 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7473 | "" |
9db1d521 | 7474 | { |
416cf582 UW |
7475 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7476 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 7477 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
7478 | return ""; |
7479 | } | |
b628bd8e | 7480 | [(set (attr "length") |
416cf582 | 7481 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 7482 | |
9bb86f41 UW |
7483 | (define_insn "pool_align" |
7484 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
7485 | UNSPECV_POOL_ALIGN)] | |
7486 | "" | |
7487 | ".align\t%0" | |
b628bd8e | 7488 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 7489 | |
9bb86f41 UW |
7490 | (define_insn "pool_section_start" |
7491 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
7492 | "" | |
7493 | ".section\t.rodata" | |
b628bd8e | 7494 | [(set_attr "length" "0")]) |
b2ccb744 | 7495 | |
9bb86f41 UW |
7496 | (define_insn "pool_section_end" |
7497 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
7498 | "" | |
b2ccb744 | 7499 | ".previous" |
b628bd8e | 7500 | [(set_attr "length" "0")]) |
b2ccb744 | 7501 | |
5af2f3d3 | 7502 | (define_insn "main_base_31_small" |
9e8327e3 UW |
7503 | [(set (match_operand 0 "register_operand" "=a") |
7504 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7505 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7506 | "basr\t%0,0" |
7507 | [(set_attr "op_type" "RR") | |
7508 | (set_attr "type" "la")]) | |
7509 | ||
7510 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
7511 | [(set (match_operand 0 "register_operand" "=a") |
7512 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 7513 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 7514 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
7515 | "bras\t%0,%2" |
7516 | [(set_attr "op_type" "RI")]) | |
7517 | ||
7518 | (define_insn "main_base_64" | |
9e8327e3 UW |
7519 | [(set (match_operand 0 "register_operand" "=a") |
7520 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7521 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7522 | "larl\t%0,%1" |
7523 | [(set_attr "op_type" "RIL") | |
7524 | (set_attr "type" "larl")]) | |
7525 | ||
7526 | (define_insn "main_pool" | |
585539a1 UW |
7527 | [(set (match_operand 0 "register_operand" "=a") |
7528 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
7529 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
7530 | { |
7531 | gcc_unreachable (); | |
7532 | } | |
b628bd8e | 7533 | [(set (attr "type") |
ea77e738 UW |
7534 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
7535 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 7536 | |
aee4e0db | 7537 | (define_insn "reload_base_31" |
9e8327e3 UW |
7538 | [(set (match_operand 0 "register_operand" "=a") |
7539 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7540 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7541 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
7542 | [(set_attr "length" "6") |
7543 | (set_attr "type" "la")]) | |
b2ccb744 | 7544 | |
aee4e0db | 7545 | (define_insn "reload_base_64" |
9e8327e3 UW |
7546 | [(set (match_operand 0 "register_operand" "=a") |
7547 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7548 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7549 | "larl\t%0,%1" |
aee4e0db | 7550 | [(set_attr "op_type" "RIL") |
077dab3b | 7551 | (set_attr "type" "larl")]) |
aee4e0db | 7552 | |
aee4e0db | 7553 | (define_insn "pool" |
fd7643fb | 7554 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 7555 | "" |
8d933e31 AS |
7556 | { |
7557 | gcc_unreachable (); | |
7558 | } | |
b628bd8e | 7559 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 7560 | |
4023fb28 UW |
7561 | ;; |
7562 | ;; Insns related to generating the function prologue and epilogue. | |
7563 | ;; | |
7564 | ||
7565 | ||
7566 | (define_expand "prologue" | |
7567 | [(use (const_int 0))] | |
7568 | "" | |
10bbf137 | 7569 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
7570 | |
7571 | (define_expand "epilogue" | |
7572 | [(use (const_int 1))] | |
7573 | "" | |
ed9676cf AK |
7574 | "s390_emit_epilogue (false); DONE;") |
7575 | ||
7576 | (define_expand "sibcall_epilogue" | |
7577 | [(use (const_int 0))] | |
7578 | "" | |
7579 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 7580 | |
9e8327e3 | 7581 | (define_insn "*return" |
4023fb28 | 7582 | [(return) |
9e8327e3 UW |
7583 | (use (match_operand 0 "register_operand" "a"))] |
7584 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7585 | "br\t%0" |
4023fb28 | 7586 | [(set_attr "op_type" "RR") |
c7453384 | 7587 | (set_attr "type" "jsr") |
077dab3b | 7588 | (set_attr "atype" "agen")]) |
4023fb28 | 7589 | |
4023fb28 | 7590 | |
c7453384 | 7591 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 7592 | ;; pointer. This is used for compatibility. |
c7453384 EC |
7593 | |
7594 | (define_expand "ptr_extend" | |
7595 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7596 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7597 | "TARGET_64BIT" |
c7453384 | 7598 | { |
c7453384 EC |
7599 | emit_insn (gen_anddi3 (operands[0], |
7600 | gen_lowpart (DImode, operands[1]), | |
7601 | GEN_INT (0x7fffffff))); | |
c7453384 | 7602 | DONE; |
10bbf137 | 7603 | }) |
4798630c D |
7604 | |
7605 | ;; Instruction definition to expand eh_return macro to support | |
7606 | ;; swapping in special linkage return addresses. | |
7607 | ||
7608 | (define_expand "eh_return" | |
7609 | [(use (match_operand 0 "register_operand" ""))] | |
7610 | "TARGET_TPF" | |
7611 | { | |
7612 | s390_emit_tpf_eh_return (operands[0]); | |
7613 | DONE; | |
7614 | }) | |
7615 | ||
7b8acc34 AK |
7616 | ; |
7617 | ; Stack Protector Patterns | |
7618 | ; | |
7619 | ||
7620 | (define_expand "stack_protect_set" | |
7621 | [(set (match_operand 0 "memory_operand" "") | |
7622 | (match_operand 1 "memory_operand" ""))] | |
7623 | "" | |
7624 | { | |
7625 | #ifdef TARGET_THREAD_SSP_OFFSET | |
7626 | operands[1] | |
7627 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
7628 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
7629 | #endif | |
7630 | if (TARGET_64BIT) | |
7631 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
7632 | else | |
7633 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
7634 | ||
7635 | DONE; | |
7636 | }) | |
7637 | ||
7638 | (define_insn "stack_protect_set<mode>" | |
7639 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
7640 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
7641 | "" | |
7642 | "mvc\t%O0(%G0,%R0),%S1" | |
7643 | [(set_attr "op_type" "SS")]) | |
7644 | ||
7645 | (define_expand "stack_protect_test" | |
7646 | [(set (reg:CC CC_REGNUM) | |
7647 | (compare (match_operand 0 "memory_operand" "") | |
7648 | (match_operand 1 "memory_operand" ""))) | |
7649 | (match_operand 2 "" "")] | |
7650 | "" | |
7651 | { | |
7652 | #ifdef TARGET_THREAD_SSP_OFFSET | |
7653 | operands[1] | |
7654 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
7655 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
7656 | #endif | |
7657 | s390_compare_op0 = operands[0]; | |
7658 | s390_compare_op1 = operands[1]; | |
7659 | s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM); | |
7660 | ||
7661 | if (TARGET_64BIT) | |
7662 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
7663 | else | |
7664 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
7665 | ||
7666 | emit_jump_insn (gen_beq (operands[2])); | |
7667 | ||
7668 | DONE; | |
7669 | }) | |
7670 | ||
7671 | (define_insn "stack_protect_test<mode>" | |
7672 | [(set (reg:CCZ CC_REGNUM) | |
7673 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
7674 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
7675 | "" | |
7676 | "clc\t%O0(%G0,%R0),%S1" | |
7677 | [(set_attr "op_type" "SS")]) |