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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
283334f0 KH |
2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 |
3 | ;; Free Software Foundation, Inc. | |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a UW |
20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
21 | ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | ;; 02111-1307, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
28 | ;; d -- Any register from 0 to 15. | |
29 | ;; I -- An 8-bit constant (0..255). | |
30 | ;; J -- A 12-bit constant (0..4095). | |
31 | ;; K -- A 16-bit constant (-32768..32767). | |
2f7e5a0d | 32 | ;; L -- Value appropriate as displacement. |
f19a9af7 AK |
33 | ;; (0..4095) for short displacement |
34 | ;; (-524288..524287) for long displacement | |
35 | ;; M -- Constant integer with a value of 0x7fffffff. | |
36 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
37 | ;; 0..9: number of the part counting from most to least significant | |
38 | ;; H,Q: mode of the part | |
39 | ;; D,S,H: mode of the containing operand | |
40 | ;; 0,F: value of the other parts (F - all bits set) | |
2f7e5a0d | 41 | ;; |
f19a9af7 AK |
42 | ;; The constraint matches if the specified part of a constant |
43 | ;; has a value different from its other parts. | |
44 | ;; Q -- Memory reference without index register and with short displacement. | |
45 | ;; R -- Memory reference with index register and short displacement. | |
46 | ;; S -- Memory reference without index register but with long displacement. | |
47 | ;; T -- Memory reference with index register and long displacement. | |
48 | ;; U -- Pointer with short displacement. | |
49 | ;; W -- Pointer with long displacement. | |
50 | ;; Y -- Shift count operand. | |
9db1d521 HP |
51 | ;; |
52 | ;; Special formats used for outputting 390 instructions. | |
53 | ;; | |
f19a9af7 AK |
54 | ;; %C: print opcode suffix for branch condition. |
55 | ;; %D: print opcode suffix for inverse branch condition. | |
56 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
57 | ;; %O: print only the displacement of a memory reference. | |
58 | ;; %R: print only the base register of a memory reference. | |
59 | ;; %N: print the second word of a DImode operand. | |
60 | ;; %M: print the second word of a TImode operand. | |
61 | ||
62 | ;; %b: print integer X as if it's an unsigned byte. | |
63 | ;; %x: print integer X as if it's an unsigned word. | |
64 | ;; %h: print integer X as if it's a signed word. | |
65 | ;; %i: print the first nonzero HImode part of X | |
66 | ;; %j: print the first HImode part unequal to 0xffff of X | |
67 | ||
9db1d521 HP |
68 | ;; |
69 | ;; We have a special constraint for pattern matching. | |
70 | ;; | |
71 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
72 | ;; | |
9db1d521 | 73 | |
fd3cd001 UW |
74 | ;; |
75 | ;; UNSPEC usage | |
76 | ;; | |
77 | ||
78 | (define_constants | |
10bbf137 UW |
79 | [; Miscellaneous |
80 | (UNSPEC_ROUND 1) | |
81 | (UNSPEC_SETHIGH 10) | |
82 | ||
83 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
84 | (UNSPEC_LTREL_OFFSET 100) |
85 | (UNSPEC_LTREL_BASE 101) | |
86 | (UNSPEC_GOTENT 110) | |
87 | (UNSPEC_GOT 111) | |
88 | (UNSPEC_GOTOFF 112) | |
89 | (UNSPEC_PLT 113) | |
90 | (UNSPEC_PLTOFF 114) | |
91 | ||
92 | ; Literal pool | |
93 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 94 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 95 | (UNSPEC_LTREF 212) |
fd7643fb UW |
96 | |
97 | ; TLS relocation specifiers | |
fd3cd001 UW |
98 | (UNSPEC_TLSGD 500) |
99 | (UNSPEC_TLSLDM 501) | |
100 | (UNSPEC_NTPOFF 502) | |
101 | (UNSPEC_DTPOFF 503) | |
102 | (UNSPEC_GOTNTPOFF 504) | |
103 | (UNSPEC_INDNTPOFF 505) | |
104 | ||
105 | ; TLS support | |
106 | (UNSPEC_TP 510) | |
107 | (UNSPEC_TLSLDM_NTPOFF 511) | |
108 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
109 | |
110 | ; String Functions | |
111 | (UNSPEC_SRST 600) | |
fd3cd001 UW |
112 | ]) |
113 | ||
114 | ;; | |
115 | ;; UNSPEC_VOLATILE usage | |
116 | ;; | |
117 | ||
118 | (define_constants | |
10bbf137 UW |
119 | [; Blockage |
120 | (UNSPECV_BLOCKAGE 0) | |
121 | ||
2f7e5a0d EC |
122 | ; TPF Support |
123 | (UNSPECV_TPF_PROLOGUE 20) | |
124 | (UNSPECV_TPF_EPILOGUE 21) | |
125 | ||
10bbf137 | 126 | ; Literal pool |
fd7643fb UW |
127 | (UNSPECV_POOL 200) |
128 | (UNSPECV_POOL_START 201) | |
129 | (UNSPECV_POOL_END 202) | |
416cf582 | 130 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
131 | (UNSPECV_MAIN_POOL 300) |
132 | ||
133 | ; TLS support | |
fd3cd001 UW |
134 | (UNSPECV_SET_TP 500) |
135 | ]) | |
136 | ||
137 | ||
1fec52be | 138 | ;; Processor type. This attribute must exactly match the processor_type |
64e1e4c4 SB |
139 | ;; enumeration in s390.h. The current machine description does not |
140 | ;; distinguish between g5 and g6, but there are differences between the two | |
141 | ;; CPUs could in theory be modeled. | |
1fec52be | 142 | |
f13e0d4e UW |
143 | (define_attr "cpu" "g5,g6,z900,z990" |
144 | (const (symbol_ref "s390_tune"))) | |
9db1d521 | 145 | |
f2d3c02a HP |
146 | ;; Define an insn type attribute. This is used in function unit delay |
147 | ;; computations. | |
9db1d521 | 148 | |
077dab3b HP |
149 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
150 | cs,vs,store,imul,idiv, | |
151 | branch,jsr,fsimpd,fsimps, | |
152 | floadd,floads,fstored, fstores, | |
153 | fmuld,fmuls,fdivd,fdivs, | |
154 | ftoi,itof,fsqrtd,fsqrts, | |
155 | other,o2,o3" | |
c7453384 | 156 | (const_string "integer")) |
9db1d521 | 157 | |
077dab3b | 158 | ;; Operand type. Used to default length attribute values |
9db1d521 | 159 | |
077dab3b | 160 | (define_attr "op_type" |
d3632d41 | 161 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" |
077dab3b HP |
162 | (const_string "RX")) |
163 | ||
164 | ;; Insn are devide in two classes: | |
165 | ;; agen: Insn using agen | |
166 | ;; reg: Insn not using agen | |
167 | ||
168 | (define_attr "atype" "agen,reg" | |
169 | (cond [ (eq_attr "op_type" "E") (const_string "reg") | |
170 | (eq_attr "op_type" "RR") (const_string "reg") | |
171 | (eq_attr "op_type" "RX") (const_string "agen") | |
172 | (eq_attr "op_type" "RI") (const_string "reg") | |
173 | (eq_attr "op_type" "RRE") (const_string "reg") | |
174 | (eq_attr "op_type" "RS") (const_string "agen") | |
175 | (eq_attr "op_type" "RSI") (const_string "agen") | |
176 | (eq_attr "op_type" "S") (const_string "agen") | |
177 | (eq_attr "op_type" "SI") (const_string "agen") | |
178 | (eq_attr "op_type" "SS") (const_string "agen") | |
179 | (eq_attr "op_type" "SSE") (const_string "agen") | |
180 | (eq_attr "op_type" "RXE") (const_string "agen") | |
181 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
182 | (eq_attr "op_type" "RIL") (const_string "agen") |
183 | (eq_attr "op_type" "RXY") (const_string "agen") | |
184 | (eq_attr "op_type" "RSY") (const_string "agen") | |
185 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
077dab3b | 186 | (const_string "reg"))) |
9db1d521 | 187 | |
64e1e4c4 SB |
188 | ;; Pipeline description for z900. For lack of anything better, |
189 | ;; this description is also used for the g5 and g6. | |
077dab3b | 190 | (include "2064.md") |
64e1e4c4 SB |
191 | |
192 | ;; Pipeline description for z990. | |
52609473 | 193 | (include "2084.md") |
9db1d521 HP |
194 | |
195 | ;; Length in bytes. | |
196 | ||
197 | (define_attr "length" "" | |
198 | (cond [ (eq_attr "op_type" "E") (const_int 2) | |
199 | (eq_attr "op_type" "RR") (const_int 2) | |
200 | (eq_attr "op_type" "RX") (const_int 4) | |
201 | (eq_attr "op_type" "RI") (const_int 4) | |
202 | (eq_attr "op_type" "RRE") (const_int 4) | |
203 | (eq_attr "op_type" "RS") (const_int 4) | |
204 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
205 | (eq_attr "op_type" "S") (const_int 4) |
206 | (eq_attr "op_type" "SI") (const_int 4) | |
207 | (eq_attr "op_type" "SS") (const_int 6) | |
208 | (eq_attr "op_type" "SSE") (const_int 6) | |
209 | (eq_attr "op_type" "RXE") (const_int 6) | |
210 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
211 | (eq_attr "op_type" "RIL") (const_int 6) |
212 | (eq_attr "op_type" "RXY") (const_int 6) | |
213 | (eq_attr "op_type" "RSY") (const_int 6) | |
214 | (eq_attr "op_type" "SIY") (const_int 6)] | |
9db1d521 HP |
215 | (const_int 4))) |
216 | ||
217 | ;; Define attributes for `asm' insns. | |
218 | ||
f2d3c02a | 219 | (define_asm_attributes [(set_attr "type" "other") |
9db1d521 HP |
220 | (set_attr "op_type" "NN")]) |
221 | ||
222 | ;; | |
223 | ;; Condition Codes | |
224 | ;; | |
225 | ; | |
226 | ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) | |
227 | ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) | |
228 | ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) | |
229 | ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) | |
230 | ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) | |
c7453384 | 231 | |
9db1d521 HP |
232 | ; CCZ -> CCL / CCZ1 |
233 | ; CCZ1 -> CCA/CCU/CCS/CCT | |
234 | ; CCS -> CCA | |
c7453384 | 235 | |
9db1d521 HP |
236 | ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST |
237 | ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT | |
238 | ||
239 | ||
240 | ;; | |
241 | ;;- Compare instructions. | |
242 | ;; | |
243 | ||
244 | (define_expand "cmpdi" | |
245 | [(set (reg:CC 33) | |
246 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
247 | (match_operand:DI 1 "general_operand" "")))] | |
248 | "TARGET_64BIT" | |
9db1d521 HP |
249 | { |
250 | s390_compare_op0 = operands[0]; | |
251 | s390_compare_op1 = operands[1]; | |
252 | DONE; | |
10bbf137 | 253 | }) |
9db1d521 HP |
254 | |
255 | (define_expand "cmpsi" | |
256 | [(set (reg:CC 33) | |
257 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
258 | (match_operand:SI 1 "general_operand" "")))] | |
259 | "" | |
9db1d521 HP |
260 | { |
261 | s390_compare_op0 = operands[0]; | |
262 | s390_compare_op1 = operands[1]; | |
263 | DONE; | |
10bbf137 | 264 | }) |
9db1d521 | 265 | |
9db1d521 HP |
266 | (define_expand "cmpdf" |
267 | [(set (reg:CC 33) | |
268 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
269 | (match_operand:DF 1 "general_operand" "")))] | |
270 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
271 | { |
272 | s390_compare_op0 = operands[0]; | |
273 | s390_compare_op1 = operands[1]; | |
274 | DONE; | |
10bbf137 | 275 | }) |
9db1d521 HP |
276 | |
277 | (define_expand "cmpsf" | |
278 | [(set (reg:CC 33) | |
279 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
280 | (match_operand:SF 1 "general_operand" "")))] | |
281 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
282 | { |
283 | s390_compare_op0 = operands[0]; | |
284 | s390_compare_op1 = operands[1]; | |
285 | DONE; | |
10bbf137 | 286 | }) |
9db1d521 HP |
287 | |
288 | ||
07893d4f | 289 | ; Test-under-Mask (zero_extract) instructions |
9db1d521 | 290 | |
07893d4f | 291 | (define_insn "*tmdi_ext" |
9db1d521 HP |
292 | [(set (reg 33) |
293 | (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d") | |
4023fb28 UW |
294 | (match_operand:DI 1 "const_int_operand" "n") |
295 | (match_operand:DI 2 "const_int_operand" "n")) | |
9db1d521 | 296 | (const_int 0)))] |
4023fb28 | 297 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
c7453384 | 298 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
4023fb28 UW |
299 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 |
300 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
301 | == INTVAL (operands[2]) >> 4" | |
9db1d521 | 302 | { |
4023fb28 UW |
303 | int part = INTVAL (operands[2]) >> 4; |
304 | int block = (1 << INTVAL (operands[1])) - 1; | |
305 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
9db1d521 | 306 | |
4023fb28 | 307 | operands[2] = GEN_INT (block << shift); |
9db1d521 | 308 | |
4023fb28 UW |
309 | switch (part) |
310 | { | |
d40c829f UW |
311 | case 0: return "tmhh\t%0,%x2"; |
312 | case 1: return "tmhl\t%0,%x2"; | |
313 | case 2: return "tmlh\t%0,%x2"; | |
314 | case 3: return "tmll\t%0,%x2"; | |
4023fb28 UW |
315 | default: abort (); |
316 | } | |
10bbf137 | 317 | } |
4023fb28 UW |
318 | [(set_attr "op_type" "RI")]) |
319 | ||
07893d4f | 320 | (define_insn "*tmsi_ext" |
9db1d521 | 321 | [(set (reg 33) |
07893d4f UW |
322 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") |
323 | (match_operand:SI 1 "const_int_operand" "n") | |
324 | (match_operand:SI 2 "const_int_operand" "n")) | |
9db1d521 | 325 | (const_int 0)))] |
07893d4f | 326 | "s390_match_ccmode(insn, CCTmode) |
c7453384 | 327 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
07893d4f UW |
328 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 |
329 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
330 | == INTVAL (operands[2]) >> 4" | |
9db1d521 | 331 | { |
07893d4f UW |
332 | int part = INTVAL (operands[2]) >> 4; |
333 | int block = (1 << INTVAL (operands[1])) - 1; | |
334 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
335 | ||
336 | operands[2] = GEN_INT (block << shift); | |
9db1d521 | 337 | |
4023fb28 | 338 | switch (part) |
9db1d521 | 339 | { |
d40c829f UW |
340 | case 0: return "tmh\t%0,%x2"; |
341 | case 1: return "tml\t%0,%x2"; | |
4023fb28 | 342 | default: abort (); |
9db1d521 | 343 | } |
10bbf137 | 344 | } |
4023fb28 UW |
345 | [(set_attr "op_type" "RI")]) |
346 | ||
19796784 | 347 | (define_insn "*tmqisi_ext" |
4023fb28 | 348 | [(set (reg 33) |
d3632d41 UW |
349 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S") |
350 | (match_operand:SI 1 "const_int_operand" "n,n") | |
351 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
4023fb28 | 352 | (const_int 0)))] |
19796784 | 353 | "!TARGET_64BIT && s390_match_ccmode(insn, CCTmode) |
c7453384 | 354 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
07893d4f | 355 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" |
4023fb28 | 356 | { |
07893d4f UW |
357 | int block = (1 << INTVAL (operands[1])) - 1; |
358 | int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); | |
9db1d521 | 359 | |
07893d4f | 360 | operands[2] = GEN_INT (block << shift); |
d40c829f | 361 | return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; |
10bbf137 | 362 | } |
d3632d41 | 363 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 364 | |
19796784 AK |
365 | (define_insn "*tmqidi_ext" |
366 | [(set (reg 33) | |
367 | (compare (zero_extract:DI (match_operand:QI 0 "memory_operand" "Q,S") | |
368 | (match_operand:SI 1 "const_int_operand" "n,n") | |
369 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
370 | (const_int 0)))] | |
371 | "TARGET_64BIT && s390_match_ccmode(insn, CCTmode) | |
372 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 | |
373 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" | |
374 | { | |
375 | int block = (1 << INTVAL (operands[1])) - 1; | |
376 | int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); | |
377 | ||
378 | operands[2] = GEN_INT (block << shift); | |
379 | return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; | |
380 | } | |
381 | [(set_attr "op_type" "SI,SIY")]) | |
382 | ||
383 | ||
07893d4f | 384 | ; Test-under-Mask instructions |
9db1d521 | 385 | |
07893d4f UW |
386 | (define_insn "*tmdi_mem" |
387 | [(set (reg 33) | |
d3632d41 UW |
388 | (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S") |
389 | (match_operand:DI 1 "immediate_operand" "n,n")) | |
390 | (match_operand:DI 2 "immediate_operand" "n,n")))] | |
9e8327e3 | 391 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
f19a9af7 | 392 | && s390_single_part (operands[1], DImode, QImode, 0) >= 0" |
07893d4f | 393 | { |
f19a9af7 AK |
394 | int part = s390_single_part (operands[1], DImode, QImode, 0); |
395 | operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); | |
07893d4f | 396 | |
c7453384 | 397 | operands[0] = gen_rtx_MEM (QImode, |
07893d4f | 398 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 399 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 400 | } |
d3632d41 | 401 | [(set_attr "op_type" "SI,SIY")]) |
07893d4f UW |
402 | |
403 | (define_insn "*tmsi_mem" | |
4023fb28 | 404 | [(set (reg 33) |
d3632d41 UW |
405 | (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S") |
406 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
407 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 408 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
f19a9af7 | 409 | && s390_single_part (operands[1], SImode, QImode, 0) >= 0" |
4023fb28 | 410 | { |
f19a9af7 AK |
411 | int part = s390_single_part (operands[1], SImode, QImode, 0); |
412 | operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); | |
4023fb28 | 413 | |
c7453384 | 414 | operands[0] = gen_rtx_MEM (QImode, |
4023fb28 | 415 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 416 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 417 | } |
077dab3b | 418 | [(set_attr "op_type" "SI")]) |
9db1d521 | 419 | |
07893d4f | 420 | (define_insn "*tmhi_mem" |
9db1d521 | 421 | [(set (reg 33) |
d3632d41 UW |
422 | (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0) |
423 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
424 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 425 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
f19a9af7 | 426 | && s390_single_part (operands[1], HImode, QImode, 0) >= 0" |
07893d4f | 427 | { |
f19a9af7 AK |
428 | int part = s390_single_part (operands[1], HImode, QImode, 0); |
429 | operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); | |
9db1d521 | 430 | |
c7453384 | 431 | operands[0] = gen_rtx_MEM (QImode, |
07893d4f | 432 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 433 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 434 | } |
077dab3b | 435 | [(set_attr "op_type" "SI")]) |
9db1d521 | 436 | |
07893d4f | 437 | (define_insn "*tmqi_mem" |
9db1d521 | 438 | [(set (reg 33) |
d3632d41 UW |
439 | (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0) |
440 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
441 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 442 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" |
d3632d41 | 443 | "@ |
d40c829f UW |
444 | tm\t%0,%b1 |
445 | tmy\t%0,%b1" | |
d3632d41 | 446 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 447 | |
05b9aaaa UW |
448 | (define_insn "*tmdi_reg" |
449 | [(set (reg 33) | |
f19a9af7 | 450 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 451 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
452 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
453 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa UW |
454 | "TARGET_64BIT |
455 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
f19a9af7 AK |
456 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
457 | "@ | |
458 | tmhh\t%0,%i1 | |
459 | tmhl\t%0,%i1 | |
460 | tmlh\t%0,%i1 | |
461 | tmll\t%0,%i1" | |
05b9aaaa UW |
462 | [(set_attr "op_type" "RI")]) |
463 | ||
464 | (define_insn "*tmsi_reg" | |
465 | [(set (reg 33) | |
f19a9af7 AK |
466 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
467 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
468 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
05b9aaaa | 469 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) |
f19a9af7 AK |
470 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
471 | "@ | |
472 | tmh\t%0,%i1 | |
473 | tml\t%0,%i1" | |
05b9aaaa UW |
474 | [(set_attr "op_type" "RI")]) |
475 | ||
07893d4f | 476 | (define_insn "*tmhi_full" |
9db1d521 | 477 | [(set (reg 33) |
07893d4f UW |
478 | (compare (match_operand:HI 0 "register_operand" "d") |
479 | (match_operand:HI 1 "immediate_operand" "n")))] | |
a556fd39 | 480 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
d40c829f | 481 | "tml\t%0,65535" |
07893d4f | 482 | [(set_attr "op_type" "RX")]) |
9db1d521 | 483 | |
07893d4f | 484 | (define_insn "*tmqi_full" |
9db1d521 | 485 | [(set (reg 33) |
07893d4f UW |
486 | (compare (match_operand:QI 0 "register_operand" "d") |
487 | (match_operand:QI 1 "immediate_operand" "n")))] | |
a556fd39 | 488 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
d40c829f | 489 | "tml\t%0,255" |
07893d4f | 490 | [(set_attr "op_type" "RI")]) |
9db1d521 | 491 | |
07893d4f UW |
492 | |
493 | ; Load-and-Test instructions | |
494 | ||
495 | (define_insn "*tstdi_sign" | |
9db1d521 | 496 | [(set (reg 33) |
07893d4f UW |
497 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
498 | (const_int 32)) (const_int 32)) | |
499 | (match_operand:DI 1 "const0_operand" ""))) | |
500 | (set (match_operand:DI 2 "register_operand" "=d") | |
501 | (sign_extend:DI (match_dup 0)))] | |
502 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 503 | "ltgfr\t%2,%0" |
07893d4f UW |
504 | [(set_attr "op_type" "RRE")]) |
505 | ||
506 | (define_insn "*tstdi" | |
9db1d521 | 507 | [(set (reg 33) |
07893d4f UW |
508 | (compare (match_operand:DI 0 "register_operand" "d") |
509 | (match_operand:DI 1 "const0_operand" ""))) | |
510 | (set (match_operand:DI 2 "register_operand" "=d") | |
511 | (match_dup 0))] | |
512 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 513 | "ltgr\t%2,%0" |
07893d4f | 514 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 515 | |
07893d4f | 516 | (define_insn "*tstdi_cconly" |
9db1d521 | 517 | [(set (reg 33) |
07893d4f UW |
518 | (compare (match_operand:DI 0 "register_operand" "d") |
519 | (match_operand:DI 1 "const0_operand" "")))] | |
520 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 521 | "ltgr\t%0,%0" |
07893d4f | 522 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 523 | |
07893d4f UW |
524 | (define_insn "*tstdi_cconly_31" |
525 | [(set (reg 33) | |
526 | (compare (match_operand:DI 0 "register_operand" "d") | |
527 | (match_operand:DI 1 "const0_operand" "")))] | |
528 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 529 | "srda\t%0,0" |
077dab3b HP |
530 | [(set_attr "op_type" "RS") |
531 | (set_attr "atype" "reg")]) | |
532 | ||
4023fb28 | 533 | |
07893d4f UW |
534 | (define_insn "*tstsi" |
535 | [(set (reg 33) | |
d3632d41 | 536 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 537 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 538 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f UW |
539 | (match_dup 0))] |
540 | "s390_match_ccmode(insn, CCSmode)" | |
541 | "@ | |
d40c829f UW |
542 | ltr\t%2,%0 |
543 | icm\t%2,15,%0 | |
544 | icmy\t%2,15,%0" | |
d3632d41 | 545 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 546 | |
07893d4f | 547 | (define_insn "*tstsi_cconly" |
4023fb28 | 548 | [(set (reg 33) |
d3632d41 | 549 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 550 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 551 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
552 | "s390_match_ccmode(insn, CCSmode)" |
553 | "@ | |
d40c829f UW |
554 | ltr\t%0,%0 |
555 | icm\t%2,15,%0 | |
556 | icmy\t%2,15,%0" | |
d3632d41 | 557 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 558 | |
07893d4f UW |
559 | (define_insn "*tstsi_cconly2" |
560 | [(set (reg 33) | |
561 | (compare (match_operand:SI 0 "register_operand" "d") | |
562 | (match_operand:SI 1 "const0_operand" "")))] | |
563 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 564 | "ltr\t%0,%0" |
07893d4f | 565 | [(set_attr "op_type" "RR")]) |
4023fb28 | 566 | |
3af97654 UW |
567 | (define_insn "*tsthiCCT" |
568 | [(set (reg 33) | |
d3632d41 | 569 | (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 570 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 571 | (set (match_operand:HI 2 "register_operand" "=d,d,0") |
3af97654 UW |
572 | (match_dup 0))] |
573 | "s390_match_ccmode(insn, CCTmode)" | |
574 | "@ | |
d40c829f UW |
575 | icm\t%2,3,%0 |
576 | icmy\t%2,3,%0 | |
577 | tml\t%0,65535" | |
d3632d41 | 578 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
579 | |
580 | (define_insn "*tsthiCCT_cconly" | |
581 | [(set (reg 33) | |
d3632d41 | 582 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 583 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 584 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
585 | "s390_match_ccmode(insn, CCTmode)" |
586 | "@ | |
d40c829f UW |
587 | icm\t%2,3,%0 |
588 | icmy\t%2,3,%0 | |
589 | tml\t%0,65535" | |
d3632d41 | 590 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 591 | |
07893d4f | 592 | (define_insn "*tsthi" |
9db1d521 | 593 | [(set (reg 33) |
d3632d41 | 594 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 595 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 596 | (set (match_operand:HI 2 "register_operand" "=d,d") |
9db1d521 HP |
597 | (match_dup 0))] |
598 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 599 | "@ |
d40c829f UW |
600 | icm\t%2,3,%0 |
601 | icmy\t%2,3,%0" | |
d3632d41 | 602 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 603 | |
07893d4f | 604 | (define_insn "*tsthi_cconly" |
9db1d521 | 605 | [(set (reg 33) |
d3632d41 | 606 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 607 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 608 | (clobber (match_scratch:HI 2 "=d,d"))] |
9db1d521 | 609 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 610 | "@ |
d40c829f UW |
611 | icm\t%2,3,%0 |
612 | icmy\t%2,3,%0" | |
d3632d41 | 613 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 614 | |
3af97654 UW |
615 | (define_insn "*tstqiCCT" |
616 | [(set (reg 33) | |
d3632d41 | 617 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 618 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 619 | (set (match_operand:QI 2 "register_operand" "=d,d,0") |
3af97654 UW |
620 | (match_dup 0))] |
621 | "s390_match_ccmode(insn, CCTmode)" | |
622 | "@ | |
d40c829f UW |
623 | icm\t%2,1,%0 |
624 | icmy\t%2,1,%0 | |
625 | tml\t%0,255" | |
d3632d41 | 626 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
627 | |
628 | (define_insn "*tstqiCCT_cconly" | |
629 | [(set (reg 33) | |
d3632d41 | 630 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
631 | (match_operand:QI 1 "const0_operand" "")))] |
632 | "s390_match_ccmode(insn, CCTmode)" | |
633 | "@ | |
d40c829f UW |
634 | cli\t%0,0 |
635 | cliy\t%0,0 | |
636 | tml\t%0,255" | |
d3632d41 | 637 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 638 | |
07893d4f | 639 | (define_insn "*tstqi" |
9db1d521 | 640 | [(set (reg 33) |
d3632d41 | 641 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 642 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 643 | (set (match_operand:QI 2 "register_operand" "=d,d") |
07893d4f UW |
644 | (match_dup 0))] |
645 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 646 | "@ |
d40c829f UW |
647 | icm\t%2,1,%0 |
648 | icmy\t%2,1,%0" | |
d3632d41 | 649 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 650 | |
07893d4f | 651 | (define_insn "*tstqi_cconly" |
9db1d521 | 652 | [(set (reg 33) |
d3632d41 | 653 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 654 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 655 | (clobber (match_scratch:QI 2 "=d,d"))] |
07893d4f | 656 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 657 | "@ |
d40c829f UW |
658 | icm\t%2,1,%0 |
659 | icmy\t%2,1,%0" | |
d3632d41 UW |
660 | [(set_attr "op_type" "RS,RSY")]) |
661 | ||
9db1d521 | 662 | |
07893d4f | 663 | ; Compare (signed) instructions |
4023fb28 | 664 | |
07893d4f | 665 | (define_insn "*cmpdi_ccs_sign" |
4023fb28 | 666 | [(set (reg 33) |
07893d4f UW |
667 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
668 | (match_operand:DI 0 "register_operand" "d,d")))] | |
669 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 670 | "@ |
d40c829f UW |
671 | cgfr\t%0,%1 |
672 | cgf\t%0,%1" | |
d3632d41 | 673 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 674 | |
07893d4f | 675 | (define_insn "*cmpdi_ccs" |
4023fb28 | 676 | [(set (reg 33) |
07893d4f UW |
677 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
678 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
679 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
680 | "@ | |
d40c829f UW |
681 | cgr\t%0,%1 |
682 | cghi\t%0,%c1 | |
683 | cg\t%0,%1" | |
d3632d41 | 684 | [(set_attr "op_type" "RRE,RI,RXY")]) |
c7453384 | 685 | |
07893d4f UW |
686 | (define_insn "*cmpsi_ccs_sign" |
687 | [(set (reg 33) | |
d3632d41 UW |
688 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
689 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 690 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 691 | "@ |
d40c829f UW |
692 | ch\t%0,%1 |
693 | chy\t%0,%1" | |
d3632d41 | 694 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 695 | |
07893d4f | 696 | (define_insn "*cmpsi_ccs" |
9db1d521 | 697 | [(set (reg 33) |
d3632d41 UW |
698 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
699 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
9db1d521 | 700 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 701 | "@ |
d40c829f UW |
702 | cr\t%0,%1 |
703 | chi\t%0,%c1 | |
704 | c\t%0,%1 | |
705 | cy\t%0,%1" | |
d3632d41 | 706 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
c7453384 | 707 | |
07893d4f UW |
708 | |
709 | ; Compare (unsigned) instructions | |
9db1d521 | 710 | |
07893d4f | 711 | (define_insn "*cmpdi_ccu_zero" |
9db1d521 | 712 | [(set (reg 33) |
07893d4f UW |
713 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
714 | (match_operand:DI 0 "register_operand" "d,d")))] | |
715 | "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT" | |
716 | "@ | |
d40c829f UW |
717 | clgfr\t%0,%1 |
718 | clgf\t%0,%1" | |
d3632d41 | 719 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 720 | |
07893d4f | 721 | (define_insn "*cmpdi_ccu" |
9db1d521 | 722 | [(set (reg 33) |
07893d4f UW |
723 | (compare (match_operand:DI 0 "register_operand" "d,d") |
724 | (match_operand:DI 1 "general_operand" "d,m")))] | |
725 | "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" | |
726 | "@ | |
d40c829f UW |
727 | clgr\t%0,%1 |
728 | clg\t%0,%1" | |
d3632d41 | 729 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 730 | |
07893d4f | 731 | (define_insn "*cmpsi_ccu" |
9db1d521 | 732 | [(set (reg 33) |
d3632d41 UW |
733 | (compare (match_operand:SI 0 "register_operand" "d,d,d") |
734 | (match_operand:SI 1 "general_operand" "d,R,T")))] | |
07893d4f UW |
735 | "s390_match_ccmode(insn, CCUmode)" |
736 | "@ | |
d40c829f UW |
737 | clr\t%0,%1 |
738 | cl\t%0,%1 | |
739 | cly\t%0,%1" | |
d3632d41 | 740 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 741 | |
07893d4f | 742 | (define_insn "*cmphi_ccu" |
9db1d521 | 743 | [(set (reg 33) |
d3632d41 UW |
744 | (compare (match_operand:HI 0 "register_operand" "d,d") |
745 | (match_operand:HI 1 "s_imm_operand" "Q,S")))] | |
9db1d521 | 746 | "s390_match_ccmode(insn, CCUmode)" |
d3632d41 | 747 | "@ |
d40c829f UW |
748 | clm\t%0,3,%1 |
749 | clmy\t%0,3,%1" | |
d3632d41 | 750 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
751 | |
752 | (define_insn "*cmpqi_ccu" | |
753 | [(set (reg 33) | |
d3632d41 UW |
754 | (compare (match_operand:QI 0 "register_operand" "d,d") |
755 | (match_operand:QI 1 "s_imm_operand" "Q,S")))] | |
9db1d521 | 756 | "s390_match_ccmode(insn, CCUmode)" |
d3632d41 | 757 | "@ |
d40c829f UW |
758 | clm\t%0,1,%1 |
759 | clmy\t%0,1,%1" | |
d3632d41 | 760 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 761 | |
07893d4f | 762 | (define_insn "*cli" |
9db1d521 | 763 | [(set (reg 33) |
d3632d41 UW |
764 | (compare (match_operand:QI 0 "memory_operand" "Q,S") |
765 | (match_operand:QI 1 "immediate_operand" "n,n")))] | |
07893d4f | 766 | "s390_match_ccmode (insn, CCUmode)" |
d3632d41 | 767 | "@ |
d40c829f UW |
768 | cli\t%0,%b1 |
769 | cliy\t%0,%b1" | |
d3632d41 | 770 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 771 | |
07893d4f UW |
772 | (define_insn "*cmpdi_ccu_mem" |
773 | [(set (reg 33) | |
ccfc6cc8 UW |
774 | (compare (match_operand:DI 0 "s_operand" "Q") |
775 | (match_operand:DI 1 "s_imm_operand" "Q")))] | |
07893d4f | 776 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 777 | "clc\t%O0(8,%R0),%1" |
077dab3b | 778 | [(set_attr "op_type" "SS")]) |
07893d4f UW |
779 | |
780 | (define_insn "*cmpsi_ccu_mem" | |
781 | [(set (reg 33) | |
ccfc6cc8 UW |
782 | (compare (match_operand:SI 0 "s_operand" "Q") |
783 | (match_operand:SI 1 "s_imm_operand" "Q")))] | |
07893d4f | 784 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 785 | "clc\t%O0(4,%R0),%1" |
077dab3b | 786 | [(set_attr "op_type" "SS")]) |
07893d4f UW |
787 | |
788 | (define_insn "*cmphi_ccu_mem" | |
789 | [(set (reg 33) | |
ccfc6cc8 UW |
790 | (compare (match_operand:HI 0 "s_operand" "Q") |
791 | (match_operand:HI 1 "s_imm_operand" "Q")))] | |
07893d4f | 792 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 793 | "clc\t%O0(2,%R0),%1" |
077dab3b | 794 | [(set_attr "op_type" "SS")]) |
07893d4f | 795 | |
9db1d521 HP |
796 | (define_insn "*cmpqi_ccu_mem" |
797 | [(set (reg 33) | |
ccfc6cc8 UW |
798 | (compare (match_operand:QI 0 "s_operand" "Q") |
799 | (match_operand:QI 1 "s_imm_operand" "Q")))] | |
9db1d521 | 800 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 801 | "clc\t%O0(1,%R0),%1" |
077dab3b | 802 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
803 | |
804 | ||
805 | ; DF instructions | |
806 | ||
807 | (define_insn "*cmpdf_ccs_0" | |
808 | [(set (reg 33) | |
809 | (compare (match_operand:DF 0 "register_operand" "f") | |
810 | (match_operand:DF 1 "const0_operand" "")))] | |
811 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 812 | "ltdbr\t%0,%0" |
077dab3b HP |
813 | [(set_attr "op_type" "RRE") |
814 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
815 | |
816 | (define_insn "*cmpdf_ccs_0_ibm" | |
817 | [(set (reg 33) | |
818 | (compare (match_operand:DF 0 "register_operand" "f") | |
819 | (match_operand:DF 1 "const0_operand" "")))] | |
820 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 821 | "ltdr\t%0,%0" |
077dab3b HP |
822 | [(set_attr "op_type" "RR") |
823 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
824 | |
825 | (define_insn "*cmpdf_ccs" | |
826 | [(set (reg 33) | |
827 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 828 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
829 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
830 | "@ | |
d40c829f UW |
831 | cdbr\t%0,%1 |
832 | cdb\t%0,%1" | |
ce50cae8 | 833 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 834 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
835 | |
836 | (define_insn "*cmpdf_ccs_ibm" | |
837 | [(set (reg 33) | |
838 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 839 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
840 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
841 | "@ | |
d40c829f UW |
842 | cdr\t%0,%1 |
843 | cd\t%0,%1" | |
9db1d521 | 844 | [(set_attr "op_type" "RR,RX") |
077dab3b | 845 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
846 | |
847 | ||
848 | ; SF instructions | |
849 | ||
850 | (define_insn "*cmpsf_ccs_0" | |
851 | [(set (reg 33) | |
852 | (compare (match_operand:SF 0 "register_operand" "f") | |
853 | (match_operand:SF 1 "const0_operand" "")))] | |
854 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 855 | "ltebr\t%0,%0" |
077dab3b HP |
856 | [(set_attr "op_type" "RRE") |
857 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
858 | |
859 | (define_insn "*cmpsf_ccs_0_ibm" | |
860 | [(set (reg 33) | |
861 | (compare (match_operand:SF 0 "register_operand" "f") | |
862 | (match_operand:SF 1 "const0_operand" "")))] | |
863 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 864 | "lter\t%0,%0" |
077dab3b HP |
865 | [(set_attr "op_type" "RR") |
866 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
867 | |
868 | (define_insn "*cmpsf_ccs" | |
869 | [(set (reg 33) | |
870 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 871 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
872 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
873 | "@ | |
d40c829f UW |
874 | cebr\t%0,%1 |
875 | ceb\t%0,%1" | |
077dab3b HP |
876 | [(set_attr "op_type" "RRE,RXE") |
877 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
878 | |
879 | (define_insn "*cmpsf_ccs" | |
880 | [(set (reg 33) | |
881 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 882 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
883 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
884 | "@ | |
d40c829f UW |
885 | cer\t%0,%1 |
886 | ce\t%0,%1" | |
077dab3b HP |
887 | [(set_attr "op_type" "RR,RX") |
888 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
889 | |
890 | ||
891 | ;; | |
892 | ;;- Move instructions. | |
893 | ;; | |
894 | ||
895 | ; | |
896 | ; movti instruction pattern(s). | |
897 | ; | |
898 | ||
899 | (define_insn "movti" | |
d3632d41 UW |
900 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
901 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
9db1d521 | 902 | "TARGET_64BIT" |
4023fb28 | 903 | "@ |
d40c829f UW |
904 | lmg\t%0,%N0,%1 |
905 | stmg\t%1,%N1,%0 | |
4023fb28 | 906 | # |
9b7c75b9 | 907 | # |
d40c829f | 908 | mvc\t%O0(16,%R0),%1" |
d3632d41 | 909 | [(set_attr "op_type" "RSY,RSY,NN,NN,SS") |
fe03d631 | 910 | (set_attr "type" "lm,stm,*,*,cs")]) |
4023fb28 UW |
911 | |
912 | (define_split | |
913 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
914 | (match_operand:TI 1 "general_operand" ""))] | |
915 | "TARGET_64BIT && reload_completed | |
dc65c307 | 916 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
917 | [(set (match_dup 2) (match_dup 4)) |
918 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 919 | { |
dc65c307 UW |
920 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
921 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
922 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
923 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
924 | }) | |
925 | ||
926 | (define_split | |
927 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
928 | (match_operand:TI 1 "general_operand" ""))] | |
929 | "TARGET_64BIT && reload_completed | |
930 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
931 | [(set (match_dup 2) (match_dup 4)) | |
932 | (set (match_dup 3) (match_dup 5))] | |
933 | { | |
934 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
935 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
936 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
937 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
938 | }) | |
4023fb28 UW |
939 | |
940 | (define_split | |
941 | [(set (match_operand:TI 0 "register_operand" "") | |
942 | (match_operand:TI 1 "memory_operand" ""))] | |
943 | "TARGET_64BIT && reload_completed | |
944 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 945 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
946 | { |
947 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
948 | s390_load_address (addr, XEXP (operands[1], 0)); | |
949 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
950 | }) |
951 | ||
952 | (define_expand "reload_outti" | |
953 | [(parallel [(match_operand:TI 0 "memory_operand" "") | |
954 | (match_operand:TI 1 "register_operand" "d") | |
955 | (match_operand:DI 2 "register_operand" "=&a")])] | |
956 | "TARGET_64BIT" | |
957 | { | |
958 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
959 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
960 | emit_move_insn (operands[0], operands[1]); | |
961 | DONE; | |
962 | }) | |
9db1d521 HP |
963 | |
964 | ; | |
965 | ; movdi instruction pattern(s). | |
966 | ; | |
967 | ||
9db1d521 HP |
968 | (define_expand "movdi" |
969 | [(set (match_operand:DI 0 "general_operand" "") | |
970 | (match_operand:DI 1 "general_operand" ""))] | |
971 | "" | |
9db1d521 | 972 | { |
fd3cd001 UW |
973 | /* Handle symbolic constants. */ |
974 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
975 | emit_symbolic_move (operands); | |
4023fb28 UW |
976 | |
977 | /* During and after reload, we need to force constants | |
978 | to the literal pool ourselves, if necessary. */ | |
979 | if ((reload_in_progress || reload_completed) | |
c7453384 | 980 | && CONSTANT_P (operands[1]) |
4023fb28 | 981 | && (!legitimate_reload_constant_p (operands[1]) |
8e509cf9 | 982 | || FP_REG_P (operands[0]))) |
4023fb28 | 983 | operands[1] = force_const_mem (DImode, operands[1]); |
10bbf137 | 984 | }) |
9db1d521 | 985 | |
4023fb28 UW |
986 | (define_insn "*movdi_larl" |
987 | [(set (match_operand:DI 0 "register_operand" "=d") | |
988 | (match_operand:DI 1 "larl_operand" "X"))] | |
989 | "TARGET_64BIT | |
8e509cf9 | 990 | && !FP_REG_P (operands[0])" |
d40c829f | 991 | "larl\t%0,%1" |
4023fb28 | 992 | [(set_attr "op_type" "RIL") |
077dab3b | 993 | (set_attr "type" "larl")]) |
4023fb28 | 994 | |
9db1d521 | 995 | (define_insn "*movdi_64" |
2f7e5a0d | 996 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f19a9af7 | 997 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q") |
2f7e5a0d | 998 | (match_operand:DI 1 "general_operand" |
f19a9af7 | 999 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))] |
9db1d521 HP |
1000 | "TARGET_64BIT" |
1001 | "@ | |
f19a9af7 AK |
1002 | lghi\t%0,%h1 |
1003 | llihh\t%0,%i1 | |
1004 | llihl\t%0,%i1 | |
1005 | llilh\t%0,%i1 | |
1006 | llill\t%0,%i1 | |
1007 | lay\t%0,%a1 | |
d40c829f UW |
1008 | lgr\t%0,%1 |
1009 | lg\t%0,%1 | |
1010 | stg\t%1,%0 | |
1011 | ldr\t%0,%1 | |
1012 | ld\t%0,%1 | |
1013 | ldy\t%0,%1 | |
1014 | std\t%1,%0 | |
1015 | stdy\t%1,%0 | |
1016 | mvc\t%O0(8,%R0),%1" | |
f19a9af7 AK |
1017 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS") |
1018 | (set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd, | |
1019 | fstored,fstored,cs")]) | |
9db1d521 HP |
1020 | |
1021 | (define_insn "*movdi_31" | |
d3632d41 UW |
1022 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
1023 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
9db1d521 | 1024 | "!TARGET_64BIT" |
4023fb28 | 1025 | "@ |
d40c829f UW |
1026 | lm\t%0,%N0,%1 |
1027 | stm\t%1,%N1,%0 | |
4023fb28 UW |
1028 | # |
1029 | # | |
d40c829f UW |
1030 | ldr\t%0,%1 |
1031 | ld\t%0,%1 | |
1032 | ldy\t%0,%1 | |
1033 | std\t%1,%0 | |
1034 | stdy\t%1,%0 | |
1035 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1036 | [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS") |
1037 | (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")]) | |
4023fb28 UW |
1038 | |
1039 | (define_split | |
1040 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1041 | (match_operand:DI 1 "general_operand" ""))] | |
1042 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1043 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1044 | [(set (match_dup 2) (match_dup 4)) |
1045 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1046 | { |
dc65c307 UW |
1047 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1048 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1049 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1050 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1051 | }) | |
1052 | ||
1053 | (define_split | |
1054 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1055 | (match_operand:DI 1 "general_operand" ""))] | |
1056 | "!TARGET_64BIT && reload_completed | |
1057 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1058 | [(set (match_dup 2) (match_dup 4)) | |
1059 | (set (match_dup 3) (match_dup 5))] | |
1060 | { | |
1061 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1062 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1063 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1064 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1065 | }) | |
9db1d521 | 1066 | |
4023fb28 UW |
1067 | (define_split |
1068 | [(set (match_operand:DI 0 "register_operand" "") | |
1069 | (match_operand:DI 1 "memory_operand" ""))] | |
1070 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1071 | && !FP_REG_P (operands[0]) |
4023fb28 | 1072 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1073 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1074 | { |
1075 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1076 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1077 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1078 | }) |
1079 | ||
1080 | (define_expand "reload_outdi" | |
1081 | [(parallel [(match_operand:DI 0 "memory_operand" "") | |
1082 | (match_operand:DI 1 "register_operand" "d") | |
1083 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1084 | "!TARGET_64BIT" | |
1085 | { | |
1086 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1087 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1088 | emit_move_insn (operands[0], operands[1]); | |
1089 | DONE; | |
1090 | }) | |
9db1d521 | 1091 | |
84817c5d UW |
1092 | (define_peephole2 |
1093 | [(set (match_operand:DI 0 "register_operand" "") | |
1094 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1095 | "TARGET_64BIT | |
1096 | && !FP_REG_P (operands[0]) | |
1097 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1098 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1099 | && get_pool_mode (operands[1]) == DImode | |
1100 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1101 | [(set (match_dup 0) (match_dup 2))] | |
1102 | "operands[2] = get_pool_constant (operands[1]);") | |
1103 | ||
7bdff56f UW |
1104 | (define_insn "*la_64" |
1105 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1106 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1107 | "TARGET_64BIT" | |
1108 | "@ | |
1109 | la\t%0,%a1 | |
1110 | lay\t%0,%a1" | |
1111 | [(set_attr "op_type" "RX,RXY") | |
1112 | (set_attr "type" "la")]) | |
1113 | ||
1114 | (define_peephole2 | |
1115 | [(parallel | |
1116 | [(set (match_operand:DI 0 "register_operand" "") | |
1117 | (match_operand:QI 1 "address_operand" "")) | |
1118 | (clobber (reg:CC 33))])] | |
1119 | "TARGET_64BIT | |
1120 | && strict_memory_address_p (VOIDmode, operands[1]) | |
1121 | && preferred_la_operand_p (operands[1])" | |
1122 | [(set (match_dup 0) (match_dup 1))] | |
1123 | "") | |
1124 | ||
1125 | (define_peephole2 | |
1126 | [(set (match_operand:DI 0 "register_operand" "") | |
1127 | (match_operand:DI 1 "register_operand" "")) | |
1128 | (parallel | |
1129 | [(set (match_dup 0) | |
1130 | (plus:DI (match_dup 0) | |
1131 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
1132 | (clobber (reg:CC 33))])] | |
1133 | "TARGET_64BIT | |
1134 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
1135 | && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2])) | |
1136 | && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))" | |
1137 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] | |
1138 | "") | |
1139 | ||
1140 | (define_expand "reload_indi" | |
1141 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1142 | (match_operand:DI 1 "s390_plus_operand" "") | |
1143 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1144 | "TARGET_64BIT" | |
1145 | { | |
1146 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1147 | DONE; | |
1148 | }) | |
1149 | ||
9db1d521 HP |
1150 | ; |
1151 | ; movsi instruction pattern(s). | |
1152 | ; | |
1153 | ||
9db1d521 HP |
1154 | (define_expand "movsi" |
1155 | [(set (match_operand:SI 0 "general_operand" "") | |
1156 | (match_operand:SI 1 "general_operand" ""))] | |
1157 | "" | |
9db1d521 | 1158 | { |
fd3cd001 UW |
1159 | /* Handle symbolic constants. */ |
1160 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1161 | emit_symbolic_move (operands); | |
ba956982 | 1162 | |
c7453384 EC |
1163 | /* expr.c tries to load an effective address using |
1164 | force_reg. This fails because we don't have a | |
ba956982 UW |
1165 | generic load_address pattern. Convert the move |
1166 | to a proper arithmetic operation instead, unless | |
1167 | it is guaranteed to be OK. */ | |
1168 | if (GET_CODE (operands[1]) == PLUS | |
1169 | && !legitimate_la_operand_p (operands[1])) | |
1170 | { | |
1171 | operands[1] = force_operand (operands[1], operands[0]); | |
1172 | if (operands[1] == operands[0]) | |
1173 | DONE; | |
1174 | } | |
4023fb28 UW |
1175 | |
1176 | /* During and after reload, we need to force constants | |
1177 | to the literal pool ourselves, if necessary. */ | |
1178 | if ((reload_in_progress || reload_completed) | |
c7453384 | 1179 | && CONSTANT_P (operands[1]) |
4023fb28 | 1180 | && (!legitimate_reload_constant_p (operands[1]) |
8e509cf9 | 1181 | || FP_REG_P (operands[0]))) |
4023fb28 | 1182 | operands[1] = force_const_mem (SImode, operands[1]); |
10bbf137 | 1183 | }) |
9db1d521 | 1184 | |
9e8327e3 UW |
1185 | (define_insn "*movsi_larl" |
1186 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1187 | (match_operand:SI 1 "larl_operand" "X"))] | |
1188 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1189 | && !FP_REG_P (operands[0])" | |
1190 | "larl\t%0,%1" | |
1191 | [(set_attr "op_type" "RIL") | |
1192 | (set_attr "type" "larl")]) | |
1193 | ||
f19a9af7 | 1194 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1195 | [(set (match_operand:SI 0 "nonimmediate_operand" |
f19a9af7 | 1196 | "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") |
2f7e5a0d | 1197 | (match_operand:SI 1 "general_operand" |
f19a9af7 AK |
1198 | "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))] |
1199 | "TARGET_ZARCH" | |
9db1d521 | 1200 | "@ |
f19a9af7 AK |
1201 | lhi\t%0,%h1 |
1202 | llilh\t%0,%i1 | |
1203 | llill\t%0,%i1 | |
1204 | lay\t%0,%a1 | |
d40c829f UW |
1205 | lr\t%0,%1 |
1206 | l\t%0,%1 | |
1207 | ly\t%0,%1 | |
1208 | st\t%1,%0 | |
1209 | sty\t%1,%0 | |
1210 | ler\t%0,%1 | |
1211 | le\t%0,%1 | |
1212 | ley\t%0,%1 | |
1213 | ste\t%1,%0 | |
1214 | stey\t%1,%0 | |
1215 | mvc\t%O0(4,%R0),%1" | |
f19a9af7 AK |
1216 | [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1217 | (set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")]) | |
1218 | ||
1219 | (define_insn "*movsi_esa" | |
1220 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,?Q") | |
1221 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,?Q"))] | |
1222 | "!TARGET_ZARCH" | |
1223 | "@ | |
1224 | lhi\t%0,%h1 | |
1225 | lr\t%0,%1 | |
1226 | l\t%0,%1 | |
1227 | st\t%1,%0 | |
1228 | ler\t%0,%1 | |
1229 | le\t%0,%1 | |
1230 | ste\t%1,%0 | |
1231 | mvc\t%O0(4,%R0),%1" | |
1232 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,SS") | |
1233 | (set_attr "type" "*,lr,load,store,floads,floads,fstores,cs")]) | |
9db1d521 | 1234 | |
84817c5d UW |
1235 | (define_peephole2 |
1236 | [(set (match_operand:SI 0 "register_operand" "") | |
1237 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1238 | "!FP_REG_P (operands[0]) | |
1239 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1240 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1241 | && get_pool_mode (operands[1]) == SImode | |
1242 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1243 | [(set (match_dup 0) (match_dup 2))] | |
1244 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1245 | |
7bdff56f UW |
1246 | (define_insn "*la_31" |
1247 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1248 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1249 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1250 | "@ | |
1251 | la\t%0,%a1 | |
1252 | lay\t%0,%a1" | |
1253 | [(set_attr "op_type" "RX,RXY") | |
1254 | (set_attr "type" "la")]) | |
1255 | ||
1256 | (define_peephole2 | |
1257 | [(parallel | |
1258 | [(set (match_operand:SI 0 "register_operand" "") | |
1259 | (match_operand:QI 1 "address_operand" "")) | |
1260 | (clobber (reg:CC 33))])] | |
1261 | "!TARGET_64BIT | |
1262 | && strict_memory_address_p (VOIDmode, operands[1]) | |
1263 | && preferred_la_operand_p (operands[1])" | |
1264 | [(set (match_dup 0) (match_dup 1))] | |
1265 | "") | |
1266 | ||
1267 | (define_peephole2 | |
1268 | [(set (match_operand:SI 0 "register_operand" "") | |
1269 | (match_operand:SI 1 "register_operand" "")) | |
1270 | (parallel | |
1271 | [(set (match_dup 0) | |
1272 | (plus:SI (match_dup 0) | |
1273 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
1274 | (clobber (reg:CC 33))])] | |
1275 | "!TARGET_64BIT | |
1276 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
1277 | && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2])) | |
1278 | && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))" | |
1279 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] | |
1280 | "") | |
1281 | ||
1282 | (define_insn "*la_31_and" | |
1283 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1284 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1285 | (const_int 2147483647)))] | |
1286 | "!TARGET_64BIT" | |
1287 | "@ | |
1288 | la\t%0,%a1 | |
1289 | lay\t%0,%a1" | |
1290 | [(set_attr "op_type" "RX,RXY") | |
1291 | (set_attr "type" "la")]) | |
1292 | ||
1293 | (define_insn_and_split "*la_31_and_cc" | |
1294 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1295 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1296 | (const_int 2147483647))) | |
1297 | (clobber (reg:CC 33))] | |
1298 | "!TARGET_64BIT" | |
1299 | "#" | |
1300 | "&& reload_completed" | |
1301 | [(set (match_dup 0) | |
1302 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1303 | "" | |
1304 | [(set_attr "op_type" "RX") | |
1305 | (set_attr "type" "la")]) | |
1306 | ||
1307 | (define_insn "force_la_31" | |
1308 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1309 | (match_operand:QI 1 "address_operand" "U,W")) | |
1310 | (use (const_int 0))] | |
1311 | "!TARGET_64BIT" | |
1312 | "@ | |
1313 | la\t%0,%a1 | |
1314 | lay\t%0,%a1" | |
1315 | [(set_attr "op_type" "RX") | |
1316 | (set_attr "type" "la")]) | |
1317 | ||
1318 | (define_expand "reload_insi" | |
1319 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1320 | (match_operand:SI 1 "s390_plus_operand" "") | |
1321 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1322 | "!TARGET_64BIT" | |
1323 | { | |
1324 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1325 | DONE; | |
1326 | }) | |
1327 | ||
9db1d521 HP |
1328 | ; |
1329 | ; movhi instruction pattern(s). | |
1330 | ; | |
1331 | ||
02ed3c5e UW |
1332 | (define_expand "movhi" |
1333 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1334 | (match_operand:HI 1 "general_operand" ""))] | |
1335 | "" | |
1336 | { | |
2f7e5a0d | 1337 | /* Make it explicit that loading a register from memory |
02ed3c5e UW |
1338 | always sign-extends (at least) to SImode. */ |
1339 | if (optimize && !no_new_pseudos | |
1340 | && register_operand (operands[0], VOIDmode) | |
d71a8c3b UW |
1341 | && GET_CODE (operands[1]) == MEM |
1342 | && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF) | |
02ed3c5e UW |
1343 | { |
1344 | rtx tmp = gen_reg_rtx (SImode); | |
1345 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1346 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1347 | operands[1] = gen_lowpart (HImode, tmp); | |
1348 | } | |
1349 | }) | |
1350 | ||
1351 | (define_insn "*movhi" | |
d3632d41 UW |
1352 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1353 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1354 | "" |
1355 | "@ | |
d40c829f UW |
1356 | lr\t%0,%1 |
1357 | lhi\t%0,%h1 | |
1358 | lh\t%0,%1 | |
1359 | lhy\t%0,%1 | |
1360 | sth\t%1,%0 | |
1361 | sthy\t%1,%0 | |
1362 | mvc\t%O0(2,%R0),%1" | |
d3632d41 UW |
1363 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
1364 | (set_attr "type" "lr,*,*,*,store,store,cs")]) | |
9db1d521 | 1365 | |
84817c5d UW |
1366 | (define_peephole2 |
1367 | [(set (match_operand:HI 0 "register_operand" "") | |
1368 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1369 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1370 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1371 | && get_pool_mode (operands[1]) == HImode | |
1372 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1373 | [(set (match_dup 0) (match_dup 2))] | |
1374 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1375 | |
9db1d521 HP |
1376 | ; |
1377 | ; movqi instruction pattern(s). | |
1378 | ; | |
1379 | ||
02ed3c5e UW |
1380 | (define_expand "movqi" |
1381 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1382 | (match_operand:QI 1 "general_operand" ""))] | |
1383 | "" | |
1384 | { | |
c19ec8f9 | 1385 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1386 | is just as fast as a QImode load. */ |
c19ec8f9 | 1387 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1388 | && register_operand (operands[0], VOIDmode) |
d71a8c3b UW |
1389 | && GET_CODE (operands[1]) == MEM |
1390 | && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF) | |
02ed3c5e | 1391 | { |
c19ec8f9 UW |
1392 | rtx tmp = gen_reg_rtx (word_mode); |
1393 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1394 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1395 | operands[1] = gen_lowpart (QImode, tmp); | |
1396 | } | |
1397 | }) | |
4023fb28 | 1398 | |
02ed3c5e | 1399 | (define_insn "*movqi" |
d3632d41 UW |
1400 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1401 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1402 | "" |
1403 | "@ | |
d40c829f UW |
1404 | lr\t%0,%1 |
1405 | lhi\t%0,%b1 | |
1406 | ic\t%0,%1 | |
1407 | icy\t%0,%1 | |
1408 | stc\t%1,%0 | |
1409 | stcy\t%1,%0 | |
1410 | mvi\t%0,%b1 | |
1411 | mviy\t%0,%b1 | |
1412 | mvc\t%O0(1,%R0),%1" | |
d3632d41 UW |
1413 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1414 | (set_attr "type" "lr,*,*,*,store,store,store,store,cs")]) | |
9db1d521 | 1415 | |
84817c5d UW |
1416 | (define_peephole2 |
1417 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1418 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1419 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1420 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1421 | && get_pool_mode (operands[1]) == QImode | |
1422 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1423 | [(set (match_dup 0) (match_dup 2))] | |
1424 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1425 | |
9db1d521 | 1426 | ; |
05b9aaaa | 1427 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1428 | ; |
1429 | ||
1430 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1431 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1432 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1433 | "" |
d3632d41 | 1434 | "@ |
d40c829f UW |
1435 | ic\t%0,%1 |
1436 | icy\t%0,%1" | |
d3632d41 | 1437 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1438 | |
1439 | ; | |
1440 | ; movstricthi instruction pattern(s). | |
1441 | ; | |
1442 | ||
1443 | (define_insn "*movstricthi" | |
d3632d41 UW |
1444 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
1445 | (match_operand:HI 1 "s_imm_operand" "Q,S")) | |
9db1d521 HP |
1446 | (clobber (reg:CC 33))] |
1447 | "" | |
d3632d41 | 1448 | "@ |
d40c829f UW |
1449 | icm\t%0,3,%1 |
1450 | icmy\t%0,3,%1" | |
d3632d41 | 1451 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1452 | |
1453 | ; | |
1454 | ; movstrictsi instruction pattern(s). | |
1455 | ; | |
1456 | ||
05b9aaaa | 1457 | (define_insn "movstrictsi" |
d3632d41 UW |
1458 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d")) |
1459 | (match_operand:SI 1 "general_operand" "d,R,T"))] | |
9db1d521 HP |
1460 | "TARGET_64BIT" |
1461 | "@ | |
d40c829f UW |
1462 | lr\t%0,%1 |
1463 | l\t%0,%1 | |
1464 | ly\t%0,%1" | |
d3632d41 UW |
1465 | [(set_attr "op_type" "RR,RX,RXY") |
1466 | (set_attr "type" "lr,load,load")]) | |
9db1d521 HP |
1467 | |
1468 | ; | |
1469 | ; movdf instruction pattern(s). | |
1470 | ; | |
1471 | ||
1472 | (define_expand "movdf" | |
1473 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1474 | (match_operand:DF 1 "general_operand" ""))] | |
1475 | "" | |
9db1d521 | 1476 | { |
4023fb28 UW |
1477 | /* During and after reload, we need to force constants |
1478 | to the literal pool ourselves, if necessary. */ | |
1479 | if ((reload_in_progress || reload_completed) | |
1480 | && CONSTANT_P (operands[1])) | |
1481 | operands[1] = force_const_mem (DFmode, operands[1]); | |
10bbf137 | 1482 | }) |
9db1d521 HP |
1483 | |
1484 | (define_insn "*movdf_64" | |
d3632d41 UW |
1485 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") |
1486 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1487 | "TARGET_64BIT" |
9db1d521 | 1488 | "@ |
d40c829f UW |
1489 | ldr\t%0,%1 |
1490 | ld\t%0,%1 | |
1491 | ldy\t%0,%1 | |
1492 | std\t%1,%0 | |
1493 | stdy\t%1,%0 | |
1494 | lgr\t%0,%1 | |
1495 | lg\t%0,%1 | |
1496 | stg\t%1,%0 | |
1497 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1498 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
1499 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")]) | |
9db1d521 HP |
1500 | |
1501 | (define_insn "*movdf_31" | |
d3632d41 UW |
1502 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") |
1503 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] | |
4023fb28 | 1504 | "!TARGET_64BIT" |
9db1d521 | 1505 | "@ |
d40c829f UW |
1506 | ldr\t%0,%1 |
1507 | ld\t%0,%1 | |
1508 | ldy\t%0,%1 | |
1509 | std\t%1,%0 | |
1510 | stdy\t%1,%0 | |
1511 | lm\t%0,%N0,%1 | |
1512 | stm\t%1,%N1,%0 | |
4023fb28 | 1513 | # |
9b7c75b9 | 1514 | # |
d40c829f | 1515 | mvc\t%O0(8,%R0),%1" |
d3632d41 UW |
1516 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS") |
1517 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")]) | |
4023fb28 UW |
1518 | |
1519 | (define_split | |
1520 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1521 | (match_operand:DF 1 "general_operand" ""))] | |
1522 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1523 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1524 | [(set (match_dup 2) (match_dup 4)) |
1525 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1526 | { |
dc65c307 UW |
1527 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1528 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1529 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1530 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1531 | }) | |
1532 | ||
1533 | (define_split | |
1534 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1535 | (match_operand:DF 1 "general_operand" ""))] | |
1536 | "!TARGET_64BIT && reload_completed | |
1537 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1538 | [(set (match_dup 2) (match_dup 4)) | |
1539 | (set (match_dup 3) (match_dup 5))] | |
1540 | { | |
1541 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1542 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1543 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1544 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1545 | }) | |
9db1d521 | 1546 | |
4023fb28 UW |
1547 | (define_split |
1548 | [(set (match_operand:DF 0 "register_operand" "") | |
1549 | (match_operand:DF 1 "memory_operand" ""))] | |
1550 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1551 | && !FP_REG_P (operands[0]) |
4023fb28 | 1552 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1553 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1554 | { |
1555 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1556 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1557 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1558 | }) |
1559 | ||
1560 | (define_expand "reload_outdf" | |
1561 | [(parallel [(match_operand:DF 0 "memory_operand" "") | |
1562 | (match_operand:DF 1 "register_operand" "d") | |
1563 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1564 | "!TARGET_64BIT" | |
1565 | { | |
1566 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1567 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1568 | emit_move_insn (operands[0], operands[1]); | |
1569 | DONE; | |
1570 | }) | |
9db1d521 HP |
1571 | |
1572 | ; | |
1573 | ; movsf instruction pattern(s). | |
1574 | ; | |
1575 | ||
1576 | (define_expand "movsf" | |
1577 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
1578 | (match_operand:SF 1 "general_operand" ""))] | |
1579 | "" | |
9db1d521 | 1580 | { |
4023fb28 UW |
1581 | /* During and after reload, we need to force constants |
1582 | to the literal pool ourselves, if necessary. */ | |
1583 | if ((reload_in_progress || reload_completed) | |
1584 | && CONSTANT_P (operands[1])) | |
1585 | operands[1] = force_const_mem (SFmode, operands[1]); | |
10bbf137 | 1586 | }) |
9db1d521 | 1587 | |
4023fb28 | 1588 | (define_insn "*movsf" |
d3632d41 UW |
1589 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") |
1590 | (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1591 | "" |
9db1d521 | 1592 | "@ |
d40c829f UW |
1593 | ler\t%0,%1 |
1594 | le\t%0,%1 | |
1595 | ley\t%0,%1 | |
1596 | ste\t%1,%0 | |
1597 | stey\t%1,%0 | |
1598 | lr\t%0,%1 | |
1599 | l\t%0,%1 | |
1600 | ly\t%0,%1 | |
1601 | st\t%1,%0 | |
1602 | sty\t%1,%0 | |
1603 | mvc\t%O0(4,%R0),%1" | |
d3632d41 UW |
1604 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1605 | (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")]) | |
4023fb28 | 1606 | |
9db1d521 HP |
1607 | ; |
1608 | ; load_multiple pattern(s). | |
1609 | ; | |
22ea6b4f UW |
1610 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1611 | ; we currently support load_multiple/store_multiple only after reload. | |
1612 | ; | |
9db1d521 HP |
1613 | |
1614 | (define_expand "load_multiple" | |
1615 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1616 | (match_operand 1 "" "")) | |
1617 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1618 | "reload_completed" |
9db1d521 | 1619 | { |
c19ec8f9 | 1620 | enum machine_mode mode; |
9db1d521 HP |
1621 | int regno; |
1622 | int count; | |
1623 | rtx from; | |
4023fb28 | 1624 | int i, off; |
9db1d521 HP |
1625 | |
1626 | /* Support only loading a constant number of fixed-point registers from | |
1627 | memory and only bother with this if more than two */ | |
1628 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1629 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1630 | || INTVAL (operands[2]) > 16 |
1631 | || GET_CODE (operands[1]) != MEM | |
1632 | || GET_CODE (operands[0]) != REG | |
1633 | || REGNO (operands[0]) >= 16) | |
1634 | FAIL; | |
1635 | ||
1636 | count = INTVAL (operands[2]); | |
1637 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1638 | mode = GET_MODE (operands[0]); |
1639 | if (mode != SImode && mode != word_mode) | |
1640 | FAIL; | |
9db1d521 HP |
1641 | |
1642 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1643 | if (no_new_pseudos) |
1644 | { | |
1645 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1646 | { | |
1647 | from = XEXP (operands[1], 0); | |
1648 | off = 0; | |
1649 | } | |
1650 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1651 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1652 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1653 | { | |
1654 | from = XEXP (XEXP (operands[1], 0), 0); | |
1655 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1656 | } | |
1657 | else | |
1658 | FAIL; | |
1659 | ||
1660 | if (from == frame_pointer_rtx || from == arg_pointer_rtx) | |
1661 | FAIL; | |
1662 | } | |
1663 | else | |
1664 | { | |
1665 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1666 | off = 0; | |
1667 | } | |
9db1d521 HP |
1668 | |
1669 | for (i = 0; i < count; i++) | |
1670 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1671 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1672 | change_address (operands[1], mode, | |
1673 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1674 | }) |
9db1d521 HP |
1675 | |
1676 | (define_insn "*load_multiple_di" | |
1677 | [(match_parallel 0 "load_multiple_operation" | |
1678 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1679 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1680 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1681 | { |
1682 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1683 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
d40c829f | 1684 | return "lmg\t%1,%0,%2"; |
10bbf137 | 1685 | } |
d3632d41 | 1686 | [(set_attr "op_type" "RSY") |
4023fb28 | 1687 | (set_attr "type" "lm")]) |
9db1d521 HP |
1688 | |
1689 | (define_insn "*load_multiple_si" | |
1690 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1691 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1692 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1693 | "reload_completed" |
9db1d521 HP |
1694 | { |
1695 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1696 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
d40c829f | 1697 | return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2"; |
10bbf137 | 1698 | } |
d3632d41 | 1699 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1700 | (set_attr "type" "lm")]) |
9db1d521 HP |
1701 | |
1702 | ; | |
c7453384 | 1703 | ; store multiple pattern(s). |
9db1d521 HP |
1704 | ; |
1705 | ||
1706 | (define_expand "store_multiple" | |
1707 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1708 | (match_operand 1 "" "")) | |
1709 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1710 | "reload_completed" |
9db1d521 | 1711 | { |
c19ec8f9 | 1712 | enum machine_mode mode; |
9db1d521 HP |
1713 | int regno; |
1714 | int count; | |
1715 | rtx to; | |
4023fb28 | 1716 | int i, off; |
9db1d521 HP |
1717 | |
1718 | /* Support only storing a constant number of fixed-point registers to | |
1719 | memory and only bother with this if more than two. */ | |
1720 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1721 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1722 | || INTVAL (operands[2]) > 16 |
1723 | || GET_CODE (operands[0]) != MEM | |
1724 | || GET_CODE (operands[1]) != REG | |
1725 | || REGNO (operands[1]) >= 16) | |
1726 | FAIL; | |
1727 | ||
1728 | count = INTVAL (operands[2]); | |
1729 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1730 | mode = GET_MODE (operands[1]); |
1731 | if (mode != SImode && mode != word_mode) | |
1732 | FAIL; | |
9db1d521 HP |
1733 | |
1734 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1735 | |
1736 | if (no_new_pseudos) | |
1737 | { | |
1738 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1739 | { | |
1740 | to = XEXP (operands[0], 0); | |
1741 | off = 0; | |
1742 | } | |
1743 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1744 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1745 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1746 | { | |
1747 | to = XEXP (XEXP (operands[0], 0), 0); | |
1748 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1749 | } | |
1750 | else | |
1751 | FAIL; | |
1752 | ||
1753 | if (to == frame_pointer_rtx || to == arg_pointer_rtx) | |
1754 | FAIL; | |
1755 | } | |
c7453384 | 1756 | else |
4023fb28 UW |
1757 | { |
1758 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1759 | off = 0; | |
1760 | } | |
9db1d521 HP |
1761 | |
1762 | for (i = 0; i < count; i++) | |
1763 | XVECEXP (operands[3], 0, i) | |
1764 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1765 | change_address (operands[0], mode, |
1766 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1767 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1768 | }) |
9db1d521 HP |
1769 | |
1770 | (define_insn "*store_multiple_di" | |
1771 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1772 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1773 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1774 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1775 | { |
1776 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1777 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
d40c829f | 1778 | return "stmg\t%2,%0,%1"; |
10bbf137 | 1779 | } |
d3632d41 | 1780 | [(set_attr "op_type" "RSY") |
4023fb28 | 1781 | (set_attr "type" "stm")]) |
9db1d521 HP |
1782 | |
1783 | ||
1784 | (define_insn "*store_multiple_si" | |
1785 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1786 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1787 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1788 | "reload_completed" |
9db1d521 HP |
1789 | { |
1790 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1791 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
d40c829f | 1792 | return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1"; |
10bbf137 | 1793 | } |
d3632d41 | 1794 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1795 | (set_attr "type" "stm")]) |
9db1d521 HP |
1796 | |
1797 | ;; | |
1798 | ;; String instructions. | |
1799 | ;; | |
1800 | ||
91d39d71 UW |
1801 | ; |
1802 | ; strlenM instruction pattern(s). | |
1803 | ; | |
1804 | ||
1805 | (define_expand "strlendi" | |
1806 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) | |
2f7e5a0d | 1807 | (parallel |
91d39d71 UW |
1808 | [(set (match_dup 4) |
1809 | (unspec:DI [(const_int 0) | |
1810 | (match_operand:BLK 1 "memory_operand" "") | |
1811 | (reg:QI 0) | |
1812 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
1813 | (clobber (scratch:DI)) | |
1814 | (clobber (reg:CC 33))]) | |
1815 | (parallel | |
1816 | [(set (match_operand:DI 0 "register_operand" "") | |
1817 | (minus:DI (match_dup 4) (match_dup 5))) | |
1818 | (clobber (reg:CC 33))])] | |
1819 | "TARGET_64BIT" | |
1820 | { | |
1821 | operands[4] = gen_reg_rtx (DImode); | |
1822 | operands[5] = gen_reg_rtx (DImode); | |
1823 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1824 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1825 | }) | |
1826 | ||
1827 | (define_insn "*strlendi" | |
1828 | [(set (match_operand:DI 0 "register_operand" "=a") | |
1829 | (unspec:DI [(match_operand:DI 2 "general_operand" "0") | |
1830 | (mem:BLK (match_operand:DI 3 "register_operand" "1")) | |
1831 | (reg:QI 0) | |
1832 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
1833 | (clobber (match_scratch:DI 1 "=a")) | |
1834 | (clobber (reg:CC 33))] | |
1835 | "TARGET_64BIT" | |
1836 | "srst\t%0,%1\;jo\t.-4" | |
1837 | [(set_attr "op_type" "NN") | |
1838 | (set_attr "type" "vs") | |
1839 | (set_attr "length" "8")]) | |
1840 | ||
1841 | (define_expand "strlensi" | |
1842 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) | |
2f7e5a0d | 1843 | (parallel |
91d39d71 UW |
1844 | [(set (match_dup 4) |
1845 | (unspec:SI [(const_int 0) | |
1846 | (match_operand:BLK 1 "memory_operand" "") | |
1847 | (reg:QI 0) | |
1848 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
1849 | (clobber (scratch:SI)) | |
1850 | (clobber (reg:CC 33))]) | |
1851 | (parallel | |
1852 | [(set (match_operand:SI 0 "register_operand" "") | |
1853 | (minus:SI (match_dup 4) (match_dup 5))) | |
1854 | (clobber (reg:CC 33))])] | |
1855 | "!TARGET_64BIT" | |
1856 | { | |
1857 | operands[4] = gen_reg_rtx (SImode); | |
1858 | operands[5] = gen_reg_rtx (SImode); | |
1859 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1860 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1861 | }) | |
1862 | ||
1863 | (define_insn "*strlensi" | |
1864 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1865 | (unspec:SI [(match_operand:SI 2 "general_operand" "0") | |
1866 | (mem:BLK (match_operand:SI 3 "register_operand" "1")) | |
1867 | (reg:QI 0) | |
1868 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
1869 | (clobber (match_scratch:SI 1 "=a")) | |
2f7e5a0d | 1870 | (clobber (reg:CC 33))] |
91d39d71 UW |
1871 | "!TARGET_64BIT" |
1872 | "srst\t%0,%1\;jo\t.-4" | |
1873 | [(set_attr "op_type" "NN") | |
1874 | (set_attr "type" "vs") | |
1875 | (set_attr "length" "8")]) | |
1876 | ||
9db1d521 | 1877 | ; |
a41c6c53 | 1878 | ; movstrM instruction pattern(s). |
9db1d521 HP |
1879 | ; |
1880 | ||
1881 | (define_expand "movstrdi" | |
a41c6c53 UW |
1882 | [(set (match_operand:BLK 0 "memory_operand" "") |
1883 | (match_operand:BLK 1 "memory_operand" "")) | |
1884 | (use (match_operand:DI 2 "general_operand" "")) | |
1885 | (match_operand 3 "" "")] | |
1886 | "TARGET_64BIT" | |
1887 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
9db1d521 HP |
1888 | |
1889 | (define_expand "movstrsi" | |
a41c6c53 UW |
1890 | [(set (match_operand:BLK 0 "memory_operand" "") |
1891 | (match_operand:BLK 1 "memory_operand" "")) | |
1892 | (use (match_operand:SI 2 "general_operand" "")) | |
1893 | (match_operand 3 "" "")] | |
1894 | "" | |
1895 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
9db1d521 | 1896 | |
ecbe845e UW |
1897 | ; Move a block that is up to 256 bytes in length. |
1898 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1899 | |
b9404c99 UW |
1900 | (define_expand "movstr_short" |
1901 | [(parallel | |
1902 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1903 | (match_operand:BLK 1 "memory_operand" "")) | |
1904 | (use (match_operand 2 "nonmemory_operand" "")) | |
1905 | (clobber (match_dup 3))])] | |
1906 | "" | |
1907 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 1908 | |
b9404c99 | 1909 | (define_insn "*movstr_short" |
a41c6c53 UW |
1910 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") |
1911 | (match_operand:BLK 1 "memory_operand" "Q,Q")) | |
b9404c99 UW |
1912 | (use (match_operand 2 "nonmemory_operand" "n,a")) |
1913 | (clobber (match_scratch 3 "=X,&a"))] | |
1914 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) | |
1915 | && GET_MODE (operands[3]) == Pmode" | |
ecbe845e UW |
1916 | { |
1917 | switch (which_alternative) | |
1918 | { | |
1919 | case 0: | |
d40c829f | 1920 | return "mvc\t%O0(%b2+1,%R0),%1"; |
ecbe845e UW |
1921 | |
1922 | case 1: | |
d40c829f UW |
1923 | output_asm_insn ("bras\t%3,.+10", operands); |
1924 | output_asm_insn ("mvc\t%O0(1,%R0),%1", operands); | |
1925 | return "ex\t%2,0(%3)"; | |
9db1d521 | 1926 | |
ecbe845e UW |
1927 | default: |
1928 | abort (); | |
1929 | } | |
10bbf137 | 1930 | } |
ecbe845e | 1931 | [(set_attr "op_type" "SS,NN") |
a41c6c53 | 1932 | (set_attr "type" "cs,cs") |
077dab3b | 1933 | (set_attr "atype" "*,agen") |
ecbe845e | 1934 | (set_attr "length" "*,14")]) |
9db1d521 | 1935 | |
a41c6c53 | 1936 | ; Move a block of arbitrary length. |
9db1d521 | 1937 | |
b9404c99 UW |
1938 | (define_expand "movstr_long" |
1939 | [(parallel | |
1940 | [(clobber (match_dup 2)) | |
1941 | (clobber (match_dup 3)) | |
1942 | (set (match_operand:BLK 0 "memory_operand" "") | |
1943 | (match_operand:BLK 1 "memory_operand" "")) | |
1944 | (use (match_operand 2 "general_operand" "")) | |
1945 | (use (match_dup 3)) | |
1946 | (clobber (reg:CC 33))])] | |
1947 | "" | |
1948 | { | |
1949 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
1950 | rtx reg0 = gen_reg_rtx (dword_mode); | |
1951 | rtx reg1 = gen_reg_rtx (dword_mode); | |
1952 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
1953 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
1954 | rtx len0 = gen_lowpart (Pmode, reg0); | |
1955 | rtx len1 = gen_lowpart (Pmode, reg1); | |
1956 | ||
1957 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
1958 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
1959 | emit_move_insn (len0, operands[2]); | |
1960 | ||
1961 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
1962 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1963 | emit_move_insn (len1, operands[2]); | |
1964 | ||
1965 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
1966 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
1967 | operands[2] = reg0; | |
1968 | operands[3] = reg1; | |
1969 | }) | |
1970 | ||
1971 | (define_insn "*movstr_long_64" | |
1972 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
1973 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
1974 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
1975 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) | |
1976 | (use (match_dup 2)) | |
1977 | (use (match_dup 3)) | |
9db1d521 | 1978 | (clobber (reg:CC 33))] |
9f37ccb1 | 1979 | "TARGET_64BIT" |
d40c829f | 1980 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 1981 | [(set_attr "op_type" "NN") |
a41c6c53 | 1982 | (set_attr "type" "vs") |
9db1d521 HP |
1983 | (set_attr "length" "8")]) |
1984 | ||
b9404c99 UW |
1985 | (define_insn "*movstr_long_31" |
1986 | [(clobber (match_operand:DI 0 "register_operand" "=d")) | |
1987 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
1988 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
1989 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) | |
1990 | (use (match_dup 2)) | |
1991 | (use (match_dup 3)) | |
9db1d521 | 1992 | (clobber (reg:CC 33))] |
9f37ccb1 | 1993 | "!TARGET_64BIT" |
d40c829f | 1994 | "mvcle\t%0,%1,0\;jo\t.-4" |
a41c6c53 UW |
1995 | [(set_attr "op_type" "NN") |
1996 | (set_attr "type" "vs") | |
a41c6c53 | 1997 | (set_attr "length" "8")]) |
9db1d521 HP |
1998 | |
1999 | ; | |
a41c6c53 | 2000 | ; clrstrM instruction pattern(s). |
9db1d521 HP |
2001 | ; |
2002 | ||
2003 | (define_expand "clrstrdi" | |
a41c6c53 | 2004 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
2005 | (const_int 0)) |
2006 | (use (match_operand:DI 1 "general_operand" "")) | |
2007 | (match_operand 2 "" "")] | |
2008 | "TARGET_64BIT" | |
a41c6c53 | 2009 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") |
9db1d521 HP |
2010 | |
2011 | (define_expand "clrstrsi" | |
a41c6c53 | 2012 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
2013 | (const_int 0)) |
2014 | (use (match_operand:SI 1 "general_operand" "")) | |
2015 | (match_operand 2 "" "")] | |
a41c6c53 UW |
2016 | "" |
2017 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") | |
9db1d521 | 2018 | |
a41c6c53 | 2019 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2020 | ; The block length is taken as (operands[1] % 256) + 1. |
2021 | ||
2022 | (define_expand "clrstr_short" | |
2023 | [(parallel | |
2024 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2025 | (const_int 0)) | |
2026 | (use (match_operand 1 "nonmemory_operand" "")) | |
2027 | (clobber (match_dup 2)) | |
2028 | (clobber (reg:CC 33))])] | |
2029 | "" | |
2030 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2031 | |
b9404c99 | 2032 | (define_insn "*clrstr_short" |
a41c6c53 UW |
2033 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") |
2034 | (const_int 0)) | |
b9404c99 UW |
2035 | (use (match_operand 1 "nonmemory_operand" "n,a")) |
2036 | (clobber (match_scratch 2 "=X,&a")) | |
a41c6c53 | 2037 | (clobber (reg:CC 33))] |
b9404c99 UW |
2038 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
2039 | && GET_MODE (operands[2]) == Pmode" | |
a41c6c53 UW |
2040 | { |
2041 | switch (which_alternative) | |
2042 | { | |
2043 | case 0: | |
d40c829f | 2044 | return "xc\t%O0(%b1+1,%R0),%0"; |
9db1d521 | 2045 | |
a41c6c53 | 2046 | case 1: |
d40c829f UW |
2047 | output_asm_insn ("bras\t%2,.+10", operands); |
2048 | output_asm_insn ("xc\t%O0(1,%R0),%0", operands); | |
2049 | return "ex\t%1,0(%2)"; | |
9db1d521 | 2050 | |
a41c6c53 UW |
2051 | default: |
2052 | abort (); | |
2053 | } | |
10bbf137 | 2054 | } |
a41c6c53 UW |
2055 | [(set_attr "op_type" "SS,NN") |
2056 | (set_attr "type" "cs,cs") | |
077dab3b | 2057 | (set_attr "atype" "*,agen") |
a41c6c53 | 2058 | (set_attr "length" "*,14")]) |
9db1d521 | 2059 | |
b9404c99 UW |
2060 | ; Clear a block of arbitrary length. |
2061 | ||
2062 | (define_expand "clrstr_long" | |
2063 | [(parallel | |
2064 | [(clobber (match_dup 1)) | |
2065 | (set (match_operand:BLK 0 "memory_operand" "") | |
2066 | (const_int 0)) | |
2067 | (use (match_operand 1 "general_operand" "")) | |
2068 | (use (match_dup 2)) | |
2069 | (clobber (reg:CC 33))])] | |
2070 | "" | |
a41c6c53 | 2071 | { |
b9404c99 UW |
2072 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2073 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2074 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2075 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2076 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2077 | |
b9404c99 UW |
2078 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2079 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2080 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2081 | |
b9404c99 | 2082 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2083 | |
b9404c99 UW |
2084 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2085 | operands[1] = reg0; | |
2086 | operands[2] = reg1; | |
2087 | }) | |
a41c6c53 | 2088 | |
b9404c99 UW |
2089 | (define_insn "*clrstr_long_64" |
2090 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2091 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
9db1d521 | 2092 | (const_int 0)) |
b9404c99 | 2093 | (use (match_dup 2)) |
9f37ccb1 | 2094 | (use (match_operand:TI 1 "register_operand" "d")) |
9db1d521 HP |
2095 | (clobber (reg:CC 33))] |
2096 | "TARGET_64BIT" | |
d40c829f | 2097 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 2098 | [(set_attr "op_type" "NN") |
4023fb28 | 2099 | (set_attr "type" "vs") |
9db1d521 HP |
2100 | (set_attr "length" "8")]) |
2101 | ||
b9404c99 UW |
2102 | (define_insn "*clrstr_long_31" |
2103 | [(clobber (match_operand:DI 0 "register_operand" "=d")) | |
2104 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
9db1d521 | 2105 | (const_int 0)) |
b9404c99 | 2106 | (use (match_dup 2)) |
9f37ccb1 | 2107 | (use (match_operand:DI 1 "register_operand" "d")) |
9db1d521 HP |
2108 | (clobber (reg:CC 33))] |
2109 | "!TARGET_64BIT" | |
d40c829f | 2110 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 2111 | [(set_attr "op_type" "NN") |
4023fb28 | 2112 | (set_attr "type" "vs") |
9db1d521 HP |
2113 | (set_attr "length" "8")]) |
2114 | ||
2115 | ; | |
358b8f01 | 2116 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2117 | ; |
2118 | ||
358b8f01 | 2119 | (define_expand "cmpmemdi" |
a41c6c53 UW |
2120 | [(set (match_operand:DI 0 "register_operand" "") |
2121 | (compare:DI (match_operand:BLK 1 "memory_operand" "") | |
2122 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2123 | (use (match_operand:DI 3 "general_operand" "")) | |
2124 | (use (match_operand:DI 4 "" ""))] | |
2125 | "TARGET_64BIT" | |
c7453384 | 2126 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2127 | operands[2], operands[3]); DONE;") |
9db1d521 | 2128 | |
358b8f01 | 2129 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2130 | [(set (match_operand:SI 0 "register_operand" "") |
2131 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2132 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2133 | (use (match_operand:SI 3 "general_operand" "")) | |
2134 | (use (match_operand:SI 4 "" ""))] | |
2135 | "" | |
c7453384 | 2136 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2137 | operands[2], operands[3]); DONE;") |
9db1d521 | 2138 | |
a41c6c53 UW |
2139 | ; Compare a block that is up to 256 bytes in length. |
2140 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2141 | |
b9404c99 UW |
2142 | (define_expand "cmpmem_short" |
2143 | [(parallel | |
2144 | [(set (reg:CCS 33) | |
2145 | (compare:CCS (match_operand:BLK 0 "memory_operand" "") | |
2146 | (match_operand:BLK 1 "memory_operand" ""))) | |
2147 | (use (match_operand 2 "nonmemory_operand" "")) | |
2148 | (clobber (match_dup 3))])] | |
2149 | "" | |
2150 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2151 | |
b9404c99 | 2152 | (define_insn "*cmpmem_short" |
a41c6c53 UW |
2153 | [(set (reg:CCS 33) |
2154 | (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
2155 | (match_operand:BLK 1 "memory_operand" "Q,Q"))) | |
b9404c99 UW |
2156 | (use (match_operand 2 "nonmemory_operand" "n,a")) |
2157 | (clobber (match_scratch 3 "=X,&a"))] | |
2158 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) | |
2159 | && GET_MODE (operands[3]) == Pmode" | |
9db1d521 | 2160 | { |
a41c6c53 | 2161 | switch (which_alternative) |
9db1d521 | 2162 | { |
a41c6c53 | 2163 | case 0: |
d40c829f | 2164 | return "clc\t%O0(%b2+1,%R0),%1"; |
9db1d521 | 2165 | |
a41c6c53 | 2166 | case 1: |
d40c829f UW |
2167 | output_asm_insn ("bras\t%3,.+10", operands); |
2168 | output_asm_insn ("clc\t%O0(1,%R0),%1", operands); | |
2169 | return "ex\t%2,0(%3)"; | |
9db1d521 | 2170 | |
a41c6c53 UW |
2171 | default: |
2172 | abort (); | |
9db1d521 | 2173 | } |
10bbf137 | 2174 | } |
a41c6c53 UW |
2175 | [(set_attr "op_type" "SS,NN") |
2176 | (set_attr "type" "cs,cs") | |
077dab3b | 2177 | (set_attr "atype" "*,agen") |
a41c6c53 | 2178 | (set_attr "length" "*,14")]) |
9db1d521 | 2179 | |
a41c6c53 | 2180 | ; Compare a block of arbitrary length. |
9db1d521 | 2181 | |
b9404c99 UW |
2182 | (define_expand "cmpmem_long" |
2183 | [(parallel | |
2184 | [(clobber (match_dup 2)) | |
2185 | (clobber (match_dup 3)) | |
2186 | (set (reg:CCS 33) | |
2187 | (compare:CCS (match_operand:BLK 0 "memory_operand" "") | |
2188 | (match_operand:BLK 1 "memory_operand" ""))) | |
2189 | (use (match_operand 2 "general_operand" "")) | |
2190 | (use (match_dup 3))])] | |
2191 | "" | |
2192 | { | |
2193 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2194 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2195 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2196 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2197 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2198 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2199 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2200 | ||
2201 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2202 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2203 | emit_move_insn (len0, operands[2]); | |
2204 | ||
2205 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2206 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2207 | emit_move_insn (len1, operands[2]); | |
2208 | ||
2209 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2210 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2211 | operands[2] = reg0; | |
2212 | operands[3] = reg1; | |
2213 | }) | |
2214 | ||
2215 | (define_insn "*cmpmem_long_64" | |
4023fb28 UW |
2216 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2217 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2218 | (set (reg:CCS 33) | |
2219 | (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2220 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
2221 | (use (match_dup 2)) | |
2222 | (use (match_dup 3))] | |
9db1d521 | 2223 | "TARGET_64BIT" |
287ff198 UW |
2224 | "clcle\t%0,%1,0\;jo\t.-4" |
2225 | [(set_attr "op_type" "NN") | |
2226 | (set_attr "type" "vs") | |
2227 | (set_attr "length" "8")]) | |
9db1d521 | 2228 | |
b9404c99 | 2229 | (define_insn "*cmpmem_long_31" |
4023fb28 UW |
2230 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2231 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
2232 | (set (reg:CCS 33) | |
2233 | (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2234 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
2235 | (use (match_dup 2)) | |
2236 | (use (match_dup 3))] | |
9db1d521 | 2237 | "!TARGET_64BIT" |
287ff198 UW |
2238 | "clcle\t%0,%1,0\;jo\t.-4" |
2239 | [(set_attr "op_type" "NN") | |
2240 | (set_attr "type" "vs") | |
2241 | (set_attr "length" "8")]) | |
9db1d521 HP |
2242 | |
2243 | ; Convert condition code to integer in range (-1, 0, 1) | |
2244 | ||
2245 | (define_insn "cmpint_si" | |
2246 | [(set (match_operand:SI 0 "register_operand" "=d") | |
ba956982 | 2247 | (compare:SI (reg:CCS 33) (const_int 0)))] |
9db1d521 | 2248 | "" |
9db1d521 | 2249 | { |
d40c829f UW |
2250 | output_asm_insn ("lhi\t%0,1", operands); |
2251 | output_asm_insn ("jh\t.+12", operands); | |
2252 | output_asm_insn ("jl\t.+6", operands); | |
2253 | output_asm_insn ("sr\t%0,%0", operands); | |
2254 | return "lcr\t%0,%0"; | |
10bbf137 | 2255 | } |
9db1d521 HP |
2256 | [(set_attr "op_type" "NN") |
2257 | (set_attr "length" "16") | |
f2d3c02a | 2258 | (set_attr "type" "other")]) |
9db1d521 HP |
2259 | |
2260 | (define_insn "cmpint_di" | |
2261 | [(set (match_operand:DI 0 "register_operand" "=d") | |
ba956982 | 2262 | (compare:DI (reg:CCS 33) (const_int 0)))] |
9db1d521 | 2263 | "TARGET_64BIT" |
9db1d521 | 2264 | { |
d40c829f | 2265 | output_asm_insn ("lghi\t%0,1", operands); |
fd87a357 UW |
2266 | output_asm_insn ("jh\t.+16", operands); |
2267 | output_asm_insn ("jl\t.+8", operands); | |
d40c829f UW |
2268 | output_asm_insn ("sgr\t%0,%0", operands); |
2269 | return "lcgr\t%0,%0"; | |
10bbf137 | 2270 | } |
9db1d521 | 2271 | [(set_attr "op_type" "NN") |
fd87a357 | 2272 | (set_attr "length" "20") |
f2d3c02a | 2273 | (set_attr "type" "other")]) |
9db1d521 | 2274 | |
4023fb28 | 2275 | |
9db1d521 HP |
2276 | ;; |
2277 | ;;- Conversion instructions. | |
2278 | ;; | |
2279 | ||
4023fb28 | 2280 | (define_insn "*sethighqisi" |
d3632d41 | 2281 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2282 | (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2283 | (clobber (reg:CC 33))] |
2284 | "" | |
d3632d41 | 2285 | "@ |
d40c829f UW |
2286 | icm\t%0,8,%1 |
2287 | icmy\t%0,8,%1" | |
d3632d41 | 2288 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2289 | |
2290 | (define_insn "*sethighhisi" | |
d3632d41 | 2291 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2292 | (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2293 | (clobber (reg:CC 33))] |
2294 | "" | |
d3632d41 | 2295 | "@ |
d40c829f UW |
2296 | icm\t%0,12,%1 |
2297 | icmy\t%0,12,%1" | |
d3632d41 | 2298 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2299 | |
2300 | (define_insn "*sethighqidi_64" | |
2301 | [(set (match_operand:DI 0 "register_operand" "=d") | |
10bbf137 | 2302 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2303 | (clobber (reg:CC 33))] |
2304 | "TARGET_64BIT" | |
d40c829f | 2305 | "icmh\t%0,8,%1" |
d3632d41 | 2306 | [(set_attr "op_type" "RSY")]) |
4023fb28 UW |
2307 | |
2308 | (define_insn "*sethighqidi_31" | |
d3632d41 | 2309 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
10bbf137 | 2310 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2311 | (clobber (reg:CC 33))] |
2312 | "!TARGET_64BIT" | |
d3632d41 | 2313 | "@ |
d40c829f UW |
2314 | icm\t%0,8,%1 |
2315 | icmy\t%0,8,%1" | |
d3632d41 | 2316 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2317 | |
cc7ab9b7 UW |
2318 | (define_insn_and_split "*extractqi" |
2319 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2320 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2321 | (match_operand 2 "const_int_operand" "n") | |
2322 | (const_int 0))) | |
2323 | (clobber (reg:CC 33))] | |
2324 | "!TARGET_64BIT | |
4023fb28 | 2325 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
cc7ab9b7 UW |
2326 | "#" |
2327 | "&& reload_completed" | |
4023fb28 | 2328 | [(parallel |
10bbf137 | 2329 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2330 | (clobber (reg:CC 33))]) |
2331 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2332 | { |
2333 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2334 | operands[1] = change_address (operands[1], QImode, 0); | |
10bbf137 | 2335 | } |
0796c16a | 2336 | [(set_attr "atype" "agen")]) |
4023fb28 | 2337 | |
cc7ab9b7 UW |
2338 | (define_insn_and_split "*extracthi" |
2339 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2340 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2341 | (match_operand 2 "const_int_operand" "n") | |
2342 | (const_int 0))) | |
2343 | (clobber (reg:CC 33))] | |
2344 | "!TARGET_64BIT | |
4023fb28 | 2345 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
cc7ab9b7 UW |
2346 | "#" |
2347 | "&& reload_completed" | |
4023fb28 | 2348 | [(parallel |
10bbf137 | 2349 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2350 | (clobber (reg:CC 33))]) |
2351 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2352 | { |
2353 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2354 | operands[1] = change_address (operands[1], HImode, 0); | |
10bbf137 | 2355 | } |
0796c16a | 2356 | [(set_attr "atype" "agen")]) |
4023fb28 | 2357 | |
9db1d521 HP |
2358 | ; |
2359 | ; extendsidi2 instruction pattern(s). | |
2360 | ; | |
2361 | ||
4023fb28 UW |
2362 | (define_expand "extendsidi2" |
2363 | [(set (match_operand:DI 0 "register_operand" "") | |
2364 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2365 | "" | |
2366 | " | |
2367 | { | |
2368 | if (!TARGET_64BIT) | |
2369 | { | |
9f37ccb1 UW |
2370 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2371 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2372 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2373 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2374 | DONE; |
2375 | } | |
2376 | } | |
2377 | ") | |
2378 | ||
2379 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2380 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2381 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2382 | "TARGET_64BIT" | |
2383 | "@ | |
d40c829f UW |
2384 | lgfr\t%0,%1 |
2385 | lgf\t%0,%1" | |
d3632d41 | 2386 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2387 | |
9db1d521 HP |
2388 | ; |
2389 | ; extendhidi2 instruction pattern(s). | |
2390 | ; | |
2391 | ||
4023fb28 UW |
2392 | (define_expand "extendhidi2" |
2393 | [(set (match_operand:DI 0 "register_operand" "") | |
2394 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2395 | "" | |
2396 | " | |
2397 | { | |
2398 | if (!TARGET_64BIT) | |
2399 | { | |
2400 | rtx tmp = gen_reg_rtx (SImode); | |
2401 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
2402 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2403 | DONE; | |
2404 | } | |
2405 | else | |
2406 | { | |
2407 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2408 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2409 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2410 | DONE; |
2411 | } | |
2412 | } | |
2413 | ") | |
2414 | ||
2415 | (define_insn "*extendhidi2" | |
9db1d521 | 2416 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2417 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2418 | "TARGET_64BIT" |
d40c829f | 2419 | "lgh\t%0,%1" |
d3632d41 | 2420 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2421 | |
2422 | ; | |
2423 | ; extendqidi2 instruction pattern(s). | |
2424 | ; | |
2425 | ||
4023fb28 UW |
2426 | (define_expand "extendqidi2" |
2427 | [(set (match_operand:DI 0 "register_operand" "") | |
2428 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
2429 | "" | |
2430 | " | |
2431 | { | |
2432 | if (!TARGET_64BIT) | |
2433 | { | |
2434 | rtx tmp = gen_reg_rtx (SImode); | |
2435 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
2436 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2437 | DONE; | |
2438 | } | |
2439 | else | |
2440 | { | |
2441 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2442 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2443 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2444 | DONE; |
2445 | } | |
2446 | } | |
2447 | ") | |
2448 | ||
d3632d41 UW |
2449 | (define_insn "*extendqidi2" |
2450 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2451 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2452 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2453 | "lgb\t%0,%1" |
d3632d41 UW |
2454 | [(set_attr "op_type" "RXY")]) |
2455 | ||
19796784 AK |
2456 | (define_insn_and_split "*extendqidi2_short_displ" |
2457 | [(set (match_operand:DI 0 "register_operand" "=d") | |
59f8a8be UW |
2458 | (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) |
2459 | (clobber (reg:CC 33))] | |
19796784 AK |
2460 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" |
2461 | "#" | |
2462 | "&& reload_completed" | |
4023fb28 | 2463 | [(parallel |
10bbf137 | 2464 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2465 | (clobber (reg:CC 33))]) |
2466 | (parallel | |
2467 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
2468 | (clobber (reg:CC 33))])] | |
2469 | "") | |
9db1d521 HP |
2470 | |
2471 | ; | |
2472 | ; extendhisi2 instruction pattern(s). | |
2473 | ; | |
2474 | ||
4023fb28 UW |
2475 | (define_expand "extendhisi2" |
2476 | [(set (match_operand:SI 0 "register_operand" "") | |
2477 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2478 | "" |
4023fb28 UW |
2479 | " |
2480 | { | |
2481 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2482 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
c7453384 | 2483 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); |
4023fb28 UW |
2484 | DONE; |
2485 | } | |
2486 | ") | |
9db1d521 | 2487 | |
4023fb28 | 2488 | (define_insn "*extendhisi2" |
d3632d41 UW |
2489 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2490 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
4023fb28 | 2491 | "" |
d3632d41 | 2492 | "@ |
d40c829f UW |
2493 | lh\t%0,%1 |
2494 | lhy\t%0,%1" | |
d3632d41 | 2495 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
2496 | |
2497 | ; | |
2498 | ; extendqisi2 instruction pattern(s). | |
2499 | ; | |
2500 | ||
4023fb28 UW |
2501 | (define_expand "extendqisi2" |
2502 | [(set (match_operand:SI 0 "register_operand" "") | |
2503 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 | 2504 | "" |
4023fb28 UW |
2505 | " |
2506 | { | |
2507 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2508 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
c7453384 | 2509 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); |
4023fb28 UW |
2510 | DONE; |
2511 | } | |
2512 | ") | |
9db1d521 | 2513 | |
d3632d41 UW |
2514 | (define_insn "*extendqisi2" |
2515 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2516 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2517 | "TARGET_LONG_DISPLACEMENT" |
d40c829f | 2518 | "lb\t%0,%1" |
d3632d41 UW |
2519 | [(set_attr "op_type" "RXY")]) |
2520 | ||
eb457a7a | 2521 | (define_insn_and_split "*extendqisi2_short_displ" |
19796784 | 2522 | [(set (match_operand:SI 0 "register_operand" "=d") |
59f8a8be UW |
2523 | (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) |
2524 | (clobber (reg:CC 33))] | |
19796784 AK |
2525 | "!TARGET_LONG_DISPLACEMENT" |
2526 | "#" | |
2527 | "&& reload_completed" | |
4023fb28 | 2528 | [(parallel |
10bbf137 | 2529 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2530 | (clobber (reg:CC 33))]) |
2531 | (parallel | |
2532 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
2533 | (clobber (reg:CC 33))])] | |
2534 | "") | |
9db1d521 HP |
2535 | |
2536 | ; | |
2537 | ; extendqihi2 instruction pattern(s). | |
2538 | ; | |
2539 | ||
9db1d521 HP |
2540 | |
2541 | ; | |
2542 | ; zero_extendsidi2 instruction pattern(s). | |
2543 | ; | |
2544 | ||
4023fb28 UW |
2545 | (define_expand "zero_extendsidi2" |
2546 | [(set (match_operand:DI 0 "register_operand" "") | |
2547 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2548 | "" | |
2549 | " | |
2550 | { | |
2551 | if (!TARGET_64BIT) | |
2552 | { | |
9f37ccb1 UW |
2553 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2554 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2555 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2556 | DONE; |
2557 | } | |
2558 | } | |
2559 | ") | |
2560 | ||
2561 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2562 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2563 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2564 | "TARGET_64BIT" | |
2565 | "@ | |
d40c829f UW |
2566 | llgfr\t%0,%1 |
2567 | llgf\t%0,%1" | |
d3632d41 | 2568 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2569 | |
9db1d521 HP |
2570 | ; |
2571 | ; zero_extendhidi2 instruction pattern(s). | |
2572 | ; | |
2573 | ||
4023fb28 UW |
2574 | (define_expand "zero_extendhidi2" |
2575 | [(set (match_operand:DI 0 "register_operand" "") | |
2576 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2577 | "" | |
2578 | " | |
2579 | { | |
2580 | if (!TARGET_64BIT) | |
2581 | { | |
2582 | rtx tmp = gen_reg_rtx (SImode); | |
2583 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
2584 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
2585 | DONE; | |
2586 | } | |
2587 | else | |
2588 | { | |
2589 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2590 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2591 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2592 | DONE; |
2593 | } | |
2594 | } | |
2595 | ") | |
9db1d521 | 2596 | |
4023fb28 UW |
2597 | (define_insn "*zero_extendhidi2" |
2598 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2599 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
9db1d521 | 2600 | "TARGET_64BIT" |
d40c829f | 2601 | "llgh\t%0,%1" |
d3632d41 | 2602 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2603 | |
288e517f AK |
2604 | ; |
2605 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2606 | ; | |
2607 | ||
2608 | (define_insn "*llgt_sisi" | |
2609 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2610 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2611 | (const_int 2147483647)))] | |
2612 | "TARGET_64BIT" | |
2613 | "@ | |
2614 | llgtr\t%0,%1 | |
2615 | llgt\t%0,%1" | |
2616 | [(set_attr "op_type" "RRE,RXE")]) | |
2617 | ||
f19a9af7 AK |
2618 | (define_split |
2619 | [(set (match_operand:SI 0 "register_operand" "") | |
2620 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
288e517f AK |
2621 | (const_int 2147483647))) |
2622 | (clobber (reg:CC 33))] | |
f19a9af7 | 2623 | "TARGET_64BIT && reload_completed" |
288e517f AK |
2624 | [(set (match_dup 0) |
2625 | (and:SI (match_dup 1) | |
2626 | (const_int 2147483647)))] | |
2627 | "") | |
2628 | ||
2629 | (define_insn "*llgt_didi" | |
2630 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2631 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2632 | (const_int 2147483647)))] | |
2633 | "TARGET_64BIT" | |
2634 | "@ | |
2635 | llgtr\t%0,%1 | |
2636 | llgt\t%0,%N1" | |
2637 | [(set_attr "op_type" "RRE,RXE")]) | |
2638 | ||
f19a9af7 AK |
2639 | (define_split |
2640 | [(set (match_operand:DI 0 "register_operand" "") | |
2641 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
288e517f AK |
2642 | (const_int 2147483647))) |
2643 | (clobber (reg:CC 33))] | |
f19a9af7 | 2644 | "TARGET_64BIT && reload_completed" |
288e517f AK |
2645 | [(set (match_dup 0) |
2646 | (and:DI (match_dup 1) | |
2647 | (const_int 2147483647)))] | |
2648 | "") | |
2649 | ||
2650 | (define_insn "*llgt_sidi" | |
2651 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2652 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2653 | (const_int 2147483647)))] | |
2654 | "TARGET_64BIT" | |
2655 | "llgt\t%0,%1" | |
2656 | [(set_attr "op_type" "RXE")]) | |
2657 | ||
2658 | (define_insn_and_split "*llgt_sidi_split" | |
2659 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2f7e5a0d | 2660 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) |
288e517f AK |
2661 | (const_int 2147483647))) |
2662 | (clobber (reg:CC 33))] | |
2663 | "TARGET_64BIT" | |
2664 | "#" | |
2665 | "&& reload_completed" | |
2666 | [(set (match_dup 0) | |
2f7e5a0d | 2667 | (and:DI (subreg:DI (match_dup 1) 0) |
288e517f AK |
2668 | (const_int 2147483647)))] |
2669 | "") | |
2670 | ||
9db1d521 | 2671 | ; |
4023fb28 | 2672 | ; zero_extendqidi2 instruction pattern(s) |
9db1d521 HP |
2673 | ; |
2674 | ||
4023fb28 UW |
2675 | (define_expand "zero_extendqidi2" |
2676 | [(set (match_operand:DI 0 "register_operand" "") | |
2677 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 HP |
2678 | "" |
2679 | " | |
2680 | { | |
2681 | if (!TARGET_64BIT) | |
2682 | { | |
4023fb28 UW |
2683 | rtx tmp = gen_reg_rtx (SImode); |
2684 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
2685 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
9db1d521 HP |
2686 | DONE; |
2687 | } | |
4023fb28 UW |
2688 | else |
2689 | { | |
2690 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2691 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2692 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2693 | DONE; |
2694 | } | |
2695 | } | |
2696 | ") | |
9db1d521 | 2697 | |
4023fb28 UW |
2698 | (define_insn "*zero_extendqidi2" |
2699 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2700 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
9db1d521 | 2701 | "TARGET_64BIT" |
d40c829f | 2702 | "llgc\t%0,%1" |
d3632d41 | 2703 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2704 | |
2705 | ; | |
4023fb28 | 2706 | ; zero_extendhisi2 instruction pattern(s). |
9db1d521 HP |
2707 | ; |
2708 | ||
4023fb28 UW |
2709 | (define_expand "zero_extendhisi2" |
2710 | [(set (match_operand:SI 0 "register_operand" "") | |
2711 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2712 | "" |
4023fb28 UW |
2713 | " |
2714 | { | |
2715 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2716 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
2717 | DONE; | |
2718 | } | |
2719 | ") | |
9db1d521 | 2720 | |
4023fb28 | 2721 | (define_insn "*zero_extendhisi2_64" |
9db1d521 | 2722 | [(set (match_operand:SI 0 "register_operand" "=d") |
4023fb28 | 2723 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2724 | "TARGET_64BIT" |
d40c829f | 2725 | "llgh\t%0,%1" |
d3632d41 | 2726 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2727 | |
2728 | (define_insn_and_split "*zero_extendhisi2_31" | |
2729 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2730 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
cc7ab9b7 UW |
2731 | (clobber (reg:CC 33))] |
2732 | "!TARGET_64BIT" | |
2733 | "#" | |
2734 | "&& reload_completed" | |
2735 | [(set (match_dup 0) (const_int 0)) | |
2736 | (parallel | |
2737 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
2738 | (clobber (reg:CC 33))])] | |
2739 | "operands[2] = gen_lowpart (HImode, operands[0]);" | |
0796c16a | 2740 | [(set_attr "atype" "agen")]) |
c7453384 | 2741 | |
4023fb28 UW |
2742 | ; |
2743 | ; zero_extendqisi2 instruction pattern(s). | |
2744 | ; | |
9db1d521 HP |
2745 | |
2746 | (define_expand "zero_extendqisi2" | |
2747 | [(set (match_operand:SI 0 "register_operand" "") | |
4023fb28 | 2748 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
9db1d521 HP |
2749 | "" |
2750 | " | |
2751 | { | |
4023fb28 UW |
2752 | operands[1] = gen_lowpart (SImode, operands[1]); |
2753 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2754 | DONE; | |
2755 | } | |
2756 | ") | |
9db1d521 | 2757 | |
4023fb28 UW |
2758 | (define_insn "*zero_extendqisi2_64" |
2759 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2760 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2761 | "TARGET_ZARCH" |
d40c829f | 2762 | "llgc\t%0,%1" |
d3632d41 | 2763 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2764 | |
2765 | (define_insn_and_split "*zero_extendqisi2_31" | |
2766 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2767 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2768 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2769 | "#" |
2770 | "&& reload_completed" | |
2771 | [(set (match_dup 0) (const_int 0)) | |
2772 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2773 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
0796c16a | 2774 | [(set_attr "atype" "agen")]) |
c7453384 | 2775 | |
9db1d521 HP |
2776 | ; |
2777 | ; zero_extendqihi2 instruction pattern(s). | |
2778 | ; | |
2779 | ||
9db1d521 HP |
2780 | (define_expand "zero_extendqihi2" |
2781 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2782 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
9e8327e3 | 2783 | "TARGET_ZARCH" |
9db1d521 HP |
2784 | " |
2785 | { | |
4023fb28 UW |
2786 | operands[1] = gen_lowpart (HImode, operands[1]); |
2787 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2788 | DONE; | |
2789 | } | |
2790 | ") | |
9db1d521 | 2791 | |
4023fb28 | 2792 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2793 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2794 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
9e8327e3 | 2795 | "TARGET_ZARCH" |
d40c829f | 2796 | "llgc\t%0,%1" |
d3632d41 | 2797 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2798 | |
cc7ab9b7 UW |
2799 | (define_insn_and_split "*zero_extendqihi2_31" |
2800 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2801 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2802 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2803 | "#" |
2804 | "&& reload_completed" | |
2805 | [(set (match_dup 0) (const_int 0)) | |
2806 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2807 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
0796c16a | 2808 | [(set_attr "atype" "agen")]) |
cc7ab9b7 UW |
2809 | |
2810 | ||
9db1d521 HP |
2811 | ; |
2812 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
2813 | ; | |
2814 | ||
2815 | (define_expand "fixuns_truncdfdi2" | |
2816 | [(set (match_operand:DI 0 "register_operand" "") | |
2817 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
2818 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2819 | { |
2820 | rtx label1 = gen_label_rtx (); | |
2821 | rtx label2 = gen_label_rtx (); | |
2822 | rtx temp = gen_reg_rtx (DFmode); | |
2823 | operands[1] = force_reg (DFmode, operands[1]); | |
2824 | ||
c7453384 | 2825 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2826 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2827 | REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); |
9db1d521 | 2828 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2829 | emit_insn (gen_subdf3 (temp, operands[1], |
2830 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2831 | REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); |
9db1d521 | 2832 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2833 | emit_jump (label2); |
9db1d521 HP |
2834 | |
2835 | emit_label (label1); | |
2836 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2837 | emit_label (label2); | |
2838 | DONE; | |
10bbf137 | 2839 | }) |
9db1d521 HP |
2840 | |
2841 | (define_expand "fix_truncdfdi2" | |
2842 | [(set (match_operand:DI 0 "register_operand" "") | |
2843 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2844 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2845 | { |
2846 | operands[1] = force_reg (DFmode, operands[1]); | |
2847 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2848 | DONE; | |
10bbf137 | 2849 | }) |
9db1d521 HP |
2850 | |
2851 | (define_insn "fix_truncdfdi2_ieee" | |
2852 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2853 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2854 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2855 | (clobber (reg:CC 33))] |
2856 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2857 | "cgdbr\t%0,%h2,%1" |
9db1d521 | 2858 | [(set_attr "op_type" "RRE") |
077dab3b | 2859 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2860 | |
2861 | ; | |
2862 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
2863 | ; | |
2864 | ||
2865 | (define_expand "fixuns_truncdfsi2" | |
2866 | [(set (match_operand:SI 0 "register_operand" "") | |
2867 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
2868 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2869 | { |
2870 | rtx label1 = gen_label_rtx (); | |
2871 | rtx label2 = gen_label_rtx (); | |
2872 | rtx temp = gen_reg_rtx (DFmode); | |
2873 | ||
2874 | operands[1] = force_reg (DFmode,operands[1]); | |
c7453384 | 2875 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2876 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2877 | REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); |
9db1d521 | 2878 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2879 | emit_insn (gen_subdf3 (temp, operands[1], |
2880 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2881 | REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); |
9db1d521 | 2882 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2883 | emit_jump (label2); |
9db1d521 HP |
2884 | |
2885 | emit_label (label1); | |
2886 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2887 | emit_label (label2); | |
2888 | DONE; | |
10bbf137 | 2889 | }) |
9db1d521 HP |
2890 | |
2891 | (define_expand "fix_truncdfsi2" | |
2892 | [(set (match_operand:SI 0 "register_operand" "") | |
2893 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2894 | "TARGET_HARD_FLOAT" | |
9db1d521 | 2895 | { |
c7453384 | 2896 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2897 | { |
2898 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2899 | ||
c19ec8f9 | 2900 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
2901 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2902 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
2903 | |
2904 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 2905 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 2906 | two31r, two32, temp)); |
c7453384 EC |
2907 | } |
2908 | else | |
9db1d521 HP |
2909 | { |
2910 | operands[1] = force_reg (DFmode, operands[1]); | |
2911 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2912 | } | |
2913 | ||
2914 | DONE; | |
10bbf137 | 2915 | }) |
9db1d521 HP |
2916 | |
2917 | (define_insn "fix_truncdfsi2_ieee" | |
2918 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2919 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2920 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2921 | (clobber (reg:CC 33))] |
2922 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2923 | "cfdbr\t%0,%h2,%1" |
9db1d521 | 2924 | [(set_attr "op_type" "RRE") |
4023fb28 | 2925 | (set_attr "type" "other" )]) |
9db1d521 HP |
2926 | |
2927 | (define_insn "fix_truncdfsi2_ibm" | |
2928 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2929 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
2930 | (use (match_operand:DI 2 "immediate_operand" "m")) |
2931 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 HP |
2932 | (use (match_operand:BLK 4 "memory_operand" "m")) |
2933 | (clobber (reg:CC 33))] | |
2934 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 2935 | { |
d40c829f UW |
2936 | output_asm_insn ("sd\t%1,%2", operands); |
2937 | output_asm_insn ("aw\t%1,%3", operands); | |
2938 | output_asm_insn ("std\t%1,%4", operands); | |
2939 | output_asm_insn ("xi\t%N4,128", operands); | |
2940 | return "l\t%0,%N4"; | |
10bbf137 | 2941 | } |
9db1d521 | 2942 | [(set_attr "op_type" "NN") |
077dab3b HP |
2943 | (set_attr "type" "ftoi") |
2944 | (set_attr "atype" "agen") | |
9db1d521 HP |
2945 | (set_attr "length" "20")]) |
2946 | ||
2947 | ; | |
2948 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
2949 | ; | |
2950 | ||
2951 | (define_expand "fixuns_truncsfdi2" | |
2952 | [(set (match_operand:DI 0 "register_operand" "") | |
2953 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
2954 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2955 | { |
2956 | rtx label1 = gen_label_rtx (); | |
2957 | rtx label2 = gen_label_rtx (); | |
2958 | rtx temp = gen_reg_rtx (SFmode); | |
2959 | ||
2960 | operands[1] = force_reg (SFmode, operands[1]); | |
c7453384 | 2961 | emit_insn (gen_cmpsf (operands[1], |
4023fb28 | 2962 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2963 | REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); |
9db1d521 HP |
2964 | emit_jump_insn (gen_blt (label1)); |
2965 | ||
4023fb28 UW |
2966 | emit_insn (gen_subsf3 (temp, operands[1], |
2967 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2968 | REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); |
9db1d521 | 2969 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2970 | emit_jump (label2); |
9db1d521 HP |
2971 | |
2972 | emit_label (label1); | |
2973 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2974 | emit_label (label2); | |
2975 | DONE; | |
10bbf137 | 2976 | }) |
9db1d521 HP |
2977 | |
2978 | (define_expand "fix_truncsfdi2" | |
2979 | [(set (match_operand:DI 0 "register_operand" "") | |
2980 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2981 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2982 | { |
2983 | operands[1] = force_reg (SFmode, operands[1]); | |
2984 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2985 | DONE; | |
10bbf137 | 2986 | }) |
9db1d521 HP |
2987 | |
2988 | (define_insn "fix_truncsfdi2_ieee" | |
2989 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2990 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 2991 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2992 | (clobber (reg:CC 33))] |
2993 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2994 | "cgebr\t%0,%h2,%1" |
9db1d521 | 2995 | [(set_attr "op_type" "RRE") |
077dab3b | 2996 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2997 | |
2998 | ; | |
2999 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
3000 | ; | |
3001 | ||
3002 | (define_expand "fixuns_truncsfsi2" | |
3003 | [(set (match_operand:SI 0 "register_operand" "") | |
3004 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
3005 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3006 | { |
3007 | rtx label1 = gen_label_rtx (); | |
3008 | rtx label2 = gen_label_rtx (); | |
3009 | rtx temp = gen_reg_rtx (SFmode); | |
3010 | ||
3011 | operands[1] = force_reg (SFmode, operands[1]); | |
4023fb28 UW |
3012 | emit_insn (gen_cmpsf (operands[1], |
3013 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 3014 | REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); |
9db1d521 | 3015 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
3016 | emit_insn (gen_subsf3 (temp, operands[1], |
3017 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 3018 | REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); |
9db1d521 | 3019 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 3020 | emit_jump (label2); |
9db1d521 HP |
3021 | |
3022 | emit_label (label1); | |
3023 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3024 | emit_label (label2); | |
3025 | DONE; | |
10bbf137 | 3026 | }) |
9db1d521 HP |
3027 | |
3028 | (define_expand "fix_truncsfsi2" | |
3029 | [(set (match_operand:SI 0 "register_operand" "") | |
3030 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3031 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3032 | { |
3033 | if (TARGET_IBM_FLOAT) | |
3034 | { | |
3035 | /* Convert to DFmode and then use the POP algorithm. */ | |
3036 | rtx temp = gen_reg_rtx (DFmode); | |
3037 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
3038 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
3039 | } | |
3040 | else | |
3041 | { | |
3042 | operands[1] = force_reg (SFmode, operands[1]); | |
3043 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3044 | } | |
3045 | ||
3046 | DONE; | |
10bbf137 | 3047 | }) |
9db1d521 HP |
3048 | |
3049 | (define_insn "fix_truncsfsi2_ieee" | |
3050 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3051 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 3052 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
3053 | (clobber (reg:CC 33))] |
3054 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 3055 | "cfebr\t%0,%h2,%1" |
9db1d521 | 3056 | [(set_attr "op_type" "RRE") |
077dab3b | 3057 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
3058 | |
3059 | ; | |
3060 | ; floatdidf2 instruction pattern(s). | |
3061 | ; | |
3062 | ||
3063 | (define_insn "floatdidf2" | |
3064 | [(set (match_operand:DF 0 "register_operand" "=f") | |
4023fb28 UW |
3065 | (float:DF (match_operand:DI 1 "register_operand" "d"))) |
3066 | (clobber (reg:CC 33))] | |
9db1d521 | 3067 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3068 | "cdgbr\t%0,%1" |
9db1d521 | 3069 | [(set_attr "op_type" "RRE") |
f0bf1270 | 3070 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3071 | |
3072 | ; | |
3073 | ; floatdisf2 instruction pattern(s). | |
3074 | ; | |
3075 | ||
3076 | (define_insn "floatdisf2" | |
3077 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 UW |
3078 | (float:SF (match_operand:DI 1 "register_operand" "d"))) |
3079 | (clobber (reg:CC 33))] | |
9db1d521 | 3080 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3081 | "cegbr\t%0,%1" |
9db1d521 | 3082 | [(set_attr "op_type" "RRE") |
077dab3b | 3083 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3084 | |
3085 | ; | |
3086 | ; floatsidf2 instruction pattern(s). | |
3087 | ; | |
3088 | ||
3089 | (define_expand "floatsidf2" | |
4023fb28 UW |
3090 | [(parallel |
3091 | [(set (match_operand:DF 0 "register_operand" "") | |
3092 | (float:DF (match_operand:SI 1 "register_operand" ""))) | |
3093 | (clobber (reg:CC 33))])] | |
9db1d521 | 3094 | "TARGET_HARD_FLOAT" |
9db1d521 | 3095 | { |
c7453384 | 3096 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3097 | { |
3098 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
3099 | ||
c19ec8f9 | 3100 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 3101 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
3102 | |
3103 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
3104 | DONE; | |
3105 | } | |
10bbf137 | 3106 | }) |
9db1d521 HP |
3107 | |
3108 | (define_insn "floatsidf2_ieee" | |
3109 | [(set (match_operand:DF 0 "register_operand" "=f") | |
4023fb28 UW |
3110 | (float:DF (match_operand:SI 1 "register_operand" "d"))) |
3111 | (clobber (reg:CC 33))] | |
9db1d521 | 3112 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3113 | "cdfbr\t%0,%1" |
9db1d521 | 3114 | [(set_attr "op_type" "RRE") |
077dab3b | 3115 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3116 | |
3117 | (define_insn "floatsidf2_ibm" | |
3118 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3119 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3120 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 HP |
3121 | (use (match_operand:BLK 3 "memory_operand" "m")) |
3122 | (clobber (reg:CC 33))] | |
3123 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 3124 | { |
d40c829f UW |
3125 | output_asm_insn ("st\t%1,%N3", operands); |
3126 | output_asm_insn ("xi\t%N3,128", operands); | |
3127 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3128 | output_asm_insn ("ld\t%0,%3", operands); | |
3129 | return "sd\t%0,%2"; | |
10bbf137 | 3130 | } |
9db1d521 | 3131 | [(set_attr "op_type" "NN") |
4023fb28 | 3132 | (set_attr "type" "other" ) |
077dab3b | 3133 | (set_attr "atype" "agen") |
9db1d521 HP |
3134 | (set_attr "length" "20")]) |
3135 | ||
3136 | ; | |
3137 | ; floatsisf2 instruction pattern(s). | |
3138 | ; | |
3139 | ||
3140 | (define_expand "floatsisf2" | |
4023fb28 UW |
3141 | [(parallel |
3142 | [(set (match_operand:SF 0 "register_operand" "") | |
3143 | (float:SF (match_operand:SI 1 "register_operand" ""))) | |
3144 | (clobber (reg:CC 33))])] | |
9db1d521 | 3145 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3146 | { |
3147 | if (TARGET_IBM_FLOAT) | |
3148 | { | |
3149 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3150 | rtx temp = gen_reg_rtx (DFmode); | |
3151 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3152 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3153 | DONE; | |
3154 | } | |
10bbf137 | 3155 | }) |
9db1d521 HP |
3156 | |
3157 | (define_insn "floatsisf2_ieee" | |
3158 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 UW |
3159 | (float:SF (match_operand:SI 1 "register_operand" "d"))) |
3160 | (clobber (reg:CC 33))] | |
9db1d521 | 3161 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3162 | "cefbr\t%0,%1" |
9db1d521 | 3163 | [(set_attr "op_type" "RRE") |
077dab3b | 3164 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3165 | |
3166 | ; | |
3167 | ; truncdfsf2 instruction pattern(s). | |
3168 | ; | |
3169 | ||
3170 | (define_expand "truncdfsf2" | |
3171 | [(set (match_operand:SF 0 "register_operand" "") | |
3172 | (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] | |
3173 | "TARGET_HARD_FLOAT" | |
4023fb28 | 3174 | "") |
9db1d521 HP |
3175 | |
3176 | (define_insn "truncdfsf2_ieee" | |
3177 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 | 3178 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] |
9db1d521 | 3179 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3180 | "ledbr\t%0,%1" |
ce50cae8 | 3181 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
3182 | |
3183 | (define_insn "truncdfsf2_ibm" | |
3184 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 3185 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
3186 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3187 | "@ | |
d40c829f UW |
3188 | lrer\t%0,%1 |
3189 | le\t%0,%1" | |
4023fb28 | 3190 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3191 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3192 | |
3193 | ; | |
3194 | ; extendsfdf2 instruction pattern(s). | |
3195 | ; | |
3196 | ||
3197 | (define_expand "extendsfdf2" | |
3198 | [(set (match_operand:DF 0 "register_operand" "") | |
3199 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3200 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3201 | { |
3202 | if (TARGET_IBM_FLOAT) | |
3203 | { | |
3204 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3205 | DONE; | |
3206 | } | |
10bbf137 | 3207 | }) |
9db1d521 HP |
3208 | |
3209 | (define_insn "extendsfdf2_ieee" | |
3210 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3211 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3212 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3213 | "@ | |
d40c829f UW |
3214 | ldebr\t%0,%1 |
3215 | ldeb\t%0,%1" | |
077dab3b HP |
3216 | [(set_attr "op_type" "RRE,RXE") |
3217 | (set_attr "type" "floads,floads")]) | |
9db1d521 HP |
3218 | |
3219 | (define_insn "extendsfdf2_ibm" | |
3220 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3221 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
9db1d521 HP |
3222 | (clobber (reg:CC 33))] |
3223 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3224 | "@ | |
d40c829f UW |
3225 | sdr\t%0,%0\;ler\t%0,%1 |
3226 | sdr\t%0,%0\;le\t%0,%1" | |
077dab3b HP |
3227 | [(set_attr "op_type" "NN,NN") |
3228 | (set_attr "atype" "reg,agen") | |
3229 | (set_attr "length" "4,6") | |
c7453384 | 3230 | (set_attr "type" "o2,o2")]) |
9db1d521 HP |
3231 | |
3232 | ||
3233 | ;; | |
fae778eb | 3234 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3235 | ;; |
fae778eb | 3236 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3237 | ; because of unpredictable Bits in Register for Halfword and Byte |
3238 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3239 | ||
07893d4f UW |
3240 | ;; |
3241 | ;;- Add instructions. | |
3242 | ;; | |
3243 | ||
1c7b1b7e UW |
3244 | ; |
3245 | ; addti3 instruction pattern(s). | |
3246 | ; | |
3247 | ||
3248 | (define_insn_and_split "addti3" | |
3249 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3250 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
3251 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3252 | (clobber (reg:CC 33))] | |
3253 | "TARGET_64BIT" | |
3254 | "#" | |
3255 | "&& reload_completed" | |
3256 | [(parallel | |
3257 | [(set (reg:CCL1 33) | |
3258 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) | |
3259 | (match_dup 7))) | |
3260 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
3261 | (parallel | |
3262 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
3263 | (ltu:DI (reg:CCL1 33) (const_int 0)))) | |
3264 | (clobber (reg:CC 33))])] | |
3265 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3266 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3267 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3268 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3269 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
3270 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" | |
3271 | [(set_attr "op_type" "NN")]) | |
3272 | ||
07893d4f UW |
3273 | ; |
3274 | ; adddi3 instruction pattern(s). | |
3275 | ; | |
3276 | ||
07893d4f UW |
3277 | (define_insn "*adddi3_sign" |
3278 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3279 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3280 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3281 | (clobber (reg:CC 33))] | |
3282 | "TARGET_64BIT" | |
3283 | "@ | |
d40c829f UW |
3284 | agfr\t%0,%2 |
3285 | agf\t%0,%2" | |
d3632d41 | 3286 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3287 | |
3288 | (define_insn "*adddi3_zero_cc" | |
c7453384 | 3289 | [(set (reg 33) |
07893d4f UW |
3290 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3291 | (match_operand:DI 1 "register_operand" "0,0")) | |
3292 | (const_int 0))) | |
3293 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3294 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3295 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3296 | "@ | |
d40c829f UW |
3297 | algfr\t%0,%2 |
3298 | algf\t%0,%2" | |
d3632d41 | 3299 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3300 | |
3301 | (define_insn "*adddi3_zero_cconly" | |
c7453384 | 3302 | [(set (reg 33) |
07893d4f UW |
3303 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3304 | (match_operand:DI 1 "register_operand" "0,0")) | |
3305 | (const_int 0))) | |
3306 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3307 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3308 | "@ | |
d40c829f UW |
3309 | algfr\t%0,%2 |
3310 | algf\t%0,%2" | |
d3632d41 | 3311 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3312 | |
3313 | (define_insn "*adddi3_zero" | |
3314 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3315 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3316 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3317 | (clobber (reg:CC 33))] | |
3318 | "TARGET_64BIT" | |
3319 | "@ | |
d40c829f UW |
3320 | algfr\t%0,%2 |
3321 | algf\t%0,%2" | |
d3632d41 | 3322 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3323 | |
0a3bdf9d | 3324 | (define_insn "*adddi3_imm_cc" |
c7453384 | 3325 | [(set (reg 33) |
0a3bdf9d UW |
3326 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
3327 | (match_operand:DI 2 "const_int_operand" "K")) | |
3328 | (const_int 0))) | |
3329 | (set (match_operand:DI 0 "register_operand" "=d") | |
3330 | (plus:DI (match_dup 1) (match_dup 2)))] | |
c7453384 EC |
3331 | "TARGET_64BIT |
3332 | && s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3333 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3334 | "aghi\t%0,%h2" |
077dab3b | 3335 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3336 | |
b2ba71ca UW |
3337 | (define_insn "*adddi3_carry1_cc" |
3338 | [(set (reg 33) | |
3339 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3340 | (match_operand:DI 2 "general_operand" "d,m")) | |
3341 | (match_dup 1))) | |
3342 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3343 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3344 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3345 | "@ | |
3346 | algr\t%0,%2 | |
3347 | alg\t%0,%2" | |
3348 | [(set_attr "op_type" "RRE,RXY")]) | |
3349 | ||
3350 | (define_insn "*adddi3_carry1_cconly" | |
3351 | [(set (reg 33) | |
3352 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3353 | (match_operand:DI 2 "general_operand" "d,m")) | |
3354 | (match_dup 1))) | |
3355 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3356 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3357 | "@ | |
3358 | algr\t%0,%2 | |
3359 | alg\t%0,%2" | |
3360 | [(set_attr "op_type" "RRE,RXY")]) | |
3361 | ||
3362 | (define_insn "*adddi3_carry2_cc" | |
3363 | [(set (reg 33) | |
3364 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3365 | (match_operand:DI 2 "general_operand" "d,m")) | |
3366 | (match_dup 2))) | |
3367 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3368 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3369 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3370 | "@ | |
3371 | algr\t%0,%2 | |
3372 | alg\t%0,%2" | |
3373 | [(set_attr "op_type" "RRE,RXY")]) | |
3374 | ||
3375 | (define_insn "*adddi3_carry2_cconly" | |
3376 | [(set (reg 33) | |
3377 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3378 | (match_operand:DI 2 "general_operand" "d,m")) | |
3379 | (match_dup 2))) | |
3380 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3381 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3382 | "@ | |
3383 | algr\t%0,%2 | |
3384 | alg\t%0,%2" | |
3385 | [(set_attr "op_type" "RRE,RXY")]) | |
3386 | ||
07893d4f | 3387 | (define_insn "*adddi3_cc" |
c7453384 | 3388 | [(set (reg 33) |
96fd3851 | 3389 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3390 | (match_operand:DI 2 "general_operand" "d,m")) |
3391 | (const_int 0))) | |
3392 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3393 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3394 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3395 | "@ | |
d40c829f UW |
3396 | algr\t%0,%2 |
3397 | alg\t%0,%2" | |
d3632d41 | 3398 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3399 | |
07893d4f | 3400 | (define_insn "*adddi3_cconly" |
c7453384 | 3401 | [(set (reg 33) |
96fd3851 | 3402 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3403 | (match_operand:DI 2 "general_operand" "d,m")) |
3404 | (const_int 0))) | |
3405 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3406 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3407 | "@ | |
d40c829f UW |
3408 | algr\t%0,%2 |
3409 | alg\t%0,%2" | |
d3632d41 | 3410 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3411 | |
07893d4f | 3412 | (define_insn "*adddi3_cconly2" |
c7453384 | 3413 | [(set (reg 33) |
96fd3851 | 3414 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3415 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3416 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3417 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3418 | "@ |
d40c829f UW |
3419 | algr\t%0,%2 |
3420 | alg\t%0,%2" | |
d3632d41 | 3421 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3422 | |
07893d4f | 3423 | (define_insn "*adddi3_64" |
9db1d521 | 3424 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3425 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
9db1d521 HP |
3426 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
3427 | (clobber (reg:CC 33))] | |
3428 | "TARGET_64BIT" | |
3429 | "@ | |
d40c829f UW |
3430 | agr\t%0,%2 |
3431 | aghi\t%0,%h2 | |
3432 | ag\t%0,%2" | |
d3632d41 | 3433 | [(set_attr "op_type" "RRE,RI,RXY")]) |
9db1d521 | 3434 | |
e69166de UW |
3435 | (define_insn_and_split "*adddi3_31z" |
3436 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3437 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3438 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3439 | (clobber (reg:CC 33))] | |
3440 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3441 | "#" | |
3442 | "&& reload_completed" | |
3443 | [(parallel | |
3444 | [(set (reg:CCL1 33) | |
3445 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3446 | (match_dup 7))) | |
3447 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3448 | (parallel | |
3449 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
3450 | (ltu:SI (reg:CCL1 33) (const_int 0)))) | |
3451 | (clobber (reg:CC 33))])] | |
3452 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3453 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3454 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3455 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3456 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3457 | operands[8] = operand_subword (operands[2], 1, 0, DImode);" | |
3458 | [(set_attr "op_type" "NN")]) | |
3459 | ||
07893d4f UW |
3460 | (define_insn_and_split "*adddi3_31" |
3461 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3462 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3463 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3464 | (clobber (reg:CC 33))] |
e69166de | 3465 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3466 | "#" |
3467 | "&& reload_completed" | |
3468 | [(parallel | |
3469 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
3470 | (clobber (reg:CC 33))]) | |
3471 | (parallel | |
3472 | [(set (reg:CCL1 33) | |
3473 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3474 | (match_dup 7))) | |
3475 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3476 | (set (pc) | |
3477 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
3478 | (pc) | |
3479 | (label_ref (match_dup 9)))) | |
3480 | (parallel | |
3481 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
3482 | (clobber (reg:CC 33))]) | |
3483 | (match_dup 9)] | |
97c6f7ad UW |
3484 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3485 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3486 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3487 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3488 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3489 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
07893d4f | 3490 | operands[9] = gen_label_rtx ();" |
0796c16a | 3491 | [(set_attr "op_type" "NN")]) |
9db1d521 HP |
3492 | |
3493 | (define_expand "adddi3" | |
07893d4f UW |
3494 | [(parallel |
3495 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3496 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f UW |
3497 | (match_operand:DI 2 "general_operand" ""))) |
3498 | (clobber (reg:CC 33))])] | |
9db1d521 | 3499 | "" |
07893d4f | 3500 | "") |
9db1d521 | 3501 | |
9db1d521 HP |
3502 | ; |
3503 | ; addsi3 instruction pattern(s). | |
3504 | ; | |
9db1d521 | 3505 | |
0a3bdf9d | 3506 | (define_insn "*addsi3_imm_cc" |
c7453384 | 3507 | [(set (reg 33) |
0a3bdf9d UW |
3508 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3509 | (match_operand:SI 2 "const_int_operand" "K")) | |
3510 | (const_int 0))) | |
3511 | (set (match_operand:SI 0 "register_operand" "=d") | |
3512 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3513 | "s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3514 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3515 | "ahi\t%0,%h2" |
077dab3b | 3516 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3517 | |
07893d4f | 3518 | (define_insn "*addsi3_carry1_cc" |
c7453384 | 3519 | [(set (reg 33) |
d3632d41 UW |
3520 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3521 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3522 | (match_dup 1))) |
d3632d41 | 3523 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3524 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3525 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3526 | "@ |
d40c829f UW |
3527 | alr\t%0,%2 |
3528 | al\t%0,%2 | |
3529 | aly\t%0,%2" | |
d3632d41 | 3530 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3531 | |
3532 | (define_insn "*addsi3_carry1_cconly" | |
c7453384 | 3533 | [(set (reg 33) |
d3632d41 UW |
3534 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3535 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3536 | (match_dup 1))) |
d3632d41 | 3537 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3538 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3539 | "@ |
d40c829f UW |
3540 | alr\t%0,%2 |
3541 | al\t%0,%2 | |
3542 | aly\t%0,%2" | |
d3632d41 | 3543 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3544 | |
3545 | (define_insn "*addsi3_carry2_cc" | |
c7453384 | 3546 | [(set (reg 33) |
d3632d41 UW |
3547 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3548 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3549 | (match_dup 2))) |
d3632d41 | 3550 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3551 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3552 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3553 | "@ |
d40c829f UW |
3554 | alr\t%0,%2 |
3555 | al\t%0,%2 | |
3556 | aly\t%0,%2" | |
d3632d41 | 3557 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3558 | |
3559 | (define_insn "*addsi3_carry2_cconly" | |
c7453384 | 3560 | [(set (reg 33) |
d3632d41 UW |
3561 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3562 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3563 | (match_dup 2))) |
d3632d41 | 3564 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3565 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3566 | "@ |
d40c829f UW |
3567 | alr\t%0,%2 |
3568 | al\t%0,%2 | |
3569 | aly\t%0,%2" | |
d3632d41 | 3570 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3571 | |
9db1d521 | 3572 | (define_insn "*addsi3_cc" |
c7453384 | 3573 | [(set (reg 33) |
d3632d41 UW |
3574 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3575 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3576 | (const_int 0))) |
d3632d41 | 3577 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3578 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3579 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3580 | "@ |
d40c829f UW |
3581 | alr\t%0,%2 |
3582 | al\t%0,%2 | |
3583 | aly\t%0,%2" | |
d3632d41 | 3584 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3585 | |
3586 | (define_insn "*addsi3_cconly" | |
c7453384 | 3587 | [(set (reg 33) |
d3632d41 UW |
3588 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3589 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3590 | (const_int 0))) |
d3632d41 | 3591 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3592 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3593 | "@ |
d40c829f UW |
3594 | alr\t%0,%2 |
3595 | al\t%0,%2 | |
3596 | aly\t%0,%2" | |
d3632d41 | 3597 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3598 | |
3599 | (define_insn "*addsi3_cconly2" | |
c7453384 | 3600 | [(set (reg 33) |
d3632d41 UW |
3601 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3602 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3603 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3604 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3605 | "@ |
d40c829f UW |
3606 | alr\t%0,%2 |
3607 | al\t%0,%2 | |
3608 | aly\t%0,%2" | |
d3632d41 | 3609 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3610 | |
07893d4f | 3611 | (define_insn "*addsi3_sign" |
d3632d41 UW |
3612 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3613 | (plus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3614 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
3615 | (clobber (reg:CC 33))] |
3616 | "" | |
d3632d41 | 3617 | "@ |
d40c829f UW |
3618 | ah\t%0,%2 |
3619 | ahy\t%0,%2" | |
d3632d41 | 3620 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3621 | |
9db1d521 | 3622 | (define_insn "addsi3" |
d3632d41 UW |
3623 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3624 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3625 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
9db1d521 HP |
3626 | (clobber (reg:CC 33))] |
3627 | "" | |
3628 | "@ | |
d40c829f UW |
3629 | ar\t%0,%2 |
3630 | ahi\t%0,%h2 | |
3631 | a\t%0,%2 | |
3632 | ay\t%0,%2" | |
d3632d41 | 3633 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
9db1d521 | 3634 | |
9db1d521 HP |
3635 | ; |
3636 | ; adddf3 instruction pattern(s). | |
3637 | ; | |
3638 | ||
3639 | (define_expand "adddf3" | |
3640 | [(parallel | |
3641 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3642 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3643 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3644 | (clobber (reg:CC 33))])] |
3645 | "TARGET_HARD_FLOAT" | |
3646 | "") | |
3647 | ||
3648 | (define_insn "*adddf3" | |
3649 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3650 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3651 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3652 | (clobber (reg:CC 33))] |
3653 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3654 | "@ | |
d40c829f UW |
3655 | adbr\t%0,%2 |
3656 | adb\t%0,%2" | |
ce50cae8 | 3657 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3658 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3659 | |
3ef093a8 AK |
3660 | (define_insn "*adddf3_cc" |
3661 | [(set (reg 33) | |
3662 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3663 | (match_operand:DF 2 "general_operand" "f,R")) | |
3664 | (match_operand:DF 3 "const0_operand" ""))) | |
3665 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
3666 | (plus:DF (match_dup 1) (match_dup 2)))] | |
3667 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3668 | "@ | |
d40c829f UW |
3669 | adbr\t%0,%2 |
3670 | adb\t%0,%2" | |
3ef093a8 AK |
3671 | [(set_attr "op_type" "RRE,RXE") |
3672 | (set_attr "type" "fsimpd,fsimpd")]) | |
3673 | ||
3674 | (define_insn "*adddf3_cconly" | |
3675 | [(set (reg 33) | |
3676 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3677 | (match_operand:DF 2 "general_operand" "f,R")) | |
3678 | (match_operand:DF 3 "const0_operand" ""))) | |
3679 | (clobber (match_scratch:DF 0 "=f,f"))] | |
3680 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3681 | "@ | |
d40c829f UW |
3682 | adbr\t%0,%2 |
3683 | adb\t%0,%2" | |
3ef093a8 AK |
3684 | [(set_attr "op_type" "RRE,RXE") |
3685 | (set_attr "type" "fsimpd,fsimpd")]) | |
3686 | ||
9db1d521 HP |
3687 | (define_insn "*adddf3_ibm" |
3688 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3689 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3690 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3691 | (clobber (reg:CC 33))] |
3692 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3693 | "@ | |
d40c829f UW |
3694 | adr\t%0,%2 |
3695 | ad\t%0,%2" | |
9db1d521 | 3696 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3697 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
3698 | |
3699 | ; | |
3700 | ; addsf3 instruction pattern(s). | |
3701 | ; | |
3702 | ||
3703 | (define_expand "addsf3" | |
3704 | [(parallel | |
3705 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3706 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3707 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3708 | (clobber (reg:CC 33))])] |
3709 | "TARGET_HARD_FLOAT" | |
3710 | "") | |
3711 | ||
3712 | (define_insn "*addsf3" | |
3713 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3714 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3715 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3716 | (clobber (reg:CC 33))] |
3717 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3718 | "@ | |
d40c829f UW |
3719 | aebr\t%0,%2 |
3720 | aeb\t%0,%2" | |
ce50cae8 | 3721 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3722 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 3723 | |
3ef093a8 AK |
3724 | (define_insn "*addsf3_cc" |
3725 | [(set (reg 33) | |
3726 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3727 | (match_operand:SF 2 "general_operand" "f,R")) | |
3728 | (match_operand:SF 3 "const0_operand" ""))) | |
3729 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
3730 | (plus:SF (match_dup 1) (match_dup 2)))] | |
3731 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3732 | "@ | |
d40c829f UW |
3733 | aebr\t%0,%2 |
3734 | aeb\t%0,%2" | |
3ef093a8 AK |
3735 | [(set_attr "op_type" "RRE,RXE") |
3736 | (set_attr "type" "fsimps,fsimps")]) | |
3737 | ||
3738 | (define_insn "*addsf3_cconly" | |
3739 | [(set (reg 33) | |
3740 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3741 | (match_operand:SF 2 "general_operand" "f,R")) | |
3742 | (match_operand:SF 3 "const0_operand" ""))) | |
3743 | (clobber (match_scratch:SF 0 "=f,f"))] | |
3744 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3745 | "@ | |
d40c829f UW |
3746 | aebr\t%0,%2 |
3747 | aeb\t%0,%2" | |
3ef093a8 AK |
3748 | [(set_attr "op_type" "RRE,RXE") |
3749 | (set_attr "type" "fsimps,fsimps")]) | |
3750 | ||
9db1d521 HP |
3751 | (define_insn "*addsf3" |
3752 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3753 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3754 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3755 | (clobber (reg:CC 33))] |
3756 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3757 | "@ | |
d40c829f UW |
3758 | aer\t%0,%2 |
3759 | ae\t%0,%2" | |
9db1d521 | 3760 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3761 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
3762 | |
3763 | ||
3764 | ;; | |
3765 | ;;- Subtract instructions. | |
3766 | ;; | |
3767 | ||
1c7b1b7e UW |
3768 | ; |
3769 | ; subti3 instruction pattern(s). | |
3770 | ; | |
3771 | ||
3772 | (define_insn_and_split "subti3" | |
3773 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3774 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3775 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3776 | (clobber (reg:CC 33))] | |
3777 | "TARGET_64BIT" | |
3778 | "#" | |
3779 | "&& reload_completed" | |
3780 | [(parallel | |
3781 | [(set (reg:CCL2 33) | |
3782 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) | |
3783 | (match_dup 7))) | |
3784 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3785 | (parallel | |
3786 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
3787 | (gtu:DI (reg:CCL2 33) (const_int 0)))) | |
3788 | (clobber (reg:CC 33))])] | |
3789 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3790 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3791 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3792 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3793 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
3794 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" | |
3795 | [(set_attr "op_type" "NN")]) | |
3796 | ||
9db1d521 HP |
3797 | ; |
3798 | ; subdi3 instruction pattern(s). | |
3799 | ; | |
3800 | ||
07893d4f UW |
3801 | (define_insn "*subdi3_sign" |
3802 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3803 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3804 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3805 | (clobber (reg:CC 33))] | |
3806 | "TARGET_64BIT" | |
3807 | "@ | |
d40c829f UW |
3808 | sgfr\t%0,%2 |
3809 | sgf\t%0,%2" | |
d3632d41 | 3810 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3811 | |
3812 | (define_insn "*subdi3_zero_cc" | |
c7453384 | 3813 | [(set (reg 33) |
07893d4f UW |
3814 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3815 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3816 | (const_int 0))) | |
3817 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3818 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3819 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3820 | "@ | |
d40c829f UW |
3821 | slgfr\t%0,%2 |
3822 | slgf\t%0,%2" | |
d3632d41 | 3823 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3824 | |
3825 | (define_insn "*subdi3_zero_cconly" | |
c7453384 | 3826 | [(set (reg 33) |
07893d4f UW |
3827 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3828 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3829 | (const_int 0))) | |
3830 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3831 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3832 | "@ | |
d40c829f UW |
3833 | slgfr\t%0,%2 |
3834 | slgf\t%0,%2" | |
d3632d41 | 3835 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3836 | |
3837 | (define_insn "*subdi3_zero" | |
3838 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3839 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3840 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3841 | (clobber (reg:CC 33))] | |
3842 | "TARGET_64BIT" | |
3843 | "@ | |
d40c829f UW |
3844 | slgfr\t%0,%2 |
3845 | slgf\t%0,%2" | |
d3632d41 | 3846 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3847 | |
b2ba71ca UW |
3848 | (define_insn "*subdi3_borrow_cc" |
3849 | [(set (reg 33) | |
3850 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3851 | (match_operand:DI 2 "general_operand" "d,m")) | |
3852 | (match_dup 1))) | |
3853 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3854 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3855 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3856 | "@ | |
3857 | slgr\t%0,%2 | |
3858 | slg\t%0,%2" | |
3859 | [(set_attr "op_type" "RRE,RXY")]) | |
3860 | ||
3861 | (define_insn "*subdi3_borrow_cconly" | |
3862 | [(set (reg 33) | |
3863 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3864 | (match_operand:DI 2 "general_operand" "d,m")) | |
3865 | (match_dup 1))) | |
3866 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3867 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3868 | "@ | |
3869 | slgr\t%0,%2 | |
3870 | slg\t%0,%2" | |
3871 | [(set_attr "op_type" "RRE,RXY")]) | |
3872 | ||
07893d4f UW |
3873 | (define_insn "*subdi3_cc" |
3874 | [(set (reg 33) | |
3875 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3876 | (match_operand:DI 2 "general_operand" "d,m")) | |
3877 | (const_int 0))) | |
3878 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3879 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3880 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3881 | "@ |
d40c829f UW |
3882 | slgr\t%0,%2 |
3883 | slg\t%0,%2" | |
d3632d41 | 3884 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3885 | |
5d880bd2 UW |
3886 | (define_insn "*subdi3_cc2" |
3887 | [(set (reg 33) | |
3888 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
3889 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3890 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3891 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3892 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3893 | "@ | |
3894 | slgr\t%0,%2 | |
3895 | slg\t%0,%2" | |
3896 | [(set_attr "op_type" "RRE,RXY")]) | |
3897 | ||
07893d4f UW |
3898 | (define_insn "*subdi3_cconly" |
3899 | [(set (reg 33) | |
3900 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3901 | (match_operand:DI 2 "general_operand" "d,m")) | |
3902 | (const_int 0))) | |
3903 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3904 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3905 | "@ |
d40c829f UW |
3906 | slgr\t%0,%2 |
3907 | slg\t%0,%2" | |
d3632d41 | 3908 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3909 | |
5d880bd2 UW |
3910 | (define_insn "*subdi3_cconly2" |
3911 | [(set (reg 33) | |
3912 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
3913 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3914 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3915 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3916 | "@ | |
3917 | slgr\t%0,%2 | |
3918 | slg\t%0,%2" | |
3919 | [(set_attr "op_type" "RRE,RXY")]) | |
3920 | ||
9db1d521 HP |
3921 | (define_insn "*subdi3_64" |
3922 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3923 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3924 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
3925 | (clobber (reg:CC 33))] | |
3926 | "TARGET_64BIT" | |
3927 | "@ | |
d40c829f UW |
3928 | sgr\t%0,%2 |
3929 | sg\t%0,%2" | |
077dab3b | 3930 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3931 | |
e69166de UW |
3932 | (define_insn_and_split "*subdi3_31z" |
3933 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3934 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3935 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3936 | (clobber (reg:CC 33))] | |
3937 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3938 | "#" | |
3939 | "&& reload_completed" | |
3940 | [(parallel | |
3941 | [(set (reg:CCL2 33) | |
3942 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3943 | (match_dup 7))) | |
3944 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3945 | (parallel | |
3946 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
3947 | (gtu:SI (reg:CCL2 33) (const_int 0)))) | |
3948 | (clobber (reg:CC 33))])] | |
3949 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3950 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3951 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3952 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3953 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3954 | operands[8] = operand_subword (operands[2], 1, 0, DImode);" | |
3955 | [(set_attr "op_type" "NN")]) | |
3956 | ||
07893d4f UW |
3957 | (define_insn_and_split "*subdi3_31" |
3958 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3959 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3960 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3961 | (clobber (reg:CC 33))] |
e69166de | 3962 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3963 | "#" |
3964 | "&& reload_completed" | |
3965 | [(parallel | |
3966 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
3967 | (clobber (reg:CC 33))]) | |
3968 | (parallel | |
3969 | [(set (reg:CCL2 33) | |
3970 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3971 | (match_dup 7))) | |
3972 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3973 | (set (pc) | |
3974 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
3975 | (pc) | |
3976 | (label_ref (match_dup 9)))) | |
3977 | (parallel | |
3978 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
3979 | (clobber (reg:CC 33))]) | |
3980 | (match_dup 9)] | |
97c6f7ad UW |
3981 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3982 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3983 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3984 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3985 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3986 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
07893d4f | 3987 | operands[9] = gen_label_rtx ();" |
0796c16a | 3988 | [(set_attr "op_type" "NN")]) |
07893d4f UW |
3989 | |
3990 | (define_expand "subdi3" | |
3991 | [(parallel | |
3992 | [(set (match_operand:DI 0 "register_operand" "") | |
3993 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3994 | (match_operand:DI 2 "general_operand" ""))) | |
3995 | (clobber (reg:CC 33))])] | |
9db1d521 | 3996 | "" |
07893d4f | 3997 | "") |
9db1d521 HP |
3998 | |
3999 | ; | |
4000 | ; subsi3 instruction pattern(s). | |
4001 | ; | |
4002 | ||
07893d4f UW |
4003 | (define_insn "*subsi3_borrow_cc" |
4004 | [(set (reg 33) | |
d3632d41 UW |
4005 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4006 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 4007 | (match_dup 1))) |
d3632d41 | 4008 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 4009 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4010 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4011 | "@ |
d40c829f UW |
4012 | slr\t%0,%2 |
4013 | sl\t%0,%2 | |
4014 | sly\t%0,%2" | |
d3632d41 | 4015 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
4016 | |
4017 | (define_insn "*subsi3_borrow_cconly" | |
4018 | [(set (reg 33) | |
d3632d41 UW |
4019 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4020 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 4021 | (match_dup 1))) |
d3632d41 | 4022 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4023 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4024 | "@ |
d40c829f UW |
4025 | slr\t%0,%2 |
4026 | sl\t%0,%2 | |
4027 | sly\t%0,%2" | |
b2ba71ca | 4028 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 4029 | |
9db1d521 HP |
4030 | (define_insn "*subsi3_cc" |
4031 | [(set (reg 33) | |
d3632d41 UW |
4032 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4033 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4034 | (const_int 0))) |
d3632d41 | 4035 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 4036 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4037 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4038 | "@ |
d40c829f UW |
4039 | slr\t%0,%2 |
4040 | sl\t%0,%2 | |
4041 | sly\t%0,%2" | |
d3632d41 | 4042 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4043 | |
5d880bd2 UW |
4044 | (define_insn "*subsi3_cc2" |
4045 | [(set (reg 33) | |
4046 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
4047 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4048 | (set (match_operand:SI 0 "register_operand" "=d,d,d") | |
4049 | (minus:SI (match_dup 1) (match_dup 2)))] | |
4050 | "s390_match_ccmode (insn, CCL3mode)" | |
4051 | "@ | |
4052 | slr\t%0,%2 | |
4053 | sl\t%0,%2 | |
4054 | sly\t%0,%2" | |
4055 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4056 | ||
9db1d521 HP |
4057 | (define_insn "*subsi3_cconly" |
4058 | [(set (reg 33) | |
d3632d41 UW |
4059 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4060 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4061 | (const_int 0))) |
d3632d41 | 4062 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4063 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4064 | "@ |
d40c829f UW |
4065 | slr\t%0,%2 |
4066 | sl\t%0,%2 | |
4067 | sly\t%0,%2" | |
d3632d41 | 4068 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4069 | |
5d880bd2 UW |
4070 | (define_insn "*subsi3_cconly2" |
4071 | [(set (reg 33) | |
4072 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
4073 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4074 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
4075 | "s390_match_ccmode (insn, CCL3mode)" | |
4076 | "@ | |
4077 | slr\t%0,%2 | |
4078 | sl\t%0,%2 | |
4079 | sly\t%0,%2" | |
4080 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4081 | ||
07893d4f | 4082 | (define_insn "*subsi3_sign" |
d3632d41 UW |
4083 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4084 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4085 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
4086 | (clobber (reg:CC 33))] |
4087 | "" | |
d3632d41 | 4088 | "@ |
d40c829f UW |
4089 | sh\t%0,%2 |
4090 | shy\t%0,%2" | |
d3632d41 | 4091 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 4092 | |
9db1d521 | 4093 | (define_insn "subsi3" |
d3632d41 UW |
4094 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4095 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
4096 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
4097 | (clobber (reg:CC 33))] |
4098 | "" | |
4099 | "@ | |
d40c829f UW |
4100 | sr\t%0,%2 |
4101 | s\t%0,%2 | |
4102 | sy\t%0,%2" | |
d3632d41 | 4103 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4104 | |
9db1d521 HP |
4105 | |
4106 | ; | |
4107 | ; subdf3 instruction pattern(s). | |
4108 | ; | |
4109 | ||
4110 | (define_expand "subdf3" | |
4111 | [(parallel | |
4112 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4113 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4114 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4115 | (clobber (reg:CC 33))])] |
4116 | "TARGET_HARD_FLOAT" | |
4117 | "") | |
4118 | ||
4119 | (define_insn "*subdf3" | |
4120 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4121 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4122 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4123 | (clobber (reg:CC 33))] |
4124 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4125 | "@ | |
d40c829f UW |
4126 | sdbr\t%0,%2 |
4127 | sdb\t%0,%2" | |
ce50cae8 | 4128 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4129 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 4130 | |
3ef093a8 AK |
4131 | (define_insn "*subdf3_cc" |
4132 | [(set (reg 33) | |
4dbb5970 | 4133 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4134 | (match_operand:DF 2 "general_operand" "f,R")) |
4135 | (match_operand:DF 3 "const0_operand" ""))) | |
4136 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
4137 | (plus:DF (match_dup 1) (match_dup 2)))] | |
4138 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4139 | "@ | |
d40c829f UW |
4140 | sdbr\t%0,%2 |
4141 | sdb\t%0,%2" | |
3ef093a8 AK |
4142 | [(set_attr "op_type" "RRE,RXE") |
4143 | (set_attr "type" "fsimpd,fsimpd")]) | |
4144 | ||
4145 | (define_insn "*subdf3_cconly" | |
4146 | [(set (reg 33) | |
4dbb5970 | 4147 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4148 | (match_operand:DF 2 "general_operand" "f,R")) |
4149 | (match_operand:DF 3 "const0_operand" ""))) | |
4150 | (clobber (match_scratch:DF 0 "=f,f"))] | |
4151 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4152 | "@ | |
d40c829f UW |
4153 | sdbr\t%0,%2 |
4154 | sdb\t%0,%2" | |
3ef093a8 AK |
4155 | [(set_attr "op_type" "RRE,RXE") |
4156 | (set_attr "type" "fsimpd,fsimpd")]) | |
4157 | ||
9db1d521 HP |
4158 | (define_insn "*subdf3_ibm" |
4159 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4160 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4161 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4162 | (clobber (reg:CC 33))] |
4163 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4164 | "@ | |
d40c829f UW |
4165 | sdr\t%0,%2 |
4166 | sd\t%0,%2" | |
9db1d521 | 4167 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4168 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
4169 | |
4170 | ; | |
4171 | ; subsf3 instruction pattern(s). | |
4172 | ; | |
4173 | ||
4174 | (define_expand "subsf3" | |
4175 | [(parallel | |
4176 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4177 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4178 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4179 | (clobber (reg:CC 33))])] |
4180 | "TARGET_HARD_FLOAT" | |
4181 | "") | |
4182 | ||
4183 | (define_insn "*subsf3" | |
4184 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4185 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4186 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4187 | (clobber (reg:CC 33))] |
4188 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4189 | "@ | |
d40c829f UW |
4190 | sebr\t%0,%2 |
4191 | seb\t%0,%2" | |
ce50cae8 | 4192 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4193 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 4194 | |
3ef093a8 AK |
4195 | (define_insn "*subsf3_cc" |
4196 | [(set (reg 33) | |
4dbb5970 | 4197 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4198 | (match_operand:SF 2 "general_operand" "f,R")) |
4199 | (match_operand:SF 3 "const0_operand" ""))) | |
4200 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
4201 | (minus:SF (match_dup 1) (match_dup 2)))] | |
4202 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4203 | "@ | |
d40c829f UW |
4204 | sebr\t%0,%2 |
4205 | seb\t%0,%2" | |
3ef093a8 AK |
4206 | [(set_attr "op_type" "RRE,RXE") |
4207 | (set_attr "type" "fsimps,fsimps")]) | |
4208 | ||
4209 | (define_insn "*subsf3_cconly" | |
4210 | [(set (reg 33) | |
4dbb5970 | 4211 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4212 | (match_operand:SF 2 "general_operand" "f,R")) |
4213 | (match_operand:SF 3 "const0_operand" ""))) | |
4214 | (clobber (match_scratch:SF 0 "=f,f"))] | |
4215 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4216 | "@ | |
d40c829f UW |
4217 | sebr\t%0,%2 |
4218 | seb\t%0,%2" | |
3ef093a8 AK |
4219 | [(set_attr "op_type" "RRE,RXE") |
4220 | (set_attr "type" "fsimps,fsimps")]) | |
4221 | ||
9db1d521 HP |
4222 | (define_insn "*subsf3_ibm" |
4223 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4224 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4225 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4226 | (clobber (reg:CC 33))] |
4227 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4228 | "@ | |
d40c829f UW |
4229 | ser\t%0,%2 |
4230 | se\t%0,%2" | |
9db1d521 | 4231 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4232 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
4233 | |
4234 | ||
e69166de UW |
4235 | ;; |
4236 | ;;- Conditional add/subtract instructions. | |
4237 | ;; | |
4238 | ||
4239 | ; | |
4240 | ; adddicc instruction pattern(s). | |
4241 | ; | |
4242 | ||
4243 | (define_insn "*adddi3_alc_cc" | |
2f7e5a0d | 4244 | [(set (reg 33) |
e69166de UW |
4245 | (compare |
4246 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4247 | (match_operand:DI 2 "general_operand" "d,m")) | |
4248 | (match_operand:DI 3 "s390_alc_comparison" "")) | |
4249 | (const_int 0))) | |
4250 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4251 | (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4252 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
e69166de UW |
4253 | "@ |
4254 | alcgr\\t%0,%2 | |
4255 | alcg\\t%0,%2" | |
4256 | [(set_attr "op_type" "RRE,RXY")]) | |
4257 | ||
4258 | (define_insn "*adddi3_alc" | |
4259 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4260 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4261 | (match_operand:DI 2 "general_operand" "d,m")) | |
4262 | (match_operand:DI 3 "s390_alc_comparison" ""))) | |
2f7e5a0d EC |
4263 | (clobber (reg:CC 33))] |
4264 | "TARGET_64BIT" | |
e69166de UW |
4265 | "@ |
4266 | alcgr\\t%0,%2 | |
4267 | alcg\\t%0,%2" | |
4268 | [(set_attr "op_type" "RRE,RXY")]) | |
4269 | ||
4270 | (define_insn "*subdi3_slb_cc" | |
2f7e5a0d | 4271 | [(set (reg 33) |
e69166de UW |
4272 | (compare |
4273 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4274 | (match_operand:DI 2 "general_operand" "d,m")) | |
4275 | (match_operand:DI 3 "s390_slb_comparison" "")) | |
4276 | (const_int 0))) | |
4277 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4278 | (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4279 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
e69166de UW |
4280 | "@ |
4281 | slbgr\\t%0,%2 | |
4282 | slbg\\t%0,%2" | |
4283 | [(set_attr "op_type" "RRE,RXY")]) | |
4284 | ||
4285 | (define_insn "*subdi3_slb" | |
4286 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4287 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4288 | (match_operand:DI 2 "general_operand" "d,m")) | |
4289 | (match_operand:DI 3 "s390_slb_comparison" ""))) | |
2f7e5a0d EC |
4290 | (clobber (reg:CC 33))] |
4291 | "TARGET_64BIT" | |
e69166de UW |
4292 | "@ |
4293 | slbgr\\t%0,%2 | |
4294 | slbg\\t%0,%2" | |
4295 | [(set_attr "op_type" "RRE,RXY")]) | |
4296 | ||
5d880bd2 UW |
4297 | (define_expand "adddicc" |
4298 | [(match_operand:DI 0 "register_operand" "") | |
4299 | (match_operand 1 "comparison_operator" "") | |
4300 | (match_operand:DI 2 "register_operand" "") | |
4301 | (match_operand:DI 3 "const_int_operand" "")] | |
4302 | "TARGET_64BIT" | |
4303 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4304 | s390_compare_op0, s390_compare_op1, | |
4305 | operands[0], operands[2], | |
4306 | operands[3])) FAIL; DONE;") | |
4307 | ||
e69166de UW |
4308 | ; |
4309 | ; addsicc instruction pattern(s). | |
4310 | ; | |
4311 | ||
4312 | (define_insn "*addsi3_alc_cc" | |
2f7e5a0d | 4313 | [(set (reg 33) |
e69166de UW |
4314 | (compare |
4315 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4316 | (match_operand:SI 2 "general_operand" "d,m")) | |
4317 | (match_operand:SI 3 "s390_alc_comparison" "")) | |
4318 | (const_int 0))) | |
4319 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4320 | (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4321 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de UW |
4322 | "@ |
4323 | alcr\\t%0,%2 | |
4324 | alc\\t%0,%2" | |
4325 | [(set_attr "op_type" "RRE,RXY")]) | |
4326 | ||
4327 | (define_insn "*addsi3_alc" | |
4328 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4329 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4330 | (match_operand:SI 2 "general_operand" "d,m")) | |
4331 | (match_operand:SI 3 "s390_alc_comparison" ""))) | |
4332 | (clobber (reg:CC 33))] | |
2f7e5a0d | 4333 | "TARGET_CPU_ZARCH" |
e69166de UW |
4334 | "@ |
4335 | alcr\\t%0,%2 | |
4336 | alc\\t%0,%2" | |
4337 | [(set_attr "op_type" "RRE,RXY")]) | |
4338 | ||
4339 | (define_insn "*subsi3_slb_cc" | |
2f7e5a0d | 4340 | [(set (reg 33) |
e69166de UW |
4341 | (compare |
4342 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4343 | (match_operand:SI 2 "general_operand" "d,m")) | |
4344 | (match_operand:SI 3 "s390_slb_comparison" "")) | |
4345 | (const_int 0))) | |
4346 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4347 | (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4348 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de UW |
4349 | "@ |
4350 | slbr\\t%0,%2 | |
4351 | slb\\t%0,%2" | |
4352 | [(set_attr "op_type" "RRE,RXY")]) | |
4353 | ||
4354 | (define_insn "*subsi3_slb" | |
4355 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4356 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4357 | (match_operand:SI 2 "general_operand" "d,m")) | |
4358 | (match_operand:SI 3 "s390_slb_comparison" ""))) | |
2f7e5a0d EC |
4359 | (clobber (reg:CC 33))] |
4360 | "TARGET_CPU_ZARCH" | |
e69166de UW |
4361 | "@ |
4362 | slbr\\t%0,%2 | |
4363 | slb\\t%0,%2" | |
4364 | [(set_attr "op_type" "RRE,RXY")]) | |
4365 | ||
5d880bd2 UW |
4366 | (define_expand "addsicc" |
4367 | [(match_operand:SI 0 "register_operand" "") | |
4368 | (match_operand 1 "comparison_operator" "") | |
4369 | (match_operand:SI 2 "register_operand" "") | |
4370 | (match_operand:SI 3 "const_int_operand" "")] | |
4371 | "TARGET_CPU_ZARCH" | |
4372 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4373 | s390_compare_op0, s390_compare_op1, | |
4374 | operands[0], operands[2], | |
4375 | operands[3])) FAIL; DONE;") | |
4376 | ||
4377 | ; | |
4378 | ; scond instruction pattern(s). | |
4379 | ; | |
4380 | ||
4381 | (define_insn_and_split "*sconddi" | |
4382 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4383 | (match_operand:DI 1 "s390_alc_comparison" "")) | |
4384 | (clobber (reg:CC 33))] | |
4385 | "TARGET_64BIT" | |
4386 | "#" | |
4387 | "&& reload_completed" | |
4388 | [(set (match_dup 0) (const_int 0)) | |
4389 | (parallel | |
4390 | [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0)) | |
4391 | (match_dup 1))) | |
4392 | (clobber (reg:CC 33))])] | |
4393 | "" | |
4394 | [(set_attr "op_type" "NN")]) | |
4395 | ||
4396 | (define_insn_and_split "*scondsi" | |
4397 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
4398 | (match_operand:SI 1 "s390_alc_comparison" "")) | |
4399 | (clobber (reg:CC 33))] | |
4400 | "TARGET_CPU_ZARCH" | |
4401 | "#" | |
4402 | "&& reload_completed" | |
4403 | [(set (match_dup 0) (const_int 0)) | |
4404 | (parallel | |
4405 | [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0)) | |
4406 | (match_dup 1))) | |
4407 | (clobber (reg:CC 33))])] | |
4408 | "" | |
4409 | [(set_attr "op_type" "NN")]) | |
4410 | ||
4411 | (define_insn_and_split "*sconddi_neg" | |
4412 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4413 | (match_operand:DI 1 "s390_slb_comparison" "")) | |
4414 | (clobber (reg:CC 33))] | |
4415 | "TARGET_64BIT" | |
4416 | "#" | |
4417 | "&& reload_completed" | |
4418 | [(set (match_dup 0) (const_int 0)) | |
4419 | (parallel | |
4420 | [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0)) | |
4421 | (match_dup 1))) | |
4422 | (clobber (reg:CC 33))]) | |
4423 | (parallel | |
4424 | [(set (match_dup 0) (neg:DI (match_dup 0))) | |
4425 | (clobber (reg:CC 33))])] | |
4426 | "" | |
4427 | [(set_attr "op_type" "NN")]) | |
4428 | ||
4429 | (define_insn_and_split "*scondsi_neg" | |
4430 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
4431 | (match_operand:SI 1 "s390_slb_comparison" "")) | |
4432 | (clobber (reg:CC 33))] | |
4433 | "TARGET_CPU_ZARCH" | |
4434 | "#" | |
4435 | "&& reload_completed" | |
4436 | [(set (match_dup 0) (const_int 0)) | |
4437 | (parallel | |
4438 | [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0)) | |
4439 | (match_dup 1))) | |
4440 | (clobber (reg:CC 33))]) | |
4441 | (parallel | |
4442 | [(set (match_dup 0) (neg:SI (match_dup 0))) | |
4443 | (clobber (reg:CC 33))])] | |
4444 | "" | |
4445 | [(set_attr "op_type" "NN")]) | |
4446 | ||
4447 | (define_expand "sltu" | |
4448 | [(match_operand:SI 0 "register_operand" "")] | |
4449 | "TARGET_CPU_ZARCH" | |
4450 | "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1, | |
4451 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4452 | ||
4453 | (define_expand "sgtu" | |
4454 | [(match_operand:SI 0 "register_operand" "")] | |
4455 | "TARGET_CPU_ZARCH" | |
4456 | "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1, | |
4457 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4458 | ||
4459 | (define_expand "sleu" | |
4460 | [(match_operand:SI 0 "register_operand" "")] | |
4461 | "TARGET_CPU_ZARCH" | |
4462 | "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1, | |
4463 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4464 | ||
4465 | (define_expand "sgeu" | |
4466 | [(match_operand:SI 0 "register_operand" "")] | |
4467 | "TARGET_CPU_ZARCH" | |
4468 | "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1, | |
4469 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4470 | ||
e69166de | 4471 | |
9db1d521 HP |
4472 | ;; |
4473 | ;;- Multiply instructions. | |
4474 | ;; | |
4475 | ||
4023fb28 UW |
4476 | ; |
4477 | ; muldi3 instruction pattern(s). | |
4478 | ; | |
9db1d521 | 4479 | |
07893d4f UW |
4480 | (define_insn "*muldi3_sign" |
4481 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4482 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4483 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4484 | "TARGET_64BIT" | |
4485 | "@ | |
d40c829f UW |
4486 | msgfr\t%0,%2 |
4487 | msgf\t%0,%2" | |
d3632d41 | 4488 | [(set_attr "op_type" "RRE,RXY") |
07893d4f UW |
4489 | (set_attr "type" "imul")]) |
4490 | ||
4023fb28 | 4491 | (define_insn "muldi3" |
9db1d521 | 4492 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4493 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4494 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4495 | "TARGET_64BIT" |
4496 | "@ | |
d40c829f UW |
4497 | msgr\t%0,%2 |
4498 | mghi\t%0,%h2 | |
4499 | msg\t%0,%2" | |
d3632d41 | 4500 | [(set_attr "op_type" "RRE,RI,RXY") |
f2d3c02a HP |
4501 | (set_attr "type" "imul")]) |
4502 | ||
9db1d521 HP |
4503 | ; |
4504 | ; mulsi3 instruction pattern(s). | |
4505 | ; | |
4506 | ||
f1e77d83 UW |
4507 | (define_insn "*mulsi3_sign" |
4508 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4509 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4510 | (match_operand:SI 1 "register_operand" "0")))] | |
4511 | "" | |
4512 | "mh\t%0,%2" | |
4513 | [(set_attr "op_type" "RX") | |
4514 | (set_attr "type" "imul")]) | |
4515 | ||
9db1d521 | 4516 | (define_insn "mulsi3" |
d3632d41 UW |
4517 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4518 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4519 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4520 | "" |
4521 | "@ | |
d40c829f UW |
4522 | msr\t%0,%2 |
4523 | mhi\t%0,%h2 | |
4524 | ms\t%0,%2 | |
4525 | msy\t%0,%2" | |
d3632d41 | 4526 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
f2d3c02a | 4527 | (set_attr "type" "imul")]) |
9db1d521 | 4528 | |
4023fb28 UW |
4529 | ; |
4530 | ; mulsidi3 instruction pattern(s). | |
4531 | ; | |
4532 | ||
f1e77d83 UW |
4533 | (define_insn "mulsidi3" |
4534 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4535 | (mult:DI (sign_extend:DI | |
4536 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4537 | (sign_extend:DI | |
4538 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4539 | "!TARGET_64BIT" |
f1e77d83 UW |
4540 | "@ |
4541 | mr\t%0,%2 | |
4542 | m\t%0,%2" | |
4543 | [(set_attr "op_type" "RR,RX") | |
4544 | (set_attr "type" "imul")]) | |
4023fb28 | 4545 | |
f1e77d83 UW |
4546 | ; |
4547 | ; umulsidi3 instruction pattern(s). | |
4548 | ; | |
c7453384 | 4549 | |
f1e77d83 UW |
4550 | (define_insn "umulsidi3" |
4551 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4552 | (mult:DI (zero_extend:DI | |
4553 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4554 | (zero_extend:DI | |
4555 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4556 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4557 | "@ | |
4558 | mlr\t%0,%2 | |
4559 | ml\t%0,%2" | |
4560 | [(set_attr "op_type" "RRE,RXY") | |
f2d3c02a | 4561 | (set_attr "type" "imul")]) |
c7453384 | 4562 | |
9db1d521 HP |
4563 | ; |
4564 | ; muldf3 instruction pattern(s). | |
4565 | ; | |
4566 | ||
4567 | (define_expand "muldf3" | |
553e5ce9 UW |
4568 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4569 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
4570 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4571 | "TARGET_HARD_FLOAT" |
4572 | "") | |
4573 | ||
4574 | (define_insn "*muldf3" | |
4575 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4576 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4577 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4578 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4579 | "@ | |
d40c829f UW |
4580 | mdbr\t%0,%2 |
4581 | mdb\t%0,%2" | |
ce50cae8 | 4582 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4583 | (set_attr "type" "fmuld")]) |
9db1d521 HP |
4584 | |
4585 | (define_insn "*muldf3_ibm" | |
4586 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4587 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4588 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4589 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4590 | "@ | |
d40c829f UW |
4591 | mdr\t%0,%2 |
4592 | md\t%0,%2" | |
9db1d521 | 4593 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4594 | (set_attr "type" "fmuld")]) |
9db1d521 | 4595 | |
a1b892b5 AK |
4596 | (define_insn "*fmadddf" |
4597 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4598 | (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") | |
4599 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4600 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4601 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4602 | "@ |
4603 | madbr\t%0,%1,%2 | |
4604 | madb\t%0,%1,%2" | |
4605 | [(set_attr "op_type" "RRE,RXE") | |
4606 | (set_attr "type" "fmuld")]) | |
4607 | ||
4608 | (define_insn "*fmsubdf" | |
4609 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4610 | (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") | |
4611 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4612 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4613 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4614 | "@ |
4615 | msdbr\t%0,%1,%2 | |
4616 | msdb\t%0,%1,%2" | |
4617 | [(set_attr "op_type" "RRE,RXE") | |
4618 | (set_attr "type" "fmuld")]) | |
4619 | ||
9db1d521 HP |
4620 | ; |
4621 | ; mulsf3 instruction pattern(s). | |
4622 | ; | |
4623 | ||
4624 | (define_expand "mulsf3" | |
553e5ce9 UW |
4625 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4626 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
4627 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4628 | "TARGET_HARD_FLOAT" |
4629 | "") | |
4630 | ||
4631 | (define_insn "*mulsf3" | |
4632 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4633 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4634 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4635 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4636 | "@ | |
d40c829f UW |
4637 | meebr\t%0,%2 |
4638 | meeb\t%0,%2" | |
ce50cae8 | 4639 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4640 | (set_attr "type" "fmuls")]) |
9db1d521 HP |
4641 | |
4642 | (define_insn "*mulsf3_ibm" | |
4643 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4644 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4645 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4646 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4647 | "@ | |
d40c829f UW |
4648 | mer\t%0,%2 |
4649 | me\t%0,%2" | |
9db1d521 | 4650 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4651 | (set_attr "type" "fmuls")]) |
9db1d521 | 4652 | |
a1b892b5 AK |
4653 | (define_insn "*fmaddsf" |
4654 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4655 | (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") | |
4656 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4657 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4658 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4659 | "@ |
4660 | maebr\t%0,%1,%2 | |
4661 | maeb\t%0,%1,%2" | |
4662 | [(set_attr "op_type" "RRE,RXE") | |
4663 | (set_attr "type" "fmuls")]) | |
4664 | ||
4665 | (define_insn "*fmsubsf" | |
4666 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4667 | (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") | |
4668 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4669 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4670 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4671 | "@ |
4672 | msebr\t%0,%1,%2 | |
4673 | mseb\t%0,%1,%2" | |
4674 | [(set_attr "op_type" "RRE,RXE") | |
4675 | (set_attr "type" "fmuls")]) | |
9db1d521 HP |
4676 | |
4677 | ;; | |
4678 | ;;- Divide and modulo instructions. | |
4679 | ;; | |
4680 | ||
4681 | ; | |
4023fb28 | 4682 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4683 | ; |
4684 | ||
4023fb28 UW |
4685 | (define_expand "divmoddi4" |
4686 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4687 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4688 | (match_operand:DI 2 "general_operand" ""))) |
4689 | (set (match_operand:DI 3 "general_operand" "") | |
4690 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4691 | (clobber (match_dup 4))] | |
9db1d521 | 4692 | "TARGET_64BIT" |
9db1d521 | 4693 | { |
f1e77d83 | 4694 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4695 | |
4696 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4697 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4698 | |
4699 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4700 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4701 | |
4702 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4703 | REG_NOTES (insn) = | |
4704 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4705 | ||
4706 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4707 | REG_NOTES (insn) = | |
4708 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4709 | |
9db1d521 | 4710 | DONE; |
10bbf137 | 4711 | }) |
9db1d521 HP |
4712 | |
4713 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4714 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4715 | (ior:TI | |
4023fb28 UW |
4716 | (ashift:TI |
4717 | (zero_extend:TI | |
5665e398 UW |
4718 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4719 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4720 | (const_int 64)) | |
4721 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4722 | "TARGET_64BIT" |
4723 | "@ | |
d40c829f UW |
4724 | dsgr\t%0,%2 |
4725 | dsg\t%0,%2" | |
d3632d41 | 4726 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4727 | (set_attr "type" "idiv")]) |
9db1d521 | 4728 | |
4023fb28 UW |
4729 | (define_insn "divmodtisi3" |
4730 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4731 | (ior:TI | |
4023fb28 UW |
4732 | (ashift:TI |
4733 | (zero_extend:TI | |
5665e398 | 4734 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 4735 | (sign_extend:DI |
5665e398 UW |
4736 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4737 | (const_int 64)) | |
4738 | (zero_extend:TI | |
4739 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4740 | "TARGET_64BIT" |
4023fb28 | 4741 | "@ |
d40c829f UW |
4742 | dsgfr\t%0,%2 |
4743 | dsgf\t%0,%2" | |
d3632d41 | 4744 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4745 | (set_attr "type" "idiv")]) |
9db1d521 | 4746 | |
4023fb28 UW |
4747 | ; |
4748 | ; udivmoddi4 instruction pattern(s). | |
4749 | ; | |
9db1d521 | 4750 | |
4023fb28 UW |
4751 | (define_expand "udivmoddi4" |
4752 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4753 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4754 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4755 | (set (match_operand:DI 3 "general_operand" "") | |
4756 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4757 | (clobber (match_dup 4))] | |
9db1d521 | 4758 | "TARGET_64BIT" |
9db1d521 | 4759 | { |
4023fb28 UW |
4760 | rtx insn, div_equal, mod_equal, equal; |
4761 | ||
4762 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4763 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4764 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4765 | gen_rtx_ASHIFT (TImode, |
4766 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4767 | GEN_INT (64)), |
4768 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4769 | |
4770 | operands[4] = gen_reg_rtx(TImode); | |
4771 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4772 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4773 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4774 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4775 | REG_NOTES (insn) = | |
4776 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4777 | ||
4778 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4779 | REG_NOTES (insn) = | |
4780 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4781 | ||
4782 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4783 | REG_NOTES (insn) = | |
4784 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4785 | |
9db1d521 | 4786 | DONE; |
10bbf137 | 4787 | }) |
9db1d521 HP |
4788 | |
4789 | (define_insn "udivmodtidi3" | |
4023fb28 | 4790 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 4791 | (ior:TI |
5665e398 UW |
4792 | (ashift:TI |
4793 | (zero_extend:TI | |
4794 | (truncate:DI | |
2f7e5a0d EC |
4795 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
4796 | (zero_extend:TI | |
5665e398 UW |
4797 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
4798 | (const_int 64)) | |
4799 | (zero_extend:TI | |
4800 | (truncate:DI | |
4801 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4802 | "TARGET_64BIT" |
4803 | "@ | |
d40c829f UW |
4804 | dlgr\t%0,%2 |
4805 | dlg\t%0,%2" | |
d3632d41 | 4806 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4807 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4808 | |
4809 | ; | |
4023fb28 | 4810 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4811 | ; |
4812 | ||
4023fb28 UW |
4813 | (define_expand "divmodsi4" |
4814 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4815 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4816 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4817 | (set (match_operand:SI 3 "general_operand" "") | |
4818 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4819 | (clobber (match_dup 4))] | |
9db1d521 | 4820 | "!TARGET_64BIT" |
9db1d521 | 4821 | { |
4023fb28 UW |
4822 | rtx insn, div_equal, mod_equal, equal; |
4823 | ||
4824 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4825 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4826 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4827 | gen_rtx_ASHIFT (DImode, |
4828 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4829 | GEN_INT (32)), |
4830 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4831 | |
4832 | operands[4] = gen_reg_rtx(DImode); | |
4833 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4834 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4835 | REG_NOTES (insn) = | |
4836 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4837 | ||
4838 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4839 | REG_NOTES (insn) = | |
4840 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4841 | ||
4842 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4843 | REG_NOTES (insn) = | |
4844 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4845 | |
9db1d521 | 4846 | DONE; |
10bbf137 | 4847 | }) |
9db1d521 HP |
4848 | |
4849 | (define_insn "divmoddisi3" | |
4023fb28 | 4850 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 4851 | (ior:DI |
5665e398 UW |
4852 | (ashift:DI |
4853 | (zero_extend:DI | |
4854 | (truncate:SI | |
2f7e5a0d EC |
4855 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4856 | (sign_extend:DI | |
5665e398 UW |
4857 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4858 | (const_int 32)) | |
4859 | (zero_extend:DI | |
4860 | (truncate:SI | |
4861 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4862 | "!TARGET_64BIT" |
4863 | "@ | |
d40c829f UW |
4864 | dr\t%0,%2 |
4865 | d\t%0,%2" | |
9db1d521 | 4866 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4867 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4868 | |
4869 | ; | |
4870 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4871 | ; | |
4872 | ||
f1e77d83 UW |
4873 | (define_expand "udivmodsi4" |
4874 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4875 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4876 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4877 | (set (match_operand:SI 3 "general_operand" "") | |
4878 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4879 | (clobber (match_dup 4))] | |
4880 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4881 | { | |
4882 | rtx insn, div_equal, mod_equal, equal; | |
4883 | ||
4884 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4885 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4886 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4887 | gen_rtx_ASHIFT (DImode, |
4888 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4889 | GEN_INT (32)), |
4890 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4891 | |
4892 | operands[4] = gen_reg_rtx(DImode); | |
4893 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4894 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4895 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4896 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4897 | REG_NOTES (insn) = | |
4898 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4899 | ||
4900 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4901 | REG_NOTES (insn) = | |
4902 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4903 | ||
4904 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4905 | REG_NOTES (insn) = | |
4906 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4907 | ||
4908 | DONE; | |
4909 | }) | |
4910 | ||
4911 | (define_insn "udivmoddisi3" | |
4912 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 4913 | (ior:DI |
5665e398 UW |
4914 | (ashift:DI |
4915 | (zero_extend:DI | |
4916 | (truncate:SI | |
2f7e5a0d EC |
4917 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
4918 | (zero_extend:DI | |
5665e398 UW |
4919 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
4920 | (const_int 32)) | |
4921 | (zero_extend:DI | |
4922 | (truncate:SI | |
4923 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4924 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4925 | "@ | |
4926 | dlr\t%0,%2 | |
4927 | dl\t%0,%2" | |
4928 | [(set_attr "op_type" "RRE,RXY") | |
4929 | (set_attr "type" "idiv")]) | |
4023fb28 | 4930 | |
9db1d521 HP |
4931 | (define_expand "udivsi3" |
4932 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4933 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4934 | (match_operand:SI 2 "general_operand" ""))) |
4935 | (clobber (match_dup 3))] | |
f1e77d83 | 4936 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4937 | { |
4023fb28 UW |
4938 | rtx insn, udiv_equal, umod_equal, equal; |
4939 | ||
4940 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4941 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4942 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4943 | gen_rtx_ASHIFT (DImode, |
4944 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4945 | GEN_INT (32)), |
4946 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4947 | |
4023fb28 | 4948 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4949 | |
4950 | if (CONSTANT_P (operands[2])) | |
4951 | { | |
4952 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4953 | { | |
4954 | rtx label1 = gen_label_rtx (); | |
4955 | ||
4023fb28 UW |
4956 | operands[1] = make_safe_from (operands[1], operands[0]); |
4957 | emit_move_insn (operands[0], const0_rtx); | |
4958 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4959 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4960 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4961 | emit_label (label1); |
4962 | } | |
4963 | else | |
4964 | { | |
c7453384 EC |
4965 | operands[2] = force_reg (SImode, operands[2]); |
4966 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4967 | |
4968 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4969 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4970 | operands[2])); | |
4971 | REG_NOTES (insn) = | |
4972 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4973 | |
4974 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4975 | gen_lowpart (SImode, operands[3])); |
4976 | REG_NOTES (insn) = | |
c7453384 | 4977 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4978 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4979 | } |
4980 | } | |
4981 | else | |
c7453384 | 4982 | { |
9db1d521 HP |
4983 | rtx label1 = gen_label_rtx (); |
4984 | rtx label2 = gen_label_rtx (); | |
4985 | rtx label3 = gen_label_rtx (); | |
4986 | ||
c7453384 EC |
4987 | operands[1] = force_reg (SImode, operands[1]); |
4988 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4989 | operands[2] = force_reg (SImode, operands[2]); | |
4990 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4991 | |
4992 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4993 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4994 | emit_jump_insn (gen_bgtu (label3)); | |
4995 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4996 | emit_jump_insn (gen_blt (label2)); | |
4997 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4998 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4999 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5000 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5001 | operands[2])); | |
5002 | REG_NOTES (insn) = | |
5003 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5004 | |
5005 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5006 | gen_lowpart (SImode, operands[3])); |
5007 | REG_NOTES (insn) = | |
c7453384 | 5008 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5009 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 5010 | emit_jump (label3); |
9db1d521 | 5011 | emit_label (label1); |
4023fb28 | 5012 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 5013 | emit_jump (label3); |
9db1d521 | 5014 | emit_label (label2); |
4023fb28 | 5015 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5016 | emit_label (label3); |
5017 | } | |
c7453384 | 5018 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 5019 | DONE; |
10bbf137 | 5020 | }) |
9db1d521 HP |
5021 | |
5022 | (define_expand "umodsi3" | |
5023 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5024 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
5025 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
5026 | (clobber (match_dup 3))] | |
f1e77d83 | 5027 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 5028 | { |
4023fb28 UW |
5029 | rtx insn, udiv_equal, umod_equal, equal; |
5030 | ||
5031 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5032 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5033 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5034 | gen_rtx_ASHIFT (DImode, |
5035 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5036 | GEN_INT (32)), |
5037 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5038 | |
4023fb28 | 5039 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5040 | |
5041 | if (CONSTANT_P (operands[2])) | |
5042 | { | |
5043 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
5044 | { | |
5045 | rtx label1 = gen_label_rtx (); | |
5046 | ||
4023fb28 UW |
5047 | operands[1] = make_safe_from (operands[1], operands[0]); |
5048 | emit_move_insn (operands[0], operands[1]); | |
5049 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 5050 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
5051 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
5052 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
5053 | emit_label (label1); |
5054 | } | |
5055 | else | |
5056 | { | |
c7453384 EC |
5057 | operands[2] = force_reg (SImode, operands[2]); |
5058 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5059 | |
5060 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5061 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5062 | operands[2])); | |
5063 | REG_NOTES (insn) = | |
5064 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5065 | |
5066 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5067 | gen_highpart (SImode, operands[3])); |
5068 | REG_NOTES (insn) = | |
c7453384 | 5069 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5070 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
5071 | } |
5072 | } | |
5073 | else | |
5074 | { | |
5075 | rtx label1 = gen_label_rtx (); | |
5076 | rtx label2 = gen_label_rtx (); | |
5077 | rtx label3 = gen_label_rtx (); | |
5078 | ||
c7453384 EC |
5079 | operands[1] = force_reg (SImode, operands[1]); |
5080 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5081 | operands[2] = force_reg (SImode, operands[2]); | |
5082 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5083 | |
c7453384 | 5084 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 5085 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 HP |
5086 | emit_jump_insn (gen_bgtu (label3)); |
5087 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5088 | emit_jump_insn (gen_blt (label2)); | |
5089 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5090 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
5091 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5092 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5093 | operands[2])); | |
5094 | REG_NOTES (insn) = | |
5095 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5096 | |
5097 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5098 | gen_highpart (SImode, operands[3])); |
5099 | REG_NOTES (insn) = | |
c7453384 | 5100 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5101 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 5102 | emit_jump (label3); |
9db1d521 | 5103 | emit_label (label1); |
4023fb28 | 5104 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5105 | emit_jump (label3); |
9db1d521 | 5106 | emit_label (label2); |
4023fb28 | 5107 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5108 | emit_label (label3); |
5109 | } | |
9db1d521 | 5110 | DONE; |
10bbf137 | 5111 | }) |
9db1d521 HP |
5112 | |
5113 | ; | |
5114 | ; divdf3 instruction pattern(s). | |
5115 | ; | |
5116 | ||
5117 | (define_expand "divdf3" | |
553e5ce9 UW |
5118 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5119 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
5120 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
5121 | "TARGET_HARD_FLOAT" |
5122 | "") | |
5123 | ||
5124 | (define_insn "*divdf3" | |
4023fb28 UW |
5125 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5126 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 5127 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5128 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5129 | "@ | |
d40c829f UW |
5130 | ddbr\t%0,%2 |
5131 | ddb\t%0,%2" | |
ce50cae8 | 5132 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 5133 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
5134 | |
5135 | (define_insn "*divdf3_ibm" | |
4023fb28 UW |
5136 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5137 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 5138 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5139 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5140 | "@ | |
d40c829f UW |
5141 | ddr\t%0,%2 |
5142 | dd\t%0,%2" | |
9db1d521 | 5143 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5144 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
5145 | |
5146 | ; | |
5147 | ; divsf3 instruction pattern(s). | |
5148 | ; | |
5149 | ||
5150 | (define_expand "divsf3" | |
553e5ce9 UW |
5151 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5152 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
5153 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
5154 | "TARGET_HARD_FLOAT" |
5155 | "") | |
5156 | ||
5157 | (define_insn "*divsf3" | |
4023fb28 UW |
5158 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5159 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 5160 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5161 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5162 | "@ | |
d40c829f UW |
5163 | debr\t%0,%2 |
5164 | deb\t%0,%2" | |
ce50cae8 | 5165 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 5166 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
5167 | |
5168 | (define_insn "*divsf3" | |
4023fb28 UW |
5169 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5170 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 5171 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5172 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5173 | "@ | |
d40c829f UW |
5174 | der\t%0,%2 |
5175 | de\t%0,%2" | |
9db1d521 | 5176 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5177 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
5178 | |
5179 | ||
5180 | ;; | |
5181 | ;;- And instructions. | |
5182 | ;; | |
5183 | ||
5184 | ; | |
5185 | ; anddi3 instruction pattern(s). | |
5186 | ; | |
5187 | ||
5188 | (define_insn "*anddi3_cc" | |
5189 | [(set (reg 33) | |
96fd3851 | 5190 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5191 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 5192 | (const_int 0))) |
4023fb28 | 5193 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
5194 | (and:DI (match_dup 1) (match_dup 2)))] |
5195 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5196 | "@ | |
d40c829f UW |
5197 | ngr\t%0,%2 |
5198 | ng\t%0,%2" | |
d3632d41 | 5199 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
5200 | |
5201 | (define_insn "*anddi3_cconly" | |
5202 | [(set (reg 33) | |
96fd3851 | 5203 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5204 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
5205 | (const_int 0))) |
5206 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5207 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5208 | "@ | |
d40c829f UW |
5209 | ngr\t%0,%2 |
5210 | ng\t%0,%2" | |
d3632d41 | 5211 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
5212 | |
5213 | (define_insn "anddi3" | |
f19a9af7 AK |
5214 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d,d,d") |
5215 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o,0,0,0,0,0,0") | |
2f7e5a0d | 5216 | (match_operand:DI 2 "general_operand" |
f19a9af7 AK |
5217 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m"))) |
5218 | (clobber (reg:CC 33))] | |
5219 | "TARGET_64BIT" | |
5220 | "@ | |
5221 | # | |
5222 | # | |
5223 | nihh\t%0,%j2 | |
5224 | nihl\t%0,%j2 | |
5225 | nilh\t%0,%j2 | |
5226 | nill\t%0,%j2 | |
5227 | ngr\t%0,%2 | |
5228 | ng\t%0,%2" | |
5229 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY")]) | |
4023fb28 UW |
5230 | |
5231 | (define_insn "*anddi3_ss" | |
ccfc6cc8 | 5232 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5233 | (and:DI (match_dup 0) |
ccfc6cc8 | 5234 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5235 | (clobber (reg:CC 33))] |
5236 | "" | |
d40c829f | 5237 | "nc\t%O0(8,%R0),%1" |
077dab3b | 5238 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5239 | |
5240 | (define_insn "*anddi3_ss_inv" | |
ccfc6cc8 UW |
5241 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5242 | (and:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5243 | (match_dup 0))) |
5244 | (clobber (reg:CC 33))] | |
5245 | "" | |
d40c829f | 5246 | "nc\t%O0(8,%R0),%1" |
077dab3b | 5247 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5248 | |
5249 | ; | |
5250 | ; andsi3 instruction pattern(s). | |
5251 | ; | |
5252 | ||
5253 | (define_insn "*andsi3_cc" | |
5254 | [(set (reg 33) | |
d3632d41 UW |
5255 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5256 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5257 | (const_int 0))) |
d3632d41 | 5258 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 HP |
5259 | (and:SI (match_dup 1) (match_dup 2)))] |
5260 | "s390_match_ccmode(insn, CCTmode)" | |
5261 | "@ | |
d40c829f UW |
5262 | nr\t%0,%2 |
5263 | n\t%0,%2 | |
5264 | ny\t%0,%2" | |
d3632d41 | 5265 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
5266 | |
5267 | (define_insn "*andsi3_cconly" | |
5268 | [(set (reg 33) | |
d3632d41 UW |
5269 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5270 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5271 | (const_int 0))) |
d3632d41 | 5272 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
9db1d521 HP |
5273 | "s390_match_ccmode(insn, CCTmode)" |
5274 | "@ | |
d40c829f UW |
5275 | nr\t%0,%2 |
5276 | n\t%0,%2 | |
5277 | ny\t%0,%2" | |
d3632d41 | 5278 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5279 | |
f19a9af7 | 5280 | (define_expand "andsi3" |
2f7e5a0d | 5281 | [(parallel |
f19a9af7 AK |
5282 | [(set (match_operand:SI 0 "register_operand" "") |
5283 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5284 | (match_operand:SI 2 "general_operand" ""))) | |
5285 | (clobber (reg:CC 33))])] | |
5286 | "" | |
5287 | "") | |
4023fb28 | 5288 | |
f19a9af7 AK |
5289 | (define_insn "*andsi3_zarch" |
5290 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d,d") | |
5291 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,o,0,0,0,0,0") | |
5292 | (match_operand:SI 2 "general_operand" "M,M,N0HSF,N1HSF,d,R,T"))) | |
9db1d521 | 5293 | (clobber (reg:CC 33))] |
f19a9af7 | 5294 | "TARGET_ZARCH" |
9db1d521 | 5295 | "@ |
f19a9af7 AK |
5296 | # |
5297 | # | |
5298 | nilh\t%0,%j2 | |
2f7e5a0d | 5299 | nill\t%0,%j2 |
d40c829f UW |
5300 | nr\t%0,%2 |
5301 | n\t%0,%2 | |
5302 | ny\t%0,%2" | |
f19a9af7 AK |
5303 | [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY")]) |
5304 | ||
5305 | (define_insn "*andsi3_esa" | |
5306 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5307 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
5308 | (match_operand:SI 2 "general_operand" "d,R"))) | |
5309 | (clobber (reg:CC 33))] | |
5310 | "!TARGET_ZARCH" | |
5311 | "@ | |
5312 | nr\t%0,%2 | |
5313 | n\t%0,%2" | |
5314 | [(set_attr "op_type" "RR,RX")]) | |
4023fb28 UW |
5315 | |
5316 | (define_insn "*andsi3_ss" | |
ccfc6cc8 | 5317 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5318 | (and:SI (match_dup 0) |
ccfc6cc8 | 5319 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5320 | (clobber (reg:CC 33))] |
5321 | "" | |
d40c829f | 5322 | "nc\t%O0(4,%R0),%1" |
077dab3b | 5323 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5324 | |
5325 | (define_insn "*andsi3_ss_inv" | |
ccfc6cc8 UW |
5326 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5327 | (and:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5328 | (match_dup 0))) |
5329 | (clobber (reg:CC 33))] | |
5330 | "" | |
d40c829f | 5331 | "nc\t%O0(4,%R0),%1" |
077dab3b | 5332 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5333 | |
5334 | ; | |
5335 | ; andhi3 instruction pattern(s). | |
5336 | ; | |
5337 | ||
4023fb28 UW |
5338 | (define_insn "*andhi3_ni" |
5339 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
5340 | (and:HI (match_operand:HI 1 "register_operand" "%0,0") | |
5341 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
5342 | (clobber (reg:CC 33))] | |
9e8327e3 | 5343 | "TARGET_ZARCH" |
4023fb28 | 5344 | "@ |
d40c829f UW |
5345 | nr\t%0,%2 |
5346 | nill\t%0,%x2" | |
077dab3b | 5347 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 UW |
5348 | |
5349 | (define_insn "andhi3" | |
5350 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5351 | (and:HI (match_operand:HI 1 "register_operand" "%0") | |
5352 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5353 | (clobber (reg:CC 33))] | |
9db1d521 | 5354 | "" |
d40c829f | 5355 | "nr\t%0,%2" |
077dab3b | 5356 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5357 | |
5358 | (define_insn "*andhi3_ss" | |
ccfc6cc8 | 5359 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5360 | (and:HI (match_dup 0) |
ccfc6cc8 | 5361 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5362 | (clobber (reg:CC 33))] |
5363 | "" | |
d40c829f | 5364 | "nc\t%O0(2,%R0),%1" |
077dab3b | 5365 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5366 | |
4023fb28 | 5367 | (define_insn "*andhi3_ss_inv" |
ccfc6cc8 UW |
5368 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5369 | (and:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5370 | (match_dup 0))) |
9db1d521 HP |
5371 | (clobber (reg:CC 33))] |
5372 | "" | |
d40c829f | 5373 | "nc\t%O0(2,%R0),%1" |
077dab3b | 5374 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5375 | |
5376 | ; | |
5377 | ; andqi3 instruction pattern(s). | |
5378 | ; | |
5379 | ||
4023fb28 UW |
5380 | (define_insn "*andqi3_ni" |
5381 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
5382 | (and:QI (match_operand:QI 1 "register_operand" "%0,0") | |
5383 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
5384 | (clobber (reg:CC 33))] | |
9e8327e3 | 5385 | "TARGET_ZARCH" |
4023fb28 | 5386 | "@ |
d40c829f UW |
5387 | nr\t%0,%2 |
5388 | nill\t%0,%b2" | |
077dab3b | 5389 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 | 5390 | |
9db1d521 | 5391 | (define_insn "andqi3" |
4023fb28 UW |
5392 | [(set (match_operand:QI 0 "register_operand" "=d") |
5393 | (and:QI (match_operand:QI 1 "register_operand" "%0") | |
5394 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5395 | (clobber (reg:CC 33))] | |
5396 | "" | |
d40c829f | 5397 | "nr\t%0,%2" |
077dab3b | 5398 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5399 | |
5400 | (define_insn "*andqi3_ss" | |
d3632d41 | 5401 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5402 | (and:QI (match_dup 0) |
d3632d41 | 5403 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5404 | (clobber (reg:CC 33))] |
5405 | "" | |
5406 | "@ | |
d40c829f UW |
5407 | ni\t%0,%b1 |
5408 | niy\t%0,%b1 | |
5409 | nc\t%O0(1,%R0),%1" | |
d3632d41 | 5410 | [(set_attr "op_type" "SI,SIY,SS")]) |
4023fb28 UW |
5411 | |
5412 | (define_insn "*andqi3_ss_inv" | |
d3632d41 UW |
5413 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5414 | (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 UW |
5415 | (match_dup 0))) |
5416 | (clobber (reg:CC 33))] | |
5417 | "" | |
5418 | "@ | |
d40c829f UW |
5419 | ni\t%0,%b1 |
5420 | niy\t%0,%b1 | |
5421 | nc\t%O0(1,%R0),%1" | |
d3632d41 | 5422 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5423 | |
5424 | ||
5425 | ;; | |
5426 | ;;- Bit set (inclusive or) instructions. | |
5427 | ;; | |
5428 | ||
5429 | ; | |
5430 | ; iordi3 instruction pattern(s). | |
5431 | ; | |
5432 | ||
4023fb28 UW |
5433 | (define_insn "*iordi3_cc" |
5434 | [(set (reg 33) | |
96fd3851 | 5435 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5436 | (match_operand:DI 2 "general_operand" "d,m")) |
5437 | (const_int 0))) | |
5438 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5439 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5440 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5441 | "@ | |
d40c829f UW |
5442 | ogr\t%0,%2 |
5443 | og\t%0,%2" | |
d3632d41 | 5444 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5445 | |
5446 | (define_insn "*iordi3_cconly" | |
5447 | [(set (reg 33) | |
96fd3851 | 5448 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5449 | (match_operand:DI 2 "general_operand" "d,m")) |
5450 | (const_int 0))) | |
5451 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5452 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5453 | "@ | |
d40c829f UW |
5454 | ogr\t%0,%2 |
5455 | og\t%0,%2" | |
d3632d41 | 5456 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5457 | |
9db1d521 | 5458 | (define_insn "iordi3" |
f19a9af7 AK |
5459 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d") |
5460 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0,0,0,0,0,0") | |
5461 | (match_operand:DI 2 "general_operand" "N0HD0,N1HD0,N2HD0,N3HD0,d,m"))) | |
9db1d521 HP |
5462 | (clobber (reg:CC 33))] |
5463 | "TARGET_64BIT" | |
5464 | "@ | |
f19a9af7 AK |
5465 | oihh\t%0,%i2 |
5466 | oihl\t%0,%i2 | |
5467 | oilh\t%0,%i2 | |
5468 | oill\t%0,%i2 | |
d40c829f UW |
5469 | ogr\t%0,%2 |
5470 | og\t%0,%2" | |
f19a9af7 | 5471 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY")]) |
4023fb28 UW |
5472 | |
5473 | (define_insn "*iordi3_ss" | |
ccfc6cc8 | 5474 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5475 | (ior:DI (match_dup 0) |
ccfc6cc8 | 5476 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5477 | (clobber (reg:CC 33))] |
5478 | "" | |
d40c829f | 5479 | "oc\t%O0(8,%R0),%1" |
077dab3b | 5480 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5481 | |
5482 | (define_insn "*iordi3_ss_inv" | |
ccfc6cc8 UW |
5483 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5484 | (ior:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5485 | (match_dup 0))) |
5486 | (clobber (reg:CC 33))] | |
5487 | "" | |
d40c829f | 5488 | "oc\t%O0(8,%R0),%1" |
077dab3b | 5489 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5490 | |
5491 | ; | |
5492 | ; iorsi3 instruction pattern(s). | |
5493 | ; | |
5494 | ||
4023fb28 UW |
5495 | (define_insn "*iorsi3_cc" |
5496 | [(set (reg 33) | |
d3632d41 UW |
5497 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5498 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5499 | (const_int 0))) |
d3632d41 | 5500 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5501 | (ior:SI (match_dup 1) (match_dup 2)))] |
5502 | "s390_match_ccmode(insn, CCTmode)" | |
5503 | "@ | |
d40c829f UW |
5504 | or\t%0,%2 |
5505 | o\t%0,%2 | |
5506 | oy\t%0,%2" | |
d3632d41 | 5507 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5508 | |
5509 | (define_insn "*iorsi3_cconly" | |
5510 | [(set (reg 33) | |
d3632d41 UW |
5511 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5512 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5513 | (const_int 0))) |
d3632d41 | 5514 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5515 | "s390_match_ccmode(insn, CCTmode)" |
5516 | "@ | |
d40c829f UW |
5517 | or\t%0,%2 |
5518 | o\t%0,%2 | |
5519 | oy\t%0,%2" | |
d3632d41 | 5520 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 | 5521 | |
f19a9af7 | 5522 | (define_expand "iorsi3" |
2f7e5a0d | 5523 | [(parallel |
f19a9af7 AK |
5524 | [(set (match_operand:SI 0 "register_operand" "") |
5525 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5526 | (match_operand:SI 2 "general_operand" ""))) | |
5527 | (clobber (reg:CC 33))])] | |
5528 | "" | |
5529 | "") | |
4023fb28 | 5530 | |
f19a9af7 AK |
5531 | (define_insn "iorsi3_zarch" |
5532 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") | |
5533 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0,0,0") | |
5534 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T"))) | |
4023fb28 | 5535 | (clobber (reg:CC 33))] |
f19a9af7 | 5536 | "TARGET_ZARCH" |
4023fb28 | 5537 | "@ |
f19a9af7 AK |
5538 | oilh\t%0,%i2 |
5539 | oill\t%0,%i2 | |
d40c829f UW |
5540 | or\t%0,%2 |
5541 | o\t%0,%2 | |
5542 | oy\t%0,%2" | |
f19a9af7 AK |
5543 | [(set_attr "op_type" "RI,RI,RR,RX,RXY")]) |
5544 | ||
5545 | (define_insn "iorsi3_esa" | |
5546 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5547 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
5548 | (match_operand:SI 2 "general_operand" "d,R"))) | |
5549 | (clobber (reg:CC 33))] | |
5550 | "!TARGET_ZARCH" | |
5551 | "@ | |
5552 | or\t%0,%2 | |
5553 | o\t%0,%2" | |
5554 | [(set_attr "op_type" "RR,RX")]) | |
4023fb28 UW |
5555 | |
5556 | (define_insn "*iorsi3_ss" | |
ccfc6cc8 | 5557 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5558 | (ior:SI (match_dup 0) |
ccfc6cc8 | 5559 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5560 | (clobber (reg:CC 33))] |
5561 | "" | |
d40c829f | 5562 | "oc\t%O0(4,%R0),%1" |
077dab3b | 5563 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5564 | |
5565 | (define_insn "*iorsi3_ss_inv" | |
ccfc6cc8 UW |
5566 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5567 | (ior:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5568 | (match_dup 0))) |
5569 | (clobber (reg:CC 33))] | |
5570 | "" | |
d40c829f | 5571 | "oc\t%O0(4,%R0),%1" |
077dab3b | 5572 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5573 | |
5574 | ; | |
5575 | ; iorhi3 instruction pattern(s). | |
5576 | ; | |
5577 | ||
5578 | (define_insn "*iorhi3_oi" | |
5579 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
5580 | (ior:HI (match_operand:HI 1 "register_operand" "%0,0") | |
5581 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
5582 | (clobber (reg:CC 33))] | |
9e8327e3 | 5583 | "TARGET_ZARCH" |
4023fb28 | 5584 | "@ |
d40c829f UW |
5585 | or\t%0,%2 |
5586 | oill\t%0,%x2" | |
077dab3b | 5587 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 UW |
5588 | |
5589 | (define_insn "iorhi3" | |
5590 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5591 | (ior:HI (match_operand:HI 1 "register_operand" "%0") | |
5592 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5593 | (clobber (reg:CC 33))] | |
9db1d521 | 5594 | "" |
d40c829f | 5595 | "or\t%0,%2" |
077dab3b | 5596 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5597 | |
5598 | (define_insn "*iorhi3_ss" | |
ccfc6cc8 | 5599 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5600 | (ior:HI (match_dup 0) |
ccfc6cc8 | 5601 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5602 | (clobber (reg:CC 33))] |
5603 | "" | |
d40c829f | 5604 | "oc\t%O0(2,%R0),%1" |
077dab3b | 5605 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5606 | |
4023fb28 | 5607 | (define_insn "*iorhi3_ss_inv" |
ccfc6cc8 UW |
5608 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5609 | (ior:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5610 | (match_dup 0))) |
9db1d521 HP |
5611 | (clobber (reg:CC 33))] |
5612 | "" | |
d40c829f | 5613 | "oc\t%O0(2,%R0),%1" |
077dab3b | 5614 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5615 | |
5616 | ; | |
4023fb28 | 5617 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5618 | ; |
5619 | ||
4023fb28 UW |
5620 | (define_insn "*iorqi3_oi" |
5621 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
5622 | (ior:QI (match_operand:QI 1 "register_operand" "%0,0") | |
5623 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
5624 | (clobber (reg:CC 33))] | |
9e8327e3 | 5625 | "TARGET_ZARCH" |
4023fb28 | 5626 | "@ |
d40c829f UW |
5627 | or\t%0,%2 |
5628 | oill\t%0,%b2" | |
077dab3b | 5629 | [(set_attr "op_type" "RR,RI")]) |
9db1d521 | 5630 | |
4023fb28 UW |
5631 | (define_insn "iorqi3" |
5632 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5633 | (ior:QI (match_operand:QI 1 "register_operand" "%0") | |
5634 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5635 | (clobber (reg:CC 33))] | |
5636 | "" | |
d40c829f | 5637 | "or\t%0,%2" |
077dab3b | 5638 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5639 | |
5640 | (define_insn "*iorqi3_ss" | |
d3632d41 | 5641 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5642 | (ior:QI (match_dup 0) |
d3632d41 | 5643 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5644 | (clobber (reg:CC 33))] |
5645 | "" | |
5646 | "@ | |
d40c829f UW |
5647 | oi\t%0,%b1 |
5648 | oiy\t%0,%b1 | |
5649 | oc\t%O0(1,%R0),%1" | |
d3632d41 | 5650 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 | 5651 | |
4023fb28 | 5652 | (define_insn "*iorqi3_ss_inv" |
d3632d41 UW |
5653 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5654 | (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 | 5655 | (match_dup 0))) |
9db1d521 HP |
5656 | (clobber (reg:CC 33))] |
5657 | "" | |
5658 | "@ | |
d40c829f UW |
5659 | oi\t%0,%b1 |
5660 | oiy\t%0,%b1 | |
5661 | oc\t%O0(1,%R0),%1" | |
d3632d41 | 5662 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5663 | |
5664 | ||
5665 | ;; | |
5666 | ;;- Xor instructions. | |
5667 | ;; | |
5668 | ||
5669 | ; | |
5670 | ; xordi3 instruction pattern(s). | |
5671 | ; | |
5672 | ||
4023fb28 UW |
5673 | (define_insn "*xordi3_cc" |
5674 | [(set (reg 33) | |
96fd3851 | 5675 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5676 | (match_operand:DI 2 "general_operand" "d,m")) |
5677 | (const_int 0))) | |
5678 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5679 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5680 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5681 | "@ | |
d40c829f UW |
5682 | xgr\t%0,%2 |
5683 | xg\t%0,%2" | |
d3632d41 | 5684 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5685 | |
5686 | (define_insn "*xordi3_cconly" | |
5687 | [(set (reg 33) | |
96fd3851 | 5688 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5689 | (match_operand:DI 2 "general_operand" "d,m")) |
5690 | (const_int 0))) | |
5691 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5692 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5693 | "@ | |
d40c829f UW |
5694 | xgr\t%0,%2 |
5695 | xr\t%0,%2" | |
d3632d41 | 5696 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5697 | |
9db1d521 | 5698 | (define_insn "xordi3" |
4023fb28 | 5699 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
96fd3851 | 5700 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5701 | (match_operand:DI 2 "general_operand" "d,m"))) |
9db1d521 HP |
5702 | (clobber (reg:CC 33))] |
5703 | "TARGET_64BIT" | |
5704 | "@ | |
d40c829f UW |
5705 | xgr\t%0,%2 |
5706 | xg\t%0,%2" | |
d3632d41 | 5707 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5708 | |
5709 | (define_insn "*xordi3_ss" | |
ccfc6cc8 | 5710 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5711 | (xor:DI (match_dup 0) |
ccfc6cc8 | 5712 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5713 | (clobber (reg:CC 33))] |
5714 | "" | |
d40c829f | 5715 | "xc\t%O0(8,%R0),%1" |
077dab3b | 5716 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5717 | |
5718 | (define_insn "*xordi3_ss_inv" | |
ccfc6cc8 UW |
5719 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5720 | (xor:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5721 | (match_dup 0))) |
5722 | (clobber (reg:CC 33))] | |
5723 | "" | |
d40c829f | 5724 | "xc\t%O0(8,%R0),%1" |
077dab3b | 5725 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5726 | |
5727 | ; | |
5728 | ; xorsi3 instruction pattern(s). | |
5729 | ; | |
5730 | ||
4023fb28 UW |
5731 | (define_insn "*xorsi3_cc" |
5732 | [(set (reg 33) | |
d3632d41 UW |
5733 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5734 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5735 | (const_int 0))) |
d3632d41 | 5736 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5737 | (xor:SI (match_dup 1) (match_dup 2)))] |
5738 | "s390_match_ccmode(insn, CCTmode)" | |
5739 | "@ | |
d40c829f UW |
5740 | xr\t%0,%2 |
5741 | x\t%0,%2 | |
5742 | xy\t%0,%2" | |
d3632d41 | 5743 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5744 | |
5745 | (define_insn "*xorsi3_cconly" | |
5746 | [(set (reg 33) | |
d3632d41 UW |
5747 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5748 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5749 | (const_int 0))) |
d3632d41 | 5750 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5751 | "s390_match_ccmode(insn, CCTmode)" |
5752 | "@ | |
d40c829f UW |
5753 | xr\t%0,%2 |
5754 | x\t%0,%2 | |
5755 | xy\t%0,%2" | |
d3632d41 | 5756 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5757 | |
4023fb28 | 5758 | (define_insn "xorsi3" |
d3632d41 UW |
5759 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
5760 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
5761 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
5762 | (clobber (reg:CC 33))] |
5763 | "" | |
5764 | "@ | |
d40c829f UW |
5765 | xr\t%0,%2 |
5766 | x\t%0,%2 | |
5767 | xy\t%0,%2" | |
d3632d41 | 5768 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5769 | |
5770 | (define_insn "*xorsi3_ss" | |
ccfc6cc8 | 5771 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5772 | (xor:SI (match_dup 0) |
ccfc6cc8 | 5773 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5774 | (clobber (reg:CC 33))] |
5775 | "" | |
d40c829f | 5776 | "xc\t%O0(4,%R0),%1" |
077dab3b | 5777 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5778 | |
5779 | (define_insn "*xorsi3_ss_inv" | |
ccfc6cc8 UW |
5780 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5781 | (xor:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5782 | (match_dup 0))) |
5783 | (clobber (reg:CC 33))] | |
5784 | "" | |
d40c829f | 5785 | "xc\t%O0(4,%R0),%1" |
077dab3b | 5786 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5787 | |
5788 | ; | |
5789 | ; xorhi3 instruction pattern(s). | |
5790 | ; | |
5791 | ||
4023fb28 UW |
5792 | (define_insn "xorhi3" |
5793 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5794 | (xor:HI (match_operand:HI 1 "register_operand" "%0") | |
5795 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5796 | (clobber (reg:CC 33))] | |
9db1d521 | 5797 | "" |
d40c829f | 5798 | "xr\t%0,%2" |
d3632d41 | 5799 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5800 | |
5801 | (define_insn "*xorhi3_ss" | |
ccfc6cc8 | 5802 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5803 | (xor:HI (match_dup 0) |
ccfc6cc8 | 5804 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5805 | (clobber (reg:CC 33))] |
5806 | "" | |
d40c829f | 5807 | "xc\t%O0(2,%R0),%1" |
077dab3b | 5808 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5809 | |
4023fb28 | 5810 | (define_insn "*xorhi3_ss_inv" |
ccfc6cc8 UW |
5811 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5812 | (xor:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5813 | (match_dup 0))) |
9db1d521 HP |
5814 | (clobber (reg:CC 33))] |
5815 | "" | |
d40c829f | 5816 | "xc\t%O0(2,%R0),%1" |
077dab3b | 5817 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5818 | |
5819 | ; | |
5820 | ; xorqi3 instruction pattern(s). | |
5821 | ; | |
5822 | ||
5823 | (define_insn "xorqi3" | |
4023fb28 UW |
5824 | [(set (match_operand:QI 0 "register_operand" "=d") |
5825 | (xor:QI (match_operand:QI 1 "register_operand" "%0") | |
5826 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5827 | (clobber (reg:CC 33))] | |
5828 | "" | |
d40c829f | 5829 | "xr\t%0,%2" |
077dab3b | 5830 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5831 | |
5832 | (define_insn "*xorqi3_ss" | |
d3632d41 | 5833 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5834 | (xor:QI (match_dup 0) |
d3632d41 | 5835 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5836 | (clobber (reg:CC 33))] |
5837 | "" | |
5838 | "@ | |
d40c829f UW |
5839 | xi\t%0,%b1 |
5840 | xiy\t%0,%b1 | |
5841 | xc\t%O0(1,%R0),%1" | |
d3632d41 | 5842 | [(set_attr "op_type" "SI,SIY,SS")]) |
4023fb28 UW |
5843 | |
5844 | (define_insn "*xorqi3_ss_inv" | |
d3632d41 UW |
5845 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5846 | (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 UW |
5847 | (match_dup 0))) |
5848 | (clobber (reg:CC 33))] | |
5849 | "" | |
5850 | "@ | |
d40c829f UW |
5851 | xi\t%0,%b1 |
5852 | xiy\t%0,%b1 | |
5853 | xc\t%O0(1,%R0),%1" | |
d3632d41 | 5854 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5855 | |
5856 | ||
5857 | ;; | |
5858 | ;;- Negate instructions. | |
5859 | ;; | |
5860 | ||
5861 | ; | |
5862 | ; negdi2 instruction pattern(s). | |
5863 | ; | |
5864 | ||
5865 | (define_expand "negdi2" | |
5866 | [(parallel | |
5867 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5868 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5869 | (clobber (reg:CC 33))])] | |
5870 | "" | |
5871 | "") | |
5872 | ||
5873 | (define_insn "*negdi2_64" | |
5874 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5875 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5876 | (clobber (reg:CC 33))] | |
5877 | "TARGET_64BIT" | |
d40c829f | 5878 | "lcgr\t%0,%1" |
f2d3c02a | 5879 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
5880 | |
5881 | (define_insn "*negdi2_31" | |
5882 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5883 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5884 | (clobber (reg:CC 33))] | |
5885 | "!TARGET_64BIT" | |
9db1d521 HP |
5886 | { |
5887 | rtx xop[1]; | |
5888 | xop[0] = gen_label_rtx (); | |
d40c829f UW |
5889 | output_asm_insn ("lcr\t%0,%1", operands); |
5890 | output_asm_insn ("lcr\t%N0,%N1", operands); | |
5891 | output_asm_insn ("je\t%l0", xop); | |
5892 | output_asm_insn ("bctr\t%0,0", operands); | |
47798692 | 5893 | targetm.asm_out.internal_label (asm_out_file, "L", |
9db1d521 | 5894 | CODE_LABEL_NUMBER (xop[0])); |
10bbf137 UW |
5895 | return ""; |
5896 | } | |
9db1d521 | 5897 | [(set_attr "op_type" "NN") |
4023fb28 UW |
5898 | (set_attr "type" "other") |
5899 | (set_attr "length" "10")]) | |
9db1d521 HP |
5900 | |
5901 | ; | |
5902 | ; negsi2 instruction pattern(s). | |
5903 | ; | |
5904 | ||
5905 | (define_insn "negsi2" | |
5906 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5907 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
5908 | (clobber (reg:CC 33))] | |
5909 | "" | |
d40c829f | 5910 | "lcr\t%0,%1" |
f2d3c02a | 5911 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
5912 | |
5913 | ; | |
5914 | ; negdf2 instruction pattern(s). | |
5915 | ; | |
5916 | ||
5917 | (define_expand "negdf2" | |
5918 | [(parallel | |
5919 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5920 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5921 | (clobber (reg:CC 33))])] | |
5922 | "TARGET_HARD_FLOAT" | |
5923 | "") | |
5924 | ||
5925 | (define_insn "*negdf2" | |
5926 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5927 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5928 | (clobber (reg:CC 33))] | |
5929 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5930 | "lcdbr\t%0,%1" |
077dab3b HP |
5931 | [(set_attr "op_type" "RRE") |
5932 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5933 | |
5934 | (define_insn "*negdf2_ibm" | |
5935 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5936 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5937 | (clobber (reg:CC 33))] | |
5938 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5939 | "lcdr\t%0,%1" |
077dab3b HP |
5940 | [(set_attr "op_type" "RR") |
5941 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5942 | |
5943 | ; | |
5944 | ; negsf2 instruction pattern(s). | |
5945 | ; | |
5946 | ||
5947 | (define_expand "negsf2" | |
5948 | [(parallel | |
5949 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5950 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5951 | (clobber (reg:CC 33))])] | |
5952 | "TARGET_HARD_FLOAT" | |
5953 | "") | |
5954 | ||
5955 | (define_insn "*negsf2" | |
5956 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5957 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5958 | (clobber (reg:CC 33))] | |
5959 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5960 | "lcebr\t%0,%1" |
077dab3b HP |
5961 | [(set_attr "op_type" "RRE") |
5962 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5963 | |
5964 | (define_insn "*negsf2" | |
5965 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5966 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5967 | (clobber (reg:CC 33))] | |
5968 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5969 | "lcer\t%0,%1" |
077dab3b HP |
5970 | [(set_attr "op_type" "RR") |
5971 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5972 | |
5973 | ||
5974 | ;; | |
5975 | ;;- Absolute value instructions. | |
5976 | ;; | |
5977 | ||
5978 | ; | |
5979 | ; absdi2 instruction pattern(s). | |
5980 | ; | |
5981 | ||
5982 | (define_insn "absdi2" | |
5983 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5984 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
5985 | (clobber (reg:CC 33))] | |
5986 | "TARGET_64BIT" | |
d40c829f | 5987 | "lpgr\t%0,%1" |
f2d3c02a | 5988 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
5989 | |
5990 | ; | |
5991 | ; abssi2 instruction pattern(s). | |
5992 | ; | |
5993 | ||
5994 | (define_insn "abssi2" | |
5995 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5996 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
5997 | (clobber (reg:CC 33))] | |
5998 | "" | |
d40c829f | 5999 | "lpr\t%0,%1" |
f2d3c02a | 6000 | [(set_attr "op_type" "RR")]) |
9db1d521 | 6001 | |
9db1d521 HP |
6002 | ; |
6003 | ; absdf2 instruction pattern(s). | |
6004 | ; | |
6005 | ||
6006 | (define_expand "absdf2" | |
6007 | [(parallel | |
6008 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6009 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6010 | (clobber (reg:CC 33))])] | |
6011 | "TARGET_HARD_FLOAT" | |
6012 | "") | |
6013 | ||
6014 | (define_insn "*absdf2" | |
6015 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6016 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6017 | (clobber (reg:CC 33))] | |
6018 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6019 | "lpdbr\t%0,%1" |
077dab3b HP |
6020 | [(set_attr "op_type" "RRE") |
6021 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6022 | |
6023 | (define_insn "*absdf2_ibm" | |
6024 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6025 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6026 | (clobber (reg:CC 33))] | |
6027 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6028 | "lpdr\t%0,%1" |
077dab3b HP |
6029 | [(set_attr "op_type" "RR") |
6030 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6031 | |
6032 | ; | |
6033 | ; abssf2 instruction pattern(s). | |
6034 | ; | |
6035 | ||
6036 | (define_expand "abssf2" | |
6037 | [(parallel | |
6038 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6039 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6040 | (clobber (reg:CC 33))])] | |
6041 | "TARGET_HARD_FLOAT" | |
6042 | "") | |
6043 | ||
6044 | (define_insn "*abssf2" | |
6045 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6046 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6047 | (clobber (reg:CC 33))] | |
6048 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6049 | "lpebr\t%0,%1" |
077dab3b HP |
6050 | [(set_attr "op_type" "RRE") |
6051 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
6052 | |
6053 | (define_insn "*abssf2_ibm" | |
6054 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6055 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6056 | (clobber (reg:CC 33))] | |
6057 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6058 | "lper\t%0,%1" |
077dab3b HP |
6059 | [(set_attr "op_type" "RR") |
6060 | (set_attr "type" "fsimps")]) | |
9db1d521 | 6061 | |
3ef093a8 AK |
6062 | ;; |
6063 | ;;- Negated absolute value instructions | |
6064 | ;; | |
6065 | ||
6066 | ; | |
6067 | ; Integer | |
6068 | ; | |
6069 | ||
6070 | (define_insn "*negabssi2" | |
6071 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6072 | (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) | |
6073 | (clobber (reg:CC 33))] | |
6074 | "" | |
d40c829f | 6075 | "lnr\t%0,%1" |
3ef093a8 AK |
6076 | [(set_attr "op_type" "RR")]) |
6077 | ||
6078 | (define_insn "*negabsdi2" | |
6079 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6080 | (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) | |
6081 | (clobber (reg:CC 33))] | |
6082 | "TARGET_64BIT" | |
d40c829f | 6083 | "lngr\t%0,%1" |
3ef093a8 AK |
6084 | [(set_attr "op_type" "RRE")]) |
6085 | ||
6086 | ; | |
6087 | ; Floating point | |
6088 | ; | |
6089 | ||
6090 | (define_insn "*negabssf2" | |
6091 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6092 | (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) | |
6093 | (clobber (reg:CC 33))] | |
6094 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6095 | "lnebr\t%0,%1" |
3ef093a8 AK |
6096 | [(set_attr "op_type" "RRE") |
6097 | (set_attr "type" "fsimps")]) | |
6098 | ||
6099 | (define_insn "*negabsdf2" | |
6100 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6101 | (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) | |
6102 | (clobber (reg:CC 33))] | |
6103 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6104 | "lndbr\t%0,%1" |
3ef093a8 AK |
6105 | [(set_attr "op_type" "RRE") |
6106 | (set_attr "type" "fsimpd")]) | |
6107 | ||
4023fb28 UW |
6108 | ;; |
6109 | ;;- Square root instructions. | |
6110 | ;; | |
6111 | ||
6112 | ; | |
6113 | ; sqrtdf2 instruction pattern(s). | |
6114 | ; | |
6115 | ||
6116 | (define_insn "sqrtdf2" | |
6117 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 6118 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6119 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6120 | "@ | |
d40c829f UW |
6121 | sqdbr\t%0,%1 |
6122 | sqdb\t%0,%1" | |
d3632d41 | 6123 | [(set_attr "op_type" "RRE,RXE")]) |
4023fb28 UW |
6124 | |
6125 | ; | |
6126 | ; sqrtsf2 instruction pattern(s). | |
6127 | ; | |
6128 | ||
6129 | (define_insn "sqrtsf2" | |
6130 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 6131 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6132 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6133 | "@ | |
d40c829f UW |
6134 | sqebr\t%0,%1 |
6135 | sqeb\t%0,%1" | |
d3632d41 | 6136 | [(set_attr "op_type" "RRE,RXE")]) |
9db1d521 HP |
6137 | |
6138 | ;; | |
6139 | ;;- One complement instructions. | |
6140 | ;; | |
6141 | ||
6142 | ; | |
6143 | ; one_cmpldi2 instruction pattern(s). | |
6144 | ; | |
c7453384 | 6145 | |
9db1d521 HP |
6146 | (define_expand "one_cmpldi2" |
6147 | [(parallel | |
4023fb28 UW |
6148 | [(set (match_operand:DI 0 "register_operand" "") |
6149 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
6150 | (const_int -1))) | |
9db1d521 HP |
6151 | (clobber (reg:CC 33))])] |
6152 | "TARGET_64BIT" | |
4023fb28 | 6153 | "") |
c7453384 | 6154 | |
9db1d521 HP |
6155 | ; |
6156 | ; one_cmplsi2 instruction pattern(s). | |
6157 | ; | |
c7453384 | 6158 | |
9db1d521 HP |
6159 | (define_expand "one_cmplsi2" |
6160 | [(parallel | |
4023fb28 UW |
6161 | [(set (match_operand:SI 0 "register_operand" "") |
6162 | (xor:SI (match_operand:SI 1 "register_operand" "") | |
6163 | (const_int -1))) | |
9db1d521 HP |
6164 | (clobber (reg:CC 33))])] |
6165 | "" | |
4023fb28 | 6166 | "") |
c7453384 | 6167 | |
9db1d521 HP |
6168 | ; |
6169 | ; one_cmplhi2 instruction pattern(s). | |
6170 | ; | |
c7453384 | 6171 | |
9db1d521 HP |
6172 | (define_expand "one_cmplhi2" |
6173 | [(parallel | |
4023fb28 UW |
6174 | [(set (match_operand:HI 0 "register_operand" "") |
6175 | (xor:HI (match_operand:HI 1 "register_operand" "") | |
6176 | (const_int -1))) | |
9db1d521 HP |
6177 | (clobber (reg:CC 33))])] |
6178 | "" | |
4023fb28 | 6179 | "") |
c7453384 | 6180 | |
9db1d521 HP |
6181 | ; |
6182 | ; one_cmplqi2 instruction pattern(s). | |
6183 | ; | |
c7453384 | 6184 | |
4023fb28 UW |
6185 | (define_expand "one_cmplqi2" |
6186 | [(parallel | |
6187 | [(set (match_operand:QI 0 "register_operand" "") | |
6188 | (xor:QI (match_operand:QI 1 "register_operand" "") | |
6189 | (const_int -1))) | |
6190 | (clobber (reg:CC 33))])] | |
9db1d521 | 6191 | "" |
4023fb28 | 6192 | "") |
9db1d521 HP |
6193 | |
6194 | ||
6195 | ;; | |
6196 | ;;- Rotate instructions. | |
6197 | ;; | |
6198 | ||
6199 | ; | |
6200 | ; rotldi3 instruction pattern(s). | |
6201 | ; | |
6202 | ||
6203 | (define_insn "rotldi3" | |
ac32b25e UW |
6204 | [(set (match_operand:DI 0 "register_operand" "=d") |
6205 | (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
6206 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6207 | "TARGET_64BIT" |
ac32b25e | 6208 | "rllg\t%0,%1,%Y2" |
077dab3b HP |
6209 | [(set_attr "op_type" "RSE") |
6210 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6211 | |
6212 | ; | |
6213 | ; rotlsi3 instruction pattern(s). | |
6214 | ; | |
6215 | ||
6216 | (define_insn "rotlsi3" | |
ac32b25e UW |
6217 | [(set (match_operand:SI 0 "register_operand" "=d") |
6218 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
6219 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9e8327e3 | 6220 | "TARGET_CPU_ZARCH" |
ac32b25e | 6221 | "rll\t%0,%1,%Y2" |
077dab3b HP |
6222 | [(set_attr "op_type" "RSE") |
6223 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6224 | |
6225 | ||
6226 | ;; | |
6227 | ;;- Arithmetic shift instructions. | |
6228 | ;; | |
9db1d521 HP |
6229 | |
6230 | ; | |
6231 | ; ashldi3 instruction pattern(s). | |
6232 | ; | |
6233 | ||
6234 | (define_expand "ashldi3" | |
ecbe845e UW |
6235 | [(set (match_operand:DI 0 "register_operand" "") |
6236 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6237 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6238 | "" |
6239 | "") | |
6240 | ||
6241 | (define_insn "*ashldi3_31" | |
ac32b25e UW |
6242 | [(set (match_operand:DI 0 "register_operand" "=d") |
6243 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
6244 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6245 | "!TARGET_64BIT" |
ac32b25e | 6246 | "sldl\t%0,%Y2" |
077dab3b HP |
6247 | [(set_attr "op_type" "RS") |
6248 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6249 | |
6250 | (define_insn "*ashldi3_64" | |
ac32b25e UW |
6251 | [(set (match_operand:DI 0 "register_operand" "=d") |
6252 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
6253 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6254 | "TARGET_64BIT" |
ac32b25e | 6255 | "sllg\t%0,%1,%Y2" |
077dab3b HP |
6256 | [(set_attr "op_type" "RSE") |
6257 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6258 | |
6259 | ; | |
6260 | ; ashrdi3 instruction pattern(s). | |
6261 | ; | |
6262 | ||
6263 | (define_expand "ashrdi3" | |
6264 | [(parallel | |
6265 | [(set (match_operand:DI 0 "register_operand" "") | |
6266 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6267 | (match_operand:SI 2 "shift_count_operand" ""))) |
9db1d521 HP |
6268 | (clobber (reg:CC 33))])] |
6269 | "" | |
6270 | "") | |
6271 | ||
ecbe845e UW |
6272 | (define_insn "*ashrdi3_cc_31" |
6273 | [(set (reg 33) | |
ac32b25e UW |
6274 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6275 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6276 | (const_int 0))) |
ac32b25e | 6277 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6278 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6279 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6280 | "srda\t%0,%Y2" |
077dab3b HP |
6281 | [(set_attr "op_type" "RS") |
6282 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6283 | |
6284 | (define_insn "*ashrdi3_cconly_31" | |
6285 | [(set (reg 33) | |
ac32b25e UW |
6286 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6287 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6288 | (const_int 0))) |
ac32b25e | 6289 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6290 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6291 | "srda\t%0,%Y2" |
077dab3b HP |
6292 | [(set_attr "op_type" "RS") |
6293 | (set_attr "atype" "reg")]) | |
ecbe845e | 6294 | |
9db1d521 | 6295 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6296 | [(set (match_operand:DI 0 "register_operand" "=d") |
6297 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6298 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6299 | (clobber (reg:CC 33))] |
6300 | "!TARGET_64BIT" | |
ac32b25e | 6301 | "srda\t%0,%Y2" |
077dab3b HP |
6302 | [(set_attr "op_type" "RS") |
6303 | (set_attr "atype" "reg")]) | |
c7453384 | 6304 | |
ecbe845e UW |
6305 | (define_insn "*ashrdi3_cc_64" |
6306 | [(set (reg 33) | |
ac32b25e UW |
6307 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6308 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6309 | (const_int 0))) |
ac32b25e | 6310 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6311 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6312 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
ac32b25e | 6313 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6314 | [(set_attr "op_type" "RSE") |
6315 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6316 | |
6317 | (define_insn "*ashrdi3_cconly_64" | |
6318 | [(set (reg 33) | |
ac32b25e UW |
6319 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6320 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6321 | (const_int 0))) |
ac32b25e | 6322 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6323 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
ac32b25e | 6324 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6325 | [(set_attr "op_type" "RSE") |
6326 | (set_attr "atype" "reg")]) | |
ecbe845e | 6327 | |
9db1d521 | 6328 | (define_insn "*ashrdi3_64" |
ac32b25e UW |
6329 | [(set (match_operand:DI 0 "register_operand" "=d") |
6330 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6331 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6332 | (clobber (reg:CC 33))] |
6333 | "TARGET_64BIT" | |
ac32b25e | 6334 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6335 | [(set_attr "op_type" "RSE") |
6336 | (set_attr "atype" "reg")]) | |
6337 | ||
9db1d521 HP |
6338 | |
6339 | ; | |
6340 | ; ashlsi3 instruction pattern(s). | |
6341 | ; | |
9db1d521 HP |
6342 | |
6343 | (define_insn "ashlsi3" | |
ac32b25e UW |
6344 | [(set (match_operand:SI 0 "register_operand" "=d") |
6345 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
6346 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6347 | "" |
ac32b25e | 6348 | "sll\t%0,%Y2" |
077dab3b HP |
6349 | [(set_attr "op_type" "RS") |
6350 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6351 | |
6352 | ; | |
6353 | ; ashrsi3 instruction pattern(s). | |
6354 | ; | |
6355 | ||
ecbe845e UW |
6356 | (define_insn "*ashrsi3_cc" |
6357 | [(set (reg 33) | |
ac32b25e UW |
6358 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6359 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6360 | (const_int 0))) |
ac32b25e | 6361 | (set (match_operand:SI 0 "register_operand" "=d") |
ecbe845e UW |
6362 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
6363 | "s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6364 | "sra\t%0,%Y2" |
077dab3b HP |
6365 | [(set_attr "op_type" "RS") |
6366 | (set_attr "atype" "reg")]) | |
6367 | ||
ecbe845e UW |
6368 | |
6369 | (define_insn "*ashrsi3_cconly" | |
6370 | [(set (reg 33) | |
ac32b25e UW |
6371 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6372 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6373 | (const_int 0))) |
ac32b25e | 6374 | (clobber (match_scratch:SI 0 "=d"))] |
ecbe845e | 6375 | "s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6376 | "sra\t%0,%Y2" |
077dab3b HP |
6377 | [(set_attr "op_type" "RS") |
6378 | (set_attr "atype" "reg")]) | |
ecbe845e | 6379 | |
9db1d521 | 6380 | (define_insn "ashrsi3" |
ac32b25e UW |
6381 | [(set (match_operand:SI 0 "register_operand" "=d") |
6382 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6383 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6384 | (clobber (reg:CC 33))] |
6385 | "" | |
ac32b25e | 6386 | "sra\t%0,%Y2" |
077dab3b HP |
6387 | [(set_attr "op_type" "RS") |
6388 | (set_attr "atype" "reg")]) | |
9db1d521 | 6389 | |
9db1d521 HP |
6390 | |
6391 | ;; | |
6392 | ;;- logical shift instructions. | |
6393 | ;; | |
6394 | ||
6395 | ; | |
6396 | ; lshrdi3 instruction pattern(s). | |
6397 | ; | |
6398 | ||
6399 | (define_expand "lshrdi3" | |
ecbe845e UW |
6400 | [(set (match_operand:DI 0 "register_operand" "") |
6401 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6402 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6403 | "" |
6404 | "") | |
6405 | ||
6406 | (define_insn "*lshrdi3_31" | |
ac32b25e UW |
6407 | [(set (match_operand:DI 0 "register_operand" "=d") |
6408 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6409 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6410 | "!TARGET_64BIT" |
ac32b25e UW |
6411 | "srdl\t%0,%Y2" |
6412 | [(set_attr "op_type" "RS") | |
077dab3b | 6413 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6414 | |
6415 | (define_insn "*lshrdi3_64" | |
ac32b25e UW |
6416 | [(set (match_operand:DI 0 "register_operand" "=d") |
6417 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6418 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6419 | "TARGET_64BIT" |
ac32b25e UW |
6420 | "srlg\t%0,%1,%Y2" |
6421 | [(set_attr "op_type" "RSE") | |
077dab3b | 6422 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6423 | |
6424 | ; | |
6425 | ; lshrsi3 instruction pattern(s). | |
6426 | ; | |
6427 | ||
6428 | (define_insn "lshrsi3" | |
ac32b25e UW |
6429 | [(set (match_operand:SI 0 "register_operand" "=d") |
6430 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6431 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6432 | "" |
ac32b25e | 6433 | "srl\t%0,%Y2" |
077dab3b HP |
6434 | [(set_attr "op_type" "RS") |
6435 | (set_attr "atype" "reg")]) | |
9db1d521 | 6436 | |
9db1d521 HP |
6437 | |
6438 | ;; | |
6439 | ;; Branch instruction patterns. | |
6440 | ;; | |
6441 | ||
6442 | (define_expand "beq" | |
6590e19a | 6443 | [(match_operand 0 "" "")] |
9db1d521 | 6444 | "" |
6590e19a UW |
6445 | "s390_emit_jump (operands[0], |
6446 | s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6447 | |
6448 | (define_expand "bne" | |
6590e19a | 6449 | [(match_operand 0 "" "")] |
9db1d521 | 6450 | "" |
6590e19a UW |
6451 | "s390_emit_jump (operands[0], |
6452 | s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6453 | |
6454 | (define_expand "bgt" | |
6590e19a | 6455 | [(match_operand 0 "" "")] |
9db1d521 | 6456 | "" |
6590e19a UW |
6457 | "s390_emit_jump (operands[0], |
6458 | s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6459 | |
6460 | (define_expand "bgtu" | |
6590e19a | 6461 | [(match_operand 0 "" "")] |
9db1d521 | 6462 | "" |
6590e19a UW |
6463 | "s390_emit_jump (operands[0], |
6464 | s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6465 | |
6466 | (define_expand "blt" | |
6590e19a | 6467 | [(match_operand 0 "" "")] |
9db1d521 | 6468 | "" |
6590e19a UW |
6469 | "s390_emit_jump (operands[0], |
6470 | s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6471 | |
6472 | (define_expand "bltu" | |
6590e19a | 6473 | [(match_operand 0 "" "")] |
9db1d521 | 6474 | "" |
6590e19a UW |
6475 | "s390_emit_jump (operands[0], |
6476 | s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6477 | |
6478 | (define_expand "bge" | |
6590e19a | 6479 | [(match_operand 0 "" "")] |
9db1d521 | 6480 | "" |
6590e19a UW |
6481 | "s390_emit_jump (operands[0], |
6482 | s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6483 | |
6484 | (define_expand "bgeu" | |
6590e19a | 6485 | [(match_operand 0 "" "")] |
9db1d521 | 6486 | "" |
6590e19a UW |
6487 | "s390_emit_jump (operands[0], |
6488 | s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6489 | |
6490 | (define_expand "ble" | |
6590e19a | 6491 | [(match_operand 0 "" "")] |
9db1d521 | 6492 | "" |
6590e19a UW |
6493 | "s390_emit_jump (operands[0], |
6494 | s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6495 | |
6496 | (define_expand "bleu" | |
6590e19a | 6497 | [(match_operand 0 "" "")] |
9db1d521 | 6498 | "" |
6590e19a UW |
6499 | "s390_emit_jump (operands[0], |
6500 | s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 | 6501 | |
ba956982 | 6502 | (define_expand "bunordered" |
6590e19a | 6503 | [(match_operand 0 "" "")] |
ba956982 | 6504 | "" |
6590e19a UW |
6505 | "s390_emit_jump (operands[0], |
6506 | s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
6507 | |
6508 | (define_expand "bordered" | |
6590e19a | 6509 | [(match_operand 0 "" "")] |
ba956982 | 6510 | "" |
6590e19a UW |
6511 | "s390_emit_jump (operands[0], |
6512 | s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
6513 | |
6514 | (define_expand "buneq" | |
6590e19a | 6515 | [(match_operand 0 "" "")] |
ba956982 | 6516 | "" |
6590e19a UW |
6517 | "s390_emit_jump (operands[0], |
6518 | s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
6519 | |
6520 | (define_expand "bunlt" | |
6590e19a | 6521 | [(match_operand 0 "" "")] |
ba956982 | 6522 | "" |
6590e19a UW |
6523 | "s390_emit_jump (operands[0], |
6524 | s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 | 6525 | |
6590e19a UW |
6526 | (define_expand "bungt" |
6527 | [(match_operand 0 "" "")] | |
ba956982 | 6528 | "" |
6590e19a UW |
6529 | "s390_emit_jump (operands[0], |
6530 | s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
6531 | |
6532 | (define_expand "bunle" | |
6590e19a | 6533 | [(match_operand 0 "" "")] |
ba956982 | 6534 | "" |
6590e19a UW |
6535 | "s390_emit_jump (operands[0], |
6536 | s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;") | |
6537 | ||
6538 | (define_expand "bunge" | |
6539 | [(match_operand 0 "" "")] | |
6540 | "" | |
6541 | "s390_emit_jump (operands[0], | |
6542 | s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
6543 | |
6544 | (define_expand "bltgt" | |
6590e19a | 6545 | [(match_operand 0 "" "")] |
ba956982 | 6546 | "" |
6590e19a UW |
6547 | "s390_emit_jump (operands[0], |
6548 | s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 | 6549 | |
9db1d521 HP |
6550 | |
6551 | ;; | |
6552 | ;;- Conditional jump instructions. | |
6553 | ;; | |
6554 | ||
6590e19a UW |
6555 | (define_insn "*cjump_64" |
6556 | [(set (pc) | |
6557 | (if_then_else | |
6558 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
6559 | (label_ref (match_operand 0 "" "")) | |
6560 | (pc)))] | |
6561 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6562 | { |
13e58269 | 6563 | if (get_attr_length (insn) == 4) |
d40c829f | 6564 | return "j%C1\t%l0"; |
6590e19a | 6565 | else |
d40c829f | 6566 | return "jg%C1\t%l0"; |
6590e19a UW |
6567 | } |
6568 | [(set_attr "op_type" "RI") | |
6569 | (set_attr "type" "branch") | |
6570 | (set (attr "length") | |
6571 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6572 | (const_int 4) (const_int 6)))]) | |
6573 | ||
6574 | (define_insn "*cjump_31" | |
6575 | [(set (pc) | |
6576 | (if_then_else | |
6577 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
6578 | (label_ref (match_operand 0 "" "")) | |
6579 | (pc)))] | |
6580 | "!TARGET_CPU_ZARCH" | |
6581 | { | |
6582 | if (get_attr_length (insn) == 4) | |
6583 | return "j%C1\t%l0"; | |
9db1d521 | 6584 | else |
13e58269 | 6585 | abort (); |
10bbf137 | 6586 | } |
9db1d521 | 6587 | [(set_attr "op_type" "RI") |
077dab3b | 6588 | (set_attr "type" "branch") |
13e58269 | 6589 | (set (attr "length") |
6590e19a UW |
6590 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6591 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6592 | (const_int 4) (const_int 6)) | |
6593 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6594 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6595 | |
f314b9b1 | 6596 | (define_insn "*cjump_long" |
6590e19a UW |
6597 | [(set (pc) |
6598 | (if_then_else | |
6599 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
6600 | (match_operand 0 "address_operand" "U") | |
6601 | (pc)))] | |
9db1d521 | 6602 | "" |
f314b9b1 UW |
6603 | { |
6604 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6605 | return "b%C1r\t%0"; |
f314b9b1 | 6606 | else |
d40c829f | 6607 | return "b%C1\t%a0"; |
10bbf137 | 6608 | } |
c7453384 | 6609 | [(set (attr "op_type") |
f314b9b1 UW |
6610 | (if_then_else (match_operand 0 "register_operand" "") |
6611 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 6612 | (set_attr "type" "branch") |
077dab3b | 6613 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6614 | |
6615 | ||
6616 | ;; | |
6617 | ;;- Negated conditional jump instructions. | |
6618 | ;; | |
6619 | ||
6590e19a UW |
6620 | (define_insn "*icjump_64" |
6621 | [(set (pc) | |
6622 | (if_then_else | |
6623 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
6624 | (pc) | |
6625 | (label_ref (match_operand 0 "" ""))))] | |
6626 | "TARGET_CPU_ZARCH" | |
c7453384 | 6627 | { |
13e58269 | 6628 | if (get_attr_length (insn) == 4) |
d40c829f | 6629 | return "j%D1\t%l0"; |
6590e19a | 6630 | else |
d40c829f | 6631 | return "jg%D1\t%l0"; |
6590e19a UW |
6632 | } |
6633 | [(set_attr "op_type" "RI") | |
6634 | (set_attr "type" "branch") | |
6635 | (set (attr "length") | |
6636 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6637 | (const_int 4) (const_int 6)))]) | |
6638 | ||
6639 | (define_insn "*icjump_31" | |
6640 | [(set (pc) | |
6641 | (if_then_else | |
6642 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
6643 | (pc) | |
6644 | (label_ref (match_operand 0 "" ""))))] | |
6645 | "!TARGET_CPU_ZARCH" | |
6646 | { | |
6647 | if (get_attr_length (insn) == 4) | |
6648 | return "j%D1\t%l0"; | |
9db1d521 | 6649 | else |
13e58269 | 6650 | abort (); |
10bbf137 | 6651 | } |
9db1d521 | 6652 | [(set_attr "op_type" "RI") |
077dab3b | 6653 | (set_attr "type" "branch") |
13e58269 | 6654 | (set (attr "length") |
6590e19a UW |
6655 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6656 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6657 | (const_int 4) (const_int 6)) | |
6658 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6659 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6660 | |
f314b9b1 | 6661 | (define_insn "*icjump_long" |
6590e19a UW |
6662 | [(set (pc) |
6663 | (if_then_else | |
6664 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
6665 | (pc) | |
6666 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 6667 | "" |
f314b9b1 UW |
6668 | { |
6669 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6670 | return "b%D1r\t%0"; |
f314b9b1 | 6671 | else |
d40c829f | 6672 | return "b%D1\t%a0"; |
10bbf137 | 6673 | } |
c7453384 | 6674 | [(set (attr "op_type") |
f314b9b1 UW |
6675 | (if_then_else (match_operand 0 "register_operand" "") |
6676 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6677 | (set_attr "type" "branch") |
6678 | (set_attr "atype" "agen")]) | |
9db1d521 | 6679 | |
4456530d HP |
6680 | ;; |
6681 | ;;- Trap instructions. | |
6682 | ;; | |
6683 | ||
6684 | (define_insn "trap" | |
6685 | [(trap_if (const_int 1) (const_int 0))] | |
6686 | "" | |
d40c829f | 6687 | "j\t.+2" |
6590e19a | 6688 | [(set_attr "op_type" "RI") |
077dab3b | 6689 | (set_attr "type" "branch")]) |
4456530d HP |
6690 | |
6691 | (define_expand "conditional_trap" | |
6590e19a UW |
6692 | [(trap_if (match_operand 0 "comparison_operator" "") |
6693 | (match_operand 1 "general_operand" ""))] | |
4456530d | 6694 | "" |
4456530d | 6695 | { |
6590e19a UW |
6696 | if (operands[1] != const0_rtx) FAIL; |
6697 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
6698 | s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6699 | }) |
4456530d HP |
6700 | |
6701 | (define_insn "*trap" | |
6702 | [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)]) | |
6703 | (const_int 0))] | |
6704 | "" | |
d40c829f | 6705 | "j%C0\t.+2"; |
077dab3b HP |
6706 | [(set_attr "op_type" "RI") |
6707 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6708 | |
6709 | ;; | |
0a3bdf9d | 6710 | ;;- Loop instructions. |
9db1d521 | 6711 | ;; |
0a3bdf9d UW |
6712 | ;; This is all complicated by the fact that since this is a jump insn |
6713 | ;; we must handle our own output reloads. | |
c7453384 | 6714 | |
0a3bdf9d UW |
6715 | (define_expand "doloop_end" |
6716 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6717 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6718 | (use (match_operand 2 "" "")) ; max iterations | |
6719 | (use (match_operand 3 "" "")) ; loop level | |
6720 | (use (match_operand 4 "" ""))] ; label | |
6721 | "" | |
0a3bdf9d | 6722 | { |
6590e19a UW |
6723 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
6724 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
6725 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
6726 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
6727 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
6728 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6729 | else | |
6730 | FAIL; | |
6731 | ||
6732 | DONE; | |
10bbf137 | 6733 | }) |
0a3bdf9d | 6734 | |
6590e19a | 6735 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
6736 | [(set (pc) |
6737 | (if_then_else | |
6738 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6739 | (const_int 1)) | |
6740 | (label_ref (match_operand 0 "" "")) | |
6741 | (pc))) | |
bd446804 | 6742 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d UW |
6743 | (plus:SI (match_dup 1) (const_int -1))) |
6744 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6745 | (clobber (reg:CC 33))] | |
6590e19a | 6746 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6747 | { |
6748 | if (which_alternative != 0) | |
10bbf137 | 6749 | return "#"; |
0a3bdf9d | 6750 | else if (get_attr_length (insn) == 4) |
d40c829f | 6751 | return "brct\t%1,%l0"; |
6590e19a | 6752 | else |
545d16ff | 6753 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
6754 | } |
6755 | "&& reload_completed | |
6756 | && (! REG_P (operands[2]) | |
6757 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6758 | [(set (match_dup 3) (match_dup 1)) | |
6759 | (parallel [(set (reg:CCAN 33) | |
6760 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
6761 | (const_int 0))) | |
6762 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6763 | (set (match_dup 2) (match_dup 3)) | |
6764 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6765 | (label_ref (match_dup 0)) | |
6766 | (pc)))] | |
6767 | "" | |
6768 | [(set_attr "op_type" "RI") | |
6769 | (set_attr "type" "branch") | |
6770 | (set (attr "length") | |
6771 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6772 | (const_int 4) (const_int 10)))]) | |
6773 | ||
6774 | (define_insn_and_split "doloop_si31" | |
6775 | [(set (pc) | |
6776 | (if_then_else | |
6777 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6778 | (const_int 1)) | |
6779 | (label_ref (match_operand 0 "" "")) | |
6780 | (pc))) | |
6781 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") | |
6782 | (plus:SI (match_dup 1) (const_int -1))) | |
6783 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6784 | (clobber (reg:CC 33))] | |
6785 | "!TARGET_CPU_ZARCH" | |
6786 | { | |
6787 | if (which_alternative != 0) | |
6788 | return "#"; | |
6789 | else if (get_attr_length (insn) == 4) | |
6790 | return "brct\t%1,%l0"; | |
0a3bdf9d UW |
6791 | else |
6792 | abort (); | |
10bbf137 | 6793 | } |
6590e19a UW |
6794 | "&& reload_completed |
6795 | && (! REG_P (operands[2]) | |
6796 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6797 | [(set (match_dup 3) (match_dup 1)) | |
6798 | (parallel [(set (reg:CCAN 33) | |
6799 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
6800 | (const_int 0))) | |
6801 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6802 | (set (match_dup 2) (match_dup 3)) | |
6803 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6804 | (label_ref (match_dup 0)) | |
6805 | (pc)))] | |
6806 | "" | |
0a3bdf9d | 6807 | [(set_attr "op_type" "RI") |
077dab3b | 6808 | (set_attr "type" "branch") |
0a3bdf9d | 6809 | (set (attr "length") |
6590e19a UW |
6810 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6811 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6812 | (const_int 4) (const_int 6)) | |
6813 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6814 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6815 | |
0a3bdf9d UW |
6816 | (define_insn "*doloop_si_long" |
6817 | [(set (pc) | |
6818 | (if_then_else | |
6819 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6820 | (const_int 1)) | |
d3632d41 | 6821 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6822 | (pc))) |
6823 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6824 | (plus:SI (match_dup 1) (const_int -1))) | |
6825 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6826 | (clobber (reg:CC 33))] | |
6590e19a | 6827 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6828 | { |
6829 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6830 | return "bctr\t%1,%0"; |
0a3bdf9d | 6831 | else |
d40c829f | 6832 | return "bct\t%1,%a0"; |
10bbf137 | 6833 | } |
c7453384 | 6834 | [(set (attr "op_type") |
0a3bdf9d UW |
6835 | (if_then_else (match_operand 0 "register_operand" "") |
6836 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6837 | (set_attr "type" "branch") |
6838 | (set_attr "atype" "agen")]) | |
0a3bdf9d | 6839 | |
6590e19a | 6840 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
6841 | [(set (pc) |
6842 | (if_then_else | |
6843 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6844 | (const_int 1)) | |
6845 | (label_ref (match_operand 0 "" "")) | |
6846 | (pc))) | |
bd446804 | 6847 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*r") |
0a3bdf9d UW |
6848 | (plus:DI (match_dup 1) (const_int -1))) |
6849 | (clobber (match_scratch:DI 3 "=X,&d")) | |
6850 | (clobber (reg:CC 33))] | |
6851 | "TARGET_64BIT" | |
0a3bdf9d UW |
6852 | { |
6853 | if (which_alternative != 0) | |
10bbf137 | 6854 | return "#"; |
0a3bdf9d | 6855 | else if (get_attr_length (insn) == 4) |
d40c829f | 6856 | return "brctg\t%1,%l0"; |
0a3bdf9d | 6857 | else |
545d16ff | 6858 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 6859 | } |
6590e19a | 6860 | "&& reload_completed |
0a3bdf9d UW |
6861 | && (! REG_P (operands[2]) |
6862 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6863 | [(set (match_dup 3) (match_dup 1)) | |
6864 | (parallel [(set (reg:CCAN 33) | |
6865 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) | |
6866 | (const_int 0))) | |
6867 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6868 | (set (match_dup 2) (match_dup 3)) | |
6869 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6590e19a | 6870 | (label_ref (match_dup 0)) |
0a3bdf9d | 6871 | (pc)))] |
6590e19a UW |
6872 | "" |
6873 | [(set_attr "op_type" "RI") | |
6874 | (set_attr "type" "branch") | |
6875 | (set (attr "length") | |
6876 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6877 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
6878 | |
6879 | ;; | |
6880 | ;;- Unconditional jump instructions. | |
6881 | ;; | |
6882 | ||
6883 | ; | |
6884 | ; jump instruction pattern(s). | |
6885 | ; | |
6886 | ||
6590e19a UW |
6887 | (define_expand "jump" |
6888 | [(match_operand 0 "" "")] | |
9db1d521 | 6889 | "" |
6590e19a UW |
6890 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
6891 | ||
6892 | (define_insn "*jump64" | |
6893 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6894 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6895 | { |
13e58269 | 6896 | if (get_attr_length (insn) == 4) |
d40c829f | 6897 | return "j\t%l0"; |
6590e19a | 6898 | else |
d40c829f | 6899 | return "jg\t%l0"; |
6590e19a UW |
6900 | } |
6901 | [(set_attr "op_type" "RI") | |
6902 | (set_attr "type" "branch") | |
6903 | (set (attr "length") | |
6904 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6905 | (const_int 4) (const_int 6)))]) | |
6906 | ||
6907 | (define_insn "*jump31" | |
6908 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6909 | "!TARGET_CPU_ZARCH" | |
6910 | { | |
6911 | if (get_attr_length (insn) == 4) | |
6912 | return "j\t%l0"; | |
9db1d521 | 6913 | else |
13e58269 | 6914 | abort (); |
10bbf137 | 6915 | } |
9db1d521 | 6916 | [(set_attr "op_type" "RI") |
077dab3b | 6917 | (set_attr "type" "branch") |
13e58269 | 6918 | (set (attr "length") |
6590e19a UW |
6919 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6920 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6921 | (const_int 4) (const_int 6)) | |
6922 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6923 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
6924 | |
6925 | ; | |
6926 | ; indirect-jump instruction pattern(s). | |
6927 | ; | |
6928 | ||
6929 | (define_insn "indirect_jump" | |
d3632d41 | 6930 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6931 | "" |
f314b9b1 UW |
6932 | { |
6933 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6934 | return "br\t%0"; |
f314b9b1 | 6935 | else |
d40c829f | 6936 | return "b\t%a0"; |
10bbf137 | 6937 | } |
c7453384 | 6938 | [(set (attr "op_type") |
f314b9b1 UW |
6939 | (if_then_else (match_operand 0 "register_operand" "") |
6940 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6941 | (set_attr "type" "branch") |
6942 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6943 | |
6944 | ; | |
f314b9b1 | 6945 | ; casesi instruction pattern(s). |
9db1d521 HP |
6946 | ; |
6947 | ||
f314b9b1 | 6948 | (define_insn "casesi_jump" |
d3632d41 | 6949 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 6950 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 6951 | "" |
9db1d521 | 6952 | { |
f314b9b1 | 6953 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 6954 | return "br\t%0"; |
f314b9b1 | 6955 | else |
d40c829f | 6956 | return "b\t%a0"; |
10bbf137 | 6957 | } |
c7453384 | 6958 | [(set (attr "op_type") |
f314b9b1 UW |
6959 | (if_then_else (match_operand 0 "register_operand" "") |
6960 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6961 | (set_attr "type" "branch") |
6962 | (set_attr "atype" "agen")]) | |
9db1d521 | 6963 | |
f314b9b1 UW |
6964 | (define_expand "casesi" |
6965 | [(match_operand:SI 0 "general_operand" "") | |
6966 | (match_operand:SI 1 "general_operand" "") | |
6967 | (match_operand:SI 2 "general_operand" "") | |
6968 | (label_ref (match_operand 3 "" "")) | |
6969 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 6970 | "" |
f314b9b1 UW |
6971 | { |
6972 | rtx index = gen_reg_rtx (SImode); | |
6973 | rtx base = gen_reg_rtx (Pmode); | |
6974 | rtx target = gen_reg_rtx (Pmode); | |
6975 | ||
6976 | emit_move_insn (index, operands[0]); | |
6977 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6978 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 6979 | operands[4]); |
f314b9b1 UW |
6980 | |
6981 | if (Pmode != SImode) | |
6982 | index = convert_to_mode (Pmode, index, 1); | |
6983 | if (GET_CODE (index) != REG) | |
6984 | index = copy_to_mode_reg (Pmode, index); | |
6985 | ||
6986 | if (TARGET_64BIT) | |
6987 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6988 | else | |
a556fd39 | 6989 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 6990 | |
f314b9b1 UW |
6991 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6992 | ||
6993 | index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index)); | |
cfa29496 UW |
6994 | RTX_UNCHANGING_P (index) = 1; |
6995 | MEM_NOTRAP_P (index) = 1; | |
f314b9b1 UW |
6996 | emit_move_insn (target, index); |
6997 | ||
6998 | if (flag_pic) | |
6999 | target = gen_rtx_PLUS (Pmode, base, target); | |
7000 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
7001 | ||
7002 | DONE; | |
10bbf137 | 7003 | }) |
9db1d521 HP |
7004 | |
7005 | ||
7006 | ;; | |
7007 | ;;- Jump to subroutine. | |
7008 | ;; | |
7009 | ;; | |
7010 | ||
7011 | ; | |
7012 | ; untyped call instruction pattern(s). | |
7013 | ; | |
7014 | ||
7015 | ;; Call subroutine returning any type. | |
7016 | (define_expand "untyped_call" | |
7017 | [(parallel [(call (match_operand 0 "" "") | |
7018 | (const_int 0)) | |
7019 | (match_operand 1 "" "") | |
7020 | (match_operand 2 "" "")])] | |
7021 | "" | |
9db1d521 HP |
7022 | { |
7023 | int i; | |
7024 | ||
7025 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
7026 | ||
7027 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7028 | { | |
7029 | rtx set = XVECEXP (operands[2], 0, i); | |
7030 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7031 | } | |
7032 | ||
7033 | /* The optimizer does not know that the call sets the function value | |
7034 | registers we stored in the result block. We avoid problems by | |
7035 | claiming that all hard registers are used and clobbered at this | |
7036 | point. */ | |
7037 | emit_insn (gen_blockage ()); | |
7038 | ||
7039 | DONE; | |
10bbf137 | 7040 | }) |
9db1d521 HP |
7041 | |
7042 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7043 | ;; all of memory. This blocks insns from being moved across this point. | |
7044 | ||
7045 | (define_insn "blockage" | |
10bbf137 | 7046 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 7047 | "" |
4023fb28 | 7048 | "" |
d5869ca0 UW |
7049 | [(set_attr "type" "none") |
7050 | (set_attr "length" "0")]) | |
4023fb28 | 7051 | |
9db1d521 | 7052 | ; |
ed9676cf | 7053 | ; sibcall patterns |
9db1d521 HP |
7054 | ; |
7055 | ||
ed9676cf | 7056 | (define_expand "sibcall" |
44b8152b | 7057 | [(call (match_operand 0 "" "") |
ed9676cf | 7058 | (match_operand 1 "" ""))] |
9db1d521 | 7059 | "" |
9db1d521 | 7060 | { |
ed9676cf AK |
7061 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
7062 | DONE; | |
7063 | }) | |
9db1d521 | 7064 | |
ed9676cf AK |
7065 | (define_insn "*sibcall_br" |
7066 | [(call (mem:QI (reg 1)) | |
7067 | (match_operand 0 "const_int_operand" "n"))] | |
2f7e5a0d | 7068 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7069 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
7070 | "br\t%%r1" | |
7071 | [(set_attr "op_type" "RR") | |
7072 | (set_attr "type" "branch") | |
7073 | (set_attr "atype" "agen")]) | |
9db1d521 | 7074 | |
ed9676cf AK |
7075 | (define_insn "*sibcall_brc" |
7076 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7077 | (match_operand 1 "const_int_operand" "n"))] | |
7078 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7079 | "j\t%0" | |
7080 | [(set_attr "op_type" "RI") | |
7081 | (set_attr "type" "branch")]) | |
9db1d521 | 7082 | |
ed9676cf AK |
7083 | (define_insn "*sibcall_brcl" |
7084 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7085 | (match_operand 1 "const_int_operand" "n"))] | |
7086 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7087 | "jg\t%0" | |
7088 | [(set_attr "op_type" "RIL") | |
7089 | (set_attr "type" "branch")]) | |
44b8152b | 7090 | |
ed9676cf AK |
7091 | ; |
7092 | ; sibcall_value patterns | |
7093 | ; | |
9e8327e3 | 7094 | |
ed9676cf AK |
7095 | (define_expand "sibcall_value" |
7096 | [(set (match_operand 0 "" "") | |
7097 | (call (match_operand 1 "" "") | |
7098 | (match_operand 2 "" "")))] | |
7099 | "" | |
7100 | { | |
7101 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 7102 | DONE; |
10bbf137 | 7103 | }) |
9db1d521 | 7104 | |
ed9676cf AK |
7105 | (define_insn "*sibcall_value_br" |
7106 | [(set (match_operand 0 "" "") | |
7107 | (call (mem:QI (reg 1)) | |
7108 | (match_operand 1 "const_int_operand" "n")))] | |
2f7e5a0d | 7109 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7110 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
7111 | "br\t%%r1" | |
7112 | [(set_attr "op_type" "RR") | |
7113 | (set_attr "type" "branch") | |
7114 | (set_attr "atype" "agen")]) | |
7115 | ||
7116 | (define_insn "*sibcall_value_brc" | |
7117 | [(set (match_operand 0 "" "") | |
7118 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7119 | (match_operand 2 "const_int_operand" "n")))] | |
7120 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7121 | "j\t%1" | |
7122 | [(set_attr "op_type" "RI") | |
7123 | (set_attr "type" "branch")]) | |
7124 | ||
7125 | (define_insn "*sibcall_value_brcl" | |
7126 | [(set (match_operand 0 "" "") | |
7127 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7128 | (match_operand 2 "const_int_operand" "n")))] | |
7129 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7130 | "jg\t%1" | |
7131 | [(set_attr "op_type" "RIL") | |
7132 | (set_attr "type" "branch")]) | |
7133 | ||
7134 | ||
7135 | ; | |
7136 | ; call instruction pattern(s). | |
7137 | ; | |
7138 | ||
7139 | (define_expand "call" | |
7140 | [(call (match_operand 0 "" "") | |
7141 | (match_operand 1 "" "")) | |
7142 | (use (match_operand 2 "" ""))] | |
44b8152b | 7143 | "" |
ed9676cf | 7144 | { |
2f7e5a0d | 7145 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
7146 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
7147 | DONE; | |
7148 | }) | |
44b8152b | 7149 | |
9e8327e3 UW |
7150 | (define_insn "*bras" |
7151 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7152 | (match_operand 1 "const_int_operand" "n")) | |
7153 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7154 | "!SIBLING_CALL_P (insn) |
7155 | && TARGET_SMALL_EXEC | |
ed9676cf | 7156 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 7157 | "bras\t%2,%0" |
9db1d521 | 7158 | [(set_attr "op_type" "RI") |
4023fb28 | 7159 | (set_attr "type" "jsr")]) |
9db1d521 | 7160 | |
9e8327e3 UW |
7161 | (define_insn "*brasl" |
7162 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7163 | (match_operand 1 "const_int_operand" "n")) | |
7164 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7165 | "!SIBLING_CALL_P (insn) |
7166 | && TARGET_CPU_ZARCH | |
ed9676cf | 7167 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7168 | "brasl\t%2,%0" |
7169 | [(set_attr "op_type" "RIL") | |
077dab3b | 7170 | (set_attr "type" "jsr")]) |
9db1d521 | 7171 | |
9e8327e3 UW |
7172 | (define_insn "*basr" |
7173 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
7174 | (match_operand 1 "const_int_operand" "n")) | |
7175 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 7176 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7177 | { |
7178 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7179 | return "basr\t%2,%0"; | |
7180 | else | |
7181 | return "bas\t%2,%a0"; | |
7182 | } | |
7183 | [(set (attr "op_type") | |
7184 | (if_then_else (match_operand 0 "register_operand" "") | |
7185 | (const_string "RR") (const_string "RX"))) | |
7186 | (set_attr "type" "jsr") | |
7187 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7188 | |
7189 | ; | |
7190 | ; call_value instruction pattern(s). | |
7191 | ; | |
7192 | ||
7193 | (define_expand "call_value" | |
44b8152b UW |
7194 | [(set (match_operand 0 "" "") |
7195 | (call (match_operand 1 "" "") | |
7196 | (match_operand 2 "" ""))) | |
7197 | (use (match_operand 3 "" ""))] | |
9db1d521 | 7198 | "" |
9db1d521 | 7199 | { |
2f7e5a0d | 7200 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 7201 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 7202 | DONE; |
10bbf137 | 7203 | }) |
9db1d521 | 7204 | |
9e8327e3 | 7205 | (define_insn "*bras_r" |
c19ec8f9 | 7206 | [(set (match_operand 0 "" "") |
9e8327e3 | 7207 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7208 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 7209 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
7210 | "!SIBLING_CALL_P (insn) |
7211 | && TARGET_SMALL_EXEC | |
ed9676cf | 7212 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7213 | "bras\t%3,%1" |
9db1d521 | 7214 | [(set_attr "op_type" "RI") |
f2d3c02a | 7215 | (set_attr "type" "jsr")]) |
9db1d521 | 7216 | |
9e8327e3 | 7217 | (define_insn "*brasl_r" |
c19ec8f9 | 7218 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7219 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7220 | (match_operand 2 "const_int_operand" "n"))) | |
7221 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
7222 | "!SIBLING_CALL_P (insn) |
7223 | && TARGET_CPU_ZARCH | |
ed9676cf | 7224 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7225 | "brasl\t%3,%1" |
7226 | [(set_attr "op_type" "RIL") | |
077dab3b | 7227 | (set_attr "type" "jsr")]) |
9db1d521 | 7228 | |
9e8327e3 | 7229 | (define_insn "*basr_r" |
c19ec8f9 | 7230 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7231 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7232 | (match_operand 2 "const_int_operand" "n"))) | |
7233 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 7234 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7235 | { |
7236 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7237 | return "basr\t%3,%1"; | |
7238 | else | |
7239 | return "bas\t%3,%a1"; | |
7240 | } | |
7241 | [(set (attr "op_type") | |
7242 | (if_then_else (match_operand 1 "register_operand" "") | |
7243 | (const_string "RR") (const_string "RX"))) | |
7244 | (set_attr "type" "jsr") | |
7245 | (set_attr "atype" "agen")]) | |
9db1d521 | 7246 | |
fd3cd001 UW |
7247 | ;; |
7248 | ;;- Thread-local storage support. | |
7249 | ;; | |
7250 | ||
7251 | (define_insn "get_tp_64" | |
7252 | [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q") | |
7253 | (unspec:DI [(const_int 0)] UNSPEC_TP))] | |
7254 | "TARGET_64BIT" | |
7255 | "@ | |
d40c829f UW |
7256 | ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1 |
7257 | stam\t%%a0,%%a1,%0" | |
fd3cd001 UW |
7258 | [(set_attr "op_type" "NN,RS") |
7259 | (set_attr "atype" "reg,*") | |
7260 | (set_attr "type" "o3,*") | |
7261 | (set_attr "length" "14,*")]) | |
7262 | ||
7263 | (define_insn "get_tp_31" | |
7264 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q") | |
7265 | (unspec:SI [(const_int 0)] UNSPEC_TP))] | |
7266 | "!TARGET_64BIT" | |
7267 | "@ | |
d40c829f UW |
7268 | ear\t%0,%%a0 |
7269 | stam\t%%a0,%%a0,%0" | |
fd3cd001 UW |
7270 | [(set_attr "op_type" "RRE,RS")]) |
7271 | ||
7272 | (define_insn "set_tp_64" | |
7273 | [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP) | |
7274 | (clobber (match_scratch:SI 1 "=d,X"))] | |
7275 | "TARGET_64BIT" | |
7276 | "@ | |
d40c829f UW |
7277 | sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1 |
7278 | lam\t%%a0,%%a1,%0" | |
fd3cd001 UW |
7279 | [(set_attr "op_type" "NN,RS") |
7280 | (set_attr "atype" "reg,*") | |
7281 | (set_attr "type" "o3,*") | |
7282 | (set_attr "length" "14,*")]) | |
7283 | ||
7284 | (define_insn "set_tp_31" | |
7285 | [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)] | |
7286 | "!TARGET_64BIT" | |
7287 | "@ | |
d40c829f UW |
7288 | sar\t%%a0,%0 |
7289 | lam\t%%a0,%%a0,%0" | |
fd3cd001 | 7290 | [(set_attr "op_type" "RRE,RS")]) |
c7453384 | 7291 | |
fd3cd001 UW |
7292 | (define_insn "*tls_load_64" |
7293 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7294 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7295 | (match_operand:DI 2 "" "")] | |
7296 | UNSPEC_TLS_LOAD))] | |
7297 | "TARGET_64BIT" | |
d40c829f | 7298 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7299 | [(set_attr "op_type" "RXE")]) |
7300 | ||
7301 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7302 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7303 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7304 | (match_operand:SI 2 "" "")] |
7305 | UNSPEC_TLS_LOAD))] | |
7306 | "!TARGET_64BIT" | |
d3632d41 | 7307 | "@ |
d40c829f UW |
7308 | l\t%0,%1%J2 |
7309 | ly\t%0,%1%J2" | |
d3632d41 | 7310 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 | 7311 | |
9e8327e3 | 7312 | (define_insn "*bras_tls" |
c19ec8f9 | 7313 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7314 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7315 | (match_operand 2 "const_int_operand" "n"))) | |
7316 | (clobber (match_operand 3 "register_operand" "=r")) | |
7317 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7318 | "!SIBLING_CALL_P (insn) |
7319 | && TARGET_SMALL_EXEC | |
ed9676cf | 7320 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7321 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7322 | [(set_attr "op_type" "RI") |
7323 | (set_attr "type" "jsr")]) | |
7324 | ||
9e8327e3 | 7325 | (define_insn "*brasl_tls" |
c19ec8f9 | 7326 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7327 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7328 | (match_operand 2 "const_int_operand" "n"))) | |
7329 | (clobber (match_operand 3 "register_operand" "=r")) | |
7330 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7331 | "!SIBLING_CALL_P (insn) |
7332 | && TARGET_CPU_ZARCH | |
ed9676cf | 7333 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7334 | "brasl\t%3,%1%J4" |
7335 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7336 | (set_attr "type" "jsr")]) |
7337 | ||
9e8327e3 | 7338 | (define_insn "*basr_tls" |
c19ec8f9 | 7339 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7340 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7341 | (match_operand 2 "const_int_operand" "n"))) | |
7342 | (clobber (match_operand 3 "register_operand" "=r")) | |
7343 | (use (match_operand 4 "" ""))] | |
ed9676cf | 7344 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7345 | { |
7346 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7347 | return "basr\t%3,%1%J4"; | |
7348 | else | |
7349 | return "bas\t%3,%a1%J4"; | |
7350 | } | |
7351 | [(set (attr "op_type") | |
7352 | (if_then_else (match_operand 1 "register_operand" "") | |
7353 | (const_string "RR") (const_string "RX"))) | |
7354 | (set_attr "type" "jsr") | |
7355 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7356 | |
9db1d521 HP |
7357 | ;; |
7358 | ;;- Miscellaneous instructions. | |
7359 | ;; | |
7360 | ||
7361 | ; | |
7362 | ; allocate stack instruction pattern(s). | |
7363 | ; | |
7364 | ||
7365 | (define_expand "allocate_stack" | |
7366 | [(set (reg 15) | |
7367 | (plus (reg 15) (match_operand 1 "general_operand" ""))) | |
7368 | (set (match_operand 0 "general_operand" "") | |
7369 | (reg 15))] | |
590fcf48 | 7370 | "TARGET_BACKCHAIN" |
9db1d521 | 7371 | { |
f1c25d3b KH |
7372 | rtx stack = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
7373 | rtx chain = gen_rtx_MEM (Pmode, stack); | |
9db1d521 | 7374 | rtx temp = gen_reg_rtx (Pmode); |
c7453384 | 7375 | |
9db1d521 HP |
7376 | emit_move_insn (temp, chain); |
7377 | ||
7378 | if (TARGET_64BIT) | |
7379 | emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
7380 | else | |
7381 | emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
7382 | ||
7383 | emit_move_insn (chain, temp); | |
7384 | ||
c7453384 | 7385 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
9db1d521 | 7386 | DONE; |
10bbf137 | 7387 | }) |
9db1d521 HP |
7388 | |
7389 | ||
7390 | ; | |
43ab026f | 7391 | ; setjmp instruction pattern. |
9db1d521 HP |
7392 | ; |
7393 | ||
9db1d521 | 7394 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7395 | [(match_operand 0 "" "")] |
f314b9b1 | 7396 | "flag_pic" |
9db1d521 | 7397 | { |
585539a1 | 7398 | emit_insn (s390_load_got ()); |
fd7643fb | 7399 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
9db1d521 | 7400 | DONE; |
fd7643fb | 7401 | }) |
9db1d521 | 7402 | |
9db1d521 HP |
7403 | ;; These patterns say how to save and restore the stack pointer. We need not |
7404 | ;; save the stack pointer at function level since we are careful to | |
7405 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7406 | ;; when we restore the stack pointer. | |
7407 | ;; | |
7408 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7409 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7410 | ;; save area is a memory location. | |
7411 | ||
7412 | (define_expand "save_stack_function" | |
7413 | [(match_operand 0 "general_operand" "") | |
7414 | (match_operand 1 "general_operand" "")] | |
7415 | "" | |
7416 | "DONE;") | |
7417 | ||
7418 | (define_expand "restore_stack_function" | |
7419 | [(match_operand 0 "general_operand" "") | |
7420 | (match_operand 1 "general_operand" "")] | |
7421 | "" | |
7422 | "DONE;") | |
7423 | ||
7424 | (define_expand "restore_stack_block" | |
7425 | [(use (match_operand 0 "register_operand" "")) | |
7426 | (set (match_dup 2) (match_dup 3)) | |
7427 | (set (match_dup 0) (match_operand 1 "register_operand" "")) | |
7428 | (set (match_dup 3) (match_dup 2))] | |
7429 | "" | |
9db1d521 HP |
7430 | { |
7431 | operands[2] = gen_reg_rtx (Pmode); | |
7432 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); | |
10bbf137 | 7433 | }) |
9db1d521 HP |
7434 | |
7435 | (define_expand "save_stack_nonlocal" | |
7436 | [(match_operand 0 "memory_operand" "") | |
7437 | (match_operand 1 "register_operand" "")] | |
7438 | "" | |
9db1d521 HP |
7439 | { |
7440 | rtx temp = gen_reg_rtx (Pmode); | |
7441 | ||
43ab026f | 7442 | /* Copy the backchain to the first word, sp to the second and the literal pool |
ff482c8d | 7443 | base to the third. */ |
43ab026f AK |
7444 | emit_move_insn (operand_subword (operands[0], 2, 0, |
7445 | TARGET_64BIT ? OImode : TImode), | |
7446 | gen_rtx_REG (Pmode, BASE_REGISTER)); | |
9db1d521 HP |
7447 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
7448 | emit_move_insn (operand_subword (operands[0], 0, 0, | |
43ab026f | 7449 | TARGET_64BIT ? OImode : TImode), |
9db1d521 HP |
7450 | temp); |
7451 | emit_move_insn (operand_subword (operands[0], 1, 0, | |
43ab026f | 7452 | TARGET_64BIT ? OImode : TImode), |
9db1d521 HP |
7453 | operands[1]); |
7454 | DONE; | |
10bbf137 | 7455 | }) |
9db1d521 HP |
7456 | |
7457 | (define_expand "restore_stack_nonlocal" | |
7458 | [(match_operand 0 "register_operand" "") | |
7459 | (match_operand 1 "memory_operand" "")] | |
7460 | "" | |
9db1d521 HP |
7461 | { |
7462 | rtx temp = gen_reg_rtx (Pmode); | |
43ab026f | 7463 | rtx base = gen_rtx_REG (Pmode, BASE_REGISTER); |
9db1d521 | 7464 | |
43ab026f | 7465 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 7466 | literal pool base from the third. */ |
9db1d521 HP |
7467 | emit_move_insn (temp, |
7468 | operand_subword (operands[1], 0, 0, | |
43ab026f | 7469 | TARGET_64BIT ? OImode : TImode)); |
9db1d521 HP |
7470 | emit_move_insn (operands[0], |
7471 | operand_subword (operands[1], 1, 0, | |
43ab026f | 7472 | TARGET_64BIT ? OImode : TImode)); |
9db1d521 | 7473 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
43ab026f AK |
7474 | emit_move_insn (base, |
7475 | operand_subword (operands[1], 2, 0, | |
7476 | TARGET_64BIT ? OImode : TImode)); | |
7477 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
7478 | ||
9db1d521 | 7479 | DONE; |
10bbf137 | 7480 | }) |
9db1d521 HP |
7481 | |
7482 | ||
7483 | ; | |
7484 | ; nop instruction pattern(s). | |
7485 | ; | |
7486 | ||
7487 | (define_insn "nop" | |
7488 | [(const_int 0)] | |
7489 | "" | |
d40c829f | 7490 | "lr\t0,0" |
9db1d521 HP |
7491 | [(set_attr "op_type" "RR")]) |
7492 | ||
7493 | ||
7494 | ; | |
7495 | ; Special literal pool access instruction pattern(s). | |
7496 | ; | |
7497 | ||
416cf582 UW |
7498 | (define_insn "*pool_entry" |
7499 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7500 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7501 | "" |
9db1d521 | 7502 | { |
416cf582 UW |
7503 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7504 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 7505 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
7506 | return ""; |
7507 | } | |
416cf582 | 7508 | [(set_attr "op_type" "NN") |
2f7e5a0d | 7509 | (set (attr "length") |
416cf582 | 7510 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 UW |
7511 | |
7512 | (define_insn "pool_start_31" | |
fd7643fb | 7513 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] |
9e8327e3 | 7514 | "!TARGET_CPU_ZARCH" |
d40c829f | 7515 | ".align\t4" |
b2ccb744 UW |
7516 | [(set_attr "op_type" "NN") |
7517 | (set_attr "length" "2")]) | |
7518 | ||
7519 | (define_insn "pool_end_31" | |
fd7643fb | 7520 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] |
9e8327e3 | 7521 | "!TARGET_CPU_ZARCH" |
d40c829f | 7522 | ".align\t2" |
b2ccb744 UW |
7523 | [(set_attr "op_type" "NN") |
7524 | (set_attr "length" "2")]) | |
7525 | ||
7526 | (define_insn "pool_start_64" | |
fd7643fb | 7527 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] |
9e8327e3 | 7528 | "TARGET_CPU_ZARCH" |
d40c829f | 7529 | ".section\t.rodata\;.align\t8" |
b2ccb744 UW |
7530 | [(set_attr "op_type" "NN") |
7531 | (set_attr "length" "0")]) | |
7532 | ||
7533 | (define_insn "pool_end_64" | |
fd7643fb | 7534 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] |
9e8327e3 | 7535 | "TARGET_CPU_ZARCH" |
b2ccb744 UW |
7536 | ".previous" |
7537 | [(set_attr "op_type" "NN") | |
7538 | (set_attr "length" "0")]) | |
7539 | ||
5af2f3d3 | 7540 | (define_insn "main_base_31_small" |
9e8327e3 UW |
7541 | [(set (match_operand 0 "register_operand" "=a") |
7542 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7543 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7544 | "basr\t%0,0" |
7545 | [(set_attr "op_type" "RR") | |
7546 | (set_attr "type" "la")]) | |
7547 | ||
7548 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
7549 | [(set (match_operand 0 "register_operand" "=a") |
7550 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 7551 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 7552 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
7553 | "bras\t%0,%2" |
7554 | [(set_attr "op_type" "RI")]) | |
7555 | ||
7556 | (define_insn "main_base_64" | |
9e8327e3 UW |
7557 | [(set (match_operand 0 "register_operand" "=a") |
7558 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7559 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7560 | "larl\t%0,%1" |
7561 | [(set_attr "op_type" "RIL") | |
7562 | (set_attr "type" "larl")]) | |
7563 | ||
7564 | (define_insn "main_pool" | |
585539a1 UW |
7565 | [(set (match_operand 0 "register_operand" "=a") |
7566 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
7567 | "GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7568 | "* abort ();" |
7569 | [(set_attr "op_type" "NN")]) | |
7570 | ||
aee4e0db | 7571 | (define_insn "reload_base_31" |
9e8327e3 UW |
7572 | [(set (match_operand 0 "register_operand" "=a") |
7573 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7574 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7575 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
9db1d521 | 7576 | [(set_attr "op_type" "NN") |
b2ccb744 UW |
7577 | (set_attr "type" "la") |
7578 | (set_attr "length" "6")]) | |
7579 | ||
aee4e0db | 7580 | (define_insn "reload_base_64" |
9e8327e3 UW |
7581 | [(set (match_operand 0 "register_operand" "=a") |
7582 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7583 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7584 | "larl\t%0,%1" |
aee4e0db | 7585 | [(set_attr "op_type" "RIL") |
077dab3b | 7586 | (set_attr "type" "larl")]) |
aee4e0db | 7587 | |
aee4e0db | 7588 | (define_insn "pool" |
fd7643fb | 7589 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db UW |
7590 | "" |
7591 | "* abort ();" | |
7592 | [(set_attr "op_type" "NN") | |
7593 | (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
9db1d521 | 7594 | |
4023fb28 UW |
7595 | ;; |
7596 | ;; Insns related to generating the function prologue and epilogue. | |
7597 | ;; | |
7598 | ||
7599 | ||
7600 | (define_expand "prologue" | |
7601 | [(use (const_int 0))] | |
7602 | "" | |
10bbf137 | 7603 | "s390_emit_prologue (); DONE;") |
4023fb28 | 7604 | |
2f7e5a0d EC |
7605 | (define_insn "prologue_tpf" |
7606 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE) | |
7607 | (clobber (reg:DI 1))] | |
3839e36a | 7608 | "TARGET_TPF_PROFILING" |
2f7e5a0d EC |
7609 | "bas\t%%r1,4064" |
7610 | [(set_attr "type" "jsr") | |
7611 | (set_attr "op_type" "RX")]) | |
7612 | ||
4023fb28 UW |
7613 | (define_expand "epilogue" |
7614 | [(use (const_int 1))] | |
7615 | "" | |
ed9676cf AK |
7616 | "s390_emit_epilogue (false); DONE;") |
7617 | ||
2f7e5a0d EC |
7618 | (define_insn "epilogue_tpf" |
7619 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE) | |
7620 | (clobber (reg:DI 1))] | |
3839e36a | 7621 | "TARGET_TPF_PROFILING" |
2f7e5a0d EC |
7622 | "bas\t%%r1,4070" |
7623 | [(set_attr "type" "jsr") | |
7624 | (set_attr "op_type" "RX")]) | |
7625 | ||
7626 | ||
ed9676cf AK |
7627 | (define_expand "sibcall_epilogue" |
7628 | [(use (const_int 0))] | |
7629 | "" | |
7630 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 7631 | |
9e8327e3 | 7632 | (define_insn "*return" |
4023fb28 | 7633 | [(return) |
9e8327e3 UW |
7634 | (use (match_operand 0 "register_operand" "a"))] |
7635 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7636 | "br\t%0" |
4023fb28 | 7637 | [(set_attr "op_type" "RR") |
c7453384 | 7638 | (set_attr "type" "jsr") |
077dab3b | 7639 | (set_attr "atype" "agen")]) |
4023fb28 | 7640 | |
4023fb28 | 7641 | |
c7453384 | 7642 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 7643 | ;; pointer. This is used for compatibility. |
c7453384 EC |
7644 | |
7645 | (define_expand "ptr_extend" | |
7646 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7647 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7648 | "TARGET_64BIT" |
c7453384 | 7649 | { |
c7453384 EC |
7650 | emit_insn (gen_anddi3 (operands[0], |
7651 | gen_lowpart (DImode, operands[1]), | |
7652 | GEN_INT (0x7fffffff))); | |
c7453384 | 7653 | DONE; |
10bbf137 | 7654 | }) |