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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
cbe34bb5 | 2 | ;; Copyright (C) 1999-2017 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
77 | UNSPEC_LTREL_OFFSET |
78 | UNSPEC_LTREL_BASE | |
79 | UNSPEC_POOL_OFFSET | |
80 | UNSPEC_GOTENT | |
81 | UNSPEC_GOT | |
82 | UNSPEC_GOTOFF | |
83 | UNSPEC_PLT | |
84 | UNSPEC_PLTOFF | |
fd7643fb UW |
85 | |
86 | ; Literal pool | |
30a49b23 AK |
87 | UNSPEC_RELOAD_BASE |
88 | UNSPEC_MAIN_BASE | |
89 | UNSPEC_LTREF | |
90 | UNSPEC_INSN | |
91 | UNSPEC_EXECUTE | |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
3af82a61 AK |
159 | UNSPEC_VEC_MERGEH |
160 | UNSPEC_VEC_MERGEL | |
161 | UNSPEC_VEC_PACK | |
162 | UNSPEC_VEC_PACK_SATURATE | |
163 | UNSPEC_VEC_PACK_SATURATE_CC | |
164 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
165 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
168 | UNSPEC_VEC_PERM | |
169 | UNSPEC_VEC_PERMI | |
170 | UNSPEC_VEC_EXTEND | |
171 | UNSPEC_VEC_STORE_LEN | |
172 | UNSPEC_VEC_UNPACKH | |
173 | UNSPEC_VEC_UNPACKH_L | |
174 | UNSPEC_VEC_UNPACKL | |
175 | UNSPEC_VEC_UNPACKL_L | |
176 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
177 | UNSPEC_VEC_ADDE_U128 |
178 | UNSPEC_VEC_ADDEC_U128 | |
179 | UNSPEC_VEC_AVG | |
180 | UNSPEC_VEC_AVGU | |
181 | UNSPEC_VEC_CHECKSUM | |
182 | UNSPEC_VEC_GFMSUM | |
183 | UNSPEC_VEC_GFMSUM_128 | |
184 | UNSPEC_VEC_GFMSUM_ACCUM | |
185 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
186 | UNSPEC_VEC_SET | |
187 | ||
188 | UNSPEC_VEC_VSUMG | |
189 | UNSPEC_VEC_VSUMQ | |
190 | UNSPEC_VEC_VSUM | |
191 | UNSPEC_VEC_RL_MASK | |
192 | UNSPEC_VEC_SLL | |
193 | UNSPEC_VEC_SLB | |
194 | UNSPEC_VEC_SLDB | |
195 | UNSPEC_VEC_SRAL | |
196 | UNSPEC_VEC_SRAB | |
197 | UNSPEC_VEC_SRL | |
198 | UNSPEC_VEC_SRLB | |
199 | ||
3af82a61 | 200 | UNSPEC_VEC_SUBC |
3af82a61 AK |
201 | UNSPEC_VEC_SUBE_U128 |
202 | UNSPEC_VEC_SUBEC_U128 | |
203 | ||
204 | UNSPEC_VEC_TEST_MASK | |
205 | ||
206 | UNSPEC_VEC_VFAE | |
207 | UNSPEC_VEC_VFAECC | |
208 | ||
209 | UNSPEC_VEC_VFEE | |
210 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
211 | UNSPEC_VEC_VFENE |
212 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
213 | |
214 | UNSPEC_VEC_VISTR | |
215 | UNSPEC_VEC_VISTRCC | |
216 | ||
217 | UNSPEC_VEC_VSTRC | |
218 | UNSPEC_VEC_VSTRCCC | |
219 | ||
220 | UNSPEC_VEC_VCDGB | |
221 | UNSPEC_VEC_VCDLGB | |
222 | ||
223 | UNSPEC_VEC_VCGDB | |
224 | UNSPEC_VEC_VCLGDB | |
225 | ||
226 | UNSPEC_VEC_VFIDB | |
227 | ||
228 | UNSPEC_VEC_VLDEB | |
229 | UNSPEC_VEC_VLEDB | |
230 | ||
231 | UNSPEC_VEC_VFTCIDB | |
232 | UNSPEC_VEC_VFTCIDBCC | |
085261c8 | 233 | ]) |
fd3cd001 UW |
234 | |
235 | ;; | |
236 | ;; UNSPEC_VOLATILE usage | |
237 | ;; | |
238 | ||
30a49b23 AK |
239 | (define_c_enum "unspecv" [ |
240 | ; Blockage | |
241 | UNSPECV_BLOCKAGE | |
10bbf137 | 242 | |
2f7e5a0d | 243 | ; TPF Support |
30a49b23 AK |
244 | UNSPECV_TPF_PROLOGUE |
245 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 246 | |
10bbf137 | 247 | ; Literal pool |
30a49b23 AK |
248 | UNSPECV_POOL |
249 | UNSPECV_POOL_SECTION | |
250 | UNSPECV_POOL_ALIGN | |
251 | UNSPECV_POOL_ENTRY | |
252 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
253 | |
254 | ; TLS support | |
30a49b23 | 255 | UNSPECV_SET_TP |
e0374221 AS |
256 | |
257 | ; Atomic Support | |
30a49b23 AK |
258 | UNSPECV_CAS |
259 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 260 | |
f8af0e30 DV |
261 | ; Hotpatching (unremovable NOPs) |
262 | UNSPECV_NOP_2_BYTE | |
263 | UNSPECV_NOP_4_BYTE | |
264 | UNSPECV_NOP_6_BYTE | |
265 | ||
5a3fe9b6 AK |
266 | ; Transactional Execution support |
267 | UNSPECV_TBEGIN | |
2561451d | 268 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
269 | UNSPECV_TBEGINC |
270 | UNSPECV_TEND | |
271 | UNSPECV_TABORT | |
272 | UNSPECV_ETND | |
273 | UNSPECV_NTSTG | |
274 | UNSPECV_PPA | |
004f64e1 AK |
275 | |
276 | ; Set and get floating point control register | |
277 | UNSPECV_SFPC | |
278 | UNSPECV_EFPC | |
4cb4721f MK |
279 | |
280 | ; Split stack support | |
281 | UNSPECV_SPLIT_STACK_CALL | |
282 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
283 | |
284 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
285 | ]) |
286 | ||
ae156f85 AS |
287 | ;; |
288 | ;; Registers | |
289 | ;; | |
290 | ||
35dd9a0e AK |
291 | ; Registers with special meaning |
292 | ||
ae156f85 AS |
293 | (define_constants |
294 | [ | |
295 | ; Sibling call register. | |
296 | (SIBCALL_REGNUM 1) | |
297 | ; Literal pool base register. | |
298 | (BASE_REGNUM 13) | |
299 | ; Return address register. | |
300 | (RETURN_REGNUM 14) | |
82c6f58a AK |
301 | ; Stack pointer register. |
302 | (STACK_REGNUM 15) | |
ae156f85 AS |
303 | ; Condition code register. |
304 | (CC_REGNUM 33) | |
f4aa3848 | 305 | ; Thread local storage pointer register. |
ae156f85 AS |
306 | (TP_REGNUM 36) |
307 | ]) | |
308 | ||
35dd9a0e AK |
309 | ; Hardware register names |
310 | ||
311 | (define_constants | |
312 | [ | |
313 | ; General purpose registers | |
314 | (GPR0_REGNUM 0) | |
af344a30 | 315 | (GPR1_REGNUM 1) |
82379bdf AK |
316 | (GPR2_REGNUM 2) |
317 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
318 | ; Floating point registers. |
319 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
320 | (FPR1_REGNUM 20) |
321 | (FPR2_REGNUM 17) | |
322 | (FPR3_REGNUM 21) | |
323 | (FPR4_REGNUM 18) | |
324 | (FPR5_REGNUM 22) | |
325 | (FPR6_REGNUM 19) | |
326 | (FPR7_REGNUM 23) | |
327 | (FPR8_REGNUM 24) | |
328 | (FPR9_REGNUM 28) | |
329 | (FPR10_REGNUM 25) | |
330 | (FPR11_REGNUM 29) | |
331 | (FPR12_REGNUM 26) | |
332 | (FPR13_REGNUM 30) | |
333 | (FPR14_REGNUM 27) | |
334 | (FPR15_REGNUM 31) | |
085261c8 AK |
335 | (VR0_REGNUM 16) |
336 | (VR16_REGNUM 38) | |
337 | (VR23_REGNUM 45) | |
338 | (VR24_REGNUM 46) | |
339 | (VR31_REGNUM 53) | |
35dd9a0e AK |
340 | ]) |
341 | ||
ae8e301e AK |
342 | ; Rounding modes for binary floating point numbers |
343 | (define_constants | |
344 | [(BFP_RND_CURRENT 0) | |
345 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
346 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
347 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
348 | (BFP_RND_TOWARD_0 5) | |
349 | (BFP_RND_TOWARD_INF 6) | |
350 | (BFP_RND_TOWARD_MINF 7)]) | |
351 | ||
352 | ; Rounding modes for decimal floating point numbers | |
353 | ; 1-7 were introduced with the floating point extension facility | |
354 | ; available with z196 | |
355 | ; With these rounding modes (1-7) a quantum exception might occur | |
356 | ; which is suppressed for the other modes. | |
357 | (define_constants | |
358 | [(DFP_RND_CURRENT 0) | |
359 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
360 | (DFP_RND_CURRENT_QUANTEXC 2) | |
361 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
362 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
363 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
364 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
365 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
366 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
367 | (DFP_RND_TOWARD_0 9) | |
368 | (DFP_RND_TOWARD_INF 10) | |
369 | (DFP_RND_TOWARD_MINF 11) | |
370 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
371 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
372 | (DFP_RND_AWAY_FROM_0 14) | |
373 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
374 | ||
35dd9a0e AK |
375 | ;; |
376 | ;; PFPO GPR0 argument format | |
377 | ;; | |
378 | ||
379 | (define_constants | |
380 | [ | |
381 | ; PFPO operation type | |
382 | (PFPO_CONVERT 0x1000000) | |
383 | ; PFPO operand types | |
384 | (PFPO_OP_TYPE_SF 0x5) | |
385 | (PFPO_OP_TYPE_DF 0x6) | |
386 | (PFPO_OP_TYPE_TF 0x7) | |
387 | (PFPO_OP_TYPE_SD 0x8) | |
388 | (PFPO_OP_TYPE_DD 0x9) | |
389 | (PFPO_OP_TYPE_TD 0xa) | |
390 | ; Bitposition of operand types | |
391 | (PFPO_OP0_TYPE_SHIFT 16) | |
392 | (PFPO_OP1_TYPE_SHIFT 8) | |
393 | ]) | |
394 | ||
5a3fe9b6 AK |
395 | ; Immediate operands for tbegin and tbeginc |
396 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
397 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 398 | |
29a74354 UW |
399 | ;; Instruction operand type as used in the Principles of Operation. |
400 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 401 | |
29a74354 | 402 | (define_attr "op_type" |
62d3f261 | 403 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" |
b628bd8e | 404 | (const_string "NN")) |
9db1d521 | 405 | |
29a74354 | 406 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 407 | |
077dab3b | 408 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 409 | cs,vs,store,sem,idiv, |
ed0e512a | 410 | imulhi,imulsi,imuldi, |
2cdece44 | 411 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
412 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
413 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 414 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 415 | fmadddf,fmaddsf, |
9381e3f1 WG |
416 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
417 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
418 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
419 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
420 | ftoidfp, other" | |
29a74354 UW |
421 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
422 | (eq_attr "op_type" "SS") (const_string "cs")] | |
423 | (const_string "integer"))) | |
9db1d521 | 424 | |
29a74354 UW |
425 | ;; Another attribute used for scheduling purposes: |
426 | ;; agen: Instruction uses the address generation unit | |
427 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
428 | |
429 | (define_attr "atype" "agen,reg" | |
62d3f261 | 430 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
431 | (const_string "reg") |
432 | (const_string "agen"))) | |
9db1d521 | 433 | |
9381e3f1 WG |
434 | ;; Properties concerning Z10 execution grouping and value forwarding. |
435 | ;; z10_super: instruction is superscalar. | |
436 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
437 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
438 | ;; target register. It can forward this value to a second instruction that reads | |
439 | ;; the same register if that second instruction is issued in the same group. | |
440 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
441 | ;; instruction in the S pipe writes to the register, then the T instruction | |
442 | ;; can immediately read the new value. | |
443 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
444 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
445 | ;; |
446 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
447 | ||
448 | ||
449 | (define_attr "z10prop" "none, | |
450 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
451 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
452 | z10_rec, | |
453 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 454 | z10_c" |
9381e3f1 WG |
455 | (const_string "none")) |
456 | ||
65b1d8ea AK |
457 | ;; Properties concerning Z196 decoding |
458 | ;; z196_alone: must group alone | |
459 | ;; z196_end: ends a group | |
460 | ;; z196_cracked: instruction is cracked or expanded | |
461 | (define_attr "z196prop" "none, | |
462 | z196_alone, z196_ends, | |
463 | z196_cracked" | |
464 | (const_string "none")) | |
9381e3f1 | 465 | |
a9cc3f58 | 466 | (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 467 | |
9db1d521 HP |
468 | ;; Length in bytes. |
469 | ||
470 | (define_attr "length" "" | |
62d3f261 AK |
471 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
472 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 473 | (const_int 6))) |
9db1d521 | 474 | |
29a74354 UW |
475 | |
476 | ;; Processor type. This attribute must exactly match the processor_type | |
477 | ;; enumeration in s390.h. The current machine description does not | |
478 | ;; distinguish between g5 and g6, but there are differences between the two | |
479 | ;; CPUs could in theory be modeled. | |
480 | ||
55ac540c | 481 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13" |
90c6fd8a | 482 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 483 | |
b5e0425c | 484 | (define_attr "cpu_facility" |
285363a1 | 485 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13" |
3af8e996 AK |
486 | (const_string "standard")) |
487 | ||
488 | (define_attr "enabled" "" | |
489 | (cond [(eq_attr "cpu_facility" "standard") | |
490 | (const_int 1) | |
491 | ||
492 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 493 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
494 | (const_int 1) |
495 | ||
496 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 497 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
498 | (const_int 1) |
499 | ||
500 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 501 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
502 | (const_int 1) |
503 | ||
504 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 505 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
506 | (const_int 1) |
507 | ||
508 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 509 | (match_test "TARGET_DFP")) |
93538e8e AK |
510 | (const_int 1) |
511 | ||
b5e0425c AK |
512 | (and (eq_attr "cpu_facility" "cpu_zarch") |
513 | (match_test "TARGET_CPU_ZARCH")) | |
514 | (const_int 1) | |
515 | ||
93538e8e | 516 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 517 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
518 | (const_int 1) |
519 | ||
520 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 521 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
522 | (const_int 1) |
523 | ||
524 | (and (eq_attr "cpu_facility" "zEC12") | |
525 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
526 | (const_int 1) |
527 | ||
285363a1 | 528 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 529 | (match_test "TARGET_VX")) |
bf749919 DV |
530 | (const_int 1) |
531 | ||
532 | (and (eq_attr "cpu_facility" "z13") | |
533 | (match_test "TARGET_Z13")) | |
534 | (const_int 1) | |
535 | ] | |
3af8e996 AK |
536 | (const_int 0))) |
537 | ||
29a74354 UW |
538 | ;; Pipeline description for z900. For lack of anything better, |
539 | ;; this description is also used for the g5 and g6. | |
540 | (include "2064.md") | |
541 | ||
3443392a | 542 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
543 | (include "2084.md") |
544 | ||
9381e3f1 WG |
545 | ;; Pipeline description for z10 |
546 | (include "2097.md") | |
547 | ||
65b1d8ea AK |
548 | ;; Pipeline description for z196 |
549 | (include "2817.md") | |
550 | ||
22ac2c2f AK |
551 | ;; Pipeline description for zEC12 |
552 | (include "2827.md") | |
553 | ||
23902021 AK |
554 | ;; Pipeline description for z13 |
555 | (include "2964.md") | |
556 | ||
0bfc3f69 AS |
557 | ;; Predicates |
558 | (include "predicates.md") | |
559 | ||
cd8dc1f9 WG |
560 | ;; Constraint definitions |
561 | (include "constraints.md") | |
562 | ||
a8ba31f2 EC |
563 | ;; Other includes |
564 | (include "tpf.md") | |
f52c81dd | 565 | |
3abcb3a7 | 566 | ;; Iterators |
f52c81dd | 567 | |
085261c8 AK |
568 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
569 | ||
3abcb3a7 | 570 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 571 | ;; same template. |
f4aa3848 | 572 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 573 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
574 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
575 | (define_mode_iterator BFP [TF DF SF]) | |
576 | (define_mode_iterator DFP [TD DD]) | |
577 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
578 | (define_mode_iterator DSF [DF SF]) | |
579 | (define_mode_iterator SD_SF [SF SD]) | |
580 | (define_mode_iterator DD_DF [DF DD]) | |
581 | (define_mode_iterator TD_TF [TF TD]) | |
582 | ||
3abcb3a7 | 583 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 584 | ;; from the same template. |
9602b6a1 | 585 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 586 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 587 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 588 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 589 | |
3abcb3a7 | 590 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 591 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 592 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 593 | |
78ce265b RH |
594 | ;; These macros refer to the actual word_mode of the configuration. |
595 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
596 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
597 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
598 | ||
6e0d70c9 AK |
599 | ;; Used by the umul pattern to express modes having half the size. |
600 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
601 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
602 | ||
3abcb3a7 | 603 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 604 | ;; the same template. |
3abcb3a7 | 605 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 606 | |
3abcb3a7 | 607 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 608 | ;; same template. |
9602b6a1 | 609 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 610 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 611 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 612 | |
3abcb3a7 | 613 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 614 | ;; the same template. |
3abcb3a7 | 615 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 616 | |
d12a76f3 | 617 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
618 | (define_code_iterator IXOR [ior xor]) |
619 | ||
d12a76f3 AK |
620 | ;; This iterator is used to expand the patterns for the nearest |
621 | ;; integer functions. | |
622 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
623 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
624 | UNSPEC_FPINT_NEARBYINT]) | |
625 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
626 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
627 | (UNSPEC_FPINT_ROUND "round") | |
628 | (UNSPEC_FPINT_CEIL "ceil") | |
629 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
630 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
631 | (UNSPEC_FPINT_BTRUNC "5") | |
632 | (UNSPEC_FPINT_ROUND "1") | |
633 | (UNSPEC_FPINT_CEIL "6") | |
634 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
635 | ||
3abcb3a7 HPN |
636 | ;; This iterator and attribute allow to combine most atomic operations. |
637 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 638 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 639 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 640 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 641 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 642 | |
f4aa3848 | 643 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
644 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
645 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 646 | |
f4aa3848 AK |
647 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
648 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
649 | ;; SDmode. |
650 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 651 | |
609e7e80 | 652 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
653 | ;; Likewise for "<RXe>". |
654 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
655 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
656 | ||
609e7e80 | 657 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 658 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
659 | ;; dfp variants in a single insn definition. |
660 | ||
62d3f261 AK |
661 | ;; These mode attributes are supposed to be used in the `enabled' insn |
662 | ;; attribute to disable certain alternatives for certain modes. | |
663 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
664 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
665 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
666 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
667 | (TD "0") (DD "0") (DD "0") | |
668 | (TI "0") (DI "*") (SI "0")]) | |
f5905b37 | 669 | |
85dae55a AK |
670 | ;; This attribute is used in the operand constraint list |
671 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
672 | ;; TFmode values are represented by a fp register pair. Since the | |
673 | ;; sign bit instructions only handle single source and target fp registers | |
674 | ;; these instructions can only be used for TFmode values if the source and | |
675 | ;; target operand uses the same fp register. | |
676 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
677 | ||
3abcb3a7 | 678 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
679 | ;; within instruction mnemonics. |
680 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
681 | ||
0387c142 WG |
682 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
683 | ;; modes and to an empty string for bfp modes. | |
684 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
685 | ||
1b48c8cc AS |
686 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
687 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
688 | ;; version only operates on one register. | |
689 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
690 | ||
691 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
692 | ;; version only operates on one register. The DImode version needs an additional | |
693 | ;; register for the assembler output. | |
694 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
695 | |
696 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
697 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
698 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
699 | ||
700 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 701 | ;; pattern itself and the corresponding function calls. |
f337b930 | 702 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
703 | |
704 | ;; This attribute handles differences in the instruction 'type' and will result | |
705 | ;; in "RRE" for DImode and "RR" for SImode. | |
706 | (define_mode_attr E [(DI "E") (SI "")]) | |
707 | ||
3298c037 AK |
708 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
709 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
710 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
711 | ||
8006eaa6 AS |
712 | ;; This attribute handles differences in the instruction 'type' and will result |
713 | ;; in "RSE" for TImode and "RS" for DImode. | |
714 | (define_mode_attr TE [(TI "E") (DI "")]) | |
715 | ||
9a91a21f AS |
716 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
717 | ;; and "lcr" in SImode. | |
718 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 719 | |
3298c037 AK |
720 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
721 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
722 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
723 | ;; variant for long displacements. | |
724 | (define_mode_attr y [(DI "g") (SI "y")]) | |
725 | ||
9602b6a1 | 726 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
727 | ;; and "cds" in DImode. |
728 | (define_mode_attr tg [(TI "g") (DI "")]) | |
729 | ||
78ce265b RH |
730 | ;; In TDI templates, a string like "c<d>sg". |
731 | (define_mode_attr td [(TI "d") (DI "")]) | |
732 | ||
2f8f8434 AS |
733 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
734 | ;; and "cfdbr" in SImode. | |
735 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
736 | ||
65b1d8ea AK |
737 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
738 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
739 | ;; 3 operands shift instructions into the existing patterns. | |
740 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
741 | ||
f52c81dd AS |
742 | ;; ICM mask required to load MODE value into the lowest subreg |
743 | ;; of a SImode register. | |
744 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
745 | ||
f6ee577c AS |
746 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
747 | ;; HImode and "llgc" in QImode. | |
748 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
749 | ||
a1aed706 AS |
750 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
751 | ;; in SImode. | |
752 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
753 | ||
609e7e80 AK |
754 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
755 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
756 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
757 | ||
f52c81dd AS |
758 | ;; Maximum unsigned integer that fits in MODE. |
759 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
760 | ||
75ca1b39 RH |
761 | ;; Start and end field computations for RISBG et al. |
762 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
763 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
764 | ||
2542ef05 RH |
765 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
766 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
767 | ;; 64 - bitsize |
768 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
769 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 770 | |
da0dcab1 DV |
771 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
772 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
773 | ||
177bc204 RS |
774 | ;; Allow return and simple_return to be defined from a single template. |
775 | (define_code_iterator ANY_RETURN [return simple_return]) | |
776 | ||
6e5b5de8 AK |
777 | |
778 | ||
779 | ; Condition code modes generated by vector fp comparisons. These will | |
780 | ; be used also in single element mode. | |
781 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
782 | ; Used with VFCMP to expand part of the mnemonic | |
783 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
784 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 785 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 786 | |
191eb16d AK |
787 | ;; Subst pattern definitions |
788 | (include "subst.md") | |
6e5b5de8 | 789 | |
085261c8 AK |
790 | (include "vector.md") |
791 | ||
9db1d521 HP |
792 | ;; |
793 | ;;- Compare instructions. | |
794 | ;; | |
795 | ||
07893d4f | 796 | ; Test-under-Mask instructions |
9db1d521 | 797 | |
07893d4f | 798 | (define_insn "*tmqi_mem" |
ae156f85 | 799 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
800 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
801 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
802 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 803 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 804 | "@ |
fc0ea003 UW |
805 | tm\t%S0,%b1 |
806 | tmy\t%S0,%b1" | |
9381e3f1 | 807 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 808 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 809 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 810 | |
05b9aaaa | 811 | (define_insn "*tmdi_reg" |
ae156f85 | 812 | [(set (reg CC_REGNUM) |
f19a9af7 | 813 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 814 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
815 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
816 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 817 | "TARGET_ZARCH |
3ed99cc9 | 818 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
819 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
820 | "@ | |
821 | tmhh\t%0,%i1 | |
822 | tmhl\t%0,%i1 | |
823 | tmlh\t%0,%i1 | |
824 | tmll\t%0,%i1" | |
9381e3f1 WG |
825 | [(set_attr "op_type" "RI") |
826 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
827 | |
828 | (define_insn "*tmsi_reg" | |
ae156f85 | 829 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
830 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
831 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
832 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 833 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
834 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
835 | "@ | |
836 | tmh\t%0,%i1 | |
837 | tml\t%0,%i1" | |
729e750f WG |
838 | [(set_attr "op_type" "RI") |
839 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 840 | |
f52c81dd | 841 | (define_insn "*tm<mode>_full" |
ae156f85 | 842 | [(set (reg CC_REGNUM) |
f52c81dd AS |
843 | (compare (match_operand:HQI 0 "register_operand" "d") |
844 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 845 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 846 | "tml\t%0,<max_uint>" |
729e750f WG |
847 | [(set_attr "op_type" "RI") |
848 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 849 | |
07893d4f | 850 | |
08a5aaa2 | 851 | ; |
07893d4f | 852 | ; Load-and-Test instructions |
08a5aaa2 AS |
853 | ; |
854 | ||
c0220ea4 | 855 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
856 | |
857 | (define_insn "*tstdi_sign" | |
ae156f85 | 858 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
859 | (compare |
860 | (ashiftrt:DI | |
861 | (ashift:DI | |
3e4be43f | 862 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
863 | (const_int 32)) (const_int 32)) |
864 | (match_operand:DI 1 "const0_operand" ""))) | |
865 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 866 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 867 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
868 | "ltgfr\t%2,%0 |
869 | ltgf\t%2,%0" | |
870 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
871 | (set_attr "cpu_facility" "*,z10") |
872 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 873 | |
43a09b63 | 874 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 875 | (define_insn "*tst<mode>_extimm" |
ec24698e | 876 | [(set (reg CC_REGNUM) |
3e4be43f | 877 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
878 | (match_operand:GPR 1 "const0_operand" ""))) |
879 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 880 | (match_dup 0))] |
08a5aaa2 | 881 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 882 | "@ |
08a5aaa2 AS |
883 | lt<g>r\t%2,%0 |
884 | lt<g>\t%2,%0" | |
9381e3f1 | 885 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 886 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 887 | |
43a09b63 | 888 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 889 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 890 | [(set (reg CC_REGNUM) |
3e4be43f | 891 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
892 | (match_operand:GPR 1 "const0_operand" ""))) |
893 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
894 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 895 | "@ |
08a5aaa2 AS |
896 | lt<g>r\t%0,%0 |
897 | lt<g>\t%2,%0" | |
9381e3f1 | 898 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 899 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 900 | |
07893d4f | 901 | (define_insn "*tstdi" |
ae156f85 | 902 | [(set (reg CC_REGNUM) |
07893d4f UW |
903 | (compare (match_operand:DI 0 "register_operand" "d") |
904 | (match_operand:DI 1 "const0_operand" ""))) | |
905 | (set (match_operand:DI 2 "register_operand" "=d") | |
906 | (match_dup 0))] | |
9602b6a1 | 907 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 908 | "ltgr\t%2,%0" |
9381e3f1 WG |
909 | [(set_attr "op_type" "RRE") |
910 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 911 | |
07893d4f | 912 | (define_insn "*tstsi" |
ae156f85 | 913 | [(set (reg CC_REGNUM) |
d3632d41 | 914 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 915 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 916 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 917 | (match_dup 0))] |
ec24698e | 918 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 919 | "@ |
d40c829f | 920 | ltr\t%2,%0 |
fc0ea003 UW |
921 | icm\t%2,15,%S0 |
922 | icmy\t%2,15,%S0" | |
9381e3f1 | 923 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 924 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 925 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 926 | |
07893d4f | 927 | (define_insn "*tstsi_cconly" |
ae156f85 | 928 | [(set (reg CC_REGNUM) |
d3632d41 | 929 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 930 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 931 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
932 | "s390_match_ccmode(insn, CCSmode)" |
933 | "@ | |
d40c829f | 934 | ltr\t%0,%0 |
fc0ea003 UW |
935 | icm\t%2,15,%S0 |
936 | icmy\t%2,15,%S0" | |
9381e3f1 | 937 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 938 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 939 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 940 | |
08a5aaa2 AS |
941 | (define_insn "*tstdi_cconly_31" |
942 | [(set (reg CC_REGNUM) | |
943 | (compare (match_operand:DI 0 "register_operand" "d") | |
944 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 945 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
946 | "srda\t%0,0" |
947 | [(set_attr "op_type" "RS") | |
948 | (set_attr "atype" "reg")]) | |
949 | ||
43a09b63 | 950 | ; ltr, ltgr |
08a5aaa2 | 951 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 952 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
953 | (compare (match_operand:GPR 0 "register_operand" "d") |
954 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 955 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 956 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
957 | [(set_attr "op_type" "RR<E>") |
958 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 959 | |
c0220ea4 | 960 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 961 | |
f52c81dd | 962 | (define_insn "*tst<mode>CCT" |
ae156f85 | 963 | [(set (reg CC_REGNUM) |
f52c81dd AS |
964 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
965 | (match_operand:HQI 1 "const0_operand" ""))) | |
966 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
967 | (match_dup 0))] |
968 | "s390_match_ccmode(insn, CCTmode)" | |
969 | "@ | |
f52c81dd AS |
970 | icm\t%2,<icm_lo>,%S0 |
971 | icmy\t%2,<icm_lo>,%S0 | |
972 | tml\t%0,<max_uint>" | |
9381e3f1 | 973 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 974 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 975 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
976 | |
977 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 978 | [(set (reg CC_REGNUM) |
d3632d41 | 979 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 980 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 981 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
982 | "s390_match_ccmode(insn, CCTmode)" |
983 | "@ | |
fc0ea003 UW |
984 | icm\t%2,3,%S0 |
985 | icmy\t%2,3,%S0 | |
d40c829f | 986 | tml\t%0,65535" |
9381e3f1 | 987 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 988 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 989 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 990 | |
3af97654 | 991 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 992 | [(set (reg CC_REGNUM) |
d3632d41 | 993 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
994 | (match_operand:QI 1 "const0_operand" "")))] |
995 | "s390_match_ccmode(insn, CCTmode)" | |
996 | "@ | |
fc0ea003 UW |
997 | cli\t%S0,0 |
998 | cliy\t%S0,0 | |
d40c829f | 999 | tml\t%0,255" |
9381e3f1 | 1000 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1001 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1002 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1003 | |
f52c81dd | 1004 | (define_insn "*tst<mode>" |
ae156f85 | 1005 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1006 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1007 | (match_operand:HQI 1 "const0_operand" ""))) | |
1008 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1009 | (match_dup 0))] |
1010 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1011 | "@ |
f52c81dd AS |
1012 | icm\t%2,<icm_lo>,%S0 |
1013 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1014 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1015 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1016 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1017 | |
f52c81dd | 1018 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1019 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1020 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1021 | (match_operand:HQI 1 "const0_operand" ""))) | |
1022 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1023 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1024 | "@ |
f52c81dd AS |
1025 | icm\t%2,<icm_lo>,%S0 |
1026 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1027 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1028 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1029 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1030 | |
9db1d521 | 1031 | |
575f7c2b UW |
1032 | ; Compare (equality) instructions |
1033 | ||
1034 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1035 | [(set (reg CC_REGNUM) |
ec24698e | 1036 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1037 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1038 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1039 | "@ |
1040 | cgr\t%0,%1 | |
f4f41b4e | 1041 | cghi\t%0,%h1 |
ec24698e | 1042 | cgfi\t%0,%1 |
575f7c2b | 1043 | cg\t%0,%1 |
19b63d8e | 1044 | #" |
9381e3f1 WG |
1045 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1046 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1047 | |
1048 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1049 | [(set (reg CC_REGNUM) |
ec24698e UW |
1050 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1051 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1052 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1053 | "@ |
1054 | cr\t%0,%1 | |
f4f41b4e | 1055 | chi\t%0,%h1 |
ec24698e | 1056 | cfi\t%0,%1 |
575f7c2b UW |
1057 | c\t%0,%1 |
1058 | cy\t%0,%1 | |
19b63d8e | 1059 | #" |
9381e3f1 | 1060 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1061 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1062 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1063 | |
07893d4f | 1064 | ; Compare (signed) instructions |
4023fb28 | 1065 | |
07893d4f | 1066 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1067 | [(set (reg CC_REGNUM) |
963fc8d0 | 1068 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1069 | "d,T,b")) |
963fc8d0 | 1070 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1071 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1072 | "@ |
d40c829f | 1073 | cgfr\t%0,%1 |
963fc8d0 AK |
1074 | cgf\t%0,%1 |
1075 | cgfrl\t%0,%1" | |
1076 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1077 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1078 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1079 | |
9381e3f1 WG |
1080 | |
1081 | ||
07893d4f | 1082 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1083 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1084 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1085 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1086 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1087 | "@ |
d40c829f | 1088 | ch\t%0,%1 |
963fc8d0 AK |
1089 | chy\t%0,%1 |
1090 | chrl\t%0,%1" | |
1091 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1092 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea AK |
1093 | (set_attr "type" "*,*,larl") |
1094 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1095 | |
1096 | (define_insn "*cmphi_ccs_z10" | |
1097 | [(set (reg CC_REGNUM) | |
1098 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1099 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1100 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1101 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1102 | [(set_attr "op_type" "SIL") |
1103 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1104 | |
1105 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1106 | [(set (reg CC_REGNUM) | |
3e4be43f | 1107 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1108 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1109 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1110 | "@ | |
1111 | cgh\t%0,%1 | |
1112 | cghrl\t%0,%1" | |
1113 | [(set_attr "op_type" "RXY,RIL") | |
1114 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1115 | |
963fc8d0 | 1116 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1117 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1118 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1119 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1120 | "d,d,Q, d,d,d,d") | |
1121 | (match_operand:GPR 1 "general_operand" | |
1122 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1123 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1124 | "@ |
3298c037 AK |
1125 | c<g>r\t%0,%1 |
1126 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1127 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1128 | c<g>fi\t%0,%1 |
1129 | c<g>\t%0,%1 | |
963fc8d0 AK |
1130 | c<y>\t%0,%1 |
1131 | c<g>rl\t%0,%1" | |
1132 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1133 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 WG |
1134 | (set_attr "type" "*,*,*,*,*,*,larl") |
1135 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1136 | |
07893d4f UW |
1137 | |
1138 | ; Compare (unsigned) instructions | |
9db1d521 | 1139 | |
963fc8d0 AK |
1140 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1141 | [(set (reg CC_REGNUM) | |
1142 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1143 | "larl_operand" "X"))) | |
1144 | (match_operand:SI 0 "register_operand" "d")))] | |
1145 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1146 | "clhrl\t%0,%1" | |
1147 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1148 | (set_attr "type" "larl") |
1149 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1150 | |
1151 | ; clhrl, clghrl | |
1152 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1153 | [(set (reg CC_REGNUM) | |
1154 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1155 | "larl_operand" "X"))) | |
1156 | (match_operand:GPR 0 "register_operand" "d")))] | |
1157 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1158 | "cl<g>hrl\t%0,%1" | |
1159 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1160 | (set_attr "type" "larl") |
1161 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1162 | |
07893d4f | 1163 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1164 | [(set (reg CC_REGNUM) |
963fc8d0 | 1165 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1166 | "d,T,b")) |
1167 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1168 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1169 | "@ |
d40c829f | 1170 | clgfr\t%0,%1 |
963fc8d0 AK |
1171 | clgf\t%0,%1 |
1172 | clgfrl\t%0,%1" | |
1173 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1174 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1175 | (set_attr "type" "*,*,larl") |
1176 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1177 | |
07893d4f | 1178 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1179 | [(set (reg CC_REGNUM) |
963fc8d0 | 1180 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1181 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1182 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1183 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1184 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1185 | "@ |
d40c829f | 1186 | clgr\t%0,%1 |
ec24698e | 1187 | clgfi\t%0,%1 |
963fc8d0 AK |
1188 | clgrl\t%0,%1 |
1189 | clghsi\t%0,%x1 | |
575f7c2b | 1190 | clg\t%0,%1 |
e221ef54 | 1191 | # |
19b63d8e | 1192 | #" |
963fc8d0 AK |
1193 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1194 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1195 | (set_attr "type" "*,*,larl,*,*,*,*") |
1196 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1197 | |
07893d4f | 1198 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1199 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1200 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1201 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1202 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1203 | "@ |
d40c829f | 1204 | clr\t%0,%1 |
ec24698e | 1205 | clfi\t%0,%o1 |
963fc8d0 AK |
1206 | clrl\t%0,%1 |
1207 | clfhsi\t%0,%x1 | |
d40c829f | 1208 | cl\t%0,%1 |
575f7c2b | 1209 | cly\t%0,%1 |
e221ef54 | 1210 | # |
19b63d8e | 1211 | #" |
963fc8d0 | 1212 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1213 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 WG |
1214 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1215 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1216 | |
07893d4f | 1217 | (define_insn "*cmphi_ccu" |
ae156f85 | 1218 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1219 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1220 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1221 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1222 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1223 | "@ |
fc0ea003 UW |
1224 | clm\t%0,3,%S1 |
1225 | clmy\t%0,3,%S1 | |
963fc8d0 | 1226 | clhhsi\t%0,%1 |
e221ef54 | 1227 | # |
19b63d8e | 1228 | #" |
963fc8d0 | 1229 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1230 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1231 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1232 | |
1233 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1234 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1235 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1236 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1237 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1238 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1239 | "@ |
fc0ea003 UW |
1240 | clm\t%0,1,%S1 |
1241 | clmy\t%0,1,%S1 | |
1242 | cli\t%S0,%b1 | |
1243 | cliy\t%S0,%b1 | |
e221ef54 | 1244 | # |
19b63d8e | 1245 | #" |
9381e3f1 | 1246 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1247 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1248 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1249 | |
1250 | ||
19b63d8e UW |
1251 | ; Block compare (CLC) instruction patterns. |
1252 | ||
1253 | (define_insn "*clc" | |
ae156f85 | 1254 | [(set (reg CC_REGNUM) |
d4f52f0e | 1255 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1256 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1257 | (use (match_operand 2 "const_int_operand" "n"))] | |
1258 | "s390_match_ccmode (insn, CCUmode) | |
1259 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1260 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1261 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1262 | |
1263 | (define_split | |
ae156f85 | 1264 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1265 | (compare (match_operand 0 "memory_operand" "") |
1266 | (match_operand 1 "memory_operand" "")))] | |
1267 | "reload_completed | |
1268 | && s390_match_ccmode (insn, CCUmode) | |
1269 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1270 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1271 | [(parallel | |
1272 | [(set (match_dup 0) (match_dup 1)) | |
1273 | (use (match_dup 2))])] | |
1274 | { | |
1275 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1276 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1277 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1278 | ||
1279 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1280 | operands[0], operands[1]); | |
1281 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1282 | }) | |
1283 | ||
1284 | ||
609e7e80 | 1285 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1286 | |
e325aba2 AK |
1287 | |
1288 | ; load and test instructions turn SNaN into QNaN what is not | |
1289 | ; acceptable if the target will be used afterwards. On the other hand | |
1290 | ; they are quite convenient for implementing comparisons with 0.0. So | |
1291 | ; try to enable them via splitter if the value isn't needed anymore. | |
1292 | ||
609e7e80 | 1293 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1294 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1295 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1296 | (compare (match_operand:FP 0 "register_operand" "f") |
1297 | (match_operand:FP 1 "const0_operand" ""))) | |
1298 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1299 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1300 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1301 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1302 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1303 | |
e325aba2 AK |
1304 | (define_split |
1305 | [(set (match_operand 0 "cc_reg_operand") | |
1306 | (compare (match_operand:FP 1 "register_operand") | |
1307 | (match_operand:FP 2 "const0_operand")))] | |
1308 | "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])" | |
1309 | [(parallel | |
1310 | [(set (match_dup 0) (match_dup 3)) | |
1311 | (clobber (match_dup 1))])] | |
1312 | { | |
1313 | /* s390_match_ccmode requires the compare to have the same CC mode | |
1314 | as the CC destination register. */ | |
1315 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]), | |
1316 | operands[1], operands[2]); | |
1317 | }) | |
1318 | ||
1319 | ||
77c585ca | 1320 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcdb |
f5905b37 | 1321 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1322 | [(set (reg CC_REGNUM) |
77c585ca AK |
1323 | (compare (match_operand:FP 0 "register_operand" "f,f,v") |
1324 | (match_operand:FP 1 "general_operand" "f,R,v")))] | |
142cd70f | 1325 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1326 | "@ |
609e7e80 | 1327 | c<xde><bt>r\t%0,%1 |
77c585ca AK |
1328 | c<xde>b\t%0,%1 |
1329 | wfcdb\t%0,%1" | |
1330 | [(set_attr "op_type" "RRE,RXE,VRR") | |
1331 | (set_attr "cpu_facility" "*,*,vx") | |
1332 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) | |
1333 | ||
963fc8d0 AK |
1334 | |
1335 | ; Compare and Branch instructions | |
1336 | ||
1337 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1338 | ; The following instructions do a complementary access of their second |
1339 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1340 | (define_insn "*cmp_and_br_signed_<mode>" |
1341 | [(set (pc) | |
1342 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1343 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1344 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1345 | (label_ref (match_operand 3 "" "")) | |
1346 | (pc))) | |
1347 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1348 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1349 | { |
1350 | if (get_attr_length (insn) == 6) | |
1351 | return which_alternative ? | |
1352 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1353 | else | |
1354 | return which_alternative ? | |
1355 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1356 | } | |
1357 | [(set_attr "op_type" "RIE") | |
1358 | (set_attr "type" "branch") | |
e3cba5e5 | 1359 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1360 | (set (attr "length") |
1361 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1362 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1363 | ; 10 byte for cgr/jg | |
1364 | ||
1365 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1366 | ; The following instructions do a complementary access of their second |
1367 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1368 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1369 | [(set (pc) | |
1370 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1371 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1372 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1373 | (label_ref (match_operand 3 "" "")) | |
1374 | (pc))) | |
1375 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1376 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1377 | { |
1378 | if (get_attr_length (insn) == 6) | |
1379 | return which_alternative ? | |
1380 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1381 | else | |
1382 | return which_alternative ? | |
1383 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1384 | } | |
1385 | [(set_attr "op_type" "RIE") | |
1386 | (set_attr "type" "branch") | |
e3cba5e5 | 1387 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1388 | (set (attr "length") |
1389 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1390 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1391 | ; 10 byte for clgr/jg | |
1392 | ||
b0f86a7e AK |
1393 | ; And now the same two patterns as above but with a negated CC mask. |
1394 | ||
1395 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1396 | ; The following instructions do a complementary access of their second | |
1397 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1398 | (define_insn "*icmp_and_br_signed_<mode>" | |
1399 | [(set (pc) | |
1400 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1401 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1402 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1403 | (pc) | |
1404 | (label_ref (match_operand 3 "" "")))) | |
1405 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1406 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1407 | { |
1408 | if (get_attr_length (insn) == 6) | |
1409 | return which_alternative ? | |
1410 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1411 | else | |
1412 | return which_alternative ? | |
1413 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1414 | } | |
1415 | [(set_attr "op_type" "RIE") | |
1416 | (set_attr "type" "branch") | |
1417 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1418 | (set (attr "length") | |
1419 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1420 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1421 | ; 10 byte for cgr/jg | |
1422 | ||
1423 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1424 | ; The following instructions do a complementary access of their second | |
1425 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1426 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1427 | [(set (pc) | |
1428 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1429 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1430 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1431 | (pc) | |
1432 | (label_ref (match_operand 3 "" "")))) | |
1433 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1434 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1435 | { |
1436 | if (get_attr_length (insn) == 6) | |
1437 | return which_alternative ? | |
1438 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1439 | else | |
1440 | return which_alternative ? | |
1441 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1442 | } | |
1443 | [(set_attr "op_type" "RIE") | |
1444 | (set_attr "type" "branch") | |
1445 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1446 | (set (attr "length") | |
1447 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1448 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1449 | ; 10 byte for clgr/jg | |
1450 | ||
9db1d521 HP |
1451 | ;; |
1452 | ;;- Move instructions. | |
1453 | ;; | |
1454 | ||
1455 | ; | |
1456 | ; movti instruction pattern(s). | |
1457 | ; | |
1458 | ||
085261c8 AK |
1459 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1460 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1461 | (define_insn "movti" |
3e4be43f UW |
1462 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o") |
1463 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dPT,d"))] | |
9602b6a1 | 1464 | "TARGET_ZARCH" |
4023fb28 | 1465 | "@ |
fc0ea003 UW |
1466 | lmg\t%0,%N0,%S1 |
1467 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1468 | vlr\t%v0,%v1 |
1469 | vzero\t%v0 | |
1470 | vone\t%v0 | |
1471 | vlvgp\t%v0,%1,%N1 | |
1472 | # | |
1473 | vl\t%v0,%1 | |
1474 | vst\t%v1,%0 | |
4023fb28 | 1475 | # |
19b63d8e | 1476 | #" |
085261c8 AK |
1477 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1478 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
285363a1 | 1479 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")]) |
4023fb28 UW |
1480 | |
1481 | (define_split | |
1482 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1483 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1484 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1485 | && !s_operand (operands[0], TImode) |
1486 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1487 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1488 | [(set (match_dup 2) (match_dup 4)) |
1489 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1490 | { |
dc65c307 UW |
1491 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1492 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1493 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1494 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1495 | }) | |
1496 | ||
1497 | (define_split | |
1498 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1499 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1500 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1501 | && !s_operand (operands[0], TImode) |
1502 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1503 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1504 | [(set (match_dup 2) (match_dup 4)) | |
1505 | (set (match_dup 3) (match_dup 5))] | |
1506 | { | |
1507 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1508 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1509 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1510 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1511 | }) | |
4023fb28 | 1512 | |
085261c8 AK |
1513 | ; Use part of the TImode target reg to perform the address |
1514 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1515 | ; this splitter is not necessary. | |
4023fb28 UW |
1516 | (define_split |
1517 | [(set (match_operand:TI 0 "register_operand" "") | |
1518 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1519 | "TARGET_ZARCH && reload_completed |
085261c8 | 1520 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1521 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1522 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1523 | { |
1524 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1525 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1526 | s390_load_address (addr, XEXP (operands[1], 0)); |
1527 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1528 | }) |
1529 | ||
833cd70a | 1530 | |
085261c8 AK |
1531 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1532 | ; For the higher order bits we do simply a DImode move while the | |
1533 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1534 | (define_split | |
1535 | [(set (match_operand:TI 0 "register_operand" "") | |
1536 | (match_operand:TI 1 "register_operand" ""))] | |
1537 | "TARGET_VX && reload_completed | |
1538 | && GENERAL_REG_P (operands[0]) | |
1539 | && VECTOR_REG_P (operands[1])" | |
1540 | [(set (match_dup 2) (match_dup 4)) | |
1541 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1542 | UNSPEC_VEC_EXTRACT))] | |
1543 | { | |
1544 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1545 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1546 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1547 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1548 | }) | |
1549 | ||
833cd70a AK |
1550 | ; |
1551 | ; Patterns used for secondary reloads | |
1552 | ; | |
1553 | ||
963fc8d0 AK |
1554 | ; z10 provides move instructions accepting larl memory operands. |
1555 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1556 | ; These patterns are also used for unaligned SI and DI accesses. | |
1557 | ||
085261c8 AK |
1558 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1559 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1560 | (match_operand:ALL 1 "register_operand" "=d") | |
1561 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1562 | "TARGET_Z10" |
1563 | { | |
1564 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1565 | DONE; | |
1566 | }) | |
1567 | ||
085261c8 AK |
1568 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1569 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1570 | (match_operand:ALL 1 "memory_operand" "") | |
1571 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1572 | "TARGET_Z10" |
1573 | { | |
1574 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1575 | DONE; | |
1576 | }) | |
1577 | ||
1578 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1579 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1580 | (match_operand:P 1 "larl_operand" "") | |
1581 | (match_operand:P 2 "register_operand" "=a")])] | |
1582 | "TARGET_Z10" | |
1583 | { | |
1584 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1585 | DONE; | |
1586 | }) | |
1587 | ||
833cd70a AK |
1588 | ; Handles loading a PLUS (load address) expression |
1589 | ||
1590 | (define_expand "reload<mode>_plus" | |
1591 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1592 | (match_operand:P 1 "s390_plus_operand" "") | |
1593 | (match_operand:P 2 "register_operand" "=&a")])] | |
1594 | "" | |
1595 | { | |
1596 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1597 | DONE; | |
1598 | }) | |
1599 | ||
085261c8 AK |
1600 | ; Not all the indirect memory access instructions support the full |
1601 | ; format (long disp + index + base). So whenever a move from/to such | |
1602 | ; an address is required and the instruction cannot deal with it we do | |
1603 | ; a load address into a scratch register first and use this as the new | |
1604 | ; base register. | |
1605 | ; This in particular is used for: | |
1606 | ; - non-offsetable memory accesses for multiword moves | |
1607 | ; - full vector reg moves with long displacements | |
833cd70a | 1608 | |
085261c8 | 1609 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1610 | [(parallel [(match_operand 0 "register_operand" "") |
1611 | (match_operand 1 "" "") | |
1612 | (match_operand:P 2 "register_operand" "=&a")])] | |
1613 | "" | |
1614 | { | |
1615 | gcc_assert (MEM_P (operands[1])); | |
1616 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1617 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1618 | emit_move_insn (operands[0], operands[1]); | |
1619 | DONE; | |
1620 | }) | |
1621 | ||
085261c8 | 1622 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1623 | [(parallel [(match_operand 0 "" "") |
1624 | (match_operand 1 "register_operand" "") | |
1625 | (match_operand:P 2 "register_operand" "=&a")])] | |
1626 | "" | |
dc65c307 | 1627 | { |
9c3c3dcc | 1628 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1629 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1630 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1631 | emit_move_insn (operands[0], operands[1]); | |
1632 | DONE; | |
1633 | }) | |
9db1d521 | 1634 | |
1f9e1fc6 AK |
1635 | (define_expand "reload<mode>_PIC_addr" |
1636 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1637 | (match_operand 1 "larl_operand" "") | |
1638 | (match_operand:P 2 "register_operand" "=a")])] | |
1639 | "" | |
1640 | { | |
0a2aaacc KG |
1641 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1642 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1643 | }) |
1644 | ||
9db1d521 HP |
1645 | ; |
1646 | ; movdi instruction pattern(s). | |
1647 | ; | |
1648 | ||
9db1d521 HP |
1649 | (define_expand "movdi" |
1650 | [(set (match_operand:DI 0 "general_operand" "") | |
1651 | (match_operand:DI 1 "general_operand" ""))] | |
1652 | "" | |
9db1d521 | 1653 | { |
fd3cd001 | 1654 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1655 | if (TARGET_64BIT |
1656 | && (SYMBOLIC_CONST (operands[1]) | |
1657 | || (GET_CODE (operands[1]) == PLUS | |
1658 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1659 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1660 | emit_symbolic_move (operands); |
10bbf137 | 1661 | }) |
9db1d521 | 1662 | |
4023fb28 UW |
1663 | (define_insn "*movdi_larl" |
1664 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1665 | (match_operand:DI 1 "larl_operand" "X"))] | |
1666 | "TARGET_64BIT | |
8e509cf9 | 1667 | && !FP_REG_P (operands[0])" |
d40c829f | 1668 | "larl\t%0,%1" |
4023fb28 | 1669 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1670 | (set_attr "type" "larl") |
1671 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1672 | |
3af8e996 | 1673 | (define_insn "*movdi_64" |
85dae55a | 1674 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1675 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R") |
85dae55a | 1676 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1677 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))] |
9602b6a1 | 1678 | "TARGET_ZARCH" |
85dae55a AK |
1679 | "@ |
1680 | lghi\t%0,%h1 | |
1681 | llihh\t%0,%i1 | |
1682 | llihl\t%0,%i1 | |
1683 | llilh\t%0,%i1 | |
1684 | llill\t%0,%i1 | |
1685 | lgfi\t%0,%1 | |
1686 | llihf\t%0,%k1 | |
1687 | llilf\t%0,%k1 | |
1688 | ldgr\t%0,%1 | |
1689 | lgdr\t%0,%1 | |
1690 | lay\t%0,%a1 | |
963fc8d0 | 1691 | lgrl\t%0,%1 |
85dae55a AK |
1692 | lgr\t%0,%1 |
1693 | lg\t%0,%1 | |
1694 | stg\t%1,%0 | |
1695 | ldr\t%0,%1 | |
1696 | ld\t%0,%1 | |
1697 | ldy\t%0,%1 | |
1698 | std\t%1,%0 | |
1699 | stdy\t%1,%0 | |
963fc8d0 AK |
1700 | stgrl\t%1,%0 |
1701 | mvghi\t%0,%1 | |
85dae55a AK |
1702 | # |
1703 | # | |
1704 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1705 | lam\t%0,%N0,%S1 |
1706 | vleig\t%v0,%h1,0 | |
1707 | vlr\t%v0,%v1 | |
1708 | vlvgg\t%v0,%1,0 | |
1709 | vlgvg\t%0,%v1,0 | |
1710 | vleg\t%v0,%1,0 | |
1711 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1712 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1713 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1714 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1715 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1716 | *,*,*,*,*,*,*") | |
3af8e996 | 1717 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1718 | z10,*,*,*,*,*,longdisp,*,longdisp, |
285363a1 | 1719 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
1720 | (set_attr "z10prop" "z10_fwd_A1, |
1721 | z10_fwd_E1, | |
1722 | z10_fwd_E1, | |
1723 | z10_fwd_E1, | |
1724 | z10_fwd_E1, | |
1725 | z10_fwd_A1, | |
1726 | z10_fwd_E1, | |
1727 | z10_fwd_E1, | |
1728 | *, | |
1729 | *, | |
1730 | z10_fwd_A1, | |
1731 | z10_fwd_A3, | |
1732 | z10_fr_E1, | |
1733 | z10_fwd_A3, | |
1734 | z10_rec, | |
1735 | *, | |
1736 | *, | |
1737 | *, | |
1738 | *, | |
1739 | *, | |
1740 | z10_rec, | |
1741 | z10_super, | |
1742 | *, | |
1743 | *, | |
1744 | *, | |
085261c8 | 1745 | *,*,*,*,*,*,*") |
9381e3f1 | 1746 | ]) |
c5aa1d12 UW |
1747 | |
1748 | (define_split | |
1749 | [(set (match_operand:DI 0 "register_operand" "") | |
1750 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1751 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1752 | [(set (match_dup 2) (match_dup 3)) |
1753 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1754 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1755 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1756 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1757 | ||
1758 | (define_split | |
1759 | [(set (match_operand:DI 0 "register_operand" "") | |
1760 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1761 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1762 | && dead_or_set_p (insn, operands[1])" |
1763 | [(set (match_dup 3) (match_dup 2)) | |
1764 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1765 | (set (match_dup 4) (match_dup 2))] | |
1766 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1767 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1768 | ||
1769 | (define_split | |
1770 | [(set (match_operand:DI 0 "register_operand" "") | |
1771 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1772 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1773 | && !dead_or_set_p (insn, operands[1])" |
1774 | [(set (match_dup 3) (match_dup 2)) | |
1775 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1776 | (set (match_dup 4) (match_dup 2)) | |
1777 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1778 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1779 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1780 | |
1781 | (define_insn "*movdi_31" | |
963fc8d0 | 1782 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1783 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1784 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1785 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1786 | "!TARGET_ZARCH" |
4023fb28 | 1787 | "@ |
fc0ea003 | 1788 | lm\t%0,%N0,%S1 |
c4d50129 | 1789 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1790 | stm\t%1,%N1,%S0 |
c4d50129 | 1791 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1792 | # |
1793 | # | |
d40c829f UW |
1794 | ldr\t%0,%1 |
1795 | ld\t%0,%1 | |
1796 | ldy\t%0,%1 | |
1797 | std\t%1,%0 | |
1798 | stdy\t%1,%0 | |
19b63d8e | 1799 | #" |
f2dc2f86 AK |
1800 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1801 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1802 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1803 | |
1804 | ; For a load from a symbol ref we can use one of the target registers | |
1805 | ; together with larl to load the address. | |
1806 | (define_split | |
1807 | [(set (match_operand:DI 0 "register_operand" "") | |
1808 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1809 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1810 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1811 | [(set (match_dup 2) (match_dup 3)) | |
1812 | (set (match_dup 0) (match_dup 1))] | |
1813 | { | |
1814 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1815 | operands[3] = XEXP (operands[1], 0); | |
1816 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1817 | }) | |
4023fb28 UW |
1818 | |
1819 | (define_split | |
1820 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1821 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1822 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1823 | && !s_operand (operands[0], DImode) |
1824 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1825 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1826 | [(set (match_dup 2) (match_dup 4)) |
1827 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1828 | { |
dc65c307 UW |
1829 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1830 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1831 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1832 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1833 | }) | |
1834 | ||
1835 | (define_split | |
1836 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1837 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1838 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1839 | && !s_operand (operands[0], DImode) |
1840 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1841 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1842 | [(set (match_dup 2) (match_dup 4)) | |
1843 | (set (match_dup 3) (match_dup 5))] | |
1844 | { | |
1845 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1846 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1847 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1848 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1849 | }) | |
9db1d521 | 1850 | |
4023fb28 UW |
1851 | (define_split |
1852 | [(set (match_operand:DI 0 "register_operand" "") | |
1853 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1854 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1855 | && !FP_REG_P (operands[0]) |
4023fb28 | 1856 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1857 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1858 | { |
1859 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1860 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1861 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1862 | }) |
1863 | ||
84817c5d UW |
1864 | (define_peephole2 |
1865 | [(set (match_operand:DI 0 "register_operand" "") | |
1866 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1867 | "TARGET_ZARCH |
84817c5d UW |
1868 | && !FP_REG_P (operands[0]) |
1869 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1870 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1871 | && get_pool_mode (operands[1]) == DImode | |
1872 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1873 | [(set (match_dup 0) (match_dup 2))] | |
1874 | "operands[2] = get_pool_constant (operands[1]);") | |
1875 | ||
7bdff56f UW |
1876 | (define_insn "*la_64" |
1877 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1878 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1879 | "TARGET_64BIT" |
1880 | "@ | |
1881 | la\t%0,%a1 | |
1882 | lay\t%0,%a1" | |
1883 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1884 | (set_attr "type" "la") |
3e4be43f | 1885 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1886 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1887 | |
1888 | (define_peephole2 | |
1889 | [(parallel | |
1890 | [(set (match_operand:DI 0 "register_operand" "") | |
1891 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1892 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1893 | "TARGET_64BIT |
e1d5ee28 | 1894 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1895 | [(set (match_dup 0) (match_dup 1))] |
1896 | "") | |
1897 | ||
1898 | (define_peephole2 | |
1899 | [(set (match_operand:DI 0 "register_operand" "") | |
1900 | (match_operand:DI 1 "register_operand" "")) | |
1901 | (parallel | |
1902 | [(set (match_dup 0) | |
1903 | (plus:DI (match_dup 0) | |
1904 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1905 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1906 | "TARGET_64BIT |
1907 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1908 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1909 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1910 | "") | |
1911 | ||
9db1d521 HP |
1912 | ; |
1913 | ; movsi instruction pattern(s). | |
1914 | ; | |
1915 | ||
9db1d521 HP |
1916 | (define_expand "movsi" |
1917 | [(set (match_operand:SI 0 "general_operand" "") | |
1918 | (match_operand:SI 1 "general_operand" ""))] | |
1919 | "" | |
9db1d521 | 1920 | { |
fd3cd001 | 1921 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1922 | if (!TARGET_64BIT |
1923 | && (SYMBOLIC_CONST (operands[1]) | |
1924 | || (GET_CODE (operands[1]) == PLUS | |
1925 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1926 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1927 | emit_symbolic_move (operands); |
10bbf137 | 1928 | }) |
9db1d521 | 1929 | |
9e8327e3 UW |
1930 | (define_insn "*movsi_larl" |
1931 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1932 | (match_operand:SI 1 "larl_operand" "X"))] | |
1933 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1934 | && !FP_REG_P (operands[0])" | |
1935 | "larl\t%0,%1" | |
1936 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1937 | (set_attr "type" "larl") |
729e750f | 1938 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1939 | |
f19a9af7 | 1940 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1941 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 1942 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 1943 | (match_operand:SI 1 "general_operand" |
3e4be43f | 1944 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 1945 | "TARGET_ZARCH" |
9db1d521 | 1946 | "@ |
f19a9af7 AK |
1947 | lhi\t%0,%h1 |
1948 | llilh\t%0,%i1 | |
1949 | llill\t%0,%i1 | |
ec24698e | 1950 | iilf\t%0,%o1 |
f19a9af7 | 1951 | lay\t%0,%a1 |
963fc8d0 | 1952 | lrl\t%0,%1 |
d40c829f UW |
1953 | lr\t%0,%1 |
1954 | l\t%0,%1 | |
1955 | ly\t%0,%1 | |
1956 | st\t%1,%0 | |
1957 | sty\t%1,%0 | |
ae1c6198 | 1958 | ldr\t%0,%1 |
d40c829f | 1959 | ler\t%0,%1 |
085261c8 | 1960 | lde\t%0,%1 |
d40c829f UW |
1961 | le\t%0,%1 |
1962 | ley\t%0,%1 | |
1963 | ste\t%1,%0 | |
1964 | stey\t%1,%0 | |
c5aa1d12 UW |
1965 | ear\t%0,%1 |
1966 | sar\t%0,%1 | |
1967 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1968 | strl\t%1,%0 |
1969 | mvhi\t%0,%1 | |
085261c8 AK |
1970 | lam\t%0,%0,%S1 |
1971 | vleif\t%v0,%h1,0 | |
1972 | vlr\t%v0,%v1 | |
1973 | vlvgf\t%v0,%1,0 | |
1974 | vlgvf\t%0,%v1,0 | |
1975 | vlef\t%v0,%1,0 | |
1976 | vstef\t%v1,%0,0" | |
963fc8d0 | 1977 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 1978 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
1979 | (set_attr "type" "*, |
1980 | *, | |
1981 | *, | |
1982 | *, | |
1983 | la, | |
1984 | larl, | |
1985 | lr, | |
1986 | load, | |
1987 | load, | |
1988 | store, | |
1989 | store, | |
1990 | floadsf, | |
1991 | floadsf, | |
1992 | floadsf, | |
085261c8 AK |
1993 | floadsf, |
1994 | floadsf, | |
9381e3f1 WG |
1995 | fstoresf, |
1996 | fstoresf, | |
1997 | *, | |
1998 | *, | |
1999 | *, | |
2000 | larl, | |
2001 | *, | |
085261c8 | 2002 | *,*,*,*,*,*,*") |
963fc8d0 | 2003 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2004 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2005 | (set_attr "z10prop" "z10_fwd_A1, |
2006 | z10_fwd_E1, | |
2007 | z10_fwd_E1, | |
2008 | z10_fwd_A1, | |
2009 | z10_fwd_A1, | |
2010 | z10_fwd_A3, | |
2011 | z10_fr_E1, | |
2012 | z10_fwd_A3, | |
2013 | z10_fwd_A3, | |
729e750f | 2014 | z10_rec, |
9381e3f1 WG |
2015 | z10_rec, |
2016 | *, | |
2017 | *, | |
2018 | *, | |
2019 | *, | |
2020 | *, | |
085261c8 AK |
2021 | *, |
2022 | *, | |
9381e3f1 WG |
2023 | z10_super_E1, |
2024 | z10_super, | |
2025 | *, | |
2026 | z10_rec, | |
2027 | z10_super, | |
085261c8 | 2028 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
2029 | |
2030 | (define_insn "*movsi_esa" | |
085261c8 AK |
2031 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2032 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2033 | "!TARGET_ZARCH" |
2034 | "@ | |
2035 | lhi\t%0,%h1 | |
2036 | lr\t%0,%1 | |
2037 | l\t%0,%1 | |
2038 | st\t%1,%0 | |
ae1c6198 | 2039 | ldr\t%0,%1 |
f19a9af7 | 2040 | ler\t%0,%1 |
085261c8 | 2041 | lde\t%0,%1 |
f19a9af7 AK |
2042 | le\t%0,%1 |
2043 | ste\t%1,%0 | |
c5aa1d12 UW |
2044 | ear\t%0,%1 |
2045 | sar\t%0,%1 | |
2046 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2047 | lam\t%0,%0,%S1" |
ae1c6198 | 2048 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2049 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2050 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2051 | z10_super,*,*") | |
285363a1 | 2052 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2053 | ]) |
9db1d521 | 2054 | |
84817c5d UW |
2055 | (define_peephole2 |
2056 | [(set (match_operand:SI 0 "register_operand" "") | |
2057 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2058 | "!FP_REG_P (operands[0]) | |
2059 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2060 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2061 | && get_pool_mode (operands[1]) == SImode | |
2062 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2063 | [(set (match_dup 0) (match_dup 2))] | |
2064 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2065 | |
7bdff56f UW |
2066 | (define_insn "*la_31" |
2067 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2068 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2069 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2070 | "@ | |
2071 | la\t%0,%a1 | |
2072 | lay\t%0,%a1" | |
2073 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2074 | (set_attr "type" "la") |
3e4be43f | 2075 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2076 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2077 | |
2078 | (define_peephole2 | |
2079 | [(parallel | |
2080 | [(set (match_operand:SI 0 "register_operand" "") | |
2081 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2082 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2083 | "!TARGET_64BIT |
e1d5ee28 | 2084 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2085 | [(set (match_dup 0) (match_dup 1))] |
2086 | "") | |
2087 | ||
2088 | (define_peephole2 | |
2089 | [(set (match_operand:SI 0 "register_operand" "") | |
2090 | (match_operand:SI 1 "register_operand" "")) | |
2091 | (parallel | |
2092 | [(set (match_dup 0) | |
2093 | (plus:SI (match_dup 0) | |
2094 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2095 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2096 | "!TARGET_64BIT |
2097 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2098 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2099 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2100 | "") | |
2101 | ||
2102 | (define_insn "*la_31_and" | |
2103 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2104 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2105 | (const_int 2147483647)))] |
2106 | "!TARGET_64BIT" | |
2107 | "@ | |
2108 | la\t%0,%a1 | |
2109 | lay\t%0,%a1" | |
2110 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2111 | (set_attr "type" "la") |
3e4be43f | 2112 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2113 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2114 | |
2115 | (define_insn_and_split "*la_31_and_cc" | |
2116 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2117 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2118 | (const_int 2147483647))) | |
ae156f85 | 2119 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2120 | "!TARGET_64BIT" |
2121 | "#" | |
2122 | "&& reload_completed" | |
2123 | [(set (match_dup 0) | |
2124 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2125 | "" | |
2126 | [(set_attr "op_type" "RX") | |
2127 | (set_attr "type" "la")]) | |
2128 | ||
2129 | (define_insn "force_la_31" | |
2130 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2131 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2132 | (use (const_int 0))] |
2133 | "!TARGET_64BIT" | |
2134 | "@ | |
2135 | la\t%0,%a1 | |
2136 | lay\t%0,%a1" | |
2137 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2138 | (set_attr "type" "la") |
3e4be43f | 2139 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2140 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2141 | |
9db1d521 HP |
2142 | ; |
2143 | ; movhi instruction pattern(s). | |
2144 | ; | |
2145 | ||
02ed3c5e UW |
2146 | (define_expand "movhi" |
2147 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2148 | (match_operand:HI 1 "general_operand" ""))] | |
2149 | "" | |
2150 | { | |
2f7e5a0d | 2151 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2152 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2153 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2154 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2155 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2156 | { |
2157 | rtx tmp = gen_reg_rtx (SImode); | |
2158 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2159 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2160 | operands[1] = gen_lowpart (HImode, tmp); |
2161 | } | |
2162 | }) | |
2163 | ||
2164 | (define_insn "*movhi" | |
3e4be43f UW |
2165 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2166 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2167 | "" |
2168 | "@ | |
d40c829f UW |
2169 | lr\t%0,%1 |
2170 | lhi\t%0,%h1 | |
2171 | lh\t%0,%1 | |
2172 | lhy\t%0,%1 | |
963fc8d0 | 2173 | lhrl\t%0,%1 |
d40c829f UW |
2174 | sth\t%1,%0 |
2175 | sthy\t%1,%0 | |
963fc8d0 | 2176 | sthrl\t%1,%0 |
085261c8 AK |
2177 | mvhhi\t%0,%1 |
2178 | vleih\t%v0,%h1,0 | |
2179 | vlr\t%v0,%v1 | |
2180 | vlvgh\t%v0,%1,0 | |
2181 | vlgvh\t%0,%v1,0 | |
2182 | vleh\t%v0,%1,0 | |
2183 | vsteh\t%v1,%0,0" | |
2184 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2185 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2186 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2187 | (set_attr "z10prop" "z10_fr_E1, |
2188 | z10_fwd_A1, | |
2189 | z10_super_E1, | |
2190 | z10_super_E1, | |
2191 | z10_super_E1, | |
729e750f | 2192 | z10_rec, |
9381e3f1 WG |
2193 | z10_rec, |
2194 | z10_rec, | |
085261c8 | 2195 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2196 | |
84817c5d UW |
2197 | (define_peephole2 |
2198 | [(set (match_operand:HI 0 "register_operand" "") | |
2199 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2200 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2201 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2202 | && get_pool_mode (operands[1]) == HImode | |
2203 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2204 | [(set (match_dup 0) (match_dup 2))] | |
2205 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2206 | |
9db1d521 HP |
2207 | ; |
2208 | ; movqi instruction pattern(s). | |
2209 | ; | |
2210 | ||
02ed3c5e UW |
2211 | (define_expand "movqi" |
2212 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2213 | (match_operand:QI 1 "general_operand" ""))] | |
2214 | "" | |
2215 | { | |
c19ec8f9 | 2216 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2217 | is just as fast as a QImode load. */ |
b3a13419 | 2218 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2219 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2220 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2221 | { |
9602b6a1 AK |
2222 | rtx tmp = gen_reg_rtx (DImode); |
2223 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2224 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2225 | operands[1] = gen_lowpart (QImode, tmp); |
2226 | } | |
2227 | }) | |
4023fb28 | 2228 | |
02ed3c5e | 2229 | (define_insn "*movqi" |
3e4be43f UW |
2230 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2231 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2232 | "" |
2233 | "@ | |
d40c829f UW |
2234 | lr\t%0,%1 |
2235 | lhi\t%0,%b1 | |
2236 | ic\t%0,%1 | |
2237 | icy\t%0,%1 | |
2238 | stc\t%1,%0 | |
2239 | stcy\t%1,%0 | |
fc0ea003 | 2240 | mvi\t%S0,%b1 |
0a88561f | 2241 | mviy\t%S0,%b1 |
085261c8 AK |
2242 | # |
2243 | vleib\t%v0,%b1,0 | |
2244 | vlr\t%v0,%v1 | |
2245 | vlvgb\t%v0,%1,0 | |
2246 | vlgvb\t%0,%v1,0 | |
2247 | vleb\t%v0,%1,0 | |
2248 | vsteb\t%v1,%0,0" | |
2249 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2250 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2251 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2252 | (set_attr "z10prop" "z10_fr_E1, |
2253 | z10_fwd_A1, | |
2254 | z10_super_E1, | |
2255 | z10_super_E1, | |
729e750f | 2256 | z10_rec, |
9381e3f1 WG |
2257 | z10_rec, |
2258 | z10_super, | |
0a88561f | 2259 | z10_super, |
085261c8 | 2260 | *,*,*,*,*,*,*")]) |
9db1d521 | 2261 | |
84817c5d UW |
2262 | (define_peephole2 |
2263 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2264 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2265 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2266 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2267 | && get_pool_mode (operands[1]) == QImode | |
2268 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2269 | [(set (match_dup 0) (match_dup 2))] | |
2270 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2271 | |
9db1d521 | 2272 | ; |
05b9aaaa | 2273 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2274 | ; |
2275 | ||
2276 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2277 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2278 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2279 | "" |
d3632d41 | 2280 | "@ |
d40c829f UW |
2281 | ic\t%0,%1 |
2282 | icy\t%0,%1" | |
9381e3f1 | 2283 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2284 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2285 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2286 | |
2287 | ; | |
2288 | ; movstricthi instruction pattern(s). | |
2289 | ; | |
2290 | ||
2291 | (define_insn "*movstricthi" | |
d3632d41 | 2292 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2293 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2294 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2295 | "" |
d3632d41 | 2296 | "@ |
fc0ea003 UW |
2297 | icm\t%0,3,%S1 |
2298 | icmy\t%0,3,%S1" | |
9381e3f1 | 2299 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2300 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2301 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2302 | |
2303 | ; | |
2304 | ; movstrictsi instruction pattern(s). | |
2305 | ; | |
2306 | ||
05b9aaaa | 2307 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2308 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2309 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2310 | "TARGET_ZARCH" |
9db1d521 | 2311 | "@ |
d40c829f UW |
2312 | lr\t%0,%1 |
2313 | l\t%0,%1 | |
c5aa1d12 UW |
2314 | ly\t%0,%1 |
2315 | ear\t%0,%1" | |
2316 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2317 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2318 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2319 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2320 | |
f61a2c7d | 2321 | ; |
609e7e80 | 2322 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2323 | ; |
2324 | ||
609e7e80 AK |
2325 | (define_expand "mov<mode>" |
2326 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2327 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2328 | "" |
2329 | "") | |
2330 | ||
609e7e80 | 2331 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2332 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2333 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2334 | "TARGET_ZARCH" |
f61a2c7d | 2335 | "@ |
65b1d8ea | 2336 | lzxr\t%0 |
f61a2c7d AK |
2337 | lxr\t%0,%1 |
2338 | # | |
2339 | # | |
2340 | lmg\t%0,%N0,%S1 | |
2341 | stmg\t%1,%N1,%S0 | |
2342 | # | |
f61a2c7d | 2343 | #" |
65b1d8ea AK |
2344 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2345 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2346 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2347 | |
609e7e80 | 2348 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2349 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2350 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2351 | "!TARGET_ZARCH" |
f61a2c7d | 2352 | "@ |
65b1d8ea | 2353 | lzxr\t%0 |
f61a2c7d AK |
2354 | lxr\t%0,%1 |
2355 | # | |
f61a2c7d | 2356 | #" |
65b1d8ea AK |
2357 | [(set_attr "op_type" "RRE,RRE,*,*") |
2358 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2359 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2360 | |
2361 | ; TFmode in GPRs splitters | |
2362 | ||
2363 | (define_split | |
609e7e80 AK |
2364 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2365 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2366 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2367 | && !s_operand (operands[0], <MODE>mode) |
2368 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2369 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2370 | [(set (match_dup 2) (match_dup 4)) |
2371 | (set (match_dup 3) (match_dup 5))] | |
2372 | { | |
609e7e80 AK |
2373 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2374 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2375 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2376 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2377 | }) |
2378 | ||
2379 | (define_split | |
609e7e80 AK |
2380 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2381 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2382 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2383 | && !s_operand (operands[0], <MODE>mode) |
2384 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2385 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2386 | [(set (match_dup 2) (match_dup 4)) |
2387 | (set (match_dup 3) (match_dup 5))] | |
2388 | { | |
609e7e80 AK |
2389 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2390 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2391 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2392 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2393 | }) |
2394 | ||
2395 | (define_split | |
609e7e80 AK |
2396 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2397 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2398 | "TARGET_ZARCH && reload_completed |
085261c8 | 2399 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2400 | && !s_operand (operands[1], VOIDmode)" |
2401 | [(set (match_dup 0) (match_dup 1))] | |
2402 | { | |
609e7e80 | 2403 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2404 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2405 | s390_load_address (addr, XEXP (operands[1], 0)); |
2406 | operands[1] = replace_equiv_address (operands[1], addr); | |
2407 | }) | |
2408 | ||
7b6baae1 | 2409 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2410 | |
2411 | (define_split | |
609e7e80 AK |
2412 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2413 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2414 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2415 | && FP_REG_P (operands[0])" |
2416 | [(set (match_dup 2) (match_dup 4)) | |
2417 | (set (match_dup 3) (match_dup 5))] | |
2418 | { | |
609e7e80 AK |
2419 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2420 | <MODE>mode, 0); | |
2421 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2422 | <MODE>mode, 8); | |
2423 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2424 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2425 | }) |
2426 | ||
2427 | (define_split | |
609e7e80 AK |
2428 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2429 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2430 | "reload_completed && offsettable_memref_p (operands[0]) |
2431 | && FP_REG_P (operands[1])" | |
2432 | [(set (match_dup 2) (match_dup 4)) | |
2433 | (set (match_dup 3) (match_dup 5))] | |
2434 | { | |
609e7e80 AK |
2435 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2436 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2437 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2438 | <MODE>mode, 0); | |
2439 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2440 | <MODE>mode, 8); | |
f61a2c7d AK |
2441 | }) |
2442 | ||
9db1d521 | 2443 | ; |
609e7e80 | 2444 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2445 | ; |
2446 | ||
609e7e80 AK |
2447 | (define_expand "mov<mode>" |
2448 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2449 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2450 | "" |
13c025c1 | 2451 | "") |
9db1d521 | 2452 | |
609e7e80 AK |
2453 | (define_insn "*mov<mode>_64dfp" |
2454 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2455 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2456 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2457 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2458 | "TARGET_DFP" |
85dae55a | 2459 | "@ |
65b1d8ea | 2460 | lzdr\t%0 |
85dae55a AK |
2461 | ldr\t%0,%1 |
2462 | ldgr\t%0,%1 | |
2463 | lgdr\t%0,%1 | |
2464 | ld\t%0,%1 | |
2465 | ldy\t%0,%1 | |
2466 | std\t%1,%0 | |
2467 | stdy\t%1,%0 | |
45e5214c | 2468 | lghi\t%0,0 |
85dae55a | 2469 | lgr\t%0,%1 |
085261c8 | 2470 | lgrl\t%0,%1 |
85dae55a | 2471 | lg\t%0,%1 |
085261c8 AK |
2472 | stgrl\t%1,%0 |
2473 | stg\t%1,%0 | |
2474 | vlr\t%v0,%v1 | |
590961cf | 2475 | vleig\t%v0,0,0 |
085261c8 AK |
2476 | vlvgg\t%v0,%1,0 |
2477 | vlgvg\t%0,%v1,0 | |
2478 | vleg\t%0,%1,0 | |
2479 | vsteg\t%1,%0,0" | |
590961cf | 2480 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2481 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2482 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2483 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
2484 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")]) | |
85dae55a | 2485 | |
609e7e80 | 2486 | (define_insn "*mov<mode>_64" |
590961cf AK |
2487 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2488 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2489 | "TARGET_ZARCH" |
9db1d521 | 2490 | "@ |
65b1d8ea | 2491 | lzdr\t%0 |
d40c829f UW |
2492 | ldr\t%0,%1 |
2493 | ld\t%0,%1 | |
2494 | ldy\t%0,%1 | |
2495 | std\t%1,%0 | |
2496 | stdy\t%1,%0 | |
45e5214c | 2497 | lghi\t%0,0 |
d40c829f | 2498 | lgr\t%0,%1 |
085261c8 | 2499 | lgrl\t%0,%1 |
d40c829f | 2500 | lg\t%0,%1 |
085261c8 | 2501 | stgrl\t%1,%0 |
590961cf AK |
2502 | stg\t%1,%0" |
2503 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2504 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2505 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2506 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2507 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")]) | |
609e7e80 AK |
2508 | |
2509 | (define_insn "*mov<mode>_31" | |
2510 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2511 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2512 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2513 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2514 | "!TARGET_ZARCH" |
9db1d521 | 2515 | "@ |
65b1d8ea | 2516 | lzdr\t%0 |
d40c829f UW |
2517 | ldr\t%0,%1 |
2518 | ld\t%0,%1 | |
2519 | ldy\t%0,%1 | |
2520 | std\t%1,%0 | |
2521 | stdy\t%1,%0 | |
fc0ea003 | 2522 | lm\t%0,%N0,%S1 |
c4d50129 | 2523 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2524 | stm\t%1,%N1,%S0 |
c4d50129 | 2525 | stmy\t%1,%N1,%S0 |
4023fb28 | 2526 | # |
19b63d8e | 2527 | #" |
65b1d8ea AK |
2528 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2529 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2530 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2531 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2532 | |
2533 | (define_split | |
609e7e80 AK |
2534 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2535 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2536 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2537 | && !s_operand (operands[0], <MODE>mode) |
2538 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2539 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2540 | [(set (match_dup 2) (match_dup 4)) |
2541 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2542 | { |
609e7e80 AK |
2543 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2544 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2545 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2546 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2547 | }) |
2548 | ||
2549 | (define_split | |
609e7e80 AK |
2550 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2551 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2552 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2553 | && !s_operand (operands[0], <MODE>mode) |
2554 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2555 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2556 | [(set (match_dup 2) (match_dup 4)) |
2557 | (set (match_dup 3) (match_dup 5))] | |
2558 | { | |
609e7e80 AK |
2559 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2560 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2561 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2562 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2563 | }) |
9db1d521 | 2564 | |
4023fb28 | 2565 | (define_split |
609e7e80 AK |
2566 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2567 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2568 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2569 | && !FP_REG_P (operands[0]) |
4023fb28 | 2570 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2571 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2572 | { |
609e7e80 | 2573 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2574 | s390_load_address (addr, XEXP (operands[1], 0)); |
2575 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2576 | }) |
2577 | ||
9db1d521 | 2578 | ; |
609e7e80 | 2579 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2580 | ; |
2581 | ||
609e7e80 AK |
2582 | (define_insn "mov<mode>" |
2583 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2584 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2585 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2586 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2587 | "" |
9db1d521 | 2588 | "@ |
65b1d8ea | 2589 | lzer\t%0 |
ae1c6198 | 2590 | ldr\t%0,%1 |
d40c829f | 2591 | ler\t%0,%1 |
085261c8 | 2592 | lde\t%0,%1 |
d40c829f UW |
2593 | le\t%0,%1 |
2594 | ley\t%0,%1 | |
2595 | ste\t%1,%0 | |
2596 | stey\t%1,%0 | |
45e5214c | 2597 | lhi\t%0,0 |
d40c829f | 2598 | lr\t%0,%1 |
085261c8 | 2599 | lrl\t%0,%1 |
d40c829f UW |
2600 | l\t%0,%1 |
2601 | ly\t%0,%1 | |
085261c8 | 2602 | strl\t%1,%0 |
d40c829f | 2603 | st\t%1,%0 |
085261c8 AK |
2604 | sty\t%1,%0 |
2605 | vlr\t%v0,%v1 | |
298f4647 | 2606 | vleif\t%v0,0,0 |
085261c8 AK |
2607 | vlvgf\t%v0,%1,0 |
2608 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2609 | vlef\t%0,%1,0 |
2610 | vstef\t%1,%0,0" | |
ae1c6198 | 2611 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2612 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2613 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2614 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
285363a1 | 2615 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")]) |
4023fb28 | 2616 | |
9dc62c00 AK |
2617 | ; |
2618 | ; movcc instruction pattern | |
2619 | ; | |
2620 | ||
2621 | (define_insn "movcc" | |
2622 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2623 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2624 | "" |
2625 | "@ | |
2626 | lr\t%0,%1 | |
2627 | tmh\t%1,12288 | |
2628 | ipm\t%0 | |
a71f0749 DV |
2629 | l\t%0,%1 |
2630 | ly\t%0,%1 | |
2631 | st\t%1,%0 | |
2632 | sty\t%1,%0" | |
8dd3b235 | 2633 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2634 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2635 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2636 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2637 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2638 | |
19b63d8e UW |
2639 | ; |
2640 | ; Block move (MVC) patterns. | |
2641 | ; | |
2642 | ||
2643 | (define_insn "*mvc" | |
2644 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2645 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2646 | (use (match_operand 2 "const_int_operand" "n"))] | |
2647 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2648 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2649 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2650 | |
0a88561f AK |
2651 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2652 | ; order to have it implemented with mvc. | |
2653 | ||
2654 | (define_split | |
2655 | [(set (match_operand:QI 0 "memory_operand" "") | |
2656 | (match_operand:QI 1 "memory_operand" ""))] | |
2657 | "reload_completed" | |
2658 | [(parallel | |
2659 | [(set (match_dup 0) (match_dup 1)) | |
2660 | (use (const_int 1))])] | |
2661 | { | |
2662 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2663 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2664 | }) | |
2665 | ||
2666 | ||
19b63d8e UW |
2667 | (define_peephole2 |
2668 | [(parallel | |
2669 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2670 | (match_operand:BLK 1 "memory_operand" "")) | |
2671 | (use (match_operand 2 "const_int_operand" ""))]) | |
2672 | (parallel | |
2673 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2674 | (match_operand:BLK 4 "memory_operand" "")) | |
2675 | (use (match_operand 5 "const_int_operand" ""))])] | |
2676 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2677 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2678 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2679 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2680 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2681 | [(parallel | |
2682 | [(set (match_dup 6) (match_dup 7)) | |
2683 | (use (match_dup 8))])] | |
2684 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2685 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2686 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2687 | ||
2688 | ||
9db1d521 HP |
2689 | ; |
2690 | ; load_multiple pattern(s). | |
2691 | ; | |
22ea6b4f UW |
2692 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2693 | ; we currently support load_multiple/store_multiple only after reload. | |
2694 | ; | |
9db1d521 HP |
2695 | |
2696 | (define_expand "load_multiple" | |
2697 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2698 | (match_operand 1 "" "")) | |
2699 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2700 | "reload_completed" |
9db1d521 | 2701 | { |
ef4bddc2 | 2702 | machine_mode mode; |
9db1d521 HP |
2703 | int regno; |
2704 | int count; | |
2705 | rtx from; | |
4023fb28 | 2706 | int i, off; |
9db1d521 HP |
2707 | |
2708 | /* Support only loading a constant number of fixed-point registers from | |
2709 | memory and only bother with this if more than two */ | |
2710 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2711 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2712 | || INTVAL (operands[2]) > 16 |
2713 | || GET_CODE (operands[1]) != MEM | |
2714 | || GET_CODE (operands[0]) != REG | |
2715 | || REGNO (operands[0]) >= 16) | |
2716 | FAIL; | |
2717 | ||
2718 | count = INTVAL (operands[2]); | |
2719 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2720 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2721 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2722 | FAIL; |
9db1d521 HP |
2723 | |
2724 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2725 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2726 | { |
2727 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2728 | { | |
2729 | from = XEXP (operands[1], 0); | |
2730 | off = 0; | |
2731 | } | |
2732 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2733 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2734 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2735 | { | |
2736 | from = XEXP (XEXP (operands[1], 0), 0); | |
2737 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2738 | } | |
2739 | else | |
2740 | FAIL; | |
4023fb28 UW |
2741 | } |
2742 | else | |
2743 | { | |
2744 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2745 | off = 0; | |
2746 | } | |
9db1d521 HP |
2747 | |
2748 | for (i = 0; i < count; i++) | |
2749 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2750 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2751 | change_address (operands[1], mode, |
0a81f074 RS |
2752 | plus_constant (Pmode, from, |
2753 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2754 | }) |
9db1d521 HP |
2755 | |
2756 | (define_insn "*load_multiple_di" | |
2757 | [(match_parallel 0 "load_multiple_operation" | |
2758 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2759 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2760 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2761 | { |
2762 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2763 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2764 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2765 | } |
d3632d41 | 2766 | [(set_attr "op_type" "RSY") |
4023fb28 | 2767 | (set_attr "type" "lm")]) |
9db1d521 HP |
2768 | |
2769 | (define_insn "*load_multiple_si" | |
2770 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2771 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2772 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2773 | "reload_completed" |
9db1d521 HP |
2774 | { |
2775 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2776 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2777 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2778 | } |
d3632d41 | 2779 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2780 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2781 | (set_attr "type" "lm")]) |
9db1d521 HP |
2782 | |
2783 | ; | |
c7453384 | 2784 | ; store multiple pattern(s). |
9db1d521 HP |
2785 | ; |
2786 | ||
2787 | (define_expand "store_multiple" | |
2788 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2789 | (match_operand 1 "" "")) | |
2790 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2791 | "reload_completed" |
9db1d521 | 2792 | { |
ef4bddc2 | 2793 | machine_mode mode; |
9db1d521 HP |
2794 | int regno; |
2795 | int count; | |
2796 | rtx to; | |
4023fb28 | 2797 | int i, off; |
9db1d521 HP |
2798 | |
2799 | /* Support only storing a constant number of fixed-point registers to | |
2800 | memory and only bother with this if more than two. */ | |
2801 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2802 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2803 | || INTVAL (operands[2]) > 16 |
2804 | || GET_CODE (operands[0]) != MEM | |
2805 | || GET_CODE (operands[1]) != REG | |
2806 | || REGNO (operands[1]) >= 16) | |
2807 | FAIL; | |
2808 | ||
2809 | count = INTVAL (operands[2]); | |
2810 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2811 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2812 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2813 | FAIL; |
9db1d521 HP |
2814 | |
2815 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2816 | |
b3a13419 | 2817 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2818 | { |
2819 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2820 | { | |
2821 | to = XEXP (operands[0], 0); | |
2822 | off = 0; | |
2823 | } | |
2824 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2825 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2826 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2827 | { | |
2828 | to = XEXP (XEXP (operands[0], 0), 0); | |
2829 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2830 | } | |
2831 | else | |
2832 | FAIL; | |
4023fb28 | 2833 | } |
c7453384 | 2834 | else |
4023fb28 UW |
2835 | { |
2836 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2837 | off = 0; | |
2838 | } | |
9db1d521 HP |
2839 | |
2840 | for (i = 0; i < count; i++) | |
2841 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2842 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2843 | plus_constant (Pmode, to, |
2844 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2845 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2846 | }) |
9db1d521 HP |
2847 | |
2848 | (define_insn "*store_multiple_di" | |
2849 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2850 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2851 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2852 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2853 | { |
2854 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2855 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2856 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2857 | } |
d3632d41 | 2858 | [(set_attr "op_type" "RSY") |
4023fb28 | 2859 | (set_attr "type" "stm")]) |
9db1d521 HP |
2860 | |
2861 | ||
2862 | (define_insn "*store_multiple_si" | |
2863 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2864 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2865 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2866 | "reload_completed" |
9db1d521 HP |
2867 | { |
2868 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2869 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2870 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2871 | } |
d3632d41 | 2872 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2873 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2874 | (set_attr "type" "stm")]) |
9db1d521 HP |
2875 | |
2876 | ;; | |
2877 | ;; String instructions. | |
2878 | ;; | |
2879 | ||
963fc8d0 | 2880 | (define_insn "*execute_rl" |
2771c2f9 | 2881 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2882 | [(unspec [(match_operand 1 "register_operand" "a") |
2883 | (match_operand 2 "" "") | |
2884 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2885 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2886 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2887 | "exrl\t%1,%3" | |
2888 | [(set_attr "op_type" "RIL") | |
2889 | (set_attr "type" "cs")]) | |
2890 | ||
9bb86f41 | 2891 | (define_insn "*execute" |
2771c2f9 | 2892 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2893 | [(unspec [(match_operand 1 "register_operand" "a") |
2894 | (match_operand:BLK 2 "memory_operand" "R") | |
2895 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2896 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2897 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2898 | "ex\t%1,%2" | |
29a74354 UW |
2899 | [(set_attr "op_type" "RX") |
2900 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2901 | |
2902 | ||
91d39d71 UW |
2903 | ; |
2904 | ; strlenM instruction pattern(s). | |
2905 | ; | |
2906 | ||
9db2f16d | 2907 | (define_expand "strlen<mode>" |
085261c8 AK |
2908 | [(match_operand:P 0 "register_operand" "") ; result |
2909 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2910 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2911 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2912 | "" | |
2913 | { | |
2914 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2915 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2916 | operands[2], operands[3])); | |
2917 | else | |
2918 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2919 | ||
2920 | DONE; | |
2921 | }) | |
2922 | ||
2923 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 2924 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2925 | (parallel |
91d39d71 | 2926 | [(set (match_dup 4) |
9db2f16d | 2927 | (unspec:P [(const_int 0) |
91d39d71 | 2928 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2929 | (reg:SI 0) |
91d39d71 | 2930 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2931 | (clobber (scratch:P)) |
ae156f85 | 2932 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2933 | (parallel |
9db2f16d AS |
2934 | [(set (match_operand:P 0 "register_operand" "") |
2935 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2936 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2937 | "" |
91d39d71 | 2938 | { |
9db2f16d AS |
2939 | operands[4] = gen_reg_rtx (Pmode); |
2940 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2941 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2942 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2943 | }) | |
2944 | ||
9db2f16d AS |
2945 | (define_insn "*strlen<mode>" |
2946 | [(set (match_operand:P 0 "register_operand" "=a") | |
2947 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2948 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2949 | (reg:SI 0) |
91d39d71 | 2950 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2951 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2952 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2953 | "" |
91d39d71 | 2954 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2955 | [(set_attr "length" "8") |
2956 | (set_attr "type" "vs")]) | |
91d39d71 | 2957 | |
ccbdc0d4 AS |
2958 | ; |
2959 | ; cmpstrM instruction pattern(s). | |
2960 | ; | |
2961 | ||
2962 | (define_expand "cmpstrsi" | |
2963 | [(set (reg:SI 0) (const_int 0)) | |
2964 | (parallel | |
2965 | [(clobber (match_operand 3 "" "")) | |
2966 | (clobber (match_dup 4)) | |
2967 | (set (reg:CCU CC_REGNUM) | |
2968 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2969 | (match_operand:BLK 2 "memory_operand" ""))) | |
2970 | (use (reg:SI 0))]) | |
2971 | (parallel | |
2972 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2973 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
2974 | (clobber (reg:CC CC_REGNUM))])] |
2975 | "" | |
2976 | { | |
2977 | /* As the result of CMPINT is inverted compared to what we need, | |
2978 | we have to swap the operands. */ | |
2979 | rtx op1 = operands[2]; | |
2980 | rtx op2 = operands[1]; | |
2981 | rtx addr1 = gen_reg_rtx (Pmode); | |
2982 | rtx addr2 = gen_reg_rtx (Pmode); | |
2983 | ||
2984 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2985 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2986 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2987 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2988 | operands[3] = addr1; | |
2989 | operands[4] = addr2; | |
2990 | }) | |
2991 | ||
2992 | (define_insn "*cmpstr<mode>" | |
2993 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2994 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2995 | (set (reg:CCU CC_REGNUM) | |
2996 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2997 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2998 | (use (reg:SI 0))] | |
2999 | "" | |
3000 | "clst\t%0,%1\;jo\t.-4" | |
3001 | [(set_attr "length" "8") | |
3002 | (set_attr "type" "vs")]) | |
9381e3f1 | 3003 | |
742090fc AS |
3004 | ; |
3005 | ; movstr instruction pattern. | |
3006 | ; | |
3007 | ||
3008 | (define_expand "movstr" | |
4a7dec25 DV |
3009 | [(match_operand 0 "register_operand" "") |
3010 | (match_operand 1 "memory_operand" "") | |
3011 | (match_operand 2 "memory_operand" "")] | |
3012 | "" | |
3013 | { | |
3014 | if (TARGET_64BIT) | |
3015 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3016 | else | |
3017 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3018 | DONE; | |
3019 | }) | |
3020 | ||
3021 | (define_expand "movstr<P:mode>" | |
742090fc | 3022 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3023 | (parallel |
742090fc AS |
3024 | [(clobber (match_dup 3)) |
3025 | (set (match_operand:BLK 1 "memory_operand" "") | |
3026 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3027 | (set (match_operand:P 0 "register_operand" "") |
3028 | (unspec:P [(match_dup 1) | |
742090fc AS |
3029 | (match_dup 2) |
3030 | (reg:SI 0)] UNSPEC_MVST)) | |
3031 | (clobber (reg:CC CC_REGNUM))])] | |
3032 | "" | |
3033 | { | |
859a4c0e AK |
3034 | rtx addr1, addr2; |
3035 | ||
3036 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3037 | { | |
3038 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3039 | DONE; | |
3040 | } | |
3041 | ||
3042 | addr1 = gen_reg_rtx (Pmode); | |
3043 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3044 | |
3045 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3046 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3047 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3048 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3049 | operands[3] = addr2; | |
3050 | }) | |
3051 | ||
3052 | (define_insn "*movstr" | |
3053 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3054 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3055 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3056 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3057 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3058 | (mem:BLK (match_dup 3)) |
3059 | (reg:SI 0)] UNSPEC_MVST)) | |
3060 | (clobber (reg:CC CC_REGNUM))] | |
3061 | "" | |
3062 | "mvst\t%1,%2\;jo\t.-4" | |
3063 | [(set_attr "length" "8") | |
3064 | (set_attr "type" "vs")]) | |
9381e3f1 | 3065 | |
742090fc | 3066 | |
9db1d521 | 3067 | ; |
70128ad9 | 3068 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3069 | ; |
3070 | ||
9db2f16d | 3071 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3072 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3073 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3074 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3075 | (match_operand 3 "" "")] |
3076 | "" | |
367d32f3 AK |
3077 | { |
3078 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3079 | DONE; | |
3080 | else | |
3081 | FAIL; | |
3082 | }) | |
9db1d521 | 3083 | |
ecbe845e UW |
3084 | ; Move a block that is up to 256 bytes in length. |
3085 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3086 | |
70128ad9 | 3087 | (define_expand "movmem_short" |
b9404c99 UW |
3088 | [(parallel |
3089 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3090 | (match_operand:BLK 1 "memory_operand" "")) | |
3091 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3092 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3093 | (clobber (match_dup 3))])] |
3094 | "" | |
3095 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3096 | |
70128ad9 | 3097 | (define_insn "*movmem_short" |
963fc8d0 AK |
3098 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3099 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3100 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3101 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3102 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3103 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3104 | "#" |
963fc8d0 | 3105 | [(set_attr "type" "cs") |
b5e0425c | 3106 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3107 | |
9bb86f41 UW |
3108 | (define_split |
3109 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3110 | (match_operand:BLK 1 "memory_operand" "")) | |
3111 | (use (match_operand 2 "const_int_operand" "")) | |
3112 | (use (match_operand 3 "immediate_operand" "")) | |
3113 | (clobber (scratch))] | |
3114 | "reload_completed" | |
3115 | [(parallel | |
3116 | [(set (match_dup 0) (match_dup 1)) | |
3117 | (use (match_dup 2))])] | |
3118 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3119 | |
9bb86f41 UW |
3120 | (define_split |
3121 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3122 | (match_operand:BLK 1 "memory_operand" "")) | |
3123 | (use (match_operand 2 "register_operand" "")) | |
3124 | (use (match_operand 3 "memory_operand" "")) | |
3125 | (clobber (scratch))] | |
3126 | "reload_completed" | |
3127 | [(parallel | |
3128 | [(unspec [(match_dup 2) (match_dup 3) | |
3129 | (const_int 0)] UNSPEC_EXECUTE) | |
3130 | (set (match_dup 0) (match_dup 1)) | |
3131 | (use (const_int 1))])] | |
3132 | "") | |
3133 | ||
963fc8d0 AK |
3134 | (define_split |
3135 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3136 | (match_operand:BLK 1 "memory_operand" "")) | |
3137 | (use (match_operand 2 "register_operand" "")) | |
3138 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3139 | (clobber (scratch))] | |
3140 | "TARGET_Z10 && reload_completed" | |
3141 | [(parallel | |
3142 | [(unspec [(match_dup 2) (const_int 0) | |
3143 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3144 | (set (match_dup 0) (match_dup 1)) | |
3145 | (use (const_int 1))])] | |
3146 | "operands[3] = gen_label_rtx ();") | |
3147 | ||
9bb86f41 UW |
3148 | (define_split |
3149 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3150 | (match_operand:BLK 1 "memory_operand" "")) | |
3151 | (use (match_operand 2 "register_operand" "")) | |
3152 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3153 | (clobber (match_operand 3 "register_operand" ""))] | |
3154 | "reload_completed && TARGET_CPU_ZARCH" | |
3155 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3156 | (parallel | |
9381e3f1 | 3157 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3158 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3159 | (set (match_dup 0) (match_dup 1)) | |
3160 | (use (const_int 1))])] | |
3161 | "operands[4] = gen_label_rtx ();") | |
3162 | ||
a41c6c53 | 3163 | ; Move a block of arbitrary length. |
9db1d521 | 3164 | |
70128ad9 | 3165 | (define_expand "movmem_long" |
b9404c99 UW |
3166 | [(parallel |
3167 | [(clobber (match_dup 2)) | |
3168 | (clobber (match_dup 3)) | |
3169 | (set (match_operand:BLK 0 "memory_operand" "") | |
3170 | (match_operand:BLK 1 "memory_operand" "")) | |
3171 | (use (match_operand 2 "general_operand" "")) | |
3172 | (use (match_dup 3)) | |
ae156f85 | 3173 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3174 | "" |
3175 | { | |
ef4bddc2 RS |
3176 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3177 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3178 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3179 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3180 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3181 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3182 | rtx len0 = gen_lowpart (Pmode, reg0); |
3183 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3184 | ||
c41c1387 | 3185 | emit_clobber (reg0); |
b9404c99 UW |
3186 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3187 | emit_move_insn (len0, operands[2]); | |
3188 | ||
c41c1387 | 3189 | emit_clobber (reg1); |
b9404c99 UW |
3190 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3191 | emit_move_insn (len1, operands[2]); | |
3192 | ||
3193 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3194 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3195 | operands[2] = reg0; | |
3196 | operands[3] = reg1; | |
3197 | }) | |
3198 | ||
a1aed706 AS |
3199 | (define_insn "*movmem_long" |
3200 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3201 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3202 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3203 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3204 | (use (match_dup 2)) |
3205 | (use (match_dup 3)) | |
ae156f85 | 3206 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3207 | "TARGET_64BIT || !TARGET_ZARCH" |
3208 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3209 | [(set_attr "length" "8") | |
3210 | (set_attr "type" "vs")]) | |
3211 | ||
3212 | (define_insn "*movmem_long_31z" | |
3213 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3214 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3215 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3216 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3217 | (use (match_dup 2)) | |
3218 | (use (match_dup 3)) | |
3219 | (clobber (reg:CC CC_REGNUM))] | |
3220 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3221 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3222 | [(set_attr "length" "8") |
3223 | (set_attr "type" "vs")]) | |
9db1d521 | 3224 | |
638e37c2 WG |
3225 | |
3226 | ; | |
3227 | ; Test data class. | |
3228 | ; | |
3229 | ||
0f67fa83 WG |
3230 | (define_expand "signbit<mode>2" |
3231 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3232 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3233 | (match_dup 2)] | |
0f67fa83 WG |
3234 | UNSPEC_TDC_INSN)) |
3235 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3236 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3237 | "TARGET_HARD_FLOAT" |
3238 | { | |
3239 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3240 | }) | |
3241 | ||
638e37c2 WG |
3242 | (define_expand "isinf<mode>2" |
3243 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3244 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3245 | (match_dup 2)] | |
638e37c2 WG |
3246 | UNSPEC_TDC_INSN)) |
3247 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3248 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3249 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3250 | { |
3251 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3252 | }) | |
3253 | ||
085261c8 AK |
3254 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3255 | ; instruction will be issued by reload. The constraint of operand 1 | |
3256 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3257 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3258 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3259 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3260 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3261 | UNSPEC_CC_TO_INT))] | |
3262 | "operands != NULL" | |
3263 | "#" | |
3264 | "reload_completed" | |
3265 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3266 | ||
638e37c2 WG |
3267 | ; This insn is used to generate all variants of the Test Data Class |
3268 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3269 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3270 | ; specifying the required test(s). |
638e37c2 | 3271 | ; |
be5de7a1 | 3272 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3273 | (define_insn "*TDC_insn_<mode>" |
3274 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3275 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3276 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3277 | "TARGET_HARD_FLOAT" |
0387c142 | 3278 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3279 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3280 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3281 | |
638e37c2 WG |
3282 | |
3283 | ||
9db1d521 | 3284 | ; |
57e84f18 | 3285 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3286 | ; |
3287 | ||
57e84f18 | 3288 | (define_expand "setmem<mode>" |
a41c6c53 | 3289 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3290 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3291 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3292 | (match_operand 3 "" "")] |
a41c6c53 | 3293 | "" |
6d057022 | 3294 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3295 | |
a41c6c53 | 3296 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3297 | ; The block length is taken as (operands[1] % 256) + 1. |
3298 | ||
70128ad9 | 3299 | (define_expand "clrmem_short" |
b9404c99 UW |
3300 | [(parallel |
3301 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3302 | (const_int 0)) | |
3303 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3304 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3305 | (clobber (match_dup 2)) |
ae156f85 | 3306 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3307 | "" |
3308 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3309 | |
70128ad9 | 3310 | (define_insn "*clrmem_short" |
963fc8d0 | 3311 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3312 | (const_int 0)) |
963fc8d0 AK |
3313 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3314 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3315 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3316 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3317 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3318 | "#" |
963fc8d0 | 3319 | [(set_attr "type" "cs") |
b5e0425c | 3320 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3321 | |
3322 | (define_split | |
3323 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3324 | (const_int 0)) | |
3325 | (use (match_operand 1 "const_int_operand" "")) | |
3326 | (use (match_operand 2 "immediate_operand" "")) | |
3327 | (clobber (scratch)) | |
ae156f85 | 3328 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3329 | "reload_completed" |
3330 | [(parallel | |
3331 | [(set (match_dup 0) (const_int 0)) | |
3332 | (use (match_dup 1)) | |
ae156f85 | 3333 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3334 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3335 | |
9bb86f41 UW |
3336 | (define_split |
3337 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3338 | (const_int 0)) | |
3339 | (use (match_operand 1 "register_operand" "")) | |
3340 | (use (match_operand 2 "memory_operand" "")) | |
3341 | (clobber (scratch)) | |
ae156f85 | 3342 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3343 | "reload_completed" |
3344 | [(parallel | |
3345 | [(unspec [(match_dup 1) (match_dup 2) | |
3346 | (const_int 0)] UNSPEC_EXECUTE) | |
3347 | (set (match_dup 0) (const_int 0)) | |
3348 | (use (const_int 1)) | |
ae156f85 | 3349 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3350 | "") |
9db1d521 | 3351 | |
963fc8d0 AK |
3352 | (define_split |
3353 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3354 | (const_int 0)) | |
3355 | (use (match_operand 1 "register_operand" "")) | |
3356 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3357 | (clobber (scratch)) | |
3358 | (clobber (reg:CC CC_REGNUM))] | |
3359 | "TARGET_Z10 && reload_completed" | |
3360 | [(parallel | |
3361 | [(unspec [(match_dup 1) (const_int 0) | |
3362 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3363 | (set (match_dup 0) (const_int 0)) | |
3364 | (use (const_int 1)) | |
3365 | (clobber (reg:CC CC_REGNUM))])] | |
3366 | "operands[3] = gen_label_rtx ();") | |
3367 | ||
9bb86f41 UW |
3368 | (define_split |
3369 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3370 | (const_int 0)) | |
3371 | (use (match_operand 1 "register_operand" "")) | |
3372 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3373 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3374 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3375 | "reload_completed && TARGET_CPU_ZARCH" |
3376 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3377 | (parallel | |
9381e3f1 | 3378 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3379 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3380 | (set (match_dup 0) (const_int 0)) | |
3381 | (use (const_int 1)) | |
ae156f85 | 3382 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3383 | "operands[3] = gen_label_rtx ();") |
3384 | ||
9381e3f1 | 3385 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3386 | |
da0dcab1 | 3387 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3388 | [(parallel |
3389 | [(clobber (match_dup 1)) | |
3390 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3391 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3392 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3393 | (use (match_dup 3)) |
ae156f85 | 3394 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3395 | "" |
a41c6c53 | 3396 | { |
ef4bddc2 RS |
3397 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3398 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3399 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3400 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3401 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3402 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3403 | |
c41c1387 | 3404 | emit_clobber (reg0); |
b9404c99 UW |
3405 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3406 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3407 | |
b9404c99 | 3408 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3409 | |
b9404c99 UW |
3410 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3411 | operands[1] = reg0; | |
6d057022 | 3412 | operands[3] = reg1; |
da0dcab1 | 3413 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3414 | }) |
a41c6c53 | 3415 | |
da0dcab1 DV |
3416 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3417 | ||
db340c73 | 3418 | (define_insn "*setmem_long" |
a1aed706 | 3419 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3420 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3421 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3422 | (subreg:P (match_dup 3) <modesize>)] |
3423 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3424 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3425 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3426 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3427 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3428 | [(set_attr "length" "8") |
3429 | (set_attr "type" "vs")]) | |
9db1d521 | 3430 | |
db340c73 AK |
3431 | (define_insn "*setmem_long_and" |
3432 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3433 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3434 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3435 | (subreg:P (match_dup 3) <modesize>)] |
3436 | UNSPEC_REPLICATE_BYTE)) | |
3437 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3438 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3439 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3440 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3441 | [(set_attr "length" "8") | |
3442 | (set_attr "type" "vs")]) | |
3443 | ||
da0dcab1 DV |
3444 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3445 | ; of the SImode subregs. | |
3446 | ||
db340c73 | 3447 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3448 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3449 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3450 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3451 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3452 | (use (match_operand:TI 1 "register_operand" "d")) |
3453 | (clobber (reg:CC CC_REGNUM))] | |
3454 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3455 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3456 | [(set_attr "length" "8") | |
3457 | (set_attr "type" "vs")]) | |
9602b6a1 | 3458 | |
db340c73 AK |
3459 | (define_insn "*setmem_long_and_31z" |
3460 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3461 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3462 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3463 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3464 | (use (match_operand:TI 1 "register_operand" "d")) | |
3465 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3466 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3467 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3468 | [(set_attr "length" "8") | |
3469 | (set_attr "type" "vs")]) | |
3470 | ||
9db1d521 | 3471 | ; |
358b8f01 | 3472 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3473 | ; |
3474 | ||
358b8f01 | 3475 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3476 | [(set (match_operand:SI 0 "register_operand" "") |
3477 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3478 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3479 | (use (match_operand:SI 3 "general_operand" "")) | |
3480 | (use (match_operand:SI 4 "" ""))] | |
3481 | "" | |
367d32f3 AK |
3482 | { |
3483 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3484 | operands[2], operands[3])) | |
3485 | DONE; | |
3486 | else | |
3487 | FAIL; | |
3488 | }) | |
9db1d521 | 3489 | |
a41c6c53 UW |
3490 | ; Compare a block that is up to 256 bytes in length. |
3491 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3492 | |
b9404c99 UW |
3493 | (define_expand "cmpmem_short" |
3494 | [(parallel | |
ae156f85 | 3495 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3496 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3497 | (match_operand:BLK 1 "memory_operand" ""))) |
3498 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3499 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3500 | (clobber (match_dup 3))])] |
3501 | "" | |
3502 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3503 | |
b9404c99 | 3504 | (define_insn "*cmpmem_short" |
ae156f85 | 3505 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3506 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3507 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3508 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3509 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3510 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3511 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3512 | "#" |
963fc8d0 | 3513 | [(set_attr "type" "cs") |
b5e0425c | 3514 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3515 | |
9bb86f41 | 3516 | (define_split |
ae156f85 | 3517 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3518 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3519 | (match_operand:BLK 1 "memory_operand" ""))) | |
3520 | (use (match_operand 2 "const_int_operand" "")) | |
3521 | (use (match_operand 3 "immediate_operand" "")) | |
3522 | (clobber (scratch))] | |
3523 | "reload_completed" | |
3524 | [(parallel | |
ae156f85 | 3525 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3526 | (use (match_dup 2))])] |
3527 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3528 | |
9bb86f41 | 3529 | (define_split |
ae156f85 | 3530 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3531 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3532 | (match_operand:BLK 1 "memory_operand" ""))) | |
3533 | (use (match_operand 2 "register_operand" "")) | |
3534 | (use (match_operand 3 "memory_operand" "")) | |
3535 | (clobber (scratch))] | |
3536 | "reload_completed" | |
3537 | [(parallel | |
3538 | [(unspec [(match_dup 2) (match_dup 3) | |
3539 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3540 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3541 | (use (const_int 1))])] |
3542 | "") | |
3543 | ||
963fc8d0 AK |
3544 | (define_split |
3545 | [(set (reg:CCU CC_REGNUM) | |
3546 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3547 | (match_operand:BLK 1 "memory_operand" ""))) | |
3548 | (use (match_operand 2 "register_operand" "")) | |
3549 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3550 | (clobber (scratch))] | |
3551 | "TARGET_Z10 && reload_completed" | |
3552 | [(parallel | |
3553 | [(unspec [(match_dup 2) (const_int 0) | |
3554 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3555 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3556 | (use (const_int 1))])] | |
3557 | "operands[4] = gen_label_rtx ();") | |
3558 | ||
9bb86f41 | 3559 | (define_split |
ae156f85 | 3560 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3561 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3562 | (match_operand:BLK 1 "memory_operand" ""))) | |
3563 | (use (match_operand 2 "register_operand" "")) | |
3564 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3565 | (clobber (match_operand 3 "register_operand" ""))] | |
3566 | "reload_completed && TARGET_CPU_ZARCH" | |
3567 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3568 | (parallel | |
9381e3f1 | 3569 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3570 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3571 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3572 | (use (const_int 1))])] |
3573 | "operands[4] = gen_label_rtx ();") | |
3574 | ||
a41c6c53 | 3575 | ; Compare a block of arbitrary length. |
9db1d521 | 3576 | |
b9404c99 UW |
3577 | (define_expand "cmpmem_long" |
3578 | [(parallel | |
3579 | [(clobber (match_dup 2)) | |
3580 | (clobber (match_dup 3)) | |
ae156f85 | 3581 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3582 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3583 | (match_operand:BLK 1 "memory_operand" ""))) |
3584 | (use (match_operand 2 "general_operand" "")) | |
3585 | (use (match_dup 3))])] | |
3586 | "" | |
3587 | { | |
ef4bddc2 RS |
3588 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3589 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3590 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3591 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3592 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3593 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3594 | rtx len0 = gen_lowpart (Pmode, reg0); |
3595 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3596 | ||
c41c1387 | 3597 | emit_clobber (reg0); |
b9404c99 UW |
3598 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3599 | emit_move_insn (len0, operands[2]); | |
3600 | ||
c41c1387 | 3601 | emit_clobber (reg1); |
b9404c99 UW |
3602 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3603 | emit_move_insn (len1, operands[2]); | |
3604 | ||
3605 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3606 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3607 | operands[2] = reg0; | |
3608 | operands[3] = reg1; | |
3609 | }) | |
3610 | ||
a1aed706 AS |
3611 | (define_insn "*cmpmem_long" |
3612 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3613 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3614 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3615 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3616 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3617 | (use (match_dup 2)) |
3618 | (use (match_dup 3))] | |
9602b6a1 | 3619 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3620 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3621 | [(set_attr "length" "8") |
3622 | (set_attr "type" "vs")]) | |
9db1d521 | 3623 | |
9602b6a1 AK |
3624 | (define_insn "*cmpmem_long_31z" |
3625 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3626 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3627 | (set (reg:CCU CC_REGNUM) | |
3628 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3629 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3630 | (use (match_dup 2)) | |
3631 | (use (match_dup 3))] | |
3632 | "!TARGET_64BIT && TARGET_ZARCH" | |
3633 | "clcle\t%0,%1,0\;jo\t.-4" | |
3634 | [(set_attr "op_type" "NN") | |
3635 | (set_attr "type" "vs") | |
3636 | (set_attr "length" "8")]) | |
3637 | ||
02887425 UW |
3638 | ; Convert CCUmode condition code to integer. |
3639 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3640 | |
02887425 | 3641 | (define_insn_and_split "cmpint" |
9db1d521 | 3642 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3643 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3644 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3645 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3646 | "" |
02887425 UW |
3647 | "#" |
3648 | "reload_completed" | |
3649 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3650 | (parallel | |
3651 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3652 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3653 | |
3654 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3655 | [(set (reg CC_REGNUM) |
02887425 | 3656 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3657 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3658 | (const_int 0))) |
3659 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3660 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3661 | "s390_match_ccmode (insn, CCSmode)" |
3662 | "#" | |
3663 | "&& reload_completed" | |
3664 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3665 | (parallel | |
3666 | [(set (match_dup 2) (match_dup 3)) | |
3667 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3668 | { |
02887425 UW |
3669 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3670 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3671 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3672 | }) | |
9db1d521 | 3673 | |
02887425 | 3674 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3675 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3676 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3677 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3678 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3679 | "TARGET_ZARCH" |
02887425 UW |
3680 | "#" |
3681 | "&& reload_completed" | |
3682 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3683 | (parallel | |
3684 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3685 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3686 | |
3687 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3688 | [(set (reg CC_REGNUM) |
9381e3f1 | 3689 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3690 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3691 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3692 | (const_int 32)) (const_int 32)) |
3693 | (const_int 0))) | |
3694 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3695 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3696 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3697 | "#" |
3698 | "&& reload_completed" | |
3699 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3700 | (parallel | |
3701 | [(set (match_dup 2) (match_dup 3)) | |
3702 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3703 | { |
02887425 UW |
3704 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3705 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3706 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3707 | }) | |
9db1d521 | 3708 | |
4023fb28 | 3709 | |
9db1d521 HP |
3710 | ;; |
3711 | ;;- Conversion instructions. | |
3712 | ;; | |
3713 | ||
6fa05db6 | 3714 | (define_insn "*sethighpartsi" |
d3632d41 | 3715 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3716 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3717 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3718 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3719 | "" |
d3632d41 | 3720 | "@ |
6fa05db6 AS |
3721 | icm\t%0,%2,%S1 |
3722 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3723 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3724 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3725 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3726 | |
6fa05db6 | 3727 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3728 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3729 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3730 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3731 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3732 | "TARGET_ZARCH" |
6fa05db6 | 3733 | "icmh\t%0,%2,%S1" |
729e750f WG |
3734 | [(set_attr "op_type" "RSY") |
3735 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3736 | |
6fa05db6 | 3737 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3738 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3739 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3740 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3741 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3742 | "!TARGET_ZARCH" |
d3632d41 | 3743 | "@ |
6fa05db6 AS |
3744 | icm\t%0,%2,%S1 |
3745 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3746 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3747 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3748 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3749 | ||
1a2e356e RH |
3750 | ; |
3751 | ; extv instruction patterns | |
3752 | ; | |
3753 | ||
3754 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3755 | ; after resolving some issues with it. | |
3756 | ||
3757 | (define_expand "extzv" | |
3758 | [(parallel | |
3759 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3760 | (zero_extract:DI | |
3761 | (match_operand:DI 1 "register_operand" "d") | |
3762 | (match_operand 2 "const_int_operand" "") ; size | |
3763 | (match_operand 3 "const_int_operand" ""))) ; start | |
3764 | (clobber (reg:CC CC_REGNUM))])] | |
3765 | "TARGET_Z10" | |
3766 | { | |
0f6f72e8 DV |
3767 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3768 | FAIL; | |
1a2e356e RH |
3769 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3770 | if (TARGET_ZEC12) | |
3771 | { | |
3772 | emit_move_insn (operands[0], | |
3773 | gen_rtx_ZERO_EXTRACT (DImode, | |
3774 | operands[1], | |
3775 | operands[2], | |
3776 | operands[3])); | |
3777 | DONE; | |
3778 | } | |
3779 | }) | |
3780 | ||
64c744b9 | 3781 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3782 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3783 | (zero_extract:GPR | |
3784 | (match_operand:GPR 1 "register_operand" "d") | |
3785 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3786 | (match_operand 3 "const_int_operand" ""))) ; start |
3787 | ] | |
0f6f72e8 DV |
3788 | "<z10_or_zEC12_cond> |
3789 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3790 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3791 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3792 | [(set_attr "op_type" "RIE") | |
3793 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3794 | |
64c744b9 DV |
3795 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3796 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3797 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3798 | (match_operand 1 "const_int_operand" "") ; size | |
3799 | (match_operand 2 "const_int_operand" "")) ; start | |
3800 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3801 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3802 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3803 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3804 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3805 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3806 | [(set_attr "op_type" "RIE") | |
3807 | (set_attr "z10prop" "z10_super_E1")]) | |
3808 | ||
3809 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3810 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3811 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3812 | (ior:SI (and:SI | |
3813 | (match_operand:SI 1 "register_operand" "0") | |
3814 | (match_operand:SI 2 "const_int_operand" "")) | |
3815 | (subreg:SI | |
3816 | (zero_extract:DI | |
3817 | (match_operand:DI 3 "register_operand" "d") | |
3818 | (match_operand 4 "const_int_operand" "") ; size | |
3819 | (match_operand 5 "const_int_operand" "")) ; start | |
3820 | 4)))] | |
3821 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3822 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
64c744b9 DV |
3823 | && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))" |
3824 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" | |
3825 | [(set_attr "op_type" "RIE") | |
3826 | (set_attr "z10prop" "z10_super_E1")]) | |
3827 | ||
3828 | ; ((int)foo >> 10) & 1; | |
3829 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3830 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3831 | (ne:DI (zero_extract:DI | |
3832 | (match_operand:DI 1 "register_operand" "d") | |
3833 | (const_int 1) ; size | |
3834 | (match_operand 2 "const_int_operand" "")) ; start | |
3835 | (const_int 0)))] | |
0f6f72e8 DV |
3836 | "<z10_or_zEC12_cond> |
3837 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3838 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3839 | [(set_attr "op_type" "RIE") | |
3840 | (set_attr "z10prop" "z10_super_E1")]) | |
3841 | ||
3842 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3843 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3844 | (and:DI (subreg:DI | |
3845 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3846 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3847 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3848 | "<z10_or_zEC12_cond> | |
3849 | && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))" | |
3850 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift | |
3851 | [(set_attr "op_type" "RIE") | |
3852 | (set_attr "z10prop" "z10_super_E1")]) | |
3853 | ||
3854 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3855 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3856 | (and:DI (subreg:DI | |
3857 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3858 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3859 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3860 | "<z10_or_zEC12_cond> | |
3861 | && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
3862 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
3863 | [(set_attr "op_type" "RIE") | |
3864 | (set_attr "z10prop" "z10_super_E1")]) | |
3865 | ||
3866 | (define_insn "*<risbg_n>_di_and_rot" | |
3867 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3868 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
3869 | (match_operand:DI 2 "const_int_operand" "")) | |
3870 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3871 | "<z10_or_zEC12_cond>" | |
3872 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
3873 | [(set_attr "op_type" "RIE") |
3874 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3875 | |
1a2e356e | 3876 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 3877 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3878 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3879 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3880 | (const_int 0))) |
ae156f85 | 3881 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3882 | "!TARGET_Z10" |
cc7ab9b7 UW |
3883 | "#" |
3884 | "&& reload_completed" | |
4023fb28 | 3885 | [(parallel |
6fa05db6 | 3886 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3887 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3888 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3889 | { |
6fa05db6 AS |
3890 | int bitsize = INTVAL (operands[2]); |
3891 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3892 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3893 | ||
3894 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3895 | set_mem_size (operands[1], size); |
2542ef05 | 3896 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3897 | operands[3] = GEN_INT (mask); |
b628bd8e | 3898 | }) |
4023fb28 | 3899 | |
1a2e356e | 3900 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 3901 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3902 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3903 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3904 | (const_int 0))) |
ae156f85 | 3905 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3906 | "" |
cc7ab9b7 UW |
3907 | "#" |
3908 | "&& reload_completed" | |
4023fb28 | 3909 | [(parallel |
6fa05db6 | 3910 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3911 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3912 | (parallel |
3913 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3914 | (clobber (reg:CC CC_REGNUM))])] | |
3915 | { | |
3916 | int bitsize = INTVAL (operands[2]); | |
3917 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3918 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3919 | ||
3920 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3921 | set_mem_size (operands[1], size); |
2542ef05 | 3922 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3923 | operands[3] = GEN_INT (mask); |
3924 | }) | |
3925 | ||
3926 | ; | |
3927 | ; insv instruction patterns | |
3928 | ; | |
3929 | ||
3930 | (define_expand "insv" | |
3931 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3932 | (match_operand 1 "const_int_operand" "") | |
3933 | (match_operand 2 "const_int_operand" "")) | |
3934 | (match_operand 3 "general_operand" ""))] | |
3935 | "" | |
4023fb28 | 3936 | { |
6fa05db6 AS |
3937 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3938 | DONE; | |
3939 | FAIL; | |
b628bd8e | 3940 | }) |
4023fb28 | 3941 | |
2542ef05 RH |
3942 | |
3943 | ; The normal RTL expansion will never generate a zero_extract where | |
3944 | ; the location operand isn't word mode. However, we do this in the | |
3945 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 3946 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 3947 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
3948 | (match_operand 1 "const_int_operand" "I") ; size |
3949 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 3950 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 3951 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
3952 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
3953 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 3954 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 3955 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
3956 | [(set_attr "op_type" "RIE") |
3957 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3958 | |
22ac2c2f AK |
3959 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3960 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
3961 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
3962 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
3963 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 3964 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 3965 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 3966 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
3967 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3968 | "@ | |
3969 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
3970 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
3971 | [(set_attr "op_type" "RIE") | |
3972 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 3973 | |
64c744b9 DV |
3974 | (define_insn "*insv_z10_noshift_cc" |
3975 | [(set (reg CC_REGNUM) | |
3976 | (compare | |
3977 | (ior:DI | |
3978 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
3979 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
3980 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
3981 | (match_operand:DI 4 "const_int_operand" ""))) | |
3982 | (const_int 0))) | |
3983 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
3984 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
3985 | (and:DI (match_dup 3) (match_dup 4))))] | |
3986 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
3987 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3988 | "@ | |
3989 | risbg\t%0,%1,%s2,%e2,0 | |
3990 | risbg\t%0,%3,%s4,%e4,0" | |
3991 | [(set_attr "op_type" "RIE") | |
3992 | (set_attr "z10prop" "z10_super_E1")]) | |
3993 | ||
3994 | (define_insn "*insv_z10_noshift_cconly" | |
3995 | [(set | |
3996 | (reg CC_REGNUM) | |
3997 | (compare | |
3998 | (ior:DI | |
3999 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4000 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4001 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4002 | (match_operand:DI 4 "const_int_operand" ""))) | |
4003 | (const_int 0))) | |
4004 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4005 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4006 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4007 | "@ | |
4008 | risbg\t%0,%1,%s2,%e2,0 | |
4009 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4010 | [(set_attr "op_type" "RIE") |
4011 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4012 | |
3d44ff99 AK |
4013 | ; Implement appending Y on the left of S bits of X |
4014 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4015 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4016 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4017 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4018 | (match_operand:GPR 2 "immediate_operand" "")) | |
4019 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4020 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 DV |
4021 | "<z10_or_zEC12_cond> |
4022 | && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
4023 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" | |
3d44ff99 AK |
4024 | [(set_attr "op_type" "RIE") |
4025 | (set_attr "z10prop" "z10_super_E1")]) | |
4026 | ||
64c744b9 DV |
4027 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4028 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4029 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4030 | (ior:GPR (and:GPR | |
4031 | (match_operand:GPR 1 "register_operand" "0") | |
4032 | (match_operand:GPR 2 "const_int_operand" "")) | |
4033 | (lshiftrt:GPR | |
4034 | (match_operand:GPR 3 "register_operand" "d") | |
4035 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4036 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
4037 | == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
4038 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" | |
4039 | [(set_attr "op_type" "RIE") | |
4040 | (set_attr "z10prop" "z10_super_E1")]) | |
4041 | ||
4042 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4043 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4044 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4045 | (ior:SI (and:SI | |
4046 | (match_operand:SI 1 "register_operand" "0") | |
4047 | (match_operand:SI 2 "const_int_operand" "")) | |
4048 | (subreg:SI | |
4049 | (lshiftrt:DI | |
4050 | (match_operand:DI 3 "register_operand" "d") | |
4051 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4052 | "<z10_or_zEC12_cond> | |
4053 | && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))" | |
4054 | "<risbg_n>\t%0,%3,%4,63,64-%4" | |
4055 | [(set_attr "op_type" "RIE") | |
4056 | (set_attr "z10prop" "z10_super_E1")]) | |
4057 | ||
4058 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4059 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4060 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4061 | (and:SI | |
4062 | (subreg:SI (lshiftrt:DI | |
4063 | (match_operand:DI 1 "register_operand" "d") | |
4064 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4065 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4066 | "<z10_or_zEC12_cond>" | |
4067 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4068 | [(set_attr "op_type" "RIE") |
4069 | (set_attr "z10prop" "z10_super_E1")]) | |
4070 | ||
4071 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4072 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4073 | ; -> z = y >> d; z = risbg; | |
4074 | ||
4075 | (define_split | |
4076 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4077 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4078 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4079 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4080 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4081 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4082 | [(set (match_dup 6) |
3d44ff99 AK |
4083 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4084 | (set (match_dup 0) | |
1d11f7ce | 4085 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4086 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4087 | { | |
4088 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4089 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4090 | { |
4091 | if (!can_create_pseudo_p ()) | |
4092 | FAIL; | |
4093 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4094 | } | |
4095 | else | |
4096 | operands[6] = operands[0]; | |
3d44ff99 AK |
4097 | }) |
4098 | ||
4099 | (define_split | |
4100 | [(parallel | |
4101 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4102 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4103 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4104 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4105 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4106 | (clobber (reg:CC CC_REGNUM))])] | |
4107 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4108 | [(set (match_dup 6) |
3d44ff99 AK |
4109 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4110 | (parallel | |
4111 | [(set (match_dup 0) | |
1d11f7ce | 4112 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4113 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4114 | (clobber (reg:CC CC_REGNUM))])] | |
4115 | { | |
4116 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4117 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4118 | { |
4119 | if (!can_create_pseudo_p ()) | |
4120 | FAIL; | |
4121 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4122 | } | |
4123 | else | |
4124 | operands[6] = operands[0]; | |
3d44ff99 AK |
4125 | }) |
4126 | ||
50dc4eed | 4127 | ; rosbg, rxsbg |
571e408a | 4128 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4129 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4130 | (IXOR:GPR |
4131 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4132 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4133 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4134 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4135 | "TARGET_Z10" |
571e408a RH |
4136 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4137 | [(set_attr "op_type" "RIE")]) | |
4138 | ||
50dc4eed | 4139 | ; rosbg, rxsbg |
571e408a RH |
4140 | (define_insn "*r<noxa>sbg_di_rotl" |
4141 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4142 | (IXOR:DI | |
4143 | (and:DI | |
4144 | (rotate:DI | |
4145 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4146 | (match_operand:DI 3 "const_int_operand" "")) | |
4147 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4148 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4149 | (clobber (reg:CC CC_REGNUM))] | |
4150 | "TARGET_Z10" | |
4151 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
4152 | [(set_attr "op_type" "RIE")]) | |
4153 | ||
50dc4eed | 4154 | ; rosbg, rxsbg |
f3d90045 | 4155 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4156 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4157 | (IXOR:GPR | |
4158 | (and:GPR | |
4159 | (lshiftrt:GPR | |
4160 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4161 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4162 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4163 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4164 | (clobber (reg:CC CC_REGNUM))] | |
4165 | "TARGET_Z10 | |
4166 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4167 | INTVAL (operands[2]))" | |
4168 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
4169 | [(set_attr "op_type" "RIE")]) | |
4170 | ||
50dc4eed | 4171 | ; rosbg, rxsbg |
f3d90045 | 4172 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4173 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4174 | (IXOR:GPR | |
4175 | (and:GPR | |
4176 | (ashift:GPR | |
4177 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4178 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4179 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4180 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4181 | (clobber (reg:CC CC_REGNUM))] | |
4182 | "TARGET_Z10 | |
4183 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4184 | INTVAL (operands[2]))" | |
4185 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4186 | [(set_attr "op_type" "RIE")]) |
4187 | ||
f3d90045 DV |
4188 | ;; unsigned {int,long} a, b |
4189 | ;; a = a | (b << const_int) | |
4190 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4191 | ; rosbg, rxsbg |
f3d90045 DV |
4192 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4193 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4194 | (IXOR:GPR | |
4195 | (ashift:GPR | |
4196 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4197 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4198 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4199 | (clobber (reg:CC CC_REGNUM))] | |
4200 | "TARGET_Z10" | |
576987fc | 4201 | "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2" |
f3d90045 DV |
4202 | [(set_attr "op_type" "RIE")]) |
4203 | ||
4204 | ;; unsigned {int,long} a, b | |
4205 | ;; a = a | (b >> const_int) | |
4206 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4207 | ; rosbg, rxsbg |
f3d90045 DV |
4208 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4209 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4210 | (IXOR:GPR | |
4211 | (lshiftrt:GPR | |
4212 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4213 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4214 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4215 | (clobber (reg:CC CC_REGNUM))] | |
4216 | "TARGET_Z10" | |
576987fc | 4217 | "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2" |
f3d90045 DV |
4218 | [(set_attr "op_type" "RIE")]) |
4219 | ||
5bb33936 RH |
4220 | ;; These two are generated by combine for s.bf &= val. |
4221 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4222 | ;; shifts and ands, which results in some truly awful patterns | |
4223 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4224 | ;; Instead of | |
4225 | ;; | |
4226 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4227 | ;; (const_int 24 [0x18]) | |
4228 | ;; (const_int 0 [0])) | |
4229 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4230 | ;; (const_int 40 [0x28])) 4) | |
4231 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4232 | ;; | |
4233 | ;; we should instead generate | |
4234 | ;; | |
4235 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4236 | ;; (const_int 24 [0x18]) | |
4237 | ;; (const_int 0 [0])) | |
4238 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4239 | ;; (const_int 40 [0x28])) | |
4240 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4241 | ;; | |
4242 | ;; by noticing that we can push down the outer paradoxical subreg | |
4243 | ;; into the operation. | |
4244 | ||
4245 | (define_insn "*insv_rnsbg_noshift" | |
4246 | [(set (zero_extract:DI | |
4247 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4248 | (match_operand 1 "const_int_operand" "") | |
4249 | (match_operand 2 "const_int_operand" "")) | |
4250 | (and:DI | |
4251 | (match_dup 0) | |
4252 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4253 | (clobber (reg:CC CC_REGNUM))] | |
4254 | "TARGET_Z10 | |
0f6f72e8 | 4255 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4256 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4257 | "rnsbg\t%0,%3,%2,63,0" | |
4258 | [(set_attr "op_type" "RIE")]) | |
4259 | ||
4260 | (define_insn "*insv_rnsbg_srl" | |
4261 | [(set (zero_extract:DI | |
4262 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4263 | (match_operand 1 "const_int_operand" "") | |
4264 | (match_operand 2 "const_int_operand" "")) | |
4265 | (and:DI | |
4266 | (lshiftrt:DI | |
4267 | (match_dup 0) | |
4268 | (match_operand 3 "const_int_operand" "")) | |
4269 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4270 | (clobber (reg:CC CC_REGNUM))] | |
4271 | "TARGET_Z10 | |
0f6f72e8 | 4272 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4273 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4274 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4275 | [(set_attr "op_type" "RIE")]) | |
4276 | ||
6fa05db6 | 4277 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4278 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4279 | (match_operand 1 "const_int_operand" "n,n") |
4280 | (const_int 0)) | |
9602b6a1 | 4281 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4282 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4283 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4284 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4285 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4286 | { | |
4287 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4288 | ||
4289 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4290 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4291 | : "stcmy\t%2,%1,%S0"; |
4292 | } | |
9381e3f1 | 4293 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4294 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4295 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4296 | |
4297 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4298 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4299 | (match_operand 1 "const_int_operand" "n") |
4300 | (const_int 0)) | |
4301 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4302 | (const_int 32)))] | |
9602b6a1 | 4303 | "TARGET_ZARCH |
0f6f72e8 | 4304 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4305 | && INTVAL (operands[1]) > 0 |
4306 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4307 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4308 | { | |
4309 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4310 | ||
4311 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4312 | return "stcmh\t%2,%1,%S0"; | |
4313 | } | |
9381e3f1 WG |
4314 | [(set_attr "op_type" "RSY") |
4315 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4316 | |
9602b6a1 AK |
4317 | (define_insn "*insvdi_reg_imm" |
4318 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4319 | (const_int 16) | |
4320 | (match_operand 1 "const_int_operand" "n")) | |
4321 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4322 | "TARGET_ZARCH |
0f6f72e8 | 4323 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4324 | && INTVAL (operands[1]) >= 0 |
4325 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4326 | && INTVAL (operands[1]) % 16 == 0" | |
4327 | { | |
4328 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4329 | { | |
4330 | case 64: return "iihh\t%0,%x2"; break; | |
4331 | case 48: return "iihl\t%0,%x2"; break; | |
4332 | case 32: return "iilh\t%0,%x2"; break; | |
4333 | case 16: return "iill\t%0,%x2"; break; | |
4334 | default: gcc_unreachable(); | |
4335 | } | |
4336 | } | |
9381e3f1 WG |
4337 | [(set_attr "op_type" "RI") |
4338 | (set_attr "z10prop" "z10_super_E1")]) | |
4339 | ||
9fec758d WG |
4340 | ; Update the left-most 32 bit of a DI. |
4341 | (define_insn "*insv_h_di_reg_extimm" | |
4342 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4343 | (const_int 32) | |
4344 | (const_int 0)) | |
4345 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4346 | "TARGET_EXTIMM" | |
4347 | "iihf\t%0,%o1" | |
4348 | [(set_attr "op_type" "RIL") | |
4349 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4350 | |
d378b983 RH |
4351 | ; Update the right-most 32 bit of a DI. |
4352 | (define_insn "*insv_l_di_reg_extimm" | |
4353 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4354 | (const_int 32) | |
4355 | (const_int 32)) | |
4356 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4357 | "TARGET_EXTIMM" | |
4358 | "iilf\t%0,%o1" | |
9381e3f1 | 4359 | [(set_attr "op_type" "RIL") |
9fec758d | 4360 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4361 | |
9db1d521 HP |
4362 | ; |
4363 | ; extendsidi2 instruction pattern(s). | |
4364 | ; | |
4365 | ||
4023fb28 UW |
4366 | (define_expand "extendsidi2" |
4367 | [(set (match_operand:DI 0 "register_operand" "") | |
4368 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4369 | "" | |
4023fb28 | 4370 | { |
9602b6a1 | 4371 | if (!TARGET_ZARCH) |
4023fb28 | 4372 | { |
c41c1387 | 4373 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4374 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4375 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4376 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4377 | DONE; |
4378 | } | |
ec24698e | 4379 | }) |
4023fb28 UW |
4380 | |
4381 | (define_insn "*extendsidi2" | |
963fc8d0 | 4382 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4383 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4384 | "TARGET_ZARCH" |
9db1d521 | 4385 | "@ |
d40c829f | 4386 | lgfr\t%0,%1 |
963fc8d0 AK |
4387 | lgf\t%0,%1 |
4388 | lgfrl\t%0,%1" | |
4389 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4390 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4391 | (set_attr "cpu_facility" "*,*,z10") |
4392 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4393 | |
9db1d521 | 4394 | ; |
56477c21 | 4395 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4396 | ; |
4397 | ||
56477c21 AS |
4398 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4399 | [(set (match_operand:DSI 0 "register_operand" "") | |
4400 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4401 | "" |
4023fb28 | 4402 | { |
9602b6a1 | 4403 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4404 | { |
4405 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4406 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4407 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4408 | DONE; | |
4409 | } | |
ec24698e | 4410 | else if (!TARGET_EXTIMM) |
4023fb28 | 4411 | { |
2542ef05 | 4412 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4413 | |
4414 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4415 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4416 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4417 | DONE; |
4418 | } | |
ec24698e UW |
4419 | }) |
4420 | ||
56477c21 AS |
4421 | ; |
4422 | ; extendhidi2 instruction pattern(s). | |
4423 | ; | |
4424 | ||
ec24698e | 4425 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4426 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4427 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4428 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4429 | "@ |
4430 | lghr\t%0,%1 | |
963fc8d0 AK |
4431 | lgh\t%0,%1 |
4432 | lghrl\t%0,%1" | |
4433 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4434 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4435 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4436 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4437 | |
4438 | (define_insn "*extendhidi2" | |
9db1d521 | 4439 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4440 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4441 | "TARGET_ZARCH" |
d40c829f | 4442 | "lgh\t%0,%1" |
9381e3f1 WG |
4443 | [(set_attr "op_type" "RXY") |
4444 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4445 | |
9db1d521 | 4446 | ; |
56477c21 | 4447 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4448 | ; |
4449 | ||
ec24698e | 4450 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4451 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4452 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4453 | "TARGET_EXTIMM" |
4454 | "@ | |
4455 | lhr\t%0,%1 | |
4456 | lh\t%0,%1 | |
963fc8d0 AK |
4457 | lhy\t%0,%1 |
4458 | lhrl\t%0,%1" | |
4459 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4460 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4461 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4462 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4463 | |
4023fb28 | 4464 | (define_insn "*extendhisi2" |
d3632d41 UW |
4465 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4466 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4467 | "!TARGET_EXTIMM" |
d3632d41 | 4468 | "@ |
d40c829f UW |
4469 | lh\t%0,%1 |
4470 | lhy\t%0,%1" | |
9381e3f1 | 4471 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4472 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4473 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4474 | |
56477c21 AS |
4475 | ; |
4476 | ; extendqi(si|di)2 instruction pattern(s). | |
4477 | ; | |
4478 | ||
43a09b63 | 4479 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4480 | (define_insn "*extendqi<mode>2_extimm" |
4481 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4482 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4483 | "TARGET_EXTIMM" |
4484 | "@ | |
56477c21 AS |
4485 | l<g>br\t%0,%1 |
4486 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4487 | [(set_attr "op_type" "RRE,RXY") |
4488 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4489 | |
43a09b63 | 4490 | ; lb, lgb |
56477c21 AS |
4491 | (define_insn "*extendqi<mode>2" |
4492 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4493 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4494 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4495 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4496 | [(set_attr "op_type" "RXY") |
4497 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4498 | |
56477c21 AS |
4499 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4500 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4501 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4502 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4503 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4504 | "#" |
4505 | "&& reload_completed" | |
4023fb28 | 4506 | [(parallel |
56477c21 | 4507 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4508 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4509 | (parallel |
56477c21 | 4510 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4511 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4512 | { |
4513 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4514 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4515 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4516 | }) |
9db1d521 | 4517 | |
9db1d521 HP |
4518 | ; |
4519 | ; zero_extendsidi2 instruction pattern(s). | |
4520 | ; | |
4521 | ||
4023fb28 UW |
4522 | (define_expand "zero_extendsidi2" |
4523 | [(set (match_operand:DI 0 "register_operand" "") | |
4524 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4525 | "" | |
4023fb28 | 4526 | { |
9602b6a1 | 4527 | if (!TARGET_ZARCH) |
4023fb28 | 4528 | { |
c41c1387 | 4529 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4530 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4531 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4532 | DONE; |
4533 | } | |
ec24698e | 4534 | }) |
4023fb28 UW |
4535 | |
4536 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4537 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4538 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4539 | "TARGET_ZARCH" |
9db1d521 | 4540 | "@ |
d40c829f | 4541 | llgfr\t%0,%1 |
963fc8d0 AK |
4542 | llgf\t%0,%1 |
4543 | llgfrl\t%0,%1" | |
4544 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4545 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4546 | (set_attr "cpu_facility" "*,*,z10") |
4547 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4548 | |
288e517f AK |
4549 | ; |
4550 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4551 | ; | |
4552 | ||
d6083c7d UW |
4553 | (define_insn "*llgt_sidi" |
4554 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4555 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4556 | (const_int 2147483647)))] |
9602b6a1 | 4557 | "TARGET_ZARCH" |
d6083c7d | 4558 | "llgt\t%0,%1" |
9381e3f1 WG |
4559 | [(set_attr "op_type" "RXE") |
4560 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4561 | |
4562 | (define_insn_and_split "*llgt_sidi_split" | |
4563 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4564 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4565 | (const_int 2147483647))) |
ae156f85 | 4566 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4567 | "TARGET_ZARCH" |
d6083c7d UW |
4568 | "#" |
4569 | "&& reload_completed" | |
4570 | [(set (match_dup 0) | |
4571 | (and:DI (subreg:DI (match_dup 1) 0) | |
4572 | (const_int 2147483647)))] | |
4573 | "") | |
4574 | ||
288e517f AK |
4575 | (define_insn "*llgt_sisi" |
4576 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4577 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4578 | (const_int 2147483647)))] |
c4d50129 | 4579 | "TARGET_ZARCH" |
288e517f AK |
4580 | "@ |
4581 | llgtr\t%0,%1 | |
4582 | llgt\t%0,%1" | |
9381e3f1 WG |
4583 | [(set_attr "op_type" "RRE,RXE") |
4584 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4585 | |
288e517f AK |
4586 | (define_insn "*llgt_didi" |
4587 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4588 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4589 | (const_int 2147483647)))] | |
9602b6a1 | 4590 | "TARGET_ZARCH" |
288e517f AK |
4591 | "@ |
4592 | llgtr\t%0,%1 | |
4593 | llgt\t%0,%N1" | |
9381e3f1 WG |
4594 | [(set_attr "op_type" "RRE,RXE") |
4595 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4596 | |
f19a9af7 | 4597 | (define_split |
9602b6a1 AK |
4598 | [(set (match_operand:DSI 0 "register_operand" "") |
4599 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4600 | (const_int 2147483647))) |
ae156f85 | 4601 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4602 | "TARGET_ZARCH && reload_completed" |
288e517f | 4603 | [(set (match_dup 0) |
9602b6a1 | 4604 | (and:DSI (match_dup 1) |
f6ee577c | 4605 | (const_int 2147483647)))] |
288e517f AK |
4606 | "") |
4607 | ||
9db1d521 | 4608 | ; |
56477c21 | 4609 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4610 | ; |
4611 | ||
56477c21 AS |
4612 | (define_expand "zero_extend<mode>di2" |
4613 | [(set (match_operand:DI 0 "register_operand" "") | |
4614 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4615 | "" | |
4616 | { | |
9602b6a1 | 4617 | if (!TARGET_ZARCH) |
56477c21 AS |
4618 | { |
4619 | rtx tmp = gen_reg_rtx (SImode); | |
4620 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4621 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4622 | DONE; | |
4623 | } | |
4624 | else if (!TARGET_EXTIMM) | |
4625 | { | |
2542ef05 | 4626 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4627 | operands[1] = gen_lowpart (DImode, operands[1]); |
4628 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4629 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4630 | DONE; | |
4631 | } | |
4632 | }) | |
4633 | ||
f6ee577c | 4634 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4635 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4636 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4637 | "" |
4023fb28 | 4638 | { |
ec24698e UW |
4639 | if (!TARGET_EXTIMM) |
4640 | { | |
4641 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4642 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4643 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4644 | DONE; |
56477c21 | 4645 | } |
ec24698e UW |
4646 | }) |
4647 | ||
963fc8d0 AK |
4648 | ; llhrl, llghrl |
4649 | (define_insn "*zero_extendhi<mode>2_z10" | |
4650 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4651 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4652 | "TARGET_Z10" |
4653 | "@ | |
4654 | ll<g>hr\t%0,%1 | |
4655 | ll<g>h\t%0,%1 | |
4656 | ll<g>hrl\t%0,%1" | |
4657 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4658 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4659 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4660 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4661 | |
43a09b63 | 4662 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4663 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4664 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4665 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4666 | "TARGET_EXTIMM" |
4667 | "@ | |
56477c21 AS |
4668 | ll<g><hc>r\t%0,%1 |
4669 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4670 | [(set_attr "op_type" "RRE,RXY") |
4671 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4672 | |
43a09b63 | 4673 | ; llgh, llgc |
56477c21 AS |
4674 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4675 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4676 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4677 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4678 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4679 | [(set_attr "op_type" "RXY") |
4680 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4681 | |
4682 | (define_insn_and_split "*zero_extendhisi2_31" | |
4683 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4684 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4685 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4686 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4687 | "#" |
4688 | "&& reload_completed" | |
4689 | [(set (match_dup 0) (const_int 0)) | |
4690 | (parallel | |
4691 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4692 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4693 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4694 | |
cc7ab9b7 UW |
4695 | (define_insn_and_split "*zero_extendqisi2_31" |
4696 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4697 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4698 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4699 | "#" |
4700 | "&& reload_completed" | |
4701 | [(set (match_dup 0) (const_int 0)) | |
4702 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4703 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4704 | |
9db1d521 HP |
4705 | ; |
4706 | ; zero_extendqihi2 instruction pattern(s). | |
4707 | ; | |
4708 | ||
9db1d521 HP |
4709 | (define_expand "zero_extendqihi2" |
4710 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4711 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4712 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4713 | { |
4023fb28 UW |
4714 | operands[1] = gen_lowpart (HImode, operands[1]); |
4715 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4716 | DONE; | |
ec24698e | 4717 | }) |
9db1d521 | 4718 | |
4023fb28 | 4719 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4720 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4721 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4722 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4723 | "llgc\t%0,%1" |
9381e3f1 WG |
4724 | [(set_attr "op_type" "RXY") |
4725 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4726 | |
cc7ab9b7 UW |
4727 | (define_insn_and_split "*zero_extendqihi2_31" |
4728 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4729 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4730 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4731 | "#" |
4732 | "&& reload_completed" | |
4733 | [(set (match_dup 0) (const_int 0)) | |
4734 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4735 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4736 | |
609e7e80 AK |
4737 | ; |
4738 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
4739 | ; | |
4740 | ||
4741 | (define_expand "fixuns_truncdddi2" | |
4742 | [(parallel | |
4743 | [(set (match_operand:DI 0 "register_operand" "") | |
4744 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
ae8e301e | 4745 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4746 | (clobber (reg:CC CC_REGNUM))])] |
9381e3f1 | 4747 | |
fb068247 | 4748 | "TARGET_HARD_DFP" |
609e7e80 | 4749 | { |
65b1d8ea AK |
4750 | if (!TARGET_Z196) |
4751 | { | |
19f8b229 TS |
4752 | rtx_code_label *label1 = gen_label_rtx (); |
4753 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4754 | rtx temp = gen_reg_rtx (TDmode); |
4755 | REAL_VALUE_TYPE cmp, sub; | |
4756 | ||
4757 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4758 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4759 | ||
4760 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4761 | solution is doing the check and the subtraction in TD mode and using a | |
4762 | TD -> DI convert afterwards. */ | |
4763 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4764 | temp = force_reg (TDmode, temp); | |
4765 | emit_cmp_and_jump_insns (temp, | |
555affd7 | 4766 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4767 | LT, NULL_RTX, VOIDmode, 0, label1); |
4768 | emit_insn (gen_subtd3 (temp, temp, | |
555affd7 | 4769 | const_double_from_real_value (sub, TDmode))); |
ae8e301e AK |
4770 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, |
4771 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
65b1d8ea AK |
4772 | emit_jump (label2); |
4773 | ||
4774 | emit_label (label1); | |
ae8e301e AK |
4775 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], |
4776 | GEN_INT (DFP_RND_TOWARD_0))); | |
65b1d8ea AK |
4777 | emit_label (label2); |
4778 | DONE; | |
4779 | } | |
609e7e80 AK |
4780 | }) |
4781 | ||
4782 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
4783 | [(parallel |
4784 | [(set (match_operand:DI 0 "register_operand" "") | |
4785 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
ae8e301e | 4786 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4787 | (clobber (reg:CC CC_REGNUM))])] |
4788 | ||
fb068247 | 4789 | "TARGET_HARD_DFP" |
609e7e80 | 4790 | { |
65b1d8ea AK |
4791 | if (!TARGET_Z196) |
4792 | { | |
19f8b229 TS |
4793 | rtx_code_label *label1 = gen_label_rtx (); |
4794 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4795 | rtx temp = gen_reg_rtx (TDmode); |
4796 | REAL_VALUE_TYPE cmp, sub; | |
4797 | ||
4798 | operands[1] = force_reg (TDmode, operands[1]); | |
4799 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4800 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4801 | ||
4802 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4803 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4804 | LT, NULL_RTX, VOIDmode, 0, label1); |
4805 | emit_insn (gen_subtd3 (temp, operands[1], | |
555affd7 | 4806 | const_double_from_real_value (sub, TDmode))); |
ae8e301e AK |
4807 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, |
4808 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
65b1d8ea AK |
4809 | emit_jump (label2); |
4810 | ||
4811 | emit_label (label1); | |
ae8e301e AK |
4812 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], |
4813 | GEN_INT (DFP_RND_TOWARD_0))); | |
65b1d8ea AK |
4814 | emit_label (label2); |
4815 | DONE; | |
4816 | } | |
609e7e80 | 4817 | }) |
cc7ab9b7 | 4818 | |
9db1d521 | 4819 | ; |
65b1d8ea | 4820 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 4821 | ; instruction pattern(s). |
9db1d521 HP |
4822 | ; |
4823 | ||
7b6baae1 | 4824 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
4825 | [(parallel |
4826 | [(set (match_operand:GPR 0 "register_operand" "") | |
4827 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
ae8e301e | 4828 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4829 | (clobber (reg:CC CC_REGNUM))])] |
142cd70f | 4830 | "TARGET_HARD_FLOAT" |
9db1d521 | 4831 | { |
65b1d8ea AK |
4832 | if (!TARGET_Z196) |
4833 | { | |
19f8b229 TS |
4834 | rtx_code_label *label1 = gen_label_rtx (); |
4835 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4836 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); |
4837 | REAL_VALUE_TYPE cmp, sub; | |
4838 | ||
4839 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
2542ef05 RH |
4840 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); |
4841 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
65b1d8ea AK |
4842 | |
4843 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4844 | const_double_from_real_value (cmp, <BFP:MODE>mode), |
65b1d8ea AK |
4845 | LT, NULL_RTX, VOIDmode, 0, label1); |
4846 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
555affd7 | 4847 | const_double_from_real_value (sub, <BFP:MODE>mode))); |
65b1d8ea | 4848 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, |
ae8e301e | 4849 | GEN_INT (BFP_RND_TOWARD_MINF))); |
65b1d8ea AK |
4850 | emit_jump (label2); |
4851 | ||
4852 | emit_label (label1); | |
4853 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
ae8e301e | 4854 | operands[1], GEN_INT (BFP_RND_TOWARD_0))); |
65b1d8ea AK |
4855 | emit_label (label2); |
4856 | DONE; | |
4857 | } | |
10bbf137 | 4858 | }) |
9db1d521 | 4859 | |
65b1d8ea AK |
4860 | ; fixuns_trunc(td|dd)si2 expander |
4861 | (define_expand "fixuns_trunc<mode>si2" | |
4862 | [(parallel | |
4863 | [(set (match_operand:SI 0 "register_operand" "") | |
4864 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
ae8e301e | 4865 | (unspec:SI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4866 | (clobber (reg:CC CC_REGNUM))])] |
8540e6e8 | 4867 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4868 | "") |
4869 | ||
4870 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4871 | ||
6e5b5de8 AK |
4872 | (define_insn "*fixuns_truncdfdi2_z13" |
4873 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4874 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4875 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4876 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 4877 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4878 | "@ |
4879 | clgdbr\t%0,%h2,%1,0 | |
4880 | wclgdb\t%v0,%v1,0,%h2" | |
4881 | [(set_attr "op_type" "RRF,VRR") | |
4882 | (set_attr "type" "ftoi")]) | |
4883 | ||
65b1d8ea AK |
4884 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4885 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4886 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4887 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4888 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4889 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 4890 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 4891 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 4892 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
4893 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
4894 | [(set_attr "op_type" "RRF") | |
4895 | (set_attr "type" "ftoi")]) | |
4896 | ||
b60cb710 AK |
4897 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4898 | [(set (match_operand:GPR 0 "register_operand" "") | |
4899 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4900 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4901 | { |
b60cb710 | 4902 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 4903 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 4904 | DONE; |
10bbf137 | 4905 | }) |
9db1d521 | 4906 | |
6e5b5de8 AK |
4907 | (define_insn "*fix_truncdfdi2_bfp_z13" |
4908 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4909 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4910 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4911 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 4912 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4913 | "@ |
4914 | cgdbr\t%0,%h2,%1 | |
4915 | wcgdb\t%v0,%v1,0,%h2" | |
4916 | [(set_attr "op_type" "RRE,VRR") | |
4917 | (set_attr "type" "ftoi")]) | |
4918 | ||
43a09b63 | 4919 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
4920 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4921 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4922 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4923 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 4924 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4925 | "TARGET_HARD_FLOAT |
4926 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 4927 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4928 | [(set_attr "op_type" "RRE") |
077dab3b | 4929 | (set_attr "type" "ftoi")]) |
9db1d521 | 4930 | |
6e5b5de8 AK |
4931 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4932 | [(parallel | |
4933 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4934 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4935 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4936 | (clobber (reg:CC CC_REGNUM))])] | |
4937 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
4938 | ; |
4939 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4940 | ; | |
4941 | ||
99cd7dd0 AK |
4942 | (define_expand "fix_trunc<mode>di2" |
4943 | [(set (match_operand:DI 0 "register_operand" "") | |
4944 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4945 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4946 | { |
4947 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4948 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 4949 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
4950 | DONE; |
4951 | }) | |
4952 | ||
609e7e80 | 4953 | ; cgxtr, cgdtr |
99cd7dd0 | 4954 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4955 | [(set (match_operand:DI 0 "register_operand" "=d") |
4956 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4957 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4958 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4959 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4960 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4961 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4962 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4963 | |
4964 | ||
f61a2c7d AK |
4965 | ; |
4966 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4967 | ; | |
4968 | ||
4969 | (define_expand "fix_trunctf<mode>2" | |
4970 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4971 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 4972 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 4973 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4974 | "TARGET_HARD_FLOAT" |
142cd70f | 4975 | "") |
9db1d521 | 4976 | |
9db1d521 | 4977 | |
9db1d521 | 4978 | ; |
142cd70f | 4979 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4980 | ; |
4981 | ||
609e7e80 | 4982 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4983 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
4984 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
4985 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 4986 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4987 | "@ |
4988 | c<xde>g<bt>r\t%0,%1 | |
4989 | wcdgb\t%v0,%v1,0,0" | |
4990 | [(set_attr "op_type" "RRE,VRR") | |
4991 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 4992 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 4993 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 4994 | |
43a09b63 | 4995 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4996 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4997 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4998 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4999 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
5000 | "c<xde>fbr\t%0,%1" |
5001 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 5002 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 5003 | |
65b1d8ea AK |
5004 | ; cxftr, cdftr |
5005 | (define_insn "floatsi<mode>2" | |
5006 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5007 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5008 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5009 | "c<xde>ftr\t%0,0,%1,0" | |
5010 | [(set_attr "op_type" "RRE") | |
5011 | (set_attr "type" "itof<mode>" )]) | |
5012 | ||
5013 | ; | |
5014 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5015 | ; | |
5016 | ||
6e5b5de8 AK |
5017 | (define_insn "*floatunsdidf2_z13" |
5018 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
5019 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
a579871b | 5020 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5021 | "@ |
5022 | cdlgbr\t%0,0,%1,0 | |
5023 | wcdlgb\t%v0,%v1,0,0" | |
5024 | [(set_attr "op_type" "RRE,VRR") | |
5025 | (set_attr "type" "itofdf")]) | |
5026 | ||
65b1d8ea AK |
5027 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5028 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5029 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5030 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5031 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5032 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5033 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5034 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5035 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5036 | (set_attr "type" "itof<FP:mode>")]) |
5037 | ||
5038 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5039 | [(set (match_operand:FP 0 "register_operand" "") | |
5040 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5041 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5042 | |
9db1d521 HP |
5043 | ; |
5044 | ; truncdfsf2 instruction pattern(s). | |
5045 | ; | |
5046 | ||
142cd70f | 5047 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5048 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5049 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5050 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5051 | "@ |
5052 | ledbr\t%0,%1 | |
5053 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5054 | ; According to BFP rounding mode | |
5055 | [(set_attr "op_type" "RRE,VRR") | |
5056 | (set_attr "type" "ftruncdf") | |
285363a1 | 5057 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5058 | |
f61a2c7d | 5059 | ; |
142cd70f | 5060 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5061 | ; |
5062 | ||
142cd70f AK |
5063 | ; ldxbr, lexbr |
5064 | (define_insn "trunctf<mode>2" | |
5065 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5066 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5067 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5068 | "TARGET_HARD_FLOAT" |
5069 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5070 | [(set_attr "length" "6") |
9381e3f1 | 5071 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5072 | |
609e7e80 AK |
5073 | ; |
5074 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5075 | ; | |
5076 | ||
432d4670 AK |
5077 | |
5078 | (define_expand "trunctddd2" | |
5079 | [(parallel | |
5080 | [(set (match_operand:DD 0 "register_operand" "") | |
5081 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5082 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5083 | (clobber (scratch:TD))])] | |
5084 | "TARGET_HARD_DFP") | |
5085 | ||
5086 | (define_insn "*trunctddd2" | |
609e7e80 | 5087 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5088 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5089 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5090 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5091 | "TARGET_HARD_DFP" |
432d4670 | 5092 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5093 | [(set_attr "length" "6") |
9381e3f1 | 5094 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5095 | |
5096 | (define_insn "truncddsd2" | |
5097 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5098 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5099 | "TARGET_HARD_DFP" |
609e7e80 AK |
5100 | "ledtr\t%0,0,%1,0" |
5101 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5102 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5103 | |
feade5a8 AK |
5104 | (define_expand "trunctdsd2" |
5105 | [(parallel | |
d5a216fa | 5106 | [(set (match_dup 2) |
feade5a8 | 5107 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5108 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5109 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5110 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5111 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5112 | "TARGET_HARD_DFP" |
5113 | { | |
d5a216fa | 5114 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5115 | }) |
5116 | ||
9db1d521 | 5117 | ; |
142cd70f | 5118 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5119 | ; |
5120 | ||
6e5b5de8 AK |
5121 | (define_insn "*extendsfdf2_z13" |
5122 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5123 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5124 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5125 | "@ |
5126 | ldebr\t%0,%1 | |
5127 | ldeb\t%0,%1 | |
5128 | wldeb\t%v0,%v1" | |
5129 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5130 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5131 | ||
142cd70f | 5132 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5133 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5134 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5135 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5136 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5137 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5138 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5139 | "@ |
142cd70f AK |
5140 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5141 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5142 | [(set_attr "op_type" "RRE,RXE") |
5143 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5144 | ||
5145 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5146 | [(set (match_operand:BFP 0 "register_operand" "") | |
5147 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5148 | "TARGET_HARD_FLOAT | |
5149 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5150 | |
609e7e80 AK |
5151 | ; |
5152 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5153 | ; | |
5154 | ||
5155 | (define_insn "extendddtd2" | |
5156 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5157 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5158 | "TARGET_HARD_DFP" |
609e7e80 AK |
5159 | "lxdtr\t%0,%1,0" |
5160 | [(set_attr "op_type" "RRF") | |
5161 | (set_attr "type" "fsimptf")]) | |
5162 | ||
5163 | (define_insn "extendsddd2" | |
5164 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5165 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5166 | "TARGET_HARD_DFP" |
609e7e80 AK |
5167 | "ldetr\t%0,%1,0" |
5168 | [(set_attr "op_type" "RRF") | |
5169 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5170 | |
feade5a8 AK |
5171 | (define_expand "extendsdtd2" |
5172 | [(set (match_dup 2) | |
5173 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5174 | (set (match_operand:TD 0 "register_operand" "") | |
5175 | (float_extend:TD (match_dup 2)))] | |
5176 | "TARGET_HARD_DFP" | |
5177 | { | |
5178 | operands[2] = gen_reg_rtx (DDmode); | |
5179 | }) | |
5180 | ||
d12a76f3 AK |
5181 | ; Binary Floating Point - load fp integer |
5182 | ||
5183 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5184 | ; For all of them the inexact exceptions are suppressed. | |
5185 | ||
5186 | ; fiebra, fidbra, fixbra | |
5187 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5188 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5189 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5190 | FPINT))] | |
5191 | "TARGET_Z196" | |
5192 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5193 | [(set_attr "op_type" "RRF") | |
5194 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5195 | ||
5196 | ; rint is supposed to raise an inexact exception so we can use the | |
5197 | ; older instructions. | |
5198 | ||
5199 | ; fiebr, fidbr, fixbr | |
5200 | (define_insn "rint<BFP:mode>2" | |
5201 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5202 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5203 | UNSPEC_FPINT_RINT))] | |
5204 | "" | |
5205 | "fi<BFP:xde>br\t%0,0,%1" | |
5206 | [(set_attr "op_type" "RRF") | |
5207 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5208 | ||
5209 | ||
5210 | ; Decimal Floating Point - load fp integer | |
5211 | ||
5212 | ; fidtr, fixtr | |
5213 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5214 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5215 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5216 | FPINT))] | |
5217 | "TARGET_HARD_DFP" | |
5218 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5219 | [(set_attr "op_type" "RRF") | |
5220 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5221 | ||
5222 | ; fidtr, fixtr | |
5223 | (define_insn "rint<DFP:mode>2" | |
5224 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5225 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5226 | UNSPEC_FPINT_RINT))] | |
5227 | "TARGET_HARD_DFP" | |
5228 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5229 | [(set_attr "op_type" "RRF") | |
5230 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5231 | ||
5232 | ; | |
35dd9a0e AK |
5233 | ; Binary <-> Decimal floating point trunc patterns |
5234 | ; | |
5235 | ||
5236 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5237 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5238 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5239 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5240 | (clobber (reg:CC CC_REGNUM)) |
5241 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5242 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5243 | "pfpo") |
5244 | ||
5245 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5246 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5247 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5248 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5249 | (clobber (reg:CC CC_REGNUM)) |
5250 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5251 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5252 | "pfpo") |
5253 | ||
5254 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5255 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5256 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5257 | (parallel | |
5258 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5259 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5260 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5261 | (clobber (reg:CC CC_REGNUM)) |
5262 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5263 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5264 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5265 | "TARGET_HARD_DFP |
35dd9a0e AK |
5266 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5267 | { | |
5268 | HOST_WIDE_INT flags; | |
5269 | ||
5270 | flags = (PFPO_CONVERT | | |
5271 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5272 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5273 | ||
5274 | operands[2] = GEN_INT (flags); | |
5275 | }) | |
5276 | ||
5277 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5278 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5279 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5280 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5281 | (parallel | |
2cf4c39e | 5282 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5283 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5284 | (clobber (reg:CC CC_REGNUM)) |
5285 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5286 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5287 | "TARGET_HARD_DFP |
35dd9a0e AK |
5288 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5289 | { | |
5290 | HOST_WIDE_INT flags; | |
5291 | ||
5292 | flags = (PFPO_CONVERT | | |
5293 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5294 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5295 | ||
5296 | operands[2] = GEN_INT (flags); | |
5297 | }) | |
5298 | ||
5299 | ; | |
5300 | ; Binary <-> Decimal floating point extend patterns | |
5301 | ; | |
5302 | ||
5303 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5304 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5305 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5306 | (clobber (reg:CC CC_REGNUM)) |
5307 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5308 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5309 | "pfpo") |
5310 | ||
5311 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5312 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5313 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5314 | (clobber (reg:CC CC_REGNUM)) |
5315 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5316 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5317 | "pfpo") |
5318 | ||
5319 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5320 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5321 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5322 | (parallel | |
5323 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5324 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5325 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5326 | (clobber (reg:CC CC_REGNUM)) |
5327 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5328 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5329 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5330 | "TARGET_HARD_DFP |
35dd9a0e AK |
5331 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5332 | { | |
5333 | HOST_WIDE_INT flags; | |
5334 | ||
5335 | flags = (PFPO_CONVERT | | |
5336 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5337 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5338 | ||
5339 | operands[2] = GEN_INT (flags); | |
5340 | }) | |
5341 | ||
5342 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5343 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5344 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5345 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5346 | (parallel | |
2cf4c39e | 5347 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5348 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5349 | (clobber (reg:CC CC_REGNUM)) |
5350 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5351 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5352 | "TARGET_HARD_DFP |
35dd9a0e AK |
5353 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5354 | { | |
5355 | HOST_WIDE_INT flags; | |
5356 | ||
5357 | flags = (PFPO_CONVERT | | |
5358 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5359 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5360 | ||
5361 | operands[2] = GEN_INT (flags); | |
5362 | }) | |
5363 | ||
5364 | ||
9db1d521 | 5365 | ;; |
fae778eb | 5366 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5367 | ;; |
fae778eb | 5368 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5369 | ; because of unpredictable Bits in Register for Halfword and Byte |
5370 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5371 | ||
07893d4f UW |
5372 | ;; |
5373 | ;;- Add instructions. | |
5374 | ;; | |
5375 | ||
1c7b1b7e UW |
5376 | ; |
5377 | ; addti3 instruction pattern(s). | |
5378 | ; | |
5379 | ||
085261c8 AK |
5380 | (define_expand "addti3" |
5381 | [(parallel | |
5382 | [(set (match_operand:TI 0 "register_operand" "") | |
5383 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5384 | (match_operand:TI 2 "general_operand" "") ) ) | |
5385 | (clobber (reg:CC CC_REGNUM))])] | |
5386 | "TARGET_ZARCH" | |
5387 | { | |
5388 | /* For z13 we have vaq which doesn't set CC. */ | |
5389 | if (TARGET_VX) | |
5390 | { | |
5391 | emit_insn (gen_rtx_SET (operands[0], | |
5392 | gen_rtx_PLUS (TImode, | |
5393 | copy_to_mode_reg (TImode, operands[1]), | |
5394 | copy_to_mode_reg (TImode, operands[2])))); | |
5395 | DONE; | |
5396 | } | |
5397 | }) | |
5398 | ||
5399 | (define_insn_and_split "*addti3" | |
5400 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5401 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5402 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5403 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5404 | "TARGET_ZARCH" |
1c7b1b7e UW |
5405 | "#" |
5406 | "&& reload_completed" | |
5407 | [(parallel | |
ae156f85 | 5408 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5409 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5410 | (match_dup 7))) | |
5411 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5412 | (parallel | |
a94a76a7 UW |
5413 | [(set (match_dup 3) (plus:DI |
5414 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5415 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5416 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5417 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5418 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5419 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5420 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5421 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5422 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5423 | [(set_attr "op_type" "*") | |
5424 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5425 | |
07893d4f UW |
5426 | ; |
5427 | ; adddi3 instruction pattern(s). | |
5428 | ; | |
5429 | ||
3298c037 AK |
5430 | (define_expand "adddi3" |
5431 | [(parallel | |
963fc8d0 | 5432 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5433 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5434 | (match_operand:DI 2 "general_operand" ""))) | |
5435 | (clobber (reg:CC CC_REGNUM))])] | |
5436 | "" | |
5437 | "") | |
5438 | ||
07893d4f UW |
5439 | (define_insn "*adddi3_sign" |
5440 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5441 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5442 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5443 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5444 | "TARGET_ZARCH" |
07893d4f | 5445 | "@ |
d40c829f UW |
5446 | agfr\t%0,%2 |
5447 | agf\t%0,%2" | |
65b1d8ea AK |
5448 | [(set_attr "op_type" "RRE,RXY") |
5449 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5450 | |
5451 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5452 | [(set (reg CC_REGNUM) |
3e4be43f | 5453 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5454 | (match_operand:DI 1 "register_operand" "0,0")) |
5455 | (const_int 0))) | |
5456 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5457 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5458 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5459 | "@ |
d40c829f UW |
5460 | algfr\t%0,%2 |
5461 | algf\t%0,%2" | |
9381e3f1 WG |
5462 | [(set_attr "op_type" "RRE,RXY") |
5463 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5464 | |
5465 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5466 | [(set (reg CC_REGNUM) |
3e4be43f | 5467 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5468 | (match_operand:DI 1 "register_operand" "0,0")) |
5469 | (const_int 0))) | |
5470 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5471 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5472 | "@ |
d40c829f UW |
5473 | algfr\t%0,%2 |
5474 | algf\t%0,%2" | |
9381e3f1 WG |
5475 | [(set_attr "op_type" "RRE,RXY") |
5476 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5477 | |
5478 | (define_insn "*adddi3_zero" | |
5479 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5480 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5481 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5482 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5483 | "TARGET_ZARCH" |
07893d4f | 5484 | "@ |
d40c829f UW |
5485 | algfr\t%0,%2 |
5486 | algf\t%0,%2" | |
9381e3f1 WG |
5487 | [(set_attr "op_type" "RRE,RXY") |
5488 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5489 | |
e69166de | 5490 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5491 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5492 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5493 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5494 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5495 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5496 | "#" |
5497 | "&& reload_completed" | |
5498 | [(parallel | |
ae156f85 | 5499 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5500 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5501 | (match_dup 7))) | |
5502 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5503 | (parallel | |
a94a76a7 UW |
5504 | [(set (match_dup 3) (plus:SI |
5505 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5506 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5507 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5508 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5509 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5510 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5511 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5512 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5513 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5514 | |
07893d4f | 5515 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 5516 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 5517 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 5518 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5519 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5520 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5521 | "#" |
5522 | "&& reload_completed" | |
5523 | [(parallel | |
5524 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5525 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5526 | (parallel |
ae156f85 | 5527 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
5528 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5529 | (match_dup 7))) | |
5530 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5531 | (set (pc) | |
ae156f85 | 5532 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5533 | (pc) |
5534 | (label_ref (match_dup 9)))) | |
5535 | (parallel | |
5536 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 5537 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5538 | (match_dup 9)] |
97c6f7ad UW |
5539 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5540 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5541 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5542 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5543 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5544 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5545 | operands[9] = gen_label_rtx ();") |
9db1d521 | 5546 | |
3298c037 AK |
5547 | ; |
5548 | ; addsi3 instruction pattern(s). | |
5549 | ; | |
5550 | ||
5551 | (define_expand "addsi3" | |
07893d4f | 5552 | [(parallel |
963fc8d0 | 5553 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5554 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5555 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5556 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5557 | "" |
07893d4f | 5558 | "") |
9db1d521 | 5559 | |
3298c037 AK |
5560 | (define_insn "*addsi3_sign" |
5561 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5562 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5563 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5564 | (clobber (reg:CC CC_REGNUM))] | |
5565 | "" | |
5566 | "@ | |
5567 | ah\t%0,%2 | |
5568 | ahy\t%0,%2" | |
65b1d8ea | 5569 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5570 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5571 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5572 | |
9db1d521 | 5573 | ; |
3298c037 | 5574 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5575 | ; |
9db1d521 | 5576 | |
65b1d8ea | 5577 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5578 | (define_insn "*add<mode>3" |
3e4be43f UW |
5579 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5580 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5581 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5582 | (clobber (reg:CC CC_REGNUM))] |
5583 | "" | |
ec24698e | 5584 | "@ |
3298c037 | 5585 | a<g>r\t%0,%2 |
65b1d8ea | 5586 | a<g>rk\t%0,%1,%2 |
3298c037 | 5587 | a<g>hi\t%0,%h2 |
65b1d8ea | 5588 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5589 | al<g>fi\t%0,%2 |
5590 | sl<g>fi\t%0,%n2 | |
5591 | a<g>\t%0,%2 | |
963fc8d0 AK |
5592 | a<y>\t%0,%2 |
5593 | a<g>si\t%0,%c2" | |
65b1d8ea | 5594 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5595 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5596 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5597 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5598 | |
65b1d8ea | 5599 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5600 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5601 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5602 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5603 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5604 | (match_dup 1))) |
65b1d8ea | 5605 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5606 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5607 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5608 | "@ |
3298c037 | 5609 | al<g>r\t%0,%2 |
65b1d8ea | 5610 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5611 | al<g>fi\t%0,%2 |
5612 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5613 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5614 | al<g>\t%0,%2 |
963fc8d0 AK |
5615 | al<y>\t%0,%2 |
5616 | al<g>si\t%0,%c2" | |
65b1d8ea | 5617 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5618 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5619 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5620 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5621 | |
65b1d8ea | 5622 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5623 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5624 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5625 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5626 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5627 | (match_dup 1))) |
65b1d8ea | 5628 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5629 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5630 | "@ |
3298c037 | 5631 | al<g>r\t%0,%2 |
65b1d8ea | 5632 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5633 | al<g>\t%0,%2 |
5634 | al<y>\t%0,%2" | |
65b1d8ea | 5635 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5636 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5637 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5638 | |
65b1d8ea | 5639 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5640 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5641 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5642 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5643 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5644 | (match_dup 2))) |
3e4be43f | 5645 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5646 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5647 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5648 | "@ |
3298c037 | 5649 | al<g>r\t%0,%2 |
65b1d8ea | 5650 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5651 | al<g>fi\t%0,%2 |
5652 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5653 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5654 | al<g>\t%0,%2 |
963fc8d0 AK |
5655 | al<y>\t%0,%2 |
5656 | al<g>si\t%0,%c2" | |
65b1d8ea | 5657 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5658 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5659 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5660 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5661 | |
65b1d8ea | 5662 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5663 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5664 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5665 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5666 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5667 | (match_dup 2))) |
65b1d8ea | 5668 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5669 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5670 | "@ |
3298c037 | 5671 | al<g>r\t%0,%2 |
65b1d8ea | 5672 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5673 | al<g>\t%0,%2 |
5674 | al<y>\t%0,%2" | |
65b1d8ea | 5675 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5676 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5677 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5678 | |
65b1d8ea | 5679 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5680 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5681 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5682 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5683 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5684 | (const_int 0))) |
3e4be43f | 5685 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5686 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5687 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5688 | "@ |
3298c037 | 5689 | al<g>r\t%0,%2 |
65b1d8ea | 5690 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5691 | al<g>fi\t%0,%2 |
5692 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5693 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5694 | al<g>\t%0,%2 |
963fc8d0 AK |
5695 | al<y>\t%0,%2 |
5696 | al<g>si\t%0,%c2" | |
65b1d8ea | 5697 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5698 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5699 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5700 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5701 | |
65b1d8ea | 5702 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5703 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5704 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5705 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5706 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5707 | (const_int 0))) |
65b1d8ea | 5708 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5709 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5710 | "@ |
3298c037 | 5711 | al<g>r\t%0,%2 |
65b1d8ea | 5712 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5713 | al<g>\t%0,%2 |
5714 | al<y>\t%0,%2" | |
65b1d8ea | 5715 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5716 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5717 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5718 | |
65b1d8ea | 5719 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5720 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5721 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5722 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5723 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5724 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5725 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5726 | "@ |
3298c037 | 5727 | al<g>r\t%0,%2 |
65b1d8ea | 5728 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5729 | al<g>\t%0,%2 |
5730 | al<y>\t%0,%2" | |
65b1d8ea | 5731 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5732 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5733 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5734 | |
963fc8d0 | 5735 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5736 | (define_insn "*add<mode>3_imm_cc" |
5737 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5738 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5739 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5740 | (const_int 0))) |
3e4be43f | 5741 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5742 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5743 | "s390_match_ccmode (insn, CCAmode) | |
5744 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5745 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5746 | /* Avoid INT32_MIN on 32 bit. */ | |
5747 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5748 | "@ |
3298c037 | 5749 | a<g>hi\t%0,%h2 |
65b1d8ea | 5750 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5751 | a<g>fi\t%0,%2 |
5752 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5753 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5754 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5755 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5756 | |
9db1d521 | 5757 | ; |
609e7e80 | 5758 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5759 | ; |
5760 | ||
609e7e80 | 5761 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5762 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5763 | (define_insn "add<mode>3" |
62d3f261 AK |
5764 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
5765 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") | |
5766 | (match_operand:FP 2 "general_operand" "f,f,R,v"))) | |
ae156f85 | 5767 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5768 | "TARGET_HARD_FLOAT" |
9db1d521 | 5769 | "@ |
62d3f261 AK |
5770 | a<xde>tr\t%0,%1,%2 |
5771 | a<xde>br\t%0,%2 | |
6e5b5de8 AK |
5772 | a<xde>b\t%0,%2 |
5773 | wfadb\t%v0,%v1,%v2" | |
62d3f261 | 5774 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 5775 | (set_attr "type" "fsimp<mode>") |
285363a1 | 5776 | (set_attr "cpu_facility" "*,*,*,vx") |
62d3f261 | 5777 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) |
9db1d521 | 5778 | |
609e7e80 | 5779 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5780 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5781 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5782 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5783 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5784 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5785 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5786 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5787 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5788 | "@ |
62d3f261 AK |
5789 | a<xde>tr\t%0,%1,%2 |
5790 | a<xde>br\t%0,%2 | |
f61a2c7d | 5791 | a<xde>b\t%0,%2" |
62d3f261 AK |
5792 | [(set_attr "op_type" "RRF,RRE,RXE") |
5793 | (set_attr "type" "fsimp<mode>") | |
5794 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5795 | |
609e7e80 | 5796 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5797 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5798 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5799 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5800 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5801 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5802 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5803 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5804 | "@ |
62d3f261 AK |
5805 | a<xde>tr\t%0,%1,%2 |
5806 | a<xde>br\t%0,%2 | |
f61a2c7d | 5807 | a<xde>b\t%0,%2" |
62d3f261 AK |
5808 | [(set_attr "op_type" "RRF,RRE,RXE") |
5809 | (set_attr "type" "fsimp<mode>") | |
5810 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5811 | |
72a4ddf2 AK |
5812 | ; |
5813 | ; Pointer add instruction patterns | |
5814 | ; | |
5815 | ||
5816 | ; This will match "*la_64" | |
5817 | (define_expand "addptrdi3" | |
5818 | [(set (match_operand:DI 0 "register_operand" "") | |
5819 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5820 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5821 | "TARGET_64BIT" | |
5822 | { | |
72a4ddf2 AK |
5823 | if (GET_CODE (operands[2]) == CONST_INT) |
5824 | { | |
357ddc7d TV |
5825 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5826 | ||
72a4ddf2 AK |
5827 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5828 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5829 | { | |
5830 | operands[2] = force_const_mem (DImode, operands[2]); | |
5831 | operands[2] = force_reg (DImode, operands[2]); | |
5832 | } | |
5833 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5834 | operands[2] = force_reg (DImode, operands[2]); | |
5835 | } | |
5836 | }) | |
5837 | ||
5838 | ; For 31 bit we have to prevent the generated pattern from matching | |
5839 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5840 | ; match "force_la_31". | |
5841 | (define_expand "addptrsi3" | |
5842 | [(parallel | |
5843 | [(set (match_operand:SI 0 "register_operand" "") | |
5844 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5845 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5846 | (use (const_int 0))])] | |
5847 | "!TARGET_64BIT" | |
5848 | { | |
72a4ddf2 AK |
5849 | if (GET_CODE (operands[2]) == CONST_INT) |
5850 | { | |
357ddc7d TV |
5851 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5852 | ||
72a4ddf2 AK |
5853 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5854 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5855 | { | |
5856 | operands[2] = force_const_mem (SImode, operands[2]); | |
5857 | operands[2] = force_reg (SImode, operands[2]); | |
5858 | } | |
5859 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5860 | operands[2] = force_reg (SImode, operands[2]); | |
5861 | } | |
5862 | }) | |
9db1d521 HP |
5863 | |
5864 | ;; | |
5865 | ;;- Subtract instructions. | |
5866 | ;; | |
5867 | ||
1c7b1b7e UW |
5868 | ; |
5869 | ; subti3 instruction pattern(s). | |
5870 | ; | |
5871 | ||
085261c8 AK |
5872 | (define_expand "subti3" |
5873 | [(parallel | |
5874 | [(set (match_operand:TI 0 "register_operand" "") | |
5875 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5876 | (match_operand:TI 2 "general_operand" "") ) ) | |
5877 | (clobber (reg:CC CC_REGNUM))])] | |
5878 | "TARGET_ZARCH" | |
5879 | { | |
2d71f118 | 5880 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
5881 | if (TARGET_VX) |
5882 | { | |
5883 | emit_insn (gen_rtx_SET (operands[0], | |
5884 | gen_rtx_MINUS (TImode, | |
5885 | operands[1], | |
5886 | copy_to_mode_reg (TImode, operands[2])))); | |
5887 | DONE; | |
5888 | } | |
5889 | }) | |
5890 | ||
5891 | (define_insn_and_split "*subti3" | |
5892 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
5893 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
5894 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 5895 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5896 | "TARGET_ZARCH" |
1c7b1b7e UW |
5897 | "#" |
5898 | "&& reload_completed" | |
5899 | [(parallel | |
ae156f85 | 5900 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
5901 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
5902 | (match_dup 7))) | |
5903 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
5904 | (parallel | |
5905 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5906 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5907 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
5908 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5909 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5910 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5911 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5912 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5913 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5914 | [(set_attr "op_type" "*") | |
5915 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5916 | |
9db1d521 HP |
5917 | ; |
5918 | ; subdi3 instruction pattern(s). | |
5919 | ; | |
5920 | ||
3298c037 AK |
5921 | (define_expand "subdi3" |
5922 | [(parallel | |
5923 | [(set (match_operand:DI 0 "register_operand" "") | |
5924 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
5925 | (match_operand:DI 2 "general_operand" ""))) | |
5926 | (clobber (reg:CC CC_REGNUM))])] | |
5927 | "" | |
5928 | "") | |
5929 | ||
07893d4f UW |
5930 | (define_insn "*subdi3_sign" |
5931 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5932 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 5933 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 5934 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5935 | "TARGET_ZARCH" |
07893d4f | 5936 | "@ |
d40c829f UW |
5937 | sgfr\t%0,%2 |
5938 | sgf\t%0,%2" | |
9381e3f1 | 5939 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
5940 | (set_attr "z10prop" "z10_c,*") |
5941 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
5942 | |
5943 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 5944 | [(set (reg CC_REGNUM) |
07893d4f | 5945 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 5946 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
5947 | (const_int 0))) |
5948 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5949 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 5950 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5951 | "@ |
d40c829f UW |
5952 | slgfr\t%0,%2 |
5953 | slgf\t%0,%2" | |
9381e3f1 WG |
5954 | [(set_attr "op_type" "RRE,RXY") |
5955 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5956 | |
5957 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 5958 | [(set (reg CC_REGNUM) |
07893d4f | 5959 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 5960 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
5961 | (const_int 0))) |
5962 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5963 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5964 | "@ |
d40c829f UW |
5965 | slgfr\t%0,%2 |
5966 | slgf\t%0,%2" | |
9381e3f1 WG |
5967 | [(set_attr "op_type" "RRE,RXY") |
5968 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5969 | |
5970 | (define_insn "*subdi3_zero" | |
5971 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5972 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 5973 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 5974 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5975 | "TARGET_ZARCH" |
07893d4f | 5976 | "@ |
d40c829f UW |
5977 | slgfr\t%0,%2 |
5978 | slgf\t%0,%2" | |
9381e3f1 WG |
5979 | [(set_attr "op_type" "RRE,RXY") |
5980 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 5981 | |
e69166de UW |
5982 | (define_insn_and_split "*subdi3_31z" |
5983 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5984 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
5985 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5986 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5987 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5988 | "#" |
5989 | "&& reload_completed" | |
5990 | [(parallel | |
ae156f85 | 5991 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
5992 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5993 | (match_dup 7))) | |
5994 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5995 | (parallel | |
5996 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5997 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5998 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
5999 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6000 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6001 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6002 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6003 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6004 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6005 | |
07893d4f UW |
6006 | (define_insn_and_split "*subdi3_31" |
6007 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6008 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 6009 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 6010 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 6011 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
6012 | "#" |
6013 | "&& reload_completed" | |
6014 | [(parallel | |
6015 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 6016 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 6017 | (parallel |
ae156f85 | 6018 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
6019 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6020 | (match_dup 7))) | |
6021 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6022 | (set (pc) | |
ae156f85 | 6023 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
6024 | (pc) |
6025 | (label_ref (match_dup 9)))) | |
6026 | (parallel | |
6027 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 6028 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 6029 | (match_dup 9)] |
97c6f7ad UW |
6030 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6031 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6032 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6033 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6034 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
6035 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 6036 | operands[9] = gen_label_rtx ();") |
07893d4f | 6037 | |
3298c037 AK |
6038 | ; |
6039 | ; subsi3 instruction pattern(s). | |
6040 | ; | |
6041 | ||
6042 | (define_expand "subsi3" | |
07893d4f | 6043 | [(parallel |
3298c037 AK |
6044 | [(set (match_operand:SI 0 "register_operand" "") |
6045 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6046 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6047 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6048 | "" |
07893d4f | 6049 | "") |
9db1d521 | 6050 | |
3298c037 AK |
6051 | (define_insn "*subsi3_sign" |
6052 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6053 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6054 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6055 | (clobber (reg:CC CC_REGNUM))] | |
6056 | "" | |
6057 | "@ | |
6058 | sh\t%0,%2 | |
6059 | shy\t%0,%2" | |
65b1d8ea | 6060 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6061 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6062 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6063 | |
9db1d521 | 6064 | ; |
3298c037 | 6065 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6066 | ; |
6067 | ||
65b1d8ea | 6068 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6069 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6070 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6071 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6072 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6073 | (clobber (reg:CC CC_REGNUM))] |
6074 | "" | |
6075 | "@ | |
6076 | s<g>r\t%0,%2 | |
65b1d8ea | 6077 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6078 | s<g>\t%0,%2 |
6079 | s<y>\t%0,%2" | |
65b1d8ea | 6080 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6081 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6082 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6083 | |
65b1d8ea | 6084 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6085 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6086 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6087 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6088 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6089 | (match_dup 1))) |
65b1d8ea | 6090 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6091 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6092 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6093 | "@ |
3298c037 | 6094 | sl<g>r\t%0,%2 |
65b1d8ea | 6095 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6096 | sl<g>\t%0,%2 |
6097 | sl<y>\t%0,%2" | |
65b1d8ea | 6098 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6099 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6100 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6101 | |
65b1d8ea | 6102 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6103 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6104 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6105 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6106 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6107 | (match_dup 1))) |
65b1d8ea | 6108 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6109 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6110 | "@ |
3298c037 | 6111 | sl<g>r\t%0,%2 |
65b1d8ea | 6112 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6113 | sl<g>\t%0,%2 |
6114 | sl<y>\t%0,%2" | |
65b1d8ea | 6115 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6116 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6117 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6118 | |
65b1d8ea | 6119 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6120 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6121 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6122 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6123 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6124 | (const_int 0))) |
65b1d8ea | 6125 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6126 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6127 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6128 | "@ |
3298c037 | 6129 | sl<g>r\t%0,%2 |
65b1d8ea | 6130 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6131 | sl<g>\t%0,%2 |
6132 | sl<y>\t%0,%2" | |
65b1d8ea | 6133 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6134 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6135 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6136 | |
65b1d8ea | 6137 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6138 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6139 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6140 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6141 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6142 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6143 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6144 | "s390_match_ccmode (insn, CCL3mode)" |
6145 | "@ | |
3298c037 | 6146 | sl<g>r\t%0,%2 |
65b1d8ea | 6147 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6148 | sl<g>\t%0,%2 |
6149 | sl<y>\t%0,%2" | |
65b1d8ea | 6150 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6151 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6152 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6153 | |
65b1d8ea | 6154 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6155 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6156 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6157 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6158 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6159 | (const_int 0))) |
65b1d8ea | 6160 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6161 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6162 | "@ |
3298c037 | 6163 | sl<g>r\t%0,%2 |
65b1d8ea | 6164 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6165 | sl<g>\t%0,%2 |
6166 | sl<y>\t%0,%2" | |
65b1d8ea | 6167 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6168 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6169 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6170 | |
9db1d521 | 6171 | |
65b1d8ea | 6172 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6173 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6174 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6175 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6176 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6177 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6178 | "s390_match_ccmode (insn, CCL3mode)" |
6179 | "@ | |
3298c037 | 6180 | sl<g>r\t%0,%2 |
65b1d8ea | 6181 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6182 | sl<g>\t%0,%2 |
6183 | sl<y>\t%0,%2" | |
65b1d8ea | 6184 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6185 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6186 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6187 | |
9db1d521 HP |
6188 | |
6189 | ; | |
609e7e80 | 6190 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6191 | ; |
6192 | ||
d46f24b6 | 6193 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6194 | (define_insn "sub<mode>3" |
62d3f261 AK |
6195 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
6196 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v") | |
6197 | (match_operand:FP 2 "general_operand" "f,f,R,v"))) | |
ae156f85 | 6198 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6199 | "TARGET_HARD_FLOAT" |
9db1d521 | 6200 | "@ |
62d3f261 AK |
6201 | s<xde>tr\t%0,%1,%2 |
6202 | s<xde>br\t%0,%2 | |
6e5b5de8 AK |
6203 | s<xde>b\t%0,%2 |
6204 | wfsdb\t%v0,%v1,%v2" | |
62d3f261 | 6205 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 6206 | (set_attr "type" "fsimp<mode>") |
285363a1 | 6207 | (set_attr "cpu_facility" "*,*,*,vx") |
62d3f261 | 6208 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) |
9db1d521 | 6209 | |
d46f24b6 | 6210 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6211 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6212 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6213 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6214 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6215 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6216 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6217 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6218 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6219 | "@ |
62d3f261 AK |
6220 | s<xde>tr\t%0,%1,%2 |
6221 | s<xde>br\t%0,%2 | |
f61a2c7d | 6222 | s<xde>b\t%0,%2" |
62d3f261 AK |
6223 | [(set_attr "op_type" "RRF,RRE,RXE") |
6224 | (set_attr "type" "fsimp<mode>") | |
6225 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6226 | |
d46f24b6 | 6227 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6228 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6229 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6230 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6231 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6232 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6233 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6234 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6235 | "@ |
62d3f261 AK |
6236 | s<xde>tr\t%0,%1,%2 |
6237 | s<xde>br\t%0,%2 | |
f61a2c7d | 6238 | s<xde>b\t%0,%2" |
62d3f261 AK |
6239 | [(set_attr "op_type" "RRF,RRE,RXE") |
6240 | (set_attr "type" "fsimp<mode>") | |
6241 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6242 | |
9db1d521 | 6243 | |
e69166de UW |
6244 | ;; |
6245 | ;;- Conditional add/subtract instructions. | |
6246 | ;; | |
6247 | ||
6248 | ; | |
9a91a21f | 6249 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6250 | ; |
6251 | ||
a996720c UW |
6252 | ; the following 4 patterns are used when the result of an add with |
6253 | ; carry is checked for an overflow condition | |
6254 | ||
6255 | ; op1 + op2 + c < op1 | |
6256 | ||
6257 | ; alcr, alc, alcgr, alcg | |
6258 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6259 | [(set (reg CC_REGNUM) | |
6260 | (compare | |
6261 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6262 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6263 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6264 | (match_dup 1))) |
6265 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6266 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6267 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6268 | "@ | |
6269 | alc<g>r\t%0,%2 | |
6270 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6271 | [(set_attr "op_type" "RRE,RXY") |
6272 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6273 | |
6274 | ; alcr, alc, alcgr, alcg | |
6275 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6276 | [(set (reg CC_REGNUM) | |
6277 | (compare | |
6278 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6279 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6280 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6281 | (match_dup 1))) |
6282 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6283 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6284 | "@ | |
6285 | alc<g>r\t%0,%2 | |
6286 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6287 | [(set_attr "op_type" "RRE,RXY") |
6288 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6289 | |
6290 | ; op1 + op2 + c < op2 | |
6291 | ||
6292 | ; alcr, alc, alcgr, alcg | |
6293 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6294 | [(set (reg CC_REGNUM) | |
6295 | (compare | |
6296 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6297 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6298 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6299 | (match_dup 2))) |
6300 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6301 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6302 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6303 | "@ | |
6304 | alc<g>r\t%0,%2 | |
6305 | alc<g>\t%0,%2" | |
6306 | [(set_attr "op_type" "RRE,RXY")]) | |
6307 | ||
6308 | ; alcr, alc, alcgr, alcg | |
6309 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6310 | [(set (reg CC_REGNUM) | |
6311 | (compare | |
6312 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6313 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6314 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6315 | (match_dup 2))) |
6316 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6317 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6318 | "@ | |
6319 | alc<g>r\t%0,%2 | |
6320 | alc<g>\t%0,%2" | |
6321 | [(set_attr "op_type" "RRE,RXY")]) | |
6322 | ||
43a09b63 | 6323 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6324 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6325 | [(set (reg CC_REGNUM) |
e69166de | 6326 | (compare |
a94a76a7 UW |
6327 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6328 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6329 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6330 | (const_int 0))) |
9a91a21f | 6331 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6332 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 6333 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6334 | "@ |
9a91a21f AS |
6335 | alc<g>r\t%0,%2 |
6336 | alc<g>\t%0,%2" | |
e69166de UW |
6337 | [(set_attr "op_type" "RRE,RXY")]) |
6338 | ||
43a09b63 | 6339 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6340 | (define_insn "*add<mode>3_alc" |
6341 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6342 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6343 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6344 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6345 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6346 | "TARGET_CPU_ZARCH" |
e69166de | 6347 | "@ |
9a91a21f AS |
6348 | alc<g>r\t%0,%2 |
6349 | alc<g>\t%0,%2" | |
e69166de UW |
6350 | [(set_attr "op_type" "RRE,RXY")]) |
6351 | ||
43a09b63 | 6352 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6353 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6354 | [(set (reg CC_REGNUM) |
e69166de | 6355 | (compare |
9a91a21f | 6356 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6357 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6358 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6359 | (const_int 0))) |
9a91a21f AS |
6360 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6361 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 6362 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6363 | "@ |
9a91a21f AS |
6364 | slb<g>r\t%0,%2 |
6365 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6366 | [(set_attr "op_type" "RRE,RXY") |
6367 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6368 | |
43a09b63 | 6369 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6370 | (define_insn "*sub<mode>3_slb" |
6371 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6372 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6373 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6374 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6375 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6376 | "TARGET_CPU_ZARCH" |
e69166de | 6377 | "@ |
9a91a21f AS |
6378 | slb<g>r\t%0,%2 |
6379 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6380 | [(set_attr "op_type" "RRE,RXY") |
6381 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6382 | |
9a91a21f AS |
6383 | (define_expand "add<mode>cc" |
6384 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6385 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6386 | (match_operand:GPR 2 "register_operand" "") |
6387 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 6388 | "TARGET_CPU_ZARCH" |
9381e3f1 | 6389 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6390 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6391 | operands[0], operands[2], |
5d880bd2 UW |
6392 | operands[3])) FAIL; DONE;") |
6393 | ||
6394 | ; | |
6395 | ; scond instruction pattern(s). | |
6396 | ; | |
6397 | ||
9a91a21f AS |
6398 | (define_insn_and_split "*scond<mode>" |
6399 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6400 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6401 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6402 | "TARGET_CPU_ZARCH" |
6403 | "#" | |
6404 | "&& reload_completed" | |
6405 | [(set (match_dup 0) (const_int 0)) | |
6406 | (parallel | |
a94a76a7 UW |
6407 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6408 | (match_dup 0))) | |
ae156f85 | 6409 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6410 | "") |
5d880bd2 | 6411 | |
9a91a21f AS |
6412 | (define_insn_and_split "*scond<mode>_neg" |
6413 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6414 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6415 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6416 | "TARGET_CPU_ZARCH" |
6417 | "#" | |
6418 | "&& reload_completed" | |
6419 | [(set (match_dup 0) (const_int 0)) | |
6420 | (parallel | |
9a91a21f AS |
6421 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6422 | (match_dup 1))) | |
ae156f85 | 6423 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6424 | (parallel |
9a91a21f | 6425 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6426 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6427 | "") |
5d880bd2 | 6428 | |
5d880bd2 | 6429 | |
f90b7a5a | 6430 | (define_expand "cstore<mode>4" |
9a91a21f | 6431 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6432 | (match_operator:SI 1 "s390_scond_operator" |
6433 | [(match_operand:GPR 2 "register_operand" "") | |
6434 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 6435 | "TARGET_CPU_ZARCH" |
f90b7a5a | 6436 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6437 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6438 | ||
f90b7a5a | 6439 | (define_expand "cstorecc4" |
69950452 | 6440 | [(parallel |
f90b7a5a PB |
6441 | [(set (match_operand:SI 0 "register_operand" "") |
6442 | (match_operator:SI 1 "s390_eqne_operator" | |
6443 | [(match_operand:CCZ1 2 "register_operand") | |
6444 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
6445 | (clobber (reg:CC CC_REGNUM))])] |
6446 | "" | |
f90b7a5a PB |
6447 | "emit_insn (gen_sne (operands[0], operands[2])); |
6448 | if (GET_CODE (operands[1]) == EQ) | |
6449 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6450 | DONE;") | |
69950452 | 6451 | |
f90b7a5a | 6452 | (define_insn_and_split "sne" |
69950452 | 6453 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6454 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6455 | (const_int 0))) |
6456 | (clobber (reg:CC CC_REGNUM))] | |
6457 | "" | |
6458 | "#" | |
6459 | "reload_completed" | |
6460 | [(parallel | |
6461 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6462 | (clobber (reg:CC CC_REGNUM))])]) | |
6463 | ||
e69166de | 6464 | |
65b1d8ea AK |
6465 | ;; |
6466 | ;; - Conditional move instructions (introduced with z196) | |
6467 | ;; | |
6468 | ||
6469 | (define_expand "mov<mode>cc" | |
6470 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6471 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6472 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6473 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6474 | "TARGET_Z196" | |
7477de01 AK |
6475 | { |
6476 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6477 | if (!s390_comparison (operands[1], VOIDmode)) | |
6478 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6479 | XEXP (operands[1], 0), | |
6480 | XEXP (operands[1], 1)); | |
6481 | }) | |
65b1d8ea | 6482 | |
bf749919 | 6483 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi |
65b1d8ea | 6484 | (define_insn_and_split "*mov<mode>cc" |
bf749919 | 6485 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S,&d") |
65b1d8ea AK |
6486 | (if_then_else:GPR |
6487 | (match_operator 1 "s390_comparison" | |
bf749919 | 6488 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c") |
5a3fe9b6 | 6489 | (match_operand 5 "const_int_operand" "")]) |
bf749919 DV |
6490 | (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S") |
6491 | (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))] | |
65b1d8ea AK |
6492 | "TARGET_Z196" |
6493 | "@ | |
6494 | loc<g>r%C1\t%0,%3 | |
6495 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6496 | loc<g>%C1\t%0,%3 |
6497 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6498 | loc<g>hi%C1\t%0,%h3 |
6499 | loc<g>hi%D1\t%0,%h4 | |
a6510374 AK |
6500 | stoc<g>%C1\t%3,%0 |
6501 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
6502 | #" |
6503 | "&& reload_completed | |
6504 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
6505 | [(set (match_dup 0) | |
6506 | (if_then_else:GPR | |
6507 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6508 | (match_dup 3) | |
6509 | (match_dup 0))) | |
6510 | (set (match_dup 0) | |
6511 | (if_then_else:GPR | |
6512 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6513 | (match_dup 0) | |
6514 | (match_dup 4)))] | |
6515 | "" | |
bf749919 DV |
6516 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*") |
6517 | (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")]) | |
65b1d8ea | 6518 | |
9db1d521 HP |
6519 | ;; |
6520 | ;;- Multiply instructions. | |
6521 | ;; | |
6522 | ||
4023fb28 UW |
6523 | ; |
6524 | ; muldi3 instruction pattern(s). | |
6525 | ; | |
9db1d521 | 6526 | |
07893d4f UW |
6527 | (define_insn "*muldi3_sign" |
6528 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6529 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6530 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6531 | "TARGET_ZARCH" |
07893d4f | 6532 | "@ |
d40c829f UW |
6533 | msgfr\t%0,%2 |
6534 | msgf\t%0,%2" | |
963fc8d0 AK |
6535 | [(set_attr "op_type" "RRE,RXY") |
6536 | (set_attr "type" "imuldi")]) | |
07893d4f | 6537 | |
4023fb28 | 6538 | (define_insn "muldi3" |
963fc8d0 AK |
6539 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
6540 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
3e4be43f | 6541 | (match_operand:DI 2 "general_operand" "d,K,T,Os")))] |
9602b6a1 | 6542 | "TARGET_ZARCH" |
9db1d521 | 6543 | "@ |
d40c829f UW |
6544 | msgr\t%0,%2 |
6545 | mghi\t%0,%h2 | |
963fc8d0 AK |
6546 | msg\t%0,%2 |
6547 | msgfi\t%0,%2" | |
6548 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
6549 | (set_attr "type" "imuldi") | |
6550 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 6551 | |
9db1d521 HP |
6552 | ; |
6553 | ; mulsi3 instruction pattern(s). | |
6554 | ; | |
6555 | ||
f1e77d83 | 6556 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6557 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6558 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6559 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6560 | "" |
963fc8d0 AK |
6561 | "@ |
6562 | mh\t%0,%2 | |
6563 | mhy\t%0,%2" | |
6564 | [(set_attr "op_type" "RX,RXY") | |
6565 | (set_attr "type" "imulhi") | |
6566 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6567 | |
9db1d521 | 6568 | (define_insn "mulsi3" |
963fc8d0 AK |
6569 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
6570 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6571 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
6572 | "" |
6573 | "@ | |
d40c829f UW |
6574 | msr\t%0,%2 |
6575 | mhi\t%0,%h2 | |
6576 | ms\t%0,%2 | |
963fc8d0 AK |
6577 | msy\t%0,%2 |
6578 | msfi\t%0,%2" | |
6579 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
6580 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
3e4be43f | 6581 | (set_attr "cpu_facility" "*,*,*,longdisp,z10")]) |
9db1d521 | 6582 | |
4023fb28 UW |
6583 | ; |
6584 | ; mulsidi3 instruction pattern(s). | |
6585 | ; | |
6586 | ||
f1e77d83 | 6587 | (define_insn "mulsidi3" |
963fc8d0 | 6588 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6589 | (mult:DI (sign_extend:DI |
963fc8d0 | 6590 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6591 | (sign_extend:DI |
963fc8d0 | 6592 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6593 | "!TARGET_ZARCH" |
f1e77d83 UW |
6594 | "@ |
6595 | mr\t%0,%2 | |
963fc8d0 AK |
6596 | m\t%0,%2 |
6597 | mfy\t%0,%2" | |
6598 | [(set_attr "op_type" "RR,RX,RXY") | |
6599 | (set_attr "type" "imulsi") | |
6600 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6601 | |
f1e77d83 | 6602 | ; |
6e0d70c9 | 6603 | ; umul instruction pattern(s). |
f1e77d83 | 6604 | ; |
c7453384 | 6605 | |
6e0d70c9 AK |
6606 | ; mlr, ml, mlgr, mlg |
6607 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 6608 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 6609 | (mult:DW (zero_extend:DW |
3e4be43f | 6610 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 6611 | (zero_extend:DW |
3e4be43f | 6612 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
6e0d70c9 | 6613 | "TARGET_CPU_ZARCH" |
f1e77d83 | 6614 | "@ |
6e0d70c9 AK |
6615 | ml<tg>r\t%0,%2 |
6616 | ml<tg>\t%0,%2" | |
f1e77d83 | 6617 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6618 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6619 | |
9db1d521 | 6620 | ; |
609e7e80 | 6621 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6622 | ; |
6623 | ||
9381e3f1 | 6624 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6625 | (define_insn "mul<mode>3" |
62d3f261 AK |
6626 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
6627 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") | |
6628 | (match_operand:FP 2 "general_operand" "f,f,R,v")))] | |
142cd70f | 6629 | "TARGET_HARD_FLOAT" |
9db1d521 | 6630 | "@ |
62d3f261 AK |
6631 | m<xdee>tr\t%0,%1,%2 |
6632 | m<xdee>br\t%0,%2 | |
6e5b5de8 AK |
6633 | m<xdee>b\t%0,%2 |
6634 | wfmdb\t%v0,%v1,%v2" | |
62d3f261 | 6635 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 6636 | (set_attr "type" "fmul<mode>") |
285363a1 | 6637 | (set_attr "cpu_facility" "*,*,*,vx") |
62d3f261 | 6638 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) |
9db1d521 | 6639 | |
9381e3f1 | 6640 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6641 | (define_insn "fma<mode>4" |
62d3f261 AK |
6642 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v") |
6643 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") | |
6644 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") | |
6645 | (match_operand:DSF 3 "register_operand" "0,0,v")))] | |
d7ecb504 | 6646 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6647 | "@ |
f61a2c7d | 6648 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6649 | ma<xde>b\t%0,%1,%2 |
6650 | wfmadb\t%v0,%v1,%v2,%v3" | |
6651 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6652 | (set_attr "type" "fmadd<mode>") | |
285363a1 | 6653 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 6654 | (set_attr "enabled" "*,*,<DFDI>")]) |
a1b892b5 | 6655 | |
43a09b63 | 6656 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6657 | (define_insn "fms<mode>4" |
62d3f261 AK |
6658 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v") |
6659 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") | |
6660 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") | |
6661 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))] | |
d7ecb504 | 6662 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6663 | "@ |
f61a2c7d | 6664 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6665 | ms<xde>b\t%0,%1,%2 |
6666 | wfmsdb\t%v0,%v1,%v2,%v3" | |
6667 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6668 | (set_attr "type" "fmadd<mode>") | |
285363a1 | 6669 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 6670 | (set_attr "enabled" "*,*,<DFDI>")]) |
9db1d521 HP |
6671 | |
6672 | ;; | |
6673 | ;;- Divide and modulo instructions. | |
6674 | ;; | |
6675 | ||
6676 | ; | |
4023fb28 | 6677 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6678 | ; |
6679 | ||
4023fb28 UW |
6680 | (define_expand "divmoddi4" |
6681 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6682 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6683 | (match_operand:DI 2 "general_operand" ""))) |
6684 | (set (match_operand:DI 3 "general_operand" "") | |
6685 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6686 | (clobber (match_dup 4))] | |
9602b6a1 | 6687 | "TARGET_ZARCH" |
9db1d521 | 6688 | { |
d8485bdb TS |
6689 | rtx div_equal, mod_equal; |
6690 | rtx_insn *insn; | |
4023fb28 UW |
6691 | |
6692 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6693 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6694 | |
6695 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6696 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6697 | |
6698 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6699 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6700 | |
6701 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6702 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6703 | |
9db1d521 | 6704 | DONE; |
10bbf137 | 6705 | }) |
9db1d521 HP |
6706 | |
6707 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6708 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6709 | (ior:TI | |
4023fb28 UW |
6710 | (ashift:TI |
6711 | (zero_extend:TI | |
5665e398 | 6712 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6713 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
6714 | (const_int 64)) |
6715 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6716 | "TARGET_ZARCH" |
9db1d521 | 6717 | "@ |
d40c829f UW |
6718 | dsgr\t%0,%2 |
6719 | dsg\t%0,%2" | |
d3632d41 | 6720 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6721 | (set_attr "type" "idiv")]) |
9db1d521 | 6722 | |
4023fb28 UW |
6723 | (define_insn "divmodtisi3" |
6724 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6725 | (ior:TI | |
4023fb28 UW |
6726 | (ashift:TI |
6727 | (zero_extend:TI | |
5665e398 | 6728 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6729 | (sign_extend:DI |
3e4be43f | 6730 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
6731 | (const_int 64)) |
6732 | (zero_extend:TI | |
6733 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6734 | "TARGET_ZARCH" |
4023fb28 | 6735 | "@ |
d40c829f UW |
6736 | dsgfr\t%0,%2 |
6737 | dsgf\t%0,%2" | |
d3632d41 | 6738 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6739 | (set_attr "type" "idiv")]) |
9db1d521 | 6740 | |
4023fb28 UW |
6741 | ; |
6742 | ; udivmoddi4 instruction pattern(s). | |
6743 | ; | |
9db1d521 | 6744 | |
4023fb28 UW |
6745 | (define_expand "udivmoddi4" |
6746 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6747 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6748 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6749 | (set (match_operand:DI 3 "general_operand" "") | |
6750 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6751 | (clobber (match_dup 4))] | |
9602b6a1 | 6752 | "TARGET_ZARCH" |
9db1d521 | 6753 | { |
d8485bdb TS |
6754 | rtx div_equal, mod_equal, equal; |
6755 | rtx_insn *insn; | |
4023fb28 UW |
6756 | |
6757 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6758 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6759 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6760 | gen_rtx_ASHIFT (TImode, |
6761 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6762 | GEN_INT (64)), |
6763 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6764 | |
6765 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6766 | emit_clobber (operands[4]); |
4023fb28 UW |
6767 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6768 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6769 | |
4023fb28 | 6770 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6771 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6772 | |
6773 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6774 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6775 | |
6776 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6777 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6778 | |
9db1d521 | 6779 | DONE; |
10bbf137 | 6780 | }) |
9db1d521 HP |
6781 | |
6782 | (define_insn "udivmodtidi3" | |
4023fb28 | 6783 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6784 | (ior:TI |
5665e398 UW |
6785 | (ashift:TI |
6786 | (zero_extend:TI | |
6787 | (truncate:DI | |
2f7e5a0d EC |
6788 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6789 | (zero_extend:TI | |
3e4be43f | 6790 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
6791 | (const_int 64)) |
6792 | (zero_extend:TI | |
6793 | (truncate:DI | |
6794 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6795 | "TARGET_ZARCH" |
9db1d521 | 6796 | "@ |
d40c829f UW |
6797 | dlgr\t%0,%2 |
6798 | dlg\t%0,%2" | |
d3632d41 | 6799 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6800 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6801 | |
6802 | ; | |
4023fb28 | 6803 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6804 | ; |
6805 | ||
4023fb28 UW |
6806 | (define_expand "divmodsi4" |
6807 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6808 | (div:SI (match_operand:SI 1 "general_operand" "") | |
6809 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6810 | (set (match_operand:SI 3 "general_operand" "") | |
6811 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
6812 | (clobber (match_dup 4))] | |
9602b6a1 | 6813 | "!TARGET_ZARCH" |
9db1d521 | 6814 | { |
d8485bdb TS |
6815 | rtx div_equal, mod_equal, equal; |
6816 | rtx_insn *insn; | |
4023fb28 UW |
6817 | |
6818 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
6819 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
6820 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6821 | gen_rtx_ASHIFT (DImode, |
6822 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6823 | GEN_INT (32)), |
6824 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
6825 | |
6826 | operands[4] = gen_reg_rtx(DImode); | |
6827 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 6828 | |
4023fb28 | 6829 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6830 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6831 | |
6832 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6833 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6834 | |
6835 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6836 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6837 | |
9db1d521 | 6838 | DONE; |
10bbf137 | 6839 | }) |
9db1d521 HP |
6840 | |
6841 | (define_insn "divmoddisi3" | |
4023fb28 | 6842 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 6843 | (ior:DI |
5665e398 UW |
6844 | (ashift:DI |
6845 | (zero_extend:DI | |
6846 | (truncate:SI | |
2f7e5a0d EC |
6847 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
6848 | (sign_extend:DI | |
5665e398 UW |
6849 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
6850 | (const_int 32)) | |
6851 | (zero_extend:DI | |
6852 | (truncate:SI | |
6853 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6854 | "!TARGET_ZARCH" |
9db1d521 | 6855 | "@ |
d40c829f UW |
6856 | dr\t%0,%2 |
6857 | d\t%0,%2" | |
9db1d521 | 6858 | [(set_attr "op_type" "RR,RX") |
077dab3b | 6859 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6860 | |
6861 | ; | |
6862 | ; udivsi3 and umodsi3 instruction pattern(s). | |
6863 | ; | |
6864 | ||
f1e77d83 UW |
6865 | (define_expand "udivmodsi4" |
6866 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6867 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
6868 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6869 | (set (match_operand:SI 3 "general_operand" "") | |
6870 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
6871 | (clobber (match_dup 4))] | |
9602b6a1 | 6872 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 | 6873 | { |
d8485bdb TS |
6874 | rtx div_equal, mod_equal, equal; |
6875 | rtx_insn *insn; | |
f1e77d83 UW |
6876 | |
6877 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6878 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6879 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
6880 | gen_rtx_ASHIFT (DImode, |
6881 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6882 | GEN_INT (32)), |
6883 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
6884 | |
6885 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 6886 | emit_clobber (operands[4]); |
f1e77d83 UW |
6887 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
6888 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 6889 | |
f1e77d83 | 6890 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6891 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
6892 | |
6893 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6894 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
6895 | |
6896 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6897 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
6898 | |
6899 | DONE; | |
6900 | }) | |
6901 | ||
6902 | (define_insn "udivmoddisi3" | |
6903 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 6904 | (ior:DI |
5665e398 UW |
6905 | (ashift:DI |
6906 | (zero_extend:DI | |
6907 | (truncate:SI | |
2f7e5a0d EC |
6908 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
6909 | (zero_extend:DI | |
3e4be43f | 6910 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
6911 | (const_int 32)) |
6912 | (zero_extend:DI | |
6913 | (truncate:SI | |
6914 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6915 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6916 | "@ |
6917 | dlr\t%0,%2 | |
6918 | dl\t%0,%2" | |
6919 | [(set_attr "op_type" "RRE,RXY") | |
6920 | (set_attr "type" "idiv")]) | |
4023fb28 | 6921 | |
9db1d521 HP |
6922 | (define_expand "udivsi3" |
6923 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6924 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
6925 | (match_operand:SI 2 "general_operand" ""))) |
6926 | (clobber (match_dup 3))] | |
9602b6a1 | 6927 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6928 | { |
d8485bdb TS |
6929 | rtx udiv_equal, umod_equal, equal; |
6930 | rtx_insn *insn; | |
4023fb28 UW |
6931 | |
6932 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6933 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6934 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6935 | gen_rtx_ASHIFT (DImode, |
6936 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6937 | GEN_INT (32)), |
6938 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6939 | |
4023fb28 | 6940 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6941 | |
6942 | if (CONSTANT_P (operands[2])) | |
6943 | { | |
6944 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
6945 | { | |
19f8b229 | 6946 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6947 | |
4023fb28 UW |
6948 | operands[1] = make_safe_from (operands[1], operands[0]); |
6949 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6950 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
6951 | SImode, 1, label1); | |
4023fb28 | 6952 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6953 | emit_label (label1); |
6954 | } | |
6955 | else | |
6956 | { | |
c7453384 EC |
6957 | operands[2] = force_reg (SImode, operands[2]); |
6958 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6959 | |
6960 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6961 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6962 | operands[2])); | |
bd94cb6e | 6963 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6964 | |
6965 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6966 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 6967 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
6968 | } |
6969 | } | |
6970 | else | |
c7453384 | 6971 | { |
19f8b229 TS |
6972 | rtx_code_label *label1 = gen_label_rtx (); |
6973 | rtx_code_label *label2 = gen_label_rtx (); | |
6974 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6975 | |
c7453384 EC |
6976 | operands[1] = force_reg (SImode, operands[1]); |
6977 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6978 | operands[2] = force_reg (SImode, operands[2]); | |
6979 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6980 | |
6981 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6982 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6983 | SImode, 1, label3); | |
6984 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6985 | SImode, 0, label2); | |
6986 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6987 | SImode, 0, label1); | |
4023fb28 UW |
6988 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6989 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6990 | operands[2])); | |
bd94cb6e | 6991 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6992 | |
6993 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6994 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
6995 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
6996 | ||
f314b9b1 | 6997 | emit_jump (label3); |
9db1d521 | 6998 | emit_label (label1); |
4023fb28 | 6999 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 7000 | emit_jump (label3); |
9db1d521 | 7001 | emit_label (label2); |
4023fb28 | 7002 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
7003 | emit_label (label3); |
7004 | } | |
c7453384 | 7005 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 7006 | DONE; |
10bbf137 | 7007 | }) |
9db1d521 HP |
7008 | |
7009 | (define_expand "umodsi3" | |
7010 | [(set (match_operand:SI 0 "register_operand" "=d") | |
7011 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
7012 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
7013 | (clobber (match_dup 3))] | |
9602b6a1 | 7014 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 7015 | { |
d8485bdb TS |
7016 | rtx udiv_equal, umod_equal, equal; |
7017 | rtx_insn *insn; | |
4023fb28 UW |
7018 | |
7019 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7020 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7021 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7022 | gen_rtx_ASHIFT (DImode, |
7023 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
7024 | GEN_INT (32)), |
7025 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 7026 | |
4023fb28 | 7027 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
7028 | |
7029 | if (CONSTANT_P (operands[2])) | |
7030 | { | |
7031 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
7032 | { | |
19f8b229 | 7033 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 7034 | |
4023fb28 UW |
7035 | operands[1] = make_safe_from (operands[1], operands[0]); |
7036 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
7037 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
7038 | SImode, 1, label1); | |
4023fb28 UW |
7039 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
7040 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
7041 | emit_label (label1); |
7042 | } | |
7043 | else | |
7044 | { | |
c7453384 EC |
7045 | operands[2] = force_reg (SImode, operands[2]); |
7046 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7047 | |
7048 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
7049 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7050 | operands[2])); | |
bd94cb6e | 7051 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7052 | |
7053 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7054 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 7055 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
7056 | } |
7057 | } | |
7058 | else | |
7059 | { | |
19f8b229 TS |
7060 | rtx_code_label *label1 = gen_label_rtx (); |
7061 | rtx_code_label *label2 = gen_label_rtx (); | |
7062 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 7063 | |
c7453384 EC |
7064 | operands[1] = force_reg (SImode, operands[1]); |
7065 | operands[1] = make_safe_from (operands[1], operands[0]); | |
7066 | operands[2] = force_reg (SImode, operands[2]); | |
7067 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 7068 | |
c7453384 | 7069 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
7070 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
7071 | SImode, 1, label3); | |
7072 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
7073 | SImode, 0, label2); | |
7074 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
7075 | SImode, 0, label1); | |
4023fb28 UW |
7076 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
7077 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7078 | operands[2])); | |
bd94cb6e | 7079 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7080 | |
7081 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7082 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
7083 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
7084 | ||
f314b9b1 | 7085 | emit_jump (label3); |
9db1d521 | 7086 | emit_label (label1); |
4023fb28 | 7087 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 7088 | emit_jump (label3); |
9db1d521 | 7089 | emit_label (label2); |
4023fb28 | 7090 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
7091 | emit_label (label3); |
7092 | } | |
9db1d521 | 7093 | DONE; |
10bbf137 | 7094 | }) |
9db1d521 HP |
7095 | |
7096 | ; | |
f5905b37 | 7097 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7098 | ; |
7099 | ||
609e7e80 | 7100 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7101 | (define_insn "div<mode>3" |
62d3f261 AK |
7102 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
7103 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v") | |
7104 | (match_operand:FP 2 "general_operand" "f,f,R,v")))] | |
142cd70f | 7105 | "TARGET_HARD_FLOAT" |
9db1d521 | 7106 | "@ |
62d3f261 AK |
7107 | d<xde>tr\t%0,%1,%2 |
7108 | d<xde>br\t%0,%2 | |
6e5b5de8 AK |
7109 | d<xde>b\t%0,%2 |
7110 | wfddb\t%v0,%v1,%v2" | |
62d3f261 | 7111 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 7112 | (set_attr "type" "fdiv<mode>") |
285363a1 | 7113 | (set_attr "cpu_facility" "*,*,*,vx") |
62d3f261 | 7114 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) |
9db1d521 | 7115 | |
9db1d521 HP |
7116 | |
7117 | ;; | |
7118 | ;;- And instructions. | |
7119 | ;; | |
7120 | ||
047d35ed AS |
7121 | (define_expand "and<mode>3" |
7122 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7123 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7124 | (match_operand:INT 2 "general_operand" ""))) | |
7125 | (clobber (reg:CC CC_REGNUM))] | |
7126 | "" | |
7127 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7128 | ||
9db1d521 HP |
7129 | ; |
7130 | ; anddi3 instruction pattern(s). | |
7131 | ; | |
7132 | ||
7133 | (define_insn "*anddi3_cc" | |
ae156f85 | 7134 | [(set (reg CC_REGNUM) |
e3140518 | 7135 | (compare |
3e4be43f | 7136 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7137 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7138 | (const_int 0))) |
3e4be43f | 7139 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7140 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7141 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7142 | "@ |
d40c829f | 7143 | ngr\t%0,%2 |
65b1d8ea | 7144 | ngrk\t%0,%1,%2 |
e3140518 RH |
7145 | ng\t%0,%2 |
7146 | risbg\t%0,%1,%s2,128+%e2,0" | |
7147 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7148 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7149 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7150 | |
7151 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7152 | [(set (reg CC_REGNUM) |
e3140518 | 7153 | (compare |
3e4be43f | 7154 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7155 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7156 | (const_int 0))) |
3e4be43f | 7157 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7158 | "TARGET_ZARCH |
7159 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7160 | /* Do not steal TM patterns. */ |
7161 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7162 | "@ |
d40c829f | 7163 | ngr\t%0,%2 |
65b1d8ea | 7164 | ngrk\t%0,%1,%2 |
e3140518 RH |
7165 | ng\t%0,%2 |
7166 | risbg\t%0,%1,%s2,128+%e2,0" | |
7167 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7168 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7169 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7170 | |
3af8e996 | 7171 | (define_insn "*anddi3" |
65b1d8ea | 7172 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7173 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7174 | (and:DI |
7175 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7176 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7177 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7178 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7179 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7180 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7181 | "@ |
7182 | # | |
7183 | # | |
7184 | nihh\t%0,%j2 | |
7185 | nihl\t%0,%j2 | |
7186 | nilh\t%0,%j2 | |
7187 | nill\t%0,%j2 | |
7188 | nihf\t%0,%m2 | |
7189 | nilf\t%0,%m2 | |
7190 | ngr\t%0,%2 | |
65b1d8ea | 7191 | ngrk\t%0,%1,%2 |
ec24698e | 7192 | ng\t%0,%2 |
e3140518 | 7193 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7194 | # |
7195 | #" | |
e3140518 RH |
7196 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7197 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7198 | (set_attr "z10prop" "*, |
7199 | *, | |
7200 | z10_super_E1, | |
7201 | z10_super_E1, | |
7202 | z10_super_E1, | |
7203 | z10_super_E1, | |
7204 | z10_super_E1, | |
7205 | z10_super_E1, | |
7206 | z10_super_E1, | |
65b1d8ea | 7207 | *, |
9381e3f1 | 7208 | z10_super_E1, |
e3140518 | 7209 | z10_super_E1, |
9381e3f1 WG |
7210 | *, |
7211 | *")]) | |
0dfa6c5e UW |
7212 | |
7213 | (define_split | |
7214 | [(set (match_operand:DI 0 "s_operand" "") | |
7215 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7216 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7217 | "reload_completed" |
7218 | [(parallel | |
7219 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7220 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7221 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7222 | |
1a2e356e | 7223 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7224 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7225 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7226 | (and:GPR (lshiftrt:GPR | |
7227 | (match_operand:GPR 1 "register_operand" "d") | |
7228 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7229 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7230 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7231 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7232 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7233 | INTVAL (operands[3]))" | |
64c744b9 | 7234 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7235 | [(set_attr "op_type" "RIE") |
7236 | (set_attr "z10prop" "z10_super_E1")]) | |
7237 | ||
64c744b9 | 7238 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7239 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7240 | (and:GPR (ashift:GPR | |
7241 | (match_operand:GPR 1 "register_operand" "d") | |
7242 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7243 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7244 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7245 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7246 | INTVAL (operands[3]))" | |
64c744b9 | 7247 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7248 | [(set_attr "op_type" "RIE") |
7249 | (set_attr "z10prop" "z10_super_E1")]) | |
7250 | ||
9db1d521 HP |
7251 | |
7252 | ; | |
7253 | ; andsi3 instruction pattern(s). | |
7254 | ; | |
7255 | ||
7256 | (define_insn "*andsi3_cc" | |
ae156f85 | 7257 | [(set (reg CC_REGNUM) |
e3140518 RH |
7258 | (compare |
7259 | (and:SI | |
7260 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7261 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7262 | (const_int 0))) | |
7263 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7264 | (and:SI (match_dup 1) (match_dup 2)))] |
7265 | "s390_match_ccmode(insn, CCTmode)" | |
7266 | "@ | |
ec24698e | 7267 | nilf\t%0,%o2 |
d40c829f | 7268 | nr\t%0,%2 |
65b1d8ea | 7269 | nrk\t%0,%1,%2 |
d40c829f | 7270 | n\t%0,%2 |
e3140518 RH |
7271 | ny\t%0,%2 |
7272 | risbg\t%0,%1,%t2,128+%f2,0" | |
7273 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7274 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7275 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7276 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7277 | |
7278 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7279 | [(set (reg CC_REGNUM) |
e3140518 RH |
7280 | (compare |
7281 | (and:SI | |
7282 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7283 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7284 | (const_int 0))) | |
7285 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7286 | "s390_match_ccmode(insn, CCTmode) |
7287 | /* Do not steal TM patterns. */ | |
7288 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7289 | "@ |
ec24698e | 7290 | nilf\t%0,%o2 |
d40c829f | 7291 | nr\t%0,%2 |
65b1d8ea | 7292 | nrk\t%0,%1,%2 |
d40c829f | 7293 | n\t%0,%2 |
e3140518 RH |
7294 | ny\t%0,%2 |
7295 | risbg\t%0,%1,%t2,128+%f2,0" | |
7296 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7297 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7298 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7299 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7300 | |
f19a9af7 | 7301 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7302 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7303 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7304 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7305 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7306 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7307 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7308 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7309 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7310 | "@ |
f19a9af7 AK |
7311 | # |
7312 | # | |
7313 | nilh\t%0,%j2 | |
2f7e5a0d | 7314 | nill\t%0,%j2 |
ec24698e | 7315 | nilf\t%0,%o2 |
d40c829f | 7316 | nr\t%0,%2 |
65b1d8ea | 7317 | nrk\t%0,%1,%2 |
d40c829f | 7318 | n\t%0,%2 |
8cb66696 | 7319 | ny\t%0,%2 |
e3140518 | 7320 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7321 | # |
19b63d8e | 7322 | #" |
e3140518 | 7323 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7324 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7325 | (set_attr "z10prop" "*, |
7326 | *, | |
7327 | z10_super_E1, | |
7328 | z10_super_E1, | |
7329 | z10_super_E1, | |
7330 | z10_super_E1, | |
65b1d8ea | 7331 | *, |
9381e3f1 WG |
7332 | z10_super_E1, |
7333 | z10_super_E1, | |
e3140518 | 7334 | z10_super_E1, |
9381e3f1 WG |
7335 | *, |
7336 | *")]) | |
f19a9af7 AK |
7337 | |
7338 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7339 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7340 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7341 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7342 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7343 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7344 | "@ |
7345 | nr\t%0,%2 | |
8cb66696 | 7346 | n\t%0,%2 |
0dfa6c5e | 7347 | # |
19b63d8e | 7348 | #" |
9381e3f1 WG |
7349 | [(set_attr "op_type" "RR,RX,SI,SS") |
7350 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7351 | ||
0dfa6c5e UW |
7352 | |
7353 | (define_split | |
7354 | [(set (match_operand:SI 0 "s_operand" "") | |
7355 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7356 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7357 | "reload_completed" |
7358 | [(parallel | |
7359 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7360 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7361 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7362 | |
9db1d521 HP |
7363 | ; |
7364 | ; andhi3 instruction pattern(s). | |
7365 | ; | |
7366 | ||
8cb66696 | 7367 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7368 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7369 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7370 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7371 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7372 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7373 | "@ |
d40c829f | 7374 | nr\t%0,%2 |
65b1d8ea | 7375 | nrk\t%0,%1,%2 |
8cb66696 | 7376 | nill\t%0,%x2 |
0dfa6c5e | 7377 | # |
19b63d8e | 7378 | #" |
65b1d8ea AK |
7379 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7380 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7381 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7382 | ]) |
8cb66696 UW |
7383 | |
7384 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7385 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7386 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7387 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7388 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7389 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7390 | "@ | |
7391 | nr\t%0,%2 | |
0dfa6c5e | 7392 | # |
19b63d8e | 7393 | #" |
9381e3f1 WG |
7394 | [(set_attr "op_type" "RR,SI,SS") |
7395 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7396 | ]) | |
0dfa6c5e UW |
7397 | |
7398 | (define_split | |
7399 | [(set (match_operand:HI 0 "s_operand" "") | |
7400 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7401 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7402 | "reload_completed" |
7403 | [(parallel | |
7404 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7405 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7406 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7407 | |
9db1d521 HP |
7408 | ; |
7409 | ; andqi3 instruction pattern(s). | |
7410 | ; | |
7411 | ||
8cb66696 | 7412 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7413 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7414 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7415 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7416 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7417 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7418 | "@ |
d40c829f | 7419 | nr\t%0,%2 |
65b1d8ea | 7420 | nrk\t%0,%1,%2 |
8cb66696 | 7421 | nill\t%0,%b2 |
fc0ea003 UW |
7422 | ni\t%S0,%b2 |
7423 | niy\t%S0,%b2 | |
19b63d8e | 7424 | #" |
65b1d8ea | 7425 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7426 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7427 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7428 | |
7429 | (define_insn "*andqi3_esa" | |
7430 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7431 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7432 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7433 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7434 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7435 | "@ |
8cb66696 | 7436 | nr\t%0,%2 |
fc0ea003 | 7437 | ni\t%S0,%b2 |
19b63d8e | 7438 | #" |
9381e3f1 WG |
7439 | [(set_attr "op_type" "RR,SI,SS") |
7440 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7441 | |
deb9351f DV |
7442 | ; |
7443 | ; And with complement | |
7444 | ; | |
7445 | ; c = ~b & a = (b & a) ^ a | |
7446 | ||
7447 | (define_insn_and_split "*andc_split_<mode>" | |
7448 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7449 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7450 | (match_operand:GPR 2 "general_operand" ""))) | |
7451 | (clobber (reg:CC CC_REGNUM))] | |
ad7ab32e DV |
7452 | "! reload_completed |
7453 | && (GET_CODE (operands[0]) != MEM | |
7454 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7455 | on the split xor if (b & a) is stored into a pseudo. */ | |
7456 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7457 | "#" |
7458 | "&& 1" | |
7459 | [ | |
7460 | (parallel | |
7461 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7462 | (clobber (reg:CC CC_REGNUM))]) | |
7463 | (parallel | |
7464 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7465 | (clobber (reg:CC CC_REGNUM))])] | |
7466 | { | |
7467 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7468 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7469 | else | |
7470 | operands[3] = operands[0]; | |
7471 | }) | |
7472 | ||
19b63d8e UW |
7473 | ; |
7474 | ; Block and (NC) patterns. | |
7475 | ; | |
7476 | ||
7477 | (define_insn "*nc" | |
7478 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7479 | (and:BLK (match_dup 0) | |
7480 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7481 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7482 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7483 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7484 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7485 | [(set_attr "op_type" "SS") |
7486 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7487 | |
7488 | (define_split | |
7489 | [(set (match_operand 0 "memory_operand" "") | |
7490 | (and (match_dup 0) | |
7491 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7492 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7493 | "reload_completed |
7494 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7495 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7496 | [(parallel | |
7497 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7498 | (use (match_dup 2)) | |
ae156f85 | 7499 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7500 | { |
7501 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7502 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7503 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7504 | }) | |
7505 | ||
7506 | (define_peephole2 | |
7507 | [(parallel | |
7508 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7509 | (and:BLK (match_dup 0) | |
7510 | (match_operand:BLK 1 "memory_operand" ""))) | |
7511 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7512 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7513 | (parallel |
7514 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7515 | (and:BLK (match_dup 3) | |
7516 | (match_operand:BLK 4 "memory_operand" ""))) | |
7517 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7518 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7519 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7520 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7521 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7522 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7523 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7524 | [(parallel | |
7525 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7526 | (use (match_dup 8)) | |
ae156f85 | 7527 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7528 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7529 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7530 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7531 | ||
9db1d521 HP |
7532 | |
7533 | ;; | |
7534 | ;;- Bit set (inclusive or) instructions. | |
7535 | ;; | |
7536 | ||
047d35ed AS |
7537 | (define_expand "ior<mode>3" |
7538 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7539 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7540 | (match_operand:INT 2 "general_operand" ""))) | |
7541 | (clobber (reg:CC CC_REGNUM))] | |
7542 | "" | |
7543 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7544 | ||
9db1d521 HP |
7545 | ; |
7546 | ; iordi3 instruction pattern(s). | |
7547 | ; | |
7548 | ||
4023fb28 | 7549 | (define_insn "*iordi3_cc" |
ae156f85 | 7550 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7551 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7552 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7553 | (const_int 0))) |
3e4be43f | 7554 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7555 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7556 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7557 | "@ |
d40c829f | 7558 | ogr\t%0,%2 |
65b1d8ea | 7559 | ogrk\t%0,%1,%2 |
d40c829f | 7560 | og\t%0,%2" |
65b1d8ea AK |
7561 | [(set_attr "op_type" "RRE,RRF,RXY") |
7562 | (set_attr "cpu_facility" "*,z196,*") | |
7563 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7564 | |
7565 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7566 | [(set (reg CC_REGNUM) |
65b1d8ea | 7567 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7568 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7569 | (const_int 0))) |
65b1d8ea | 7570 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7571 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7572 | "@ |
d40c829f | 7573 | ogr\t%0,%2 |
65b1d8ea | 7574 | ogrk\t%0,%1,%2 |
d40c829f | 7575 | og\t%0,%2" |
65b1d8ea AK |
7576 | [(set_attr "op_type" "RRE,RRF,RXY") |
7577 | (set_attr "cpu_facility" "*,z196,*") | |
7578 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7579 | |
3af8e996 | 7580 | (define_insn "*iordi3" |
65b1d8ea | 7581 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7582 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7583 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7584 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7585 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7586 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7587 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7588 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7589 | "@ |
7590 | oihh\t%0,%i2 | |
7591 | oihl\t%0,%i2 | |
7592 | oilh\t%0,%i2 | |
7593 | oill\t%0,%i2 | |
7594 | oihf\t%0,%k2 | |
7595 | oilf\t%0,%k2 | |
7596 | ogr\t%0,%2 | |
65b1d8ea | 7597 | ogrk\t%0,%1,%2 |
ec24698e UW |
7598 | og\t%0,%2 |
7599 | # | |
7600 | #" | |
65b1d8ea AK |
7601 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7602 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7603 | (set_attr "z10prop" "z10_super_E1, |
7604 | z10_super_E1, | |
7605 | z10_super_E1, | |
7606 | z10_super_E1, | |
7607 | z10_super_E1, | |
7608 | z10_super_E1, | |
7609 | z10_super_E1, | |
65b1d8ea | 7610 | *, |
9381e3f1 WG |
7611 | z10_super_E1, |
7612 | *, | |
7613 | *")]) | |
0dfa6c5e UW |
7614 | |
7615 | (define_split | |
7616 | [(set (match_operand:DI 0 "s_operand" "") | |
7617 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7618 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7619 | "reload_completed" |
7620 | [(parallel | |
7621 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7622 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7623 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7624 | |
9db1d521 HP |
7625 | ; |
7626 | ; iorsi3 instruction pattern(s). | |
7627 | ; | |
7628 | ||
4023fb28 | 7629 | (define_insn "*iorsi3_cc" |
ae156f85 | 7630 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7631 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7632 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7633 | (const_int 0))) |
65b1d8ea | 7634 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7635 | (ior:SI (match_dup 1) (match_dup 2)))] |
7636 | "s390_match_ccmode(insn, CCTmode)" | |
7637 | "@ | |
ec24698e | 7638 | oilf\t%0,%o2 |
d40c829f | 7639 | or\t%0,%2 |
65b1d8ea | 7640 | ork\t%0,%1,%2 |
d40c829f UW |
7641 | o\t%0,%2 |
7642 | oy\t%0,%2" | |
65b1d8ea | 7643 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7644 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7645 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7646 | |
7647 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7648 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7649 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7650 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7651 | (const_int 0))) |
65b1d8ea | 7652 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7653 | "s390_match_ccmode(insn, CCTmode)" |
7654 | "@ | |
ec24698e | 7655 | oilf\t%0,%o2 |
d40c829f | 7656 | or\t%0,%2 |
65b1d8ea | 7657 | ork\t%0,%1,%2 |
d40c829f UW |
7658 | o\t%0,%2 |
7659 | oy\t%0,%2" | |
65b1d8ea | 7660 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7661 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7662 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7663 | |
8cb66696 | 7664 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7665 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7666 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7667 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7668 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7669 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7670 | "@ |
f19a9af7 AK |
7671 | oilh\t%0,%i2 |
7672 | oill\t%0,%i2 | |
ec24698e | 7673 | oilf\t%0,%o2 |
d40c829f | 7674 | or\t%0,%2 |
65b1d8ea | 7675 | ork\t%0,%1,%2 |
d40c829f | 7676 | o\t%0,%2 |
8cb66696 | 7677 | oy\t%0,%2 |
0dfa6c5e | 7678 | # |
19b63d8e | 7679 | #" |
65b1d8ea | 7680 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7681 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7682 | (set_attr "z10prop" "z10_super_E1, |
7683 | z10_super_E1, | |
7684 | z10_super_E1, | |
7685 | z10_super_E1, | |
65b1d8ea | 7686 | *, |
9381e3f1 WG |
7687 | z10_super_E1, |
7688 | z10_super_E1, | |
7689 | *, | |
7690 | *")]) | |
8cb66696 UW |
7691 | |
7692 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7693 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7694 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7695 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7696 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7697 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7698 | "@ |
7699 | or\t%0,%2 | |
8cb66696 | 7700 | o\t%0,%2 |
0dfa6c5e | 7701 | # |
19b63d8e | 7702 | #" |
9381e3f1 WG |
7703 | [(set_attr "op_type" "RR,RX,SI,SS") |
7704 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7705 | |
7706 | (define_split | |
7707 | [(set (match_operand:SI 0 "s_operand" "") | |
7708 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7709 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7710 | "reload_completed" |
7711 | [(parallel | |
7712 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7713 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7714 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7715 | |
4023fb28 UW |
7716 | ; |
7717 | ; iorhi3 instruction pattern(s). | |
7718 | ; | |
7719 | ||
8cb66696 | 7720 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7721 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7722 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7723 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7724 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7725 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7726 | "@ |
d40c829f | 7727 | or\t%0,%2 |
65b1d8ea | 7728 | ork\t%0,%1,%2 |
8cb66696 | 7729 | oill\t%0,%x2 |
0dfa6c5e | 7730 | # |
19b63d8e | 7731 | #" |
65b1d8ea AK |
7732 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7733 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7734 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7735 | |
7736 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7737 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7738 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7739 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7740 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7741 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7742 | "@ | |
7743 | or\t%0,%2 | |
0dfa6c5e | 7744 | # |
19b63d8e | 7745 | #" |
9381e3f1 WG |
7746 | [(set_attr "op_type" "RR,SI,SS") |
7747 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7748 | |
7749 | (define_split | |
7750 | [(set (match_operand:HI 0 "s_operand" "") | |
7751 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7752 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7753 | "reload_completed" |
7754 | [(parallel | |
7755 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7756 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7757 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7758 | |
9db1d521 | 7759 | ; |
4023fb28 | 7760 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7761 | ; |
7762 | ||
8cb66696 | 7763 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7764 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7765 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7766 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7767 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7768 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7769 | "@ |
d40c829f | 7770 | or\t%0,%2 |
65b1d8ea | 7771 | ork\t%0,%1,%2 |
8cb66696 | 7772 | oill\t%0,%b2 |
fc0ea003 UW |
7773 | oi\t%S0,%b2 |
7774 | oiy\t%S0,%b2 | |
19b63d8e | 7775 | #" |
65b1d8ea | 7776 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7777 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
7778 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
7779 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7780 | |
7781 | (define_insn "*iorqi3_esa" | |
7782 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7783 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7784 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7785 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7786 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7787 | "@ |
8cb66696 | 7788 | or\t%0,%2 |
fc0ea003 | 7789 | oi\t%S0,%b2 |
19b63d8e | 7790 | #" |
9381e3f1 WG |
7791 | [(set_attr "op_type" "RR,SI,SS") |
7792 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7793 | |
19b63d8e UW |
7794 | ; |
7795 | ; Block inclusive or (OC) patterns. | |
7796 | ; | |
7797 | ||
7798 | (define_insn "*oc" | |
7799 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7800 | (ior:BLK (match_dup 0) | |
7801 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7802 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7803 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7804 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7805 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7806 | [(set_attr "op_type" "SS") |
7807 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7808 | |
7809 | (define_split | |
7810 | [(set (match_operand 0 "memory_operand" "") | |
7811 | (ior (match_dup 0) | |
7812 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7813 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7814 | "reload_completed |
7815 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7816 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7817 | [(parallel | |
7818 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7819 | (use (match_dup 2)) | |
ae156f85 | 7820 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7821 | { |
7822 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7823 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7824 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7825 | }) | |
7826 | ||
7827 | (define_peephole2 | |
7828 | [(parallel | |
7829 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7830 | (ior:BLK (match_dup 0) | |
7831 | (match_operand:BLK 1 "memory_operand" ""))) | |
7832 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7833 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7834 | (parallel |
7835 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7836 | (ior:BLK (match_dup 3) | |
7837 | (match_operand:BLK 4 "memory_operand" ""))) | |
7838 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7839 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7840 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7841 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7842 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7843 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7844 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7845 | [(parallel | |
7846 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7847 | (use (match_dup 8)) | |
ae156f85 | 7848 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7849 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7850 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7851 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7852 | ||
9db1d521 HP |
7853 | |
7854 | ;; | |
7855 | ;;- Xor instructions. | |
7856 | ;; | |
7857 | ||
047d35ed AS |
7858 | (define_expand "xor<mode>3" |
7859 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7860 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7861 | (match_operand:INT 2 "general_operand" ""))) | |
7862 | (clobber (reg:CC CC_REGNUM))] | |
7863 | "" | |
7864 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7865 | ||
3c91f126 AK |
7866 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7867 | ; simplifications. So its better to have something matching. | |
7868 | (define_split | |
7869 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7870 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7871 | "" | |
7872 | [(parallel | |
7873 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7874 | (clobber (reg:CC CC_REGNUM))])] | |
7875 | { | |
7876 | operands[2] = constm1_rtx; | |
7877 | if (!s390_logical_operator_ok_p (operands)) | |
7878 | FAIL; | |
7879 | }) | |
7880 | ||
9db1d521 HP |
7881 | ; |
7882 | ; xordi3 instruction pattern(s). | |
7883 | ; | |
7884 | ||
4023fb28 | 7885 | (define_insn "*xordi3_cc" |
ae156f85 | 7886 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7887 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7888 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7889 | (const_int 0))) |
3e4be43f | 7890 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7891 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7892 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7893 | "@ |
d40c829f | 7894 | xgr\t%0,%2 |
65b1d8ea | 7895 | xgrk\t%0,%1,%2 |
d40c829f | 7896 | xg\t%0,%2" |
65b1d8ea | 7897 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7898 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7899 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7900 | |
7901 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7902 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7903 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7904 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7905 | (const_int 0))) |
3e4be43f | 7906 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7907 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7908 | "@ |
d40c829f | 7909 | xgr\t%0,%2 |
65b1d8ea | 7910 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 7911 | xg\t%0,%2" |
65b1d8ea AK |
7912 | [(set_attr "op_type" "RRE,RRF,RXY") |
7913 | (set_attr "cpu_facility" "*,z196,*") | |
7914 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7915 | |
3af8e996 | 7916 | (define_insn "*xordi3" |
3e4be43f UW |
7917 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
7918 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
7919 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 7920 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7921 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7922 | "@ |
7923 | xihf\t%0,%k2 | |
7924 | xilf\t%0,%k2 | |
7925 | xgr\t%0,%2 | |
65b1d8ea | 7926 | xgrk\t%0,%1,%2 |
ec24698e UW |
7927 | xg\t%0,%2 |
7928 | # | |
7929 | #" | |
65b1d8ea AK |
7930 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
7931 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
7932 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
7933 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7934 | |
7935 | (define_split | |
7936 | [(set (match_operand:DI 0 "s_operand" "") | |
7937 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7938 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7939 | "reload_completed" |
7940 | [(parallel | |
7941 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7942 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7943 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 7944 | |
9db1d521 HP |
7945 | ; |
7946 | ; xorsi3 instruction pattern(s). | |
7947 | ; | |
7948 | ||
4023fb28 | 7949 | (define_insn "*xorsi3_cc" |
ae156f85 | 7950 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7951 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7952 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7953 | (const_int 0))) |
65b1d8ea | 7954 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7955 | (xor:SI (match_dup 1) (match_dup 2)))] |
7956 | "s390_match_ccmode(insn, CCTmode)" | |
7957 | "@ | |
ec24698e | 7958 | xilf\t%0,%o2 |
d40c829f | 7959 | xr\t%0,%2 |
65b1d8ea | 7960 | xrk\t%0,%1,%2 |
d40c829f UW |
7961 | x\t%0,%2 |
7962 | xy\t%0,%2" | |
65b1d8ea | 7963 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7964 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
7965 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7966 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7967 | |
7968 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 7969 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7970 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7971 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7972 | (const_int 0))) |
65b1d8ea | 7973 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7974 | "s390_match_ccmode(insn, CCTmode)" |
7975 | "@ | |
ec24698e | 7976 | xilf\t%0,%o2 |
d40c829f | 7977 | xr\t%0,%2 |
65b1d8ea | 7978 | xrk\t%0,%1,%2 |
d40c829f UW |
7979 | x\t%0,%2 |
7980 | xy\t%0,%2" | |
65b1d8ea | 7981 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7982 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
7983 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7984 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7985 | |
8cb66696 | 7986 | (define_insn "*xorsi3" |
65b1d8ea AK |
7987 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
7988 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
7989 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7990 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7991 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7992 | "@ |
ec24698e | 7993 | xilf\t%0,%o2 |
d40c829f | 7994 | xr\t%0,%2 |
65b1d8ea | 7995 | xrk\t%0,%1,%2 |
d40c829f | 7996 | x\t%0,%2 |
8cb66696 | 7997 | xy\t%0,%2 |
0dfa6c5e | 7998 | # |
19b63d8e | 7999 | #" |
65b1d8ea | 8000 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8001 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8002 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8003 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8004 | |
8005 | (define_split | |
8006 | [(set (match_operand:SI 0 "s_operand" "") | |
8007 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8008 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8009 | "reload_completed" |
8010 | [(parallel | |
8011 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8012 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8013 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8014 | |
9db1d521 HP |
8015 | ; |
8016 | ; xorhi3 instruction pattern(s). | |
8017 | ; | |
8018 | ||
8cb66696 | 8019 | (define_insn "*xorhi3" |
65b1d8ea AK |
8020 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8021 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8022 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8023 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8024 | "s390_logical_operator_ok_p (operands)" |
8025 | "@ | |
ec24698e | 8026 | xilf\t%0,%x2 |
8cb66696 | 8027 | xr\t%0,%2 |
65b1d8ea | 8028 | xrk\t%0,%1,%2 |
0dfa6c5e | 8029 | # |
19b63d8e | 8030 | #" |
65b1d8ea AK |
8031 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8032 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8033 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8034 | |
8035 | (define_split | |
8036 | [(set (match_operand:HI 0 "s_operand" "") | |
8037 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8038 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8039 | "reload_completed" |
8040 | [(parallel | |
8041 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8042 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8043 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8044 | |
9db1d521 HP |
8045 | ; |
8046 | ; xorqi3 instruction pattern(s). | |
8047 | ; | |
8048 | ||
8cb66696 | 8049 | (define_insn "*xorqi3" |
65b1d8ea AK |
8050 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8051 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8052 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8053 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8054 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8055 | "@ |
ec24698e | 8056 | xilf\t%0,%b2 |
8cb66696 | 8057 | xr\t%0,%2 |
65b1d8ea | 8058 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8059 | xi\t%S0,%b2 |
8060 | xiy\t%S0,%b2 | |
19b63d8e | 8061 | #" |
65b1d8ea | 8062 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8063 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8064 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8065 | |
4023fb28 | 8066 | |
19b63d8e UW |
8067 | ; |
8068 | ; Block exclusive or (XC) patterns. | |
8069 | ; | |
8070 | ||
8071 | (define_insn "*xc" | |
8072 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8073 | (xor:BLK (match_dup 0) | |
8074 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8075 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8076 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8077 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8078 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8079 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8080 | |
8081 | (define_split | |
8082 | [(set (match_operand 0 "memory_operand" "") | |
8083 | (xor (match_dup 0) | |
8084 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8085 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8086 | "reload_completed |
8087 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8088 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8089 | [(parallel | |
8090 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8091 | (use (match_dup 2)) | |
ae156f85 | 8092 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8093 | { |
8094 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8095 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8096 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8097 | }) | |
8098 | ||
8099 | (define_peephole2 | |
8100 | [(parallel | |
8101 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8102 | (xor:BLK (match_dup 0) | |
8103 | (match_operand:BLK 1 "memory_operand" ""))) | |
8104 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8105 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8106 | (parallel |
8107 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8108 | (xor:BLK (match_dup 3) | |
8109 | (match_operand:BLK 4 "memory_operand" ""))) | |
8110 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8111 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8112 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8113 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8114 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8115 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8116 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8117 | [(parallel | |
8118 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8119 | (use (match_dup 8)) | |
ae156f85 | 8120 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8121 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8122 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8123 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8124 | ||
8125 | ; | |
8126 | ; Block xor (XC) patterns with src == dest. | |
8127 | ; | |
8128 | ||
8129 | (define_insn "*xc_zero" | |
8130 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8131 | (const_int 0)) | |
8132 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8133 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8134 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8135 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8136 | [(set_attr "op_type" "SS") |
8137 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8138 | |
8139 | (define_peephole2 | |
8140 | [(parallel | |
8141 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8142 | (const_int 0)) | |
8143 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8144 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8145 | (parallel |
8146 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8147 | (const_int 0)) | |
8148 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8149 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8150 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8151 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8152 | [(parallel | |
8153 | [(set (match_dup 4) (const_int 0)) | |
8154 | (use (match_dup 5)) | |
ae156f85 | 8155 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8156 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8157 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8158 | ||
9db1d521 HP |
8159 | |
8160 | ;; | |
8161 | ;;- Negate instructions. | |
8162 | ;; | |
8163 | ||
8164 | ; | |
9a91a21f | 8165 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8166 | ; |
8167 | ||
9a91a21f | 8168 | (define_expand "neg<mode>2" |
9db1d521 | 8169 | [(parallel |
9a91a21f AS |
8170 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8171 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8172 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8173 | "" |
8174 | "") | |
8175 | ||
26a89301 | 8176 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8177 | [(set (reg CC_REGNUM) |
26a89301 UW |
8178 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8179 | (match_operand:SI 1 "register_operand" "d") 0) | |
8180 | (const_int 32)) (const_int 32))) | |
8181 | (const_int 0))) | |
8182 | (set (match_operand:DI 0 "register_operand" "=d") | |
8183 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8184 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8185 | "lcgfr\t%0,%1" |
729e750f WG |
8186 | [(set_attr "op_type" "RRE") |
8187 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8188 | |
26a89301 UW |
8189 | (define_insn "*negdi2_sign" |
8190 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8191 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8192 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8193 | "TARGET_ZARCH" |
26a89301 | 8194 | "lcgfr\t%0,%1" |
729e750f WG |
8195 | [(set_attr "op_type" "RRE") |
8196 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8197 | |
43a09b63 | 8198 | ; lcr, lcgr |
9a91a21f | 8199 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8200 | [(set (reg CC_REGNUM) |
9a91a21f | 8201 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8202 | (const_int 0))) |
9a91a21f AS |
8203 | (set (match_operand:GPR 0 "register_operand" "=d") |
8204 | (neg:GPR (match_dup 1)))] | |
8205 | "s390_match_ccmode (insn, CCAmode)" | |
8206 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8207 | [(set_attr "op_type" "RR<E>") |
8208 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8209 | |
8210 | ; lcr, lcgr | |
9a91a21f | 8211 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8212 | [(set (reg CC_REGNUM) |
9a91a21f | 8213 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8214 | (const_int 0))) |
9a91a21f AS |
8215 | (clobber (match_scratch:GPR 0 "=d"))] |
8216 | "s390_match_ccmode (insn, CCAmode)" | |
8217 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8218 | [(set_attr "op_type" "RR<E>") |
8219 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8220 | |
8221 | ; lcr, lcgr | |
9a91a21f AS |
8222 | (define_insn "*neg<mode>2" |
8223 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8224 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8225 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8226 | "" |
8227 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8228 | [(set_attr "op_type" "RR<E>") |
8229 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8230 | |
b7d19263 | 8231 | (define_insn "*negdi2_31" |
9db1d521 HP |
8232 | [(set (match_operand:DI 0 "register_operand" "=d") |
8233 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8234 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8235 | "!TARGET_ZARCH" |
b7d19263 AK |
8236 | "#") |
8237 | ||
8238 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8239 | ||
8240 | ; Doing the twos complement separately on the SImode parts does an | |
8241 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8242 | ; ... unless the +1 on the low part created an overflow. | |
8243 | ||
8244 | (define_split | |
8245 | [(set (match_operand:DI 0 "register_operand" "") | |
8246 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8247 | (clobber (reg:CC CC_REGNUM))] | |
8248 | "!TARGET_ZARCH | |
8249 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8250 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8251 | && reload_completed" | |
26a89301 UW |
8252 | [(parallel |
8253 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8254 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8255 | (parallel |
ae156f85 | 8256 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8257 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8258 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8259 | (set (pc) | |
ae156f85 | 8260 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8261 | (pc) |
8262 | (label_ref (match_dup 6)))) | |
8263 | (parallel | |
8264 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8265 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8266 | (match_dup 6)] |
8267 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8268 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8269 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8270 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8271 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8272 | |
b7d19263 AK |
8273 | ; Like above but first make a copy of the low part of the src operand |
8274 | ; since it might overlap with the high part of the destination. | |
8275 | ||
8276 | (define_split | |
8277 | [(set (match_operand:DI 0 "register_operand" "") | |
8278 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8279 | (clobber (reg:CC CC_REGNUM))] | |
8280 | "!TARGET_ZARCH | |
8281 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8282 | && reload_completed" | |
8283 | [; Make a backup of op5 first | |
8284 | (set (match_dup 4) (match_dup 5)) | |
8285 | ; Setting op2 here might clobber op5 | |
8286 | (parallel | |
8287 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8288 | (clobber (reg:CC CC_REGNUM))]) | |
8289 | (parallel | |
8290 | [(set (reg:CCAP CC_REGNUM) | |
8291 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8292 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8293 | (set (pc) | |
8294 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8295 | (pc) | |
8296 | (label_ref (match_dup 6)))) | |
8297 | (parallel | |
8298 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8299 | (clobber (reg:CC CC_REGNUM))]) | |
8300 | (match_dup 6)] | |
8301 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8302 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8303 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8304 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8305 | operands[6] = gen_label_rtx ();") | |
8306 | ||
9db1d521 | 8307 | ; |
f5905b37 | 8308 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8309 | ; |
8310 | ||
f5905b37 | 8311 | (define_expand "neg<mode>2" |
9db1d521 | 8312 | [(parallel |
7b6baae1 AK |
8313 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8314 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8315 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8316 | "TARGET_HARD_FLOAT" |
8317 | "") | |
8318 | ||
43a09b63 | 8319 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8320 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8321 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8322 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8323 | (match_operand:BFP 2 "const0_operand" ""))) | |
8324 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8325 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8326 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8327 | "lc<xde>br\t%0,%1" |
26a89301 | 8328 | [(set_attr "op_type" "RRE") |
f5905b37 | 8329 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8330 | |
8331 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8332 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8333 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8334 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8335 | (match_operand:BFP 2 "const0_operand" ""))) | |
8336 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8337 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8338 | "lc<xde>br\t%0,%1" |
26a89301 | 8339 | [(set_attr "op_type" "RRE") |
f5905b37 | 8340 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8341 | |
85dae55a AK |
8342 | ; lcdfr |
8343 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8344 | [(set (match_operand:FP 0 "register_operand" "=f") |
8345 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8346 | "TARGET_DFP" |
85dae55a AK |
8347 | "lcdfr\t%0,%1" |
8348 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8349 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8350 | |
43a09b63 | 8351 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8352 | ; FIXME: wflcdb does not clobber cc |
f5905b37 | 8353 | (define_insn "*neg<mode>2" |
62d3f261 AK |
8354 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8355 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8356 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8357 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8358 | "@ |
8359 | lc<xde>br\t%0,%1 | |
8360 | wflcdb\t%0,%1" | |
8361 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8362 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8363 | (set_attr "type" "fsimp<mode>,*") |
8364 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8365 | |
9db1d521 HP |
8366 | |
8367 | ;; | |
8368 | ;;- Absolute value instructions. | |
8369 | ;; | |
8370 | ||
8371 | ; | |
9a91a21f | 8372 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8373 | ; |
8374 | ||
26a89301 | 8375 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8376 | [(set (reg CC_REGNUM) |
26a89301 UW |
8377 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8378 | (match_operand:SI 1 "register_operand" "d") 0) | |
8379 | (const_int 32)) (const_int 32))) | |
8380 | (const_int 0))) | |
8381 | (set (match_operand:DI 0 "register_operand" "=d") | |
8382 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8383 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8384 | "lpgfr\t%0,%1" |
729e750f WG |
8385 | [(set_attr "op_type" "RRE") |
8386 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8387 | |
8388 | (define_insn "*absdi2_sign" | |
8389 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8390 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8391 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8392 | "TARGET_ZARCH" |
26a89301 | 8393 | "lpgfr\t%0,%1" |
729e750f WG |
8394 | [(set_attr "op_type" "RRE") |
8395 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8396 | |
43a09b63 | 8397 | ; lpr, lpgr |
9a91a21f | 8398 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8399 | [(set (reg CC_REGNUM) |
9a91a21f | 8400 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8401 | (const_int 0))) |
9a91a21f AS |
8402 | (set (match_operand:GPR 0 "register_operand" "=d") |
8403 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8404 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8405 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8406 | [(set_attr "op_type" "RR<E>") |
8407 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8408 | |
9381e3f1 | 8409 | ; lpr, lpgr |
9a91a21f | 8410 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8411 | [(set (reg CC_REGNUM) |
9a91a21f | 8412 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8413 | (const_int 0))) |
9a91a21f | 8414 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8415 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8416 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8417 | [(set_attr "op_type" "RR<E>") |
8418 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8419 | |
8420 | ; lpr, lpgr | |
9a91a21f AS |
8421 | (define_insn "abs<mode>2" |
8422 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8423 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8424 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8425 | "" |
9a91a21f | 8426 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8427 | [(set_attr "op_type" "RR<E>") |
8428 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8429 | |
9db1d521 | 8430 | ; |
f5905b37 | 8431 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8432 | ; |
8433 | ||
f5905b37 | 8434 | (define_expand "abs<mode>2" |
9db1d521 | 8435 | [(parallel |
7b6baae1 AK |
8436 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8437 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8438 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8439 | "TARGET_HARD_FLOAT" |
8440 | "") | |
8441 | ||
43a09b63 | 8442 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8443 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8444 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8445 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8446 | (match_operand:BFP 2 "const0_operand" ""))) | |
8447 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8448 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8449 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8450 | "lp<xde>br\t%0,%1" |
26a89301 | 8451 | [(set_attr "op_type" "RRE") |
f5905b37 | 8452 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8453 | |
8454 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8455 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8456 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8457 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8458 | (match_operand:BFP 2 "const0_operand" ""))) | |
8459 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8460 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8461 | "lp<xde>br\t%0,%1" |
26a89301 | 8462 | [(set_attr "op_type" "RRE") |
f5905b37 | 8463 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8464 | |
85dae55a AK |
8465 | ; lpdfr |
8466 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8467 | [(set (match_operand:FP 0 "register_operand" "=f") |
8468 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8469 | "TARGET_DFP" |
85dae55a AK |
8470 | "lpdfr\t%0,%1" |
8471 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8472 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8473 | |
43a09b63 | 8474 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8475 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8476 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8477 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8478 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8479 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8480 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8481 | "@ |
8482 | lp<xde>br\t%0,%1 | |
8483 | wflpdb\t%0,%1" | |
8484 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8485 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8486 | (set_attr "type" "fsimp<mode>,*") |
8487 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8488 | |
9db1d521 | 8489 | |
3ef093a8 AK |
8490 | ;; |
8491 | ;;- Negated absolute value instructions | |
8492 | ;; | |
8493 | ||
8494 | ; | |
8495 | ; Integer | |
8496 | ; | |
8497 | ||
26a89301 | 8498 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8499 | [(set (reg CC_REGNUM) |
26a89301 UW |
8500 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8501 | (match_operand:SI 1 "register_operand" "d") 0) | |
8502 | (const_int 32)) (const_int 32)))) | |
8503 | (const_int 0))) | |
8504 | (set (match_operand:DI 0 "register_operand" "=d") | |
8505 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8506 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8507 | "lngfr\t%0,%1" |
729e750f WG |
8508 | [(set_attr "op_type" "RRE") |
8509 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8510 | |
26a89301 UW |
8511 | (define_insn "*negabsdi2_sign" |
8512 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8513 | (neg:DI (abs:DI (sign_extend:DI | |
8514 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8515 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8516 | "TARGET_ZARCH" |
26a89301 | 8517 | "lngfr\t%0,%1" |
729e750f WG |
8518 | [(set_attr "op_type" "RRE") |
8519 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8520 | |
43a09b63 | 8521 | ; lnr, lngr |
9a91a21f | 8522 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8523 | [(set (reg CC_REGNUM) |
9a91a21f | 8524 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8525 | (const_int 0))) |
9a91a21f AS |
8526 | (set (match_operand:GPR 0 "register_operand" "=d") |
8527 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8528 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8529 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8530 | [(set_attr "op_type" "RR<E>") |
8531 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8532 | |
8533 | ; lnr, lngr | |
9a91a21f | 8534 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8535 | [(set (reg CC_REGNUM) |
9a91a21f | 8536 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8537 | (const_int 0))) |
9a91a21f | 8538 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8539 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8540 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8541 | [(set_attr "op_type" "RR<E>") |
8542 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8543 | |
8544 | ; lnr, lngr | |
9a91a21f AS |
8545 | (define_insn "*negabs<mode>2" |
8546 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8547 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8548 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8549 | "" |
9a91a21f | 8550 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8551 | [(set_attr "op_type" "RR<E>") |
8552 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8553 | |
3ef093a8 AK |
8554 | ; |
8555 | ; Floating point | |
8556 | ; | |
8557 | ||
43a09b63 | 8558 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8559 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8560 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8561 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8562 | (match_operand:BFP 2 "const0_operand" ""))) | |
8563 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8564 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8565 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8566 | "ln<xde>br\t%0,%1" |
26a89301 | 8567 | [(set_attr "op_type" "RRE") |
f5905b37 | 8568 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8569 | |
8570 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8571 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8572 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8573 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8574 | (match_operand:BFP 2 "const0_operand" ""))) | |
8575 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8576 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8577 | "ln<xde>br\t%0,%1" |
26a89301 | 8578 | [(set_attr "op_type" "RRE") |
f5905b37 | 8579 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8580 | |
85dae55a AK |
8581 | ; lndfr |
8582 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8583 | [(set (match_operand:FP 0 "register_operand" "=f") |
8584 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8585 | "TARGET_DFP" |
85dae55a AK |
8586 | "lndfr\t%0,%1" |
8587 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8588 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8589 | |
43a09b63 | 8590 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8591 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8592 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8593 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8594 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8595 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8596 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8597 | "@ |
8598 | ln<xde>br\t%0,%1 | |
8599 | wflndb\t%0,%1" | |
8600 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8601 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8602 | (set_attr "type" "fsimp<mode>,*") |
8603 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8604 | |
4023fb28 UW |
8605 | ;; |
8606 | ;;- Square root instructions. | |
8607 | ;; | |
8608 | ||
8609 | ; | |
f5905b37 | 8610 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8611 | ; |
8612 | ||
9381e3f1 | 8613 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8614 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8615 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8616 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8617 | "TARGET_HARD_FLOAT" |
4023fb28 | 8618 | "@ |
f61a2c7d | 8619 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8620 | sq<xde>b\t%0,%1 |
8621 | wfsqdb\t%v0,%v1" | |
8622 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8623 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 8624 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 8625 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 8626 | |
9db1d521 HP |
8627 | |
8628 | ;; | |
8629 | ;;- One complement instructions. | |
8630 | ;; | |
8631 | ||
8632 | ; | |
342cf42b | 8633 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8634 | ; |
c7453384 | 8635 | |
342cf42b | 8636 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8637 | [(parallel |
342cf42b AS |
8638 | [(set (match_operand:INT 0 "register_operand" "") |
8639 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8640 | (const_int -1))) | |
ae156f85 | 8641 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8642 | "" |
4023fb28 | 8643 | "") |
9db1d521 HP |
8644 | |
8645 | ||
ec24698e UW |
8646 | ;; |
8647 | ;; Find leftmost bit instructions. | |
8648 | ;; | |
8649 | ||
8650 | (define_expand "clzdi2" | |
8651 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8652 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8653 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 8654 | { |
d8485bdb TS |
8655 | rtx_insn *insn; |
8656 | rtx clz_equal; | |
ec24698e | 8657 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 8658 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
8659 | |
8660 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8661 | ||
8662 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8663 | ||
9381e3f1 | 8664 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8665 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8666 | |
8667 | DONE; | |
8668 | }) | |
8669 | ||
8670 | (define_insn "clztidi2" | |
8671 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8672 | (ior:TI | |
9381e3f1 WG |
8673 | (ashift:TI |
8674 | (zero_extend:TI | |
ec24698e UW |
8675 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8676 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8677 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8678 | |
ec24698e UW |
8679 | (const_int 64)) |
8680 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8681 | (clobber (reg:CC CC_REGNUM))] | |
406fde6e | 8682 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 8683 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8684 | "flogr\t%0,%1" |
8685 | [(set_attr "op_type" "RRE")]) | |
8686 | ||
8687 | ||
9db1d521 HP |
8688 | ;; |
8689 | ;;- Rotate instructions. | |
8690 | ;; | |
8691 | ||
8692 | ; | |
9a91a21f | 8693 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8694 | ; |
8695 | ||
191eb16d AK |
8696 | (define_expand "rotl<mode>3" |
8697 | [(set (match_operand:GPR 0 "register_operand" "") | |
8698 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8699 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
9e8327e3 | 8700 | "TARGET_CPU_ZARCH" |
191eb16d | 8701 | "") |
9db1d521 | 8702 | |
43a09b63 | 8703 | ; rll, rllg |
191eb16d AK |
8704 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8705 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8706 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8707 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8708 | "TARGET_CPU_ZARCH" | |
8709 | "rll<g>\t%0,%1,<addr_style_op_ops>" | |
4989e88a | 8710 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8711 | (set_attr "atype" "reg") |
191eb16d | 8712 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8713 | |
9db1d521 HP |
8714 | |
8715 | ;; | |
f337b930 | 8716 | ;;- Shift instructions. |
9db1d521 | 8717 | ;; |
9db1d521 HP |
8718 | |
8719 | ; | |
1b48c8cc | 8720 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8721 | ; Left shifts and logical right shifts |
9db1d521 | 8722 | |
1b48c8cc AS |
8723 | (define_expand "<shift><mode>3" |
8724 | [(set (match_operand:DSI 0 "register_operand" "") | |
8725 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8726 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8727 | "" |
8728 | "") | |
8729 | ||
adf22b3f | 8730 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8731 | ; sldl, srdl |
adf22b3f AK |
8732 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8733 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8734 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8735 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8736 | "!TARGET_ZARCH" |
adf22b3f | 8737 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8738 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8739 | (set_attr "atype" "reg") |
8740 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8741 | |
adf22b3f AK |
8742 | |
8743 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8744 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8745 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8746 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8747 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8748 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8749 | "" |
65b1d8ea | 8750 | "@ |
adf22b3f AK |
8751 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8752 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8753 | [(set_attr "op_type" "RS<E>,RSY") |
8754 | (set_attr "atype" "reg,reg") | |
8755 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8756 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8757 | |
9db1d521 | 8758 | ; |
1b48c8cc | 8759 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8760 | ; Arithmetic right shifts |
9db1d521 | 8761 | |
1b48c8cc | 8762 | (define_expand "ashr<mode>3" |
9db1d521 | 8763 | [(parallel |
1b48c8cc AS |
8764 | [(set (match_operand:DSI 0 "register_operand" "") |
8765 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8766 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8767 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8768 | "" |
8769 | "") | |
8770 | ||
a9fcf821 AK |
8771 | ; FIXME: The number of alternatives is doubled here to match the fix |
8772 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8773 | ; The right fix should be to support match_scratch in the output | |
8774 | ; pattern of a define_subst. | |
8775 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8776 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8777 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8778 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8779 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8780 | "!TARGET_ZARCH" |
65b1d8ea | 8781 | "@ |
a9fcf821 AK |
8782 | srda\t%0,<addr_style_op_cc_ops> |
8783 | srda\t%0,<addr_style_op_cc_ops>" | |
8784 | [(set_attr "op_type" "RS") | |
8785 | (set_attr "atype" "reg")]) | |
ecbe845e | 8786 | |
ecbe845e | 8787 | |
43a09b63 | 8788 | ; sra, srag |
a9fcf821 AK |
8789 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8790 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8791 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8792 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8793 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8794 | "" |
65b1d8ea | 8795 | "@ |
a9fcf821 AK |
8796 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8797 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8798 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8799 | (set_attr "atype" "reg") |
01496eca | 8800 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8801 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8802 | |
9db1d521 | 8803 | |
9db1d521 HP |
8804 | ;; |
8805 | ;; Branch instruction patterns. | |
8806 | ;; | |
8807 | ||
f90b7a5a | 8808 | (define_expand "cbranch<mode>4" |
fa77b251 | 8809 | [(set (pc) |
f90b7a5a PB |
8810 | (if_then_else (match_operator 0 "comparison_operator" |
8811 | [(match_operand:GPR 1 "register_operand" "") | |
8812 | (match_operand:GPR 2 "general_operand" "")]) | |
8813 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8814 | (pc)))] |
ba956982 | 8815 | "" |
f90b7a5a PB |
8816 | "s390_emit_jump (operands[3], |
8817 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8818 | DONE;") | |
8819 | ||
8820 | (define_expand "cbranch<mode>4" | |
8821 | [(set (pc) | |
8822 | (if_then_else (match_operator 0 "comparison_operator" | |
8823 | [(match_operand:FP 1 "register_operand" "") | |
8824 | (match_operand:FP 2 "general_operand" "")]) | |
8825 | (label_ref (match_operand 3 "" "")) | |
8826 | (pc)))] | |
8827 | "TARGET_HARD_FLOAT" | |
8828 | "s390_emit_jump (operands[3], | |
8829 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8830 | DONE;") | |
8831 | ||
8832 | (define_expand "cbranchcc4" | |
8833 | [(set (pc) | |
de6fba39 | 8834 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8835 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8836 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8837 | (label_ref (match_operand 3 "" "")) |
8838 | (pc)))] | |
de6fba39 UW |
8839 | "" |
8840 | "") | |
ba956982 | 8841 | |
9db1d521 HP |
8842 | |
8843 | ;; | |
8844 | ;;- Conditional jump instructions. | |
8845 | ;; | |
8846 | ||
6590e19a UW |
8847 | (define_insn "*cjump_64" |
8848 | [(set (pc) | |
8849 | (if_then_else | |
5a3fe9b6 AK |
8850 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8851 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8852 | (label_ref (match_operand 0 "" "")) |
8853 | (pc)))] | |
8854 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8855 | { |
13e58269 | 8856 | if (get_attr_length (insn) == 4) |
d40c829f | 8857 | return "j%C1\t%l0"; |
6590e19a | 8858 | else |
d40c829f | 8859 | return "jg%C1\t%l0"; |
6590e19a UW |
8860 | } |
8861 | [(set_attr "op_type" "RI") | |
8862 | (set_attr "type" "branch") | |
8863 | (set (attr "length") | |
8864 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8865 | (const_int 4) (const_int 6)))]) | |
8866 | ||
8867 | (define_insn "*cjump_31" | |
8868 | [(set (pc) | |
8869 | (if_then_else | |
5a3fe9b6 AK |
8870 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8871 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8872 | (label_ref (match_operand 0 "" "")) |
8873 | (pc)))] | |
8874 | "!TARGET_CPU_ZARCH" | |
8875 | { | |
8d933e31 AS |
8876 | gcc_assert (get_attr_length (insn) == 4); |
8877 | return "j%C1\t%l0"; | |
10bbf137 | 8878 | } |
9db1d521 | 8879 | [(set_attr "op_type" "RI") |
077dab3b | 8880 | (set_attr "type" "branch") |
13e58269 | 8881 | (set (attr "length") |
d7f99b2c | 8882 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8883 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8884 | (const_int 4) (const_int 6)) | |
8885 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8886 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8887 | |
f314b9b1 | 8888 | (define_insn "*cjump_long" |
6590e19a UW |
8889 | [(set (pc) |
8890 | (if_then_else | |
ae156f85 | 8891 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8892 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8893 | (pc)))] |
9db1d521 | 8894 | "" |
f314b9b1 UW |
8895 | { |
8896 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8897 | return "b%C1r\t%0"; |
f314b9b1 | 8898 | else |
d40c829f | 8899 | return "b%C1\t%a0"; |
10bbf137 | 8900 | } |
c7453384 | 8901 | [(set (attr "op_type") |
f314b9b1 UW |
8902 | (if_then_else (match_operand 0 "register_operand" "") |
8903 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 8904 | (set_attr "type" "branch") |
077dab3b | 8905 | (set_attr "atype" "agen")]) |
9db1d521 | 8906 | |
177bc204 RS |
8907 | ;; A conditional return instruction. |
8908 | (define_insn "*c<code>" | |
8909 | [(set (pc) | |
8910 | (if_then_else | |
8911 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8912 | (ANY_RETURN) | |
8913 | (pc)))] | |
8914 | "s390_can_use_<code>_insn ()" | |
8915 | "b%C0r\t%%r14" | |
8916 | [(set_attr "op_type" "RR") | |
8917 | (set_attr "type" "jsr") | |
8918 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8919 | |
8920 | ;; | |
8921 | ;;- Negated conditional jump instructions. | |
8922 | ;; | |
8923 | ||
6590e19a UW |
8924 | (define_insn "*icjump_64" |
8925 | [(set (pc) | |
8926 | (if_then_else | |
ae156f85 | 8927 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8928 | (pc) |
8929 | (label_ref (match_operand 0 "" ""))))] | |
8930 | "TARGET_CPU_ZARCH" | |
c7453384 | 8931 | { |
13e58269 | 8932 | if (get_attr_length (insn) == 4) |
d40c829f | 8933 | return "j%D1\t%l0"; |
6590e19a | 8934 | else |
d40c829f | 8935 | return "jg%D1\t%l0"; |
6590e19a UW |
8936 | } |
8937 | [(set_attr "op_type" "RI") | |
8938 | (set_attr "type" "branch") | |
8939 | (set (attr "length") | |
8940 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8941 | (const_int 4) (const_int 6)))]) | |
8942 | ||
8943 | (define_insn "*icjump_31" | |
8944 | [(set (pc) | |
8945 | (if_then_else | |
ae156f85 | 8946 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8947 | (pc) |
8948 | (label_ref (match_operand 0 "" ""))))] | |
8949 | "!TARGET_CPU_ZARCH" | |
8950 | { | |
8d933e31 AS |
8951 | gcc_assert (get_attr_length (insn) == 4); |
8952 | return "j%D1\t%l0"; | |
10bbf137 | 8953 | } |
9db1d521 | 8954 | [(set_attr "op_type" "RI") |
077dab3b | 8955 | (set_attr "type" "branch") |
13e58269 | 8956 | (set (attr "length") |
d7f99b2c | 8957 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8958 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8959 | (const_int 4) (const_int 6)) | |
8960 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8961 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8962 | |
f314b9b1 | 8963 | (define_insn "*icjump_long" |
6590e19a UW |
8964 | [(set (pc) |
8965 | (if_then_else | |
ae156f85 | 8966 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 8967 | (pc) |
4fe6dea8 | 8968 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 8969 | "" |
f314b9b1 UW |
8970 | { |
8971 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8972 | return "b%D1r\t%0"; |
f314b9b1 | 8973 | else |
d40c829f | 8974 | return "b%D1\t%a0"; |
10bbf137 | 8975 | } |
c7453384 | 8976 | [(set (attr "op_type") |
f314b9b1 UW |
8977 | (if_then_else (match_operand 0 "register_operand" "") |
8978 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8979 | (set_attr "type" "branch") |
8980 | (set_attr "atype" "agen")]) | |
9db1d521 | 8981 | |
4456530d HP |
8982 | ;; |
8983 | ;;- Trap instructions. | |
8984 | ;; | |
8985 | ||
8986 | (define_insn "trap" | |
8987 | [(trap_if (const_int 1) (const_int 0))] | |
8988 | "" | |
d40c829f | 8989 | "j\t.+2" |
6590e19a | 8990 | [(set_attr "op_type" "RI") |
077dab3b | 8991 | (set_attr "type" "branch")]) |
4456530d | 8992 | |
f90b7a5a PB |
8993 | (define_expand "ctrap<mode>4" |
8994 | [(trap_if (match_operator 0 "comparison_operator" | |
8995 | [(match_operand:GPR 1 "register_operand" "") | |
8996 | (match_operand:GPR 2 "general_operand" "")]) | |
8997 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 8998 | "" |
f90b7a5a PB |
8999 | { |
9000 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9001 | operands[1], operands[2]); | |
9002 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9003 | DONE; | |
9004 | }) | |
9005 | ||
9006 | (define_expand "ctrap<mode>4" | |
9007 | [(trap_if (match_operator 0 "comparison_operator" | |
9008 | [(match_operand:FP 1 "register_operand" "") | |
9009 | (match_operand:FP 2 "general_operand" "")]) | |
9010 | (match_operand 3 "const0_operand" ""))] | |
9011 | "" | |
9012 | { | |
9013 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9014 | operands[1], operands[2]); | |
9015 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9016 | DONE; | |
9017 | }) | |
4456530d | 9018 | |
f90b7a5a PB |
9019 | (define_insn "condtrap" |
9020 | [(trap_if (match_operator 0 "s390_comparison" | |
9021 | [(match_operand 1 "cc_reg_operand" "c") | |
9022 | (const_int 0)]) | |
4456530d HP |
9023 | (const_int 0))] |
9024 | "" | |
d40c829f | 9025 | "j%C0\t.+2"; |
077dab3b HP |
9026 | [(set_attr "op_type" "RI") |
9027 | (set_attr "type" "branch")]) | |
9db1d521 | 9028 | |
963fc8d0 AK |
9029 | ; crt, cgrt, cit, cgit |
9030 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9031 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9032 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9033 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9034 | (const_int 0))] | |
9035 | "TARGET_Z10" | |
9036 | "@ | |
9037 | c<g>rt%C0\t%1,%2 | |
9038 | c<g>it%C0\t%1,%h2" | |
9039 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9040 | (set_attr "type" "branch") |
729e750f | 9041 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9042 | |
22ac2c2f | 9043 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9044 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9045 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9046 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9047 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9048 | (const_int 0))] |
9049 | "TARGET_Z10" | |
9050 | "@ | |
9051 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9052 | cl<gf>it%C0\t%1,%x2 |
9053 | cl<g>t%C0\t%1,%2" | |
9054 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9055 | (set_attr "type" "branch") | |
9056 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9057 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9058 | ||
9059 | ; lat, lgat | |
9060 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9061 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9062 | (const_int 0)) |
9063 | (const_int 0)) | |
9064 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9065 | (match_dup 0))] | |
9066 | "TARGET_ZEC12" | |
9067 | "l<g>at\t%1,%0" | |
9068 | [(set_attr "op_type" "RXY")]) | |
9069 | ||
963fc8d0 | 9070 | |
9db1d521 | 9071 | ;; |
0a3bdf9d | 9072 | ;;- Loop instructions. |
9db1d521 | 9073 | ;; |
0a3bdf9d UW |
9074 | ;; This is all complicated by the fact that since this is a jump insn |
9075 | ;; we must handle our own output reloads. | |
c7453384 | 9076 | |
f1149235 AK |
9077 | ;; branch on index |
9078 | ||
9079 | ; This splitter will be matched by combine and has to add the 2 moves | |
9080 | ; necessary to load the compare and the increment values into a | |
9081 | ; register pair as needed by brxle. | |
9082 | ||
9083 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9084 | [(set (pc) | |
9085 | (if_then_else | |
9086 | (match_operator 6 "s390_brx_operator" | |
9087 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9088 | (match_operand:GPR 2 "general_operand" "")) | |
9089 | (match_operand:GPR 3 "register_operand" "")]) | |
9090 | (label_ref (match_operand 0 "" "")) | |
9091 | (pc))) | |
9092 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9093 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9094 | (clobber (match_scratch:GPR 5 ""))] | |
9095 | "TARGET_CPU_ZARCH" | |
9096 | "#" | |
9097 | "!reload_completed && !reload_in_progress" | |
9098 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9099 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9100 | (parallel [(set (pc) | |
9101 | (if_then_else | |
9102 | (match_op_dup 6 | |
9103 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9104 | (match_dup 8)]) | |
9105 | (label_ref (match_dup 0)) | |
9106 | (pc))) | |
9107 | (set (match_dup 4) | |
9108 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9109 | (clobber (match_dup 5)) | |
9110 | (clobber (reg:CC CC_REGNUM))])] | |
9111 | { | |
9112 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9113 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9114 | gen_highpart (word_mode, dreg)); | |
9115 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9116 | gen_lowpart (word_mode, dreg)); | |
9117 | }) | |
9118 | ||
9119 | ; brxlg, brxhg | |
9120 | ||
9121 | (define_insn_and_split "*brxg_64bit" | |
9122 | [(set (pc) | |
9123 | (if_then_else | |
9124 | (match_operator 5 "s390_brx_operator" | |
9125 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9126 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9127 | (subreg:DI (match_dup 2) 8)]) | |
9128 | (label_ref (match_operand 0 "" "")) | |
9129 | (pc))) | |
9130 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9131 | (plus:DI (match_dup 1) | |
9132 | (subreg:DI (match_dup 2) 0))) | |
9133 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9134 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9135 | "TARGET_ZARCH" |
f1149235 AK |
9136 | { |
9137 | if (which_alternative != 0) | |
9138 | return "#"; | |
9139 | else if (get_attr_length (insn) == 6) | |
9140 | return "brx%E5g\t%1,%2,%l0"; | |
9141 | else | |
9142 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9143 | } | |
9144 | "&& reload_completed | |
9145 | && (!REG_P (operands[3]) | |
9146 | || !rtx_equal_p (operands[1], operands[3]))" | |
9147 | [(set (match_dup 4) (match_dup 1)) | |
9148 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9149 | (clobber (reg:CC CC_REGNUM))]) | |
9150 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9151 | (set (match_dup 3) (match_dup 4)) | |
9152 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9153 | (label_ref (match_dup 0)) | |
9154 | (pc)))] | |
9155 | "" | |
9156 | [(set_attr "op_type" "RIE") | |
9157 | (set_attr "type" "branch") | |
9158 | (set (attr "length") | |
9159 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9160 | (const_int 6) (const_int 16)))]) | |
9161 | ||
9162 | ; brxle, brxh | |
9163 | ||
9164 | (define_insn_and_split "*brx_64bit" | |
9165 | [(set (pc) | |
9166 | (if_then_else | |
9167 | (match_operator 5 "s390_brx_operator" | |
9168 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9169 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9170 | (subreg:SI (match_dup 2) 12)]) | |
9171 | (label_ref (match_operand 0 "" "")) | |
9172 | (pc))) | |
9173 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9174 | (plus:SI (match_dup 1) | |
9175 | (subreg:SI (match_dup 2) 4))) | |
9176 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9177 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9178 | "TARGET_ZARCH" |
f1149235 AK |
9179 | { |
9180 | if (which_alternative != 0) | |
9181 | return "#"; | |
9182 | else if (get_attr_length (insn) == 6) | |
9183 | return "brx%C5\t%1,%2,%l0"; | |
9184 | else | |
9185 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9186 | } | |
9187 | "&& reload_completed | |
9188 | && (!REG_P (operands[3]) | |
9189 | || !rtx_equal_p (operands[1], operands[3]))" | |
9190 | [(set (match_dup 4) (match_dup 1)) | |
9191 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9192 | (clobber (reg:CC CC_REGNUM))]) | |
9193 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9194 | (set (match_dup 3) (match_dup 4)) | |
9195 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9196 | (label_ref (match_dup 0)) | |
9197 | (pc)))] | |
9198 | "" | |
9199 | [(set_attr "op_type" "RSI") | |
9200 | (set_attr "type" "branch") | |
9201 | (set (attr "length") | |
9202 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9203 | (const_int 6) (const_int 14)))]) | |
9204 | ||
9205 | ; brxle, brxh | |
9206 | ||
9207 | (define_insn_and_split "*brx_31bit" | |
9208 | [(set (pc) | |
9209 | (if_then_else | |
9210 | (match_operator 5 "s390_brx_operator" | |
9211 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9212 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9213 | (subreg:SI (match_dup 2) 4)]) | |
9214 | (label_ref (match_operand 0 "" "")) | |
9215 | (pc))) | |
9216 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9217 | (plus:SI (match_dup 1) | |
9218 | (subreg:SI (match_dup 2) 0))) | |
9219 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9220 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9221 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
9222 | { |
9223 | if (which_alternative != 0) | |
9224 | return "#"; | |
9225 | else if (get_attr_length (insn) == 6) | |
9226 | return "brx%C5\t%1,%2,%l0"; | |
9227 | else | |
9228 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9229 | } | |
9230 | "&& reload_completed | |
9231 | && (!REG_P (operands[3]) | |
9232 | || !rtx_equal_p (operands[1], operands[3]))" | |
9233 | [(set (match_dup 4) (match_dup 1)) | |
9234 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9235 | (clobber (reg:CC CC_REGNUM))]) | |
9236 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9237 | (set (match_dup 3) (match_dup 4)) | |
9238 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9239 | (label_ref (match_dup 0)) | |
9240 | (pc)))] | |
9241 | "" | |
9242 | [(set_attr "op_type" "RSI") | |
9243 | (set_attr "type" "branch") | |
9244 | (set (attr "length") | |
9245 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9246 | (const_int 6) (const_int 14)))]) | |
9247 | ||
9248 | ||
9249 | ;; branch on count | |
9250 | ||
0a3bdf9d UW |
9251 | (define_expand "doloop_end" |
9252 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9253 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9254 | "" |
0a3bdf9d | 9255 | { |
6590e19a | 9256 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 9257 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 9258 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 9259 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9260 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9261 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9262 | else |
9263 | FAIL; | |
9264 | ||
9265 | DONE; | |
10bbf137 | 9266 | }) |
0a3bdf9d | 9267 | |
6590e19a | 9268 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9269 | [(set (pc) |
9270 | (if_then_else | |
7e665d18 | 9271 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9272 | (const_int 1)) |
9273 | (label_ref (match_operand 0 "" "")) | |
9274 | (pc))) | |
7e665d18 | 9275 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9276 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9277 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9278 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9279 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9280 | { |
9281 | if (which_alternative != 0) | |
10bbf137 | 9282 | return "#"; |
0a3bdf9d | 9283 | else if (get_attr_length (insn) == 4) |
d40c829f | 9284 | return "brct\t%1,%l0"; |
6590e19a | 9285 | else |
545d16ff | 9286 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9287 | } |
9288 | "&& reload_completed | |
9289 | && (! REG_P (operands[2]) | |
9290 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9291 | [(set (match_dup 3) (match_dup 1)) |
9292 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9293 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9294 | (const_int 0))) | |
9295 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9296 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9297 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9298 | (label_ref (match_dup 0)) |
9299 | (pc)))] | |
9300 | "" | |
9301 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9302 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9303 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9304 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9305 | (set_attr "type" "branch") |
9306 | (set (attr "length") | |
9307 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9308 | (const_int 4) (const_int 10)))]) | |
9309 | ||
9310 | (define_insn_and_split "doloop_si31" | |
9311 | [(set (pc) | |
9312 | (if_then_else | |
7e665d18 | 9313 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
9314 | (const_int 1)) |
9315 | (label_ref (match_operand 0 "" "")) | |
9316 | (pc))) | |
7e665d18 | 9317 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 9318 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9319 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9320 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
9321 | "!TARGET_CPU_ZARCH" |
9322 | { | |
9323 | if (which_alternative != 0) | |
9324 | return "#"; | |
9325 | else if (get_attr_length (insn) == 4) | |
9326 | return "brct\t%1,%l0"; | |
0a3bdf9d | 9327 | else |
8d933e31 | 9328 | gcc_unreachable (); |
10bbf137 | 9329 | } |
6590e19a UW |
9330 | "&& reload_completed |
9331 | && (! REG_P (operands[2]) | |
9332 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9333 | [(set (match_dup 3) (match_dup 1)) |
9334 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9335 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9336 | (const_int 0))) | |
9337 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9338 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9339 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9340 | (label_ref (match_dup 0)) |
9341 | (pc)))] | |
9342 | "" | |
0a3bdf9d | 9343 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
9344 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9345 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9346 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 9347 | (set_attr "type" "branch") |
0a3bdf9d | 9348 | (set (attr "length") |
d7f99b2c | 9349 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9350 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9351 | (const_int 4) (const_int 6)) | |
9352 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9353 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9354 | |
0a3bdf9d UW |
9355 | (define_insn "*doloop_si_long" |
9356 | [(set (pc) | |
9357 | (if_then_else | |
7e665d18 | 9358 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 9359 | (const_int 1)) |
3e4be43f | 9360 | (match_operand 0 "address_operand" "ZR") |
0a3bdf9d | 9361 | (pc))) |
7e665d18 | 9362 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 9363 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9364 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 9365 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9366 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9367 | { |
9368 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9369 | return "bctr\t%1,%0"; |
0a3bdf9d | 9370 | else |
d40c829f | 9371 | return "bct\t%1,%a0"; |
10bbf137 | 9372 | } |
c7453384 | 9373 | [(set (attr "op_type") |
0a3bdf9d UW |
9374 | (if_then_else (match_operand 0 "register_operand" "") |
9375 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9376 | (set_attr "type" "branch") |
729e750f | 9377 | (set_attr "atype" "agen") |
65b1d8ea AK |
9378 | (set_attr "z10prop" "z10_c") |
9379 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 9380 | |
6590e19a | 9381 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9382 | [(set (pc) |
9383 | (if_then_else | |
7e665d18 | 9384 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9385 | (const_int 1)) |
9386 | (label_ref (match_operand 0 "" "")) | |
9387 | (pc))) | |
7e665d18 | 9388 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9389 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9390 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9391 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9392 | "TARGET_ZARCH" |
0a3bdf9d UW |
9393 | { |
9394 | if (which_alternative != 0) | |
10bbf137 | 9395 | return "#"; |
0a3bdf9d | 9396 | else if (get_attr_length (insn) == 4) |
d40c829f | 9397 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9398 | else |
545d16ff | 9399 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9400 | } |
6590e19a | 9401 | "&& reload_completed |
0a3bdf9d UW |
9402 | && (! REG_P (operands[2]) |
9403 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9404 | [(set (match_dup 3) (match_dup 1)) |
9405 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9406 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9407 | (const_int 0))) | |
9408 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9409 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9410 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9411 | (label_ref (match_dup 0)) |
0a3bdf9d | 9412 | (pc)))] |
6590e19a UW |
9413 | "" |
9414 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9415 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9416 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9417 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9418 | (set_attr "type" "branch") |
9419 | (set (attr "length") | |
9420 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9421 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9422 | |
9423 | ;; | |
9424 | ;;- Unconditional jump instructions. | |
9425 | ;; | |
9426 | ||
9427 | ; | |
9428 | ; jump instruction pattern(s). | |
9429 | ; | |
9430 | ||
6590e19a UW |
9431 | (define_expand "jump" |
9432 | [(match_operand 0 "" "")] | |
9db1d521 | 9433 | "" |
6590e19a UW |
9434 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9435 | ||
9436 | (define_insn "*jump64" | |
9437 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9438 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9439 | { |
13e58269 | 9440 | if (get_attr_length (insn) == 4) |
d40c829f | 9441 | return "j\t%l0"; |
6590e19a | 9442 | else |
d40c829f | 9443 | return "jg\t%l0"; |
6590e19a UW |
9444 | } |
9445 | [(set_attr "op_type" "RI") | |
9446 | (set_attr "type" "branch") | |
9447 | (set (attr "length") | |
9448 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9449 | (const_int 4) (const_int 6)))]) | |
9450 | ||
9451 | (define_insn "*jump31" | |
9452 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9453 | "!TARGET_CPU_ZARCH" | |
9454 | { | |
8d933e31 AS |
9455 | gcc_assert (get_attr_length (insn) == 4); |
9456 | return "j\t%l0"; | |
10bbf137 | 9457 | } |
9db1d521 | 9458 | [(set_attr "op_type" "RI") |
077dab3b | 9459 | (set_attr "type" "branch") |
13e58269 | 9460 | (set (attr "length") |
d7f99b2c | 9461 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9462 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9463 | (const_int 4) (const_int 6)) | |
9464 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9465 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
9466 | |
9467 | ; | |
9468 | ; indirect-jump instruction pattern(s). | |
9469 | ; | |
9470 | ||
9471 | (define_insn "indirect_jump" | |
3e4be43f | 9472 | [(set (pc) (match_operand 0 "address_operand" "ZR"))] |
9db1d521 | 9473 | "" |
f314b9b1 UW |
9474 | { |
9475 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9476 | return "br\t%0"; |
f314b9b1 | 9477 | else |
d40c829f | 9478 | return "b\t%a0"; |
10bbf137 | 9479 | } |
c7453384 | 9480 | [(set (attr "op_type") |
f314b9b1 UW |
9481 | (if_then_else (match_operand 0 "register_operand" "") |
9482 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9483 | (set_attr "type" "branch") |
729e750f | 9484 | (set_attr "atype" "agen")]) |
9db1d521 HP |
9485 | |
9486 | ; | |
f314b9b1 | 9487 | ; casesi instruction pattern(s). |
9db1d521 HP |
9488 | ; |
9489 | ||
f314b9b1 | 9490 | (define_insn "casesi_jump" |
3e4be43f | 9491 | [(set (pc) (match_operand 0 "address_operand" "ZR")) |
f314b9b1 | 9492 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 9493 | "" |
9db1d521 | 9494 | { |
f314b9b1 | 9495 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9496 | return "br\t%0"; |
f314b9b1 | 9497 | else |
d40c829f | 9498 | return "b\t%a0"; |
10bbf137 | 9499 | } |
c7453384 | 9500 | [(set (attr "op_type") |
f314b9b1 UW |
9501 | (if_then_else (match_operand 0 "register_operand" "") |
9502 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9503 | (set_attr "type" "branch") |
9504 | (set_attr "atype" "agen")]) | |
9db1d521 | 9505 | |
f314b9b1 UW |
9506 | (define_expand "casesi" |
9507 | [(match_operand:SI 0 "general_operand" "") | |
9508 | (match_operand:SI 1 "general_operand" "") | |
9509 | (match_operand:SI 2 "general_operand" "") | |
9510 | (label_ref (match_operand 3 "" "")) | |
9511 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9512 | "" |
f314b9b1 UW |
9513 | { |
9514 | rtx index = gen_reg_rtx (SImode); | |
9515 | rtx base = gen_reg_rtx (Pmode); | |
9516 | rtx target = gen_reg_rtx (Pmode); | |
9517 | ||
9518 | emit_move_insn (index, operands[0]); | |
9519 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9520 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9521 | operands[4]); |
f314b9b1 UW |
9522 | |
9523 | if (Pmode != SImode) | |
9524 | index = convert_to_mode (Pmode, index, 1); | |
9525 | if (GET_CODE (index) != REG) | |
9526 | index = copy_to_mode_reg (Pmode, index); | |
9527 | ||
9528 | if (TARGET_64BIT) | |
9529 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9530 | else | |
a556fd39 | 9531 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9532 | |
f314b9b1 UW |
9533 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9534 | ||
542a8afa | 9535 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9536 | emit_move_insn (target, index); |
9537 | ||
9538 | if (flag_pic) | |
9539 | target = gen_rtx_PLUS (Pmode, base, target); | |
9540 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9541 | ||
9542 | DONE; | |
10bbf137 | 9543 | }) |
9db1d521 HP |
9544 | |
9545 | ||
9546 | ;; | |
9547 | ;;- Jump to subroutine. | |
9548 | ;; | |
9549 | ;; | |
9550 | ||
9551 | ; | |
9552 | ; untyped call instruction pattern(s). | |
9553 | ; | |
9554 | ||
9555 | ;; Call subroutine returning any type. | |
9556 | (define_expand "untyped_call" | |
9557 | [(parallel [(call (match_operand 0 "" "") | |
9558 | (const_int 0)) | |
9559 | (match_operand 1 "" "") | |
9560 | (match_operand 2 "" "")])] | |
9561 | "" | |
9db1d521 HP |
9562 | { |
9563 | int i; | |
9564 | ||
9565 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9566 | ||
9567 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9568 | { | |
9569 | rtx set = XVECEXP (operands[2], 0, i); | |
9570 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9571 | } | |
9572 | ||
9573 | /* The optimizer does not know that the call sets the function value | |
9574 | registers we stored in the result block. We avoid problems by | |
9575 | claiming that all hard registers are used and clobbered at this | |
9576 | point. */ | |
9577 | emit_insn (gen_blockage ()); | |
9578 | ||
9579 | DONE; | |
10bbf137 | 9580 | }) |
9db1d521 HP |
9581 | |
9582 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9583 | ;; all of memory. This blocks insns from being moved across this point. | |
9584 | ||
9585 | (define_insn "blockage" | |
10bbf137 | 9586 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9587 | "" |
4023fb28 | 9588 | "" |
d5869ca0 UW |
9589 | [(set_attr "type" "none") |
9590 | (set_attr "length" "0")]) | |
4023fb28 | 9591 | |
9db1d521 | 9592 | ; |
ed9676cf | 9593 | ; sibcall patterns |
9db1d521 HP |
9594 | ; |
9595 | ||
ed9676cf | 9596 | (define_expand "sibcall" |
44b8152b | 9597 | [(call (match_operand 0 "" "") |
ed9676cf | 9598 | (match_operand 1 "" ""))] |
9db1d521 | 9599 | "" |
9db1d521 | 9600 | { |
ed9676cf AK |
9601 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9602 | DONE; | |
9603 | }) | |
9db1d521 | 9604 | |
ed9676cf | 9605 | (define_insn "*sibcall_br" |
ae156f85 | 9606 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9607 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9608 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9609 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
9610 | "br\t%%r1" | |
9611 | [(set_attr "op_type" "RR") | |
9612 | (set_attr "type" "branch") | |
9613 | (set_attr "atype" "agen")]) | |
9db1d521 | 9614 | |
ed9676cf AK |
9615 | (define_insn "*sibcall_brc" |
9616 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9617 | (match_operand 1 "const_int_operand" "n"))] | |
9618 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9619 | "j\t%0" | |
9620 | [(set_attr "op_type" "RI") | |
9621 | (set_attr "type" "branch")]) | |
9db1d521 | 9622 | |
ed9676cf AK |
9623 | (define_insn "*sibcall_brcl" |
9624 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9625 | (match_operand 1 "const_int_operand" "n"))] | |
9626 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9627 | "jg\t%0" | |
9628 | [(set_attr "op_type" "RIL") | |
9629 | (set_attr "type" "branch")]) | |
44b8152b | 9630 | |
ed9676cf AK |
9631 | ; |
9632 | ; sibcall_value patterns | |
9633 | ; | |
9e8327e3 | 9634 | |
ed9676cf AK |
9635 | (define_expand "sibcall_value" |
9636 | [(set (match_operand 0 "" "") | |
9637 | (call (match_operand 1 "" "") | |
9638 | (match_operand 2 "" "")))] | |
9639 | "" | |
9640 | { | |
9641 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9642 | DONE; |
10bbf137 | 9643 | }) |
9db1d521 | 9644 | |
ed9676cf AK |
9645 | (define_insn "*sibcall_value_br" |
9646 | [(set (match_operand 0 "" "") | |
ae156f85 | 9647 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9648 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9649 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9650 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
9651 | "br\t%%r1" | |
9652 | [(set_attr "op_type" "RR") | |
9653 | (set_attr "type" "branch") | |
9654 | (set_attr "atype" "agen")]) | |
9655 | ||
9656 | (define_insn "*sibcall_value_brc" | |
9657 | [(set (match_operand 0 "" "") | |
9658 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9659 | (match_operand 2 "const_int_operand" "n")))] | |
9660 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9661 | "j\t%1" | |
9662 | [(set_attr "op_type" "RI") | |
9663 | (set_attr "type" "branch")]) | |
9664 | ||
9665 | (define_insn "*sibcall_value_brcl" | |
9666 | [(set (match_operand 0 "" "") | |
9667 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9668 | (match_operand 2 "const_int_operand" "n")))] | |
9669 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9670 | "jg\t%1" | |
9671 | [(set_attr "op_type" "RIL") | |
9672 | (set_attr "type" "branch")]) | |
9673 | ||
9674 | ||
9675 | ; | |
9676 | ; call instruction pattern(s). | |
9677 | ; | |
9678 | ||
9679 | (define_expand "call" | |
9680 | [(call (match_operand 0 "" "") | |
9681 | (match_operand 1 "" "")) | |
9682 | (use (match_operand 2 "" ""))] | |
44b8152b | 9683 | "" |
ed9676cf | 9684 | { |
2f7e5a0d | 9685 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9686 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9687 | DONE; | |
9688 | }) | |
44b8152b | 9689 | |
9e8327e3 UW |
9690 | (define_insn "*bras" |
9691 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9692 | (match_operand 1 "const_int_operand" "n")) | |
9693 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9694 | "!SIBLING_CALL_P (insn) |
9695 | && TARGET_SMALL_EXEC | |
ed9676cf | 9696 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9697 | "bras\t%2,%0" |
9db1d521 | 9698 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9699 | (set_attr "type" "jsr") |
9700 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9701 | |
9e8327e3 UW |
9702 | (define_insn "*brasl" |
9703 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9704 | (match_operand 1 "const_int_operand" "n")) | |
9705 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9706 | "!SIBLING_CALL_P (insn) |
9707 | && TARGET_CPU_ZARCH | |
ed9676cf | 9708 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9709 | "brasl\t%2,%0" |
9710 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9711 | (set_attr "type" "jsr") |
9712 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9713 | |
9e8327e3 | 9714 | (define_insn "*basr" |
3e4be43f | 9715 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
9716 | (match_operand 1 "const_int_operand" "n")) |
9717 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 9718 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9719 | { |
9720 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9721 | return "basr\t%2,%0"; | |
9722 | else | |
9723 | return "bas\t%2,%a0"; | |
9724 | } | |
9725 | [(set (attr "op_type") | |
9726 | (if_then_else (match_operand 0 "register_operand" "") | |
9727 | (const_string "RR") (const_string "RX"))) | |
9728 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9729 | (set_attr "atype" "agen") |
9730 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
9731 | |
9732 | ; | |
9733 | ; call_value instruction pattern(s). | |
9734 | ; | |
9735 | ||
9736 | (define_expand "call_value" | |
44b8152b UW |
9737 | [(set (match_operand 0 "" "") |
9738 | (call (match_operand 1 "" "") | |
9739 | (match_operand 2 "" ""))) | |
9740 | (use (match_operand 3 "" ""))] | |
9db1d521 | 9741 | "" |
9db1d521 | 9742 | { |
2f7e5a0d | 9743 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 9744 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 9745 | DONE; |
10bbf137 | 9746 | }) |
9db1d521 | 9747 | |
9e8327e3 | 9748 | (define_insn "*bras_r" |
c19ec8f9 | 9749 | [(set (match_operand 0 "" "") |
9e8327e3 | 9750 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 9751 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 9752 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
9753 | "!SIBLING_CALL_P (insn) |
9754 | && TARGET_SMALL_EXEC | |
ed9676cf | 9755 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9756 | "bras\t%3,%1" |
9db1d521 | 9757 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9758 | (set_attr "type" "jsr") |
9759 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9760 | |
9e8327e3 | 9761 | (define_insn "*brasl_r" |
c19ec8f9 | 9762 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9763 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9764 | (match_operand 2 "const_int_operand" "n"))) | |
9765 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
9766 | "!SIBLING_CALL_P (insn) |
9767 | && TARGET_CPU_ZARCH | |
ed9676cf | 9768 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9769 | "brasl\t%3,%1" |
9770 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9771 | (set_attr "type" "jsr") |
9772 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9773 | |
9e8327e3 | 9774 | (define_insn "*basr_r" |
c19ec8f9 | 9775 | [(set (match_operand 0 "" "") |
3e4be43f | 9776 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
9777 | (match_operand 2 "const_int_operand" "n"))) |
9778 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 9779 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9780 | { |
9781 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9782 | return "basr\t%3,%1"; | |
9783 | else | |
9784 | return "bas\t%3,%a1"; | |
9785 | } | |
9786 | [(set (attr "op_type") | |
9787 | (if_then_else (match_operand 1 "register_operand" "") | |
9788 | (const_string "RR") (const_string "RX"))) | |
9789 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9790 | (set_attr "atype" "agen") |
9791 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9792 | |
fd3cd001 UW |
9793 | ;; |
9794 | ;;- Thread-local storage support. | |
9795 | ;; | |
9796 | ||
f959607b CLT |
9797 | (define_expand "get_thread_pointer<mode>" |
9798 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
9799 | "" | |
c5aa1d12 | 9800 | "") |
fd3cd001 | 9801 | |
f959607b CLT |
9802 | (define_expand "set_thread_pointer<mode>" |
9803 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
9804 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
9805 | "" | |
c5aa1d12 UW |
9806 | "") |
9807 | ||
9808 | (define_insn "*set_tp" | |
ae156f85 | 9809 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
9810 | "" |
9811 | "" | |
9812 | [(set_attr "type" "none") | |
9813 | (set_attr "length" "0")]) | |
c7453384 | 9814 | |
fd3cd001 UW |
9815 | (define_insn "*tls_load_64" |
9816 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 9817 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
9818 | (match_operand:DI 2 "" "")] |
9819 | UNSPEC_TLS_LOAD))] | |
9820 | "TARGET_64BIT" | |
d40c829f | 9821 | "lg\t%0,%1%J2" |
9381e3f1 WG |
9822 | [(set_attr "op_type" "RXE") |
9823 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
9824 | |
9825 | (define_insn "*tls_load_31" | |
d3632d41 UW |
9826 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
9827 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
9828 | (match_operand:SI 2 "" "")] |
9829 | UNSPEC_TLS_LOAD))] | |
9830 | "!TARGET_64BIT" | |
d3632d41 | 9831 | "@ |
d40c829f UW |
9832 | l\t%0,%1%J2 |
9833 | ly\t%0,%1%J2" | |
9381e3f1 | 9834 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 9835 | (set_attr "type" "load") |
3e4be43f | 9836 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 9837 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 9838 | |
9e8327e3 | 9839 | (define_insn "*bras_tls" |
c19ec8f9 | 9840 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9841 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9842 | (match_operand 2 "const_int_operand" "n"))) | |
9843 | (clobber (match_operand 3 "register_operand" "=r")) | |
9844 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9845 | "!SIBLING_CALL_P (insn) |
9846 | && TARGET_SMALL_EXEC | |
ed9676cf | 9847 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9848 | "bras\t%3,%1%J4" |
fd3cd001 | 9849 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9850 | (set_attr "type" "jsr") |
9851 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9852 | |
9e8327e3 | 9853 | (define_insn "*brasl_tls" |
c19ec8f9 | 9854 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9855 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9856 | (match_operand 2 "const_int_operand" "n"))) | |
9857 | (clobber (match_operand 3 "register_operand" "=r")) | |
9858 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9859 | "!SIBLING_CALL_P (insn) |
9860 | && TARGET_CPU_ZARCH | |
ed9676cf | 9861 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9862 | "brasl\t%3,%1%J4" |
9863 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9864 | (set_attr "type" "jsr") |
9865 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9866 | |
9e8327e3 | 9867 | (define_insn "*basr_tls" |
c19ec8f9 | 9868 | [(set (match_operand 0 "" "") |
3e4be43f | 9869 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
9870 | (match_operand 2 "const_int_operand" "n"))) |
9871 | (clobber (match_operand 3 "register_operand" "=r")) | |
9872 | (use (match_operand 4 "" ""))] | |
ed9676cf | 9873 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9874 | { |
9875 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9876 | return "basr\t%3,%1%J4"; | |
9877 | else | |
9878 | return "bas\t%3,%a1%J4"; | |
9879 | } | |
9880 | [(set (attr "op_type") | |
9881 | (if_then_else (match_operand 1 "register_operand" "") | |
9882 | (const_string "RR") (const_string "RX"))) | |
9883 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9884 | (set_attr "atype" "agen") |
9885 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9886 | |
e0374221 AS |
9887 | ;; |
9888 | ;;- Atomic operations | |
9889 | ;; | |
9890 | ||
9891 | ; | |
78ce265b | 9892 | ; memory barrier patterns. |
e0374221 AS |
9893 | ; |
9894 | ||
78ce265b RH |
9895 | (define_expand "mem_signal_fence" |
9896 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
9897 | "" |
9898 | { | |
78ce265b RH |
9899 | /* The s390 memory model is strong enough not to require any |
9900 | barrier in order to synchronize a thread with itself. */ | |
9901 | DONE; | |
9902 | }) | |
9903 | ||
9904 | (define_expand "mem_thread_fence" | |
9905 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
9906 | "" | |
9907 | { | |
9908 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
9909 | enough not to require barriers of any kind. */ | |
46b35980 | 9910 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
9911 | { |
9912 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
9913 | MEM_VOLATILE_P (mem) = 1; | |
9914 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
9915 | } | |
9916 | DONE; | |
e0374221 AS |
9917 | }) |
9918 | ||
78ce265b RH |
9919 | ; Although bcr is superscalar on Z10, this variant will never |
9920 | ; become part of an execution group. | |
a9cc3f58 AK |
9921 | ; With z196 we can make use of the fast-BCR-serialization facility. |
9922 | ; This allows for a slightly faster sync which is sufficient for our | |
9923 | ; purposes. | |
78ce265b | 9924 | (define_insn "mem_thread_fence_1" |
e0374221 | 9925 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 9926 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 9927 | "" |
a9cc3f58 AK |
9928 | { |
9929 | if (TARGET_Z196) | |
9930 | return "bcr\t14,0"; | |
9931 | else | |
9932 | return "bcr\t15,0"; | |
9933 | } | |
9934 | [(set_attr "op_type" "RR") | |
9935 | (set_attr "mnemonic" "bcr_flush") | |
9936 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 9937 | |
78ce265b RH |
9938 | ; |
9939 | ; atomic load/store operations | |
9940 | ; | |
9941 | ||
9942 | ; Atomic loads need not examine the memory model at all. | |
9943 | (define_expand "atomic_load<mode>" | |
9944 | [(match_operand:DINT 0 "register_operand") ;; output | |
9945 | (match_operand:DINT 1 "memory_operand") ;; memory | |
9946 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9947 | "" | |
9948 | { | |
75cc21e2 AK |
9949 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
9950 | FAIL; | |
9951 | ||
78ce265b RH |
9952 | if (<MODE>mode == TImode) |
9953 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
9954 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9955 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
9956 | else | |
9957 | emit_move_insn (operands[0], operands[1]); | |
9958 | DONE; | |
9959 | }) | |
9960 | ||
9961 | ; Different from movdi_31 in that we want no splitters. | |
9962 | (define_insn "atomic_loaddi_1" | |
9963 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
9964 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
9965 | UNSPEC_MOVA))] | |
9966 | "!TARGET_ZARCH" | |
9967 | "@ | |
9968 | lm\t%0,%M0,%S1 | |
9969 | lmy\t%0,%M0,%S1 | |
9970 | ld\t%0,%1 | |
9971 | ldy\t%0,%1" | |
9972 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 9973 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
9974 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
9975 | ||
9976 | (define_insn "atomic_loadti_1" | |
9977 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 9978 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
9979 | UNSPEC_MOVA))] |
9980 | "TARGET_ZARCH" | |
9981 | "lpq\t%0,%1" | |
9982 | [(set_attr "op_type" "RXY") | |
9983 | (set_attr "type" "other")]) | |
9984 | ||
9985 | ; Atomic stores must(?) enforce sequential consistency. | |
9986 | (define_expand "atomic_store<mode>" | |
9987 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
9988 | (match_operand:DINT 1 "register_operand") ;; input | |
9989 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9990 | "" | |
9991 | { | |
46b35980 | 9992 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 9993 | |
75cc21e2 AK |
9994 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
9995 | FAIL; | |
9996 | ||
78ce265b RH |
9997 | if (<MODE>mode == TImode) |
9998 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
9999 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10000 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10001 | else | |
10002 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10003 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10004 | emit_insn (gen_mem_thread_fence (operands[2])); |
10005 | DONE; | |
10006 | }) | |
10007 | ||
10008 | ; Different from movdi_31 in that we want no splitters. | |
10009 | (define_insn "atomic_storedi_1" | |
10010 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10011 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10012 | UNSPEC_MOVA))] | |
10013 | "!TARGET_ZARCH" | |
10014 | "@ | |
10015 | stm\t%1,%N1,%S0 | |
10016 | stmy\t%1,%N1,%S0 | |
10017 | std %1,%0 | |
10018 | stdy %1,%0" | |
10019 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10020 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10021 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10022 | ||
10023 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10024 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10025 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10026 | UNSPEC_MOVA))] | |
10027 | "TARGET_ZARCH" | |
10028 | "stpq\t%1,%0" | |
10029 | [(set_attr "op_type" "RXY") | |
10030 | (set_attr "type" "other")]) | |
e0374221 AS |
10031 | |
10032 | ; | |
10033 | ; compare and swap patterns. | |
10034 | ; | |
10035 | ||
78ce265b RH |
10036 | (define_expand "atomic_compare_and_swap<mode>" |
10037 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 10038 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
10039 | (match_operand:DGPR 2 "memory_operand") ;; memory |
10040 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
10041 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
10042 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
10043 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10044 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10045 | "" | |
10046 | { | |
215770ad UW |
10047 | rtx cc, cmp, output = operands[1]; |
10048 | ||
10049 | if (!register_operand (output, <MODE>mode)) | |
10050 | output = gen_reg_rtx (<MODE>mode); | |
10051 | ||
75cc21e2 AK |
10052 | if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2]))) |
10053 | FAIL; | |
10054 | ||
78ce265b | 10055 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
10056 | (output, operands[2], operands[3], operands[4])); |
10057 | ||
10058 | /* We deliberately accept non-register operands in the predicate | |
10059 | to ensure the write back to the output operand happens *before* | |
10060 | the store-flags code below. This makes it easier for combine | |
10061 | to merge the store-flags code with a potential test-and-branch | |
10062 | pattern following (immediately!) afterwards. */ | |
10063 | if (output != operands[1]) | |
10064 | emit_move_insn (operands[1], output); | |
10065 | ||
78ce265b RH |
10066 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
10067 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
10068 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
10069 | DONE; | |
10070 | }) | |
e0374221 | 10071 | |
78ce265b RH |
10072 | (define_expand "atomic_compare_and_swap<mode>" |
10073 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 10074 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
10075 | (match_operand:HQI 2 "memory_operand") ;; memory |
10076 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
10077 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
10078 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
10079 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10080 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 10081 | "" |
78ce265b RH |
10082 | { |
10083 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
10084 | operands[3], operands[4], INTVAL (operands[5])); | |
10085 | DONE; | |
10086 | }) | |
3093f076 | 10087 | |
78ce265b RH |
10088 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10089 | [(parallel | |
10090 | [(set (match_operand:DGPR 0 "register_operand") | |
10091 | (match_operand:DGPR 1 "memory_operand")) | |
10092 | (set (match_dup 1) | |
10093 | (unspec_volatile:DGPR | |
10094 | [(match_dup 1) | |
10095 | (match_operand:DGPR 2 "register_operand") | |
10096 | (match_operand:DGPR 3 "register_operand")] | |
10097 | UNSPECV_CAS)) | |
10098 | (set (reg:CCZ1 CC_REGNUM) | |
10099 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
10100 | "") | |
10101 | ||
10102 | ; cdsg, csg | |
10103 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10104 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
3e4be43f | 10105 | (match_operand:TDI 1 "memory_operand" "+S")) |
8006eaa6 | 10106 | (set (match_dup 1) |
78ce265b | 10107 | (unspec_volatile:TDI |
8006eaa6 | 10108 | [(match_dup 1) |
78ce265b RH |
10109 | (match_operand:TDI 2 "register_operand" "0") |
10110 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
10111 | UNSPECV_CAS)) |
10112 | (set (reg:CCZ1 CC_REGNUM) | |
10113 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
10114 | "TARGET_ZARCH" |
10115 | "c<td>sg\t%0,%3,%S1" | |
10116 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10117 | (set_attr "type" "sem")]) |
10118 | ||
78ce265b RH |
10119 | ; cds, cdsy |
10120 | (define_insn "*atomic_compare_and_swapdi_2" | |
10121 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
10122 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 10123 | (set (match_dup 1) |
78ce265b RH |
10124 | (unspec_volatile:DI |
10125 | [(match_dup 1) | |
10126 | (match_operand:DI 2 "register_operand" "0,0") | |
10127 | (match_operand:DI 3 "register_operand" "r,r")] | |
10128 | UNSPECV_CAS)) | |
10129 | (set (reg:CCZ1 CC_REGNUM) | |
10130 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
10131 | "!TARGET_ZARCH" | |
10132 | "@ | |
10133 | cds\t%0,%3,%S1 | |
10134 | cdsy\t%0,%3,%S1" | |
10135 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10136 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10137 | (set_attr "type" "sem")]) |
10138 | ||
10139 | ; cs, csy | |
10140 | (define_insn "*atomic_compare_and_swapsi_3" | |
10141 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
10142 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
10143 | (set (match_dup 1) | |
10144 | (unspec_volatile:SI | |
e0374221 | 10145 | [(match_dup 1) |
78ce265b RH |
10146 | (match_operand:SI 2 "register_operand" "0,0") |
10147 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10148 | UNSPECV_CAS)) |
69950452 AS |
10149 | (set (reg:CCZ1 CC_REGNUM) |
10150 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 10151 | "" |
78ce265b RH |
10152 | "@ |
10153 | cs\t%0,%3,%S1 | |
10154 | csy\t%0,%3,%S1" | |
10155 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10156 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10157 | (set_attr "type" "sem")]) |
10158 | ||
45d18331 AS |
10159 | ; |
10160 | ; Other atomic instruction patterns. | |
10161 | ; | |
10162 | ||
65b1d8ea AK |
10163 | ; z196 load and add, xor, or and and instructions |
10164 | ||
78ce265b RH |
10165 | (define_expand "atomic_fetch_<atomic><mode>" |
10166 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10167 | (ATOMIC_Z196:GPR | |
10168 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10169 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10170 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10171 | "TARGET_Z196" |
78ce265b | 10172 | { |
75cc21e2 AK |
10173 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10174 | FAIL; | |
10175 | ||
78ce265b RH |
10176 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10177 | (operands[0], operands[1], operands[2])); | |
10178 | DONE; | |
10179 | }) | |
65b1d8ea AK |
10180 | |
10181 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10182 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10183 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10184 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10185 | (set (match_dup 1) |
10186 | (unspec_volatile:GPR | |
10187 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10188 | (match_operand:GPR 2 "general_operand" "d"))] | |
10189 | UNSPECV_ATOMIC_OP)) | |
10190 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10191 | "TARGET_Z196" |
78ce265b RH |
10192 | "la<noxa><g>\t%0,%2,%1" |
10193 | [(set_attr "op_type" "RSY") | |
10194 | (set_attr "type" "sem")]) | |
65b1d8ea | 10195 | |
78ce265b RH |
10196 | ;; For SImode and larger, the optabs.c code will do just fine in |
10197 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10198 | ;; better by expanding our own loop. | |
65b1d8ea | 10199 | |
78ce265b RH |
10200 | (define_expand "atomic_<atomic><mode>" |
10201 | [(ATOMIC:HQI | |
10202 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10203 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10204 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10205 | "" |
78ce265b RH |
10206 | { |
10207 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10208 | operands[1], false); | |
10209 | DONE; | |
10210 | }) | |
45d18331 | 10211 | |
78ce265b RH |
10212 | (define_expand "atomic_fetch_<atomic><mode>" |
10213 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10214 | (ATOMIC:HQI | |
10215 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10216 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10217 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10218 | "" |
78ce265b RH |
10219 | { |
10220 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10221 | operands[2], false); | |
10222 | DONE; | |
10223 | }) | |
10224 | ||
10225 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10226 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10227 | (ATOMIC:HQI | |
10228 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10229 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10230 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10231 | "" | |
10232 | { | |
10233 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10234 | operands[2], true); | |
10235 | DONE; | |
10236 | }) | |
10237 | ||
10238 | (define_expand "atomic_exchange<mode>" | |
10239 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10240 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10241 | (match_operand:HQI 2 "general_operand") ;; val in | |
10242 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10243 | "" |
78ce265b RH |
10244 | { |
10245 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
10246 | operands[2], false); | |
10247 | DONE; | |
10248 | }) | |
45d18331 | 10249 | |
9db1d521 HP |
10250 | ;; |
10251 | ;;- Miscellaneous instructions. | |
10252 | ;; | |
10253 | ||
10254 | ; | |
10255 | ; allocate stack instruction pattern(s). | |
10256 | ; | |
10257 | ||
10258 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10259 | [(match_operand 0 "general_operand" "") |
10260 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10261 | "TARGET_BACKCHAIN" |
9db1d521 | 10262 | { |
ef44a6ff | 10263 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10264 | |
ef44a6ff UW |
10265 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10266 | anti_adjust_stack (operands[1]); | |
10267 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10268 | |
ef44a6ff UW |
10269 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10270 | DONE; | |
10bbf137 | 10271 | }) |
9db1d521 HP |
10272 | |
10273 | ||
10274 | ; | |
43ab026f | 10275 | ; setjmp instruction pattern. |
9db1d521 HP |
10276 | ; |
10277 | ||
9db1d521 | 10278 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10279 | [(match_operand 0 "" "")] |
f314b9b1 | 10280 | "flag_pic" |
9db1d521 | 10281 | { |
585539a1 | 10282 | emit_insn (s390_load_got ()); |
c41c1387 | 10283 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10284 | DONE; |
fd7643fb | 10285 | }) |
9db1d521 | 10286 | |
9db1d521 HP |
10287 | ;; These patterns say how to save and restore the stack pointer. We need not |
10288 | ;; save the stack pointer at function level since we are careful to | |
10289 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10290 | ;; when we restore the stack pointer. | |
10291 | ;; | |
10292 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10293 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10294 | ;; save area is a memory location. | |
10295 | ||
10296 | (define_expand "save_stack_function" | |
10297 | [(match_operand 0 "general_operand" "") | |
10298 | (match_operand 1 "general_operand" "")] | |
10299 | "" | |
10300 | "DONE;") | |
10301 | ||
10302 | (define_expand "restore_stack_function" | |
10303 | [(match_operand 0 "general_operand" "") | |
10304 | (match_operand 1 "general_operand" "")] | |
10305 | "" | |
10306 | "DONE;") | |
10307 | ||
10308 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10309 | [(match_operand 0 "register_operand" "") |
10310 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10311 | "TARGET_BACKCHAIN" |
9db1d521 | 10312 | { |
ef44a6ff UW |
10313 | rtx temp = gen_reg_rtx (Pmode); |
10314 | ||
10315 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10316 | emit_move_insn (operands[0], operands[1]); | |
10317 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10318 | ||
10319 | DONE; | |
10bbf137 | 10320 | }) |
9db1d521 HP |
10321 | |
10322 | (define_expand "save_stack_nonlocal" | |
10323 | [(match_operand 0 "memory_operand" "") | |
10324 | (match_operand 1 "register_operand" "")] | |
10325 | "" | |
9db1d521 | 10326 | { |
ef44a6ff UW |
10327 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10328 | ||
10329 | /* Copy the backchain to the first word, sp to the second and the | |
10330 | literal pool base to the third. */ | |
10331 | ||
9602b6a1 AK |
10332 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10333 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10334 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10335 | ||
b3d31392 | 10336 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10337 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10338 | |
9602b6a1 AK |
10339 | emit_move_insn (save_sp, operands[1]); |
10340 | emit_move_insn (save_bp, base); | |
9db1d521 | 10341 | |
9db1d521 | 10342 | DONE; |
10bbf137 | 10343 | }) |
9db1d521 HP |
10344 | |
10345 | (define_expand "restore_stack_nonlocal" | |
10346 | [(match_operand 0 "register_operand" "") | |
10347 | (match_operand 1 "memory_operand" "")] | |
10348 | "" | |
9db1d521 | 10349 | { |
490ceeb4 | 10350 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10351 | rtx temp = NULL_RTX; |
9db1d521 | 10352 | |
43ab026f | 10353 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10354 | literal pool base from the third. */ |
43ab026f | 10355 | |
9602b6a1 AK |
10356 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10357 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10358 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10359 | ||
b3d31392 | 10360 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10361 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10362 | |
9602b6a1 AK |
10363 | emit_move_insn (base, save_bp); |
10364 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10365 | |
10366 | if (temp) | |
10367 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10368 | ||
c41c1387 | 10369 | emit_use (base); |
9db1d521 | 10370 | DONE; |
10bbf137 | 10371 | }) |
9db1d521 | 10372 | |
7bcebb25 AK |
10373 | (define_expand "exception_receiver" |
10374 | [(const_int 0)] | |
10375 | "" | |
10376 | { | |
10377 | s390_set_has_landing_pad_p (true); | |
10378 | DONE; | |
10379 | }) | |
9db1d521 HP |
10380 | |
10381 | ; | |
10382 | ; nop instruction pattern(s). | |
10383 | ; | |
10384 | ||
10385 | (define_insn "nop" | |
10386 | [(const_int 0)] | |
10387 | "" | |
d40c829f | 10388 | "lr\t0,0" |
729e750f WG |
10389 | [(set_attr "op_type" "RR") |
10390 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10391 | |
d277db6b WG |
10392 | (define_insn "nop1" |
10393 | [(const_int 1)] | |
10394 | "" | |
10395 | "lr\t1,1" | |
10396 | [(set_attr "op_type" "RR")]) | |
10397 | ||
f8af0e30 DV |
10398 | ;;- Undeletable nops (used for hotpatching) |
10399 | ||
10400 | (define_insn "nop_2_byte" | |
10401 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10402 | "" | |
4bbc8970 | 10403 | "nopr\t%%r0" |
f8af0e30 DV |
10404 | [(set_attr "op_type" "RR")]) |
10405 | ||
10406 | (define_insn "nop_4_byte" | |
10407 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10408 | "" | |
10409 | "nop\t0" | |
10410 | [(set_attr "op_type" "RX")]) | |
10411 | ||
10412 | (define_insn "nop_6_byte" | |
10413 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
10414 | "TARGET_CPU_ZARCH" | |
10415 | "brcl\t0, 0" | |
10416 | [(set_attr "op_type" "RIL")]) | |
10417 | ||
9db1d521 HP |
10418 | |
10419 | ; | |
10420 | ; Special literal pool access instruction pattern(s). | |
10421 | ; | |
10422 | ||
416cf582 UW |
10423 | (define_insn "*pool_entry" |
10424 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10425 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10426 | "" |
9db1d521 | 10427 | { |
ef4bddc2 | 10428 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10429 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10430 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10431 | return ""; |
10432 | } | |
b628bd8e | 10433 | [(set (attr "length") |
416cf582 | 10434 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10435 | |
9bb86f41 UW |
10436 | (define_insn "pool_align" |
10437 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10438 | UNSPECV_POOL_ALIGN)] | |
10439 | "" | |
10440 | ".align\t%0" | |
b628bd8e | 10441 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10442 | |
9bb86f41 UW |
10443 | (define_insn "pool_section_start" |
10444 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10445 | "" | |
b929b470 MK |
10446 | { |
10447 | switch_to_section (targetm.asm_out.function_rodata_section | |
10448 | (current_function_decl)); | |
10449 | return ""; | |
10450 | } | |
b628bd8e | 10451 | [(set_attr "length" "0")]) |
b2ccb744 | 10452 | |
9bb86f41 UW |
10453 | (define_insn "pool_section_end" |
10454 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10455 | "" | |
b929b470 MK |
10456 | { |
10457 | switch_to_section (current_function_section ()); | |
10458 | return ""; | |
10459 | } | |
b628bd8e | 10460 | [(set_attr "length" "0")]) |
b2ccb744 | 10461 | |
5af2f3d3 | 10462 | (define_insn "main_base_31_small" |
9e8327e3 UW |
10463 | [(set (match_operand 0 "register_operand" "=a") |
10464 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10465 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10466 | "basr\t%0,0" |
10467 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
10468 | (set_attr "type" "la") |
10469 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10470 | |
10471 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
10472 | [(set (match_operand 0 "register_operand" "=a") |
10473 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 10474 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 10475 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 10476 | "bras\t%0,%2" |
65b1d8ea AK |
10477 | [(set_attr "op_type" "RI") |
10478 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10479 | |
10480 | (define_insn "main_base_64" | |
9e8327e3 UW |
10481 | [(set (match_operand 0 "register_operand" "=a") |
10482 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10483 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10484 | "larl\t%0,%1" |
10485 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10486 | (set_attr "type" "larl") |
729e750f | 10487 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
10488 | |
10489 | (define_insn "main_pool" | |
585539a1 UW |
10490 | [(set (match_operand 0 "register_operand" "=a") |
10491 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10492 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10493 | { |
10494 | gcc_unreachable (); | |
10495 | } | |
9381e3f1 | 10496 | [(set (attr "type") |
d7f99b2c | 10497 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 10498 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 10499 | |
aee4e0db | 10500 | (define_insn "reload_base_31" |
9e8327e3 UW |
10501 | [(set (match_operand 0 "register_operand" "=a") |
10502 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10503 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10504 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 10505 | [(set_attr "length" "6") |
65b1d8ea AK |
10506 | (set_attr "type" "la") |
10507 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 10508 | |
aee4e0db | 10509 | (define_insn "reload_base_64" |
9e8327e3 UW |
10510 | [(set (match_operand 0 "register_operand" "=a") |
10511 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10512 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10513 | "larl\t%0,%1" |
aee4e0db | 10514 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10515 | (set_attr "type" "larl") |
729e750f | 10516 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10517 | |
aee4e0db | 10518 | (define_insn "pool" |
fd7643fb | 10519 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10520 | "" |
8d933e31 AS |
10521 | { |
10522 | gcc_unreachable (); | |
10523 | } | |
b628bd8e | 10524 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10525 | |
4023fb28 UW |
10526 | ;; |
10527 | ;; Insns related to generating the function prologue and epilogue. | |
10528 | ;; | |
10529 | ||
10530 | ||
10531 | (define_expand "prologue" | |
10532 | [(use (const_int 0))] | |
10533 | "" | |
10bbf137 | 10534 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10535 | |
10536 | (define_expand "epilogue" | |
10537 | [(use (const_int 1))] | |
10538 | "" | |
ed9676cf AK |
10539 | "s390_emit_epilogue (false); DONE;") |
10540 | ||
10541 | (define_expand "sibcall_epilogue" | |
10542 | [(use (const_int 0))] | |
10543 | "" | |
10544 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10545 | |
177bc204 RS |
10546 | ;; A direct return instruction, without using an epilogue. |
10547 | (define_insn "<code>" | |
10548 | [(ANY_RETURN)] | |
10549 | "s390_can_use_<code>_insn ()" | |
10550 | "br\t%%r14" | |
10551 | [(set_attr "op_type" "RR") | |
10552 | (set_attr "type" "jsr") | |
10553 | (set_attr "atype" "agen")]) | |
10554 | ||
9e8327e3 | 10555 | (define_insn "*return" |
4023fb28 | 10556 | [(return) |
9e8327e3 UW |
10557 | (use (match_operand 0 "register_operand" "a"))] |
10558 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10559 | "br\t%0" |
4023fb28 | 10560 | [(set_attr "op_type" "RR") |
c7453384 | 10561 | (set_attr "type" "jsr") |
077dab3b | 10562 | (set_attr "atype" "agen")]) |
4023fb28 | 10563 | |
4023fb28 | 10564 | |
c7453384 | 10565 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 10566 | ;; pointer. This is used for compatibility. |
c7453384 EC |
10567 | |
10568 | (define_expand "ptr_extend" | |
10569 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10570 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 10571 | "TARGET_64BIT" |
c7453384 | 10572 | { |
c7453384 EC |
10573 | emit_insn (gen_anddi3 (operands[0], |
10574 | gen_lowpart (DImode, operands[1]), | |
10575 | GEN_INT (0x7fffffff))); | |
c7453384 | 10576 | DONE; |
10bbf137 | 10577 | }) |
4798630c D |
10578 | |
10579 | ;; Instruction definition to expand eh_return macro to support | |
10580 | ;; swapping in special linkage return addresses. | |
10581 | ||
10582 | (define_expand "eh_return" | |
10583 | [(use (match_operand 0 "register_operand" ""))] | |
10584 | "TARGET_TPF" | |
10585 | { | |
10586 | s390_emit_tpf_eh_return (operands[0]); | |
10587 | DONE; | |
10588 | }) | |
10589 | ||
7b8acc34 AK |
10590 | ; |
10591 | ; Stack Protector Patterns | |
10592 | ; | |
10593 | ||
10594 | (define_expand "stack_protect_set" | |
10595 | [(set (match_operand 0 "memory_operand" "") | |
10596 | (match_operand 1 "memory_operand" ""))] | |
10597 | "" | |
10598 | { | |
10599 | #ifdef TARGET_THREAD_SSP_OFFSET | |
10600 | operands[1] | |
10601 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10602 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10603 | #endif | |
10604 | if (TARGET_64BIT) | |
10605 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10606 | else | |
10607 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10608 | ||
10609 | DONE; | |
10610 | }) | |
10611 | ||
10612 | (define_insn "stack_protect_set<mode>" | |
10613 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
10614 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
10615 | "" | |
10616 | "mvc\t%O0(%G0,%R0),%S1" | |
10617 | [(set_attr "op_type" "SS")]) | |
10618 | ||
10619 | (define_expand "stack_protect_test" | |
10620 | [(set (reg:CC CC_REGNUM) | |
10621 | (compare (match_operand 0 "memory_operand" "") | |
10622 | (match_operand 1 "memory_operand" ""))) | |
10623 | (match_operand 2 "" "")] | |
10624 | "" | |
10625 | { | |
f90b7a5a | 10626 | rtx cc_reg, test; |
7b8acc34 AK |
10627 | #ifdef TARGET_THREAD_SSP_OFFSET |
10628 | operands[1] | |
10629 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10630 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10631 | #endif | |
7b8acc34 AK |
10632 | if (TARGET_64BIT) |
10633 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
10634 | else | |
10635 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
10636 | ||
f90b7a5a PB |
10637 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
10638 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
10639 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
10640 | DONE; |
10641 | }) | |
10642 | ||
10643 | (define_insn "stack_protect_test<mode>" | |
10644 | [(set (reg:CCZ CC_REGNUM) | |
10645 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
10646 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
10647 | "" | |
10648 | "clc\t%O0(%G0,%R0),%S1" | |
10649 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
10650 | |
10651 | ; This is used in s390_emit_prologue in order to prevent insns | |
10652 | ; adjusting the stack pointer to be moved over insns writing stack | |
10653 | ; slots using a copy of the stack pointer in a different register. | |
10654 | (define_insn "stack_tie" | |
10655 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
10656 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
10657 | "" | |
10658 | "" | |
10659 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
10660 | |
10661 | ||
82c6f58a AK |
10662 | (define_insn "stack_restore_from_fpr" |
10663 | [(set (reg:DI STACK_REGNUM) | |
10664 | (match_operand:DI 0 "register_operand" "f")) | |
10665 | (clobber (mem:BLK (scratch)))] | |
10666 | "TARGET_Z10" | |
10667 | "lgdr\t%%r15,%0" | |
10668 | [(set_attr "op_type" "RRE")]) | |
10669 | ||
963fc8d0 AK |
10670 | ; |
10671 | ; Data prefetch patterns | |
10672 | ; | |
10673 | ||
10674 | (define_insn "prefetch" | |
3e4be43f UW |
10675 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
10676 | (match_operand:SI 1 "const_int_operand" " n,n") | |
10677 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 10678 | "TARGET_Z10" |
963fc8d0 | 10679 | { |
4fe6dea8 AK |
10680 | switch (which_alternative) |
10681 | { | |
10682 | case 0: | |
4fe6dea8 | 10683 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 10684 | case 1: |
4fe6dea8 AK |
10685 | if (larl_operand (operands[0], Pmode)) |
10686 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 10687 | /* fallthrough */ |
4fe6dea8 AK |
10688 | default: |
10689 | ||
10690 | /* This might be reached for symbolic operands with an odd | |
10691 | addend. We simply omit the prefetch for such rare cases. */ | |
10692 | ||
10693 | return ""; | |
10694 | } | |
9381e3f1 | 10695 | } |
22d72dbc AK |
10696 | [(set_attr "type" "load,larl") |
10697 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
10698 | (set_attr "z10prop" "z10_super") |
10699 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
10700 | |
10701 | ||
10702 | ; | |
10703 | ; Byte swap instructions | |
10704 | ; | |
10705 | ||
511f5bb1 AK |
10706 | ; FIXME: There is also mvcin but we cannot use it since src and target |
10707 | ; may overlap. | |
50dc4eed | 10708 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 10709 | (define_insn "bswap<mode>2" |
3e4be43f UW |
10710 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
10711 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
677fbff4 | 10712 | "TARGET_CPU_ZARCH" |
07da44ab AK |
10713 | "@ |
10714 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
10715 | lrv<g>\t%0,%1 |
10716 | strv<g>\t%1,%0" | |
10717 | [(set_attr "type" "*,load,store") | |
10718 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 10719 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10720 | |
511f5bb1 | 10721 | (define_insn "bswaphi2" |
3e4be43f UW |
10722 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
10723 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
511f5bb1 | 10724 | "TARGET_CPU_ZARCH" |
6f5a59d1 AK |
10725 | "@ |
10726 | # | |
10727 | lrvh\t%0,%1 | |
10728 | strvh\t%1,%0" | |
10729 | [(set_attr "type" "*,load,store") | |
10730 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 10731 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10732 | |
6f5a59d1 AK |
10733 | (define_split |
10734 | [(set (match_operand:HI 0 "register_operand" "") | |
10735 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
10736 | "TARGET_CPU_ZARCH" | |
10737 | [(set (match_dup 2) (bswap:SI (match_dup 3))) | |
9060e335 | 10738 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 10739 | { |
9060e335 | 10740 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
10741 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
10742 | }) | |
10743 | ||
10744 | ||
65b1d8ea AK |
10745 | ; |
10746 | ; Population count instruction | |
10747 | ; | |
10748 | ||
10749 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
10750 | ; portions and stores the result in the corresponding bytes in op0. | |
10751 | (define_insn "*popcount<mode>" | |
10752 | [(set (match_operand:INT 0 "register_operand" "=d") | |
10753 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
10754 | (clobber (reg:CC CC_REGNUM))] | |
10755 | "TARGET_Z196" | |
10756 | "popcnt\t%0,%1" | |
10757 | [(set_attr "op_type" "RRE")]) | |
10758 | ||
10759 | (define_expand "popcountdi2" | |
10760 | [; popcnt op0, op1 | |
10761 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
10762 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
10763 | UNSPEC_POPCNT)) | |
10764 | (clobber (reg:CC CC_REGNUM))]) | |
10765 | ; sllg op2, op0, 32 | |
10766 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
10767 | ; agr op0, op2 | |
10768 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10769 | (clobber (reg:CC CC_REGNUM))]) | |
10770 | ; sllg op2, op0, 16 | |
17465c6e | 10771 | (set (match_dup 2) |
65b1d8ea AK |
10772 | (ashift:DI (match_dup 0) (const_int 16))) |
10773 | ; agr op0, op2 | |
10774 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10775 | (clobber (reg:CC CC_REGNUM))]) | |
10776 | ; sllg op2, op0, 8 | |
10777 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
10778 | ; agr op0, op2 | |
10779 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10780 | (clobber (reg:CC CC_REGNUM))]) | |
10781 | ; srlg op0, op0, 56 | |
10782 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
10783 | "TARGET_Z196 && TARGET_64BIT" | |
10784 | "operands[2] = gen_reg_rtx (DImode);") | |
10785 | ||
10786 | (define_expand "popcountsi2" | |
10787 | [; popcnt op0, op1 | |
10788 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
10789 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
10790 | UNSPEC_POPCNT)) | |
10791 | (clobber (reg:CC CC_REGNUM))]) | |
10792 | ; sllk op2, op0, 16 | |
17465c6e | 10793 | (set (match_dup 2) |
65b1d8ea AK |
10794 | (ashift:SI (match_dup 0) (const_int 16))) |
10795 | ; ar op0, op2 | |
10796 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10797 | (clobber (reg:CC CC_REGNUM))]) | |
10798 | ; sllk op2, op0, 8 | |
10799 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
10800 | ; ar op0, op2 | |
10801 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10802 | (clobber (reg:CC CC_REGNUM))]) | |
10803 | ; srl op0, op0, 24 | |
10804 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
10805 | "TARGET_Z196" | |
10806 | "operands[2] = gen_reg_rtx (SImode);") | |
10807 | ||
10808 | (define_expand "popcounthi2" | |
10809 | [; popcnt op0, op1 | |
10810 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
10811 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
10812 | UNSPEC_POPCNT)) | |
10813 | (clobber (reg:CC CC_REGNUM))]) | |
10814 | ; sllk op2, op0, 8 | |
17465c6e | 10815 | (set (match_dup 2) |
65b1d8ea AK |
10816 | (ashift:SI (match_dup 0) (const_int 8))) |
10817 | ; ar op0, op2 | |
10818 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10819 | (clobber (reg:CC CC_REGNUM))]) | |
10820 | ; srl op0, op0, 8 | |
10821 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
10822 | "TARGET_Z196" | |
10823 | "operands[2] = gen_reg_rtx (SImode);") | |
10824 | ||
10825 | (define_expand "popcountqi2" | |
10826 | [; popcnt op0, op1 | |
10827 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
10828 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
10829 | UNSPEC_POPCNT)) | |
10830 | (clobber (reg:CC CC_REGNUM))])] | |
10831 | "TARGET_Z196" | |
10832 | "") | |
10833 | ||
10834 | ;; | |
10835 | ;;- Copy sign instructions | |
10836 | ;; | |
10837 | ||
10838 | (define_insn "copysign<mode>3" | |
10839 | [(set (match_operand:FP 0 "register_operand" "=f") | |
10840 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
10841 | (match_operand:FP 2 "register_operand" "f")] | |
10842 | UNSPEC_COPYSIGN))] | |
10843 | "TARGET_Z196" | |
10844 | "cpsdr\t%0,%2,%1" | |
10845 | [(set_attr "op_type" "RRF") | |
10846 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
10847 | |
10848 | ||
10849 | ;; | |
10850 | ;;- Transactional execution instructions | |
10851 | ;; | |
10852 | ||
10853 | ; This splitter helps combine to make use of CC directly when | |
10854 | ; comparing the integer result of a tbegin builtin with a constant. | |
10855 | ; The unspec is already removed by canonicalize_comparison. So this | |
10856 | ; splitters only job is to turn the PARALLEL into separate insns | |
10857 | ; again. Unfortunately this only works with the very first cc/int | |
10858 | ; compare since combine is not able to deal with data flow across | |
10859 | ; basic block boundaries. | |
10860 | ||
10861 | ; It needs to be an insn pattern as well since combine does not apply | |
10862 | ; the splitter directly. Combine would only use it if it actually | |
10863 | ; would reduce the number of instructions. | |
10864 | (define_insn_and_split "*ccraw_to_int" | |
10865 | [(set (pc) | |
10866 | (if_then_else | |
10867 | (match_operator 0 "s390_eqne_operator" | |
10868 | [(reg:CCRAW CC_REGNUM) | |
10869 | (match_operand 1 "const_int_operand" "")]) | |
10870 | (label_ref (match_operand 2 "" "")) | |
10871 | (pc))) | |
10872 | (set (match_operand:SI 3 "register_operand" "=d") | |
10873 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
10874 | "" | |
10875 | "#" | |
10876 | "" | |
10877 | [(set (match_dup 3) | |
10878 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
10879 | (set (pc) | |
10880 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
10881 | (label_ref (match_dup 2)) | |
10882 | (pc)))] | |
10883 | "") | |
10884 | ||
10885 | ; Non-constrained transaction begin | |
10886 | ||
10887 | (define_expand "tbegin" | |
ee163e72 AK |
10888 | [(match_operand:SI 0 "register_operand" "") |
10889 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10890 | "TARGET_HTM" |
10891 | { | |
10892 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
10893 | DONE; | |
10894 | }) | |
10895 | ||
10896 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
10897 | [(match_operand:SI 0 "register_operand" "") |
10898 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10899 | "TARGET_HTM" |
10900 | { | |
10901 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
10902 | DONE; | |
10903 | }) | |
10904 | ||
10905 | (define_expand "tbegin_retry" | |
ee163e72 AK |
10906 | [(match_operand:SI 0 "register_operand" "") |
10907 | (match_operand:BLK 1 "memory_operand" "") | |
10908 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10909 | "TARGET_HTM" |
10910 | { | |
10911 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
10912 | DONE; | |
10913 | }) | |
10914 | ||
10915 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
10916 | [(match_operand:SI 0 "register_operand" "") |
10917 | (match_operand:BLK 1 "memory_operand" "") | |
10918 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10919 | "TARGET_HTM" |
10920 | { | |
10921 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
10922 | DONE; | |
10923 | }) | |
10924 | ||
c914ac45 AK |
10925 | ; Clobber VRs since they don't get restored |
10926 | (define_insn "tbegin_1_z13" | |
10927 | [(set (reg:CCRAW CC_REGNUM) | |
10928 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
10929 | UNSPECV_TBEGIN)) | |
10930 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10931 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
10932 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
10933 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
10934 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
10935 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
10936 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
10937 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
10938 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
10939 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
10940 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
10941 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
10942 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
10943 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
10944 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
10945 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
10946 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
10947 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
10948 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10949 | ; not supposed to be used for immediates (see genpreds.c). | |
10950 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10951 | "tbegin\t%1,%x0" | |
10952 | [(set_attr "op_type" "SIL")]) | |
10953 | ||
5a3fe9b6 AK |
10954 | (define_insn "tbegin_1" |
10955 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 10956 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 10957 | UNSPECV_TBEGIN)) |
2561451d AK |
10958 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
10959 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
10960 | (clobber (reg:DF 16)) |
10961 | (clobber (reg:DF 17)) | |
10962 | (clobber (reg:DF 18)) | |
10963 | (clobber (reg:DF 19)) | |
10964 | (clobber (reg:DF 20)) | |
10965 | (clobber (reg:DF 21)) | |
10966 | (clobber (reg:DF 22)) | |
10967 | (clobber (reg:DF 23)) | |
10968 | (clobber (reg:DF 24)) | |
10969 | (clobber (reg:DF 25)) | |
10970 | (clobber (reg:DF 26)) | |
10971 | (clobber (reg:DF 27)) | |
10972 | (clobber (reg:DF 28)) | |
10973 | (clobber (reg:DF 29)) | |
10974 | (clobber (reg:DF 30)) | |
10975 | (clobber (reg:DF 31))] | |
10976 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10977 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
10978 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
10979 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10980 | [(set_attr "op_type" "SIL")]) |
10981 | ||
10982 | ; Same as above but without the FPR clobbers | |
10983 | (define_insn "tbegin_nofloat_1" | |
10984 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
10985 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
10986 | UNSPECV_TBEGIN)) | |
10987 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10988 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
10989 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10990 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10991 | [(set_attr "op_type" "SIL")]) |
10992 | ||
10993 | ||
10994 | ; Constrained transaction begin | |
10995 | ||
10996 | (define_expand "tbeginc" | |
10997 | [(set (reg:CCRAW CC_REGNUM) | |
10998 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
10999 | UNSPECV_TBEGINC))] | |
11000 | "TARGET_HTM" | |
11001 | "") | |
11002 | ||
11003 | (define_insn "*tbeginc_1" | |
11004 | [(set (reg:CCRAW CC_REGNUM) | |
11005 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11006 | UNSPECV_TBEGINC))] | |
11007 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11008 | "tbeginc\t0,%x0" | |
11009 | [(set_attr "op_type" "SIL")]) | |
11010 | ||
11011 | ; Transaction end | |
11012 | ||
11013 | (define_expand "tend" | |
11014 | [(set (reg:CCRAW CC_REGNUM) | |
11015 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11016 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11017 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11018 | "TARGET_HTM" | |
11019 | "") | |
11020 | ||
11021 | (define_insn "*tend_1" | |
11022 | [(set (reg:CCRAW CC_REGNUM) | |
11023 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11024 | "TARGET_HTM" | |
11025 | "tend" | |
11026 | [(set_attr "op_type" "S")]) | |
11027 | ||
11028 | ; Transaction abort | |
11029 | ||
11030 | (define_expand "tabort" | |
eae48192 | 11031 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11032 | UNSPECV_TABORT)] |
11033 | "TARGET_HTM && operands != NULL" | |
11034 | { | |
11035 | if (CONST_INT_P (operands[0]) | |
11036 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11037 | { | |
f3981e7e | 11038 | error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC |
5a3fe9b6 AK |
11039 | ". Values in range 0 through 255 are reserved.", |
11040 | INTVAL (operands[0])); | |
11041 | FAIL; | |
11042 | } | |
11043 | }) | |
11044 | ||
11045 | (define_insn "*tabort_1" | |
eae48192 | 11046 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11047 | UNSPECV_TABORT)] |
11048 | "TARGET_HTM && operands != NULL" | |
11049 | "tabort\t%Y0" | |
11050 | [(set_attr "op_type" "S")]) | |
11051 | ||
eae48192 AK |
11052 | (define_insn "*tabort_1_plus" |
11053 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11054 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11055 | UNSPECV_TABORT)] | |
11056 | "TARGET_HTM && operands != NULL | |
11057 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11058 | "tabort\t%1(%0)" | |
11059 | [(set_attr "op_type" "S")]) | |
11060 | ||
5a3fe9b6 AK |
11061 | ; Transaction extract nesting depth |
11062 | ||
11063 | (define_insn "etnd" | |
11064 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11065 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11066 | "TARGET_HTM" | |
11067 | "etnd\t%0" | |
11068 | [(set_attr "op_type" "RRE")]) | |
11069 | ||
11070 | ; Non-transactional store | |
11071 | ||
11072 | (define_insn "ntstg" | |
3e4be43f | 11073 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11074 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11075 | UNSPECV_NTSTG))] | |
11076 | "TARGET_HTM" | |
11077 | "ntstg\t%1,%0" | |
11078 | [(set_attr "op_type" "RXY")]) | |
11079 | ||
11080 | ; Transaction perform processor assist | |
11081 | ||
11082 | (define_expand "tx_assist" | |
2561451d AK |
11083 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11084 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
11085 | (const_int 1)] |
11086 | UNSPECV_PPA)] | |
11087 | "TARGET_HTM" | |
2561451d | 11088 | "") |
5a3fe9b6 AK |
11089 | |
11090 | (define_insn "*ppa" | |
11091 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11092 | (match_operand:SI 1 "register_operand" "d") | |
11093 | (match_operand 2 "const_int_operand" "I")] | |
11094 | UNSPECV_PPA)] | |
11095 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 11096 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11097 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11098 | |
11099 | ||
11100 | ; Set and get floating point control register | |
11101 | ||
3af82a61 | 11102 | (define_insn "sfpc" |
004f64e1 AK |
11103 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11104 | UNSPECV_SFPC)] | |
11105 | "TARGET_HARD_FLOAT" | |
11106 | "sfpc\t%0") | |
11107 | ||
3af82a61 | 11108 | (define_insn "efpc" |
004f64e1 AK |
11109 | [(set (match_operand:SI 0 "register_operand" "=d") |
11110 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11111 | "TARGET_HARD_FLOAT" | |
11112 | "efpc\t%0") | |
3af82a61 AK |
11113 | |
11114 | ||
11115 | ; Load count to block boundary | |
11116 | ||
11117 | (define_insn "lcbb" | |
11118 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11119 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11120 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11121 | (clobber (reg:CC CC_REGNUM))] | |
11122 | "TARGET_Z13" | |
9a36359e | 11123 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11124 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11125 | |
11126 | ; Handle -fsplit-stack. | |
11127 | ||
11128 | (define_expand "split_stack_prologue" | |
11129 | [(const_int 0)] | |
11130 | "" | |
11131 | { | |
11132 | s390_expand_split_stack_prologue (); | |
11133 | DONE; | |
11134 | }) | |
11135 | ||
11136 | ;; If there are operand 0 bytes available on the stack, jump to | |
11137 | ;; operand 1. | |
11138 | ||
11139 | (define_expand "split_stack_space_check" | |
11140 | [(set (pc) (if_then_else | |
11141 | (ltu (minus (reg 15) | |
11142 | (match_operand 0 "register_operand")) | |
11143 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11144 | (label_ref (match_operand 1)) | |
11145 | (pc)))] | |
11146 | "" | |
11147 | { | |
11148 | /* Offset from thread pointer to __private_ss. */ | |
11149 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11150 | rtx tp = s390_get_thread_pointer (); | |
11151 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11152 | rtx reg = gen_reg_rtx (Pmode); | |
11153 | rtx cc; | |
11154 | if (TARGET_64BIT) | |
11155 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11156 | else | |
11157 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11158 | cc = s390_emit_compare (GT, reg, guard); | |
11159 | s390_emit_jump (operands[1], cc); | |
11160 | ||
11161 | DONE; | |
11162 | }) | |
11163 | ||
11164 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
11165 | ;; parameter block label, label to be called by __morestack, frame size, | |
11166 | ;; stack parameter size. | |
11167 | ||
11168 | (define_insn "split_stack_data" | |
11169 | [(unspec_volatile [(match_operand 0 "" "X") | |
11170 | (match_operand 1 "" "X") | |
11171 | (match_operand 2 "const_int_operand" "X") | |
11172 | (match_operand 3 "const_int_operand" "X")] | |
11173 | UNSPECV_SPLIT_STACK_DATA)] | |
11174 | "TARGET_CPU_ZARCH" | |
11175 | { | |
11176 | switch_to_section (targetm.asm_out.function_rodata_section | |
11177 | (current_function_decl)); | |
11178 | ||
11179 | if (TARGET_64BIT) | |
11180 | output_asm_insn (".align\t8", operands); | |
11181 | else | |
11182 | output_asm_insn (".align\t4", operands); | |
11183 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11184 | CODE_LABEL_NUMBER (operands[0])); | |
11185 | if (TARGET_64BIT) | |
11186 | { | |
11187 | output_asm_insn (".quad\t%2", operands); | |
11188 | output_asm_insn (".quad\t%3", operands); | |
11189 | output_asm_insn (".quad\t%1-%0", operands); | |
11190 | } | |
11191 | else | |
11192 | { | |
11193 | output_asm_insn (".long\t%2", operands); | |
11194 | output_asm_insn (".long\t%3", operands); | |
11195 | output_asm_insn (".long\t%1-%0", operands); | |
11196 | } | |
11197 | ||
11198 | switch_to_section (current_function_section ()); | |
11199 | return ""; | |
11200 | } | |
11201 | [(set_attr "length" "0")]) | |
11202 | ||
11203 | ||
11204 | ;; A jg with minimal fuss for use in split stack prologue. | |
11205 | ||
11206 | (define_expand "split_stack_call" | |
11207 | [(match_operand 0 "bras_sym_operand" "X") | |
11208 | (match_operand 1 "" "")] | |
11209 | "TARGET_CPU_ZARCH" | |
11210 | { | |
11211 | if (TARGET_64BIT) | |
11212 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11213 | else | |
11214 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11215 | DONE; | |
11216 | }) | |
11217 | ||
11218 | (define_insn "split_stack_call_<mode>" | |
11219 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11220 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11221 | (reg:P 1)] | |
11222 | UNSPECV_SPLIT_STACK_CALL))] | |
11223 | "TARGET_CPU_ZARCH" | |
11224 | "jg\t%0" | |
11225 | [(set_attr "op_type" "RIL") | |
11226 | (set_attr "type" "branch")]) | |
11227 | ||
11228 | ;; Also a conditional one. | |
11229 | ||
11230 | (define_expand "split_stack_cond_call" | |
11231 | [(match_operand 0 "bras_sym_operand" "X") | |
11232 | (match_operand 1 "" "") | |
11233 | (match_operand 2 "" "")] | |
11234 | "TARGET_CPU_ZARCH" | |
11235 | { | |
11236 | if (TARGET_64BIT) | |
11237 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11238 | else | |
11239 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11240 | DONE; | |
11241 | }) | |
11242 | ||
11243 | (define_insn "split_stack_cond_call_<mode>" | |
11244 | [(set (pc) | |
11245 | (if_then_else | |
11246 | (match_operand 1 "" "") | |
11247 | (label_ref (match_operand 2 "" "")) | |
11248 | (pc))) | |
11249 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11250 | (reg:P 1)] | |
11251 | UNSPECV_SPLIT_STACK_CALL))] | |
11252 | "TARGET_CPU_ZARCH" | |
11253 | "jg%C1\t%0" | |
11254 | [(set_attr "op_type" "RIL") | |
11255 | (set_attr "type" "branch")]) | |
539405d5 AK |
11256 | |
11257 | (define_insn "osc_break" | |
11258 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
11259 | "" | |
11260 | "bcr\t7,%%r0" | |
11261 | [(set_attr "op_type" "RR")]) |