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4673c1a0 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
dc4951d9 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
4673c1a0 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
0c0a8ea5 | 4 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
4673c1a0 | 5 | ;; This file is part of GNU CC. |
6 | ||
7 | ;; GNU CC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
10 | ;; any later version. | |
11 | ||
12 | ;; GNU CC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GNU CC; see the file COPYING. If not, write to | |
19 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | ;; Boston, MA 02111-1307, USA. | |
21 | ||
22 | ;; | |
23 | ;; Special constraints for s/390 machine description: | |
24 | ;; | |
25 | ;; a -- Any address register from 1 to 15. | |
26 | ;; d -- Any register from 0 to 15. | |
27 | ;; I -- An 8-bit constant (0..255). | |
28 | ;; J -- A 12-bit constant (0..4095). | |
29 | ;; K -- A 16-bit constant (-32768..32767). | |
30 | ;; Q -- A memory reference without index-register. | |
31 | ;; S -- Valid operand for the LARL instruction. | |
32 | ;; | |
33 | ;; Special formats used for outputting 390 instructions. | |
34 | ;; | |
35 | ;; %b -- Print a constant byte integer. xy | |
36 | ;; %h -- Print a signed 16-bit. wxyz | |
37 | ;; %N -- Print next register (second word of a DImode reg) or next word. | |
38 | ;; %M -- Print next register (second word of a TImode reg) or next word. | |
39 | ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)). | |
40 | ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). | |
41 | ;; | |
42 | ;; We have a special constraint for pattern matching. | |
43 | ;; | |
44 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
45 | ;; | |
4673c1a0 | 46 | |
4673c1a0 | 47 | |
369293ed | 48 | ;; Define an insn type attribute. This is used in function unit delay |
49 | ;; computations. | |
4673c1a0 | 50 | |
8b4a4127 | 51 | (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3" |
369293ed | 52 | (const_string "integer")) |
4673c1a0 | 53 | |
369293ed | 54 | ;; Insn are devide in two classes: |
cb0ccc1e | 55 | ;; mem: Insn accessing memory |
369293ed | 56 | ;; reg: Insn operands all in registers |
4673c1a0 | 57 | |
369293ed | 58 | (define_attr "atype" "reg,mem" |
59 | (const_string "reg")) | |
4673c1a0 | 60 | |
369293ed | 61 | ;; Generic pipeline function unit. |
4673c1a0 | 62 | |
8b4a4127 | 63 | (define_function_unit "integer" 1 0 |
64 | (eq_attr "type" "none") 0 0) | |
65 | ||
369293ed | 66 | (define_function_unit "integer" 1 0 |
67 | (eq_attr "type" "integer") 1 1) | |
4673c1a0 | 68 | |
369293ed | 69 | (define_function_unit "integer" 1 0 |
70 | (eq_attr "type" "load") 1 1) | |
4673c1a0 | 71 | |
369293ed | 72 | (define_function_unit "integer" 1 0 |
73 | (eq_attr "type" "la") 1 1) | |
4673c1a0 | 74 | |
369293ed | 75 | (define_function_unit "integer" 1 0 |
76 | (eq_attr "type" "lr") 1 1) | |
4673c1a0 | 77 | |
369293ed | 78 | (define_function_unit "integer" 1 0 |
79 | (eq_attr "type" "store") 1 1) | |
4673c1a0 | 80 | |
8b4a4127 | 81 | (define_function_unit "integer" 1 0 |
82 | (eq_attr "type" "lm") 2 2) | |
83 | ||
84 | (define_function_unit "integer" 1 0 | |
85 | (eq_attr "type" "stm") 2 2) | |
86 | ||
87 | (define_function_unit "integer" 1 0 | |
88 | (eq_attr "type" "cs") 5 5) | |
89 | ||
90 | (define_function_unit "integer" 1 0 | |
91 | (eq_attr "type" "vs") 30 30) | |
92 | ||
369293ed | 93 | (define_function_unit "integer" 1 0 |
94 | (eq_attr "type" "jsr") 5 5) | |
4673c1a0 | 95 | |
369293ed | 96 | (define_function_unit "integer" 1 0 |
97 | (eq_attr "type" "imul") 7 7) | |
98 | ||
99 | (define_function_unit "integer" 1 0 | |
100 | (eq_attr "type" "fmul") 6 6) | |
4673c1a0 | 101 | |
369293ed | 102 | (define_function_unit "integer" 1 0 |
103 | (eq_attr "type" "idiv") 33 33) | |
4673c1a0 | 104 | |
369293ed | 105 | (define_function_unit "integer" 1 0 |
106 | (eq_attr "type" "fdiv") 33 33) | |
4673c1a0 | 107 | |
369293ed | 108 | (define_function_unit "integer" 1 0 |
109 | (eq_attr "type" "o2") 2 2) | |
4673c1a0 | 110 | |
369293ed | 111 | (define_function_unit "integer" 1 0 |
112 | (eq_attr "type" "o3") 3 3) | |
4673c1a0 | 113 | |
369293ed | 114 | (define_function_unit "integer" 1 0 |
115 | (eq_attr "type" "other") 5 5) | |
116 | ||
117 | ;; Operand type. Used to default length attribute values | |
4673c1a0 | 118 | |
119 | (define_attr "op_type" | |
120 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE" | |
121 | (const_string "RX")) | |
122 | ||
123 | ;; Length in bytes. | |
124 | ||
125 | (define_attr "length" "" | |
126 | (cond [ (eq_attr "op_type" "E") (const_int 2) | |
127 | (eq_attr "op_type" "RR") (const_int 2) | |
128 | (eq_attr "op_type" "RX") (const_int 4) | |
129 | (eq_attr "op_type" "RI") (const_int 4) | |
130 | (eq_attr "op_type" "RRE") (const_int 4) | |
131 | (eq_attr "op_type" "RS") (const_int 4) | |
132 | (eq_attr "op_type" "RSI") (const_int 4) | |
133 | (eq_attr "op_type" "RX") (const_int 4) | |
134 | (eq_attr "op_type" "S") (const_int 4) | |
135 | (eq_attr "op_type" "SI") (const_int 4) | |
136 | (eq_attr "op_type" "SS") (const_int 6) | |
137 | (eq_attr "op_type" "SSE") (const_int 6) | |
138 | (eq_attr "op_type" "RXE") (const_int 6) | |
139 | (eq_attr "op_type" "RSE") (const_int 6) | |
140 | (eq_attr "op_type" "RIL") (const_int 6)] | |
141 | (const_int 4))) | |
142 | ||
143 | ;; Define attributes for `asm' insns. | |
144 | ||
369293ed | 145 | (define_asm_attributes [(set_attr "type" "other") |
4673c1a0 | 146 | (set_attr "op_type" "NN")]) |
147 | ||
148 | ;; | |
149 | ;; Condition Codes | |
150 | ;; | |
151 | ; | |
152 | ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) | |
153 | ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) | |
154 | ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) | |
155 | ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) | |
156 | ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) | |
157 | ||
158 | ; CCZ -> CCL / CCZ1 | |
159 | ; CCZ1 -> CCA/CCU/CCS/CCT | |
160 | ; CCS -> CCA | |
161 | ||
162 | ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST | |
163 | ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT | |
164 | ||
165 | ||
166 | ;; | |
167 | ;;- Compare instructions. | |
168 | ;; | |
169 | ||
170 | (define_expand "cmpdi" | |
171 | [(set (reg:CC 33) | |
172 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
173 | (match_operand:DI 1 "general_operand" "")))] | |
174 | "TARGET_64BIT" | |
175 | " | |
176 | { | |
177 | s390_compare_op0 = operands[0]; | |
178 | s390_compare_op1 = operands[1]; | |
179 | DONE; | |
180 | }") | |
181 | ||
182 | (define_expand "cmpsi" | |
183 | [(set (reg:CC 33) | |
184 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
185 | (match_operand:SI 1 "general_operand" "")))] | |
186 | "" | |
187 | " | |
188 | { | |
189 | s390_compare_op0 = operands[0]; | |
190 | s390_compare_op1 = operands[1]; | |
191 | DONE; | |
192 | }") | |
193 | ||
4673c1a0 | 194 | (define_expand "cmpdf" |
195 | [(set (reg:CC 33) | |
196 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
197 | (match_operand:DF 1 "general_operand" "")))] | |
198 | "TARGET_HARD_FLOAT" | |
199 | " | |
200 | { | |
201 | s390_compare_op0 = operands[0]; | |
202 | s390_compare_op1 = operands[1]; | |
203 | DONE; | |
204 | }") | |
205 | ||
206 | (define_expand "cmpsf" | |
207 | [(set (reg:CC 33) | |
208 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
209 | (match_operand:SF 1 "general_operand" "")))] | |
210 | "TARGET_HARD_FLOAT" | |
211 | " | |
212 | { | |
213 | s390_compare_op0 = operands[0]; | |
214 | s390_compare_op1 = operands[1]; | |
215 | DONE; | |
216 | }") | |
217 | ||
218 | ||
c6821d1c | 219 | ; Test-under-Mask (zero_extract) instructions |
4673c1a0 | 220 | |
c6821d1c | 221 | (define_insn "*tmdi_ext" |
4673c1a0 | 222 | [(set (reg 33) |
223 | (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d") | |
8b4a4127 | 224 | (match_operand:DI 1 "const_int_operand" "n") |
225 | (match_operand:DI 2 "const_int_operand" "n")) | |
4673c1a0 | 226 | (const_int 0)))] |
8b4a4127 | 227 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
228 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 | |
229 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 | |
230 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
231 | == INTVAL (operands[2]) >> 4" | |
4673c1a0 | 232 | "* |
233 | { | |
8b4a4127 | 234 | int part = INTVAL (operands[2]) >> 4; |
235 | int block = (1 << INTVAL (operands[1])) - 1; | |
236 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
4673c1a0 | 237 | |
8b4a4127 | 238 | operands[2] = GEN_INT (block << shift); |
4673c1a0 | 239 | |
8b4a4127 | 240 | switch (part) |
241 | { | |
242 | case 0: return \"tmhh\\t%0,%x2\"; | |
243 | case 1: return \"tmhl\\t%0,%x2\"; | |
244 | case 2: return \"tmlh\\t%0,%x2\"; | |
245 | case 3: return \"tmll\\t%0,%x2\"; | |
246 | default: abort (); | |
247 | } | |
248 | }" | |
249 | [(set_attr "op_type" "RI")]) | |
250 | ||
c6821d1c | 251 | (define_insn "*tmsi_ext" |
4673c1a0 | 252 | [(set (reg 33) |
c6821d1c | 253 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") |
254 | (match_operand:SI 1 "const_int_operand" "n") | |
255 | (match_operand:SI 2 "const_int_operand" "n")) | |
4673c1a0 | 256 | (const_int 0)))] |
c6821d1c | 257 | "s390_match_ccmode(insn, CCTmode) |
258 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 | |
259 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 | |
260 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
261 | == INTVAL (operands[2]) >> 4" | |
4673c1a0 | 262 | "* |
263 | { | |
c6821d1c | 264 | int part = INTVAL (operands[2]) >> 4; |
265 | int block = (1 << INTVAL (operands[1])) - 1; | |
266 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
267 | ||
268 | operands[2] = GEN_INT (block << shift); | |
4673c1a0 | 269 | |
8b4a4127 | 270 | switch (part) |
4673c1a0 | 271 | { |
c6821d1c | 272 | case 0: return \"tmh\\t%0,%x2\"; |
273 | case 1: return \"tml\\t%0,%x2\"; | |
8b4a4127 | 274 | default: abort (); |
4673c1a0 | 275 | } |
4673c1a0 | 276 | }" |
8b4a4127 | 277 | [(set_attr "op_type" "RI")]) |
278 | ||
c6821d1c | 279 | (define_insn "*tmqi_ext" |
8b4a4127 | 280 | [(set (reg 33) |
e7f0624a | 281 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q") |
c6821d1c | 282 | (match_operand:SI 1 "const_int_operand" "n") |
283 | (match_operand:SI 2 "const_int_operand" "n")) | |
8b4a4127 | 284 | (const_int 0)))] |
c6821d1c | 285 | "s390_match_ccmode(insn, CCTmode) |
286 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 | |
287 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" | |
8b4a4127 | 288 | "* |
289 | { | |
c6821d1c | 290 | int block = (1 << INTVAL (operands[1])) - 1; |
291 | int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); | |
4673c1a0 | 292 | |
c6821d1c | 293 | operands[2] = GEN_INT (block << shift); |
294 | return \"tm\\t%0,%b2\"; | |
8b4a4127 | 295 | }" |
296 | [(set_attr "op_type" "SI") | |
297 | (set_attr "atype" "mem")]) | |
4673c1a0 | 298 | |
c6821d1c | 299 | ; Test-under-Mask instructions |
4673c1a0 | 300 | |
c6821d1c | 301 | (define_insn "*tmdi_mem" |
302 | [(set (reg 33) | |
2e5d1042 | 303 | (compare (and:DI (match_operand:DI 0 "memory_operand" "Q") |
c6821d1c | 304 | (match_operand:DI 1 "immediate_operand" "n")) |
305 | (match_operand:DI 2 "immediate_operand" "n")))] | |
306 | "TARGET_64BIT | |
307 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) | |
308 | && s390_single_qi (operands[1], DImode, 0) >= 0" | |
309 | "* | |
310 | { | |
311 | int part = s390_single_qi (operands[1], DImode, 0); | |
312 | operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part)); | |
313 | ||
314 | operands[0] = gen_rtx_MEM (QImode, | |
315 | plus_constant (XEXP (operands[0], 0), part)); | |
316 | return \"tm\\t%0,%b1\"; | |
317 | }" | |
318 | [(set_attr "op_type" "SI") | |
319 | (set_attr "atype" "mem")]) | |
320 | ||
321 | (define_insn "*tmsi_mem" | |
8b4a4127 | 322 | [(set (reg 33) |
2e5d1042 | 323 | (compare (and:SI (match_operand:SI 0 "memory_operand" "Q") |
8b4a4127 | 324 | (match_operand:SI 1 "immediate_operand" "n")) |
c6821d1c | 325 | (match_operand:SI 2 "immediate_operand" "n")))] |
326 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) | |
8b4a4127 | 327 | && s390_single_qi (operands[1], SImode, 0) >= 0" |
328 | "* | |
329 | { | |
330 | int part = s390_single_qi (operands[1], SImode, 0); | |
331 | operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part)); | |
332 | ||
333 | operands[0] = gen_rtx_MEM (QImode, | |
334 | plus_constant (XEXP (operands[0], 0), part)); | |
335 | return \"tm\\t%0,%b1\"; | |
336 | }" | |
337 | [(set_attr "op_type" "SI") | |
338 | (set_attr "atype" "mem")]) | |
4673c1a0 | 339 | |
c6821d1c | 340 | (define_insn "*tmhi_mem" |
4673c1a0 | 341 | [(set (reg 33) |
2e5d1042 | 342 | (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q") 0) |
c6821d1c | 343 | (match_operand:SI 1 "immediate_operand" "n")) |
344 | (match_operand:SI 2 "immediate_operand" "n")))] | |
345 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) | |
346 | && s390_single_qi (operands[1], HImode, 0) >= 0" | |
347 | "* | |
348 | { | |
349 | int part = s390_single_qi (operands[1], HImode, 0); | |
350 | operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part)); | |
4673c1a0 | 351 | |
c6821d1c | 352 | operands[0] = gen_rtx_MEM (QImode, |
353 | plus_constant (XEXP (operands[0], 0), part)); | |
354 | return \"tm\\t%0,%b1\"; | |
355 | }" | |
356 | [(set_attr "op_type" "SI") | |
369293ed | 357 | (set_attr "atype" "mem")]) |
4673c1a0 | 358 | |
c6821d1c | 359 | (define_insn "*tmqi_mem" |
4673c1a0 | 360 | [(set (reg 33) |
2e5d1042 | 361 | (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q") 0) |
c6821d1c | 362 | (match_operand:SI 1 "immediate_operand" "n")) |
363 | (match_operand:SI 2 "immediate_operand" "n")))] | |
364 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" | |
365 | "tm\\t%0,%b1" | |
366 | [(set_attr "op_type" "SI") | |
369293ed | 367 | (set_attr "atype" "mem")]) |
4673c1a0 | 368 | |
2e5d1042 | 369 | (define_insn "*tmdi_reg" |
370 | [(set (reg 33) | |
371 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d") | |
372 | (match_operand:DI 1 "immediate_operand" "n")) | |
373 | (match_operand:DI 2 "immediate_operand" "n")))] | |
374 | "TARGET_64BIT | |
375 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
376 | && s390_single_hi (operands[1], DImode, 0) >= 0" | |
377 | "* | |
378 | { | |
379 | int part = s390_single_hi (operands[1], DImode, 0); | |
380 | operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); | |
381 | ||
382 | switch (part) | |
383 | { | |
384 | case 0: return \"tmhh\\t%0,%x1\"; | |
385 | case 1: return \"tmhl\\t%0,%x1\"; | |
386 | case 2: return \"tmlh\\t%0,%x1\"; | |
387 | case 3: return \"tmll\\t%0,%x1\"; | |
388 | default: abort (); | |
389 | } | |
390 | }" | |
391 | [(set_attr "op_type" "RI")]) | |
392 | ||
393 | (define_insn "*tmsi_reg" | |
394 | [(set (reg 33) | |
395 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d") | |
396 | (match_operand:SI 1 "immediate_operand" "n")) | |
397 | (match_operand:SI 2 "immediate_operand" "n")))] | |
398 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
399 | && s390_single_hi (operands[1], SImode, 0) >= 0" | |
400 | "* | |
401 | { | |
402 | int part = s390_single_hi (operands[1], SImode, 0); | |
403 | operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); | |
404 | ||
405 | switch (part) | |
406 | { | |
407 | case 0: return \"tmh\\t%0,%x1\"; | |
408 | case 1: return \"tml\\t%0,%x1\"; | |
409 | default: abort (); | |
410 | } | |
411 | }" | |
412 | [(set_attr "op_type" "RI")]) | |
413 | ||
c6821d1c | 414 | (define_insn "*tmhi_full" |
4673c1a0 | 415 | [(set (reg 33) |
c6821d1c | 416 | (compare (match_operand:HI 0 "register_operand" "d") |
417 | (match_operand:HI 1 "immediate_operand" "n")))] | |
418 | "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" | |
419 | "tml\\t%0,65535" | |
420 | [(set_attr "op_type" "RX")]) | |
4673c1a0 | 421 | |
c6821d1c | 422 | (define_insn "*tmqi_full" |
4673c1a0 | 423 | [(set (reg 33) |
c6821d1c | 424 | (compare (match_operand:QI 0 "register_operand" "d") |
425 | (match_operand:QI 1 "immediate_operand" "n")))] | |
426 | "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" | |
427 | "tml\\t%0,255" | |
428 | [(set_attr "op_type" "RI")]) | |
4673c1a0 | 429 | |
c6821d1c | 430 | |
431 | ; Load-and-Test instructions | |
432 | ||
433 | (define_insn "*tstdi_sign" | |
4673c1a0 | 434 | [(set (reg 33) |
c6821d1c | 435 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
436 | (const_int 32)) (const_int 32)) | |
437 | (match_operand:DI 1 "const0_operand" ""))) | |
438 | (set (match_operand:DI 2 "register_operand" "=d") | |
439 | (sign_extend:DI (match_dup 0)))] | |
440 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
441 | "ltgfr\\t%2,%0" | |
442 | [(set_attr "op_type" "RRE")]) | |
443 | ||
444 | (define_insn "*tstdi" | |
4673c1a0 | 445 | [(set (reg 33) |
c6821d1c | 446 | (compare (match_operand:DI 0 "register_operand" "d") |
447 | (match_operand:DI 1 "const0_operand" ""))) | |
448 | (set (match_operand:DI 2 "register_operand" "=d") | |
449 | (match_dup 0))] | |
450 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
451 | "ltgr\\t%2,%0" | |
452 | [(set_attr "op_type" "RRE")]) | |
4673c1a0 | 453 | |
c6821d1c | 454 | (define_insn "*tstdi_cconly" |
4673c1a0 | 455 | [(set (reg 33) |
c6821d1c | 456 | (compare (match_operand:DI 0 "register_operand" "d") |
457 | (match_operand:DI 1 "const0_operand" "")))] | |
458 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
459 | "ltgr\\t%0,%0" | |
460 | [(set_attr "op_type" "RRE")]) | |
4673c1a0 | 461 | |
c6821d1c | 462 | (define_insn "*tstdi_cconly_31" |
463 | [(set (reg 33) | |
464 | (compare (match_operand:DI 0 "register_operand" "d") | |
465 | (match_operand:DI 1 "const0_operand" "")))] | |
466 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
467 | "srda\\t%0,0" | |
468 | [(set_attr "op_type" "RS")]) | |
8b4a4127 | 469 | |
c6821d1c | 470 | (define_insn "*tstsi" |
471 | [(set (reg 33) | |
472 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q") | |
473 | (match_operand:SI 1 "const0_operand" ""))) | |
474 | (set (match_operand:SI 2 "register_operand" "=d,d") | |
475 | (match_dup 0))] | |
476 | "s390_match_ccmode(insn, CCSmode)" | |
477 | "@ | |
478 | ltr\\t%2,%0 | |
479 | icm\\t%2,15,%0" | |
480 | [(set_attr "op_type" "RR,RS") | |
481 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 482 | |
c6821d1c | 483 | (define_insn "*tstsi_cconly" |
8b4a4127 | 484 | [(set (reg 33) |
c6821d1c | 485 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q") |
486 | (match_operand:SI 1 "const0_operand" ""))) | |
487 | (clobber (match_scratch:SI 2 "=X,d"))] | |
488 | "s390_match_ccmode(insn, CCSmode)" | |
489 | "@ | |
490 | ltr\\t%0,%0 | |
491 | icm\\t%2,15,%0" | |
492 | [(set_attr "op_type" "RR,RS") | |
493 | (set_attr "atype" "reg,mem")]) | |
8b4a4127 | 494 | |
c6821d1c | 495 | (define_insn "*tstsi_cconly2" |
496 | [(set (reg 33) | |
497 | (compare (match_operand:SI 0 "register_operand" "d") | |
498 | (match_operand:SI 1 "const0_operand" "")))] | |
499 | "s390_match_ccmode(insn, CCSmode)" | |
500 | "ltr\\t%0,%0" | |
501 | [(set_attr "op_type" "RR")]) | |
8b4a4127 | 502 | |
c6821d1c | 503 | (define_insn "*tsthi" |
4673c1a0 | 504 | [(set (reg 33) |
a5004c3d | 505 | (compare (match_operand:HI 0 "s_operand" "Q") |
4673c1a0 | 506 | (match_operand:HI 1 "const0_operand" ""))) |
507 | (set (match_operand:HI 2 "register_operand" "=d") | |
508 | (match_dup 0))] | |
509 | "s390_match_ccmode(insn, CCSmode)" | |
510 | "icm\\t%2,3,%0" | |
511 | [(set_attr "op_type" "RS") | |
369293ed | 512 | (set_attr "atype" "mem")]) |
4673c1a0 | 513 | |
c6821d1c | 514 | (define_insn "*tsthi_cconly" |
4673c1a0 | 515 | [(set (reg 33) |
a5004c3d | 516 | (compare (match_operand:HI 0 "s_operand" "Q") |
4673c1a0 | 517 | (match_operand:HI 1 "const0_operand" ""))) |
518 | (clobber (match_scratch:HI 2 "=d"))] | |
519 | "s390_match_ccmode(insn, CCSmode)" | |
520 | "icm\\t%2,3,%0" | |
521 | [(set_attr "op_type" "RS") | |
369293ed | 522 | (set_attr "atype" "mem")]) |
4673c1a0 | 523 | |
c6821d1c | 524 | (define_insn "*tstqi" |
4673c1a0 | 525 | [(set (reg 33) |
a5004c3d | 526 | (compare (match_operand:QI 0 "s_operand" "Q") |
c6821d1c | 527 | (match_operand:QI 1 "const0_operand" ""))) |
528 | (set (match_operand:QI 2 "register_operand" "=d") | |
529 | (match_dup 0))] | |
530 | "s390_match_ccmode(insn, CCSmode)" | |
531 | "icm\\t%2,1,%0" | |
4673c1a0 | 532 | [(set_attr "op_type" "RS") |
369293ed | 533 | (set_attr "atype" "mem")]) |
4673c1a0 | 534 | |
c6821d1c | 535 | (define_insn "*tstqi_cconly" |
4673c1a0 | 536 | [(set (reg 33) |
a5004c3d | 537 | (compare (match_operand:QI 0 "s_operand" "Q") |
c6821d1c | 538 | (match_operand:QI 1 "const0_operand" ""))) |
539 | (clobber (match_scratch:QI 2 "=d"))] | |
540 | "s390_match_ccmode(insn, CCSmode)" | |
541 | "icm\\t%2,1,%0" | |
542 | [(set_attr "op_type" "RS") | |
369293ed | 543 | (set_attr "atype" "mem")]) |
4673c1a0 | 544 | |
545 | ||
c6821d1c | 546 | ; Compare (signed) instructions |
8b4a4127 | 547 | |
c6821d1c | 548 | (define_insn "*cmpdi_ccs_sign" |
8b4a4127 | 549 | [(set (reg 33) |
c6821d1c | 550 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
551 | (match_operand:DI 0 "register_operand" "d,d")))] | |
552 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
8b4a4127 | 553 | "@ |
c6821d1c | 554 | cgfr\\t%0,%1 |
555 | cgf\\t%0,%1" | |
556 | [(set_attr "op_type" "RRE,RXE") | |
8b4a4127 | 557 | (set_attr "atype" "reg,mem")]) |
558 | ||
c6821d1c | 559 | (define_insn "*cmpdi_ccs" |
8b4a4127 | 560 | [(set (reg 33) |
c6821d1c | 561 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
562 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
563 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
564 | "@ | |
565 | cgr\\t%0,%1 | |
566 | cghi\\t%0,%c1 | |
567 | cg\\t%0,%1" | |
568 | [(set_attr "op_type" "RRE,RI,RXE") | |
569 | (set_attr "atype" "reg,reg,mem")]) | |
570 | ||
571 | (define_insn "*cmpsi_ccs_sign" | |
572 | [(set (reg 33) | |
573 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")) | |
574 | (match_operand:SI 0 "register_operand" "d")))] | |
575 | "s390_match_ccmode(insn, CCSRmode)" | |
576 | "ch\\t%0,%1" | |
577 | [(set_attr "op_type" "RX") | |
8b4a4127 | 578 | (set_attr "atype" "mem")]) |
579 | ||
c6821d1c | 580 | (define_insn "*cmpsi_ccs" |
4673c1a0 | 581 | [(set (reg 33) |
c6821d1c | 582 | (compare (match_operand:SI 0 "register_operand" "d,d,d") |
583 | (match_operand:SI 1 "general_operand" "d,K,m")))] | |
4673c1a0 | 584 | "s390_match_ccmode(insn, CCSmode)" |
c6821d1c | 585 | "@ |
586 | cr\\t%0,%1 | |
587 | chi\\t%0,%c1 | |
588 | c\\t%0,%1" | |
589 | [(set_attr "op_type" "RR,RI,RX") | |
590 | (set_attr "atype" "reg,reg,mem")]) | |
591 | ||
592 | ||
593 | ; Compare (unsigned) instructions | |
4673c1a0 | 594 | |
c6821d1c | 595 | (define_insn "*cmpdi_ccu_zero" |
4673c1a0 | 596 | [(set (reg 33) |
c6821d1c | 597 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
598 | (match_operand:DI 0 "register_operand" "d,d")))] | |
599 | "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT" | |
600 | "@ | |
601 | clgfr\\t%0,%1 | |
602 | clgf\\t%0,%1" | |
603 | [(set_attr "op_type" "RRE,RXE") | |
604 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 605 | |
c6821d1c | 606 | (define_insn "*cmpdi_ccu" |
4673c1a0 | 607 | [(set (reg 33) |
c6821d1c | 608 | (compare (match_operand:DI 0 "register_operand" "d,d") |
609 | (match_operand:DI 1 "general_operand" "d,m")))] | |
610 | "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" | |
611 | "@ | |
612 | clgr\\t%0,%1 | |
613 | clg\\t%0,%1" | |
614 | [(set_attr "op_type" "RRE,RXE") | |
615 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 616 | |
c6821d1c | 617 | (define_insn "*cmpsi_ccu" |
4673c1a0 | 618 | [(set (reg 33) |
c6821d1c | 619 | (compare (match_operand:SI 0 "register_operand" "d,d") |
620 | (match_operand:SI 1 "general_operand" "d,m")))] | |
621 | "s390_match_ccmode(insn, CCUmode)" | |
622 | "@ | |
623 | clr\\t%0,%1 | |
624 | cl\\t%0,%1" | |
625 | [(set_attr "op_type" "RR,RX") | |
626 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 627 | |
c6821d1c | 628 | (define_insn "*cmphi_ccu" |
4673c1a0 | 629 | [(set (reg 33) |
c6821d1c | 630 | (compare (match_operand:HI 0 "register_operand" "d") |
a5004c3d | 631 | (match_operand:HI 1 "s_imm_operand" "Q")))] |
4673c1a0 | 632 | "s390_match_ccmode(insn, CCUmode)" |
c6821d1c | 633 | "clm\\t%0,3,%1" |
634 | [(set_attr "op_type" "RS") | |
369293ed | 635 | (set_attr "atype" "mem")]) |
4673c1a0 | 636 | |
637 | (define_insn "*cmpqi_ccu" | |
638 | [(set (reg 33) | |
639 | (compare (match_operand:QI 0 "register_operand" "d") | |
a5004c3d | 640 | (match_operand:QI 1 "s_imm_operand" "Q")))] |
4673c1a0 | 641 | "s390_match_ccmode(insn, CCUmode)" |
642 | "clm\\t%0,1,%1" | |
643 | [(set_attr "op_type" "RS") | |
369293ed | 644 | (set_attr "atype" "mem")]) |
4673c1a0 | 645 | |
c6821d1c | 646 | (define_insn "*cli" |
4673c1a0 | 647 | [(set (reg 33) |
e7f0624a | 648 | (compare (match_operand:QI 0 "memory_operand" "Q") |
c6821d1c | 649 | (match_operand:QI 1 "immediate_operand" "n")))] |
650 | "s390_match_ccmode (insn, CCUmode)" | |
651 | "cli\\t%0,%b1" | |
4673c1a0 | 652 | [(set_attr "op_type" "SI") |
369293ed | 653 | (set_attr "atype" "mem")]) |
4673c1a0 | 654 | |
c6821d1c | 655 | (define_insn "*cmpdi_ccu_mem" |
656 | [(set (reg 33) | |
a5004c3d | 657 | (compare (match_operand:DI 0 "s_operand" "Q") |
658 | (match_operand:DI 1 "s_imm_operand" "Q")))] | |
c6821d1c | 659 | "s390_match_ccmode(insn, CCUmode)" |
660 | "clc\\t%O0(8,%R0),%1" | |
661 | [(set_attr "op_type" "SS") | |
662 | (set_attr "atype" "mem")]) | |
663 | ||
664 | (define_insn "*cmpsi_ccu_mem" | |
665 | [(set (reg 33) | |
a5004c3d | 666 | (compare (match_operand:SI 0 "s_operand" "Q") |
667 | (match_operand:SI 1 "s_imm_operand" "Q")))] | |
c6821d1c | 668 | "s390_match_ccmode(insn, CCUmode)" |
669 | "clc\\t%O0(4,%R0),%1" | |
670 | [(set_attr "op_type" "SS") | |
671 | (set_attr "atype" "mem")]) | |
672 | ||
673 | (define_insn "*cmphi_ccu_mem" | |
674 | [(set (reg 33) | |
a5004c3d | 675 | (compare (match_operand:HI 0 "s_operand" "Q") |
676 | (match_operand:HI 1 "s_imm_operand" "Q")))] | |
c6821d1c | 677 | "s390_match_ccmode(insn, CCUmode)" |
678 | "clc\\t%O0(2,%R0),%1" | |
679 | [(set_attr "op_type" "SS") | |
680 | (set_attr "atype" "mem")]) | |
681 | ||
4673c1a0 | 682 | (define_insn "*cmpqi_ccu_mem" |
683 | [(set (reg 33) | |
a5004c3d | 684 | (compare (match_operand:QI 0 "s_operand" "Q") |
685 | (match_operand:QI 1 "s_imm_operand" "Q")))] | |
4673c1a0 | 686 | "s390_match_ccmode(insn, CCUmode)" |
687 | "clc\\t%O0(1,%R0),%1" | |
688 | [(set_attr "op_type" "SS") | |
369293ed | 689 | (set_attr "atype" "mem")]) |
4673c1a0 | 690 | |
691 | ||
692 | ; DF instructions | |
693 | ||
694 | (define_insn "*cmpdf_ccs_0" | |
695 | [(set (reg 33) | |
696 | (compare (match_operand:DF 0 "register_operand" "f") | |
697 | (match_operand:DF 1 "const0_operand" "")))] | |
698 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
699 | "ltdbr\\t%0,%0" | |
9fa6d5d9 | 700 | [(set_attr "op_type" "RRE")]) |
4673c1a0 | 701 | |
702 | (define_insn "*cmpdf_ccs_0_ibm" | |
703 | [(set (reg 33) | |
704 | (compare (match_operand:DF 0 "register_operand" "f") | |
705 | (match_operand:DF 1 "const0_operand" "")))] | |
706 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
707 | "ltdr\\t%0,%0" | |
369293ed | 708 | [(set_attr "op_type" "RR")]) |
4673c1a0 | 709 | |
710 | (define_insn "*cmpdf_ccs" | |
711 | [(set (reg 33) | |
712 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
8b4a4127 | 713 | (match_operand:DF 1 "general_operand" "f,m")))] |
4673c1a0 | 714 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
715 | "@ | |
716 | cdbr\\t%0,%1 | |
717 | cdb\\t%0,%1" | |
9fa6d5d9 | 718 | [(set_attr "op_type" "RRE,RXE") |
369293ed | 719 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 720 | |
721 | (define_insn "*cmpdf_ccs_ibm" | |
722 | [(set (reg 33) | |
723 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
8b4a4127 | 724 | (match_operand:DF 1 "general_operand" "f,m")))] |
4673c1a0 | 725 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
726 | "@ | |
727 | cdr\\t%0,%1 | |
728 | cd\\t%0,%1" | |
729 | [(set_attr "op_type" "RR,RX") | |
369293ed | 730 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 731 | |
732 | ||
733 | ; SF instructions | |
734 | ||
735 | (define_insn "*cmpsf_ccs_0" | |
736 | [(set (reg 33) | |
737 | (compare (match_operand:SF 0 "register_operand" "f") | |
738 | (match_operand:SF 1 "const0_operand" "")))] | |
739 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
740 | "ltebr\\t%0,%0" | |
9fa6d5d9 | 741 | [(set_attr "op_type" "RRE")]) |
4673c1a0 | 742 | |
743 | (define_insn "*cmpsf_ccs_0_ibm" | |
744 | [(set (reg 33) | |
745 | (compare (match_operand:SF 0 "register_operand" "f") | |
746 | (match_operand:SF 1 "const0_operand" "")))] | |
747 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
748 | "lter\\t%0,%0" | |
369293ed | 749 | [(set_attr "op_type" "RR")]) |
4673c1a0 | 750 | |
751 | (define_insn "*cmpsf_ccs" | |
752 | [(set (reg 33) | |
753 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
8b4a4127 | 754 | (match_operand:SF 1 "general_operand" "f,m")))] |
4673c1a0 | 755 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
756 | "@ | |
757 | cebr\\t%0,%1 | |
758 | ceb\\t%0,%1" | |
9fa6d5d9 | 759 | [(set_attr "op_type" "RRE,RXE") |
369293ed | 760 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 761 | |
762 | (define_insn "*cmpsf_ccs" | |
763 | [(set (reg 33) | |
764 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
8b4a4127 | 765 | (match_operand:SF 1 "general_operand" "f,m")))] |
4673c1a0 | 766 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
767 | "@ | |
768 | cer\\t%0,%1 | |
769 | ce\\t%0,%1" | |
770 | [(set_attr "op_type" "RR,RX") | |
369293ed | 771 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 772 | |
773 | ||
774 | ;; | |
775 | ;;- Move instructions. | |
776 | ;; | |
777 | ||
778 | ; | |
779 | ; movti instruction pattern(s). | |
780 | ; | |
781 | ||
782 | (define_insn "movti" | |
957d1b91 | 783 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m,Q") |
784 | (match_operand:TI 1 "general_operand" "Q,d,dKm,d,Q"))] | |
4673c1a0 | 785 | "TARGET_64BIT" |
8b4a4127 | 786 | "@ |
787 | lmg\\t%0,%N0,%1 | |
788 | stmg\\t%1,%N1,%0 | |
789 | # | |
957d1b91 | 790 | # |
791 | mvc\\t%O0(16,%R0),%1" | |
792 | [(set_attr "op_type" "RSE,RSE,NN,NN,SS") | |
8b4a4127 | 793 | (set_attr "atype" "mem")]) |
794 | ||
795 | (define_split | |
796 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
797 | (match_operand:TI 1 "general_operand" ""))] | |
798 | "TARGET_64BIT && reload_completed | |
799 | && !s_operand (operands[0], VOIDmode) | |
800 | && !s_operand (operands[1], VOIDmode) | |
801 | && (register_operand (operands[0], VOIDmode) | |
802 | || register_operand (operands[1], VOIDmode)) | |
803 | && (!register_operand (operands[0], VOIDmode) | |
804 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode), | |
805 | operands[1]) | |
806 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode), | |
807 | operands[1]))" | |
808 | [(set (match_dup 2) (match_dup 4)) | |
809 | (set (match_dup 3) (match_dup 5))] | |
810 | " | |
4673c1a0 | 811 | { |
8b4a4127 | 812 | if (!register_operand (operands[0], VOIDmode) |
813 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode), | |
814 | operands[1])) | |
4673c1a0 | 815 | { |
8b4a4127 | 816 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
817 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
818 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
819 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
4673c1a0 | 820 | } |
8b4a4127 | 821 | else |
822 | { | |
823 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
824 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
825 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
826 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
827 | } | |
828 | }") | |
829 | ||
830 | (define_split | |
831 | [(set (match_operand:TI 0 "register_operand" "") | |
832 | (match_operand:TI 1 "memory_operand" ""))] | |
833 | "TARGET_64BIT && reload_completed | |
834 | && !s_operand (operands[1], VOIDmode)" | |
4fbc4db5 | 835 | [(set (match_dup 0) (match_dup 1))] |
836 | " | |
837 | { | |
838 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
839 | s390_load_address (addr, XEXP (operands[1], 0)); | |
840 | operands[1] = replace_equiv_address (operands[1], addr); | |
841 | }") | |
4673c1a0 | 842 | |
843 | ; | |
844 | ; movdi instruction pattern(s). | |
845 | ; | |
846 | ||
847 | ;; If generating PIC code and operands[1] is a symbolic CONST, emit a | |
848 | ;; move to get the address of the symbolic object from the GOT. | |
849 | ||
850 | (define_expand "movdi" | |
851 | [(set (match_operand:DI 0 "general_operand" "") | |
852 | (match_operand:DI 1 "general_operand" ""))] | |
853 | "" | |
854 | " | |
855 | { | |
8b4a4127 | 856 | /* Handle PIC symbolic constants. */ |
4673c1a0 | 857 | if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1])) |
858 | emit_pic_move (operands, DImode); | |
8b4a4127 | 859 | |
860 | /* During and after reload, we need to force constants | |
861 | to the literal pool ourselves, if necessary. */ | |
862 | if ((reload_in_progress || reload_completed) | |
863 | && CONSTANT_P (operands[1]) | |
864 | && (!legitimate_reload_constant_p (operands[1]) | |
25da9e9f | 865 | || FP_REG_P (operands[0]))) |
8b4a4127 | 866 | operands[1] = force_const_mem (DImode, operands[1]); |
4673c1a0 | 867 | }") |
868 | ||
8b4a4127 | 869 | (define_insn "*movdi_lhi" |
870 | [(set (match_operand:DI 0 "register_operand" "=d") | |
871 | (match_operand:DI 1 "immediate_operand" "K"))] | |
872 | "TARGET_64BIT | |
873 | && GET_CODE (operands[1]) == CONST_INT | |
874 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') | |
25da9e9f | 875 | && !FP_REG_P (operands[0])" |
8b4a4127 | 876 | "lghi\\t%0,%h1" |
877 | [(set_attr "op_type" "RI") | |
878 | (set_attr "atype" "reg")]) | |
879 | ||
880 | (define_insn "*movdi_lli" | |
881 | [(set (match_operand:DI 0 "register_operand" "=d") | |
882 | (match_operand:DI 1 "immediate_operand" "n"))] | |
883 | "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0 | |
25da9e9f | 884 | && !FP_REG_P (operands[0])" |
8b4a4127 | 885 | "* |
886 | { | |
887 | int part = s390_single_hi (operands[1], DImode, 0); | |
888 | operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); | |
889 | ||
890 | switch (part) | |
891 | { | |
892 | case 0: return \"llihh\\t%0,%x1\"; | |
893 | case 1: return \"llihl\\t%0,%x1\"; | |
894 | case 2: return \"llilh\\t%0,%x1\"; | |
895 | case 3: return \"llill\\t%0,%x1\"; | |
896 | default: abort (); | |
897 | } | |
898 | }" | |
899 | [(set_attr "op_type" "RI") | |
900 | (set_attr "atype" "reg")]) | |
901 | ||
902 | (define_insn "*movdi_larl" | |
903 | [(set (match_operand:DI 0 "register_operand" "=d") | |
904 | (match_operand:DI 1 "larl_operand" "X"))] | |
905 | "TARGET_64BIT | |
25da9e9f | 906 | && !FP_REG_P (operands[0])" |
8b4a4127 | 907 | "larl\\t%0,%1" |
908 | [(set_attr "op_type" "RIL") | |
909 | (set_attr "atype" "reg") | |
910 | (set_attr "type" "la")]) | |
911 | ||
4673c1a0 | 912 | (define_insn "*movdi_64" |
957d1b91 | 913 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q") |
914 | (match_operand:DI 1 "general_operand" "d,m,d,*f,m,*f,Q"))] | |
4673c1a0 | 915 | "TARGET_64BIT" |
916 | "@ | |
917 | lgr\\t%0,%1 | |
4673c1a0 | 918 | lg\\t%0,%1 |
919 | stg\\t%1,%0 | |
8b4a4127 | 920 | ldr\\t%0,%1 |
921 | ld\\t%0,%1 | |
957d1b91 | 922 | std\\t%1,%0 |
923 | mvc\\t%O0(8,%R0),%1" | |
c36e6d0b | 924 | [(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS") |
957d1b91 | 925 | (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) |
4673c1a0 | 926 | |
927 | (define_insn "*movdi_31" | |
957d1b91 | 928 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q") |
929 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,m,*f,Q"))] | |
4673c1a0 | 930 | "!TARGET_64BIT" |
8b4a4127 | 931 | "@ |
932 | lm\\t%0,%N0,%1 | |
933 | stm\\t%1,%N1,%0 | |
934 | # | |
935 | # | |
936 | ldr\\t%0,%1 | |
937 | ld\\t%0,%1 | |
957d1b91 | 938 | std\\t%1,%0 |
939 | mvc\\t%O0(8,%R0),%1" | |
940 | [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS") | |
941 | (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")]) | |
8b4a4127 | 942 | |
943 | (define_split | |
944 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
945 | (match_operand:DI 1 "general_operand" ""))] | |
946 | "!TARGET_64BIT && reload_completed | |
25da9e9f | 947 | && !FP_REG_P (operands[0]) |
948 | && !FP_REG_P (operands[1]) | |
8b4a4127 | 949 | && !s_operand (operands[0], VOIDmode) |
950 | && !s_operand (operands[1], VOIDmode) | |
951 | && (register_operand (operands[0], VOIDmode) | |
952 | || register_operand (operands[1], VOIDmode)) | |
953 | && (!register_operand (operands[0], VOIDmode) | |
954 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode), | |
955 | operands[1]) | |
956 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode), | |
957 | operands[1]))" | |
958 | [(set (match_dup 2) (match_dup 4)) | |
959 | (set (match_dup 3) (match_dup 5))] | |
960 | " | |
4673c1a0 | 961 | { |
8b4a4127 | 962 | if (!register_operand (operands[0], VOIDmode) |
963 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode), | |
964 | operands[1])) | |
4673c1a0 | 965 | { |
8b4a4127 | 966 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
967 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
968 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
969 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
970 | } | |
971 | else | |
972 | { | |
973 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
974 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
975 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
976 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
977 | } | |
978 | }") | |
4673c1a0 | 979 | |
8b4a4127 | 980 | (define_split |
981 | [(set (match_operand:DI 0 "register_operand" "") | |
982 | (match_operand:DI 1 "memory_operand" ""))] | |
983 | "!TARGET_64BIT && reload_completed | |
25da9e9f | 984 | && !FP_REG_P (operands[0]) |
985 | && !FP_REG_P (operands[1]) | |
8b4a4127 | 986 | && !s_operand (operands[1], VOIDmode)" |
4fbc4db5 | 987 | [(set (match_dup 0) (match_dup 1))] |
988 | " | |
989 | { | |
990 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
991 | s390_load_address (addr, XEXP (operands[1], 0)); | |
992 | operands[1] = replace_equiv_address (operands[1], addr); | |
993 | }") | |
4673c1a0 | 994 | |
fb829af4 | 995 | (define_peephole2 |
996 | [(set (match_operand:DI 0 "register_operand" "") | |
997 | (mem:DI (match_operand 1 "address_operand" "")))] | |
998 | "TARGET_64BIT | |
999 | && !FP_REG_P (operands[0]) | |
1000 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1001 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1002 | && get_pool_mode (operands[1]) == DImode | |
1003 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1004 | [(set (match_dup 0) (match_dup 2))] | |
1005 | "operands[2] = get_pool_constant (operands[1]);") | |
1006 | ||
4673c1a0 | 1007 | ; |
1008 | ; movsi instruction pattern(s). | |
1009 | ; | |
1010 | ||
1011 | ;; If generating PIC code and operands[1] is a symbolic CONST, emit a | |
1012 | ;; move to get the address of the symbolic object from the GOT. | |
1013 | ||
1014 | (define_expand "movsi" | |
1015 | [(set (match_operand:SI 0 "general_operand" "") | |
1016 | (match_operand:SI 1 "general_operand" ""))] | |
1017 | "" | |
1018 | " | |
1019 | { | |
8b4a4127 | 1020 | /* Handle PIC symbolic constants. */ |
1021 | if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1])) | |
4673c1a0 | 1022 | emit_pic_move (operands, SImode); |
2eb8fe23 | 1023 | |
1024 | /* expr.c tries to load an effective address using | |
1025 | force_reg. This fails because we don't have a | |
1026 | generic load_address pattern. Convert the move | |
1027 | to a proper arithmetic operation instead, unless | |
1028 | it is guaranteed to be OK. */ | |
1029 | if (GET_CODE (operands[1]) == PLUS | |
1030 | && !legitimate_la_operand_p (operands[1])) | |
1031 | { | |
1032 | operands[1] = force_operand (operands[1], operands[0]); | |
1033 | if (operands[1] == operands[0]) | |
1034 | DONE; | |
1035 | } | |
8b4a4127 | 1036 | |
1037 | /* During and after reload, we need to force constants | |
1038 | to the literal pool ourselves, if necessary. */ | |
1039 | if ((reload_in_progress || reload_completed) | |
1040 | && CONSTANT_P (operands[1]) | |
1041 | && (!legitimate_reload_constant_p (operands[1]) | |
25da9e9f | 1042 | || FP_REG_P (operands[0]))) |
8b4a4127 | 1043 | operands[1] = force_const_mem (SImode, operands[1]); |
4673c1a0 | 1044 | }") |
1045 | ||
8b4a4127 | 1046 | (define_insn "*movsi_lhi" |
1047 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1048 | (match_operand:SI 1 "immediate_operand" "K"))] | |
1049 | "GET_CODE (operands[1]) == CONST_INT | |
1050 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') | |
25da9e9f | 1051 | && !FP_REG_P (operands[0])" |
8b4a4127 | 1052 | "lhi\\t%0,%h1" |
1053 | [(set_attr "op_type" "RI")]) | |
1054 | ||
1055 | (define_insn "*movsi_lli" | |
1056 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1057 | (match_operand:SI 1 "immediate_operand" "n"))] | |
1058 | "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0 | |
25da9e9f | 1059 | && !FP_REG_P (operands[0])" |
8b4a4127 | 1060 | "* |
1061 | { | |
1062 | int part = s390_single_hi (operands[1], SImode, 0); | |
1063 | operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); | |
1064 | ||
1065 | switch (part) | |
1066 | { | |
1067 | case 0: return \"llilh\\t%0,%x1\"; | |
1068 | case 1: return \"llill\\t%0,%x1\"; | |
1069 | default: abort (); | |
1070 | } | |
1071 | }" | |
1072 | [(set_attr "op_type" "RI")]) | |
1073 | ||
4673c1a0 | 1074 | (define_insn "*movsi" |
957d1b91 | 1075 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q") |
1076 | (match_operand:SI 1 "general_operand" "d,m,d,*f,m,*f,Q"))] | |
4673c1a0 | 1077 | "" |
1078 | "@ | |
1079 | lr\\t%0,%1 | |
4673c1a0 | 1080 | l\\t%0,%1 |
1081 | st\\t%1,%0 | |
8b4a4127 | 1082 | ler\\t%0,%1 |
1083 | le\\t%0,%1 | |
957d1b91 | 1084 | ste\\t%1,%0 |
1085 | mvc\\t%O0(4,%R0),%1" | |
1086 | [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS") | |
1087 | (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) | |
4673c1a0 | 1088 | |
fb829af4 | 1089 | (define_peephole2 |
1090 | [(set (match_operand:SI 0 "register_operand" "") | |
1091 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1092 | "!FP_REG_P (operands[0]) | |
1093 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1094 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1095 | && get_pool_mode (operands[1]) == SImode | |
1096 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1097 | [(set (match_dup 0) (match_dup 2))] | |
1098 | "operands[2] = get_pool_constant (operands[1]);") | |
4673c1a0 | 1099 | |
1100 | ; | |
1101 | ; movhi instruction pattern(s). | |
1102 | ; | |
1103 | ||
1104 | (define_insn "movhi" | |
957d1b91 | 1105 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,Q") |
1106 | (match_operand:HI 1 "general_operand" "d,n,m,d,Q"))] | |
4673c1a0 | 1107 | "" |
1108 | "@ | |
1109 | lr\\t%0,%1 | |
1110 | lhi\\t%0,%h1 | |
1111 | lh\\t%0,%1 | |
957d1b91 | 1112 | sth\\t%1,%0 |
1113 | mvc\\t%O0(2,%R0),%1" | |
1114 | [(set_attr "op_type" "RR,RI,RX,RX,SS") | |
1115 | (set_attr "atype" "reg,reg,mem,mem,mem")]) | |
4673c1a0 | 1116 | |
fb829af4 | 1117 | (define_peephole2 |
1118 | [(set (match_operand:HI 0 "register_operand" "") | |
1119 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1120 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1121 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1122 | && get_pool_mode (operands[1]) == HImode | |
1123 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1124 | [(set (match_dup 0) (match_dup 2))] | |
1125 | "operands[2] = get_pool_constant (operands[1]);") | |
8b4a4127 | 1126 | |
4673c1a0 | 1127 | ; |
1128 | ; movqi instruction pattern(s). | |
1129 | ; | |
1130 | ||
1131 | (define_insn "movqi_64" | |
957d1b91 | 1132 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q") |
1133 | (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))] | |
4673c1a0 | 1134 | "TARGET_64BIT" |
1135 | "@ | |
1136 | lr\\t%0,%1 | |
8b4a4127 | 1137 | lhi\\t%0,%b1 |
4673c1a0 | 1138 | llgc\\t%0,%1 |
1139 | stc\\t%1,%0 | |
957d1b91 | 1140 | mvi\\t%0,%b1 |
1141 | mvc\\t%O0(1,%R0),%1" | |
1142 | [(set_attr "op_type" "RR,RI,RXE,RX,SI,SS") | |
1143 | (set_attr "atype" "reg,reg,mem,mem,mem,mem")]) | |
4673c1a0 | 1144 | |
8b4a4127 | 1145 | |
4673c1a0 | 1146 | (define_insn "movqi" |
957d1b91 | 1147 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q") |
1148 | (match_operand:QI 1 "general_operand" "d,n,m,d,n,Q"))] | |
4673c1a0 | 1149 | "" |
1150 | "@ | |
1151 | lr\\t%0,%1 | |
8b4a4127 | 1152 | lhi\\t%0,%b1 |
4673c1a0 | 1153 | ic\\t%0,%1 |
1154 | stc\\t%1,%0 | |
957d1b91 | 1155 | mvi\\t%0,%b1 |
1156 | mvc\\t%O0(1,%R0),%1" | |
1157 | [(set_attr "op_type" "RR,RI,RX,RX,SI,SS") | |
1158 | (set_attr "atype" "reg,reg,mem,mem,mem,mem")]) | |
4673c1a0 | 1159 | |
fb829af4 | 1160 | (define_peephole2 |
1161 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1162 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1163 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1164 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1165 | && get_pool_mode (operands[1]) == QImode | |
1166 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1167 | [(set (match_dup 0) (match_dup 2))] | |
1168 | "operands[2] = get_pool_constant (operands[1]);") | |
8b4a4127 | 1169 | |
4673c1a0 | 1170 | ; |
2e5d1042 | 1171 | ; movstrictqi instruction pattern(s). |
4673c1a0 | 1172 | ; |
1173 | ||
1174 | (define_insn "*movstrictqi" | |
8b4a4127 | 1175 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) |
1176 | (match_operand:QI 1 "memory_operand" "m"))] | |
4673c1a0 | 1177 | "" |
8b4a4127 | 1178 | "ic\\t%0,%1" |
1179 | [(set_attr "op_type" "RX") | |
1180 | (set_attr "atype" "mem")]) | |
4673c1a0 | 1181 | |
1182 | ; | |
1183 | ; movstricthi instruction pattern(s). | |
1184 | ; | |
1185 | ||
1186 | (define_insn "*movstricthi" | |
8b4a4127 | 1187 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) |
a5004c3d | 1188 | (match_operand:HI 1 "s_imm_operand" "Q")) |
4673c1a0 | 1189 | (clobber (reg:CC 33))] |
1190 | "" | |
8b4a4127 | 1191 | "icm\\t%0,3,%1" |
1192 | [(set_attr "op_type" "RS") | |
369293ed | 1193 | (set_attr "atype" "mem")]) |
4673c1a0 | 1194 | |
1195 | ||
1196 | ; | |
1197 | ; movstrictsi instruction pattern(s). | |
1198 | ; | |
1199 | ||
2e5d1042 | 1200 | (define_insn "movstrictsi" |
8b4a4127 | 1201 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d")) |
1202 | (match_operand:SI 1 "general_operand" "d,m"))] | |
4673c1a0 | 1203 | "TARGET_64BIT" |
1204 | "@ | |
1205 | lr\\t%0,%1 | |
8b4a4127 | 1206 | l\\t%0,%1" |
1207 | [(set_attr "op_type" "RR,RS") | |
1208 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 1209 | |
1210 | ||
1211 | ; | |
1212 | ; movdf instruction pattern(s). | |
1213 | ; | |
1214 | ||
1215 | (define_expand "movdf" | |
1216 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1217 | (match_operand:DF 1 "general_operand" ""))] | |
1218 | "" | |
1219 | " | |
1220 | { | |
8b4a4127 | 1221 | /* During and after reload, we need to force constants |
1222 | to the literal pool ourselves, if necessary. */ | |
1223 | if ((reload_in_progress || reload_completed) | |
1224 | && CONSTANT_P (operands[1])) | |
1225 | operands[1] = force_const_mem (DFmode, operands[1]); | |
4673c1a0 | 1226 | }") |
1227 | ||
1228 | (define_insn "*movdf_64" | |
957d1b91 | 1229 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q") |
1230 | (match_operand:DF 1 "general_operand" "f,m,f,d,m,d,Q"))] | |
8b4a4127 | 1231 | "TARGET_64BIT" |
4673c1a0 | 1232 | "@ |
1233 | ldr\\t%0,%1 | |
1234 | ld\\t%0,%1 | |
1235 | std\\t%1,%0 | |
4673c1a0 | 1236 | lgr\\t%0,%1 |
8b4a4127 | 1237 | lg\\t%0,%1 |
957d1b91 | 1238 | stg\\t%1,%0 |
1239 | mvc\\t%O0(8,%R0),%1" | |
c36e6d0b | 1240 | [(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS") |
957d1b91 | 1241 | (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) |
4673c1a0 | 1242 | |
1243 | (define_insn "*movdf_31" | |
957d1b91 | 1244 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q") |
1245 | (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d,Q"))] | |
8b4a4127 | 1246 | "!TARGET_64BIT" |
4673c1a0 | 1247 | "@ |
8b4a4127 | 1248 | ldr\\t%0,%1 |
1249 | ld\\t%0,%1 | |
1250 | std\\t%1,%0 | |
1251 | lm\\t%0,%N0,%1 | |
1252 | stm\\t%1,%N1,%0 | |
1253 | # | |
957d1b91 | 1254 | # |
1255 | mvc\\t%O0(8,%R0),%1" | |
1256 | [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS") | |
1257 | (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")]) | |
8b4a4127 | 1258 | |
1259 | (define_split | |
1260 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1261 | (match_operand:DF 1 "general_operand" ""))] | |
1262 | "!TARGET_64BIT && reload_completed | |
25da9e9f | 1263 | && !FP_REG_P (operands[0]) |
1264 | && !FP_REG_P (operands[1]) | |
8b4a4127 | 1265 | && !s_operand (operands[0], VOIDmode) |
1266 | && !s_operand (operands[1], VOIDmode) | |
1267 | && (register_operand (operands[0], VOIDmode) | |
1268 | || register_operand (operands[1], VOIDmode)) | |
1269 | && (!register_operand (operands[0], VOIDmode) | |
1270 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode), | |
1271 | operands[1]) | |
1272 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode), | |
1273 | operands[1]))" | |
1274 | [(set (match_dup 2) (match_dup 4)) | |
1275 | (set (match_dup 3) (match_dup 5))] | |
1276 | " | |
4673c1a0 | 1277 | { |
8b4a4127 | 1278 | if (!register_operand (operands[0], VOIDmode) |
1279 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode), | |
1280 | operands[1])) | |
4673c1a0 | 1281 | { |
8b4a4127 | 1282 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1283 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1284 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1285 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
4673c1a0 | 1286 | } |
8b4a4127 | 1287 | else |
1288 | { | |
1289 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1290 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1291 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1292 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1293 | } | |
1294 | }") | |
4673c1a0 | 1295 | |
8b4a4127 | 1296 | (define_split |
1297 | [(set (match_operand:DF 0 "register_operand" "") | |
1298 | (match_operand:DF 1 "memory_operand" ""))] | |
1299 | "!TARGET_64BIT && reload_completed | |
25da9e9f | 1300 | && !FP_REG_P (operands[0]) |
1301 | && !FP_REG_P (operands[1]) | |
8b4a4127 | 1302 | && !s_operand (operands[1], VOIDmode)" |
4fbc4db5 | 1303 | [(set (match_dup 0) (match_dup 1))] |
1304 | " | |
1305 | { | |
1306 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1307 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1308 | operands[1] = replace_equiv_address (operands[1], addr); | |
1309 | }") | |
4673c1a0 | 1310 | |
1311 | ; | |
1312 | ; movsf instruction pattern(s). | |
1313 | ; | |
1314 | ||
1315 | (define_expand "movsf" | |
1316 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
1317 | (match_operand:SF 1 "general_operand" ""))] | |
1318 | "" | |
1319 | " | |
1320 | { | |
8b4a4127 | 1321 | /* During and after reload, we need to force constants |
1322 | to the literal pool ourselves, if necessary. */ | |
1323 | if ((reload_in_progress || reload_completed) | |
1324 | && CONSTANT_P (operands[1])) | |
1325 | operands[1] = force_const_mem (SFmode, operands[1]); | |
4673c1a0 | 1326 | }") |
1327 | ||
8b4a4127 | 1328 | (define_insn "*movsf" |
957d1b91 | 1329 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m,Q") |
1330 | (match_operand:SF 1 "general_operand" "f,m,f,d,m,d,Q"))] | |
8b4a4127 | 1331 | "" |
4673c1a0 | 1332 | "@ |
1333 | ler\\t%0,%1 | |
1334 | le\\t%0,%1 | |
1335 | ste\\t%1,%0 | |
4673c1a0 | 1336 | lr\\t%0,%1 |
1337 | l\\t%0,%1 | |
957d1b91 | 1338 | st\\t%1,%0 |
1339 | mvc\\t%O0(4,%R0),%1" | |
1340 | [(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS") | |
1341 | (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")]) | |
8b4a4127 | 1342 | |
4673c1a0 | 1343 | ; |
1344 | ; load_multiple pattern(s). | |
1345 | ; | |
1346 | ||
1347 | (define_expand "load_multiple" | |
1348 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1349 | (match_operand 1 "" "")) | |
1350 | (use (match_operand 2 "" ""))])] | |
1351 | "" | |
1352 | " | |
1353 | { | |
1354 | int regno; | |
1355 | int count; | |
1356 | rtx from; | |
8b4a4127 | 1357 | int i, off; |
4673c1a0 | 1358 | |
1359 | /* Support only loading a constant number of fixed-point registers from | |
1360 | memory and only bother with this if more than two */ | |
1361 | if (GET_CODE (operands[2]) != CONST_INT | |
8b4a4127 | 1362 | || INTVAL (operands[2]) < 2 |
4673c1a0 | 1363 | || INTVAL (operands[2]) > 16 |
1364 | || GET_CODE (operands[1]) != MEM | |
1365 | || GET_CODE (operands[0]) != REG | |
1366 | || REGNO (operands[0]) >= 16) | |
1367 | FAIL; | |
1368 | ||
1369 | count = INTVAL (operands[2]); | |
1370 | regno = REGNO (operands[0]); | |
1371 | ||
1372 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
8b4a4127 | 1373 | if (no_new_pseudos) |
1374 | { | |
1375 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1376 | { | |
1377 | from = XEXP (operands[1], 0); | |
1378 | off = 0; | |
1379 | } | |
1380 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1381 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1382 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1383 | { | |
1384 | from = XEXP (XEXP (operands[1], 0), 0); | |
1385 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1386 | } | |
1387 | else | |
1388 | FAIL; | |
1389 | ||
1390 | if (from == frame_pointer_rtx || from == arg_pointer_rtx) | |
1391 | FAIL; | |
1392 | } | |
1393 | else | |
1394 | { | |
1395 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1396 | off = 0; | |
1397 | } | |
4673c1a0 | 1398 | |
1399 | for (i = 0; i < count; i++) | |
1400 | XVECEXP (operands[3], 0, i) | |
1401 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i), | |
1402 | change_address (operands[1], Pmode, | |
8b4a4127 | 1403 | plus_constant (from, |
1404 | off + i * UNITS_PER_WORD))); | |
4673c1a0 | 1405 | }") |
1406 | ||
1407 | (define_insn "*load_multiple_di" | |
1408 | [(match_parallel 0 "load_multiple_operation" | |
1409 | [(set (match_operand:DI 1 "register_operand" "=r") | |
a5004c3d | 1410 | (match_operand:DI 2 "s_operand" "Q"))])] |
4673c1a0 | 1411 | "" |
1412 | "* | |
1413 | { | |
1414 | int words = XVECLEN (operands[0], 0); | |
1415 | ||
1416 | if (XVECLEN (operands[0], 0) == 1) | |
1417 | return \"lg\\t%1,0(%2)\"; | |
1418 | ||
1419 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); | |
1420 | return \"lmg\\t%1,%0,%2\"; | |
1421 | }" | |
1422 | [(set_attr "op_type" "RXE") | |
8b4a4127 | 1423 | (set_attr "atype" "mem") |
1424 | (set_attr "type" "lm")]) | |
4673c1a0 | 1425 | |
1426 | (define_insn "*load_multiple_si" | |
1427 | [(match_parallel 0 "load_multiple_operation" | |
1428 | [(set (match_operand:SI 1 "register_operand" "=r") | |
a5004c3d | 1429 | (match_operand:SI 2 "s_operand" "Q"))])] |
4673c1a0 | 1430 | "" |
1431 | "* | |
1432 | { | |
1433 | int words = XVECLEN (operands[0], 0); | |
1434 | ||
1435 | if (XVECLEN (operands[0], 0) == 1) | |
1436 | return \"l\\t%1,0(%2)\"; | |
1437 | ||
1438 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); | |
1439 | return \"lm\\t%1,%0,%2\"; | |
1440 | }" | |
1441 | [(set_attr "op_type" "RXE") | |
8b4a4127 | 1442 | (set_attr "atype" "mem") |
1443 | (set_attr "type" "lm")]) | |
4673c1a0 | 1444 | |
1445 | ; | |
1446 | ; store multiple pattern(s). | |
1447 | ; | |
1448 | ||
1449 | (define_expand "store_multiple" | |
1450 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1451 | (match_operand 1 "" "")) | |
1452 | (use (match_operand 2 "" ""))])] | |
1453 | "" | |
1454 | " | |
1455 | { | |
1456 | int regno; | |
1457 | int count; | |
1458 | rtx to; | |
8b4a4127 | 1459 | int i, off; |
4673c1a0 | 1460 | |
1461 | /* Support only storing a constant number of fixed-point registers to | |
1462 | memory and only bother with this if more than two. */ | |
1463 | if (GET_CODE (operands[2]) != CONST_INT | |
8b4a4127 | 1464 | || INTVAL (operands[2]) < 2 |
4673c1a0 | 1465 | || INTVAL (operands[2]) > 16 |
1466 | || GET_CODE (operands[0]) != MEM | |
1467 | || GET_CODE (operands[1]) != REG | |
1468 | || REGNO (operands[1]) >= 16) | |
1469 | FAIL; | |
1470 | ||
1471 | count = INTVAL (operands[2]); | |
1472 | regno = REGNO (operands[1]); | |
1473 | ||
1474 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
8b4a4127 | 1475 | |
1476 | if (no_new_pseudos) | |
1477 | { | |
1478 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1479 | { | |
1480 | to = XEXP (operands[0], 0); | |
1481 | off = 0; | |
1482 | } | |
1483 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1484 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1485 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1486 | { | |
1487 | to = XEXP (XEXP (operands[0], 0), 0); | |
1488 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1489 | } | |
1490 | else | |
1491 | FAIL; | |
1492 | ||
1493 | if (to == frame_pointer_rtx || to == arg_pointer_rtx) | |
1494 | FAIL; | |
1495 | } | |
1496 | else | |
1497 | { | |
1498 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1499 | off = 0; | |
1500 | } | |
4673c1a0 | 1501 | |
1502 | for (i = 0; i < count; i++) | |
1503 | XVECEXP (operands[3], 0, i) | |
1504 | = gen_rtx_SET (VOIDmode, | |
1505 | change_address (operands[0], Pmode, | |
8b4a4127 | 1506 | plus_constant (to, |
1507 | off + i * UNITS_PER_WORD)), | |
4673c1a0 | 1508 | gen_rtx_REG (Pmode, regno + i)); |
1509 | }") | |
1510 | ||
1511 | (define_insn "*store_multiple_di" | |
1512 | [(match_parallel 0 "store_multiple_operation" | |
a5004c3d | 1513 | [(set (match_operand:DI 1 "s_operand" "=Q") |
4673c1a0 | 1514 | (match_operand:DI 2 "register_operand" "r"))])] |
1515 | "" | |
1516 | "* | |
1517 | { | |
1518 | int words = XVECLEN (operands[0], 0); | |
1519 | ||
1520 | if (XVECLEN (operands[0], 0) == 1) | |
1521 | return \"stg\\t%1,0(%2)\"; | |
1522 | ||
1523 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); | |
1524 | return \"stmg\\t%2,%0,%1\"; | |
1525 | }" | |
1526 | [(set_attr "op_type" "RXE") | |
1527 | (set_attr "atype" "mem") | |
8b4a4127 | 1528 | (set_attr "type" "stm")]) |
4673c1a0 | 1529 | |
1530 | ||
1531 | (define_insn "*store_multiple_si" | |
1532 | [(match_parallel 0 "store_multiple_operation" | |
a5004c3d | 1533 | [(set (match_operand:SI 1 "s_operand" "=Q") |
4673c1a0 | 1534 | (match_operand:SI 2 "register_operand" "r"))])] |
1535 | "" | |
1536 | "* | |
1537 | { | |
1538 | int words = XVECLEN (operands[0], 0); | |
1539 | ||
1540 | if (XVECLEN (operands[0], 0) == 1) | |
1541 | return \"st\\t%1,0(%2)\"; | |
1542 | ||
1543 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); | |
1544 | return \"stm\\t%2,%0,%1\"; | |
1545 | }" | |
1546 | [(set_attr "op_type" "RXE") | |
1547 | (set_attr "atype" "mem") | |
8b4a4127 | 1548 | (set_attr "type" "stm")]) |
4673c1a0 | 1549 | |
1550 | ;; | |
1551 | ;; String instructions. | |
1552 | ;; | |
1553 | ||
1554 | ; | |
4fbc4db5 | 1555 | ; movstrM instruction pattern(s). |
4673c1a0 | 1556 | ; |
1557 | ||
1558 | (define_expand "movstrdi" | |
4fbc4db5 | 1559 | [(set (match_operand:BLK 0 "memory_operand" "") |
1560 | (match_operand:BLK 1 "memory_operand" "")) | |
1561 | (use (match_operand:DI 2 "general_operand" "")) | |
1562 | (match_operand 3 "" "")] | |
1563 | "TARGET_64BIT" | |
1564 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
4673c1a0 | 1565 | |
1566 | (define_expand "movstrsi" | |
4fbc4db5 | 1567 | [(set (match_operand:BLK 0 "memory_operand" "") |
1568 | (match_operand:BLK 1 "memory_operand" "")) | |
1569 | (use (match_operand:SI 2 "general_operand" "")) | |
1570 | (match_operand 3 "" "")] | |
1571 | "" | |
1572 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
4673c1a0 | 1573 | |
66a63c5b | 1574 | ; Move a block that is up to 256 bytes in length. |
1575 | ; The block length is taken as (operands[2] % 256) + 1. | |
4673c1a0 | 1576 | |
4fbc4db5 | 1577 | (define_insn "movstr_short_64" |
1578 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1579 | (match_operand:BLK 1 "memory_operand" "Q,Q")) | |
66a63c5b | 1580 | (use (match_operand:DI 2 "nonmemory_operand" "n,a")) |
1581 | (clobber (match_scratch:DI 3 "=X,&a"))] | |
1582 | "TARGET_64BIT" | |
1583 | "* | |
1584 | { | |
1585 | switch (which_alternative) | |
1586 | { | |
1587 | case 0: | |
1588 | return \"mvc\\t%O0(%b2+1,%R0),%1\"; | |
1589 | ||
1590 | case 1: | |
1591 | output_asm_insn (\"bras\\t%3,.+10\", operands); | |
1592 | output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands); | |
1593 | return \"ex\\t%2,0(%3)\"; | |
1594 | ||
1595 | default: | |
1596 | abort (); | |
1597 | } | |
1598 | }" | |
1599 | [(set_attr "op_type" "SS,NN") | |
4fbc4db5 | 1600 | (set_attr "type" "cs,cs") |
66a63c5b | 1601 | (set_attr "atype" "mem,mem") |
1602 | (set_attr "length" "*,14")]) | |
1603 | ||
4fbc4db5 | 1604 | (define_insn "movstr_short_31" |
1605 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1606 | (match_operand:BLK 1 "memory_operand" "Q,Q")) | |
66a63c5b | 1607 | (use (match_operand:SI 2 "nonmemory_operand" "n,a")) |
1608 | (clobber (match_scratch:SI 3 "=X,&a"))] | |
1609 | "!TARGET_64BIT" | |
1610 | "* | |
1611 | { | |
1612 | switch (which_alternative) | |
1613 | { | |
1614 | case 0: | |
1615 | return \"mvc\\t%O0(%b2+1,%R0),%1\"; | |
1616 | ||
1617 | case 1: | |
1618 | output_asm_insn (\"bras\\t%3,.+10\", operands); | |
1619 | output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands); | |
1620 | return \"ex\\t%2,0(%3)\"; | |
4673c1a0 | 1621 | |
66a63c5b | 1622 | default: |
1623 | abort (); | |
1624 | } | |
1625 | }" | |
1626 | [(set_attr "op_type" "SS,NN") | |
4fbc4db5 | 1627 | (set_attr "type" "cs,cs") |
66a63c5b | 1628 | (set_attr "atype" "mem,mem") |
1629 | (set_attr "length" "*,14")]) | |
4673c1a0 | 1630 | |
4fbc4db5 | 1631 | ; Move a block of arbitrary length. |
4673c1a0 | 1632 | |
4fbc4db5 | 1633 | (define_insn "movstr_long_64" |
9f4d041d | 1634 | [(set (match_operand:TI 0 "register_operand" "=d") |
1635 | (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0") | |
1636 | (lshiftrt:TI (match_dup 2) (const_int 64))) | |
1637 | (const_int 64))) | |
1638 | (set (match_operand:TI 1 "register_operand" "=d") | |
1639 | (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1") | |
1640 | (lshiftrt:TI (match_dup 3) (const_int 64))) | |
1641 | (const_int 64))) | |
1642 | (set (mem:BLK (subreg:DI (match_dup 2) 0)) | |
1643 | (mem:BLK (subreg:DI (match_dup 3) 0))) | |
4673c1a0 | 1644 | (clobber (reg:CC 33))] |
9f4d041d | 1645 | "TARGET_64BIT" |
4673c1a0 | 1646 | "mvcle\\t%0,%1,0\;jo\\t.-4" |
1647 | [(set_attr "op_type" "NN") | |
4fbc4db5 | 1648 | (set_attr "type" "vs") |
4673c1a0 | 1649 | (set_attr "atype" "mem") |
1650 | (set_attr "length" "8")]) | |
1651 | ||
4fbc4db5 | 1652 | (define_insn "movstr_long_31" |
9f4d041d | 1653 | [(set (match_operand:DI 0 "register_operand" "=d") |
1654 | (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0") | |
1655 | (lshiftrt:DI (match_dup 2) (const_int 32))) | |
1656 | (const_int 32))) | |
1657 | (set (match_operand:DI 1 "register_operand" "=d") | |
1658 | (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1") | |
1659 | (lshiftrt:DI (match_dup 3) (const_int 32))) | |
1660 | (const_int 32))) | |
1661 | (set (mem:BLK (subreg:SI (match_dup 2) 0)) | |
1662 | (mem:BLK (subreg:SI (match_dup 3) 0))) | |
4673c1a0 | 1663 | (clobber (reg:CC 33))] |
9f4d041d | 1664 | "!TARGET_64BIT" |
4673c1a0 | 1665 | "mvcle\\t%0,%1,0\;jo\\t.-4" |
4fbc4db5 | 1666 | [(set_attr "op_type" "NN") |
1667 | (set_attr "type" "vs") | |
1668 | (set_attr "atype" "mem") | |
1669 | (set_attr "length" "8")]) | |
4673c1a0 | 1670 | |
1671 | ; | |
4fbc4db5 | 1672 | ; clrstrM instruction pattern(s). |
4673c1a0 | 1673 | ; |
1674 | ||
1675 | (define_expand "clrstrdi" | |
4fbc4db5 | 1676 | [(set (match_operand:BLK 0 "memory_operand" "") |
4673c1a0 | 1677 | (const_int 0)) |
1678 | (use (match_operand:DI 1 "general_operand" "")) | |
1679 | (match_operand 2 "" "")] | |
1680 | "TARGET_64BIT" | |
4fbc4db5 | 1681 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") |
4673c1a0 | 1682 | |
1683 | (define_expand "clrstrsi" | |
4fbc4db5 | 1684 | [(set (match_operand:BLK 0 "memory_operand" "") |
4673c1a0 | 1685 | (const_int 0)) |
1686 | (use (match_operand:SI 1 "general_operand" "")) | |
1687 | (match_operand 2 "" "")] | |
4fbc4db5 | 1688 | "" |
1689 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") | |
4673c1a0 | 1690 | |
4fbc4db5 | 1691 | ; Clear a block that is up to 256 bytes in length. |
1692 | ; The block length is taken as (operands[2] % 256) + 1. | |
4673c1a0 | 1693 | |
4fbc4db5 | 1694 | (define_insn "clrstr_short_64" |
1695 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1696 | (const_int 0)) | |
1697 | (use (match_operand:DI 1 "nonmemory_operand" "n,a")) | |
1698 | (clobber (match_scratch:DI 2 "=X,&a")) | |
1699 | (clobber (reg:CC 33))] | |
1700 | "TARGET_64BIT" | |
1701 | "* | |
1702 | { | |
1703 | switch (which_alternative) | |
1704 | { | |
1705 | case 0: | |
1706 | return \"xc\\t%O0(%b1+1,%R0),%0\"; | |
4673c1a0 | 1707 | |
4fbc4db5 | 1708 | case 1: |
1709 | output_asm_insn (\"bras\\t%2,.+10\", operands); | |
1710 | output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands); | |
1711 | return \"ex\\t%1,0(%2)\"; | |
4673c1a0 | 1712 | |
4fbc4db5 | 1713 | default: |
1714 | abort (); | |
1715 | } | |
1716 | }" | |
1717 | [(set_attr "op_type" "SS,NN") | |
1718 | (set_attr "type" "cs,cs") | |
1719 | (set_attr "atype" "mem,mem") | |
1720 | (set_attr "length" "*,14")]) | |
4673c1a0 | 1721 | |
4fbc4db5 | 1722 | (define_insn "clrstr_short_31" |
1723 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
4673c1a0 | 1724 | (const_int 0)) |
4fbc4db5 | 1725 | (use (match_operand:SI 1 "nonmemory_operand" "n,a")) |
1726 | (clobber (match_scratch:SI 2 "=X,&a")) | |
4673c1a0 | 1727 | (clobber (reg:CC 33))] |
4fbc4db5 | 1728 | "!TARGET_64BIT" |
1729 | "* | |
1730 | { | |
1731 | switch (which_alternative) | |
1732 | { | |
1733 | case 0: | |
1734 | return \"xc\\t%O0(%b1+1,%R0),%0\"; | |
4673c1a0 | 1735 | |
4fbc4db5 | 1736 | case 1: |
1737 | output_asm_insn (\"bras\\t%2,.+10\", operands); | |
1738 | output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands); | |
1739 | return \"ex\\t%1,0(%2)\"; | |
4673c1a0 | 1740 | |
4fbc4db5 | 1741 | default: |
1742 | abort (); | |
1743 | } | |
1744 | }" | |
1745 | [(set_attr "op_type" "SS,NN") | |
1746 | (set_attr "type" "cs,cs") | |
1747 | (set_attr "atype" "mem,mem") | |
1748 | (set_attr "length" "*,14")]) | |
1749 | ||
1750 | ; Clear a block of arbitrary length. | |
1751 | ||
1752 | (define_insn "clrstr_long_64" | |
9f4d041d | 1753 | [(set (match_operand:TI 0 "register_operand" "=d") |
1754 | (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0") | |
1755 | (lshiftrt:TI (match_dup 2) (const_int 64))) | |
1756 | (const_int 64))) | |
1757 | (set (mem:BLK (subreg:DI (match_dup 2) 0)) | |
4673c1a0 | 1758 | (const_int 0)) |
9f4d041d | 1759 | (use (match_operand:TI 1 "register_operand" "d")) |
4673c1a0 | 1760 | (clobber (reg:CC 33))] |
1761 | "TARGET_64BIT" | |
1762 | "mvcle\\t%0,%1,0\;jo\\t.-4" | |
1763 | [(set_attr "op_type" "NN") | |
1764 | (set_attr "atype" "mem") | |
8b4a4127 | 1765 | (set_attr "type" "vs") |
4673c1a0 | 1766 | (set_attr "length" "8")]) |
1767 | ||
4fbc4db5 | 1768 | (define_insn "clrstr_long_31" |
9f4d041d | 1769 | [(set (match_operand:DI 0 "register_operand" "=d") |
1770 | (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0") | |
1771 | (lshiftrt:DI (match_dup 2) (const_int 32))) | |
1772 | (const_int 32))) | |
1773 | (set (mem:BLK (subreg:SI (match_dup 2) 0)) | |
4673c1a0 | 1774 | (const_int 0)) |
9f4d041d | 1775 | (use (match_operand:DI 1 "register_operand" "d")) |
4673c1a0 | 1776 | (clobber (reg:CC 33))] |
1777 | "!TARGET_64BIT" | |
1778 | "mvcle\\t%0,%1,0\;jo\\t.-4" | |
1779 | [(set_attr "op_type" "NN") | |
1780 | (set_attr "atype" "mem") | |
8b4a4127 | 1781 | (set_attr "type" "vs") |
4673c1a0 | 1782 | (set_attr "length" "8")]) |
1783 | ||
1784 | ; | |
4fbc4db5 | 1785 | ; cmpstrM instruction pattern(s). |
4673c1a0 | 1786 | ; |
1787 | ||
1788 | (define_expand "cmpstrdi" | |
4fbc4db5 | 1789 | [(set (match_operand:DI 0 "register_operand" "") |
1790 | (compare:DI (match_operand:BLK 1 "memory_operand" "") | |
1791 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
1792 | (use (match_operand:DI 3 "general_operand" "")) | |
1793 | (use (match_operand:DI 4 "" ""))] | |
1794 | "TARGET_64BIT" | |
1795 | "s390_expand_cmpstr (operands[0], operands[1], | |
1796 | operands[2], operands[3]); DONE;") | |
4673c1a0 | 1797 | |
4fbc4db5 | 1798 | (define_expand "cmpstrsi" |
1799 | [(set (match_operand:SI 0 "register_operand" "") | |
1800 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
1801 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
1802 | (use (match_operand:SI 3 "general_operand" "")) | |
1803 | (use (match_operand:SI 4 "" ""))] | |
1804 | "" | |
1805 | "s390_expand_cmpstr (operands[0], operands[1], | |
1806 | operands[2], operands[3]); DONE;") | |
4673c1a0 | 1807 | |
4fbc4db5 | 1808 | ; Compare a block that is up to 256 bytes in length. |
1809 | ; The block length is taken as (operands[2] % 256) + 1. | |
4673c1a0 | 1810 | |
4fbc4db5 | 1811 | (define_insn "cmpstr_short_64" |
1812 | [(set (reg:CCS 33) | |
1813 | (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1814 | (match_operand:BLK 1 "memory_operand" "Q,Q"))) | |
1815 | (use (match_operand:DI 2 "nonmemory_operand" "n,a")) | |
1816 | (clobber (match_scratch:DI 3 "=X,&a"))] | |
1817 | "TARGET_64BIT" | |
1818 | "* | |
1819 | { | |
1820 | switch (which_alternative) | |
4673c1a0 | 1821 | { |
4fbc4db5 | 1822 | case 0: |
1823 | return \"clc\\t%O0(%b2+1,%R0),%1\"; | |
4673c1a0 | 1824 | |
4fbc4db5 | 1825 | case 1: |
1826 | output_asm_insn (\"bras\\t%3,.+10\", operands); | |
1827 | output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands); | |
1828 | return \"ex\\t%2,0(%3)\"; | |
4673c1a0 | 1829 | |
4fbc4db5 | 1830 | default: |
1831 | abort (); | |
4673c1a0 | 1832 | } |
4fbc4db5 | 1833 | }" |
1834 | [(set_attr "op_type" "SS,NN") | |
1835 | (set_attr "type" "cs,cs") | |
1836 | (set_attr "atype" "mem,mem") | |
1837 | (set_attr "length" "*,14")]) | |
4673c1a0 | 1838 | |
4fbc4db5 | 1839 | (define_insn "cmpstr_short_31" |
1840 | [(set (reg:CCS 33) | |
1841 | (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1842 | (match_operand:BLK 1 "memory_operand" "Q,Q"))) | |
1843 | (use (match_operand:SI 2 "nonmemory_operand" "n,a")) | |
1844 | (clobber (match_scratch:SI 3 "=X,&a"))] | |
1845 | "!TARGET_64BIT" | |
1846 | "* | |
4673c1a0 | 1847 | { |
4fbc4db5 | 1848 | switch (which_alternative) |
4673c1a0 | 1849 | { |
4fbc4db5 | 1850 | case 0: |
1851 | return \"clc\\t%O0(%b2+1,%R0),%1\"; | |
4673c1a0 | 1852 | |
4fbc4db5 | 1853 | case 1: |
1854 | output_asm_insn (\"bras\\t%3,.+10\", operands); | |
1855 | output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands); | |
1856 | return \"ex\\t%2,0(%3)\"; | |
4673c1a0 | 1857 | |
4fbc4db5 | 1858 | default: |
1859 | abort (); | |
4673c1a0 | 1860 | } |
4fbc4db5 | 1861 | }" |
1862 | [(set_attr "op_type" "SS,NN") | |
1863 | (set_attr "type" "cs,cs") | |
1864 | (set_attr "atype" "mem,mem") | |
1865 | (set_attr "length" "*,14")]) | |
4673c1a0 | 1866 | |
4fbc4db5 | 1867 | ; Compare a block of arbitrary length. |
4673c1a0 | 1868 | |
4fbc4db5 | 1869 | (define_insn "cmpstr_long_64" |
8b4a4127 | 1870 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
1871 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
1872 | (set (reg:CCS 33) | |
1873 | (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
e3233937 | 1874 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
1875 | (use (match_dup 2)) | |
1876 | (use (match_dup 3))] | |
4673c1a0 | 1877 | "TARGET_64BIT" |
1878 | "clcl\\t%0,%1" | |
1879 | [(set_attr "op_type" "RR") | |
1880 | (set_attr "atype" "mem") | |
8b4a4127 | 1881 | (set_attr "type" "vs")]) |
4673c1a0 | 1882 | |
4fbc4db5 | 1883 | (define_insn "cmpstr_long_31" |
8b4a4127 | 1884 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
1885 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
1886 | (set (reg:CCS 33) | |
1887 | (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
e3233937 | 1888 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
1889 | (use (match_dup 2)) | |
1890 | (use (match_dup 3))] | |
4673c1a0 | 1891 | "!TARGET_64BIT" |
1892 | "clcl\\t%0,%1" | |
1893 | [(set_attr "op_type" "RR") | |
1894 | (set_attr "atype" "mem") | |
8b4a4127 | 1895 | (set_attr "type" "vs")]) |
4673c1a0 | 1896 | |
1897 | ; Convert condition code to integer in range (-1, 0, 1) | |
1898 | ||
1899 | (define_insn "cmpint_si" | |
1900 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2eb8fe23 | 1901 | (compare:SI (reg:CCS 33) (const_int 0)))] |
4673c1a0 | 1902 | "" |
1903 | "* | |
1904 | { | |
1905 | output_asm_insn (\"lhi\\t%0,1\", operands); | |
1906 | output_asm_insn (\"jh\\t.+12\", operands); | |
1907 | output_asm_insn (\"jl\\t.+6\", operands); | |
1908 | output_asm_insn (\"sr\\t%0,%0\", operands); | |
1909 | return \"lcr\\t%0,%0\"; | |
1910 | }" | |
1911 | [(set_attr "op_type" "NN") | |
1912 | (set_attr "length" "16") | |
1913 | (set_attr "atype" "reg") | |
369293ed | 1914 | (set_attr "type" "other")]) |
4673c1a0 | 1915 | |
1916 | (define_insn "cmpint_di" | |
1917 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2eb8fe23 | 1918 | (compare:DI (reg:CCS 33) (const_int 0)))] |
4673c1a0 | 1919 | "TARGET_64BIT" |
1920 | "* | |
1921 | { | |
1922 | output_asm_insn (\"lghi\\t%0,1\", operands); | |
1923 | output_asm_insn (\"jh\\t.+12\", operands); | |
1924 | output_asm_insn (\"jl\\t.+6\", operands); | |
1925 | output_asm_insn (\"sgr\\t%0,%0\", operands); | |
1926 | return \"lcgr\\t%0,%0\"; | |
1927 | }" | |
1928 | [(set_attr "op_type" "NN") | |
1929 | (set_attr "length" "22") | |
1930 | (set_attr "atype" "reg") | |
369293ed | 1931 | (set_attr "type" "other")]) |
4673c1a0 | 1932 | |
8b4a4127 | 1933 | |
4673c1a0 | 1934 | ;; |
1935 | ;;- Conversion instructions. | |
1936 | ;; | |
1937 | ||
8b4a4127 | 1938 | (define_insn "*sethighqisi" |
1939 | [(set (match_operand:SI 0 "register_operand" "=d") | |
a5004c3d | 1940 | (unspec:SI [(match_operand:QI 1 "s_operand" "Q")] 10)) |
8b4a4127 | 1941 | (clobber (reg:CC 33))] |
1942 | "" | |
1943 | "icm\\t%0,8,%1" | |
1944 | [(set_attr "op_type" "RS") | |
1945 | (set_attr "atype" "mem")]) | |
1946 | ||
1947 | (define_insn "*sethighhisi" | |
1948 | [(set (match_operand:SI 0 "register_operand" "=d") | |
a5004c3d | 1949 | (unspec:SI [(match_operand:HI 1 "s_operand" "Q")] 10)) |
8b4a4127 | 1950 | (clobber (reg:CC 33))] |
1951 | "" | |
1952 | "icm\\t%0,12,%1" | |
1953 | [(set_attr "op_type" "RS") | |
1954 | (set_attr "atype" "mem")]) | |
1955 | ||
1956 | (define_insn "*sethighqidi_64" | |
1957 | [(set (match_operand:DI 0 "register_operand" "=d") | |
a5004c3d | 1958 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10)) |
8b4a4127 | 1959 | (clobber (reg:CC 33))] |
1960 | "TARGET_64BIT" | |
1961 | "icmh\\t%0,8,%1" | |
1962 | [(set_attr "op_type" "RSE") | |
1963 | (set_attr "atype" "mem")]) | |
1964 | ||
1965 | (define_insn "*sethighqidi_31" | |
1966 | [(set (match_operand:DI 0 "register_operand" "=d") | |
a5004c3d | 1967 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q")] 10)) |
8b4a4127 | 1968 | (clobber (reg:CC 33))] |
1969 | "!TARGET_64BIT" | |
1970 | "icm\\t%0,8,%1" | |
1971 | [(set_attr "op_type" "RS") | |
1972 | (set_attr "atype" "mem")]) | |
1973 | ||
147b6a2d | 1974 | (define_insn_and_split "*extractqi" |
1975 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1976 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
1977 | (match_operand 2 "const_int_operand" "n") | |
1978 | (const_int 0))) | |
1979 | (clobber (reg:CC 33))] | |
1980 | "!TARGET_64BIT | |
8b4a4127 | 1981 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
147b6a2d | 1982 | "#" |
1983 | "&& reload_completed" | |
8b4a4127 | 1984 | [(parallel |
1985 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) | |
1986 | (clobber (reg:CC 33))]) | |
1987 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
1988 | " | |
1989 | { | |
1990 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
1991 | operands[1] = change_address (operands[1], QImode, 0); | |
147b6a2d | 1992 | }" |
1993 | [(set_attr "type" "o2") | |
1994 | (set_attr "atype" "mem")]) | |
8b4a4127 | 1995 | |
147b6a2d | 1996 | (define_insn_and_split "*extracthi" |
1997 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1998 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
1999 | (match_operand 2 "const_int_operand" "n") | |
2000 | (const_int 0))) | |
2001 | (clobber (reg:CC 33))] | |
2002 | "!TARGET_64BIT | |
8b4a4127 | 2003 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
147b6a2d | 2004 | "#" |
2005 | "&& reload_completed" | |
8b4a4127 | 2006 | [(parallel |
2007 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) | |
2008 | (clobber (reg:CC 33))]) | |
2009 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
2010 | " | |
2011 | { | |
2012 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2013 | operands[1] = change_address (operands[1], HImode, 0); | |
147b6a2d | 2014 | }" |
2015 | [(set_attr "type" "o2") | |
2016 | (set_attr "atype" "mem")]) | |
8b4a4127 | 2017 | |
4673c1a0 | 2018 | ; |
2019 | ; extendsidi2 instruction pattern(s). | |
2020 | ; | |
2021 | ||
8b4a4127 | 2022 | (define_expand "extendsidi2" |
2023 | [(set (match_operand:DI 0 "register_operand" "") | |
2024 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2025 | "" | |
2026 | " | |
2027 | { | |
2028 | if (!TARGET_64BIT) | |
2029 | { | |
9f4d041d | 2030 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2031 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2032 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2033 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
8b4a4127 | 2034 | DONE; |
2035 | } | |
2036 | } | |
2037 | ") | |
2038 | ||
2039 | (define_insn "*extendsidi2" | |
4673c1a0 | 2040 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2041 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2042 | "TARGET_64BIT" | |
2043 | "@ | |
2044 | lgfr\\t%0,%1 | |
2045 | lgf\\t%0,%1" | |
2046 | [(set_attr "op_type" "RRE,RXE") | |
369293ed | 2047 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 2048 | |
4673c1a0 | 2049 | ; |
2050 | ; extendhidi2 instruction pattern(s). | |
2051 | ; | |
2052 | ||
8b4a4127 | 2053 | (define_expand "extendhidi2" |
2054 | [(set (match_operand:DI 0 "register_operand" "") | |
2055 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2056 | "" | |
2057 | " | |
2058 | { | |
2059 | if (!TARGET_64BIT) | |
2060 | { | |
2061 | rtx tmp = gen_reg_rtx (SImode); | |
2062 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
2063 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2064 | DONE; | |
2065 | } | |
2066 | else | |
2067 | { | |
2068 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2069 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
2070 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); | |
2071 | DONE; | |
2072 | } | |
2073 | } | |
2074 | ") | |
2075 | ||
2076 | (define_insn "*extendhidi2" | |
4673c1a0 | 2077 | [(set (match_operand:DI 0 "register_operand" "=d") |
8b4a4127 | 2078 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
4673c1a0 | 2079 | "TARGET_64BIT" |
8b4a4127 | 2080 | "lgh\\t%0,%1" |
2081 | [(set_attr "op_type" "RXE") | |
2082 | (set_attr "atype" "mem")]) | |
4673c1a0 | 2083 | |
2084 | ; | |
2085 | ; extendqidi2 instruction pattern(s). | |
2086 | ; | |
2087 | ||
8b4a4127 | 2088 | (define_expand "extendqidi2" |
2089 | [(set (match_operand:DI 0 "register_operand" "") | |
2090 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
2091 | "" | |
2092 | " | |
2093 | { | |
2094 | if (!TARGET_64BIT) | |
2095 | { | |
2096 | rtx tmp = gen_reg_rtx (SImode); | |
2097 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
2098 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2099 | DONE; | |
2100 | } | |
2101 | else | |
2102 | { | |
2103 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2104 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
2105 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); | |
2106 | DONE; | |
2107 | } | |
2108 | } | |
2109 | ") | |
2110 | ||
2111 | (define_split | |
2112 | [(set (match_operand:DI 0 "register_operand" "") | |
2113 | (sign_extend:DI (match_operand:QI 1 "s_operand" "")))] | |
2114 | "TARGET_64BIT && !reload_completed" | |
2115 | [(parallel | |
2116 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10)) | |
2117 | (clobber (reg:CC 33))]) | |
2118 | (parallel | |
2119 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
2120 | (clobber (reg:CC 33))])] | |
2121 | "") | |
4673c1a0 | 2122 | |
2123 | ; | |
2124 | ; extendhisi2 instruction pattern(s). | |
2125 | ; | |
2126 | ||
8b4a4127 | 2127 | (define_expand "extendhisi2" |
2128 | [(set (match_operand:SI 0 "register_operand" "") | |
2129 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
4673c1a0 | 2130 | "" |
8b4a4127 | 2131 | " |
2132 | { | |
2133 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2134 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
2135 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); | |
2136 | DONE; | |
2137 | } | |
2138 | ") | |
4673c1a0 | 2139 | |
8b4a4127 | 2140 | (define_insn "*extendhisi2" |
2141 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2142 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] | |
2143 | "" | |
2144 | "lh\\t%0,%1" | |
2145 | [(set_attr "op_type" "RX") | |
2146 | (set_attr "atype" "mem")]) | |
4673c1a0 | 2147 | |
2148 | ; | |
2149 | ; extendqisi2 instruction pattern(s). | |
2150 | ; | |
2151 | ||
8b4a4127 | 2152 | (define_expand "extendqisi2" |
2153 | [(set (match_operand:SI 0 "register_operand" "") | |
2154 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
4673c1a0 | 2155 | "" |
8b4a4127 | 2156 | " |
2157 | { | |
2158 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2159 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
2160 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); | |
2161 | DONE; | |
2162 | } | |
2163 | ") | |
4673c1a0 | 2164 | |
8b4a4127 | 2165 | (define_split |
2166 | [(set (match_operand:SI 0 "register_operand" "") | |
2167 | (sign_extend:SI (match_operand:QI 1 "s_operand" "")))] | |
2168 | "!reload_completed" | |
2169 | [(parallel | |
2170 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) | |
2171 | (clobber (reg:CC 33))]) | |
2172 | (parallel | |
2173 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
2174 | (clobber (reg:CC 33))])] | |
2175 | "") | |
4673c1a0 | 2176 | |
2177 | ; | |
2178 | ; extendqihi2 instruction pattern(s). | |
2179 | ; | |
2180 | ||
4673c1a0 | 2181 | |
2182 | ; | |
2183 | ; zero_extendsidi2 instruction pattern(s). | |
2184 | ; | |
2185 | ||
8b4a4127 | 2186 | (define_expand "zero_extendsidi2" |
2187 | [(set (match_operand:DI 0 "register_operand" "") | |
2188 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2189 | "" | |
2190 | " | |
2191 | { | |
2192 | if (!TARGET_64BIT) | |
2193 | { | |
9f4d041d | 2194 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2195 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2196 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
8b4a4127 | 2197 | DONE; |
2198 | } | |
2199 | } | |
2200 | ") | |
2201 | ||
2202 | (define_insn "*zero_extendsidi2" | |
4673c1a0 | 2203 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2204 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2205 | "TARGET_64BIT" | |
2206 | "@ | |
2207 | llgfr\\t%0,%1 | |
2208 | llgf\\t%0,%1" | |
2209 | [(set_attr "op_type" "RRE,RXE") | |
369293ed | 2210 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 2211 | |
4673c1a0 | 2212 | ; |
2213 | ; zero_extendhidi2 instruction pattern(s). | |
2214 | ; | |
2215 | ||
8b4a4127 | 2216 | (define_expand "zero_extendhidi2" |
2217 | [(set (match_operand:DI 0 "register_operand" "") | |
2218 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2219 | "" | |
2220 | " | |
2221 | { | |
2222 | if (!TARGET_64BIT) | |
2223 | { | |
2224 | rtx tmp = gen_reg_rtx (SImode); | |
2225 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
2226 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
2227 | DONE; | |
2228 | } | |
2229 | else | |
2230 | { | |
2231 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2232 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
2233 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); | |
2234 | DONE; | |
2235 | } | |
2236 | } | |
2237 | ") | |
4673c1a0 | 2238 | |
8b4a4127 | 2239 | (define_insn "*zero_extendhidi2" |
2240 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2241 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
4673c1a0 | 2242 | "TARGET_64BIT" |
8b4a4127 | 2243 | "llgh\\t%0,%1" |
2244 | [(set_attr "op_type" "RXE") | |
2245 | (set_attr "atype" "mem")]) | |
4673c1a0 | 2246 | |
2247 | ; | |
8b4a4127 | 2248 | ; zero_extendqidi2 instruction pattern(s) |
4673c1a0 | 2249 | ; |
2250 | ||
8b4a4127 | 2251 | (define_expand "zero_extendqidi2" |
2252 | [(set (match_operand:DI 0 "register_operand" "") | |
2253 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
4673c1a0 | 2254 | "" |
2255 | " | |
2256 | { | |
2257 | if (!TARGET_64BIT) | |
2258 | { | |
8b4a4127 | 2259 | rtx tmp = gen_reg_rtx (SImode); |
2260 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
2261 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4673c1a0 | 2262 | DONE; |
2263 | } | |
8b4a4127 | 2264 | else |
2265 | { | |
2266 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2267 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
2268 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); | |
2269 | DONE; | |
2270 | } | |
2271 | } | |
2272 | ") | |
4673c1a0 | 2273 | |
8b4a4127 | 2274 | (define_insn "*zero_extendqidi2" |
2275 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2276 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
4673c1a0 | 2277 | "TARGET_64BIT" |
8b4a4127 | 2278 | "llgc\\t%0,%1" |
2279 | [(set_attr "op_type" "RXE") | |
2280 | (set_attr "atype" "mem")]) | |
4673c1a0 | 2281 | |
2282 | ; | |
8b4a4127 | 2283 | ; zero_extendhisi2 instruction pattern(s). |
4673c1a0 | 2284 | ; |
2285 | ||
8b4a4127 | 2286 | (define_expand "zero_extendhisi2" |
2287 | [(set (match_operand:SI 0 "register_operand" "") | |
2288 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
4673c1a0 | 2289 | "" |
8b4a4127 | 2290 | " |
2291 | { | |
2292 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2293 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
2294 | DONE; | |
2295 | } | |
2296 | ") | |
4673c1a0 | 2297 | |
8b4a4127 | 2298 | (define_insn "*zero_extendhisi2_64" |
4673c1a0 | 2299 | [(set (match_operand:SI 0 "register_operand" "=d") |
8b4a4127 | 2300 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
4673c1a0 | 2301 | "TARGET_64BIT" |
8b4a4127 | 2302 | "llgh\\t%0,%1" |
2303 | [(set_attr "op_type" "RXE") | |
2304 | (set_attr "atype" "mem")]) | |
147b6a2d | 2305 | |
2306 | (define_insn_and_split "*zero_extendhisi2_31" | |
2307 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2308 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "Q"))) | |
2309 | (clobber (reg:CC 33))] | |
2310 | "!TARGET_64BIT" | |
2311 | "#" | |
2312 | "&& reload_completed" | |
2313 | [(set (match_dup 0) (const_int 0)) | |
2314 | (parallel | |
2315 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
2316 | (clobber (reg:CC 33))])] | |
2317 | "operands[2] = gen_lowpart (HImode, operands[0]);" | |
2318 | [(set_attr "type" "o2") | |
2319 | (set_attr "atype" "mem")]) | |
8b4a4127 | 2320 | |
2321 | ; | |
2322 | ; zero_extendqisi2 instruction pattern(s). | |
2323 | ; | |
4673c1a0 | 2324 | |
2325 | (define_expand "zero_extendqisi2" | |
2326 | [(set (match_operand:SI 0 "register_operand" "") | |
8b4a4127 | 2327 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
4673c1a0 | 2328 | "" |
2329 | " | |
2330 | { | |
8b4a4127 | 2331 | operands[1] = gen_lowpart (SImode, operands[1]); |
2332 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2333 | DONE; | |
2334 | } | |
2335 | ") | |
4673c1a0 | 2336 | |
8b4a4127 | 2337 | (define_insn "*zero_extendqisi2_64" |
2338 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2339 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
2340 | "TARGET_64BIT" | |
2341 | "llgc\\t%0,%1" | |
2342 | [(set_attr "op_type" "RXE") | |
2343 | (set_attr "atype" "mem")]) | |
147b6a2d | 2344 | |
2345 | (define_insn_and_split "*zero_extendqisi2_31" | |
2346 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2347 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
2348 | "!TARGET_64BIT" | |
2349 | "#" | |
2350 | "&& reload_completed" | |
2351 | [(set (match_dup 0) (const_int 0)) | |
2352 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2353 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
2354 | [(set_attr "type" "o2") | |
2355 | (set_attr "atype" "mem")]) | |
8b4a4127 | 2356 | |
4673c1a0 | 2357 | ; |
2358 | ; zero_extendqihi2 instruction pattern(s). | |
2359 | ; | |
2360 | ||
4673c1a0 | 2361 | (define_expand "zero_extendqihi2" |
2362 | [(set (match_operand:HI 0 "register_operand" "") | |
8b4a4127 | 2363 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
4673c1a0 | 2364 | "TARGET_64BIT" |
4673c1a0 | 2365 | " |
2366 | { | |
8b4a4127 | 2367 | operands[1] = gen_lowpart (HImode, operands[1]); |
2368 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2369 | DONE; | |
2370 | } | |
2371 | ") | |
4673c1a0 | 2372 | |
8b4a4127 | 2373 | (define_insn "*zero_extendqihi2_64" |
4673c1a0 | 2374 | [(set (match_operand:HI 0 "register_operand" "=d") |
147b6a2d | 2375 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
4673c1a0 | 2376 | "TARGET_64BIT" |
8b4a4127 | 2377 | "llgc\\t%0,%1" |
2378 | [(set_attr "op_type" "RXE") | |
2379 | (set_attr "atype" "mem")]) | |
4673c1a0 | 2380 | |
147b6a2d | 2381 | (define_insn_and_split "*zero_extendqihi2_31" |
2382 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2383 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
2384 | "!TARGET_64BIT" | |
2385 | "#" | |
2386 | "&& reload_completed" | |
2387 | [(set (match_dup 0) (const_int 0)) | |
2388 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2389 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
2390 | [(set_attr "type" "o2") | |
2391 | (set_attr "atype" "mem")]) | |
2392 | ||
2393 | ||
4673c1a0 | 2394 | ; |
2395 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
2396 | ; | |
2397 | ||
2398 | (define_expand "fixuns_truncdfdi2" | |
2399 | [(set (match_operand:DI 0 "register_operand" "") | |
2400 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
2401 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2402 | " | |
2403 | { | |
2404 | rtx label1 = gen_label_rtx (); | |
2405 | rtx label2 = gen_label_rtx (); | |
2406 | rtx temp = gen_reg_rtx (DFmode); | |
2407 | operands[1] = force_reg (DFmode, operands[1]); | |
2408 | ||
8b4a4127 | 2409 | emit_insn (gen_cmpdf (operands[1], |
2410 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
2411 | REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode))); | |
4673c1a0 | 2412 | emit_jump_insn (gen_blt (label1)); |
8b4a4127 | 2413 | emit_insn (gen_subdf3 (temp, operands[1], |
2414 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
2415 | REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode))); | |
4673c1a0 | 2416 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
0c0a8ea5 | 2417 | emit_jump (label2); |
4673c1a0 | 2418 | |
2419 | emit_label (label1); | |
2420 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2421 | emit_label (label2); | |
2422 | DONE; | |
2423 | }") | |
2424 | ||
2425 | (define_expand "fix_truncdfdi2" | |
2426 | [(set (match_operand:DI 0 "register_operand" "") | |
2427 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2428 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2429 | " | |
2430 | { | |
2431 | operands[1] = force_reg (DFmode, operands[1]); | |
2432 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2433 | DONE; | |
2434 | }") | |
2435 | ||
2436 | (define_insn "fix_truncdfdi2_ieee" | |
2437 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2438 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
2439 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1) | |
2440 | (clobber (reg:CC 33))] | |
2441 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2442 | "cgdbr\\t%0,%h2,%1" | |
2443 | [(set_attr "op_type" "RRE") | |
8b4a4127 | 2444 | (set_attr "type" "other")]) |
4673c1a0 | 2445 | |
2446 | ; | |
2447 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
2448 | ; | |
2449 | ||
2450 | (define_expand "fixuns_truncdfsi2" | |
2451 | [(set (match_operand:SI 0 "register_operand" "") | |
2452 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
2453 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2454 | " | |
2455 | { | |
2456 | rtx label1 = gen_label_rtx (); | |
2457 | rtx label2 = gen_label_rtx (); | |
2458 | rtx temp = gen_reg_rtx (DFmode); | |
2459 | ||
2460 | operands[1] = force_reg (DFmode,operands[1]); | |
8b4a4127 | 2461 | emit_insn (gen_cmpdf (operands[1], |
2462 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
2463 | REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode))); | |
4673c1a0 | 2464 | emit_jump_insn (gen_blt (label1)); |
8b4a4127 | 2465 | emit_insn (gen_subdf3 (temp, operands[1], |
2466 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
2467 | REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode))); | |
4673c1a0 | 2468 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
0c0a8ea5 | 2469 | emit_jump (label2); |
4673c1a0 | 2470 | |
2471 | emit_label (label1); | |
2472 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2473 | emit_label (label2); | |
2474 | DONE; | |
2475 | }") | |
2476 | ||
2477 | (define_expand "fix_truncdfsi2" | |
2478 | [(set (match_operand:SI 0 "register_operand" "") | |
2479 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2480 | "TARGET_HARD_FLOAT" | |
2481 | " | |
2482 | { | |
2483 | if (TARGET_IBM_FLOAT) | |
2484 | { | |
2485 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2486 | ||
2487 | rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); | |
8b4a4127 | 2488 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2489 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
4673c1a0 | 2490 | |
2491 | operands[1] = force_reg (DFmode, operands[1]); | |
2492 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], | |
2493 | two31r, two32, temp)); | |
2494 | } | |
2495 | else | |
2496 | { | |
2497 | operands[1] = force_reg (DFmode, operands[1]); | |
2498 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2499 | } | |
2500 | ||
2501 | DONE; | |
2502 | }") | |
2503 | ||
2504 | (define_insn "fix_truncdfsi2_ieee" | |
2505 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2506 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
2507 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1) | |
2508 | (clobber (reg:CC 33))] | |
2509 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2510 | "cfdbr\\t%0,%h2,%1" | |
2511 | [(set_attr "op_type" "RRE") | |
8b4a4127 | 2512 | (set_attr "type" "other" )]) |
4673c1a0 | 2513 | |
2514 | (define_insn "fix_truncdfsi2_ibm" | |
2515 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2516 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
8b4a4127 | 2517 | (use (match_operand:DI 2 "immediate_operand" "m")) |
2518 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
4673c1a0 | 2519 | (use (match_operand:BLK 4 "memory_operand" "m")) |
2520 | (clobber (reg:CC 33))] | |
2521 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
2522 | "* | |
2523 | { | |
2524 | output_asm_insn (\"sd\\t%1,%2\", operands); | |
2525 | output_asm_insn (\"aw\\t%1,%3\", operands); | |
2526 | output_asm_insn (\"std\\t%1,%4\", operands); | |
2527 | output_asm_insn (\"xi\\t%N4,128\", operands); | |
2528 | return \"l\\t%0,%N4\"; | |
2529 | }" | |
2530 | [(set_attr "op_type" "NN") | |
8b4a4127 | 2531 | (set_attr "type" "other") |
4673c1a0 | 2532 | (set_attr "length" "20")]) |
2533 | ||
2534 | ; | |
2535 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
2536 | ; | |
2537 | ||
2538 | (define_expand "fixuns_truncsfdi2" | |
2539 | [(set (match_operand:DI 0 "register_operand" "") | |
2540 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
2541 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2542 | " | |
2543 | { | |
2544 | rtx label1 = gen_label_rtx (); | |
2545 | rtx label2 = gen_label_rtx (); | |
2546 | rtx temp = gen_reg_rtx (SFmode); | |
2547 | ||
2548 | operands[1] = force_reg (SFmode, operands[1]); | |
8b4a4127 | 2549 | emit_insn (gen_cmpsf (operands[1], |
2550 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
2551 | REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode))); | |
4673c1a0 | 2552 | emit_jump_insn (gen_blt (label1)); |
2553 | ||
8b4a4127 | 2554 | emit_insn (gen_subsf3 (temp, operands[1], |
2555 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
2556 | REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode))); | |
4673c1a0 | 2557 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
0c0a8ea5 | 2558 | emit_jump (label2); |
4673c1a0 | 2559 | |
2560 | emit_label (label1); | |
2561 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2562 | emit_label (label2); | |
2563 | DONE; | |
2564 | }") | |
2565 | ||
2566 | (define_expand "fix_truncsfdi2" | |
2567 | [(set (match_operand:DI 0 "register_operand" "") | |
2568 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2569 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2570 | " | |
2571 | { | |
2572 | operands[1] = force_reg (SFmode, operands[1]); | |
2573 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2574 | DONE; | |
2575 | }") | |
2576 | ||
2577 | (define_insn "fix_truncsfdi2_ieee" | |
2578 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2579 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
2580 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1) | |
2581 | (clobber (reg:CC 33))] | |
2582 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2583 | "cgebr\\t%0,%h2,%1" | |
2584 | [(set_attr "op_type" "RRE") | |
8b4a4127 | 2585 | (set_attr "type" "other")]) |
4673c1a0 | 2586 | |
2587 | ; | |
2588 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
2589 | ; | |
2590 | ||
2591 | (define_expand "fixuns_truncsfsi2" | |
2592 | [(set (match_operand:SI 0 "register_operand" "") | |
2593 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
2594 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2595 | " | |
2596 | { | |
2597 | rtx label1 = gen_label_rtx (); | |
2598 | rtx label2 = gen_label_rtx (); | |
2599 | rtx temp = gen_reg_rtx (SFmode); | |
2600 | ||
2601 | operands[1] = force_reg (SFmode, operands[1]); | |
8b4a4127 | 2602 | emit_insn (gen_cmpsf (operands[1], |
2603 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
2604 | REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode))); | |
4673c1a0 | 2605 | emit_jump_insn (gen_blt (label1)); |
8b4a4127 | 2606 | emit_insn (gen_subsf3 (temp, operands[1], |
2607 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
2608 | REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode))); | |
4673c1a0 | 2609 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
0c0a8ea5 | 2610 | emit_jump (label2); |
4673c1a0 | 2611 | |
2612 | emit_label (label1); | |
2613 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2614 | emit_label (label2); | |
2615 | DONE; | |
2616 | }") | |
2617 | ||
2618 | (define_expand "fix_truncsfsi2" | |
2619 | [(set (match_operand:SI 0 "register_operand" "") | |
2620 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2621 | "TARGET_HARD_FLOAT" | |
2622 | " | |
2623 | { | |
2624 | if (TARGET_IBM_FLOAT) | |
2625 | { | |
2626 | /* Convert to DFmode and then use the POP algorithm. */ | |
2627 | rtx temp = gen_reg_rtx (DFmode); | |
2628 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
2629 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
2630 | } | |
2631 | else | |
2632 | { | |
2633 | operands[1] = force_reg (SFmode, operands[1]); | |
2634 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2635 | } | |
2636 | ||
2637 | DONE; | |
2638 | }") | |
2639 | ||
2640 | (define_insn "fix_truncsfsi2_ieee" | |
2641 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2642 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
2643 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1) | |
2644 | (clobber (reg:CC 33))] | |
2645 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2646 | "cfebr\\t%0,%h2,%1" | |
2647 | [(set_attr "op_type" "RRE") | |
8b4a4127 | 2648 | (set_attr "type" "other")]) |
4673c1a0 | 2649 | |
2650 | ; | |
2651 | ; floatdidf2 instruction pattern(s). | |
2652 | ; | |
2653 | ||
2654 | (define_insn "floatdidf2" | |
2655 | [(set (match_operand:DF 0 "register_operand" "=f") | |
8b4a4127 | 2656 | (float:DF (match_operand:DI 1 "register_operand" "d"))) |
2657 | (clobber (reg:CC 33))] | |
4673c1a0 | 2658 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
2659 | "cdgbr\\t%0,%1" | |
2660 | [(set_attr "op_type" "RRE") | |
8b4a4127 | 2661 | (set_attr "type" "other" )]) |
4673c1a0 | 2662 | |
2663 | ; | |
2664 | ; floatdisf2 instruction pattern(s). | |
2665 | ; | |
2666 | ||
2667 | (define_insn "floatdisf2" | |
2668 | [(set (match_operand:SF 0 "register_operand" "=f") | |
8b4a4127 | 2669 | (float:SF (match_operand:DI 1 "register_operand" "d"))) |
2670 | (clobber (reg:CC 33))] | |
4673c1a0 | 2671 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
2672 | "cegbr\\t%0,%1" | |
2673 | [(set_attr "op_type" "RRE") | |
8b4a4127 | 2674 | (set_attr "type" "other" )]) |
4673c1a0 | 2675 | |
2676 | ; | |
2677 | ; floatsidf2 instruction pattern(s). | |
2678 | ; | |
2679 | ||
2680 | (define_expand "floatsidf2" | |
8b4a4127 | 2681 | [(parallel |
2682 | [(set (match_operand:DF 0 "register_operand" "") | |
2683 | (float:DF (match_operand:SI 1 "register_operand" ""))) | |
2684 | (clobber (reg:CC 33))])] | |
4673c1a0 | 2685 | "TARGET_HARD_FLOAT" |
2686 | " | |
2687 | { | |
2688 | if (TARGET_IBM_FLOAT) | |
2689 | { | |
2690 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
2691 | ||
2692 | rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); | |
8b4a4127 | 2693 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
4673c1a0 | 2694 | |
2695 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
2696 | DONE; | |
2697 | } | |
2698 | }") | |
2699 | ||
2700 | (define_insn "floatsidf2_ieee" | |
2701 | [(set (match_operand:DF 0 "register_operand" "=f") | |
8b4a4127 | 2702 | (float:DF (match_operand:SI 1 "register_operand" "d"))) |
2703 | (clobber (reg:CC 33))] | |
4673c1a0 | 2704 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
2705 | "cdfbr\\t%0,%1" | |
2706 | [(set_attr "op_type" "RRE") | |
369293ed | 2707 | (set_attr "type" "other" )]) |
4673c1a0 | 2708 | |
2709 | (define_insn "floatsidf2_ibm" | |
2710 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2711 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
8b4a4127 | 2712 | (use (match_operand:DI 2 "immediate_operand" "m")) |
4673c1a0 | 2713 | (use (match_operand:BLK 3 "memory_operand" "m")) |
2714 | (clobber (reg:CC 33))] | |
2715 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
2716 | "* | |
2717 | { | |
8b4a4127 | 2718 | output_asm_insn (\"st\\t%1,%N3\", operands); |
4673c1a0 | 2719 | output_asm_insn (\"xi\\t%N3,128\", operands); |
2720 | output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands); | |
2721 | output_asm_insn (\"ld\\t%0,%3\", operands); | |
2722 | return \"sd\\t%0,%2\"; | |
2723 | }" | |
2724 | [(set_attr "op_type" "NN") | |
8b4a4127 | 2725 | (set_attr "type" "other" ) |
4673c1a0 | 2726 | (set_attr "length" "20")]) |
2727 | ||
2728 | ; | |
2729 | ; floatsisf2 instruction pattern(s). | |
2730 | ; | |
2731 | ||
2732 | (define_expand "floatsisf2" | |
8b4a4127 | 2733 | [(parallel |
2734 | [(set (match_operand:SF 0 "register_operand" "") | |
2735 | (float:SF (match_operand:SI 1 "register_operand" ""))) | |
2736 | (clobber (reg:CC 33))])] | |
4673c1a0 | 2737 | "TARGET_HARD_FLOAT" |
2738 | " | |
2739 | { | |
2740 | if (TARGET_IBM_FLOAT) | |
2741 | { | |
2742 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
2743 | rtx temp = gen_reg_rtx (DFmode); | |
2744 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
2745 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
2746 | DONE; | |
2747 | } | |
2748 | }") | |
2749 | ||
2750 | (define_insn "floatsisf2_ieee" | |
2751 | [(set (match_operand:SF 0 "register_operand" "=f") | |
8b4a4127 | 2752 | (float:SF (match_operand:SI 1 "register_operand" "d"))) |
2753 | (clobber (reg:CC 33))] | |
4673c1a0 | 2754 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
2755 | "cefbr\\t%0,%1" | |
2756 | [(set_attr "op_type" "RRE") | |
8b4a4127 | 2757 | (set_attr "type" "other" )]) |
4673c1a0 | 2758 | |
2759 | ; | |
2760 | ; truncdfsf2 instruction pattern(s). | |
2761 | ; | |
2762 | ||
2763 | (define_expand "truncdfsf2" | |
2764 | [(set (match_operand:SF 0 "register_operand" "") | |
2765 | (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] | |
2766 | "TARGET_HARD_FLOAT" | |
8b4a4127 | 2767 | "") |
4673c1a0 | 2768 | |
2769 | (define_insn "truncdfsf2_ieee" | |
2770 | [(set (match_operand:SF 0 "register_operand" "=f") | |
8b4a4127 | 2771 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] |
4673c1a0 | 2772 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
2773 | "ledbr\\t%0,%1" | |
9fa6d5d9 | 2774 | [(set_attr "op_type" "RRE")]) |
4673c1a0 | 2775 | |
2776 | (define_insn "truncdfsf2_ibm" | |
2777 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
8b4a4127 | 2778 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))] |
4673c1a0 | 2779 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
2780 | "@ | |
2781 | lrer\\t%0,%1 | |
2782 | le\\t%0,%1" | |
8b4a4127 | 2783 | [(set_attr "op_type" "RR,RX") |
2784 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 2785 | |
2786 | ; | |
2787 | ; extendsfdf2 instruction pattern(s). | |
2788 | ; | |
2789 | ||
2790 | (define_expand "extendsfdf2" | |
2791 | [(set (match_operand:DF 0 "register_operand" "") | |
2792 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2793 | "TARGET_HARD_FLOAT" | |
2794 | " | |
2795 | { | |
2796 | if (TARGET_IBM_FLOAT) | |
2797 | { | |
2798 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
2799 | DONE; | |
2800 | } | |
2801 | }") | |
2802 | ||
2803 | (define_insn "extendsfdf2_ieee" | |
2804 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
2805 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))] | |
2806 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
2807 | "@ | |
2808 | ldebr\\t%0,%1 | |
2809 | ldeb\\t%0,%1" | |
2810 | [(set_attr "op_type" "RRE,RXE")]) | |
2811 | ||
2812 | (define_insn "extendsfdf2_ibm" | |
2813 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
2814 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m"))) | |
2815 | (clobber (reg:CC 33))] | |
2816 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
2817 | "@ | |
2818 | sdr\\t%0,%0\;ler\\t%0,%1 | |
2819 | sdr\\t%0,%0\;le\\t%0,%1" | |
8b4a4127 | 2820 | [(set_attr "op_type" "RRE,RXE") |
2821 | (set_attr "atype" "reg,mem") | |
2822 | (set_attr "type" "o2,o2")]) | |
4673c1a0 | 2823 | |
2824 | ||
2825 | ;; | |
2826 | ;; ARITHMETRIC OPERATIONS | |
2827 | ;; | |
2828 | ; arithmetric operations set the ConditionCode, | |
2829 | ; because of unpredictable Bits in Register for Halfword and Byte | |
2830 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
2831 | ||
c6821d1c | 2832 | ;; |
2833 | ;;- Add instructions. | |
2834 | ;; | |
2835 | ||
2836 | ; | |
2837 | ; adddi3 instruction pattern(s). | |
2838 | ; | |
2839 | ||
a40b2054 | 2840 | (define_insn "*la_64_cc" |
2841 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2842 | (match_operand:QI 1 "address_operand" "p")) | |
2843 | (clobber (reg:CC 33))] | |
2844 | "TARGET_64BIT | |
2845 | && preferred_la_operand_p (operands[1], 1)" | |
2846 | "#" | |
2847 | [(set_attr "op_type" "RX") | |
2848 | (set_attr "atype" "mem") | |
2849 | (set_attr "type" "la")]) | |
2850 | ||
2851 | (define_split | |
2852 | [(set (match_operand:DI 0 "register_operand" "") | |
2853 | (match_operand:QI 1 "address_operand" "")) | |
2854 | (clobber (reg:CC 33))] | |
2855 | "TARGET_64BIT && reload_completed | |
2856 | && preferred_la_operand_p (operands[1], 0)" | |
2857 | [(set (match_dup 0) (match_dup 1))]) | |
c6821d1c | 2858 | |
2859 | (define_insn "*adddi3_sign" | |
2860 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2861 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
2862 | (match_operand:DI 1 "register_operand" "0,0"))) | |
2863 | (clobber (reg:CC 33))] | |
2864 | "TARGET_64BIT" | |
2865 | "@ | |
2866 | agfr\\t%0,%2 | |
2867 | agf\\t%0,%2" | |
2868 | [(set_attr "op_type" "RRE,RXE") | |
2869 | (set_attr "atype" "reg,mem")]) | |
2870 | ||
2871 | (define_insn "*adddi3_zero_cc" | |
2872 | [(set (reg 33) | |
2873 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
2874 | (match_operand:DI 1 "register_operand" "0,0")) | |
2875 | (const_int 0))) | |
2876 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
2877 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
2878 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
2879 | "@ | |
2880 | algfr\\t%0,%2 | |
2881 | algf\\t%0,%2" | |
2882 | [(set_attr "op_type" "RRE,RXE") | |
2883 | (set_attr "atype" "reg,mem")]) | |
2884 | ||
2885 | (define_insn "*adddi3_zero_cconly" | |
2886 | [(set (reg 33) | |
2887 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
2888 | (match_operand:DI 1 "register_operand" "0,0")) | |
2889 | (const_int 0))) | |
2890 | (clobber (match_scratch:DI 0 "=d,d"))] | |
2891 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
2892 | "@ | |
2893 | algfr\\t%0,%2 | |
2894 | algf\\t%0,%2" | |
2895 | [(set_attr "op_type" "RRE,RXE") | |
2896 | (set_attr "atype" "reg,mem")]) | |
2897 | ||
2898 | (define_insn "*adddi3_zero" | |
2899 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2900 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
2901 | (match_operand:DI 1 "register_operand" "0,0"))) | |
2902 | (clobber (reg:CC 33))] | |
2903 | "TARGET_64BIT" | |
2904 | "@ | |
2905 | algfr\\t%0,%2 | |
2906 | algf\\t%0,%2" | |
2907 | [(set_attr "op_type" "RRE,RXE") | |
2908 | (set_attr "atype" "reg,mem")]) | |
2909 | ||
3c482144 | 2910 | (define_insn "*adddi3_imm_cc" |
2911 | [(set (reg 33) | |
2912 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") | |
2913 | (match_operand:DI 2 "const_int_operand" "K")) | |
2914 | (const_int 0))) | |
2915 | (set (match_operand:DI 0 "register_operand" "=d") | |
2916 | (plus:DI (match_dup 1) (match_dup 2)))] | |
2917 | "TARGET_64BIT | |
2918 | && s390_match_ccmode (insn, CCAmode) | |
2919 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" | |
2920 | "aghi\\t%0,%h2" | |
2921 | [(set_attr "op_type" "RI") | |
2922 | (set_attr "atype" "reg")]) | |
2923 | ||
c6821d1c | 2924 | (define_insn "*adddi3_cc" |
2925 | [(set (reg 33) | |
7c3aefa0 | 2926 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
c6821d1c | 2927 | (match_operand:DI 2 "general_operand" "d,m")) |
2928 | (const_int 0))) | |
2929 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
2930 | (plus:DI (match_dup 1) (match_dup 2)))] | |
2931 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
2932 | "@ | |
2933 | algr\\t%0,%2 | |
2934 | alg\\t%0,%2" | |
2935 | [(set_attr "op_type" "RRE,RXE") | |
2936 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 2937 | |
c6821d1c | 2938 | (define_insn "*adddi3_cconly" |
2939 | [(set (reg 33) | |
7c3aefa0 | 2940 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
c6821d1c | 2941 | (match_operand:DI 2 "general_operand" "d,m")) |
2942 | (const_int 0))) | |
2943 | (clobber (match_scratch:DI 0 "=d,d"))] | |
2944 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
2945 | "@ | |
2946 | algr\\t%0,%2 | |
2947 | alg\\t%0,%2" | |
2948 | [(set_attr "op_type" "RRE,RXE") | |
2949 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 2950 | |
c6821d1c | 2951 | (define_insn "*adddi3_cconly2" |
2952 | [(set (reg 33) | |
7c3aefa0 | 2953 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
c6821d1c | 2954 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
2955 | (clobber (match_scratch:DI 0 "=d,d"))] | |
2956 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
4673c1a0 | 2957 | "@ |
c6821d1c | 2958 | algr\\t%0,%2 |
2959 | alg\\t%0,%2" | |
2960 | [(set_attr "op_type" "RRE,RXE") | |
2961 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 2962 | |
c6821d1c | 2963 | (define_insn "*adddi3_64" |
4673c1a0 | 2964 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
7c3aefa0 | 2965 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
4673c1a0 | 2966 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
2967 | (clobber (reg:CC 33))] | |
2968 | "TARGET_64BIT" | |
2969 | "@ | |
2970 | agr\\t%0,%2 | |
2971 | aghi\\t%0,%h2 | |
2972 | ag\\t%0,%2" | |
2973 | [(set_attr "op_type" "RRE,RI,RXE") | |
369293ed | 2974 | (set_attr "atype" "reg,reg,mem")]) |
4673c1a0 | 2975 | |
c6821d1c | 2976 | (define_insn_and_split "*adddi3_31" |
2977 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
7c3aefa0 | 2978 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
c6821d1c | 2979 | (match_operand:DI 2 "general_operand" "dm") ) ) |
4673c1a0 | 2980 | (clobber (reg:CC 33))] |
2981 | "!TARGET_64BIT" | |
c6821d1c | 2982 | "#" |
2983 | "&& reload_completed" | |
2984 | [(parallel | |
2985 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
2986 | (clobber (reg:CC 33))]) | |
2987 | (parallel | |
2988 | [(set (reg:CCL1 33) | |
2989 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
2990 | (match_dup 7))) | |
2991 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
2992 | (set (pc) | |
2993 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
2994 | (pc) | |
2995 | (label_ref (match_dup 9)))) | |
2996 | (parallel | |
2997 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
2998 | (clobber (reg:CC 33))]) | |
2999 | (match_dup 9)] | |
3000 | "operands[3] = operand_subword (operands[0], 0, 1, DImode); | |
3001 | operands[4] = operand_subword (operands[1], 0, 1, DImode); | |
3002 | operands[5] = operand_subword (operands[2], 0, 1, DImode); | |
3003 | operands[6] = operand_subword (operands[0], 1, 1, DImode); | |
3004 | operands[7] = operand_subword (operands[1], 1, 1, DImode); | |
3005 | operands[8] = operand_subword (operands[2], 1, 1, DImode); | |
3006 | operands[9] = gen_label_rtx ();" | |
3007 | [(set_attr "op_type" "NN") | |
3008 | (set_attr "type" "o3")]) | |
4673c1a0 | 3009 | |
3010 | (define_expand "adddi3" | |
c6821d1c | 3011 | [(parallel |
3012 | [(set (match_operand:DI 0 "register_operand" "") | |
7c3aefa0 | 3013 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
c6821d1c | 3014 | (match_operand:DI 2 "general_operand" ""))) |
3015 | (clobber (reg:CC 33))])] | |
4673c1a0 | 3016 | "" |
c6821d1c | 3017 | "") |
4673c1a0 | 3018 | |
64f977d6 | 3019 | (define_insn "*la_64" |
3020 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4673c1a0 | 3021 | (match_operand:QI 1 "address_operand" "p"))] |
3022 | "TARGET_64BIT" | |
3023 | "la\\t%0,%a1" | |
3024 | [(set_attr "op_type" "RX") | |
3025 | (set_attr "atype" "mem") | |
3026 | (set_attr "type" "la")]) | |
3027 | ||
64f977d6 | 3028 | (define_expand "reload_indi" |
3029 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
3030 | (match_operand:DI 1 "s390_plus_operand" "") | |
e7f0624a | 3031 | (match_operand:DI 2 "register_operand" "=&a")])] |
4673c1a0 | 3032 | "TARGET_64BIT" |
8b4a4127 | 3033 | " |
3034 | { | |
64f977d6 | 3035 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); |
3036 | DONE; | |
8b4a4127 | 3037 | }") |
3038 | ||
4673c1a0 | 3039 | |
3040 | ; | |
3041 | ; addsi3 instruction pattern(s). | |
3042 | ; | |
4673c1a0 | 3043 | |
a40b2054 | 3044 | (define_insn "*la_31_cc" |
64f977d6 | 3045 | [(set (match_operand:SI 0 "register_operand" "=d") |
8b4a4127 | 3046 | (match_operand:QI 1 "address_operand" "p")) |
3047 | (clobber (reg:CC 33))] | |
a40b2054 | 3048 | "!TARGET_64BIT |
3049 | && preferred_la_operand_p (operands[1], 1)" | |
3050 | "#" | |
3051 | [(set_attr "op_type" "RX") | |
3052 | (set_attr "atype" "mem") | |
3053 | (set_attr "type" "la")]) | |
3054 | ||
3055 | (define_split | |
3056 | [(set (match_operand:SI 0 "register_operand" "") | |
3057 | (match_operand:QI 1 "address_operand" "")) | |
3058 | (clobber (reg:CC 33))] | |
3059 | "!TARGET_64BIT && reload_completed | |
3060 | && preferred_la_operand_p (operands[1], 0)" | |
3061 | [(set (match_dup 0) (match_dup 1))]) | |
8b4a4127 | 3062 | |
3c482144 | 3063 | (define_insn "*addsi3_imm_cc" |
3064 | [(set (reg 33) | |
3065 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") | |
3066 | (match_operand:SI 2 "const_int_operand" "K")) | |
3067 | (const_int 0))) | |
3068 | (set (match_operand:SI 0 "register_operand" "=d") | |
3069 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3070 | "s390_match_ccmode (insn, CCAmode) | |
3071 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" | |
3072 | "ahi\\t%0,%h2" | |
3073 | [(set_attr "op_type" "RI") | |
3074 | (set_attr "atype" "reg")]) | |
3075 | ||
c6821d1c | 3076 | (define_insn "*addsi3_carry1_cc" |
3077 | [(set (reg 33) | |
7c3aefa0 | 3078 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
c6821d1c | 3079 | (match_operand:SI 2 "general_operand" "d,m")) |
3080 | (match_dup 1))) | |
3081 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
3082 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3083 | "s390_match_ccmode (insn, CCL1mode)" | |
3084 | "@ | |
3085 | alr\\t%0,%2 | |
3086 | al\\t%0,%2" | |
3087 | [(set_attr "op_type" "RR,RX") | |
3088 | (set_attr "atype" "reg,mem")]) | |
3089 | ||
3090 | (define_insn "*addsi3_carry1_cconly" | |
3091 | [(set (reg 33) | |
7c3aefa0 | 3092 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
c6821d1c | 3093 | (match_operand:SI 2 "general_operand" "d,m")) |
3094 | (match_dup 1))) | |
3095 | (clobber (match_scratch:SI 0 "=d,d"))] | |
3096 | "s390_match_ccmode (insn, CCL1mode)" | |
3097 | "@ | |
3098 | alr\\t%0,%2 | |
3099 | al\\t%0,%2" | |
3100 | [(set_attr "op_type" "RR,RX") | |
3101 | (set_attr "atype" "reg,mem")]) | |
3102 | ||
3103 | (define_insn "*addsi3_carry2_cc" | |
3104 | [(set (reg 33) | |
7c3aefa0 | 3105 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
c6821d1c | 3106 | (match_operand:SI 2 "general_operand" "d,m")) |
3107 | (match_dup 2))) | |
3108 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
3109 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3110 | "s390_match_ccmode (insn, CCL1mode)" | |
3111 | "@ | |
3112 | alr\\t%0,%2 | |
3113 | al\\t%0,%2" | |
3114 | [(set_attr "op_type" "RR,RX") | |
3115 | (set_attr "atype" "reg,mem")]) | |
3116 | ||
3117 | (define_insn "*addsi3_carry2_cconly" | |
3118 | [(set (reg 33) | |
7c3aefa0 | 3119 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
c6821d1c | 3120 | (match_operand:SI 2 "general_operand" "d,m")) |
3121 | (match_dup 2))) | |
3122 | (clobber (match_scratch:SI 0 "=d,d"))] | |
3123 | "s390_match_ccmode (insn, CCL1mode)" | |
3124 | "@ | |
3125 | alr\\t%0,%2 | |
3126 | al\\t%0,%2" | |
3127 | [(set_attr "op_type" "RR,RX") | |
3128 | (set_attr "atype" "reg,mem")]) | |
3129 | ||
4673c1a0 | 3130 | (define_insn "*addsi3_cc" |
3131 | [(set (reg 33) | |
7c3aefa0 | 3132 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
c6821d1c | 3133 | (match_operand:SI 2 "general_operand" "d,m")) |
4673c1a0 | 3134 | (const_int 0))) |
2eb8fe23 | 3135 | (set (match_operand:SI 0 "register_operand" "=d,d") |
4673c1a0 | 3136 | (plus:SI (match_dup 1) (match_dup 2)))] |
c6821d1c | 3137 | "s390_match_ccmode (insn, CCLmode)" |
4673c1a0 | 3138 | "@ |
2eb8fe23 | 3139 | alr\\t%0,%2 |
3140 | al\\t%0,%2" | |
3141 | [(set_attr "op_type" "RR,RX") | |
3142 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 3143 | |
3144 | (define_insn "*addsi3_cconly" | |
3145 | [(set (reg 33) | |
7c3aefa0 | 3146 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
2eb8fe23 | 3147 | (match_operand:SI 2 "general_operand" "d,m")) |
4673c1a0 | 3148 | (const_int 0))) |
2eb8fe23 | 3149 | (clobber (match_scratch:SI 0 "=d,d"))] |
c6821d1c | 3150 | "s390_match_ccmode (insn, CCLmode)" |
4673c1a0 | 3151 | "@ |
2eb8fe23 | 3152 | alr\\t%0,%2 |
3153 | al\\t%0,%2" | |
3154 | [(set_attr "op_type" "RR,RX") | |
3155 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 3156 | |
3157 | (define_insn "*addsi3_cconly2" | |
3158 | [(set (reg 33) | |
7c3aefa0 | 3159 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
2eb8fe23 | 3160 | (neg:SI (match_operand:SI 2 "general_operand" "d,m")))) |
3161 | (clobber (match_scratch:SI 0 "=d,d"))] | |
3162 | "s390_match_ccmode(insn, CCLmode)" | |
4673c1a0 | 3163 | "@ |
2eb8fe23 | 3164 | alr\\t%0,%2 |
3165 | al\\t%0,%2" | |
3166 | [(set_attr "op_type" "RR,RX") | |
3167 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 3168 | |
c6821d1c | 3169 | (define_insn "*addsi3_sign" |
3170 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3171 | (plus:SI (match_operand:SI 1 "register_operand" "0") | |
3172 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "m")))) | |
3173 | (clobber (reg:CC 33))] | |
3174 | "" | |
3175 | "ah\\t%0,%2" | |
3176 | [(set_attr "op_type" "RX") | |
3177 | (set_attr "atype" "mem")]) | |
3178 | ||
3179 | (define_insn "*addsi3_sub" | |
3180 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3181 | (plus:SI (match_operand:SI 1 "register_operand" "0") | |
3182 | (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0))) | |
3183 | (clobber (reg:CC 33))] | |
3184 | "" | |
3185 | "ah\\t%0,%2" | |
3186 | [(set_attr "op_type" "RX") | |
3187 | (set_attr "atype" "mem")]) | |
3188 | ||
4673c1a0 | 3189 | (define_insn "addsi3" |
3190 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
7c3aefa0 | 3191 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4673c1a0 | 3192 | (match_operand:SI 2 "general_operand" "d,K,m"))) |
3193 | (clobber (reg:CC 33))] | |
3194 | "" | |
3195 | "@ | |
3196 | ar\\t%0,%2 | |
3197 | ahi\\t%0,%h2 | |
3198 | a\\t%0,%2" | |
3199 | [(set_attr "op_type" "RR,RI,RX") | |
369293ed | 3200 | (set_attr "atype" "reg,reg,mem")]) |
4673c1a0 | 3201 | |
64f977d6 | 3202 | (define_insn "*la_31" |
3203 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4673c1a0 | 3204 | (match_operand:QI 1 "address_operand" "p"))] |
a40b2054 | 3205 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
3206 | "la\\t%0,%a1" | |
3207 | [(set_attr "op_type" "RX") | |
3208 | (set_attr "atype" "mem") | |
3209 | (set_attr "type" "la")]) | |
3210 | ||
3211 | (define_insn "*la_31_and" | |
3212 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3213 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
3214 | (const_int 2147483647)))] | |
3215 | "!TARGET_64BIT" | |
4673c1a0 | 3216 | "la\\t%0,%a1" |
3217 | [(set_attr "op_type" "RX") | |
3218 | (set_attr "atype" "mem") | |
3219 | (set_attr "type" "la")]) | |
a40b2054 | 3220 | |
3221 | (define_insn_and_split "*la_31_and_cc" | |
3222 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3223 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
3224 | (const_int 2147483647))) | |
3225 | (clobber (reg:CC 33))] | |
3226 | "!TARGET_64BIT" | |
3227 | "#" | |
3228 | "&& reload_completed" | |
3229 | [(set (match_dup 0) | |
3230 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
3231 | "" | |
3232 | [(set_attr "op_type" "RX") | |
3233 | (set_attr "atype" "mem") | |
3234 | (set_attr "type" "la")]) | |
4673c1a0 | 3235 | |
4fbc4db5 | 3236 | (define_insn "force_la_31" |
3237 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3238 | (match_operand:QI 1 "address_operand" "p")) | |
3239 | (use (const_int 0))] | |
3240 | "!TARGET_64BIT" | |
3241 | "la\\t%0,%a1" | |
3242 | [(set_attr "op_type" "RX") | |
3243 | (set_attr "atype" "mem") | |
3244 | (set_attr "type" "la")]) | |
3245 | ||
64f977d6 | 3246 | (define_expand "reload_insi" |
3247 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
3248 | (match_operand:SI 1 "s390_plus_operand" "") | |
e7f0624a | 3249 | (match_operand:SI 2 "register_operand" "=&a")])] |
64f977d6 | 3250 | "!TARGET_64BIT" |
8b4a4127 | 3251 | " |
3252 | { | |
64f977d6 | 3253 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); |
3254 | DONE; | |
8b4a4127 | 3255 | }") |
f3fd783b | 3256 | |
4673c1a0 | 3257 | |
4673c1a0 | 3258 | ; |
3259 | ; adddf3 instruction pattern(s). | |
3260 | ; | |
3261 | ||
3262 | (define_expand "adddf3" | |
3263 | [(parallel | |
3264 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3265 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3266 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3267 | (clobber (reg:CC 33))])] |
3268 | "TARGET_HARD_FLOAT" | |
3269 | "") | |
3270 | ||
3271 | (define_insn "*adddf3" | |
3272 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3273 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3274 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3275 | (clobber (reg:CC 33))] |
3276 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3277 | "@ | |
3278 | adbr\\t%0,%2 | |
3279 | adb\\t%0,%2" | |
9fa6d5d9 | 3280 | [(set_attr "op_type" "RRE,RXE") |
4673c1a0 | 3281 | (set_attr "atype" "reg,mem")]) |
3282 | ||
3283 | (define_insn "*adddf3_ibm" | |
3284 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3285 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3286 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3287 | (clobber (reg:CC 33))] |
3288 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3289 | "@ | |
3290 | adr\\t%0,%2 | |
3291 | ad\\t%0,%2" | |
3292 | [(set_attr "op_type" "RR,RX") | |
3293 | (set_attr "atype" "reg,mem")]) | |
3294 | ||
3295 | ; | |
3296 | ; addsf3 instruction pattern(s). | |
3297 | ; | |
3298 | ||
3299 | (define_expand "addsf3" | |
3300 | [(parallel | |
3301 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3302 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3303 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3304 | (clobber (reg:CC 33))])] |
3305 | "TARGET_HARD_FLOAT" | |
3306 | "") | |
3307 | ||
3308 | (define_insn "*addsf3" | |
3309 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3310 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3311 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3312 | (clobber (reg:CC 33))] |
3313 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3314 | "@ | |
3315 | aebr\\t%0,%2 | |
3316 | aeb\\t%0,%2" | |
9fa6d5d9 | 3317 | [(set_attr "op_type" "RRE,RXE") |
4673c1a0 | 3318 | (set_attr "atype" "reg,mem")]) |
3319 | ||
3320 | (define_insn "*addsf3" | |
3321 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3322 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3323 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3324 | (clobber (reg:CC 33))] |
3325 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3326 | "@ | |
3327 | aer\\t%0,%2 | |
3328 | ae\\t%0,%2" | |
3329 | [(set_attr "op_type" "RR,RX") | |
3330 | (set_attr "atype" "reg,mem")]) | |
3331 | ||
3332 | ||
3333 | ;; | |
3334 | ;;- Subtract instructions. | |
3335 | ;; | |
3336 | ||
3337 | ; | |
3338 | ; subdi3 instruction pattern(s). | |
3339 | ; | |
3340 | ||
c6821d1c | 3341 | (define_insn "*subdi3_sign" |
3342 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3343 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3344 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3345 | (clobber (reg:CC 33))] | |
3346 | "TARGET_64BIT" | |
3347 | "@ | |
3348 | sgfr\\t%0,%2 | |
3349 | sgf\\t%0,%2" | |
3350 | [(set_attr "op_type" "RRE,RXE") | |
3351 | (set_attr "atype" "reg,mem")]) | |
3352 | ||
3353 | (define_insn "*subdi3_zero_cc" | |
3354 | [(set (reg 33) | |
3355 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3356 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3357 | (const_int 0))) | |
3358 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3359 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3360 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3361 | "@ | |
3362 | slgfr\\t%0,%2 | |
3363 | slgf\\t%0,%2" | |
3364 | [(set_attr "op_type" "RRE,RXE") | |
3365 | (set_attr "atype" "reg,mem")]) | |
3366 | ||
3367 | (define_insn "*subdi3_zero_cconly" | |
3368 | [(set (reg 33) | |
3369 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3370 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3371 | (const_int 0))) | |
3372 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3373 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3374 | "@ | |
3375 | slgfr\\t%0,%2 | |
3376 | slgf\\t%0,%2" | |
3377 | [(set_attr "op_type" "RRE,RXE") | |
3378 | (set_attr "atype" "reg,mem")]) | |
3379 | ||
3380 | (define_insn "*subdi3_zero" | |
3381 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3382 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3383 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3384 | (clobber (reg:CC 33))] | |
3385 | "TARGET_64BIT" | |
3386 | "@ | |
3387 | slgfr\\t%0,%2 | |
3388 | slgf\\t%0,%2" | |
3389 | [(set_attr "op_type" "RRE,RXE") | |
3390 | (set_attr "atype" "reg,mem")]) | |
3391 | ||
3392 | (define_insn "*subdi3_cc" | |
3393 | [(set (reg 33) | |
3394 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3395 | (match_operand:DI 2 "general_operand" "d,m")) | |
3396 | (const_int 0))) | |
3397 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3398 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3399 | "s390_match_ccmode (insn, CCLmode)" | |
3400 | "@ | |
3401 | slgr\\t%0,%2 | |
3402 | slg\\t%0,%2" | |
3403 | [(set_attr "op_type" "RRE,RXE") | |
3404 | (set_attr "atype" "reg,mem")]) | |
3405 | ||
3406 | (define_insn "*subdi3_cconly" | |
3407 | [(set (reg 33) | |
3408 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3409 | (match_operand:DI 2 "general_operand" "d,m")) | |
3410 | (const_int 0))) | |
3411 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3412 | "s390_match_ccmode (insn, CCLmode)" | |
3413 | "@ | |
3414 | slgr\\t%0,%2 | |
3415 | slg\\t%0,%2" | |
3416 | [(set_attr "op_type" "RRE,RXE") | |
3417 | (set_attr "atype" "reg,mem")]) | |
3418 | ||
4673c1a0 | 3419 | (define_insn "*subdi3_64" |
3420 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3421 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3422 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
3423 | (clobber (reg:CC 33))] | |
3424 | "TARGET_64BIT" | |
3425 | "@ | |
3426 | sgr\\t%0,%2 | |
3427 | sg\\t%0,%2" | |
3428 | [(set_attr "op_type" "RRE,RRE") | |
369293ed | 3429 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 3430 | |
c6821d1c | 3431 | (define_insn_and_split "*subdi3_31" |
3432 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3433 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3434 | (match_operand:DI 2 "general_operand" "dm") ) ) | |
4673c1a0 | 3435 | (clobber (reg:CC 33))] |
c6821d1c | 3436 | "!TARGET_64BIT" |
3437 | "#" | |
3438 | "&& reload_completed" | |
3439 | [(parallel | |
3440 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
3441 | (clobber (reg:CC 33))]) | |
3442 | (parallel | |
3443 | [(set (reg:CCL2 33) | |
3444 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3445 | (match_dup 7))) | |
3446 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3447 | (set (pc) | |
3448 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
3449 | (pc) | |
3450 | (label_ref (match_dup 9)))) | |
3451 | (parallel | |
3452 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
3453 | (clobber (reg:CC 33))]) | |
3454 | (match_dup 9)] | |
3455 | "operands[3] = operand_subword (operands[0], 0, 1, DImode); | |
3456 | operands[4] = operand_subword (operands[1], 0, 1, DImode); | |
3457 | operands[5] = operand_subword (operands[2], 0, 1, DImode); | |
3458 | operands[6] = operand_subword (operands[0], 1, 1, DImode); | |
3459 | operands[7] = operand_subword (operands[1], 1, 1, DImode); | |
3460 | operands[8] = operand_subword (operands[2], 1, 1, DImode); | |
3461 | operands[9] = gen_label_rtx ();" | |
3462 | [(set_attr "op_type" "NN") | |
3463 | (set_attr "type" "o3")]) | |
3464 | ||
3465 | (define_expand "subdi3" | |
3466 | [(parallel | |
3467 | [(set (match_operand:DI 0 "register_operand" "") | |
3468 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3469 | (match_operand:DI 2 "general_operand" ""))) | |
3470 | (clobber (reg:CC 33))])] | |
4673c1a0 | 3471 | "" |
c6821d1c | 3472 | "") |
4673c1a0 | 3473 | |
3474 | ; | |
3475 | ; subsi3 instruction pattern(s). | |
3476 | ; | |
3477 | ||
c6821d1c | 3478 | (define_insn "*subsi3_borrow_cc" |
3479 | [(set (reg 33) | |
3480 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3481 | (match_operand:SI 2 "general_operand" "d,m")) | |
3482 | (match_dup 1))) | |
3483 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
3484 | (minus:SI (match_dup 1) (match_dup 2)))] | |
3485 | "s390_match_ccmode(insn, CCL2mode)" | |
3486 | "@ | |
3487 | slr\\t%0,%2 | |
3488 | sl\\t%0,%2" | |
3489 | [(set_attr "op_type" "RR,RX") | |
3490 | (set_attr "atype" "reg,mem")]) | |
3491 | ||
3492 | (define_insn "*subsi3_borrow_cconly" | |
3493 | [(set (reg 33) | |
3494 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3495 | (match_operand:SI 2 "general_operand" "d,m")) | |
3496 | (match_dup 1))) | |
3497 | (clobber (match_scratch:SI 0 "=d,d"))] | |
3498 | "s390_match_ccmode(insn, CCL2mode)" | |
3499 | "@ | |
3500 | slr\\t%0,%2 | |
3501 | sl\\t%0,%2" | |
3502 | [(set_attr "op_type" "RR,RX") | |
3503 | (set_attr "atype" "reg,mem")]) | |
3504 | ||
4673c1a0 | 3505 | (define_insn "*subsi3_cc" |
3506 | [(set (reg 33) | |
3507 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3508 | (match_operand:SI 2 "general_operand" "d,m")) | |
3509 | (const_int 0))) | |
3510 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
3511 | (minus:SI (match_dup 1) (match_dup 2)))] | |
2eb8fe23 | 3512 | "s390_match_ccmode(insn, CCLmode)" |
4673c1a0 | 3513 | "@ |
2eb8fe23 | 3514 | slr\\t%0,%2 |
3515 | sl\\t%0,%2" | |
4673c1a0 | 3516 | [(set_attr "op_type" "RR,RX") |
369293ed | 3517 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 3518 | |
3519 | (define_insn "*subsi3_cconly" | |
3520 | [(set (reg 33) | |
3521 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3522 | (match_operand:SI 2 "general_operand" "d,m")) | |
3523 | (const_int 0))) | |
3524 | (clobber (match_scratch:SI 0 "=d,d"))] | |
2eb8fe23 | 3525 | "s390_match_ccmode(insn, CCLmode)" |
4673c1a0 | 3526 | "@ |
2eb8fe23 | 3527 | slr\\t%0,%2 |
3528 | sl\\t%0,%2" | |
4673c1a0 | 3529 | [(set_attr "op_type" "RR,RX") |
369293ed | 3530 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 3531 | |
c6821d1c | 3532 | (define_insn "*subsi3_sign" |
3533 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3534 | (minus:SI (match_operand:SI 1 "register_operand" "0") | |
3535 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "m")))) | |
3536 | (clobber (reg:CC 33))] | |
3537 | "" | |
3538 | "sh\\t%0,%2" | |
3539 | [(set_attr "op_type" "RX") | |
3540 | (set_attr "atype" "mem")]) | |
3541 | ||
3542 | (define_insn "*subsi3_sub" | |
3543 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3544 | (minus:SI (match_operand:SI 1 "register_operand" "0") | |
3545 | (subreg:SI (match_operand:HI 2 "memory_operand" "m") 0))) | |
3546 | (clobber (reg:CC 33))] | |
3547 | "" | |
3548 | "sh\\t%0,%2" | |
3549 | [(set_attr "op_type" "RX") | |
3550 | (set_attr "atype" "mem")]) | |
3551 | ||
4673c1a0 | 3552 | (define_insn "subsi3" |
3553 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3554 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3555 | (match_operand:SI 2 "general_operand" "d,m"))) | |
3556 | (clobber (reg:CC 33))] | |
3557 | "" | |
3558 | "@ | |
3559 | sr\\t%0,%2 | |
3560 | s\\t%0,%2" | |
3561 | [(set_attr "op_type" "RR,RX") | |
369293ed | 3562 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 3563 | |
4673c1a0 | 3564 | |
3565 | ; | |
3566 | ; subdf3 instruction pattern(s). | |
3567 | ; | |
3568 | ||
3569 | (define_expand "subdf3" | |
3570 | [(parallel | |
3571 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
3572 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
8b4a4127 | 3573 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3574 | (clobber (reg:CC 33))])] |
3575 | "TARGET_HARD_FLOAT" | |
3576 | "") | |
3577 | ||
3578 | (define_insn "*subdf3" | |
3579 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
3580 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
8b4a4127 | 3581 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3582 | (clobber (reg:CC 33))] |
3583 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3584 | "@ | |
3585 | sdbr\\t%0,%2 | |
3586 | sdb\\t%0,%2" | |
9fa6d5d9 | 3587 | [(set_attr "op_type" "RRE,RXE") |
4673c1a0 | 3588 | (set_attr "atype" "reg,mem")]) |
3589 | ||
3590 | (define_insn "*subdf3_ibm" | |
3591 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
3592 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
8b4a4127 | 3593 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3594 | (clobber (reg:CC 33))] |
3595 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3596 | "@ | |
3597 | sdr\\t%0,%2 | |
3598 | sd\\t%0,%2" | |
3599 | [(set_attr "op_type" "RR,RX") | |
3600 | (set_attr "atype" "reg,mem")]) | |
3601 | ||
3602 | ; | |
3603 | ; subsf3 instruction pattern(s). | |
3604 | ; | |
3605 | ||
3606 | (define_expand "subsf3" | |
3607 | [(parallel | |
3608 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
3609 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
8b4a4127 | 3610 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3611 | (clobber (reg:CC 33))])] |
3612 | "TARGET_HARD_FLOAT" | |
3613 | "") | |
3614 | ||
3615 | (define_insn "*subsf3" | |
3616 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
3617 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
8b4a4127 | 3618 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3619 | (clobber (reg:CC 33))] |
3620 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3621 | "@ | |
3622 | sebr\\t%0,%2 | |
3623 | seb\\t%0,%2" | |
9fa6d5d9 | 3624 | [(set_attr "op_type" "RRE,RXE") |
4673c1a0 | 3625 | (set_attr "atype" "reg,mem")]) |
3626 | ||
3627 | (define_insn "*subsf3_ibm" | |
3628 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
3629 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
8b4a4127 | 3630 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3631 | (clobber (reg:CC 33))] |
3632 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3633 | "@ | |
3634 | ser\\t%0,%2 | |
3635 | se\\t%0,%2" | |
3636 | [(set_attr "op_type" "RR,RX") | |
3637 | (set_attr "atype" "reg,mem")]) | |
3638 | ||
3639 | ||
3640 | ;; | |
3641 | ;;- Multiply instructions. | |
3642 | ;; | |
3643 | ||
8b4a4127 | 3644 | ; |
3645 | ; muldi3 instruction pattern(s). | |
3646 | ; | |
4673c1a0 | 3647 | |
c6821d1c | 3648 | (define_insn "*muldi3_sign" |
3649 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3650 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
3651 | (match_operand:DI 1 "register_operand" "0,0")))] | |
3652 | "TARGET_64BIT" | |
3653 | "@ | |
3654 | msgfr\\t%0,%2 | |
3655 | msgf\\t%0,%2" | |
3656 | [(set_attr "op_type" "RRE,RXE") | |
3657 | (set_attr "atype" "reg,mem") | |
3658 | (set_attr "type" "imul")]) | |
3659 | ||
3660 | ||
8b4a4127 | 3661 | (define_insn "muldi3" |
4673c1a0 | 3662 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
7c3aefa0 | 3663 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
c6821d1c | 3664 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
4673c1a0 | 3665 | "TARGET_64BIT" |
3666 | "@ | |
3667 | msgr\\t%0,%2 | |
3668 | mghi\\t%0,%h2 | |
3669 | msg\\t%0,%2" | |
c6821d1c | 3670 | [(set_attr "op_type" "RRE,RI,RXE") |
4673c1a0 | 3671 | (set_attr "atype" "reg,reg,mem") |
369293ed | 3672 | (set_attr "type" "imul")]) |
3673 | ||
4673c1a0 | 3674 | ; |
3675 | ; mulsi3 instruction pattern(s). | |
3676 | ; | |
3677 | ||
3678 | (define_insn "mulsi3" | |
3679 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
7c3aefa0 | 3680 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
c6821d1c | 3681 | (match_operand:SI 2 "general_operand" "d,K,m")))] |
4673c1a0 | 3682 | "" |
3683 | "@ | |
3684 | msr\\t%0,%2 | |
3685 | mhi\\t%0,%h2 | |
3686 | ms\\t%0,%2" | |
3687 | [(set_attr "op_type" "RRE,RI,RX") | |
4673c1a0 | 3688 | (set_attr "atype" "reg,reg,mem") |
369293ed | 3689 | (set_attr "type" "imul")]) |
4673c1a0 | 3690 | |
8b4a4127 | 3691 | ; |
3692 | ; mulsidi3 instruction pattern(s). | |
3693 | ; | |
3694 | ||
3695 | (define_expand "mulsidi3" | |
3696 | [(set (match_operand:DI 0 "register_operand" "") | |
7c3aefa0 | 3697 | (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")) |
8b4a4127 | 3698 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))] |
3699 | "!TARGET_64BIT" | |
3700 | " | |
3701 | { | |
3702 | rtx insn; | |
3703 | ||
ee85965c | 3704 | emit_insn (gen_zero_extendsidi2 (operands[0], operands[1])); |
8b4a4127 | 3705 | insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2])); |
3706 | ||
3707 | REG_NOTES (insn) = | |
3708 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
3709 | gen_rtx_MULT (DImode, | |
3710 | gen_rtx_SIGN_EXTEND (DImode, operands[1]), | |
3711 | gen_rtx_SIGN_EXTEND (DImode, operands[2])), | |
3712 | REG_NOTES (insn)); | |
3713 | DONE; | |
3714 | }") | |
3715 | ||
4673c1a0 | 3716 | (define_insn "mulsi_6432" |
3717 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3718 | (mult:DI (sign_extend:DI | |
8b4a4127 | 3719 | (truncate:SI (match_operand:DI 1 "register_operand" "0,0"))) |
4673c1a0 | 3720 | (sign_extend:DI |
c6821d1c | 3721 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] |
4673c1a0 | 3722 | "!TARGET_64BIT" |
3723 | "@ | |
3724 | mr\\t%0,%2 | |
3725 | m\\t%0,%2" | |
3726 | [(set_attr "op_type" "RR,RX") | |
4673c1a0 | 3727 | (set_attr "atype" "reg,mem") |
369293ed | 3728 | (set_attr "type" "imul")]) |
4673c1a0 | 3729 | |
4673c1a0 | 3730 | ; |
3731 | ; muldf3 instruction pattern(s). | |
3732 | ; | |
3733 | ||
3734 | (define_expand "muldf3" | |
3735 | [(parallel | |
3736 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3737 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3738 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3739 | (clobber (reg:CC 33))])] |
3740 | "TARGET_HARD_FLOAT" | |
3741 | "") | |
3742 | ||
3743 | (define_insn "*muldf3" | |
3744 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3745 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3746 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3747 | (clobber (reg:CC 33))] |
3748 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3749 | "@ | |
3750 | mdbr\\t%0,%2 | |
3751 | mdb\\t%0,%2" | |
9fa6d5d9 | 3752 | [(set_attr "op_type" "RRE,RXE") |
8b4a4127 | 3753 | (set_attr "type" "fmul") |
4673c1a0 | 3754 | (set_attr "atype" "reg,mem")]) |
3755 | ||
3756 | (define_insn "*muldf3_ibm" | |
3757 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3758 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3759 | (match_operand:DF 2 "general_operand" "f,m"))) |
4673c1a0 | 3760 | (clobber (reg:CC 33))] |
3761 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3762 | "@ | |
3763 | mdr\\t%0,%2 | |
3764 | md\\t%0,%2" | |
3765 | [(set_attr "op_type" "RR,RX") | |
369293ed | 3766 | (set_attr "type" "fmul") |
4673c1a0 | 3767 | (set_attr "atype" "reg,mem")]) |
3768 | ||
3769 | ; | |
3770 | ; mulsf3 instruction pattern(s). | |
3771 | ; | |
3772 | ||
3773 | (define_expand "mulsf3" | |
3774 | [(parallel | |
3775 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3776 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3777 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3778 | (clobber (reg:CC 33))])] |
3779 | "TARGET_HARD_FLOAT" | |
3780 | "") | |
3781 | ||
3782 | (define_insn "*mulsf3" | |
3783 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3784 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3785 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3786 | (clobber (reg:CC 33))] |
3787 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3788 | "@ | |
3789 | meebr\\t%0,%2 | |
3790 | meeb\\t%0,%2" | |
9fa6d5d9 | 3791 | [(set_attr "op_type" "RRE,RXE") |
369293ed | 3792 | (set_attr "type" "fmul") |
4673c1a0 | 3793 | (set_attr "atype" "reg,mem")]) |
3794 | ||
3795 | (define_insn "*mulsf3_ibm" | |
3796 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
7c3aefa0 | 3797 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 3798 | (match_operand:SF 2 "general_operand" "f,m"))) |
4673c1a0 | 3799 | (clobber (reg:CC 33))] |
3800 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3801 | "@ | |
3802 | mer\\t%0,%2 | |
3803 | me\\t%0,%2" | |
3804 | [(set_attr "op_type" "RR,RX") | |
369293ed | 3805 | (set_attr "type" "fmul") |
4673c1a0 | 3806 | (set_attr "atype" "reg,mem")]) |
3807 | ||
3808 | ||
3809 | ;; | |
3810 | ;;- Divide and modulo instructions. | |
3811 | ;; | |
3812 | ||
3813 | ; | |
8b4a4127 | 3814 | ; divmoddi4 instruction pattern(s). |
4673c1a0 | 3815 | ; |
3816 | ||
8b4a4127 | 3817 | (define_expand "divmoddi4" |
3818 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
3819 | (div:DI (match_operand:DI 1 "general_operand" "") | |
3820 | (match_operand:DI 2 "general_operand" ""))) | |
3821 | (set (match_operand:DI 3 "general_operand" "") | |
3822 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
3823 | (clobber (match_dup 4))] | |
4673c1a0 | 3824 | "TARGET_64BIT" |
3825 | " | |
3826 | { | |
8b4a4127 | 3827 | rtx insn, div_equal, mod_equal, equal; |
3828 | ||
3829 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
3830 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
3831 | equal = gen_rtx_IOR (TImode, | |
3832 | gen_rtx_ZERO_EXTEND (TImode, div_equal), | |
3833 | gen_rtx_ASHIFT (TImode, | |
3834 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
3835 | GEN_INT (64))); | |
3836 | ||
3837 | operands[4] = gen_reg_rtx(TImode); | |
3838 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
3839 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
66a63c5b | 3840 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); |
8b4a4127 | 3841 | insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2])); |
3842 | REG_NOTES (insn) = | |
3843 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
3844 | ||
3845 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
3846 | REG_NOTES (insn) = | |
3847 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
3848 | ||
3849 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
3850 | REG_NOTES (insn) = | |
3851 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4673c1a0 | 3852 | |
4673c1a0 | 3853 | DONE; |
3854 | }") | |
3855 | ||
3856 | (define_insn "divmodtidi3" | |
8b4a4127 | 3857 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
3858 | (ior:TI | |
3859 | (zero_extend:TI | |
3860 | (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) | |
3861 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3862 | (ashift:TI | |
3863 | (zero_extend:TI | |
3864 | (mod:DI (truncate:DI (match_dup 1)) | |
3865 | (match_dup 2))) | |
3866 | (const_int 64))))] | |
4673c1a0 | 3867 | "TARGET_64BIT" |
3868 | "@ | |
3869 | dsgr\\t%0,%2 | |
3870 | dsg\\t%0,%2" | |
3871 | [(set_attr "op_type" "RRE,RXE") | |
369293ed | 3872 | (set_attr "type" "idiv") |
4673c1a0 | 3873 | (set_attr "atype" "reg,mem")]) |
3874 | ||
8b4a4127 | 3875 | (define_insn "divmodtisi3" |
3876 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
3877 | (ior:TI | |
3878 | (zero_extend:TI | |
3879 | (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) | |
3880 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) | |
3881 | (ashift:TI | |
3882 | (zero_extend:TI | |
3883 | (mod:DI (truncate:DI (match_dup 1)) | |
3884 | (sign_extend:DI (match_dup 2)))) | |
3885 | (const_int 64))))] | |
4673c1a0 | 3886 | "TARGET_64BIT" |
8b4a4127 | 3887 | "@ |
3888 | dsgfr\\t%0,%2 | |
3889 | dsgf\\t%0,%2" | |
3890 | [(set_attr "op_type" "RRE,RXE") | |
3891 | (set_attr "type" "idiv") | |
3892 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 3893 | |
8b4a4127 | 3894 | ; |
3895 | ; udivmoddi4 instruction pattern(s). | |
3896 | ; | |
4673c1a0 | 3897 | |
8b4a4127 | 3898 | (define_expand "udivmoddi4" |
3899 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
3900 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
3901 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
3902 | (set (match_operand:DI 3 "general_operand" "") | |
3903 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
3904 | (clobber (match_dup 4))] | |
4673c1a0 | 3905 | "TARGET_64BIT" |
3906 | " | |
3907 | { | |
8b4a4127 | 3908 | rtx insn, div_equal, mod_equal, equal; |
3909 | ||
3910 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
3911 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
3912 | equal = gen_rtx_IOR (TImode, | |
3913 | gen_rtx_ZERO_EXTEND (TImode, div_equal), | |
3914 | gen_rtx_ASHIFT (TImode, | |
3915 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
3916 | GEN_INT (64))); | |
3917 | ||
3918 | operands[4] = gen_reg_rtx(TImode); | |
3919 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
3920 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
3921 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
3922 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
3923 | REG_NOTES (insn) = | |
3924 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
3925 | ||
3926 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
3927 | REG_NOTES (insn) = | |
3928 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
3929 | ||
3930 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
3931 | REG_NOTES (insn) = | |
3932 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4673c1a0 | 3933 | |
4673c1a0 | 3934 | DONE; |
3935 | }") | |
3936 | ||
3937 | (define_insn "udivmodtidi3" | |
8b4a4127 | 3938 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
3939 | (ior:TI (zero_extend:TI | |
3940 | (truncate:DI | |
3941 | (udiv:TI (match_operand:TI 1 "register_operand" "0,0") | |
3942 | (zero_extend:TI | |
3943 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) | |
3944 | (ashift:TI | |
3945 | (zero_extend:TI | |
3946 | (truncate:DI | |
3947 | (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2))))) | |
3948 | (const_int 64))))] | |
4673c1a0 | 3949 | "TARGET_64BIT" |
3950 | "@ | |
3951 | dlgr\\t%0,%2 | |
3952 | dlg\\t%0,%2" | |
3953 | [(set_attr "op_type" "RRE,RXE") | |
369293ed | 3954 | (set_attr "type" "idiv") |
4673c1a0 | 3955 | (set_attr "atype" "reg,mem")]) |
3956 | ||
3957 | ; | |
8b4a4127 | 3958 | ; divmodsi4 instruction pattern(s). |
4673c1a0 | 3959 | ; |
3960 | ||
8b4a4127 | 3961 | (define_expand "divmodsi4" |
3962 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
3963 | (div:SI (match_operand:SI 1 "general_operand" "") | |
3964 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
3965 | (set (match_operand:SI 3 "general_operand" "") | |
3966 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
3967 | (clobber (match_dup 4))] | |
4673c1a0 | 3968 | "!TARGET_64BIT" |
3969 | " | |
3970 | { | |
8b4a4127 | 3971 | rtx insn, div_equal, mod_equal, equal; |
3972 | ||
3973 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
3974 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
3975 | equal = gen_rtx_IOR (DImode, | |
3976 | gen_rtx_ZERO_EXTEND (DImode, div_equal), | |
3977 | gen_rtx_ASHIFT (DImode, | |
3978 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
3979 | GEN_INT (32))); | |
3980 | ||
3981 | operands[4] = gen_reg_rtx(DImode); | |
3982 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
3983 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
3984 | REG_NOTES (insn) = | |
3985 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
3986 | ||
3987 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
3988 | REG_NOTES (insn) = | |
3989 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
3990 | ||
3991 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
3992 | REG_NOTES (insn) = | |
3993 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4673c1a0 | 3994 | |
4673c1a0 | 3995 | DONE; |
3996 | }") | |
3997 | ||
3998 | (define_insn "divmoddisi3" | |
8b4a4127 | 3999 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
4000 | (ior:DI (zero_extend:DI | |
4001 | (truncate:SI | |
4002 | (div:DI (match_operand:DI 1 "register_operand" "0,0") | |
4003 | (sign_extend:DI | |
4004 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) | |
4005 | (ashift:DI | |
4006 | (zero_extend:DI | |
4007 | (truncate:SI | |
4008 | (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2))))) | |
4009 | (const_int 32))))] | |
4673c1a0 | 4010 | "!TARGET_64BIT" |
4011 | "@ | |
4012 | dr\\t%0,%2 | |
4013 | d\\t%0,%2" | |
4014 | [(set_attr "op_type" "RR,RX") | |
369293ed | 4015 | (set_attr "type" "idiv") |
4673c1a0 | 4016 | (set_attr "atype" "reg,mem")]) |
4017 | ||
4018 | ; | |
4019 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4020 | ; | |
4021 | ||
8b4a4127 | 4022 | |
4673c1a0 | 4023 | (define_expand "udivsi3" |
4024 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4025 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
8b4a4127 | 4026 | (match_operand:SI 2 "general_operand" ""))) |
4027 | (clobber (match_dup 3))] | |
4673c1a0 | 4028 | "!TARGET_64BIT" |
4029 | " | |
4030 | { | |
8b4a4127 | 4031 | rtx insn, udiv_equal, umod_equal, equal; |
4032 | ||
4033 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4034 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4035 | equal = gen_rtx_IOR (DImode, | |
4036 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal), | |
4037 | gen_rtx_ASHIFT (DImode, | |
4038 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
4039 | GEN_INT (32))); | |
4673c1a0 | 4040 | |
8b4a4127 | 4041 | operands[3] = gen_reg_rtx (DImode); |
4673c1a0 | 4042 | |
4043 | if (CONSTANT_P (operands[2])) | |
4044 | { | |
4045 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4046 | { | |
4047 | rtx label1 = gen_label_rtx (); | |
4048 | ||
8b4a4127 | 4049 | operands[1] = make_safe_from (operands[1], operands[0]); |
4050 | emit_move_insn (operands[0], const0_rtx); | |
4051 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
4673c1a0 | 4052 | emit_jump_insn (gen_bltu (label1)); |
8b4a4127 | 4053 | emit_move_insn (operands[0], const1_rtx); |
4673c1a0 | 4054 | emit_label (label1); |
4055 | } | |
4056 | else | |
4057 | { | |
8b4a4127 | 4058 | operands[2] = force_reg (SImode, operands[2]); |
4059 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4060 | ||
4061 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4062 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4063 | operands[2])); | |
4064 | REG_NOTES (insn) = | |
4065 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4066 | ||
4067 | insn = emit_move_insn (operands[0], | |
4068 | gen_lowpart (SImode, operands[3])); | |
4069 | REG_NOTES (insn) = | |
4070 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
4071 | udiv_equal, REG_NOTES (insn)); | |
4673c1a0 | 4072 | } |
4073 | } | |
4074 | else | |
4075 | { | |
4076 | rtx label1 = gen_label_rtx (); | |
4077 | rtx label2 = gen_label_rtx (); | |
4078 | rtx label3 = gen_label_rtx (); | |
4079 | ||
4080 | operands[1] = force_reg (SImode, operands[1]); | |
8b4a4127 | 4081 | operands[1] = make_safe_from (operands[1], operands[0]); |
4673c1a0 | 4082 | operands[2] = force_reg (SImode, operands[2]); |
8b4a4127 | 4083 | operands[2] = make_safe_from (operands[2], operands[0]); |
4084 | ||
4085 | emit_move_insn (operands[0], const0_rtx); | |
4673c1a0 | 4086 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4087 | emit_jump_insn (gen_bgtu (label3)); | |
4088 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4089 | emit_jump_insn (gen_blt (label2)); | |
4090 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4091 | emit_jump_insn (gen_beq (label1)); | |
8b4a4127 | 4092 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4093 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4094 | operands[2])); | |
4095 | REG_NOTES (insn) = | |
4096 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4097 | ||
4098 | insn = emit_move_insn (operands[0], | |
4099 | gen_lowpart (SImode, operands[3])); | |
4100 | REG_NOTES (insn) = | |
4101 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
4102 | udiv_equal, REG_NOTES (insn)); | |
0c0a8ea5 | 4103 | emit_jump (label3); |
4673c1a0 | 4104 | emit_label (label1); |
8b4a4127 | 4105 | emit_move_insn (operands[0], operands[1]); |
0c0a8ea5 | 4106 | emit_jump (label3); |
4673c1a0 | 4107 | emit_label (label2); |
8b4a4127 | 4108 | emit_move_insn (operands[0], const1_rtx); |
4673c1a0 | 4109 | emit_label (label3); |
4110 | } | |
8b4a4127 | 4111 | emit_move_insn (operands[0], operands[0]); |
4673c1a0 | 4112 | DONE; |
4113 | }") | |
4114 | ||
4115 | (define_expand "umodsi3" | |
4116 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4117 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
8b4a4127 | 4118 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4119 | (clobber (match_dup 3))] | |
4673c1a0 | 4120 | "!TARGET_64BIT" |
4121 | " | |
4122 | { | |
8b4a4127 | 4123 | rtx insn, udiv_equal, umod_equal, equal; |
4124 | ||
4125 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4126 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4127 | equal = gen_rtx_IOR (DImode, | |
4128 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal), | |
4129 | gen_rtx_ASHIFT (DImode, | |
4130 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
4131 | GEN_INT (32))); | |
4673c1a0 | 4132 | |
8b4a4127 | 4133 | operands[3] = gen_reg_rtx (DImode); |
4673c1a0 | 4134 | |
4135 | if (CONSTANT_P (operands[2])) | |
4136 | { | |
4137 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4138 | { | |
4139 | rtx label1 = gen_label_rtx (); | |
4140 | ||
8b4a4127 | 4141 | operands[1] = make_safe_from (operands[1], operands[0]); |
4142 | emit_move_insn (operands[0], operands[1]); | |
4143 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
4673c1a0 | 4144 | emit_jump_insn (gen_bltu (label1)); |
8b4a4127 | 4145 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4146 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
4673c1a0 | 4147 | emit_label (label1); |
4148 | } | |
4149 | else | |
4150 | { | |
8b4a4127 | 4151 | operands[2] = force_reg (SImode, operands[2]); |
4152 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4153 | ||
4154 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4155 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4156 | operands[2])); | |
4157 | REG_NOTES (insn) = | |
4158 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4159 | ||
4160 | insn = emit_move_insn (operands[0], | |
4161 | gen_highpart (SImode, operands[3])); | |
4162 | REG_NOTES (insn) = | |
4163 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
4164 | umod_equal, REG_NOTES (insn)); | |
4673c1a0 | 4165 | } |
4166 | } | |
4167 | else | |
4168 | { | |
4169 | rtx label1 = gen_label_rtx (); | |
4170 | rtx label2 = gen_label_rtx (); | |
4171 | rtx label3 = gen_label_rtx (); | |
4172 | ||
4173 | operands[1] = force_reg (SImode, operands[1]); | |
8b4a4127 | 4174 | operands[1] = make_safe_from (operands[1], operands[0]); |
4673c1a0 | 4175 | operands[2] = force_reg (SImode, operands[2]); |
8b4a4127 | 4176 | operands[2] = make_safe_from (operands[2], operands[0]); |
4673c1a0 | 4177 | |
8b4a4127 | 4178 | emit_move_insn(operands[0], operands[1]); |
4179 | emit_insn (gen_cmpsi (operands[2], operands[1])); | |
4673c1a0 | 4180 | emit_jump_insn (gen_bgtu (label3)); |
4181 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4182 | emit_jump_insn (gen_blt (label2)); | |
4183 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4184 | emit_jump_insn (gen_beq (label1)); | |
8b4a4127 | 4185 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4186 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4187 | operands[2])); | |
4188 | REG_NOTES (insn) = | |
4189 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4190 | ||
4191 | insn = emit_move_insn (operands[0], | |
4192 | gen_highpart (SImode, operands[3])); | |
4193 | REG_NOTES (insn) = | |
4194 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
4195 | umod_equal, REG_NOTES (insn)); | |
0c0a8ea5 | 4196 | emit_jump (label3); |
4673c1a0 | 4197 | emit_label (label1); |
8b4a4127 | 4198 | emit_move_insn (operands[0], const0_rtx); |
0c0a8ea5 | 4199 | emit_jump (label3); |
4673c1a0 | 4200 | emit_label (label2); |
8b4a4127 | 4201 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
4673c1a0 | 4202 | emit_label (label3); |
4203 | } | |
4673c1a0 | 4204 | DONE; |
4205 | }") | |
4206 | ||
4207 | ; | |
4208 | ; divdf3 instruction pattern(s). | |
4209 | ; | |
4210 | ||
4211 | (define_expand "divdf3" | |
4212 | [(parallel | |
8b4a4127 | 4213 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4214 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
4215 | (match_operand:DF 2 "general_operand" "f,m"))) | |
4673c1a0 | 4216 | (clobber (reg:CC 33))])] |
4217 | "TARGET_HARD_FLOAT" | |
4218 | "") | |
4219 | ||
4220 | (define_insn "*divdf3" | |
8b4a4127 | 4221 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4222 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
4223 | (match_operand:DF 2 "general_operand" "f,m"))) | |
4673c1a0 | 4224 | (clobber (reg:CC 33))] |
4225 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4226 | "@ | |
4227 | ddbr\\t%0,%2 | |
4228 | ddb\\t%0,%2" | |
9fa6d5d9 | 4229 | [(set_attr "op_type" "RRE,RXE") |
8b4a4127 | 4230 | (set_attr "type" "fdiv") |
4673c1a0 | 4231 | (set_attr "atype" "reg,mem")]) |
4232 | ||
4233 | (define_insn "*divdf3_ibm" | |
8b4a4127 | 4234 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4235 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
4236 | (match_operand:DF 2 "general_operand" "f,m"))) | |
4673c1a0 | 4237 | (clobber (reg:CC 33))] |
4238 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4239 | "@ | |
4240 | ddr\\t%0,%2 | |
4241 | dd\\t%0,%2" | |
4242 | [(set_attr "op_type" "RR,RX") | |
8b4a4127 | 4243 | (set_attr "type" "fdiv") |
4673c1a0 | 4244 | (set_attr "atype" "reg,mem")]) |
4245 | ||
4246 | ; | |
4247 | ; divsf3 instruction pattern(s). | |
4248 | ; | |
4249 | ||
4250 | (define_expand "divsf3" | |
4251 | [(parallel | |
8b4a4127 | 4252 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4253 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
4254 | (match_operand:SF 2 "general_operand" "f,m"))) | |
4673c1a0 | 4255 | (clobber (reg:CC 33))])] |
4256 | "TARGET_HARD_FLOAT" | |
4257 | "") | |
4258 | ||
4259 | (define_insn "*divsf3" | |
8b4a4127 | 4260 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4261 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
4262 | (match_operand:SF 2 "general_operand" "f,m"))) | |
4673c1a0 | 4263 | (clobber (reg:CC 33))] |
4264 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4265 | "@ | |
4266 | debr\\t%0,%2 | |
4267 | deb\\t%0,%2" | |
9fa6d5d9 | 4268 | [(set_attr "op_type" "RRE,RXE") |
369293ed | 4269 | (set_attr "type" "fdiv") |
4673c1a0 | 4270 | (set_attr "atype" "reg,mem")]) |
4271 | ||
4272 | (define_insn "*divsf3" | |
8b4a4127 | 4273 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4274 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
4275 | (match_operand:SF 2 "general_operand" "f,m"))) | |
4673c1a0 | 4276 | (clobber (reg:CC 33))] |
4277 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4278 | "@ | |
4279 | der\\t%0,%2 | |
4280 | de\\t%0,%2" | |
4281 | [(set_attr "op_type" "RR,RX") | |
369293ed | 4282 | (set_attr "type" "fdiv") |
4673c1a0 | 4283 | (set_attr "atype" "reg,mem")]) |
4284 | ||
4285 | ||
4286 | ;; | |
4287 | ;;- And instructions. | |
4288 | ;; | |
4289 | ||
4290 | ; | |
4291 | ; anddi3 instruction pattern(s). | |
4292 | ; | |
4293 | ||
4294 | (define_insn "*anddi3_cc" | |
4295 | [(set (reg 33) | |
7c3aefa0 | 4296 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4297 | (match_operand:DI 2 "general_operand" "d,m")) |
4673c1a0 | 4298 | (const_int 0))) |
8b4a4127 | 4299 | (set (match_operand:DI 0 "register_operand" "=d,d") |
4673c1a0 | 4300 | (and:DI (match_dup 1) (match_dup 2)))] |
4301 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4302 | "@ | |
4303 | ngr\\t%0,%2 | |
8b4a4127 | 4304 | ng\\t%0,%2" |
4305 | [(set_attr "op_type" "RRE,RXE") | |
4306 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 4307 | |
4308 | (define_insn "*anddi3_cconly" | |
4309 | [(set (reg 33) | |
7c3aefa0 | 4310 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4311 | (match_operand:DI 2 "general_operand" "d,m")) |
4673c1a0 | 4312 | (const_int 0))) |
4313 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4314 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4315 | "@ | |
4316 | ngr\\t%0,%2 | |
4317 | ng\\t%0,%2" | |
8b4a4127 | 4318 | [(set_attr "op_type" "RRE,RXE") |
369293ed | 4319 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 4320 | |
8b4a4127 | 4321 | (define_insn "*anddi3_ni" |
4322 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2e5d1042 | 4323 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
8b4a4127 | 4324 | (match_operand:DI 2 "immediate_operand" "n"))) |
4325 | (clobber (reg:CC 33))] | |
4326 | "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0" | |
4327 | "* | |
4328 | { | |
4329 | int part = s390_single_hi (operands[2], DImode, -1); | |
4330 | operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); | |
4331 | ||
4332 | switch (part) | |
4333 | { | |
4334 | case 0: return \"nihh\\t%0,%x2\"; | |
4335 | case 1: return \"nihl\\t%0,%x2\"; | |
4336 | case 2: return \"nilh\\t%0,%x2\"; | |
4337 | case 3: return \"nill\\t%0,%x2\"; | |
4338 | default: abort (); | |
4339 | } | |
4340 | }" | |
4341 | [(set_attr "op_type" "RI") | |
4342 | (set_attr "atype" "reg")]) | |
4343 | ||
4673c1a0 | 4344 | (define_insn "anddi3" |
8b4a4127 | 4345 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
7c3aefa0 | 4346 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4347 | (match_operand:DI 2 "general_operand" "d,m"))) |
4673c1a0 | 4348 | (clobber (reg:CC 33))] |
4349 | "TARGET_64BIT" | |
4350 | "@ | |
4351 | ngr\\t%0,%2 | |
8b4a4127 | 4352 | ng\\t%0,%2" |
4353 | [(set_attr "op_type" "RRE,RXE") | |
4354 | (set_attr "atype" "reg,mem")]) | |
4355 | ||
4356 | (define_insn "*anddi3_ss" | |
a5004c3d | 4357 | [(set (match_operand:DI 0 "s_operand" "=Q") |
8b4a4127 | 4358 | (and:DI (match_dup 0) |
a5004c3d | 4359 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4360 | (clobber (reg:CC 33))] |
4361 | "" | |
4362 | "nc\\t%O0(8,%R0),%1" | |
4363 | [(set_attr "op_type" "SS") | |
4364 | (set_attr "atype" "mem")]) | |
4365 | ||
4366 | (define_insn "*anddi3_ss_inv" | |
a5004c3d | 4367 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4368 | (and:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4369 | (match_dup 0))) |
4370 | (clobber (reg:CC 33))] | |
4371 | "" | |
4372 | "nc\\t%O0(8,%R0),%1" | |
4373 | [(set_attr "op_type" "SS") | |
4374 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4375 | |
4376 | ; | |
4377 | ; andsi3 instruction pattern(s). | |
4378 | ; | |
4379 | ||
4380 | (define_insn "*andsi3_cc" | |
4381 | [(set (reg 33) | |
7c3aefa0 | 4382 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4383 | (match_operand:SI 2 "general_operand" "d,m")) |
4673c1a0 | 4384 | (const_int 0))) |
8b4a4127 | 4385 | (set (match_operand:SI 0 "register_operand" "=d,d") |
4673c1a0 | 4386 | (and:SI (match_dup 1) (match_dup 2)))] |
4387 | "s390_match_ccmode(insn, CCTmode)" | |
4388 | "@ | |
4389 | nr\\t%0,%2 | |
8b4a4127 | 4390 | n\\t%0,%2" |
4391 | [(set_attr "op_type" "RR,RX") | |
4392 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 4393 | |
4394 | (define_insn "*andsi3_cconly" | |
4395 | [(set (reg 33) | |
7c3aefa0 | 4396 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4397 | (match_operand:SI 2 "general_operand" "d,m")) |
4673c1a0 | 4398 | (const_int 0))) |
4399 | (clobber (match_scratch:SI 0 "=d,d"))] | |
4400 | "s390_match_ccmode(insn, CCTmode)" | |
4401 | "@ | |
4402 | nr\\t%0,%2 | |
4403 | n\\t%0,%2" | |
4404 | [(set_attr "op_type" "RR,RX") | |
369293ed | 4405 | (set_attr "atype" "reg,mem")]) |
4673c1a0 | 4406 | |
8b4a4127 | 4407 | (define_insn "*andsi3_ni" |
4408 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2e5d1042 | 4409 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
8b4a4127 | 4410 | (match_operand:SI 2 "immediate_operand" "n"))) |
4411 | (clobber (reg:CC 33))] | |
4412 | "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0" | |
4413 | "* | |
4414 | { | |
4415 | int part = s390_single_hi (operands[2], SImode, -1); | |
4416 | operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); | |
4417 | ||
4418 | switch (part) | |
4419 | { | |
4420 | case 0: return \"nilh\\t%0,%x2\"; | |
4421 | case 1: return \"nill\\t%0,%x2\"; | |
4422 | default: abort (); | |
4423 | } | |
4424 | }" | |
4425 | [(set_attr "op_type" "RI") | |
4426 | (set_attr "atype" "reg")]) | |
4427 | ||
4673c1a0 | 4428 | (define_insn "andsi3" |
8b4a4127 | 4429 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7c3aefa0 | 4430 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4431 | (match_operand:SI 2 "general_operand" "d,m"))) |
4673c1a0 | 4432 | (clobber (reg:CC 33))] |
4433 | "" | |
4434 | "@ | |
4435 | nr\\t%0,%2 | |
8b4a4127 | 4436 | n\\t%0,%2" |
4437 | [(set_attr "op_type" "RR,RX") | |
4438 | (set_attr "atype" "reg,mem")]) | |
4439 | ||
4440 | (define_insn "*andsi3_ss" | |
a5004c3d | 4441 | [(set (match_operand:SI 0 "s_operand" "=Q") |
8b4a4127 | 4442 | (and:SI (match_dup 0) |
a5004c3d | 4443 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4444 | (clobber (reg:CC 33))] |
4445 | "" | |
4446 | "nc\\t%O0(4,%R0),%1" | |
4447 | [(set_attr "op_type" "SS") | |
4448 | (set_attr "atype" "mem")]) | |
4449 | ||
4450 | (define_insn "*andsi3_ss_inv" | |
a5004c3d | 4451 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4452 | (and:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4453 | (match_dup 0))) |
4454 | (clobber (reg:CC 33))] | |
4455 | "" | |
4456 | "nc\\t%O0(4,%R0),%1" | |
4457 | [(set_attr "op_type" "SS") | |
4458 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4459 | |
4460 | ; | |
4461 | ; andhi3 instruction pattern(s). | |
4462 | ; | |
4463 | ||
8b4a4127 | 4464 | (define_insn "*andhi3_ni" |
4465 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
4466 | (and:HI (match_operand:HI 1 "register_operand" "%0,0") | |
4467 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
4468 | (clobber (reg:CC 33))] | |
4469 | "TARGET_64BIT" | |
4470 | "@ | |
4471 | nr\\t%0,%2 | |
4472 | nill\\t%0,%x2" | |
4473 | [(set_attr "op_type" "RR,RI") | |
4474 | (set_attr "atype" "reg")]) | |
4475 | ||
4476 | (define_insn "andhi3" | |
4477 | [(set (match_operand:HI 0 "register_operand" "=d") | |
4478 | (and:HI (match_operand:HI 1 "register_operand" "%0") | |
4479 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
4480 | (clobber (reg:CC 33))] | |
4673c1a0 | 4481 | "" |
8b4a4127 | 4482 | "nr\\t%0,%2" |
4483 | [(set_attr "op_type" "RR") | |
4484 | (set_attr "atype" "reg")]) | |
4485 | ||
4486 | (define_insn "*andhi3_ss" | |
a5004c3d | 4487 | [(set (match_operand:HI 0 "s_operand" "=Q") |
8b4a4127 | 4488 | (and:HI (match_dup 0) |
a5004c3d | 4489 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4490 | (clobber (reg:CC 33))] |
4491 | "" | |
4492 | "nc\\t%O0(2,%R0),%1" | |
4493 | [(set_attr "op_type" "SS") | |
4494 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4495 | |
8b4a4127 | 4496 | (define_insn "*andhi3_ss_inv" |
a5004c3d | 4497 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4498 | (and:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4499 | (match_dup 0))) |
4673c1a0 | 4500 | (clobber (reg:CC 33))] |
4501 | "" | |
8b4a4127 | 4502 | "nc\\t%O0(2,%R0),%1" |
4503 | [(set_attr "op_type" "SS") | |
4504 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4505 | |
4506 | ; | |
4507 | ; andqi3 instruction pattern(s). | |
4508 | ; | |
4509 | ||
8b4a4127 | 4510 | (define_insn "*andqi3_ni" |
4511 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
4512 | (and:QI (match_operand:QI 1 "register_operand" "%0,0") | |
4513 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
4514 | (clobber (reg:CC 33))] | |
4515 | "TARGET_64BIT" | |
4516 | "@ | |
4517 | nr\\t%0,%2 | |
4518 | nill\\t%0,%b2" | |
4519 | [(set_attr "op_type" "RR,RI") | |
4520 | (set_attr "atype" "reg")]) | |
4521 | ||
4673c1a0 | 4522 | (define_insn "andqi3" |
8b4a4127 | 4523 | [(set (match_operand:QI 0 "register_operand" "=d") |
4524 | (and:QI (match_operand:QI 1 "register_operand" "%0") | |
4525 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
4526 | (clobber (reg:CC 33))] | |
4527 | "" | |
4528 | "nr\\t%0,%2" | |
4529 | [(set_attr "op_type" "RR") | |
4530 | (set_attr "atype" "reg")]) | |
4531 | ||
4532 | (define_insn "*andqi3_ss" | |
a5004c3d | 4533 | [(set (match_operand:QI 0 "s_operand" "=Q,Q") |
8b4a4127 | 4534 | (and:QI (match_dup 0) |
a5004c3d | 4535 | (match_operand:QI 1 "s_imm_operand" "n,Q"))) |
4673c1a0 | 4536 | (clobber (reg:CC 33))] |
4537 | "" | |
4538 | "@ | |
8b4a4127 | 4539 | ni\\t%0,%b1 |
4540 | nc\\t%O0(1,%R0),%1" | |
4541 | [(set_attr "op_type" "SI,SS") | |
4542 | (set_attr "atype" "mem")]) | |
4543 | ||
4544 | (define_insn "*andqi3_ss_inv" | |
a5004c3d | 4545 | [(set (match_operand:QI 0 "s_operand" "=Q,Q") |
4546 | (and:QI (match_operand:QI 1 "s_imm_operand" "n,Q") | |
8b4a4127 | 4547 | (match_dup 0))) |
4548 | (clobber (reg:CC 33))] | |
4549 | "" | |
4550 | "@ | |
4551 | ni\\t%0,%b1 | |
4552 | nc\\t%O0(1,%R0),%1" | |
4553 | [(set_attr "op_type" "SI,SS") | |
4554 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4555 | |
4556 | ||
4557 | ;; | |
4558 | ;;- Bit set (inclusive or) instructions. | |
4559 | ;; | |
4560 | ||
4561 | ; | |
4562 | ; iordi3 instruction pattern(s). | |
4563 | ; | |
4564 | ||
8b4a4127 | 4565 | (define_insn "*iordi3_cc" |
4566 | [(set (reg 33) | |
7c3aefa0 | 4567 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4568 | (match_operand:DI 2 "general_operand" "d,m")) |
4569 | (const_int 0))) | |
4570 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4571 | (ior:DI (match_dup 1) (match_dup 2)))] | |
4572 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4573 | "@ | |
4574 | ogr\\t%0,%2 | |
4575 | og\\t%0,%2" | |
4576 | [(set_attr "op_type" "RRE,RXE") | |
4577 | (set_attr "atype" "reg,mem")]) | |
4578 | ||
4579 | (define_insn "*iordi3_cconly" | |
4580 | [(set (reg 33) | |
7c3aefa0 | 4581 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4582 | (match_operand:DI 2 "general_operand" "d,m")) |
4583 | (const_int 0))) | |
4584 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4585 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4586 | "@ | |
4587 | ogr\\t%0,%2 | |
4588 | og\\t%0,%2" | |
4589 | [(set_attr "op_type" "RRE,RXE") | |
4590 | (set_attr "atype" "reg,mem")]) | |
4591 | ||
4592 | (define_insn "*iordi3_oi" | |
4593 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2e5d1042 | 4594 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
8b4a4127 | 4595 | (match_operand:DI 2 "immediate_operand" "n"))) |
4596 | (clobber (reg:CC 33))] | |
4597 | "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0" | |
4598 | "* | |
4599 | { | |
4600 | int part = s390_single_hi (operands[2], DImode, 0); | |
4601 | operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); | |
4602 | ||
4603 | switch (part) | |
4604 | { | |
4605 | case 0: return \"oihh\\t%0,%x2\"; | |
4606 | case 1: return \"oihl\\t%0,%x2\"; | |
4607 | case 2: return \"oilh\\t%0,%x2\"; | |
4608 | case 3: return \"oill\\t%0,%x2\"; | |
4609 | default: abort (); | |
4610 | } | |
4611 | }" | |
4612 | [(set_attr "op_type" "RI") | |
4613 | (set_attr "atype" "reg")]) | |
4614 | ||
4673c1a0 | 4615 | (define_insn "iordi3" |
8b4a4127 | 4616 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
7c3aefa0 | 4617 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4618 | (match_operand:DI 2 "general_operand" "d,m"))) |
4673c1a0 | 4619 | (clobber (reg:CC 33))] |
4620 | "TARGET_64BIT" | |
4621 | "@ | |
4622 | ogr\\t%0,%2 | |
8b4a4127 | 4623 | og\\t%0,%2" |
4624 | [(set_attr "op_type" "RRE,RXE") | |
4625 | (set_attr "atype" "reg,mem")]) | |
4626 | ||
4627 | (define_insn "*iordi3_ss" | |
a5004c3d | 4628 | [(set (match_operand:DI 0 "s_operand" "=Q") |
8b4a4127 | 4629 | (ior:DI (match_dup 0) |
a5004c3d | 4630 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4631 | (clobber (reg:CC 33))] |
4632 | "" | |
4633 | "oc\\t%O0(8,%R0),%1" | |
4634 | [(set_attr "op_type" "SS") | |
4635 | (set_attr "atype" "mem")]) | |
4636 | ||
4637 | (define_insn "*iordi3_ss_inv" | |
a5004c3d | 4638 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4639 | (ior:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4640 | (match_dup 0))) |
4641 | (clobber (reg:CC 33))] | |
4642 | "" | |
4643 | "oc\\t%O0(8,%R0),%1" | |
4644 | [(set_attr "op_type" "SS") | |
4645 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4646 | |
4647 | ; | |
4648 | ; iorsi3 instruction pattern(s). | |
4649 | ; | |
4650 | ||
8b4a4127 | 4651 | (define_insn "*iorsi3_cc" |
4652 | [(set (reg 33) | |
7c3aefa0 | 4653 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4654 | (match_operand:SI 2 "general_operand" "d,m")) |
4655 | (const_int 0))) | |
4656 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4657 | (ior:SI (match_dup 1) (match_dup 2)))] | |
4658 | "s390_match_ccmode(insn, CCTmode)" | |
4659 | "@ | |
4660 | or\\t%0,%2 | |
4661 | o\\t%0,%2" | |
4662 | [(set_attr "op_type" "RR,RX") | |
4663 | (set_attr "atype" "reg,mem")]) | |
4664 | ||
4665 | (define_insn "*iorsi3_cconly" | |
4666 | [(set (reg 33) | |
7c3aefa0 | 4667 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4668 | (match_operand:SI 2 "general_operand" "d,m")) |
4669 | (const_int 0))) | |
4670 | (clobber (match_scratch:SI 0 "=d,d"))] | |
4671 | "s390_match_ccmode(insn, CCTmode)" | |
4672 | "@ | |
4673 | or\\t%0,%2 | |
4674 | o\\t%0,%2" | |
4675 | [(set_attr "op_type" "RR,RX") | |
4676 | (set_attr "atype" "reg,mem")]) | |
4677 | ||
4678 | (define_insn "*iorsi3_oi" | |
4679 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2e5d1042 | 4680 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0") |
8b4a4127 | 4681 | (match_operand:SI 2 "immediate_operand" "n"))) |
4682 | (clobber (reg:CC 33))] | |
4683 | "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0" | |
4684 | "* | |
4685 | { | |
4686 | int part = s390_single_hi (operands[2], SImode, 0); | |
4687 | operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); | |
4688 | ||
4689 | switch (part) | |
4690 | { | |
4691 | case 0: return \"oilh\\t%0,%x2\"; | |
4692 | case 1: return \"oill\\t%0,%x2\"; | |
4693 | default: abort (); | |
4694 | } | |
4695 | }" | |
4696 | [(set_attr "op_type" "RI") | |
4697 | (set_attr "atype" "reg")]) | |
4698 | ||
4699 | (define_insn "iorsi3" | |
4700 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
7c3aefa0 | 4701 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4702 | (match_operand:SI 2 "general_operand" "d,m"))) |
4703 | (clobber (reg:CC 33))] | |
4704 | "" | |
4705 | "@ | |
4706 | or\\t%0,%2 | |
4707 | o\\t%0,%2" | |
4708 | [(set_attr "op_type" "RR,RX") | |
4709 | (set_attr "atype" "reg,mem")]) | |
4710 | ||
4711 | (define_insn "*iorsi3_ss" | |
a5004c3d | 4712 | [(set (match_operand:SI 0 "s_operand" "=Q") |
8b4a4127 | 4713 | (ior:SI (match_dup 0) |
a5004c3d | 4714 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4715 | (clobber (reg:CC 33))] |
4716 | "" | |
4717 | "oc\\t%O0(4,%R0),%1" | |
4718 | [(set_attr "op_type" "SS") | |
4719 | (set_attr "atype" "mem")]) | |
4720 | ||
4721 | (define_insn "*iorsi3_ss_inv" | |
a5004c3d | 4722 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4723 | (ior:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4724 | (match_dup 0))) |
4725 | (clobber (reg:CC 33))] | |
4726 | "" | |
4727 | "oc\\t%O0(4,%R0),%1" | |
4728 | [(set_attr "op_type" "SS") | |
4729 | (set_attr "atype" "mem")]) | |
4730 | ||
4731 | ; | |
4732 | ; iorhi3 instruction pattern(s). | |
4733 | ; | |
4734 | ||
4735 | (define_insn "*iorhi3_oi" | |
4736 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
4737 | (ior:HI (match_operand:HI 1 "register_operand" "%0,0") | |
4738 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
4739 | (clobber (reg:CC 33))] | |
4740 | "TARGET_64BIT" | |
4741 | "@ | |
4742 | or\\t%0,%2 | |
4743 | oill\\t%0,%x2" | |
4744 | [(set_attr "op_type" "RR,RI") | |
4745 | (set_attr "atype" "reg")]) | |
4746 | ||
4747 | (define_insn "iorhi3" | |
4748 | [(set (match_operand:HI 0 "register_operand" "=d") | |
4749 | (ior:HI (match_operand:HI 1 "register_operand" "%0") | |
4750 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
4751 | (clobber (reg:CC 33))] | |
4673c1a0 | 4752 | "" |
8b4a4127 | 4753 | "or\\t%0,%2" |
4754 | [(set_attr "op_type" "RR") | |
4755 | (set_attr "atype" "reg")]) | |
4756 | ||
4757 | (define_insn "*iorhi3_ss" | |
a5004c3d | 4758 | [(set (match_operand:HI 0 "s_operand" "=Q") |
8b4a4127 | 4759 | (ior:HI (match_dup 0) |
a5004c3d | 4760 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4761 | (clobber (reg:CC 33))] |
4762 | "" | |
4763 | "oc\\t%O0(2,%R0),%1" | |
4764 | [(set_attr "op_type" "SS") | |
4765 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4766 | |
8b4a4127 | 4767 | (define_insn "*iorhi3_ss_inv" |
a5004c3d | 4768 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4769 | (ior:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4770 | (match_dup 0))) |
4673c1a0 | 4771 | (clobber (reg:CC 33))] |
4772 | "" | |
8b4a4127 | 4773 | "oc\\t%O0(2,%R0),%1" |
4774 | [(set_attr "op_type" "SS") | |
4775 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4776 | |
4777 | ; | |
8b4a4127 | 4778 | ; iorqi3 instruction pattern(s). |
4673c1a0 | 4779 | ; |
4780 | ||
8b4a4127 | 4781 | (define_insn "*iorqi3_oi" |
4782 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
4783 | (ior:QI (match_operand:QI 1 "register_operand" "%0,0") | |
4784 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
4785 | (clobber (reg:CC 33))] | |
4786 | "TARGET_64BIT" | |
4787 | "@ | |
4788 | or\\t%0,%2 | |
4789 | oill\\t%0,%b2" | |
4790 | [(set_attr "op_type" "RR,RI") | |
4791 | (set_attr "atype" "reg")]) | |
4673c1a0 | 4792 | |
8b4a4127 | 4793 | (define_insn "iorqi3" |
4794 | [(set (match_operand:QI 0 "register_operand" "=d") | |
4795 | (ior:QI (match_operand:QI 1 "register_operand" "%0") | |
4796 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
4797 | (clobber (reg:CC 33))] | |
4798 | "" | |
4799 | "or\\t%0,%2" | |
4800 | [(set_attr "op_type" "RR") | |
4801 | (set_attr "atype" "reg")]) | |
4802 | ||
4803 | (define_insn "*iorqi3_ss" | |
a5004c3d | 4804 | [(set (match_operand:QI 0 "s_operand" "=Q,Q") |
8b4a4127 | 4805 | (ior:QI (match_dup 0) |
a5004c3d | 4806 | (match_operand:QI 1 "s_imm_operand" "n,Q"))) |
4673c1a0 | 4807 | (clobber (reg:CC 33))] |
4808 | "" | |
4809 | "@ | |
8b4a4127 | 4810 | oi\\t%0,%b1 |
4811 | oc\\t%O0(1,%R0),%1" | |
4812 | [(set_attr "op_type" "SI,SS") | |
4673c1a0 | 4813 | (set_attr "atype" "reg,mem")]) |
4814 | ||
8b4a4127 | 4815 | (define_insn "*iorqi3_ss_inv" |
a5004c3d | 4816 | [(set (match_operand:QI 0 "s_operand" "=Q,Q") |
4817 | (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Q") | |
8b4a4127 | 4818 | (match_dup 0))) |
4673c1a0 | 4819 | (clobber (reg:CC 33))] |
4820 | "" | |
4821 | "@ | |
8b4a4127 | 4822 | oi\\t%0,%b1 |
4823 | oc\\t%O0(1,%R0),%1" | |
4824 | [(set_attr "op_type" "SI,SS") | |
4825 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 4826 | |
4827 | ||
4828 | ;; | |
4829 | ;;- Xor instructions. | |
4830 | ;; | |
4831 | ||
4832 | ; | |
4833 | ; xordi3 instruction pattern(s). | |
4834 | ; | |
4835 | ||
8b4a4127 | 4836 | (define_insn "*xordi3_cc" |
4837 | [(set (reg 33) | |
7c3aefa0 | 4838 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4839 | (match_operand:DI 2 "general_operand" "d,m")) |
4840 | (const_int 0))) | |
4841 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4842 | (xor:DI (match_dup 1) (match_dup 2)))] | |
4843 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4844 | "@ | |
4845 | xgr\\t%0,%2 | |
4846 | xg\\t%0,%2" | |
4847 | [(set_attr "op_type" "RRE,RXE") | |
4848 | (set_attr "atype" "reg,mem")]) | |
4849 | ||
4850 | (define_insn "*xordi3_cconly" | |
4851 | [(set (reg 33) | |
7c3aefa0 | 4852 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4853 | (match_operand:DI 2 "general_operand" "d,m")) |
4854 | (const_int 0))) | |
4855 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4856 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4857 | "@ | |
4858 | xgr\\t%0,%2 | |
4859 | xr\\t%0,%2" | |
4860 | [(set_attr "op_type" "RRE,RXE") | |
4861 | (set_attr "atype" "reg,mem")]) | |
4862 | ||
4673c1a0 | 4863 | (define_insn "xordi3" |
8b4a4127 | 4864 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
7c3aefa0 | 4865 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4866 | (match_operand:DI 2 "general_operand" "d,m"))) |
4673c1a0 | 4867 | (clobber (reg:CC 33))] |
4868 | "TARGET_64BIT" | |
4869 | "@ | |
4870 | xgr\\t%0,%2 | |
8b4a4127 | 4871 | xg\\t%0,%2" |
4872 | [(set_attr "op_type" "RRE,RXE") | |
4873 | (set_attr "atype" "reg,mem")]) | |
4874 | ||
4875 | (define_insn "*xordi3_ss" | |
a5004c3d | 4876 | [(set (match_operand:DI 0 "s_operand" "=Q") |
8b4a4127 | 4877 | (xor:DI (match_dup 0) |
a5004c3d | 4878 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4879 | (clobber (reg:CC 33))] |
4880 | "" | |
4881 | "xc\\t%O0(8,%R0),%1" | |
4882 | [(set_attr "op_type" "SS") | |
4883 | (set_attr "atype" "mem")]) | |
4884 | ||
4885 | (define_insn "*xordi3_ss_inv" | |
a5004c3d | 4886 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4887 | (xor:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4888 | (match_dup 0))) |
4889 | (clobber (reg:CC 33))] | |
4890 | "" | |
4891 | "xc\\t%O0(8,%R0),%1" | |
4892 | [(set_attr "op_type" "SS") | |
4893 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4894 | |
4895 | ; | |
4896 | ; xorsi3 instruction pattern(s). | |
4897 | ; | |
4898 | ||
8b4a4127 | 4899 | (define_insn "*xorsi3_cc" |
4900 | [(set (reg 33) | |
7c3aefa0 | 4901 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4902 | (match_operand:SI 2 "general_operand" "d,m")) |
4903 | (const_int 0))) | |
4904 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4905 | (xor:SI (match_dup 1) (match_dup 2)))] | |
4906 | "s390_match_ccmode(insn, CCTmode)" | |
4907 | "@ | |
4908 | xr\\t%0,%2 | |
4909 | x\\t%0,%2" | |
4910 | [(set_attr "op_type" "RR,RX") | |
4911 | (set_attr "atype" "reg,mem")]) | |
4912 | ||
4913 | (define_insn "*xorsi3_cconly" | |
4914 | [(set (reg 33) | |
7c3aefa0 | 4915 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4916 | (match_operand:SI 2 "general_operand" "d,m")) |
4917 | (const_int 0))) | |
4918 | (clobber (match_scratch:SI 0 "=d,d"))] | |
4919 | "s390_match_ccmode(insn, CCTmode)" | |
4920 | "@ | |
4921 | xr\\t%0,%2 | |
4922 | x\\t%0,%2" | |
4923 | [(set_attr "op_type" "RR,RX") | |
4924 | (set_attr "atype" "reg,mem")]) | |
4673c1a0 | 4925 | |
8b4a4127 | 4926 | (define_insn "xorsi3" |
4927 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
7c3aefa0 | 4928 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") |
8b4a4127 | 4929 | (match_operand:SI 2 "general_operand" "d,m"))) |
4673c1a0 | 4930 | (clobber (reg:CC 33))] |
4931 | "" | |
4932 | "@ | |
4933 | xr\\t%0,%2 | |
8b4a4127 | 4934 | x\\t%0,%2" |
4935 | [(set_attr "op_type" "RR,RX") | |
4936 | (set_attr "atype" "reg,mem")]) | |
4937 | ||
4938 | (define_insn "*xorsi3_ss" | |
a5004c3d | 4939 | [(set (match_operand:SI 0 "s_operand" "=Q") |
8b4a4127 | 4940 | (xor:SI (match_dup 0) |
a5004c3d | 4941 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4942 | (clobber (reg:CC 33))] |
4943 | "" | |
4944 | "xc\\t%O0(4,%R0),%1" | |
4945 | [(set_attr "op_type" "SS") | |
4946 | (set_attr "atype" "mem")]) | |
4947 | ||
4948 | (define_insn "*xorsi3_ss_inv" | |
a5004c3d | 4949 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4950 | (xor:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4951 | (match_dup 0))) |
4952 | (clobber (reg:CC 33))] | |
4953 | "" | |
4954 | "xc\\t%O0(4,%R0),%1" | |
4955 | [(set_attr "op_type" "SS") | |
4956 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4957 | |
4958 | ; | |
4959 | ; xorhi3 instruction pattern(s). | |
4960 | ; | |
4961 | ||
8b4a4127 | 4962 | (define_insn "xorhi3" |
4963 | [(set (match_operand:HI 0 "register_operand" "=d") | |
4964 | (xor:HI (match_operand:HI 1 "register_operand" "%0") | |
4965 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
4966 | (clobber (reg:CC 33))] | |
4673c1a0 | 4967 | "" |
8b4a4127 | 4968 | "xr\\t%0,%2" |
4969 | [(set_attr "op_type" "RR") | |
4970 | (set_attr "atype" "reg")]) | |
4971 | ||
4972 | (define_insn "*xorhi3_ss" | |
a5004c3d | 4973 | [(set (match_operand:HI 0 "s_operand" "=Q") |
8b4a4127 | 4974 | (xor:HI (match_dup 0) |
a5004c3d | 4975 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
8b4a4127 | 4976 | (clobber (reg:CC 33))] |
4977 | "" | |
4978 | "xc\\t%O0(2,%R0),%1" | |
4979 | [(set_attr "op_type" "SS") | |
4980 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4981 | |
8b4a4127 | 4982 | (define_insn "*xorhi3_ss_inv" |
a5004c3d | 4983 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4984 | (xor:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
8b4a4127 | 4985 | (match_dup 0))) |
4673c1a0 | 4986 | (clobber (reg:CC 33))] |
4987 | "" | |
8b4a4127 | 4988 | "xc\\t%O0(2,%R0),%1" |
4989 | [(set_attr "op_type" "SS") | |
4990 | (set_attr "atype" "mem")]) | |
4673c1a0 | 4991 | |
4992 | ; | |
4993 | ; xorqi3 instruction pattern(s). | |
4994 | ; | |
4995 | ||
4996 | (define_insn "xorqi3" | |
8b4a4127 | 4997 | [(set (match_operand:QI 0 "register_operand" "=d") |
4998 | (xor:QI (match_operand:QI 1 "register_operand" "%0") | |
4999 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5000 | (clobber (reg:CC 33))] | |
5001 | "" | |
5002 | "xr\\t%0,%2" | |
5003 | [(set_attr "op_type" "RR") | |
5004 | (set_attr "atype" "reg")]) | |
5005 | ||
5006 | (define_insn "*xorqi3_ss" | |
a5004c3d | 5007 | [(set (match_operand:QI 0 "s_operand" "=Q,Q") |
8b4a4127 | 5008 | (xor:QI (match_dup 0) |
a5004c3d | 5009 | (match_operand:QI 1 "s_imm_operand" "n,Q"))) |
4673c1a0 | 5010 | (clobber (reg:CC 33))] |
5011 | "" | |
5012 | "@ | |
8b4a4127 | 5013 | xi\\t%0,%b1 |
5014 | xc\\t%O0(1,%R0),%1" | |
5015 | [(set_attr "op_type" "SI,SS") | |
5016 | (set_attr "atype" "mem")]) | |
5017 | ||
5018 | (define_insn "*xorqi3_ss_inv" | |
a5004c3d | 5019 | [(set (match_operand:QI 0 "s_operand" "=Q,Q") |
5020 | (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Q") | |
8b4a4127 | 5021 | (match_dup 0))) |
5022 | (clobber (reg:CC 33))] | |
5023 | "" | |
5024 | "@ | |
5025 | xi\\t%0,%b1 | |
5026 | xc\\t%O0(1,%R0),%1" | |
5027 | [(set_attr "op_type" "SI,SS") | |
5028 | (set_attr "atype" "mem")]) | |
4673c1a0 | 5029 | |
5030 | ||
5031 | ;; | |
5032 | ;;- Negate instructions. | |
5033 | ;; | |
5034 | ||
5035 | ; | |
5036 | ; negdi2 instruction pattern(s). | |
5037 | ; | |
5038 | ||
5039 | (define_expand "negdi2" | |
5040 | [(parallel | |
5041 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5042 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5043 | (clobber (reg:CC 33))])] | |
5044 | "" | |
5045 | "") | |
5046 | ||
5047 | (define_insn "*negdi2_64" | |
5048 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5049 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5050 | (clobber (reg:CC 33))] | |
5051 | "TARGET_64BIT" | |
5052 | "lcgr\\t%0,%1" | |
369293ed | 5053 | [(set_attr "op_type" "RR")]) |
4673c1a0 | 5054 | |
5055 | (define_insn "*negdi2_31" | |
5056 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5057 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5058 | (clobber (reg:CC 33))] | |
5059 | "!TARGET_64BIT" | |
5060 | "* | |
5061 | { | |
5062 | rtx xop[1]; | |
5063 | xop[0] = gen_label_rtx (); | |
5064 | output_asm_insn (\"lcr\\t%0,%1\", operands); | |
5065 | output_asm_insn (\"lcr\\t%N0,%N1\", operands); | |
5066 | output_asm_insn (\"je\\t%l0\", xop); | |
5067 | output_asm_insn (\"bctr\\t%0,0\", operands); | |
805e22b2 | 5068 | (*targetm.asm_out.internal_label) (asm_out_file, \"L\", |
4673c1a0 | 5069 | CODE_LABEL_NUMBER (xop[0])); |
5070 | return \"\"; | |
5071 | }" | |
5072 | [(set_attr "op_type" "NN") | |
8b4a4127 | 5073 | (set_attr "type" "other") |
5074 | (set_attr "length" "10")]) | |
4673c1a0 | 5075 | |
5076 | ; | |
5077 | ; negsi2 instruction pattern(s). | |
5078 | ; | |
5079 | ||
5080 | (define_insn "negsi2" | |
5081 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5082 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
5083 | (clobber (reg:CC 33))] | |
5084 | "" | |
5085 | "lcr\\t%0,%1" | |
369293ed | 5086 | [(set_attr "op_type" "RR")]) |
4673c1a0 | 5087 | |
5088 | ; | |
5089 | ; negdf2 instruction pattern(s). | |
5090 | ; | |
5091 | ||
5092 | (define_expand "negdf2" | |
5093 | [(parallel | |
5094 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5095 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5096 | (clobber (reg:CC 33))])] | |
5097 | "TARGET_HARD_FLOAT" | |
5098 | "") | |
5099 | ||
5100 | (define_insn "*negdf2" | |
5101 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5102 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5103 | (clobber (reg:CC 33))] | |
5104 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5105 | "lcdbr\\t%0,%1" | |
9fa6d5d9 | 5106 | [(set_attr "op_type" "RRE")]) |
4673c1a0 | 5107 | |
5108 | (define_insn "*negdf2_ibm" | |
5109 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5110 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5111 | (clobber (reg:CC 33))] | |
5112 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
5113 | "lcdr\\t%0,%1" | |
5114 | [(set_attr "op_type" "RR")]) | |
5115 | ||
5116 | ; | |
5117 | ; negsf2 instruction pattern(s). | |
5118 | ; | |
5119 | ||
5120 | (define_expand "negsf2" | |
5121 | [(parallel | |
5122 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5123 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5124 | (clobber (reg:CC 33))])] | |
5125 | "TARGET_HARD_FLOAT" | |
5126 | "") | |
5127 | ||
5128 | (define_insn "*negsf2" | |
5129 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5130 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5131 | (clobber (reg:CC 33))] | |
5132 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5133 | "lcebr\\t%0,%1" | |
9fa6d5d9 | 5134 | [(set_attr "op_type" "RRE")]) |
4673c1a0 | 5135 | |
5136 | (define_insn "*negsf2" | |
5137 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5138 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5139 | (clobber (reg:CC 33))] | |
5140 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
5141 | "lcer\\t%0,%1" | |
5142 | [(set_attr "op_type" "RR")]) | |
5143 | ||
5144 | ||
5145 | ;; | |
5146 | ;;- Absolute value instructions. | |
5147 | ;; | |
5148 | ||
5149 | ; | |
5150 | ; absdi2 instruction pattern(s). | |
5151 | ; | |
5152 | ||
5153 | (define_insn "absdi2" | |
5154 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5155 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
5156 | (clobber (reg:CC 33))] | |
5157 | "TARGET_64BIT" | |
5158 | "lpgr\\t%0,%1" | |
369293ed | 5159 | [(set_attr "op_type" "RRE")]) |
4673c1a0 | 5160 | |
5161 | ; | |
5162 | ; abssi2 instruction pattern(s). | |
5163 | ; | |
5164 | ||
5165 | (define_insn "abssi2" | |
5166 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5167 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
5168 | (clobber (reg:CC 33))] | |
5169 | "" | |
5170 | "lpr\\t%0,%1" | |
369293ed | 5171 | [(set_attr "op_type" "RR")]) |
4673c1a0 | 5172 | |
4673c1a0 | 5173 | ; |
5174 | ; absdf2 instruction pattern(s). | |
5175 | ; | |
5176 | ||
5177 | (define_expand "absdf2" | |
5178 | [(parallel | |
5179 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5180 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5181 | (clobber (reg:CC 33))])] | |
5182 | "TARGET_HARD_FLOAT" | |
5183 | "") | |
5184 | ||
5185 | (define_insn "*absdf2" | |
5186 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5187 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5188 | (clobber (reg:CC 33))] | |
5189 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5190 | "lpdbr\\t%0,%1" | |
9fa6d5d9 | 5191 | [(set_attr "op_type" "RRE")]) |
4673c1a0 | 5192 | |
5193 | (define_insn "*absdf2_ibm" | |
5194 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5195 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5196 | (clobber (reg:CC 33))] | |
5197 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
5198 | "lpdr\\t%0,%1" | |
5199 | [(set_attr "op_type" "RR")]) | |
5200 | ||
5201 | ; | |
5202 | ; abssf2 instruction pattern(s). | |
5203 | ; | |
5204 | ||
5205 | (define_expand "abssf2" | |
5206 | [(parallel | |
5207 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5208 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5209 | (clobber (reg:CC 33))])] | |
5210 | "TARGET_HARD_FLOAT" | |
5211 | "") | |
5212 | ||
5213 | (define_insn "*abssf2" | |
5214 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5215 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5216 | (clobber (reg:CC 33))] | |
5217 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5218 | "lpebr\\t%0,%1" | |
9fa6d5d9 | 5219 | [(set_attr "op_type" "RRE")]) |
4673c1a0 | 5220 | |
5221 | (define_insn "*abssf2_ibm" | |
5222 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5223 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5224 | (clobber (reg:CC 33))] | |
5225 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
5226 | "lper\\t%0,%1" | |
5227 | [(set_attr "op_type" "RR")]) | |
5228 | ||
8b4a4127 | 5229 | ;; |
5230 | ;;- Square root instructions. | |
5231 | ;; | |
5232 | ||
5233 | ; | |
5234 | ; sqrtdf2 instruction pattern(s). | |
5235 | ; | |
5236 | ||
5237 | (define_insn "sqrtdf2" | |
5238 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
5239 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))] | |
5240 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5241 | "@ | |
5242 | sqdbr\\t%0,%1 | |
5243 | sqdb\\t%0,%1" | |
5244 | [(set_attr "op_type" "RRE,RSE")]) | |
5245 | ||
5246 | ; | |
5247 | ; sqrtsf2 instruction pattern(s). | |
5248 | ; | |
5249 | ||
5250 | (define_insn "sqrtsf2" | |
5251 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
5252 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))] | |
5253 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5254 | "@ | |
5255 | sqebr\\t%0,%1 | |
5256 | sqeb\\t%0,%1" | |
5257 | [(set_attr "op_type" "RRE,RSE")]) | |
4673c1a0 | 5258 | |
5259 | ;; | |
5260 | ;;- One complement instructions. | |
5261 | ;; | |
5262 | ||
5263 | ; | |
5264 | ; one_cmpldi2 instruction pattern(s). | |
5265 | ; | |
8b4a4127 | 5266 | |
4673c1a0 | 5267 | (define_expand "one_cmpldi2" |
5268 | [(parallel | |
8b4a4127 | 5269 | [(set (match_operand:DI 0 "register_operand" "") |
5270 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
5271 | (const_int -1))) | |
4673c1a0 | 5272 | (clobber (reg:CC 33))])] |
5273 | "TARGET_64BIT" | |
8b4a4127 | 5274 | "") |
5275 | ||
4673c1a0 | 5276 | ; |
5277 | ; one_cmplsi2 instruction pattern(s). | |
5278 | ; | |
8b4a4127 | 5279 | |
4673c1a0 | 5280 | (define_expand "one_cmplsi2" |
5281 | [(parallel | |
8b4a4127 | 5282 | [(set (match_operand:SI 0 "register_operand" "") |
5283 | (xor:SI (match_operand:SI 1 "register_operand" "") | |
5284 | (const_int -1))) | |
4673c1a0 | 5285 | (clobber (reg:CC 33))])] |
5286 | "" | |
8b4a4127 | 5287 | "") |
5288 | ||
4673c1a0 | 5289 | ; |
5290 | ; one_cmplhi2 instruction pattern(s). | |
5291 | ; | |
8b4a4127 | 5292 | |
4673c1a0 | 5293 | (define_expand "one_cmplhi2" |
5294 | [(parallel | |
8b4a4127 | 5295 | [(set (match_operand:HI 0 "register_operand" "") |
5296 | (xor:HI (match_operand:HI 1 "register_operand" "") | |
5297 | (const_int -1))) | |
4673c1a0 | 5298 | (clobber (reg:CC 33))])] |
5299 | "" | |
8b4a4127 | 5300 | "") |
5301 | ||
4673c1a0 | 5302 | ; |
5303 | ; one_cmplqi2 instruction pattern(s). | |
5304 | ; | |
8b4a4127 | 5305 | |
5306 | (define_expand "one_cmplqi2" | |
5307 | [(parallel | |
5308 | [(set (match_operand:QI 0 "register_operand" "") | |
5309 | (xor:QI (match_operand:QI 1 "register_operand" "") | |
5310 | (const_int -1))) | |
5311 | (clobber (reg:CC 33))])] | |
4673c1a0 | 5312 | "" |
8b4a4127 | 5313 | "") |
4673c1a0 | 5314 | |
5315 | ||
5316 | ;; | |
5317 | ;;- Rotate instructions. | |
5318 | ;; | |
5319 | ||
5320 | ; | |
5321 | ; rotldi3 instruction pattern(s). | |
5322 | ; | |
5323 | ||
5324 | (define_insn "rotldi3" | |
5325 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5326 | (rotate:DI (match_operand:DI 1 "register_operand" "d,d") | |
66a63c5b | 5327 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
4673c1a0 | 5328 | "TARGET_64BIT" |
5329 | "@ | |
5330 | rllg\\t%0,%1,%c2 | |
5331 | rllg\\t%0,%1,0(%2)" | |
369293ed | 5332 | [(set_attr "op_type" "RSE")]) |
4673c1a0 | 5333 | |
5334 | ; | |
5335 | ; rotlsi3 instruction pattern(s). | |
5336 | ; | |
5337 | ||
5338 | (define_insn "rotlsi3" | |
5339 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5340 | (rotate:SI (match_operand:SI 1 "register_operand" "d,d") | |
66a63c5b | 5341 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
4673c1a0 | 5342 | "TARGET_64BIT" |
5343 | "@ | |
5344 | rll\\t%0,%1,%c2 | |
5345 | rll\\t%0,%1,0(%2)" | |
369293ed | 5346 | [(set_attr "op_type" "RSE")]) |
4673c1a0 | 5347 | |
5348 | ||
5349 | ;; | |
5350 | ;;- Arithmetic shift instructions. | |
5351 | ;; | |
4673c1a0 | 5352 | |
5353 | ; | |
5354 | ; ashldi3 instruction pattern(s). | |
5355 | ; | |
5356 | ||
5357 | (define_expand "ashldi3" | |
66a63c5b | 5358 | [(set (match_operand:DI 0 "register_operand" "") |
5359 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
5360 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
4673c1a0 | 5361 | "" |
5362 | "") | |
5363 | ||
5364 | (define_insn "*ashldi3_31" | |
5365 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5366 | (ashift:DI (match_operand:DI 1 "register_operand" "0,0") | |
66a63c5b | 5367 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
4673c1a0 | 5368 | "!TARGET_64BIT" |
5369 | "@ | |
5370 | sldl\\t%0,%c2 | |
5371 | sldl\\t%0,0(%2)" | |
369293ed | 5372 | [(set_attr "op_type" "RS")]) |
4673c1a0 | 5373 | |
5374 | (define_insn "*ashldi3_64" | |
66a63c5b | 5375 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
4673c1a0 | 5376 | (ashift:DI (match_operand:DI 1 "register_operand" "d,d") |
66a63c5b | 5377 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
4673c1a0 | 5378 | "TARGET_64BIT" |
5379 | "@ | |
5380 | sllg\\t%0,%1,%2 | |
5381 | sllg\\t%0,%1,0(%2)" | |
369293ed | 5382 | [(set_attr "op_type" "RSE")]) |
4673c1a0 | 5383 | |
5384 | ; | |
5385 | ; ashrdi3 instruction pattern(s). | |
5386 | ; | |
5387 | ||
5388 | (define_expand "ashrdi3" | |
5389 | [(parallel | |
5390 | [(set (match_operand:DI 0 "register_operand" "") | |
5391 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
5392 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5393 | (clobber (reg:CC 33))])] | |
5394 | "" | |
5395 | "") | |
5396 | ||
66a63c5b | 5397 | (define_insn "*ashrdi3_cc_31" |
5398 | [(set (reg 33) | |
5399 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
5400 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5401 | (const_int 0))) | |
5402 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5403 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
5404 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
5405 | "@ | |
5406 | srda\\t%0,%c2 | |
5407 | srda\\t%0,0(%2)" | |
5408 | [(set_attr "op_type" "RS")]) | |
5409 | ||
5410 | (define_insn "*ashrdi3_cconly_31" | |
5411 | [(set (reg 33) | |
5412 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
5413 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5414 | (const_int 0))) | |
5415 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5416 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
5417 | "@ | |
5418 | srda\\t%0,%c2 | |
5419 | srda\\t%0,0(%2)" | |
5420 | [(set_attr "op_type" "RS")]) | |
5421 | ||
4673c1a0 | 5422 | (define_insn "*ashrdi3_31" |
5423 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5424 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
5425 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
5426 | (clobber (reg:CC 33))] | |
5427 | "!TARGET_64BIT" | |
5428 | "@ | |
5429 | srda\\t%0,%c2 | |
5430 | srda\\t%0,0(%2)" | |
5431 | [(set_attr "op_type" "RS")]) | |
5432 | ||
66a63c5b | 5433 | (define_insn "*ashrdi3_cc_64" |
5434 | [(set (reg 33) | |
5435 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
5436 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5437 | (const_int 0))) | |
5438 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5439 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
5440 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
5441 | "@ | |
5442 | srag\\t%0,%1,%c2 | |
5443 | srag\\t%0,%1,0(%2)" | |
5444 | [(set_attr "op_type" "RSE")]) | |
5445 | ||
5446 | (define_insn "*ashrdi3_cconly_64" | |
5447 | [(set (reg 33) | |
5448 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
5449 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5450 | (const_int 0))) | |
5451 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5452 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
5453 | "@ | |
5454 | srag\\t%0,%1,%c2 | |
5455 | srag\\t%0,%1,0(%2)" | |
5456 | [(set_attr "op_type" "RSE")]) | |
5457 | ||
4673c1a0 | 5458 | (define_insn "*ashrdi3_64" |
5459 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5460 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
5461 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
5462 | (clobber (reg:CC 33))] | |
5463 | "TARGET_64BIT" | |
5464 | "@ | |
5465 | srag\\t%0,%1,%c2 | |
5466 | srag\\t%0,%1,0(%2)" | |
369293ed | 5467 | [(set_attr "op_type" "RSE")]) |
4673c1a0 | 5468 | |
5469 | ; | |
5470 | ; ashlsi3 instruction pattern(s). | |
5471 | ; | |
4673c1a0 | 5472 | |
5473 | (define_insn "ashlsi3" | |
5474 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5475 | (ashift:SI (match_operand:SI 1 "register_operand" "0,0") | |
66a63c5b | 5476 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
4673c1a0 | 5477 | "" |
5478 | "@ | |
5479 | sll\\t%0,%c2 | |
5480 | sll\\t%0,0(%2)" | |
369293ed | 5481 | [(set_attr "op_type" "RS")]) |
4673c1a0 | 5482 | |
5483 | ; | |
5484 | ; ashrsi3 instruction pattern(s). | |
5485 | ; | |
5486 | ||
66a63c5b | 5487 | (define_insn "*ashrsi3_cc" |
5488 | [(set (reg 33) | |
5489 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
5490 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5491 | (const_int 0))) | |
5492 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
5493 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
5494 | "s390_match_ccmode(insn, CCSmode)" | |
5495 | "@ | |
5496 | sra\\t%0,%c2 | |
5497 | sra\\t%0,0(%2)" | |
5498 | [(set_attr "op_type" "RS")]) | |
5499 | ||
5500 | (define_insn "*ashrsi3_cconly" | |
5501 | [(set (reg 33) | |
5502 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
5503 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5504 | (const_int 0))) | |
5505 | (clobber (match_scratch:SI 0 "=d,d"))] | |
5506 | "s390_match_ccmode(insn, CCSmode)" | |
5507 | "@ | |
5508 | sra\\t%0,%c2 | |
5509 | sra\\t%0,0(%2)" | |
5510 | [(set_attr "op_type" "RS")]) | |
5511 | ||
4673c1a0 | 5512 | (define_insn "ashrsi3" |
5513 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5514 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
8b4a4127 | 5515 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) |
4673c1a0 | 5516 | (clobber (reg:CC 33))] |
5517 | "" | |
5518 | "@ | |
5519 | sra\\t%0,%c2 | |
5520 | sra\\t%0,0(%2)" | |
369293ed | 5521 | [(set_attr "op_type" "RS")]) |
4673c1a0 | 5522 | |
4673c1a0 | 5523 | |
5524 | ;; | |
5525 | ;;- logical shift instructions. | |
5526 | ;; | |
5527 | ||
5528 | ; | |
5529 | ; lshrdi3 instruction pattern(s). | |
5530 | ; | |
5531 | ||
5532 | (define_expand "lshrdi3" | |
66a63c5b | 5533 | [(set (match_operand:DI 0 "register_operand" "") |
5534 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
5535 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
4673c1a0 | 5536 | "" |
5537 | "") | |
5538 | ||
5539 | (define_insn "*lshrdi3_31" | |
5540 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5541 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
66a63c5b | 5542 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
4673c1a0 | 5543 | "!TARGET_64BIT" |
5544 | "@ | |
5545 | srdl\\t%0,%c2 | |
5546 | srdl\\t%0,0(%2)" | |
5547 | [(set_attr "op_type" "RS,RS")]) | |
5548 | ||
5549 | (define_insn "*lshrdi3_64" | |
5550 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5551 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
66a63c5b | 5552 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
4673c1a0 | 5553 | "TARGET_64BIT" |
5554 | "@ | |
5555 | srlg\\t%0,%1,%c2 | |
5556 | srlg\\t%0,%1,0(%2)" | |
c36e6d0b | 5557 | [(set_attr "op_type" "RSE,RSE")]) |
4673c1a0 | 5558 | |
5559 | ; | |
5560 | ; lshrsi3 instruction pattern(s). | |
5561 | ; | |
5562 | ||
5563 | (define_insn "lshrsi3" | |
5564 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5565 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
66a63c5b | 5566 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
4673c1a0 | 5567 | "" |
5568 | "@ | |
5569 | srl\\t%0,%c2 | |
5570 | srl\\t%0,0(%2)" | |
369293ed | 5571 | [(set_attr "op_type" "RS")]) |
4673c1a0 | 5572 | |
4673c1a0 | 5573 | |
5574 | ;; | |
5575 | ;; Branch instruction patterns. | |
5576 | ;; | |
5577 | ||
5578 | (define_expand "beq" | |
5579 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
5580 | (set (pc) | |
5581 | (if_then_else (eq (reg:CCZ 33) (const_int 0)) | |
5582 | (label_ref (match_operand 0 "" "")) | |
5583 | (pc)))] | |
5584 | "" | |
5585 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5586 | ||
5587 | (define_expand "bne" | |
5588 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
5589 | (set (pc) | |
5590 | (if_then_else (ne (reg:CCZ 33) (const_int 0)) | |
5591 | (label_ref (match_operand 0 "" "")) | |
5592 | (pc)))] | |
5593 | "" | |
5594 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5595 | ||
5596 | (define_expand "bgt" | |
5597 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5598 | (set (pc) | |
5599 | (if_then_else (gt (reg:CCS 33) (const_int 0)) | |
5600 | (label_ref (match_operand 0 "" "")) | |
5601 | (pc)))] | |
5602 | "" | |
5603 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5604 | ||
5605 | (define_expand "bgtu" | |
5606 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
5607 | (set (pc) | |
5608 | (if_then_else (gtu (reg:CCU 33) (const_int 0)) | |
5609 | (label_ref (match_operand 0 "" "")) | |
5610 | (pc)))] | |
5611 | "" | |
5612 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5613 | ||
5614 | (define_expand "blt" | |
5615 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5616 | (set (pc) | |
5617 | (if_then_else (lt (reg:CCS 33) (const_int 0)) | |
5618 | (label_ref (match_operand 0 "" "")) | |
5619 | (pc)))] | |
5620 | "" | |
5621 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5622 | ||
5623 | (define_expand "bltu" | |
5624 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
5625 | (set (pc) | |
5626 | (if_then_else (ltu (reg:CCU 33) (const_int 0)) | |
5627 | (label_ref (match_operand 0 "" "")) | |
5628 | (pc)))] | |
5629 | "" | |
5630 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5631 | ||
5632 | (define_expand "bge" | |
5633 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5634 | (set (pc) | |
5635 | (if_then_else (ge (reg:CCS 33) (const_int 0)) | |
5636 | (label_ref (match_operand 0 "" "")) | |
5637 | (pc)))] | |
5638 | "" | |
5639 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5640 | ||
5641 | (define_expand "bgeu" | |
5642 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
5643 | (set (pc) | |
5644 | (if_then_else (geu (reg:CCU 33) (const_int 0)) | |
5645 | (label_ref (match_operand 0 "" "")) | |
5646 | (pc)))] | |
5647 | "" | |
5648 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5649 | ||
5650 | (define_expand "ble" | |
5651 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5652 | (set (pc) | |
5653 | (if_then_else (le (reg:CCS 33) (const_int 0)) | |
5654 | (label_ref (match_operand 0 "" "")) | |
5655 | (pc)))] | |
5656 | "" | |
5657 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5658 | ||
5659 | (define_expand "bleu" | |
5660 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
5661 | (set (pc) | |
5662 | (if_then_else (leu (reg:CCU 33) (const_int 0)) | |
5663 | (label_ref (match_operand 0 "" "")) | |
5664 | (pc)))] | |
5665 | "" | |
5666 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5667 | ||
2eb8fe23 | 5668 | (define_expand "bunordered" |
5669 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5670 | (set (pc) | |
5671 | (if_then_else (unordered (reg:CCS 33) (const_int 0)) | |
5672 | (label_ref (match_operand 0 "" "")) | |
5673 | (pc)))] | |
5674 | "" | |
5675 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5676 | ||
5677 | (define_expand "bordered" | |
5678 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5679 | (set (pc) | |
5680 | (if_then_else (ordered (reg:CCS 33) (const_int 0)) | |
5681 | (label_ref (match_operand 0 "" "")) | |
5682 | (pc)))] | |
5683 | "" | |
5684 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5685 | ||
5686 | (define_expand "buneq" | |
5687 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5688 | (set (pc) | |
5689 | (if_then_else (uneq (reg:CCS 33) (const_int 0)) | |
5690 | (label_ref (match_operand 0 "" "")) | |
5691 | (pc)))] | |
5692 | "" | |
5693 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5694 | ||
5695 | (define_expand "bungt" | |
5696 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5697 | (set (pc) | |
5698 | (if_then_else (ungt (reg:CCS 33) (const_int 0)) | |
5699 | (label_ref (match_operand 0 "" "")) | |
5700 | (pc)))] | |
5701 | "" | |
5702 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5703 | ||
5704 | (define_expand "bunlt" | |
5705 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5706 | (set (pc) | |
5707 | (if_then_else (unlt (reg:CCS 33) (const_int 0)) | |
5708 | (label_ref (match_operand 0 "" "")) | |
5709 | (pc)))] | |
5710 | "" | |
5711 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5712 | ||
5713 | (define_expand "bunge" | |
5714 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5715 | (set (pc) | |
5716 | (if_then_else (unge (reg:CCS 33) (const_int 0)) | |
5717 | (label_ref (match_operand 0 "" "")) | |
5718 | (pc)))] | |
5719 | "" | |
5720 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5721 | ||
5722 | (define_expand "bunle" | |
5723 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5724 | (set (pc) | |
5725 | (if_then_else (unle (reg:CCS 33) (const_int 0)) | |
5726 | (label_ref (match_operand 0 "" "")) | |
5727 | (pc)))] | |
5728 | "" | |
5729 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5730 | ||
5731 | (define_expand "bltgt" | |
5732 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5733 | (set (pc) | |
5734 | (if_then_else (ltgt (reg:CCS 33) (const_int 0)) | |
5735 | (label_ref (match_operand 0 "" "")) | |
5736 | (pc)))] | |
5737 | "" | |
5738 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
5739 | ||
4673c1a0 | 5740 | |
5741 | ;; | |
5742 | ;;- Conditional jump instructions. | |
5743 | ;; | |
5744 | ||
5745 | (define_insn "cjump" | |
5746 | [(set (pc) | |
5747 | (if_then_else | |
5748 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
5749 | (label_ref (match_operand 0 "" "")) | |
5750 | (pc)))] | |
5751 | "" | |
5752 | "* | |
5753 | { | |
479ca6e8 | 5754 | if (get_attr_length (insn) == 4) |
5755 | return \"j%C1\\t%l0\"; | |
5756 | else if (TARGET_64BIT) | |
5757 | return \"jg%C1\\t%l0\"; | |
4673c1a0 | 5758 | else |
479ca6e8 | 5759 | abort (); |
4673c1a0 | 5760 | }" |
5761 | [(set_attr "op_type" "RI") | |
479ca6e8 | 5762 | (set (attr "length") |
5763 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
5764 | (const_int 4) | |
5765 | (ne (symbol_ref "TARGET_64BIT") (const_int 0)) | |
5766 | (const_int 6) | |
5767 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
5768 | (const_int 6)] (const_int 8)))]) | |
4673c1a0 | 5769 | |
0c0a8ea5 | 5770 | (define_insn "*cjump_long" |
4673c1a0 | 5771 | [(set (pc) |
5772 | (if_then_else | |
5773 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
0c0a8ea5 | 5774 | (match_operand 0 "address_operand" "p") |
4673c1a0 | 5775 | (pc)))] |
5776 | "" | |
0c0a8ea5 | 5777 | "* |
5778 | { | |
5779 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
5780 | return \"b%C1r\\t%0\"; | |
5781 | else | |
5782 | return \"b%C1\\t%a0\"; | |
5783 | }" | |
5784 | [(set (attr "op_type") | |
5785 | (if_then_else (match_operand 0 "register_operand" "") | |
5786 | (const_string "RR") (const_string "RX"))) | |
5787 | (set_attr "atype" "mem")]) | |
4673c1a0 | 5788 | |
5789 | ||
5790 | ;; | |
5791 | ;;- Negated conditional jump instructions. | |
5792 | ;; | |
5793 | ||
5794 | (define_insn "icjump" | |
5795 | [(set (pc) | |
5796 | (if_then_else | |
5797 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
5798 | (pc) | |
5799 | (label_ref (match_operand 0 "" ""))))] | |
5800 | "" | |
5801 | "* | |
5802 | { | |
479ca6e8 | 5803 | if (get_attr_length (insn) == 4) |
5804 | return \"j%D1\\t%l0\"; | |
5805 | else if (TARGET_64BIT) | |
5806 | return \"jg%D1\\t%l0\"; | |
4673c1a0 | 5807 | else |
479ca6e8 | 5808 | abort (); |
4673c1a0 | 5809 | }" |
5810 | [(set_attr "op_type" "RI") | |
479ca6e8 | 5811 | (set (attr "length") |
5812 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
5813 | (const_int 4) | |
5814 | (ne (symbol_ref "TARGET_64BIT") (const_int 0)) | |
5815 | (const_int 6) | |
5816 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
5817 | (const_int 6)] (const_int 8)))]) | |
4673c1a0 | 5818 | |
0c0a8ea5 | 5819 | (define_insn "*icjump_long" |
4673c1a0 | 5820 | [(set (pc) |
5821 | (if_then_else | |
5822 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
0c0a8ea5 | 5823 | (pc) |
5824 | (match_operand 0 "address_operand" "p")))] | |
4673c1a0 | 5825 | "" |
0c0a8ea5 | 5826 | "* |
5827 | { | |
5828 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
5829 | return \"b%D1r\\t%0\"; | |
5830 | else | |
5831 | return \"b%D1\\t%a0\"; | |
5832 | }" | |
5833 | [(set (attr "op_type") | |
5834 | (if_then_else (match_operand 0 "register_operand" "") | |
5835 | (const_string "RR") (const_string "RX"))) | |
5836 | (set_attr "atype" "mem")]) | |
4673c1a0 | 5837 | |
49df79a5 | 5838 | ;; |
5839 | ;;- Trap instructions. | |
5840 | ;; | |
5841 | ||
5842 | (define_insn "trap" | |
5843 | [(trap_if (const_int 1) (const_int 0))] | |
5844 | "" | |
5845 | "j\\t.+2" | |
5846 | [(set_attr "op_type" "RX")]) | |
5847 | ||
5848 | (define_expand "conditional_trap" | |
5849 | [(set (match_dup 2) (match_dup 3)) | |
5850 | (trap_if (match_operator 0 "comparison_operator" | |
5851 | [(match_dup 2) (const_int 0)]) | |
5852 | (match_operand:SI 1 "general_operand" ""))] | |
5853 | "" | |
5854 | " | |
5855 | { | |
5856 | enum machine_mode ccmode; | |
5857 | ||
5858 | if (operands[1] != const0_rtx) FAIL; | |
5859 | ||
5860 | ccmode = s390_select_ccmode (GET_CODE (operands[0]), | |
5861 | s390_compare_op0, s390_compare_op1); | |
5862 | operands[2] = gen_rtx_REG (ccmode, 33); | |
5863 | operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1); | |
5864 | }") | |
5865 | ||
5866 | (define_insn "*trap" | |
5867 | [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)]) | |
5868 | (const_int 0))] | |
5869 | "" | |
5870 | "j%C0\\t.+2"; | |
5871 | [(set_attr "op_type" "RX")]) | |
4673c1a0 | 5872 | |
5873 | ;; | |
3c482144 | 5874 | ;;- Loop instructions. |
4673c1a0 | 5875 | ;; |
3c482144 | 5876 | ;; This is all complicated by the fact that since this is a jump insn |
5877 | ;; we must handle our own output reloads. | |
5878 | ||
5879 | (define_expand "doloop_end" | |
5880 | [(use (match_operand 0 "" "")) ; loop pseudo | |
5881 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
5882 | (use (match_operand 2 "" "")) ; max iterations | |
5883 | (use (match_operand 3 "" "")) ; loop level | |
5884 | (use (match_operand 4 "" ""))] ; label | |
5885 | "" | |
5886 | " | |
5887 | { | |
5888 | if (GET_MODE (operands[0]) == SImode) | |
5889 | emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0])); | |
5890 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) | |
5891 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
5892 | else | |
5893 | FAIL; | |
5894 | ||
5895 | DONE; | |
5896 | }") | |
5897 | ||
5898 | (define_insn "doloop_si" | |
5899 | [(set (pc) | |
5900 | (if_then_else | |
5901 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
5902 | (const_int 1)) | |
5903 | (label_ref (match_operand 0 "" "")) | |
5904 | (pc))) | |
5905 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
5906 | (plus:SI (match_dup 1) (const_int -1))) | |
5907 | (clobber (match_scratch:SI 3 "=X,&d")) | |
5908 | (clobber (reg:CC 33))] | |
5909 | "" | |
5910 | "* | |
5911 | { | |
5912 | if (which_alternative != 0) | |
5913 | return \"#\"; | |
5914 | else if (get_attr_length (insn) == 4) | |
5915 | return \"brct\\t%1,%l0\"; | |
5916 | else | |
5917 | abort (); | |
5918 | }" | |
5919 | [(set_attr "op_type" "RI") | |
5920 | (set (attr "length") | |
5921 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
5922 | (const_int 4) | |
5923 | (ne (symbol_ref "TARGET_64BIT") (const_int 0)) | |
5924 | (const_int 10) | |
3c482144 | 5925 | (eq (symbol_ref "flag_pic") (const_int 0)) |
5926 | (const_int 6)] (const_int 8)))]) | |
4673c1a0 | 5927 | |
3c482144 | 5928 | (define_insn "*doloop_si_long" |
5929 | [(set (pc) | |
5930 | (if_then_else | |
5931 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
5932 | (const_int 1)) | |
5933 | (match_operand 0 "address_operand" "p,p") | |
5934 | (pc))) | |
5935 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
5936 | (plus:SI (match_dup 1) (const_int -1))) | |
5937 | (clobber (match_scratch:SI 3 "=X,&d")) | |
5938 | (clobber (reg:CC 33))] | |
5939 | "" | |
5940 | "* | |
5941 | { | |
5942 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
1150f6b0 | 5943 | return \"bctr\\t%1,%0\"; |
3c482144 | 5944 | else |
1150f6b0 | 5945 | return \"bct\\t%1,%a0\"; |
3c482144 | 5946 | }" |
5947 | [(set (attr "op_type") | |
5948 | (if_then_else (match_operand 0 "register_operand" "") | |
5949 | (const_string "RR") (const_string "RX"))) | |
5950 | (set_attr "atype" "mem")]) | |
5951 | ||
5952 | (define_split | |
5953 | [(set (pc) | |
5954 | (if_then_else (ne (match_operand:SI 1 "register_operand" "") | |
5955 | (const_int 1)) | |
5956 | (match_operand 0 "" "") | |
5957 | (pc))) | |
5958 | (set (match_operand:SI 2 "nonimmediate_operand" "") | |
5959 | (plus:SI (match_dup 1) (const_int -1))) | |
5960 | (clobber (match_scratch:SI 3 "")) | |
5961 | (clobber (reg:CC 33))] | |
5962 | "reload_completed | |
5963 | && (! REG_P (operands[2]) | |
5964 | || ! rtx_equal_p (operands[1], operands[2]))" | |
5965 | [(set (match_dup 3) (match_dup 1)) | |
5966 | (parallel [(set (reg:CCAN 33) | |
5967 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
5968 | (const_int 0))) | |
5969 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
5970 | (set (match_dup 2) (match_dup 3)) | |
5971 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
5972 | (match_dup 0) | |
5973 | (pc)))] | |
5974 | "") | |
4673c1a0 | 5975 | |
3c482144 | 5976 | (define_insn "doloop_di" |
5977 | [(set (pc) | |
5978 | (if_then_else | |
5979 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
5980 | (const_int 1)) | |
5981 | (label_ref (match_operand 0 "" "")) | |
5982 | (pc))) | |
5983 | (set (match_operand:DI 2 "register_operand" "=1,?*m*r") | |
5984 | (plus:DI (match_dup 1) (const_int -1))) | |
5985 | (clobber (match_scratch:DI 3 "=X,&d")) | |
5986 | (clobber (reg:CC 33))] | |
5987 | "TARGET_64BIT" | |
5988 | "* | |
5989 | { | |
5990 | if (which_alternative != 0) | |
5991 | return \"#\"; | |
5992 | else if (get_attr_length (insn) == 4) | |
5993 | return \"brctg\\t%1,%l0\"; | |
5994 | else | |
5995 | abort (); | |
5996 | }" | |
5997 | [(set_attr "op_type" "RI") | |
5998 | (set (attr "length") | |
5999 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6000 | (const_int 4) (const_int 12)))]) | |
6001 | ||
6002 | (define_insn "*doloop_di_long" | |
6003 | [(set (pc) | |
6004 | (if_then_else | |
6005 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6006 | (const_int 1)) | |
6007 | (match_operand 0 "address_operand" "p,p") | |
6008 | (pc))) | |
6009 | (set (match_operand:DI 2 "register_operand" "=1,?*m*d") | |
6010 | (plus:DI (match_dup 1) (const_int -1))) | |
6011 | (clobber (match_scratch:DI 3 "=X,&d")) | |
6012 | (clobber (reg:CC 33))] | |
6013 | "" | |
6014 | "* | |
6015 | { | |
6016 | if (get_attr_op_type (insn) == OP_TYPE_RRE) | |
1150f6b0 | 6017 | return \"bctgr\\t%1,%0\"; |
3c482144 | 6018 | else |
1150f6b0 | 6019 | return \"bctg\\t%1,%a0\"; |
3c482144 | 6020 | }" |
6021 | [(set (attr "op_type") | |
6022 | (if_then_else (match_operand 0 "register_operand" "") | |
6023 | (const_string "RRE") (const_string "RXE"))) | |
6024 | (set_attr "atype" "mem")]) | |
6025 | ||
6026 | (define_split | |
6027 | [(set (pc) | |
6028 | (if_then_else (ne (match_operand:DI 1 "register_operand" "") | |
6029 | (const_int 1)) | |
6030 | (match_operand 0 "" "") | |
6031 | (pc))) | |
6032 | (set (match_operand:DI 2 "nonimmediate_operand" "") | |
6033 | (plus:DI (match_dup 1) (const_int -1))) | |
6034 | (clobber (match_scratch:DI 3 "")) | |
6035 | (clobber (reg:CC 33))] | |
6036 | "reload_completed | |
6037 | && (! REG_P (operands[2]) | |
6038 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6039 | [(set (match_dup 3) (match_dup 1)) | |
6040 | (parallel [(set (reg:CCAN 33) | |
6041 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) | |
6042 | (const_int 0))) | |
6043 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6044 | (set (match_dup 2) (match_dup 3)) | |
6045 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6046 | (match_dup 0) | |
6047 | (pc)))] | |
6048 | "") | |
4673c1a0 | 6049 | |
6050 | ;; | |
6051 | ;;- Unconditional jump instructions. | |
6052 | ;; | |
6053 | ||
6054 | ; | |
6055 | ; jump instruction pattern(s). | |
6056 | ; | |
6057 | ||
6058 | (define_insn "jump" | |
6059 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6060 | "" | |
6061 | "* | |
6062 | { | |
479ca6e8 | 6063 | if (get_attr_length (insn) == 4) |
6064 | return \"j\\t%l0\"; | |
6065 | else if (TARGET_64BIT) | |
6066 | return \"jg\\t%l0\"; | |
4673c1a0 | 6067 | else |
479ca6e8 | 6068 | abort (); |
4673c1a0 | 6069 | }" |
6070 | [(set_attr "op_type" "RI") | |
479ca6e8 | 6071 | (set (attr "length") |
6072 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6073 | (const_int 4) | |
6074 | (ne (symbol_ref "TARGET_64BIT") (const_int 0)) | |
6075 | (const_int 6) | |
6076 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6077 | (const_int 6)] (const_int 8)))]) | |
4673c1a0 | 6078 | |
6079 | ; | |
6080 | ; indirect-jump instruction pattern(s). | |
6081 | ; | |
6082 | ||
6083 | (define_insn "indirect_jump" | |
0c0a8ea5 | 6084 | [(set (pc) (match_operand 0 "address_operand" "p"))] |
4673c1a0 | 6085 | "" |
0c0a8ea5 | 6086 | "* |
6087 | { | |
6088 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
6089 | return \"br\\t%0\"; | |
6090 | else | |
6091 | return \"b\\t%a0\"; | |
6092 | }" | |
6093 | [(set (attr "op_type") | |
6094 | (if_then_else (match_operand 0 "register_operand" "") | |
6095 | (const_string "RR") (const_string "RX"))) | |
6096 | (set_attr "atype" "mem")]) | |
4673c1a0 | 6097 | |
6098 | ; | |
0c0a8ea5 | 6099 | ; casesi instruction pattern(s). |
4673c1a0 | 6100 | ; |
6101 | ||
0c0a8ea5 | 6102 | (define_insn "casesi_jump" |
6103 | [(set (pc) (match_operand 0 "address_operand" "p")) | |
6104 | (use (label_ref (match_operand 1 "" "")))] | |
4673c1a0 | 6105 | "" |
0c0a8ea5 | 6106 | "* |
4673c1a0 | 6107 | { |
0c0a8ea5 | 6108 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
6109 | return \"br\\t%0\"; | |
6110 | else | |
6111 | return \"b\\t%a0\"; | |
6112 | }" | |
6113 | [(set (attr "op_type") | |
6114 | (if_then_else (match_operand 0 "register_operand" "") | |
6115 | (const_string "RR") (const_string "RX"))) | |
6116 | (set_attr "atype" "mem")]) | |
4673c1a0 | 6117 | |
0c0a8ea5 | 6118 | (define_expand "casesi" |
6119 | [(match_operand:SI 0 "general_operand" "") | |
6120 | (match_operand:SI 1 "general_operand" "") | |
6121 | (match_operand:SI 2 "general_operand" "") | |
6122 | (label_ref (match_operand 3 "" "")) | |
6123 | (label_ref (match_operand 4 "" ""))] | |
4673c1a0 | 6124 | "" |
0c0a8ea5 | 6125 | " |
6126 | { | |
6127 | rtx index = gen_reg_rtx (SImode); | |
6128 | rtx base = gen_reg_rtx (Pmode); | |
6129 | rtx target = gen_reg_rtx (Pmode); | |
6130 | ||
6131 | emit_move_insn (index, operands[0]); | |
6132 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6133 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
3d182d84 | 6134 | operands[4]); |
0c0a8ea5 | 6135 | |
6136 | if (Pmode != SImode) | |
6137 | index = convert_to_mode (Pmode, index, 1); | |
6138 | if (GET_CODE (index) != REG) | |
6139 | index = copy_to_mode_reg (Pmode, index); | |
6140 | ||
6141 | if (TARGET_64BIT) | |
6142 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6143 | else | |
6144 | emit_insn (gen_ashlsi3 (index, index, GEN_INT (2))); | |
4673c1a0 | 6145 | |
0c0a8ea5 | 6146 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6147 | ||
6148 | index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index)); | |
6149 | emit_move_insn (target, index); | |
6150 | ||
6151 | if (flag_pic) | |
6152 | target = gen_rtx_PLUS (Pmode, base, target); | |
6153 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
6154 | ||
6155 | DONE; | |
6156 | }") | |
4673c1a0 | 6157 | |
6158 | ||
6159 | ;; | |
6160 | ;;- Jump to subroutine. | |
6161 | ;; | |
6162 | ;; | |
6163 | ||
6164 | ; | |
6165 | ; untyped call instruction pattern(s). | |
6166 | ; | |
6167 | ||
6168 | ;; Call subroutine returning any type. | |
6169 | (define_expand "untyped_call" | |
6170 | [(parallel [(call (match_operand 0 "" "") | |
6171 | (const_int 0)) | |
6172 | (match_operand 1 "" "") | |
6173 | (match_operand 2 "" "")])] | |
6174 | "" | |
6175 | " | |
6176 | { | |
6177 | int i; | |
6178 | ||
6179 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
6180 | ||
6181 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
6182 | { | |
6183 | rtx set = XVECEXP (operands[2], 0, i); | |
6184 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
6185 | } | |
6186 | ||
6187 | /* The optimizer does not know that the call sets the function value | |
6188 | registers we stored in the result block. We avoid problems by | |
6189 | claiming that all hard registers are used and clobbered at this | |
6190 | point. */ | |
6191 | emit_insn (gen_blockage ()); | |
6192 | ||
6193 | DONE; | |
6194 | }") | |
6195 | ||
6196 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
6197 | ;; all of memory. This blocks insns from being moved across this point. | |
6198 | ||
6199 | (define_insn "blockage" | |
6200 | [(unspec_volatile [(const_int 0)] 0)] | |
6201 | "" | |
8b4a4127 | 6202 | "" |
c36e6d0b | 6203 | [(set_attr "type" "none") |
6204 | (set_attr "length" "0")]) | |
8b4a4127 | 6205 | |
4673c1a0 | 6206 | |
6207 | ||
6208 | ; | |
6209 | ; call instruction pattern(s). | |
6210 | ; | |
6211 | ||
6212 | (define_expand "call" | |
c89f9ed7 | 6213 | [(call (match_operand 0 "" "") |
6214 | (match_operand 1 "" "")) | |
6215 | (use (match_operand 2 "" ""))] | |
4673c1a0 | 6216 | "" |
6217 | " | |
6218 | { | |
c89f9ed7 | 6219 | int plt_call = 0; |
6220 | rtx insn; | |
4673c1a0 | 6221 | |
6222 | /* Direct function calls need special treatment. */ | |
6223 | if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) | |
6224 | { | |
6225 | rtx sym = XEXP (operands[0], 0); | |
6226 | ||
6227 | /* When calling a global routine in PIC mode, we must | |
6228 | replace the symbol itself with the PLT stub. */ | |
c89f9ed7 | 6229 | if (flag_pic && !SYMBOL_REF_FLAG (sym)) |
4673c1a0 | 6230 | { |
6231 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); | |
6232 | sym = gen_rtx_CONST (Pmode, sym); | |
c89f9ed7 | 6233 | |
6234 | plt_call = 1; | |
4673c1a0 | 6235 | } |
6236 | ||
6237 | /* Unless we can use the bras(l) insn, force the | |
6238 | routine address into a register. */ | |
6239 | if (!TARGET_SMALL_EXEC && !TARGET_64BIT) | |
6240 | { | |
6241 | rtx target = gen_reg_rtx (Pmode); | |
6242 | emit_move_insn (target, sym); | |
6243 | sym = target; | |
6244 | } | |
6245 | ||
6246 | operands[0] = gen_rtx_MEM (QImode, sym); | |
6247 | } | |
c89f9ed7 | 6248 | |
6249 | /* Emit insn. */ | |
6250 | insn = emit_call_insn (gen_call_exp (operands[0], operands[1], | |
6251 | gen_rtx_REG (Pmode, RETURN_REGNUM))); | |
6252 | ||
6253 | /* In 31-bit, we must load the GOT register even if the | |
6254 | compiler doesn't know about it, because the PLT glue | |
6255 | code uses it. In 64-bit, this is not necessary. */ | |
6256 | if (plt_call && !TARGET_64BIT) | |
9a2a66ae | 6257 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
c89f9ed7 | 6258 | |
6259 | DONE; | |
4673c1a0 | 6260 | }") |
6261 | ||
c89f9ed7 | 6262 | (define_expand "call_exp" |
6263 | [(parallel [(call (match_operand 0 "" "") | |
6264 | (match_operand 1 "" "")) | |
6265 | (clobber (match_operand 2 "" ""))])] | |
6266 | "" | |
6267 | "") | |
6268 | ||
4673c1a0 | 6269 | (define_insn "brasl" |
6270 | [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X")) | |
6271 | (match_operand:SI 1 "const_int_operand" "n")) | |
6272 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
6273 | "TARGET_64BIT" | |
6274 | "brasl\\t%2,%0" | |
6275 | [(set_attr "op_type" "RIL") | |
8b4a4127 | 6276 | (set_attr "type" "jsr")]) |
4673c1a0 | 6277 | |
6278 | (define_insn "bras" | |
6279 | [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X")) | |
6280 | (match_operand:SI 1 "const_int_operand" "n")) | |
6281 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
6282 | "TARGET_SMALL_EXEC" | |
6283 | "bras\\t%2,%0" | |
6284 | [(set_attr "op_type" "RI") | |
8b4a4127 | 6285 | (set_attr "type" "jsr")]) |
4673c1a0 | 6286 | |
6287 | (define_insn "basr_64" | |
6288 | [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) | |
6289 | (match_operand:SI 1 "const_int_operand" "n")) | |
6290 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
6291 | "TARGET_64BIT" | |
6292 | "basr\\t%2,%0" | |
6293 | [(set_attr "op_type" "RR") | |
369293ed | 6294 | (set_attr "type" "jsr") |
4673c1a0 | 6295 | (set_attr "atype" "mem")]) |
6296 | ||
6297 | (define_insn "basr_31" | |
6298 | [(call (mem:QI (match_operand:SI 0 "register_operand" "a")) | |
6299 | (match_operand:SI 1 "const_int_operand" "n")) | |
6300 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
6301 | "!TARGET_64BIT" | |
6302 | "basr\\t%2,%0" | |
6303 | [(set_attr "op_type" "RR") | |
369293ed | 6304 | (set_attr "type" "jsr") |
4673c1a0 | 6305 | (set_attr "atype" "mem")]) |
6306 | ||
6307 | (define_insn "bas_64" | |
6308 | [(call (mem:QI (match_operand:QI 0 "address_operand" "p")) | |
6309 | (match_operand:SI 1 "const_int_operand" "n")) | |
6310 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
6311 | "TARGET_64BIT" | |
6312 | "bas\\t%2,%a0" | |
6313 | [(set_attr "op_type" "RX") | |
369293ed | 6314 | (set_attr "type" "jsr") |
4673c1a0 | 6315 | (set_attr "atype" "mem")]) |
6316 | ||
6317 | (define_insn "bas_31" | |
6318 | [(call (mem:QI (match_operand:QI 0 "address_operand" "p")) | |
6319 | (match_operand:SI 1 "const_int_operand" "n")) | |
6320 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
6321 | "!TARGET_64BIT" | |
6322 | "bas\\t%2,%a0" | |
6323 | [(set_attr "op_type" "RX") | |
369293ed | 6324 | (set_attr "type" "jsr") |
4673c1a0 | 6325 | (set_attr "atype" "mem")]) |
6326 | ||
6327 | ||
6328 | ; | |
6329 | ; call_value instruction pattern(s). | |
6330 | ; | |
6331 | ||
6332 | (define_expand "call_value" | |
c89f9ed7 | 6333 | [(set (match_operand 0 "" "") |
6334 | (call (match_operand 1 "" "") | |
6335 | (match_operand 2 "" ""))) | |
6336 | (use (match_operand 3 "" ""))] | |
4673c1a0 | 6337 | "" |
6338 | " | |
6339 | { | |
c89f9ed7 | 6340 | int plt_call = 0; |
6341 | rtx insn; | |
4673c1a0 | 6342 | |
6343 | /* Direct function calls need special treatment. */ | |
6344 | if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) | |
6345 | { | |
6346 | rtx sym = XEXP (operands[1], 0); | |
6347 | ||
6348 | /* When calling a global routine in PIC mode, we must | |
6349 | replace the symbol itself with the PLT stub. */ | |
c89f9ed7 | 6350 | if (flag_pic && !SYMBOL_REF_FLAG (sym)) |
4673c1a0 | 6351 | { |
6352 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); | |
6353 | sym = gen_rtx_CONST (Pmode, sym); | |
c89f9ed7 | 6354 | |
6355 | plt_call = 1; | |
4673c1a0 | 6356 | } |
6357 | ||
6358 | /* Unless we can use the bras(l) insn, force the | |
6359 | routine address into a register. */ | |
6360 | if (!TARGET_SMALL_EXEC && !TARGET_64BIT) | |
6361 | { | |
6362 | rtx target = gen_reg_rtx (Pmode); | |
6363 | emit_move_insn (target, sym); | |
6364 | sym = target; | |
6365 | } | |
6366 | ||
6367 | operands[1] = gen_rtx_MEM (QImode, sym); | |
6368 | } | |
c89f9ed7 | 6369 | |
6370 | /* Emit insn. */ | |
6371 | insn = emit_call_insn ( | |
6372 | gen_call_value_exp (operands[0], operands[1], operands[2], | |
6373 | gen_rtx_REG (Pmode, RETURN_REGNUM))); | |
6374 | ||
6375 | /* In 31-bit, we must load the GOT register even if the | |
6376 | compiler doesn't know about it, because the PLT glue | |
6377 | code uses it. In 64-bit, this is not necessary. */ | |
6378 | if (plt_call && !TARGET_64BIT) | |
9a2a66ae | 6379 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
c89f9ed7 | 6380 | |
6381 | DONE; | |
4673c1a0 | 6382 | }") |
6383 | ||
c89f9ed7 | 6384 | (define_expand "call_value_exp" |
6385 | [(parallel [(set (match_operand 0 "" "") | |
6386 | (call (match_operand 1 "" "") | |
6387 | (match_operand 2 "" ""))) | |
6388 | (clobber (match_operand 3 "" ""))])] | |
6389 | "" | |
6390 | "") | |
6391 | ||
4673c1a0 | 6392 | (define_insn "brasl_r" |
6393 | [(set (match_operand 0 "register_operand" "=df") | |
6394 | (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) | |
6395 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6396 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
6397 | "TARGET_64BIT" | |
6398 | "brasl\\t%3,%1" | |
6399 | [(set_attr "op_type" "RIL") | |
369293ed | 6400 | (set_attr "type" "jsr")]) |
4673c1a0 | 6401 | |
6402 | (define_insn "bras_r" | |
6403 | [(set (match_operand 0 "register_operand" "=df") | |
6404 | (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) | |
6405 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6406 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
6407 | "TARGET_SMALL_EXEC" | |
6408 | "bras\\t%3,%1" | |
6409 | [(set_attr "op_type" "RI") | |
369293ed | 6410 | (set_attr "type" "jsr")]) |
4673c1a0 | 6411 | |
6412 | (define_insn "basr_r_64" | |
6413 | [(set (match_operand 0 "register_operand" "=df") | |
6414 | (call (mem:QI (match_operand:DI 1 "register_operand" "a")) | |
6415 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6416 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
6417 | "TARGET_64BIT" | |
6418 | "basr\\t%3,%1" | |
6419 | [(set_attr "op_type" "RR") | |
369293ed | 6420 | (set_attr "type" "jsr")]) |
4673c1a0 | 6421 | |
6422 | (define_insn "basr_r_31" | |
6423 | [(set (match_operand 0 "register_operand" "=df") | |
6424 | (call (mem:QI (match_operand:SI 1 "register_operand" "a")) | |
6425 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6426 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
6427 | "!TARGET_64BIT" | |
6428 | "basr\\t%3,%1" | |
6429 | [(set_attr "op_type" "RR") | |
369293ed | 6430 | (set_attr "type" "jsr") |
4673c1a0 | 6431 | (set_attr "atype" "mem")]) |
6432 | ||
6433 | (define_insn "bas_r_64" | |
6434 | [(set (match_operand 0 "register_operand" "=df") | |
6435 | (call (mem:QI (match_operand:QI 1 "address_operand" "p")) | |
6436 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6437 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
6438 | "TARGET_64BIT" | |
6439 | "bas\\t%3,%a1" | |
6440 | [(set_attr "op_type" "RX") | |
369293ed | 6441 | (set_attr "type" "jsr") |
4673c1a0 | 6442 | (set_attr "atype" "mem")]) |
6443 | ||
6444 | (define_insn "bas_r_31" | |
6445 | [(set (match_operand 0 "register_operand" "=df") | |
6446 | (call (mem:QI (match_operand:QI 1 "address_operand" "p")) | |
6447 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6448 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
6449 | "!TARGET_64BIT" | |
6450 | "bas\\t%3,%a1" | |
6451 | [(set_attr "op_type" "RX") | |
369293ed | 6452 | (set_attr "type" "jsr") |
4673c1a0 | 6453 | (set_attr "atype" "mem")]) |
6454 | ||
6455 | ||
6456 | ;; | |
6457 | ;;- Miscellaneous instructions. | |
6458 | ;; | |
6459 | ||
6460 | ; | |
6461 | ; allocate stack instruction pattern(s). | |
6462 | ; | |
6463 | ||
6464 | (define_expand "allocate_stack" | |
6465 | [(set (reg 15) | |
6466 | (plus (reg 15) (match_operand 1 "general_operand" ""))) | |
6467 | (set (match_operand 0 "general_operand" "") | |
6468 | (reg 15))] | |
6469 | "" | |
6470 | " | |
6471 | { | |
6472 | rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); | |
6473 | rtx chain = gen_rtx (MEM, Pmode, stack); | |
6474 | rtx temp = gen_reg_rtx (Pmode); | |
6475 | ||
6476 | emit_move_insn (temp, chain); | |
6477 | ||
6478 | if (TARGET_64BIT) | |
6479 | emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
6480 | else | |
6481 | emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
6482 | ||
6483 | emit_move_insn (chain, temp); | |
6484 | ||
6485 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
6486 | DONE; | |
6487 | }") | |
6488 | ||
6489 | ||
6490 | ; | |
6491 | ; setjmp/longjmp instruction pattern(s). | |
6492 | ; | |
6493 | ||
6494 | (define_expand "builtin_setjmp_setup" | |
6495 | [(unspec [(match_operand 0 "register_operand" "a")] 1)] | |
6496 | "" | |
6497 | " | |
6498 | { | |
0c0a8ea5 | 6499 | rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); |
6500 | rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); | |
6501 | ||
6502 | emit_move_insn (base, basereg); | |
4673c1a0 | 6503 | DONE; |
6504 | }") | |
6505 | ||
6506 | (define_expand "builtin_setjmp_receiver" | |
6507 | [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)] | |
0c0a8ea5 | 6508 | "flag_pic" |
4673c1a0 | 6509 | " |
6510 | { | |
0c0a8ea5 | 6511 | rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); |
6512 | rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); | |
6513 | SYMBOL_REF_FLAG (got) = 1; | |
6514 | ||
6515 | emit_move_insn (gotreg, got); | |
6516 | emit_insn (gen_rtx_USE (VOIDmode, gotreg)); | |
4673c1a0 | 6517 | DONE; |
6518 | }") | |
6519 | ||
4673c1a0 | 6520 | (define_expand "builtin_longjmp" |
6521 | [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)] | |
6522 | "" | |
6523 | " | |
6524 | { | |
6525 | /* The elements of the buffer are, in order: */ | |
6526 | rtx fp = gen_rtx_MEM (Pmode, operands[0]); | |
0c0a8ea5 | 6527 | rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode))); |
6528 | rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode))); | |
6529 | rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); | |
6530 | rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); | |
4673c1a0 | 6531 | rtx jmp = gen_rtx_REG (Pmode, 14); |
6532 | ||
6533 | emit_move_insn (jmp, lab); | |
0c0a8ea5 | 6534 | emit_move_insn (basereg, base); |
4673c1a0 | 6535 | emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); |
6536 | emit_move_insn (hard_frame_pointer_rtx, fp); | |
6537 | ||
6538 | emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx)); | |
6539 | emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); | |
0c0a8ea5 | 6540 | emit_insn (gen_rtx_USE (VOIDmode, basereg)); |
4673c1a0 | 6541 | emit_indirect_jump (jmp); |
6542 | DONE; | |
6543 | }") | |
6544 | ||
6545 | ||
6546 | ;; These patterns say how to save and restore the stack pointer. We need not | |
6547 | ;; save the stack pointer at function level since we are careful to | |
6548 | ;; preserve the backchain. At block level, we have to restore the backchain | |
6549 | ;; when we restore the stack pointer. | |
6550 | ;; | |
6551 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
6552 | ;; backchain and restore both. Note that in the nonlocal case, the | |
6553 | ;; save area is a memory location. | |
6554 | ||
6555 | (define_expand "save_stack_function" | |
6556 | [(match_operand 0 "general_operand" "") | |
6557 | (match_operand 1 "general_operand" "")] | |
6558 | "" | |
6559 | "DONE;") | |
6560 | ||
6561 | (define_expand "restore_stack_function" | |
6562 | [(match_operand 0 "general_operand" "") | |
6563 | (match_operand 1 "general_operand" "")] | |
6564 | "" | |
6565 | "DONE;") | |
6566 | ||
6567 | (define_expand "restore_stack_block" | |
6568 | [(use (match_operand 0 "register_operand" "")) | |
6569 | (set (match_dup 2) (match_dup 3)) | |
6570 | (set (match_dup 0) (match_operand 1 "register_operand" "")) | |
6571 | (set (match_dup 3) (match_dup 2))] | |
6572 | "" | |
6573 | " | |
6574 | { | |
6575 | operands[2] = gen_reg_rtx (Pmode); | |
6576 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); | |
6577 | }") | |
6578 | ||
6579 | (define_expand "save_stack_nonlocal" | |
6580 | [(match_operand 0 "memory_operand" "") | |
6581 | (match_operand 1 "register_operand" "")] | |
6582 | "" | |
6583 | " | |
6584 | { | |
6585 | rtx temp = gen_reg_rtx (Pmode); | |
6586 | ||
6587 | /* Copy the backchain to the first word, sp to the second. */ | |
6588 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); | |
6589 | emit_move_insn (operand_subword (operands[0], 0, 0, | |
6590 | TARGET_64BIT ? TImode : DImode), | |
6591 | temp); | |
6592 | emit_move_insn (operand_subword (operands[0], 1, 0, | |
6593 | TARGET_64BIT ? TImode : DImode), | |
6594 | operands[1]); | |
6595 | DONE; | |
6596 | }") | |
6597 | ||
6598 | (define_expand "restore_stack_nonlocal" | |
6599 | [(match_operand 0 "register_operand" "") | |
6600 | (match_operand 1 "memory_operand" "")] | |
6601 | "" | |
6602 | " | |
6603 | { | |
6604 | rtx temp = gen_reg_rtx (Pmode); | |
6605 | ||
6606 | /* Restore the backchain from the first word, sp from the second. */ | |
6607 | emit_move_insn (temp, | |
6608 | operand_subword (operands[1], 0, 0, | |
6609 | TARGET_64BIT ? TImode : DImode)); | |
6610 | emit_move_insn (operands[0], | |
6611 | operand_subword (operands[1], 1, 0, | |
6612 | TARGET_64BIT ? TImode : DImode)); | |
6613 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); | |
6614 | DONE; | |
6615 | }") | |
6616 | ||
6617 | ||
6618 | ; | |
6619 | ; nop instruction pattern(s). | |
6620 | ; | |
6621 | ||
6622 | (define_insn "nop" | |
6623 | [(const_int 0)] | |
6624 | "" | |
6625 | "lr\\t0,0" | |
6626 | [(set_attr "op_type" "RR")]) | |
6627 | ||
6628 | ||
6629 | ; | |
6630 | ; Special literal pool access instruction pattern(s). | |
6631 | ; | |
6632 | ||
0756cebb | 6633 | (define_insn "consttable_qi" |
6634 | [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)] | |
4673c1a0 | 6635 | "" |
6636 | "* | |
6637 | { | |
0756cebb | 6638 | assemble_integer (operands[0], 1, BITS_PER_UNIT, 1); |
6639 | return \"\"; | |
4673c1a0 | 6640 | }" |
0756cebb | 6641 | [(set_attr "op_type" "NN") |
6642 | (set_attr "length" "1")]) | |
6643 | ||
6644 | (define_insn "consttable_hi" | |
6645 | [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)] | |
6646 | "" | |
6647 | "* | |
6648 | { | |
6649 | assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1); | |
6650 | return \"\"; | |
6651 | }" | |
6652 | [(set_attr "op_type" "NN") | |
6653 | (set_attr "length" "2")]) | |
6654 | ||
6655 | (define_insn "consttable_si" | |
6656 | [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)] | |
6657 | "" | |
6658 | "* | |
6659 | { | |
6660 | if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0])) | |
6661 | return \".long\\t%0\"; | |
4673c1a0 | 6662 | |
0756cebb | 6663 | assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1); |
6664 | return \"\"; | |
6665 | }" | |
6666 | [(set_attr "op_type" "NN") | |
6667 | (set_attr "length" "4")]) | |
6668 | ||
6669 | (define_insn "consttable_di" | |
6670 | [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)] | |
4673c1a0 | 6671 | "" |
6672 | "* | |
6673 | { | |
0756cebb | 6674 | assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1); |
6675 | return \"\"; | |
6676 | }" | |
6677 | [(set_attr "op_type" "NN") | |
6678 | (set_attr "length" "8")]) | |
6679 | ||
6680 | (define_insn "consttable_sf" | |
6681 | [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)] | |
6682 | "" | |
6683 | "* | |
6684 | { | |
6685 | REAL_VALUE_TYPE r; | |
6686 | ||
6687 | if (GET_CODE (operands[0]) != CONST_DOUBLE) | |
6688 | abort (); | |
6689 | ||
6690 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); | |
6691 | assemble_real (r, SFmode, 4*BITS_PER_UNIT); | |
6692 | return \"\"; | |
4673c1a0 | 6693 | }" |
0756cebb | 6694 | [(set_attr "op_type" "NN") |
6695 | (set_attr "length" "4")]) | |
6696 | ||
6697 | (define_insn "consttable_df" | |
6698 | [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)] | |
6699 | "" | |
6700 | "* | |
6701 | { | |
6702 | REAL_VALUE_TYPE r; | |
6703 | ||
6704 | if (GET_CODE (operands[0]) != CONST_DOUBLE) | |
6705 | abort (); | |
6706 | ||
6707 | REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); | |
6708 | assemble_real (r, DFmode, 8*BITS_PER_UNIT); | |
6709 | return \"\"; | |
6710 | }" | |
6711 | [(set_attr "op_type" "NN") | |
6712 | (set_attr "length" "8")]) | |
6713 | ||
6714 | (define_insn "pool_start_31" | |
6715 | [(unspec_volatile [(const_int 0)] 206)] | |
6716 | "!TARGET_64BIT" | |
6717 | ".align\\t4" | |
6718 | [(set_attr "op_type" "NN") | |
6719 | (set_attr "length" "2")]) | |
6720 | ||
6721 | (define_insn "pool_end_31" | |
6722 | [(unspec_volatile [(const_int 0)] 207)] | |
6723 | "!TARGET_64BIT" | |
6724 | ".align\\t2" | |
6725 | [(set_attr "op_type" "NN") | |
6726 | (set_attr "length" "2")]) | |
6727 | ||
6728 | (define_insn "pool_start_64" | |
6729 | [(unspec_volatile [(const_int 0)] 206)] | |
6730 | "TARGET_64BIT" | |
6731 | ".section\\t.rodata\;.align\\t8" | |
6732 | [(set_attr "op_type" "NN") | |
6733 | (set_attr "length" "0")]) | |
6734 | ||
6735 | (define_insn "pool_end_64" | |
6736 | [(unspec_volatile [(const_int 0)] 207)] | |
6737 | "TARGET_64BIT" | |
6738 | ".previous" | |
6739 | [(set_attr "op_type" "NN") | |
6740 | (set_attr "length" "0")]) | |
6741 | ||
96be3ab6 | 6742 | (define_insn "reload_base_31" |
0756cebb | 6743 | [(set (match_operand:SI 0 "register_operand" "=a") |
6744 | (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))] | |
6745 | "!TARGET_64BIT" | |
6746 | "basr\\t%0,0\;la\\t%0,%1-.(%0)" | |
4673c1a0 | 6747 | [(set_attr "op_type" "NN") |
0756cebb | 6748 | (set_attr "type" "la") |
6749 | (set_attr "length" "6")]) | |
6750 | ||
96be3ab6 | 6751 | (define_insn "reload_base_64" |
6752 | [(set (match_operand:DI 0 "register_operand" "=a") | |
6753 | (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))] | |
6754 | "TARGET_64BIT" | |
6755 | "larl\\t%0,%1" | |
6756 | [(set_attr "op_type" "RIL") | |
6757 | (set_attr "type" "la")]) | |
6758 | ||
6759 | (define_insn "reload_anchor" | |
0756cebb | 6760 | [(set (match_operand:SI 0 "register_operand" "=a") |
96be3ab6 | 6761 | (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))] |
0756cebb | 6762 | "!TARGET_64BIT" |
96be3ab6 | 6763 | "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)" |
0756cebb | 6764 | [(set_attr "op_type" "NN") |
6765 | (set_attr "type" "la") | |
96be3ab6 | 6766 | (set_attr "length" "8")]) |
0756cebb | 6767 | |
96be3ab6 | 6768 | (define_insn "pool" |
6769 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)] | |
6770 | "" | |
6771 | "* abort ();" | |
6772 | [(set_attr "op_type" "NN") | |
6773 | (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
4673c1a0 | 6774 | |
8b4a4127 | 6775 | ;; |
6776 | ;; Insns related to generating the function prologue and epilogue. | |
6777 | ;; | |
6778 | ||
6779 | ||
6780 | (define_expand "prologue" | |
6781 | [(use (const_int 0))] | |
6782 | "" | |
6783 | " | |
6784 | { | |
6785 | s390_emit_prologue (); | |
6786 | DONE; | |
6787 | }") | |
6788 | ||
6789 | (define_expand "epilogue" | |
6790 | [(use (const_int 1))] | |
6791 | "" | |
6792 | " | |
6793 | { | |
6794 | s390_emit_epilogue (); | |
6795 | DONE; | |
6796 | }") | |
6797 | ||
6798 | ||
6799 | (define_insn "*return_si" | |
6800 | [(return) | |
6801 | (use (match_operand:SI 0 "register_operand" "a"))] | |
6802 | "!TARGET_64BIT" | |
6803 | "br\\t%0" | |
6804 | [(set_attr "op_type" "RR") | |
6805 | (set_attr "type" "jsr") | |
6806 | (set_attr "atype" "mem")]) | |
6807 | ||
6808 | (define_insn "*return_di" | |
6809 | [(return) | |
6810 | (use (match_operand:DI 0 "register_operand" "a"))] | |
6811 | "TARGET_64BIT" | |
6812 | "br\\t%0" | |
6813 | [(set_attr "op_type" "RR") | |
6814 | (set_attr "type" "jsr") | |
6815 | (set_attr "atype" "mem")]) | |
6816 | ||
5a5e802f | 6817 | (define_insn "literal_pool_31" |
6818 | [(unspec_volatile [(const_int 0)] 300) | |
6819 | (set (match_operand:SI 0 "register_operand" "=a") | |
6820 | (label_ref (match_operand 1 "" ""))) | |
6821 | (use (label_ref (match_operand 2 "" "")))] | |
8b4a4127 | 6822 | "" |
6823 | "* | |
6824 | { | |
5a5e802f | 6825 | if (s390_nr_constants) { |
6826 | output_asm_insn (\"bras\\t%0,%2\", operands); | |
6827 | s390_output_constant_pool (operands[1], operands[2]); | |
6828 | } | |
6829 | return \"\"; | |
8b4a4127 | 6830 | }" |
6831 | [(set_attr "op_type" "NN") | |
5a5e802f | 6832 | (set_attr "type" "la")]) |
8b4a4127 | 6833 | |
5a5e802f | 6834 | (define_insn "literal_pool_64" |
6835 | [(unspec_volatile [(const_int 0)] 300) | |
6836 | (set (match_operand:DI 0 "register_operand" "=a") | |
6837 | (label_ref (match_operand 1 "" ""))) | |
6838 | (use (label_ref (match_operand 2 "" "")))] | |
6839 | "" | |
6840 | "* | |
6841 | { | |
6842 | if (s390_nr_constants) { | |
6843 | output_asm_insn (\"larl\\t%0,%1\", operands); | |
6844 | s390_output_constant_pool (operands[1], operands[2]); | |
6845 | } | |
6846 | return \"\"; | |
6847 | }" | |
6848 | [(set_attr "op_type" "NN") | |
6849 | (set_attr "type" "la")]) |