projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
| 283334f0 KH |
2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 |
| 3 | ;; Free Software Foundation, Inc. | |
| 9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
| f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
| 9db1d521 | 6 | |
| 58add37a UW |
7 | ;; This file is part of GCC. |
| 8 | ||
| 9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
| 10 | ;; the terms of the GNU General Public License as published by the Free | |
| 11 | ;; Software Foundation; either version 2, or (at your option) any later | |
| 12 | ;; version. | |
| 13 | ||
| 14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
| 15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 17 | ;; for more details. | |
| 9db1d521 HP |
18 | |
| 19 | ;; You should have received a copy of the GNU General Public License | |
| 58add37a UW |
20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
| 21 | ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
| 22 | ;; 02111-1307, USA. | |
| 9db1d521 HP |
23 | |
| 24 | ;; | |
| 25 | ;; Special constraints for s/390 machine description: | |
| 26 | ;; | |
| 27 | ;; a -- Any address register from 1 to 15. | |
| 28 | ;; d -- Any register from 0 to 15. | |
| 29 | ;; I -- An 8-bit constant (0..255). | |
| 30 | ;; J -- A 12-bit constant (0..4095). | |
| 31 | ;; K -- A 16-bit constant (-32768..32767). | |
| 2f7e5a0d | 32 | ;; L -- Value appropriate as displacement. |
| f19a9af7 AK |
33 | ;; (0..4095) for short displacement |
| 34 | ;; (-524288..524287) for long displacement | |
| 35 | ;; M -- Constant integer with a value of 0x7fffffff. | |
| 36 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
| 37 | ;; 0..9: number of the part counting from most to least significant | |
| 38 | ;; H,Q: mode of the part | |
| 39 | ;; D,S,H: mode of the containing operand | |
| 40 | ;; 0,F: value of the other parts (F - all bits set) | |
| 2f7e5a0d | 41 | ;; |
| f19a9af7 AK |
42 | ;; The constraint matches if the specified part of a constant |
| 43 | ;; has a value different from its other parts. | |
| 44 | ;; Q -- Memory reference without index register and with short displacement. | |
| 45 | ;; R -- Memory reference with index register and short displacement. | |
| 46 | ;; S -- Memory reference without index register but with long displacement. | |
| 47 | ;; T -- Memory reference with index register and long displacement. | |
| 48 | ;; U -- Pointer with short displacement. | |
| 49 | ;; W -- Pointer with long displacement. | |
| 50 | ;; Y -- Shift count operand. | |
| 9db1d521 HP |
51 | ;; |
| 52 | ;; Special formats used for outputting 390 instructions. | |
| 53 | ;; | |
| f19a9af7 AK |
54 | ;; %C: print opcode suffix for branch condition. |
| 55 | ;; %D: print opcode suffix for inverse branch condition. | |
| 56 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
| 57 | ;; %O: print only the displacement of a memory reference. | |
| 58 | ;; %R: print only the base register of a memory reference. | |
| 59 | ;; %N: print the second word of a DImode operand. | |
| 60 | ;; %M: print the second word of a TImode operand. | |
| 61 | ||
| 62 | ;; %b: print integer X as if it's an unsigned byte. | |
| 63 | ;; %x: print integer X as if it's an unsigned word. | |
| 64 | ;; %h: print integer X as if it's a signed word. | |
| 65 | ;; %i: print the first nonzero HImode part of X | |
| 66 | ;; %j: print the first HImode part unequal to 0xffff of X | |
| 67 | ||
| 9db1d521 HP |
68 | ;; |
| 69 | ;; We have a special constraint for pattern matching. | |
| 70 | ;; | |
| 71 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
| 72 | ;; | |
| 9db1d521 | 73 | |
| fd3cd001 UW |
74 | ;; |
| 75 | ;; UNSPEC usage | |
| 76 | ;; | |
| 77 | ||
| 78 | (define_constants | |
| 10bbf137 UW |
79 | [; Miscellaneous |
| 80 | (UNSPEC_ROUND 1) | |
| 5b022de5 | 81 | (UNSPEC_CMPINT 2) |
| 10bbf137 UW |
82 | (UNSPEC_SETHIGH 10) |
| 83 | ||
| 84 | ; GOT/PLT and lt-relative accesses | |
| fd7643fb UW |
85 | (UNSPEC_LTREL_OFFSET 100) |
| 86 | (UNSPEC_LTREL_BASE 101) | |
| 87 | (UNSPEC_GOTENT 110) | |
| 88 | (UNSPEC_GOT 111) | |
| 89 | (UNSPEC_GOTOFF 112) | |
| 90 | (UNSPEC_PLT 113) | |
| 91 | (UNSPEC_PLTOFF 114) | |
| 92 | ||
| 93 | ; Literal pool | |
| 94 | (UNSPEC_RELOAD_BASE 210) | |
| 5af2f3d3 | 95 | (UNSPEC_MAIN_BASE 211) |
| 585539a1 | 96 | (UNSPEC_LTREF 212) |
| 9bb86f41 UW |
97 | (UNSPEC_INSN 213) |
| 98 | (UNSPEC_EXECUTE 214) | |
| fd7643fb UW |
99 | |
| 100 | ; TLS relocation specifiers | |
| fd3cd001 UW |
101 | (UNSPEC_TLSGD 500) |
| 102 | (UNSPEC_TLSLDM 501) | |
| 103 | (UNSPEC_NTPOFF 502) | |
| 104 | (UNSPEC_DTPOFF 503) | |
| 105 | (UNSPEC_GOTNTPOFF 504) | |
| 106 | (UNSPEC_INDNTPOFF 505) | |
| 107 | ||
| 108 | ; TLS support | |
| 109 | (UNSPEC_TP 510) | |
| 110 | (UNSPEC_TLSLDM_NTPOFF 511) | |
| 111 | (UNSPEC_TLS_LOAD 512) | |
| 91d39d71 UW |
112 | |
| 113 | ; String Functions | |
| 114 | (UNSPEC_SRST 600) | |
| fd3cd001 UW |
115 | ]) |
| 116 | ||
| 117 | ;; | |
| 118 | ;; UNSPEC_VOLATILE usage | |
| 119 | ;; | |
| 120 | ||
| 121 | (define_constants | |
| 10bbf137 UW |
122 | [; Blockage |
| 123 | (UNSPECV_BLOCKAGE 0) | |
| 124 | ||
| 2f7e5a0d EC |
125 | ; TPF Support |
| 126 | (UNSPECV_TPF_PROLOGUE 20) | |
| 127 | (UNSPECV_TPF_EPILOGUE 21) | |
| 128 | ||
| 10bbf137 | 129 | ; Literal pool |
| fd7643fb | 130 | (UNSPECV_POOL 200) |
| 9bb86f41 UW |
131 | (UNSPECV_POOL_SECTION 201) |
| 132 | (UNSPECV_POOL_ALIGN 202) | |
| 416cf582 | 133 | (UNSPECV_POOL_ENTRY 203) |
| fd7643fb UW |
134 | (UNSPECV_MAIN_POOL 300) |
| 135 | ||
| 136 | ; TLS support | |
| fd3cd001 UW |
137 | (UNSPECV_SET_TP 500) |
| 138 | ]) | |
| 139 | ||
| 140 | ||
| 1fec52be | 141 | ;; Processor type. This attribute must exactly match the processor_type |
| 64e1e4c4 SB |
142 | ;; enumeration in s390.h. The current machine description does not |
| 143 | ;; distinguish between g5 and g6, but there are differences between the two | |
| 144 | ;; CPUs could in theory be modeled. | |
| 1fec52be | 145 | |
| f13e0d4e UW |
146 | (define_attr "cpu" "g5,g6,z900,z990" |
| 147 | (const (symbol_ref "s390_tune"))) | |
| 9db1d521 | 148 | |
| f2d3c02a HP |
149 | ;; Define an insn type attribute. This is used in function unit delay |
| 150 | ;; computations. | |
| 9db1d521 | 151 | |
| 077dab3b HP |
152 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
| 153 | cs,vs,store,imul,idiv, | |
| 154 | branch,jsr,fsimpd,fsimps, | |
| 155 | floadd,floads,fstored, fstores, | |
| 156 | fmuld,fmuls,fdivd,fdivs, | |
| 157 | ftoi,itof,fsqrtd,fsqrts, | |
| 158 | other,o2,o3" | |
| c7453384 | 159 | (const_string "integer")) |
| 9db1d521 | 160 | |
| 077dab3b | 161 | ;; Operand type. Used to default length attribute values |
| 9db1d521 | 162 | |
| 077dab3b | 163 | (define_attr "op_type" |
| d3632d41 | 164 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" |
| 077dab3b HP |
165 | (const_string "RX")) |
| 166 | ||
| 167 | ;; Insn are devide in two classes: | |
| 168 | ;; agen: Insn using agen | |
| 169 | ;; reg: Insn not using agen | |
| 170 | ||
| 171 | (define_attr "atype" "agen,reg" | |
| 172 | (cond [ (eq_attr "op_type" "E") (const_string "reg") | |
| 173 | (eq_attr "op_type" "RR") (const_string "reg") | |
| 174 | (eq_attr "op_type" "RX") (const_string "agen") | |
| 175 | (eq_attr "op_type" "RI") (const_string "reg") | |
| 176 | (eq_attr "op_type" "RRE") (const_string "reg") | |
| 177 | (eq_attr "op_type" "RS") (const_string "agen") | |
| 178 | (eq_attr "op_type" "RSI") (const_string "agen") | |
| 179 | (eq_attr "op_type" "S") (const_string "agen") | |
| 180 | (eq_attr "op_type" "SI") (const_string "agen") | |
| 181 | (eq_attr "op_type" "SS") (const_string "agen") | |
| 182 | (eq_attr "op_type" "SSE") (const_string "agen") | |
| 183 | (eq_attr "op_type" "RXE") (const_string "agen") | |
| 184 | (eq_attr "op_type" "RSE") (const_string "agen") | |
| d3632d41 UW |
185 | (eq_attr "op_type" "RIL") (const_string "agen") |
| 186 | (eq_attr "op_type" "RXY") (const_string "agen") | |
| 187 | (eq_attr "op_type" "RSY") (const_string "agen") | |
| 188 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
| 077dab3b | 189 | (const_string "reg"))) |
| 9db1d521 | 190 | |
| 64e1e4c4 SB |
191 | ;; Pipeline description for z900. For lack of anything better, |
| 192 | ;; this description is also used for the g5 and g6. | |
| 077dab3b | 193 | (include "2064.md") |
| 64e1e4c4 SB |
194 | |
| 195 | ;; Pipeline description for z990. | |
| 52609473 | 196 | (include "2084.md") |
| 9db1d521 HP |
197 | |
| 198 | ;; Length in bytes. | |
| 199 | ||
| 200 | (define_attr "length" "" | |
| 201 | (cond [ (eq_attr "op_type" "E") (const_int 2) | |
| 202 | (eq_attr "op_type" "RR") (const_int 2) | |
| 203 | (eq_attr "op_type" "RX") (const_int 4) | |
| 204 | (eq_attr "op_type" "RI") (const_int 4) | |
| 205 | (eq_attr "op_type" "RRE") (const_int 4) | |
| 206 | (eq_attr "op_type" "RS") (const_int 4) | |
| 207 | (eq_attr "op_type" "RSI") (const_int 4) | |
| 9db1d521 HP |
208 | (eq_attr "op_type" "S") (const_int 4) |
| 209 | (eq_attr "op_type" "SI") (const_int 4) | |
| 210 | (eq_attr "op_type" "SS") (const_int 6) | |
| 211 | (eq_attr "op_type" "SSE") (const_int 6) | |
| 212 | (eq_attr "op_type" "RXE") (const_int 6) | |
| 213 | (eq_attr "op_type" "RSE") (const_int 6) | |
| d3632d41 UW |
214 | (eq_attr "op_type" "RIL") (const_int 6) |
| 215 | (eq_attr "op_type" "RXY") (const_int 6) | |
| 216 | (eq_attr "op_type" "RSY") (const_int 6) | |
| 217 | (eq_attr "op_type" "SIY") (const_int 6)] | |
| 9db1d521 HP |
218 | (const_int 4))) |
| 219 | ||
| 220 | ;; Define attributes for `asm' insns. | |
| 221 | ||
| f2d3c02a | 222 | (define_asm_attributes [(set_attr "type" "other") |
| 9db1d521 HP |
223 | (set_attr "op_type" "NN")]) |
| 224 | ||
| 225 | ;; | |
| 226 | ;; Condition Codes | |
| 227 | ;; | |
| 228 | ; | |
| 229 | ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) | |
| 230 | ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) | |
| 231 | ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) | |
| 232 | ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) | |
| 233 | ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) | |
| c7453384 | 234 | |
| 9db1d521 HP |
235 | ; CCZ -> CCL / CCZ1 |
| 236 | ; CCZ1 -> CCA/CCU/CCS/CCT | |
| 237 | ; CCS -> CCA | |
| c7453384 | 238 | |
| 9db1d521 HP |
239 | ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST |
| 240 | ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT | |
| 241 | ||
| 242 | ||
| 243 | ;; | |
| 244 | ;;- Compare instructions. | |
| 245 | ;; | |
| 246 | ||
| 247 | (define_expand "cmpdi" | |
| 248 | [(set (reg:CC 33) | |
| 249 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
| 250 | (match_operand:DI 1 "general_operand" "")))] | |
| 251 | "TARGET_64BIT" | |
| 9db1d521 HP |
252 | { |
| 253 | s390_compare_op0 = operands[0]; | |
| 254 | s390_compare_op1 = operands[1]; | |
| 255 | DONE; | |
| 10bbf137 | 256 | }) |
| 9db1d521 HP |
257 | |
| 258 | (define_expand "cmpsi" | |
| 259 | [(set (reg:CC 33) | |
| 260 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
| 261 | (match_operand:SI 1 "general_operand" "")))] | |
| 262 | "" | |
| 9db1d521 HP |
263 | { |
| 264 | s390_compare_op0 = operands[0]; | |
| 265 | s390_compare_op1 = operands[1]; | |
| 266 | DONE; | |
| 10bbf137 | 267 | }) |
| 9db1d521 | 268 | |
| 9db1d521 HP |
269 | (define_expand "cmpdf" |
| 270 | [(set (reg:CC 33) | |
| 271 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
| 272 | (match_operand:DF 1 "general_operand" "")))] | |
| 273 | "TARGET_HARD_FLOAT" | |
| 9db1d521 HP |
274 | { |
| 275 | s390_compare_op0 = operands[0]; | |
| 276 | s390_compare_op1 = operands[1]; | |
| 277 | DONE; | |
| 10bbf137 | 278 | }) |
| 9db1d521 HP |
279 | |
| 280 | (define_expand "cmpsf" | |
| 281 | [(set (reg:CC 33) | |
| 282 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
| 283 | (match_operand:SF 1 "general_operand" "")))] | |
| 284 | "TARGET_HARD_FLOAT" | |
| 9db1d521 HP |
285 | { |
| 286 | s390_compare_op0 = operands[0]; | |
| 287 | s390_compare_op1 = operands[1]; | |
| 288 | DONE; | |
| 10bbf137 | 289 | }) |
| 9db1d521 HP |
290 | |
| 291 | ||
| 07893d4f | 292 | ; Test-under-Mask instructions |
| 9db1d521 | 293 | |
| 07893d4f | 294 | (define_insn "*tmqi_mem" |
| 9db1d521 | 295 | [(set (reg 33) |
| 68f9c5e2 UW |
296 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
| 297 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
| 298 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
| 07893d4f | 299 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" |
| d3632d41 | 300 | "@ |
| d40c829f UW |
301 | tm\t%0,%b1 |
| 302 | tmy\t%0,%b1" | |
| d3632d41 | 303 | [(set_attr "op_type" "SI,SIY")]) |
| 9db1d521 | 304 | |
| 05b9aaaa UW |
305 | (define_insn "*tmdi_reg" |
| 306 | [(set (reg 33) | |
| f19a9af7 | 307 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
| 2f7e5a0d | 308 | (match_operand:DI 1 "immediate_operand" |
| f19a9af7 AK |
309 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
| 310 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
| 05b9aaaa UW |
311 | "TARGET_64BIT |
| 312 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
| f19a9af7 AK |
313 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
| 314 | "@ | |
| 315 | tmhh\t%0,%i1 | |
| 316 | tmhl\t%0,%i1 | |
| 317 | tmlh\t%0,%i1 | |
| 318 | tmll\t%0,%i1" | |
| 05b9aaaa UW |
319 | [(set_attr "op_type" "RI")]) |
| 320 | ||
| 321 | (define_insn "*tmsi_reg" | |
| 322 | [(set (reg 33) | |
| f19a9af7 AK |
323 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
| 324 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
| 325 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
| 05b9aaaa | 326 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) |
| f19a9af7 AK |
327 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
| 328 | "@ | |
| 329 | tmh\t%0,%i1 | |
| 330 | tml\t%0,%i1" | |
| 05b9aaaa UW |
331 | [(set_attr "op_type" "RI")]) |
| 332 | ||
| 07893d4f | 333 | (define_insn "*tmhi_full" |
| 9db1d521 | 334 | [(set (reg 33) |
| 07893d4f UW |
335 | (compare (match_operand:HI 0 "register_operand" "d") |
| 336 | (match_operand:HI 1 "immediate_operand" "n")))] | |
| a556fd39 | 337 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
| d40c829f | 338 | "tml\t%0,65535" |
| 07893d4f | 339 | [(set_attr "op_type" "RX")]) |
| 9db1d521 | 340 | |
| 07893d4f | 341 | (define_insn "*tmqi_full" |
| 9db1d521 | 342 | [(set (reg 33) |
| 07893d4f UW |
343 | (compare (match_operand:QI 0 "register_operand" "d") |
| 344 | (match_operand:QI 1 "immediate_operand" "n")))] | |
| a556fd39 | 345 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
| d40c829f | 346 | "tml\t%0,255" |
| 07893d4f | 347 | [(set_attr "op_type" "RI")]) |
| 9db1d521 | 348 | |
| 07893d4f UW |
349 | |
| 350 | ; Load-and-Test instructions | |
| 351 | ||
| 352 | (define_insn "*tstdi_sign" | |
| 9db1d521 | 353 | [(set (reg 33) |
| 07893d4f UW |
354 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
| 355 | (const_int 32)) (const_int 32)) | |
| 356 | (match_operand:DI 1 "const0_operand" ""))) | |
| 357 | (set (match_operand:DI 2 "register_operand" "=d") | |
| 358 | (sign_extend:DI (match_dup 0)))] | |
| 359 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
| d40c829f | 360 | "ltgfr\t%2,%0" |
| 07893d4f UW |
361 | [(set_attr "op_type" "RRE")]) |
| 362 | ||
| 363 | (define_insn "*tstdi" | |
| 9db1d521 | 364 | [(set (reg 33) |
| 07893d4f UW |
365 | (compare (match_operand:DI 0 "register_operand" "d") |
| 366 | (match_operand:DI 1 "const0_operand" ""))) | |
| 367 | (set (match_operand:DI 2 "register_operand" "=d") | |
| 368 | (match_dup 0))] | |
| 369 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
| d40c829f | 370 | "ltgr\t%2,%0" |
| 07893d4f | 371 | [(set_attr "op_type" "RRE")]) |
| 9db1d521 | 372 | |
| 07893d4f | 373 | (define_insn "*tstdi_cconly" |
| 9db1d521 | 374 | [(set (reg 33) |
| 07893d4f UW |
375 | (compare (match_operand:DI 0 "register_operand" "d") |
| 376 | (match_operand:DI 1 "const0_operand" "")))] | |
| 377 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
| d40c829f | 378 | "ltgr\t%0,%0" |
| 07893d4f | 379 | [(set_attr "op_type" "RRE")]) |
| 9db1d521 | 380 | |
| 07893d4f UW |
381 | (define_insn "*tstdi_cconly_31" |
| 382 | [(set (reg 33) | |
| 383 | (compare (match_operand:DI 0 "register_operand" "d") | |
| 384 | (match_operand:DI 1 "const0_operand" "")))] | |
| 385 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
| d40c829f | 386 | "srda\t%0,0" |
| 077dab3b HP |
387 | [(set_attr "op_type" "RS") |
| 388 | (set_attr "atype" "reg")]) | |
| 389 | ||
| 4023fb28 | 390 | |
| 07893d4f UW |
391 | (define_insn "*tstsi" |
| 392 | [(set (reg 33) | |
| d3632d41 | 393 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
| 07893d4f | 394 | (match_operand:SI 1 "const0_operand" ""))) |
| d3632d41 | 395 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
| 07893d4f UW |
396 | (match_dup 0))] |
| 397 | "s390_match_ccmode(insn, CCSmode)" | |
| 398 | "@ | |
| d40c829f UW |
399 | ltr\t%2,%0 |
| 400 | icm\t%2,15,%0 | |
| 401 | icmy\t%2,15,%0" | |
| d3632d41 | 402 | [(set_attr "op_type" "RR,RS,RSY")]) |
| 9db1d521 | 403 | |
| 07893d4f | 404 | (define_insn "*tstsi_cconly" |
| 4023fb28 | 405 | [(set (reg 33) |
| d3632d41 | 406 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
| 07893d4f | 407 | (match_operand:SI 1 "const0_operand" ""))) |
| d3632d41 | 408 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
| 07893d4f UW |
409 | "s390_match_ccmode(insn, CCSmode)" |
| 410 | "@ | |
| d40c829f UW |
411 | ltr\t%0,%0 |
| 412 | icm\t%2,15,%0 | |
| 413 | icmy\t%2,15,%0" | |
| d3632d41 | 414 | [(set_attr "op_type" "RR,RS,RSY")]) |
| 4023fb28 | 415 | |
| 07893d4f UW |
416 | (define_insn "*tstsi_cconly2" |
| 417 | [(set (reg 33) | |
| 418 | (compare (match_operand:SI 0 "register_operand" "d") | |
| 419 | (match_operand:SI 1 "const0_operand" "")))] | |
| 420 | "s390_match_ccmode(insn, CCSmode)" | |
| d40c829f | 421 | "ltr\t%0,%0" |
| 07893d4f | 422 | [(set_attr "op_type" "RR")]) |
| 4023fb28 | 423 | |
| 3af97654 UW |
424 | (define_insn "*tsthiCCT" |
| 425 | [(set (reg 33) | |
| d3632d41 | 426 | (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d") |
| 3af97654 | 427 | (match_operand:HI 1 "const0_operand" ""))) |
| d3632d41 | 428 | (set (match_operand:HI 2 "register_operand" "=d,d,0") |
| 3af97654 UW |
429 | (match_dup 0))] |
| 430 | "s390_match_ccmode(insn, CCTmode)" | |
| 431 | "@ | |
| d40c829f UW |
432 | icm\t%2,3,%0 |
| 433 | icmy\t%2,3,%0 | |
| 434 | tml\t%0,65535" | |
| d3632d41 | 435 | [(set_attr "op_type" "RS,RSY,RI")]) |
| 3af97654 UW |
436 | |
| 437 | (define_insn "*tsthiCCT_cconly" | |
| 438 | [(set (reg 33) | |
| d3632d41 | 439 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
| 3af97654 | 440 | (match_operand:HI 1 "const0_operand" ""))) |
| d3632d41 | 441 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
| 3af97654 UW |
442 | "s390_match_ccmode(insn, CCTmode)" |
| 443 | "@ | |
| d40c829f UW |
444 | icm\t%2,3,%0 |
| 445 | icmy\t%2,3,%0 | |
| 446 | tml\t%0,65535" | |
| d3632d41 | 447 | [(set_attr "op_type" "RS,RSY,RI")]) |
| 3af97654 | 448 | |
| 07893d4f | 449 | (define_insn "*tsthi" |
| 9db1d521 | 450 | [(set (reg 33) |
| d3632d41 | 451 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
| 9db1d521 | 452 | (match_operand:HI 1 "const0_operand" ""))) |
| d3632d41 | 453 | (set (match_operand:HI 2 "register_operand" "=d,d") |
| 9db1d521 HP |
454 | (match_dup 0))] |
| 455 | "s390_match_ccmode(insn, CCSmode)" | |
| d3632d41 | 456 | "@ |
| d40c829f UW |
457 | icm\t%2,3,%0 |
| 458 | icmy\t%2,3,%0" | |
| d3632d41 | 459 | [(set_attr "op_type" "RS,RSY")]) |
| 9db1d521 | 460 | |
| 07893d4f | 461 | (define_insn "*tsthi_cconly" |
| 9db1d521 | 462 | [(set (reg 33) |
| d3632d41 | 463 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
| 9db1d521 | 464 | (match_operand:HI 1 "const0_operand" ""))) |
| d3632d41 | 465 | (clobber (match_scratch:HI 2 "=d,d"))] |
| 9db1d521 | 466 | "s390_match_ccmode(insn, CCSmode)" |
| d3632d41 | 467 | "@ |
| d40c829f UW |
468 | icm\t%2,3,%0 |
| 469 | icmy\t%2,3,%0" | |
| d3632d41 | 470 | [(set_attr "op_type" "RS,RSY")]) |
| 9db1d521 | 471 | |
| 3af97654 UW |
472 | (define_insn "*tstqiCCT" |
| 473 | [(set (reg 33) | |
| d3632d41 | 474 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
| 3af97654 | 475 | (match_operand:QI 1 "const0_operand" ""))) |
| d3632d41 | 476 | (set (match_operand:QI 2 "register_operand" "=d,d,0") |
| 3af97654 UW |
477 | (match_dup 0))] |
| 478 | "s390_match_ccmode(insn, CCTmode)" | |
| 479 | "@ | |
| d40c829f UW |
480 | icm\t%2,1,%0 |
| 481 | icmy\t%2,1,%0 | |
| 482 | tml\t%0,255" | |
| d3632d41 | 483 | [(set_attr "op_type" "RS,RSY,RI")]) |
| 3af97654 UW |
484 | |
| 485 | (define_insn "*tstqiCCT_cconly" | |
| 486 | [(set (reg 33) | |
| d3632d41 | 487 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
| 3af97654 UW |
488 | (match_operand:QI 1 "const0_operand" "")))] |
| 489 | "s390_match_ccmode(insn, CCTmode)" | |
| 490 | "@ | |
| d40c829f UW |
491 | cli\t%0,0 |
| 492 | cliy\t%0,0 | |
| 493 | tml\t%0,255" | |
| d3632d41 | 494 | [(set_attr "op_type" "SI,SIY,RI")]) |
| 3af97654 | 495 | |
| 07893d4f | 496 | (define_insn "*tstqi" |
| 9db1d521 | 497 | [(set (reg 33) |
| d3632d41 | 498 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
| 07893d4f | 499 | (match_operand:QI 1 "const0_operand" ""))) |
| d3632d41 | 500 | (set (match_operand:QI 2 "register_operand" "=d,d") |
| 07893d4f UW |
501 | (match_dup 0))] |
| 502 | "s390_match_ccmode(insn, CCSmode)" | |
| d3632d41 | 503 | "@ |
| d40c829f UW |
504 | icm\t%2,1,%0 |
| 505 | icmy\t%2,1,%0" | |
| d3632d41 | 506 | [(set_attr "op_type" "RS,RSY")]) |
| 9db1d521 | 507 | |
| 07893d4f | 508 | (define_insn "*tstqi_cconly" |
| 9db1d521 | 509 | [(set (reg 33) |
| d3632d41 | 510 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
| 07893d4f | 511 | (match_operand:QI 1 "const0_operand" ""))) |
| d3632d41 | 512 | (clobber (match_scratch:QI 2 "=d,d"))] |
| 07893d4f | 513 | "s390_match_ccmode(insn, CCSmode)" |
| d3632d41 | 514 | "@ |
| d40c829f UW |
515 | icm\t%2,1,%0 |
| 516 | icmy\t%2,1,%0" | |
| d3632d41 UW |
517 | [(set_attr "op_type" "RS,RSY")]) |
| 518 | ||
| 9db1d521 | 519 | |
| 575f7c2b UW |
520 | ; Compare (equality) instructions |
| 521 | ||
| 522 | (define_insn "*cmpdi_cct" | |
| 523 | [(set (reg 33) | |
| 524 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,m,Q") | |
| 525 | (match_operand:DI 1 "general_operand" "d,K,m,d,Q")))] | |
| 526 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT | |
| 527 | && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))" | |
| 528 | "@ | |
| 529 | cgr\t%0,%1 | |
| 530 | cghi\t%0,%c1 | |
| 531 | cg\t%0,%1 | |
| 532 | cg\t%1,%0 | |
| 533 | clc\t%O0(8,%R0),%1" | |
| 534 | [(set_attr "op_type" "RRE,RI,RXY,RXY,SS")]) | |
| 535 | ||
| 536 | (define_insn "*cmpsi_cct" | |
| 537 | [(set (reg 33) | |
| 538 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,R,T,Q") | |
| 539 | (match_operand:SI 1 "general_operand" "d,K,R,T,d,d,Q")))] | |
| 540 | "s390_match_ccmode (insn, CCTmode) | |
| 541 | && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))" | |
| 542 | "@ | |
| 543 | cr\t%0,%1 | |
| 544 | chi\t%0,%c1 | |
| 545 | c\t%0,%1 | |
| 546 | cy\t%0,%1 | |
| 547 | c\t%1,%0 | |
| 548 | cy\t%1,%0 | |
| 549 | clc\t%O0(4,%R0),%1" | |
| 550 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")]) | |
| 551 | ||
| 552 | ||
| 07893d4f | 553 | ; Compare (signed) instructions |
| 4023fb28 | 554 | |
| 07893d4f | 555 | (define_insn "*cmpdi_ccs_sign" |
| 4023fb28 | 556 | [(set (reg 33) |
| 07893d4f UW |
557 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
| 558 | (match_operand:DI 0 "register_operand" "d,d")))] | |
| 559 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
| 4023fb28 | 560 | "@ |
| d40c829f UW |
561 | cgfr\t%0,%1 |
| 562 | cgf\t%0,%1" | |
| d3632d41 | 563 | [(set_attr "op_type" "RRE,RXY")]) |
| 4023fb28 | 564 | |
| 07893d4f | 565 | (define_insn "*cmpdi_ccs" |
| 4023fb28 | 566 | [(set (reg 33) |
| 07893d4f UW |
567 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
| 568 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
| 569 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
| 570 | "@ | |
| d40c829f UW |
571 | cgr\t%0,%1 |
| 572 | cghi\t%0,%c1 | |
| 573 | cg\t%0,%1" | |
| d3632d41 | 574 | [(set_attr "op_type" "RRE,RI,RXY")]) |
| c7453384 | 575 | |
| 07893d4f UW |
576 | (define_insn "*cmpsi_ccs_sign" |
| 577 | [(set (reg 33) | |
| d3632d41 UW |
578 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
| 579 | (match_operand:SI 0 "register_operand" "d,d")))] | |
| 07893d4f | 580 | "s390_match_ccmode(insn, CCSRmode)" |
| d3632d41 | 581 | "@ |
| d40c829f UW |
582 | ch\t%0,%1 |
| 583 | chy\t%0,%1" | |
| d3632d41 | 584 | [(set_attr "op_type" "RX,RXY")]) |
| 4023fb28 | 585 | |
| 07893d4f | 586 | (define_insn "*cmpsi_ccs" |
| 9db1d521 | 587 | [(set (reg 33) |
| d3632d41 UW |
588 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
| 589 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
| 9db1d521 | 590 | "s390_match_ccmode(insn, CCSmode)" |
| 07893d4f | 591 | "@ |
| d40c829f UW |
592 | cr\t%0,%1 |
| 593 | chi\t%0,%c1 | |
| 594 | c\t%0,%1 | |
| 595 | cy\t%0,%1" | |
| d3632d41 | 596 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
| c7453384 | 597 | |
| 07893d4f UW |
598 | |
| 599 | ; Compare (unsigned) instructions | |
| 9db1d521 | 600 | |
| 07893d4f | 601 | (define_insn "*cmpdi_ccu_zero" |
| 9db1d521 | 602 | [(set (reg 33) |
| 07893d4f UW |
603 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
| 604 | (match_operand:DI 0 "register_operand" "d,d")))] | |
| 575f7c2b | 605 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
| 07893d4f | 606 | "@ |
| d40c829f UW |
607 | clgfr\t%0,%1 |
| 608 | clgf\t%0,%1" | |
| d3632d41 | 609 | [(set_attr "op_type" "RRE,RXY")]) |
| 9db1d521 | 610 | |
| 07893d4f | 611 | (define_insn "*cmpdi_ccu" |
| 9db1d521 | 612 | [(set (reg 33) |
| 575f7c2b UW |
613 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q") |
| 614 | (match_operand:DI 1 "general_operand" "d,m,Q")))] | |
| 615 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT | |
| 616 | && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))" | |
| 07893d4f | 617 | "@ |
| d40c829f | 618 | clgr\t%0,%1 |
| 575f7c2b UW |
619 | clg\t%0,%1 |
| 620 | clc\t%O0(8,%R0),%1" | |
| 621 | [(set_attr "op_type" "RRE,RXY,SS")]) | |
| 9db1d521 | 622 | |
| 07893d4f | 623 | (define_insn "*cmpsi_ccu" |
| 9db1d521 | 624 | [(set (reg 33) |
| 575f7c2b UW |
625 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q") |
| 626 | (match_operand:SI 1 "general_operand" "d,R,T,Q")))] | |
| 627 | "s390_match_ccmode (insn, CCUmode) | |
| 628 | && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1]))" | |
| 07893d4f | 629 | "@ |
| d40c829f UW |
630 | clr\t%0,%1 |
| 631 | cl\t%0,%1 | |
| 575f7c2b UW |
632 | cly\t%0,%1 |
| 633 | clc\t%O0(4,%R0),%1" | |
| 634 | [(set_attr "op_type" "RR,RX,RXY,SS")]) | |
| 9db1d521 | 635 | |
| 07893d4f | 636 | (define_insn "*cmphi_ccu" |
| 9db1d521 | 637 | [(set (reg 33) |
| 575f7c2b UW |
638 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q") |
| 639 | (match_operand:HI 1 "general_operand" "Q,S,Q")))] | |
| 640 | "s390_match_ccmode (insn, CCUmode) | |
| 641 | && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1])) | |
| 642 | && !register_operand (operands[1], HImode)" | |
| d3632d41 | 643 | "@ |
| d40c829f | 644 | clm\t%0,3,%1 |
| 575f7c2b UW |
645 | clmy\t%0,3,%1 |
| 646 | clc\t%O0(2,%R0),%1" | |
| 647 | [(set_attr "op_type" "RS,RSY,SS")]) | |
| 9db1d521 HP |
648 | |
| 649 | (define_insn "*cmpqi_ccu" | |
| 650 | [(set (reg 33) | |
| 575f7c2b UW |
651 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q") |
| 652 | (match_operand:QI 1 "general_operand" "Q,S,n,n,Q")))] | |
| 653 | "s390_match_ccmode (insn, CCUmode) | |
| 654 | && (!s390_pool_operand (operands[0]) || !s390_pool_operand (operands[1])) | |
| 655 | && !register_operand (operands[1], QImode)" | |
| d3632d41 | 656 | "@ |
| d40c829f | 657 | clm\t%0,1,%1 |
| 575f7c2b | 658 | clmy\t%0,1,%1 |
| d40c829f | 659 | cli\t%0,%b1 |
| 575f7c2b UW |
660 | cliy\t%0,%b1 |
| 661 | clc\t%O0(1,%R0),%1" | |
| 662 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS")]) | |
| 9db1d521 HP |
663 | |
| 664 | ||
| 665 | ; DF instructions | |
| 666 | ||
| 667 | (define_insn "*cmpdf_ccs_0" | |
| 668 | [(set (reg 33) | |
| 669 | (compare (match_operand:DF 0 "register_operand" "f") | |
| 670 | (match_operand:DF 1 "const0_operand" "")))] | |
| 671 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 672 | "ltdbr\t%0,%0" |
| 077dab3b HP |
673 | [(set_attr "op_type" "RRE") |
| 674 | (set_attr "type" "fsimpd")]) | |
| 9db1d521 HP |
675 | |
| 676 | (define_insn "*cmpdf_ccs_0_ibm" | |
| 677 | [(set (reg 33) | |
| 678 | (compare (match_operand:DF 0 "register_operand" "f") | |
| 679 | (match_operand:DF 1 "const0_operand" "")))] | |
| 680 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| d40c829f | 681 | "ltdr\t%0,%0" |
| 077dab3b HP |
682 | [(set_attr "op_type" "RR") |
| 683 | (set_attr "type" "fsimpd")]) | |
| 9db1d521 HP |
684 | |
| 685 | (define_insn "*cmpdf_ccs" | |
| 686 | [(set (reg 33) | |
| 687 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
| d3632d41 | 688 | (match_operand:DF 1 "general_operand" "f,R")))] |
| 9db1d521 HP |
689 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 690 | "@ | |
| d40c829f UW |
691 | cdbr\t%0,%1 |
| 692 | cdb\t%0,%1" | |
| ce50cae8 | 693 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 694 | (set_attr "type" "fsimpd")]) |
| 9db1d521 HP |
695 | |
| 696 | (define_insn "*cmpdf_ccs_ibm" | |
| 697 | [(set (reg 33) | |
| 698 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
| d3632d41 | 699 | (match_operand:DF 1 "general_operand" "f,R")))] |
| 9db1d521 HP |
700 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 701 | "@ | |
| d40c829f UW |
702 | cdr\t%0,%1 |
| 703 | cd\t%0,%1" | |
| 9db1d521 | 704 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 705 | (set_attr "type" "fsimpd")]) |
| 9db1d521 HP |
706 | |
| 707 | ||
| 708 | ; SF instructions | |
| 709 | ||
| 710 | (define_insn "*cmpsf_ccs_0" | |
| 711 | [(set (reg 33) | |
| 712 | (compare (match_operand:SF 0 "register_operand" "f") | |
| 713 | (match_operand:SF 1 "const0_operand" "")))] | |
| 714 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 715 | "ltebr\t%0,%0" |
| 077dab3b HP |
716 | [(set_attr "op_type" "RRE") |
| 717 | (set_attr "type" "fsimps")]) | |
| 9db1d521 HP |
718 | |
| 719 | (define_insn "*cmpsf_ccs_0_ibm" | |
| 720 | [(set (reg 33) | |
| 721 | (compare (match_operand:SF 0 "register_operand" "f") | |
| 722 | (match_operand:SF 1 "const0_operand" "")))] | |
| 723 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| d40c829f | 724 | "lter\t%0,%0" |
| 077dab3b HP |
725 | [(set_attr "op_type" "RR") |
| 726 | (set_attr "type" "fsimps")]) | |
| 9db1d521 HP |
727 | |
| 728 | (define_insn "*cmpsf_ccs" | |
| 729 | [(set (reg 33) | |
| 730 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
| d3632d41 | 731 | (match_operand:SF 1 "general_operand" "f,R")))] |
| 9db1d521 HP |
732 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 733 | "@ | |
| d40c829f UW |
734 | cebr\t%0,%1 |
| 735 | ceb\t%0,%1" | |
| 077dab3b HP |
736 | [(set_attr "op_type" "RRE,RXE") |
| 737 | (set_attr "type" "fsimps")]) | |
| 9db1d521 HP |
738 | |
| 739 | (define_insn "*cmpsf_ccs" | |
| 740 | [(set (reg 33) | |
| 741 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
| d3632d41 | 742 | (match_operand:SF 1 "general_operand" "f,R")))] |
| 9db1d521 HP |
743 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 744 | "@ | |
| d40c829f UW |
745 | cer\t%0,%1 |
| 746 | ce\t%0,%1" | |
| 077dab3b HP |
747 | [(set_attr "op_type" "RR,RX") |
| 748 | (set_attr "type" "fsimps")]) | |
| 9db1d521 HP |
749 | |
| 750 | ||
| 751 | ;; | |
| 752 | ;;- Move instructions. | |
| 753 | ;; | |
| 754 | ||
| 755 | ; | |
| 756 | ; movti instruction pattern(s). | |
| 757 | ; | |
| 758 | ||
| 759 | (define_insn "movti" | |
| d3632d41 UW |
760 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
| 761 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
| 9db1d521 | 762 | "TARGET_64BIT" |
| 4023fb28 | 763 | "@ |
| d40c829f UW |
764 | lmg\t%0,%N0,%1 |
| 765 | stmg\t%1,%N1,%0 | |
| 4023fb28 | 766 | # |
| 9b7c75b9 | 767 | # |
| d40c829f | 768 | mvc\t%O0(16,%R0),%1" |
| d3632d41 | 769 | [(set_attr "op_type" "RSY,RSY,NN,NN,SS") |
| fe03d631 | 770 | (set_attr "type" "lm,stm,*,*,cs")]) |
| 4023fb28 UW |
771 | |
| 772 | (define_split | |
| 773 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
| 774 | (match_operand:TI 1 "general_operand" ""))] | |
| 775 | "TARGET_64BIT && reload_completed | |
| dc65c307 | 776 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
| 4023fb28 UW |
777 | [(set (match_dup 2) (match_dup 4)) |
| 778 | (set (match_dup 3) (match_dup 5))] | |
| 9db1d521 | 779 | { |
| dc65c307 UW |
780 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
| 781 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
| 782 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
| 783 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
| 784 | }) | |
| 785 | ||
| 786 | (define_split | |
| 787 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
| 788 | (match_operand:TI 1 "general_operand" ""))] | |
| 789 | "TARGET_64BIT && reload_completed | |
| 790 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
| 791 | [(set (match_dup 2) (match_dup 4)) | |
| 792 | (set (match_dup 3) (match_dup 5))] | |
| 793 | { | |
| 794 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
| 795 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
| 796 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
| 797 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
| 798 | }) | |
| 4023fb28 UW |
799 | |
| 800 | (define_split | |
| 801 | [(set (match_operand:TI 0 "register_operand" "") | |
| 802 | (match_operand:TI 1 "memory_operand" ""))] | |
| 803 | "TARGET_64BIT && reload_completed | |
| 804 | && !s_operand (operands[1], VOIDmode)" | |
| a41c6c53 | 805 | [(set (match_dup 0) (match_dup 1))] |
| a41c6c53 UW |
806 | { |
| 807 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
| 808 | s390_load_address (addr, XEXP (operands[1], 0)); | |
| 809 | operands[1] = replace_equiv_address (operands[1], addr); | |
| dc65c307 UW |
810 | }) |
| 811 | ||
| 812 | (define_expand "reload_outti" | |
| 813 | [(parallel [(match_operand:TI 0 "memory_operand" "") | |
| 814 | (match_operand:TI 1 "register_operand" "d") | |
| 815 | (match_operand:DI 2 "register_operand" "=&a")])] | |
| 816 | "TARGET_64BIT" | |
| 817 | { | |
| 818 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
| 819 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
| 820 | emit_move_insn (operands[0], operands[1]); | |
| 821 | DONE; | |
| 822 | }) | |
| 9db1d521 HP |
823 | |
| 824 | ; | |
| 825 | ; movdi instruction pattern(s). | |
| 826 | ; | |
| 827 | ||
| 9db1d521 HP |
828 | (define_expand "movdi" |
| 829 | [(set (match_operand:DI 0 "general_operand" "") | |
| 830 | (match_operand:DI 1 "general_operand" ""))] | |
| 831 | "" | |
| 9db1d521 | 832 | { |
| fd3cd001 UW |
833 | /* Handle symbolic constants. */ |
| 834 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
| 835 | emit_symbolic_move (operands); | |
| 10bbf137 | 836 | }) |
| 9db1d521 | 837 | |
| 4023fb28 UW |
838 | (define_insn "*movdi_larl" |
| 839 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 840 | (match_operand:DI 1 "larl_operand" "X"))] | |
| 841 | "TARGET_64BIT | |
| 8e509cf9 | 842 | && !FP_REG_P (operands[0])" |
| d40c829f | 843 | "larl\t%0,%1" |
| 4023fb28 | 844 | [(set_attr "op_type" "RIL") |
| 077dab3b | 845 | (set_attr "type" "larl")]) |
| 4023fb28 | 846 | |
| 9db1d521 | 847 | (define_insn "*movdi_64" |
| 2f7e5a0d | 848 | [(set (match_operand:DI 0 "nonimmediate_operand" |
| f19a9af7 | 849 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q") |
| 2f7e5a0d | 850 | (match_operand:DI 1 "general_operand" |
| f19a9af7 | 851 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))] |
| 9db1d521 HP |
852 | "TARGET_64BIT" |
| 853 | "@ | |
| f19a9af7 AK |
854 | lghi\t%0,%h1 |
| 855 | llihh\t%0,%i1 | |
| 856 | llihl\t%0,%i1 | |
| 857 | llilh\t%0,%i1 | |
| 858 | llill\t%0,%i1 | |
| 859 | lay\t%0,%a1 | |
| d40c829f UW |
860 | lgr\t%0,%1 |
| 861 | lg\t%0,%1 | |
| 862 | stg\t%1,%0 | |
| 863 | ldr\t%0,%1 | |
| 864 | ld\t%0,%1 | |
| 865 | ldy\t%0,%1 | |
| 866 | std\t%1,%0 | |
| 867 | stdy\t%1,%0 | |
| 868 | mvc\t%O0(8,%R0),%1" | |
| f19a9af7 AK |
869 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS") |
| 870 | (set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd, | |
| 871 | fstored,fstored,cs")]) | |
| 9db1d521 HP |
872 | |
| 873 | (define_insn "*movdi_31" | |
| d3632d41 UW |
874 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
| 875 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
| 9db1d521 | 876 | "!TARGET_64BIT" |
| 4023fb28 | 877 | "@ |
| d40c829f UW |
878 | lm\t%0,%N0,%1 |
| 879 | stm\t%1,%N1,%0 | |
| 4023fb28 UW |
880 | # |
| 881 | # | |
| d40c829f UW |
882 | ldr\t%0,%1 |
| 883 | ld\t%0,%1 | |
| 884 | ldy\t%0,%1 | |
| 885 | std\t%1,%0 | |
| 886 | stdy\t%1,%0 | |
| 887 | mvc\t%O0(8,%R0),%1" | |
| d3632d41 UW |
888 | [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS") |
| 889 | (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")]) | |
| 4023fb28 UW |
890 | |
| 891 | (define_split | |
| 892 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
| 893 | (match_operand:DI 1 "general_operand" ""))] | |
| 894 | "!TARGET_64BIT && reload_completed | |
| dc65c307 | 895 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
| 4023fb28 UW |
896 | [(set (match_dup 2) (match_dup 4)) |
| 897 | (set (match_dup 3) (match_dup 5))] | |
| 9db1d521 | 898 | { |
| dc65c307 UW |
899 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
| 900 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
| 901 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
| 902 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
| 903 | }) | |
| 904 | ||
| 905 | (define_split | |
| 906 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
| 907 | (match_operand:DI 1 "general_operand" ""))] | |
| 908 | "!TARGET_64BIT && reload_completed | |
| 909 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
| 910 | [(set (match_dup 2) (match_dup 4)) | |
| 911 | (set (match_dup 3) (match_dup 5))] | |
| 912 | { | |
| 913 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
| 914 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
| 915 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
| 916 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
| 917 | }) | |
| 9db1d521 | 918 | |
| 4023fb28 UW |
919 | (define_split |
| 920 | [(set (match_operand:DI 0 "register_operand" "") | |
| 921 | (match_operand:DI 1 "memory_operand" ""))] | |
| 922 | "!TARGET_64BIT && reload_completed | |
| 8e509cf9 | 923 | && !FP_REG_P (operands[0]) |
| 4023fb28 | 924 | && !s_operand (operands[1], VOIDmode)" |
| a41c6c53 | 925 | [(set (match_dup 0) (match_dup 1))] |
| a41c6c53 UW |
926 | { |
| 927 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
| 928 | s390_load_address (addr, XEXP (operands[1], 0)); | |
| 929 | operands[1] = replace_equiv_address (operands[1], addr); | |
| dc65c307 UW |
930 | }) |
| 931 | ||
| 932 | (define_expand "reload_outdi" | |
| 933 | [(parallel [(match_operand:DI 0 "memory_operand" "") | |
| 934 | (match_operand:DI 1 "register_operand" "d") | |
| 935 | (match_operand:SI 2 "register_operand" "=&a")])] | |
| 936 | "!TARGET_64BIT" | |
| 937 | { | |
| 938 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
| 939 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
| 940 | emit_move_insn (operands[0], operands[1]); | |
| 941 | DONE; | |
| 942 | }) | |
| 9db1d521 | 943 | |
| 84817c5d UW |
944 | (define_peephole2 |
| 945 | [(set (match_operand:DI 0 "register_operand" "") | |
| 946 | (mem:DI (match_operand 1 "address_operand" "")))] | |
| 947 | "TARGET_64BIT | |
| 948 | && !FP_REG_P (operands[0]) | |
| 949 | && GET_CODE (operands[1]) == SYMBOL_REF | |
| 950 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
| 951 | && get_pool_mode (operands[1]) == DImode | |
| 952 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
| 953 | [(set (match_dup 0) (match_dup 2))] | |
| 954 | "operands[2] = get_pool_constant (operands[1]);") | |
| 955 | ||
| 7bdff56f UW |
956 | (define_insn "*la_64" |
| 957 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 958 | (match_operand:QI 1 "address_operand" "U,W"))] | |
| 959 | "TARGET_64BIT" | |
| 960 | "@ | |
| 961 | la\t%0,%a1 | |
| 962 | lay\t%0,%a1" | |
| 963 | [(set_attr "op_type" "RX,RXY") | |
| 964 | (set_attr "type" "la")]) | |
| 965 | ||
| 966 | (define_peephole2 | |
| 967 | [(parallel | |
| 968 | [(set (match_operand:DI 0 "register_operand" "") | |
| 969 | (match_operand:QI 1 "address_operand" "")) | |
| 970 | (clobber (reg:CC 33))])] | |
| 971 | "TARGET_64BIT | |
| e1d5ee28 | 972 | && preferred_la_operand_p (operands[1], const0_rtx)" |
| 7bdff56f UW |
973 | [(set (match_dup 0) (match_dup 1))] |
| 974 | "") | |
| 975 | ||
| 976 | (define_peephole2 | |
| 977 | [(set (match_operand:DI 0 "register_operand" "") | |
| 978 | (match_operand:DI 1 "register_operand" "")) | |
| 979 | (parallel | |
| 980 | [(set (match_dup 0) | |
| 981 | (plus:DI (match_dup 0) | |
| 982 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
| 983 | (clobber (reg:CC 33))])] | |
| 984 | "TARGET_64BIT | |
| 985 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
| e1d5ee28 | 986 | && preferred_la_operand_p (operands[1], operands[2])" |
| 7bdff56f UW |
987 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
| 988 | "") | |
| 989 | ||
| 990 | (define_expand "reload_indi" | |
| 991 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
| 992 | (match_operand:DI 1 "s390_plus_operand" "") | |
| 993 | (match_operand:DI 2 "register_operand" "=&a")])] | |
| 994 | "TARGET_64BIT" | |
| 995 | { | |
| 996 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
| 997 | DONE; | |
| 998 | }) | |
| 999 | ||
| 9db1d521 HP |
1000 | ; |
| 1001 | ; movsi instruction pattern(s). | |
| 1002 | ; | |
| 1003 | ||
| 9db1d521 HP |
1004 | (define_expand "movsi" |
| 1005 | [(set (match_operand:SI 0 "general_operand" "") | |
| 1006 | (match_operand:SI 1 "general_operand" ""))] | |
| 1007 | "" | |
| 9db1d521 | 1008 | { |
| fd3cd001 UW |
1009 | /* Handle symbolic constants. */ |
| 1010 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
| 1011 | emit_symbolic_move (operands); | |
| 10bbf137 | 1012 | }) |
| 9db1d521 | 1013 | |
| 9e8327e3 UW |
1014 | (define_insn "*movsi_larl" |
| 1015 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1016 | (match_operand:SI 1 "larl_operand" "X"))] | |
| 1017 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
| 1018 | && !FP_REG_P (operands[0])" | |
| 1019 | "larl\t%0,%1" | |
| 1020 | [(set_attr "op_type" "RIL") | |
| 1021 | (set_attr "type" "larl")]) | |
| 1022 | ||
| f19a9af7 | 1023 | (define_insn "*movsi_zarch" |
| 2f7e5a0d | 1024 | [(set (match_operand:SI 0 "nonimmediate_operand" |
| f19a9af7 | 1025 | "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") |
| 2f7e5a0d | 1026 | (match_operand:SI 1 "general_operand" |
| f19a9af7 AK |
1027 | "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))] |
| 1028 | "TARGET_ZARCH" | |
| 9db1d521 | 1029 | "@ |
| f19a9af7 AK |
1030 | lhi\t%0,%h1 |
| 1031 | llilh\t%0,%i1 | |
| 1032 | llill\t%0,%i1 | |
| 1033 | lay\t%0,%a1 | |
| d40c829f UW |
1034 | lr\t%0,%1 |
| 1035 | l\t%0,%1 | |
| 1036 | ly\t%0,%1 | |
| 1037 | st\t%1,%0 | |
| 1038 | sty\t%1,%0 | |
| 1039 | ler\t%0,%1 | |
| 1040 | le\t%0,%1 | |
| 1041 | ley\t%0,%1 | |
| 1042 | ste\t%1,%0 | |
| 1043 | stey\t%1,%0 | |
| 1044 | mvc\t%O0(4,%R0),%1" | |
| f19a9af7 AK |
1045 | [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
| 1046 | (set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")]) | |
| 1047 | ||
| 1048 | (define_insn "*movsi_esa" | |
| 1049 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,?Q") | |
| 1050 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,?Q"))] | |
| 1051 | "!TARGET_ZARCH" | |
| 1052 | "@ | |
| 1053 | lhi\t%0,%h1 | |
| 1054 | lr\t%0,%1 | |
| 1055 | l\t%0,%1 | |
| 1056 | st\t%1,%0 | |
| 1057 | ler\t%0,%1 | |
| 1058 | le\t%0,%1 | |
| 1059 | ste\t%1,%0 | |
| 1060 | mvc\t%O0(4,%R0),%1" | |
| 1061 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,SS") | |
| 1062 | (set_attr "type" "*,lr,load,store,floads,floads,fstores,cs")]) | |
| 9db1d521 | 1063 | |
| 84817c5d UW |
1064 | (define_peephole2 |
| 1065 | [(set (match_operand:SI 0 "register_operand" "") | |
| 1066 | (mem:SI (match_operand 1 "address_operand" "")))] | |
| 1067 | "!FP_REG_P (operands[0]) | |
| 1068 | && GET_CODE (operands[1]) == SYMBOL_REF | |
| 1069 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
| 1070 | && get_pool_mode (operands[1]) == SImode | |
| 1071 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
| 1072 | [(set (match_dup 0) (match_dup 2))] | |
| 1073 | "operands[2] = get_pool_constant (operands[1]);") | |
| 9db1d521 | 1074 | |
| 7bdff56f UW |
1075 | (define_insn "*la_31" |
| 1076 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 1077 | (match_operand:QI 1 "address_operand" "U,W"))] | |
| 1078 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
| 1079 | "@ | |
| 1080 | la\t%0,%a1 | |
| 1081 | lay\t%0,%a1" | |
| 1082 | [(set_attr "op_type" "RX,RXY") | |
| 1083 | (set_attr "type" "la")]) | |
| 1084 | ||
| 1085 | (define_peephole2 | |
| 1086 | [(parallel | |
| 1087 | [(set (match_operand:SI 0 "register_operand" "") | |
| 1088 | (match_operand:QI 1 "address_operand" "")) | |
| 1089 | (clobber (reg:CC 33))])] | |
| 1090 | "!TARGET_64BIT | |
| e1d5ee28 | 1091 | && preferred_la_operand_p (operands[1], const0_rtx)" |
| 7bdff56f UW |
1092 | [(set (match_dup 0) (match_dup 1))] |
| 1093 | "") | |
| 1094 | ||
| 1095 | (define_peephole2 | |
| 1096 | [(set (match_operand:SI 0 "register_operand" "") | |
| 1097 | (match_operand:SI 1 "register_operand" "")) | |
| 1098 | (parallel | |
| 1099 | [(set (match_dup 0) | |
| 1100 | (plus:SI (match_dup 0) | |
| 1101 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
| 1102 | (clobber (reg:CC 33))])] | |
| 1103 | "!TARGET_64BIT | |
| 1104 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
| e1d5ee28 | 1105 | && preferred_la_operand_p (operands[1], operands[2])" |
| 7bdff56f UW |
1106 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
| 1107 | "") | |
| 1108 | ||
| 1109 | (define_insn "*la_31_and" | |
| 1110 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 1111 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
| 1112 | (const_int 2147483647)))] | |
| 1113 | "!TARGET_64BIT" | |
| 1114 | "@ | |
| 1115 | la\t%0,%a1 | |
| 1116 | lay\t%0,%a1" | |
| 1117 | [(set_attr "op_type" "RX,RXY") | |
| 1118 | (set_attr "type" "la")]) | |
| 1119 | ||
| 1120 | (define_insn_and_split "*la_31_and_cc" | |
| 1121 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1122 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
| 1123 | (const_int 2147483647))) | |
| 1124 | (clobber (reg:CC 33))] | |
| 1125 | "!TARGET_64BIT" | |
| 1126 | "#" | |
| 1127 | "&& reload_completed" | |
| 1128 | [(set (match_dup 0) | |
| 1129 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
| 1130 | "" | |
| 1131 | [(set_attr "op_type" "RX") | |
| 1132 | (set_attr "type" "la")]) | |
| 1133 | ||
| 1134 | (define_insn "force_la_31" | |
| 1135 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 1136 | (match_operand:QI 1 "address_operand" "U,W")) | |
| 1137 | (use (const_int 0))] | |
| 1138 | "!TARGET_64BIT" | |
| 1139 | "@ | |
| 1140 | la\t%0,%a1 | |
| 1141 | lay\t%0,%a1" | |
| 1142 | [(set_attr "op_type" "RX") | |
| 1143 | (set_attr "type" "la")]) | |
| 1144 | ||
| 1145 | (define_expand "reload_insi" | |
| 1146 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
| 1147 | (match_operand:SI 1 "s390_plus_operand" "") | |
| 1148 | (match_operand:SI 2 "register_operand" "=&a")])] | |
| 1149 | "!TARGET_64BIT" | |
| 1150 | { | |
| 1151 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
| 1152 | DONE; | |
| 1153 | }) | |
| 1154 | ||
| 9db1d521 HP |
1155 | ; |
| 1156 | ; movhi instruction pattern(s). | |
| 1157 | ; | |
| 1158 | ||
| 02ed3c5e UW |
1159 | (define_expand "movhi" |
| 1160 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 1161 | (match_operand:HI 1 "general_operand" ""))] | |
| 1162 | "" | |
| 1163 | { | |
| 2f7e5a0d | 1164 | /* Make it explicit that loading a register from memory |
| 02ed3c5e UW |
1165 | always sign-extends (at least) to SImode. */ |
| 1166 | if (optimize && !no_new_pseudos | |
| 1167 | && register_operand (operands[0], VOIDmode) | |
| 8fff4fc1 | 1168 | && GET_CODE (operands[1]) == MEM) |
| 02ed3c5e UW |
1169 | { |
| 1170 | rtx tmp = gen_reg_rtx (SImode); | |
| 1171 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
| 1172 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
| 1173 | operands[1] = gen_lowpart (HImode, tmp); | |
| 1174 | } | |
| 1175 | }) | |
| 1176 | ||
| 1177 | (define_insn "*movhi" | |
| d3632d41 UW |
1178 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
| 1179 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
| 9db1d521 HP |
1180 | "" |
| 1181 | "@ | |
| d40c829f UW |
1182 | lr\t%0,%1 |
| 1183 | lhi\t%0,%h1 | |
| 1184 | lh\t%0,%1 | |
| 1185 | lhy\t%0,%1 | |
| 1186 | sth\t%1,%0 | |
| 1187 | sthy\t%1,%0 | |
| 1188 | mvc\t%O0(2,%R0),%1" | |
| d3632d41 UW |
1189 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
| 1190 | (set_attr "type" "lr,*,*,*,store,store,cs")]) | |
| 9db1d521 | 1191 | |
| 84817c5d UW |
1192 | (define_peephole2 |
| 1193 | [(set (match_operand:HI 0 "register_operand" "") | |
| 1194 | (mem:HI (match_operand 1 "address_operand" "")))] | |
| 1195 | "GET_CODE (operands[1]) == SYMBOL_REF | |
| 1196 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
| 1197 | && get_pool_mode (operands[1]) == HImode | |
| 1198 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
| 1199 | [(set (match_dup 0) (match_dup 2))] | |
| 1200 | "operands[2] = get_pool_constant (operands[1]);") | |
| 4023fb28 | 1201 | |
| 9db1d521 HP |
1202 | ; |
| 1203 | ; movqi instruction pattern(s). | |
| 1204 | ; | |
| 1205 | ||
| 02ed3c5e UW |
1206 | (define_expand "movqi" |
| 1207 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 1208 | (match_operand:QI 1 "general_operand" ""))] | |
| 1209 | "" | |
| 1210 | { | |
| c19ec8f9 | 1211 | /* On z/Architecture, zero-extending from memory to register |
| 02ed3c5e | 1212 | is just as fast as a QImode load. */ |
| c19ec8f9 | 1213 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
| 02ed3c5e | 1214 | && register_operand (operands[0], VOIDmode) |
| 8fff4fc1 | 1215 | && GET_CODE (operands[1]) == MEM) |
| 02ed3c5e | 1216 | { |
| c19ec8f9 UW |
1217 | rtx tmp = gen_reg_rtx (word_mode); |
| 1218 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
| 02ed3c5e UW |
1219 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
| 1220 | operands[1] = gen_lowpart (QImode, tmp); | |
| 1221 | } | |
| 1222 | }) | |
| 4023fb28 | 1223 | |
| 02ed3c5e | 1224 | (define_insn "*movqi" |
| d3632d41 UW |
1225 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
| 1226 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
| 9db1d521 HP |
1227 | "" |
| 1228 | "@ | |
| d40c829f UW |
1229 | lr\t%0,%1 |
| 1230 | lhi\t%0,%b1 | |
| 1231 | ic\t%0,%1 | |
| 1232 | icy\t%0,%1 | |
| 1233 | stc\t%1,%0 | |
| 1234 | stcy\t%1,%0 | |
| 1235 | mvi\t%0,%b1 | |
| 1236 | mviy\t%0,%b1 | |
| 1237 | mvc\t%O0(1,%R0),%1" | |
| d3632d41 UW |
1238 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
| 1239 | (set_attr "type" "lr,*,*,*,store,store,store,store,cs")]) | |
| 9db1d521 | 1240 | |
| 84817c5d UW |
1241 | (define_peephole2 |
| 1242 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 1243 | (mem:QI (match_operand 1 "address_operand" "")))] | |
| 1244 | "GET_CODE (operands[1]) == SYMBOL_REF | |
| 1245 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
| 1246 | && get_pool_mode (operands[1]) == QImode | |
| 1247 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
| 1248 | [(set (match_dup 0) (match_dup 2))] | |
| 1249 | "operands[2] = get_pool_constant (operands[1]);") | |
| 4023fb28 | 1250 | |
| 9db1d521 | 1251 | ; |
| 05b9aaaa | 1252 | ; movstrictqi instruction pattern(s). |
| 9db1d521 HP |
1253 | ; |
| 1254 | ||
| 1255 | (define_insn "*movstrictqi" | |
| d3632d41 UW |
1256 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
| 1257 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
| 9db1d521 | 1258 | "" |
| d3632d41 | 1259 | "@ |
| d40c829f UW |
1260 | ic\t%0,%1 |
| 1261 | icy\t%0,%1" | |
| d3632d41 | 1262 | [(set_attr "op_type" "RX,RXY")]) |
| 9db1d521 HP |
1263 | |
| 1264 | ; | |
| 1265 | ; movstricthi instruction pattern(s). | |
| 1266 | ; | |
| 1267 | ||
| 1268 | (define_insn "*movstricthi" | |
| d3632d41 | 1269 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
| 575f7c2b | 1270 | (match_operand:HI 1 "memory_operand" "Q,S")) |
| 9db1d521 HP |
1271 | (clobber (reg:CC 33))] |
| 1272 | "" | |
| d3632d41 | 1273 | "@ |
| d40c829f UW |
1274 | icm\t%0,3,%1 |
| 1275 | icmy\t%0,3,%1" | |
| d3632d41 | 1276 | [(set_attr "op_type" "RS,RSY")]) |
| 9db1d521 HP |
1277 | |
| 1278 | ; | |
| 1279 | ; movstrictsi instruction pattern(s). | |
| 1280 | ; | |
| 1281 | ||
| 05b9aaaa | 1282 | (define_insn "movstrictsi" |
| d3632d41 UW |
1283 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d")) |
| 1284 | (match_operand:SI 1 "general_operand" "d,R,T"))] | |
| 9db1d521 HP |
1285 | "TARGET_64BIT" |
| 1286 | "@ | |
| d40c829f UW |
1287 | lr\t%0,%1 |
| 1288 | l\t%0,%1 | |
| 1289 | ly\t%0,%1" | |
| d3632d41 UW |
1290 | [(set_attr "op_type" "RR,RX,RXY") |
| 1291 | (set_attr "type" "lr,load,load")]) | |
| 9db1d521 HP |
1292 | |
| 1293 | ; | |
| 1294 | ; movdf instruction pattern(s). | |
| 1295 | ; | |
| 1296 | ||
| 1297 | (define_expand "movdf" | |
| 1298 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
| 1299 | (match_operand:DF 1 "general_operand" ""))] | |
| 1300 | "" | |
| 13c025c1 | 1301 | "") |
| 9db1d521 HP |
1302 | |
| 1303 | (define_insn "*movdf_64" | |
| d3632d41 UW |
1304 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") |
| 1305 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] | |
| 4023fb28 | 1306 | "TARGET_64BIT" |
| 9db1d521 | 1307 | "@ |
| d40c829f UW |
1308 | ldr\t%0,%1 |
| 1309 | ld\t%0,%1 | |
| 1310 | ldy\t%0,%1 | |
| 1311 | std\t%1,%0 | |
| 1312 | stdy\t%1,%0 | |
| 1313 | lgr\t%0,%1 | |
| 1314 | lg\t%0,%1 | |
| 1315 | stg\t%1,%0 | |
| 1316 | mvc\t%O0(8,%R0),%1" | |
| d3632d41 UW |
1317 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
| 1318 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")]) | |
| 9db1d521 HP |
1319 | |
| 1320 | (define_insn "*movdf_31" | |
| d3632d41 UW |
1321 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") |
| 1322 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] | |
| 4023fb28 | 1323 | "!TARGET_64BIT" |
| 9db1d521 | 1324 | "@ |
| d40c829f UW |
1325 | ldr\t%0,%1 |
| 1326 | ld\t%0,%1 | |
| 1327 | ldy\t%0,%1 | |
| 1328 | std\t%1,%0 | |
| 1329 | stdy\t%1,%0 | |
| 1330 | lm\t%0,%N0,%1 | |
| 1331 | stm\t%1,%N1,%0 | |
| 4023fb28 | 1332 | # |
| 9b7c75b9 | 1333 | # |
| d40c829f | 1334 | mvc\t%O0(8,%R0),%1" |
| d3632d41 UW |
1335 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS") |
| 1336 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")]) | |
| 4023fb28 UW |
1337 | |
| 1338 | (define_split | |
| 1339 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
| 1340 | (match_operand:DF 1 "general_operand" ""))] | |
| 1341 | "!TARGET_64BIT && reload_completed | |
| dc65c307 | 1342 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
| 4023fb28 UW |
1343 | [(set (match_dup 2) (match_dup 4)) |
| 1344 | (set (match_dup 3) (match_dup 5))] | |
| 9db1d521 | 1345 | { |
| dc65c307 UW |
1346 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
| 1347 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
| 1348 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
| 1349 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
| 1350 | }) | |
| 1351 | ||
| 1352 | (define_split | |
| 1353 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
| 1354 | (match_operand:DF 1 "general_operand" ""))] | |
| 1355 | "!TARGET_64BIT && reload_completed | |
| 1356 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
| 1357 | [(set (match_dup 2) (match_dup 4)) | |
| 1358 | (set (match_dup 3) (match_dup 5))] | |
| 1359 | { | |
| 1360 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
| 1361 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
| 1362 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
| 1363 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
| 1364 | }) | |
| 9db1d521 | 1365 | |
| 4023fb28 UW |
1366 | (define_split |
| 1367 | [(set (match_operand:DF 0 "register_operand" "") | |
| 1368 | (match_operand:DF 1 "memory_operand" ""))] | |
| 1369 | "!TARGET_64BIT && reload_completed | |
| 8e509cf9 | 1370 | && !FP_REG_P (operands[0]) |
| 4023fb28 | 1371 | && !s_operand (operands[1], VOIDmode)" |
| a41c6c53 | 1372 | [(set (match_dup 0) (match_dup 1))] |
| a41c6c53 UW |
1373 | { |
| 1374 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
| 1375 | s390_load_address (addr, XEXP (operands[1], 0)); | |
| 1376 | operands[1] = replace_equiv_address (operands[1], addr); | |
| dc65c307 UW |
1377 | }) |
| 1378 | ||
| 1379 | (define_expand "reload_outdf" | |
| 1380 | [(parallel [(match_operand:DF 0 "memory_operand" "") | |
| 1381 | (match_operand:DF 1 "register_operand" "d") | |
| 1382 | (match_operand:SI 2 "register_operand" "=&a")])] | |
| 1383 | "!TARGET_64BIT" | |
| 1384 | { | |
| 1385 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
| 1386 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
| 1387 | emit_move_insn (operands[0], operands[1]); | |
| 1388 | DONE; | |
| 1389 | }) | |
| 9db1d521 HP |
1390 | |
| 1391 | ; | |
| 1392 | ; movsf instruction pattern(s). | |
| 1393 | ; | |
| 1394 | ||
| 13c025c1 | 1395 | (define_insn "movsf" |
| d3632d41 UW |
1396 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") |
| 1397 | (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] | |
| 4023fb28 | 1398 | "" |
| 9db1d521 | 1399 | "@ |
| d40c829f UW |
1400 | ler\t%0,%1 |
| 1401 | le\t%0,%1 | |
| 1402 | ley\t%0,%1 | |
| 1403 | ste\t%1,%0 | |
| 1404 | stey\t%1,%0 | |
| 1405 | lr\t%0,%1 | |
| 1406 | l\t%0,%1 | |
| 1407 | ly\t%0,%1 | |
| 1408 | st\t%1,%0 | |
| 1409 | sty\t%1,%0 | |
| 1410 | mvc\t%O0(4,%R0),%1" | |
| d3632d41 UW |
1411 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
| 1412 | (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")]) | |
| 4023fb28 | 1413 | |
| 9db1d521 HP |
1414 | ; |
| 1415 | ; load_multiple pattern(s). | |
| 1416 | ; | |
| 22ea6b4f UW |
1417 | ; ??? Due to reload problems with replacing registers inside match_parallel |
| 1418 | ; we currently support load_multiple/store_multiple only after reload. | |
| 1419 | ; | |
| 9db1d521 HP |
1420 | |
| 1421 | (define_expand "load_multiple" | |
| 1422 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
| 1423 | (match_operand 1 "" "")) | |
| 1424 | (use (match_operand 2 "" ""))])] | |
| 22ea6b4f | 1425 | "reload_completed" |
| 9db1d521 | 1426 | { |
| c19ec8f9 | 1427 | enum machine_mode mode; |
| 9db1d521 HP |
1428 | int regno; |
| 1429 | int count; | |
| 1430 | rtx from; | |
| 4023fb28 | 1431 | int i, off; |
| 9db1d521 HP |
1432 | |
| 1433 | /* Support only loading a constant number of fixed-point registers from | |
| 1434 | memory and only bother with this if more than two */ | |
| 1435 | if (GET_CODE (operands[2]) != CONST_INT | |
| 4023fb28 | 1436 | || INTVAL (operands[2]) < 2 |
| 9db1d521 HP |
1437 | || INTVAL (operands[2]) > 16 |
| 1438 | || GET_CODE (operands[1]) != MEM | |
| 1439 | || GET_CODE (operands[0]) != REG | |
| 1440 | || REGNO (operands[0]) >= 16) | |
| 1441 | FAIL; | |
| 1442 | ||
| 1443 | count = INTVAL (operands[2]); | |
| 1444 | regno = REGNO (operands[0]); | |
| c19ec8f9 UW |
1445 | mode = GET_MODE (operands[0]); |
| 1446 | if (mode != SImode && mode != word_mode) | |
| 1447 | FAIL; | |
| 9db1d521 HP |
1448 | |
| 1449 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
| 4023fb28 UW |
1450 | if (no_new_pseudos) |
| 1451 | { | |
| 1452 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
| 1453 | { | |
| 1454 | from = XEXP (operands[1], 0); | |
| 1455 | off = 0; | |
| 1456 | } | |
| 1457 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
| 1458 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
| 1459 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
| 1460 | { | |
| 1461 | from = XEXP (XEXP (operands[1], 0), 0); | |
| 1462 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
| 1463 | } | |
| 1464 | else | |
| 1465 | FAIL; | |
| 4023fb28 UW |
1466 | } |
| 1467 | else | |
| 1468 | { | |
| 1469 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
| 1470 | off = 0; | |
| 1471 | } | |
| 9db1d521 HP |
1472 | |
| 1473 | for (i = 0; i < count; i++) | |
| 1474 | XVECEXP (operands[3], 0, i) | |
| c19ec8f9 UW |
1475 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
| 1476 | change_address (operands[1], mode, | |
| 1477 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
| 10bbf137 | 1478 | }) |
| 9db1d521 HP |
1479 | |
| 1480 | (define_insn "*load_multiple_di" | |
| 1481 | [(match_parallel 0 "load_multiple_operation" | |
| 1482 | [(set (match_operand:DI 1 "register_operand" "=r") | |
| d3632d41 | 1483 | (match_operand:DI 2 "s_operand" "QS"))])] |
| 22ea6b4f | 1484 | "reload_completed && word_mode == DImode" |
| 9db1d521 HP |
1485 | { |
| 1486 | int words = XVECLEN (operands[0], 0); | |
| 9db1d521 | 1487 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
| d40c829f | 1488 | return "lmg\t%1,%0,%2"; |
| 10bbf137 | 1489 | } |
| d3632d41 | 1490 | [(set_attr "op_type" "RSY") |
| 4023fb28 | 1491 | (set_attr "type" "lm")]) |
| 9db1d521 HP |
1492 | |
| 1493 | (define_insn "*load_multiple_si" | |
| 1494 | [(match_parallel 0 "load_multiple_operation" | |
| d3632d41 UW |
1495 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
| 1496 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
| 22ea6b4f | 1497 | "reload_completed" |
| 9db1d521 HP |
1498 | { |
| 1499 | int words = XVECLEN (operands[0], 0); | |
| 9db1d521 | 1500 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
| d40c829f | 1501 | return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2"; |
| 10bbf137 | 1502 | } |
| d3632d41 | 1503 | [(set_attr "op_type" "RS,RSY") |
| 4023fb28 | 1504 | (set_attr "type" "lm")]) |
| 9db1d521 HP |
1505 | |
| 1506 | ; | |
| c7453384 | 1507 | ; store multiple pattern(s). |
| 9db1d521 HP |
1508 | ; |
| 1509 | ||
| 1510 | (define_expand "store_multiple" | |
| 1511 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
| 1512 | (match_operand 1 "" "")) | |
| 1513 | (use (match_operand 2 "" ""))])] | |
| 22ea6b4f | 1514 | "reload_completed" |
| 9db1d521 | 1515 | { |
| c19ec8f9 | 1516 | enum machine_mode mode; |
| 9db1d521 HP |
1517 | int regno; |
| 1518 | int count; | |
| 1519 | rtx to; | |
| 4023fb28 | 1520 | int i, off; |
| 9db1d521 HP |
1521 | |
| 1522 | /* Support only storing a constant number of fixed-point registers to | |
| 1523 | memory and only bother with this if more than two. */ | |
| 1524 | if (GET_CODE (operands[2]) != CONST_INT | |
| 4023fb28 | 1525 | || INTVAL (operands[2]) < 2 |
| 9db1d521 HP |
1526 | || INTVAL (operands[2]) > 16 |
| 1527 | || GET_CODE (operands[0]) != MEM | |
| 1528 | || GET_CODE (operands[1]) != REG | |
| 1529 | || REGNO (operands[1]) >= 16) | |
| 1530 | FAIL; | |
| 1531 | ||
| 1532 | count = INTVAL (operands[2]); | |
| 1533 | regno = REGNO (operands[1]); | |
| c19ec8f9 UW |
1534 | mode = GET_MODE (operands[1]); |
| 1535 | if (mode != SImode && mode != word_mode) | |
| 1536 | FAIL; | |
| 9db1d521 HP |
1537 | |
| 1538 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
| 4023fb28 UW |
1539 | |
| 1540 | if (no_new_pseudos) | |
| 1541 | { | |
| 1542 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
| 1543 | { | |
| 1544 | to = XEXP (operands[0], 0); | |
| 1545 | off = 0; | |
| 1546 | } | |
| 1547 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
| 1548 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
| 1549 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
| 1550 | { | |
| 1551 | to = XEXP (XEXP (operands[0], 0), 0); | |
| 1552 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
| 1553 | } | |
| 1554 | else | |
| 1555 | FAIL; | |
| 4023fb28 | 1556 | } |
| c7453384 | 1557 | else |
| 4023fb28 UW |
1558 | { |
| 1559 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
| 1560 | off = 0; | |
| 1561 | } | |
| 9db1d521 HP |
1562 | |
| 1563 | for (i = 0; i < count; i++) | |
| 1564 | XVECEXP (operands[3], 0, i) | |
| 1565 | = gen_rtx_SET (VOIDmode, | |
| c19ec8f9 UW |
1566 | change_address (operands[0], mode, |
| 1567 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
| 1568 | gen_rtx_REG (mode, regno + i)); | |
| 10bbf137 | 1569 | }) |
| 9db1d521 HP |
1570 | |
| 1571 | (define_insn "*store_multiple_di" | |
| 1572 | [(match_parallel 0 "store_multiple_operation" | |
| d3632d41 | 1573 | [(set (match_operand:DI 1 "s_operand" "=QS") |
| 9db1d521 | 1574 | (match_operand:DI 2 "register_operand" "r"))])] |
| 22ea6b4f | 1575 | "reload_completed && word_mode == DImode" |
| 9db1d521 HP |
1576 | { |
| 1577 | int words = XVECLEN (operands[0], 0); | |
| 9db1d521 | 1578 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
| d40c829f | 1579 | return "stmg\t%2,%0,%1"; |
| 10bbf137 | 1580 | } |
| d3632d41 | 1581 | [(set_attr "op_type" "RSY") |
| 4023fb28 | 1582 | (set_attr "type" "stm")]) |
| 9db1d521 HP |
1583 | |
| 1584 | ||
| 1585 | (define_insn "*store_multiple_si" | |
| 1586 | [(match_parallel 0 "store_multiple_operation" | |
| d3632d41 UW |
1587 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
| 1588 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
| 22ea6b4f | 1589 | "reload_completed" |
| 9db1d521 HP |
1590 | { |
| 1591 | int words = XVECLEN (operands[0], 0); | |
| 9db1d521 | 1592 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
| d40c829f | 1593 | return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1"; |
| 10bbf137 | 1594 | } |
| d3632d41 | 1595 | [(set_attr "op_type" "RS,RSY") |
| 4023fb28 | 1596 | (set_attr "type" "stm")]) |
| 9db1d521 HP |
1597 | |
| 1598 | ;; | |
| 1599 | ;; String instructions. | |
| 1600 | ;; | |
| 1601 | ||
| 9bb86f41 UW |
1602 | (define_insn "*execute" |
| 1603 | [(match_parallel 0 "" | |
| 1604 | [(unspec [(match_operand 1 "register_operand" "a") | |
| 1605 | (match_operand:BLK 2 "memory_operand" "R") | |
| 1606 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
| 1607 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
| 1608 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
| 1609 | "ex\t%1,%2" | |
| 1610 | [(set_attr "op_type" "RX")]) | |
| 1611 | ||
| 1612 | ||
| 91d39d71 UW |
1613 | ; |
| 1614 | ; strlenM instruction pattern(s). | |
| 1615 | ; | |
| 1616 | ||
| 1617 | (define_expand "strlendi" | |
| 1618 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) | |
| 2f7e5a0d | 1619 | (parallel |
| 91d39d71 UW |
1620 | [(set (match_dup 4) |
| 1621 | (unspec:DI [(const_int 0) | |
| 1622 | (match_operand:BLK 1 "memory_operand" "") | |
| 1623 | (reg:QI 0) | |
| 1624 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
| 1625 | (clobber (scratch:DI)) | |
| 1626 | (clobber (reg:CC 33))]) | |
| 1627 | (parallel | |
| 1628 | [(set (match_operand:DI 0 "register_operand" "") | |
| 1629 | (minus:DI (match_dup 4) (match_dup 5))) | |
| 1630 | (clobber (reg:CC 33))])] | |
| 1631 | "TARGET_64BIT" | |
| 1632 | { | |
| 1633 | operands[4] = gen_reg_rtx (DImode); | |
| 1634 | operands[5] = gen_reg_rtx (DImode); | |
| 1635 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
| 1636 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
| 1637 | }) | |
| 1638 | ||
| 1639 | (define_insn "*strlendi" | |
| 1640 | [(set (match_operand:DI 0 "register_operand" "=a") | |
| 1641 | (unspec:DI [(match_operand:DI 2 "general_operand" "0") | |
| 1642 | (mem:BLK (match_operand:DI 3 "register_operand" "1")) | |
| 1643 | (reg:QI 0) | |
| 1644 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
| 1645 | (clobber (match_scratch:DI 1 "=a")) | |
| 1646 | (clobber (reg:CC 33))] | |
| 1647 | "TARGET_64BIT" | |
| 1648 | "srst\t%0,%1\;jo\t.-4" | |
| 1649 | [(set_attr "op_type" "NN") | |
| 1650 | (set_attr "type" "vs") | |
| 1651 | (set_attr "length" "8")]) | |
| 1652 | ||
| 1653 | (define_expand "strlensi" | |
| 1654 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) | |
| 2f7e5a0d | 1655 | (parallel |
| 91d39d71 UW |
1656 | [(set (match_dup 4) |
| 1657 | (unspec:SI [(const_int 0) | |
| 1658 | (match_operand:BLK 1 "memory_operand" "") | |
| 1659 | (reg:QI 0) | |
| 1660 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
| 1661 | (clobber (scratch:SI)) | |
| 1662 | (clobber (reg:CC 33))]) | |
| 1663 | (parallel | |
| 1664 | [(set (match_operand:SI 0 "register_operand" "") | |
| 1665 | (minus:SI (match_dup 4) (match_dup 5))) | |
| 1666 | (clobber (reg:CC 33))])] | |
| 1667 | "!TARGET_64BIT" | |
| 1668 | { | |
| 1669 | operands[4] = gen_reg_rtx (SImode); | |
| 1670 | operands[5] = gen_reg_rtx (SImode); | |
| 1671 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
| 1672 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
| 1673 | }) | |
| 1674 | ||
| 1675 | (define_insn "*strlensi" | |
| 1676 | [(set (match_operand:SI 0 "register_operand" "=a") | |
| 1677 | (unspec:SI [(match_operand:SI 2 "general_operand" "0") | |
| 1678 | (mem:BLK (match_operand:SI 3 "register_operand" "1")) | |
| 1679 | (reg:QI 0) | |
| 1680 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
| 1681 | (clobber (match_scratch:SI 1 "=a")) | |
| 2f7e5a0d | 1682 | (clobber (reg:CC 33))] |
| 91d39d71 UW |
1683 | "!TARGET_64BIT" |
| 1684 | "srst\t%0,%1\;jo\t.-4" | |
| 1685 | [(set_attr "op_type" "NN") | |
| 1686 | (set_attr "type" "vs") | |
| 1687 | (set_attr "length" "8")]) | |
| 1688 | ||
| 9db1d521 | 1689 | ; |
| 70128ad9 | 1690 | ; movmemM instruction pattern(s). |
| 9db1d521 HP |
1691 | ; |
| 1692 | ||
| 70128ad9 | 1693 | (define_expand "movmemdi" |
| a41c6c53 UW |
1694 | [(set (match_operand:BLK 0 "memory_operand" "") |
| 1695 | (match_operand:BLK 1 "memory_operand" "")) | |
| 1696 | (use (match_operand:DI 2 "general_operand" "")) | |
| 1697 | (match_operand 3 "" "")] | |
| 1698 | "TARGET_64BIT" | |
| 70128ad9 | 1699 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
| 9db1d521 | 1700 | |
| 70128ad9 | 1701 | (define_expand "movmemsi" |
| a41c6c53 UW |
1702 | [(set (match_operand:BLK 0 "memory_operand" "") |
| 1703 | (match_operand:BLK 1 "memory_operand" "")) | |
| 1704 | (use (match_operand:SI 2 "general_operand" "")) | |
| 1705 | (match_operand 3 "" "")] | |
| 1706 | "" | |
| 70128ad9 | 1707 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
| 9db1d521 | 1708 | |
| ecbe845e UW |
1709 | ; Move a block that is up to 256 bytes in length. |
| 1710 | ; The block length is taken as (operands[2] % 256) + 1. | |
| 9db1d521 | 1711 | |
| 70128ad9 | 1712 | (define_expand "movmem_short" |
| b9404c99 UW |
1713 | [(parallel |
| 1714 | [(set (match_operand:BLK 0 "memory_operand" "") | |
| 1715 | (match_operand:BLK 1 "memory_operand" "")) | |
| 1716 | (use (match_operand 2 "nonmemory_operand" "")) | |
| 9bb86f41 | 1717 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
| b9404c99 UW |
1718 | (clobber (match_dup 3))])] |
| 1719 | "" | |
| 1720 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
| ecbe845e | 1721 | |
| 70128ad9 | 1722 | (define_insn "*movmem_short" |
| 9bb86f41 UW |
1723 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
| 1724 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) | |
| 1725 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
| 1726 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
| 1727 | (clobber (match_scratch 4 "=X,X,&a"))] | |
| b9404c99 | 1728 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
| 9bb86f41 UW |
1729 | && GET_MODE (operands[4]) == Pmode" |
| 1730 | "#" | |
| 1731 | [(set_attr "op_type" "SS,RX,RX") | |
| 1732 | (set_attr "type" "cs")]) | |
| ecbe845e | 1733 | |
| 9bb86f41 UW |
1734 | (define_split |
| 1735 | [(set (match_operand:BLK 0 "memory_operand" "") | |
| 1736 | (match_operand:BLK 1 "memory_operand" "")) | |
| 1737 | (use (match_operand 2 "const_int_operand" "")) | |
| 1738 | (use (match_operand 3 "immediate_operand" "")) | |
| 1739 | (clobber (scratch))] | |
| 1740 | "reload_completed" | |
| 1741 | [(parallel | |
| 1742 | [(set (match_dup 0) (match_dup 1)) | |
| 1743 | (use (match_dup 2))])] | |
| 1744 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
| 9db1d521 | 1745 | |
| 9bb86f41 UW |
1746 | (define_split |
| 1747 | [(set (match_operand:BLK 0 "memory_operand" "") | |
| 1748 | (match_operand:BLK 1 "memory_operand" "")) | |
| 1749 | (use (match_operand 2 "register_operand" "")) | |
| 1750 | (use (match_operand 3 "memory_operand" "")) | |
| 1751 | (clobber (scratch))] | |
| 1752 | "reload_completed" | |
| 1753 | [(parallel | |
| 1754 | [(unspec [(match_dup 2) (match_dup 3) | |
| 1755 | (const_int 0)] UNSPEC_EXECUTE) | |
| 1756 | (set (match_dup 0) (match_dup 1)) | |
| 1757 | (use (const_int 1))])] | |
| 1758 | "") | |
| 1759 | ||
| 1760 | (define_split | |
| 1761 | [(set (match_operand:BLK 0 "memory_operand" "") | |
| 1762 | (match_operand:BLK 1 "memory_operand" "")) | |
| 1763 | (use (match_operand 2 "register_operand" "")) | |
| 1764 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
| 1765 | (clobber (match_operand 3 "register_operand" ""))] | |
| 1766 | "reload_completed && TARGET_CPU_ZARCH" | |
| 1767 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
| 1768 | (parallel | |
| 1769 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
| 1770 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
| 1771 | (set (match_dup 0) (match_dup 1)) | |
| 1772 | (use (const_int 1))])] | |
| 1773 | "operands[4] = gen_label_rtx ();") | |
| 1774 | ||
| 1775 | (define_insn "*mvc" | |
| 1776 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
| 1777 | (match_operand:BLK 1 "memory_operand" "Q")) | |
| 1778 | (use (match_operand 2 "const_int_operand" "n"))] | |
| 1779 | "" | |
| 1780 | "mvc\t%O0(%2,%R0),%1" | |
| 1781 | [(set_attr "op_type" "SS") | |
| 1782 | (set_attr "type" "cs")]) | |
| 9db1d521 | 1783 | |
| a41c6c53 | 1784 | ; Move a block of arbitrary length. |
| 9db1d521 | 1785 | |
| 70128ad9 | 1786 | (define_expand "movmem_long" |
| b9404c99 UW |
1787 | [(parallel |
| 1788 | [(clobber (match_dup 2)) | |
| 1789 | (clobber (match_dup 3)) | |
| 1790 | (set (match_operand:BLK 0 "memory_operand" "") | |
| 1791 | (match_operand:BLK 1 "memory_operand" "")) | |
| 1792 | (use (match_operand 2 "general_operand" "")) | |
| 1793 | (use (match_dup 3)) | |
| 1794 | (clobber (reg:CC 33))])] | |
| 1795 | "" | |
| 1796 | { | |
| 1797 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
| 1798 | rtx reg0 = gen_reg_rtx (dword_mode); | |
| 1799 | rtx reg1 = gen_reg_rtx (dword_mode); | |
| 1800 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
| 1801 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
| 1802 | rtx len0 = gen_lowpart (Pmode, reg0); | |
| 1803 | rtx len1 = gen_lowpart (Pmode, reg1); | |
| 1804 | ||
| 1805 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
| 1806 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
| 1807 | emit_move_insn (len0, operands[2]); | |
| 1808 | ||
| 1809 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
| 1810 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
| 1811 | emit_move_insn (len1, operands[2]); | |
| 1812 | ||
| 1813 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
| 1814 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
| 1815 | operands[2] = reg0; | |
| 1816 | operands[3] = reg1; | |
| 1817 | }) | |
| 1818 | ||
| 70128ad9 | 1819 | (define_insn "*movmem_long_64" |
| b9404c99 UW |
1820 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
| 1821 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
| 1822 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
| 1823 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) | |
| 1824 | (use (match_dup 2)) | |
| 1825 | (use (match_dup 3)) | |
| 9db1d521 | 1826 | (clobber (reg:CC 33))] |
| 9f37ccb1 | 1827 | "TARGET_64BIT" |
| d40c829f | 1828 | "mvcle\t%0,%1,0\;jo\t.-4" |
| 9db1d521 | 1829 | [(set_attr "op_type" "NN") |
| a41c6c53 | 1830 | (set_attr "type" "vs") |
| 9db1d521 HP |
1831 | (set_attr "length" "8")]) |
| 1832 | ||
| 70128ad9 | 1833 | (define_insn "*movmem_long_31" |
| b9404c99 UW |
1834 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
| 1835 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
| 1836 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
| 1837 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) | |
| 1838 | (use (match_dup 2)) | |
| 1839 | (use (match_dup 3)) | |
| 9db1d521 | 1840 | (clobber (reg:CC 33))] |
| 9f37ccb1 | 1841 | "!TARGET_64BIT" |
| d40c829f | 1842 | "mvcle\t%0,%1,0\;jo\t.-4" |
| a41c6c53 UW |
1843 | [(set_attr "op_type" "NN") |
| 1844 | (set_attr "type" "vs") | |
| a41c6c53 | 1845 | (set_attr "length" "8")]) |
| 9db1d521 HP |
1846 | |
| 1847 | ; | |
| 70128ad9 | 1848 | ; clrmemM instruction pattern(s). |
| 9db1d521 HP |
1849 | ; |
| 1850 | ||
| 70128ad9 | 1851 | (define_expand "clrmemdi" |
| a41c6c53 | 1852 | [(set (match_operand:BLK 0 "memory_operand" "") |
| 9db1d521 HP |
1853 | (const_int 0)) |
| 1854 | (use (match_operand:DI 1 "general_operand" "")) | |
| 1855 | (match_operand 2 "" "")] | |
| 1856 | "TARGET_64BIT" | |
| 70128ad9 | 1857 | "s390_expand_clrmem (operands[0], operands[1]); DONE;") |
| 9db1d521 | 1858 | |
| 70128ad9 | 1859 | (define_expand "clrmemsi" |
| a41c6c53 | 1860 | [(set (match_operand:BLK 0 "memory_operand" "") |
| 9db1d521 HP |
1861 | (const_int 0)) |
| 1862 | (use (match_operand:SI 1 "general_operand" "")) | |
| 1863 | (match_operand 2 "" "")] | |
| a41c6c53 | 1864 | "" |
| 70128ad9 | 1865 | "s390_expand_clrmem (operands[0], operands[1]); DONE;") |
| 9db1d521 | 1866 | |
| a41c6c53 | 1867 | ; Clear a block that is up to 256 bytes in length. |
| b9404c99 UW |
1868 | ; The block length is taken as (operands[1] % 256) + 1. |
| 1869 | ||
| 70128ad9 | 1870 | (define_expand "clrmem_short" |
| b9404c99 UW |
1871 | [(parallel |
| 1872 | [(set (match_operand:BLK 0 "memory_operand" "") | |
| 1873 | (const_int 0)) | |
| 1874 | (use (match_operand 1 "nonmemory_operand" "")) | |
| 9bb86f41 | 1875 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
| b9404c99 UW |
1876 | (clobber (match_dup 2)) |
| 1877 | (clobber (reg:CC 33))])] | |
| 1878 | "" | |
| 1879 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
| 9db1d521 | 1880 | |
| 70128ad9 | 1881 | (define_insn "*clrmem_short" |
| 9bb86f41 | 1882 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
| a41c6c53 | 1883 | (const_int 0)) |
| 9bb86f41 UW |
1884 | (use (match_operand 1 "nonmemory_operand" "n,a,a")) |
| 1885 | (use (match_operand 2 "immediate_operand" "X,R,X")) | |
| 1886 | (clobber (match_scratch 3 "=X,X,&a")) | |
| a41c6c53 | 1887 | (clobber (reg:CC 33))] |
| b9404c99 | 1888 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
| 9bb86f41 UW |
1889 | && GET_MODE (operands[3]) == Pmode" |
| 1890 | "#" | |
| 1891 | [(set_attr "op_type" "SS,RX,RX") | |
| 1892 | (set_attr "type" "cs")]) | |
| 1893 | ||
| 1894 | (define_split | |
| 1895 | [(set (match_operand:BLK 0 "memory_operand" "") | |
| 1896 | (const_int 0)) | |
| 1897 | (use (match_operand 1 "const_int_operand" "")) | |
| 1898 | (use (match_operand 2 "immediate_operand" "")) | |
| 1899 | (clobber (scratch)) | |
| 1900 | (clobber (reg:CC 33))] | |
| 1901 | "reload_completed" | |
| 1902 | [(parallel | |
| 1903 | [(set (match_dup 0) (const_int 0)) | |
| 1904 | (use (match_dup 1)) | |
| 1905 | (clobber (reg:CC 33))])] | |
| 1906 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") | |
| 9db1d521 | 1907 | |
| 9bb86f41 UW |
1908 | (define_split |
| 1909 | [(set (match_operand:BLK 0 "memory_operand" "") | |
| 1910 | (const_int 0)) | |
| 1911 | (use (match_operand 1 "register_operand" "")) | |
| 1912 | (use (match_operand 2 "memory_operand" "")) | |
| 1913 | (clobber (scratch)) | |
| 1914 | (clobber (reg:CC 33))] | |
| 1915 | "reload_completed" | |
| 1916 | [(parallel | |
| 1917 | [(unspec [(match_dup 1) (match_dup 2) | |
| 1918 | (const_int 0)] UNSPEC_EXECUTE) | |
| 1919 | (set (match_dup 0) (const_int 0)) | |
| 1920 | (use (const_int 1)) | |
| 1921 | (clobber (reg:CC 33))])] | |
| 1922 | "") | |
| 9db1d521 | 1923 | |
| 9bb86f41 UW |
1924 | (define_split |
| 1925 | [(set (match_operand:BLK 0 "memory_operand" "") | |
| 1926 | (const_int 0)) | |
| 1927 | (use (match_operand 1 "register_operand" "")) | |
| 1928 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
| 1929 | (clobber (match_operand 2 "register_operand" "")) | |
| 1930 | (clobber (reg:CC 33))] | |
| 1931 | "reload_completed && TARGET_CPU_ZARCH" | |
| 1932 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
| 1933 | (parallel | |
| 1934 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
| 1935 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
| 1936 | (set (match_dup 0) (const_int 0)) | |
| 1937 | (use (const_int 1)) | |
| 1938 | (clobber (reg:CC 33))])] | |
| 1939 | "operands[3] = gen_label_rtx ();") | |
| 1940 | ||
| 1941 | (define_insn "*xc_zero" | |
| 1942 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
| 1943 | (const_int 0)) | |
| 1944 | (use (match_operand 1 "const_int_operand" "n")) | |
| 1945 | (clobber (reg:CC 33))] | |
| 1946 | "" | |
| 1947 | "xc\t%O0(%1,%R0),%0" | |
| 1948 | [(set_attr "op_type" "SS") | |
| 1949 | (set_attr "type" "cs")]) | |
| 9db1d521 | 1950 | |
| b9404c99 UW |
1951 | ; Clear a block of arbitrary length. |
| 1952 | ||
| 70128ad9 | 1953 | (define_expand "clrmem_long" |
| b9404c99 UW |
1954 | [(parallel |
| 1955 | [(clobber (match_dup 1)) | |
| 1956 | (set (match_operand:BLK 0 "memory_operand" "") | |
| 1957 | (const_int 0)) | |
| 1958 | (use (match_operand 1 "general_operand" "")) | |
| 1959 | (use (match_dup 2)) | |
| 1960 | (clobber (reg:CC 33))])] | |
| 1961 | "" | |
| a41c6c53 | 1962 | { |
| b9404c99 UW |
1963 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
| 1964 | rtx reg0 = gen_reg_rtx (dword_mode); | |
| 1965 | rtx reg1 = gen_reg_rtx (dword_mode); | |
| 1966 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
| 1967 | rtx len0 = gen_lowpart (Pmode, reg0); | |
| 9db1d521 | 1968 | |
| b9404c99 UW |
1969 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
| 1970 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
| 1971 | emit_move_insn (len0, operands[1]); | |
| 9db1d521 | 1972 | |
| b9404c99 | 1973 | emit_move_insn (reg1, const0_rtx); |
| a41c6c53 | 1974 | |
| b9404c99 UW |
1975 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
| 1976 | operands[1] = reg0; | |
| 1977 | operands[2] = reg1; | |
| 1978 | }) | |
| a41c6c53 | 1979 | |
| 70128ad9 | 1980 | (define_insn "*clrmem_long_64" |
| b9404c99 UW |
1981 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
| 1982 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
| 9db1d521 | 1983 | (const_int 0)) |
| b9404c99 | 1984 | (use (match_dup 2)) |
| 9f37ccb1 | 1985 | (use (match_operand:TI 1 "register_operand" "d")) |
| 9db1d521 HP |
1986 | (clobber (reg:CC 33))] |
| 1987 | "TARGET_64BIT" | |
| d40c829f | 1988 | "mvcle\t%0,%1,0\;jo\t.-4" |
| 9db1d521 | 1989 | [(set_attr "op_type" "NN") |
| 4023fb28 | 1990 | (set_attr "type" "vs") |
| 9db1d521 HP |
1991 | (set_attr "length" "8")]) |
| 1992 | ||
| 70128ad9 | 1993 | (define_insn "*clrmem_long_31" |
| b9404c99 UW |
1994 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
| 1995 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
| 9db1d521 | 1996 | (const_int 0)) |
| b9404c99 | 1997 | (use (match_dup 2)) |
| 9f37ccb1 | 1998 | (use (match_operand:DI 1 "register_operand" "d")) |
| 9db1d521 HP |
1999 | (clobber (reg:CC 33))] |
| 2000 | "!TARGET_64BIT" | |
| d40c829f | 2001 | "mvcle\t%0,%1,0\;jo\t.-4" |
| 9db1d521 | 2002 | [(set_attr "op_type" "NN") |
| 4023fb28 | 2003 | (set_attr "type" "vs") |
| 9db1d521 HP |
2004 | (set_attr "length" "8")]) |
| 2005 | ||
| 2006 | ; | |
| 358b8f01 | 2007 | ; cmpmemM instruction pattern(s). |
| 9db1d521 HP |
2008 | ; |
| 2009 | ||
| 358b8f01 | 2010 | (define_expand "cmpmemsi" |
| a41c6c53 UW |
2011 | [(set (match_operand:SI 0 "register_operand" "") |
| 2012 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
| 2013 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
| 2014 | (use (match_operand:SI 3 "general_operand" "")) | |
| 2015 | (use (match_operand:SI 4 "" ""))] | |
| 2016 | "" | |
| c7453384 | 2017 | "s390_expand_cmpmem (operands[0], operands[1], |
| a41c6c53 | 2018 | operands[2], operands[3]); DONE;") |
| 9db1d521 | 2019 | |
| a41c6c53 UW |
2020 | ; Compare a block that is up to 256 bytes in length. |
| 2021 | ; The block length is taken as (operands[2] % 256) + 1. | |
| 9db1d521 | 2022 | |
| b9404c99 UW |
2023 | (define_expand "cmpmem_short" |
| 2024 | [(parallel | |
| 5b022de5 UW |
2025 | [(set (reg:CCU 33) |
| 2026 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
| b9404c99 UW |
2027 | (match_operand:BLK 1 "memory_operand" ""))) |
| 2028 | (use (match_operand 2 "nonmemory_operand" "")) | |
| 9bb86f41 | 2029 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
| b9404c99 UW |
2030 | (clobber (match_dup 3))])] |
| 2031 | "" | |
| 2032 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
| 9db1d521 | 2033 | |
| b9404c99 | 2034 | (define_insn "*cmpmem_short" |
| 5b022de5 | 2035 | [(set (reg:CCU 33) |
| 9bb86f41 UW |
2036 | (compare:CCU (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
| 2037 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) | |
| 2038 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
| 2039 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
| 2040 | (clobber (match_scratch 4 "=X,X,&a"))] | |
| b9404c99 | 2041 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
| 9bb86f41 UW |
2042 | && GET_MODE (operands[4]) == Pmode" |
| 2043 | "#" | |
| 2044 | [(set_attr "op_type" "SS,RX,RX") | |
| 2045 | (set_attr "type" "cs")]) | |
| 9db1d521 | 2046 | |
| 9bb86f41 UW |
2047 | (define_split |
| 2048 | [(set (reg:CCU 33) | |
| 2049 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
| 2050 | (match_operand:BLK 1 "memory_operand" ""))) | |
| 2051 | (use (match_operand 2 "const_int_operand" "")) | |
| 2052 | (use (match_operand 3 "immediate_operand" "")) | |
| 2053 | (clobber (scratch))] | |
| 2054 | "reload_completed" | |
| 2055 | [(parallel | |
| 2056 | [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
| 2057 | (use (match_dup 2))])] | |
| 2058 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
| 9db1d521 | 2059 | |
| 9bb86f41 UW |
2060 | (define_split |
| 2061 | [(set (reg:CCU 33) | |
| 2062 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
| 2063 | (match_operand:BLK 1 "memory_operand" ""))) | |
| 2064 | (use (match_operand 2 "register_operand" "")) | |
| 2065 | (use (match_operand 3 "memory_operand" "")) | |
| 2066 | (clobber (scratch))] | |
| 2067 | "reload_completed" | |
| 2068 | [(parallel | |
| 2069 | [(unspec [(match_dup 2) (match_dup 3) | |
| 2070 | (const_int 0)] UNSPEC_EXECUTE) | |
| 2071 | (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
| 2072 | (use (const_int 1))])] | |
| 2073 | "") | |
| 2074 | ||
| 2075 | (define_split | |
| 2076 | [(set (reg:CCU 33) | |
| 2077 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
| 2078 | (match_operand:BLK 1 "memory_operand" ""))) | |
| 2079 | (use (match_operand 2 "register_operand" "")) | |
| 2080 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
| 2081 | (clobber (match_operand 3 "register_operand" ""))] | |
| 2082 | "reload_completed && TARGET_CPU_ZARCH" | |
| 2083 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
| 2084 | (parallel | |
| 2085 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
| 2086 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
| 2087 | (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
| 2088 | (use (const_int 1))])] | |
| 2089 | "operands[4] = gen_label_rtx ();") | |
| 2090 | ||
| 2091 | (define_insn "*clc" | |
| 2092 | [(set (reg:CCU 33) | |
| 2093 | (compare:CCU (match_operand:BLK 0 "memory_operand" "=Q") | |
| 2094 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
| 2095 | (use (match_operand 2 "const_int_operand" "n"))] | |
| 2096 | "" | |
| 2097 | "clc\t%O0(%2,%R0),%1" | |
| 2098 | [(set_attr "op_type" "SS") | |
| 2099 | (set_attr "type" "cs")]) | |
| 9db1d521 | 2100 | |
| a41c6c53 | 2101 | ; Compare a block of arbitrary length. |
| 9db1d521 | 2102 | |
| b9404c99 UW |
2103 | (define_expand "cmpmem_long" |
| 2104 | [(parallel | |
| 2105 | [(clobber (match_dup 2)) | |
| 2106 | (clobber (match_dup 3)) | |
| 5b022de5 UW |
2107 | (set (reg:CCU 33) |
| 2108 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
| b9404c99 UW |
2109 | (match_operand:BLK 1 "memory_operand" ""))) |
| 2110 | (use (match_operand 2 "general_operand" "")) | |
| 2111 | (use (match_dup 3))])] | |
| 2112 | "" | |
| 2113 | { | |
| 2114 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
| 2115 | rtx reg0 = gen_reg_rtx (dword_mode); | |
| 2116 | rtx reg1 = gen_reg_rtx (dword_mode); | |
| 2117 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
| 2118 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
| 2119 | rtx len0 = gen_lowpart (Pmode, reg0); | |
| 2120 | rtx len1 = gen_lowpart (Pmode, reg1); | |
| 2121 | ||
| 2122 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
| 2123 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
| 2124 | emit_move_insn (len0, operands[2]); | |
| 2125 | ||
| 2126 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
| 2127 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
| 2128 | emit_move_insn (len1, operands[2]); | |
| 2129 | ||
| 2130 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
| 2131 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
| 2132 | operands[2] = reg0; | |
| 2133 | operands[3] = reg1; | |
| 2134 | }) | |
| 2135 | ||
| 2136 | (define_insn "*cmpmem_long_64" | |
| 4023fb28 UW |
2137 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
| 2138 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
| 5b022de5 UW |
2139 | (set (reg:CCU 33) |
| 2140 | (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
| f8766020 HP |
2141 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
| 2142 | (use (match_dup 2)) | |
| 2143 | (use (match_dup 3))] | |
| 9db1d521 | 2144 | "TARGET_64BIT" |
| 287ff198 UW |
2145 | "clcle\t%0,%1,0\;jo\t.-4" |
| 2146 | [(set_attr "op_type" "NN") | |
| 2147 | (set_attr "type" "vs") | |
| 2148 | (set_attr "length" "8")]) | |
| 9db1d521 | 2149 | |
| b9404c99 | 2150 | (define_insn "*cmpmem_long_31" |
| 4023fb28 UW |
2151 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
| 2152 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
| 5b022de5 UW |
2153 | (set (reg:CCU 33) |
| 2154 | (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
| f8766020 HP |
2155 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
| 2156 | (use (match_dup 2)) | |
| 2157 | (use (match_dup 3))] | |
| 9db1d521 | 2158 | "!TARGET_64BIT" |
| 287ff198 UW |
2159 | "clcle\t%0,%1,0\;jo\t.-4" |
| 2160 | [(set_attr "op_type" "NN") | |
| 2161 | (set_attr "type" "vs") | |
| 2162 | (set_attr "length" "8")]) | |
| 9db1d521 HP |
2163 | |
| 2164 | ; Convert condition code to integer in range (-1, 0, 1) | |
| 2165 | ||
| 5b022de5 | 2166 | (define_insn "*cmpint_si" |
| 9db1d521 | 2167 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 5b022de5 | 2168 | (unspec:SI [(reg:CCU 33)] UNSPEC_CMPINT))] |
| 9db1d521 | 2169 | "" |
| 9db1d521 | 2170 | { |
| d40c829f UW |
2171 | output_asm_insn ("lhi\t%0,1", operands); |
| 2172 | output_asm_insn ("jh\t.+12", operands); | |
| 2173 | output_asm_insn ("jl\t.+6", operands); | |
| 2174 | output_asm_insn ("sr\t%0,%0", operands); | |
| 2175 | return "lcr\t%0,%0"; | |
| 10bbf137 | 2176 | } |
| 9db1d521 HP |
2177 | [(set_attr "op_type" "NN") |
| 2178 | (set_attr "length" "16") | |
| f2d3c02a | 2179 | (set_attr "type" "other")]) |
| 9db1d521 | 2180 | |
| 5b022de5 | 2181 | (define_insn "*cmpint_di" |
| 9db1d521 | 2182 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 5b022de5 | 2183 | (sign_extend:DI (unspec:SI [(reg:CCU 33)] UNSPEC_CMPINT)))] |
| 9db1d521 | 2184 | "TARGET_64BIT" |
| 9db1d521 | 2185 | { |
| d40c829f | 2186 | output_asm_insn ("lghi\t%0,1", operands); |
| fd87a357 UW |
2187 | output_asm_insn ("jh\t.+16", operands); |
| 2188 | output_asm_insn ("jl\t.+8", operands); | |
| d40c829f UW |
2189 | output_asm_insn ("sgr\t%0,%0", operands); |
| 2190 | return "lcgr\t%0,%0"; | |
| 10bbf137 | 2191 | } |
| 9db1d521 | 2192 | [(set_attr "op_type" "NN") |
| fd87a357 | 2193 | (set_attr "length" "20") |
| f2d3c02a | 2194 | (set_attr "type" "other")]) |
| 9db1d521 | 2195 | |
| 4023fb28 | 2196 | |
| 9db1d521 HP |
2197 | ;; |
| 2198 | ;;- Conversion instructions. | |
| 2199 | ;; | |
| 2200 | ||
| 4023fb28 | 2201 | (define_insn "*sethighqisi" |
| d3632d41 | 2202 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 10bbf137 | 2203 | (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
| 4023fb28 UW |
2204 | (clobber (reg:CC 33))] |
| 2205 | "" | |
| d3632d41 | 2206 | "@ |
| d40c829f UW |
2207 | icm\t%0,8,%1 |
| 2208 | icmy\t%0,8,%1" | |
| d3632d41 | 2209 | [(set_attr "op_type" "RS,RSY")]) |
| 4023fb28 UW |
2210 | |
| 2211 | (define_insn "*sethighhisi" | |
| d3632d41 | 2212 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 10bbf137 | 2213 | (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
| 4023fb28 UW |
2214 | (clobber (reg:CC 33))] |
| 2215 | "" | |
| d3632d41 | 2216 | "@ |
| d40c829f UW |
2217 | icm\t%0,12,%1 |
| 2218 | icmy\t%0,12,%1" | |
| d3632d41 | 2219 | [(set_attr "op_type" "RS,RSY")]) |
| 4023fb28 UW |
2220 | |
| 2221 | (define_insn "*sethighqidi_64" | |
| 2222 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 10bbf137 | 2223 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
| 4023fb28 UW |
2224 | (clobber (reg:CC 33))] |
| 2225 | "TARGET_64BIT" | |
| d40c829f | 2226 | "icmh\t%0,8,%1" |
| d3632d41 | 2227 | [(set_attr "op_type" "RSY")]) |
| 4023fb28 UW |
2228 | |
| 2229 | (define_insn "*sethighqidi_31" | |
| d3632d41 | 2230 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 10bbf137 | 2231 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
| 4023fb28 UW |
2232 | (clobber (reg:CC 33))] |
| 2233 | "!TARGET_64BIT" | |
| d3632d41 | 2234 | "@ |
| d40c829f UW |
2235 | icm\t%0,8,%1 |
| 2236 | icmy\t%0,8,%1" | |
| d3632d41 | 2237 | [(set_attr "op_type" "RS,RSY")]) |
| 4023fb28 | 2238 | |
| cc7ab9b7 UW |
2239 | (define_insn_and_split "*extractqi" |
| 2240 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2241 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
| 2242 | (match_operand 2 "const_int_operand" "n") | |
| 2243 | (const_int 0))) | |
| 2244 | (clobber (reg:CC 33))] | |
| 2245 | "!TARGET_64BIT | |
| 4023fb28 | 2246 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
| cc7ab9b7 UW |
2247 | "#" |
| 2248 | "&& reload_completed" | |
| 4023fb28 | 2249 | [(parallel |
| 10bbf137 | 2250 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
| 4023fb28 UW |
2251 | (clobber (reg:CC 33))]) |
| 2252 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
| 4023fb28 UW |
2253 | { |
| 2254 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
| 2255 | operands[1] = change_address (operands[1], QImode, 0); | |
| 10bbf137 | 2256 | } |
| 0796c16a | 2257 | [(set_attr "atype" "agen")]) |
| 4023fb28 | 2258 | |
| cc7ab9b7 UW |
2259 | (define_insn_and_split "*extracthi" |
| 2260 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2261 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
| 2262 | (match_operand 2 "const_int_operand" "n") | |
| 2263 | (const_int 0))) | |
| 2264 | (clobber (reg:CC 33))] | |
| 2265 | "!TARGET_64BIT | |
| 4023fb28 | 2266 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
| cc7ab9b7 UW |
2267 | "#" |
| 2268 | "&& reload_completed" | |
| 4023fb28 | 2269 | [(parallel |
| 10bbf137 | 2270 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
| 4023fb28 UW |
2271 | (clobber (reg:CC 33))]) |
| 2272 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
| 4023fb28 UW |
2273 | { |
| 2274 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
| 2275 | operands[1] = change_address (operands[1], HImode, 0); | |
| 10bbf137 | 2276 | } |
| 0796c16a | 2277 | [(set_attr "atype" "agen")]) |
| 4023fb28 | 2278 | |
| 9db1d521 HP |
2279 | ; |
| 2280 | ; extendsidi2 instruction pattern(s). | |
| 2281 | ; | |
| 2282 | ||
| 4023fb28 UW |
2283 | (define_expand "extendsidi2" |
| 2284 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2285 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
| 2286 | "" | |
| 2287 | " | |
| 2288 | { | |
| 2289 | if (!TARGET_64BIT) | |
| 2290 | { | |
| 9f37ccb1 UW |
2291 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
| 2292 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
| 2293 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
| 2294 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
| 4023fb28 UW |
2295 | DONE; |
| 2296 | } | |
| 2297 | } | |
| 2298 | ") | |
| 2299 | ||
| 2300 | (define_insn "*extendsidi2" | |
| 9db1d521 HP |
2301 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 2302 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
| 2303 | "TARGET_64BIT" | |
| 2304 | "@ | |
| d40c829f UW |
2305 | lgfr\t%0,%1 |
| 2306 | lgf\t%0,%1" | |
| d3632d41 | 2307 | [(set_attr "op_type" "RRE,RXY")]) |
| 9db1d521 | 2308 | |
| 9db1d521 HP |
2309 | ; |
| 2310 | ; extendhidi2 instruction pattern(s). | |
| 2311 | ; | |
| 2312 | ||
| 4023fb28 UW |
2313 | (define_expand "extendhidi2" |
| 2314 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2315 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
| 2316 | "" | |
| 2317 | " | |
| 2318 | { | |
| 2319 | if (!TARGET_64BIT) | |
| 2320 | { | |
| 2321 | rtx tmp = gen_reg_rtx (SImode); | |
| 2322 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
| 2323 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
| 2324 | DONE; | |
| 2325 | } | |
| 2326 | else | |
| 2327 | { | |
| 2328 | operands[1] = gen_lowpart (DImode, operands[1]); | |
| 2329 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
| c7453384 | 2330 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); |
| 4023fb28 UW |
2331 | DONE; |
| 2332 | } | |
| 2333 | } | |
| 2334 | ") | |
| 2335 | ||
| 2336 | (define_insn "*extendhidi2" | |
| 9db1d521 | 2337 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 4023fb28 | 2338 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
| 9db1d521 | 2339 | "TARGET_64BIT" |
| d40c829f | 2340 | "lgh\t%0,%1" |
| d3632d41 | 2341 | [(set_attr "op_type" "RXY")]) |
| 9db1d521 HP |
2342 | |
| 2343 | ; | |
| 2344 | ; extendqidi2 instruction pattern(s). | |
| 2345 | ; | |
| 2346 | ||
| 4023fb28 UW |
2347 | (define_expand "extendqidi2" |
| 2348 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2349 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
| 2350 | "" | |
| 2351 | " | |
| 2352 | { | |
| 2353 | if (!TARGET_64BIT) | |
| 2354 | { | |
| 2355 | rtx tmp = gen_reg_rtx (SImode); | |
| 2356 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
| 2357 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
| 2358 | DONE; | |
| 2359 | } | |
| 2360 | else | |
| 2361 | { | |
| 2362 | operands[1] = gen_lowpart (DImode, operands[1]); | |
| 2363 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
| c7453384 | 2364 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); |
| 4023fb28 UW |
2365 | DONE; |
| 2366 | } | |
| 2367 | } | |
| 2368 | ") | |
| 2369 | ||
| d3632d41 UW |
2370 | (define_insn "*extendqidi2" |
| 2371 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2372 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
| 2373 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
| d40c829f | 2374 | "lgb\t%0,%1" |
| d3632d41 UW |
2375 | [(set_attr "op_type" "RXY")]) |
| 2376 | ||
| 19796784 AK |
2377 | (define_insn_and_split "*extendqidi2_short_displ" |
| 2378 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 59f8a8be UW |
2379 | (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) |
| 2380 | (clobber (reg:CC 33))] | |
| 19796784 AK |
2381 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" |
| 2382 | "#" | |
| 2383 | "&& reload_completed" | |
| 4023fb28 | 2384 | [(parallel |
| 10bbf137 | 2385 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
| 4023fb28 UW |
2386 | (clobber (reg:CC 33))]) |
| 2387 | (parallel | |
| 2388 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
| 2389 | (clobber (reg:CC 33))])] | |
| 2390 | "") | |
| 9db1d521 HP |
2391 | |
| 2392 | ; | |
| 2393 | ; extendhisi2 instruction pattern(s). | |
| 2394 | ; | |
| 2395 | ||
| 4023fb28 UW |
2396 | (define_expand "extendhisi2" |
| 2397 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2398 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
| 9db1d521 | 2399 | "" |
| 4023fb28 UW |
2400 | " |
| 2401 | { | |
| 2402 | operands[1] = gen_lowpart (SImode, operands[1]); | |
| 2403 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
| c7453384 | 2404 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); |
| 4023fb28 UW |
2405 | DONE; |
| 2406 | } | |
| 2407 | ") | |
| 9db1d521 | 2408 | |
| 4023fb28 | 2409 | (define_insn "*extendhisi2" |
| d3632d41 UW |
2410 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 2411 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
| 4023fb28 | 2412 | "" |
| d3632d41 | 2413 | "@ |
| d40c829f UW |
2414 | lh\t%0,%1 |
| 2415 | lhy\t%0,%1" | |
| d3632d41 | 2416 | [(set_attr "op_type" "RX,RXY")]) |
| 9db1d521 HP |
2417 | |
| 2418 | ; | |
| 2419 | ; extendqisi2 instruction pattern(s). | |
| 2420 | ; | |
| 2421 | ||
| 4023fb28 UW |
2422 | (define_expand "extendqisi2" |
| 2423 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2424 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
| 9db1d521 | 2425 | "" |
| 4023fb28 UW |
2426 | " |
| 2427 | { | |
| 2428 | operands[1] = gen_lowpart (SImode, operands[1]); | |
| 2429 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
| c7453384 | 2430 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); |
| 4023fb28 UW |
2431 | DONE; |
| 2432 | } | |
| 2433 | ") | |
| 9db1d521 | 2434 | |
| d3632d41 UW |
2435 | (define_insn "*extendqisi2" |
| 2436 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2437 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
| 9e8327e3 | 2438 | "TARGET_LONG_DISPLACEMENT" |
| d40c829f | 2439 | "lb\t%0,%1" |
| d3632d41 UW |
2440 | [(set_attr "op_type" "RXY")]) |
| 2441 | ||
| eb457a7a | 2442 | (define_insn_and_split "*extendqisi2_short_displ" |
| 19796784 | 2443 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 59f8a8be UW |
2444 | (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) |
| 2445 | (clobber (reg:CC 33))] | |
| 19796784 AK |
2446 | "!TARGET_LONG_DISPLACEMENT" |
| 2447 | "#" | |
| 2448 | "&& reload_completed" | |
| 4023fb28 | 2449 | [(parallel |
| 10bbf137 | 2450 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
| 4023fb28 UW |
2451 | (clobber (reg:CC 33))]) |
| 2452 | (parallel | |
| 2453 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
| 2454 | (clobber (reg:CC 33))])] | |
| 2455 | "") | |
| 9db1d521 HP |
2456 | |
| 2457 | ; | |
| 2458 | ; extendqihi2 instruction pattern(s). | |
| 2459 | ; | |
| 2460 | ||
| 9db1d521 HP |
2461 | |
| 2462 | ; | |
| 2463 | ; zero_extendsidi2 instruction pattern(s). | |
| 2464 | ; | |
| 2465 | ||
| 4023fb28 UW |
2466 | (define_expand "zero_extendsidi2" |
| 2467 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2468 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
| 2469 | "" | |
| 2470 | " | |
| 2471 | { | |
| 2472 | if (!TARGET_64BIT) | |
| 2473 | { | |
| 9f37ccb1 UW |
2474 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
| 2475 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
| 2476 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
| 4023fb28 UW |
2477 | DONE; |
| 2478 | } | |
| 2479 | } | |
| 2480 | ") | |
| 2481 | ||
| 2482 | (define_insn "*zero_extendsidi2" | |
| 9db1d521 HP |
2483 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 2484 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
| 2485 | "TARGET_64BIT" | |
| 2486 | "@ | |
| d40c829f UW |
2487 | llgfr\t%0,%1 |
| 2488 | llgf\t%0,%1" | |
| d3632d41 | 2489 | [(set_attr "op_type" "RRE,RXY")]) |
| 9db1d521 | 2490 | |
| 9db1d521 HP |
2491 | ; |
| 2492 | ; zero_extendhidi2 instruction pattern(s). | |
| 2493 | ; | |
| 2494 | ||
| 4023fb28 UW |
2495 | (define_expand "zero_extendhidi2" |
| 2496 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2497 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
| 2498 | "" | |
| 2499 | " | |
| 2500 | { | |
| 2501 | if (!TARGET_64BIT) | |
| 2502 | { | |
| 2503 | rtx tmp = gen_reg_rtx (SImode); | |
| 2504 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
| 2505 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
| 2506 | DONE; | |
| 2507 | } | |
| 2508 | else | |
| 2509 | { | |
| 2510 | operands[1] = gen_lowpart (DImode, operands[1]); | |
| 2511 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
| c7453384 | 2512 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); |
| 4023fb28 UW |
2513 | DONE; |
| 2514 | } | |
| 2515 | } | |
| 2516 | ") | |
| 9db1d521 | 2517 | |
| 4023fb28 UW |
2518 | (define_insn "*zero_extendhidi2" |
| 2519 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2520 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
| 9db1d521 | 2521 | "TARGET_64BIT" |
| d40c829f | 2522 | "llgh\t%0,%1" |
| d3632d41 | 2523 | [(set_attr "op_type" "RXY")]) |
| 9db1d521 | 2524 | |
| 288e517f AK |
2525 | ; |
| 2526 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
| 2527 | ; | |
| 2528 | ||
| 2529 | (define_insn "*llgt_sisi" | |
| 2530 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 2531 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
| 2532 | (const_int 2147483647)))] | |
| 2533 | "TARGET_64BIT" | |
| 2534 | "@ | |
| 2535 | llgtr\t%0,%1 | |
| 2536 | llgt\t%0,%1" | |
| 2537 | [(set_attr "op_type" "RRE,RXE")]) | |
| 2538 | ||
| f19a9af7 AK |
2539 | (define_split |
| 2540 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2541 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
| 288e517f AK |
2542 | (const_int 2147483647))) |
| 2543 | (clobber (reg:CC 33))] | |
| f19a9af7 | 2544 | "TARGET_64BIT && reload_completed" |
| 288e517f AK |
2545 | [(set (match_dup 0) |
| 2546 | (and:SI (match_dup 1) | |
| 2547 | (const_int 2147483647)))] | |
| 2548 | "") | |
| 2549 | ||
| 2550 | (define_insn "*llgt_didi" | |
| 2551 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 2552 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
| 2553 | (const_int 2147483647)))] | |
| 2554 | "TARGET_64BIT" | |
| 2555 | "@ | |
| 2556 | llgtr\t%0,%1 | |
| 2557 | llgt\t%0,%N1" | |
| 2558 | [(set_attr "op_type" "RRE,RXE")]) | |
| 2559 | ||
| f19a9af7 AK |
2560 | (define_split |
| 2561 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2562 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
| 288e517f AK |
2563 | (const_int 2147483647))) |
| 2564 | (clobber (reg:CC 33))] | |
| f19a9af7 | 2565 | "TARGET_64BIT && reload_completed" |
| 288e517f AK |
2566 | [(set (match_dup 0) |
| 2567 | (and:DI (match_dup 1) | |
| 2568 | (const_int 2147483647)))] | |
| 2569 | "") | |
| 2570 | ||
| 2571 | (define_insn "*llgt_sidi" | |
| 2572 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2573 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
| 2574 | (const_int 2147483647)))] | |
| 2575 | "TARGET_64BIT" | |
| 2576 | "llgt\t%0,%1" | |
| 2577 | [(set_attr "op_type" "RXE")]) | |
| 2578 | ||
| 2579 | (define_insn_and_split "*llgt_sidi_split" | |
| 2580 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2f7e5a0d | 2581 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) |
| 288e517f AK |
2582 | (const_int 2147483647))) |
| 2583 | (clobber (reg:CC 33))] | |
| 2584 | "TARGET_64BIT" | |
| 2585 | "#" | |
| 2586 | "&& reload_completed" | |
| 2587 | [(set (match_dup 0) | |
| 2f7e5a0d | 2588 | (and:DI (subreg:DI (match_dup 1) 0) |
| 288e517f AK |
2589 | (const_int 2147483647)))] |
| 2590 | "") | |
| 2591 | ||
| 9db1d521 | 2592 | ; |
| 4023fb28 | 2593 | ; zero_extendqidi2 instruction pattern(s) |
| 9db1d521 HP |
2594 | ; |
| 2595 | ||
| 4023fb28 UW |
2596 | (define_expand "zero_extendqidi2" |
| 2597 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2598 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
| 9db1d521 HP |
2599 | "" |
| 2600 | " | |
| 2601 | { | |
| 2602 | if (!TARGET_64BIT) | |
| 2603 | { | |
| 4023fb28 UW |
2604 | rtx tmp = gen_reg_rtx (SImode); |
| 2605 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
| 2606 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
| 9db1d521 HP |
2607 | DONE; |
| 2608 | } | |
| 4023fb28 UW |
2609 | else |
| 2610 | { | |
| 2611 | operands[1] = gen_lowpart (DImode, operands[1]); | |
| 2612 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
| c7453384 | 2613 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); |
| 4023fb28 UW |
2614 | DONE; |
| 2615 | } | |
| 2616 | } | |
| 2617 | ") | |
| 9db1d521 | 2618 | |
| 4023fb28 UW |
2619 | (define_insn "*zero_extendqidi2" |
| 2620 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2621 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
| 9db1d521 | 2622 | "TARGET_64BIT" |
| d40c829f | 2623 | "llgc\t%0,%1" |
| d3632d41 | 2624 | [(set_attr "op_type" "RXY")]) |
| 9db1d521 HP |
2625 | |
| 2626 | ; | |
| 4023fb28 | 2627 | ; zero_extendhisi2 instruction pattern(s). |
| 9db1d521 HP |
2628 | ; |
| 2629 | ||
| 4023fb28 UW |
2630 | (define_expand "zero_extendhisi2" |
| 2631 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2632 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
| 9db1d521 | 2633 | "" |
| 4023fb28 UW |
2634 | " |
| 2635 | { | |
| 2636 | operands[1] = gen_lowpart (SImode, operands[1]); | |
| 2637 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
| 2638 | DONE; | |
| 2639 | } | |
| 2640 | ") | |
| 9db1d521 | 2641 | |
| 4023fb28 | 2642 | (define_insn "*zero_extendhisi2_64" |
| 9db1d521 | 2643 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 4023fb28 | 2644 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
| 9db1d521 | 2645 | "TARGET_64BIT" |
| d40c829f | 2646 | "llgh\t%0,%1" |
| d3632d41 | 2647 | [(set_attr "op_type" "RXY")]) |
| cc7ab9b7 UW |
2648 | |
| 2649 | (define_insn_and_split "*zero_extendhisi2_31" | |
| 2650 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
| 02ed3c5e | 2651 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
| cc7ab9b7 UW |
2652 | (clobber (reg:CC 33))] |
| 2653 | "!TARGET_64BIT" | |
| 2654 | "#" | |
| 2655 | "&& reload_completed" | |
| 2656 | [(set (match_dup 0) (const_int 0)) | |
| 2657 | (parallel | |
| 2658 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
| 2659 | (clobber (reg:CC 33))])] | |
| 2660 | "operands[2] = gen_lowpart (HImode, operands[0]);" | |
| 0796c16a | 2661 | [(set_attr "atype" "agen")]) |
| c7453384 | 2662 | |
| 4023fb28 UW |
2663 | ; |
| 2664 | ; zero_extendqisi2 instruction pattern(s). | |
| 2665 | ; | |
| 9db1d521 HP |
2666 | |
| 2667 | (define_expand "zero_extendqisi2" | |
| 2668 | [(set (match_operand:SI 0 "register_operand" "") | |
| 4023fb28 | 2669 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
| 9db1d521 HP |
2670 | "" |
| 2671 | " | |
| 2672 | { | |
| 4023fb28 UW |
2673 | operands[1] = gen_lowpart (SImode, operands[1]); |
| 2674 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
| 2675 | DONE; | |
| 2676 | } | |
| 2677 | ") | |
| 9db1d521 | 2678 | |
| 4023fb28 UW |
2679 | (define_insn "*zero_extendqisi2_64" |
| 2680 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2681 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
| 9e8327e3 | 2682 | "TARGET_ZARCH" |
| d40c829f | 2683 | "llgc\t%0,%1" |
| d3632d41 | 2684 | [(set_attr "op_type" "RXY")]) |
| cc7ab9b7 UW |
2685 | |
| 2686 | (define_insn_and_split "*zero_extendqisi2_31" | |
| 2687 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
| 2688 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
| 9e8327e3 | 2689 | "!TARGET_ZARCH" |
| cc7ab9b7 UW |
2690 | "#" |
| 2691 | "&& reload_completed" | |
| 2692 | [(set (match_dup 0) (const_int 0)) | |
| 2693 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
| 2694 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
| 0796c16a | 2695 | [(set_attr "atype" "agen")]) |
| c7453384 | 2696 | |
| 9db1d521 HP |
2697 | ; |
| 2698 | ; zero_extendqihi2 instruction pattern(s). | |
| 2699 | ; | |
| 2700 | ||
| 9db1d521 HP |
2701 | (define_expand "zero_extendqihi2" |
| 2702 | [(set (match_operand:HI 0 "register_operand" "") | |
| 4023fb28 | 2703 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
| 9e8327e3 | 2704 | "TARGET_ZARCH" |
| 9db1d521 HP |
2705 | " |
| 2706 | { | |
| 4023fb28 UW |
2707 | operands[1] = gen_lowpart (HImode, operands[1]); |
| 2708 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
| 2709 | DONE; | |
| 2710 | } | |
| 2711 | ") | |
| 9db1d521 | 2712 | |
| 4023fb28 | 2713 | (define_insn "*zero_extendqihi2_64" |
| 9db1d521 | 2714 | [(set (match_operand:HI 0 "register_operand" "=d") |
| cc7ab9b7 | 2715 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
| 9e8327e3 | 2716 | "TARGET_ZARCH" |
| d40c829f | 2717 | "llgc\t%0,%1" |
| d3632d41 | 2718 | [(set_attr "op_type" "RXY")]) |
| 9db1d521 | 2719 | |
| cc7ab9b7 UW |
2720 | (define_insn_and_split "*zero_extendqihi2_31" |
| 2721 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
| 2722 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
| 9e8327e3 | 2723 | "!TARGET_ZARCH" |
| cc7ab9b7 UW |
2724 | "#" |
| 2725 | "&& reload_completed" | |
| 2726 | [(set (match_dup 0) (const_int 0)) | |
| 2727 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
| 2728 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
| 0796c16a | 2729 | [(set_attr "atype" "agen")]) |
| cc7ab9b7 UW |
2730 | |
| 2731 | ||
| 9db1d521 HP |
2732 | ; |
| 2733 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
| 2734 | ; | |
| 2735 | ||
| 2736 | (define_expand "fixuns_truncdfdi2" | |
| 2737 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2738 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
| 2739 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 9db1d521 HP |
2740 | { |
| 2741 | rtx label1 = gen_label_rtx (); | |
| 2742 | rtx label2 = gen_label_rtx (); | |
| 2743 | rtx temp = gen_reg_rtx (DFmode); | |
| 2744 | operands[1] = force_reg (DFmode, operands[1]); | |
| 2745 | ||
| c7453384 | 2746 | emit_insn (gen_cmpdf (operands[1], |
| 4023fb28 | 2747 | CONST_DOUBLE_FROM_REAL_VALUE ( |
| 10bbf137 | 2748 | REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); |
| 9db1d521 | 2749 | emit_jump_insn (gen_blt (label1)); |
| 4023fb28 UW |
2750 | emit_insn (gen_subdf3 (temp, operands[1], |
| 2751 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 10bbf137 | 2752 | REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); |
| 9db1d521 | 2753 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
| f314b9b1 | 2754 | emit_jump (label2); |
| 9db1d521 HP |
2755 | |
| 2756 | emit_label (label1); | |
| 2757 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
| 2758 | emit_label (label2); | |
| 2759 | DONE; | |
| 10bbf137 | 2760 | }) |
| 9db1d521 HP |
2761 | |
| 2762 | (define_expand "fix_truncdfdi2" | |
| 2763 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2764 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
| 2765 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 9db1d521 HP |
2766 | { |
| 2767 | operands[1] = force_reg (DFmode, operands[1]); | |
| 2768 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
| 2769 | DONE; | |
| 10bbf137 | 2770 | }) |
| 9db1d521 HP |
2771 | |
| 2772 | (define_insn "fix_truncdfdi2_ieee" | |
| 2773 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2774 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
| 10bbf137 | 2775 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
| 9db1d521 HP |
2776 | (clobber (reg:CC 33))] |
| 2777 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 2778 | "cgdbr\t%0,%h2,%1" |
| 9db1d521 | 2779 | [(set_attr "op_type" "RRE") |
| 077dab3b | 2780 | (set_attr "type" "ftoi")]) |
| 9db1d521 HP |
2781 | |
| 2782 | ; | |
| 2783 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
| 2784 | ; | |
| 2785 | ||
| 2786 | (define_expand "fixuns_truncdfsi2" | |
| 2787 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2788 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
| 2789 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 9db1d521 HP |
2790 | { |
| 2791 | rtx label1 = gen_label_rtx (); | |
| 2792 | rtx label2 = gen_label_rtx (); | |
| 2793 | rtx temp = gen_reg_rtx (DFmode); | |
| 2794 | ||
| 2795 | operands[1] = force_reg (DFmode,operands[1]); | |
| c7453384 | 2796 | emit_insn (gen_cmpdf (operands[1], |
| 4023fb28 | 2797 | CONST_DOUBLE_FROM_REAL_VALUE ( |
| 10bbf137 | 2798 | REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); |
| 9db1d521 | 2799 | emit_jump_insn (gen_blt (label1)); |
| 4023fb28 UW |
2800 | emit_insn (gen_subdf3 (temp, operands[1], |
| 2801 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 10bbf137 | 2802 | REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); |
| 9db1d521 | 2803 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
| f314b9b1 | 2804 | emit_jump (label2); |
| 9db1d521 HP |
2805 | |
| 2806 | emit_label (label1); | |
| 2807 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
| 2808 | emit_label (label2); | |
| 2809 | DONE; | |
| 10bbf137 | 2810 | }) |
| 9db1d521 HP |
2811 | |
| 2812 | (define_expand "fix_truncdfsi2" | |
| 2813 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2814 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
| 2815 | "TARGET_HARD_FLOAT" | |
| 9db1d521 | 2816 | { |
| c7453384 | 2817 | if (TARGET_IBM_FLOAT) |
| 9db1d521 HP |
2818 | { |
| 2819 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
| 2820 | ||
| c19ec8f9 | 2821 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
| 4023fb28 UW |
2822 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
| 2823 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
| 9db1d521 HP |
2824 | |
| 2825 | operands[1] = force_reg (DFmode, operands[1]); | |
| c7453384 | 2826 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
| 9db1d521 | 2827 | two31r, two32, temp)); |
| c7453384 EC |
2828 | } |
| 2829 | else | |
| 9db1d521 HP |
2830 | { |
| 2831 | operands[1] = force_reg (DFmode, operands[1]); | |
| 2832 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
| 2833 | } | |
| 2834 | ||
| 2835 | DONE; | |
| 10bbf137 | 2836 | }) |
| 9db1d521 HP |
2837 | |
| 2838 | (define_insn "fix_truncdfsi2_ieee" | |
| 2839 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2840 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
| 10bbf137 | 2841 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
| 9db1d521 HP |
2842 | (clobber (reg:CC 33))] |
| 2843 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 2844 | "cfdbr\t%0,%h2,%1" |
| 9db1d521 | 2845 | [(set_attr "op_type" "RRE") |
| 4023fb28 | 2846 | (set_attr "type" "other" )]) |
| 9db1d521 HP |
2847 | |
| 2848 | (define_insn "fix_truncdfsi2_ibm" | |
| 2849 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2850 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
| 4023fb28 UW |
2851 | (use (match_operand:DI 2 "immediate_operand" "m")) |
| 2852 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
| 9db1d521 HP |
2853 | (use (match_operand:BLK 4 "memory_operand" "m")) |
| 2854 | (clobber (reg:CC 33))] | |
| 2855 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 9db1d521 | 2856 | { |
| d40c829f UW |
2857 | output_asm_insn ("sd\t%1,%2", operands); |
| 2858 | output_asm_insn ("aw\t%1,%3", operands); | |
| 2859 | output_asm_insn ("std\t%1,%4", operands); | |
| 2860 | output_asm_insn ("xi\t%N4,128", operands); | |
| 2861 | return "l\t%0,%N4"; | |
| 10bbf137 | 2862 | } |
| 9db1d521 | 2863 | [(set_attr "op_type" "NN") |
| 077dab3b HP |
2864 | (set_attr "type" "ftoi") |
| 2865 | (set_attr "atype" "agen") | |
| 9db1d521 HP |
2866 | (set_attr "length" "20")]) |
| 2867 | ||
| 2868 | ; | |
| 2869 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
| 2870 | ; | |
| 2871 | ||
| 2872 | (define_expand "fixuns_truncsfdi2" | |
| 2873 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2874 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
| 2875 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 9db1d521 HP |
2876 | { |
| 2877 | rtx label1 = gen_label_rtx (); | |
| 2878 | rtx label2 = gen_label_rtx (); | |
| 2879 | rtx temp = gen_reg_rtx (SFmode); | |
| 2880 | ||
| 2881 | operands[1] = force_reg (SFmode, operands[1]); | |
| c7453384 | 2882 | emit_insn (gen_cmpsf (operands[1], |
| 4023fb28 | 2883 | CONST_DOUBLE_FROM_REAL_VALUE ( |
| 10bbf137 | 2884 | REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); |
| 9db1d521 HP |
2885 | emit_jump_insn (gen_blt (label1)); |
| 2886 | ||
| 4023fb28 UW |
2887 | emit_insn (gen_subsf3 (temp, operands[1], |
| 2888 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 10bbf137 | 2889 | REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); |
| 9db1d521 | 2890 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
| f314b9b1 | 2891 | emit_jump (label2); |
| 9db1d521 HP |
2892 | |
| 2893 | emit_label (label1); | |
| 2894 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
| 2895 | emit_label (label2); | |
| 2896 | DONE; | |
| 10bbf137 | 2897 | }) |
| 9db1d521 HP |
2898 | |
| 2899 | (define_expand "fix_truncsfdi2" | |
| 2900 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2901 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
| 2902 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 9db1d521 HP |
2903 | { |
| 2904 | operands[1] = force_reg (SFmode, operands[1]); | |
| 2905 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
| 2906 | DONE; | |
| 10bbf137 | 2907 | }) |
| 9db1d521 HP |
2908 | |
| 2909 | (define_insn "fix_truncsfdi2_ieee" | |
| 2910 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2911 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
| 10bbf137 | 2912 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
| 9db1d521 HP |
2913 | (clobber (reg:CC 33))] |
| 2914 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 2915 | "cgebr\t%0,%h2,%1" |
| 9db1d521 | 2916 | [(set_attr "op_type" "RRE") |
| 077dab3b | 2917 | (set_attr "type" "ftoi")]) |
| 9db1d521 HP |
2918 | |
| 2919 | ; | |
| 2920 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
| 2921 | ; | |
| 2922 | ||
| 2923 | (define_expand "fixuns_truncsfsi2" | |
| 2924 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2925 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
| 2926 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 9db1d521 HP |
2927 | { |
| 2928 | rtx label1 = gen_label_rtx (); | |
| 2929 | rtx label2 = gen_label_rtx (); | |
| 2930 | rtx temp = gen_reg_rtx (SFmode); | |
| 2931 | ||
| 2932 | operands[1] = force_reg (SFmode, operands[1]); | |
| 4023fb28 UW |
2933 | emit_insn (gen_cmpsf (operands[1], |
| 2934 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 10bbf137 | 2935 | REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); |
| 9db1d521 | 2936 | emit_jump_insn (gen_blt (label1)); |
| 4023fb28 UW |
2937 | emit_insn (gen_subsf3 (temp, operands[1], |
| 2938 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 10bbf137 | 2939 | REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); |
| 9db1d521 | 2940 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
| f314b9b1 | 2941 | emit_jump (label2); |
| 9db1d521 HP |
2942 | |
| 2943 | emit_label (label1); | |
| 2944 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
| 2945 | emit_label (label2); | |
| 2946 | DONE; | |
| 10bbf137 | 2947 | }) |
| 9db1d521 HP |
2948 | |
| 2949 | (define_expand "fix_truncsfsi2" | |
| 2950 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2951 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
| 2952 | "TARGET_HARD_FLOAT" | |
| 9db1d521 HP |
2953 | { |
| 2954 | if (TARGET_IBM_FLOAT) | |
| 2955 | { | |
| 2956 | /* Convert to DFmode and then use the POP algorithm. */ | |
| 2957 | rtx temp = gen_reg_rtx (DFmode); | |
| 2958 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
| 2959 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
| 2960 | } | |
| 2961 | else | |
| 2962 | { | |
| 2963 | operands[1] = force_reg (SFmode, operands[1]); | |
| 2964 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
| 2965 | } | |
| 2966 | ||
| 2967 | DONE; | |
| 10bbf137 | 2968 | }) |
| 9db1d521 HP |
2969 | |
| 2970 | (define_insn "fix_truncsfsi2_ieee" | |
| 2971 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2972 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
| 10bbf137 | 2973 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
| 9db1d521 HP |
2974 | (clobber (reg:CC 33))] |
| 2975 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 2976 | "cfebr\t%0,%h2,%1" |
| 9db1d521 | 2977 | [(set_attr "op_type" "RRE") |
| 077dab3b | 2978 | (set_attr "type" "ftoi")]) |
| 9db1d521 HP |
2979 | |
| 2980 | ; | |
| 2981 | ; floatdidf2 instruction pattern(s). | |
| 2982 | ; | |
| 2983 | ||
| 2984 | (define_insn "floatdidf2" | |
| 2985 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 4023fb28 UW |
2986 | (float:DF (match_operand:DI 1 "register_operand" "d"))) |
| 2987 | (clobber (reg:CC 33))] | |
| 9db1d521 | 2988 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| d40c829f | 2989 | "cdgbr\t%0,%1" |
| 9db1d521 | 2990 | [(set_attr "op_type" "RRE") |
| f0bf1270 | 2991 | (set_attr "type" "itof" )]) |
| 9db1d521 HP |
2992 | |
| 2993 | ; | |
| 2994 | ; floatdisf2 instruction pattern(s). | |
| 2995 | ; | |
| 2996 | ||
| 2997 | (define_insn "floatdisf2" | |
| 2998 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 4023fb28 UW |
2999 | (float:SF (match_operand:DI 1 "register_operand" "d"))) |
| 3000 | (clobber (reg:CC 33))] | |
| 9db1d521 | 3001 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| d40c829f | 3002 | "cegbr\t%0,%1" |
| 9db1d521 | 3003 | [(set_attr "op_type" "RRE") |
| 077dab3b | 3004 | (set_attr "type" "itof" )]) |
| 9db1d521 HP |
3005 | |
| 3006 | ; | |
| 3007 | ; floatsidf2 instruction pattern(s). | |
| 3008 | ; | |
| 3009 | ||
| 3010 | (define_expand "floatsidf2" | |
| 4023fb28 UW |
3011 | [(parallel |
| 3012 | [(set (match_operand:DF 0 "register_operand" "") | |
| 3013 | (float:DF (match_operand:SI 1 "register_operand" ""))) | |
| 3014 | (clobber (reg:CC 33))])] | |
| 9db1d521 | 3015 | "TARGET_HARD_FLOAT" |
| 9db1d521 | 3016 | { |
| c7453384 | 3017 | if (TARGET_IBM_FLOAT) |
| 9db1d521 HP |
3018 | { |
| 3019 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
| 3020 | ||
| c19ec8f9 | 3021 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
| c7453384 | 3022 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
| 9db1d521 HP |
3023 | |
| 3024 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
| 3025 | DONE; | |
| 3026 | } | |
| 10bbf137 | 3027 | }) |
| 9db1d521 HP |
3028 | |
| 3029 | (define_insn "floatsidf2_ieee" | |
| 3030 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 4023fb28 UW |
3031 | (float:DF (match_operand:SI 1 "register_operand" "d"))) |
| 3032 | (clobber (reg:CC 33))] | |
| 9db1d521 | 3033 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| d40c829f | 3034 | "cdfbr\t%0,%1" |
| 9db1d521 | 3035 | [(set_attr "op_type" "RRE") |
| 077dab3b | 3036 | (set_attr "type" "itof" )]) |
| 9db1d521 HP |
3037 | |
| 3038 | (define_insn "floatsidf2_ibm" | |
| 3039 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 3040 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
| 4023fb28 | 3041 | (use (match_operand:DI 2 "immediate_operand" "m")) |
| 9db1d521 HP |
3042 | (use (match_operand:BLK 3 "memory_operand" "m")) |
| 3043 | (clobber (reg:CC 33))] | |
| 3044 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 9db1d521 | 3045 | { |
| d40c829f UW |
3046 | output_asm_insn ("st\t%1,%N3", operands); |
| 3047 | output_asm_insn ("xi\t%N3,128", operands); | |
| 3048 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
| 3049 | output_asm_insn ("ld\t%0,%3", operands); | |
| 3050 | return "sd\t%0,%2"; | |
| 10bbf137 | 3051 | } |
| 9db1d521 | 3052 | [(set_attr "op_type" "NN") |
| 4023fb28 | 3053 | (set_attr "type" "other" ) |
| 077dab3b | 3054 | (set_attr "atype" "agen") |
| 9db1d521 HP |
3055 | (set_attr "length" "20")]) |
| 3056 | ||
| 3057 | ; | |
| 3058 | ; floatsisf2 instruction pattern(s). | |
| 3059 | ; | |
| 3060 | ||
| 3061 | (define_expand "floatsisf2" | |
| 4023fb28 UW |
3062 | [(parallel |
| 3063 | [(set (match_operand:SF 0 "register_operand" "") | |
| 3064 | (float:SF (match_operand:SI 1 "register_operand" ""))) | |
| 3065 | (clobber (reg:CC 33))])] | |
| 9db1d521 | 3066 | "TARGET_HARD_FLOAT" |
| 9db1d521 HP |
3067 | { |
| 3068 | if (TARGET_IBM_FLOAT) | |
| 3069 | { | |
| 3070 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
| 3071 | rtx temp = gen_reg_rtx (DFmode); | |
| 3072 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
| 3073 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
| 3074 | DONE; | |
| 3075 | } | |
| 10bbf137 | 3076 | }) |
| 9db1d521 HP |
3077 | |
| 3078 | (define_insn "floatsisf2_ieee" | |
| 3079 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 4023fb28 UW |
3080 | (float:SF (match_operand:SI 1 "register_operand" "d"))) |
| 3081 | (clobber (reg:CC 33))] | |
| 9db1d521 | 3082 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| d40c829f | 3083 | "cefbr\t%0,%1" |
| 9db1d521 | 3084 | [(set_attr "op_type" "RRE") |
| 077dab3b | 3085 | (set_attr "type" "itof" )]) |
| 9db1d521 HP |
3086 | |
| 3087 | ; | |
| 3088 | ; truncdfsf2 instruction pattern(s). | |
| 3089 | ; | |
| 3090 | ||
| 3091 | (define_expand "truncdfsf2" | |
| 3092 | [(set (match_operand:SF 0 "register_operand" "") | |
| 3093 | (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] | |
| 3094 | "TARGET_HARD_FLOAT" | |
| 4023fb28 | 3095 | "") |
| 9db1d521 HP |
3096 | |
| 3097 | (define_insn "truncdfsf2_ieee" | |
| 3098 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 4023fb28 | 3099 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] |
| 9db1d521 | 3100 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| d40c829f | 3101 | "ledbr\t%0,%1" |
| ce50cae8 | 3102 | [(set_attr "op_type" "RRE")]) |
| 9db1d521 HP |
3103 | |
| 3104 | (define_insn "truncdfsf2_ibm" | |
| 3105 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| d3632d41 | 3106 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))] |
| 9db1d521 HP |
3107 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 3108 | "@ | |
| d40c829f UW |
3109 | lrer\t%0,%1 |
| 3110 | le\t%0,%1" | |
| 4023fb28 | 3111 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 3112 | (set_attr "type" "floads,floads")]) |
| 9db1d521 HP |
3113 | |
| 3114 | ; | |
| 3115 | ; extendsfdf2 instruction pattern(s). | |
| 3116 | ; | |
| 3117 | ||
| 3118 | (define_expand "extendsfdf2" | |
| 3119 | [(set (match_operand:DF 0 "register_operand" "") | |
| 3120 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
| 3121 | "TARGET_HARD_FLOAT" | |
| 9db1d521 HP |
3122 | { |
| 3123 | if (TARGET_IBM_FLOAT) | |
| 3124 | { | |
| 3125 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
| 3126 | DONE; | |
| 3127 | } | |
| 10bbf137 | 3128 | }) |
| 9db1d521 HP |
3129 | |
| 3130 | (define_insn "extendsfdf2_ieee" | |
| 3131 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| d3632d41 | 3132 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
| 9db1d521 HP |
3133 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 3134 | "@ | |
| d40c829f UW |
3135 | ldebr\t%0,%1 |
| 3136 | ldeb\t%0,%1" | |
| 077dab3b HP |
3137 | [(set_attr "op_type" "RRE,RXE") |
| 3138 | (set_attr "type" "floads,floads")]) | |
| 9db1d521 HP |
3139 | |
| 3140 | (define_insn "extendsfdf2_ibm" | |
| 3141 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| d3632d41 | 3142 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
| 9db1d521 HP |
3143 | (clobber (reg:CC 33))] |
| 3144 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3145 | "@ | |
| d40c829f UW |
3146 | sdr\t%0,%0\;ler\t%0,%1 |
| 3147 | sdr\t%0,%0\;le\t%0,%1" | |
| 077dab3b HP |
3148 | [(set_attr "op_type" "NN,NN") |
| 3149 | (set_attr "atype" "reg,agen") | |
| 3150 | (set_attr "length" "4,6") | |
| c7453384 | 3151 | (set_attr "type" "o2,o2")]) |
| 9db1d521 HP |
3152 | |
| 3153 | ||
| 3154 | ;; | |
| fae778eb | 3155 | ;; ARITHMETIC OPERATIONS |
| 9db1d521 | 3156 | ;; |
| fae778eb | 3157 | ; arithmetic operations set the ConditionCode, |
| 9db1d521 HP |
3158 | ; because of unpredictable Bits in Register for Halfword and Byte |
| 3159 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
| 3160 | ||
| 07893d4f UW |
3161 | ;; |
| 3162 | ;;- Add instructions. | |
| 3163 | ;; | |
| 3164 | ||
| 1c7b1b7e UW |
3165 | ; |
| 3166 | ; addti3 instruction pattern(s). | |
| 3167 | ; | |
| 3168 | ||
| 3169 | (define_insn_and_split "addti3" | |
| 3170 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
| 3171 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
| 3172 | (match_operand:TI 2 "general_operand" "do") ) ) | |
| 3173 | (clobber (reg:CC 33))] | |
| 3174 | "TARGET_64BIT" | |
| 3175 | "#" | |
| 3176 | "&& reload_completed" | |
| 3177 | [(parallel | |
| 3178 | [(set (reg:CCL1 33) | |
| 3179 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) | |
| 3180 | (match_dup 7))) | |
| 3181 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
| 3182 | (parallel | |
| 3183 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
| 3184 | (ltu:DI (reg:CCL1 33) (const_int 0)))) | |
| 3185 | (clobber (reg:CC 33))])] | |
| 3186 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
| 3187 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
| 3188 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
| 3189 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
| 3190 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
| 3191 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" | |
| 3192 | [(set_attr "op_type" "NN")]) | |
| 3193 | ||
| 07893d4f UW |
3194 | ; |
| 3195 | ; adddi3 instruction pattern(s). | |
| 3196 | ; | |
| 3197 | ||
| 07893d4f UW |
3198 | (define_insn "*adddi3_sign" |
| 3199 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3200 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
| 3201 | (match_operand:DI 1 "register_operand" "0,0"))) | |
| 3202 | (clobber (reg:CC 33))] | |
| 3203 | "TARGET_64BIT" | |
| 3204 | "@ | |
| d40c829f UW |
3205 | agfr\t%0,%2 |
| 3206 | agf\t%0,%2" | |
| d3632d41 | 3207 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f UW |
3208 | |
| 3209 | (define_insn "*adddi3_zero_cc" | |
| c7453384 | 3210 | [(set (reg 33) |
| 07893d4f UW |
3211 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
| 3212 | (match_operand:DI 1 "register_operand" "0,0")) | |
| 3213 | (const_int 0))) | |
| 3214 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3215 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
| 3216 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
| 3217 | "@ | |
| d40c829f UW |
3218 | algfr\t%0,%2 |
| 3219 | algf\t%0,%2" | |
| d3632d41 | 3220 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f UW |
3221 | |
| 3222 | (define_insn "*adddi3_zero_cconly" | |
| c7453384 | 3223 | [(set (reg 33) |
| 07893d4f UW |
3224 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
| 3225 | (match_operand:DI 1 "register_operand" "0,0")) | |
| 3226 | (const_int 0))) | |
| 3227 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 3228 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
| 3229 | "@ | |
| d40c829f UW |
3230 | algfr\t%0,%2 |
| 3231 | algf\t%0,%2" | |
| d3632d41 | 3232 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f UW |
3233 | |
| 3234 | (define_insn "*adddi3_zero" | |
| 3235 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3236 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
| 3237 | (match_operand:DI 1 "register_operand" "0,0"))) | |
| 3238 | (clobber (reg:CC 33))] | |
| 3239 | "TARGET_64BIT" | |
| 3240 | "@ | |
| d40c829f UW |
3241 | algfr\t%0,%2 |
| 3242 | algf\t%0,%2" | |
| d3632d41 | 3243 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f | 3244 | |
| 0a3bdf9d | 3245 | (define_insn "*adddi3_imm_cc" |
| c7453384 | 3246 | [(set (reg 33) |
| 0a3bdf9d UW |
3247 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
| 3248 | (match_operand:DI 2 "const_int_operand" "K")) | |
| 3249 | (const_int 0))) | |
| 3250 | (set (match_operand:DI 0 "register_operand" "=d") | |
| 3251 | (plus:DI (match_dup 1) (match_dup 2)))] | |
| c7453384 EC |
3252 | "TARGET_64BIT |
| 3253 | && s390_match_ccmode (insn, CCAmode) | |
| f19a9af7 | 3254 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
| d40c829f | 3255 | "aghi\t%0,%h2" |
| 077dab3b | 3256 | [(set_attr "op_type" "RI")]) |
| 0a3bdf9d | 3257 | |
| b2ba71ca UW |
3258 | (define_insn "*adddi3_carry1_cc" |
| 3259 | [(set (reg 33) | |
| 3260 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
| 3261 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 3262 | (match_dup 1))) | |
| 3263 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3264 | (plus:DI (match_dup 1) (match_dup 2)))] | |
| 3265 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
| 3266 | "@ | |
| 3267 | algr\t%0,%2 | |
| 3268 | alg\t%0,%2" | |
| 3269 | [(set_attr "op_type" "RRE,RXY")]) | |
| 3270 | ||
| 3271 | (define_insn "*adddi3_carry1_cconly" | |
| 3272 | [(set (reg 33) | |
| 3273 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
| 3274 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 3275 | (match_dup 1))) | |
| 3276 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 3277 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
| 3278 | "@ | |
| 3279 | algr\t%0,%2 | |
| 3280 | alg\t%0,%2" | |
| 3281 | [(set_attr "op_type" "RRE,RXY")]) | |
| 3282 | ||
| 3283 | (define_insn "*adddi3_carry2_cc" | |
| 3284 | [(set (reg 33) | |
| 3285 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
| 3286 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 3287 | (match_dup 2))) | |
| 3288 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3289 | (plus:DI (match_dup 1) (match_dup 2)))] | |
| 3290 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
| 3291 | "@ | |
| 3292 | algr\t%0,%2 | |
| 3293 | alg\t%0,%2" | |
| 3294 | [(set_attr "op_type" "RRE,RXY")]) | |
| 3295 | ||
| 3296 | (define_insn "*adddi3_carry2_cconly" | |
| 3297 | [(set (reg 33) | |
| 3298 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
| 3299 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 3300 | (match_dup 2))) | |
| 3301 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 3302 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
| 3303 | "@ | |
| 3304 | algr\t%0,%2 | |
| 3305 | alg\t%0,%2" | |
| 3306 | [(set_attr "op_type" "RRE,RXY")]) | |
| 3307 | ||
| 07893d4f | 3308 | (define_insn "*adddi3_cc" |
| c7453384 | 3309 | [(set (reg 33) |
| 96fd3851 | 3310 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 07893d4f UW |
3311 | (match_operand:DI 2 "general_operand" "d,m")) |
| 3312 | (const_int 0))) | |
| 3313 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3314 | (plus:DI (match_dup 1) (match_dup 2)))] | |
| 3315 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
| 3316 | "@ | |
| d40c829f UW |
3317 | algr\t%0,%2 |
| 3318 | alg\t%0,%2" | |
| d3632d41 | 3319 | [(set_attr "op_type" "RRE,RXY")]) |
| 9db1d521 | 3320 | |
| 07893d4f | 3321 | (define_insn "*adddi3_cconly" |
| c7453384 | 3322 | [(set (reg 33) |
| 96fd3851 | 3323 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 07893d4f UW |
3324 | (match_operand:DI 2 "general_operand" "d,m")) |
| 3325 | (const_int 0))) | |
| 3326 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 3327 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
| 3328 | "@ | |
| d40c829f UW |
3329 | algr\t%0,%2 |
| 3330 | alg\t%0,%2" | |
| d3632d41 | 3331 | [(set_attr "op_type" "RRE,RXY")]) |
| 9db1d521 | 3332 | |
| 07893d4f | 3333 | (define_insn "*adddi3_cconly2" |
| c7453384 | 3334 | [(set (reg 33) |
| 96fd3851 | 3335 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 07893d4f UW |
3336 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
| 3337 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 3338 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
| 9db1d521 | 3339 | "@ |
| d40c829f UW |
3340 | algr\t%0,%2 |
| 3341 | alg\t%0,%2" | |
| d3632d41 | 3342 | [(set_attr "op_type" "RRE,RXY")]) |
| 9db1d521 | 3343 | |
| 07893d4f | 3344 | (define_insn "*adddi3_64" |
| 9db1d521 | 3345 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
| 96fd3851 | 3346 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
| 9db1d521 HP |
3347 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
| 3348 | (clobber (reg:CC 33))] | |
| 3349 | "TARGET_64BIT" | |
| 3350 | "@ | |
| d40c829f UW |
3351 | agr\t%0,%2 |
| 3352 | aghi\t%0,%h2 | |
| 3353 | ag\t%0,%2" | |
| d3632d41 | 3354 | [(set_attr "op_type" "RRE,RI,RXY")]) |
| 9db1d521 | 3355 | |
| e69166de UW |
3356 | (define_insn_and_split "*adddi3_31z" |
| 3357 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
| 3358 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
| 3359 | (match_operand:DI 2 "general_operand" "do") ) ) | |
| 3360 | (clobber (reg:CC 33))] | |
| 3361 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
| 3362 | "#" | |
| 3363 | "&& reload_completed" | |
| 3364 | [(parallel | |
| 3365 | [(set (reg:CCL1 33) | |
| 3366 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
| 3367 | (match_dup 7))) | |
| 3368 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
| 3369 | (parallel | |
| 3370 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
| 3371 | (ltu:SI (reg:CCL1 33) (const_int 0)))) | |
| 3372 | (clobber (reg:CC 33))])] | |
| 3373 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
| 3374 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
| 3375 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
| 3376 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
| 3377 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
| 3378 | operands[8] = operand_subword (operands[2], 1, 0, DImode);" | |
| 3379 | [(set_attr "op_type" "NN")]) | |
| 3380 | ||
| 07893d4f UW |
3381 | (define_insn_and_split "*adddi3_31" |
| 3382 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
| 96fd3851 | 3383 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
| 97c6f7ad | 3384 | (match_operand:DI 2 "general_operand" "do") ) ) |
| 9db1d521 | 3385 | (clobber (reg:CC 33))] |
| e69166de | 3386 | "!TARGET_CPU_ZARCH" |
| 07893d4f UW |
3387 | "#" |
| 3388 | "&& reload_completed" | |
| 3389 | [(parallel | |
| 3390 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
| 3391 | (clobber (reg:CC 33))]) | |
| 3392 | (parallel | |
| 3393 | [(set (reg:CCL1 33) | |
| 3394 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
| 3395 | (match_dup 7))) | |
| 3396 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
| 3397 | (set (pc) | |
| 3398 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
| 3399 | (pc) | |
| 3400 | (label_ref (match_dup 9)))) | |
| 3401 | (parallel | |
| 3402 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
| 3403 | (clobber (reg:CC 33))]) | |
| 3404 | (match_dup 9)] | |
| 97c6f7ad UW |
3405 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
| 3406 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
| 3407 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
| 3408 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
| 3409 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
| 3410 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
| 07893d4f | 3411 | operands[9] = gen_label_rtx ();" |
| 0796c16a | 3412 | [(set_attr "op_type" "NN")]) |
| 9db1d521 HP |
3413 | |
| 3414 | (define_expand "adddi3" | |
| 07893d4f UW |
3415 | [(parallel |
| 3416 | [(set (match_operand:DI 0 "register_operand" "") | |
| 96fd3851 | 3417 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
| 07893d4f UW |
3418 | (match_operand:DI 2 "general_operand" ""))) |
| 3419 | (clobber (reg:CC 33))])] | |
| 9db1d521 | 3420 | "" |
| 07893d4f | 3421 | "") |
| 9db1d521 | 3422 | |
| 9db1d521 HP |
3423 | ; |
| 3424 | ; addsi3 instruction pattern(s). | |
| 3425 | ; | |
| 9db1d521 | 3426 | |
| 0a3bdf9d | 3427 | (define_insn "*addsi3_imm_cc" |
| c7453384 | 3428 | [(set (reg 33) |
| 0a3bdf9d UW |
3429 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
| 3430 | (match_operand:SI 2 "const_int_operand" "K")) | |
| 3431 | (const_int 0))) | |
| 3432 | (set (match_operand:SI 0 "register_operand" "=d") | |
| 3433 | (plus:SI (match_dup 1) (match_dup 2)))] | |
| 3434 | "s390_match_ccmode (insn, CCAmode) | |
| f19a9af7 | 3435 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
| d40c829f | 3436 | "ahi\t%0,%h2" |
| 077dab3b | 3437 | [(set_attr "op_type" "RI")]) |
| 0a3bdf9d | 3438 | |
| 07893d4f | 3439 | (define_insn "*addsi3_carry1_cc" |
| c7453384 | 3440 | [(set (reg 33) |
| d3632d41 UW |
3441 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 3442 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 07893d4f | 3443 | (match_dup 1))) |
| d3632d41 | 3444 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 07893d4f | 3445 | (plus:SI (match_dup 1) (match_dup 2)))] |
| c7453384 | 3446 | "s390_match_ccmode (insn, CCL1mode)" |
| 07893d4f | 3447 | "@ |
| d40c829f UW |
3448 | alr\t%0,%2 |
| 3449 | al\t%0,%2 | |
| 3450 | aly\t%0,%2" | |
| d3632d41 | 3451 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 07893d4f UW |
3452 | |
| 3453 | (define_insn "*addsi3_carry1_cconly" | |
| c7453384 | 3454 | [(set (reg 33) |
| d3632d41 UW |
3455 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 3456 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 07893d4f | 3457 | (match_dup 1))) |
| d3632d41 | 3458 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
| c7453384 | 3459 | "s390_match_ccmode (insn, CCL1mode)" |
| 07893d4f | 3460 | "@ |
| d40c829f UW |
3461 | alr\t%0,%2 |
| 3462 | al\t%0,%2 | |
| 3463 | aly\t%0,%2" | |
| d3632d41 | 3464 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 07893d4f UW |
3465 | |
| 3466 | (define_insn "*addsi3_carry2_cc" | |
| c7453384 | 3467 | [(set (reg 33) |
| d3632d41 UW |
3468 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 3469 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 07893d4f | 3470 | (match_dup 2))) |
| d3632d41 | 3471 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 07893d4f | 3472 | (plus:SI (match_dup 1) (match_dup 2)))] |
| c7453384 | 3473 | "s390_match_ccmode (insn, CCL1mode)" |
| 07893d4f | 3474 | "@ |
| d40c829f UW |
3475 | alr\t%0,%2 |
| 3476 | al\t%0,%2 | |
| 3477 | aly\t%0,%2" | |
| d3632d41 | 3478 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 07893d4f UW |
3479 | |
| 3480 | (define_insn "*addsi3_carry2_cconly" | |
| c7453384 | 3481 | [(set (reg 33) |
| d3632d41 UW |
3482 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 3483 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 07893d4f | 3484 | (match_dup 2))) |
| d3632d41 | 3485 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
| c7453384 | 3486 | "s390_match_ccmode (insn, CCL1mode)" |
| 07893d4f | 3487 | "@ |
| d40c829f UW |
3488 | alr\t%0,%2 |
| 3489 | al\t%0,%2 | |
| 3490 | aly\t%0,%2" | |
| d3632d41 | 3491 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 07893d4f | 3492 | |
| 9db1d521 | 3493 | (define_insn "*addsi3_cc" |
| c7453384 | 3494 | [(set (reg 33) |
| d3632d41 UW |
3495 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 3496 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 9db1d521 | 3497 | (const_int 0))) |
| d3632d41 | 3498 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 9db1d521 | 3499 | (plus:SI (match_dup 1) (match_dup 2)))] |
| c7453384 | 3500 | "s390_match_ccmode (insn, CCLmode)" |
| 9db1d521 | 3501 | "@ |
| d40c829f UW |
3502 | alr\t%0,%2 |
| 3503 | al\t%0,%2 | |
| 3504 | aly\t%0,%2" | |
| d3632d41 | 3505 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 HP |
3506 | |
| 3507 | (define_insn "*addsi3_cconly" | |
| c7453384 | 3508 | [(set (reg 33) |
| d3632d41 UW |
3509 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 3510 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 9db1d521 | 3511 | (const_int 0))) |
| d3632d41 | 3512 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
| c7453384 | 3513 | "s390_match_ccmode (insn, CCLmode)" |
| 9db1d521 | 3514 | "@ |
| d40c829f UW |
3515 | alr\t%0,%2 |
| 3516 | al\t%0,%2 | |
| 3517 | aly\t%0,%2" | |
| d3632d41 | 3518 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 HP |
3519 | |
| 3520 | (define_insn "*addsi3_cconly2" | |
| c7453384 | 3521 | [(set (reg 33) |
| d3632d41 UW |
3522 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 3523 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
| 3524 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
| b2ba71ca | 3525 | "s390_match_ccmode (insn, CCLmode)" |
| 9db1d521 | 3526 | "@ |
| d40c829f UW |
3527 | alr\t%0,%2 |
| 3528 | al\t%0,%2 | |
| 3529 | aly\t%0,%2" | |
| d3632d41 | 3530 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 | 3531 | |
| 07893d4f | 3532 | (define_insn "*addsi3_sign" |
| d3632d41 UW |
3533 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 3534 | (plus:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 3535 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
| 07893d4f UW |
3536 | (clobber (reg:CC 33))] |
| 3537 | "" | |
| d3632d41 | 3538 | "@ |
| d40c829f UW |
3539 | ah\t%0,%2 |
| 3540 | ahy\t%0,%2" | |
| d3632d41 | 3541 | [(set_attr "op_type" "RX,RXY")]) |
| 07893d4f | 3542 | |
| 9db1d521 | 3543 | (define_insn "addsi3" |
| d3632d41 UW |
3544 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
| 3545 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
| 3546 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
| 9db1d521 HP |
3547 | (clobber (reg:CC 33))] |
| 3548 | "" | |
| 3549 | "@ | |
| d40c829f UW |
3550 | ar\t%0,%2 |
| 3551 | ahi\t%0,%h2 | |
| 3552 | a\t%0,%2 | |
| 3553 | ay\t%0,%2" | |
| d3632d41 | 3554 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
| 9db1d521 | 3555 | |
| 9db1d521 HP |
3556 | ; |
| 3557 | ; adddf3 instruction pattern(s). | |
| 3558 | ; | |
| 3559 | ||
| 3560 | (define_expand "adddf3" | |
| 3561 | [(parallel | |
| 3562 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 96fd3851 | 3563 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
| d3632d41 | 3564 | (match_operand:DF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
3565 | (clobber (reg:CC 33))])] |
| 3566 | "TARGET_HARD_FLOAT" | |
| 3567 | "") | |
| 3568 | ||
| 3569 | (define_insn "*adddf3" | |
| 3570 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 96fd3851 | 3571 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
| d3632d41 | 3572 | (match_operand:DF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
3573 | (clobber (reg:CC 33))] |
| 3574 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3575 | "@ | |
| d40c829f UW |
3576 | adbr\t%0,%2 |
| 3577 | adb\t%0,%2" | |
| ce50cae8 | 3578 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 3579 | (set_attr "type" "fsimpd,fsimpd")]) |
| 9db1d521 | 3580 | |
| 3ef093a8 AK |
3581 | (define_insn "*adddf3_cc" |
| 3582 | [(set (reg 33) | |
| 3583 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
| 3584 | (match_operand:DF 2 "general_operand" "f,R")) | |
| 3585 | (match_operand:DF 3 "const0_operand" ""))) | |
| 3586 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3587 | (plus:DF (match_dup 1) (match_dup 2)))] | |
| 3588 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3589 | "@ | |
| d40c829f UW |
3590 | adbr\t%0,%2 |
| 3591 | adb\t%0,%2" | |
| 3ef093a8 AK |
3592 | [(set_attr "op_type" "RRE,RXE") |
| 3593 | (set_attr "type" "fsimpd,fsimpd")]) | |
| 3594 | ||
| 3595 | (define_insn "*adddf3_cconly" | |
| 3596 | [(set (reg 33) | |
| 3597 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
| 3598 | (match_operand:DF 2 "general_operand" "f,R")) | |
| 3599 | (match_operand:DF 3 "const0_operand" ""))) | |
| 3600 | (clobber (match_scratch:DF 0 "=f,f"))] | |
| 3601 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3602 | "@ | |
| d40c829f UW |
3603 | adbr\t%0,%2 |
| 3604 | adb\t%0,%2" | |
| 3ef093a8 AK |
3605 | [(set_attr "op_type" "RRE,RXE") |
| 3606 | (set_attr "type" "fsimpd,fsimpd")]) | |
| 3607 | ||
| 9db1d521 HP |
3608 | (define_insn "*adddf3_ibm" |
| 3609 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 96fd3851 | 3610 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
| d3632d41 | 3611 | (match_operand:DF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
3612 | (clobber (reg:CC 33))] |
| 3613 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3614 | "@ | |
| d40c829f UW |
3615 | adr\t%0,%2 |
| 3616 | ad\t%0,%2" | |
| 9db1d521 | 3617 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 3618 | (set_attr "type" "fsimpd,fsimpd")]) |
| 9db1d521 HP |
3619 | |
| 3620 | ; | |
| 3621 | ; addsf3 instruction pattern(s). | |
| 3622 | ; | |
| 3623 | ||
| 3624 | (define_expand "addsf3" | |
| 3625 | [(parallel | |
| 3626 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 96fd3851 | 3627 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
| d3632d41 | 3628 | (match_operand:SF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
3629 | (clobber (reg:CC 33))])] |
| 3630 | "TARGET_HARD_FLOAT" | |
| 3631 | "") | |
| 3632 | ||
| 3633 | (define_insn "*addsf3" | |
| 3634 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 96fd3851 | 3635 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
| d3632d41 | 3636 | (match_operand:SF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
3637 | (clobber (reg:CC 33))] |
| 3638 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3639 | "@ | |
| d40c829f UW |
3640 | aebr\t%0,%2 |
| 3641 | aeb\t%0,%2" | |
| ce50cae8 | 3642 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 3643 | (set_attr "type" "fsimps,fsimps")]) |
| 9db1d521 | 3644 | |
| 3ef093a8 AK |
3645 | (define_insn "*addsf3_cc" |
| 3646 | [(set (reg 33) | |
| 3647 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
| 3648 | (match_operand:SF 2 "general_operand" "f,R")) | |
| 3649 | (match_operand:SF 3 "const0_operand" ""))) | |
| 3650 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3651 | (plus:SF (match_dup 1) (match_dup 2)))] | |
| 3652 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3653 | "@ | |
| d40c829f UW |
3654 | aebr\t%0,%2 |
| 3655 | aeb\t%0,%2" | |
| 3ef093a8 AK |
3656 | [(set_attr "op_type" "RRE,RXE") |
| 3657 | (set_attr "type" "fsimps,fsimps")]) | |
| 3658 | ||
| 3659 | (define_insn "*addsf3_cconly" | |
| 3660 | [(set (reg 33) | |
| 3661 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
| 3662 | (match_operand:SF 2 "general_operand" "f,R")) | |
| 3663 | (match_operand:SF 3 "const0_operand" ""))) | |
| 3664 | (clobber (match_scratch:SF 0 "=f,f"))] | |
| 3665 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3666 | "@ | |
| d40c829f UW |
3667 | aebr\t%0,%2 |
| 3668 | aeb\t%0,%2" | |
| 3ef093a8 AK |
3669 | [(set_attr "op_type" "RRE,RXE") |
| 3670 | (set_attr "type" "fsimps,fsimps")]) | |
| 3671 | ||
| 9db1d521 HP |
3672 | (define_insn "*addsf3" |
| 3673 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 96fd3851 | 3674 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
| d3632d41 | 3675 | (match_operand:SF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
3676 | (clobber (reg:CC 33))] |
| 3677 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3678 | "@ | |
| d40c829f UW |
3679 | aer\t%0,%2 |
| 3680 | ae\t%0,%2" | |
| 9db1d521 | 3681 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 3682 | (set_attr "type" "fsimps,fsimps")]) |
| 9db1d521 HP |
3683 | |
| 3684 | ||
| 3685 | ;; | |
| 3686 | ;;- Subtract instructions. | |
| 3687 | ;; | |
| 3688 | ||
| 1c7b1b7e UW |
3689 | ; |
| 3690 | ; subti3 instruction pattern(s). | |
| 3691 | ; | |
| 3692 | ||
| 3693 | (define_insn_and_split "subti3" | |
| 3694 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
| 3695 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
| 3696 | (match_operand:TI 2 "general_operand" "do") ) ) | |
| 3697 | (clobber (reg:CC 33))] | |
| 3698 | "TARGET_64BIT" | |
| 3699 | "#" | |
| 3700 | "&& reload_completed" | |
| 3701 | [(parallel | |
| 3702 | [(set (reg:CCL2 33) | |
| 3703 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) | |
| 3704 | (match_dup 7))) | |
| 3705 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
| 3706 | (parallel | |
| 3707 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
| 3708 | (gtu:DI (reg:CCL2 33) (const_int 0)))) | |
| 3709 | (clobber (reg:CC 33))])] | |
| 3710 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
| 3711 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
| 3712 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
| 3713 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
| 3714 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
| 3715 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" | |
| 3716 | [(set_attr "op_type" "NN")]) | |
| 3717 | ||
| 9db1d521 HP |
3718 | ; |
| 3719 | ; subdi3 instruction pattern(s). | |
| 3720 | ; | |
| 3721 | ||
| 07893d4f UW |
3722 | (define_insn "*subdi3_sign" |
| 3723 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3724 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3725 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
| 3726 | (clobber (reg:CC 33))] | |
| 3727 | "TARGET_64BIT" | |
| 3728 | "@ | |
| d40c829f UW |
3729 | sgfr\t%0,%2 |
| 3730 | sgf\t%0,%2" | |
| d3632d41 | 3731 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f UW |
3732 | |
| 3733 | (define_insn "*subdi3_zero_cc" | |
| c7453384 | 3734 | [(set (reg 33) |
| 07893d4f UW |
3735 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
| 3736 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
| 3737 | (const_int 0))) | |
| 3738 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3739 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
| 3740 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
| 3741 | "@ | |
| d40c829f UW |
3742 | slgfr\t%0,%2 |
| 3743 | slgf\t%0,%2" | |
| d3632d41 | 3744 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f UW |
3745 | |
| 3746 | (define_insn "*subdi3_zero_cconly" | |
| c7453384 | 3747 | [(set (reg 33) |
| 07893d4f UW |
3748 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
| 3749 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
| 3750 | (const_int 0))) | |
| 3751 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 3752 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
| 3753 | "@ | |
| d40c829f UW |
3754 | slgfr\t%0,%2 |
| 3755 | slgf\t%0,%2" | |
| d3632d41 | 3756 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f UW |
3757 | |
| 3758 | (define_insn "*subdi3_zero" | |
| 3759 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3760 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3761 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
| 3762 | (clobber (reg:CC 33))] | |
| 3763 | "TARGET_64BIT" | |
| 3764 | "@ | |
| d40c829f UW |
3765 | slgfr\t%0,%2 |
| 3766 | slgf\t%0,%2" | |
| d3632d41 | 3767 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f | 3768 | |
| b2ba71ca UW |
3769 | (define_insn "*subdi3_borrow_cc" |
| 3770 | [(set (reg 33) | |
| 3771 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3772 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 3773 | (match_dup 1))) | |
| 3774 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3775 | (minus:DI (match_dup 1) (match_dup 2)))] | |
| 3776 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
| 3777 | "@ | |
| 3778 | slgr\t%0,%2 | |
| 3779 | slg\t%0,%2" | |
| 3780 | [(set_attr "op_type" "RRE,RXY")]) | |
| 3781 | ||
| 3782 | (define_insn "*subdi3_borrow_cconly" | |
| 3783 | [(set (reg 33) | |
| 3784 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3785 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 3786 | (match_dup 1))) | |
| 3787 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 3788 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
| 3789 | "@ | |
| 3790 | slgr\t%0,%2 | |
| 3791 | slg\t%0,%2" | |
| 3792 | [(set_attr "op_type" "RRE,RXY")]) | |
| 3793 | ||
| 07893d4f UW |
3794 | (define_insn "*subdi3_cc" |
| 3795 | [(set (reg 33) | |
| 3796 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3797 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 3798 | (const_int 0))) | |
| 3799 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3800 | (minus:DI (match_dup 1) (match_dup 2)))] | |
| b2ba71ca | 3801 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
| 07893d4f | 3802 | "@ |
| d40c829f UW |
3803 | slgr\t%0,%2 |
| 3804 | slg\t%0,%2" | |
| d3632d41 | 3805 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f | 3806 | |
| 5d880bd2 UW |
3807 | (define_insn "*subdi3_cc2" |
| 3808 | [(set (reg 33) | |
| 3809 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
| 3810 | (match_operand:DI 2 "general_operand" "d,m"))) | |
| 3811 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3812 | (minus:DI (match_dup 1) (match_dup 2)))] | |
| 3813 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
| 3814 | "@ | |
| 3815 | slgr\t%0,%2 | |
| 3816 | slg\t%0,%2" | |
| 3817 | [(set_attr "op_type" "RRE,RXY")]) | |
| 3818 | ||
| 07893d4f UW |
3819 | (define_insn "*subdi3_cconly" |
| 3820 | [(set (reg 33) | |
| 3821 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3822 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 3823 | (const_int 0))) | |
| 3824 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| b2ba71ca | 3825 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
| 07893d4f | 3826 | "@ |
| d40c829f UW |
3827 | slgr\t%0,%2 |
| 3828 | slg\t%0,%2" | |
| d3632d41 | 3829 | [(set_attr "op_type" "RRE,RXY")]) |
| 07893d4f | 3830 | |
| 5d880bd2 UW |
3831 | (define_insn "*subdi3_cconly2" |
| 3832 | [(set (reg 33) | |
| 3833 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
| 3834 | (match_operand:DI 2 "general_operand" "d,m"))) | |
| 3835 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 3836 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
| 3837 | "@ | |
| 3838 | slgr\t%0,%2 | |
| 3839 | slg\t%0,%2" | |
| 3840 | [(set_attr "op_type" "RRE,RXY")]) | |
| 3841 | ||
| 9db1d521 HP |
3842 | (define_insn "*subdi3_64" |
| 3843 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3844 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3845 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
| 3846 | (clobber (reg:CC 33))] | |
| 3847 | "TARGET_64BIT" | |
| 3848 | "@ | |
| d40c829f UW |
3849 | sgr\t%0,%2 |
| 3850 | sg\t%0,%2" | |
| 077dab3b | 3851 | [(set_attr "op_type" "RRE,RRE")]) |
| 9db1d521 | 3852 | |
| e69166de UW |
3853 | (define_insn_and_split "*subdi3_31z" |
| 3854 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
| 3855 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
| 3856 | (match_operand:DI 2 "general_operand" "do") ) ) | |
| 3857 | (clobber (reg:CC 33))] | |
| 3858 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
| 3859 | "#" | |
| 3860 | "&& reload_completed" | |
| 3861 | [(parallel | |
| 3862 | [(set (reg:CCL2 33) | |
| 3863 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
| 3864 | (match_dup 7))) | |
| 3865 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
| 3866 | (parallel | |
| 3867 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
| 3868 | (gtu:SI (reg:CCL2 33) (const_int 0)))) | |
| 3869 | (clobber (reg:CC 33))])] | |
| 3870 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
| 3871 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
| 3872 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
| 3873 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
| 3874 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
| 3875 | operands[8] = operand_subword (operands[2], 1, 0, DImode);" | |
| 3876 | [(set_attr "op_type" "NN")]) | |
| 3877 | ||
| 07893d4f UW |
3878 | (define_insn_and_split "*subdi3_31" |
| 3879 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
| 3880 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
| 97c6f7ad | 3881 | (match_operand:DI 2 "general_operand" "do") ) ) |
| 9db1d521 | 3882 | (clobber (reg:CC 33))] |
| e69166de | 3883 | "!TARGET_CPU_ZARCH" |
| 07893d4f UW |
3884 | "#" |
| 3885 | "&& reload_completed" | |
| 3886 | [(parallel | |
| 3887 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
| 3888 | (clobber (reg:CC 33))]) | |
| 3889 | (parallel | |
| 3890 | [(set (reg:CCL2 33) | |
| 3891 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
| 3892 | (match_dup 7))) | |
| 3893 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
| 3894 | (set (pc) | |
| 3895 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
| 3896 | (pc) | |
| 3897 | (label_ref (match_dup 9)))) | |
| 3898 | (parallel | |
| 3899 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
| 3900 | (clobber (reg:CC 33))]) | |
| 3901 | (match_dup 9)] | |
| 97c6f7ad UW |
3902 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
| 3903 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
| 3904 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
| 3905 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
| 3906 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
| 3907 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
| 07893d4f | 3908 | operands[9] = gen_label_rtx ();" |
| 0796c16a | 3909 | [(set_attr "op_type" "NN")]) |
| 07893d4f UW |
3910 | |
| 3911 | (define_expand "subdi3" | |
| 3912 | [(parallel | |
| 3913 | [(set (match_operand:DI 0 "register_operand" "") | |
| 3914 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
| 3915 | (match_operand:DI 2 "general_operand" ""))) | |
| 3916 | (clobber (reg:CC 33))])] | |
| 9db1d521 | 3917 | "" |
| 07893d4f | 3918 | "") |
| 9db1d521 HP |
3919 | |
| 3920 | ; | |
| 3921 | ; subsi3 instruction pattern(s). | |
| 3922 | ; | |
| 3923 | ||
| 07893d4f UW |
3924 | (define_insn "*subsi3_borrow_cc" |
| 3925 | [(set (reg 33) | |
| d3632d41 UW |
3926 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
| 3927 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 07893d4f | 3928 | (match_dup 1))) |
| d3632d41 | 3929 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 07893d4f | 3930 | (minus:SI (match_dup 1) (match_dup 2)))] |
| b2ba71ca | 3931 | "s390_match_ccmode (insn, CCL2mode)" |
| 07893d4f | 3932 | "@ |
| d40c829f UW |
3933 | slr\t%0,%2 |
| 3934 | sl\t%0,%2 | |
| 3935 | sly\t%0,%2" | |
| d3632d41 | 3936 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 07893d4f UW |
3937 | |
| 3938 | (define_insn "*subsi3_borrow_cconly" | |
| 3939 | [(set (reg 33) | |
| d3632d41 UW |
3940 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
| 3941 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 07893d4f | 3942 | (match_dup 1))) |
| d3632d41 | 3943 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
| b2ba71ca | 3944 | "s390_match_ccmode (insn, CCL2mode)" |
| 07893d4f | 3945 | "@ |
| d40c829f UW |
3946 | slr\t%0,%2 |
| 3947 | sl\t%0,%2 | |
| 3948 | sly\t%0,%2" | |
| b2ba71ca | 3949 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 07893d4f | 3950 | |
| 9db1d521 HP |
3951 | (define_insn "*subsi3_cc" |
| 3952 | [(set (reg 33) | |
| d3632d41 UW |
3953 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
| 3954 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 9db1d521 | 3955 | (const_int 0))) |
| d3632d41 | 3956 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 9db1d521 | 3957 | (minus:SI (match_dup 1) (match_dup 2)))] |
| b2ba71ca | 3958 | "s390_match_ccmode (insn, CCLmode)" |
| 9db1d521 | 3959 | "@ |
| d40c829f UW |
3960 | slr\t%0,%2 |
| 3961 | sl\t%0,%2 | |
| 3962 | sly\t%0,%2" | |
| d3632d41 | 3963 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 | 3964 | |
| 5d880bd2 UW |
3965 | (define_insn "*subsi3_cc2" |
| 3966 | [(set (reg 33) | |
| 3967 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
| 3968 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
| 3969 | (set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 3970 | (minus:SI (match_dup 1) (match_dup 2)))] | |
| 3971 | "s390_match_ccmode (insn, CCL3mode)" | |
| 3972 | "@ | |
| 3973 | slr\t%0,%2 | |
| 3974 | sl\t%0,%2 | |
| 3975 | sly\t%0,%2" | |
| 3976 | [(set_attr "op_type" "RR,RX,RXY")]) | |
| 3977 | ||
| 9db1d521 HP |
3978 | (define_insn "*subsi3_cconly" |
| 3979 | [(set (reg 33) | |
| d3632d41 UW |
3980 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
| 3981 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 9db1d521 | 3982 | (const_int 0))) |
| d3632d41 | 3983 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
| b2ba71ca | 3984 | "s390_match_ccmode (insn, CCLmode)" |
| 9db1d521 | 3985 | "@ |
| d40c829f UW |
3986 | slr\t%0,%2 |
| 3987 | sl\t%0,%2 | |
| 3988 | sly\t%0,%2" | |
| d3632d41 | 3989 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 | 3990 | |
| 5d880bd2 UW |
3991 | (define_insn "*subsi3_cconly2" |
| 3992 | [(set (reg 33) | |
| 3993 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
| 3994 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
| 3995 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
| 3996 | "s390_match_ccmode (insn, CCL3mode)" | |
| 3997 | "@ | |
| 3998 | slr\t%0,%2 | |
| 3999 | sl\t%0,%2 | |
| 4000 | sly\t%0,%2" | |
| 4001 | [(set_attr "op_type" "RR,RX,RXY")]) | |
| 4002 | ||
| 07893d4f | 4003 | (define_insn "*subsi3_sign" |
| d3632d41 UW |
4004 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 4005 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 4006 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
| 07893d4f UW |
4007 | (clobber (reg:CC 33))] |
| 4008 | "" | |
| d3632d41 | 4009 | "@ |
| d40c829f UW |
4010 | sh\t%0,%2 |
| 4011 | shy\t%0,%2" | |
| d3632d41 | 4012 | [(set_attr "op_type" "RX,RXY")]) |
| 07893d4f | 4013 | |
| 9db1d521 | 4014 | (define_insn "subsi3" |
| d3632d41 UW |
4015 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 4016 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
| 4017 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
| 9db1d521 HP |
4018 | (clobber (reg:CC 33))] |
| 4019 | "" | |
| 4020 | "@ | |
| d40c829f UW |
4021 | sr\t%0,%2 |
| 4022 | s\t%0,%2 | |
| 4023 | sy\t%0,%2" | |
| d3632d41 | 4024 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 | 4025 | |
| 9db1d521 HP |
4026 | |
| 4027 | ; | |
| 4028 | ; subdf3 instruction pattern(s). | |
| 4029 | ; | |
| 4030 | ||
| 4031 | (define_expand "subdf3" | |
| 4032 | [(parallel | |
| 4033 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 4034 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
| d3632d41 | 4035 | (match_operand:DF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
4036 | (clobber (reg:CC 33))])] |
| 4037 | "TARGET_HARD_FLOAT" | |
| 4038 | "") | |
| 4039 | ||
| 4040 | (define_insn "*subdf3" | |
| 4041 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 4042 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
| d3632d41 | 4043 | (match_operand:DF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
4044 | (clobber (reg:CC 33))] |
| 4045 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 4046 | "@ | |
| d40c829f UW |
4047 | sdbr\t%0,%2 |
| 4048 | sdb\t%0,%2" | |
| ce50cae8 | 4049 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 4050 | (set_attr "type" "fsimpd,fsimpd")]) |
| 9db1d521 | 4051 | |
| 3ef093a8 AK |
4052 | (define_insn "*subdf3_cc" |
| 4053 | [(set (reg 33) | |
| 4dbb5970 | 4054 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
| 3ef093a8 AK |
4055 | (match_operand:DF 2 "general_operand" "f,R")) |
| 4056 | (match_operand:DF 3 "const0_operand" ""))) | |
| 4057 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
| 4058 | (plus:DF (match_dup 1) (match_dup 2)))] | |
| 4059 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 4060 | "@ | |
| d40c829f UW |
4061 | sdbr\t%0,%2 |
| 4062 | sdb\t%0,%2" | |
| 3ef093a8 AK |
4063 | [(set_attr "op_type" "RRE,RXE") |
| 4064 | (set_attr "type" "fsimpd,fsimpd")]) | |
| 4065 | ||
| 4066 | (define_insn "*subdf3_cconly" | |
| 4067 | [(set (reg 33) | |
| 4dbb5970 | 4068 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
| 3ef093a8 AK |
4069 | (match_operand:DF 2 "general_operand" "f,R")) |
| 4070 | (match_operand:DF 3 "const0_operand" ""))) | |
| 4071 | (clobber (match_scratch:DF 0 "=f,f"))] | |
| 4072 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 4073 | "@ | |
| d40c829f UW |
4074 | sdbr\t%0,%2 |
| 4075 | sdb\t%0,%2" | |
| 3ef093a8 AK |
4076 | [(set_attr "op_type" "RRE,RXE") |
| 4077 | (set_attr "type" "fsimpd,fsimpd")]) | |
| 4078 | ||
| 9db1d521 HP |
4079 | (define_insn "*subdf3_ibm" |
| 4080 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 4081 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
| d3632d41 | 4082 | (match_operand:DF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
4083 | (clobber (reg:CC 33))] |
| 4084 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 4085 | "@ | |
| d40c829f UW |
4086 | sdr\t%0,%2 |
| 4087 | sd\t%0,%2" | |
| 9db1d521 | 4088 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 4089 | (set_attr "type" "fsimpd,fsimpd")]) |
| 9db1d521 HP |
4090 | |
| 4091 | ; | |
| 4092 | ; subsf3 instruction pattern(s). | |
| 4093 | ; | |
| 4094 | ||
| 4095 | (define_expand "subsf3" | |
| 4096 | [(parallel | |
| 4097 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 4098 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
| d3632d41 | 4099 | (match_operand:SF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
4100 | (clobber (reg:CC 33))])] |
| 4101 | "TARGET_HARD_FLOAT" | |
| 4102 | "") | |
| 4103 | ||
| 4104 | (define_insn "*subsf3" | |
| 4105 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 4106 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
| d3632d41 | 4107 | (match_operand:SF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
4108 | (clobber (reg:CC 33))] |
| 4109 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 4110 | "@ | |
| d40c829f UW |
4111 | sebr\t%0,%2 |
| 4112 | seb\t%0,%2" | |
| ce50cae8 | 4113 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 4114 | (set_attr "type" "fsimps,fsimps")]) |
| 9db1d521 | 4115 | |
| 3ef093a8 AK |
4116 | (define_insn "*subsf3_cc" |
| 4117 | [(set (reg 33) | |
| 4dbb5970 | 4118 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
| 3ef093a8 AK |
4119 | (match_operand:SF 2 "general_operand" "f,R")) |
| 4120 | (match_operand:SF 3 "const0_operand" ""))) | |
| 4121 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
| 4122 | (minus:SF (match_dup 1) (match_dup 2)))] | |
| 4123 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 4124 | "@ | |
| d40c829f UW |
4125 | sebr\t%0,%2 |
| 4126 | seb\t%0,%2" | |
| 3ef093a8 AK |
4127 | [(set_attr "op_type" "RRE,RXE") |
| 4128 | (set_attr "type" "fsimps,fsimps")]) | |
| 4129 | ||
| 4130 | (define_insn "*subsf3_cconly" | |
| 4131 | [(set (reg 33) | |
| 4dbb5970 | 4132 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
| 3ef093a8 AK |
4133 | (match_operand:SF 2 "general_operand" "f,R")) |
| 4134 | (match_operand:SF 3 "const0_operand" ""))) | |
| 4135 | (clobber (match_scratch:SF 0 "=f,f"))] | |
| 4136 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 4137 | "@ | |
| d40c829f UW |
4138 | sebr\t%0,%2 |
| 4139 | seb\t%0,%2" | |
| 3ef093a8 AK |
4140 | [(set_attr "op_type" "RRE,RXE") |
| 4141 | (set_attr "type" "fsimps,fsimps")]) | |
| 4142 | ||
| 9db1d521 HP |
4143 | (define_insn "*subsf3_ibm" |
| 4144 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 4145 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
| d3632d41 | 4146 | (match_operand:SF 2 "general_operand" "f,R"))) |
| 9db1d521 HP |
4147 | (clobber (reg:CC 33))] |
| 4148 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 4149 | "@ | |
| d40c829f UW |
4150 | ser\t%0,%2 |
| 4151 | se\t%0,%2" | |
| 9db1d521 | 4152 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 4153 | (set_attr "type" "fsimps,fsimps")]) |
| 9db1d521 HP |
4154 | |
| 4155 | ||
| e69166de UW |
4156 | ;; |
| 4157 | ;;- Conditional add/subtract instructions. | |
| 4158 | ;; | |
| 4159 | ||
| 4160 | ; | |
| 4161 | ; adddicc instruction pattern(s). | |
| 4162 | ; | |
| 4163 | ||
| 4164 | (define_insn "*adddi3_alc_cc" | |
| 2f7e5a0d | 4165 | [(set (reg 33) |
| e69166de UW |
4166 | (compare |
| 4167 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
| 4168 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 4169 | (match_operand:DI 3 "s390_alc_comparison" "")) | |
| 4170 | (const_int 0))) | |
| 4171 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4172 | (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
| 2f7e5a0d | 4173 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
| e69166de UW |
4174 | "@ |
| 4175 | alcgr\\t%0,%2 | |
| 4176 | alcg\\t%0,%2" | |
| 4177 | [(set_attr "op_type" "RRE,RXY")]) | |
| 4178 | ||
| 4179 | (define_insn "*adddi3_alc" | |
| 4180 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4181 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
| 4182 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 4183 | (match_operand:DI 3 "s390_alc_comparison" ""))) | |
| 2f7e5a0d EC |
4184 | (clobber (reg:CC 33))] |
| 4185 | "TARGET_64BIT" | |
| e69166de UW |
4186 | "@ |
| 4187 | alcgr\\t%0,%2 | |
| 4188 | alcg\\t%0,%2" | |
| 4189 | [(set_attr "op_type" "RRE,RXY")]) | |
| 4190 | ||
| 4191 | (define_insn "*subdi3_slb_cc" | |
| 2f7e5a0d | 4192 | [(set (reg 33) |
| e69166de UW |
4193 | (compare |
| 4194 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
| 4195 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 4196 | (match_operand:DI 3 "s390_slb_comparison" "")) | |
| 4197 | (const_int 0))) | |
| 4198 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4199 | (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
| 2f7e5a0d | 4200 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
| e69166de UW |
4201 | "@ |
| 4202 | slbgr\\t%0,%2 | |
| 4203 | slbg\\t%0,%2" | |
| 4204 | [(set_attr "op_type" "RRE,RXY")]) | |
| 4205 | ||
| 4206 | (define_insn "*subdi3_slb" | |
| 4207 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4208 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
| 4209 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 4210 | (match_operand:DI 3 "s390_slb_comparison" ""))) | |
| 2f7e5a0d EC |
4211 | (clobber (reg:CC 33))] |
| 4212 | "TARGET_64BIT" | |
| e69166de UW |
4213 | "@ |
| 4214 | slbgr\\t%0,%2 | |
| 4215 | slbg\\t%0,%2" | |
| 4216 | [(set_attr "op_type" "RRE,RXY")]) | |
| 4217 | ||
| 5d880bd2 UW |
4218 | (define_expand "adddicc" |
| 4219 | [(match_operand:DI 0 "register_operand" "") | |
| 4220 | (match_operand 1 "comparison_operator" "") | |
| 4221 | (match_operand:DI 2 "register_operand" "") | |
| 4222 | (match_operand:DI 3 "const_int_operand" "")] | |
| 4223 | "TARGET_64BIT" | |
| 4224 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
| 4225 | s390_compare_op0, s390_compare_op1, | |
| 4226 | operands[0], operands[2], | |
| 4227 | operands[3])) FAIL; DONE;") | |
| 4228 | ||
| e69166de UW |
4229 | ; |
| 4230 | ; addsicc instruction pattern(s). | |
| 4231 | ; | |
| 4232 | ||
| 4233 | (define_insn "*addsi3_alc_cc" | |
| 2f7e5a0d | 4234 | [(set (reg 33) |
| e69166de UW |
4235 | (compare |
| 4236 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
| 4237 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 4238 | (match_operand:SI 3 "s390_alc_comparison" "")) | |
| 4239 | (const_int 0))) | |
| 4240 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
| 4241 | (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
| 2f7e5a0d | 4242 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
| e69166de UW |
4243 | "@ |
| 4244 | alcr\\t%0,%2 | |
| 4245 | alc\\t%0,%2" | |
| 4246 | [(set_attr "op_type" "RRE,RXY")]) | |
| 4247 | ||
| 4248 | (define_insn "*addsi3_alc" | |
| 4249 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 4250 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
| 4251 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 4252 | (match_operand:SI 3 "s390_alc_comparison" ""))) | |
| 4253 | (clobber (reg:CC 33))] | |
| 2f7e5a0d | 4254 | "TARGET_CPU_ZARCH" |
| e69166de UW |
4255 | "@ |
| 4256 | alcr\\t%0,%2 | |
| 4257 | alc\\t%0,%2" | |
| 4258 | [(set_attr "op_type" "RRE,RXY")]) | |
| 4259 | ||
| 4260 | (define_insn "*subsi3_slb_cc" | |
| 2f7e5a0d | 4261 | [(set (reg 33) |
| e69166de UW |
4262 | (compare |
| 4263 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
| 4264 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 4265 | (match_operand:SI 3 "s390_slb_comparison" "")) | |
| 4266 | (const_int 0))) | |
| 4267 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
| 4268 | (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
| 2f7e5a0d | 4269 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
| e69166de UW |
4270 | "@ |
| 4271 | slbr\\t%0,%2 | |
| 4272 | slb\\t%0,%2" | |
| 4273 | [(set_attr "op_type" "RRE,RXY")]) | |
| 4274 | ||
| 4275 | (define_insn "*subsi3_slb" | |
| 4276 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 4277 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
| 4278 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 4279 | (match_operand:SI 3 "s390_slb_comparison" ""))) | |
| 2f7e5a0d EC |
4280 | (clobber (reg:CC 33))] |
| 4281 | "TARGET_CPU_ZARCH" | |
| e69166de UW |
4282 | "@ |
| 4283 | slbr\\t%0,%2 | |
| 4284 | slb\\t%0,%2" | |
| 4285 | [(set_attr "op_type" "RRE,RXY")]) | |
| 4286 | ||
| 5d880bd2 UW |
4287 | (define_expand "addsicc" |
| 4288 | [(match_operand:SI 0 "register_operand" "") | |
| 4289 | (match_operand 1 "comparison_operator" "") | |
| 4290 | (match_operand:SI 2 "register_operand" "") | |
| 4291 | (match_operand:SI 3 "const_int_operand" "")] | |
| 4292 | "TARGET_CPU_ZARCH" | |
| 4293 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
| 4294 | s390_compare_op0, s390_compare_op1, | |
| 4295 | operands[0], operands[2], | |
| 4296 | operands[3])) FAIL; DONE;") | |
| 4297 | ||
| 4298 | ; | |
| 4299 | ; scond instruction pattern(s). | |
| 4300 | ; | |
| 4301 | ||
| 4302 | (define_insn_and_split "*sconddi" | |
| 4303 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
| 4304 | (match_operand:DI 1 "s390_alc_comparison" "")) | |
| 4305 | (clobber (reg:CC 33))] | |
| 4306 | "TARGET_64BIT" | |
| 4307 | "#" | |
| 4308 | "&& reload_completed" | |
| 4309 | [(set (match_dup 0) (const_int 0)) | |
| 4310 | (parallel | |
| 4311 | [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0)) | |
| 4312 | (match_dup 1))) | |
| 4313 | (clobber (reg:CC 33))])] | |
| 4314 | "" | |
| 4315 | [(set_attr "op_type" "NN")]) | |
| 4316 | ||
| 4317 | (define_insn_and_split "*scondsi" | |
| 4318 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
| 4319 | (match_operand:SI 1 "s390_alc_comparison" "")) | |
| 4320 | (clobber (reg:CC 33))] | |
| 4321 | "TARGET_CPU_ZARCH" | |
| 4322 | "#" | |
| 4323 | "&& reload_completed" | |
| 4324 | [(set (match_dup 0) (const_int 0)) | |
| 4325 | (parallel | |
| 4326 | [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0)) | |
| 4327 | (match_dup 1))) | |
| 4328 | (clobber (reg:CC 33))])] | |
| 4329 | "" | |
| 4330 | [(set_attr "op_type" "NN")]) | |
| 4331 | ||
| 4332 | (define_insn_and_split "*sconddi_neg" | |
| 4333 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
| 4334 | (match_operand:DI 1 "s390_slb_comparison" "")) | |
| 4335 | (clobber (reg:CC 33))] | |
| 4336 | "TARGET_64BIT" | |
| 4337 | "#" | |
| 4338 | "&& reload_completed" | |
| 4339 | [(set (match_dup 0) (const_int 0)) | |
| 4340 | (parallel | |
| 4341 | [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0)) | |
| 4342 | (match_dup 1))) | |
| 4343 | (clobber (reg:CC 33))]) | |
| 4344 | (parallel | |
| 4345 | [(set (match_dup 0) (neg:DI (match_dup 0))) | |
| 4346 | (clobber (reg:CC 33))])] | |
| 4347 | "" | |
| 4348 | [(set_attr "op_type" "NN")]) | |
| 4349 | ||
| 4350 | (define_insn_and_split "*scondsi_neg" | |
| 4351 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
| 4352 | (match_operand:SI 1 "s390_slb_comparison" "")) | |
| 4353 | (clobber (reg:CC 33))] | |
| 4354 | "TARGET_CPU_ZARCH" | |
| 4355 | "#" | |
| 4356 | "&& reload_completed" | |
| 4357 | [(set (match_dup 0) (const_int 0)) | |
| 4358 | (parallel | |
| 4359 | [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0)) | |
| 4360 | (match_dup 1))) | |
| 4361 | (clobber (reg:CC 33))]) | |
| 4362 | (parallel | |
| 4363 | [(set (match_dup 0) (neg:SI (match_dup 0))) | |
| 4364 | (clobber (reg:CC 33))])] | |
| 4365 | "" | |
| 4366 | [(set_attr "op_type" "NN")]) | |
| 4367 | ||
| 4368 | (define_expand "sltu" | |
| 4369 | [(match_operand:SI 0 "register_operand" "")] | |
| 4370 | "TARGET_CPU_ZARCH" | |
| 4371 | "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1, | |
| 4372 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
| 4373 | ||
| 4374 | (define_expand "sgtu" | |
| 4375 | [(match_operand:SI 0 "register_operand" "")] | |
| 4376 | "TARGET_CPU_ZARCH" | |
| 4377 | "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1, | |
| 4378 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
| 4379 | ||
| 4380 | (define_expand "sleu" | |
| 4381 | [(match_operand:SI 0 "register_operand" "")] | |
| 4382 | "TARGET_CPU_ZARCH" | |
| 4383 | "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1, | |
| 4384 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
| 4385 | ||
| 4386 | (define_expand "sgeu" | |
| 4387 | [(match_operand:SI 0 "register_operand" "")] | |
| 4388 | "TARGET_CPU_ZARCH" | |
| 4389 | "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1, | |
| 4390 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
| 4391 | ||
| e69166de | 4392 | |
| 9db1d521 HP |
4393 | ;; |
| 4394 | ;;- Multiply instructions. | |
| 4395 | ;; | |
| 4396 | ||
| 4023fb28 UW |
4397 | ; |
| 4398 | ; muldi3 instruction pattern(s). | |
| 4399 | ; | |
| 9db1d521 | 4400 | |
| 07893d4f UW |
4401 | (define_insn "*muldi3_sign" |
| 4402 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4403 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
| 4404 | (match_operand:DI 1 "register_operand" "0,0")))] | |
| 4405 | "TARGET_64BIT" | |
| 4406 | "@ | |
| d40c829f UW |
4407 | msgfr\t%0,%2 |
| 4408 | msgf\t%0,%2" | |
| d3632d41 | 4409 | [(set_attr "op_type" "RRE,RXY") |
| 07893d4f UW |
4410 | (set_attr "type" "imul")]) |
| 4411 | ||
| 4023fb28 | 4412 | (define_insn "muldi3" |
| 9db1d521 | 4413 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
| 96fd3851 | 4414 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
| 07893d4f | 4415 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
| 9db1d521 HP |
4416 | "TARGET_64BIT" |
| 4417 | "@ | |
| d40c829f UW |
4418 | msgr\t%0,%2 |
| 4419 | mghi\t%0,%h2 | |
| 4420 | msg\t%0,%2" | |
| d3632d41 | 4421 | [(set_attr "op_type" "RRE,RI,RXY") |
| f2d3c02a HP |
4422 | (set_attr "type" "imul")]) |
| 4423 | ||
| 9db1d521 HP |
4424 | ; |
| 4425 | ; mulsi3 instruction pattern(s). | |
| 4426 | ; | |
| 4427 | ||
| f1e77d83 UW |
4428 | (define_insn "*mulsi3_sign" |
| 4429 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4430 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
| 4431 | (match_operand:SI 1 "register_operand" "0")))] | |
| 4432 | "" | |
| 4433 | "mh\t%0,%2" | |
| 4434 | [(set_attr "op_type" "RX") | |
| 4435 | (set_attr "type" "imul")]) | |
| 4436 | ||
| 9db1d521 | 4437 | (define_insn "mulsi3" |
| d3632d41 UW |
4438 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
| 4439 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
| 4440 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
| 9db1d521 HP |
4441 | "" |
| 4442 | "@ | |
| d40c829f UW |
4443 | msr\t%0,%2 |
| 4444 | mhi\t%0,%h2 | |
| 4445 | ms\t%0,%2 | |
| 4446 | msy\t%0,%2" | |
| d3632d41 | 4447 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
| f2d3c02a | 4448 | (set_attr "type" "imul")]) |
| 9db1d521 | 4449 | |
| 4023fb28 UW |
4450 | ; |
| 4451 | ; mulsidi3 instruction pattern(s). | |
| 4452 | ; | |
| 4453 | ||
| f1e77d83 UW |
4454 | (define_insn "mulsidi3" |
| 4455 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4456 | (mult:DI (sign_extend:DI | |
| 4457 | (match_operand:SI 1 "register_operand" "%0,0")) | |
| 4458 | (sign_extend:DI | |
| 4459 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
| 4023fb28 | 4460 | "!TARGET_64BIT" |
| f1e77d83 UW |
4461 | "@ |
| 4462 | mr\t%0,%2 | |
| 4463 | m\t%0,%2" | |
| 4464 | [(set_attr "op_type" "RR,RX") | |
| 4465 | (set_attr "type" "imul")]) | |
| 4023fb28 | 4466 | |
| f1e77d83 UW |
4467 | ; |
| 4468 | ; umulsidi3 instruction pattern(s). | |
| 4469 | ; | |
| c7453384 | 4470 | |
| f1e77d83 UW |
4471 | (define_insn "umulsidi3" |
| 4472 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4473 | (mult:DI (zero_extend:DI | |
| 4474 | (match_operand:SI 1 "register_operand" "%0,0")) | |
| 4475 | (zero_extend:DI | |
| 4476 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
| 4477 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
| 4478 | "@ | |
| 4479 | mlr\t%0,%2 | |
| 4480 | ml\t%0,%2" | |
| 4481 | [(set_attr "op_type" "RRE,RXY") | |
| f2d3c02a | 4482 | (set_attr "type" "imul")]) |
| c7453384 | 4483 | |
| 9db1d521 HP |
4484 | ; |
| 4485 | ; muldf3 instruction pattern(s). | |
| 4486 | ; | |
| 4487 | ||
| 4488 | (define_expand "muldf3" | |
| 553e5ce9 UW |
4489 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
| 4490 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
| 4491 | (match_operand:DF 2 "general_operand" "f,R")))] | |
| 9db1d521 HP |
4492 | "TARGET_HARD_FLOAT" |
| 4493 | "") | |
| 4494 | ||
| 4495 | (define_insn "*muldf3" | |
| 4496 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 96fd3851 | 4497 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
| 553e5ce9 | 4498 | (match_operand:DF 2 "general_operand" "f,R")))] |
| 9db1d521 HP |
4499 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 4500 | "@ | |
| d40c829f UW |
4501 | mdbr\t%0,%2 |
| 4502 | mdb\t%0,%2" | |
| ce50cae8 | 4503 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 4504 | (set_attr "type" "fmuld")]) |
| 9db1d521 HP |
4505 | |
| 4506 | (define_insn "*muldf3_ibm" | |
| 4507 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 96fd3851 | 4508 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
| 553e5ce9 | 4509 | (match_operand:DF 2 "general_operand" "f,R")))] |
| 9db1d521 HP |
4510 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 4511 | "@ | |
| d40c829f UW |
4512 | mdr\t%0,%2 |
| 4513 | md\t%0,%2" | |
| 9db1d521 | 4514 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 4515 | (set_attr "type" "fmuld")]) |
| 9db1d521 | 4516 | |
| a1b892b5 AK |
4517 | (define_insn "*fmadddf" |
| 4518 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 4519 | (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") | |
| 4520 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
| 4521 | (match_operand:DF 3 "register_operand" "0,0")))] | |
| f2d226e1 | 4522 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
| a1b892b5 AK |
4523 | "@ |
| 4524 | madbr\t%0,%1,%2 | |
| 4525 | madb\t%0,%1,%2" | |
| 4526 | [(set_attr "op_type" "RRE,RXE") | |
| 4527 | (set_attr "type" "fmuld")]) | |
| 4528 | ||
| 4529 | (define_insn "*fmsubdf" | |
| 4530 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 4531 | (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") | |
| 4532 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
| 4533 | (match_operand:DF 3 "register_operand" "0,0")))] | |
| f2d226e1 | 4534 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
| a1b892b5 AK |
4535 | "@ |
| 4536 | msdbr\t%0,%1,%2 | |
| 4537 | msdb\t%0,%1,%2" | |
| 4538 | [(set_attr "op_type" "RRE,RXE") | |
| 4539 | (set_attr "type" "fmuld")]) | |
| 4540 | ||
| 9db1d521 HP |
4541 | ; |
| 4542 | ; mulsf3 instruction pattern(s). | |
| 4543 | ; | |
| 4544 | ||
| 4545 | (define_expand "mulsf3" | |
| 553e5ce9 UW |
4546 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
| 4547 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
| 4548 | (match_operand:SF 2 "general_operand" "f,R")))] | |
| 9db1d521 HP |
4549 | "TARGET_HARD_FLOAT" |
| 4550 | "") | |
| 4551 | ||
| 4552 | (define_insn "*mulsf3" | |
| 4553 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 96fd3851 | 4554 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
| 553e5ce9 | 4555 | (match_operand:SF 2 "general_operand" "f,R")))] |
| 9db1d521 HP |
4556 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 4557 | "@ | |
| d40c829f UW |
4558 | meebr\t%0,%2 |
| 4559 | meeb\t%0,%2" | |
| ce50cae8 | 4560 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 4561 | (set_attr "type" "fmuls")]) |
| 9db1d521 HP |
4562 | |
| 4563 | (define_insn "*mulsf3_ibm" | |
| 4564 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 96fd3851 | 4565 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
| 553e5ce9 | 4566 | (match_operand:SF 2 "general_operand" "f,R")))] |
| 9db1d521 HP |
4567 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 4568 | "@ | |
| d40c829f UW |
4569 | mer\t%0,%2 |
| 4570 | me\t%0,%2" | |
| 9db1d521 | 4571 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 4572 | (set_attr "type" "fmuls")]) |
| 9db1d521 | 4573 | |
| a1b892b5 AK |
4574 | (define_insn "*fmaddsf" |
| 4575 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 4576 | (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") | |
| 4577 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
| 4578 | (match_operand:SF 3 "register_operand" "0,0")))] | |
| f2d226e1 | 4579 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
| a1b892b5 AK |
4580 | "@ |
| 4581 | maebr\t%0,%1,%2 | |
| 4582 | maeb\t%0,%1,%2" | |
| 4583 | [(set_attr "op_type" "RRE,RXE") | |
| 4584 | (set_attr "type" "fmuls")]) | |
| 4585 | ||
| 4586 | (define_insn "*fmsubsf" | |
| 4587 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 4588 | (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") | |
| 4589 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
| 4590 | (match_operand:SF 3 "register_operand" "0,0")))] | |
| f2d226e1 | 4591 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
| a1b892b5 AK |
4592 | "@ |
| 4593 | msebr\t%0,%1,%2 | |
| 4594 | mseb\t%0,%1,%2" | |
| 4595 | [(set_attr "op_type" "RRE,RXE") | |
| 4596 | (set_attr "type" "fmuls")]) | |
| 9db1d521 HP |
4597 | |
| 4598 | ;; | |
| 4599 | ;;- Divide and modulo instructions. | |
| 4600 | ;; | |
| 4601 | ||
| 4602 | ; | |
| 4023fb28 | 4603 | ; divmoddi4 instruction pattern(s). |
| 9db1d521 HP |
4604 | ; |
| 4605 | ||
| 4023fb28 UW |
4606 | (define_expand "divmoddi4" |
| 4607 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
| f1e77d83 | 4608 | (div:DI (match_operand:DI 1 "register_operand" "") |
| 4023fb28 UW |
4609 | (match_operand:DI 2 "general_operand" ""))) |
| 4610 | (set (match_operand:DI 3 "general_operand" "") | |
| 4611 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
| 4612 | (clobber (match_dup 4))] | |
| 9db1d521 | 4613 | "TARGET_64BIT" |
| 9db1d521 | 4614 | { |
| f1e77d83 | 4615 | rtx insn, div_equal, mod_equal; |
| 4023fb28 UW |
4616 | |
| 4617 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
| 4618 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
| 4023fb28 UW |
4619 | |
| 4620 | operands[4] = gen_reg_rtx(TImode); | |
| f1e77d83 | 4621 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
| 4023fb28 UW |
4622 | |
| 4623 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
| 4624 | REG_NOTES (insn) = | |
| 4625 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
| 4626 | ||
| 4627 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
| 4628 | REG_NOTES (insn) = | |
| 4629 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
| 9db1d521 | 4630 | |
| 9db1d521 | 4631 | DONE; |
| 10bbf137 | 4632 | }) |
| 9db1d521 HP |
4633 | |
| 4634 | (define_insn "divmodtidi3" | |
| 4023fb28 UW |
4635 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
| 4636 | (ior:TI | |
| 4023fb28 UW |
4637 | (ashift:TI |
| 4638 | (zero_extend:TI | |
| 5665e398 UW |
4639 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
| 4640 | (match_operand:DI 2 "general_operand" "d,m"))) | |
| 4641 | (const_int 64)) | |
| 4642 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
| 9db1d521 HP |
4643 | "TARGET_64BIT" |
| 4644 | "@ | |
| d40c829f UW |
4645 | dsgr\t%0,%2 |
| 4646 | dsg\t%0,%2" | |
| d3632d41 | 4647 | [(set_attr "op_type" "RRE,RXY") |
| 077dab3b | 4648 | (set_attr "type" "idiv")]) |
| 9db1d521 | 4649 | |
| 4023fb28 UW |
4650 | (define_insn "divmodtisi3" |
| 4651 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
| 4652 | (ior:TI | |
| 4023fb28 UW |
4653 | (ashift:TI |
| 4654 | (zero_extend:TI | |
| 5665e398 | 4655 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
| 2f7e5a0d | 4656 | (sign_extend:DI |
| 5665e398 UW |
4657 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
| 4658 | (const_int 64)) | |
| 4659 | (zero_extend:TI | |
| 4660 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
| 9db1d521 | 4661 | "TARGET_64BIT" |
| 4023fb28 | 4662 | "@ |
| d40c829f UW |
4663 | dsgfr\t%0,%2 |
| 4664 | dsgf\t%0,%2" | |
| d3632d41 | 4665 | [(set_attr "op_type" "RRE,RXY") |
| 077dab3b | 4666 | (set_attr "type" "idiv")]) |
| 9db1d521 | 4667 | |
| 4023fb28 UW |
4668 | ; |
| 4669 | ; udivmoddi4 instruction pattern(s). | |
| 4670 | ; | |
| 9db1d521 | 4671 | |
| 4023fb28 UW |
4672 | (define_expand "udivmoddi4" |
| 4673 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
| 4674 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
| 4675 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
| 4676 | (set (match_operand:DI 3 "general_operand" "") | |
| 4677 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
| 4678 | (clobber (match_dup 4))] | |
| 9db1d521 | 4679 | "TARGET_64BIT" |
| 9db1d521 | 4680 | { |
| 4023fb28 UW |
4681 | rtx insn, div_equal, mod_equal, equal; |
| 4682 | ||
| 4683 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
| 4684 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
| 4685 | equal = gen_rtx_IOR (TImode, | |
| 4023fb28 UW |
4686 | gen_rtx_ASHIFT (TImode, |
| 4687 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
| 5665e398 UW |
4688 | GEN_INT (64)), |
| 4689 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
| 4023fb28 UW |
4690 | |
| 4691 | operands[4] = gen_reg_rtx(TImode); | |
| 4692 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
| 4693 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
| 4694 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
| 4695 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
| 4696 | REG_NOTES (insn) = | |
| 4697 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 4698 | ||
| 4699 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
| 4700 | REG_NOTES (insn) = | |
| 4701 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
| 4702 | ||
| 4703 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
| 4704 | REG_NOTES (insn) = | |
| 4705 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
| 9db1d521 | 4706 | |
| 9db1d521 | 4707 | DONE; |
| 10bbf137 | 4708 | }) |
| 9db1d521 HP |
4709 | |
| 4710 | (define_insn "udivmodtidi3" | |
| 4023fb28 | 4711 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
| 2f7e5a0d | 4712 | (ior:TI |
| 5665e398 UW |
4713 | (ashift:TI |
| 4714 | (zero_extend:TI | |
| 4715 | (truncate:DI | |
| 2f7e5a0d EC |
4716 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
| 4717 | (zero_extend:TI | |
| 5665e398 UW |
4718 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
| 4719 | (const_int 64)) | |
| 4720 | (zero_extend:TI | |
| 4721 | (truncate:DI | |
| 4722 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
| 9db1d521 HP |
4723 | "TARGET_64BIT" |
| 4724 | "@ | |
| d40c829f UW |
4725 | dlgr\t%0,%2 |
| 4726 | dlg\t%0,%2" | |
| d3632d41 | 4727 | [(set_attr "op_type" "RRE,RXY") |
| 077dab3b | 4728 | (set_attr "type" "idiv")]) |
| 9db1d521 HP |
4729 | |
| 4730 | ; | |
| 4023fb28 | 4731 | ; divmodsi4 instruction pattern(s). |
| 9db1d521 HP |
4732 | ; |
| 4733 | ||
| 4023fb28 UW |
4734 | (define_expand "divmodsi4" |
| 4735 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
| 4736 | (div:SI (match_operand:SI 1 "general_operand" "") | |
| 4737 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
| 4738 | (set (match_operand:SI 3 "general_operand" "") | |
| 4739 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
| 4740 | (clobber (match_dup 4))] | |
| 9db1d521 | 4741 | "!TARGET_64BIT" |
| 9db1d521 | 4742 | { |
| 4023fb28 UW |
4743 | rtx insn, div_equal, mod_equal, equal; |
| 4744 | ||
| 4745 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
| 4746 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
| 4747 | equal = gen_rtx_IOR (DImode, | |
| 4023fb28 UW |
4748 | gen_rtx_ASHIFT (DImode, |
| 4749 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
| 5665e398 UW |
4750 | GEN_INT (32)), |
| 4751 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
| 4023fb28 UW |
4752 | |
| 4753 | operands[4] = gen_reg_rtx(DImode); | |
| 4754 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
| 4755 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
| 4756 | REG_NOTES (insn) = | |
| 4757 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 4758 | ||
| 4759 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
| 4760 | REG_NOTES (insn) = | |
| 4761 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
| 4762 | ||
| 4763 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
| 4764 | REG_NOTES (insn) = | |
| 4765 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
| 9db1d521 | 4766 | |
| 9db1d521 | 4767 | DONE; |
| 10bbf137 | 4768 | }) |
| 9db1d521 HP |
4769 | |
| 4770 | (define_insn "divmoddisi3" | |
| 4023fb28 | 4771 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 2f7e5a0d | 4772 | (ior:DI |
| 5665e398 UW |
4773 | (ashift:DI |
| 4774 | (zero_extend:DI | |
| 4775 | (truncate:SI | |
| 2f7e5a0d EC |
4776 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
| 4777 | (sign_extend:DI | |
| 5665e398 UW |
4778 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
| 4779 | (const_int 32)) | |
| 4780 | (zero_extend:DI | |
| 4781 | (truncate:SI | |
| 4782 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
| 9db1d521 HP |
4783 | "!TARGET_64BIT" |
| 4784 | "@ | |
| d40c829f UW |
4785 | dr\t%0,%2 |
| 4786 | d\t%0,%2" | |
| 9db1d521 | 4787 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 4788 | (set_attr "type" "idiv")]) |
| 9db1d521 HP |
4789 | |
| 4790 | ; | |
| 4791 | ; udivsi3 and umodsi3 instruction pattern(s). | |
| 4792 | ; | |
| 4793 | ||
| f1e77d83 UW |
4794 | (define_expand "udivmodsi4" |
| 4795 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
| 4796 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
| 4797 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
| 4798 | (set (match_operand:SI 3 "general_operand" "") | |
| 4799 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
| 4800 | (clobber (match_dup 4))] | |
| 4801 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
| 4802 | { | |
| 4803 | rtx insn, div_equal, mod_equal, equal; | |
| 4804 | ||
| 4805 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
| 4806 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
| 4807 | equal = gen_rtx_IOR (DImode, | |
| f1e77d83 UW |
4808 | gen_rtx_ASHIFT (DImode, |
| 4809 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
| 5665e398 UW |
4810 | GEN_INT (32)), |
| 4811 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
| f1e77d83 UW |
4812 | |
| 4813 | operands[4] = gen_reg_rtx(DImode); | |
| 4814 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
| 4815 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
| 4816 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
| 4817 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
| 4818 | REG_NOTES (insn) = | |
| 4819 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 4820 | ||
| 4821 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
| 4822 | REG_NOTES (insn) = | |
| 4823 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
| 4824 | ||
| 4825 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
| 4826 | REG_NOTES (insn) = | |
| 4827 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
| 4828 | ||
| 4829 | DONE; | |
| 4830 | }) | |
| 4831 | ||
| 4832 | (define_insn "udivmoddisi3" | |
| 4833 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 2f7e5a0d | 4834 | (ior:DI |
| 5665e398 UW |
4835 | (ashift:DI |
| 4836 | (zero_extend:DI | |
| 4837 | (truncate:SI | |
| 2f7e5a0d EC |
4838 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
| 4839 | (zero_extend:DI | |
| 5665e398 UW |
4840 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
| 4841 | (const_int 32)) | |
| 4842 | (zero_extend:DI | |
| 4843 | (truncate:SI | |
| 4844 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
| f1e77d83 UW |
4845 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
| 4846 | "@ | |
| 4847 | dlr\t%0,%2 | |
| 4848 | dl\t%0,%2" | |
| 4849 | [(set_attr "op_type" "RRE,RXY") | |
| 4850 | (set_attr "type" "idiv")]) | |
| 4023fb28 | 4851 | |
| 9db1d521 HP |
4852 | (define_expand "udivsi3" |
| 4853 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4854 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
| 4023fb28 UW |
4855 | (match_operand:SI 2 "general_operand" ""))) |
| 4856 | (clobber (match_dup 3))] | |
| f1e77d83 | 4857 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
| 9db1d521 | 4858 | { |
| 4023fb28 UW |
4859 | rtx insn, udiv_equal, umod_equal, equal; |
| 4860 | ||
| 4861 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
| 4862 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
| 4863 | equal = gen_rtx_IOR (DImode, | |
| 4023fb28 UW |
4864 | gen_rtx_ASHIFT (DImode, |
| 4865 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
| 5665e398 UW |
4866 | GEN_INT (32)), |
| 4867 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
| 9db1d521 | 4868 | |
| 4023fb28 | 4869 | operands[3] = gen_reg_rtx (DImode); |
| 9db1d521 HP |
4870 | |
| 4871 | if (CONSTANT_P (operands[2])) | |
| 4872 | { | |
| 4873 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
| 4874 | { | |
| 4875 | rtx label1 = gen_label_rtx (); | |
| 4876 | ||
| 4023fb28 UW |
4877 | operands[1] = make_safe_from (operands[1], operands[0]); |
| 4878 | emit_move_insn (operands[0], const0_rtx); | |
| 4879 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
| 9db1d521 | 4880 | emit_jump_insn (gen_bltu (label1)); |
| 4023fb28 | 4881 | emit_move_insn (operands[0], const1_rtx); |
| 9db1d521 HP |
4882 | emit_label (label1); |
| 4883 | } | |
| 4884 | else | |
| 4885 | { | |
| c7453384 EC |
4886 | operands[2] = force_reg (SImode, operands[2]); |
| 4887 | operands[2] = make_safe_from (operands[2], operands[0]); | |
| 4023fb28 UW |
4888 | |
| 4889 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
| 4890 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
| 4891 | operands[2])); | |
| 4892 | REG_NOTES (insn) = | |
| 4893 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| c7453384 EC |
4894 | |
| 4895 | insn = emit_move_insn (operands[0], | |
| 4023fb28 UW |
4896 | gen_lowpart (SImode, operands[3])); |
| 4897 | REG_NOTES (insn) = | |
| c7453384 | 4898 | gen_rtx_EXPR_LIST (REG_EQUAL, |
| 4023fb28 | 4899 | udiv_equal, REG_NOTES (insn)); |
| 9db1d521 HP |
4900 | } |
| 4901 | } | |
| 4902 | else | |
| c7453384 | 4903 | { |
| 9db1d521 HP |
4904 | rtx label1 = gen_label_rtx (); |
| 4905 | rtx label2 = gen_label_rtx (); | |
| 4906 | rtx label3 = gen_label_rtx (); | |
| 4907 | ||
| c7453384 EC |
4908 | operands[1] = force_reg (SImode, operands[1]); |
| 4909 | operands[1] = make_safe_from (operands[1], operands[0]); | |
| 4910 | operands[2] = force_reg (SImode, operands[2]); | |
| 4911 | operands[2] = make_safe_from (operands[2], operands[0]); | |
| 4023fb28 UW |
4912 | |
| 4913 | emit_move_insn (operands[0], const0_rtx); | |
| 9db1d521 HP |
4914 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
| 4915 | emit_jump_insn (gen_bgtu (label3)); | |
| 220a826e | 4916 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
| 9db1d521 HP |
4917 | emit_jump_insn (gen_blt (label2)); |
| 4918 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
| 4919 | emit_jump_insn (gen_beq (label1)); | |
| 4023fb28 UW |
4920 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
| 4921 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
| 4922 | operands[2])); | |
| 4923 | REG_NOTES (insn) = | |
| 4924 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| c7453384 EC |
4925 | |
| 4926 | insn = emit_move_insn (operands[0], | |
| 4023fb28 UW |
4927 | gen_lowpart (SImode, operands[3])); |
| 4928 | REG_NOTES (insn) = | |
| c7453384 | 4929 | gen_rtx_EXPR_LIST (REG_EQUAL, |
| 4023fb28 | 4930 | udiv_equal, REG_NOTES (insn)); |
| f314b9b1 | 4931 | emit_jump (label3); |
| 9db1d521 | 4932 | emit_label (label1); |
| 4023fb28 | 4933 | emit_move_insn (operands[0], operands[1]); |
| f314b9b1 | 4934 | emit_jump (label3); |
| 9db1d521 | 4935 | emit_label (label2); |
| 4023fb28 | 4936 | emit_move_insn (operands[0], const1_rtx); |
| 9db1d521 HP |
4937 | emit_label (label3); |
| 4938 | } | |
| c7453384 | 4939 | emit_move_insn (operands[0], operands[0]); |
| 9db1d521 | 4940 | DONE; |
| 10bbf137 | 4941 | }) |
| 9db1d521 HP |
4942 | |
| 4943 | (define_expand "umodsi3" | |
| 4944 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4945 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
| 4023fb28 UW |
4946 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
| 4947 | (clobber (match_dup 3))] | |
| f1e77d83 | 4948 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
| 9db1d521 | 4949 | { |
| 4023fb28 UW |
4950 | rtx insn, udiv_equal, umod_equal, equal; |
| 4951 | ||
| 4952 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
| 4953 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
| 4954 | equal = gen_rtx_IOR (DImode, | |
| 4023fb28 UW |
4955 | gen_rtx_ASHIFT (DImode, |
| 4956 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
| 5665e398 UW |
4957 | GEN_INT (32)), |
| 4958 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
| 9db1d521 | 4959 | |
| 4023fb28 | 4960 | operands[3] = gen_reg_rtx (DImode); |
| 9db1d521 HP |
4961 | |
| 4962 | if (CONSTANT_P (operands[2])) | |
| 4963 | { | |
| 4964 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
| 4965 | { | |
| 4966 | rtx label1 = gen_label_rtx (); | |
| 4967 | ||
| 4023fb28 UW |
4968 | operands[1] = make_safe_from (operands[1], operands[0]); |
| 4969 | emit_move_insn (operands[0], operands[1]); | |
| 4970 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
| 9db1d521 | 4971 | emit_jump_insn (gen_bltu (label1)); |
| 4023fb28 UW |
4972 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
| 4973 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
| 9db1d521 HP |
4974 | emit_label (label1); |
| 4975 | } | |
| 4976 | else | |
| 4977 | { | |
| c7453384 EC |
4978 | operands[2] = force_reg (SImode, operands[2]); |
| 4979 | operands[2] = make_safe_from (operands[2], operands[0]); | |
| 4023fb28 UW |
4980 | |
| 4981 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
| 4982 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
| 4983 | operands[2])); | |
| 4984 | REG_NOTES (insn) = | |
| 4985 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| c7453384 EC |
4986 | |
| 4987 | insn = emit_move_insn (operands[0], | |
| 4023fb28 UW |
4988 | gen_highpart (SImode, operands[3])); |
| 4989 | REG_NOTES (insn) = | |
| c7453384 | 4990 | gen_rtx_EXPR_LIST (REG_EQUAL, |
| 4023fb28 | 4991 | umod_equal, REG_NOTES (insn)); |
| 9db1d521 HP |
4992 | } |
| 4993 | } | |
| 4994 | else | |
| 4995 | { | |
| 4996 | rtx label1 = gen_label_rtx (); | |
| 4997 | rtx label2 = gen_label_rtx (); | |
| 4998 | rtx label3 = gen_label_rtx (); | |
| 4999 | ||
| c7453384 EC |
5000 | operands[1] = force_reg (SImode, operands[1]); |
| 5001 | operands[1] = make_safe_from (operands[1], operands[0]); | |
| 5002 | operands[2] = force_reg (SImode, operands[2]); | |
| 5003 | operands[2] = make_safe_from (operands[2], operands[0]); | |
| 9db1d521 | 5004 | |
| c7453384 | 5005 | emit_move_insn(operands[0], operands[1]); |
| 4023fb28 | 5006 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
| 9db1d521 | 5007 | emit_jump_insn (gen_bgtu (label3)); |
| 220a826e | 5008 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
| 9db1d521 HP |
5009 | emit_jump_insn (gen_blt (label2)); |
| 5010 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
| 5011 | emit_jump_insn (gen_beq (label1)); | |
| 4023fb28 UW |
5012 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
| 5013 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
| 5014 | operands[2])); | |
| 5015 | REG_NOTES (insn) = | |
| 5016 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| c7453384 EC |
5017 | |
| 5018 | insn = emit_move_insn (operands[0], | |
| 4023fb28 UW |
5019 | gen_highpart (SImode, operands[3])); |
| 5020 | REG_NOTES (insn) = | |
| c7453384 | 5021 | gen_rtx_EXPR_LIST (REG_EQUAL, |
| 4023fb28 | 5022 | umod_equal, REG_NOTES (insn)); |
| f314b9b1 | 5023 | emit_jump (label3); |
| 9db1d521 | 5024 | emit_label (label1); |
| 4023fb28 | 5025 | emit_move_insn (operands[0], const0_rtx); |
| f314b9b1 | 5026 | emit_jump (label3); |
| 9db1d521 | 5027 | emit_label (label2); |
| 4023fb28 | 5028 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
| 9db1d521 HP |
5029 | emit_label (label3); |
| 5030 | } | |
| 9db1d521 | 5031 | DONE; |
| 10bbf137 | 5032 | }) |
| 9db1d521 HP |
5033 | |
| 5034 | ; | |
| 5035 | ; divdf3 instruction pattern(s). | |
| 5036 | ; | |
| 5037 | ||
| 5038 | (define_expand "divdf3" | |
| 553e5ce9 UW |
5039 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
| 5040 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 5041 | (match_operand:DF 2 "general_operand" "f,R")))] | |
| 9db1d521 HP |
5042 | "TARGET_HARD_FLOAT" |
| 5043 | "") | |
| 5044 | ||
| 5045 | (define_insn "*divdf3" | |
| 4023fb28 UW |
5046 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
| 5047 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 553e5ce9 | 5048 | (match_operand:DF 2 "general_operand" "f,R")))] |
| 9db1d521 HP |
5049 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 5050 | "@ | |
| d40c829f UW |
5051 | ddbr\t%0,%2 |
| 5052 | ddb\t%0,%2" | |
| ce50cae8 | 5053 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 5054 | (set_attr "type" "fdivd")]) |
| 9db1d521 HP |
5055 | |
| 5056 | (define_insn "*divdf3_ibm" | |
| 4023fb28 UW |
5057 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
| 5058 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 553e5ce9 | 5059 | (match_operand:DF 2 "general_operand" "f,R")))] |
| 9db1d521 HP |
5060 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 5061 | "@ | |
| d40c829f UW |
5062 | ddr\t%0,%2 |
| 5063 | dd\t%0,%2" | |
| 9db1d521 | 5064 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 5065 | (set_attr "type" "fdivd")]) |
| 9db1d521 HP |
5066 | |
| 5067 | ; | |
| 5068 | ; divsf3 instruction pattern(s). | |
| 5069 | ; | |
| 5070 | ||
| 5071 | (define_expand "divsf3" | |
| 553e5ce9 UW |
5072 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
| 5073 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 5074 | (match_operand:SF 2 "general_operand" "f,R")))] | |
| 9db1d521 HP |
5075 | "TARGET_HARD_FLOAT" |
| 5076 | "") | |
| 5077 | ||
| 5078 | (define_insn "*divsf3" | |
| 4023fb28 UW |
5079 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
| 5080 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 553e5ce9 | 5081 | (match_operand:SF 2 "general_operand" "f,R")))] |
| 9db1d521 HP |
5082 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 5083 | "@ | |
| d40c829f UW |
5084 | debr\t%0,%2 |
| 5085 | deb\t%0,%2" | |
| ce50cae8 | 5086 | [(set_attr "op_type" "RRE,RXE") |
| 077dab3b | 5087 | (set_attr "type" "fdivs")]) |
| 9db1d521 HP |
5088 | |
| 5089 | (define_insn "*divsf3" | |
| 4023fb28 UW |
5090 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
| 5091 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 553e5ce9 | 5092 | (match_operand:SF 2 "general_operand" "f,R")))] |
| 9db1d521 HP |
5093 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 5094 | "@ | |
| d40c829f UW |
5095 | der\t%0,%2 |
| 5096 | de\t%0,%2" | |
| 9db1d521 | 5097 | [(set_attr "op_type" "RR,RX") |
| 077dab3b | 5098 | (set_attr "type" "fdivs")]) |
| 9db1d521 HP |
5099 | |
| 5100 | ||
| 5101 | ;; | |
| 5102 | ;;- And instructions. | |
| 5103 | ;; | |
| 5104 | ||
| 5105 | ; | |
| 5106 | ; anddi3 instruction pattern(s). | |
| 5107 | ; | |
| 5108 | ||
| 5109 | (define_insn "*anddi3_cc" | |
| 5110 | [(set (reg 33) | |
| 96fd3851 | 5111 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 4023fb28 | 5112 | (match_operand:DI 2 "general_operand" "d,m")) |
| 9db1d521 | 5113 | (const_int 0))) |
| 4023fb28 | 5114 | (set (match_operand:DI 0 "register_operand" "=d,d") |
| 9db1d521 HP |
5115 | (and:DI (match_dup 1) (match_dup 2)))] |
| 5116 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 5117 | "@ | |
| d40c829f UW |
5118 | ngr\t%0,%2 |
| 5119 | ng\t%0,%2" | |
| d3632d41 | 5120 | [(set_attr "op_type" "RRE,RXY")]) |
| 9db1d521 HP |
5121 | |
| 5122 | (define_insn "*anddi3_cconly" | |
| 5123 | [(set (reg 33) | |
| 96fd3851 | 5124 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 4023fb28 | 5125 | (match_operand:DI 2 "general_operand" "d,m")) |
| 9db1d521 HP |
5126 | (const_int 0))) |
| 5127 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 68f9c5e2 UW |
5128 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
| 5129 | /* Do not steal TM patterns. */ | |
| 5130 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
| 9db1d521 | 5131 | "@ |
| d40c829f UW |
5132 | ngr\t%0,%2 |
| 5133 | ng\t%0,%2" | |
| d3632d41 | 5134 | [(set_attr "op_type" "RRE,RXY")]) |
| 9db1d521 | 5135 | |
| 8cb66696 UW |
5136 | (define_insn "*anddi3" |
| 5137 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,Q") | |
| 5138 | (and:DI (match_operand:DI 1 "nonimmediate_operand" | |
| 5139 | "%d,o,0,0,0,0,0,0,0") | |
| 5140 | (match_operand:DI 2 "general_operand" | |
| 5141 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,Q"))) | |
| 4023fb28 | 5142 | (clobber (reg:CC 33))] |
| 8cb66696 UW |
5143 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
| 5144 | "@ | |
| 5145 | # | |
| 5146 | # | |
| 5147 | nihh\t%0,%j2 | |
| 5148 | nihl\t%0,%j2 | |
| 5149 | nilh\t%0,%j2 | |
| 5150 | nill\t%0,%j2 | |
| 5151 | ngr\t%0,%2 | |
| 5152 | ng\t%0,%2 | |
| 5153 | nc\t%O0(8,%R0),%2" | |
| 5154 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SS")]) | |
| 4023fb28 | 5155 | |
| 8cb66696 UW |
5156 | (define_expand "anddi3" |
| 5157 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
| 5158 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
| 5159 | (match_operand:DI 2 "general_operand" ""))) | |
| 4023fb28 | 5160 | (clobber (reg:CC 33))] |
| 8cb66696 UW |
5161 | "TARGET_64BIT" |
| 5162 | "s390_expand_logical_operator (AND, DImode, operands); DONE;") | |
| 9db1d521 HP |
5163 | |
| 5164 | ; | |
| 5165 | ; andsi3 instruction pattern(s). | |
| 5166 | ; | |
| 5167 | ||
| 5168 | (define_insn "*andsi3_cc" | |
| 5169 | [(set (reg 33) | |
| d3632d41 UW |
5170 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 5171 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 9db1d521 | 5172 | (const_int 0))) |
| d3632d41 | 5173 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 9db1d521 HP |
5174 | (and:SI (match_dup 1) (match_dup 2)))] |
| 5175 | "s390_match_ccmode(insn, CCTmode)" | |
| 5176 | "@ | |
| d40c829f UW |
5177 | nr\t%0,%2 |
| 5178 | n\t%0,%2 | |
| 5179 | ny\t%0,%2" | |
| d3632d41 | 5180 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 HP |
5181 | |
| 5182 | (define_insn "*andsi3_cconly" | |
| 5183 | [(set (reg 33) | |
| d3632d41 UW |
5184 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 5185 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 9db1d521 | 5186 | (const_int 0))) |
| d3632d41 | 5187 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
| 68f9c5e2 UW |
5188 | "s390_match_ccmode(insn, CCTmode) |
| 5189 | /* Do not steal TM patterns. */ | |
| 5190 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
| 9db1d521 | 5191 | "@ |
| d40c829f UW |
5192 | nr\t%0,%2 |
| 5193 | n\t%0,%2 | |
| 5194 | ny\t%0,%2" | |
| d3632d41 | 5195 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 | 5196 | |
| f19a9af7 | 5197 | (define_insn "*andsi3_zarch" |
| 8cb66696 UW |
5198 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,Q") |
| 5199 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%d,o,0,0,0,0,0,0") | |
| 5200 | (match_operand:SI 2 "general_operand" "M,M,N0HSF,N1HSF,d,R,T,Q"))) | |
| 9db1d521 | 5201 | (clobber (reg:CC 33))] |
| 8cb66696 | 5202 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 9db1d521 | 5203 | "@ |
| f19a9af7 AK |
5204 | # |
| 5205 | # | |
| 5206 | nilh\t%0,%j2 | |
| 2f7e5a0d | 5207 | nill\t%0,%j2 |
| d40c829f UW |
5208 | nr\t%0,%2 |
| 5209 | n\t%0,%2 | |
| 8cb66696 UW |
5210 | ny\t%0,%2 |
| 5211 | nc\t%O0(4,%R0),%2" | |
| 5212 | [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SS")]) | |
| f19a9af7 AK |
5213 | |
| 5214 | (define_insn "*andsi3_esa" | |
| 8cb66696 UW |
5215 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,Q") |
| 5216 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
| 5217 | (match_operand:SI 2 "general_operand" "d,R,Q"))) | |
| f19a9af7 | 5218 | (clobber (reg:CC 33))] |
| 8cb66696 | 5219 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| f19a9af7 AK |
5220 | "@ |
| 5221 | nr\t%0,%2 | |
| 8cb66696 UW |
5222 | n\t%0,%2 |
| 5223 | nc\t%O0(4,%R0),%2" | |
| 5224 | [(set_attr "op_type" "RR,RX,SS")]) | |
| 4023fb28 | 5225 | |
| 8cb66696 UW |
5226 | (define_expand "andsi3" |
| 5227 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
| 5228 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
| 5229 | (match_operand:SI 2 "general_operand" ""))) | |
| 4023fb28 UW |
5230 | (clobber (reg:CC 33))] |
| 5231 | "" | |
| 8cb66696 | 5232 | "s390_expand_logical_operator (AND, SImode, operands); DONE;") |
| 9db1d521 HP |
5233 | |
| 5234 | ; | |
| 5235 | ; andhi3 instruction pattern(s). | |
| 5236 | ; | |
| 5237 | ||
| 8cb66696 UW |
5238 | (define_insn "*andhi3_zarch" |
| 5239 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,Q") | |
| 5240 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
| 5241 | (match_operand:HI 2 "general_operand" "d,n,Q"))) | |
| 4023fb28 | 5242 | (clobber (reg:CC 33))] |
| 8cb66696 | 5243 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 4023fb28 | 5244 | "@ |
| d40c829f | 5245 | nr\t%0,%2 |
| 8cb66696 UW |
5246 | nill\t%0,%x2 |
| 5247 | nc\t%O0(2,%R0),%2" | |
| 5248 | [(set_attr "op_type" "RR,RI,SS")]) | |
| 5249 | ||
| 5250 | (define_insn "*andhi3_esa" | |
| 5251 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,Q") | |
| 5252 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
| 5253 | (match_operand:HI 2 "general_operand" "d,Q"))) | |
| 4023fb28 | 5254 | (clobber (reg:CC 33))] |
| 8cb66696 UW |
5255 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 5256 | "@ | |
| 5257 | nr\t%0,%2 | |
| 5258 | nc\t%O0(2,%R0),%2" | |
| 5259 | [(set_attr "op_type" "RR,SS")]) | |
| 9db1d521 | 5260 | |
| 8cb66696 UW |
5261 | (define_expand "andhi3" |
| 5262 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 5263 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
| 5264 | (match_operand:HI 2 "general_operand" ""))) | |
| 9db1d521 HP |
5265 | (clobber (reg:CC 33))] |
| 5266 | "" | |
| 8cb66696 | 5267 | "s390_expand_logical_operator (AND, HImode, operands); DONE;") |
| 9db1d521 HP |
5268 | |
| 5269 | ; | |
| 5270 | ; andqi3 instruction pattern(s). | |
| 5271 | ; | |
| 5272 | ||
| 8cb66696 UW |
5273 | (define_insn "*andqi3_zarch" |
| 5274 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
| 5275 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
| 5276 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
| 4023fb28 | 5277 | (clobber (reg:CC 33))] |
| 8cb66696 | 5278 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 4023fb28 | 5279 | "@ |
| d40c829f | 5280 | nr\t%0,%2 |
| 8cb66696 UW |
5281 | nill\t%0,%b2 |
| 5282 | ni\t%0,%b2 | |
| 5283 | niy\t%0,%b2 | |
| 5284 | nc\t%O0(1,%R0),%2" | |
| 5285 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) | |
| 5286 | ||
| 5287 | (define_insn "*andqi3_esa" | |
| 5288 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
| 5289 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
| 5290 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
| 9db1d521 | 5291 | (clobber (reg:CC 33))] |
| 8cb66696 | 5292 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 9db1d521 | 5293 | "@ |
| 8cb66696 UW |
5294 | nr\t%0,%2 |
| 5295 | ni\t%0,%b2 | |
| 5296 | nc\t%O0(1,%R0),%2" | |
| 5297 | [(set_attr "op_type" "RR,SI,SS")]) | |
| 4023fb28 | 5298 | |
| 8cb66696 UW |
5299 | (define_expand "andqi3" |
| 5300 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 5301 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
| 5302 | (match_operand:QI 2 "general_operand" ""))) | |
| 4023fb28 UW |
5303 | (clobber (reg:CC 33))] |
| 5304 | "" | |
| 8cb66696 | 5305 | "s390_expand_logical_operator (AND, QImode, operands); DONE;") |
| 9db1d521 HP |
5306 | |
| 5307 | ||
| 5308 | ;; | |
| 5309 | ;;- Bit set (inclusive or) instructions. | |
| 5310 | ;; | |
| 5311 | ||
| 5312 | ; | |
| 5313 | ; iordi3 instruction pattern(s). | |
| 5314 | ; | |
| 5315 | ||
| 4023fb28 UW |
5316 | (define_insn "*iordi3_cc" |
| 5317 | [(set (reg 33) | |
| 96fd3851 | 5318 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 4023fb28 UW |
5319 | (match_operand:DI 2 "general_operand" "d,m")) |
| 5320 | (const_int 0))) | |
| 5321 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5322 | (ior:DI (match_dup 1) (match_dup 2)))] | |
| 5323 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 5324 | "@ | |
| d40c829f UW |
5325 | ogr\t%0,%2 |
| 5326 | og\t%0,%2" | |
| d3632d41 | 5327 | [(set_attr "op_type" "RRE,RXY")]) |
| 4023fb28 UW |
5328 | |
| 5329 | (define_insn "*iordi3_cconly" | |
| 5330 | [(set (reg 33) | |
| 96fd3851 | 5331 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 4023fb28 UW |
5332 | (match_operand:DI 2 "general_operand" "d,m")) |
| 5333 | (const_int 0))) | |
| 5334 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 5335 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 5336 | "@ | |
| d40c829f UW |
5337 | ogr\t%0,%2 |
| 5338 | og\t%0,%2" | |
| d3632d41 | 5339 | [(set_attr "op_type" "RRE,RXY")]) |
| 4023fb28 | 5340 | |
| 8cb66696 UW |
5341 | (define_insn "*iordi3" |
| 5342 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,Q") | |
| 5343 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0,0,0,0,0,0,0") | |
| 5344 | (match_operand:DI 2 "general_operand" | |
| 5345 | "N0HD0,N1HD0,N2HD0,N3HD0,d,m,Q"))) | |
| 9db1d521 | 5346 | (clobber (reg:CC 33))] |
| 8cb66696 | 5347 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
| 9db1d521 | 5348 | "@ |
| f19a9af7 AK |
5349 | oihh\t%0,%i2 |
| 5350 | oihl\t%0,%i2 | |
| 5351 | oilh\t%0,%i2 | |
| 5352 | oill\t%0,%i2 | |
| d40c829f | 5353 | ogr\t%0,%2 |
| 8cb66696 UW |
5354 | og\t%0,%2 |
| 5355 | oc\t%O0(8,%R0),%2" | |
| 5356 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SS")]) | |
| 4023fb28 | 5357 | |
| 8cb66696 UW |
5358 | (define_expand "iordi3" |
| 5359 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
| 5360 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
| 5361 | (match_operand:DI 2 "general_operand" ""))) | |
| 4023fb28 | 5362 | (clobber (reg:CC 33))] |
| 8cb66696 UW |
5363 | "TARGET_64BIT" |
| 5364 | "s390_expand_logical_operator (IOR, DImode, operands); DONE;") | |
| 9db1d521 HP |
5365 | |
| 5366 | ; | |
| 5367 | ; iorsi3 instruction pattern(s). | |
| 5368 | ; | |
| 5369 | ||
| 4023fb28 UW |
5370 | (define_insn "*iorsi3_cc" |
| 5371 | [(set (reg 33) | |
| d3632d41 UW |
5372 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 5373 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 4023fb28 | 5374 | (const_int 0))) |
| d3632d41 | 5375 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 4023fb28 UW |
5376 | (ior:SI (match_dup 1) (match_dup 2)))] |
| 5377 | "s390_match_ccmode(insn, CCTmode)" | |
| 5378 | "@ | |
| d40c829f UW |
5379 | or\t%0,%2 |
| 5380 | o\t%0,%2 | |
| 5381 | oy\t%0,%2" | |
| d3632d41 | 5382 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 4023fb28 UW |
5383 | |
| 5384 | (define_insn "*iorsi3_cconly" | |
| 5385 | [(set (reg 33) | |
| d3632d41 UW |
5386 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 5387 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 4023fb28 | 5388 | (const_int 0))) |
| d3632d41 | 5389 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
| 4023fb28 UW |
5390 | "s390_match_ccmode(insn, CCTmode)" |
| 5391 | "@ | |
| d40c829f UW |
5392 | or\t%0,%2 |
| 5393 | o\t%0,%2 | |
| 5394 | oy\t%0,%2" | |
| d3632d41 | 5395 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 4023fb28 | 5396 | |
| 8cb66696 UW |
5397 | (define_insn "*iorsi3_zarch" |
| 5398 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,Q") | |
| 5399 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0,0,0,0") | |
| 5400 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,Q"))) | |
| 4023fb28 | 5401 | (clobber (reg:CC 33))] |
| 8cb66696 | 5402 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 4023fb28 | 5403 | "@ |
| f19a9af7 AK |
5404 | oilh\t%0,%i2 |
| 5405 | oill\t%0,%i2 | |
| d40c829f UW |
5406 | or\t%0,%2 |
| 5407 | o\t%0,%2 | |
| 8cb66696 UW |
5408 | oy\t%0,%2 |
| 5409 | oc\t%O0(4,%R0),%2" | |
| 5410 | [(set_attr "op_type" "RI,RI,RR,RX,RXY,SS")]) | |
| 5411 | ||
| 5412 | (define_insn "*iorsi3_esa" | |
| 5413 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,Q") | |
| 5414 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0") | |
| 5415 | (match_operand:SI 2 "general_operand" "d,R,Q"))) | |
| f19a9af7 | 5416 | (clobber (reg:CC 33))] |
| 8cb66696 | 5417 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| f19a9af7 AK |
5418 | "@ |
| 5419 | or\t%0,%2 | |
| 8cb66696 UW |
5420 | o\t%0,%2 |
| 5421 | oc\t%O0(4,%R0),%2" | |
| 5422 | [(set_attr "op_type" "RR,RX,SS")]) | |
| 4023fb28 | 5423 | |
| 8cb66696 UW |
5424 | (define_expand "iorsi3" |
| 5425 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
| 5426 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
| 5427 | (match_operand:SI 2 "general_operand" ""))) | |
| 4023fb28 UW |
5428 | (clobber (reg:CC 33))] |
| 5429 | "" | |
| 8cb66696 | 5430 | "s390_expand_logical_operator (IOR, SImode, operands); DONE;") |
| 4023fb28 UW |
5431 | |
| 5432 | ; | |
| 5433 | ; iorhi3 instruction pattern(s). | |
| 5434 | ; | |
| 5435 | ||
| 8cb66696 UW |
5436 | (define_insn "*iorhi3_zarch" |
| 5437 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,Q") | |
| 5438 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
| 5439 | (match_operand:HI 2 "general_operand" "d,n,Q"))) | |
| 4023fb28 | 5440 | (clobber (reg:CC 33))] |
| 8cb66696 | 5441 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 4023fb28 | 5442 | "@ |
| d40c829f | 5443 | or\t%0,%2 |
| 8cb66696 UW |
5444 | oill\t%0,%x2 |
| 5445 | oc\t%O0(2,%R0),%2" | |
| 5446 | [(set_attr "op_type" "RR,RI,SS")]) | |
| 5447 | ||
| 5448 | (define_insn "*iorhi3_esa" | |
| 5449 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,Q") | |
| 5450 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
| 5451 | (match_operand:HI 2 "general_operand" "d,Q"))) | |
| 4023fb28 | 5452 | (clobber (reg:CC 33))] |
| 8cb66696 UW |
5453 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 5454 | "@ | |
| 5455 | or\t%0,%2 | |
| 5456 | oc\t%O0(2,%R0),%2" | |
| 5457 | [(set_attr "op_type" "RR,SS")]) | |
| 9db1d521 | 5458 | |
| 8cb66696 UW |
5459 | (define_expand "iorhi3" |
| 5460 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 5461 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
| 5462 | (match_operand:HI 2 "general_operand" ""))) | |
| 9db1d521 HP |
5463 | (clobber (reg:CC 33))] |
| 5464 | "" | |
| 8cb66696 | 5465 | "s390_expand_logical_operator (IOR, HImode, operands); DONE;") |
| 9db1d521 HP |
5466 | |
| 5467 | ; | |
| 4023fb28 | 5468 | ; iorqi3 instruction pattern(s). |
| 9db1d521 HP |
5469 | ; |
| 5470 | ||
| 8cb66696 UW |
5471 | (define_insn "*iorqi3_zarch" |
| 5472 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
| 5473 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
| 5474 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
| 4023fb28 | 5475 | (clobber (reg:CC 33))] |
| 8cb66696 | 5476 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 4023fb28 | 5477 | "@ |
| d40c829f | 5478 | or\t%0,%2 |
| 8cb66696 UW |
5479 | oill\t%0,%b2 |
| 5480 | oi\t%0,%b2 | |
| 5481 | oiy\t%0,%b2 | |
| 5482 | oc\t%O0(1,%R0),%2" | |
| 5483 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) | |
| 5484 | ||
| 5485 | (define_insn "*iorqi3_esa" | |
| 5486 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
| 5487 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
| 5488 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
| 4023fb28 | 5489 | (clobber (reg:CC 33))] |
| 8cb66696 | 5490 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
| 9db1d521 | 5491 | "@ |
| 8cb66696 UW |
5492 | or\t%0,%2 |
| 5493 | oi\t%0,%b2 | |
| 5494 | oc\t%O0(1,%R0),%2" | |
| 5495 | [(set_attr "op_type" "RR,SI,SS")]) | |
| 9db1d521 | 5496 | |
| 8cb66696 UW |
5497 | (define_expand "iorqi3" |
| 5498 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 5499 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
| 5500 | (match_operand:QI 2 "general_operand" ""))) | |
| 9db1d521 HP |
5501 | (clobber (reg:CC 33))] |
| 5502 | "" | |
| 8cb66696 | 5503 | "s390_expand_logical_operator (IOR, QImode, operands); DONE;") |
| 9db1d521 HP |
5504 | |
| 5505 | ||
| 5506 | ;; | |
| 5507 | ;;- Xor instructions. | |
| 5508 | ;; | |
| 5509 | ||
| 5510 | ; | |
| 5511 | ; xordi3 instruction pattern(s). | |
| 5512 | ; | |
| 5513 | ||
| 4023fb28 UW |
5514 | (define_insn "*xordi3_cc" |
| 5515 | [(set (reg 33) | |
| 96fd3851 | 5516 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 4023fb28 UW |
5517 | (match_operand:DI 2 "general_operand" "d,m")) |
| 5518 | (const_int 0))) | |
| 5519 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5520 | (xor:DI (match_dup 1) (match_dup 2)))] | |
| 5521 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 5522 | "@ | |
| d40c829f UW |
5523 | xgr\t%0,%2 |
| 5524 | xg\t%0,%2" | |
| d3632d41 | 5525 | [(set_attr "op_type" "RRE,RXY")]) |
| 4023fb28 UW |
5526 | |
| 5527 | (define_insn "*xordi3_cconly" | |
| 5528 | [(set (reg 33) | |
| 96fd3851 | 5529 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
| 4023fb28 UW |
5530 | (match_operand:DI 2 "general_operand" "d,m")) |
| 5531 | (const_int 0))) | |
| 5532 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 5533 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 5534 | "@ | |
| d40c829f UW |
5535 | xgr\t%0,%2 |
| 5536 | xr\t%0,%2" | |
| d3632d41 | 5537 | [(set_attr "op_type" "RRE,RXY")]) |
| 4023fb28 | 5538 | |
| 8cb66696 UW |
5539 | (define_insn "*xordi3" |
| 5540 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q") | |
| 5541 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") | |
| 5542 | (match_operand:DI 2 "general_operand" "d,m,Q"))) | |
| 9db1d521 | 5543 | (clobber (reg:CC 33))] |
| 8cb66696 | 5544 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
| 9db1d521 | 5545 | "@ |
| d40c829f | 5546 | xgr\t%0,%2 |
| 8cb66696 UW |
5547 | xg\t%0,%2 |
| 5548 | xc\t%O0(8,%R0),%2" | |
| 5549 | [(set_attr "op_type" "RRE,RXY,SS")]) | |
| 4023fb28 | 5550 | |
| 8cb66696 UW |
5551 | (define_expand "xordi3" |
| 5552 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
| 5553 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
| 5554 | (match_operand:DI 2 "general_operand" ""))) | |
| 4023fb28 | 5555 | (clobber (reg:CC 33))] |
| 8cb66696 UW |
5556 | "TARGET_64BIT" |
| 5557 | "s390_expand_logical_operator (XOR, DImode, operands); DONE;") | |
| 9db1d521 HP |
5558 | |
| 5559 | ; | |
| 5560 | ; xorsi3 instruction pattern(s). | |
| 5561 | ; | |
| 5562 | ||
| 4023fb28 UW |
5563 | (define_insn "*xorsi3_cc" |
| 5564 | [(set (reg 33) | |
| d3632d41 UW |
5565 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 5566 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 4023fb28 | 5567 | (const_int 0))) |
| d3632d41 | 5568 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
| 4023fb28 UW |
5569 | (xor:SI (match_dup 1) (match_dup 2)))] |
| 5570 | "s390_match_ccmode(insn, CCTmode)" | |
| 5571 | "@ | |
| d40c829f UW |
5572 | xr\t%0,%2 |
| 5573 | x\t%0,%2 | |
| 5574 | xy\t%0,%2" | |
| d3632d41 | 5575 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 4023fb28 UW |
5576 | |
| 5577 | (define_insn "*xorsi3_cconly" | |
| 5578 | [(set (reg 33) | |
| d3632d41 UW |
5579 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
| 5580 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
| 4023fb28 | 5581 | (const_int 0))) |
| d3632d41 | 5582 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
| 4023fb28 UW |
5583 | "s390_match_ccmode(insn, CCTmode)" |
| 5584 | "@ | |
| d40c829f UW |
5585 | xr\t%0,%2 |
| 5586 | x\t%0,%2 | |
| 5587 | xy\t%0,%2" | |
| d3632d41 | 5588 | [(set_attr "op_type" "RR,RX,RXY")]) |
| 9db1d521 | 5589 | |
| 8cb66696 UW |
5590 | (define_insn "*xorsi3" |
| 5591 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,Q") | |
| 5592 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
| 5593 | (match_operand:SI 2 "general_operand" "d,R,T,Q"))) | |
| 9db1d521 | 5594 | (clobber (reg:CC 33))] |
| 8cb66696 | 5595 | "s390_logical_operator_ok_p (operands)" |
| 9db1d521 | 5596 | "@ |
| d40c829f UW |
5597 | xr\t%0,%2 |
| 5598 | x\t%0,%2 | |
| 8cb66696 UW |
5599 | xy\t%0,%2 |
| 5600 | xc\t%O0(4,%R0),%2" | |
| 5601 | [(set_attr "op_type" "RR,RX,RXY,SS")]) | |
| 5602 | ||
| 5603 | (define_expand "xorsi3" | |
| 5604 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
| 5605 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
| 5606 | (match_operand:SI 2 "general_operand" ""))) | |
| 4023fb28 UW |
5607 | (clobber (reg:CC 33))] |
| 5608 | "" | |
| 8cb66696 | 5609 | "s390_expand_logical_operator (XOR, SImode, operands); DONE;") |
| 9db1d521 HP |
5610 | |
| 5611 | ; | |
| 5612 | ; xorhi3 instruction pattern(s). | |
| 5613 | ; | |
| 5614 | ||
| 8cb66696 UW |
5615 | (define_insn "*xorhi3" |
| 5616 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,Q") | |
| 5617 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0") | |
| 5618 | (match_operand:HI 2 "general_operand" "d,Q"))) | |
| 4023fb28 | 5619 | (clobber (reg:CC 33))] |
| 8cb66696 UW |
5620 | "s390_logical_operator_ok_p (operands)" |
| 5621 | "@ | |
| 5622 | xr\t%0,%2 | |
| 5623 | xc\t%O0(2,%R0),%2" | |
| 5624 | [(set_attr "op_type" "RR,SS")]) | |
| 9db1d521 | 5625 | |
| 8cb66696 UW |
5626 | (define_expand "xorhi3" |
| 5627 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 5628 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
| 5629 | (match_operand:HI 2 "general_operand" ""))) | |
| 9db1d521 HP |
5630 | (clobber (reg:CC 33))] |
| 5631 | "" | |
| 8cb66696 | 5632 | "s390_expand_logical_operator (XOR, HImode, operands); DONE;") |
| 9db1d521 HP |
5633 | |
| 5634 | ; | |
| 5635 | ; xorqi3 instruction pattern(s). | |
| 5636 | ; | |
| 5637 | ||
| 8cb66696 UW |
5638 | (define_insn "*xorqi3" |
| 5639 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q") | |
| 5640 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0") | |
| 5641 | (match_operand:QI 2 "general_operand" "d,n,n,Q"))) | |
| 4023fb28 | 5642 | (clobber (reg:CC 33))] |
| 8cb66696 | 5643 | "s390_logical_operator_ok_p (operands)" |
| 9db1d521 | 5644 | "@ |
| 8cb66696 UW |
5645 | xr\t%0,%2 |
| 5646 | xi\t%0,%b2 | |
| 5647 | xiy\t%0,%b2 | |
| 5648 | xc\t%O0(1,%R0),%2" | |
| 5649 | [(set_attr "op_type" "RR,SI,SIY,SS")]) | |
| 4023fb28 | 5650 | |
| 8cb66696 UW |
5651 | (define_expand "xorqi3" |
| 5652 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 5653 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
| 5654 | (match_operand:QI 2 "general_operand" ""))) | |
| 4023fb28 UW |
5655 | (clobber (reg:CC 33))] |
| 5656 | "" | |
| 8cb66696 | 5657 | "s390_expand_logical_operator (XOR, QImode, operands); DONE;") |
| 9db1d521 HP |
5658 | |
| 5659 | ||
| 5660 | ;; | |
| 5661 | ;;- Negate instructions. | |
| 5662 | ;; | |
| 5663 | ||
| 5664 | ; | |
| 5665 | ; negdi2 instruction pattern(s). | |
| 5666 | ; | |
| 5667 | ||
| 5668 | (define_expand "negdi2" | |
| 5669 | [(parallel | |
| 5670 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5671 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 5672 | (clobber (reg:CC 33))])] | |
| 5673 | "" | |
| 5674 | "") | |
| 5675 | ||
| 5676 | (define_insn "*negdi2_64" | |
| 5677 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5678 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 5679 | (clobber (reg:CC 33))] | |
| 5680 | "TARGET_64BIT" | |
| d40c829f | 5681 | "lcgr\t%0,%1" |
| f2d3c02a | 5682 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
5683 | |
| 5684 | (define_insn "*negdi2_31" | |
| 5685 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5686 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 5687 | (clobber (reg:CC 33))] | |
| 5688 | "!TARGET_64BIT" | |
| 9db1d521 HP |
5689 | { |
| 5690 | rtx xop[1]; | |
| 5691 | xop[0] = gen_label_rtx (); | |
| d40c829f UW |
5692 | output_asm_insn ("lcr\t%0,%1", operands); |
| 5693 | output_asm_insn ("lcr\t%N0,%N1", operands); | |
| 5694 | output_asm_insn ("je\t%l0", xop); | |
| 5695 | output_asm_insn ("bctr\t%0,0", operands); | |
| 47798692 | 5696 | targetm.asm_out.internal_label (asm_out_file, "L", |
| 9db1d521 | 5697 | CODE_LABEL_NUMBER (xop[0])); |
| 10bbf137 UW |
5698 | return ""; |
| 5699 | } | |
| 9db1d521 | 5700 | [(set_attr "op_type" "NN") |
| 4023fb28 UW |
5701 | (set_attr "type" "other") |
| 5702 | (set_attr "length" "10")]) | |
| 9db1d521 HP |
5703 | |
| 5704 | ; | |
| 5705 | ; negsi2 instruction pattern(s). | |
| 5706 | ; | |
| 5707 | ||
| 5708 | (define_insn "negsi2" | |
| 5709 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5710 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
| 5711 | (clobber (reg:CC 33))] | |
| 5712 | "" | |
| d40c829f | 5713 | "lcr\t%0,%1" |
| f2d3c02a | 5714 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
5715 | |
| 5716 | ; | |
| 5717 | ; negdf2 instruction pattern(s). | |
| 5718 | ; | |
| 5719 | ||
| 5720 | (define_expand "negdf2" | |
| 5721 | [(parallel | |
| 5722 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5723 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5724 | (clobber (reg:CC 33))])] | |
| 5725 | "TARGET_HARD_FLOAT" | |
| 5726 | "") | |
| 5727 | ||
| 5728 | (define_insn "*negdf2" | |
| 5729 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5730 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5731 | (clobber (reg:CC 33))] | |
| 5732 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 5733 | "lcdbr\t%0,%1" |
| 077dab3b HP |
5734 | [(set_attr "op_type" "RRE") |
| 5735 | (set_attr "type" "fsimpd")]) | |
| 9db1d521 HP |
5736 | |
| 5737 | (define_insn "*negdf2_ibm" | |
| 5738 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5739 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5740 | (clobber (reg:CC 33))] | |
| 5741 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| d40c829f | 5742 | "lcdr\t%0,%1" |
| 077dab3b HP |
5743 | [(set_attr "op_type" "RR") |
| 5744 | (set_attr "type" "fsimpd")]) | |
| 9db1d521 HP |
5745 | |
| 5746 | ; | |
| 5747 | ; negsf2 instruction pattern(s). | |
| 5748 | ; | |
| 5749 | ||
| 5750 | (define_expand "negsf2" | |
| 5751 | [(parallel | |
| 5752 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5753 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5754 | (clobber (reg:CC 33))])] | |
| 5755 | "TARGET_HARD_FLOAT" | |
| 5756 | "") | |
| 5757 | ||
| 5758 | (define_insn "*negsf2" | |
| 5759 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5760 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5761 | (clobber (reg:CC 33))] | |
| 5762 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 5763 | "lcebr\t%0,%1" |
| 077dab3b HP |
5764 | [(set_attr "op_type" "RRE") |
| 5765 | (set_attr "type" "fsimps")]) | |
| 9db1d521 HP |
5766 | |
| 5767 | (define_insn "*negsf2" | |
| 5768 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5769 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5770 | (clobber (reg:CC 33))] | |
| 5771 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| d40c829f | 5772 | "lcer\t%0,%1" |
| 077dab3b HP |
5773 | [(set_attr "op_type" "RR") |
| 5774 | (set_attr "type" "fsimps")]) | |
| 9db1d521 HP |
5775 | |
| 5776 | ||
| 5777 | ;; | |
| 5778 | ;;- Absolute value instructions. | |
| 5779 | ;; | |
| 5780 | ||
| 5781 | ; | |
| 5782 | ; absdi2 instruction pattern(s). | |
| 5783 | ; | |
| 5784 | ||
| 5785 | (define_insn "absdi2" | |
| 5786 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5787 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 5788 | (clobber (reg:CC 33))] | |
| 5789 | "TARGET_64BIT" | |
| d40c829f | 5790 | "lpgr\t%0,%1" |
| f2d3c02a | 5791 | [(set_attr "op_type" "RRE")]) |
| 9db1d521 HP |
5792 | |
| 5793 | ; | |
| 5794 | ; abssi2 instruction pattern(s). | |
| 5795 | ; | |
| 5796 | ||
| 5797 | (define_insn "abssi2" | |
| 5798 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5799 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
| 5800 | (clobber (reg:CC 33))] | |
| 5801 | "" | |
| d40c829f | 5802 | "lpr\t%0,%1" |
| f2d3c02a | 5803 | [(set_attr "op_type" "RR")]) |
| 9db1d521 | 5804 | |
| 9db1d521 HP |
5805 | ; |
| 5806 | ; absdf2 instruction pattern(s). | |
| 5807 | ; | |
| 5808 | ||
| 5809 | (define_expand "absdf2" | |
| 5810 | [(parallel | |
| 5811 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5812 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5813 | (clobber (reg:CC 33))])] | |
| 5814 | "TARGET_HARD_FLOAT" | |
| 5815 | "") | |
| 5816 | ||
| 5817 | (define_insn "*absdf2" | |
| 5818 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5819 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5820 | (clobber (reg:CC 33))] | |
| 5821 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 5822 | "lpdbr\t%0,%1" |
| 077dab3b HP |
5823 | [(set_attr "op_type" "RRE") |
| 5824 | (set_attr "type" "fsimpd")]) | |
| 9db1d521 HP |
5825 | |
| 5826 | (define_insn "*absdf2_ibm" | |
| 5827 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5828 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5829 | (clobber (reg:CC 33))] | |
| 5830 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| d40c829f | 5831 | "lpdr\t%0,%1" |
| 077dab3b HP |
5832 | [(set_attr "op_type" "RR") |
| 5833 | (set_attr "type" "fsimpd")]) | |
| 9db1d521 HP |
5834 | |
| 5835 | ; | |
| 5836 | ; abssf2 instruction pattern(s). | |
| 5837 | ; | |
| 5838 | ||
| 5839 | (define_expand "abssf2" | |
| 5840 | [(parallel | |
| 5841 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5842 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5843 | (clobber (reg:CC 33))])] | |
| 5844 | "TARGET_HARD_FLOAT" | |
| 5845 | "") | |
| 5846 | ||
| 5847 | (define_insn "*abssf2" | |
| 5848 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5849 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5850 | (clobber (reg:CC 33))] | |
| 5851 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 5852 | "lpebr\t%0,%1" |
| 077dab3b HP |
5853 | [(set_attr "op_type" "RRE") |
| 5854 | (set_attr "type" "fsimps")]) | |
| 9db1d521 HP |
5855 | |
| 5856 | (define_insn "*abssf2_ibm" | |
| 5857 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5858 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5859 | (clobber (reg:CC 33))] | |
| 5860 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| d40c829f | 5861 | "lper\t%0,%1" |
| 077dab3b HP |
5862 | [(set_attr "op_type" "RR") |
| 5863 | (set_attr "type" "fsimps")]) | |
| 9db1d521 | 5864 | |
| 3ef093a8 AK |
5865 | ;; |
| 5866 | ;;- Negated absolute value instructions | |
| 5867 | ;; | |
| 5868 | ||
| 5869 | ; | |
| 5870 | ; Integer | |
| 5871 | ; | |
| 5872 | ||
| 5873 | (define_insn "*negabssi2" | |
| 5874 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5875 | (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) | |
| 5876 | (clobber (reg:CC 33))] | |
| 5877 | "" | |
| d40c829f | 5878 | "lnr\t%0,%1" |
| 3ef093a8 AK |
5879 | [(set_attr "op_type" "RR")]) |
| 5880 | ||
| 5881 | (define_insn "*negabsdi2" | |
| 5882 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5883 | (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) | |
| 5884 | (clobber (reg:CC 33))] | |
| 5885 | "TARGET_64BIT" | |
| d40c829f | 5886 | "lngr\t%0,%1" |
| 3ef093a8 AK |
5887 | [(set_attr "op_type" "RRE")]) |
| 5888 | ||
| 5889 | ; | |
| 5890 | ; Floating point | |
| 5891 | ; | |
| 5892 | ||
| 5893 | (define_insn "*negabssf2" | |
| 5894 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5895 | (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) | |
| 5896 | (clobber (reg:CC 33))] | |
| 5897 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 5898 | "lnebr\t%0,%1" |
| 3ef093a8 AK |
5899 | [(set_attr "op_type" "RRE") |
| 5900 | (set_attr "type" "fsimps")]) | |
| 5901 | ||
| 5902 | (define_insn "*negabsdf2" | |
| 5903 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5904 | (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) | |
| 5905 | (clobber (reg:CC 33))] | |
| 5906 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| d40c829f | 5907 | "lndbr\t%0,%1" |
| 3ef093a8 AK |
5908 | [(set_attr "op_type" "RRE") |
| 5909 | (set_attr "type" "fsimpd")]) | |
| 5910 | ||
| 4023fb28 UW |
5911 | ;; |
| 5912 | ;;- Square root instructions. | |
| 5913 | ;; | |
| 5914 | ||
| 5915 | ; | |
| 5916 | ; sqrtdf2 instruction pattern(s). | |
| 5917 | ; | |
| 5918 | ||
| 5919 | (define_insn "sqrtdf2" | |
| 5920 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| d3632d41 | 5921 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] |
| 4023fb28 UW |
5922 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 5923 | "@ | |
| d40c829f UW |
5924 | sqdbr\t%0,%1 |
| 5925 | sqdb\t%0,%1" | |
| d3632d41 | 5926 | [(set_attr "op_type" "RRE,RXE")]) |
| 4023fb28 UW |
5927 | |
| 5928 | ; | |
| 5929 | ; sqrtsf2 instruction pattern(s). | |
| 5930 | ; | |
| 5931 | ||
| 5932 | (define_insn "sqrtsf2" | |
| 5933 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| d3632d41 | 5934 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] |
| 4023fb28 UW |
5935 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 5936 | "@ | |
| d40c829f UW |
5937 | sqebr\t%0,%1 |
| 5938 | sqeb\t%0,%1" | |
| d3632d41 | 5939 | [(set_attr "op_type" "RRE,RXE")]) |
| 9db1d521 HP |
5940 | |
| 5941 | ;; | |
| 5942 | ;;- One complement instructions. | |
| 5943 | ;; | |
| 5944 | ||
| 5945 | ; | |
| 5946 | ; one_cmpldi2 instruction pattern(s). | |
| 5947 | ; | |
| c7453384 | 5948 | |
| 9db1d521 HP |
5949 | (define_expand "one_cmpldi2" |
| 5950 | [(parallel | |
| 4023fb28 UW |
5951 | [(set (match_operand:DI 0 "register_operand" "") |
| 5952 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
| 5953 | (const_int -1))) | |
| 9db1d521 HP |
5954 | (clobber (reg:CC 33))])] |
| 5955 | "TARGET_64BIT" | |
| 4023fb28 | 5956 | "") |
| c7453384 | 5957 | |
| 9db1d521 HP |
5958 | ; |
| 5959 | ; one_cmplsi2 instruction pattern(s). | |
| 5960 | ; | |
| c7453384 | 5961 | |
| 9db1d521 HP |
5962 | (define_expand "one_cmplsi2" |
| 5963 | [(parallel | |
| 4023fb28 UW |
5964 | [(set (match_operand:SI 0 "register_operand" "") |
| 5965 | (xor:SI (match_operand:SI 1 "register_operand" "") | |
| 5966 | (const_int -1))) | |
| 9db1d521 HP |
5967 | (clobber (reg:CC 33))])] |
| 5968 | "" | |
| 4023fb28 | 5969 | "") |
| c7453384 | 5970 | |
| 9db1d521 HP |
5971 | ; |
| 5972 | ; one_cmplhi2 instruction pattern(s). | |
| 5973 | ; | |
| c7453384 | 5974 | |
| 9db1d521 HP |
5975 | (define_expand "one_cmplhi2" |
| 5976 | [(parallel | |
| 4023fb28 UW |
5977 | [(set (match_operand:HI 0 "register_operand" "") |
| 5978 | (xor:HI (match_operand:HI 1 "register_operand" "") | |
| 5979 | (const_int -1))) | |
| 9db1d521 HP |
5980 | (clobber (reg:CC 33))])] |
| 5981 | "" | |
| 4023fb28 | 5982 | "") |
| c7453384 | 5983 | |
| 9db1d521 HP |
5984 | ; |
| 5985 | ; one_cmplqi2 instruction pattern(s). | |
| 5986 | ; | |
| c7453384 | 5987 | |
| 4023fb28 UW |
5988 | (define_expand "one_cmplqi2" |
| 5989 | [(parallel | |
| 5990 | [(set (match_operand:QI 0 "register_operand" "") | |
| 5991 | (xor:QI (match_operand:QI 1 "register_operand" "") | |
| 5992 | (const_int -1))) | |
| 5993 | (clobber (reg:CC 33))])] | |
| 9db1d521 | 5994 | "" |
| 4023fb28 | 5995 | "") |
| 9db1d521 HP |
5996 | |
| 5997 | ||
| 5998 | ;; | |
| 5999 | ;;- Rotate instructions. | |
| 6000 | ;; | |
| 6001 | ||
| 6002 | ; | |
| 6003 | ; rotldi3 instruction pattern(s). | |
| 6004 | ; | |
| 6005 | ||
| 6006 | (define_insn "rotldi3" | |
| ac32b25e UW |
6007 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 6008 | (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
| 6009 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
| 9db1d521 | 6010 | "TARGET_64BIT" |
| ac32b25e | 6011 | "rllg\t%0,%1,%Y2" |
| 077dab3b HP |
6012 | [(set_attr "op_type" "RSE") |
| 6013 | (set_attr "atype" "reg")]) | |
| 9db1d521 HP |
6014 | |
| 6015 | ; | |
| 6016 | ; rotlsi3 instruction pattern(s). | |
| 6017 | ; | |
| 6018 | ||
| 6019 | (define_insn "rotlsi3" | |
| ac32b25e UW |
6020 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 6021 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
| 6022 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
| 9e8327e3 | 6023 | "TARGET_CPU_ZARCH" |
| ac32b25e | 6024 | "rll\t%0,%1,%Y2" |
| 077dab3b HP |
6025 | [(set_attr "op_type" "RSE") |
| 6026 | (set_attr "atype" "reg")]) | |
| 9db1d521 HP |
6027 | |
| 6028 | ||
| 6029 | ;; | |
| 6030 | ;;- Arithmetic shift instructions. | |
| 6031 | ;; | |
| 9db1d521 HP |
6032 | |
| 6033 | ; | |
| 6034 | ; ashldi3 instruction pattern(s). | |
| 6035 | ; | |
| 6036 | ||
| 6037 | (define_expand "ashldi3" | |
| ecbe845e UW |
6038 | [(set (match_operand:DI 0 "register_operand" "") |
| 6039 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
| ac32b25e | 6040 | (match_operand:SI 2 "shift_count_operand" "")))] |
| 9db1d521 HP |
6041 | "" |
| 6042 | "") | |
| 6043 | ||
| 6044 | (define_insn "*ashldi3_31" | |
| ac32b25e UW |
6045 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 6046 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
| 6047 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
| 9db1d521 | 6048 | "!TARGET_64BIT" |
| ac32b25e | 6049 | "sldl\t%0,%Y2" |
| 077dab3b HP |
6050 | [(set_attr "op_type" "RS") |
| 6051 | (set_attr "atype" "reg")]) | |
| 9db1d521 HP |
6052 | |
| 6053 | (define_insn "*ashldi3_64" | |
| ac32b25e UW |
6054 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 6055 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
| 6056 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
| 9db1d521 | 6057 | "TARGET_64BIT" |
| ac32b25e | 6058 | "sllg\t%0,%1,%Y2" |
| 077dab3b HP |
6059 | [(set_attr "op_type" "RSE") |
| 6060 | (set_attr "atype" "reg")]) | |
| 9db1d521 HP |
6061 | |
| 6062 | ; | |
| 6063 | ; ashrdi3 instruction pattern(s). | |
| 6064 | ; | |
| 6065 | ||
| 6066 | (define_expand "ashrdi3" | |
| 6067 | [(parallel | |
| 6068 | [(set (match_operand:DI 0 "register_operand" "") | |
| 6069 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| ac32b25e | 6070 | (match_operand:SI 2 "shift_count_operand" ""))) |
| 9db1d521 HP |
6071 | (clobber (reg:CC 33))])] |
| 6072 | "" | |
| 6073 | "") | |
| 6074 | ||
| ecbe845e UW |
6075 | (define_insn "*ashrdi3_cc_31" |
| 6076 | [(set (reg 33) | |
| ac32b25e UW |
6077 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
| 6078 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
| ecbe845e | 6079 | (const_int 0))) |
| ac32b25e | 6080 | (set (match_operand:DI 0 "register_operand" "=d") |
| ecbe845e UW |
6081 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
| 6082 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
| ac32b25e | 6083 | "srda\t%0,%Y2" |
| 077dab3b HP |
6084 | [(set_attr "op_type" "RS") |
| 6085 | (set_attr "atype" "reg")]) | |
| ecbe845e UW |
6086 | |
| 6087 | (define_insn "*ashrdi3_cconly_31" | |
| 6088 | [(set (reg 33) | |
| ac32b25e UW |
6089 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
| 6090 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
| ecbe845e | 6091 | (const_int 0))) |
| ac32b25e | 6092 | (clobber (match_scratch:DI 0 "=d"))] |
| ecbe845e | 6093 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
| ac32b25e | 6094 | "srda\t%0,%Y2" |
| 077dab3b HP |
6095 | [(set_attr "op_type" "RS") |
| 6096 | (set_attr "atype" "reg")]) | |
| ecbe845e | 6097 | |
| 9db1d521 | 6098 | (define_insn "*ashrdi3_31" |
| ac32b25e UW |
6099 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 6100 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
| 6101 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
| 9db1d521 HP |
6102 | (clobber (reg:CC 33))] |
| 6103 | "!TARGET_64BIT" | |
| ac32b25e | 6104 | "srda\t%0,%Y2" |
| 077dab3b HP |
6105 | [(set_attr "op_type" "RS") |
| 6106 | (set_attr "atype" "reg")]) | |
| c7453384 | 6107 | |
| ecbe845e UW |
6108 | (define_insn "*ashrdi3_cc_64" |
| 6109 | [(set (reg 33) | |
| ac32b25e UW |
6110 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
| 6111 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
| ecbe845e | 6112 | (const_int 0))) |
| ac32b25e | 6113 | (set (match_operand:DI 0 "register_operand" "=d") |
| ecbe845e UW |
6114 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
| 6115 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
| ac32b25e | 6116 | "srag\t%0,%1,%Y2" |
| 077dab3b HP |
6117 | [(set_attr "op_type" "RSE") |
| 6118 | (set_attr "atype" "reg")]) | |
| ecbe845e UW |
6119 | |
| 6120 | (define_insn "*ashrdi3_cconly_64" | |
| 6121 | [(set (reg 33) | |
| ac32b25e UW |
6122 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
| 6123 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
| ecbe845e | 6124 | (const_int 0))) |
| ac32b25e | 6125 | (clobber (match_scratch:DI 0 "=d"))] |
| ecbe845e | 6126 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
| ac32b25e | 6127 | "srag\t%0,%1,%Y2" |
| 077dab3b HP |
6128 | [(set_attr "op_type" "RSE") |
| 6129 | (set_attr "atype" "reg")]) | |
| ecbe845e | 6130 | |
| 9db1d521 | 6131 | (define_insn "*ashrdi3_64" |
| ac32b25e UW |
6132 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 6133 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 6134 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
| 9db1d521 HP |
6135 | (clobber (reg:CC 33))] |
| 6136 | "TARGET_64BIT" | |
| ac32b25e | 6137 | "srag\t%0,%1,%Y2" |
| 077dab3b HP |
6138 | [(set_attr "op_type" "RSE") |
| 6139 | (set_attr "atype" "reg")]) | |
| 6140 | ||
| 9db1d521 HP |
6141 | |
| 6142 | ; | |
| 6143 | ; ashlsi3 instruction pattern(s). | |
| 6144 | ; | |
| 9db1d521 HP |
6145 | |
| 6146 | (define_insn "ashlsi3" | |
| ac32b25e UW |
6147 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 6148 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
| 6149 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
| 9db1d521 | 6150 | "" |
| ac32b25e | 6151 | "sll\t%0,%Y2" |
| 077dab3b HP |
6152 | [(set_attr "op_type" "RS") |
| 6153 | (set_attr "atype" "reg")]) | |
| 9db1d521 HP |
6154 | |
| 6155 | ; | |
| 6156 | ; ashrsi3 instruction pattern(s). | |
| 6157 | ; | |
| 6158 | ||
| ecbe845e UW |
6159 | (define_insn "*ashrsi3_cc" |
| 6160 | [(set (reg 33) | |
| ac32b25e UW |
6161 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
| 6162 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
| ecbe845e | 6163 | (const_int 0))) |
| ac32b25e | 6164 | (set (match_operand:SI 0 "register_operand" "=d") |
| ecbe845e UW |
6165 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
| 6166 | "s390_match_ccmode(insn, CCSmode)" | |
| ac32b25e | 6167 | "sra\t%0,%Y2" |
| 077dab3b HP |
6168 | [(set_attr "op_type" "RS") |
| 6169 | (set_attr "atype" "reg")]) | |
| 6170 | ||
| ecbe845e UW |
6171 | |
| 6172 | (define_insn "*ashrsi3_cconly" | |
| 6173 | [(set (reg 33) | |
| ac32b25e UW |
6174 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
| 6175 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
| ecbe845e | 6176 | (const_int 0))) |
| ac32b25e | 6177 | (clobber (match_scratch:SI 0 "=d"))] |
| ecbe845e | 6178 | "s390_match_ccmode(insn, CCSmode)" |
| ac32b25e | 6179 | "sra\t%0,%Y2" |
| 077dab3b HP |
6180 | [(set_attr "op_type" "RS") |
| 6181 | (set_attr "atype" "reg")]) | |
| ecbe845e | 6182 | |
| 9db1d521 | 6183 | (define_insn "ashrsi3" |
| ac32b25e UW |
6184 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 6185 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
| 6186 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
| 9db1d521 HP |
6187 | (clobber (reg:CC 33))] |
| 6188 | "" | |
| ac32b25e | 6189 | "sra\t%0,%Y2" |
| 077dab3b HP |
6190 | [(set_attr "op_type" "RS") |
| 6191 | (set_attr "atype" "reg")]) | |
| 9db1d521 | 6192 | |
| 9db1d521 HP |
6193 | |
| 6194 | ;; | |
| 6195 | ;;- logical shift instructions. | |
| 6196 | ;; | |
| 6197 | ||
| 6198 | ; | |
| 6199 | ; lshrdi3 instruction pattern(s). | |
| 6200 | ; | |
| 6201 | ||
| 6202 | (define_expand "lshrdi3" | |
| ecbe845e UW |
6203 | [(set (match_operand:DI 0 "register_operand" "") |
| 6204 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| ac32b25e | 6205 | (match_operand:SI 2 "shift_count_operand" "")))] |
| 9db1d521 HP |
6206 | "" |
| 6207 | "") | |
| 6208 | ||
| 6209 | (define_insn "*lshrdi3_31" | |
| ac32b25e UW |
6210 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 6211 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
| 6212 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
| 9db1d521 | 6213 | "!TARGET_64BIT" |
| ac32b25e UW |
6214 | "srdl\t%0,%Y2" |
| 6215 | [(set_attr "op_type" "RS") | |
| 077dab3b | 6216 | (set_attr "atype" "reg")]) |
| 9db1d521 HP |
6217 | |
| 6218 | (define_insn "*lshrdi3_64" | |
| ac32b25e UW |
6219 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 6220 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
| 6221 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
| 9db1d521 | 6222 | "TARGET_64BIT" |
| ac32b25e UW |
6223 | "srlg\t%0,%1,%Y2" |
| 6224 | [(set_attr "op_type" "RSE") | |
| 077dab3b | 6225 | (set_attr "atype" "reg")]) |
| 9db1d521 HP |
6226 | |
| 6227 | ; | |
| 6228 | ; lshrsi3 instruction pattern(s). | |
| 6229 | ; | |
| 6230 | ||
| 6231 | (define_insn "lshrsi3" | |
| ac32b25e UW |
6232 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 6233 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
| 6234 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
| 9db1d521 | 6235 | "" |
| ac32b25e | 6236 | "srl\t%0,%Y2" |
| 077dab3b HP |
6237 | [(set_attr "op_type" "RS") |
| 6238 | (set_attr "atype" "reg")]) | |
| 9db1d521 | 6239 | |
| 9db1d521 HP |
6240 | |
| 6241 | ;; | |
| 6242 | ;; Branch instruction patterns. | |
| 6243 | ;; | |
| 6244 | ||
| 6245 | (define_expand "beq" | |
| 6590e19a | 6246 | [(match_operand 0 "" "")] |
| 9db1d521 | 6247 | "" |
| 6590e19a UW |
6248 | "s390_emit_jump (operands[0], |
| 6249 | s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6250 | |
| 6251 | (define_expand "bne" | |
| 6590e19a | 6252 | [(match_operand 0 "" "")] |
| 9db1d521 | 6253 | "" |
| 6590e19a UW |
6254 | "s390_emit_jump (operands[0], |
| 6255 | s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6256 | |
| 6257 | (define_expand "bgt" | |
| 6590e19a | 6258 | [(match_operand 0 "" "")] |
| 9db1d521 | 6259 | "" |
| 6590e19a UW |
6260 | "s390_emit_jump (operands[0], |
| 6261 | s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6262 | |
| 6263 | (define_expand "bgtu" | |
| 6590e19a | 6264 | [(match_operand 0 "" "")] |
| 9db1d521 | 6265 | "" |
| 6590e19a UW |
6266 | "s390_emit_jump (operands[0], |
| 6267 | s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6268 | |
| 6269 | (define_expand "blt" | |
| 6590e19a | 6270 | [(match_operand 0 "" "")] |
| 9db1d521 | 6271 | "" |
| 6590e19a UW |
6272 | "s390_emit_jump (operands[0], |
| 6273 | s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6274 | |
| 6275 | (define_expand "bltu" | |
| 6590e19a | 6276 | [(match_operand 0 "" "")] |
| 9db1d521 | 6277 | "" |
| 6590e19a UW |
6278 | "s390_emit_jump (operands[0], |
| 6279 | s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6280 | |
| 6281 | (define_expand "bge" | |
| 6590e19a | 6282 | [(match_operand 0 "" "")] |
| 9db1d521 | 6283 | "" |
| 6590e19a UW |
6284 | "s390_emit_jump (operands[0], |
| 6285 | s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6286 | |
| 6287 | (define_expand "bgeu" | |
| 6590e19a | 6288 | [(match_operand 0 "" "")] |
| 9db1d521 | 6289 | "" |
| 6590e19a UW |
6290 | "s390_emit_jump (operands[0], |
| 6291 | s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6292 | |
| 6293 | (define_expand "ble" | |
| 6590e19a | 6294 | [(match_operand 0 "" "")] |
| 9db1d521 | 6295 | "" |
| 6590e19a UW |
6296 | "s390_emit_jump (operands[0], |
| 6297 | s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 HP |
6298 | |
| 6299 | (define_expand "bleu" | |
| 6590e19a | 6300 | [(match_operand 0 "" "")] |
| 9db1d521 | 6301 | "" |
| 6590e19a UW |
6302 | "s390_emit_jump (operands[0], |
| 6303 | s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 9db1d521 | 6304 | |
| ba956982 | 6305 | (define_expand "bunordered" |
| 6590e19a | 6306 | [(match_operand 0 "" "")] |
| ba956982 | 6307 | "" |
| 6590e19a UW |
6308 | "s390_emit_jump (operands[0], |
| 6309 | s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;") | |
| ba956982 UW |
6310 | |
| 6311 | (define_expand "bordered" | |
| 6590e19a | 6312 | [(match_operand 0 "" "")] |
| ba956982 | 6313 | "" |
| 6590e19a UW |
6314 | "s390_emit_jump (operands[0], |
| 6315 | s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;") | |
| ba956982 UW |
6316 | |
| 6317 | (define_expand "buneq" | |
| 6590e19a | 6318 | [(match_operand 0 "" "")] |
| ba956982 | 6319 | "" |
| 6590e19a UW |
6320 | "s390_emit_jump (operands[0], |
| 6321 | s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;") | |
| ba956982 UW |
6322 | |
| 6323 | (define_expand "bunlt" | |
| 6590e19a | 6324 | [(match_operand 0 "" "")] |
| ba956982 | 6325 | "" |
| 6590e19a UW |
6326 | "s390_emit_jump (operands[0], |
| 6327 | s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;") | |
| ba956982 | 6328 | |
| 6590e19a UW |
6329 | (define_expand "bungt" |
| 6330 | [(match_operand 0 "" "")] | |
| ba956982 | 6331 | "" |
| 6590e19a UW |
6332 | "s390_emit_jump (operands[0], |
| 6333 | s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;") | |
| ba956982 UW |
6334 | |
| 6335 | (define_expand "bunle" | |
| 6590e19a | 6336 | [(match_operand 0 "" "")] |
| ba956982 | 6337 | "" |
| 6590e19a UW |
6338 | "s390_emit_jump (operands[0], |
| 6339 | s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;") | |
| 6340 | ||
| 6341 | (define_expand "bunge" | |
| 6342 | [(match_operand 0 "" "")] | |
| 6343 | "" | |
| 6344 | "s390_emit_jump (operands[0], | |
| 6345 | s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;") | |
| ba956982 UW |
6346 | |
| 6347 | (define_expand "bltgt" | |
| 6590e19a | 6348 | [(match_operand 0 "" "")] |
| ba956982 | 6349 | "" |
| 6590e19a UW |
6350 | "s390_emit_jump (operands[0], |
| 6351 | s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;") | |
| ba956982 | 6352 | |
| 9db1d521 HP |
6353 | |
| 6354 | ;; | |
| 6355 | ;;- Conditional jump instructions. | |
| 6356 | ;; | |
| 6357 | ||
| 6590e19a UW |
6358 | (define_insn "*cjump_64" |
| 6359 | [(set (pc) | |
| 6360 | (if_then_else | |
| 5b022de5 | 6361 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
| 6590e19a UW |
6362 | (label_ref (match_operand 0 "" "")) |
| 6363 | (pc)))] | |
| 6364 | "TARGET_CPU_ZARCH" | |
| 9db1d521 | 6365 | { |
| 13e58269 | 6366 | if (get_attr_length (insn) == 4) |
| d40c829f | 6367 | return "j%C1\t%l0"; |
| 6590e19a | 6368 | else |
| d40c829f | 6369 | return "jg%C1\t%l0"; |
| 6590e19a UW |
6370 | } |
| 6371 | [(set_attr "op_type" "RI") | |
| 6372 | (set_attr "type" "branch") | |
| 6373 | (set (attr "length") | |
| 6374 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6375 | (const_int 4) (const_int 6)))]) | |
| 6376 | ||
| 6377 | (define_insn "*cjump_31" | |
| 6378 | [(set (pc) | |
| 6379 | (if_then_else | |
| 5b022de5 | 6380 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
| 6590e19a UW |
6381 | (label_ref (match_operand 0 "" "")) |
| 6382 | (pc)))] | |
| 6383 | "!TARGET_CPU_ZARCH" | |
| 6384 | { | |
| 6385 | if (get_attr_length (insn) == 4) | |
| 6386 | return "j%C1\t%l0"; | |
| 9db1d521 | 6387 | else |
| 13e58269 | 6388 | abort (); |
| 10bbf137 | 6389 | } |
| 9db1d521 | 6390 | [(set_attr "op_type" "RI") |
| 077dab3b | 6391 | (set_attr "type" "branch") |
| 13e58269 | 6392 | (set (attr "length") |
| 6590e19a UW |
6393 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
| 6394 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6395 | (const_int 4) (const_int 6)) | |
| 6396 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6397 | (const_int 4) (const_int 8))))]) | |
| 9db1d521 | 6398 | |
| f314b9b1 | 6399 | (define_insn "*cjump_long" |
| 6590e19a UW |
6400 | [(set (pc) |
| 6401 | (if_then_else | |
| 5b022de5 | 6402 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
| 6590e19a UW |
6403 | (match_operand 0 "address_operand" "U") |
| 6404 | (pc)))] | |
| 9db1d521 | 6405 | "" |
| f314b9b1 UW |
6406 | { |
| 6407 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| d40c829f | 6408 | return "b%C1r\t%0"; |
| f314b9b1 | 6409 | else |
| d40c829f | 6410 | return "b%C1\t%a0"; |
| 10bbf137 | 6411 | } |
| c7453384 | 6412 | [(set (attr "op_type") |
| f314b9b1 UW |
6413 | (if_then_else (match_operand 0 "register_operand" "") |
| 6414 | (const_string "RR") (const_string "RX"))) | |
| 6590e19a | 6415 | (set_attr "type" "branch") |
| 077dab3b | 6416 | (set_attr "atype" "agen")]) |
| 9db1d521 HP |
6417 | |
| 6418 | ||
| 6419 | ;; | |
| 6420 | ;;- Negated conditional jump instructions. | |
| 6421 | ;; | |
| 6422 | ||
| 6590e19a UW |
6423 | (define_insn "*icjump_64" |
| 6424 | [(set (pc) | |
| 6425 | (if_then_else | |
| 5b022de5 | 6426 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
| 6590e19a UW |
6427 | (pc) |
| 6428 | (label_ref (match_operand 0 "" ""))))] | |
| 6429 | "TARGET_CPU_ZARCH" | |
| c7453384 | 6430 | { |
| 13e58269 | 6431 | if (get_attr_length (insn) == 4) |
| d40c829f | 6432 | return "j%D1\t%l0"; |
| 6590e19a | 6433 | else |
| d40c829f | 6434 | return "jg%D1\t%l0"; |
| 6590e19a UW |
6435 | } |
| 6436 | [(set_attr "op_type" "RI") | |
| 6437 | (set_attr "type" "branch") | |
| 6438 | (set (attr "length") | |
| 6439 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6440 | (const_int 4) (const_int 6)))]) | |
| 6441 | ||
| 6442 | (define_insn "*icjump_31" | |
| 6443 | [(set (pc) | |
| 6444 | (if_then_else | |
| 5b022de5 | 6445 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
| 6590e19a UW |
6446 | (pc) |
| 6447 | (label_ref (match_operand 0 "" ""))))] | |
| 6448 | "!TARGET_CPU_ZARCH" | |
| 6449 | { | |
| 6450 | if (get_attr_length (insn) == 4) | |
| 6451 | return "j%D1\t%l0"; | |
| 9db1d521 | 6452 | else |
| 13e58269 | 6453 | abort (); |
| 10bbf137 | 6454 | } |
| 9db1d521 | 6455 | [(set_attr "op_type" "RI") |
| 077dab3b | 6456 | (set_attr "type" "branch") |
| 13e58269 | 6457 | (set (attr "length") |
| 6590e19a UW |
6458 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
| 6459 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6460 | (const_int 4) (const_int 6)) | |
| 6461 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6462 | (const_int 4) (const_int 8))))]) | |
| 9db1d521 | 6463 | |
| f314b9b1 | 6464 | (define_insn "*icjump_long" |
| 6590e19a UW |
6465 | [(set (pc) |
| 6466 | (if_then_else | |
| 5b022de5 | 6467 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
| 6590e19a UW |
6468 | (pc) |
| 6469 | (match_operand 0 "address_operand" "U")))] | |
| 9db1d521 | 6470 | "" |
| f314b9b1 UW |
6471 | { |
| 6472 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| d40c829f | 6473 | return "b%D1r\t%0"; |
| f314b9b1 | 6474 | else |
| d40c829f | 6475 | return "b%D1\t%a0"; |
| 10bbf137 | 6476 | } |
| c7453384 | 6477 | [(set (attr "op_type") |
| f314b9b1 UW |
6478 | (if_then_else (match_operand 0 "register_operand" "") |
| 6479 | (const_string "RR") (const_string "RX"))) | |
| 077dab3b HP |
6480 | (set_attr "type" "branch") |
| 6481 | (set_attr "atype" "agen")]) | |
| 9db1d521 | 6482 | |
| 4456530d HP |
6483 | ;; |
| 6484 | ;;- Trap instructions. | |
| 6485 | ;; | |
| 6486 | ||
| 6487 | (define_insn "trap" | |
| 6488 | [(trap_if (const_int 1) (const_int 0))] | |
| 6489 | "" | |
| d40c829f | 6490 | "j\t.+2" |
| 6590e19a | 6491 | [(set_attr "op_type" "RI") |
| 077dab3b | 6492 | (set_attr "type" "branch")]) |
| 4456530d HP |
6493 | |
| 6494 | (define_expand "conditional_trap" | |
| 6590e19a UW |
6495 | [(trap_if (match_operand 0 "comparison_operator" "") |
| 6496 | (match_operand 1 "general_operand" ""))] | |
| 4456530d | 6497 | "" |
| 4456530d | 6498 | { |
| 6590e19a UW |
6499 | if (operands[1] != const0_rtx) FAIL; |
| 6500 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
| 6501 | s390_compare_op0, s390_compare_op1); | |
| 10bbf137 | 6502 | }) |
| 4456530d HP |
6503 | |
| 6504 | (define_insn "*trap" | |
| 5b022de5 | 6505 | [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)]) |
| 4456530d HP |
6506 | (const_int 0))] |
| 6507 | "" | |
| d40c829f | 6508 | "j%C0\t.+2"; |
| 077dab3b HP |
6509 | [(set_attr "op_type" "RI") |
| 6510 | (set_attr "type" "branch")]) | |
| 9db1d521 HP |
6511 | |
| 6512 | ;; | |
| 0a3bdf9d | 6513 | ;;- Loop instructions. |
| 9db1d521 | 6514 | ;; |
| 0a3bdf9d UW |
6515 | ;; This is all complicated by the fact that since this is a jump insn |
| 6516 | ;; we must handle our own output reloads. | |
| c7453384 | 6517 | |
| 0a3bdf9d UW |
6518 | (define_expand "doloop_end" |
| 6519 | [(use (match_operand 0 "" "")) ; loop pseudo | |
| 6520 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
| 6521 | (use (match_operand 2 "" "")) ; max iterations | |
| 6522 | (use (match_operand 3 "" "")) ; loop level | |
| 6523 | (use (match_operand 4 "" ""))] ; label | |
| 6524 | "" | |
| 0a3bdf9d | 6525 | { |
| 6590e19a UW |
6526 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
| 6527 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
| 6528 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
| 6529 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
| 0a3bdf9d UW |
6530 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
| 6531 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
| 6532 | else | |
| 6533 | FAIL; | |
| 6534 | ||
| 6535 | DONE; | |
| 10bbf137 | 6536 | }) |
| 0a3bdf9d | 6537 | |
| 6590e19a | 6538 | (define_insn_and_split "doloop_si64" |
| 0a3bdf9d UW |
6539 | [(set (pc) |
| 6540 | (if_then_else | |
| 6541 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
| 6542 | (const_int 1)) | |
| 6543 | (label_ref (match_operand 0 "" "")) | |
| 6544 | (pc))) | |
| bd446804 | 6545 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
| 0a3bdf9d UW |
6546 | (plus:SI (match_dup 1) (const_int -1))) |
| 6547 | (clobber (match_scratch:SI 3 "=X,&d")) | |
| 6548 | (clobber (reg:CC 33))] | |
| 6590e19a | 6549 | "TARGET_CPU_ZARCH" |
| 0a3bdf9d UW |
6550 | { |
| 6551 | if (which_alternative != 0) | |
| 10bbf137 | 6552 | return "#"; |
| 0a3bdf9d | 6553 | else if (get_attr_length (insn) == 4) |
| d40c829f | 6554 | return "brct\t%1,%l0"; |
| 6590e19a | 6555 | else |
| 545d16ff | 6556 | return "ahi\t%1,-1\;jgne\t%l0"; |
| 6590e19a UW |
6557 | } |
| 6558 | "&& reload_completed | |
| 6559 | && (! REG_P (operands[2]) | |
| 6560 | || ! rtx_equal_p (operands[1], operands[2]))" | |
| 6561 | [(set (match_dup 3) (match_dup 1)) | |
| 6562 | (parallel [(set (reg:CCAN 33) | |
| 6563 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
| 6564 | (const_int 0))) | |
| 6565 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
| 6566 | (set (match_dup 2) (match_dup 3)) | |
| 6567 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
| 6568 | (label_ref (match_dup 0)) | |
| 6569 | (pc)))] | |
| 6570 | "" | |
| 6571 | [(set_attr "op_type" "RI") | |
| 6572 | (set_attr "type" "branch") | |
| 6573 | (set (attr "length") | |
| 6574 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6575 | (const_int 4) (const_int 10)))]) | |
| 6576 | ||
| 6577 | (define_insn_and_split "doloop_si31" | |
| 6578 | [(set (pc) | |
| 6579 | (if_then_else | |
| 6580 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
| 6581 | (const_int 1)) | |
| 6582 | (label_ref (match_operand 0 "" "")) | |
| 6583 | (pc))) | |
| 6584 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") | |
| 6585 | (plus:SI (match_dup 1) (const_int -1))) | |
| 6586 | (clobber (match_scratch:SI 3 "=X,&d")) | |
| 6587 | (clobber (reg:CC 33))] | |
| 6588 | "!TARGET_CPU_ZARCH" | |
| 6589 | { | |
| 6590 | if (which_alternative != 0) | |
| 6591 | return "#"; | |
| 6592 | else if (get_attr_length (insn) == 4) | |
| 6593 | return "brct\t%1,%l0"; | |
| 0a3bdf9d UW |
6594 | else |
| 6595 | abort (); | |
| 10bbf137 | 6596 | } |
| 6590e19a UW |
6597 | "&& reload_completed |
| 6598 | && (! REG_P (operands[2]) | |
| 6599 | || ! rtx_equal_p (operands[1], operands[2]))" | |
| 6600 | [(set (match_dup 3) (match_dup 1)) | |
| 6601 | (parallel [(set (reg:CCAN 33) | |
| 6602 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
| 6603 | (const_int 0))) | |
| 6604 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
| 6605 | (set (match_dup 2) (match_dup 3)) | |
| 6606 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
| 6607 | (label_ref (match_dup 0)) | |
| 6608 | (pc)))] | |
| 6609 | "" | |
| 0a3bdf9d | 6610 | [(set_attr "op_type" "RI") |
| 077dab3b | 6611 | (set_attr "type" "branch") |
| 0a3bdf9d | 6612 | (set (attr "length") |
| 6590e19a UW |
6613 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
| 6614 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6615 | (const_int 4) (const_int 6)) | |
| 6616 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6617 | (const_int 4) (const_int 8))))]) | |
| 9db1d521 | 6618 | |
| 0a3bdf9d UW |
6619 | (define_insn "*doloop_si_long" |
| 6620 | [(set (pc) | |
| 6621 | (if_then_else | |
| 6622 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
| 6623 | (const_int 1)) | |
| d3632d41 | 6624 | (match_operand 0 "address_operand" "U,U") |
| 0a3bdf9d UW |
6625 | (pc))) |
| 6626 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
| 6627 | (plus:SI (match_dup 1) (const_int -1))) | |
| 6628 | (clobber (match_scratch:SI 3 "=X,&d")) | |
| 6629 | (clobber (reg:CC 33))] | |
| 6590e19a | 6630 | "!TARGET_CPU_ZARCH" |
| 0a3bdf9d UW |
6631 | { |
| 6632 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| d40c829f | 6633 | return "bctr\t%1,%0"; |
| 0a3bdf9d | 6634 | else |
| d40c829f | 6635 | return "bct\t%1,%a0"; |
| 10bbf137 | 6636 | } |
| c7453384 | 6637 | [(set (attr "op_type") |
| 0a3bdf9d UW |
6638 | (if_then_else (match_operand 0 "register_operand" "") |
| 6639 | (const_string "RR") (const_string "RX"))) | |
| 077dab3b HP |
6640 | (set_attr "type" "branch") |
| 6641 | (set_attr "atype" "agen")]) | |
| 0a3bdf9d | 6642 | |
| 6590e19a | 6643 | (define_insn_and_split "doloop_di" |
| 0a3bdf9d UW |
6644 | [(set (pc) |
| 6645 | (if_then_else | |
| 6646 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
| 6647 | (const_int 1)) | |
| 6648 | (label_ref (match_operand 0 "" "")) | |
| 6649 | (pc))) | |
| bd446804 | 6650 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*r") |
| 0a3bdf9d UW |
6651 | (plus:DI (match_dup 1) (const_int -1))) |
| 6652 | (clobber (match_scratch:DI 3 "=X,&d")) | |
| 6653 | (clobber (reg:CC 33))] | |
| 6654 | "TARGET_64BIT" | |
| 0a3bdf9d UW |
6655 | { |
| 6656 | if (which_alternative != 0) | |
| 10bbf137 | 6657 | return "#"; |
| 0a3bdf9d | 6658 | else if (get_attr_length (insn) == 4) |
| d40c829f | 6659 | return "brctg\t%1,%l0"; |
| 0a3bdf9d | 6660 | else |
| 545d16ff | 6661 | return "aghi\t%1,-1\;jgne\t%l0"; |
| 10bbf137 | 6662 | } |
| 6590e19a | 6663 | "&& reload_completed |
| 0a3bdf9d UW |
6664 | && (! REG_P (operands[2]) |
| 6665 | || ! rtx_equal_p (operands[1], operands[2]))" | |
| 6666 | [(set (match_dup 3) (match_dup 1)) | |
| 6667 | (parallel [(set (reg:CCAN 33) | |
| 6668 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) | |
| 6669 | (const_int 0))) | |
| 6670 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
| 6671 | (set (match_dup 2) (match_dup 3)) | |
| 6672 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
| 6590e19a | 6673 | (label_ref (match_dup 0)) |
| 0a3bdf9d | 6674 | (pc)))] |
| 6590e19a UW |
6675 | "" |
| 6676 | [(set_attr "op_type" "RI") | |
| 6677 | (set_attr "type" "branch") | |
| 6678 | (set (attr "length") | |
| 6679 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6680 | (const_int 4) (const_int 10)))]) | |
| 9db1d521 HP |
6681 | |
| 6682 | ;; | |
| 6683 | ;;- Unconditional jump instructions. | |
| 6684 | ;; | |
| 6685 | ||
| 6686 | ; | |
| 6687 | ; jump instruction pattern(s). | |
| 6688 | ; | |
| 6689 | ||
| 6590e19a UW |
6690 | (define_expand "jump" |
| 6691 | [(match_operand 0 "" "")] | |
| 9db1d521 | 6692 | "" |
| 6590e19a UW |
6693 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
| 6694 | ||
| 6695 | (define_insn "*jump64" | |
| 6696 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
| 6697 | "TARGET_CPU_ZARCH" | |
| 9db1d521 | 6698 | { |
| 13e58269 | 6699 | if (get_attr_length (insn) == 4) |
| d40c829f | 6700 | return "j\t%l0"; |
| 6590e19a | 6701 | else |
| d40c829f | 6702 | return "jg\t%l0"; |
| 6590e19a UW |
6703 | } |
| 6704 | [(set_attr "op_type" "RI") | |
| 6705 | (set_attr "type" "branch") | |
| 6706 | (set (attr "length") | |
| 6707 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6708 | (const_int 4) (const_int 6)))]) | |
| 6709 | ||
| 6710 | (define_insn "*jump31" | |
| 6711 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
| 6712 | "!TARGET_CPU_ZARCH" | |
| 6713 | { | |
| 6714 | if (get_attr_length (insn) == 4) | |
| 6715 | return "j\t%l0"; | |
| 9db1d521 | 6716 | else |
| 13e58269 | 6717 | abort (); |
| 10bbf137 | 6718 | } |
| 9db1d521 | 6719 | [(set_attr "op_type" "RI") |
| 077dab3b | 6720 | (set_attr "type" "branch") |
| 13e58269 | 6721 | (set (attr "length") |
| 6590e19a UW |
6722 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
| 6723 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6724 | (const_int 4) (const_int 6)) | |
| 6725 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 6726 | (const_int 4) (const_int 8))))]) | |
| 9db1d521 HP |
6727 | |
| 6728 | ; | |
| 6729 | ; indirect-jump instruction pattern(s). | |
| 6730 | ; | |
| 6731 | ||
| 6732 | (define_insn "indirect_jump" | |
| d3632d41 | 6733 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
| 9db1d521 | 6734 | "" |
| f314b9b1 UW |
6735 | { |
| 6736 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| d40c829f | 6737 | return "br\t%0"; |
| f314b9b1 | 6738 | else |
| d40c829f | 6739 | return "b\t%a0"; |
| 10bbf137 | 6740 | } |
| c7453384 | 6741 | [(set (attr "op_type") |
| f314b9b1 UW |
6742 | (if_then_else (match_operand 0 "register_operand" "") |
| 6743 | (const_string "RR") (const_string "RX"))) | |
| 077dab3b HP |
6744 | (set_attr "type" "branch") |
| 6745 | (set_attr "atype" "agen")]) | |
| 9db1d521 HP |
6746 | |
| 6747 | ; | |
| f314b9b1 | 6748 | ; casesi instruction pattern(s). |
| 9db1d521 HP |
6749 | ; |
| 6750 | ||
| f314b9b1 | 6751 | (define_insn "casesi_jump" |
| d3632d41 | 6752 | [(set (pc) (match_operand 0 "address_operand" "U")) |
| f314b9b1 | 6753 | (use (label_ref (match_operand 1 "" "")))] |
| 9db1d521 | 6754 | "" |
| 9db1d521 | 6755 | { |
| f314b9b1 | 6756 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
| d40c829f | 6757 | return "br\t%0"; |
| f314b9b1 | 6758 | else |
| d40c829f | 6759 | return "b\t%a0"; |
| 10bbf137 | 6760 | } |
| c7453384 | 6761 | [(set (attr "op_type") |
| f314b9b1 UW |
6762 | (if_then_else (match_operand 0 "register_operand" "") |
| 6763 | (const_string "RR") (const_string "RX"))) | |
| 077dab3b HP |
6764 | (set_attr "type" "branch") |
| 6765 | (set_attr "atype" "agen")]) | |
| 9db1d521 | 6766 | |
| f314b9b1 UW |
6767 | (define_expand "casesi" |
| 6768 | [(match_operand:SI 0 "general_operand" "") | |
| 6769 | (match_operand:SI 1 "general_operand" "") | |
| 6770 | (match_operand:SI 2 "general_operand" "") | |
| 6771 | (label_ref (match_operand 3 "" "")) | |
| 6772 | (label_ref (match_operand 4 "" ""))] | |
| 9db1d521 | 6773 | "" |
| f314b9b1 UW |
6774 | { |
| 6775 | rtx index = gen_reg_rtx (SImode); | |
| 6776 | rtx base = gen_reg_rtx (Pmode); | |
| 6777 | rtx target = gen_reg_rtx (Pmode); | |
| 6778 | ||
| 6779 | emit_move_insn (index, operands[0]); | |
| 6780 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
| 6781 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
| e790b36a | 6782 | operands[4]); |
| f314b9b1 UW |
6783 | |
| 6784 | if (Pmode != SImode) | |
| 6785 | index = convert_to_mode (Pmode, index, 1); | |
| 6786 | if (GET_CODE (index) != REG) | |
| 6787 | index = copy_to_mode_reg (Pmode, index); | |
| 6788 | ||
| 6789 | if (TARGET_64BIT) | |
| 6790 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
| 6791 | else | |
| a556fd39 | 6792 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
| 9db1d521 | 6793 | |
| f314b9b1 UW |
6794 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
| 6795 | ||
| 542a8afa | 6796 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
| f314b9b1 UW |
6797 | emit_move_insn (target, index); |
| 6798 | ||
| 6799 | if (flag_pic) | |
| 6800 | target = gen_rtx_PLUS (Pmode, base, target); | |
| 6801 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
| 6802 | ||
| 6803 | DONE; | |
| 10bbf137 | 6804 | }) |
| 9db1d521 HP |
6805 | |
| 6806 | ||
| 6807 | ;; | |
| 6808 | ;;- Jump to subroutine. | |
| 6809 | ;; | |
| 6810 | ;; | |
| 6811 | ||
| 6812 | ; | |
| 6813 | ; untyped call instruction pattern(s). | |
| 6814 | ; | |
| 6815 | ||
| 6816 | ;; Call subroutine returning any type. | |
| 6817 | (define_expand "untyped_call" | |
| 6818 | [(parallel [(call (match_operand 0 "" "") | |
| 6819 | (const_int 0)) | |
| 6820 | (match_operand 1 "" "") | |
| 6821 | (match_operand 2 "" "")])] | |
| 6822 | "" | |
| 9db1d521 HP |
6823 | { |
| 6824 | int i; | |
| 6825 | ||
| 6826 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
| 6827 | ||
| 6828 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
| 6829 | { | |
| 6830 | rtx set = XVECEXP (operands[2], 0, i); | |
| 6831 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
| 6832 | } | |
| 6833 | ||
| 6834 | /* The optimizer does not know that the call sets the function value | |
| 6835 | registers we stored in the result block. We avoid problems by | |
| 6836 | claiming that all hard registers are used and clobbered at this | |
| 6837 | point. */ | |
| 6838 | emit_insn (gen_blockage ()); | |
| 6839 | ||
| 6840 | DONE; | |
| 10bbf137 | 6841 | }) |
| 9db1d521 HP |
6842 | |
| 6843 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
| 6844 | ;; all of memory. This blocks insns from being moved across this point. | |
| 6845 | ||
| 6846 | (define_insn "blockage" | |
| 10bbf137 | 6847 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
| 9db1d521 | 6848 | "" |
| 4023fb28 | 6849 | "" |
| d5869ca0 UW |
6850 | [(set_attr "type" "none") |
| 6851 | (set_attr "length" "0")]) | |
| 4023fb28 | 6852 | |
| 9db1d521 | 6853 | ; |
| ed9676cf | 6854 | ; sibcall patterns |
| 9db1d521 HP |
6855 | ; |
| 6856 | ||
| ed9676cf | 6857 | (define_expand "sibcall" |
| 44b8152b | 6858 | [(call (match_operand 0 "" "") |
| ed9676cf | 6859 | (match_operand 1 "" ""))] |
| 9db1d521 | 6860 | "" |
| 9db1d521 | 6861 | { |
| ed9676cf AK |
6862 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
| 6863 | DONE; | |
| 6864 | }) | |
| 9db1d521 | 6865 | |
| ed9676cf AK |
6866 | (define_insn "*sibcall_br" |
| 6867 | [(call (mem:QI (reg 1)) | |
| 6868 | (match_operand 0 "const_int_operand" "n"))] | |
| 2f7e5a0d | 6869 | "SIBLING_CALL_P (insn) |
| ed9676cf AK |
6870 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
| 6871 | "br\t%%r1" | |
| 6872 | [(set_attr "op_type" "RR") | |
| 6873 | (set_attr "type" "branch") | |
| 6874 | (set_attr "atype" "agen")]) | |
| 9db1d521 | 6875 | |
| ed9676cf AK |
6876 | (define_insn "*sibcall_brc" |
| 6877 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
| 6878 | (match_operand 1 "const_int_operand" "n"))] | |
| 6879 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
| 6880 | "j\t%0" | |
| 6881 | [(set_attr "op_type" "RI") | |
| 6882 | (set_attr "type" "branch")]) | |
| 9db1d521 | 6883 | |
| ed9676cf AK |
6884 | (define_insn "*sibcall_brcl" |
| 6885 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
| 6886 | (match_operand 1 "const_int_operand" "n"))] | |
| 6887 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
| 6888 | "jg\t%0" | |
| 6889 | [(set_attr "op_type" "RIL") | |
| 6890 | (set_attr "type" "branch")]) | |
| 44b8152b | 6891 | |
| ed9676cf AK |
6892 | ; |
| 6893 | ; sibcall_value patterns | |
| 6894 | ; | |
| 9e8327e3 | 6895 | |
| ed9676cf AK |
6896 | (define_expand "sibcall_value" |
| 6897 | [(set (match_operand 0 "" "") | |
| 6898 | (call (match_operand 1 "" "") | |
| 6899 | (match_operand 2 "" "")))] | |
| 6900 | "" | |
| 6901 | { | |
| 6902 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
| 44b8152b | 6903 | DONE; |
| 10bbf137 | 6904 | }) |
| 9db1d521 | 6905 | |
| ed9676cf AK |
6906 | (define_insn "*sibcall_value_br" |
| 6907 | [(set (match_operand 0 "" "") | |
| 6908 | (call (mem:QI (reg 1)) | |
| 6909 | (match_operand 1 "const_int_operand" "n")))] | |
| 2f7e5a0d | 6910 | "SIBLING_CALL_P (insn) |
| ed9676cf AK |
6911 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
| 6912 | "br\t%%r1" | |
| 6913 | [(set_attr "op_type" "RR") | |
| 6914 | (set_attr "type" "branch") | |
| 6915 | (set_attr "atype" "agen")]) | |
| 6916 | ||
| 6917 | (define_insn "*sibcall_value_brc" | |
| 6918 | [(set (match_operand 0 "" "") | |
| 6919 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
| 6920 | (match_operand 2 "const_int_operand" "n")))] | |
| 6921 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
| 6922 | "j\t%1" | |
| 6923 | [(set_attr "op_type" "RI") | |
| 6924 | (set_attr "type" "branch")]) | |
| 6925 | ||
| 6926 | (define_insn "*sibcall_value_brcl" | |
| 6927 | [(set (match_operand 0 "" "") | |
| 6928 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
| 6929 | (match_operand 2 "const_int_operand" "n")))] | |
| 6930 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
| 6931 | "jg\t%1" | |
| 6932 | [(set_attr "op_type" "RIL") | |
| 6933 | (set_attr "type" "branch")]) | |
| 6934 | ||
| 6935 | ||
| 6936 | ; | |
| 6937 | ; call instruction pattern(s). | |
| 6938 | ; | |
| 6939 | ||
| 6940 | (define_expand "call" | |
| 6941 | [(call (match_operand 0 "" "") | |
| 6942 | (match_operand 1 "" "")) | |
| 6943 | (use (match_operand 2 "" ""))] | |
| 44b8152b | 6944 | "" |
| ed9676cf | 6945 | { |
| 2f7e5a0d | 6946 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
| ed9676cf AK |
6947 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
| 6948 | DONE; | |
| 6949 | }) | |
| 44b8152b | 6950 | |
| 9e8327e3 UW |
6951 | (define_insn "*bras" |
| 6952 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
| 6953 | (match_operand 1 "const_int_operand" "n")) | |
| 6954 | (clobber (match_operand 2 "register_operand" "=r"))] | |
| 2f7e5a0d EC |
6955 | "!SIBLING_CALL_P (insn) |
| 6956 | && TARGET_SMALL_EXEC | |
| ed9676cf | 6957 | && GET_MODE (operands[2]) == Pmode" |
| d40c829f | 6958 | "bras\t%2,%0" |
| 9db1d521 | 6959 | [(set_attr "op_type" "RI") |
| 4023fb28 | 6960 | (set_attr "type" "jsr")]) |
| 9db1d521 | 6961 | |
| 9e8327e3 UW |
6962 | (define_insn "*brasl" |
| 6963 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
| 6964 | (match_operand 1 "const_int_operand" "n")) | |
| 6965 | (clobber (match_operand 2 "register_operand" "=r"))] | |
| 2f7e5a0d EC |
6966 | "!SIBLING_CALL_P (insn) |
| 6967 | && TARGET_CPU_ZARCH | |
| ed9676cf | 6968 | && GET_MODE (operands[2]) == Pmode" |
| 9e8327e3 UW |
6969 | "brasl\t%2,%0" |
| 6970 | [(set_attr "op_type" "RIL") | |
| 077dab3b | 6971 | (set_attr "type" "jsr")]) |
| 9db1d521 | 6972 | |
| 9e8327e3 UW |
6973 | (define_insn "*basr" |
| 6974 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
| 6975 | (match_operand 1 "const_int_operand" "n")) | |
| 6976 | (clobber (match_operand 2 "register_operand" "=r"))] | |
| ed9676cf | 6977 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
| 9e8327e3 UW |
6978 | { |
| 6979 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| 6980 | return "basr\t%2,%0"; | |
| 6981 | else | |
| 6982 | return "bas\t%2,%a0"; | |
| 6983 | } | |
| 6984 | [(set (attr "op_type") | |
| 6985 | (if_then_else (match_operand 0 "register_operand" "") | |
| 6986 | (const_string "RR") (const_string "RX"))) | |
| 6987 | (set_attr "type" "jsr") | |
| 6988 | (set_attr "atype" "agen")]) | |
| 9db1d521 HP |
6989 | |
| 6990 | ; | |
| 6991 | ; call_value instruction pattern(s). | |
| 6992 | ; | |
| 6993 | ||
| 6994 | (define_expand "call_value" | |
| 44b8152b UW |
6995 | [(set (match_operand 0 "" "") |
| 6996 | (call (match_operand 1 "" "") | |
| 6997 | (match_operand 2 "" ""))) | |
| 6998 | (use (match_operand 3 "" ""))] | |
| 9db1d521 | 6999 | "" |
| 9db1d521 | 7000 | { |
| 2f7e5a0d | 7001 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
| ed9676cf | 7002 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
| 44b8152b | 7003 | DONE; |
| 10bbf137 | 7004 | }) |
| 9db1d521 | 7005 | |
| 9e8327e3 | 7006 | (define_insn "*bras_r" |
| c19ec8f9 | 7007 | [(set (match_operand 0 "" "") |
| 9e8327e3 | 7008 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
| 9db1d521 | 7009 | (match_operand:SI 2 "const_int_operand" "n"))) |
| 9e8327e3 | 7010 | (clobber (match_operand 3 "register_operand" "=r"))] |
| 2f7e5a0d EC |
7011 | "!SIBLING_CALL_P (insn) |
| 7012 | && TARGET_SMALL_EXEC | |
| ed9676cf | 7013 | && GET_MODE (operands[3]) == Pmode" |
| d40c829f | 7014 | "bras\t%3,%1" |
| 9db1d521 | 7015 | [(set_attr "op_type" "RI") |
| f2d3c02a | 7016 | (set_attr "type" "jsr")]) |
| 9db1d521 | 7017 | |
| 9e8327e3 | 7018 | (define_insn "*brasl_r" |
| c19ec8f9 | 7019 | [(set (match_operand 0 "" "") |
| 9e8327e3 UW |
7020 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
| 7021 | (match_operand 2 "const_int_operand" "n"))) | |
| 7022 | (clobber (match_operand 3 "register_operand" "=r"))] | |
| 2f7e5a0d EC |
7023 | "!SIBLING_CALL_P (insn) |
| 7024 | && TARGET_CPU_ZARCH | |
| ed9676cf | 7025 | && GET_MODE (operands[3]) == Pmode" |
| 9e8327e3 UW |
7026 | "brasl\t%3,%1" |
| 7027 | [(set_attr "op_type" "RIL") | |
| 077dab3b | 7028 | (set_attr "type" "jsr")]) |
| 9db1d521 | 7029 | |
| 9e8327e3 | 7030 | (define_insn "*basr_r" |
| c19ec8f9 | 7031 | [(set (match_operand 0 "" "") |
| 9e8327e3 UW |
7032 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
| 7033 | (match_operand 2 "const_int_operand" "n"))) | |
| 7034 | (clobber (match_operand 3 "register_operand" "=r"))] | |
| ed9676cf | 7035 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
| 9e8327e3 UW |
7036 | { |
| 7037 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| 7038 | return "basr\t%3,%1"; | |
| 7039 | else | |
| 7040 | return "bas\t%3,%a1"; | |
| 7041 | } | |
| 7042 | [(set (attr "op_type") | |
| 7043 | (if_then_else (match_operand 1 "register_operand" "") | |
| 7044 | (const_string "RR") (const_string "RX"))) | |
| 7045 | (set_attr "type" "jsr") | |
| 7046 | (set_attr "atype" "agen")]) | |
| 9db1d521 | 7047 | |
| fd3cd001 UW |
7048 | ;; |
| 7049 | ;;- Thread-local storage support. | |
| 7050 | ;; | |
| 7051 | ||
| 7052 | (define_insn "get_tp_64" | |
| 7053 | [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q") | |
| 7054 | (unspec:DI [(const_int 0)] UNSPEC_TP))] | |
| 7055 | "TARGET_64BIT" | |
| 7056 | "@ | |
| d40c829f UW |
7057 | ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1 |
| 7058 | stam\t%%a0,%%a1,%0" | |
| fd3cd001 UW |
7059 | [(set_attr "op_type" "NN,RS") |
| 7060 | (set_attr "atype" "reg,*") | |
| 7061 | (set_attr "type" "o3,*") | |
| 7062 | (set_attr "length" "14,*")]) | |
| 7063 | ||
| 7064 | (define_insn "get_tp_31" | |
| 7065 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q") | |
| 7066 | (unspec:SI [(const_int 0)] UNSPEC_TP))] | |
| 7067 | "!TARGET_64BIT" | |
| 7068 | "@ | |
| d40c829f UW |
7069 | ear\t%0,%%a0 |
| 7070 | stam\t%%a0,%%a0,%0" | |
| fd3cd001 UW |
7071 | [(set_attr "op_type" "RRE,RS")]) |
| 7072 | ||
| 7073 | (define_insn "set_tp_64" | |
| 7074 | [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP) | |
| 7075 | (clobber (match_scratch:SI 1 "=d,X"))] | |
| 7076 | "TARGET_64BIT" | |
| 7077 | "@ | |
| d40c829f UW |
7078 | sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1 |
| 7079 | lam\t%%a0,%%a1,%0" | |
| fd3cd001 UW |
7080 | [(set_attr "op_type" "NN,RS") |
| 7081 | (set_attr "atype" "reg,*") | |
| 7082 | (set_attr "type" "o3,*") | |
| 7083 | (set_attr "length" "14,*")]) | |
| 7084 | ||
| 7085 | (define_insn "set_tp_31" | |
| 7086 | [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)] | |
| 7087 | "!TARGET_64BIT" | |
| 7088 | "@ | |
| d40c829f UW |
7089 | sar\t%%a0,%0 |
| 7090 | lam\t%%a0,%%a0,%0" | |
| fd3cd001 | 7091 | [(set_attr "op_type" "RRE,RS")]) |
| c7453384 | 7092 | |
| fd3cd001 UW |
7093 | (define_insn "*tls_load_64" |
| 7094 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 7095 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
| 7096 | (match_operand:DI 2 "" "")] | |
| 7097 | UNSPEC_TLS_LOAD))] | |
| 7098 | "TARGET_64BIT" | |
| d40c829f | 7099 | "lg\t%0,%1%J2" |
| fd3cd001 UW |
7100 | [(set_attr "op_type" "RXE")]) |
| 7101 | ||
| 7102 | (define_insn "*tls_load_31" | |
| d3632d41 UW |
7103 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 7104 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
| fd3cd001 UW |
7105 | (match_operand:SI 2 "" "")] |
| 7106 | UNSPEC_TLS_LOAD))] | |
| 7107 | "!TARGET_64BIT" | |
| d3632d41 | 7108 | "@ |
| d40c829f UW |
7109 | l\t%0,%1%J2 |
| 7110 | ly\t%0,%1%J2" | |
| d3632d41 | 7111 | [(set_attr "op_type" "RX,RXY")]) |
| fd3cd001 | 7112 | |
| 9e8327e3 | 7113 | (define_insn "*bras_tls" |
| c19ec8f9 | 7114 | [(set (match_operand 0 "" "") |
| 9e8327e3 UW |
7115 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
| 7116 | (match_operand 2 "const_int_operand" "n"))) | |
| 7117 | (clobber (match_operand 3 "register_operand" "=r")) | |
| 7118 | (use (match_operand 4 "" ""))] | |
| 2f7e5a0d EC |
7119 | "!SIBLING_CALL_P (insn) |
| 7120 | && TARGET_SMALL_EXEC | |
| ed9676cf | 7121 | && GET_MODE (operands[3]) == Pmode" |
| d40c829f | 7122 | "bras\t%3,%1%J4" |
| fd3cd001 UW |
7123 | [(set_attr "op_type" "RI") |
| 7124 | (set_attr "type" "jsr")]) | |
| 7125 | ||
| 9e8327e3 | 7126 | (define_insn "*brasl_tls" |
| c19ec8f9 | 7127 | [(set (match_operand 0 "" "") |
| 9e8327e3 UW |
7128 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
| 7129 | (match_operand 2 "const_int_operand" "n"))) | |
| 7130 | (clobber (match_operand 3 "register_operand" "=r")) | |
| 7131 | (use (match_operand 4 "" ""))] | |
| 2f7e5a0d EC |
7132 | "!SIBLING_CALL_P (insn) |
| 7133 | && TARGET_CPU_ZARCH | |
| ed9676cf | 7134 | && GET_MODE (operands[3]) == Pmode" |
| 9e8327e3 UW |
7135 | "brasl\t%3,%1%J4" |
| 7136 | [(set_attr "op_type" "RIL") | |
| fd3cd001 UW |
7137 | (set_attr "type" "jsr")]) |
| 7138 | ||
| 9e8327e3 | 7139 | (define_insn "*basr_tls" |
| c19ec8f9 | 7140 | [(set (match_operand 0 "" "") |
| 9e8327e3 UW |
7141 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
| 7142 | (match_operand 2 "const_int_operand" "n"))) | |
| 7143 | (clobber (match_operand 3 "register_operand" "=r")) | |
| 7144 | (use (match_operand 4 "" ""))] | |
| ed9676cf | 7145 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
| 9e8327e3 UW |
7146 | { |
| 7147 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| 7148 | return "basr\t%3,%1%J4"; | |
| 7149 | else | |
| 7150 | return "bas\t%3,%a1%J4"; | |
| 7151 | } | |
| 7152 | [(set (attr "op_type") | |
| 7153 | (if_then_else (match_operand 1 "register_operand" "") | |
| 7154 | (const_string "RR") (const_string "RX"))) | |
| 7155 | (set_attr "type" "jsr") | |
| 7156 | (set_attr "atype" "agen")]) | |
| fd3cd001 | 7157 | |
| 9db1d521 HP |
7158 | ;; |
| 7159 | ;;- Miscellaneous instructions. | |
| 7160 | ;; | |
| 7161 | ||
| 7162 | ; | |
| 7163 | ; allocate stack instruction pattern(s). | |
| 7164 | ; | |
| 7165 | ||
| 7166 | (define_expand "allocate_stack" | |
| ef44a6ff UW |
7167 | [(match_operand 0 "general_operand" "") |
| 7168 | (match_operand 1 "general_operand" "")] | |
| adf39f8f | 7169 | "TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN" |
| 9db1d521 | 7170 | { |
| ef44a6ff | 7171 | rtx temp = gen_reg_rtx (Pmode); |
| 9db1d521 | 7172 | |
| ef44a6ff UW |
7173 | emit_move_insn (temp, s390_back_chain_rtx ()); |
| 7174 | anti_adjust_stack (operands[1]); | |
| 7175 | emit_move_insn (s390_back_chain_rtx (), temp); | |
| 9db1d521 | 7176 | |
| ef44a6ff UW |
7177 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
| 7178 | DONE; | |
| 10bbf137 | 7179 | }) |
| 9db1d521 HP |
7180 | |
| 7181 | ||
| 7182 | ; | |
| 43ab026f | 7183 | ; setjmp instruction pattern. |
| 9db1d521 HP |
7184 | ; |
| 7185 | ||
| 9db1d521 | 7186 | (define_expand "builtin_setjmp_receiver" |
| fd7643fb | 7187 | [(match_operand 0 "" "")] |
| f314b9b1 | 7188 | "flag_pic" |
| 9db1d521 | 7189 | { |
| 585539a1 | 7190 | emit_insn (s390_load_got ()); |
| fd7643fb | 7191 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
| 9db1d521 | 7192 | DONE; |
| fd7643fb | 7193 | }) |
| 9db1d521 | 7194 | |
| 9db1d521 HP |
7195 | ;; These patterns say how to save and restore the stack pointer. We need not |
| 7196 | ;; save the stack pointer at function level since we are careful to | |
| 7197 | ;; preserve the backchain. At block level, we have to restore the backchain | |
| 7198 | ;; when we restore the stack pointer. | |
| 7199 | ;; | |
| 7200 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
| 7201 | ;; backchain and restore both. Note that in the nonlocal case, the | |
| 7202 | ;; save area is a memory location. | |
| 7203 | ||
| 7204 | (define_expand "save_stack_function" | |
| 7205 | [(match_operand 0 "general_operand" "") | |
| 7206 | (match_operand 1 "general_operand" "")] | |
| 7207 | "" | |
| 7208 | "DONE;") | |
| 7209 | ||
| 7210 | (define_expand "restore_stack_function" | |
| 7211 | [(match_operand 0 "general_operand" "") | |
| 7212 | (match_operand 1 "general_operand" "")] | |
| 7213 | "" | |
| 7214 | "DONE;") | |
| 7215 | ||
| 7216 | (define_expand "restore_stack_block" | |
| ef44a6ff UW |
7217 | [(match_operand 0 "register_operand" "") |
| 7218 | (match_operand 1 "register_operand" "")] | |
| 7219 | "TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN" | |
| 9db1d521 | 7220 | { |
| ef44a6ff UW |
7221 | rtx temp = gen_reg_rtx (Pmode); |
| 7222 | ||
| 7223 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
| 7224 | emit_move_insn (operands[0], operands[1]); | |
| 7225 | emit_move_insn (s390_back_chain_rtx (), temp); | |
| 7226 | ||
| 7227 | DONE; | |
| 10bbf137 | 7228 | }) |
| 9db1d521 HP |
7229 | |
| 7230 | (define_expand "save_stack_nonlocal" | |
| 7231 | [(match_operand 0 "memory_operand" "") | |
| 7232 | (match_operand 1 "register_operand" "")] | |
| 7233 | "" | |
| 9db1d521 | 7234 | { |
| ef44a6ff UW |
7235 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
| 7236 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
| 7237 | ||
| 7238 | /* Copy the backchain to the first word, sp to the second and the | |
| 7239 | literal pool base to the third. */ | |
| 7240 | ||
| 7241 | if (TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN) | |
| 7242 | { | |
| 7243 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
| 7244 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
| 7245 | } | |
| 7246 | ||
| 7247 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
| 7248 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
| 9db1d521 | 7249 | |
| 9db1d521 | 7250 | DONE; |
| 10bbf137 | 7251 | }) |
| 9db1d521 HP |
7252 | |
| 7253 | (define_expand "restore_stack_nonlocal" | |
| 7254 | [(match_operand 0 "register_operand" "") | |
| 7255 | (match_operand 1 "memory_operand" "")] | |
| 7256 | "" | |
| 9db1d521 | 7257 | { |
| ef44a6ff | 7258 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
| 490ceeb4 | 7259 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
| ef44a6ff | 7260 | rtx temp = NULL_RTX; |
| 9db1d521 | 7261 | |
| 43ab026f | 7262 | /* Restore the backchain from the first word, sp from the second and the |
| ff482c8d | 7263 | literal pool base from the third. */ |
| 43ab026f | 7264 | |
| ef44a6ff UW |
7265 | if (TARGET_BACKCHAIN || TARGET_KERNEL_BACKCHAIN) |
| 7266 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); | |
| 7267 | ||
| 7268 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
| 7269 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
| 7270 | ||
| 7271 | if (temp) | |
| 7272 | emit_move_insn (s390_back_chain_rtx (), temp); | |
| 7273 | ||
| 7274 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
| 9db1d521 | 7275 | DONE; |
| 10bbf137 | 7276 | }) |
| 9db1d521 HP |
7277 | |
| 7278 | ||
| 7279 | ; | |
| 7280 | ; nop instruction pattern(s). | |
| 7281 | ; | |
| 7282 | ||
| 7283 | (define_insn "nop" | |
| 7284 | [(const_int 0)] | |
| 7285 | "" | |
| d40c829f | 7286 | "lr\t0,0" |
| 9db1d521 HP |
7287 | [(set_attr "op_type" "RR")]) |
| 7288 | ||
| 7289 | ||
| 7290 | ; | |
| 7291 | ; Special literal pool access instruction pattern(s). | |
| 7292 | ; | |
| 7293 | ||
| 416cf582 UW |
7294 | (define_insn "*pool_entry" |
| 7295 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
| 7296 | UNSPECV_POOL_ENTRY)] | |
| 9db1d521 | 7297 | "" |
| 9db1d521 | 7298 | { |
| 416cf582 UW |
7299 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
| 7300 | unsigned int align = GET_MODE_BITSIZE (mode); | |
| faeb9bb6 | 7301 | s390_output_pool_entry (operands[0], mode, align); |
| fd7643fb UW |
7302 | return ""; |
| 7303 | } | |
| 416cf582 | 7304 | [(set_attr "op_type" "NN") |
| 2f7e5a0d | 7305 | (set (attr "length") |
| 416cf582 | 7306 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
| b2ccb744 | 7307 | |
| 9bb86f41 UW |
7308 | (define_insn "pool_align" |
| 7309 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
| 7310 | UNSPECV_POOL_ALIGN)] | |
| 7311 | "" | |
| 7312 | ".align\t%0" | |
| 7313 | [(set_attr "op_type" "NN") | |
| 7314 | (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
| b2ccb744 | 7315 | |
| 9bb86f41 UW |
7316 | (define_insn "pool_section_start" |
| 7317 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
| 7318 | "" | |
| 7319 | ".section\t.rodata" | |
| 7320 | [(set_attr "op_type" "NN") | |
| 7321 | (set_attr "length" "0")]) | |
| b2ccb744 | 7322 | |
| 9bb86f41 UW |
7323 | (define_insn "pool_section_end" |
| 7324 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
| 7325 | "" | |
| b2ccb744 | 7326 | ".previous" |
| 9bb86f41 UW |
7327 | [(set_attr "op_type" "NN") |
| 7328 | (set_attr "length" "0")]) | |
| b2ccb744 | 7329 | |
| 5af2f3d3 | 7330 | (define_insn "main_base_31_small" |
| 9e8327e3 UW |
7331 | [(set (match_operand 0 "register_operand" "=a") |
| 7332 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
| 7333 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
| 5af2f3d3 UW |
7334 | "basr\t%0,0" |
| 7335 | [(set_attr "op_type" "RR") | |
| 7336 | (set_attr "type" "la")]) | |
| 7337 | ||
| 7338 | (define_insn "main_base_31_large" | |
| 9e8327e3 UW |
7339 | [(set (match_operand 0 "register_operand" "=a") |
| 7340 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
| 5af2f3d3 | 7341 | (set (pc) (label_ref (match_operand 2 "" "")))] |
| 9e8327e3 | 7342 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
| 5af2f3d3 UW |
7343 | "bras\t%0,%2" |
| 7344 | [(set_attr "op_type" "RI")]) | |
| 7345 | ||
| 7346 | (define_insn "main_base_64" | |
| 9e8327e3 UW |
7347 | [(set (match_operand 0 "register_operand" "=a") |
| 7348 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
| 7349 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
| 5af2f3d3 UW |
7350 | "larl\t%0,%1" |
| 7351 | [(set_attr "op_type" "RIL") | |
| 7352 | (set_attr "type" "larl")]) | |
| 7353 | ||
| 7354 | (define_insn "main_pool" | |
| 585539a1 UW |
7355 | [(set (match_operand 0 "register_operand" "=a") |
| 7356 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
| 7357 | "GET_MODE (operands[0]) == Pmode" | |
| 5af2f3d3 | 7358 | "* abort ();" |
| ea77e738 UW |
7359 | [(set_attr "op_type" "NN") |
| 7360 | (set (attr "type") | |
| 7361 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) | |
| 7362 | (const_string "larl") (const_string "la")))]) | |
| 5af2f3d3 | 7363 | |
| aee4e0db | 7364 | (define_insn "reload_base_31" |
| 9e8327e3 UW |
7365 | [(set (match_operand 0 "register_operand" "=a") |
| 7366 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
| 7367 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
| d40c829f | 7368 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
| 9db1d521 | 7369 | [(set_attr "op_type" "NN") |
| b2ccb744 UW |
7370 | (set_attr "type" "la") |
| 7371 | (set_attr "length" "6")]) | |
| 7372 | ||
| aee4e0db | 7373 | (define_insn "reload_base_64" |
| 9e8327e3 UW |
7374 | [(set (match_operand 0 "register_operand" "=a") |
| 7375 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
| 7376 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
| d40c829f | 7377 | "larl\t%0,%1" |
| aee4e0db | 7378 | [(set_attr "op_type" "RIL") |
| 077dab3b | 7379 | (set_attr "type" "larl")]) |
| aee4e0db | 7380 | |
| aee4e0db | 7381 | (define_insn "pool" |
| fd7643fb | 7382 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
| aee4e0db UW |
7383 | "" |
| 7384 | "* abort ();" | |
| 7385 | [(set_attr "op_type" "NN") | |
| 7386 | (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
| 9db1d521 | 7387 | |
| 4023fb28 UW |
7388 | ;; |
| 7389 | ;; Insns related to generating the function prologue and epilogue. | |
| 7390 | ;; | |
| 7391 | ||
| 7392 | ||
| 7393 | (define_expand "prologue" | |
| 7394 | [(use (const_int 0))] | |
| 7395 | "" | |
| 10bbf137 | 7396 | "s390_emit_prologue (); DONE;") |
| 4023fb28 | 7397 | |
| 2f7e5a0d EC |
7398 | (define_insn "prologue_tpf" |
| 7399 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE) | |
| 7400 | (clobber (reg:DI 1))] | |
| 3839e36a | 7401 | "TARGET_TPF_PROFILING" |
| 2f7e5a0d EC |
7402 | "bas\t%%r1,4064" |
| 7403 | [(set_attr "type" "jsr") | |
| 7404 | (set_attr "op_type" "RX")]) | |
| 7405 | ||
| 4023fb28 UW |
7406 | (define_expand "epilogue" |
| 7407 | [(use (const_int 1))] | |
| 7408 | "" | |
| ed9676cf AK |
7409 | "s390_emit_epilogue (false); DONE;") |
| 7410 | ||
| 2f7e5a0d EC |
7411 | (define_insn "epilogue_tpf" |
| 7412 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE) | |
| 7413 | (clobber (reg:DI 1))] | |
| 3839e36a | 7414 | "TARGET_TPF_PROFILING" |
| 2f7e5a0d EC |
7415 | "bas\t%%r1,4070" |
| 7416 | [(set_attr "type" "jsr") | |
| 7417 | (set_attr "op_type" "RX")]) | |
| 7418 | ||
| 7419 | ||
| ed9676cf AK |
7420 | (define_expand "sibcall_epilogue" |
| 7421 | [(use (const_int 0))] | |
| 7422 | "" | |
| 7423 | "s390_emit_epilogue (true); DONE;") | |
| 4023fb28 | 7424 | |
| 9e8327e3 | 7425 | (define_insn "*return" |
| 4023fb28 | 7426 | [(return) |
| 9e8327e3 UW |
7427 | (use (match_operand 0 "register_operand" "a"))] |
| 7428 | "GET_MODE (operands[0]) == Pmode" | |
| d40c829f | 7429 | "br\t%0" |
| 4023fb28 | 7430 | [(set_attr "op_type" "RR") |
| c7453384 | 7431 | (set_attr "type" "jsr") |
| 077dab3b | 7432 | (set_attr "atype" "agen")]) |
| 4023fb28 | 7433 | |
| 4023fb28 | 7434 | |
| c7453384 | 7435 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
| 839a4992 | 7436 | ;; pointer. This is used for compatibility. |
| c7453384 EC |
7437 | |
| 7438 | (define_expand "ptr_extend" | |
| 7439 | [(set (match_operand:DI 0 "register_operand" "=r") | |
| 7440 | (match_operand:SI 1 "register_operand" "r"))] | |
| 9e8327e3 | 7441 | "TARGET_64BIT" |
| c7453384 | 7442 | { |
| c7453384 EC |
7443 | emit_insn (gen_anddi3 (operands[0], |
| 7444 | gen_lowpart (DImode, operands[1]), | |
| 7445 | GEN_INT (0x7fffffff))); | |
| c7453384 | 7446 | DONE; |
| 10bbf137 | 7447 | }) |
| 4798630c D |
7448 | |
| 7449 | ;; Instruction definition to expand eh_return macro to support | |
| 7450 | ;; swapping in special linkage return addresses. | |
| 7451 | ||
| 7452 | (define_expand "eh_return" | |
| 7453 | [(use (match_operand 0 "register_operand" ""))] | |
| 7454 | "TARGET_TPF" | |
| 7455 | { | |
| 7456 | s390_emit_tpf_eh_return (operands[0]); | |
| 7457 | DONE; | |
| 7458 | }) | |
| 7459 |