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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
818ab71a | 2 | ;; Copyright (C) 1999-2016 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
77 | UNSPEC_LTREL_OFFSET |
78 | UNSPEC_LTREL_BASE | |
79 | UNSPEC_POOL_OFFSET | |
80 | UNSPEC_GOTENT | |
81 | UNSPEC_GOT | |
82 | UNSPEC_GOTOFF | |
83 | UNSPEC_PLT | |
84 | UNSPEC_PLTOFF | |
fd7643fb UW |
85 | |
86 | ; Literal pool | |
30a49b23 AK |
87 | UNSPEC_RELOAD_BASE |
88 | UNSPEC_MAIN_BASE | |
89 | UNSPEC_LTREF | |
90 | UNSPEC_INSN | |
91 | UNSPEC_EXECUTE | |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
3af82a61 AK |
159 | UNSPEC_VEC_MERGEH |
160 | UNSPEC_VEC_MERGEL | |
161 | UNSPEC_VEC_PACK | |
162 | UNSPEC_VEC_PACK_SATURATE | |
163 | UNSPEC_VEC_PACK_SATURATE_CC | |
164 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
165 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
168 | UNSPEC_VEC_PERM | |
169 | UNSPEC_VEC_PERMI | |
170 | UNSPEC_VEC_EXTEND | |
171 | UNSPEC_VEC_STORE_LEN | |
172 | UNSPEC_VEC_UNPACKH | |
173 | UNSPEC_VEC_UNPACKH_L | |
174 | UNSPEC_VEC_UNPACKL | |
175 | UNSPEC_VEC_UNPACKL_L | |
176 | UNSPEC_VEC_ADDC | |
177 | UNSPEC_VEC_ADDC_U128 | |
178 | UNSPEC_VEC_ADDE_U128 | |
179 | UNSPEC_VEC_ADDEC_U128 | |
180 | UNSPEC_VEC_AVG | |
181 | UNSPEC_VEC_AVGU | |
182 | UNSPEC_VEC_CHECKSUM | |
183 | UNSPEC_VEC_GFMSUM | |
184 | UNSPEC_VEC_GFMSUM_128 | |
185 | UNSPEC_VEC_GFMSUM_ACCUM | |
186 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
187 | UNSPEC_VEC_SET | |
188 | ||
189 | UNSPEC_VEC_VSUMG | |
190 | UNSPEC_VEC_VSUMQ | |
191 | UNSPEC_VEC_VSUM | |
192 | UNSPEC_VEC_RL_MASK | |
193 | UNSPEC_VEC_SLL | |
194 | UNSPEC_VEC_SLB | |
195 | UNSPEC_VEC_SLDB | |
196 | UNSPEC_VEC_SRAL | |
197 | UNSPEC_VEC_SRAB | |
198 | UNSPEC_VEC_SRL | |
199 | UNSPEC_VEC_SRLB | |
200 | ||
201 | UNSPEC_VEC_SUB_U128 | |
202 | UNSPEC_VEC_SUBC | |
203 | UNSPEC_VEC_SUBC_U128 | |
204 | UNSPEC_VEC_SUBE_U128 | |
205 | UNSPEC_VEC_SUBEC_U128 | |
206 | ||
207 | UNSPEC_VEC_TEST_MASK | |
208 | ||
209 | UNSPEC_VEC_VFAE | |
210 | UNSPEC_VEC_VFAECC | |
211 | ||
212 | UNSPEC_VEC_VFEE | |
213 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
214 | UNSPEC_VEC_VFENE |
215 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
216 | |
217 | UNSPEC_VEC_VISTR | |
218 | UNSPEC_VEC_VISTRCC | |
219 | ||
220 | UNSPEC_VEC_VSTRC | |
221 | UNSPEC_VEC_VSTRCCC | |
222 | ||
223 | UNSPEC_VEC_VCDGB | |
224 | UNSPEC_VEC_VCDLGB | |
225 | ||
226 | UNSPEC_VEC_VCGDB | |
227 | UNSPEC_VEC_VCLGDB | |
228 | ||
229 | UNSPEC_VEC_VFIDB | |
230 | ||
231 | UNSPEC_VEC_VLDEB | |
232 | UNSPEC_VEC_VLEDB | |
233 | ||
234 | UNSPEC_VEC_VFTCIDB | |
235 | UNSPEC_VEC_VFTCIDBCC | |
085261c8 | 236 | ]) |
fd3cd001 UW |
237 | |
238 | ;; | |
239 | ;; UNSPEC_VOLATILE usage | |
240 | ;; | |
241 | ||
30a49b23 AK |
242 | (define_c_enum "unspecv" [ |
243 | ; Blockage | |
244 | UNSPECV_BLOCKAGE | |
10bbf137 | 245 | |
2f7e5a0d | 246 | ; TPF Support |
30a49b23 AK |
247 | UNSPECV_TPF_PROLOGUE |
248 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 249 | |
10bbf137 | 250 | ; Literal pool |
30a49b23 AK |
251 | UNSPECV_POOL |
252 | UNSPECV_POOL_SECTION | |
253 | UNSPECV_POOL_ALIGN | |
254 | UNSPECV_POOL_ENTRY | |
255 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
256 | |
257 | ; TLS support | |
30a49b23 | 258 | UNSPECV_SET_TP |
e0374221 AS |
259 | |
260 | ; Atomic Support | |
30a49b23 AK |
261 | UNSPECV_CAS |
262 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 263 | |
f8af0e30 DV |
264 | ; Hotpatching (unremovable NOPs) |
265 | UNSPECV_NOP_2_BYTE | |
266 | UNSPECV_NOP_4_BYTE | |
267 | UNSPECV_NOP_6_BYTE | |
268 | ||
5a3fe9b6 AK |
269 | ; Transactional Execution support |
270 | UNSPECV_TBEGIN | |
2561451d | 271 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
272 | UNSPECV_TBEGINC |
273 | UNSPECV_TEND | |
274 | UNSPECV_TABORT | |
275 | UNSPECV_ETND | |
276 | UNSPECV_NTSTG | |
277 | UNSPECV_PPA | |
004f64e1 AK |
278 | |
279 | ; Set and get floating point control register | |
280 | UNSPECV_SFPC | |
281 | UNSPECV_EFPC | |
4cb4721f MK |
282 | |
283 | ; Split stack support | |
284 | UNSPECV_SPLIT_STACK_CALL | |
285 | UNSPECV_SPLIT_STACK_DATA | |
fd3cd001 UW |
286 | ]) |
287 | ||
ae156f85 AS |
288 | ;; |
289 | ;; Registers | |
290 | ;; | |
291 | ||
35dd9a0e AK |
292 | ; Registers with special meaning |
293 | ||
ae156f85 AS |
294 | (define_constants |
295 | [ | |
296 | ; Sibling call register. | |
297 | (SIBCALL_REGNUM 1) | |
298 | ; Literal pool base register. | |
299 | (BASE_REGNUM 13) | |
300 | ; Return address register. | |
301 | (RETURN_REGNUM 14) | |
82c6f58a AK |
302 | ; Stack pointer register. |
303 | (STACK_REGNUM 15) | |
ae156f85 AS |
304 | ; Condition code register. |
305 | (CC_REGNUM 33) | |
f4aa3848 | 306 | ; Thread local storage pointer register. |
ae156f85 AS |
307 | (TP_REGNUM 36) |
308 | ]) | |
309 | ||
35dd9a0e AK |
310 | ; Hardware register names |
311 | ||
312 | (define_constants | |
313 | [ | |
314 | ; General purpose registers | |
315 | (GPR0_REGNUM 0) | |
af344a30 | 316 | (GPR1_REGNUM 1) |
82379bdf AK |
317 | (GPR2_REGNUM 2) |
318 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
319 | ; Floating point registers. |
320 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
321 | (FPR1_REGNUM 20) |
322 | (FPR2_REGNUM 17) | |
323 | (FPR3_REGNUM 21) | |
324 | (FPR4_REGNUM 18) | |
325 | (FPR5_REGNUM 22) | |
326 | (FPR6_REGNUM 19) | |
327 | (FPR7_REGNUM 23) | |
328 | (FPR8_REGNUM 24) | |
329 | (FPR9_REGNUM 28) | |
330 | (FPR10_REGNUM 25) | |
331 | (FPR11_REGNUM 29) | |
332 | (FPR12_REGNUM 26) | |
333 | (FPR13_REGNUM 30) | |
334 | (FPR14_REGNUM 27) | |
335 | (FPR15_REGNUM 31) | |
085261c8 AK |
336 | (VR0_REGNUM 16) |
337 | (VR16_REGNUM 38) | |
338 | (VR23_REGNUM 45) | |
339 | (VR24_REGNUM 46) | |
340 | (VR31_REGNUM 53) | |
35dd9a0e AK |
341 | ]) |
342 | ||
ae8e301e AK |
343 | ; Rounding modes for binary floating point numbers |
344 | (define_constants | |
345 | [(BFP_RND_CURRENT 0) | |
346 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
347 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
348 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
349 | (BFP_RND_TOWARD_0 5) | |
350 | (BFP_RND_TOWARD_INF 6) | |
351 | (BFP_RND_TOWARD_MINF 7)]) | |
352 | ||
353 | ; Rounding modes for decimal floating point numbers | |
354 | ; 1-7 were introduced with the floating point extension facility | |
355 | ; available with z196 | |
356 | ; With these rounding modes (1-7) a quantum exception might occur | |
357 | ; which is suppressed for the other modes. | |
358 | (define_constants | |
359 | [(DFP_RND_CURRENT 0) | |
360 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
361 | (DFP_RND_CURRENT_QUANTEXC 2) | |
362 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
363 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
364 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
365 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
366 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
367 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
368 | (DFP_RND_TOWARD_0 9) | |
369 | (DFP_RND_TOWARD_INF 10) | |
370 | (DFP_RND_TOWARD_MINF 11) | |
371 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
372 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
373 | (DFP_RND_AWAY_FROM_0 14) | |
374 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
375 | ||
35dd9a0e AK |
376 | ;; |
377 | ;; PFPO GPR0 argument format | |
378 | ;; | |
379 | ||
380 | (define_constants | |
381 | [ | |
382 | ; PFPO operation type | |
383 | (PFPO_CONVERT 0x1000000) | |
384 | ; PFPO operand types | |
385 | (PFPO_OP_TYPE_SF 0x5) | |
386 | (PFPO_OP_TYPE_DF 0x6) | |
387 | (PFPO_OP_TYPE_TF 0x7) | |
388 | (PFPO_OP_TYPE_SD 0x8) | |
389 | (PFPO_OP_TYPE_DD 0x9) | |
390 | (PFPO_OP_TYPE_TD 0xa) | |
391 | ; Bitposition of operand types | |
392 | (PFPO_OP0_TYPE_SHIFT 16) | |
393 | (PFPO_OP1_TYPE_SHIFT 8) | |
394 | ]) | |
395 | ||
5a3fe9b6 AK |
396 | ; Immediate operands for tbegin and tbeginc |
397 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
398 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 399 | |
29a74354 UW |
400 | ;; Instruction operand type as used in the Principles of Operation. |
401 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 402 | |
29a74354 | 403 | (define_attr "op_type" |
62d3f261 | 404 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" |
b628bd8e | 405 | (const_string "NN")) |
9db1d521 | 406 | |
29a74354 | 407 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 408 | |
077dab3b | 409 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 410 | cs,vs,store,sem,idiv, |
ed0e512a | 411 | imulhi,imulsi,imuldi, |
2cdece44 | 412 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
413 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
414 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 415 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 416 | fmadddf,fmaddsf, |
9381e3f1 WG |
417 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
418 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
419 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
420 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
421 | ftoidfp, other" | |
29a74354 UW |
422 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
423 | (eq_attr "op_type" "SS") (const_string "cs")] | |
424 | (const_string "integer"))) | |
9db1d521 | 425 | |
29a74354 UW |
426 | ;; Another attribute used for scheduling purposes: |
427 | ;; agen: Instruction uses the address generation unit | |
428 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
429 | |
430 | (define_attr "atype" "agen,reg" | |
62d3f261 | 431 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
432 | (const_string "reg") |
433 | (const_string "agen"))) | |
9db1d521 | 434 | |
9381e3f1 WG |
435 | ;; Properties concerning Z10 execution grouping and value forwarding. |
436 | ;; z10_super: instruction is superscalar. | |
437 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
438 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
439 | ;; target register. It can forward this value to a second instruction that reads | |
440 | ;; the same register if that second instruction is issued in the same group. | |
441 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
442 | ;; instruction in the S pipe writes to the register, then the T instruction | |
443 | ;; can immediately read the new value. | |
444 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
445 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
446 | ;; |
447 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
448 | ||
449 | ||
450 | (define_attr "z10prop" "none, | |
451 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
452 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
453 | z10_rec, | |
454 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 455 | z10_c" |
9381e3f1 WG |
456 | (const_string "none")) |
457 | ||
65b1d8ea AK |
458 | ;; Properties concerning Z196 decoding |
459 | ;; z196_alone: must group alone | |
460 | ;; z196_end: ends a group | |
461 | ;; z196_cracked: instruction is cracked or expanded | |
462 | (define_attr "z196prop" "none, | |
463 | z196_alone, z196_ends, | |
464 | z196_cracked" | |
465 | (const_string "none")) | |
9381e3f1 | 466 | |
a9cc3f58 | 467 | (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 468 | |
9db1d521 HP |
469 | ;; Length in bytes. |
470 | ||
471 | (define_attr "length" "" | |
62d3f261 AK |
472 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
473 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 474 | (const_int 6))) |
9db1d521 | 475 | |
29a74354 UW |
476 | |
477 | ;; Processor type. This attribute must exactly match the processor_type | |
478 | ;; enumeration in s390.h. The current machine description does not | |
479 | ;; distinguish between g5 and g6, but there are differences between the two | |
480 | ;; CPUs could in theory be modeled. | |
481 | ||
55ac540c | 482 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13" |
90c6fd8a | 483 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 484 | |
b5e0425c | 485 | (define_attr "cpu_facility" |
55ac540c | 486 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec" |
3af8e996 AK |
487 | (const_string "standard")) |
488 | ||
489 | (define_attr "enabled" "" | |
490 | (cond [(eq_attr "cpu_facility" "standard") | |
491 | (const_int 1) | |
492 | ||
493 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 494 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
495 | (const_int 1) |
496 | ||
497 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 498 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
499 | (const_int 1) |
500 | ||
501 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 502 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
503 | (const_int 1) |
504 | ||
505 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 506 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
507 | (const_int 1) |
508 | ||
509 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 510 | (match_test "TARGET_DFP")) |
93538e8e AK |
511 | (const_int 1) |
512 | ||
b5e0425c AK |
513 | (and (eq_attr "cpu_facility" "cpu_zarch") |
514 | (match_test "TARGET_CPU_ZARCH")) | |
515 | (const_int 1) | |
516 | ||
93538e8e | 517 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 518 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
519 | (const_int 1) |
520 | ||
521 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 522 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
523 | (const_int 1) |
524 | ||
525 | (and (eq_attr "cpu_facility" "zEC12") | |
526 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
527 | (const_int 1) |
528 | ||
529 | (and (eq_attr "cpu_facility" "vec") | |
530 | (match_test "TARGET_VX")) | |
3af8e996 AK |
531 | (const_int 1)] |
532 | (const_int 0))) | |
533 | ||
29a74354 UW |
534 | ;; Pipeline description for z900. For lack of anything better, |
535 | ;; this description is also used for the g5 and g6. | |
536 | (include "2064.md") | |
537 | ||
3443392a | 538 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
539 | (include "2084.md") |
540 | ||
9381e3f1 WG |
541 | ;; Pipeline description for z10 |
542 | (include "2097.md") | |
543 | ||
65b1d8ea AK |
544 | ;; Pipeline description for z196 |
545 | (include "2817.md") | |
546 | ||
22ac2c2f AK |
547 | ;; Pipeline description for zEC12 |
548 | (include "2827.md") | |
549 | ||
23902021 AK |
550 | ;; Pipeline description for z13 |
551 | (include "2964.md") | |
552 | ||
0bfc3f69 AS |
553 | ;; Predicates |
554 | (include "predicates.md") | |
555 | ||
cd8dc1f9 WG |
556 | ;; Constraint definitions |
557 | (include "constraints.md") | |
558 | ||
a8ba31f2 EC |
559 | ;; Other includes |
560 | (include "tpf.md") | |
f52c81dd | 561 | |
3abcb3a7 | 562 | ;; Iterators |
f52c81dd | 563 | |
085261c8 AK |
564 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
565 | ||
3abcb3a7 | 566 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 567 | ;; same template. |
f4aa3848 | 568 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 569 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
570 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
571 | (define_mode_iterator BFP [TF DF SF]) | |
572 | (define_mode_iterator DFP [TD DD]) | |
573 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
574 | (define_mode_iterator DSF [DF SF]) | |
575 | (define_mode_iterator SD_SF [SF SD]) | |
576 | (define_mode_iterator DD_DF [DF DD]) | |
577 | (define_mode_iterator TD_TF [TF TD]) | |
578 | ||
3abcb3a7 | 579 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 580 | ;; from the same template. |
9602b6a1 | 581 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 582 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 583 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 584 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 585 | |
3abcb3a7 | 586 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 587 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 588 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 589 | |
78ce265b RH |
590 | ;; These macros refer to the actual word_mode of the configuration. |
591 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
592 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
593 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
594 | ||
6e0d70c9 AK |
595 | ;; Used by the umul pattern to express modes having half the size. |
596 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
597 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
598 | ||
3abcb3a7 | 599 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 600 | ;; the same template. |
3abcb3a7 | 601 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 602 | |
3abcb3a7 | 603 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 604 | ;; same template. |
9602b6a1 | 605 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 606 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
342cf42b | 607 | |
3abcb3a7 | 608 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 609 | ;; the same template. |
3abcb3a7 | 610 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 611 | |
d12a76f3 | 612 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
613 | (define_code_iterator IXOR [ior xor]) |
614 | ||
d12a76f3 AK |
615 | ;; This iterator is used to expand the patterns for the nearest |
616 | ;; integer functions. | |
617 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
618 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
619 | UNSPEC_FPINT_NEARBYINT]) | |
620 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
621 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
622 | (UNSPEC_FPINT_ROUND "round") | |
623 | (UNSPEC_FPINT_CEIL "ceil") | |
624 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
625 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
626 | (UNSPEC_FPINT_BTRUNC "5") | |
627 | (UNSPEC_FPINT_ROUND "1") | |
628 | (UNSPEC_FPINT_CEIL "6") | |
629 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
630 | ||
3abcb3a7 HPN |
631 | ;; This iterator and attribute allow to combine most atomic operations. |
632 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 633 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 634 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 635 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 636 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 637 | |
f4aa3848 | 638 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
639 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
640 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 641 | |
f4aa3848 AK |
642 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
643 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
644 | ;; SDmode. |
645 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 646 | |
609e7e80 | 647 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
648 | ;; Likewise for "<RXe>". |
649 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
650 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
651 | ||
609e7e80 | 652 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 653 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
654 | ;; dfp variants in a single insn definition. |
655 | ||
62d3f261 AK |
656 | ;; These mode attributes are supposed to be used in the `enabled' insn |
657 | ;; attribute to disable certain alternatives for certain modes. | |
658 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
659 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
660 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
661 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
662 | (TD "0") (DD "0") (DD "0") | |
663 | (TI "0") (DI "*") (SI "0")]) | |
f5905b37 | 664 | |
85dae55a AK |
665 | ;; This attribute is used in the operand constraint list |
666 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
667 | ;; TFmode values are represented by a fp register pair. Since the | |
668 | ;; sign bit instructions only handle single source and target fp registers | |
669 | ;; these instructions can only be used for TFmode values if the source and | |
670 | ;; target operand uses the same fp register. | |
671 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
672 | ||
3abcb3a7 | 673 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
674 | ;; within instruction mnemonics. |
675 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
676 | ||
0387c142 WG |
677 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
678 | ;; modes and to an empty string for bfp modes. | |
679 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
680 | ||
1b48c8cc AS |
681 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
682 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
683 | ;; version only operates on one register. | |
684 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
685 | ||
686 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
687 | ;; version only operates on one register. The DImode version needs an additional | |
688 | ;; register for the assembler output. | |
689 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
690 | |
691 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
692 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
693 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
694 | ||
695 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 696 | ;; pattern itself and the corresponding function calls. |
f337b930 | 697 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
698 | |
699 | ;; This attribute handles differences in the instruction 'type' and will result | |
700 | ;; in "RRE" for DImode and "RR" for SImode. | |
701 | (define_mode_attr E [(DI "E") (SI "")]) | |
702 | ||
3298c037 AK |
703 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
704 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
705 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
706 | ||
8006eaa6 AS |
707 | ;; This attribute handles differences in the instruction 'type' and will result |
708 | ;; in "RSE" for TImode and "RS" for DImode. | |
709 | (define_mode_attr TE [(TI "E") (DI "")]) | |
710 | ||
9a91a21f AS |
711 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
712 | ;; and "lcr" in SImode. | |
713 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 714 | |
3298c037 AK |
715 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
716 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
717 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
718 | ;; variant for long displacements. | |
719 | (define_mode_attr y [(DI "g") (SI "y")]) | |
720 | ||
9602b6a1 | 721 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
722 | ;; and "cds" in DImode. |
723 | (define_mode_attr tg [(TI "g") (DI "")]) | |
724 | ||
78ce265b RH |
725 | ;; In TDI templates, a string like "c<d>sg". |
726 | (define_mode_attr td [(TI "d") (DI "")]) | |
727 | ||
2f8f8434 AS |
728 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
729 | ;; and "cfdbr" in SImode. | |
730 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
731 | ||
65b1d8ea AK |
732 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
733 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
734 | ;; 3 operands shift instructions into the existing patterns. | |
735 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
736 | ||
f52c81dd AS |
737 | ;; ICM mask required to load MODE value into the lowest subreg |
738 | ;; of a SImode register. | |
739 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
740 | ||
f6ee577c AS |
741 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
742 | ;; HImode and "llgc" in QImode. | |
743 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
744 | ||
a1aed706 AS |
745 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
746 | ;; in SImode. | |
747 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
748 | ||
609e7e80 AK |
749 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
750 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
751 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
752 | ||
f52c81dd AS |
753 | ;; Maximum unsigned integer that fits in MODE. |
754 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
755 | ||
75ca1b39 RH |
756 | ;; Start and end field computations for RISBG et al. |
757 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
758 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
759 | ||
2542ef05 RH |
760 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
761 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
762 | ||
da0dcab1 DV |
763 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
764 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
765 | ||
177bc204 RS |
766 | ;; Allow return and simple_return to be defined from a single template. |
767 | (define_code_iterator ANY_RETURN [return simple_return]) | |
768 | ||
6e5b5de8 AK |
769 | |
770 | ||
771 | ; Condition code modes generated by vector fp comparisons. These will | |
772 | ; be used also in single element mode. | |
773 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
774 | ; Used with VFCMP to expand part of the mnemonic | |
775 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
776 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
3af82a61 | 777 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 778 | |
191eb16d AK |
779 | ;; Subst pattern definitions |
780 | (include "subst.md") | |
6e5b5de8 | 781 | |
085261c8 AK |
782 | (include "vector.md") |
783 | ||
9db1d521 HP |
784 | ;; |
785 | ;;- Compare instructions. | |
786 | ;; | |
787 | ||
07893d4f | 788 | ; Test-under-Mask instructions |
9db1d521 | 789 | |
07893d4f | 790 | (define_insn "*tmqi_mem" |
ae156f85 | 791 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
792 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
793 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
794 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 795 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 796 | "@ |
fc0ea003 UW |
797 | tm\t%S0,%b1 |
798 | tmy\t%S0,%b1" | |
9381e3f1 WG |
799 | [(set_attr "op_type" "SI,SIY") |
800 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 801 | |
05b9aaaa | 802 | (define_insn "*tmdi_reg" |
ae156f85 | 803 | [(set (reg CC_REGNUM) |
f19a9af7 | 804 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 805 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
806 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
807 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 808 | "TARGET_ZARCH |
3ed99cc9 | 809 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
810 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
811 | "@ | |
812 | tmhh\t%0,%i1 | |
813 | tmhl\t%0,%i1 | |
814 | tmlh\t%0,%i1 | |
815 | tmll\t%0,%i1" | |
9381e3f1 WG |
816 | [(set_attr "op_type" "RI") |
817 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
818 | |
819 | (define_insn "*tmsi_reg" | |
ae156f85 | 820 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
821 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
822 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
823 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 824 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
825 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
826 | "@ | |
827 | tmh\t%0,%i1 | |
828 | tml\t%0,%i1" | |
729e750f WG |
829 | [(set_attr "op_type" "RI") |
830 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 831 | |
f52c81dd | 832 | (define_insn "*tm<mode>_full" |
ae156f85 | 833 | [(set (reg CC_REGNUM) |
f52c81dd AS |
834 | (compare (match_operand:HQI 0 "register_operand" "d") |
835 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 836 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 837 | "tml\t%0,<max_uint>" |
729e750f WG |
838 | [(set_attr "op_type" "RI") |
839 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 840 | |
07893d4f | 841 | |
08a5aaa2 | 842 | ; |
07893d4f | 843 | ; Load-and-Test instructions |
08a5aaa2 AS |
844 | ; |
845 | ||
c0220ea4 | 846 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
847 | |
848 | (define_insn "*tstdi_sign" | |
ae156f85 | 849 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
850 | (compare |
851 | (ashiftrt:DI | |
852 | (ashift:DI | |
853 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
854 | (const_int 32)) (const_int 32)) | |
855 | (match_operand:DI 1 "const0_operand" ""))) | |
856 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 857 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 858 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
859 | "ltgfr\t%2,%0 |
860 | ltgf\t%2,%0" | |
861 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
862 | (set_attr "cpu_facility" "*,z10") |
863 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 864 | |
43a09b63 | 865 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 866 | (define_insn "*tst<mode>_extimm" |
ec24698e | 867 | [(set (reg CC_REGNUM) |
fb492564 | 868 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
869 | (match_operand:GPR 1 "const0_operand" ""))) |
870 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 871 | (match_dup 0))] |
08a5aaa2 | 872 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 873 | "@ |
08a5aaa2 AS |
874 | lt<g>r\t%2,%0 |
875 | lt<g>\t%2,%0" | |
9381e3f1 | 876 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 877 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 878 | |
43a09b63 | 879 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 880 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 881 | [(set (reg CC_REGNUM) |
fb492564 | 882 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
883 | (match_operand:GPR 1 "const0_operand" ""))) |
884 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
885 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 886 | "@ |
08a5aaa2 AS |
887 | lt<g>r\t%0,%0 |
888 | lt<g>\t%2,%0" | |
9381e3f1 | 889 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 890 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 891 | |
07893d4f | 892 | (define_insn "*tstdi" |
ae156f85 | 893 | [(set (reg CC_REGNUM) |
07893d4f UW |
894 | (compare (match_operand:DI 0 "register_operand" "d") |
895 | (match_operand:DI 1 "const0_operand" ""))) | |
896 | (set (match_operand:DI 2 "register_operand" "=d") | |
897 | (match_dup 0))] | |
9602b6a1 | 898 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 899 | "ltgr\t%2,%0" |
9381e3f1 WG |
900 | [(set_attr "op_type" "RRE") |
901 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 902 | |
07893d4f | 903 | (define_insn "*tstsi" |
ae156f85 | 904 | [(set (reg CC_REGNUM) |
d3632d41 | 905 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 906 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 907 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 908 | (match_dup 0))] |
ec24698e | 909 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 910 | "@ |
d40c829f | 911 | ltr\t%2,%0 |
fc0ea003 UW |
912 | icm\t%2,15,%S0 |
913 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
914 | [(set_attr "op_type" "RR,RS,RSY") |
915 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 916 | |
07893d4f | 917 | (define_insn "*tstsi_cconly" |
ae156f85 | 918 | [(set (reg CC_REGNUM) |
d3632d41 | 919 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 920 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 921 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
922 | "s390_match_ccmode(insn, CCSmode)" |
923 | "@ | |
d40c829f | 924 | ltr\t%0,%0 |
fc0ea003 UW |
925 | icm\t%2,15,%S0 |
926 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
927 | [(set_attr "op_type" "RR,RS,RSY") |
928 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 929 | |
08a5aaa2 AS |
930 | (define_insn "*tstdi_cconly_31" |
931 | [(set (reg CC_REGNUM) | |
932 | (compare (match_operand:DI 0 "register_operand" "d") | |
933 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 934 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
935 | "srda\t%0,0" |
936 | [(set_attr "op_type" "RS") | |
937 | (set_attr "atype" "reg")]) | |
938 | ||
43a09b63 | 939 | ; ltr, ltgr |
08a5aaa2 | 940 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 941 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
942 | (compare (match_operand:GPR 0 "register_operand" "d") |
943 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 944 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 945 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
946 | [(set_attr "op_type" "RR<E>") |
947 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 948 | |
c0220ea4 | 949 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 950 | |
f52c81dd | 951 | (define_insn "*tst<mode>CCT" |
ae156f85 | 952 | [(set (reg CC_REGNUM) |
f52c81dd AS |
953 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
954 | (match_operand:HQI 1 "const0_operand" ""))) | |
955 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
956 | (match_dup 0))] |
957 | "s390_match_ccmode(insn, CCTmode)" | |
958 | "@ | |
f52c81dd AS |
959 | icm\t%2,<icm_lo>,%S0 |
960 | icmy\t%2,<icm_lo>,%S0 | |
961 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
962 | [(set_attr "op_type" "RS,RSY,RI") |
963 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
964 | |
965 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 966 | [(set (reg CC_REGNUM) |
d3632d41 | 967 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 968 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 969 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
970 | "s390_match_ccmode(insn, CCTmode)" |
971 | "@ | |
fc0ea003 UW |
972 | icm\t%2,3,%S0 |
973 | icmy\t%2,3,%S0 | |
d40c829f | 974 | tml\t%0,65535" |
9381e3f1 WG |
975 | [(set_attr "op_type" "RS,RSY,RI") |
976 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 977 | |
3af97654 | 978 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 979 | [(set (reg CC_REGNUM) |
d3632d41 | 980 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
981 | (match_operand:QI 1 "const0_operand" "")))] |
982 | "s390_match_ccmode(insn, CCTmode)" | |
983 | "@ | |
fc0ea003 UW |
984 | cli\t%S0,0 |
985 | cliy\t%S0,0 | |
d40c829f | 986 | tml\t%0,255" |
9381e3f1 | 987 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 988 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 989 | |
f52c81dd | 990 | (define_insn "*tst<mode>" |
ae156f85 | 991 | [(set (reg CC_REGNUM) |
f52c81dd AS |
992 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
993 | (match_operand:HQI 1 "const0_operand" ""))) | |
994 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
995 | (match_dup 0))] |
996 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 997 | "@ |
f52c81dd AS |
998 | icm\t%2,<icm_lo>,%S0 |
999 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
1000 | [(set_attr "op_type" "RS,RSY") |
1001 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 1002 | |
f52c81dd | 1003 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1004 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1005 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1006 | (match_operand:HQI 1 "const0_operand" ""))) | |
1007 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1008 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1009 | "@ |
f52c81dd AS |
1010 | icm\t%2,<icm_lo>,%S0 |
1011 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
1012 | [(set_attr "op_type" "RS,RSY") |
1013 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 1014 | |
9db1d521 | 1015 | |
575f7c2b UW |
1016 | ; Compare (equality) instructions |
1017 | ||
1018 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1019 | [(set (reg CC_REGNUM) |
ec24698e | 1020 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 1021 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 1022 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1023 | "@ |
1024 | cgr\t%0,%1 | |
f4f41b4e | 1025 | cghi\t%0,%h1 |
ec24698e | 1026 | cgfi\t%0,%1 |
575f7c2b | 1027 | cg\t%0,%1 |
19b63d8e | 1028 | #" |
9381e3f1 WG |
1029 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1030 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1031 | |
1032 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1033 | [(set (reg CC_REGNUM) |
ec24698e UW |
1034 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1035 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1036 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1037 | "@ |
1038 | cr\t%0,%1 | |
f4f41b4e | 1039 | chi\t%0,%h1 |
ec24698e | 1040 | cfi\t%0,%1 |
575f7c2b UW |
1041 | c\t%0,%1 |
1042 | cy\t%0,%1 | |
19b63d8e | 1043 | #" |
9381e3f1 | 1044 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 1045 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1046 | |
07893d4f | 1047 | ; Compare (signed) instructions |
4023fb28 | 1048 | |
07893d4f | 1049 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1050 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1051 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
1052 | "d,RT,b")) | |
1053 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 1054 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1055 | "@ |
d40c829f | 1056 | cgfr\t%0,%1 |
963fc8d0 AK |
1057 | cgf\t%0,%1 |
1058 | cgfrl\t%0,%1" | |
1059 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1060 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1061 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1062 | |
9381e3f1 WG |
1063 | |
1064 | ||
07893d4f | 1065 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1066 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1067 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1068 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1069 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1070 | "@ |
d40c829f | 1071 | ch\t%0,%1 |
963fc8d0 AK |
1072 | chy\t%0,%1 |
1073 | chrl\t%0,%1" | |
1074 | [(set_attr "op_type" "RX,RXY,RIL") | |
1075 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
1076 | (set_attr "type" "*,*,larl") |
1077 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1078 | |
1079 | (define_insn "*cmphi_ccs_z10" | |
1080 | [(set (reg CC_REGNUM) | |
1081 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1082 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1083 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1084 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1085 | [(set_attr "op_type" "SIL") |
1086 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1087 | |
1088 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1089 | [(set (reg CC_REGNUM) | |
1090 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
1091 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
1092 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1093 | "@ | |
1094 | cgh\t%0,%1 | |
1095 | cghrl\t%0,%1" | |
1096 | [(set_attr "op_type" "RXY,RIL") | |
1097 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1098 | |
963fc8d0 | 1099 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1100 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1101 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1102 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1103 | "d,d,Q, d,d,d,d") | |
1104 | (match_operand:GPR 1 "general_operand" | |
1105 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1106 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1107 | "@ |
3298c037 AK |
1108 | c<g>r\t%0,%1 |
1109 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1110 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1111 | c<g>fi\t%0,%1 |
1112 | c<g>\t%0,%1 | |
963fc8d0 AK |
1113 | c<y>\t%0,%1 |
1114 | c<g>rl\t%0,%1" | |
1115 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
1116 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
1117 | (set_attr "type" "*,*,*,*,*,*,larl") |
1118 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1119 | |
07893d4f UW |
1120 | |
1121 | ; Compare (unsigned) instructions | |
9db1d521 | 1122 | |
963fc8d0 AK |
1123 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1124 | [(set (reg CC_REGNUM) | |
1125 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1126 | "larl_operand" "X"))) | |
1127 | (match_operand:SI 0 "register_operand" "d")))] | |
1128 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1129 | "clhrl\t%0,%1" | |
1130 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1131 | (set_attr "type" "larl") |
1132 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1133 | |
1134 | ; clhrl, clghrl | |
1135 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1136 | [(set (reg CC_REGNUM) | |
1137 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1138 | "larl_operand" "X"))) | |
1139 | (match_operand:GPR 0 "register_operand" "d")))] | |
1140 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1141 | "cl<g>hrl\t%0,%1" | |
1142 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1143 | (set_attr "type" "larl") |
1144 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1145 | |
07893d4f | 1146 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1147 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1148 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
1149 | "d,RT,b")) | |
1150 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 1151 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1152 | "@ |
d40c829f | 1153 | clgfr\t%0,%1 |
963fc8d0 AK |
1154 | clgf\t%0,%1 |
1155 | clgfrl\t%0,%1" | |
1156 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1157 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1158 | (set_attr "type" "*,*,larl") |
1159 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1160 | |
07893d4f | 1161 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1162 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1163 | (compare (match_operand:DI 0 "nonimmediate_operand" |
1164 | "d, d,d,Q, d, Q,BQ") | |
1165 | (match_operand:DI 1 "general_operand" | |
1166 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 1167 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1168 | "@ |
d40c829f | 1169 | clgr\t%0,%1 |
ec24698e | 1170 | clgfi\t%0,%1 |
963fc8d0 AK |
1171 | clgrl\t%0,%1 |
1172 | clghsi\t%0,%x1 | |
575f7c2b | 1173 | clg\t%0,%1 |
e221ef54 | 1174 | # |
19b63d8e | 1175 | #" |
963fc8d0 AK |
1176 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1177 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1178 | (set_attr "type" "*,*,larl,*,*,*,*") |
1179 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1180 | |
07893d4f | 1181 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1182 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1183 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1184 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1185 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1186 | "@ |
d40c829f | 1187 | clr\t%0,%1 |
ec24698e | 1188 | clfi\t%0,%o1 |
963fc8d0 AK |
1189 | clrl\t%0,%1 |
1190 | clfhsi\t%0,%x1 | |
d40c829f | 1191 | cl\t%0,%1 |
575f7c2b | 1192 | cly\t%0,%1 |
e221ef54 | 1193 | # |
19b63d8e | 1194 | #" |
963fc8d0 AK |
1195 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
1196 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
1197 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1198 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1199 | |
07893d4f | 1200 | (define_insn "*cmphi_ccu" |
ae156f85 | 1201 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1202 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1203 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1204 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1205 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1206 | "@ |
fc0ea003 UW |
1207 | clm\t%0,3,%S1 |
1208 | clmy\t%0,3,%S1 | |
963fc8d0 | 1209 | clhhsi\t%0,%1 |
e221ef54 | 1210 | # |
19b63d8e | 1211 | #" |
963fc8d0 | 1212 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
1213 | (set_attr "cpu_facility" "*,*,z10,*,*") |
1214 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
1215 | |
1216 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1217 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1218 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1219 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1220 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1221 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1222 | "@ |
fc0ea003 UW |
1223 | clm\t%0,1,%S1 |
1224 | clmy\t%0,1,%S1 | |
1225 | cli\t%S0,%b1 | |
1226 | cliy\t%S0,%b1 | |
e221ef54 | 1227 | # |
19b63d8e | 1228 | #" |
9381e3f1 WG |
1229 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
1230 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
1231 | |
1232 | ||
19b63d8e UW |
1233 | ; Block compare (CLC) instruction patterns. |
1234 | ||
1235 | (define_insn "*clc" | |
ae156f85 | 1236 | [(set (reg CC_REGNUM) |
d4f52f0e | 1237 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1238 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1239 | (use (match_operand 2 "const_int_operand" "n"))] | |
1240 | "s390_match_ccmode (insn, CCUmode) | |
1241 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1242 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1243 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1244 | |
1245 | (define_split | |
ae156f85 | 1246 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1247 | (compare (match_operand 0 "memory_operand" "") |
1248 | (match_operand 1 "memory_operand" "")))] | |
1249 | "reload_completed | |
1250 | && s390_match_ccmode (insn, CCUmode) | |
1251 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1252 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1253 | [(parallel | |
1254 | [(set (match_dup 0) (match_dup 1)) | |
1255 | (use (match_dup 2))])] | |
1256 | { | |
1257 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1258 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1259 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1260 | ||
1261 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1262 | operands[0], operands[1]); | |
1263 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1264 | }) | |
1265 | ||
1266 | ||
609e7e80 | 1267 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1268 | |
609e7e80 | 1269 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1270 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1271 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1272 | (compare (match_operand:FP 0 "register_operand" "f") |
1273 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1274 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1275 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1276 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1277 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1278 | |
be5de7a1 | 1279 | ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb |
f5905b37 | 1280 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1281 | [(set (reg CC_REGNUM) |
609e7e80 | 1282 | (compare (match_operand:FP 0 "register_operand" "f,f") |
62d3f261 | 1283 | (match_operand:FP 1 "general_operand" "f,R")))] |
142cd70f | 1284 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1285 | "@ |
609e7e80 | 1286 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1287 | c<xde>b\t%0,%1" |
077dab3b | 1288 | [(set_attr "op_type" "RRE,RXE") |
62d3f261 AK |
1289 | (set_attr "type" "fsimp<mode>") |
1290 | (set_attr "enabled" "*,<DSF>")]) | |
9db1d521 | 1291 | |
6e5b5de8 AK |
1292 | ; wfcedbs, wfchdbs, wfchedbs |
1293 | (define_insn "*vec_cmp<insn_cmp>df_cconly" | |
1294 | [(set (reg:VFCMP CC_REGNUM) | |
1295 | (compare:VFCMP (match_operand:DF 0 "register_operand" "v") | |
1296 | (match_operand:DF 1 "register_operand" "v"))) | |
1297 | (clobber (match_scratch:V2DI 2 "=v"))] | |
1298 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
1299 | "wfc<asm_fcmp>dbs\t%v2,%v0,%v1" | |
1300 | [(set_attr "op_type" "VRR")]) | |
963fc8d0 AK |
1301 | |
1302 | ; Compare and Branch instructions | |
1303 | ||
1304 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1305 | ; The following instructions do a complementary access of their second |
1306 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1307 | (define_insn "*cmp_and_br_signed_<mode>" |
1308 | [(set (pc) | |
1309 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1310 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1311 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1312 | (label_ref (match_operand 3 "" "")) | |
1313 | (pc))) | |
1314 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1315 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1316 | { |
1317 | if (get_attr_length (insn) == 6) | |
1318 | return which_alternative ? | |
1319 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1320 | else | |
1321 | return which_alternative ? | |
1322 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1323 | } | |
1324 | [(set_attr "op_type" "RIE") | |
1325 | (set_attr "type" "branch") | |
e3cba5e5 | 1326 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1327 | (set (attr "length") |
1328 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1329 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1330 | ; 10 byte for cgr/jg | |
1331 | ||
1332 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1333 | ; The following instructions do a complementary access of their second |
1334 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1335 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1336 | [(set (pc) | |
1337 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1338 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1339 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1340 | (label_ref (match_operand 3 "" "")) | |
1341 | (pc))) | |
1342 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1343 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1344 | { |
1345 | if (get_attr_length (insn) == 6) | |
1346 | return which_alternative ? | |
1347 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1348 | else | |
1349 | return which_alternative ? | |
1350 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1351 | } | |
1352 | [(set_attr "op_type" "RIE") | |
1353 | (set_attr "type" "branch") | |
e3cba5e5 | 1354 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1355 | (set (attr "length") |
1356 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1357 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1358 | ; 10 byte for clgr/jg | |
1359 | ||
b0f86a7e AK |
1360 | ; And now the same two patterns as above but with a negated CC mask. |
1361 | ||
1362 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1363 | ; The following instructions do a complementary access of their second | |
1364 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1365 | (define_insn "*icmp_and_br_signed_<mode>" | |
1366 | [(set (pc) | |
1367 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1368 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1369 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1370 | (pc) | |
1371 | (label_ref (match_operand 3 "" "")))) | |
1372 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1373 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1374 | { |
1375 | if (get_attr_length (insn) == 6) | |
1376 | return which_alternative ? | |
1377 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1378 | else | |
1379 | return which_alternative ? | |
1380 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1381 | } | |
1382 | [(set_attr "op_type" "RIE") | |
1383 | (set_attr "type" "branch") | |
1384 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1385 | (set (attr "length") | |
1386 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1387 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1388 | ; 10 byte for cgr/jg | |
1389 | ||
1390 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1391 | ; The following instructions do a complementary access of their second | |
1392 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1393 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1394 | [(set (pc) | |
1395 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1396 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1397 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1398 | (pc) | |
1399 | (label_ref (match_operand 3 "" "")))) | |
1400 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1401 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1402 | { |
1403 | if (get_attr_length (insn) == 6) | |
1404 | return which_alternative ? | |
1405 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1406 | else | |
1407 | return which_alternative ? | |
1408 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1409 | } | |
1410 | [(set_attr "op_type" "RIE") | |
1411 | (set_attr "type" "branch") | |
1412 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1413 | (set (attr "length") | |
1414 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1415 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1416 | ; 10 byte for clgr/jg | |
1417 | ||
9db1d521 HP |
1418 | ;; |
1419 | ;;- Move instructions. | |
1420 | ;; | |
1421 | ||
1422 | ; | |
1423 | ; movti instruction pattern(s). | |
1424 | ; | |
1425 | ||
085261c8 AK |
1426 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1427 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1428 | (define_insn "movti" |
085261c8 AK |
1429 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o") |
1430 | (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))] | |
9602b6a1 | 1431 | "TARGET_ZARCH" |
4023fb28 | 1432 | "@ |
fc0ea003 UW |
1433 | lmg\t%0,%N0,%S1 |
1434 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1435 | vlr\t%v0,%v1 |
1436 | vzero\t%v0 | |
1437 | vone\t%v0 | |
1438 | vlvgp\t%v0,%1,%N1 | |
1439 | # | |
1440 | vl\t%v0,%1 | |
1441 | vst\t%v1,%0 | |
4023fb28 | 1442 | # |
19b63d8e | 1443 | #" |
085261c8 AK |
1444 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1445 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
1446 | (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")]) | |
4023fb28 UW |
1447 | |
1448 | (define_split | |
1449 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1450 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1451 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1452 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1453 | [(set (match_dup 2) (match_dup 4)) |
1454 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1455 | { |
dc65c307 UW |
1456 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1457 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1458 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1459 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1460 | }) | |
1461 | ||
1462 | (define_split | |
1463 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1464 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1465 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1466 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1467 | [(set (match_dup 2) (match_dup 4)) | |
1468 | (set (match_dup 3) (match_dup 5))] | |
1469 | { | |
1470 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1471 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1472 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1473 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1474 | }) | |
4023fb28 | 1475 | |
085261c8 AK |
1476 | ; Use part of the TImode target reg to perform the address |
1477 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1478 | ; this splitter is not necessary. | |
4023fb28 UW |
1479 | (define_split |
1480 | [(set (match_operand:TI 0 "register_operand" "") | |
1481 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1482 | "TARGET_ZARCH && reload_completed |
085261c8 | 1483 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1484 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1485 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1486 | { |
1487 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1488 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1489 | s390_load_address (addr, XEXP (operands[1], 0)); |
1490 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1491 | }) |
1492 | ||
833cd70a | 1493 | |
085261c8 AK |
1494 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1495 | ; For the higher order bits we do simply a DImode move while the | |
1496 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1497 | (define_split | |
1498 | [(set (match_operand:TI 0 "register_operand" "") | |
1499 | (match_operand:TI 1 "register_operand" ""))] | |
1500 | "TARGET_VX && reload_completed | |
1501 | && GENERAL_REG_P (operands[0]) | |
1502 | && VECTOR_REG_P (operands[1])" | |
1503 | [(set (match_dup 2) (match_dup 4)) | |
1504 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1505 | UNSPEC_VEC_EXTRACT))] | |
1506 | { | |
1507 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1508 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1509 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1510 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1511 | }) | |
1512 | ||
833cd70a AK |
1513 | ; |
1514 | ; Patterns used for secondary reloads | |
1515 | ; | |
1516 | ||
963fc8d0 AK |
1517 | ; z10 provides move instructions accepting larl memory operands. |
1518 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1519 | ; These patterns are also used for unaligned SI and DI accesses. | |
1520 | ||
085261c8 AK |
1521 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1522 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1523 | (match_operand:ALL 1 "register_operand" "=d") | |
1524 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1525 | "TARGET_Z10" |
1526 | { | |
1527 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1528 | DONE; | |
1529 | }) | |
1530 | ||
085261c8 AK |
1531 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1532 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1533 | (match_operand:ALL 1 "memory_operand" "") | |
1534 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1535 | "TARGET_Z10" |
1536 | { | |
1537 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1538 | DONE; | |
1539 | }) | |
1540 | ||
1541 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1542 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1543 | (match_operand:P 1 "larl_operand" "") | |
1544 | (match_operand:P 2 "register_operand" "=a")])] | |
1545 | "TARGET_Z10" | |
1546 | { | |
1547 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1548 | DONE; | |
1549 | }) | |
1550 | ||
833cd70a AK |
1551 | ; Handles loading a PLUS (load address) expression |
1552 | ||
1553 | (define_expand "reload<mode>_plus" | |
1554 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1555 | (match_operand:P 1 "s390_plus_operand" "") | |
1556 | (match_operand:P 2 "register_operand" "=&a")])] | |
1557 | "" | |
1558 | { | |
1559 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1560 | DONE; | |
1561 | }) | |
1562 | ||
085261c8 AK |
1563 | ; Not all the indirect memory access instructions support the full |
1564 | ; format (long disp + index + base). So whenever a move from/to such | |
1565 | ; an address is required and the instruction cannot deal with it we do | |
1566 | ; a load address into a scratch register first and use this as the new | |
1567 | ; base register. | |
1568 | ; This in particular is used for: | |
1569 | ; - non-offsetable memory accesses for multiword moves | |
1570 | ; - full vector reg moves with long displacements | |
833cd70a | 1571 | |
085261c8 | 1572 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1573 | [(parallel [(match_operand 0 "register_operand" "") |
1574 | (match_operand 1 "" "") | |
1575 | (match_operand:P 2 "register_operand" "=&a")])] | |
1576 | "" | |
1577 | { | |
1578 | gcc_assert (MEM_P (operands[1])); | |
1579 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1580 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1581 | emit_move_insn (operands[0], operands[1]); | |
1582 | DONE; | |
1583 | }) | |
1584 | ||
085261c8 | 1585 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1586 | [(parallel [(match_operand 0 "" "") |
1587 | (match_operand 1 "register_operand" "") | |
1588 | (match_operand:P 2 "register_operand" "=&a")])] | |
1589 | "" | |
dc65c307 | 1590 | { |
9c3c3dcc | 1591 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1592 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1593 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1594 | emit_move_insn (operands[0], operands[1]); | |
1595 | DONE; | |
1596 | }) | |
9db1d521 | 1597 | |
1f9e1fc6 AK |
1598 | (define_expand "reload<mode>_PIC_addr" |
1599 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1600 | (match_operand 1 "larl_operand" "") | |
1601 | (match_operand:P 2 "register_operand" "=a")])] | |
1602 | "" | |
1603 | { | |
0a2aaacc KG |
1604 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1605 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1606 | }) |
1607 | ||
9db1d521 HP |
1608 | ; |
1609 | ; movdi instruction pattern(s). | |
1610 | ; | |
1611 | ||
9db1d521 HP |
1612 | (define_expand "movdi" |
1613 | [(set (match_operand:DI 0 "general_operand" "") | |
1614 | (match_operand:DI 1 "general_operand" ""))] | |
1615 | "" | |
9db1d521 | 1616 | { |
fd3cd001 | 1617 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1618 | if (TARGET_64BIT |
1619 | && (SYMBOLIC_CONST (operands[1]) | |
1620 | || (GET_CODE (operands[1]) == PLUS | |
1621 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1622 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1623 | emit_symbolic_move (operands); |
10bbf137 | 1624 | }) |
9db1d521 | 1625 | |
4023fb28 UW |
1626 | (define_insn "*movdi_larl" |
1627 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1628 | (match_operand:DI 1 "larl_operand" "X"))] | |
1629 | "TARGET_64BIT | |
8e509cf9 | 1630 | && !FP_REG_P (operands[0])" |
d40c829f | 1631 | "larl\t%0,%1" |
4023fb28 | 1632 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1633 | (set_attr "type" "larl") |
1634 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1635 | |
3af8e996 | 1636 | (define_insn "*movdi_64" |
85dae55a | 1637 | [(set (match_operand:DI 0 "nonimmediate_operand" |
085261c8 | 1638 | "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR") |
85dae55a | 1639 | (match_operand:DI 1 "general_operand" |
085261c8 | 1640 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))] |
9602b6a1 | 1641 | "TARGET_ZARCH" |
85dae55a AK |
1642 | "@ |
1643 | lghi\t%0,%h1 | |
1644 | llihh\t%0,%i1 | |
1645 | llihl\t%0,%i1 | |
1646 | llilh\t%0,%i1 | |
1647 | llill\t%0,%i1 | |
1648 | lgfi\t%0,%1 | |
1649 | llihf\t%0,%k1 | |
1650 | llilf\t%0,%k1 | |
1651 | ldgr\t%0,%1 | |
1652 | lgdr\t%0,%1 | |
1653 | lay\t%0,%a1 | |
963fc8d0 | 1654 | lgrl\t%0,%1 |
85dae55a AK |
1655 | lgr\t%0,%1 |
1656 | lg\t%0,%1 | |
1657 | stg\t%1,%0 | |
1658 | ldr\t%0,%1 | |
1659 | ld\t%0,%1 | |
1660 | ldy\t%0,%1 | |
1661 | std\t%1,%0 | |
1662 | stdy\t%1,%0 | |
963fc8d0 AK |
1663 | stgrl\t%1,%0 |
1664 | mvghi\t%0,%1 | |
85dae55a AK |
1665 | # |
1666 | # | |
1667 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1668 | lam\t%0,%N0,%S1 |
1669 | vleig\t%v0,%h1,0 | |
1670 | vlr\t%v0,%v1 | |
1671 | vlvgg\t%v0,%1,0 | |
1672 | vlgvg\t%0,%v1,0 | |
1673 | vleg\t%v0,%1,0 | |
1674 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1675 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1676 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1677 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1678 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1679 | *,*,*,*,*,*,*") | |
3af8e996 | 1680 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1681 | z10,*,*,*,*,*,longdisp,*,longdisp, |
085261c8 | 1682 | z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec") |
9381e3f1 WG |
1683 | (set_attr "z10prop" "z10_fwd_A1, |
1684 | z10_fwd_E1, | |
1685 | z10_fwd_E1, | |
1686 | z10_fwd_E1, | |
1687 | z10_fwd_E1, | |
1688 | z10_fwd_A1, | |
1689 | z10_fwd_E1, | |
1690 | z10_fwd_E1, | |
1691 | *, | |
1692 | *, | |
1693 | z10_fwd_A1, | |
1694 | z10_fwd_A3, | |
1695 | z10_fr_E1, | |
1696 | z10_fwd_A3, | |
1697 | z10_rec, | |
1698 | *, | |
1699 | *, | |
1700 | *, | |
1701 | *, | |
1702 | *, | |
1703 | z10_rec, | |
1704 | z10_super, | |
1705 | *, | |
1706 | *, | |
1707 | *, | |
085261c8 | 1708 | *,*,*,*,*,*,*") |
9381e3f1 | 1709 | ]) |
c5aa1d12 UW |
1710 | |
1711 | (define_split | |
1712 | [(set (match_operand:DI 0 "register_operand" "") | |
1713 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1714 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1715 | [(set (match_dup 2) (match_dup 3)) |
1716 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1717 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1718 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1719 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1720 | ||
1721 | (define_split | |
1722 | [(set (match_operand:DI 0 "register_operand" "") | |
1723 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1724 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1725 | && dead_or_set_p (insn, operands[1])" |
1726 | [(set (match_dup 3) (match_dup 2)) | |
1727 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1728 | (set (match_dup 4) (match_dup 2))] | |
1729 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1730 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1731 | ||
1732 | (define_split | |
1733 | [(set (match_operand:DI 0 "register_operand" "") | |
1734 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1735 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1736 | && !dead_or_set_p (insn, operands[1])" |
1737 | [(set (match_dup 3) (match_dup 2)) | |
1738 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1739 | (set (match_dup 4) (match_dup 2)) | |
1740 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1741 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1742 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1743 | |
1744 | (define_insn "*movdi_31" | |
963fc8d0 | 1745 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1746 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1747 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1748 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1749 | "!TARGET_ZARCH" |
4023fb28 | 1750 | "@ |
fc0ea003 | 1751 | lm\t%0,%N0,%S1 |
c4d50129 | 1752 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1753 | stm\t%1,%N1,%S0 |
c4d50129 | 1754 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1755 | # |
1756 | # | |
d40c829f UW |
1757 | ldr\t%0,%1 |
1758 | ld\t%0,%1 | |
1759 | ldy\t%0,%1 | |
1760 | std\t%1,%0 | |
1761 | stdy\t%1,%0 | |
19b63d8e | 1762 | #" |
f2dc2f86 AK |
1763 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1764 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1765 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1766 | |
1767 | ; For a load from a symbol ref we can use one of the target registers | |
1768 | ; together with larl to load the address. | |
1769 | (define_split | |
1770 | [(set (match_operand:DI 0 "register_operand" "") | |
1771 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1772 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1773 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1774 | [(set (match_dup 2) (match_dup 3)) | |
1775 | (set (match_dup 0) (match_dup 1))] | |
1776 | { | |
1777 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1778 | operands[3] = XEXP (operands[1], 0); | |
1779 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1780 | }) | |
4023fb28 UW |
1781 | |
1782 | (define_split | |
1783 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1784 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1785 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1786 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1787 | [(set (match_dup 2) (match_dup 4)) |
1788 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1789 | { |
dc65c307 UW |
1790 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1791 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1792 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1793 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1794 | }) | |
1795 | ||
1796 | (define_split | |
1797 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1798 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1799 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1800 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1801 | [(set (match_dup 2) (match_dup 4)) | |
1802 | (set (match_dup 3) (match_dup 5))] | |
1803 | { | |
1804 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1805 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1806 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1807 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1808 | }) | |
9db1d521 | 1809 | |
4023fb28 UW |
1810 | (define_split |
1811 | [(set (match_operand:DI 0 "register_operand" "") | |
1812 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1813 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1814 | && !FP_REG_P (operands[0]) |
4023fb28 | 1815 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1816 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1817 | { |
1818 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1819 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1820 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1821 | }) |
1822 | ||
84817c5d UW |
1823 | (define_peephole2 |
1824 | [(set (match_operand:DI 0 "register_operand" "") | |
1825 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1826 | "TARGET_ZARCH |
84817c5d UW |
1827 | && !FP_REG_P (operands[0]) |
1828 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1829 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1830 | && get_pool_mode (operands[1]) == DImode | |
1831 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1832 | [(set (match_dup 0) (match_dup 2))] | |
1833 | "operands[2] = get_pool_constant (operands[1]);") | |
1834 | ||
7bdff56f UW |
1835 | (define_insn "*la_64" |
1836 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1837 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1838 | "TARGET_64BIT" |
1839 | "@ | |
1840 | la\t%0,%a1 | |
1841 | lay\t%0,%a1" | |
1842 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1843 | (set_attr "type" "la") |
1844 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1845 | |
1846 | (define_peephole2 | |
1847 | [(parallel | |
1848 | [(set (match_operand:DI 0 "register_operand" "") | |
1849 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1850 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1851 | "TARGET_64BIT |
e1d5ee28 | 1852 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1853 | [(set (match_dup 0) (match_dup 1))] |
1854 | "") | |
1855 | ||
1856 | (define_peephole2 | |
1857 | [(set (match_operand:DI 0 "register_operand" "") | |
1858 | (match_operand:DI 1 "register_operand" "")) | |
1859 | (parallel | |
1860 | [(set (match_dup 0) | |
1861 | (plus:DI (match_dup 0) | |
1862 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1863 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1864 | "TARGET_64BIT |
1865 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1866 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1867 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1868 | "") | |
1869 | ||
9db1d521 HP |
1870 | ; |
1871 | ; movsi instruction pattern(s). | |
1872 | ; | |
1873 | ||
9db1d521 HP |
1874 | (define_expand "movsi" |
1875 | [(set (match_operand:SI 0 "general_operand" "") | |
1876 | (match_operand:SI 1 "general_operand" ""))] | |
1877 | "" | |
9db1d521 | 1878 | { |
fd3cd001 | 1879 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1880 | if (!TARGET_64BIT |
1881 | && (SYMBOLIC_CONST (operands[1]) | |
1882 | || (GET_CODE (operands[1]) == PLUS | |
1883 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1884 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1885 | emit_symbolic_move (operands); |
10bbf137 | 1886 | }) |
9db1d521 | 1887 | |
9e8327e3 UW |
1888 | (define_insn "*movsi_larl" |
1889 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1890 | (match_operand:SI 1 "larl_operand" "X"))] | |
1891 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1892 | && !FP_REG_P (operands[0])" | |
1893 | "larl\t%0,%1" | |
1894 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1895 | (set_attr "type" "larl") |
729e750f | 1896 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1897 | |
f19a9af7 | 1898 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1899 | [(set (match_operand:SI 0 "nonimmediate_operand" |
085261c8 | 1900 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR") |
2f7e5a0d | 1901 | (match_operand:SI 1 "general_operand" |
085261c8 | 1902 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))] |
f19a9af7 | 1903 | "TARGET_ZARCH" |
9db1d521 | 1904 | "@ |
f19a9af7 AK |
1905 | lhi\t%0,%h1 |
1906 | llilh\t%0,%i1 | |
1907 | llill\t%0,%i1 | |
ec24698e | 1908 | iilf\t%0,%o1 |
f19a9af7 | 1909 | lay\t%0,%a1 |
963fc8d0 | 1910 | lrl\t%0,%1 |
d40c829f UW |
1911 | lr\t%0,%1 |
1912 | l\t%0,%1 | |
1913 | ly\t%0,%1 | |
1914 | st\t%1,%0 | |
1915 | sty\t%1,%0 | |
085261c8 | 1916 | lder\t%0,%1 |
d40c829f | 1917 | ler\t%0,%1 |
085261c8 | 1918 | lde\t%0,%1 |
d40c829f UW |
1919 | le\t%0,%1 |
1920 | ley\t%0,%1 | |
1921 | ste\t%1,%0 | |
1922 | stey\t%1,%0 | |
c5aa1d12 UW |
1923 | ear\t%0,%1 |
1924 | sar\t%0,%1 | |
1925 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1926 | strl\t%1,%0 |
1927 | mvhi\t%0,%1 | |
085261c8 AK |
1928 | lam\t%0,%0,%S1 |
1929 | vleif\t%v0,%h1,0 | |
1930 | vlr\t%v0,%v1 | |
1931 | vlvgf\t%v0,%1,0 | |
1932 | vlgvf\t%0,%v1,0 | |
1933 | vlef\t%v0,%1,0 | |
1934 | vstef\t%v1,%0,0" | |
963fc8d0 | 1935 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
085261c8 | 1936 | RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
1937 | (set_attr "type" "*, |
1938 | *, | |
1939 | *, | |
1940 | *, | |
1941 | la, | |
1942 | larl, | |
1943 | lr, | |
1944 | load, | |
1945 | load, | |
1946 | store, | |
1947 | store, | |
1948 | floadsf, | |
1949 | floadsf, | |
1950 | floadsf, | |
085261c8 AK |
1951 | floadsf, |
1952 | floadsf, | |
9381e3f1 WG |
1953 | fstoresf, |
1954 | fstoresf, | |
1955 | *, | |
1956 | *, | |
1957 | *, | |
1958 | larl, | |
1959 | *, | |
085261c8 | 1960 | *,*,*,*,*,*,*") |
963fc8d0 | 1961 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
085261c8 | 1962 | vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec") |
9381e3f1 WG |
1963 | (set_attr "z10prop" "z10_fwd_A1, |
1964 | z10_fwd_E1, | |
1965 | z10_fwd_E1, | |
1966 | z10_fwd_A1, | |
1967 | z10_fwd_A1, | |
1968 | z10_fwd_A3, | |
1969 | z10_fr_E1, | |
1970 | z10_fwd_A3, | |
1971 | z10_fwd_A3, | |
729e750f | 1972 | z10_rec, |
9381e3f1 WG |
1973 | z10_rec, |
1974 | *, | |
1975 | *, | |
1976 | *, | |
1977 | *, | |
1978 | *, | |
085261c8 AK |
1979 | *, |
1980 | *, | |
9381e3f1 WG |
1981 | z10_super_E1, |
1982 | z10_super, | |
1983 | *, | |
1984 | z10_rec, | |
1985 | z10_super, | |
085261c8 | 1986 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
1987 | |
1988 | (define_insn "*movsi_esa" | |
085261c8 AK |
1989 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
1990 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1991 | "!TARGET_ZARCH" |
1992 | "@ | |
1993 | lhi\t%0,%h1 | |
1994 | lr\t%0,%1 | |
1995 | l\t%0,%1 | |
1996 | st\t%1,%0 | |
085261c8 | 1997 | lder\t%0,%1 |
f19a9af7 | 1998 | ler\t%0,%1 |
085261c8 | 1999 | lde\t%0,%1 |
f19a9af7 AK |
2000 | le\t%0,%1 |
2001 | ste\t%1,%0 | |
c5aa1d12 UW |
2002 | ear\t%0,%1 |
2003 | sar\t%0,%1 | |
2004 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2005 | lam\t%0,%0,%S1" |
085261c8 AK |
2006 | [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
2007 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") | |
2008 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2009 | z10_super,*,*") | |
2010 | (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*") | |
9381e3f1 | 2011 | ]) |
9db1d521 | 2012 | |
84817c5d UW |
2013 | (define_peephole2 |
2014 | [(set (match_operand:SI 0 "register_operand" "") | |
2015 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2016 | "!FP_REG_P (operands[0]) | |
2017 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2018 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2019 | && get_pool_mode (operands[1]) == SImode | |
2020 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2021 | [(set (match_dup 0) (match_dup 2))] | |
2022 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2023 | |
7bdff56f UW |
2024 | (define_insn "*la_31" |
2025 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2026 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
2027 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2028 | "@ | |
2029 | la\t%0,%a1 | |
2030 | lay\t%0,%a1" | |
2031 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
2032 | (set_attr "type" "la") |
2033 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
2034 | |
2035 | (define_peephole2 | |
2036 | [(parallel | |
2037 | [(set (match_operand:SI 0 "register_operand" "") | |
2038 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2039 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2040 | "!TARGET_64BIT |
e1d5ee28 | 2041 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2042 | [(set (match_dup 0) (match_dup 1))] |
2043 | "") | |
2044 | ||
2045 | (define_peephole2 | |
2046 | [(set (match_operand:SI 0 "register_operand" "") | |
2047 | (match_operand:SI 1 "register_operand" "")) | |
2048 | (parallel | |
2049 | [(set (match_dup 0) | |
2050 | (plus:SI (match_dup 0) | |
2051 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2052 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2053 | "!TARGET_64BIT |
2054 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2055 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2056 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2057 | "") | |
2058 | ||
2059 | (define_insn "*la_31_and" | |
2060 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2061 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
2062 | (const_int 2147483647)))] |
2063 | "!TARGET_64BIT" | |
2064 | "@ | |
2065 | la\t%0,%a1 | |
2066 | lay\t%0,%a1" | |
2067 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
2068 | (set_attr "type" "la") |
2069 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
2070 | |
2071 | (define_insn_and_split "*la_31_and_cc" | |
2072 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2073 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2074 | (const_int 2147483647))) | |
ae156f85 | 2075 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2076 | "!TARGET_64BIT" |
2077 | "#" | |
2078 | "&& reload_completed" | |
2079 | [(set (match_dup 0) | |
2080 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2081 | "" | |
2082 | [(set_attr "op_type" "RX") | |
2083 | (set_attr "type" "la")]) | |
2084 | ||
2085 | (define_insn "force_la_31" | |
2086 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2087 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
2088 | (use (const_int 0))] |
2089 | "!TARGET_64BIT" | |
2090 | "@ | |
2091 | la\t%0,%a1 | |
2092 | lay\t%0,%a1" | |
2093 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
2094 | (set_attr "type" "la") |
2095 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 2096 | |
9db1d521 HP |
2097 | ; |
2098 | ; movhi instruction pattern(s). | |
2099 | ; | |
2100 | ||
02ed3c5e UW |
2101 | (define_expand "movhi" |
2102 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2103 | (match_operand:HI 1 "general_operand" ""))] | |
2104 | "" | |
2105 | { | |
2f7e5a0d | 2106 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2107 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2108 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2109 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2110 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2111 | { |
2112 | rtx tmp = gen_reg_rtx (SImode); | |
2113 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2114 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2115 | operands[1] = gen_lowpart (HImode, tmp); |
2116 | } | |
2117 | }) | |
2118 | ||
2119 | (define_insn "*movhi" | |
085261c8 AK |
2120 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR") |
2121 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))] | |
9db1d521 HP |
2122 | "" |
2123 | "@ | |
d40c829f UW |
2124 | lr\t%0,%1 |
2125 | lhi\t%0,%h1 | |
2126 | lh\t%0,%1 | |
2127 | lhy\t%0,%1 | |
963fc8d0 | 2128 | lhrl\t%0,%1 |
d40c829f UW |
2129 | sth\t%1,%0 |
2130 | sthy\t%1,%0 | |
963fc8d0 | 2131 | sthrl\t%1,%0 |
085261c8 AK |
2132 | mvhhi\t%0,%1 |
2133 | vleih\t%v0,%h1,0 | |
2134 | vlr\t%v0,%v1 | |
2135 | vlvgh\t%v0,%1,0 | |
2136 | vlgvh\t%0,%v1,0 | |
2137 | vleh\t%v0,%1,0 | |
2138 | vsteh\t%v1,%0,0" | |
2139 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2140 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
2141 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec") | |
9381e3f1 WG |
2142 | (set_attr "z10prop" "z10_fr_E1, |
2143 | z10_fwd_A1, | |
2144 | z10_super_E1, | |
2145 | z10_super_E1, | |
2146 | z10_super_E1, | |
729e750f | 2147 | z10_rec, |
9381e3f1 WG |
2148 | z10_rec, |
2149 | z10_rec, | |
085261c8 | 2150 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2151 | |
84817c5d UW |
2152 | (define_peephole2 |
2153 | [(set (match_operand:HI 0 "register_operand" "") | |
2154 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2155 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2156 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2157 | && get_pool_mode (operands[1]) == HImode | |
2158 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2159 | [(set (match_dup 0) (match_dup 2))] | |
2160 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2161 | |
9db1d521 HP |
2162 | ; |
2163 | ; movqi instruction pattern(s). | |
2164 | ; | |
2165 | ||
02ed3c5e UW |
2166 | (define_expand "movqi" |
2167 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2168 | (match_operand:QI 1 "general_operand" ""))] | |
2169 | "" | |
2170 | { | |
c19ec8f9 | 2171 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2172 | is just as fast as a QImode load. */ |
b3a13419 | 2173 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2174 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2175 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2176 | { |
9602b6a1 AK |
2177 | rtx tmp = gen_reg_rtx (DImode); |
2178 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2179 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2180 | operands[1] = gen_lowpart (QImode, tmp); |
2181 | } | |
2182 | }) | |
4023fb28 | 2183 | |
02ed3c5e | 2184 | (define_insn "*movqi" |
085261c8 AK |
2185 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR") |
2186 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))] | |
9db1d521 HP |
2187 | "" |
2188 | "@ | |
d40c829f UW |
2189 | lr\t%0,%1 |
2190 | lhi\t%0,%b1 | |
2191 | ic\t%0,%1 | |
2192 | icy\t%0,%1 | |
2193 | stc\t%1,%0 | |
2194 | stcy\t%1,%0 | |
fc0ea003 | 2195 | mvi\t%S0,%b1 |
0a88561f | 2196 | mviy\t%S0,%b1 |
085261c8 AK |
2197 | # |
2198 | vleib\t%v0,%b1,0 | |
2199 | vlr\t%v0,%v1 | |
2200 | vlvgb\t%v0,%1,0 | |
2201 | vlgvb\t%0,%v1,0 | |
2202 | vleb\t%v0,%1,0 | |
2203 | vsteb\t%v1,%0,0" | |
2204 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2205 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
2206 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec") | |
9381e3f1 WG |
2207 | (set_attr "z10prop" "z10_fr_E1, |
2208 | z10_fwd_A1, | |
2209 | z10_super_E1, | |
2210 | z10_super_E1, | |
729e750f | 2211 | z10_rec, |
9381e3f1 WG |
2212 | z10_rec, |
2213 | z10_super, | |
0a88561f | 2214 | z10_super, |
085261c8 | 2215 | *,*,*,*,*,*,*")]) |
9db1d521 | 2216 | |
84817c5d UW |
2217 | (define_peephole2 |
2218 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2219 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2220 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2221 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2222 | && get_pool_mode (operands[1]) == QImode | |
2223 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2224 | [(set (match_dup 0) (match_dup 2))] | |
2225 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2226 | |
9db1d521 | 2227 | ; |
05b9aaaa | 2228 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2229 | ; |
2230 | ||
2231 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2232 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2233 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2234 | "" |
d3632d41 | 2235 | "@ |
d40c829f UW |
2236 | ic\t%0,%1 |
2237 | icy\t%0,%1" | |
9381e3f1 | 2238 | [(set_attr "op_type" "RX,RXY") |
729e750f | 2239 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2240 | |
2241 | ; | |
2242 | ; movstricthi instruction pattern(s). | |
2243 | ; | |
2244 | ||
2245 | (define_insn "*movstricthi" | |
d3632d41 | 2246 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2247 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2248 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2249 | "" |
d3632d41 | 2250 | "@ |
fc0ea003 UW |
2251 | icm\t%0,3,%S1 |
2252 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
2253 | [(set_attr "op_type" "RS,RSY") |
2254 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
2255 | |
2256 | ; | |
2257 | ; movstrictsi instruction pattern(s). | |
2258 | ; | |
2259 | ||
05b9aaaa | 2260 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2261 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2262 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2263 | "TARGET_ZARCH" |
9db1d521 | 2264 | "@ |
d40c829f UW |
2265 | lr\t%0,%1 |
2266 | l\t%0,%1 | |
c5aa1d12 UW |
2267 | ly\t%0,%1 |
2268 | ear\t%0,%1" | |
2269 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
2270 | (set_attr "type" "lr,load,load,*") |
2271 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 2272 | |
f61a2c7d | 2273 | ; |
609e7e80 | 2274 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2275 | ; |
2276 | ||
609e7e80 AK |
2277 | (define_expand "mov<mode>" |
2278 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2279 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2280 | "" |
2281 | "") | |
2282 | ||
609e7e80 | 2283 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2284 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
2285 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 2286 | "TARGET_ZARCH" |
f61a2c7d | 2287 | "@ |
65b1d8ea | 2288 | lzxr\t%0 |
f61a2c7d AK |
2289 | lxr\t%0,%1 |
2290 | # | |
2291 | # | |
2292 | lmg\t%0,%N0,%S1 | |
2293 | stmg\t%1,%N1,%S0 | |
2294 | # | |
f61a2c7d | 2295 | #" |
65b1d8ea AK |
2296 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2297 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2298 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2299 | |
609e7e80 | 2300 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2301 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2302 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2303 | "!TARGET_ZARCH" |
f61a2c7d | 2304 | "@ |
65b1d8ea | 2305 | lzxr\t%0 |
f61a2c7d AK |
2306 | lxr\t%0,%1 |
2307 | # | |
f61a2c7d | 2308 | #" |
65b1d8ea AK |
2309 | [(set_attr "op_type" "RRE,RRE,*,*") |
2310 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2311 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2312 | |
2313 | ; TFmode in GPRs splitters | |
2314 | ||
2315 | (define_split | |
609e7e80 AK |
2316 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2317 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2318 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2319 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2320 | [(set (match_dup 2) (match_dup 4)) |
2321 | (set (match_dup 3) (match_dup 5))] | |
2322 | { | |
609e7e80 AK |
2323 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2324 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2325 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2326 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2327 | }) |
2328 | ||
2329 | (define_split | |
609e7e80 AK |
2330 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2331 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2332 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2333 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2334 | [(set (match_dup 2) (match_dup 4)) |
2335 | (set (match_dup 3) (match_dup 5))] | |
2336 | { | |
609e7e80 AK |
2337 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2338 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2339 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2340 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2341 | }) |
2342 | ||
2343 | (define_split | |
609e7e80 AK |
2344 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2345 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2346 | "TARGET_ZARCH && reload_completed |
085261c8 | 2347 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2348 | && !s_operand (operands[1], VOIDmode)" |
2349 | [(set (match_dup 0) (match_dup 1))] | |
2350 | { | |
609e7e80 | 2351 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2352 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2353 | s390_load_address (addr, XEXP (operands[1], 0)); |
2354 | operands[1] = replace_equiv_address (operands[1], addr); | |
2355 | }) | |
2356 | ||
7b6baae1 | 2357 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2358 | |
2359 | (define_split | |
609e7e80 AK |
2360 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2361 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2362 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2363 | && FP_REG_P (operands[0])" |
2364 | [(set (match_dup 2) (match_dup 4)) | |
2365 | (set (match_dup 3) (match_dup 5))] | |
2366 | { | |
609e7e80 AK |
2367 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2368 | <MODE>mode, 0); | |
2369 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2370 | <MODE>mode, 8); | |
2371 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2372 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2373 | }) |
2374 | ||
2375 | (define_split | |
609e7e80 AK |
2376 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2377 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2378 | "reload_completed && offsettable_memref_p (operands[0]) |
2379 | && FP_REG_P (operands[1])" | |
2380 | [(set (match_dup 2) (match_dup 4)) | |
2381 | (set (match_dup 3) (match_dup 5))] | |
2382 | { | |
609e7e80 AK |
2383 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2384 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2385 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2386 | <MODE>mode, 0); | |
2387 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2388 | <MODE>mode, 8); | |
f61a2c7d AK |
2389 | }) |
2390 | ||
9db1d521 | 2391 | ; |
609e7e80 | 2392 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2393 | ; |
2394 | ||
609e7e80 AK |
2395 | (define_expand "mov<mode>" |
2396 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2397 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2398 | "" |
13c025c1 | 2399 | "") |
9db1d521 | 2400 | |
609e7e80 AK |
2401 | (define_insn "*mov<mode>_64dfp" |
2402 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
085261c8 | 2403 | "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR") |
609e7e80 | 2404 | (match_operand:DD_DF 1 "general_operand" |
085261c8 | 2405 | " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))] |
9602b6a1 | 2406 | "TARGET_DFP" |
85dae55a | 2407 | "@ |
65b1d8ea | 2408 | lzdr\t%0 |
85dae55a AK |
2409 | ldr\t%0,%1 |
2410 | ldgr\t%0,%1 | |
2411 | lgdr\t%0,%1 | |
2412 | ld\t%0,%1 | |
2413 | ldy\t%0,%1 | |
2414 | std\t%1,%0 | |
2415 | stdy\t%1,%0 | |
45e5214c | 2416 | lghi\t%0,0 |
85dae55a | 2417 | lgr\t%0,%1 |
085261c8 | 2418 | lgrl\t%0,%1 |
85dae55a | 2419 | lg\t%0,%1 |
085261c8 AK |
2420 | stgrl\t%1,%0 |
2421 | stg\t%1,%0 | |
2422 | vlr\t%v0,%v1 | |
2423 | vlvgg\t%v0,%1,0 | |
2424 | vlgvg\t%0,%v1,0 | |
2425 | vleg\t%0,%1,0 | |
2426 | vsteg\t%1,%0,0" | |
2427 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX") | |
65b1d8ea | 2428 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
085261c8 AK |
2429 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store") |
2430 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*") | |
2431 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")]) | |
85dae55a | 2432 | |
609e7e80 | 2433 | (define_insn "*mov<mode>_64" |
085261c8 AK |
2434 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR") |
2435 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))] | |
9602b6a1 | 2436 | "TARGET_ZARCH" |
9db1d521 | 2437 | "@ |
65b1d8ea | 2438 | lzdr\t%0 |
d40c829f UW |
2439 | ldr\t%0,%1 |
2440 | ld\t%0,%1 | |
2441 | ldy\t%0,%1 | |
2442 | std\t%1,%0 | |
2443 | stdy\t%1,%0 | |
45e5214c | 2444 | lghi\t%0,0 |
d40c829f | 2445 | lgr\t%0,%1 |
085261c8 | 2446 | lgrl\t%0,%1 |
d40c829f | 2447 | lg\t%0,%1 |
085261c8 AK |
2448 | stgrl\t%1,%0 |
2449 | stg\t%1,%0 | |
2450 | vlr\t%v0,%v1 | |
2451 | vleg\t%v0,%1,0 | |
2452 | vsteg\t%v1,%0,0" | |
2453 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX") | |
65b1d8ea | 2454 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
085261c8 AK |
2455 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store") |
2456 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*") | |
2457 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")]) | |
609e7e80 AK |
2458 | |
2459 | (define_insn "*mov<mode>_31" | |
2460 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2461 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2462 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2463 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2464 | "!TARGET_ZARCH" |
9db1d521 | 2465 | "@ |
65b1d8ea | 2466 | lzdr\t%0 |
d40c829f UW |
2467 | ldr\t%0,%1 |
2468 | ld\t%0,%1 | |
2469 | ldy\t%0,%1 | |
2470 | std\t%1,%0 | |
2471 | stdy\t%1,%0 | |
fc0ea003 | 2472 | lm\t%0,%N0,%S1 |
c4d50129 | 2473 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2474 | stm\t%1,%N1,%S0 |
c4d50129 | 2475 | stmy\t%1,%N1,%S0 |
4023fb28 | 2476 | # |
19b63d8e | 2477 | #" |
65b1d8ea AK |
2478 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2479 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2480 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2481 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2482 | |
2483 | (define_split | |
609e7e80 AK |
2484 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2485 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2486 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2487 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2488 | [(set (match_dup 2) (match_dup 4)) |
2489 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2490 | { |
609e7e80 AK |
2491 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2492 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2493 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2494 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2495 | }) |
2496 | ||
2497 | (define_split | |
609e7e80 AK |
2498 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2499 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2500 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2501 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2502 | [(set (match_dup 2) (match_dup 4)) |
2503 | (set (match_dup 3) (match_dup 5))] | |
2504 | { | |
609e7e80 AK |
2505 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2506 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2507 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2508 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2509 | }) |
9db1d521 | 2510 | |
4023fb28 | 2511 | (define_split |
609e7e80 AK |
2512 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2513 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2514 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2515 | && !FP_REG_P (operands[0]) |
4023fb28 | 2516 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2517 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2518 | { |
609e7e80 | 2519 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2520 | s390_load_address (addr, XEXP (operands[1], 0)); |
2521 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2522 | }) |
2523 | ||
9db1d521 | 2524 | ; |
609e7e80 | 2525 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2526 | ; |
2527 | ||
609e7e80 AK |
2528 | (define_insn "mov<mode>" |
2529 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
085261c8 | 2530 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR") |
609e7e80 | 2531 | (match_operand:SD_SF 1 "general_operand" |
085261c8 | 2532 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))] |
4023fb28 | 2533 | "" |
9db1d521 | 2534 | "@ |
65b1d8ea | 2535 | lzer\t%0 |
085261c8 | 2536 | lder\t%0,%1 |
d40c829f | 2537 | ler\t%0,%1 |
085261c8 | 2538 | lde\t%0,%1 |
d40c829f UW |
2539 | le\t%0,%1 |
2540 | ley\t%0,%1 | |
2541 | ste\t%1,%0 | |
2542 | stey\t%1,%0 | |
45e5214c | 2543 | lhi\t%0,0 |
d40c829f | 2544 | lr\t%0,%1 |
085261c8 | 2545 | lrl\t%0,%1 |
d40c829f UW |
2546 | l\t%0,%1 |
2547 | ly\t%0,%1 | |
085261c8 | 2548 | strl\t%1,%0 |
d40c829f | 2549 | st\t%1,%0 |
085261c8 AK |
2550 | sty\t%1,%0 |
2551 | vlr\t%v0,%v1 | |
2552 | vleif\t%v0,0 | |
2553 | vlvgf\t%v0,%1,0 | |
2554 | vlgvf\t%0,%v1,0 | |
2555 | vleg\t%0,%1,0 | |
2556 | vsteg\t%1,%0,0" | |
2557 | [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") | |
2558 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, | |
2559 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2560 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
2561 | (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")]) | |
4023fb28 | 2562 | |
9dc62c00 AK |
2563 | ; |
2564 | ; movcc instruction pattern | |
2565 | ; | |
2566 | ||
2567 | (define_insn "movcc" | |
2568 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2569 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2570 | "" |
2571 | "@ | |
2572 | lr\t%0,%1 | |
2573 | tmh\t%1,12288 | |
2574 | ipm\t%0 | |
a71f0749 DV |
2575 | l\t%0,%1 |
2576 | ly\t%0,%1 | |
2577 | st\t%1,%0 | |
2578 | sty\t%1,%0" | |
8dd3b235 | 2579 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 DV |
2580 | (set_attr "type" "lr,*,*,load,load,store,store") |
2581 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
65b1d8ea | 2582 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2583 | |
19b63d8e UW |
2584 | ; |
2585 | ; Block move (MVC) patterns. | |
2586 | ; | |
2587 | ||
2588 | (define_insn "*mvc" | |
2589 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2590 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2591 | (use (match_operand 2 "const_int_operand" "n"))] | |
2592 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2593 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2594 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2595 | |
0a88561f AK |
2596 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2597 | ; order to have it implemented with mvc. | |
2598 | ||
2599 | (define_split | |
2600 | [(set (match_operand:QI 0 "memory_operand" "") | |
2601 | (match_operand:QI 1 "memory_operand" ""))] | |
2602 | "reload_completed" | |
2603 | [(parallel | |
2604 | [(set (match_dup 0) (match_dup 1)) | |
2605 | (use (const_int 1))])] | |
2606 | { | |
2607 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2608 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2609 | }) | |
2610 | ||
2611 | ||
19b63d8e UW |
2612 | (define_peephole2 |
2613 | [(parallel | |
2614 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2615 | (match_operand:BLK 1 "memory_operand" "")) | |
2616 | (use (match_operand 2 "const_int_operand" ""))]) | |
2617 | (parallel | |
2618 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2619 | (match_operand:BLK 4 "memory_operand" "")) | |
2620 | (use (match_operand 5 "const_int_operand" ""))])] | |
2621 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2622 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2623 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2624 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2625 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2626 | [(parallel | |
2627 | [(set (match_dup 6) (match_dup 7)) | |
2628 | (use (match_dup 8))])] | |
2629 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2630 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2631 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2632 | ||
2633 | ||
9db1d521 HP |
2634 | ; |
2635 | ; load_multiple pattern(s). | |
2636 | ; | |
22ea6b4f UW |
2637 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2638 | ; we currently support load_multiple/store_multiple only after reload. | |
2639 | ; | |
9db1d521 HP |
2640 | |
2641 | (define_expand "load_multiple" | |
2642 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2643 | (match_operand 1 "" "")) | |
2644 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2645 | "reload_completed" |
9db1d521 | 2646 | { |
ef4bddc2 | 2647 | machine_mode mode; |
9db1d521 HP |
2648 | int regno; |
2649 | int count; | |
2650 | rtx from; | |
4023fb28 | 2651 | int i, off; |
9db1d521 HP |
2652 | |
2653 | /* Support only loading a constant number of fixed-point registers from | |
2654 | memory and only bother with this if more than two */ | |
2655 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2656 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2657 | || INTVAL (operands[2]) > 16 |
2658 | || GET_CODE (operands[1]) != MEM | |
2659 | || GET_CODE (operands[0]) != REG | |
2660 | || REGNO (operands[0]) >= 16) | |
2661 | FAIL; | |
2662 | ||
2663 | count = INTVAL (operands[2]); | |
2664 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2665 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2666 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2667 | FAIL; |
9db1d521 HP |
2668 | |
2669 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2670 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2671 | { |
2672 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2673 | { | |
2674 | from = XEXP (operands[1], 0); | |
2675 | off = 0; | |
2676 | } | |
2677 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2678 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2679 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2680 | { | |
2681 | from = XEXP (XEXP (operands[1], 0), 0); | |
2682 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2683 | } | |
2684 | else | |
2685 | FAIL; | |
4023fb28 UW |
2686 | } |
2687 | else | |
2688 | { | |
2689 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2690 | off = 0; | |
2691 | } | |
9db1d521 HP |
2692 | |
2693 | for (i = 0; i < count; i++) | |
2694 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2695 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2696 | change_address (operands[1], mode, |
0a81f074 RS |
2697 | plus_constant (Pmode, from, |
2698 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2699 | }) |
9db1d521 HP |
2700 | |
2701 | (define_insn "*load_multiple_di" | |
2702 | [(match_parallel 0 "load_multiple_operation" | |
2703 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2704 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2705 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2706 | { |
2707 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2708 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2709 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2710 | } |
d3632d41 | 2711 | [(set_attr "op_type" "RSY") |
4023fb28 | 2712 | (set_attr "type" "lm")]) |
9db1d521 HP |
2713 | |
2714 | (define_insn "*load_multiple_si" | |
2715 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2716 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2717 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2718 | "reload_completed" |
9db1d521 HP |
2719 | { |
2720 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2721 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2722 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2723 | } |
d3632d41 | 2724 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2725 | (set_attr "type" "lm")]) |
9db1d521 HP |
2726 | |
2727 | ; | |
c7453384 | 2728 | ; store multiple pattern(s). |
9db1d521 HP |
2729 | ; |
2730 | ||
2731 | (define_expand "store_multiple" | |
2732 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2733 | (match_operand 1 "" "")) | |
2734 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2735 | "reload_completed" |
9db1d521 | 2736 | { |
ef4bddc2 | 2737 | machine_mode mode; |
9db1d521 HP |
2738 | int regno; |
2739 | int count; | |
2740 | rtx to; | |
4023fb28 | 2741 | int i, off; |
9db1d521 HP |
2742 | |
2743 | /* Support only storing a constant number of fixed-point registers to | |
2744 | memory and only bother with this if more than two. */ | |
2745 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2746 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2747 | || INTVAL (operands[2]) > 16 |
2748 | || GET_CODE (operands[0]) != MEM | |
2749 | || GET_CODE (operands[1]) != REG | |
2750 | || REGNO (operands[1]) >= 16) | |
2751 | FAIL; | |
2752 | ||
2753 | count = INTVAL (operands[2]); | |
2754 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2755 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2756 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2757 | FAIL; |
9db1d521 HP |
2758 | |
2759 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2760 | |
b3a13419 | 2761 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2762 | { |
2763 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2764 | { | |
2765 | to = XEXP (operands[0], 0); | |
2766 | off = 0; | |
2767 | } | |
2768 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2769 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2770 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2771 | { | |
2772 | to = XEXP (XEXP (operands[0], 0), 0); | |
2773 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2774 | } | |
2775 | else | |
2776 | FAIL; | |
4023fb28 | 2777 | } |
c7453384 | 2778 | else |
4023fb28 UW |
2779 | { |
2780 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2781 | off = 0; | |
2782 | } | |
9db1d521 HP |
2783 | |
2784 | for (i = 0; i < count; i++) | |
2785 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2786 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2787 | plus_constant (Pmode, to, |
2788 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2789 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2790 | }) |
9db1d521 HP |
2791 | |
2792 | (define_insn "*store_multiple_di" | |
2793 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2794 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2795 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2796 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2797 | { |
2798 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2799 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2800 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2801 | } |
d3632d41 | 2802 | [(set_attr "op_type" "RSY") |
4023fb28 | 2803 | (set_attr "type" "stm")]) |
9db1d521 HP |
2804 | |
2805 | ||
2806 | (define_insn "*store_multiple_si" | |
2807 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2808 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2809 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2810 | "reload_completed" |
9db1d521 HP |
2811 | { |
2812 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2813 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2814 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2815 | } |
d3632d41 | 2816 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2817 | (set_attr "type" "stm")]) |
9db1d521 HP |
2818 | |
2819 | ;; | |
2820 | ;; String instructions. | |
2821 | ;; | |
2822 | ||
963fc8d0 | 2823 | (define_insn "*execute_rl" |
2771c2f9 | 2824 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2825 | [(unspec [(match_operand 1 "register_operand" "a") |
2826 | (match_operand 2 "" "") | |
2827 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2828 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2829 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2830 | "exrl\t%1,%3" | |
2831 | [(set_attr "op_type" "RIL") | |
2832 | (set_attr "type" "cs")]) | |
2833 | ||
9bb86f41 | 2834 | (define_insn "*execute" |
2771c2f9 | 2835 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2836 | [(unspec [(match_operand 1 "register_operand" "a") |
2837 | (match_operand:BLK 2 "memory_operand" "R") | |
2838 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2839 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2840 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2841 | "ex\t%1,%2" | |
29a74354 UW |
2842 | [(set_attr "op_type" "RX") |
2843 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2844 | |
2845 | ||
91d39d71 UW |
2846 | ; |
2847 | ; strlenM instruction pattern(s). | |
2848 | ; | |
2849 | ||
9db2f16d | 2850 | (define_expand "strlen<mode>" |
085261c8 AK |
2851 | [(match_operand:P 0 "register_operand" "") ; result |
2852 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2853 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2854 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2855 | "" | |
2856 | { | |
2857 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2858 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2859 | operands[2], operands[3])); | |
2860 | else | |
2861 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2862 | ||
2863 | DONE; | |
2864 | }) | |
2865 | ||
2866 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 2867 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2868 | (parallel |
91d39d71 | 2869 | [(set (match_dup 4) |
9db2f16d | 2870 | (unspec:P [(const_int 0) |
91d39d71 | 2871 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2872 | (reg:SI 0) |
91d39d71 | 2873 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2874 | (clobber (scratch:P)) |
ae156f85 | 2875 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2876 | (parallel |
9db2f16d AS |
2877 | [(set (match_operand:P 0 "register_operand" "") |
2878 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2879 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2880 | "" |
91d39d71 | 2881 | { |
9db2f16d AS |
2882 | operands[4] = gen_reg_rtx (Pmode); |
2883 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2884 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2885 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2886 | }) | |
2887 | ||
9db2f16d AS |
2888 | (define_insn "*strlen<mode>" |
2889 | [(set (match_operand:P 0 "register_operand" "=a") | |
2890 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2891 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2892 | (reg:SI 0) |
91d39d71 | 2893 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2894 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2895 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2896 | "" |
91d39d71 | 2897 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2898 | [(set_attr "length" "8") |
2899 | (set_attr "type" "vs")]) | |
91d39d71 | 2900 | |
ccbdc0d4 AS |
2901 | ; |
2902 | ; cmpstrM instruction pattern(s). | |
2903 | ; | |
2904 | ||
2905 | (define_expand "cmpstrsi" | |
2906 | [(set (reg:SI 0) (const_int 0)) | |
2907 | (parallel | |
2908 | [(clobber (match_operand 3 "" "")) | |
2909 | (clobber (match_dup 4)) | |
2910 | (set (reg:CCU CC_REGNUM) | |
2911 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2912 | (match_operand:BLK 2 "memory_operand" ""))) | |
2913 | (use (reg:SI 0))]) | |
2914 | (parallel | |
2915 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2916 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
2917 | (clobber (reg:CC CC_REGNUM))])] |
2918 | "" | |
2919 | { | |
2920 | /* As the result of CMPINT is inverted compared to what we need, | |
2921 | we have to swap the operands. */ | |
2922 | rtx op1 = operands[2]; | |
2923 | rtx op2 = operands[1]; | |
2924 | rtx addr1 = gen_reg_rtx (Pmode); | |
2925 | rtx addr2 = gen_reg_rtx (Pmode); | |
2926 | ||
2927 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2928 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2929 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2930 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2931 | operands[3] = addr1; | |
2932 | operands[4] = addr2; | |
2933 | }) | |
2934 | ||
2935 | (define_insn "*cmpstr<mode>" | |
2936 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2937 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2938 | (set (reg:CCU CC_REGNUM) | |
2939 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2940 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2941 | (use (reg:SI 0))] | |
2942 | "" | |
2943 | "clst\t%0,%1\;jo\t.-4" | |
2944 | [(set_attr "length" "8") | |
2945 | (set_attr "type" "vs")]) | |
9381e3f1 | 2946 | |
742090fc AS |
2947 | ; |
2948 | ; movstr instruction pattern. | |
2949 | ; | |
2950 | ||
2951 | (define_expand "movstr" | |
4a7dec25 DV |
2952 | [(match_operand 0 "register_operand" "") |
2953 | (match_operand 1 "memory_operand" "") | |
2954 | (match_operand 2 "memory_operand" "")] | |
2955 | "" | |
2956 | { | |
2957 | if (TARGET_64BIT) | |
2958 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
2959 | else | |
2960 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
2961 | DONE; | |
2962 | }) | |
2963 | ||
2964 | (define_expand "movstr<P:mode>" | |
742090fc | 2965 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 2966 | (parallel |
742090fc AS |
2967 | [(clobber (match_dup 3)) |
2968 | (set (match_operand:BLK 1 "memory_operand" "") | |
2969 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
2970 | (set (match_operand:P 0 "register_operand" "") |
2971 | (unspec:P [(match_dup 1) | |
742090fc AS |
2972 | (match_dup 2) |
2973 | (reg:SI 0)] UNSPEC_MVST)) | |
2974 | (clobber (reg:CC CC_REGNUM))])] | |
2975 | "" | |
2976 | { | |
859a4c0e AK |
2977 | rtx addr1, addr2; |
2978 | ||
2979 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
2980 | { | |
2981 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
2982 | DONE; | |
2983 | } | |
2984 | ||
2985 | addr1 = gen_reg_rtx (Pmode); | |
2986 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
2987 | |
2988 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2989 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2990 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2991 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2992 | operands[3] = addr2; | |
2993 | }) | |
2994 | ||
2995 | (define_insn "*movstr" | |
2996 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2997 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2998 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2999 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3000 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3001 | (mem:BLK (match_dup 3)) |
3002 | (reg:SI 0)] UNSPEC_MVST)) | |
3003 | (clobber (reg:CC CC_REGNUM))] | |
3004 | "" | |
3005 | "mvst\t%1,%2\;jo\t.-4" | |
3006 | [(set_attr "length" "8") | |
3007 | (set_attr "type" "vs")]) | |
9381e3f1 | 3008 | |
742090fc | 3009 | |
9db1d521 | 3010 | ; |
70128ad9 | 3011 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3012 | ; |
3013 | ||
9db2f16d | 3014 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3015 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3016 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3017 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3018 | (match_operand 3 "" "")] |
3019 | "" | |
367d32f3 AK |
3020 | { |
3021 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3022 | DONE; | |
3023 | else | |
3024 | FAIL; | |
3025 | }) | |
9db1d521 | 3026 | |
ecbe845e UW |
3027 | ; Move a block that is up to 256 bytes in length. |
3028 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3029 | |
70128ad9 | 3030 | (define_expand "movmem_short" |
b9404c99 UW |
3031 | [(parallel |
3032 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3033 | (match_operand:BLK 1 "memory_operand" "")) | |
3034 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3035 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3036 | (clobber (match_dup 3))])] |
3037 | "" | |
3038 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3039 | |
70128ad9 | 3040 | (define_insn "*movmem_short" |
963fc8d0 AK |
3041 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3042 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3043 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3044 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3045 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3046 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3047 | "#" |
963fc8d0 | 3048 | [(set_attr "type" "cs") |
b5e0425c | 3049 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3050 | |
9bb86f41 UW |
3051 | (define_split |
3052 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3053 | (match_operand:BLK 1 "memory_operand" "")) | |
3054 | (use (match_operand 2 "const_int_operand" "")) | |
3055 | (use (match_operand 3 "immediate_operand" "")) | |
3056 | (clobber (scratch))] | |
3057 | "reload_completed" | |
3058 | [(parallel | |
3059 | [(set (match_dup 0) (match_dup 1)) | |
3060 | (use (match_dup 2))])] | |
3061 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3062 | |
9bb86f41 UW |
3063 | (define_split |
3064 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3065 | (match_operand:BLK 1 "memory_operand" "")) | |
3066 | (use (match_operand 2 "register_operand" "")) | |
3067 | (use (match_operand 3 "memory_operand" "")) | |
3068 | (clobber (scratch))] | |
3069 | "reload_completed" | |
3070 | [(parallel | |
3071 | [(unspec [(match_dup 2) (match_dup 3) | |
3072 | (const_int 0)] UNSPEC_EXECUTE) | |
3073 | (set (match_dup 0) (match_dup 1)) | |
3074 | (use (const_int 1))])] | |
3075 | "") | |
3076 | ||
963fc8d0 AK |
3077 | (define_split |
3078 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3079 | (match_operand:BLK 1 "memory_operand" "")) | |
3080 | (use (match_operand 2 "register_operand" "")) | |
3081 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3082 | (clobber (scratch))] | |
3083 | "TARGET_Z10 && reload_completed" | |
3084 | [(parallel | |
3085 | [(unspec [(match_dup 2) (const_int 0) | |
3086 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3087 | (set (match_dup 0) (match_dup 1)) | |
3088 | (use (const_int 1))])] | |
3089 | "operands[3] = gen_label_rtx ();") | |
3090 | ||
9bb86f41 UW |
3091 | (define_split |
3092 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3093 | (match_operand:BLK 1 "memory_operand" "")) | |
3094 | (use (match_operand 2 "register_operand" "")) | |
3095 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3096 | (clobber (match_operand 3 "register_operand" ""))] | |
3097 | "reload_completed && TARGET_CPU_ZARCH" | |
3098 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3099 | (parallel | |
9381e3f1 | 3100 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3101 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3102 | (set (match_dup 0) (match_dup 1)) | |
3103 | (use (const_int 1))])] | |
3104 | "operands[4] = gen_label_rtx ();") | |
3105 | ||
a41c6c53 | 3106 | ; Move a block of arbitrary length. |
9db1d521 | 3107 | |
70128ad9 | 3108 | (define_expand "movmem_long" |
b9404c99 UW |
3109 | [(parallel |
3110 | [(clobber (match_dup 2)) | |
3111 | (clobber (match_dup 3)) | |
3112 | (set (match_operand:BLK 0 "memory_operand" "") | |
3113 | (match_operand:BLK 1 "memory_operand" "")) | |
3114 | (use (match_operand 2 "general_operand" "")) | |
3115 | (use (match_dup 3)) | |
ae156f85 | 3116 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3117 | "" |
3118 | { | |
ef4bddc2 RS |
3119 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3120 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3121 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3122 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3123 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3124 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3125 | rtx len0 = gen_lowpart (Pmode, reg0); |
3126 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3127 | ||
c41c1387 | 3128 | emit_clobber (reg0); |
b9404c99 UW |
3129 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3130 | emit_move_insn (len0, operands[2]); | |
3131 | ||
c41c1387 | 3132 | emit_clobber (reg1); |
b9404c99 UW |
3133 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3134 | emit_move_insn (len1, operands[2]); | |
3135 | ||
3136 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3137 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3138 | operands[2] = reg0; | |
3139 | operands[3] = reg1; | |
3140 | }) | |
3141 | ||
a1aed706 AS |
3142 | (define_insn "*movmem_long" |
3143 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3144 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3145 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3146 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3147 | (use (match_dup 2)) |
3148 | (use (match_dup 3)) | |
ae156f85 | 3149 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3150 | "TARGET_64BIT || !TARGET_ZARCH" |
3151 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3152 | [(set_attr "length" "8") | |
3153 | (set_attr "type" "vs")]) | |
3154 | ||
3155 | (define_insn "*movmem_long_31z" | |
3156 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3157 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3158 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3159 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3160 | (use (match_dup 2)) | |
3161 | (use (match_dup 3)) | |
3162 | (clobber (reg:CC CC_REGNUM))] | |
3163 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3164 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3165 | [(set_attr "length" "8") |
3166 | (set_attr "type" "vs")]) | |
9db1d521 | 3167 | |
638e37c2 WG |
3168 | |
3169 | ; | |
3170 | ; Test data class. | |
3171 | ; | |
3172 | ||
0f67fa83 WG |
3173 | (define_expand "signbit<mode>2" |
3174 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3175 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3176 | (match_dup 2)] | |
0f67fa83 WG |
3177 | UNSPEC_TDC_INSN)) |
3178 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3179 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3180 | "TARGET_HARD_FLOAT" |
3181 | { | |
3182 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3183 | }) | |
3184 | ||
638e37c2 WG |
3185 | (define_expand "isinf<mode>2" |
3186 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3187 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3188 | (match_dup 2)] | |
638e37c2 WG |
3189 | UNSPEC_TDC_INSN)) |
3190 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3191 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3192 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3193 | { |
3194 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3195 | }) | |
3196 | ||
085261c8 AK |
3197 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3198 | ; instruction will be issued by reload. The constraint of operand 1 | |
3199 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3200 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3201 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3202 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3203 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3204 | UNSPEC_CC_TO_INT))] | |
3205 | "operands != NULL" | |
3206 | "#" | |
3207 | "reload_completed" | |
3208 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3209 | ||
638e37c2 WG |
3210 | ; This insn is used to generate all variants of the Test Data Class |
3211 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3212 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3213 | ; specifying the required test(s). |
638e37c2 | 3214 | ; |
be5de7a1 | 3215 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3216 | (define_insn "*TDC_insn_<mode>" |
3217 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3218 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3219 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3220 | "TARGET_HARD_FLOAT" |
0387c142 | 3221 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3222 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3223 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3224 | |
638e37c2 WG |
3225 | |
3226 | ||
9db1d521 | 3227 | ; |
57e84f18 | 3228 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3229 | ; |
3230 | ||
57e84f18 | 3231 | (define_expand "setmem<mode>" |
a41c6c53 | 3232 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3233 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3234 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3235 | (match_operand 3 "" "")] |
a41c6c53 | 3236 | "" |
6d057022 | 3237 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3238 | |
a41c6c53 | 3239 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3240 | ; The block length is taken as (operands[1] % 256) + 1. |
3241 | ||
70128ad9 | 3242 | (define_expand "clrmem_short" |
b9404c99 UW |
3243 | [(parallel |
3244 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3245 | (const_int 0)) | |
3246 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3247 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3248 | (clobber (match_dup 2)) |
ae156f85 | 3249 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3250 | "" |
3251 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3252 | |
70128ad9 | 3253 | (define_insn "*clrmem_short" |
963fc8d0 | 3254 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3255 | (const_int 0)) |
963fc8d0 AK |
3256 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3257 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3258 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3259 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3260 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3261 | "#" |
963fc8d0 | 3262 | [(set_attr "type" "cs") |
b5e0425c | 3263 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3264 | |
3265 | (define_split | |
3266 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3267 | (const_int 0)) | |
3268 | (use (match_operand 1 "const_int_operand" "")) | |
3269 | (use (match_operand 2 "immediate_operand" "")) | |
3270 | (clobber (scratch)) | |
ae156f85 | 3271 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3272 | "reload_completed" |
3273 | [(parallel | |
3274 | [(set (match_dup 0) (const_int 0)) | |
3275 | (use (match_dup 1)) | |
ae156f85 | 3276 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3277 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3278 | |
9bb86f41 UW |
3279 | (define_split |
3280 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3281 | (const_int 0)) | |
3282 | (use (match_operand 1 "register_operand" "")) | |
3283 | (use (match_operand 2 "memory_operand" "")) | |
3284 | (clobber (scratch)) | |
ae156f85 | 3285 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3286 | "reload_completed" |
3287 | [(parallel | |
3288 | [(unspec [(match_dup 1) (match_dup 2) | |
3289 | (const_int 0)] UNSPEC_EXECUTE) | |
3290 | (set (match_dup 0) (const_int 0)) | |
3291 | (use (const_int 1)) | |
ae156f85 | 3292 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3293 | "") |
9db1d521 | 3294 | |
963fc8d0 AK |
3295 | (define_split |
3296 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3297 | (const_int 0)) | |
3298 | (use (match_operand 1 "register_operand" "")) | |
3299 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3300 | (clobber (scratch)) | |
3301 | (clobber (reg:CC CC_REGNUM))] | |
3302 | "TARGET_Z10 && reload_completed" | |
3303 | [(parallel | |
3304 | [(unspec [(match_dup 1) (const_int 0) | |
3305 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3306 | (set (match_dup 0) (const_int 0)) | |
3307 | (use (const_int 1)) | |
3308 | (clobber (reg:CC CC_REGNUM))])] | |
3309 | "operands[3] = gen_label_rtx ();") | |
3310 | ||
9bb86f41 UW |
3311 | (define_split |
3312 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3313 | (const_int 0)) | |
3314 | (use (match_operand 1 "register_operand" "")) | |
3315 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3316 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3317 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3318 | "reload_completed && TARGET_CPU_ZARCH" |
3319 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3320 | (parallel | |
9381e3f1 | 3321 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3322 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3323 | (set (match_dup 0) (const_int 0)) | |
3324 | (use (const_int 1)) | |
ae156f85 | 3325 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3326 | "operands[3] = gen_label_rtx ();") |
3327 | ||
9381e3f1 | 3328 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3329 | |
da0dcab1 | 3330 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3331 | [(parallel |
3332 | [(clobber (match_dup 1)) | |
3333 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3334 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3335 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3336 | (use (match_dup 3)) |
ae156f85 | 3337 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3338 | "" |
a41c6c53 | 3339 | { |
ef4bddc2 RS |
3340 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3341 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3342 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3343 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3344 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3345 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3346 | |
c41c1387 | 3347 | emit_clobber (reg0); |
b9404c99 UW |
3348 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3349 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3350 | |
b9404c99 | 3351 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3352 | |
b9404c99 UW |
3353 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3354 | operands[1] = reg0; | |
6d057022 | 3355 | operands[3] = reg1; |
da0dcab1 | 3356 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3357 | }) |
a41c6c53 | 3358 | |
da0dcab1 DV |
3359 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3360 | ||
db340c73 | 3361 | (define_insn "*setmem_long" |
a1aed706 | 3362 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3363 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3364 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3365 | (subreg:P (match_dup 3) <modesize>)] |
3366 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3367 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3368 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3369 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3370 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3371 | [(set_attr "length" "8") |
3372 | (set_attr "type" "vs")]) | |
9db1d521 | 3373 | |
db340c73 AK |
3374 | (define_insn "*setmem_long_and" |
3375 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3376 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
3377 | (unspec:BLK [(and:P | |
dd95128b | 3378 | (match_operand:P 2 "setmem_operand" "Y") |
db340c73 AK |
3379 | (match_operand:P 4 "const_int_operand" "n")) |
3380 | (subreg:P (match_dup 3) <modesize>)] | |
3381 | UNSPEC_REPLICATE_BYTE)) | |
3382 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3383 | (clobber (reg:CC CC_REGNUM))] | |
3384 | "(TARGET_64BIT || !TARGET_ZARCH) && | |
3385 | (INTVAL (operands[4]) & 255) == 255" | |
3386 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3387 | [(set_attr "length" "8") | |
3388 | (set_attr "type" "vs")]) | |
3389 | ||
da0dcab1 DV |
3390 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3391 | ; of the SImode subregs. | |
3392 | ||
db340c73 | 3393 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3394 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3395 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3396 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3397 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3398 | (use (match_operand:TI 1 "register_operand" "d")) |
3399 | (clobber (reg:CC CC_REGNUM))] | |
3400 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3401 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3402 | [(set_attr "length" "8") | |
3403 | (set_attr "type" "vs")]) | |
9602b6a1 | 3404 | |
db340c73 AK |
3405 | (define_insn "*setmem_long_and_31z" |
3406 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3407 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
3408 | (unspec:BLK [(and:SI | |
dd95128b AK |
3409 | (match_operand:SI 2 "setmem_operand" "Y") |
3410 | (match_operand:SI 4 "const_int_operand" "n")) | |
db340c73 AK |
3411 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3412 | (use (match_operand:TI 1 "register_operand" "d")) | |
3413 | (clobber (reg:CC CC_REGNUM))] | |
3414 | "(!TARGET_64BIT && TARGET_ZARCH) && | |
3415 | (INTVAL (operands[4]) & 255) == 255" | |
3416 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3417 | [(set_attr "length" "8") | |
3418 | (set_attr "type" "vs")]) | |
3419 | ||
9db1d521 | 3420 | ; |
358b8f01 | 3421 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3422 | ; |
3423 | ||
358b8f01 | 3424 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3425 | [(set (match_operand:SI 0 "register_operand" "") |
3426 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3427 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3428 | (use (match_operand:SI 3 "general_operand" "")) | |
3429 | (use (match_operand:SI 4 "" ""))] | |
3430 | "" | |
367d32f3 AK |
3431 | { |
3432 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3433 | operands[2], operands[3])) | |
3434 | DONE; | |
3435 | else | |
3436 | FAIL; | |
3437 | }) | |
9db1d521 | 3438 | |
a41c6c53 UW |
3439 | ; Compare a block that is up to 256 bytes in length. |
3440 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3441 | |
b9404c99 UW |
3442 | (define_expand "cmpmem_short" |
3443 | [(parallel | |
ae156f85 | 3444 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3445 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3446 | (match_operand:BLK 1 "memory_operand" ""))) |
3447 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3448 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3449 | (clobber (match_dup 3))])] |
3450 | "" | |
3451 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3452 | |
b9404c99 | 3453 | (define_insn "*cmpmem_short" |
ae156f85 | 3454 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3455 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3456 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3457 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3458 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3459 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3460 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3461 | "#" |
963fc8d0 | 3462 | [(set_attr "type" "cs") |
b5e0425c | 3463 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3464 | |
9bb86f41 | 3465 | (define_split |
ae156f85 | 3466 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3467 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3468 | (match_operand:BLK 1 "memory_operand" ""))) | |
3469 | (use (match_operand 2 "const_int_operand" "")) | |
3470 | (use (match_operand 3 "immediate_operand" "")) | |
3471 | (clobber (scratch))] | |
3472 | "reload_completed" | |
3473 | [(parallel | |
ae156f85 | 3474 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3475 | (use (match_dup 2))])] |
3476 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3477 | |
9bb86f41 | 3478 | (define_split |
ae156f85 | 3479 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3480 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3481 | (match_operand:BLK 1 "memory_operand" ""))) | |
3482 | (use (match_operand 2 "register_operand" "")) | |
3483 | (use (match_operand 3 "memory_operand" "")) | |
3484 | (clobber (scratch))] | |
3485 | "reload_completed" | |
3486 | [(parallel | |
3487 | [(unspec [(match_dup 2) (match_dup 3) | |
3488 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3489 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3490 | (use (const_int 1))])] |
3491 | "") | |
3492 | ||
963fc8d0 AK |
3493 | (define_split |
3494 | [(set (reg:CCU CC_REGNUM) | |
3495 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3496 | (match_operand:BLK 1 "memory_operand" ""))) | |
3497 | (use (match_operand 2 "register_operand" "")) | |
3498 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3499 | (clobber (scratch))] | |
3500 | "TARGET_Z10 && reload_completed" | |
3501 | [(parallel | |
3502 | [(unspec [(match_dup 2) (const_int 0) | |
3503 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3504 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3505 | (use (const_int 1))])] | |
3506 | "operands[4] = gen_label_rtx ();") | |
3507 | ||
9bb86f41 | 3508 | (define_split |
ae156f85 | 3509 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3510 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3511 | (match_operand:BLK 1 "memory_operand" ""))) | |
3512 | (use (match_operand 2 "register_operand" "")) | |
3513 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3514 | (clobber (match_operand 3 "register_operand" ""))] | |
3515 | "reload_completed && TARGET_CPU_ZARCH" | |
3516 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3517 | (parallel | |
9381e3f1 | 3518 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3519 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3520 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3521 | (use (const_int 1))])] |
3522 | "operands[4] = gen_label_rtx ();") | |
3523 | ||
a41c6c53 | 3524 | ; Compare a block of arbitrary length. |
9db1d521 | 3525 | |
b9404c99 UW |
3526 | (define_expand "cmpmem_long" |
3527 | [(parallel | |
3528 | [(clobber (match_dup 2)) | |
3529 | (clobber (match_dup 3)) | |
ae156f85 | 3530 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3531 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3532 | (match_operand:BLK 1 "memory_operand" ""))) |
3533 | (use (match_operand 2 "general_operand" "")) | |
3534 | (use (match_dup 3))])] | |
3535 | "" | |
3536 | { | |
ef4bddc2 RS |
3537 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3538 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3539 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3540 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3541 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3542 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3543 | rtx len0 = gen_lowpart (Pmode, reg0); |
3544 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3545 | ||
c41c1387 | 3546 | emit_clobber (reg0); |
b9404c99 UW |
3547 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3548 | emit_move_insn (len0, operands[2]); | |
3549 | ||
c41c1387 | 3550 | emit_clobber (reg1); |
b9404c99 UW |
3551 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3552 | emit_move_insn (len1, operands[2]); | |
3553 | ||
3554 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3555 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3556 | operands[2] = reg0; | |
3557 | operands[3] = reg1; | |
3558 | }) | |
3559 | ||
a1aed706 AS |
3560 | (define_insn "*cmpmem_long" |
3561 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3562 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3563 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3564 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3565 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3566 | (use (match_dup 2)) |
3567 | (use (match_dup 3))] | |
9602b6a1 | 3568 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3569 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3570 | [(set_attr "length" "8") |
3571 | (set_attr "type" "vs")]) | |
9db1d521 | 3572 | |
9602b6a1 AK |
3573 | (define_insn "*cmpmem_long_31z" |
3574 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3575 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3576 | (set (reg:CCU CC_REGNUM) | |
3577 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3578 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3579 | (use (match_dup 2)) | |
3580 | (use (match_dup 3))] | |
3581 | "!TARGET_64BIT && TARGET_ZARCH" | |
3582 | "clcle\t%0,%1,0\;jo\t.-4" | |
3583 | [(set_attr "op_type" "NN") | |
3584 | (set_attr "type" "vs") | |
3585 | (set_attr "length" "8")]) | |
3586 | ||
02887425 UW |
3587 | ; Convert CCUmode condition code to integer. |
3588 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3589 | |
02887425 | 3590 | (define_insn_and_split "cmpint" |
9db1d521 | 3591 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3592 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3593 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3594 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3595 | "" |
02887425 UW |
3596 | "#" |
3597 | "reload_completed" | |
3598 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3599 | (parallel | |
3600 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3601 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3602 | |
3603 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3604 | [(set (reg CC_REGNUM) |
02887425 | 3605 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3606 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3607 | (const_int 0))) |
3608 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3609 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3610 | "s390_match_ccmode (insn, CCSmode)" |
3611 | "#" | |
3612 | "&& reload_completed" | |
3613 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3614 | (parallel | |
3615 | [(set (match_dup 2) (match_dup 3)) | |
3616 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3617 | { |
02887425 UW |
3618 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3619 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3620 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3621 | }) | |
9db1d521 | 3622 | |
02887425 | 3623 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3624 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3625 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3626 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3627 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3628 | "TARGET_ZARCH" |
02887425 UW |
3629 | "#" |
3630 | "&& reload_completed" | |
3631 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3632 | (parallel | |
3633 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3634 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3635 | |
3636 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3637 | [(set (reg CC_REGNUM) |
9381e3f1 | 3638 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3639 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3640 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3641 | (const_int 32)) (const_int 32)) |
3642 | (const_int 0))) | |
3643 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3644 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3645 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3646 | "#" |
3647 | "&& reload_completed" | |
3648 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3649 | (parallel | |
3650 | [(set (match_dup 2) (match_dup 3)) | |
3651 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3652 | { |
02887425 UW |
3653 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3654 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3655 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3656 | }) | |
9db1d521 | 3657 | |
4023fb28 | 3658 | |
9db1d521 HP |
3659 | ;; |
3660 | ;;- Conversion instructions. | |
3661 | ;; | |
3662 | ||
6fa05db6 | 3663 | (define_insn "*sethighpartsi" |
d3632d41 | 3664 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3665 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3666 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3667 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3668 | "" |
d3632d41 | 3669 | "@ |
6fa05db6 AS |
3670 | icm\t%0,%2,%S1 |
3671 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3672 | [(set_attr "op_type" "RS,RSY") |
3673 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3674 | |
6fa05db6 | 3675 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3676 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3677 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3678 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3679 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3680 | "TARGET_ZARCH" |
6fa05db6 | 3681 | "icmh\t%0,%2,%S1" |
729e750f WG |
3682 | [(set_attr "op_type" "RSY") |
3683 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3684 | |
6fa05db6 | 3685 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3686 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3687 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3688 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3689 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3690 | "!TARGET_ZARCH" |
d3632d41 | 3691 | "@ |
6fa05db6 AS |
3692 | icm\t%0,%2,%S1 |
3693 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3694 | [(set_attr "op_type" "RS,RSY") |
3695 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3696 | ||
1a2e356e RH |
3697 | ; |
3698 | ; extv instruction patterns | |
3699 | ; | |
3700 | ||
3701 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3702 | ; after resolving some issues with it. | |
3703 | ||
3704 | (define_expand "extzv" | |
3705 | [(parallel | |
3706 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3707 | (zero_extract:DI | |
3708 | (match_operand:DI 1 "register_operand" "d") | |
3709 | (match_operand 2 "const_int_operand" "") ; size | |
3710 | (match_operand 3 "const_int_operand" ""))) ; start | |
3711 | (clobber (reg:CC CC_REGNUM))])] | |
3712 | "TARGET_Z10" | |
3713 | { | |
3714 | /* Starting with zEC12 there is risbgn not clobbering CC. */ | |
3715 | if (TARGET_ZEC12) | |
3716 | { | |
3717 | emit_move_insn (operands[0], | |
3718 | gen_rtx_ZERO_EXTRACT (DImode, | |
3719 | operands[1], | |
3720 | operands[2], | |
3721 | operands[3])); | |
3722 | DONE; | |
3723 | } | |
3724 | }) | |
3725 | ||
3726 | (define_insn "*extzv<mode>_zEC12" | |
3727 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3728 | (zero_extract:GPR | |
3729 | (match_operand:GPR 1 "register_operand" "d") | |
3730 | (match_operand 2 "const_int_operand" "") ; size | |
3731 | (match_operand 3 "const_int_operand" "")))] ; start] | |
3732 | "TARGET_ZEC12" | |
3733 | "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3734 | [(set_attr "op_type" "RIE")]) | |
3735 | ||
3736 | (define_insn "*extzv<mode>_z10" | |
3737 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3738 | (zero_extract:GPR | |
3739 | (match_operand:GPR 1 "register_operand" "d") | |
3740 | (match_operand 2 "const_int_operand" "") ; size | |
3741 | (match_operand 3 "const_int_operand" ""))) ; start | |
3742 | (clobber (reg:CC CC_REGNUM))] | |
3743 | "TARGET_Z10" | |
3744 | "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3745 | [(set_attr "op_type" "RIE") | |
3746 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3747 | |
1a2e356e | 3748 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 AS |
3749 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3750 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3751 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3752 | (const_int 0))) |
ae156f85 | 3753 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3754 | "!TARGET_Z10" |
cc7ab9b7 UW |
3755 | "#" |
3756 | "&& reload_completed" | |
4023fb28 | 3757 | [(parallel |
6fa05db6 | 3758 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3759 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3760 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3761 | { |
6fa05db6 AS |
3762 | int bitsize = INTVAL (operands[2]); |
3763 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3764 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3765 | ||
3766 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3767 | set_mem_size (operands[1], size); |
2542ef05 | 3768 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3769 | operands[3] = GEN_INT (mask); |
b628bd8e | 3770 | }) |
4023fb28 | 3771 | |
1a2e356e | 3772 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 AS |
3773 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3774 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3775 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3776 | (const_int 0))) |
ae156f85 | 3777 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3778 | "" |
cc7ab9b7 UW |
3779 | "#" |
3780 | "&& reload_completed" | |
4023fb28 | 3781 | [(parallel |
6fa05db6 | 3782 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3783 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3784 | (parallel |
3785 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3786 | (clobber (reg:CC CC_REGNUM))])] | |
3787 | { | |
3788 | int bitsize = INTVAL (operands[2]); | |
3789 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3790 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3791 | ||
3792 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3793 | set_mem_size (operands[1], size); |
2542ef05 | 3794 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3795 | operands[3] = GEN_INT (mask); |
3796 | }) | |
3797 | ||
3798 | ; | |
3799 | ; insv instruction patterns | |
3800 | ; | |
3801 | ||
3802 | (define_expand "insv" | |
3803 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3804 | (match_operand 1 "const_int_operand" "") | |
3805 | (match_operand 2 "const_int_operand" "")) | |
3806 | (match_operand 3 "general_operand" ""))] | |
3807 | "" | |
4023fb28 | 3808 | { |
6fa05db6 AS |
3809 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3810 | DONE; | |
3811 | FAIL; | |
b628bd8e | 3812 | }) |
4023fb28 | 3813 | |
2542ef05 RH |
3814 | |
3815 | ; The normal RTL expansion will never generate a zero_extract where | |
3816 | ; the location operand isn't word mode. However, we do this in the | |
3817 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
22ac2c2f AK |
3818 | (define_insn "*insv<mode>_zEC12" |
3819 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3820 | (match_operand 1 "const_int_operand" "I") ; size |
3821 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f AK |
3822 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
3823 | "TARGET_ZEC12 | |
2542ef05 RH |
3824 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3825 | "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
22ac2c2f AK |
3826 | [(set_attr "op_type" "RIE")]) |
3827 | ||
963fc8d0 AK |
3828 | (define_insn "*insv<mode>_z10" |
3829 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3830 | (match_operand 1 "const_int_operand" "I") ; size |
3831 | (match_operand 2 "const_int_operand" "I")) ; pos | |
963fc8d0 AK |
3832 | (match_operand:GPR 3 "nonimmediate_operand" "d")) |
3833 | (clobber (reg:CC CC_REGNUM))] | |
3834 | "TARGET_Z10 | |
2542ef05 RH |
3835 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3836 | "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
9381e3f1 WG |
3837 | [(set_attr "op_type" "RIE") |
3838 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3839 | |
22ac2c2f AK |
3840 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3841 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3842 | (define_insn "*insv<mode>_zEC12_noshift" | |
3843 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3844 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3845 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
22ac2c2f | 3846 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 RH |
3847 | (match_operand:GPR 4 "const_int_operand" ""))))] |
3848 | "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3849 | "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
22ac2c2f AK |
3850 | [(set_attr "op_type" "RIE")]) |
3851 | ||
963fc8d0 AK |
3852 | (define_insn "*insv<mode>_z10_noshift" |
3853 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3854 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3855 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
963fc8d0 | 3856 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 | 3857 | (match_operand:GPR 4 "const_int_operand" "")))) |
963fc8d0 | 3858 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 RH |
3859 | "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3860 | "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
9381e3f1 WG |
3861 | [(set_attr "op_type" "RIE") |
3862 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3863 | |
3d44ff99 AK |
3864 | ; Implement appending Y on the left of S bits of X |
3865 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
3866 | (define_insn "*insv<mode>_zEC12_appendbitsleft" | |
3867 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3868 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
3869 | (match_operand:GPR 2 "immediate_operand" "")) | |
3870 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
3871 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
3872 | "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
3873 | "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4" | |
3874 | [(set_attr "op_type" "RIE") | |
3875 | (set_attr "z10prop" "z10_super_E1")]) | |
3876 | ||
3877 | (define_insn "*insv<mode>_z10_appendbitsleft" | |
3878 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3879 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
3880 | (match_operand:GPR 2 "immediate_operand" "")) | |
3881 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
3882 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
3883 | (clobber (reg:CC CC_REGNUM))] | |
3884 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
3885 | "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4" | |
3886 | [(set_attr "op_type" "RIE") | |
3887 | (set_attr "z10prop" "z10_super_E1")]) | |
3888 | ||
3889 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
3890 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
3891 | ; -> z = y >> d; z = risbg; | |
3892 | ||
3893 | (define_split | |
3894 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
3895 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3896 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
3897 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
3898 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
3899 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 3900 | [(set (match_dup 6) |
3d44ff99 AK |
3901 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
3902 | (set (match_dup 0) | |
1d11f7ce | 3903 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
3904 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
3905 | { | |
3906 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
1d11f7ce AK |
3907 | if (rtx_equal_p (operands[0], operands[3])) |
3908 | { | |
3909 | if (!can_create_pseudo_p ()) | |
3910 | FAIL; | |
3911 | operands[6] = gen_reg_rtx (<MODE>mode); | |
3912 | } | |
3913 | else | |
3914 | operands[6] = operands[0]; | |
3d44ff99 AK |
3915 | }) |
3916 | ||
3917 | (define_split | |
3918 | [(parallel | |
3919 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
3920 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3921 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
3922 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
3923 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
3924 | (clobber (reg:CC CC_REGNUM))])] | |
3925 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 3926 | [(set (match_dup 6) |
3d44ff99 AK |
3927 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
3928 | (parallel | |
3929 | [(set (match_dup 0) | |
1d11f7ce | 3930 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
3931 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
3932 | (clobber (reg:CC CC_REGNUM))])] | |
3933 | { | |
3934 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
1d11f7ce AK |
3935 | if (rtx_equal_p (operands[0], operands[3])) |
3936 | { | |
3937 | if (!can_create_pseudo_p ()) | |
3938 | FAIL; | |
3939 | operands[6] = gen_reg_rtx (<MODE>mode); | |
3940 | } | |
3941 | else | |
3942 | operands[6] = operands[0]; | |
3d44ff99 AK |
3943 | }) |
3944 | ||
571e408a | 3945 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 3946 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
3947 | (IXOR:GPR |
3948 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3949 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3950 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 3951 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 3952 | "TARGET_Z10" |
571e408a RH |
3953 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
3954 | [(set_attr "op_type" "RIE")]) | |
3955 | ||
3956 | (define_insn "*r<noxa>sbg_di_rotl" | |
3957 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
3958 | (IXOR:DI | |
3959 | (and:DI | |
3960 | (rotate:DI | |
3961 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
3962 | (match_operand:DI 3 "const_int_operand" "")) | |
3963 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
3964 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
3965 | (clobber (reg:CC CC_REGNUM))] | |
3966 | "TARGET_Z10" | |
3967 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
3968 | [(set_attr "op_type" "RIE")]) | |
3969 | ||
3970 | (define_insn "*r<noxa>sbg_<mode>_srl" | |
3971 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3972 | (IXOR:GPR | |
3973 | (and:GPR | |
3974 | (lshiftrt:GPR | |
3975 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3976 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3977 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3978 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3979 | (clobber (reg:CC CC_REGNUM))] | |
3980 | "TARGET_Z10 | |
3981 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
3982 | INTVAL (operands[2]))" | |
3983 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
3984 | [(set_attr "op_type" "RIE")]) | |
3985 | ||
3986 | (define_insn "*r<noxa>sbg_<mode>_sll" | |
3987 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3988 | (IXOR:GPR | |
3989 | (and:GPR | |
3990 | (ashift:GPR | |
3991 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3992 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3993 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3994 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3995 | (clobber (reg:CC CC_REGNUM))] | |
3996 | "TARGET_Z10 | |
3997 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
3998 | INTVAL (operands[2]))" | |
3999 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4000 | [(set_attr "op_type" "RIE")]) |
4001 | ||
5bb33936 RH |
4002 | ;; These two are generated by combine for s.bf &= val. |
4003 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4004 | ;; shifts and ands, which results in some truly awful patterns | |
4005 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4006 | ;; Instead of | |
4007 | ;; | |
4008 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4009 | ;; (const_int 24 [0x18]) | |
4010 | ;; (const_int 0 [0])) | |
4011 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4012 | ;; (const_int 40 [0x28])) 4) | |
4013 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4014 | ;; | |
4015 | ;; we should instead generate | |
4016 | ;; | |
4017 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4018 | ;; (const_int 24 [0x18]) | |
4019 | ;; (const_int 0 [0])) | |
4020 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4021 | ;; (const_int 40 [0x28])) | |
4022 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4023 | ;; | |
4024 | ;; by noticing that we can push down the outer paradoxical subreg | |
4025 | ;; into the operation. | |
4026 | ||
4027 | (define_insn "*insv_rnsbg_noshift" | |
4028 | [(set (zero_extract:DI | |
4029 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4030 | (match_operand 1 "const_int_operand" "") | |
4031 | (match_operand 2 "const_int_operand" "")) | |
4032 | (and:DI | |
4033 | (match_dup 0) | |
4034 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4035 | (clobber (reg:CC CC_REGNUM))] | |
4036 | "TARGET_Z10 | |
4037 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" | |
4038 | "rnsbg\t%0,%3,%2,63,0" | |
4039 | [(set_attr "op_type" "RIE")]) | |
4040 | ||
4041 | (define_insn "*insv_rnsbg_srl" | |
4042 | [(set (zero_extract:DI | |
4043 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4044 | (match_operand 1 "const_int_operand" "") | |
4045 | (match_operand 2 "const_int_operand" "")) | |
4046 | (and:DI | |
4047 | (lshiftrt:DI | |
4048 | (match_dup 0) | |
4049 | (match_operand 3 "const_int_operand" "")) | |
4050 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4051 | (clobber (reg:CC CC_REGNUM))] | |
4052 | "TARGET_Z10 | |
4053 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" | |
4054 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4055 | [(set_attr "op_type" "RIE")]) | |
4056 | ||
6fa05db6 | 4057 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4058 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4059 | (match_operand 1 "const_int_operand" "n,n") |
4060 | (const_int 0)) | |
9602b6a1 | 4061 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
4062 | "INTVAL (operands[1]) > 0 |
4063 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4064 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4065 | { | |
4066 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4067 | ||
4068 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4069 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4070 | : "stcmy\t%2,%1,%S0"; |
4071 | } | |
9381e3f1 WG |
4072 | [(set_attr "op_type" "RS,RSY") |
4073 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
4074 | |
4075 | (define_insn "*insvdi_mem_reghigh" | |
4076 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
4077 | (match_operand 1 "const_int_operand" "n") | |
4078 | (const_int 0)) | |
4079 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4080 | (const_int 32)))] | |
9602b6a1 | 4081 | "TARGET_ZARCH |
6fa05db6 AS |
4082 | && INTVAL (operands[1]) > 0 |
4083 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4084 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4085 | { | |
4086 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4087 | ||
4088 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4089 | return "stcmh\t%2,%1,%S0"; | |
4090 | } | |
9381e3f1 WG |
4091 | [(set_attr "op_type" "RSY") |
4092 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4093 | |
9602b6a1 AK |
4094 | (define_insn "*insvdi_reg_imm" |
4095 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4096 | (const_int 16) | |
4097 | (match_operand 1 "const_int_operand" "n")) | |
4098 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
4099 | "TARGET_ZARCH |
4100 | && INTVAL (operands[1]) >= 0 | |
4101 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4102 | && INTVAL (operands[1]) % 16 == 0" | |
4103 | { | |
4104 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4105 | { | |
4106 | case 64: return "iihh\t%0,%x2"; break; | |
4107 | case 48: return "iihl\t%0,%x2"; break; | |
4108 | case 32: return "iilh\t%0,%x2"; break; | |
4109 | case 16: return "iill\t%0,%x2"; break; | |
4110 | default: gcc_unreachable(); | |
4111 | } | |
4112 | } | |
9381e3f1 WG |
4113 | [(set_attr "op_type" "RI") |
4114 | (set_attr "z10prop" "z10_super_E1")]) | |
4115 | ||
9fec758d WG |
4116 | ; Update the left-most 32 bit of a DI. |
4117 | (define_insn "*insv_h_di_reg_extimm" | |
4118 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4119 | (const_int 32) | |
4120 | (const_int 0)) | |
4121 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4122 | "TARGET_EXTIMM" | |
4123 | "iihf\t%0,%o1" | |
4124 | [(set_attr "op_type" "RIL") | |
4125 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4126 | |
d378b983 RH |
4127 | ; Update the right-most 32 bit of a DI. |
4128 | (define_insn "*insv_l_di_reg_extimm" | |
4129 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4130 | (const_int 32) | |
4131 | (const_int 32)) | |
4132 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4133 | "TARGET_EXTIMM" | |
4134 | "iilf\t%0,%o1" | |
9381e3f1 | 4135 | [(set_attr "op_type" "RIL") |
9fec758d | 4136 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4137 | |
9db1d521 HP |
4138 | ; |
4139 | ; extendsidi2 instruction pattern(s). | |
4140 | ; | |
4141 | ||
4023fb28 UW |
4142 | (define_expand "extendsidi2" |
4143 | [(set (match_operand:DI 0 "register_operand" "") | |
4144 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4145 | "" | |
4023fb28 | 4146 | { |
9602b6a1 | 4147 | if (!TARGET_ZARCH) |
4023fb28 | 4148 | { |
c41c1387 | 4149 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4150 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4151 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4152 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4153 | DONE; |
4154 | } | |
ec24698e | 4155 | }) |
4023fb28 UW |
4156 | |
4157 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
4158 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4159 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 4160 | "TARGET_ZARCH" |
9db1d521 | 4161 | "@ |
d40c829f | 4162 | lgfr\t%0,%1 |
963fc8d0 AK |
4163 | lgf\t%0,%1 |
4164 | lgfrl\t%0,%1" | |
4165 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4166 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4167 | (set_attr "cpu_facility" "*,*,z10") |
4168 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4169 | |
9db1d521 | 4170 | ; |
56477c21 | 4171 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4172 | ; |
4173 | ||
56477c21 AS |
4174 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4175 | [(set (match_operand:DSI 0 "register_operand" "") | |
4176 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4177 | "" |
4023fb28 | 4178 | { |
9602b6a1 | 4179 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4180 | { |
4181 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4182 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4183 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4184 | DONE; | |
4185 | } | |
ec24698e | 4186 | else if (!TARGET_EXTIMM) |
4023fb28 | 4187 | { |
2542ef05 | 4188 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4189 | |
4190 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4191 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4192 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4193 | DONE; |
4194 | } | |
ec24698e UW |
4195 | }) |
4196 | ||
56477c21 AS |
4197 | ; |
4198 | ; extendhidi2 instruction pattern(s). | |
4199 | ; | |
4200 | ||
ec24698e | 4201 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
4202 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4203 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 4204 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4205 | "@ |
4206 | lghr\t%0,%1 | |
963fc8d0 AK |
4207 | lgh\t%0,%1 |
4208 | lghrl\t%0,%1" | |
4209 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4210 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4211 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4212 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4213 | |
4214 | (define_insn "*extendhidi2" | |
9db1d521 | 4215 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 4216 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 4217 | "TARGET_ZARCH" |
d40c829f | 4218 | "lgh\t%0,%1" |
9381e3f1 WG |
4219 | [(set_attr "op_type" "RXY") |
4220 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4221 | |
9db1d521 | 4222 | ; |
56477c21 | 4223 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4224 | ; |
4225 | ||
ec24698e | 4226 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4227 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4228 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4229 | "TARGET_EXTIMM" |
4230 | "@ | |
4231 | lhr\t%0,%1 | |
4232 | lh\t%0,%1 | |
963fc8d0 AK |
4233 | lhy\t%0,%1 |
4234 | lhrl\t%0,%1" | |
4235 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4236 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4237 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4238 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4239 | |
4023fb28 | 4240 | (define_insn "*extendhisi2" |
d3632d41 UW |
4241 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4242 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4243 | "!TARGET_EXTIMM" |
d3632d41 | 4244 | "@ |
d40c829f UW |
4245 | lh\t%0,%1 |
4246 | lhy\t%0,%1" | |
9381e3f1 WG |
4247 | [(set_attr "op_type" "RX,RXY") |
4248 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4249 | |
56477c21 AS |
4250 | ; |
4251 | ; extendqi(si|di)2 instruction pattern(s). | |
4252 | ; | |
4253 | ||
43a09b63 | 4254 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4255 | (define_insn "*extendqi<mode>2_extimm" |
4256 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4257 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4258 | "TARGET_EXTIMM" |
4259 | "@ | |
56477c21 AS |
4260 | l<g>br\t%0,%1 |
4261 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4262 | [(set_attr "op_type" "RRE,RXY") |
4263 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4264 | |
43a09b63 | 4265 | ; lb, lgb |
56477c21 AS |
4266 | (define_insn "*extendqi<mode>2" |
4267 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4268 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
4269 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4270 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4271 | [(set_attr "op_type" "RXY") |
4272 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4273 | |
56477c21 AS |
4274 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4275 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4276 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4277 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4278 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4279 | "#" |
4280 | "&& reload_completed" | |
4023fb28 | 4281 | [(parallel |
56477c21 | 4282 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4283 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4284 | (parallel |
56477c21 | 4285 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4286 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4287 | { |
4288 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4289 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4290 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4291 | }) |
9db1d521 | 4292 | |
9db1d521 HP |
4293 | ; |
4294 | ; zero_extendsidi2 instruction pattern(s). | |
4295 | ; | |
4296 | ||
4023fb28 UW |
4297 | (define_expand "zero_extendsidi2" |
4298 | [(set (match_operand:DI 0 "register_operand" "") | |
4299 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4300 | "" | |
4023fb28 | 4301 | { |
9602b6a1 | 4302 | if (!TARGET_ZARCH) |
4023fb28 | 4303 | { |
c41c1387 | 4304 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4305 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4306 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4307 | DONE; |
4308 | } | |
ec24698e | 4309 | }) |
4023fb28 UW |
4310 | |
4311 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
4312 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4313 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 4314 | "TARGET_ZARCH" |
9db1d521 | 4315 | "@ |
d40c829f | 4316 | llgfr\t%0,%1 |
963fc8d0 AK |
4317 | llgf\t%0,%1 |
4318 | llgfrl\t%0,%1" | |
4319 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4320 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4321 | (set_attr "cpu_facility" "*,*,z10") |
4322 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4323 | |
288e517f AK |
4324 | ; |
4325 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4326 | ; | |
4327 | ||
d6083c7d UW |
4328 | (define_insn "*llgt_sidi" |
4329 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 4330 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 4331 | (const_int 2147483647)))] |
9602b6a1 | 4332 | "TARGET_ZARCH" |
d6083c7d | 4333 | "llgt\t%0,%1" |
9381e3f1 WG |
4334 | [(set_attr "op_type" "RXE") |
4335 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4336 | |
4337 | (define_insn_and_split "*llgt_sidi_split" | |
4338 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 4339 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 4340 | (const_int 2147483647))) |
ae156f85 | 4341 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4342 | "TARGET_ZARCH" |
d6083c7d UW |
4343 | "#" |
4344 | "&& reload_completed" | |
4345 | [(set (match_dup 0) | |
4346 | (and:DI (subreg:DI (match_dup 1) 0) | |
4347 | (const_int 2147483647)))] | |
4348 | "") | |
4349 | ||
288e517f AK |
4350 | (define_insn "*llgt_sisi" |
4351 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 4352 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 4353 | (const_int 2147483647)))] |
c4d50129 | 4354 | "TARGET_ZARCH" |
288e517f AK |
4355 | "@ |
4356 | llgtr\t%0,%1 | |
4357 | llgt\t%0,%1" | |
9381e3f1 WG |
4358 | [(set_attr "op_type" "RRE,RXE") |
4359 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4360 | |
288e517f AK |
4361 | (define_insn "*llgt_didi" |
4362 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4363 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4364 | (const_int 2147483647)))] | |
9602b6a1 | 4365 | "TARGET_ZARCH" |
288e517f AK |
4366 | "@ |
4367 | llgtr\t%0,%1 | |
4368 | llgt\t%0,%N1" | |
9381e3f1 WG |
4369 | [(set_attr "op_type" "RRE,RXE") |
4370 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4371 | |
f19a9af7 | 4372 | (define_split |
9602b6a1 AK |
4373 | [(set (match_operand:DSI 0 "register_operand" "") |
4374 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4375 | (const_int 2147483647))) |
ae156f85 | 4376 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4377 | "TARGET_ZARCH && reload_completed" |
288e517f | 4378 | [(set (match_dup 0) |
9602b6a1 | 4379 | (and:DSI (match_dup 1) |
f6ee577c | 4380 | (const_int 2147483647)))] |
288e517f AK |
4381 | "") |
4382 | ||
9db1d521 | 4383 | ; |
56477c21 | 4384 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4385 | ; |
4386 | ||
56477c21 AS |
4387 | (define_expand "zero_extend<mode>di2" |
4388 | [(set (match_operand:DI 0 "register_operand" "") | |
4389 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4390 | "" | |
4391 | { | |
9602b6a1 | 4392 | if (!TARGET_ZARCH) |
56477c21 AS |
4393 | { |
4394 | rtx tmp = gen_reg_rtx (SImode); | |
4395 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4396 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4397 | DONE; | |
4398 | } | |
4399 | else if (!TARGET_EXTIMM) | |
4400 | { | |
2542ef05 | 4401 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4402 | operands[1] = gen_lowpart (DImode, operands[1]); |
4403 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4404 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4405 | DONE; | |
4406 | } | |
4407 | }) | |
4408 | ||
f6ee577c | 4409 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4410 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4411 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4412 | "" |
4023fb28 | 4413 | { |
ec24698e UW |
4414 | if (!TARGET_EXTIMM) |
4415 | { | |
4416 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4417 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4418 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4419 | DONE; |
56477c21 | 4420 | } |
ec24698e UW |
4421 | }) |
4422 | ||
963fc8d0 AK |
4423 | ; llhrl, llghrl |
4424 | (define_insn "*zero_extendhi<mode>2_z10" | |
4425 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4426 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
4427 | "TARGET_Z10" | |
4428 | "@ | |
4429 | ll<g>hr\t%0,%1 | |
4430 | ll<g>h\t%0,%1 | |
4431 | ll<g>hrl\t%0,%1" | |
4432 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4433 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4434 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4435 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4436 | |
43a09b63 | 4437 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4438 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4439 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4440 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4441 | "TARGET_EXTIMM" |
4442 | "@ | |
56477c21 AS |
4443 | ll<g><hc>r\t%0,%1 |
4444 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4445 | [(set_attr "op_type" "RRE,RXY") |
4446 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4447 | |
43a09b63 | 4448 | ; llgh, llgc |
56477c21 AS |
4449 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4450 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4451 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 4452 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4453 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4454 | [(set_attr "op_type" "RXY") |
4455 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4456 | |
4457 | (define_insn_and_split "*zero_extendhisi2_31" | |
4458 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 4459 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 4460 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4461 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4462 | "#" |
4463 | "&& reload_completed" | |
4464 | [(set (match_dup 0) (const_int 0)) | |
4465 | (parallel | |
4466 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4467 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4468 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4469 | |
cc7ab9b7 UW |
4470 | (define_insn_and_split "*zero_extendqisi2_31" |
4471 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 4472 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4473 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4474 | "#" |
4475 | "&& reload_completed" | |
4476 | [(set (match_dup 0) (const_int 0)) | |
4477 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4478 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4479 | |
9db1d521 HP |
4480 | ; |
4481 | ; zero_extendqihi2 instruction pattern(s). | |
4482 | ; | |
4483 | ||
9db1d521 HP |
4484 | (define_expand "zero_extendqihi2" |
4485 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4486 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4487 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4488 | { |
4023fb28 UW |
4489 | operands[1] = gen_lowpart (HImode, operands[1]); |
4490 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4491 | DONE; | |
ec24698e | 4492 | }) |
9db1d521 | 4493 | |
4023fb28 | 4494 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4495 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 4496 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 4497 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4498 | "llgc\t%0,%1" |
9381e3f1 WG |
4499 | [(set_attr "op_type" "RXY") |
4500 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4501 | |
cc7ab9b7 UW |
4502 | (define_insn_and_split "*zero_extendqihi2_31" |
4503 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 4504 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4505 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4506 | "#" |
4507 | "&& reload_completed" | |
4508 | [(set (match_dup 0) (const_int 0)) | |
4509 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4510 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4511 | |
609e7e80 AK |
4512 | ; |
4513 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
4514 | ; | |
4515 | ||
4516 | (define_expand "fixuns_truncdddi2" | |
4517 | [(parallel | |
4518 | [(set (match_operand:DI 0 "register_operand" "") | |
4519 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
ae8e301e | 4520 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4521 | (clobber (reg:CC CC_REGNUM))])] |
9381e3f1 | 4522 | |
fb068247 | 4523 | "TARGET_HARD_DFP" |
609e7e80 | 4524 | { |
65b1d8ea AK |
4525 | if (!TARGET_Z196) |
4526 | { | |
19f8b229 TS |
4527 | rtx_code_label *label1 = gen_label_rtx (); |
4528 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4529 | rtx temp = gen_reg_rtx (TDmode); |
4530 | REAL_VALUE_TYPE cmp, sub; | |
4531 | ||
4532 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4533 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4534 | ||
4535 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4536 | solution is doing the check and the subtraction in TD mode and using a | |
4537 | TD -> DI convert afterwards. */ | |
4538 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4539 | temp = force_reg (TDmode, temp); | |
4540 | emit_cmp_and_jump_insns (temp, | |
555affd7 | 4541 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4542 | LT, NULL_RTX, VOIDmode, 0, label1); |
4543 | emit_insn (gen_subtd3 (temp, temp, | |
555affd7 | 4544 | const_double_from_real_value (sub, TDmode))); |
ae8e301e AK |
4545 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, |
4546 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
65b1d8ea AK |
4547 | emit_jump (label2); |
4548 | ||
4549 | emit_label (label1); | |
ae8e301e AK |
4550 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], |
4551 | GEN_INT (DFP_RND_TOWARD_0))); | |
65b1d8ea AK |
4552 | emit_label (label2); |
4553 | DONE; | |
4554 | } | |
609e7e80 AK |
4555 | }) |
4556 | ||
4557 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
4558 | [(parallel |
4559 | [(set (match_operand:DI 0 "register_operand" "") | |
4560 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
ae8e301e | 4561 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4562 | (clobber (reg:CC CC_REGNUM))])] |
4563 | ||
fb068247 | 4564 | "TARGET_HARD_DFP" |
609e7e80 | 4565 | { |
65b1d8ea AK |
4566 | if (!TARGET_Z196) |
4567 | { | |
19f8b229 TS |
4568 | rtx_code_label *label1 = gen_label_rtx (); |
4569 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4570 | rtx temp = gen_reg_rtx (TDmode); |
4571 | REAL_VALUE_TYPE cmp, sub; | |
4572 | ||
4573 | operands[1] = force_reg (TDmode, operands[1]); | |
4574 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4575 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4576 | ||
4577 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4578 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4579 | LT, NULL_RTX, VOIDmode, 0, label1); |
4580 | emit_insn (gen_subtd3 (temp, operands[1], | |
555affd7 | 4581 | const_double_from_real_value (sub, TDmode))); |
ae8e301e AK |
4582 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, |
4583 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
65b1d8ea AK |
4584 | emit_jump (label2); |
4585 | ||
4586 | emit_label (label1); | |
ae8e301e AK |
4587 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], |
4588 | GEN_INT (DFP_RND_TOWARD_0))); | |
65b1d8ea AK |
4589 | emit_label (label2); |
4590 | DONE; | |
4591 | } | |
609e7e80 | 4592 | }) |
cc7ab9b7 | 4593 | |
9db1d521 | 4594 | ; |
65b1d8ea | 4595 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 4596 | ; instruction pattern(s). |
9db1d521 HP |
4597 | ; |
4598 | ||
7b6baae1 | 4599 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
4600 | [(parallel |
4601 | [(set (match_operand:GPR 0 "register_operand" "") | |
4602 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
ae8e301e | 4603 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4604 | (clobber (reg:CC CC_REGNUM))])] |
142cd70f | 4605 | "TARGET_HARD_FLOAT" |
9db1d521 | 4606 | { |
65b1d8ea AK |
4607 | if (!TARGET_Z196) |
4608 | { | |
19f8b229 TS |
4609 | rtx_code_label *label1 = gen_label_rtx (); |
4610 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4611 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); |
4612 | REAL_VALUE_TYPE cmp, sub; | |
4613 | ||
4614 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
2542ef05 RH |
4615 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); |
4616 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
65b1d8ea AK |
4617 | |
4618 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4619 | const_double_from_real_value (cmp, <BFP:MODE>mode), |
65b1d8ea AK |
4620 | LT, NULL_RTX, VOIDmode, 0, label1); |
4621 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
555affd7 | 4622 | const_double_from_real_value (sub, <BFP:MODE>mode))); |
65b1d8ea | 4623 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, |
ae8e301e | 4624 | GEN_INT (BFP_RND_TOWARD_MINF))); |
65b1d8ea AK |
4625 | emit_jump (label2); |
4626 | ||
4627 | emit_label (label1); | |
4628 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
ae8e301e | 4629 | operands[1], GEN_INT (BFP_RND_TOWARD_0))); |
65b1d8ea AK |
4630 | emit_label (label2); |
4631 | DONE; | |
4632 | } | |
10bbf137 | 4633 | }) |
9db1d521 | 4634 | |
65b1d8ea AK |
4635 | ; fixuns_trunc(td|dd)si2 expander |
4636 | (define_expand "fixuns_trunc<mode>si2" | |
4637 | [(parallel | |
4638 | [(set (match_operand:SI 0 "register_operand" "") | |
4639 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
ae8e301e | 4640 | (unspec:SI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4641 | (clobber (reg:CC CC_REGNUM))])] |
8540e6e8 | 4642 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4643 | "") |
4644 | ||
4645 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4646 | ||
6e5b5de8 AK |
4647 | (define_insn "*fixuns_truncdfdi2_z13" |
4648 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4649 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4650 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4651 | (clobber (reg:CC CC_REGNUM))] | |
4652 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4653 | "@ | |
4654 | clgdbr\t%0,%h2,%1,0 | |
4655 | wclgdb\t%v0,%v1,0,%h2" | |
4656 | [(set_attr "op_type" "RRF,VRR") | |
4657 | (set_attr "type" "ftoi")]) | |
4658 | ||
65b1d8ea AK |
4659 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4660 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4661 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4662 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4663 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4664 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 4665 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4666 | "TARGET_Z196 && TARGET_HARD_FLOAT |
4667 | && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" | |
65b1d8ea AK |
4668 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
4669 | [(set_attr "op_type" "RRF") | |
4670 | (set_attr "type" "ftoi")]) | |
4671 | ||
b60cb710 AK |
4672 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4673 | [(set (match_operand:GPR 0 "register_operand" "") | |
4674 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4675 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4676 | { |
b60cb710 | 4677 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 4678 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 4679 | DONE; |
10bbf137 | 4680 | }) |
9db1d521 | 4681 | |
6e5b5de8 AK |
4682 | (define_insn "*fix_truncdfdi2_bfp_z13" |
4683 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4684 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4685 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4686 | (clobber (reg:CC CC_REGNUM))] | |
4687 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4688 | "@ | |
4689 | cgdbr\t%0,%h2,%1 | |
4690 | wcgdb\t%v0,%v1,0,%h2" | |
4691 | [(set_attr "op_type" "RRE,VRR") | |
4692 | (set_attr "type" "ftoi")]) | |
4693 | ||
43a09b63 | 4694 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
4695 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4696 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4697 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4698 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 4699 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4700 | "TARGET_HARD_FLOAT |
4701 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 4702 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4703 | [(set_attr "op_type" "RRE") |
077dab3b | 4704 | (set_attr "type" "ftoi")]) |
9db1d521 | 4705 | |
6e5b5de8 AK |
4706 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4707 | [(parallel | |
4708 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4709 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4710 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4711 | (clobber (reg:CC CC_REGNUM))])] | |
4712 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
4713 | ; |
4714 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4715 | ; | |
4716 | ||
99cd7dd0 AK |
4717 | (define_expand "fix_trunc<mode>di2" |
4718 | [(set (match_operand:DI 0 "register_operand" "") | |
4719 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4720 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4721 | { |
4722 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4723 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 4724 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
4725 | DONE; |
4726 | }) | |
4727 | ||
609e7e80 | 4728 | ; cgxtr, cgdtr |
99cd7dd0 | 4729 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4730 | [(set (match_operand:DI 0 "register_operand" "=d") |
4731 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4732 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4733 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4734 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4735 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4736 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4737 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4738 | |
4739 | ||
f61a2c7d AK |
4740 | ; |
4741 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4742 | ; | |
4743 | ||
4744 | (define_expand "fix_trunctf<mode>2" | |
4745 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4746 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 4747 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 4748 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4749 | "TARGET_HARD_FLOAT" |
142cd70f | 4750 | "") |
9db1d521 | 4751 | |
9db1d521 | 4752 | |
9db1d521 | 4753 | ; |
142cd70f | 4754 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4755 | ; |
4756 | ||
609e7e80 | 4757 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4758 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
4759 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
4760 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 4761 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4762 | "@ |
4763 | c<xde>g<bt>r\t%0,%1 | |
4764 | wcdgb\t%v0,%v1,0,0" | |
4765 | [(set_attr "op_type" "RRE,VRR") | |
4766 | (set_attr "type" "itof<mode>" ) | |
62d3f261 AK |
4767 | (set_attr "cpu_facility" "*,vec") |
4768 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 4769 | |
43a09b63 | 4770 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4771 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4772 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4773 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4774 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4775 | "c<xde>fbr\t%0,%1" |
4776 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4777 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4778 | |
65b1d8ea AK |
4779 | ; cxftr, cdftr |
4780 | (define_insn "floatsi<mode>2" | |
4781 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4782 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4783 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4784 | "c<xde>ftr\t%0,0,%1,0" | |
4785 | [(set_attr "op_type" "RRE") | |
4786 | (set_attr "type" "itof<mode>" )]) | |
4787 | ||
4788 | ; | |
4789 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4790 | ; | |
4791 | ||
6e5b5de8 AK |
4792 | (define_insn "*floatunsdidf2_z13" |
4793 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
4794 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
4795 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4796 | "@ | |
4797 | cdlgbr\t%0,0,%1,0 | |
4798 | wcdlgb\t%v0,%v1,0,0" | |
4799 | [(set_attr "op_type" "RRE,VRR") | |
4800 | (set_attr "type" "itofdf")]) | |
4801 | ||
65b1d8ea AK |
4802 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
4803 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
4804 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
4805 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4806 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4807 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
4808 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
4809 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
4810 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
4811 | (set_attr "type" "itof<FP:mode>")]) |
4812 | ||
4813 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
4814 | [(set (match_operand:FP 0 "register_operand" "") | |
4815 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
4816 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 4817 | |
9db1d521 HP |
4818 | ; |
4819 | ; truncdfsf2 instruction pattern(s). | |
4820 | ; | |
4821 | ||
142cd70f | 4822 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
4823 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
4824 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 4825 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4826 | "@ |
4827 | ledbr\t%0,%1 | |
4828 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
4829 | ; According to BFP rounding mode | |
4830 | [(set_attr "op_type" "RRE,VRR") | |
4831 | (set_attr "type" "ftruncdf") | |
4832 | (set_attr "cpu_facility" "*,vec")]) | |
9db1d521 | 4833 | |
f61a2c7d | 4834 | ; |
142cd70f | 4835 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4836 | ; |
4837 | ||
142cd70f AK |
4838 | ; ldxbr, lexbr |
4839 | (define_insn "trunctf<mode>2" | |
4840 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4841 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4842 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4843 | "TARGET_HARD_FLOAT" |
4844 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4845 | [(set_attr "length" "6") |
9381e3f1 | 4846 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4847 | |
609e7e80 AK |
4848 | ; |
4849 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4850 | ; | |
4851 | ||
432d4670 AK |
4852 | |
4853 | (define_expand "trunctddd2" | |
4854 | [(parallel | |
4855 | [(set (match_operand:DD 0 "register_operand" "") | |
4856 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
4857 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
4858 | (clobber (scratch:TD))])] | |
4859 | "TARGET_HARD_DFP") | |
4860 | ||
4861 | (define_insn "*trunctddd2" | |
609e7e80 | 4862 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 4863 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
4864 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
4865 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 4866 | "TARGET_HARD_DFP" |
432d4670 | 4867 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 4868 | [(set_attr "length" "6") |
9381e3f1 | 4869 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4870 | |
4871 | (define_insn "truncddsd2" | |
4872 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4873 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4874 | "TARGET_HARD_DFP" |
609e7e80 AK |
4875 | "ledtr\t%0,0,%1,0" |
4876 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4877 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4878 | |
feade5a8 AK |
4879 | (define_expand "trunctdsd2" |
4880 | [(parallel | |
4881 | [(set (match_dup 3) | |
4882 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
432d4670 | 4883 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
feade5a8 AK |
4884 | (clobber (match_scratch:TD 2 ""))]) |
4885 | (set (match_operand:SD 0 "register_operand" "") | |
4886 | (float_truncate:SD (match_dup 3)))] | |
4887 | "TARGET_HARD_DFP" | |
4888 | { | |
4889 | operands[3] = gen_reg_rtx (DDmode); | |
4890 | }) | |
4891 | ||
9db1d521 | 4892 | ; |
142cd70f | 4893 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4894 | ; |
4895 | ||
6e5b5de8 AK |
4896 | (define_insn "*extendsfdf2_z13" |
4897 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
4898 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
4899 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4900 | "@ | |
4901 | ldebr\t%0,%1 | |
4902 | ldeb\t%0,%1 | |
4903 | wldeb\t%v0,%v1" | |
4904 | [(set_attr "op_type" "RRE,RXE,VRR") | |
4905 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
4906 | ||
142cd70f | 4907 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
4908 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
4909 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
4910 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
4911 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
4912 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
4913 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 4914 | "@ |
142cd70f AK |
4915 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4916 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
4917 | [(set_attr "op_type" "RRE,RXE") |
4918 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
4919 | ||
4920 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
4921 | [(set (match_operand:BFP 0 "register_operand" "") | |
4922 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
4923 | "TARGET_HARD_FLOAT | |
4924 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 4925 | |
609e7e80 AK |
4926 | ; |
4927 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4928 | ; | |
4929 | ||
4930 | (define_insn "extendddtd2" | |
4931 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4932 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4933 | "TARGET_HARD_DFP" |
609e7e80 AK |
4934 | "lxdtr\t%0,%1,0" |
4935 | [(set_attr "op_type" "RRF") | |
4936 | (set_attr "type" "fsimptf")]) | |
4937 | ||
4938 | (define_insn "extendsddd2" | |
4939 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4940 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4941 | "TARGET_HARD_DFP" |
609e7e80 AK |
4942 | "ldetr\t%0,%1,0" |
4943 | [(set_attr "op_type" "RRF") | |
4944 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4945 | |
feade5a8 AK |
4946 | (define_expand "extendsdtd2" |
4947 | [(set (match_dup 2) | |
4948 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
4949 | (set (match_operand:TD 0 "register_operand" "") | |
4950 | (float_extend:TD (match_dup 2)))] | |
4951 | "TARGET_HARD_DFP" | |
4952 | { | |
4953 | operands[2] = gen_reg_rtx (DDmode); | |
4954 | }) | |
4955 | ||
d12a76f3 AK |
4956 | ; Binary Floating Point - load fp integer |
4957 | ||
4958 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
4959 | ; For all of them the inexact exceptions are suppressed. | |
4960 | ||
4961 | ; fiebra, fidbra, fixbra | |
4962 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
4963 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4964 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4965 | FPINT))] | |
4966 | "TARGET_Z196" | |
4967 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4968 | [(set_attr "op_type" "RRF") | |
4969 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4970 | ||
4971 | ; rint is supposed to raise an inexact exception so we can use the | |
4972 | ; older instructions. | |
4973 | ||
4974 | ; fiebr, fidbr, fixbr | |
4975 | (define_insn "rint<BFP:mode>2" | |
4976 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4977 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4978 | UNSPEC_FPINT_RINT))] | |
4979 | "" | |
4980 | "fi<BFP:xde>br\t%0,0,%1" | |
4981 | [(set_attr "op_type" "RRF") | |
4982 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4983 | ||
4984 | ||
4985 | ; Decimal Floating Point - load fp integer | |
4986 | ||
4987 | ; fidtr, fixtr | |
4988 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
4989 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4990 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4991 | FPINT))] | |
4992 | "TARGET_HARD_DFP" | |
4993 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4994 | [(set_attr "op_type" "RRF") | |
4995 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4996 | ||
4997 | ; fidtr, fixtr | |
4998 | (define_insn "rint<DFP:mode>2" | |
4999 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5000 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5001 | UNSPEC_FPINT_RINT))] | |
5002 | "TARGET_HARD_DFP" | |
5003 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5004 | [(set_attr "op_type" "RRF") | |
5005 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5006 | ||
5007 | ; | |
35dd9a0e AK |
5008 | ; Binary <-> Decimal floating point trunc patterns |
5009 | ; | |
5010 | ||
5011 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5012 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5013 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5014 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5015 | (clobber (reg:CC CC_REGNUM)) |
5016 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5017 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5018 | "pfpo") |
5019 | ||
5020 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5021 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5022 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5023 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5024 | (clobber (reg:CC CC_REGNUM)) |
5025 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5026 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5027 | "pfpo") |
5028 | ||
5029 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5030 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5031 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5032 | (parallel | |
5033 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5034 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5035 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5036 | (clobber (reg:CC CC_REGNUM)) |
5037 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5038 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5039 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5040 | "TARGET_HARD_DFP |
35dd9a0e AK |
5041 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5042 | { | |
5043 | HOST_WIDE_INT flags; | |
5044 | ||
5045 | flags = (PFPO_CONVERT | | |
5046 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5047 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5048 | ||
5049 | operands[2] = GEN_INT (flags); | |
5050 | }) | |
5051 | ||
5052 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5053 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5054 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5055 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5056 | (parallel | |
2cf4c39e | 5057 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5058 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5059 | (clobber (reg:CC CC_REGNUM)) |
5060 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5061 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5062 | "TARGET_HARD_DFP |
35dd9a0e AK |
5063 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5064 | { | |
5065 | HOST_WIDE_INT flags; | |
5066 | ||
5067 | flags = (PFPO_CONVERT | | |
5068 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5069 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5070 | ||
5071 | operands[2] = GEN_INT (flags); | |
5072 | }) | |
5073 | ||
5074 | ; | |
5075 | ; Binary <-> Decimal floating point extend patterns | |
5076 | ; | |
5077 | ||
5078 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5079 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5080 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5081 | (clobber (reg:CC CC_REGNUM)) |
5082 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5083 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5084 | "pfpo") |
5085 | ||
5086 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5087 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5088 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5089 | (clobber (reg:CC CC_REGNUM)) |
5090 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5091 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5092 | "pfpo") |
5093 | ||
5094 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5095 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5096 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5097 | (parallel | |
5098 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5099 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5100 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5101 | (clobber (reg:CC CC_REGNUM)) |
5102 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5103 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5104 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5105 | "TARGET_HARD_DFP |
35dd9a0e AK |
5106 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5107 | { | |
5108 | HOST_WIDE_INT flags; | |
5109 | ||
5110 | flags = (PFPO_CONVERT | | |
5111 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5112 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5113 | ||
5114 | operands[2] = GEN_INT (flags); | |
5115 | }) | |
5116 | ||
5117 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5118 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5119 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5120 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5121 | (parallel | |
2cf4c39e | 5122 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5123 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5124 | (clobber (reg:CC CC_REGNUM)) |
5125 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5126 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5127 | "TARGET_HARD_DFP |
35dd9a0e AK |
5128 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5129 | { | |
5130 | HOST_WIDE_INT flags; | |
5131 | ||
5132 | flags = (PFPO_CONVERT | | |
5133 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5134 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5135 | ||
5136 | operands[2] = GEN_INT (flags); | |
5137 | }) | |
5138 | ||
5139 | ||
9db1d521 | 5140 | ;; |
fae778eb | 5141 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5142 | ;; |
fae778eb | 5143 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5144 | ; because of unpredictable Bits in Register for Halfword and Byte |
5145 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5146 | ||
07893d4f UW |
5147 | ;; |
5148 | ;;- Add instructions. | |
5149 | ;; | |
5150 | ||
1c7b1b7e UW |
5151 | ; |
5152 | ; addti3 instruction pattern(s). | |
5153 | ; | |
5154 | ||
085261c8 AK |
5155 | (define_expand "addti3" |
5156 | [(parallel | |
5157 | [(set (match_operand:TI 0 "register_operand" "") | |
5158 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5159 | (match_operand:TI 2 "general_operand" "") ) ) | |
5160 | (clobber (reg:CC CC_REGNUM))])] | |
5161 | "TARGET_ZARCH" | |
5162 | { | |
5163 | /* For z13 we have vaq which doesn't set CC. */ | |
5164 | if (TARGET_VX) | |
5165 | { | |
5166 | emit_insn (gen_rtx_SET (operands[0], | |
5167 | gen_rtx_PLUS (TImode, | |
5168 | copy_to_mode_reg (TImode, operands[1]), | |
5169 | copy_to_mode_reg (TImode, operands[2])))); | |
5170 | DONE; | |
5171 | } | |
5172 | }) | |
5173 | ||
5174 | (define_insn_and_split "*addti3" | |
5175 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5176 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5177 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5178 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5179 | "TARGET_ZARCH" |
1c7b1b7e UW |
5180 | "#" |
5181 | "&& reload_completed" | |
5182 | [(parallel | |
ae156f85 | 5183 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5184 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5185 | (match_dup 7))) | |
5186 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5187 | (parallel | |
a94a76a7 UW |
5188 | [(set (match_dup 3) (plus:DI |
5189 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5190 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5191 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5192 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5193 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5194 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5195 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5196 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5197 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5198 | [(set_attr "op_type" "*") | |
5199 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5200 | |
07893d4f UW |
5201 | ; |
5202 | ; adddi3 instruction pattern(s). | |
5203 | ; | |
5204 | ||
3298c037 AK |
5205 | (define_expand "adddi3" |
5206 | [(parallel | |
963fc8d0 | 5207 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5208 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5209 | (match_operand:DI 2 "general_operand" ""))) | |
5210 | (clobber (reg:CC CC_REGNUM))])] | |
5211 | "" | |
5212 | "") | |
5213 | ||
07893d4f UW |
5214 | (define_insn "*adddi3_sign" |
5215 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 5216 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5217 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5218 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5219 | "TARGET_ZARCH" |
07893d4f | 5220 | "@ |
d40c829f UW |
5221 | agfr\t%0,%2 |
5222 | agf\t%0,%2" | |
65b1d8ea AK |
5223 | [(set_attr "op_type" "RRE,RXY") |
5224 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5225 | |
5226 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5227 | [(set (reg CC_REGNUM) |
fb492564 | 5228 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5229 | (match_operand:DI 1 "register_operand" "0,0")) |
5230 | (const_int 0))) | |
5231 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5232 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5233 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5234 | "@ |
d40c829f UW |
5235 | algfr\t%0,%2 |
5236 | algf\t%0,%2" | |
9381e3f1 WG |
5237 | [(set_attr "op_type" "RRE,RXY") |
5238 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5239 | |
5240 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5241 | [(set (reg CC_REGNUM) |
fb492564 | 5242 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5243 | (match_operand:DI 1 "register_operand" "0,0")) |
5244 | (const_int 0))) | |
5245 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5246 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5247 | "@ |
d40c829f UW |
5248 | algfr\t%0,%2 |
5249 | algf\t%0,%2" | |
9381e3f1 WG |
5250 | [(set_attr "op_type" "RRE,RXY") |
5251 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5252 | |
5253 | (define_insn "*adddi3_zero" | |
5254 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 5255 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5256 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5257 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5258 | "TARGET_ZARCH" |
07893d4f | 5259 | "@ |
d40c829f UW |
5260 | algfr\t%0,%2 |
5261 | algf\t%0,%2" | |
9381e3f1 WG |
5262 | [(set_attr "op_type" "RRE,RXY") |
5263 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5264 | |
e69166de | 5265 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5266 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5267 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5268 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5269 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5270 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5271 | "#" |
5272 | "&& reload_completed" | |
5273 | [(parallel | |
ae156f85 | 5274 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5275 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5276 | (match_dup 7))) | |
5277 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5278 | (parallel | |
a94a76a7 UW |
5279 | [(set (match_dup 3) (plus:SI |
5280 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5281 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5282 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5283 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5284 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5285 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5286 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5287 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5288 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5289 | |
07893d4f | 5290 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 5291 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 5292 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 5293 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5294 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5295 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5296 | "#" |
5297 | "&& reload_completed" | |
5298 | [(parallel | |
5299 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5300 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5301 | (parallel |
ae156f85 | 5302 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
5303 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5304 | (match_dup 7))) | |
5305 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5306 | (set (pc) | |
ae156f85 | 5307 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5308 | (pc) |
5309 | (label_ref (match_dup 9)))) | |
5310 | (parallel | |
5311 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 5312 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5313 | (match_dup 9)] |
97c6f7ad UW |
5314 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5315 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5316 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5317 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5318 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5319 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5320 | operands[9] = gen_label_rtx ();") |
9db1d521 | 5321 | |
3298c037 AK |
5322 | ; |
5323 | ; addsi3 instruction pattern(s). | |
5324 | ; | |
5325 | ||
5326 | (define_expand "addsi3" | |
07893d4f | 5327 | [(parallel |
963fc8d0 | 5328 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5329 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5330 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5331 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5332 | "" |
07893d4f | 5333 | "") |
9db1d521 | 5334 | |
3298c037 AK |
5335 | (define_insn "*addsi3_sign" |
5336 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5337 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5338 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5339 | (clobber (reg:CC CC_REGNUM))] | |
5340 | "" | |
5341 | "@ | |
5342 | ah\t%0,%2 | |
5343 | ahy\t%0,%2" | |
65b1d8ea AK |
5344 | [(set_attr "op_type" "RX,RXY") |
5345 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5346 | |
9db1d521 | 5347 | ; |
3298c037 | 5348 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5349 | ; |
9db1d521 | 5350 | |
65b1d8ea | 5351 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5352 | (define_insn "*add<mode>3" |
65b1d8ea AK |
5353 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
5354 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
5355 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
5356 | (clobber (reg:CC CC_REGNUM))] |
5357 | "" | |
ec24698e | 5358 | "@ |
3298c037 | 5359 | a<g>r\t%0,%2 |
65b1d8ea | 5360 | a<g>rk\t%0,%1,%2 |
3298c037 | 5361 | a<g>hi\t%0,%h2 |
65b1d8ea | 5362 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5363 | al<g>fi\t%0,%2 |
5364 | sl<g>fi\t%0,%n2 | |
5365 | a<g>\t%0,%2 | |
963fc8d0 AK |
5366 | a<y>\t%0,%2 |
5367 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5368 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
5369 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
5370 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
5371 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5372 | |
65b1d8ea | 5373 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5374 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5375 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5376 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5377 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5378 | (match_dup 1))) |
65b1d8ea | 5379 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5380 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5381 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5382 | "@ |
3298c037 | 5383 | al<g>r\t%0,%2 |
65b1d8ea | 5384 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5385 | al<g>fi\t%0,%2 |
5386 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5387 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5388 | al<g>\t%0,%2 |
963fc8d0 AK |
5389 | al<y>\t%0,%2 |
5390 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5391 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5392 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5393 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
5394 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5395 | |
65b1d8ea | 5396 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5397 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5398 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5399 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5400 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5401 | (match_dup 1))) |
65b1d8ea | 5402 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5403 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5404 | "@ |
3298c037 | 5405 | al<g>r\t%0,%2 |
65b1d8ea | 5406 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5407 | al<g>\t%0,%2 |
5408 | al<y>\t%0,%2" | |
65b1d8ea AK |
5409 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5410 | (set_attr "cpu_facility" "*,z196,*,*") | |
5411 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5412 | |
65b1d8ea | 5413 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5414 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5415 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5416 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
5417 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 5418 | (match_dup 2))) |
65b1d8ea | 5419 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 5420 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5421 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5422 | "@ |
3298c037 | 5423 | al<g>r\t%0,%2 |
65b1d8ea | 5424 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5425 | al<g>fi\t%0,%2 |
5426 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5427 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5428 | al<g>\t%0,%2 |
963fc8d0 AK |
5429 | al<y>\t%0,%2 |
5430 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5431 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5432 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5433 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
5434 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5435 | |
65b1d8ea | 5436 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5437 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5438 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5439 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5440 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5441 | (match_dup 2))) |
65b1d8ea | 5442 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5443 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5444 | "@ |
3298c037 | 5445 | al<g>r\t%0,%2 |
65b1d8ea | 5446 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5447 | al<g>\t%0,%2 |
5448 | al<y>\t%0,%2" | |
65b1d8ea AK |
5449 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5450 | (set_attr "cpu_facility" "*,z196,*,*") | |
5451 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5452 | |
65b1d8ea | 5453 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5454 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5455 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5456 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
5457 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 5458 | (const_int 0))) |
65b1d8ea | 5459 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 5460 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5461 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5462 | "@ |
3298c037 | 5463 | al<g>r\t%0,%2 |
65b1d8ea | 5464 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5465 | al<g>fi\t%0,%2 |
5466 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5467 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5468 | al<g>\t%0,%2 |
963fc8d0 AK |
5469 | al<y>\t%0,%2 |
5470 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5471 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5472 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5473 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
5474 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5475 | |
65b1d8ea | 5476 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5477 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5478 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5479 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5480 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5481 | (const_int 0))) |
65b1d8ea | 5482 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5483 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5484 | "@ |
3298c037 | 5485 | al<g>r\t%0,%2 |
65b1d8ea | 5486 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5487 | al<g>\t%0,%2 |
5488 | al<y>\t%0,%2" | |
65b1d8ea AK |
5489 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5490 | (set_attr "cpu_facility" "*,z196,*,*") | |
5491 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5492 | |
65b1d8ea | 5493 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5494 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5495 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5496 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5497 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5498 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5499 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5500 | "@ |
3298c037 | 5501 | al<g>r\t%0,%2 |
65b1d8ea | 5502 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5503 | al<g>\t%0,%2 |
5504 | al<y>\t%0,%2" | |
65b1d8ea AK |
5505 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5506 | (set_attr "cpu_facility" "*,z196,*,*") | |
5507 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5508 | |
963fc8d0 | 5509 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5510 | (define_insn "*add<mode>3_imm_cc" |
5511 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
5512 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
5513 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 5514 | (const_int 0))) |
65b1d8ea | 5515 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
5516 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5517 | "s390_match_ccmode (insn, CCAmode) | |
5518 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5519 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5520 | /* Avoid INT32_MIN on 32 bit. */ | |
5521 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5522 | "@ |
3298c037 | 5523 | a<g>hi\t%0,%h2 |
65b1d8ea | 5524 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5525 | a<g>fi\t%0,%2 |
5526 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5527 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5528 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5529 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5530 | |
9db1d521 | 5531 | ; |
609e7e80 | 5532 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5533 | ; |
5534 | ||
609e7e80 | 5535 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5536 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5537 | (define_insn "add<mode>3" |
62d3f261 AK |
5538 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
5539 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") | |
5540 | (match_operand:FP 2 "general_operand" "f,f,R,v"))) | |
ae156f85 | 5541 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5542 | "TARGET_HARD_FLOAT" |
9db1d521 | 5543 | "@ |
62d3f261 AK |
5544 | a<xde>tr\t%0,%1,%2 |
5545 | a<xde>br\t%0,%2 | |
6e5b5de8 AK |
5546 | a<xde>b\t%0,%2 |
5547 | wfadb\t%v0,%v1,%v2" | |
62d3f261 | 5548 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 5549 | (set_attr "type" "fsimp<mode>") |
62d3f261 AK |
5550 | (set_attr "cpu_facility" "*,*,*,vec") |
5551 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) | |
9db1d521 | 5552 | |
609e7e80 | 5553 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5554 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5555 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5556 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5557 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5558 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5559 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5560 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5561 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5562 | "@ |
62d3f261 AK |
5563 | a<xde>tr\t%0,%1,%2 |
5564 | a<xde>br\t%0,%2 | |
f61a2c7d | 5565 | a<xde>b\t%0,%2" |
62d3f261 AK |
5566 | [(set_attr "op_type" "RRF,RRE,RXE") |
5567 | (set_attr "type" "fsimp<mode>") | |
5568 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5569 | |
609e7e80 | 5570 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5571 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5572 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5573 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5574 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5575 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5576 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5577 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5578 | "@ |
62d3f261 AK |
5579 | a<xde>tr\t%0,%1,%2 |
5580 | a<xde>br\t%0,%2 | |
f61a2c7d | 5581 | a<xde>b\t%0,%2" |
62d3f261 AK |
5582 | [(set_attr "op_type" "RRF,RRE,RXE") |
5583 | (set_attr "type" "fsimp<mode>") | |
5584 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5585 | |
72a4ddf2 AK |
5586 | ; |
5587 | ; Pointer add instruction patterns | |
5588 | ; | |
5589 | ||
5590 | ; This will match "*la_64" | |
5591 | (define_expand "addptrdi3" | |
5592 | [(set (match_operand:DI 0 "register_operand" "") | |
5593 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5594 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5595 | "TARGET_64BIT" | |
5596 | { | |
72a4ddf2 AK |
5597 | if (GET_CODE (operands[2]) == CONST_INT) |
5598 | { | |
357ddc7d TV |
5599 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5600 | ||
72a4ddf2 AK |
5601 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5602 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5603 | { | |
5604 | operands[2] = force_const_mem (DImode, operands[2]); | |
5605 | operands[2] = force_reg (DImode, operands[2]); | |
5606 | } | |
5607 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5608 | operands[2] = force_reg (DImode, operands[2]); | |
5609 | } | |
5610 | }) | |
5611 | ||
5612 | ; For 31 bit we have to prevent the generated pattern from matching | |
5613 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5614 | ; match "force_la_31". | |
5615 | (define_expand "addptrsi3" | |
5616 | [(parallel | |
5617 | [(set (match_operand:SI 0 "register_operand" "") | |
5618 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5619 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5620 | (use (const_int 0))])] | |
5621 | "!TARGET_64BIT" | |
5622 | { | |
72a4ddf2 AK |
5623 | if (GET_CODE (operands[2]) == CONST_INT) |
5624 | { | |
357ddc7d TV |
5625 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5626 | ||
72a4ddf2 AK |
5627 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5628 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5629 | { | |
5630 | operands[2] = force_const_mem (SImode, operands[2]); | |
5631 | operands[2] = force_reg (SImode, operands[2]); | |
5632 | } | |
5633 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5634 | operands[2] = force_reg (SImode, operands[2]); | |
5635 | } | |
5636 | }) | |
9db1d521 HP |
5637 | |
5638 | ;; | |
5639 | ;;- Subtract instructions. | |
5640 | ;; | |
5641 | ||
1c7b1b7e UW |
5642 | ; |
5643 | ; subti3 instruction pattern(s). | |
5644 | ; | |
5645 | ||
085261c8 AK |
5646 | (define_expand "subti3" |
5647 | [(parallel | |
5648 | [(set (match_operand:TI 0 "register_operand" "") | |
5649 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5650 | (match_operand:TI 2 "general_operand" "") ) ) | |
5651 | (clobber (reg:CC CC_REGNUM))])] | |
5652 | "TARGET_ZARCH" | |
5653 | { | |
5654 | /* For z13 we have vaq which doesn't set CC. */ | |
5655 | if (TARGET_VX) | |
5656 | { | |
5657 | emit_insn (gen_rtx_SET (operands[0], | |
5658 | gen_rtx_MINUS (TImode, | |
5659 | operands[1], | |
5660 | copy_to_mode_reg (TImode, operands[2])))); | |
5661 | DONE; | |
5662 | } | |
5663 | }) | |
5664 | ||
5665 | (define_insn_and_split "*subti3" | |
5666 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
5667 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
5668 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 5669 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5670 | "TARGET_ZARCH" |
1c7b1b7e UW |
5671 | "#" |
5672 | "&& reload_completed" | |
5673 | [(parallel | |
ae156f85 | 5674 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
5675 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
5676 | (match_dup 7))) | |
5677 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
5678 | (parallel | |
5679 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5680 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5681 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
5682 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5683 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5684 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5685 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5686 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5687 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5688 | [(set_attr "op_type" "*") | |
5689 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5690 | |
9db1d521 HP |
5691 | ; |
5692 | ; subdi3 instruction pattern(s). | |
5693 | ; | |
5694 | ||
3298c037 AK |
5695 | (define_expand "subdi3" |
5696 | [(parallel | |
5697 | [(set (match_operand:DI 0 "register_operand" "") | |
5698 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
5699 | (match_operand:DI 2 "general_operand" ""))) | |
5700 | (clobber (reg:CC CC_REGNUM))])] | |
5701 | "" | |
5702 | "") | |
5703 | ||
07893d4f UW |
5704 | (define_insn "*subdi3_sign" |
5705 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5706 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5707 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5708 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5709 | "TARGET_ZARCH" |
07893d4f | 5710 | "@ |
d40c829f UW |
5711 | sgfr\t%0,%2 |
5712 | sgf\t%0,%2" | |
9381e3f1 | 5713 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
5714 | (set_attr "z10prop" "z10_c,*") |
5715 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
5716 | |
5717 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 5718 | [(set (reg CC_REGNUM) |
07893d4f | 5719 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5720 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5721 | (const_int 0))) |
5722 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5723 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 5724 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5725 | "@ |
d40c829f UW |
5726 | slgfr\t%0,%2 |
5727 | slgf\t%0,%2" | |
9381e3f1 WG |
5728 | [(set_attr "op_type" "RRE,RXY") |
5729 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5730 | |
5731 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 5732 | [(set (reg CC_REGNUM) |
07893d4f | 5733 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5734 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5735 | (const_int 0))) |
5736 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5737 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5738 | "@ |
d40c829f UW |
5739 | slgfr\t%0,%2 |
5740 | slgf\t%0,%2" | |
9381e3f1 WG |
5741 | [(set_attr "op_type" "RRE,RXY") |
5742 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5743 | |
5744 | (define_insn "*subdi3_zero" | |
5745 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5746 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5747 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5748 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5749 | "TARGET_ZARCH" |
07893d4f | 5750 | "@ |
d40c829f UW |
5751 | slgfr\t%0,%2 |
5752 | slgf\t%0,%2" | |
9381e3f1 WG |
5753 | [(set_attr "op_type" "RRE,RXY") |
5754 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 5755 | |
e69166de UW |
5756 | (define_insn_and_split "*subdi3_31z" |
5757 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5758 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
5759 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5760 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5761 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5762 | "#" |
5763 | "&& reload_completed" | |
5764 | [(parallel | |
ae156f85 | 5765 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
5766 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5767 | (match_dup 7))) | |
5768 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5769 | (parallel | |
5770 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5771 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5772 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
5773 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5774 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5775 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5776 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5777 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5778 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5779 | |
07893d4f UW |
5780 | (define_insn_and_split "*subdi3_31" |
5781 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5782 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 5783 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5784 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5785 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5786 | "#" |
5787 | "&& reload_completed" | |
5788 | [(parallel | |
5789 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5790 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5791 | (parallel |
ae156f85 | 5792 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
5793 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5794 | (match_dup 7))) | |
5795 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5796 | (set (pc) | |
ae156f85 | 5797 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5798 | (pc) |
5799 | (label_ref (match_dup 9)))) | |
5800 | (parallel | |
5801 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 5802 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5803 | (match_dup 9)] |
97c6f7ad UW |
5804 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5805 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5806 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5807 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5808 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5809 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5810 | operands[9] = gen_label_rtx ();") |
07893d4f | 5811 | |
3298c037 AK |
5812 | ; |
5813 | ; subsi3 instruction pattern(s). | |
5814 | ; | |
5815 | ||
5816 | (define_expand "subsi3" | |
07893d4f | 5817 | [(parallel |
3298c037 AK |
5818 | [(set (match_operand:SI 0 "register_operand" "") |
5819 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
5820 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5821 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5822 | "" |
07893d4f | 5823 | "") |
9db1d521 | 5824 | |
3298c037 AK |
5825 | (define_insn "*subsi3_sign" |
5826 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5827 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
5828 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
5829 | (clobber (reg:CC CC_REGNUM))] | |
5830 | "" | |
5831 | "@ | |
5832 | sh\t%0,%2 | |
5833 | shy\t%0,%2" | |
65b1d8ea AK |
5834 | [(set_attr "op_type" "RX,RXY") |
5835 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5836 | |
9db1d521 | 5837 | ; |
3298c037 | 5838 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
5839 | ; |
5840 | ||
65b1d8ea | 5841 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 5842 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
5843 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
5844 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
5845 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
5846 | (clobber (reg:CC CC_REGNUM))] |
5847 | "" | |
5848 | "@ | |
5849 | s<g>r\t%0,%2 | |
65b1d8ea | 5850 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
5851 | s<g>\t%0,%2 |
5852 | s<y>\t%0,%2" | |
65b1d8ea AK |
5853 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5854 | (set_attr "cpu_facility" "*,z196,*,*") | |
5855 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 5856 | |
65b1d8ea | 5857 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5858 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 5859 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5860 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5861 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5862 | (match_dup 1))) |
65b1d8ea | 5863 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5864 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5865 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5866 | "@ |
3298c037 | 5867 | sl<g>r\t%0,%2 |
65b1d8ea | 5868 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5869 | sl<g>\t%0,%2 |
5870 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5871 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5872 | (set_attr "cpu_facility" "*,z196,*,*") | |
5873 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5874 | |
65b1d8ea | 5875 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5876 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 5877 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5878 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5879 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5880 | (match_dup 1))) |
65b1d8ea | 5881 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5882 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5883 | "@ |
3298c037 | 5884 | sl<g>r\t%0,%2 |
65b1d8ea | 5885 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5886 | sl<g>\t%0,%2 |
5887 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5888 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5889 | (set_attr "cpu_facility" "*,z196,*,*") | |
5890 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5891 | |
65b1d8ea | 5892 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5893 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5894 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5895 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5896 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5897 | (const_int 0))) |
65b1d8ea | 5898 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5899 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5900 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5901 | "@ |
3298c037 | 5902 | sl<g>r\t%0,%2 |
65b1d8ea | 5903 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5904 | sl<g>\t%0,%2 |
5905 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5906 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5907 | (set_attr "cpu_facility" "*,z196,*,*") | |
5908 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5909 | |
65b1d8ea | 5910 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5911 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5912 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5913 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5914 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5915 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5916 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5917 | "s390_match_ccmode (insn, CCL3mode)" |
5918 | "@ | |
3298c037 | 5919 | sl<g>r\t%0,%2 |
65b1d8ea | 5920 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5921 | sl<g>\t%0,%2 |
5922 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5923 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5924 | (set_attr "cpu_facility" "*,z196,*,*") | |
5925 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5926 | |
65b1d8ea | 5927 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5928 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5929 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5930 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5931 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5932 | (const_int 0))) |
65b1d8ea | 5933 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5934 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5935 | "@ |
3298c037 | 5936 | sl<g>r\t%0,%2 |
65b1d8ea | 5937 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5938 | sl<g>\t%0,%2 |
5939 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5940 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5941 | (set_attr "cpu_facility" "*,z196,*,*") | |
5942 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5943 | |
9db1d521 | 5944 | |
65b1d8ea | 5945 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5946 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5947 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5948 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5949 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5950 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5951 | "s390_match_ccmode (insn, CCL3mode)" |
5952 | "@ | |
3298c037 | 5953 | sl<g>r\t%0,%2 |
65b1d8ea | 5954 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5955 | sl<g>\t%0,%2 |
5956 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5957 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5958 | (set_attr "cpu_facility" "*,z196,*,*") | |
5959 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5960 | |
9db1d521 HP |
5961 | |
5962 | ; | |
609e7e80 | 5963 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5964 | ; |
5965 | ||
d46f24b6 | 5966 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5967 | (define_insn "sub<mode>3" |
62d3f261 AK |
5968 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
5969 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v") | |
5970 | (match_operand:FP 2 "general_operand" "f,f,R,v"))) | |
ae156f85 | 5971 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5972 | "TARGET_HARD_FLOAT" |
9db1d521 | 5973 | "@ |
62d3f261 AK |
5974 | s<xde>tr\t%0,%1,%2 |
5975 | s<xde>br\t%0,%2 | |
6e5b5de8 AK |
5976 | s<xde>b\t%0,%2 |
5977 | wfsdb\t%v0,%v1,%v2" | |
62d3f261 | 5978 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 5979 | (set_attr "type" "fsimp<mode>") |
62d3f261 AK |
5980 | (set_attr "cpu_facility" "*,*,*,vec") |
5981 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) | |
9db1d521 | 5982 | |
d46f24b6 | 5983 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5984 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5985 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5986 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
5987 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5988 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5989 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5990 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5991 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5992 | "@ |
62d3f261 AK |
5993 | s<xde>tr\t%0,%1,%2 |
5994 | s<xde>br\t%0,%2 | |
f61a2c7d | 5995 | s<xde>b\t%0,%2" |
62d3f261 AK |
5996 | [(set_attr "op_type" "RRF,RRE,RXE") |
5997 | (set_attr "type" "fsimp<mode>") | |
5998 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5999 | |
d46f24b6 | 6000 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6001 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6002 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6003 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6004 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6005 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6006 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6007 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6008 | "@ |
62d3f261 AK |
6009 | s<xde>tr\t%0,%1,%2 |
6010 | s<xde>br\t%0,%2 | |
f61a2c7d | 6011 | s<xde>b\t%0,%2" |
62d3f261 AK |
6012 | [(set_attr "op_type" "RRF,RRE,RXE") |
6013 | (set_attr "type" "fsimp<mode>") | |
6014 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6015 | |
9db1d521 | 6016 | |
e69166de UW |
6017 | ;; |
6018 | ;;- Conditional add/subtract instructions. | |
6019 | ;; | |
6020 | ||
6021 | ; | |
9a91a21f | 6022 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6023 | ; |
6024 | ||
a996720c UW |
6025 | ; the following 4 patterns are used when the result of an add with |
6026 | ; carry is checked for an overflow condition | |
6027 | ||
6028 | ; op1 + op2 + c < op1 | |
6029 | ||
6030 | ; alcr, alc, alcgr, alcg | |
6031 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6032 | [(set (reg CC_REGNUM) | |
6033 | (compare | |
6034 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6035 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6036 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
6037 | (match_dup 1))) |
6038 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6039 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6040 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6041 | "@ | |
6042 | alc<g>r\t%0,%2 | |
6043 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6044 | [(set_attr "op_type" "RRE,RXY") |
6045 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6046 | |
6047 | ; alcr, alc, alcgr, alcg | |
6048 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6049 | [(set (reg CC_REGNUM) | |
6050 | (compare | |
6051 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6052 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6053 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
6054 | (match_dup 1))) |
6055 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6056 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6057 | "@ | |
6058 | alc<g>r\t%0,%2 | |
6059 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6060 | [(set_attr "op_type" "RRE,RXY") |
6061 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6062 | |
6063 | ; op1 + op2 + c < op2 | |
6064 | ||
6065 | ; alcr, alc, alcgr, alcg | |
6066 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6067 | [(set (reg CC_REGNUM) | |
6068 | (compare | |
6069 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6070 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6071 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
6072 | (match_dup 2))) |
6073 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6074 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6075 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6076 | "@ | |
6077 | alc<g>r\t%0,%2 | |
6078 | alc<g>\t%0,%2" | |
6079 | [(set_attr "op_type" "RRE,RXY")]) | |
6080 | ||
6081 | ; alcr, alc, alcgr, alcg | |
6082 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6083 | [(set (reg CC_REGNUM) | |
6084 | (compare | |
6085 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6086 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6087 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
6088 | (match_dup 2))) |
6089 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6090 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6091 | "@ | |
6092 | alc<g>r\t%0,%2 | |
6093 | alc<g>\t%0,%2" | |
6094 | [(set_attr "op_type" "RRE,RXY")]) | |
6095 | ||
43a09b63 | 6096 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6097 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6098 | [(set (reg CC_REGNUM) |
e69166de | 6099 | (compare |
a94a76a7 UW |
6100 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6101 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6102 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 6103 | (const_int 0))) |
9a91a21f | 6104 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6105 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 6106 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6107 | "@ |
9a91a21f AS |
6108 | alc<g>r\t%0,%2 |
6109 | alc<g>\t%0,%2" | |
e69166de UW |
6110 | [(set_attr "op_type" "RRE,RXY")]) |
6111 | ||
43a09b63 | 6112 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6113 | (define_insn "*add<mode>3_alc" |
6114 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6115 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6116 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6117 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 6118 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6119 | "TARGET_CPU_ZARCH" |
e69166de | 6120 | "@ |
9a91a21f AS |
6121 | alc<g>r\t%0,%2 |
6122 | alc<g>\t%0,%2" | |
e69166de UW |
6123 | [(set_attr "op_type" "RRE,RXY")]) |
6124 | ||
43a09b63 | 6125 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6126 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6127 | [(set (reg CC_REGNUM) |
e69166de | 6128 | (compare |
9a91a21f | 6129 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 6130 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 6131 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6132 | (const_int 0))) |
9a91a21f AS |
6133 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6134 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 6135 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6136 | "@ |
9a91a21f AS |
6137 | slb<g>r\t%0,%2 |
6138 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6139 | [(set_attr "op_type" "RRE,RXY") |
6140 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6141 | |
43a09b63 | 6142 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6143 | (define_insn "*sub<mode>3_slb" |
6144 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6145 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 6146 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 6147 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6148 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6149 | "TARGET_CPU_ZARCH" |
e69166de | 6150 | "@ |
9a91a21f AS |
6151 | slb<g>r\t%0,%2 |
6152 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6153 | [(set_attr "op_type" "RRE,RXY") |
6154 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6155 | |
9a91a21f AS |
6156 | (define_expand "add<mode>cc" |
6157 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6158 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6159 | (match_operand:GPR 2 "register_operand" "") |
6160 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 6161 | "TARGET_CPU_ZARCH" |
9381e3f1 | 6162 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6163 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6164 | operands[0], operands[2], |
5d880bd2 UW |
6165 | operands[3])) FAIL; DONE;") |
6166 | ||
6167 | ; | |
6168 | ; scond instruction pattern(s). | |
6169 | ; | |
6170 | ||
9a91a21f AS |
6171 | (define_insn_and_split "*scond<mode>" |
6172 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6173 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6174 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6175 | "TARGET_CPU_ZARCH" |
6176 | "#" | |
6177 | "&& reload_completed" | |
6178 | [(set (match_dup 0) (const_int 0)) | |
6179 | (parallel | |
a94a76a7 UW |
6180 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6181 | (match_dup 0))) | |
ae156f85 | 6182 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6183 | "") |
5d880bd2 | 6184 | |
9a91a21f AS |
6185 | (define_insn_and_split "*scond<mode>_neg" |
6186 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6187 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6188 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6189 | "TARGET_CPU_ZARCH" |
6190 | "#" | |
6191 | "&& reload_completed" | |
6192 | [(set (match_dup 0) (const_int 0)) | |
6193 | (parallel | |
9a91a21f AS |
6194 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6195 | (match_dup 1))) | |
ae156f85 | 6196 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6197 | (parallel |
9a91a21f | 6198 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6199 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6200 | "") |
5d880bd2 | 6201 | |
5d880bd2 | 6202 | |
f90b7a5a | 6203 | (define_expand "cstore<mode>4" |
9a91a21f | 6204 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6205 | (match_operator:SI 1 "s390_scond_operator" |
6206 | [(match_operand:GPR 2 "register_operand" "") | |
6207 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 6208 | "TARGET_CPU_ZARCH" |
f90b7a5a | 6209 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6210 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6211 | ||
f90b7a5a | 6212 | (define_expand "cstorecc4" |
69950452 | 6213 | [(parallel |
f90b7a5a PB |
6214 | [(set (match_operand:SI 0 "register_operand" "") |
6215 | (match_operator:SI 1 "s390_eqne_operator" | |
6216 | [(match_operand:CCZ1 2 "register_operand") | |
6217 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
6218 | (clobber (reg:CC CC_REGNUM))])] |
6219 | "" | |
f90b7a5a PB |
6220 | "emit_insn (gen_sne (operands[0], operands[2])); |
6221 | if (GET_CODE (operands[1]) == EQ) | |
6222 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6223 | DONE;") | |
69950452 | 6224 | |
f90b7a5a | 6225 | (define_insn_and_split "sne" |
69950452 | 6226 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6227 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6228 | (const_int 0))) |
6229 | (clobber (reg:CC CC_REGNUM))] | |
6230 | "" | |
6231 | "#" | |
6232 | "reload_completed" | |
6233 | [(parallel | |
6234 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6235 | (clobber (reg:CC CC_REGNUM))])]) | |
6236 | ||
e69166de | 6237 | |
65b1d8ea AK |
6238 | ;; |
6239 | ;; - Conditional move instructions (introduced with z196) | |
6240 | ;; | |
6241 | ||
6242 | (define_expand "mov<mode>cc" | |
6243 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6244 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6245 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6246 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6247 | "TARGET_Z196" | |
7477de01 AK |
6248 | { |
6249 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6250 | if (!s390_comparison (operands[1], VOIDmode)) | |
6251 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6252 | XEXP (operands[1], 0), | |
6253 | XEXP (operands[1], 1)); | |
6254 | }) | |
65b1d8ea | 6255 | |
27037b5f | 6256 | ; locr, loc, stoc, locgr, locg, stocg |
65b1d8ea AK |
6257 | (define_insn_and_split "*mov<mode>cc" |
6258 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
6259 | (if_then_else:GPR | |
6260 | (match_operator 1 "s390_comparison" | |
6261 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5a3fe9b6 | 6262 | (match_operand 5 "const_int_operand" "")]) |
65b1d8ea AK |
6263 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") |
6264 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
6265 | "TARGET_Z196" | |
6266 | "@ | |
6267 | loc<g>r%C1\t%0,%3 | |
6268 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6269 | loc<g>%C1\t%0,%3 |
6270 | loc<g>%D1\t%0,%4 | |
6271 | stoc<g>%C1\t%3,%0 | |
6272 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
6273 | #" |
6274 | "&& reload_completed | |
6275 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
6276 | [(set (match_dup 0) | |
6277 | (if_then_else:GPR | |
6278 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6279 | (match_dup 3) | |
6280 | (match_dup 0))) | |
6281 | (set (match_dup 0) | |
6282 | (if_then_else:GPR | |
6283 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6284 | (match_dup 0) | |
6285 | (match_dup 4)))] | |
6286 | "" | |
6287 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
6288 | ||
9db1d521 HP |
6289 | ;; |
6290 | ;;- Multiply instructions. | |
6291 | ;; | |
6292 | ||
4023fb28 UW |
6293 | ; |
6294 | ; muldi3 instruction pattern(s). | |
6295 | ; | |
9db1d521 | 6296 | |
07893d4f UW |
6297 | (define_insn "*muldi3_sign" |
6298 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 6299 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 6300 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6301 | "TARGET_ZARCH" |
07893d4f | 6302 | "@ |
d40c829f UW |
6303 | msgfr\t%0,%2 |
6304 | msgf\t%0,%2" | |
963fc8d0 AK |
6305 | [(set_attr "op_type" "RRE,RXY") |
6306 | (set_attr "type" "imuldi")]) | |
07893d4f | 6307 | |
4023fb28 | 6308 | (define_insn "muldi3" |
963fc8d0 AK |
6309 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
6310 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
6311 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 6312 | "TARGET_ZARCH" |
9db1d521 | 6313 | "@ |
d40c829f UW |
6314 | msgr\t%0,%2 |
6315 | mghi\t%0,%h2 | |
963fc8d0 AK |
6316 | msg\t%0,%2 |
6317 | msgfi\t%0,%2" | |
6318 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
6319 | (set_attr "type" "imuldi") | |
6320 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 6321 | |
9db1d521 HP |
6322 | ; |
6323 | ; mulsi3 instruction pattern(s). | |
6324 | ; | |
6325 | ||
f1e77d83 | 6326 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6327 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6328 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6329 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6330 | "" |
963fc8d0 AK |
6331 | "@ |
6332 | mh\t%0,%2 | |
6333 | mhy\t%0,%2" | |
6334 | [(set_attr "op_type" "RX,RXY") | |
6335 | (set_attr "type" "imulhi") | |
6336 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6337 | |
9db1d521 | 6338 | (define_insn "mulsi3" |
963fc8d0 AK |
6339 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
6340 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6341 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
6342 | "" |
6343 | "@ | |
d40c829f UW |
6344 | msr\t%0,%2 |
6345 | mhi\t%0,%h2 | |
6346 | ms\t%0,%2 | |
963fc8d0 AK |
6347 | msy\t%0,%2 |
6348 | msfi\t%0,%2" | |
6349 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
6350 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
6351 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 6352 | |
4023fb28 UW |
6353 | ; |
6354 | ; mulsidi3 instruction pattern(s). | |
6355 | ; | |
6356 | ||
f1e77d83 | 6357 | (define_insn "mulsidi3" |
963fc8d0 | 6358 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6359 | (mult:DI (sign_extend:DI |
963fc8d0 | 6360 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6361 | (sign_extend:DI |
963fc8d0 | 6362 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6363 | "!TARGET_ZARCH" |
f1e77d83 UW |
6364 | "@ |
6365 | mr\t%0,%2 | |
963fc8d0 AK |
6366 | m\t%0,%2 |
6367 | mfy\t%0,%2" | |
6368 | [(set_attr "op_type" "RR,RX,RXY") | |
6369 | (set_attr "type" "imulsi") | |
6370 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6371 | |
f1e77d83 | 6372 | ; |
6e0d70c9 | 6373 | ; umul instruction pattern(s). |
f1e77d83 | 6374 | ; |
c7453384 | 6375 | |
6e0d70c9 AK |
6376 | ; mlr, ml, mlgr, mlg |
6377 | (define_insn "umul<dwh><mode>3" | |
6378 | [(set (match_operand:DW 0 "register_operand" "=d, d") | |
6379 | (mult:DW (zero_extend:DW | |
6380 | (match_operand:<DWH> 1 "register_operand" "%0, 0")) | |
6381 | (zero_extend:DW | |
6382 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] | |
6383 | "TARGET_CPU_ZARCH" | |
f1e77d83 | 6384 | "@ |
6e0d70c9 AK |
6385 | ml<tg>r\t%0,%2 |
6386 | ml<tg>\t%0,%2" | |
f1e77d83 | 6387 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6388 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6389 | |
9db1d521 | 6390 | ; |
609e7e80 | 6391 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6392 | ; |
6393 | ||
9381e3f1 | 6394 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6395 | (define_insn "mul<mode>3" |
62d3f261 AK |
6396 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
6397 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") | |
6398 | (match_operand:FP 2 "general_operand" "f,f,R,v")))] | |
142cd70f | 6399 | "TARGET_HARD_FLOAT" |
9db1d521 | 6400 | "@ |
62d3f261 AK |
6401 | m<xdee>tr\t%0,%1,%2 |
6402 | m<xdee>br\t%0,%2 | |
6e5b5de8 AK |
6403 | m<xdee>b\t%0,%2 |
6404 | wfmdb\t%v0,%v1,%v2" | |
62d3f261 | 6405 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 6406 | (set_attr "type" "fmul<mode>") |
62d3f261 AK |
6407 | (set_attr "cpu_facility" "*,*,*,vec") |
6408 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) | |
9db1d521 | 6409 | |
9381e3f1 | 6410 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6411 | (define_insn "fma<mode>4" |
62d3f261 AK |
6412 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v") |
6413 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") | |
6414 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") | |
6415 | (match_operand:DSF 3 "register_operand" "0,0,v")))] | |
d7ecb504 | 6416 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6417 | "@ |
f61a2c7d | 6418 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6419 | ma<xde>b\t%0,%1,%2 |
6420 | wfmadb\t%v0,%v1,%v2,%v3" | |
6421 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6422 | (set_attr "type" "fmadd<mode>") | |
62d3f261 AK |
6423 | (set_attr "cpu_facility" "*,*,vec") |
6424 | (set_attr "enabled" "*,*,<DFDI>")]) | |
a1b892b5 | 6425 | |
43a09b63 | 6426 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6427 | (define_insn "fms<mode>4" |
62d3f261 AK |
6428 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v") |
6429 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") | |
6430 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") | |
6431 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))] | |
d7ecb504 | 6432 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6433 | "@ |
f61a2c7d | 6434 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6435 | ms<xde>b\t%0,%1,%2 |
6436 | wfmsdb\t%v0,%v1,%v2,%v3" | |
6437 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6438 | (set_attr "type" "fmadd<mode>") | |
62d3f261 AK |
6439 | (set_attr "cpu_facility" "*,*,vec") |
6440 | (set_attr "enabled" "*,*,<DFDI>")]) | |
9db1d521 HP |
6441 | |
6442 | ;; | |
6443 | ;;- Divide and modulo instructions. | |
6444 | ;; | |
6445 | ||
6446 | ; | |
4023fb28 | 6447 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6448 | ; |
6449 | ||
4023fb28 UW |
6450 | (define_expand "divmoddi4" |
6451 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6452 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6453 | (match_operand:DI 2 "general_operand" ""))) |
6454 | (set (match_operand:DI 3 "general_operand" "") | |
6455 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6456 | (clobber (match_dup 4))] | |
9602b6a1 | 6457 | "TARGET_ZARCH" |
9db1d521 | 6458 | { |
f1e77d83 | 6459 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
6460 | |
6461 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6462 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6463 | |
6464 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6465 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6466 | |
6467 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6468 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6469 | |
6470 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6471 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6472 | |
9db1d521 | 6473 | DONE; |
10bbf137 | 6474 | }) |
9db1d521 HP |
6475 | |
6476 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6477 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6478 | (ior:TI | |
4023fb28 UW |
6479 | (ashift:TI |
6480 | (zero_extend:TI | |
5665e398 | 6481 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 6482 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
6483 | (const_int 64)) |
6484 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6485 | "TARGET_ZARCH" |
9db1d521 | 6486 | "@ |
d40c829f UW |
6487 | dsgr\t%0,%2 |
6488 | dsg\t%0,%2" | |
d3632d41 | 6489 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6490 | (set_attr "type" "idiv")]) |
9db1d521 | 6491 | |
4023fb28 UW |
6492 | (define_insn "divmodtisi3" |
6493 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6494 | (ior:TI | |
4023fb28 UW |
6495 | (ashift:TI |
6496 | (zero_extend:TI | |
5665e398 | 6497 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6498 | (sign_extend:DI |
fb492564 | 6499 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
6500 | (const_int 64)) |
6501 | (zero_extend:TI | |
6502 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6503 | "TARGET_ZARCH" |
4023fb28 | 6504 | "@ |
d40c829f UW |
6505 | dsgfr\t%0,%2 |
6506 | dsgf\t%0,%2" | |
d3632d41 | 6507 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6508 | (set_attr "type" "idiv")]) |
9db1d521 | 6509 | |
4023fb28 UW |
6510 | ; |
6511 | ; udivmoddi4 instruction pattern(s). | |
6512 | ; | |
9db1d521 | 6513 | |
4023fb28 UW |
6514 | (define_expand "udivmoddi4" |
6515 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6516 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6517 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6518 | (set (match_operand:DI 3 "general_operand" "") | |
6519 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6520 | (clobber (match_dup 4))] | |
9602b6a1 | 6521 | "TARGET_ZARCH" |
9db1d521 | 6522 | { |
4023fb28 UW |
6523 | rtx insn, div_equal, mod_equal, equal; |
6524 | ||
6525 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6526 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6527 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6528 | gen_rtx_ASHIFT (TImode, |
6529 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6530 | GEN_INT (64)), |
6531 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6532 | |
6533 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6534 | emit_clobber (operands[4]); |
4023fb28 UW |
6535 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6536 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6537 | |
4023fb28 | 6538 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6539 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6540 | |
6541 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6542 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6543 | |
6544 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6545 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6546 | |
9db1d521 | 6547 | DONE; |
10bbf137 | 6548 | }) |
9db1d521 HP |
6549 | |
6550 | (define_insn "udivmodtidi3" | |
4023fb28 | 6551 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6552 | (ior:TI |
5665e398 UW |
6553 | (ashift:TI |
6554 | (zero_extend:TI | |
6555 | (truncate:DI | |
2f7e5a0d EC |
6556 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6557 | (zero_extend:TI | |
fb492564 | 6558 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6559 | (const_int 64)) |
6560 | (zero_extend:TI | |
6561 | (truncate:DI | |
6562 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6563 | "TARGET_ZARCH" |
9db1d521 | 6564 | "@ |
d40c829f UW |
6565 | dlgr\t%0,%2 |
6566 | dlg\t%0,%2" | |
d3632d41 | 6567 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6568 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6569 | |
6570 | ; | |
4023fb28 | 6571 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6572 | ; |
6573 | ||
4023fb28 UW |
6574 | (define_expand "divmodsi4" |
6575 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6576 | (div:SI (match_operand:SI 1 "general_operand" "") | |
6577 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6578 | (set (match_operand:SI 3 "general_operand" "") | |
6579 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
6580 | (clobber (match_dup 4))] | |
9602b6a1 | 6581 | "!TARGET_ZARCH" |
9db1d521 | 6582 | { |
4023fb28 UW |
6583 | rtx insn, div_equal, mod_equal, equal; |
6584 | ||
6585 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
6586 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
6587 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6588 | gen_rtx_ASHIFT (DImode, |
6589 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6590 | GEN_INT (32)), |
6591 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
6592 | |
6593 | operands[4] = gen_reg_rtx(DImode); | |
6594 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 6595 | |
4023fb28 | 6596 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6597 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6598 | |
6599 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6600 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6601 | |
6602 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6603 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6604 | |
9db1d521 | 6605 | DONE; |
10bbf137 | 6606 | }) |
9db1d521 HP |
6607 | |
6608 | (define_insn "divmoddisi3" | |
4023fb28 | 6609 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 6610 | (ior:DI |
5665e398 UW |
6611 | (ashift:DI |
6612 | (zero_extend:DI | |
6613 | (truncate:SI | |
2f7e5a0d EC |
6614 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
6615 | (sign_extend:DI | |
5665e398 UW |
6616 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
6617 | (const_int 32)) | |
6618 | (zero_extend:DI | |
6619 | (truncate:SI | |
6620 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6621 | "!TARGET_ZARCH" |
9db1d521 | 6622 | "@ |
d40c829f UW |
6623 | dr\t%0,%2 |
6624 | d\t%0,%2" | |
9db1d521 | 6625 | [(set_attr "op_type" "RR,RX") |
077dab3b | 6626 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6627 | |
6628 | ; | |
6629 | ; udivsi3 and umodsi3 instruction pattern(s). | |
6630 | ; | |
6631 | ||
f1e77d83 UW |
6632 | (define_expand "udivmodsi4" |
6633 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6634 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
6635 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6636 | (set (match_operand:SI 3 "general_operand" "") | |
6637 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
6638 | (clobber (match_dup 4))] | |
9602b6a1 | 6639 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6640 | { |
6641 | rtx insn, div_equal, mod_equal, equal; | |
6642 | ||
6643 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6644 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6645 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
6646 | gen_rtx_ASHIFT (DImode, |
6647 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6648 | GEN_INT (32)), |
6649 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
6650 | |
6651 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 6652 | emit_clobber (operands[4]); |
f1e77d83 UW |
6653 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
6654 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 6655 | |
f1e77d83 | 6656 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6657 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
6658 | |
6659 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6660 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
6661 | |
6662 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6663 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
6664 | |
6665 | DONE; | |
6666 | }) | |
6667 | ||
6668 | (define_insn "udivmoddisi3" | |
6669 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 6670 | (ior:DI |
5665e398 UW |
6671 | (ashift:DI |
6672 | (zero_extend:DI | |
6673 | (truncate:SI | |
2f7e5a0d EC |
6674 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
6675 | (zero_extend:DI | |
fb492564 | 6676 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6677 | (const_int 32)) |
6678 | (zero_extend:DI | |
6679 | (truncate:SI | |
6680 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6681 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6682 | "@ |
6683 | dlr\t%0,%2 | |
6684 | dl\t%0,%2" | |
6685 | [(set_attr "op_type" "RRE,RXY") | |
6686 | (set_attr "type" "idiv")]) | |
4023fb28 | 6687 | |
9db1d521 HP |
6688 | (define_expand "udivsi3" |
6689 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6690 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
6691 | (match_operand:SI 2 "general_operand" ""))) |
6692 | (clobber (match_dup 3))] | |
9602b6a1 | 6693 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6694 | { |
4023fb28 UW |
6695 | rtx insn, udiv_equal, umod_equal, equal; |
6696 | ||
6697 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6698 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6699 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6700 | gen_rtx_ASHIFT (DImode, |
6701 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6702 | GEN_INT (32)), |
6703 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6704 | |
4023fb28 | 6705 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6706 | |
6707 | if (CONSTANT_P (operands[2])) | |
6708 | { | |
6709 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
6710 | { | |
19f8b229 | 6711 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6712 | |
4023fb28 UW |
6713 | operands[1] = make_safe_from (operands[1], operands[0]); |
6714 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6715 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
6716 | SImode, 1, label1); | |
4023fb28 | 6717 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6718 | emit_label (label1); |
6719 | } | |
6720 | else | |
6721 | { | |
c7453384 EC |
6722 | operands[2] = force_reg (SImode, operands[2]); |
6723 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6724 | |
6725 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6726 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6727 | operands[2])); | |
bd94cb6e | 6728 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6729 | |
6730 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6731 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 6732 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
6733 | } |
6734 | } | |
6735 | else | |
c7453384 | 6736 | { |
19f8b229 TS |
6737 | rtx_code_label *label1 = gen_label_rtx (); |
6738 | rtx_code_label *label2 = gen_label_rtx (); | |
6739 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6740 | |
c7453384 EC |
6741 | operands[1] = force_reg (SImode, operands[1]); |
6742 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6743 | operands[2] = force_reg (SImode, operands[2]); | |
6744 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6745 | |
6746 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6747 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6748 | SImode, 1, label3); | |
6749 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6750 | SImode, 0, label2); | |
6751 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6752 | SImode, 0, label1); | |
4023fb28 UW |
6753 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6754 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6755 | operands[2])); | |
bd94cb6e | 6756 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6757 | |
6758 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6759 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
6760 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
6761 | ||
f314b9b1 | 6762 | emit_jump (label3); |
9db1d521 | 6763 | emit_label (label1); |
4023fb28 | 6764 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 6765 | emit_jump (label3); |
9db1d521 | 6766 | emit_label (label2); |
4023fb28 | 6767 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6768 | emit_label (label3); |
6769 | } | |
c7453384 | 6770 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 6771 | DONE; |
10bbf137 | 6772 | }) |
9db1d521 HP |
6773 | |
6774 | (define_expand "umodsi3" | |
6775 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6776 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
6777 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
6778 | (clobber (match_dup 3))] | |
9602b6a1 | 6779 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6780 | { |
4023fb28 UW |
6781 | rtx insn, udiv_equal, umod_equal, equal; |
6782 | ||
6783 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6784 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6785 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6786 | gen_rtx_ASHIFT (DImode, |
6787 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6788 | GEN_INT (32)), |
6789 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6790 | |
4023fb28 | 6791 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6792 | |
6793 | if (CONSTANT_P (operands[2])) | |
6794 | { | |
6795 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
6796 | { | |
19f8b229 | 6797 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6798 | |
4023fb28 UW |
6799 | operands[1] = make_safe_from (operands[1], operands[0]); |
6800 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
6801 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
6802 | SImode, 1, label1); | |
4023fb28 UW |
6803 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
6804 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
6805 | emit_label (label1); |
6806 | } | |
6807 | else | |
6808 | { | |
c7453384 EC |
6809 | operands[2] = force_reg (SImode, operands[2]); |
6810 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6811 | |
6812 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6813 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6814 | operands[2])); | |
bd94cb6e | 6815 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6816 | |
6817 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6818 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 6819 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
6820 | } |
6821 | } | |
6822 | else | |
6823 | { | |
19f8b229 TS |
6824 | rtx_code_label *label1 = gen_label_rtx (); |
6825 | rtx_code_label *label2 = gen_label_rtx (); | |
6826 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6827 | |
c7453384 EC |
6828 | operands[1] = force_reg (SImode, operands[1]); |
6829 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6830 | operands[2] = force_reg (SImode, operands[2]); | |
6831 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 6832 | |
c7453384 | 6833 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
6834 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6835 | SImode, 1, label3); | |
6836 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6837 | SImode, 0, label2); | |
6838 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6839 | SImode, 0, label1); | |
4023fb28 UW |
6840 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6841 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6842 | operands[2])); | |
bd94cb6e | 6843 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6844 | |
6845 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6846 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
6847 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
6848 | ||
f314b9b1 | 6849 | emit_jump (label3); |
9db1d521 | 6850 | emit_label (label1); |
4023fb28 | 6851 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 6852 | emit_jump (label3); |
9db1d521 | 6853 | emit_label (label2); |
4023fb28 | 6854 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
6855 | emit_label (label3); |
6856 | } | |
9db1d521 | 6857 | DONE; |
10bbf137 | 6858 | }) |
9db1d521 HP |
6859 | |
6860 | ; | |
f5905b37 | 6861 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
6862 | ; |
6863 | ||
609e7e80 | 6864 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 6865 | (define_insn "div<mode>3" |
62d3f261 AK |
6866 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
6867 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v") | |
6868 | (match_operand:FP 2 "general_operand" "f,f,R,v")))] | |
142cd70f | 6869 | "TARGET_HARD_FLOAT" |
9db1d521 | 6870 | "@ |
62d3f261 AK |
6871 | d<xde>tr\t%0,%1,%2 |
6872 | d<xde>br\t%0,%2 | |
6e5b5de8 AK |
6873 | d<xde>b\t%0,%2 |
6874 | wfddb\t%v0,%v1,%v2" | |
62d3f261 | 6875 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 6876 | (set_attr "type" "fdiv<mode>") |
62d3f261 AK |
6877 | (set_attr "cpu_facility" "*,*,*,vec") |
6878 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) | |
9db1d521 | 6879 | |
9db1d521 HP |
6880 | |
6881 | ;; | |
6882 | ;;- And instructions. | |
6883 | ;; | |
6884 | ||
047d35ed AS |
6885 | (define_expand "and<mode>3" |
6886 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6887 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6888 | (match_operand:INT 2 "general_operand" ""))) | |
6889 | (clobber (reg:CC CC_REGNUM))] | |
6890 | "" | |
6891 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
6892 | ||
9db1d521 HP |
6893 | ; |
6894 | ; anddi3 instruction pattern(s). | |
6895 | ; | |
6896 | ||
6897 | (define_insn "*anddi3_cc" | |
ae156f85 | 6898 | [(set (reg CC_REGNUM) |
e3140518 RH |
6899 | (compare |
6900 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6901 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
6902 | (const_int 0))) | |
6903 | (set (match_operand:DI 0 "register_operand" "=d,d, d, d") | |
9db1d521 | 6904 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 6905 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 6906 | "@ |
d40c829f | 6907 | ngr\t%0,%2 |
65b1d8ea | 6908 | ngrk\t%0,%1,%2 |
e3140518 RH |
6909 | ng\t%0,%2 |
6910 | risbg\t%0,%1,%s2,128+%e2,0" | |
6911 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6912 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6913 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6914 | |
6915 | (define_insn "*anddi3_cconly" | |
ae156f85 | 6916 | [(set (reg CC_REGNUM) |
e3140518 RH |
6917 | (compare |
6918 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6919 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
9db1d521 | 6920 | (const_int 0))) |
e3140518 RH |
6921 | (clobber (match_scratch:DI 0 "=d,d, d, d"))] |
6922 | "TARGET_ZARCH | |
6923 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
6924 | /* Do not steal TM patterns. */ |
6925 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 6926 | "@ |
d40c829f | 6927 | ngr\t%0,%2 |
65b1d8ea | 6928 | ngrk\t%0,%1,%2 |
e3140518 RH |
6929 | ng\t%0,%2 |
6930 | risbg\t%0,%1,%s2,128+%e2,0" | |
6931 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6932 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6933 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6934 | |
3af8e996 | 6935 | (define_insn "*anddi3" |
65b1d8ea | 6936 | [(set (match_operand:DI 0 "nonimmediate_operand" |
e3140518 RH |
6937 | "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") |
6938 | (and:DI | |
6939 | (match_operand:DI 1 "nonimmediate_operand" | |
6940 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") | |
6941 | (match_operand:DI 2 "general_operand" | |
6942 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) | |
ec24698e | 6943 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6944 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6945 | "@ |
6946 | # | |
6947 | # | |
6948 | nihh\t%0,%j2 | |
6949 | nihl\t%0,%j2 | |
6950 | nilh\t%0,%j2 | |
6951 | nill\t%0,%j2 | |
6952 | nihf\t%0,%m2 | |
6953 | nilf\t%0,%m2 | |
6954 | ngr\t%0,%2 | |
65b1d8ea | 6955 | ngrk\t%0,%1,%2 |
ec24698e | 6956 | ng\t%0,%2 |
e3140518 | 6957 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
6958 | # |
6959 | #" | |
e3140518 RH |
6960 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
6961 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
6962 | (set_attr "z10prop" "*, |
6963 | *, | |
6964 | z10_super_E1, | |
6965 | z10_super_E1, | |
6966 | z10_super_E1, | |
6967 | z10_super_E1, | |
6968 | z10_super_E1, | |
6969 | z10_super_E1, | |
6970 | z10_super_E1, | |
65b1d8ea | 6971 | *, |
9381e3f1 | 6972 | z10_super_E1, |
e3140518 | 6973 | z10_super_E1, |
9381e3f1 WG |
6974 | *, |
6975 | *")]) | |
0dfa6c5e UW |
6976 | |
6977 | (define_split | |
6978 | [(set (match_operand:DI 0 "s_operand" "") | |
6979 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6980 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6981 | "reload_completed" |
6982 | [(parallel | |
6983 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6984 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6985 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6986 | |
1a2e356e RH |
6987 | ;; These two are what combine generates for (ashift (zero_extract)). |
6988 | (define_insn "*extzv_<mode>_srl" | |
6989 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6990 | (and:GPR (lshiftrt:GPR | |
6991 | (match_operand:GPR 1 "register_operand" "d") | |
6992 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6993 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6994 | (clobber (reg:CC CC_REGNUM))] | |
6995 | "TARGET_Z10 | |
6996 | /* Note that even for the SImode pattern, the rotate is always DImode. */ | |
6997 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
6998 | INTVAL (operands[3]))" | |
6999 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" | |
7000 | [(set_attr "op_type" "RIE") | |
7001 | (set_attr "z10prop" "z10_super_E1")]) | |
7002 | ||
7003 | (define_insn "*extzv_<mode>_sll" | |
7004 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7005 | (and:GPR (ashift:GPR | |
7006 | (match_operand:GPR 1 "register_operand" "d") | |
7007 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
7008 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
7009 | (clobber (reg:CC CC_REGNUM))] | |
7010 | "TARGET_Z10 | |
7011 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), | |
7012 | INTVAL (operands[3]))" | |
7013 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" | |
7014 | [(set_attr "op_type" "RIE") | |
7015 | (set_attr "z10prop" "z10_super_E1")]) | |
7016 | ||
9db1d521 HP |
7017 | |
7018 | ; | |
7019 | ; andsi3 instruction pattern(s). | |
7020 | ; | |
7021 | ||
7022 | (define_insn "*andsi3_cc" | |
ae156f85 | 7023 | [(set (reg CC_REGNUM) |
e3140518 RH |
7024 | (compare |
7025 | (and:SI | |
7026 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7027 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7028 | (const_int 0))) | |
7029 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7030 | (and:SI (match_dup 1) (match_dup 2)))] |
7031 | "s390_match_ccmode(insn, CCTmode)" | |
7032 | "@ | |
ec24698e | 7033 | nilf\t%0,%o2 |
d40c829f | 7034 | nr\t%0,%2 |
65b1d8ea | 7035 | nrk\t%0,%1,%2 |
d40c829f | 7036 | n\t%0,%2 |
e3140518 RH |
7037 | ny\t%0,%2 |
7038 | risbg\t%0,%1,%t2,128+%f2,0" | |
7039 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
7040 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
7041 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7042 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7043 | |
7044 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7045 | [(set (reg CC_REGNUM) |
e3140518 RH |
7046 | (compare |
7047 | (and:SI | |
7048 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7049 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7050 | (const_int 0))) | |
7051 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7052 | "s390_match_ccmode(insn, CCTmode) |
7053 | /* Do not steal TM patterns. */ | |
7054 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7055 | "@ |
ec24698e | 7056 | nilf\t%0,%o2 |
d40c829f | 7057 | nr\t%0,%2 |
65b1d8ea | 7058 | nrk\t%0,%1,%2 |
d40c829f | 7059 | n\t%0,%2 |
e3140518 RH |
7060 | ny\t%0,%2 |
7061 | risbg\t%0,%1,%t2,128+%f2,0" | |
7062 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
7063 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
65b1d8ea | 7064 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7065 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7066 | |
f19a9af7 | 7067 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7068 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7069 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7070 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7071 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7072 | (match_operand:SI 2 "general_operand" |
e3140518 | 7073 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q"))) |
ae156f85 | 7074 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7075 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7076 | "@ |
f19a9af7 AK |
7077 | # |
7078 | # | |
7079 | nilh\t%0,%j2 | |
2f7e5a0d | 7080 | nill\t%0,%j2 |
ec24698e | 7081 | nilf\t%0,%o2 |
d40c829f | 7082 | nr\t%0,%2 |
65b1d8ea | 7083 | nrk\t%0,%1,%2 |
d40c829f | 7084 | n\t%0,%2 |
8cb66696 | 7085 | ny\t%0,%2 |
e3140518 | 7086 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7087 | # |
19b63d8e | 7088 | #" |
e3140518 RH |
7089 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
7090 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") | |
9381e3f1 WG |
7091 | (set_attr "z10prop" "*, |
7092 | *, | |
7093 | z10_super_E1, | |
7094 | z10_super_E1, | |
7095 | z10_super_E1, | |
7096 | z10_super_E1, | |
65b1d8ea | 7097 | *, |
9381e3f1 WG |
7098 | z10_super_E1, |
7099 | z10_super_E1, | |
e3140518 | 7100 | z10_super_E1, |
9381e3f1 WG |
7101 | *, |
7102 | *")]) | |
f19a9af7 AK |
7103 | |
7104 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7105 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7106 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7107 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7108 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7109 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7110 | "@ |
7111 | nr\t%0,%2 | |
8cb66696 | 7112 | n\t%0,%2 |
0dfa6c5e | 7113 | # |
19b63d8e | 7114 | #" |
9381e3f1 WG |
7115 | [(set_attr "op_type" "RR,RX,SI,SS") |
7116 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7117 | ||
0dfa6c5e UW |
7118 | |
7119 | (define_split | |
7120 | [(set (match_operand:SI 0 "s_operand" "") | |
7121 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7122 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7123 | "reload_completed" |
7124 | [(parallel | |
7125 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7126 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7127 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7128 | |
9db1d521 HP |
7129 | ; |
7130 | ; andhi3 instruction pattern(s). | |
7131 | ; | |
7132 | ||
8cb66696 | 7133 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7134 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7135 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7136 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7137 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7138 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7139 | "@ |
d40c829f | 7140 | nr\t%0,%2 |
65b1d8ea | 7141 | nrk\t%0,%1,%2 |
8cb66696 | 7142 | nill\t%0,%x2 |
0dfa6c5e | 7143 | # |
19b63d8e | 7144 | #" |
65b1d8ea AK |
7145 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7146 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7147 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7148 | ]) |
8cb66696 UW |
7149 | |
7150 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7151 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7152 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7153 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7154 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7155 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7156 | "@ | |
7157 | nr\t%0,%2 | |
0dfa6c5e | 7158 | # |
19b63d8e | 7159 | #" |
9381e3f1 WG |
7160 | [(set_attr "op_type" "RR,SI,SS") |
7161 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7162 | ]) | |
0dfa6c5e UW |
7163 | |
7164 | (define_split | |
7165 | [(set (match_operand:HI 0 "s_operand" "") | |
7166 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7167 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7168 | "reload_completed" |
7169 | [(parallel | |
7170 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7171 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7172 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7173 | |
9db1d521 HP |
7174 | ; |
7175 | ; andqi3 instruction pattern(s). | |
7176 | ; | |
7177 | ||
8cb66696 | 7178 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7179 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7180 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7181 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7182 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7183 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7184 | "@ |
d40c829f | 7185 | nr\t%0,%2 |
65b1d8ea | 7186 | nrk\t%0,%1,%2 |
8cb66696 | 7187 | nill\t%0,%b2 |
fc0ea003 UW |
7188 | ni\t%S0,%b2 |
7189 | niy\t%S0,%b2 | |
19b63d8e | 7190 | #" |
65b1d8ea AK |
7191 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
7192 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
7193 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
7194 | |
7195 | (define_insn "*andqi3_esa" | |
7196 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7197 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7198 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7199 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7200 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7201 | "@ |
8cb66696 | 7202 | nr\t%0,%2 |
fc0ea003 | 7203 | ni\t%S0,%b2 |
19b63d8e | 7204 | #" |
9381e3f1 WG |
7205 | [(set_attr "op_type" "RR,SI,SS") |
7206 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7207 | |
19b63d8e UW |
7208 | ; |
7209 | ; Block and (NC) patterns. | |
7210 | ; | |
7211 | ||
7212 | (define_insn "*nc" | |
7213 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7214 | (and:BLK (match_dup 0) | |
7215 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7216 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7217 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7218 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7219 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7220 | [(set_attr "op_type" "SS") |
7221 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7222 | |
7223 | (define_split | |
7224 | [(set (match_operand 0 "memory_operand" "") | |
7225 | (and (match_dup 0) | |
7226 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7227 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7228 | "reload_completed |
7229 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7230 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7231 | [(parallel | |
7232 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7233 | (use (match_dup 2)) | |
ae156f85 | 7234 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7235 | { |
7236 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7237 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7238 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7239 | }) | |
7240 | ||
7241 | (define_peephole2 | |
7242 | [(parallel | |
7243 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7244 | (and:BLK (match_dup 0) | |
7245 | (match_operand:BLK 1 "memory_operand" ""))) | |
7246 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7247 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7248 | (parallel |
7249 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7250 | (and:BLK (match_dup 3) | |
7251 | (match_operand:BLK 4 "memory_operand" ""))) | |
7252 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7253 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7254 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7255 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7256 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7257 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7258 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7259 | [(parallel | |
7260 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7261 | (use (match_dup 8)) | |
ae156f85 | 7262 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7263 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7264 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7265 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7266 | ||
9db1d521 HP |
7267 | |
7268 | ;; | |
7269 | ;;- Bit set (inclusive or) instructions. | |
7270 | ;; | |
7271 | ||
047d35ed AS |
7272 | (define_expand "ior<mode>3" |
7273 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7274 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7275 | (match_operand:INT 2 "general_operand" ""))) | |
7276 | (clobber (reg:CC CC_REGNUM))] | |
7277 | "" | |
7278 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7279 | ||
9db1d521 HP |
7280 | ; |
7281 | ; iordi3 instruction pattern(s). | |
7282 | ; | |
7283 | ||
4023fb28 | 7284 | (define_insn "*iordi3_cc" |
ae156f85 | 7285 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7286 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7287 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7288 | (const_int 0))) |
65b1d8ea | 7289 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 7290 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7291 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7292 | "@ |
d40c829f | 7293 | ogr\t%0,%2 |
65b1d8ea | 7294 | ogrk\t%0,%1,%2 |
d40c829f | 7295 | og\t%0,%2" |
65b1d8ea AK |
7296 | [(set_attr "op_type" "RRE,RRF,RXY") |
7297 | (set_attr "cpu_facility" "*,z196,*") | |
7298 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7299 | |
7300 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7301 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7302 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7303 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7304 | (const_int 0))) |
65b1d8ea | 7305 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7306 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7307 | "@ |
d40c829f | 7308 | ogr\t%0,%2 |
65b1d8ea | 7309 | ogrk\t%0,%1,%2 |
d40c829f | 7310 | og\t%0,%2" |
65b1d8ea AK |
7311 | [(set_attr "op_type" "RRE,RRF,RXY") |
7312 | (set_attr "cpu_facility" "*,z196,*") | |
7313 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7314 | |
3af8e996 | 7315 | (define_insn "*iordi3" |
65b1d8ea AK |
7316 | [(set (match_operand:DI 0 "nonimmediate_operand" |
7317 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
7318 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
7319 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 7320 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 7321 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 7322 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7323 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7324 | "@ |
7325 | oihh\t%0,%i2 | |
7326 | oihl\t%0,%i2 | |
7327 | oilh\t%0,%i2 | |
7328 | oill\t%0,%i2 | |
7329 | oihf\t%0,%k2 | |
7330 | oilf\t%0,%k2 | |
7331 | ogr\t%0,%2 | |
65b1d8ea | 7332 | ogrk\t%0,%1,%2 |
ec24698e UW |
7333 | og\t%0,%2 |
7334 | # | |
7335 | #" | |
65b1d8ea AK |
7336 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7337 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7338 | (set_attr "z10prop" "z10_super_E1, |
7339 | z10_super_E1, | |
7340 | z10_super_E1, | |
7341 | z10_super_E1, | |
7342 | z10_super_E1, | |
7343 | z10_super_E1, | |
7344 | z10_super_E1, | |
65b1d8ea | 7345 | *, |
9381e3f1 WG |
7346 | z10_super_E1, |
7347 | *, | |
7348 | *")]) | |
0dfa6c5e UW |
7349 | |
7350 | (define_split | |
7351 | [(set (match_operand:DI 0 "s_operand" "") | |
7352 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7353 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7354 | "reload_completed" |
7355 | [(parallel | |
7356 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7357 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7358 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7359 | |
9db1d521 HP |
7360 | ; |
7361 | ; iorsi3 instruction pattern(s). | |
7362 | ; | |
7363 | ||
4023fb28 | 7364 | (define_insn "*iorsi3_cc" |
ae156f85 | 7365 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7366 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7367 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7368 | (const_int 0))) |
65b1d8ea | 7369 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7370 | (ior:SI (match_dup 1) (match_dup 2)))] |
7371 | "s390_match_ccmode(insn, CCTmode)" | |
7372 | "@ | |
ec24698e | 7373 | oilf\t%0,%o2 |
d40c829f | 7374 | or\t%0,%2 |
65b1d8ea | 7375 | ork\t%0,%1,%2 |
d40c829f UW |
7376 | o\t%0,%2 |
7377 | oy\t%0,%2" | |
65b1d8ea AK |
7378 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7379 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7380 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7381 | |
7382 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7383 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7384 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7385 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7386 | (const_int 0))) |
65b1d8ea | 7387 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7388 | "s390_match_ccmode(insn, CCTmode)" |
7389 | "@ | |
ec24698e | 7390 | oilf\t%0,%o2 |
d40c829f | 7391 | or\t%0,%2 |
65b1d8ea | 7392 | ork\t%0,%1,%2 |
d40c829f UW |
7393 | o\t%0,%2 |
7394 | oy\t%0,%2" | |
65b1d8ea AK |
7395 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7396 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7397 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 7398 | |
8cb66696 | 7399 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7400 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7401 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7402 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7403 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7404 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7405 | "@ |
f19a9af7 AK |
7406 | oilh\t%0,%i2 |
7407 | oill\t%0,%i2 | |
ec24698e | 7408 | oilf\t%0,%o2 |
d40c829f | 7409 | or\t%0,%2 |
65b1d8ea | 7410 | ork\t%0,%1,%2 |
d40c829f | 7411 | o\t%0,%2 |
8cb66696 | 7412 | oy\t%0,%2 |
0dfa6c5e | 7413 | # |
19b63d8e | 7414 | #" |
65b1d8ea AK |
7415 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
7416 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
7417 | (set_attr "z10prop" "z10_super_E1, |
7418 | z10_super_E1, | |
7419 | z10_super_E1, | |
7420 | z10_super_E1, | |
65b1d8ea | 7421 | *, |
9381e3f1 WG |
7422 | z10_super_E1, |
7423 | z10_super_E1, | |
7424 | *, | |
7425 | *")]) | |
8cb66696 UW |
7426 | |
7427 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7428 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7429 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7430 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7431 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7432 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7433 | "@ |
7434 | or\t%0,%2 | |
8cb66696 | 7435 | o\t%0,%2 |
0dfa6c5e | 7436 | # |
19b63d8e | 7437 | #" |
9381e3f1 WG |
7438 | [(set_attr "op_type" "RR,RX,SI,SS") |
7439 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7440 | |
7441 | (define_split | |
7442 | [(set (match_operand:SI 0 "s_operand" "") | |
7443 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7444 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7445 | "reload_completed" |
7446 | [(parallel | |
7447 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7448 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7449 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7450 | |
4023fb28 UW |
7451 | ; |
7452 | ; iorhi3 instruction pattern(s). | |
7453 | ; | |
7454 | ||
8cb66696 | 7455 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7456 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7457 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7458 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7459 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7460 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7461 | "@ |
d40c829f | 7462 | or\t%0,%2 |
65b1d8ea | 7463 | ork\t%0,%1,%2 |
8cb66696 | 7464 | oill\t%0,%x2 |
0dfa6c5e | 7465 | # |
19b63d8e | 7466 | #" |
65b1d8ea AK |
7467 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7468 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7469 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7470 | |
7471 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7472 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7473 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7474 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7475 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7476 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7477 | "@ | |
7478 | or\t%0,%2 | |
0dfa6c5e | 7479 | # |
19b63d8e | 7480 | #" |
9381e3f1 WG |
7481 | [(set_attr "op_type" "RR,SI,SS") |
7482 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7483 | |
7484 | (define_split | |
7485 | [(set (match_operand:HI 0 "s_operand" "") | |
7486 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7487 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7488 | "reload_completed" |
7489 | [(parallel | |
7490 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7491 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7492 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7493 | |
9db1d521 | 7494 | ; |
4023fb28 | 7495 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7496 | ; |
7497 | ||
8cb66696 | 7498 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7499 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7500 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7501 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7502 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7503 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7504 | "@ |
d40c829f | 7505 | or\t%0,%2 |
65b1d8ea | 7506 | ork\t%0,%1,%2 |
8cb66696 | 7507 | oill\t%0,%b2 |
fc0ea003 UW |
7508 | oi\t%S0,%b2 |
7509 | oiy\t%S0,%b2 | |
19b63d8e | 7510 | #" |
65b1d8ea AK |
7511 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
7512 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
7513 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
7514 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7515 | |
7516 | (define_insn "*iorqi3_esa" | |
7517 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7518 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7519 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7520 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7521 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7522 | "@ |
8cb66696 | 7523 | or\t%0,%2 |
fc0ea003 | 7524 | oi\t%S0,%b2 |
19b63d8e | 7525 | #" |
9381e3f1 WG |
7526 | [(set_attr "op_type" "RR,SI,SS") |
7527 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7528 | |
19b63d8e UW |
7529 | ; |
7530 | ; Block inclusive or (OC) patterns. | |
7531 | ; | |
7532 | ||
7533 | (define_insn "*oc" | |
7534 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7535 | (ior:BLK (match_dup 0) | |
7536 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7537 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7538 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7539 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7540 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7541 | [(set_attr "op_type" "SS") |
7542 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7543 | |
7544 | (define_split | |
7545 | [(set (match_operand 0 "memory_operand" "") | |
7546 | (ior (match_dup 0) | |
7547 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7548 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7549 | "reload_completed |
7550 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7551 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7552 | [(parallel | |
7553 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7554 | (use (match_dup 2)) | |
ae156f85 | 7555 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7556 | { |
7557 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7558 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7559 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7560 | }) | |
7561 | ||
7562 | (define_peephole2 | |
7563 | [(parallel | |
7564 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7565 | (ior:BLK (match_dup 0) | |
7566 | (match_operand:BLK 1 "memory_operand" ""))) | |
7567 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7568 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7569 | (parallel |
7570 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7571 | (ior:BLK (match_dup 3) | |
7572 | (match_operand:BLK 4 "memory_operand" ""))) | |
7573 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7574 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7575 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7576 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7577 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7578 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7579 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7580 | [(parallel | |
7581 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7582 | (use (match_dup 8)) | |
ae156f85 | 7583 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7584 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7585 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7586 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7587 | ||
9db1d521 HP |
7588 | |
7589 | ;; | |
7590 | ;;- Xor instructions. | |
7591 | ;; | |
7592 | ||
047d35ed AS |
7593 | (define_expand "xor<mode>3" |
7594 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7595 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7596 | (match_operand:INT 2 "general_operand" ""))) | |
7597 | (clobber (reg:CC CC_REGNUM))] | |
7598 | "" | |
7599 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7600 | ||
3c91f126 AK |
7601 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7602 | ; simplifications. So its better to have something matching. | |
7603 | (define_split | |
7604 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7605 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7606 | "" | |
7607 | [(parallel | |
7608 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7609 | (clobber (reg:CC CC_REGNUM))])] | |
7610 | { | |
7611 | operands[2] = constm1_rtx; | |
7612 | if (!s390_logical_operator_ok_p (operands)) | |
7613 | FAIL; | |
7614 | }) | |
7615 | ||
9db1d521 HP |
7616 | ; |
7617 | ; xordi3 instruction pattern(s). | |
7618 | ; | |
7619 | ||
4023fb28 | 7620 | (define_insn "*xordi3_cc" |
ae156f85 | 7621 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7622 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7623 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7624 | (const_int 0))) |
65b1d8ea | 7625 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 7626 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7627 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7628 | "@ |
d40c829f | 7629 | xgr\t%0,%2 |
65b1d8ea | 7630 | xgrk\t%0,%1,%2 |
d40c829f | 7631 | xg\t%0,%2" |
65b1d8ea | 7632 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7633 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7634 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7635 | |
7636 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7637 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7638 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7639 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7640 | (const_int 0))) |
65b1d8ea | 7641 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 7642 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7643 | "@ |
d40c829f | 7644 | xgr\t%0,%2 |
65b1d8ea | 7645 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 7646 | xg\t%0,%2" |
65b1d8ea AK |
7647 | [(set_attr "op_type" "RRE,RRF,RXY") |
7648 | (set_attr "cpu_facility" "*,z196,*") | |
7649 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7650 | |
3af8e996 | 7651 | (define_insn "*xordi3" |
65b1d8ea AK |
7652 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
7653 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
7654 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 7655 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7656 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7657 | "@ |
7658 | xihf\t%0,%k2 | |
7659 | xilf\t%0,%k2 | |
7660 | xgr\t%0,%2 | |
65b1d8ea | 7661 | xgrk\t%0,%1,%2 |
ec24698e UW |
7662 | xg\t%0,%2 |
7663 | # | |
7664 | #" | |
65b1d8ea AK |
7665 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
7666 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
7667 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
7668 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7669 | |
7670 | (define_split | |
7671 | [(set (match_operand:DI 0 "s_operand" "") | |
7672 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7673 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7674 | "reload_completed" |
7675 | [(parallel | |
7676 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7677 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7678 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 7679 | |
9db1d521 HP |
7680 | ; |
7681 | ; xorsi3 instruction pattern(s). | |
7682 | ; | |
7683 | ||
4023fb28 | 7684 | (define_insn "*xorsi3_cc" |
ae156f85 | 7685 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7686 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7687 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7688 | (const_int 0))) |
65b1d8ea | 7689 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7690 | (xor:SI (match_dup 1) (match_dup 2)))] |
7691 | "s390_match_ccmode(insn, CCTmode)" | |
7692 | "@ | |
ec24698e | 7693 | xilf\t%0,%o2 |
d40c829f | 7694 | xr\t%0,%2 |
65b1d8ea | 7695 | xrk\t%0,%1,%2 |
d40c829f UW |
7696 | x\t%0,%2 |
7697 | xy\t%0,%2" | |
65b1d8ea AK |
7698 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7699 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7700 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7701 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7702 | |
7703 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 7704 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7705 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7706 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7707 | (const_int 0))) |
65b1d8ea | 7708 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7709 | "s390_match_ccmode(insn, CCTmode)" |
7710 | "@ | |
ec24698e | 7711 | xilf\t%0,%o2 |
d40c829f | 7712 | xr\t%0,%2 |
65b1d8ea | 7713 | xrk\t%0,%1,%2 |
d40c829f UW |
7714 | x\t%0,%2 |
7715 | xy\t%0,%2" | |
65b1d8ea AK |
7716 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7717 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7718 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7719 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7720 | |
8cb66696 | 7721 | (define_insn "*xorsi3" |
65b1d8ea AK |
7722 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
7723 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
7724 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7725 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7726 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7727 | "@ |
ec24698e | 7728 | xilf\t%0,%o2 |
d40c829f | 7729 | xr\t%0,%2 |
65b1d8ea | 7730 | xrk\t%0,%1,%2 |
d40c829f | 7731 | x\t%0,%2 |
8cb66696 | 7732 | xy\t%0,%2 |
0dfa6c5e | 7733 | # |
19b63d8e | 7734 | #" |
65b1d8ea AK |
7735 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
7736 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
7737 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7738 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7739 | |
7740 | (define_split | |
7741 | [(set (match_operand:SI 0 "s_operand" "") | |
7742 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7743 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7744 | "reload_completed" |
7745 | [(parallel | |
7746 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7747 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7748 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 7749 | |
9db1d521 HP |
7750 | ; |
7751 | ; xorhi3 instruction pattern(s). | |
7752 | ; | |
7753 | ||
8cb66696 | 7754 | (define_insn "*xorhi3" |
65b1d8ea AK |
7755 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7756 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
7757 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 7758 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7759 | "s390_logical_operator_ok_p (operands)" |
7760 | "@ | |
ec24698e | 7761 | xilf\t%0,%x2 |
8cb66696 | 7762 | xr\t%0,%2 |
65b1d8ea | 7763 | xrk\t%0,%1,%2 |
0dfa6c5e | 7764 | # |
19b63d8e | 7765 | #" |
65b1d8ea AK |
7766 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
7767 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7768 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
7769 | |
7770 | (define_split | |
7771 | [(set (match_operand:HI 0 "s_operand" "") | |
7772 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7773 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7774 | "reload_completed" |
7775 | [(parallel | |
7776 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7777 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7778 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 7779 | |
9db1d521 HP |
7780 | ; |
7781 | ; xorqi3 instruction pattern(s). | |
7782 | ; | |
7783 | ||
8cb66696 | 7784 | (define_insn "*xorqi3" |
65b1d8ea AK |
7785 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7786 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
7787 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 7788 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7789 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7790 | "@ |
ec24698e | 7791 | xilf\t%0,%b2 |
8cb66696 | 7792 | xr\t%0,%2 |
65b1d8ea | 7793 | xrk\t%0,%1,%2 |
fc0ea003 UW |
7794 | xi\t%S0,%b2 |
7795 | xiy\t%S0,%b2 | |
19b63d8e | 7796 | #" |
65b1d8ea AK |
7797 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
7798 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
7799 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 7800 | |
4023fb28 | 7801 | |
19b63d8e UW |
7802 | ; |
7803 | ; Block exclusive or (XC) patterns. | |
7804 | ; | |
7805 | ||
7806 | (define_insn "*xc" | |
7807 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7808 | (xor:BLK (match_dup 0) | |
7809 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7810 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7811 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7812 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7813 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 7814 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
7815 | |
7816 | (define_split | |
7817 | [(set (match_operand 0 "memory_operand" "") | |
7818 | (xor (match_dup 0) | |
7819 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7820 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7821 | "reload_completed |
7822 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7823 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7824 | [(parallel | |
7825 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
7826 | (use (match_dup 2)) | |
ae156f85 | 7827 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7828 | { |
7829 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7830 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7831 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7832 | }) | |
7833 | ||
7834 | (define_peephole2 | |
7835 | [(parallel | |
7836 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7837 | (xor:BLK (match_dup 0) | |
7838 | (match_operand:BLK 1 "memory_operand" ""))) | |
7839 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7840 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7841 | (parallel |
7842 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7843 | (xor:BLK (match_dup 3) | |
7844 | (match_operand:BLK 4 "memory_operand" ""))) | |
7845 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7846 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7847 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7848 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7849 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7850 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7851 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7852 | [(parallel | |
7853 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
7854 | (use (match_dup 8)) | |
ae156f85 | 7855 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7856 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7857 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7858 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7859 | ||
7860 | ; | |
7861 | ; Block xor (XC) patterns with src == dest. | |
7862 | ; | |
7863 | ||
7864 | (define_insn "*xc_zero" | |
7865 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7866 | (const_int 0)) | |
7867 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 7868 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7869 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 7870 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
7871 | [(set_attr "op_type" "SS") |
7872 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7873 | |
7874 | (define_peephole2 | |
7875 | [(parallel | |
7876 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7877 | (const_int 0)) | |
7878 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 7879 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7880 | (parallel |
7881 | [(set (match_operand:BLK 2 "memory_operand" "") | |
7882 | (const_int 0)) | |
7883 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 7884 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7885 | "s390_offset_p (operands[0], operands[2], operands[1]) |
7886 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
7887 | [(parallel | |
7888 | [(set (match_dup 4) (const_int 0)) | |
7889 | (use (match_dup 5)) | |
ae156f85 | 7890 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7891 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7892 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
7893 | ||
9db1d521 HP |
7894 | |
7895 | ;; | |
7896 | ;;- Negate instructions. | |
7897 | ;; | |
7898 | ||
7899 | ; | |
9a91a21f | 7900 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
7901 | ; |
7902 | ||
9a91a21f | 7903 | (define_expand "neg<mode>2" |
9db1d521 | 7904 | [(parallel |
9a91a21f AS |
7905 | [(set (match_operand:DSI 0 "register_operand" "=d") |
7906 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 7907 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7908 | "" |
7909 | "") | |
7910 | ||
26a89301 | 7911 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 7912 | [(set (reg CC_REGNUM) |
26a89301 UW |
7913 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7914 | (match_operand:SI 1 "register_operand" "d") 0) | |
7915 | (const_int 32)) (const_int 32))) | |
7916 | (const_int 0))) | |
7917 | (set (match_operand:DI 0 "register_operand" "=d") | |
7918 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7919 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7920 | "lcgfr\t%0,%1" |
729e750f WG |
7921 | [(set_attr "op_type" "RRE") |
7922 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7923 | |
26a89301 UW |
7924 | (define_insn "*negdi2_sign" |
7925 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7926 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7927 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7928 | "TARGET_ZARCH" |
26a89301 | 7929 | "lcgfr\t%0,%1" |
729e750f WG |
7930 | [(set_attr "op_type" "RRE") |
7931 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7932 | |
43a09b63 | 7933 | ; lcr, lcgr |
9a91a21f | 7934 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7935 | [(set (reg CC_REGNUM) |
9a91a21f | 7936 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7937 | (const_int 0))) |
9a91a21f AS |
7938 | (set (match_operand:GPR 0 "register_operand" "=d") |
7939 | (neg:GPR (match_dup 1)))] | |
7940 | "s390_match_ccmode (insn, CCAmode)" | |
7941 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7942 | [(set_attr "op_type" "RR<E>") |
7943 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7944 | |
7945 | ; lcr, lcgr | |
9a91a21f | 7946 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7947 | [(set (reg CC_REGNUM) |
9a91a21f | 7948 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7949 | (const_int 0))) |
9a91a21f AS |
7950 | (clobber (match_scratch:GPR 0 "=d"))] |
7951 | "s390_match_ccmode (insn, CCAmode)" | |
7952 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7953 | [(set_attr "op_type" "RR<E>") |
7954 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7955 | |
7956 | ; lcr, lcgr | |
9a91a21f AS |
7957 | (define_insn "*neg<mode>2" |
7958 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7959 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7960 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
7961 | "" |
7962 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7963 | [(set_attr "op_type" "RR<E>") |
7964 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 7965 | |
b7d19263 | 7966 | (define_insn "*negdi2_31" |
9db1d521 HP |
7967 | [(set (match_operand:DI 0 "register_operand" "=d") |
7968 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 7969 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7970 | "!TARGET_ZARCH" |
b7d19263 AK |
7971 | "#") |
7972 | ||
7973 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
7974 | ||
7975 | ; Doing the twos complement separately on the SImode parts does an | |
7976 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
7977 | ; ... unless the +1 on the low part created an overflow. | |
7978 | ||
7979 | (define_split | |
7980 | [(set (match_operand:DI 0 "register_operand" "") | |
7981 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
7982 | (clobber (reg:CC CC_REGNUM))] | |
7983 | "!TARGET_ZARCH | |
7984 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
7985 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
7986 | && reload_completed" | |
26a89301 UW |
7987 | [(parallel |
7988 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 7989 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 7990 | (parallel |
ae156f85 | 7991 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
7992 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
7993 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
7994 | (set (pc) | |
ae156f85 | 7995 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
7996 | (pc) |
7997 | (label_ref (match_dup 6)))) | |
7998 | (parallel | |
7999 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8000 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8001 | (match_dup 6)] |
8002 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8003 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8004 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8005 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8006 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8007 | |
b7d19263 AK |
8008 | ; Like above but first make a copy of the low part of the src operand |
8009 | ; since it might overlap with the high part of the destination. | |
8010 | ||
8011 | (define_split | |
8012 | [(set (match_operand:DI 0 "register_operand" "") | |
8013 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8014 | (clobber (reg:CC CC_REGNUM))] | |
8015 | "!TARGET_ZARCH | |
8016 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8017 | && reload_completed" | |
8018 | [; Make a backup of op5 first | |
8019 | (set (match_dup 4) (match_dup 5)) | |
8020 | ; Setting op2 here might clobber op5 | |
8021 | (parallel | |
8022 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8023 | (clobber (reg:CC CC_REGNUM))]) | |
8024 | (parallel | |
8025 | [(set (reg:CCAP CC_REGNUM) | |
8026 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8027 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8028 | (set (pc) | |
8029 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8030 | (pc) | |
8031 | (label_ref (match_dup 6)))) | |
8032 | (parallel | |
8033 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8034 | (clobber (reg:CC CC_REGNUM))]) | |
8035 | (match_dup 6)] | |
8036 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8037 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8038 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8039 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8040 | operands[6] = gen_label_rtx ();") | |
8041 | ||
9db1d521 | 8042 | ; |
f5905b37 | 8043 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8044 | ; |
8045 | ||
f5905b37 | 8046 | (define_expand "neg<mode>2" |
9db1d521 | 8047 | [(parallel |
7b6baae1 AK |
8048 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8049 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8050 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8051 | "TARGET_HARD_FLOAT" |
8052 | "") | |
8053 | ||
43a09b63 | 8054 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8055 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8056 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8057 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8058 | (match_operand:BFP 2 "const0_operand" ""))) | |
8059 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8060 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8061 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8062 | "lc<xde>br\t%0,%1" |
26a89301 | 8063 | [(set_attr "op_type" "RRE") |
f5905b37 | 8064 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8065 | |
8066 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8067 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8068 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8069 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8070 | (match_operand:BFP 2 "const0_operand" ""))) | |
8071 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8072 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8073 | "lc<xde>br\t%0,%1" |
26a89301 | 8074 | [(set_attr "op_type" "RRE") |
f5905b37 | 8075 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8076 | |
85dae55a AK |
8077 | ; lcdfr |
8078 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8079 | [(set (match_operand:FP 0 "register_operand" "=f") |
8080 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8081 | "TARGET_DFP" |
85dae55a AK |
8082 | "lcdfr\t%0,%1" |
8083 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8084 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8085 | |
43a09b63 | 8086 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8087 | ; FIXME: wflcdb does not clobber cc |
f5905b37 | 8088 | (define_insn "*neg<mode>2" |
62d3f261 AK |
8089 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8090 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8091 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8092 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8093 | "@ |
8094 | lc<xde>br\t%0,%1 | |
8095 | wflcdb\t%0,%1" | |
8096 | [(set_attr "op_type" "RRE,VRR") | |
8097 | (set_attr "cpu_facility" "*,vec") | |
62d3f261 AK |
8098 | (set_attr "type" "fsimp<mode>,*") |
8099 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8100 | |
9db1d521 HP |
8101 | |
8102 | ;; | |
8103 | ;;- Absolute value instructions. | |
8104 | ;; | |
8105 | ||
8106 | ; | |
9a91a21f | 8107 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8108 | ; |
8109 | ||
26a89301 | 8110 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8111 | [(set (reg CC_REGNUM) |
26a89301 UW |
8112 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8113 | (match_operand:SI 1 "register_operand" "d") 0) | |
8114 | (const_int 32)) (const_int 32))) | |
8115 | (const_int 0))) | |
8116 | (set (match_operand:DI 0 "register_operand" "=d") | |
8117 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8118 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8119 | "lpgfr\t%0,%1" |
729e750f WG |
8120 | [(set_attr "op_type" "RRE") |
8121 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8122 | |
8123 | (define_insn "*absdi2_sign" | |
8124 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8125 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8126 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8127 | "TARGET_ZARCH" |
26a89301 | 8128 | "lpgfr\t%0,%1" |
729e750f WG |
8129 | [(set_attr "op_type" "RRE") |
8130 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8131 | |
43a09b63 | 8132 | ; lpr, lpgr |
9a91a21f | 8133 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8134 | [(set (reg CC_REGNUM) |
9a91a21f | 8135 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8136 | (const_int 0))) |
9a91a21f AS |
8137 | (set (match_operand:GPR 0 "register_operand" "=d") |
8138 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8139 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8140 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8141 | [(set_attr "op_type" "RR<E>") |
8142 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8143 | |
9381e3f1 | 8144 | ; lpr, lpgr |
9a91a21f | 8145 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8146 | [(set (reg CC_REGNUM) |
9a91a21f | 8147 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8148 | (const_int 0))) |
9a91a21f | 8149 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8150 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8151 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8152 | [(set_attr "op_type" "RR<E>") |
8153 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8154 | |
8155 | ; lpr, lpgr | |
9a91a21f AS |
8156 | (define_insn "abs<mode>2" |
8157 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8158 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8159 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8160 | "" |
9a91a21f | 8161 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8162 | [(set_attr "op_type" "RR<E>") |
8163 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8164 | |
9db1d521 | 8165 | ; |
f5905b37 | 8166 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8167 | ; |
8168 | ||
f5905b37 | 8169 | (define_expand "abs<mode>2" |
9db1d521 | 8170 | [(parallel |
7b6baae1 AK |
8171 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8172 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8173 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8174 | "TARGET_HARD_FLOAT" |
8175 | "") | |
8176 | ||
43a09b63 | 8177 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8178 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8179 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8180 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8181 | (match_operand:BFP 2 "const0_operand" ""))) | |
8182 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8183 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8184 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8185 | "lp<xde>br\t%0,%1" |
26a89301 | 8186 | [(set_attr "op_type" "RRE") |
f5905b37 | 8187 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8188 | |
8189 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8190 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8191 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8192 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8193 | (match_operand:BFP 2 "const0_operand" ""))) | |
8194 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8195 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8196 | "lp<xde>br\t%0,%1" |
26a89301 | 8197 | [(set_attr "op_type" "RRE") |
f5905b37 | 8198 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8199 | |
85dae55a AK |
8200 | ; lpdfr |
8201 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8202 | [(set (match_operand:FP 0 "register_operand" "=f") |
8203 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8204 | "TARGET_DFP" |
85dae55a AK |
8205 | "lpdfr\t%0,%1" |
8206 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8207 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8208 | |
43a09b63 | 8209 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8210 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8211 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8212 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8213 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8214 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8215 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8216 | "@ |
8217 | lp<xde>br\t%0,%1 | |
8218 | wflpdb\t%0,%1" | |
8219 | [(set_attr "op_type" "RRE,VRR") | |
8220 | (set_attr "cpu_facility" "*,vec") | |
62d3f261 AK |
8221 | (set_attr "type" "fsimp<mode>,*") |
8222 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8223 | |
9db1d521 | 8224 | |
3ef093a8 AK |
8225 | ;; |
8226 | ;;- Negated absolute value instructions | |
8227 | ;; | |
8228 | ||
8229 | ; | |
8230 | ; Integer | |
8231 | ; | |
8232 | ||
26a89301 | 8233 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8234 | [(set (reg CC_REGNUM) |
26a89301 UW |
8235 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8236 | (match_operand:SI 1 "register_operand" "d") 0) | |
8237 | (const_int 32)) (const_int 32)))) | |
8238 | (const_int 0))) | |
8239 | (set (match_operand:DI 0 "register_operand" "=d") | |
8240 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8241 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8242 | "lngfr\t%0,%1" |
729e750f WG |
8243 | [(set_attr "op_type" "RRE") |
8244 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8245 | |
26a89301 UW |
8246 | (define_insn "*negabsdi2_sign" |
8247 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8248 | (neg:DI (abs:DI (sign_extend:DI | |
8249 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8250 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8251 | "TARGET_ZARCH" |
26a89301 | 8252 | "lngfr\t%0,%1" |
729e750f WG |
8253 | [(set_attr "op_type" "RRE") |
8254 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8255 | |
43a09b63 | 8256 | ; lnr, lngr |
9a91a21f | 8257 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8258 | [(set (reg CC_REGNUM) |
9a91a21f | 8259 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8260 | (const_int 0))) |
9a91a21f AS |
8261 | (set (match_operand:GPR 0 "register_operand" "=d") |
8262 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8263 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8264 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8265 | [(set_attr "op_type" "RR<E>") |
8266 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8267 | |
8268 | ; lnr, lngr | |
9a91a21f | 8269 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8270 | [(set (reg CC_REGNUM) |
9a91a21f | 8271 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8272 | (const_int 0))) |
9a91a21f | 8273 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8274 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8275 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8276 | [(set_attr "op_type" "RR<E>") |
8277 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8278 | |
8279 | ; lnr, lngr | |
9a91a21f AS |
8280 | (define_insn "*negabs<mode>2" |
8281 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8282 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8283 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8284 | "" |
9a91a21f | 8285 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8286 | [(set_attr "op_type" "RR<E>") |
8287 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8288 | |
3ef093a8 AK |
8289 | ; |
8290 | ; Floating point | |
8291 | ; | |
8292 | ||
43a09b63 | 8293 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8294 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8295 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8296 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8297 | (match_operand:BFP 2 "const0_operand" ""))) | |
8298 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8299 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8300 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8301 | "ln<xde>br\t%0,%1" |
26a89301 | 8302 | [(set_attr "op_type" "RRE") |
f5905b37 | 8303 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8304 | |
8305 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8306 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8307 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8308 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8309 | (match_operand:BFP 2 "const0_operand" ""))) | |
8310 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8311 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8312 | "ln<xde>br\t%0,%1" |
26a89301 | 8313 | [(set_attr "op_type" "RRE") |
f5905b37 | 8314 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8315 | |
85dae55a AK |
8316 | ; lndfr |
8317 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8318 | [(set (match_operand:FP 0 "register_operand" "=f") |
8319 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8320 | "TARGET_DFP" |
85dae55a AK |
8321 | "lndfr\t%0,%1" |
8322 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8323 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8324 | |
43a09b63 | 8325 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8326 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8327 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8328 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8329 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8330 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8331 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8332 | "@ |
8333 | ln<xde>br\t%0,%1 | |
8334 | wflndb\t%0,%1" | |
8335 | [(set_attr "op_type" "RRE,VRR") | |
8336 | (set_attr "cpu_facility" "*,vec") | |
62d3f261 AK |
8337 | (set_attr "type" "fsimp<mode>,*") |
8338 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8339 | |
4023fb28 UW |
8340 | ;; |
8341 | ;;- Square root instructions. | |
8342 | ;; | |
8343 | ||
8344 | ; | |
f5905b37 | 8345 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8346 | ; |
8347 | ||
9381e3f1 | 8348 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8349 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8350 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8351 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8352 | "TARGET_HARD_FLOAT" |
4023fb28 | 8353 | "@ |
f61a2c7d | 8354 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8355 | sq<xde>b\t%0,%1 |
8356 | wfsqdb\t%v0,%v1" | |
8357 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8358 | (set_attr "type" "fsqrt<mode>") | |
62d3f261 AK |
8359 | (set_attr "cpu_facility" "*,*,vec") |
8360 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) | |
4023fb28 | 8361 | |
9db1d521 HP |
8362 | |
8363 | ;; | |
8364 | ;;- One complement instructions. | |
8365 | ;; | |
8366 | ||
8367 | ; | |
342cf42b | 8368 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8369 | ; |
c7453384 | 8370 | |
342cf42b | 8371 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8372 | [(parallel |
342cf42b AS |
8373 | [(set (match_operand:INT 0 "register_operand" "") |
8374 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8375 | (const_int -1))) | |
ae156f85 | 8376 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8377 | "" |
4023fb28 | 8378 | "") |
9db1d521 HP |
8379 | |
8380 | ||
ec24698e UW |
8381 | ;; |
8382 | ;; Find leftmost bit instructions. | |
8383 | ;; | |
8384 | ||
8385 | (define_expand "clzdi2" | |
8386 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8387 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8388 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8389 | { |
8390 | rtx insn, clz_equal; | |
8391 | rtx wide_reg = gen_reg_rtx (TImode); | |
8392 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
8393 | ||
8394 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8395 | ||
8396 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8397 | ||
9381e3f1 | 8398 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8399 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8400 | |
8401 | DONE; | |
8402 | }) | |
8403 | ||
8404 | (define_insn "clztidi2" | |
8405 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8406 | (ior:TI | |
9381e3f1 WG |
8407 | (ashift:TI |
8408 | (zero_extend:TI | |
ec24698e UW |
8409 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8410 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8411 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8412 | |
ec24698e UW |
8413 | (const_int 64)) |
8414 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8415 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 8416 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 8417 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 8418 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8419 | "flogr\t%0,%1" |
8420 | [(set_attr "op_type" "RRE")]) | |
8421 | ||
8422 | ||
9db1d521 HP |
8423 | ;; |
8424 | ;;- Rotate instructions. | |
8425 | ;; | |
8426 | ||
8427 | ; | |
9a91a21f | 8428 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8429 | ; |
8430 | ||
191eb16d AK |
8431 | (define_expand "rotl<mode>3" |
8432 | [(set (match_operand:GPR 0 "register_operand" "") | |
8433 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8434 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
9e8327e3 | 8435 | "TARGET_CPU_ZARCH" |
191eb16d | 8436 | "") |
9db1d521 | 8437 | |
43a09b63 | 8438 | ; rll, rllg |
191eb16d AK |
8439 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8440 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8441 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8442 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8443 | "TARGET_CPU_ZARCH" | |
8444 | "rll<g>\t%0,%1,<addr_style_op_ops>" | |
4989e88a | 8445 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8446 | (set_attr "atype" "reg") |
191eb16d | 8447 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8448 | |
9db1d521 HP |
8449 | |
8450 | ;; | |
f337b930 | 8451 | ;;- Shift instructions. |
9db1d521 | 8452 | ;; |
9db1d521 HP |
8453 | |
8454 | ; | |
1b48c8cc | 8455 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8456 | ; Left shifts and logical right shifts |
9db1d521 | 8457 | |
1b48c8cc AS |
8458 | (define_expand "<shift><mode>3" |
8459 | [(set (match_operand:DSI 0 "register_operand" "") | |
8460 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8461 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8462 | "" |
8463 | "") | |
8464 | ||
adf22b3f | 8465 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8466 | ; sldl, srdl |
adf22b3f AK |
8467 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8468 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8469 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8470 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8471 | "!TARGET_ZARCH" |
adf22b3f | 8472 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8473 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8474 | (set_attr "atype" "reg") |
8475 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8476 | |
adf22b3f AK |
8477 | |
8478 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8479 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8480 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8481 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8482 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8483 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8484 | "" |
65b1d8ea | 8485 | "@ |
adf22b3f AK |
8486 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8487 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8488 | [(set_attr "op_type" "RS<E>,RSY") |
8489 | (set_attr "atype" "reg,reg") | |
8490 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8491 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8492 | |
9db1d521 | 8493 | ; |
1b48c8cc | 8494 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8495 | ; Arithmetic right shifts |
9db1d521 | 8496 | |
1b48c8cc | 8497 | (define_expand "ashr<mode>3" |
9db1d521 | 8498 | [(parallel |
1b48c8cc AS |
8499 | [(set (match_operand:DSI 0 "register_operand" "") |
8500 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8501 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8502 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8503 | "" |
8504 | "") | |
8505 | ||
a9fcf821 AK |
8506 | ; FIXME: The number of alternatives is doubled here to match the fix |
8507 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8508 | ; The right fix should be to support match_scratch in the output | |
8509 | ; pattern of a define_subst. | |
8510 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8511 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8512 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8513 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8514 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8515 | "!TARGET_ZARCH" |
65b1d8ea | 8516 | "@ |
a9fcf821 AK |
8517 | srda\t%0,<addr_style_op_cc_ops> |
8518 | srda\t%0,<addr_style_op_cc_ops>" | |
8519 | [(set_attr "op_type" "RS") | |
8520 | (set_attr "atype" "reg")]) | |
ecbe845e | 8521 | |
ecbe845e | 8522 | |
43a09b63 | 8523 | ; sra, srag |
a9fcf821 AK |
8524 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8525 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8526 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8527 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8528 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8529 | "" |
65b1d8ea | 8530 | "@ |
a9fcf821 AK |
8531 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8532 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8533 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8534 | (set_attr "atype" "reg") |
01496eca | 8535 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8536 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8537 | |
9db1d521 | 8538 | |
9db1d521 HP |
8539 | ;; |
8540 | ;; Branch instruction patterns. | |
8541 | ;; | |
8542 | ||
f90b7a5a | 8543 | (define_expand "cbranch<mode>4" |
fa77b251 | 8544 | [(set (pc) |
f90b7a5a PB |
8545 | (if_then_else (match_operator 0 "comparison_operator" |
8546 | [(match_operand:GPR 1 "register_operand" "") | |
8547 | (match_operand:GPR 2 "general_operand" "")]) | |
8548 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8549 | (pc)))] |
ba956982 | 8550 | "" |
f90b7a5a PB |
8551 | "s390_emit_jump (operands[3], |
8552 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8553 | DONE;") | |
8554 | ||
8555 | (define_expand "cbranch<mode>4" | |
8556 | [(set (pc) | |
8557 | (if_then_else (match_operator 0 "comparison_operator" | |
8558 | [(match_operand:FP 1 "register_operand" "") | |
8559 | (match_operand:FP 2 "general_operand" "")]) | |
8560 | (label_ref (match_operand 3 "" "")) | |
8561 | (pc)))] | |
8562 | "TARGET_HARD_FLOAT" | |
8563 | "s390_emit_jump (operands[3], | |
8564 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8565 | DONE;") | |
8566 | ||
8567 | (define_expand "cbranchcc4" | |
8568 | [(set (pc) | |
de6fba39 | 8569 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8570 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8571 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8572 | (label_ref (match_operand 3 "" "")) |
8573 | (pc)))] | |
de6fba39 UW |
8574 | "" |
8575 | "") | |
ba956982 | 8576 | |
9db1d521 HP |
8577 | |
8578 | ;; | |
8579 | ;;- Conditional jump instructions. | |
8580 | ;; | |
8581 | ||
6590e19a UW |
8582 | (define_insn "*cjump_64" |
8583 | [(set (pc) | |
8584 | (if_then_else | |
5a3fe9b6 AK |
8585 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8586 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8587 | (label_ref (match_operand 0 "" "")) |
8588 | (pc)))] | |
8589 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8590 | { |
13e58269 | 8591 | if (get_attr_length (insn) == 4) |
d40c829f | 8592 | return "j%C1\t%l0"; |
6590e19a | 8593 | else |
d40c829f | 8594 | return "jg%C1\t%l0"; |
6590e19a UW |
8595 | } |
8596 | [(set_attr "op_type" "RI") | |
8597 | (set_attr "type" "branch") | |
8598 | (set (attr "length") | |
8599 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8600 | (const_int 4) (const_int 6)))]) | |
8601 | ||
8602 | (define_insn "*cjump_31" | |
8603 | [(set (pc) | |
8604 | (if_then_else | |
5a3fe9b6 AK |
8605 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8606 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8607 | (label_ref (match_operand 0 "" "")) |
8608 | (pc)))] | |
8609 | "!TARGET_CPU_ZARCH" | |
8610 | { | |
8d933e31 AS |
8611 | gcc_assert (get_attr_length (insn) == 4); |
8612 | return "j%C1\t%l0"; | |
10bbf137 | 8613 | } |
9db1d521 | 8614 | [(set_attr "op_type" "RI") |
077dab3b | 8615 | (set_attr "type" "branch") |
13e58269 | 8616 | (set (attr "length") |
d7f99b2c | 8617 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8618 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8619 | (const_int 4) (const_int 6)) | |
8620 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8621 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8622 | |
f314b9b1 | 8623 | (define_insn "*cjump_long" |
6590e19a UW |
8624 | [(set (pc) |
8625 | (if_then_else | |
ae156f85 | 8626 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8627 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8628 | (pc)))] |
9db1d521 | 8629 | "" |
f314b9b1 UW |
8630 | { |
8631 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8632 | return "b%C1r\t%0"; |
f314b9b1 | 8633 | else |
d40c829f | 8634 | return "b%C1\t%a0"; |
10bbf137 | 8635 | } |
c7453384 | 8636 | [(set (attr "op_type") |
f314b9b1 UW |
8637 | (if_then_else (match_operand 0 "register_operand" "") |
8638 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 8639 | (set_attr "type" "branch") |
077dab3b | 8640 | (set_attr "atype" "agen")]) |
9db1d521 | 8641 | |
177bc204 RS |
8642 | ;; A conditional return instruction. |
8643 | (define_insn "*c<code>" | |
8644 | [(set (pc) | |
8645 | (if_then_else | |
8646 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8647 | (ANY_RETURN) | |
8648 | (pc)))] | |
8649 | "s390_can_use_<code>_insn ()" | |
8650 | "b%C0r\t%%r14" | |
8651 | [(set_attr "op_type" "RR") | |
8652 | (set_attr "type" "jsr") | |
8653 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8654 | |
8655 | ;; | |
8656 | ;;- Negated conditional jump instructions. | |
8657 | ;; | |
8658 | ||
6590e19a UW |
8659 | (define_insn "*icjump_64" |
8660 | [(set (pc) | |
8661 | (if_then_else | |
ae156f85 | 8662 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8663 | (pc) |
8664 | (label_ref (match_operand 0 "" ""))))] | |
8665 | "TARGET_CPU_ZARCH" | |
c7453384 | 8666 | { |
13e58269 | 8667 | if (get_attr_length (insn) == 4) |
d40c829f | 8668 | return "j%D1\t%l0"; |
6590e19a | 8669 | else |
d40c829f | 8670 | return "jg%D1\t%l0"; |
6590e19a UW |
8671 | } |
8672 | [(set_attr "op_type" "RI") | |
8673 | (set_attr "type" "branch") | |
8674 | (set (attr "length") | |
8675 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8676 | (const_int 4) (const_int 6)))]) | |
8677 | ||
8678 | (define_insn "*icjump_31" | |
8679 | [(set (pc) | |
8680 | (if_then_else | |
ae156f85 | 8681 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8682 | (pc) |
8683 | (label_ref (match_operand 0 "" ""))))] | |
8684 | "!TARGET_CPU_ZARCH" | |
8685 | { | |
8d933e31 AS |
8686 | gcc_assert (get_attr_length (insn) == 4); |
8687 | return "j%D1\t%l0"; | |
10bbf137 | 8688 | } |
9db1d521 | 8689 | [(set_attr "op_type" "RI") |
077dab3b | 8690 | (set_attr "type" "branch") |
13e58269 | 8691 | (set (attr "length") |
d7f99b2c | 8692 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8693 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8694 | (const_int 4) (const_int 6)) | |
8695 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8696 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8697 | |
f314b9b1 | 8698 | (define_insn "*icjump_long" |
6590e19a UW |
8699 | [(set (pc) |
8700 | (if_then_else | |
ae156f85 | 8701 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 8702 | (pc) |
4fe6dea8 | 8703 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 8704 | "" |
f314b9b1 UW |
8705 | { |
8706 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8707 | return "b%D1r\t%0"; |
f314b9b1 | 8708 | else |
d40c829f | 8709 | return "b%D1\t%a0"; |
10bbf137 | 8710 | } |
c7453384 | 8711 | [(set (attr "op_type") |
f314b9b1 UW |
8712 | (if_then_else (match_operand 0 "register_operand" "") |
8713 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8714 | (set_attr "type" "branch") |
8715 | (set_attr "atype" "agen")]) | |
9db1d521 | 8716 | |
4456530d HP |
8717 | ;; |
8718 | ;;- Trap instructions. | |
8719 | ;; | |
8720 | ||
8721 | (define_insn "trap" | |
8722 | [(trap_if (const_int 1) (const_int 0))] | |
8723 | "" | |
d40c829f | 8724 | "j\t.+2" |
6590e19a | 8725 | [(set_attr "op_type" "RI") |
077dab3b | 8726 | (set_attr "type" "branch")]) |
4456530d | 8727 | |
f90b7a5a PB |
8728 | (define_expand "ctrap<mode>4" |
8729 | [(trap_if (match_operator 0 "comparison_operator" | |
8730 | [(match_operand:GPR 1 "register_operand" "") | |
8731 | (match_operand:GPR 2 "general_operand" "")]) | |
8732 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 8733 | "" |
f90b7a5a PB |
8734 | { |
8735 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8736 | operands[1], operands[2]); | |
8737 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8738 | DONE; | |
8739 | }) | |
8740 | ||
8741 | (define_expand "ctrap<mode>4" | |
8742 | [(trap_if (match_operator 0 "comparison_operator" | |
8743 | [(match_operand:FP 1 "register_operand" "") | |
8744 | (match_operand:FP 2 "general_operand" "")]) | |
8745 | (match_operand 3 "const0_operand" ""))] | |
8746 | "" | |
8747 | { | |
8748 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8749 | operands[1], operands[2]); | |
8750 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8751 | DONE; | |
8752 | }) | |
4456530d | 8753 | |
f90b7a5a PB |
8754 | (define_insn "condtrap" |
8755 | [(trap_if (match_operator 0 "s390_comparison" | |
8756 | [(match_operand 1 "cc_reg_operand" "c") | |
8757 | (const_int 0)]) | |
4456530d HP |
8758 | (const_int 0))] |
8759 | "" | |
d40c829f | 8760 | "j%C0\t.+2"; |
077dab3b HP |
8761 | [(set_attr "op_type" "RI") |
8762 | (set_attr "type" "branch")]) | |
9db1d521 | 8763 | |
963fc8d0 AK |
8764 | ; crt, cgrt, cit, cgit |
8765 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
8766 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
8767 | [(match_operand:GPR 1 "register_operand" "d,d") | |
8768 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
8769 | (const_int 0))] | |
8770 | "TARGET_Z10" | |
8771 | "@ | |
8772 | c<g>rt%C0\t%1,%2 | |
8773 | c<g>it%C0\t%1,%h2" | |
8774 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 8775 | (set_attr "type" "branch") |
729e750f | 8776 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 8777 | |
22ac2c2f | 8778 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
8779 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
8780 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
22ac2c2f AK |
8781 | [(match_operand:GPR 1 "register_operand" "d,d, d") |
8782 | (match_operand:GPR 2 "general_operand" "d,D,RT")]) | |
963fc8d0 AK |
8783 | (const_int 0))] |
8784 | "TARGET_Z10" | |
8785 | "@ | |
8786 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
8787 | cl<gf>it%C0\t%1,%x2 |
8788 | cl<g>t%C0\t%1,%2" | |
8789 | [(set_attr "op_type" "RRF,RIE,RSY") | |
8790 | (set_attr "type" "branch") | |
8791 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
8792 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
8793 | ||
8794 | ; lat, lgat | |
8795 | (define_insn "*load_and_trap<mode>" | |
8796 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") | |
8797 | (const_int 0)) | |
8798 | (const_int 0)) | |
8799 | (set (match_operand:GPR 1 "register_operand" "=d") | |
8800 | (match_dup 0))] | |
8801 | "TARGET_ZEC12" | |
8802 | "l<g>at\t%1,%0" | |
8803 | [(set_attr "op_type" "RXY")]) | |
8804 | ||
963fc8d0 | 8805 | |
9db1d521 | 8806 | ;; |
0a3bdf9d | 8807 | ;;- Loop instructions. |
9db1d521 | 8808 | ;; |
0a3bdf9d UW |
8809 | ;; This is all complicated by the fact that since this is a jump insn |
8810 | ;; we must handle our own output reloads. | |
c7453384 | 8811 | |
f1149235 AK |
8812 | ;; branch on index |
8813 | ||
8814 | ; This splitter will be matched by combine and has to add the 2 moves | |
8815 | ; necessary to load the compare and the increment values into a | |
8816 | ; register pair as needed by brxle. | |
8817 | ||
8818 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
8819 | [(set (pc) | |
8820 | (if_then_else | |
8821 | (match_operator 6 "s390_brx_operator" | |
8822 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
8823 | (match_operand:GPR 2 "general_operand" "")) | |
8824 | (match_operand:GPR 3 "register_operand" "")]) | |
8825 | (label_ref (match_operand 0 "" "")) | |
8826 | (pc))) | |
8827 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
8828 | (plus:GPR (match_dup 1) (match_dup 2))) | |
8829 | (clobber (match_scratch:GPR 5 ""))] | |
8830 | "TARGET_CPU_ZARCH" | |
8831 | "#" | |
8832 | "!reload_completed && !reload_in_progress" | |
8833 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
8834 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
8835 | (parallel [(set (pc) | |
8836 | (if_then_else | |
8837 | (match_op_dup 6 | |
8838 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
8839 | (match_dup 8)]) | |
8840 | (label_ref (match_dup 0)) | |
8841 | (pc))) | |
8842 | (set (match_dup 4) | |
8843 | (plus:GPR (match_dup 1) (match_dup 7))) | |
8844 | (clobber (match_dup 5)) | |
8845 | (clobber (reg:CC CC_REGNUM))])] | |
8846 | { | |
8847 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
8848 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
8849 | gen_highpart (word_mode, dreg)); | |
8850 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
8851 | gen_lowpart (word_mode, dreg)); | |
8852 | }) | |
8853 | ||
8854 | ; brxlg, brxhg | |
8855 | ||
8856 | (define_insn_and_split "*brxg_64bit" | |
8857 | [(set (pc) | |
8858 | (if_then_else | |
8859 | (match_operator 5 "s390_brx_operator" | |
8860 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
8861 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
8862 | (subreg:DI (match_dup 2) 8)]) | |
8863 | (label_ref (match_operand 0 "" "")) | |
8864 | (pc))) | |
8865 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
8866 | (plus:DI (match_dup 1) | |
8867 | (subreg:DI (match_dup 2) 0))) | |
8868 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
8869 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8870 | "TARGET_ZARCH" |
f1149235 AK |
8871 | { |
8872 | if (which_alternative != 0) | |
8873 | return "#"; | |
8874 | else if (get_attr_length (insn) == 6) | |
8875 | return "brx%E5g\t%1,%2,%l0"; | |
8876 | else | |
8877 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
8878 | } | |
8879 | "&& reload_completed | |
8880 | && (!REG_P (operands[3]) | |
8881 | || !rtx_equal_p (operands[1], operands[3]))" | |
8882 | [(set (match_dup 4) (match_dup 1)) | |
8883 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
8884 | (clobber (reg:CC CC_REGNUM))]) | |
8885 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
8886 | (set (match_dup 3) (match_dup 4)) | |
8887 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8888 | (label_ref (match_dup 0)) | |
8889 | (pc)))] | |
8890 | "" | |
8891 | [(set_attr "op_type" "RIE") | |
8892 | (set_attr "type" "branch") | |
8893 | (set (attr "length") | |
8894 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8895 | (const_int 6) (const_int 16)))]) | |
8896 | ||
8897 | ; brxle, brxh | |
8898 | ||
8899 | (define_insn_and_split "*brx_64bit" | |
8900 | [(set (pc) | |
8901 | (if_then_else | |
8902 | (match_operator 5 "s390_brx_operator" | |
8903 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8904 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
8905 | (subreg:SI (match_dup 2) 12)]) | |
8906 | (label_ref (match_operand 0 "" "")) | |
8907 | (pc))) | |
8908 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8909 | (plus:SI (match_dup 1) | |
8910 | (subreg:SI (match_dup 2) 4))) | |
8911 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8912 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8913 | "TARGET_ZARCH" |
f1149235 AK |
8914 | { |
8915 | if (which_alternative != 0) | |
8916 | return "#"; | |
8917 | else if (get_attr_length (insn) == 6) | |
8918 | return "brx%C5\t%1,%2,%l0"; | |
8919 | else | |
8920 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8921 | } | |
8922 | "&& reload_completed | |
8923 | && (!REG_P (operands[3]) | |
8924 | || !rtx_equal_p (operands[1], operands[3]))" | |
8925 | [(set (match_dup 4) (match_dup 1)) | |
8926 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8927 | (clobber (reg:CC CC_REGNUM))]) | |
8928 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
8929 | (set (match_dup 3) (match_dup 4)) | |
8930 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8931 | (label_ref (match_dup 0)) | |
8932 | (pc)))] | |
8933 | "" | |
8934 | [(set_attr "op_type" "RSI") | |
8935 | (set_attr "type" "branch") | |
8936 | (set (attr "length") | |
8937 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8938 | (const_int 6) (const_int 14)))]) | |
8939 | ||
8940 | ; brxle, brxh | |
8941 | ||
8942 | (define_insn_and_split "*brx_31bit" | |
8943 | [(set (pc) | |
8944 | (if_then_else | |
8945 | (match_operator 5 "s390_brx_operator" | |
8946 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8947 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
8948 | (subreg:SI (match_dup 2) 4)]) | |
8949 | (label_ref (match_operand 0 "" "")) | |
8950 | (pc))) | |
8951 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8952 | (plus:SI (match_dup 1) | |
8953 | (subreg:SI (match_dup 2) 0))) | |
8954 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8955 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8956 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
8957 | { |
8958 | if (which_alternative != 0) | |
8959 | return "#"; | |
8960 | else if (get_attr_length (insn) == 6) | |
8961 | return "brx%C5\t%1,%2,%l0"; | |
8962 | else | |
8963 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8964 | } | |
8965 | "&& reload_completed | |
8966 | && (!REG_P (operands[3]) | |
8967 | || !rtx_equal_p (operands[1], operands[3]))" | |
8968 | [(set (match_dup 4) (match_dup 1)) | |
8969 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
8970 | (clobber (reg:CC CC_REGNUM))]) | |
8971 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8972 | (set (match_dup 3) (match_dup 4)) | |
8973 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8974 | (label_ref (match_dup 0)) | |
8975 | (pc)))] | |
8976 | "" | |
8977 | [(set_attr "op_type" "RSI") | |
8978 | (set_attr "type" "branch") | |
8979 | (set (attr "length") | |
8980 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8981 | (const_int 6) (const_int 14)))]) | |
8982 | ||
8983 | ||
8984 | ;; branch on count | |
8985 | ||
0a3bdf9d UW |
8986 | (define_expand "doloop_end" |
8987 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 8988 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 8989 | "" |
0a3bdf9d | 8990 | { |
6590e19a | 8991 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 8992 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 8993 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 8994 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 8995 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 8996 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
8997 | else |
8998 | FAIL; | |
8999 | ||
9000 | DONE; | |
10bbf137 | 9001 | }) |
0a3bdf9d | 9002 | |
6590e19a | 9003 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9004 | [(set (pc) |
9005 | (if_then_else | |
7e665d18 | 9006 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9007 | (const_int 1)) |
9008 | (label_ref (match_operand 0 "" "")) | |
9009 | (pc))) | |
7e665d18 | 9010 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9011 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9012 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9013 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9014 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9015 | { |
9016 | if (which_alternative != 0) | |
10bbf137 | 9017 | return "#"; |
0a3bdf9d | 9018 | else if (get_attr_length (insn) == 4) |
d40c829f | 9019 | return "brct\t%1,%l0"; |
6590e19a | 9020 | else |
545d16ff | 9021 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9022 | } |
9023 | "&& reload_completed | |
9024 | && (! REG_P (operands[2]) | |
9025 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9026 | [(set (match_dup 3) (match_dup 1)) |
9027 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9028 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9029 | (const_int 0))) | |
9030 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9031 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9032 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9033 | (label_ref (match_dup 0)) |
9034 | (pc)))] | |
9035 | "" | |
9036 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9037 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9038 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9039 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9040 | (set_attr "type" "branch") |
9041 | (set (attr "length") | |
9042 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9043 | (const_int 4) (const_int 10)))]) | |
9044 | ||
9045 | (define_insn_and_split "doloop_si31" | |
9046 | [(set (pc) | |
9047 | (if_then_else | |
7e665d18 | 9048 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
9049 | (const_int 1)) |
9050 | (label_ref (match_operand 0 "" "")) | |
9051 | (pc))) | |
7e665d18 | 9052 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 9053 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9054 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9055 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
9056 | "!TARGET_CPU_ZARCH" |
9057 | { | |
9058 | if (which_alternative != 0) | |
9059 | return "#"; | |
9060 | else if (get_attr_length (insn) == 4) | |
9061 | return "brct\t%1,%l0"; | |
0a3bdf9d | 9062 | else |
8d933e31 | 9063 | gcc_unreachable (); |
10bbf137 | 9064 | } |
6590e19a UW |
9065 | "&& reload_completed |
9066 | && (! REG_P (operands[2]) | |
9067 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9068 | [(set (match_dup 3) (match_dup 1)) |
9069 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9070 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9071 | (const_int 0))) | |
9072 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9073 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9074 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9075 | (label_ref (match_dup 0)) |
9076 | (pc)))] | |
9077 | "" | |
0a3bdf9d | 9078 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
9079 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9080 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9081 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 9082 | (set_attr "type" "branch") |
0a3bdf9d | 9083 | (set (attr "length") |
d7f99b2c | 9084 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9085 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9086 | (const_int 4) (const_int 6)) | |
9087 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9088 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9089 | |
0a3bdf9d UW |
9090 | (define_insn "*doloop_si_long" |
9091 | [(set (pc) | |
9092 | (if_then_else | |
7e665d18 | 9093 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 9094 | (const_int 1)) |
4fe6dea8 | 9095 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 9096 | (pc))) |
7e665d18 | 9097 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 9098 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9099 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 9100 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9101 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9102 | { |
9103 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9104 | return "bctr\t%1,%0"; |
0a3bdf9d | 9105 | else |
d40c829f | 9106 | return "bct\t%1,%a0"; |
10bbf137 | 9107 | } |
c7453384 | 9108 | [(set (attr "op_type") |
0a3bdf9d UW |
9109 | (if_then_else (match_operand 0 "register_operand" "") |
9110 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9111 | (set_attr "type" "branch") |
729e750f | 9112 | (set_attr "atype" "agen") |
65b1d8ea AK |
9113 | (set_attr "z10prop" "z10_c") |
9114 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 9115 | |
6590e19a | 9116 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9117 | [(set (pc) |
9118 | (if_then_else | |
7e665d18 | 9119 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9120 | (const_int 1)) |
9121 | (label_ref (match_operand 0 "" "")) | |
9122 | (pc))) | |
7e665d18 | 9123 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9124 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9125 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9126 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9127 | "TARGET_ZARCH" |
0a3bdf9d UW |
9128 | { |
9129 | if (which_alternative != 0) | |
10bbf137 | 9130 | return "#"; |
0a3bdf9d | 9131 | else if (get_attr_length (insn) == 4) |
d40c829f | 9132 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9133 | else |
545d16ff | 9134 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9135 | } |
6590e19a | 9136 | "&& reload_completed |
0a3bdf9d UW |
9137 | && (! REG_P (operands[2]) |
9138 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9139 | [(set (match_dup 3) (match_dup 1)) |
9140 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9141 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9142 | (const_int 0))) | |
9143 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9144 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9145 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9146 | (label_ref (match_dup 0)) |
0a3bdf9d | 9147 | (pc)))] |
6590e19a UW |
9148 | "" |
9149 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9150 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9151 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9152 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9153 | (set_attr "type" "branch") |
9154 | (set (attr "length") | |
9155 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9156 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9157 | |
9158 | ;; | |
9159 | ;;- Unconditional jump instructions. | |
9160 | ;; | |
9161 | ||
9162 | ; | |
9163 | ; jump instruction pattern(s). | |
9164 | ; | |
9165 | ||
6590e19a UW |
9166 | (define_expand "jump" |
9167 | [(match_operand 0 "" "")] | |
9db1d521 | 9168 | "" |
6590e19a UW |
9169 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9170 | ||
9171 | (define_insn "*jump64" | |
9172 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9173 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9174 | { |
13e58269 | 9175 | if (get_attr_length (insn) == 4) |
d40c829f | 9176 | return "j\t%l0"; |
6590e19a | 9177 | else |
d40c829f | 9178 | return "jg\t%l0"; |
6590e19a UW |
9179 | } |
9180 | [(set_attr "op_type" "RI") | |
9181 | (set_attr "type" "branch") | |
9182 | (set (attr "length") | |
9183 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9184 | (const_int 4) (const_int 6)))]) | |
9185 | ||
9186 | (define_insn "*jump31" | |
9187 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9188 | "!TARGET_CPU_ZARCH" | |
9189 | { | |
8d933e31 AS |
9190 | gcc_assert (get_attr_length (insn) == 4); |
9191 | return "j\t%l0"; | |
10bbf137 | 9192 | } |
9db1d521 | 9193 | [(set_attr "op_type" "RI") |
077dab3b | 9194 | (set_attr "type" "branch") |
13e58269 | 9195 | (set (attr "length") |
d7f99b2c | 9196 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9197 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9198 | (const_int 4) (const_int 6)) | |
9199 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9200 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
9201 | |
9202 | ; | |
9203 | ; indirect-jump instruction pattern(s). | |
9204 | ; | |
9205 | ||
9206 | (define_insn "indirect_jump" | |
4fe6dea8 | 9207 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 9208 | "" |
f314b9b1 UW |
9209 | { |
9210 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9211 | return "br\t%0"; |
f314b9b1 | 9212 | else |
d40c829f | 9213 | return "b\t%a0"; |
10bbf137 | 9214 | } |
c7453384 | 9215 | [(set (attr "op_type") |
f314b9b1 UW |
9216 | (if_then_else (match_operand 0 "register_operand" "") |
9217 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9218 | (set_attr "type" "branch") |
729e750f | 9219 | (set_attr "atype" "agen")]) |
9db1d521 HP |
9220 | |
9221 | ; | |
f314b9b1 | 9222 | ; casesi instruction pattern(s). |
9db1d521 HP |
9223 | ; |
9224 | ||
f314b9b1 | 9225 | (define_insn "casesi_jump" |
4fe6dea8 | 9226 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 9227 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 9228 | "" |
9db1d521 | 9229 | { |
f314b9b1 | 9230 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9231 | return "br\t%0"; |
f314b9b1 | 9232 | else |
d40c829f | 9233 | return "b\t%a0"; |
10bbf137 | 9234 | } |
c7453384 | 9235 | [(set (attr "op_type") |
f314b9b1 UW |
9236 | (if_then_else (match_operand 0 "register_operand" "") |
9237 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9238 | (set_attr "type" "branch") |
9239 | (set_attr "atype" "agen")]) | |
9db1d521 | 9240 | |
f314b9b1 UW |
9241 | (define_expand "casesi" |
9242 | [(match_operand:SI 0 "general_operand" "") | |
9243 | (match_operand:SI 1 "general_operand" "") | |
9244 | (match_operand:SI 2 "general_operand" "") | |
9245 | (label_ref (match_operand 3 "" "")) | |
9246 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9247 | "" |
f314b9b1 UW |
9248 | { |
9249 | rtx index = gen_reg_rtx (SImode); | |
9250 | rtx base = gen_reg_rtx (Pmode); | |
9251 | rtx target = gen_reg_rtx (Pmode); | |
9252 | ||
9253 | emit_move_insn (index, operands[0]); | |
9254 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9255 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9256 | operands[4]); |
f314b9b1 UW |
9257 | |
9258 | if (Pmode != SImode) | |
9259 | index = convert_to_mode (Pmode, index, 1); | |
9260 | if (GET_CODE (index) != REG) | |
9261 | index = copy_to_mode_reg (Pmode, index); | |
9262 | ||
9263 | if (TARGET_64BIT) | |
9264 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9265 | else | |
a556fd39 | 9266 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9267 | |
f314b9b1 UW |
9268 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9269 | ||
542a8afa | 9270 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9271 | emit_move_insn (target, index); |
9272 | ||
9273 | if (flag_pic) | |
9274 | target = gen_rtx_PLUS (Pmode, base, target); | |
9275 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9276 | ||
9277 | DONE; | |
10bbf137 | 9278 | }) |
9db1d521 HP |
9279 | |
9280 | ||
9281 | ;; | |
9282 | ;;- Jump to subroutine. | |
9283 | ;; | |
9284 | ;; | |
9285 | ||
9286 | ; | |
9287 | ; untyped call instruction pattern(s). | |
9288 | ; | |
9289 | ||
9290 | ;; Call subroutine returning any type. | |
9291 | (define_expand "untyped_call" | |
9292 | [(parallel [(call (match_operand 0 "" "") | |
9293 | (const_int 0)) | |
9294 | (match_operand 1 "" "") | |
9295 | (match_operand 2 "" "")])] | |
9296 | "" | |
9db1d521 HP |
9297 | { |
9298 | int i; | |
9299 | ||
9300 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9301 | ||
9302 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9303 | { | |
9304 | rtx set = XVECEXP (operands[2], 0, i); | |
9305 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9306 | } | |
9307 | ||
9308 | /* The optimizer does not know that the call sets the function value | |
9309 | registers we stored in the result block. We avoid problems by | |
9310 | claiming that all hard registers are used and clobbered at this | |
9311 | point. */ | |
9312 | emit_insn (gen_blockage ()); | |
9313 | ||
9314 | DONE; | |
10bbf137 | 9315 | }) |
9db1d521 HP |
9316 | |
9317 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9318 | ;; all of memory. This blocks insns from being moved across this point. | |
9319 | ||
9320 | (define_insn "blockage" | |
10bbf137 | 9321 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9322 | "" |
4023fb28 | 9323 | "" |
d5869ca0 UW |
9324 | [(set_attr "type" "none") |
9325 | (set_attr "length" "0")]) | |
4023fb28 | 9326 | |
9db1d521 | 9327 | ; |
ed9676cf | 9328 | ; sibcall patterns |
9db1d521 HP |
9329 | ; |
9330 | ||
ed9676cf | 9331 | (define_expand "sibcall" |
44b8152b | 9332 | [(call (match_operand 0 "" "") |
ed9676cf | 9333 | (match_operand 1 "" ""))] |
9db1d521 | 9334 | "" |
9db1d521 | 9335 | { |
ed9676cf AK |
9336 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9337 | DONE; | |
9338 | }) | |
9db1d521 | 9339 | |
ed9676cf | 9340 | (define_insn "*sibcall_br" |
ae156f85 | 9341 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9342 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9343 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9344 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
9345 | "br\t%%r1" | |
9346 | [(set_attr "op_type" "RR") | |
9347 | (set_attr "type" "branch") | |
9348 | (set_attr "atype" "agen")]) | |
9db1d521 | 9349 | |
ed9676cf AK |
9350 | (define_insn "*sibcall_brc" |
9351 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9352 | (match_operand 1 "const_int_operand" "n"))] | |
9353 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9354 | "j\t%0" | |
9355 | [(set_attr "op_type" "RI") | |
9356 | (set_attr "type" "branch")]) | |
9db1d521 | 9357 | |
ed9676cf AK |
9358 | (define_insn "*sibcall_brcl" |
9359 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9360 | (match_operand 1 "const_int_operand" "n"))] | |
9361 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9362 | "jg\t%0" | |
9363 | [(set_attr "op_type" "RIL") | |
9364 | (set_attr "type" "branch")]) | |
44b8152b | 9365 | |
ed9676cf AK |
9366 | ; |
9367 | ; sibcall_value patterns | |
9368 | ; | |
9e8327e3 | 9369 | |
ed9676cf AK |
9370 | (define_expand "sibcall_value" |
9371 | [(set (match_operand 0 "" "") | |
9372 | (call (match_operand 1 "" "") | |
9373 | (match_operand 2 "" "")))] | |
9374 | "" | |
9375 | { | |
9376 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9377 | DONE; |
10bbf137 | 9378 | }) |
9db1d521 | 9379 | |
ed9676cf AK |
9380 | (define_insn "*sibcall_value_br" |
9381 | [(set (match_operand 0 "" "") | |
ae156f85 | 9382 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9383 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9384 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9385 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
9386 | "br\t%%r1" | |
9387 | [(set_attr "op_type" "RR") | |
9388 | (set_attr "type" "branch") | |
9389 | (set_attr "atype" "agen")]) | |
9390 | ||
9391 | (define_insn "*sibcall_value_brc" | |
9392 | [(set (match_operand 0 "" "") | |
9393 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9394 | (match_operand 2 "const_int_operand" "n")))] | |
9395 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9396 | "j\t%1" | |
9397 | [(set_attr "op_type" "RI") | |
9398 | (set_attr "type" "branch")]) | |
9399 | ||
9400 | (define_insn "*sibcall_value_brcl" | |
9401 | [(set (match_operand 0 "" "") | |
9402 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9403 | (match_operand 2 "const_int_operand" "n")))] | |
9404 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9405 | "jg\t%1" | |
9406 | [(set_attr "op_type" "RIL") | |
9407 | (set_attr "type" "branch")]) | |
9408 | ||
9409 | ||
9410 | ; | |
9411 | ; call instruction pattern(s). | |
9412 | ; | |
9413 | ||
9414 | (define_expand "call" | |
9415 | [(call (match_operand 0 "" "") | |
9416 | (match_operand 1 "" "")) | |
9417 | (use (match_operand 2 "" ""))] | |
44b8152b | 9418 | "" |
ed9676cf | 9419 | { |
2f7e5a0d | 9420 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9421 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9422 | DONE; | |
9423 | }) | |
44b8152b | 9424 | |
9e8327e3 UW |
9425 | (define_insn "*bras" |
9426 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9427 | (match_operand 1 "const_int_operand" "n")) | |
9428 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9429 | "!SIBLING_CALL_P (insn) |
9430 | && TARGET_SMALL_EXEC | |
ed9676cf | 9431 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9432 | "bras\t%2,%0" |
9db1d521 | 9433 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9434 | (set_attr "type" "jsr") |
9435 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9436 | |
9e8327e3 UW |
9437 | (define_insn "*brasl" |
9438 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9439 | (match_operand 1 "const_int_operand" "n")) | |
9440 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9441 | "!SIBLING_CALL_P (insn) |
9442 | && TARGET_CPU_ZARCH | |
ed9676cf | 9443 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9444 | "brasl\t%2,%0" |
9445 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9446 | (set_attr "type" "jsr") |
9447 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9448 | |
9e8327e3 | 9449 | (define_insn "*basr" |
4fe6dea8 | 9450 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
9451 | (match_operand 1 "const_int_operand" "n")) |
9452 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 9453 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9454 | { |
9455 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9456 | return "basr\t%2,%0"; | |
9457 | else | |
9458 | return "bas\t%2,%a0"; | |
9459 | } | |
9460 | [(set (attr "op_type") | |
9461 | (if_then_else (match_operand 0 "register_operand" "") | |
9462 | (const_string "RR") (const_string "RX"))) | |
9463 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9464 | (set_attr "atype" "agen") |
9465 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
9466 | |
9467 | ; | |
9468 | ; call_value instruction pattern(s). | |
9469 | ; | |
9470 | ||
9471 | (define_expand "call_value" | |
44b8152b UW |
9472 | [(set (match_operand 0 "" "") |
9473 | (call (match_operand 1 "" "") | |
9474 | (match_operand 2 "" ""))) | |
9475 | (use (match_operand 3 "" ""))] | |
9db1d521 | 9476 | "" |
9db1d521 | 9477 | { |
2f7e5a0d | 9478 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 9479 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 9480 | DONE; |
10bbf137 | 9481 | }) |
9db1d521 | 9482 | |
9e8327e3 | 9483 | (define_insn "*bras_r" |
c19ec8f9 | 9484 | [(set (match_operand 0 "" "") |
9e8327e3 | 9485 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 9486 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 9487 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
9488 | "!SIBLING_CALL_P (insn) |
9489 | && TARGET_SMALL_EXEC | |
ed9676cf | 9490 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9491 | "bras\t%3,%1" |
9db1d521 | 9492 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9493 | (set_attr "type" "jsr") |
9494 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9495 | |
9e8327e3 | 9496 | (define_insn "*brasl_r" |
c19ec8f9 | 9497 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9498 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9499 | (match_operand 2 "const_int_operand" "n"))) | |
9500 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
9501 | "!SIBLING_CALL_P (insn) |
9502 | && TARGET_CPU_ZARCH | |
ed9676cf | 9503 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9504 | "brasl\t%3,%1" |
9505 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9506 | (set_attr "type" "jsr") |
9507 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9508 | |
9e8327e3 | 9509 | (define_insn "*basr_r" |
c19ec8f9 | 9510 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9511 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9512 | (match_operand 2 "const_int_operand" "n"))) |
9513 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 9514 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9515 | { |
9516 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9517 | return "basr\t%3,%1"; | |
9518 | else | |
9519 | return "bas\t%3,%a1"; | |
9520 | } | |
9521 | [(set (attr "op_type") | |
9522 | (if_then_else (match_operand 1 "register_operand" "") | |
9523 | (const_string "RR") (const_string "RX"))) | |
9524 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9525 | (set_attr "atype" "agen") |
9526 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9527 | |
fd3cd001 UW |
9528 | ;; |
9529 | ;;- Thread-local storage support. | |
9530 | ;; | |
9531 | ||
f959607b CLT |
9532 | (define_expand "get_thread_pointer<mode>" |
9533 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
9534 | "" | |
c5aa1d12 | 9535 | "") |
fd3cd001 | 9536 | |
f959607b CLT |
9537 | (define_expand "set_thread_pointer<mode>" |
9538 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
9539 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
9540 | "" | |
c5aa1d12 UW |
9541 | "") |
9542 | ||
9543 | (define_insn "*set_tp" | |
ae156f85 | 9544 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
9545 | "" |
9546 | "" | |
9547 | [(set_attr "type" "none") | |
9548 | (set_attr "length" "0")]) | |
c7453384 | 9549 | |
fd3cd001 UW |
9550 | (define_insn "*tls_load_64" |
9551 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 9552 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
9553 | (match_operand:DI 2 "" "")] |
9554 | UNSPEC_TLS_LOAD))] | |
9555 | "TARGET_64BIT" | |
d40c829f | 9556 | "lg\t%0,%1%J2" |
9381e3f1 WG |
9557 | [(set_attr "op_type" "RXE") |
9558 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
9559 | |
9560 | (define_insn "*tls_load_31" | |
d3632d41 UW |
9561 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
9562 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
9563 | (match_operand:SI 2 "" "")] |
9564 | UNSPEC_TLS_LOAD))] | |
9565 | "!TARGET_64BIT" | |
d3632d41 | 9566 | "@ |
d40c829f UW |
9567 | l\t%0,%1%J2 |
9568 | ly\t%0,%1%J2" | |
9381e3f1 | 9569 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 9570 | (set_attr "type" "load") |
9381e3f1 | 9571 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 9572 | |
9e8327e3 | 9573 | (define_insn "*bras_tls" |
c19ec8f9 | 9574 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9575 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9576 | (match_operand 2 "const_int_operand" "n"))) | |
9577 | (clobber (match_operand 3 "register_operand" "=r")) | |
9578 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9579 | "!SIBLING_CALL_P (insn) |
9580 | && TARGET_SMALL_EXEC | |
ed9676cf | 9581 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9582 | "bras\t%3,%1%J4" |
fd3cd001 | 9583 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9584 | (set_attr "type" "jsr") |
9585 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9586 | |
9e8327e3 | 9587 | (define_insn "*brasl_tls" |
c19ec8f9 | 9588 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9589 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9590 | (match_operand 2 "const_int_operand" "n"))) | |
9591 | (clobber (match_operand 3 "register_operand" "=r")) | |
9592 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9593 | "!SIBLING_CALL_P (insn) |
9594 | && TARGET_CPU_ZARCH | |
ed9676cf | 9595 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9596 | "brasl\t%3,%1%J4" |
9597 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9598 | (set_attr "type" "jsr") |
9599 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9600 | |
9e8327e3 | 9601 | (define_insn "*basr_tls" |
c19ec8f9 | 9602 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9603 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9604 | (match_operand 2 "const_int_operand" "n"))) |
9605 | (clobber (match_operand 3 "register_operand" "=r")) | |
9606 | (use (match_operand 4 "" ""))] | |
ed9676cf | 9607 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9608 | { |
9609 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9610 | return "basr\t%3,%1%J4"; | |
9611 | else | |
9612 | return "bas\t%3,%a1%J4"; | |
9613 | } | |
9614 | [(set (attr "op_type") | |
9615 | (if_then_else (match_operand 1 "register_operand" "") | |
9616 | (const_string "RR") (const_string "RX"))) | |
9617 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9618 | (set_attr "atype" "agen") |
9619 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9620 | |
e0374221 AS |
9621 | ;; |
9622 | ;;- Atomic operations | |
9623 | ;; | |
9624 | ||
9625 | ; | |
78ce265b | 9626 | ; memory barrier patterns. |
e0374221 AS |
9627 | ; |
9628 | ||
78ce265b RH |
9629 | (define_expand "mem_signal_fence" |
9630 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
9631 | "" |
9632 | { | |
78ce265b RH |
9633 | /* The s390 memory model is strong enough not to require any |
9634 | barrier in order to synchronize a thread with itself. */ | |
9635 | DONE; | |
9636 | }) | |
9637 | ||
9638 | (define_expand "mem_thread_fence" | |
9639 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
9640 | "" | |
9641 | { | |
9642 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
9643 | enough not to require barriers of any kind. */ | |
46b35980 | 9644 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
9645 | { |
9646 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
9647 | MEM_VOLATILE_P (mem) = 1; | |
9648 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
9649 | } | |
9650 | DONE; | |
e0374221 AS |
9651 | }) |
9652 | ||
78ce265b RH |
9653 | ; Although bcr is superscalar on Z10, this variant will never |
9654 | ; become part of an execution group. | |
a9cc3f58 AK |
9655 | ; With z196 we can make use of the fast-BCR-serialization facility. |
9656 | ; This allows for a slightly faster sync which is sufficient for our | |
9657 | ; purposes. | |
78ce265b | 9658 | (define_insn "mem_thread_fence_1" |
e0374221 | 9659 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 9660 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 9661 | "" |
a9cc3f58 AK |
9662 | { |
9663 | if (TARGET_Z196) | |
9664 | return "bcr\t14,0"; | |
9665 | else | |
9666 | return "bcr\t15,0"; | |
9667 | } | |
9668 | [(set_attr "op_type" "RR") | |
9669 | (set_attr "mnemonic" "bcr_flush") | |
9670 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 9671 | |
78ce265b RH |
9672 | ; |
9673 | ; atomic load/store operations | |
9674 | ; | |
9675 | ||
9676 | ; Atomic loads need not examine the memory model at all. | |
9677 | (define_expand "atomic_load<mode>" | |
9678 | [(match_operand:DINT 0 "register_operand") ;; output | |
9679 | (match_operand:DINT 1 "memory_operand") ;; memory | |
9680 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9681 | "" | |
9682 | { | |
75cc21e2 AK |
9683 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
9684 | FAIL; | |
9685 | ||
78ce265b RH |
9686 | if (<MODE>mode == TImode) |
9687 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
9688 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9689 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
9690 | else | |
9691 | emit_move_insn (operands[0], operands[1]); | |
9692 | DONE; | |
9693 | }) | |
9694 | ||
9695 | ; Different from movdi_31 in that we want no splitters. | |
9696 | (define_insn "atomic_loaddi_1" | |
9697 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
9698 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
9699 | UNSPEC_MOVA))] | |
9700 | "!TARGET_ZARCH" | |
9701 | "@ | |
9702 | lm\t%0,%M0,%S1 | |
9703 | lmy\t%0,%M0,%S1 | |
9704 | ld\t%0,%1 | |
9705 | ldy\t%0,%1" | |
9706 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9707 | (set_attr "type" "lm,lm,floaddf,floaddf")]) | |
9708 | ||
9709 | (define_insn "atomic_loadti_1" | |
9710 | [(set (match_operand:TI 0 "register_operand" "=r") | |
9711 | (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] | |
9712 | UNSPEC_MOVA))] | |
9713 | "TARGET_ZARCH" | |
9714 | "lpq\t%0,%1" | |
9715 | [(set_attr "op_type" "RXY") | |
9716 | (set_attr "type" "other")]) | |
9717 | ||
9718 | ; Atomic stores must(?) enforce sequential consistency. | |
9719 | (define_expand "atomic_store<mode>" | |
9720 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
9721 | (match_operand:DINT 1 "register_operand") ;; input | |
9722 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9723 | "" | |
9724 | { | |
46b35980 | 9725 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 9726 | |
75cc21e2 AK |
9727 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
9728 | FAIL; | |
9729 | ||
78ce265b RH |
9730 | if (<MODE>mode == TImode) |
9731 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
9732 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9733 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
9734 | else | |
9735 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 9736 | if (is_mm_seq_cst (model)) |
78ce265b RH |
9737 | emit_insn (gen_mem_thread_fence (operands[2])); |
9738 | DONE; | |
9739 | }) | |
9740 | ||
9741 | ; Different from movdi_31 in that we want no splitters. | |
9742 | (define_insn "atomic_storedi_1" | |
9743 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
9744 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
9745 | UNSPEC_MOVA))] | |
9746 | "!TARGET_ZARCH" | |
9747 | "@ | |
9748 | stm\t%1,%N1,%S0 | |
9749 | stmy\t%1,%N1,%S0 | |
9750 | std %1,%0 | |
9751 | stdy %1,%0" | |
9752 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9753 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) | |
9754 | ||
9755 | (define_insn "atomic_storeti_1" | |
9756 | [(set (match_operand:TI 0 "memory_operand" "=RT") | |
9757 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] | |
9758 | UNSPEC_MOVA))] | |
9759 | "TARGET_ZARCH" | |
9760 | "stpq\t%1,%0" | |
9761 | [(set_attr "op_type" "RXY") | |
9762 | (set_attr "type" "other")]) | |
e0374221 AS |
9763 | |
9764 | ; | |
9765 | ; compare and swap patterns. | |
9766 | ; | |
9767 | ||
78ce265b RH |
9768 | (define_expand "atomic_compare_and_swap<mode>" |
9769 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9770 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
9771 | (match_operand:DGPR 2 "memory_operand") ;; memory |
9772 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
9773 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
9774 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9775 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9776 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
9777 | "" | |
9778 | { | |
215770ad UW |
9779 | rtx cc, cmp, output = operands[1]; |
9780 | ||
9781 | if (!register_operand (output, <MODE>mode)) | |
9782 | output = gen_reg_rtx (<MODE>mode); | |
9783 | ||
75cc21e2 AK |
9784 | if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2]))) |
9785 | FAIL; | |
9786 | ||
78ce265b | 9787 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
9788 | (output, operands[2], operands[3], operands[4])); |
9789 | ||
9790 | /* We deliberately accept non-register operands in the predicate | |
9791 | to ensure the write back to the output operand happens *before* | |
9792 | the store-flags code below. This makes it easier for combine | |
9793 | to merge the store-flags code with a potential test-and-branch | |
9794 | pattern following (immediately!) afterwards. */ | |
9795 | if (output != operands[1]) | |
9796 | emit_move_insn (operands[1], output); | |
9797 | ||
78ce265b RH |
9798 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
9799 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
9800 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
9801 | DONE; | |
9802 | }) | |
e0374221 | 9803 | |
78ce265b RH |
9804 | (define_expand "atomic_compare_and_swap<mode>" |
9805 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9806 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
9807 | (match_operand:HQI 2 "memory_operand") ;; memory |
9808 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
9809 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
9810 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9811 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9812 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 9813 | "" |
78ce265b RH |
9814 | { |
9815 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
9816 | operands[3], operands[4], INTVAL (operands[5])); | |
9817 | DONE; | |
9818 | }) | |
3093f076 | 9819 | |
78ce265b RH |
9820 | (define_expand "atomic_compare_and_swap<mode>_internal" |
9821 | [(parallel | |
9822 | [(set (match_operand:DGPR 0 "register_operand") | |
9823 | (match_operand:DGPR 1 "memory_operand")) | |
9824 | (set (match_dup 1) | |
9825 | (unspec_volatile:DGPR | |
9826 | [(match_dup 1) | |
9827 | (match_operand:DGPR 2 "register_operand") | |
9828 | (match_operand:DGPR 3 "register_operand")] | |
9829 | UNSPECV_CAS)) | |
9830 | (set (reg:CCZ1 CC_REGNUM) | |
9831 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
9832 | "") | |
9833 | ||
9834 | ; cdsg, csg | |
9835 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
9836 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
9837 | (match_operand:TDI 1 "memory_operand" "+QS")) | |
8006eaa6 | 9838 | (set (match_dup 1) |
78ce265b | 9839 | (unspec_volatile:TDI |
8006eaa6 | 9840 | [(match_dup 1) |
78ce265b RH |
9841 | (match_operand:TDI 2 "register_operand" "0") |
9842 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
9843 | UNSPECV_CAS)) |
9844 | (set (reg:CCZ1 CC_REGNUM) | |
9845 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
9846 | "TARGET_ZARCH" |
9847 | "c<td>sg\t%0,%3,%S1" | |
9848 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
9849 | (set_attr "type" "sem")]) |
9850 | ||
78ce265b RH |
9851 | ; cds, cdsy |
9852 | (define_insn "*atomic_compare_and_swapdi_2" | |
9853 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
9854 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 9855 | (set (match_dup 1) |
78ce265b RH |
9856 | (unspec_volatile:DI |
9857 | [(match_dup 1) | |
9858 | (match_operand:DI 2 "register_operand" "0,0") | |
9859 | (match_operand:DI 3 "register_operand" "r,r")] | |
9860 | UNSPECV_CAS)) | |
9861 | (set (reg:CCZ1 CC_REGNUM) | |
9862 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9863 | "!TARGET_ZARCH" | |
9864 | "@ | |
9865 | cds\t%0,%3,%S1 | |
9866 | cdsy\t%0,%3,%S1" | |
9867 | [(set_attr "op_type" "RS,RSY") | |
9868 | (set_attr "type" "sem")]) | |
9869 | ||
9870 | ; cs, csy | |
9871 | (define_insn "*atomic_compare_and_swapsi_3" | |
9872 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
9873 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
9874 | (set (match_dup 1) | |
9875 | (unspec_volatile:SI | |
e0374221 | 9876 | [(match_dup 1) |
78ce265b RH |
9877 | (match_operand:SI 2 "register_operand" "0,0") |
9878 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 9879 | UNSPECV_CAS)) |
69950452 AS |
9880 | (set (reg:CCZ1 CC_REGNUM) |
9881 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 9882 | "" |
78ce265b RH |
9883 | "@ |
9884 | cs\t%0,%3,%S1 | |
9885 | csy\t%0,%3,%S1" | |
9886 | [(set_attr "op_type" "RS,RSY") | |
e0374221 AS |
9887 | (set_attr "type" "sem")]) |
9888 | ||
45d18331 AS |
9889 | ; |
9890 | ; Other atomic instruction patterns. | |
9891 | ; | |
9892 | ||
65b1d8ea AK |
9893 | ; z196 load and add, xor, or and and instructions |
9894 | ||
78ce265b RH |
9895 | (define_expand "atomic_fetch_<atomic><mode>" |
9896 | [(match_operand:GPR 0 "register_operand") ;; val out | |
9897 | (ATOMIC_Z196:GPR | |
9898 | (match_operand:GPR 1 "memory_operand") ;; memory | |
9899 | (match_operand:GPR 2 "register_operand")) ;; val in | |
9900 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 9901 | "TARGET_Z196" |
78ce265b | 9902 | { |
75cc21e2 AK |
9903 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
9904 | FAIL; | |
9905 | ||
78ce265b RH |
9906 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
9907 | (operands[0], operands[1], operands[2])); | |
9908 | DONE; | |
9909 | }) | |
65b1d8ea AK |
9910 | |
9911 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
9912 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
9913 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
9914 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
9915 | (set (match_dup 1) | |
9916 | (unspec_volatile:GPR | |
9917 | [(ATOMIC_Z196:GPR (match_dup 1) | |
9918 | (match_operand:GPR 2 "general_operand" "d"))] | |
9919 | UNSPECV_ATOMIC_OP)) | |
9920 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 9921 | "TARGET_Z196" |
78ce265b RH |
9922 | "la<noxa><g>\t%0,%2,%1" |
9923 | [(set_attr "op_type" "RSY") | |
9924 | (set_attr "type" "sem")]) | |
65b1d8ea | 9925 | |
78ce265b RH |
9926 | ;; For SImode and larger, the optabs.c code will do just fine in |
9927 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
9928 | ;; better by expanding our own loop. | |
65b1d8ea | 9929 | |
78ce265b RH |
9930 | (define_expand "atomic_<atomic><mode>" |
9931 | [(ATOMIC:HQI | |
9932 | (match_operand:HQI 0 "memory_operand") ;; memory | |
9933 | (match_operand:HQI 1 "general_operand")) ;; val in | |
9934 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 9935 | "" |
78ce265b RH |
9936 | { |
9937 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
9938 | operands[1], false); | |
9939 | DONE; | |
9940 | }) | |
45d18331 | 9941 | |
78ce265b RH |
9942 | (define_expand "atomic_fetch_<atomic><mode>" |
9943 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9944 | (ATOMIC:HQI | |
9945 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9946 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9947 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9948 | "" |
78ce265b RH |
9949 | { |
9950 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9951 | operands[2], false); | |
9952 | DONE; | |
9953 | }) | |
9954 | ||
9955 | (define_expand "atomic_<atomic>_fetch<mode>" | |
9956 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9957 | (ATOMIC:HQI | |
9958 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9959 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9960 | (match_operand:SI 3 "const_int_operand")] ;; model | |
9961 | "" | |
9962 | { | |
9963 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9964 | operands[2], true); | |
9965 | DONE; | |
9966 | }) | |
9967 | ||
9968 | (define_expand "atomic_exchange<mode>" | |
9969 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9970 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9971 | (match_operand:HQI 2 "general_operand") ;; val in | |
9972 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9973 | "" |
78ce265b RH |
9974 | { |
9975 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
9976 | operands[2], false); | |
9977 | DONE; | |
9978 | }) | |
45d18331 | 9979 | |
9db1d521 HP |
9980 | ;; |
9981 | ;;- Miscellaneous instructions. | |
9982 | ;; | |
9983 | ||
9984 | ; | |
9985 | ; allocate stack instruction pattern(s). | |
9986 | ; | |
9987 | ||
9988 | (define_expand "allocate_stack" | |
ef44a6ff UW |
9989 | [(match_operand 0 "general_operand" "") |
9990 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 9991 | "TARGET_BACKCHAIN" |
9db1d521 | 9992 | { |
ef44a6ff | 9993 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 9994 | |
ef44a6ff UW |
9995 | emit_move_insn (temp, s390_back_chain_rtx ()); |
9996 | anti_adjust_stack (operands[1]); | |
9997 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 9998 | |
ef44a6ff UW |
9999 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10000 | DONE; | |
10bbf137 | 10001 | }) |
9db1d521 HP |
10002 | |
10003 | ||
10004 | ; | |
43ab026f | 10005 | ; setjmp instruction pattern. |
9db1d521 HP |
10006 | ; |
10007 | ||
9db1d521 | 10008 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10009 | [(match_operand 0 "" "")] |
f314b9b1 | 10010 | "flag_pic" |
9db1d521 | 10011 | { |
585539a1 | 10012 | emit_insn (s390_load_got ()); |
c41c1387 | 10013 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10014 | DONE; |
fd7643fb | 10015 | }) |
9db1d521 | 10016 | |
9db1d521 HP |
10017 | ;; These patterns say how to save and restore the stack pointer. We need not |
10018 | ;; save the stack pointer at function level since we are careful to | |
10019 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10020 | ;; when we restore the stack pointer. | |
10021 | ;; | |
10022 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10023 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10024 | ;; save area is a memory location. | |
10025 | ||
10026 | (define_expand "save_stack_function" | |
10027 | [(match_operand 0 "general_operand" "") | |
10028 | (match_operand 1 "general_operand" "")] | |
10029 | "" | |
10030 | "DONE;") | |
10031 | ||
10032 | (define_expand "restore_stack_function" | |
10033 | [(match_operand 0 "general_operand" "") | |
10034 | (match_operand 1 "general_operand" "")] | |
10035 | "" | |
10036 | "DONE;") | |
10037 | ||
10038 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10039 | [(match_operand 0 "register_operand" "") |
10040 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10041 | "TARGET_BACKCHAIN" |
9db1d521 | 10042 | { |
ef44a6ff UW |
10043 | rtx temp = gen_reg_rtx (Pmode); |
10044 | ||
10045 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10046 | emit_move_insn (operands[0], operands[1]); | |
10047 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10048 | ||
10049 | DONE; | |
10bbf137 | 10050 | }) |
9db1d521 HP |
10051 | |
10052 | (define_expand "save_stack_nonlocal" | |
10053 | [(match_operand 0 "memory_operand" "") | |
10054 | (match_operand 1 "register_operand" "")] | |
10055 | "" | |
9db1d521 | 10056 | { |
ef44a6ff UW |
10057 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10058 | ||
10059 | /* Copy the backchain to the first word, sp to the second and the | |
10060 | literal pool base to the third. */ | |
10061 | ||
9602b6a1 AK |
10062 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10063 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10064 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10065 | ||
b3d31392 | 10066 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10067 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10068 | |
9602b6a1 AK |
10069 | emit_move_insn (save_sp, operands[1]); |
10070 | emit_move_insn (save_bp, base); | |
9db1d521 | 10071 | |
9db1d521 | 10072 | DONE; |
10bbf137 | 10073 | }) |
9db1d521 HP |
10074 | |
10075 | (define_expand "restore_stack_nonlocal" | |
10076 | [(match_operand 0 "register_operand" "") | |
10077 | (match_operand 1 "memory_operand" "")] | |
10078 | "" | |
9db1d521 | 10079 | { |
490ceeb4 | 10080 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10081 | rtx temp = NULL_RTX; |
9db1d521 | 10082 | |
43ab026f | 10083 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10084 | literal pool base from the third. */ |
43ab026f | 10085 | |
9602b6a1 AK |
10086 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10087 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10088 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10089 | ||
b3d31392 | 10090 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10091 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10092 | |
9602b6a1 AK |
10093 | emit_move_insn (base, save_bp); |
10094 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10095 | |
10096 | if (temp) | |
10097 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10098 | ||
c41c1387 | 10099 | emit_use (base); |
9db1d521 | 10100 | DONE; |
10bbf137 | 10101 | }) |
9db1d521 | 10102 | |
7bcebb25 AK |
10103 | (define_expand "exception_receiver" |
10104 | [(const_int 0)] | |
10105 | "" | |
10106 | { | |
10107 | s390_set_has_landing_pad_p (true); | |
10108 | DONE; | |
10109 | }) | |
9db1d521 HP |
10110 | |
10111 | ; | |
10112 | ; nop instruction pattern(s). | |
10113 | ; | |
10114 | ||
10115 | (define_insn "nop" | |
10116 | [(const_int 0)] | |
10117 | "" | |
d40c829f | 10118 | "lr\t0,0" |
729e750f WG |
10119 | [(set_attr "op_type" "RR") |
10120 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10121 | |
d277db6b WG |
10122 | (define_insn "nop1" |
10123 | [(const_int 1)] | |
10124 | "" | |
10125 | "lr\t1,1" | |
10126 | [(set_attr "op_type" "RR")]) | |
10127 | ||
f8af0e30 DV |
10128 | ;;- Undeletable nops (used for hotpatching) |
10129 | ||
10130 | (define_insn "nop_2_byte" | |
10131 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10132 | "" | |
10133 | "nopr\t%%r7" | |
10134 | [(set_attr "op_type" "RR")]) | |
10135 | ||
10136 | (define_insn "nop_4_byte" | |
10137 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10138 | "" | |
10139 | "nop\t0" | |
10140 | [(set_attr "op_type" "RX")]) | |
10141 | ||
10142 | (define_insn "nop_6_byte" | |
10143 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
10144 | "TARGET_CPU_ZARCH" | |
10145 | "brcl\t0, 0" | |
10146 | [(set_attr "op_type" "RIL")]) | |
10147 | ||
9db1d521 HP |
10148 | |
10149 | ; | |
10150 | ; Special literal pool access instruction pattern(s). | |
10151 | ; | |
10152 | ||
416cf582 UW |
10153 | (define_insn "*pool_entry" |
10154 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10155 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10156 | "" |
9db1d521 | 10157 | { |
ef4bddc2 | 10158 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10159 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10160 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10161 | return ""; |
10162 | } | |
b628bd8e | 10163 | [(set (attr "length") |
416cf582 | 10164 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10165 | |
9bb86f41 UW |
10166 | (define_insn "pool_align" |
10167 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10168 | UNSPECV_POOL_ALIGN)] | |
10169 | "" | |
10170 | ".align\t%0" | |
b628bd8e | 10171 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10172 | |
9bb86f41 UW |
10173 | (define_insn "pool_section_start" |
10174 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10175 | "" | |
b929b470 MK |
10176 | { |
10177 | switch_to_section (targetm.asm_out.function_rodata_section | |
10178 | (current_function_decl)); | |
10179 | return ""; | |
10180 | } | |
b628bd8e | 10181 | [(set_attr "length" "0")]) |
b2ccb744 | 10182 | |
9bb86f41 UW |
10183 | (define_insn "pool_section_end" |
10184 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10185 | "" | |
b929b470 MK |
10186 | { |
10187 | switch_to_section (current_function_section ()); | |
10188 | return ""; | |
10189 | } | |
b628bd8e | 10190 | [(set_attr "length" "0")]) |
b2ccb744 | 10191 | |
5af2f3d3 | 10192 | (define_insn "main_base_31_small" |
9e8327e3 UW |
10193 | [(set (match_operand 0 "register_operand" "=a") |
10194 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10195 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10196 | "basr\t%0,0" |
10197 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
10198 | (set_attr "type" "la") |
10199 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10200 | |
10201 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
10202 | [(set (match_operand 0 "register_operand" "=a") |
10203 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 10204 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 10205 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 10206 | "bras\t%0,%2" |
65b1d8ea AK |
10207 | [(set_attr "op_type" "RI") |
10208 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10209 | |
10210 | (define_insn "main_base_64" | |
9e8327e3 UW |
10211 | [(set (match_operand 0 "register_operand" "=a") |
10212 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10213 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10214 | "larl\t%0,%1" |
10215 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10216 | (set_attr "type" "larl") |
729e750f | 10217 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
10218 | |
10219 | (define_insn "main_pool" | |
585539a1 UW |
10220 | [(set (match_operand 0 "register_operand" "=a") |
10221 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10222 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10223 | { |
10224 | gcc_unreachable (); | |
10225 | } | |
9381e3f1 | 10226 | [(set (attr "type") |
d7f99b2c | 10227 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 10228 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 10229 | |
aee4e0db | 10230 | (define_insn "reload_base_31" |
9e8327e3 UW |
10231 | [(set (match_operand 0 "register_operand" "=a") |
10232 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10233 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10234 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 10235 | [(set_attr "length" "6") |
65b1d8ea AK |
10236 | (set_attr "type" "la") |
10237 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 10238 | |
aee4e0db | 10239 | (define_insn "reload_base_64" |
9e8327e3 UW |
10240 | [(set (match_operand 0 "register_operand" "=a") |
10241 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10242 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10243 | "larl\t%0,%1" |
aee4e0db | 10244 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10245 | (set_attr "type" "larl") |
729e750f | 10246 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10247 | |
aee4e0db | 10248 | (define_insn "pool" |
fd7643fb | 10249 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10250 | "" |
8d933e31 AS |
10251 | { |
10252 | gcc_unreachable (); | |
10253 | } | |
b628bd8e | 10254 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10255 | |
4023fb28 UW |
10256 | ;; |
10257 | ;; Insns related to generating the function prologue and epilogue. | |
10258 | ;; | |
10259 | ||
10260 | ||
10261 | (define_expand "prologue" | |
10262 | [(use (const_int 0))] | |
10263 | "" | |
10bbf137 | 10264 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10265 | |
10266 | (define_expand "epilogue" | |
10267 | [(use (const_int 1))] | |
10268 | "" | |
ed9676cf AK |
10269 | "s390_emit_epilogue (false); DONE;") |
10270 | ||
10271 | (define_expand "sibcall_epilogue" | |
10272 | [(use (const_int 0))] | |
10273 | "" | |
10274 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10275 | |
177bc204 RS |
10276 | ;; A direct return instruction, without using an epilogue. |
10277 | (define_insn "<code>" | |
10278 | [(ANY_RETURN)] | |
10279 | "s390_can_use_<code>_insn ()" | |
10280 | "br\t%%r14" | |
10281 | [(set_attr "op_type" "RR") | |
10282 | (set_attr "type" "jsr") | |
10283 | (set_attr "atype" "agen")]) | |
10284 | ||
9e8327e3 | 10285 | (define_insn "*return" |
4023fb28 | 10286 | [(return) |
9e8327e3 UW |
10287 | (use (match_operand 0 "register_operand" "a"))] |
10288 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10289 | "br\t%0" |
4023fb28 | 10290 | [(set_attr "op_type" "RR") |
c7453384 | 10291 | (set_attr "type" "jsr") |
077dab3b | 10292 | (set_attr "atype" "agen")]) |
4023fb28 | 10293 | |
4023fb28 | 10294 | |
c7453384 | 10295 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 10296 | ;; pointer. This is used for compatibility. |
c7453384 EC |
10297 | |
10298 | (define_expand "ptr_extend" | |
10299 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10300 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 10301 | "TARGET_64BIT" |
c7453384 | 10302 | { |
c7453384 EC |
10303 | emit_insn (gen_anddi3 (operands[0], |
10304 | gen_lowpart (DImode, operands[1]), | |
10305 | GEN_INT (0x7fffffff))); | |
c7453384 | 10306 | DONE; |
10bbf137 | 10307 | }) |
4798630c D |
10308 | |
10309 | ;; Instruction definition to expand eh_return macro to support | |
10310 | ;; swapping in special linkage return addresses. | |
10311 | ||
10312 | (define_expand "eh_return" | |
10313 | [(use (match_operand 0 "register_operand" ""))] | |
10314 | "TARGET_TPF" | |
10315 | { | |
10316 | s390_emit_tpf_eh_return (operands[0]); | |
10317 | DONE; | |
10318 | }) | |
10319 | ||
7b8acc34 AK |
10320 | ; |
10321 | ; Stack Protector Patterns | |
10322 | ; | |
10323 | ||
10324 | (define_expand "stack_protect_set" | |
10325 | [(set (match_operand 0 "memory_operand" "") | |
10326 | (match_operand 1 "memory_operand" ""))] | |
10327 | "" | |
10328 | { | |
10329 | #ifdef TARGET_THREAD_SSP_OFFSET | |
10330 | operands[1] | |
10331 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10332 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10333 | #endif | |
10334 | if (TARGET_64BIT) | |
10335 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10336 | else | |
10337 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10338 | ||
10339 | DONE; | |
10340 | }) | |
10341 | ||
10342 | (define_insn "stack_protect_set<mode>" | |
10343 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
10344 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
10345 | "" | |
10346 | "mvc\t%O0(%G0,%R0),%S1" | |
10347 | [(set_attr "op_type" "SS")]) | |
10348 | ||
10349 | (define_expand "stack_protect_test" | |
10350 | [(set (reg:CC CC_REGNUM) | |
10351 | (compare (match_operand 0 "memory_operand" "") | |
10352 | (match_operand 1 "memory_operand" ""))) | |
10353 | (match_operand 2 "" "")] | |
10354 | "" | |
10355 | { | |
f90b7a5a | 10356 | rtx cc_reg, test; |
7b8acc34 AK |
10357 | #ifdef TARGET_THREAD_SSP_OFFSET |
10358 | operands[1] | |
10359 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10360 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10361 | #endif | |
7b8acc34 AK |
10362 | if (TARGET_64BIT) |
10363 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
10364 | else | |
10365 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
10366 | ||
f90b7a5a PB |
10367 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
10368 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
10369 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
10370 | DONE; |
10371 | }) | |
10372 | ||
10373 | (define_insn "stack_protect_test<mode>" | |
10374 | [(set (reg:CCZ CC_REGNUM) | |
10375 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
10376 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
10377 | "" | |
10378 | "clc\t%O0(%G0,%R0),%S1" | |
10379 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
10380 | |
10381 | ; This is used in s390_emit_prologue in order to prevent insns | |
10382 | ; adjusting the stack pointer to be moved over insns writing stack | |
10383 | ; slots using a copy of the stack pointer in a different register. | |
10384 | (define_insn "stack_tie" | |
10385 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
10386 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
10387 | "" | |
10388 | "" | |
10389 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
10390 | |
10391 | ||
82c6f58a AK |
10392 | (define_insn "stack_restore_from_fpr" |
10393 | [(set (reg:DI STACK_REGNUM) | |
10394 | (match_operand:DI 0 "register_operand" "f")) | |
10395 | (clobber (mem:BLK (scratch)))] | |
10396 | "TARGET_Z10" | |
10397 | "lgdr\t%%r15,%0" | |
10398 | [(set_attr "op_type" "RRE")]) | |
10399 | ||
963fc8d0 AK |
10400 | ; |
10401 | ; Data prefetch patterns | |
10402 | ; | |
10403 | ||
10404 | (define_insn "prefetch" | |
22d72dbc AK |
10405 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
10406 | (match_operand:SI 1 "const_int_operand" " n,n") | |
10407 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
10408 | "TARGET_Z10" | |
963fc8d0 | 10409 | { |
4fe6dea8 AK |
10410 | switch (which_alternative) |
10411 | { | |
10412 | case 0: | |
4fe6dea8 | 10413 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 10414 | case 1: |
4fe6dea8 AK |
10415 | if (larl_operand (operands[0], Pmode)) |
10416 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
10417 | default: | |
10418 | ||
10419 | /* This might be reached for symbolic operands with an odd | |
10420 | addend. We simply omit the prefetch for such rare cases. */ | |
10421 | ||
10422 | return ""; | |
10423 | } | |
9381e3f1 | 10424 | } |
22d72dbc AK |
10425 | [(set_attr "type" "load,larl") |
10426 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
10427 | (set_attr "z10prop" "z10_super") |
10428 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
10429 | |
10430 | ||
10431 | ; | |
10432 | ; Byte swap instructions | |
10433 | ; | |
10434 | ||
511f5bb1 AK |
10435 | ; FIXME: There is also mvcin but we cannot use it since src and target |
10436 | ; may overlap. | |
07da44ab | 10437 | (define_insn "bswap<mode>2" |
6f5a59d1 AK |
10438 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,RT") |
10439 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))] | |
677fbff4 | 10440 | "TARGET_CPU_ZARCH" |
07da44ab AK |
10441 | "@ |
10442 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
10443 | lrv<g>\t%0,%1 |
10444 | strv<g>\t%1,%0" | |
10445 | [(set_attr "type" "*,load,store") | |
10446 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 10447 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10448 | |
511f5bb1 | 10449 | (define_insn "bswaphi2" |
6f5a59d1 AK |
10450 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d, d,RT") |
10451 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))] | |
511f5bb1 | 10452 | "TARGET_CPU_ZARCH" |
6f5a59d1 AK |
10453 | "@ |
10454 | # | |
10455 | lrvh\t%0,%1 | |
10456 | strvh\t%1,%0" | |
10457 | [(set_attr "type" "*,load,store") | |
10458 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 10459 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10460 | |
6f5a59d1 AK |
10461 | (define_split |
10462 | [(set (match_operand:HI 0 "register_operand" "") | |
10463 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
10464 | "TARGET_CPU_ZARCH" | |
10465 | [(set (match_dup 2) (bswap:SI (match_dup 3))) | |
9060e335 | 10466 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 10467 | { |
9060e335 | 10468 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
10469 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
10470 | }) | |
10471 | ||
10472 | ||
65b1d8ea AK |
10473 | ; |
10474 | ; Population count instruction | |
10475 | ; | |
10476 | ||
10477 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
10478 | ; portions and stores the result in the corresponding bytes in op0. | |
10479 | (define_insn "*popcount<mode>" | |
10480 | [(set (match_operand:INT 0 "register_operand" "=d") | |
10481 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
10482 | (clobber (reg:CC CC_REGNUM))] | |
10483 | "TARGET_Z196" | |
10484 | "popcnt\t%0,%1" | |
10485 | [(set_attr "op_type" "RRE")]) | |
10486 | ||
10487 | (define_expand "popcountdi2" | |
10488 | [; popcnt op0, op1 | |
10489 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
10490 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
10491 | UNSPEC_POPCNT)) | |
10492 | (clobber (reg:CC CC_REGNUM))]) | |
10493 | ; sllg op2, op0, 32 | |
10494 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
10495 | ; agr op0, op2 | |
10496 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10497 | (clobber (reg:CC CC_REGNUM))]) | |
10498 | ; sllg op2, op0, 16 | |
17465c6e | 10499 | (set (match_dup 2) |
65b1d8ea AK |
10500 | (ashift:DI (match_dup 0) (const_int 16))) |
10501 | ; agr op0, op2 | |
10502 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10503 | (clobber (reg:CC CC_REGNUM))]) | |
10504 | ; sllg op2, op0, 8 | |
10505 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
10506 | ; agr op0, op2 | |
10507 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10508 | (clobber (reg:CC CC_REGNUM))]) | |
10509 | ; srlg op0, op0, 56 | |
10510 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
10511 | "TARGET_Z196 && TARGET_64BIT" | |
10512 | "operands[2] = gen_reg_rtx (DImode);") | |
10513 | ||
10514 | (define_expand "popcountsi2" | |
10515 | [; popcnt op0, op1 | |
10516 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
10517 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
10518 | UNSPEC_POPCNT)) | |
10519 | (clobber (reg:CC CC_REGNUM))]) | |
10520 | ; sllk op2, op0, 16 | |
17465c6e | 10521 | (set (match_dup 2) |
65b1d8ea AK |
10522 | (ashift:SI (match_dup 0) (const_int 16))) |
10523 | ; ar op0, op2 | |
10524 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10525 | (clobber (reg:CC CC_REGNUM))]) | |
10526 | ; sllk op2, op0, 8 | |
10527 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
10528 | ; ar op0, op2 | |
10529 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10530 | (clobber (reg:CC CC_REGNUM))]) | |
10531 | ; srl op0, op0, 24 | |
10532 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
10533 | "TARGET_Z196" | |
10534 | "operands[2] = gen_reg_rtx (SImode);") | |
10535 | ||
10536 | (define_expand "popcounthi2" | |
10537 | [; popcnt op0, op1 | |
10538 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
10539 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
10540 | UNSPEC_POPCNT)) | |
10541 | (clobber (reg:CC CC_REGNUM))]) | |
10542 | ; sllk op2, op0, 8 | |
17465c6e | 10543 | (set (match_dup 2) |
65b1d8ea AK |
10544 | (ashift:SI (match_dup 0) (const_int 8))) |
10545 | ; ar op0, op2 | |
10546 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10547 | (clobber (reg:CC CC_REGNUM))]) | |
10548 | ; srl op0, op0, 8 | |
10549 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
10550 | "TARGET_Z196" | |
10551 | "operands[2] = gen_reg_rtx (SImode);") | |
10552 | ||
10553 | (define_expand "popcountqi2" | |
10554 | [; popcnt op0, op1 | |
10555 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
10556 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
10557 | UNSPEC_POPCNT)) | |
10558 | (clobber (reg:CC CC_REGNUM))])] | |
10559 | "TARGET_Z196" | |
10560 | "") | |
10561 | ||
10562 | ;; | |
10563 | ;;- Copy sign instructions | |
10564 | ;; | |
10565 | ||
10566 | (define_insn "copysign<mode>3" | |
10567 | [(set (match_operand:FP 0 "register_operand" "=f") | |
10568 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
10569 | (match_operand:FP 2 "register_operand" "f")] | |
10570 | UNSPEC_COPYSIGN))] | |
10571 | "TARGET_Z196" | |
10572 | "cpsdr\t%0,%2,%1" | |
10573 | [(set_attr "op_type" "RRF") | |
10574 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
10575 | |
10576 | ||
10577 | ;; | |
10578 | ;;- Transactional execution instructions | |
10579 | ;; | |
10580 | ||
10581 | ; This splitter helps combine to make use of CC directly when | |
10582 | ; comparing the integer result of a tbegin builtin with a constant. | |
10583 | ; The unspec is already removed by canonicalize_comparison. So this | |
10584 | ; splitters only job is to turn the PARALLEL into separate insns | |
10585 | ; again. Unfortunately this only works with the very first cc/int | |
10586 | ; compare since combine is not able to deal with data flow across | |
10587 | ; basic block boundaries. | |
10588 | ||
10589 | ; It needs to be an insn pattern as well since combine does not apply | |
10590 | ; the splitter directly. Combine would only use it if it actually | |
10591 | ; would reduce the number of instructions. | |
10592 | (define_insn_and_split "*ccraw_to_int" | |
10593 | [(set (pc) | |
10594 | (if_then_else | |
10595 | (match_operator 0 "s390_eqne_operator" | |
10596 | [(reg:CCRAW CC_REGNUM) | |
10597 | (match_operand 1 "const_int_operand" "")]) | |
10598 | (label_ref (match_operand 2 "" "")) | |
10599 | (pc))) | |
10600 | (set (match_operand:SI 3 "register_operand" "=d") | |
10601 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
10602 | "" | |
10603 | "#" | |
10604 | "" | |
10605 | [(set (match_dup 3) | |
10606 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
10607 | (set (pc) | |
10608 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
10609 | (label_ref (match_dup 2)) | |
10610 | (pc)))] | |
10611 | "") | |
10612 | ||
10613 | ; Non-constrained transaction begin | |
10614 | ||
10615 | (define_expand "tbegin" | |
ee163e72 AK |
10616 | [(match_operand:SI 0 "register_operand" "") |
10617 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10618 | "TARGET_HTM" |
10619 | { | |
10620 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
10621 | DONE; | |
10622 | }) | |
10623 | ||
10624 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
10625 | [(match_operand:SI 0 "register_operand" "") |
10626 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10627 | "TARGET_HTM" |
10628 | { | |
10629 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
10630 | DONE; | |
10631 | }) | |
10632 | ||
10633 | (define_expand "tbegin_retry" | |
ee163e72 AK |
10634 | [(match_operand:SI 0 "register_operand" "") |
10635 | (match_operand:BLK 1 "memory_operand" "") | |
10636 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10637 | "TARGET_HTM" |
10638 | { | |
10639 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
10640 | DONE; | |
10641 | }) | |
10642 | ||
10643 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
10644 | [(match_operand:SI 0 "register_operand" "") |
10645 | (match_operand:BLK 1 "memory_operand" "") | |
10646 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10647 | "TARGET_HTM" |
10648 | { | |
10649 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
10650 | DONE; | |
10651 | }) | |
10652 | ||
c914ac45 AK |
10653 | ; Clobber VRs since they don't get restored |
10654 | (define_insn "tbegin_1_z13" | |
10655 | [(set (reg:CCRAW CC_REGNUM) | |
10656 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
10657 | UNSPECV_TBEGIN)) | |
10658 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10659 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
10660 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
10661 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
10662 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
10663 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
10664 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
10665 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
10666 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
10667 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
10668 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
10669 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
10670 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
10671 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
10672 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
10673 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
10674 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
10675 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
10676 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10677 | ; not supposed to be used for immediates (see genpreds.c). | |
10678 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10679 | "tbegin\t%1,%x0" | |
10680 | [(set_attr "op_type" "SIL")]) | |
10681 | ||
5a3fe9b6 AK |
10682 | (define_insn "tbegin_1" |
10683 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 10684 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 10685 | UNSPECV_TBEGIN)) |
2561451d AK |
10686 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
10687 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
10688 | (clobber (reg:DF 16)) |
10689 | (clobber (reg:DF 17)) | |
10690 | (clobber (reg:DF 18)) | |
10691 | (clobber (reg:DF 19)) | |
10692 | (clobber (reg:DF 20)) | |
10693 | (clobber (reg:DF 21)) | |
10694 | (clobber (reg:DF 22)) | |
10695 | (clobber (reg:DF 23)) | |
10696 | (clobber (reg:DF 24)) | |
10697 | (clobber (reg:DF 25)) | |
10698 | (clobber (reg:DF 26)) | |
10699 | (clobber (reg:DF 27)) | |
10700 | (clobber (reg:DF 28)) | |
10701 | (clobber (reg:DF 29)) | |
10702 | (clobber (reg:DF 30)) | |
10703 | (clobber (reg:DF 31))] | |
10704 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10705 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
10706 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
10707 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10708 | [(set_attr "op_type" "SIL")]) |
10709 | ||
10710 | ; Same as above but without the FPR clobbers | |
10711 | (define_insn "tbegin_nofloat_1" | |
10712 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
10713 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
10714 | UNSPECV_TBEGIN)) | |
10715 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10716 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
10717 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10718 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10719 | [(set_attr "op_type" "SIL")]) |
10720 | ||
10721 | ||
10722 | ; Constrained transaction begin | |
10723 | ||
10724 | (define_expand "tbeginc" | |
10725 | [(set (reg:CCRAW CC_REGNUM) | |
10726 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
10727 | UNSPECV_TBEGINC))] | |
10728 | "TARGET_HTM" | |
10729 | "") | |
10730 | ||
10731 | (define_insn "*tbeginc_1" | |
10732 | [(set (reg:CCRAW CC_REGNUM) | |
10733 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
10734 | UNSPECV_TBEGINC))] | |
10735 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10736 | "tbeginc\t0,%x0" | |
10737 | [(set_attr "op_type" "SIL")]) | |
10738 | ||
10739 | ; Transaction end | |
10740 | ||
10741 | (define_expand "tend" | |
10742 | [(set (reg:CCRAW CC_REGNUM) | |
10743 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 10744 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
10745 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
10746 | "TARGET_HTM" | |
10747 | "") | |
10748 | ||
10749 | (define_insn "*tend_1" | |
10750 | [(set (reg:CCRAW CC_REGNUM) | |
10751 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
10752 | "TARGET_HTM" | |
10753 | "tend" | |
10754 | [(set_attr "op_type" "S")]) | |
10755 | ||
10756 | ; Transaction abort | |
10757 | ||
10758 | (define_expand "tabort" | |
eae48192 | 10759 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
10760 | UNSPECV_TABORT)] |
10761 | "TARGET_HTM && operands != NULL" | |
10762 | { | |
10763 | if (CONST_INT_P (operands[0]) | |
10764 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
10765 | { | |
10766 | error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC | |
10767 | ". Values in range 0 through 255 are reserved.", | |
10768 | INTVAL (operands[0])); | |
10769 | FAIL; | |
10770 | } | |
10771 | }) | |
10772 | ||
10773 | (define_insn "*tabort_1" | |
eae48192 | 10774 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
10775 | UNSPECV_TABORT)] |
10776 | "TARGET_HTM && operands != NULL" | |
10777 | "tabort\t%Y0" | |
10778 | [(set_attr "op_type" "S")]) | |
10779 | ||
eae48192 AK |
10780 | (define_insn "*tabort_1_plus" |
10781 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
10782 | (match_operand:SI 1 "const_int_operand" "J"))] | |
10783 | UNSPECV_TABORT)] | |
10784 | "TARGET_HTM && operands != NULL | |
10785 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
10786 | "tabort\t%1(%0)" | |
10787 | [(set_attr "op_type" "S")]) | |
10788 | ||
5a3fe9b6 AK |
10789 | ; Transaction extract nesting depth |
10790 | ||
10791 | (define_insn "etnd" | |
10792 | [(set (match_operand:SI 0 "register_operand" "=d") | |
10793 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
10794 | "TARGET_HTM" | |
10795 | "etnd\t%0" | |
10796 | [(set_attr "op_type" "RRE")]) | |
10797 | ||
10798 | ; Non-transactional store | |
10799 | ||
10800 | (define_insn "ntstg" | |
10801 | [(set (match_operand:DI 0 "memory_operand" "=RT") | |
10802 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] | |
10803 | UNSPECV_NTSTG))] | |
10804 | "TARGET_HTM" | |
10805 | "ntstg\t%1,%0" | |
10806 | [(set_attr "op_type" "RXY")]) | |
10807 | ||
10808 | ; Transaction perform processor assist | |
10809 | ||
10810 | (define_expand "tx_assist" | |
2561451d AK |
10811 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
10812 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
10813 | (const_int 1)] |
10814 | UNSPECV_PPA)] | |
10815 | "TARGET_HTM" | |
2561451d | 10816 | "") |
5a3fe9b6 AK |
10817 | |
10818 | (define_insn "*ppa" | |
10819 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
10820 | (match_operand:SI 1 "register_operand" "d") | |
10821 | (match_operand 2 "const_int_operand" "I")] | |
10822 | UNSPECV_PPA)] | |
10823 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 10824 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 10825 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
10826 | |
10827 | ||
10828 | ; Set and get floating point control register | |
10829 | ||
3af82a61 | 10830 | (define_insn "sfpc" |
004f64e1 AK |
10831 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
10832 | UNSPECV_SFPC)] | |
10833 | "TARGET_HARD_FLOAT" | |
10834 | "sfpc\t%0") | |
10835 | ||
3af82a61 | 10836 | (define_insn "efpc" |
004f64e1 AK |
10837 | [(set (match_operand:SI 0 "register_operand" "=d") |
10838 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
10839 | "TARGET_HARD_FLOAT" | |
10840 | "efpc\t%0") | |
3af82a61 AK |
10841 | |
10842 | ||
10843 | ; Load count to block boundary | |
10844 | ||
10845 | (define_insn "lcbb" | |
10846 | [(set (match_operand:SI 0 "register_operand" "=d") | |
9a36359e | 10847 | (unspec:SI [(match_operand 1 "address_operand" "ZQZR") |
3af82a61 AK |
10848 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
10849 | (clobber (reg:CC CC_REGNUM))] | |
10850 | "TARGET_Z13" | |
9a36359e | 10851 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 10852 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
10853 | |
10854 | ; Handle -fsplit-stack. | |
10855 | ||
10856 | (define_expand "split_stack_prologue" | |
10857 | [(const_int 0)] | |
10858 | "" | |
10859 | { | |
10860 | s390_expand_split_stack_prologue (); | |
10861 | DONE; | |
10862 | }) | |
10863 | ||
10864 | ;; If there are operand 0 bytes available on the stack, jump to | |
10865 | ;; operand 1. | |
10866 | ||
10867 | (define_expand "split_stack_space_check" | |
10868 | [(set (pc) (if_then_else | |
10869 | (ltu (minus (reg 15) | |
10870 | (match_operand 0 "register_operand")) | |
10871 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
10872 | (label_ref (match_operand 1)) | |
10873 | (pc)))] | |
10874 | "" | |
10875 | { | |
10876 | /* Offset from thread pointer to __private_ss. */ | |
10877 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
10878 | rtx tp = s390_get_thread_pointer (); | |
10879 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
10880 | rtx reg = gen_reg_rtx (Pmode); | |
10881 | rtx cc; | |
10882 | if (TARGET_64BIT) | |
10883 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
10884 | else | |
10885 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
10886 | cc = s390_emit_compare (GT, reg, guard); | |
10887 | s390_emit_jump (operands[1], cc); | |
10888 | ||
10889 | DONE; | |
10890 | }) | |
10891 | ||
10892 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
10893 | ;; parameter block label, label to be called by __morestack, frame size, | |
10894 | ;; stack parameter size. | |
10895 | ||
10896 | (define_insn "split_stack_data" | |
10897 | [(unspec_volatile [(match_operand 0 "" "X") | |
10898 | (match_operand 1 "" "X") | |
10899 | (match_operand 2 "const_int_operand" "X") | |
10900 | (match_operand 3 "const_int_operand" "X")] | |
10901 | UNSPECV_SPLIT_STACK_DATA)] | |
10902 | "TARGET_CPU_ZARCH" | |
10903 | { | |
10904 | switch_to_section (targetm.asm_out.function_rodata_section | |
10905 | (current_function_decl)); | |
10906 | ||
10907 | if (TARGET_64BIT) | |
10908 | output_asm_insn (".align\t8", operands); | |
10909 | else | |
10910 | output_asm_insn (".align\t4", operands); | |
10911 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
10912 | CODE_LABEL_NUMBER (operands[0])); | |
10913 | if (TARGET_64BIT) | |
10914 | { | |
10915 | output_asm_insn (".quad\t%2", operands); | |
10916 | output_asm_insn (".quad\t%3", operands); | |
10917 | output_asm_insn (".quad\t%1-%0", operands); | |
10918 | } | |
10919 | else | |
10920 | { | |
10921 | output_asm_insn (".long\t%2", operands); | |
10922 | output_asm_insn (".long\t%3", operands); | |
10923 | output_asm_insn (".long\t%1-%0", operands); | |
10924 | } | |
10925 | ||
10926 | switch_to_section (current_function_section ()); | |
10927 | return ""; | |
10928 | } | |
10929 | [(set_attr "length" "0")]) | |
10930 | ||
10931 | ||
10932 | ;; A jg with minimal fuss for use in split stack prologue. | |
10933 | ||
10934 | (define_expand "split_stack_call" | |
10935 | [(match_operand 0 "bras_sym_operand" "X") | |
10936 | (match_operand 1 "" "")] | |
10937 | "TARGET_CPU_ZARCH" | |
10938 | { | |
10939 | if (TARGET_64BIT) | |
10940 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
10941 | else | |
10942 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
10943 | DONE; | |
10944 | }) | |
10945 | ||
10946 | (define_insn "split_stack_call_<mode>" | |
10947 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
10948 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
10949 | (reg:P 1)] | |
10950 | UNSPECV_SPLIT_STACK_CALL))] | |
10951 | "TARGET_CPU_ZARCH" | |
10952 | "jg\t%0" | |
10953 | [(set_attr "op_type" "RIL") | |
10954 | (set_attr "type" "branch")]) | |
10955 | ||
10956 | ;; Also a conditional one. | |
10957 | ||
10958 | (define_expand "split_stack_cond_call" | |
10959 | [(match_operand 0 "bras_sym_operand" "X") | |
10960 | (match_operand 1 "" "") | |
10961 | (match_operand 2 "" "")] | |
10962 | "TARGET_CPU_ZARCH" | |
10963 | { | |
10964 | if (TARGET_64BIT) | |
10965 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
10966 | else | |
10967 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
10968 | DONE; | |
10969 | }) | |
10970 | ||
10971 | (define_insn "split_stack_cond_call_<mode>" | |
10972 | [(set (pc) | |
10973 | (if_then_else | |
10974 | (match_operand 1 "" "") | |
10975 | (label_ref (match_operand 2 "" "")) | |
10976 | (pc))) | |
10977 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
10978 | (reg:P 1)] | |
10979 | UNSPECV_SPLIT_STACK_CALL))] | |
10980 | "TARGET_CPU_ZARCH" | |
10981 | "jg%C1\t%0" | |
10982 | [(set_attr "op_type" "RIL") | |
10983 | (set_attr "type" "branch")]) |