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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
a5544970 | 2 | ;; Copyright (C) 1999-2019 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 | 77 | UNSPEC_LTREL_OFFSET |
30a49b23 AK |
78 | UNSPEC_POOL_OFFSET |
79 | UNSPEC_GOTENT | |
80 | UNSPEC_GOT | |
81 | UNSPEC_GOTOFF | |
82 | UNSPEC_PLT | |
83 | UNSPEC_PLTOFF | |
fd7643fb UW |
84 | |
85 | ; Literal pool | |
30a49b23 AK |
86 | UNSPEC_RELOAD_BASE |
87 | UNSPEC_MAIN_BASE | |
88 | UNSPEC_LTREF | |
89 | UNSPEC_INSN | |
90 | UNSPEC_EXECUTE | |
84b4c7b5 | 91 | UNSPEC_EXECUTE_JUMP |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea | 122 | |
25cb5165 | 123 | ; Byte-wise Population Count |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
76794c52 | 159 | UNSPEC_VEC_LOAD_LEN_R |
3af82a61 AK |
160 | UNSPEC_VEC_MERGEH |
161 | UNSPEC_VEC_MERGEL | |
162 | UNSPEC_VEC_PACK | |
163 | UNSPEC_VEC_PACK_SATURATE | |
164 | UNSPEC_VEC_PACK_SATURATE_CC | |
165 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
168 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
169 | UNSPEC_VEC_PERM | |
170 | UNSPEC_VEC_PERMI | |
171 | UNSPEC_VEC_EXTEND | |
172 | UNSPEC_VEC_STORE_LEN | |
76794c52 AK |
173 | UNSPEC_VEC_STORE_LEN_R |
174 | UNSPEC_VEC_VBPERM | |
3af82a61 AK |
175 | UNSPEC_VEC_UNPACKH |
176 | UNSPEC_VEC_UNPACKH_L | |
177 | UNSPEC_VEC_UNPACKL | |
178 | UNSPEC_VEC_UNPACKL_L | |
179 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
180 | UNSPEC_VEC_ADDE_U128 |
181 | UNSPEC_VEC_ADDEC_U128 | |
182 | UNSPEC_VEC_AVG | |
183 | UNSPEC_VEC_AVGU | |
184 | UNSPEC_VEC_CHECKSUM | |
185 | UNSPEC_VEC_GFMSUM | |
186 | UNSPEC_VEC_GFMSUM_128 | |
187 | UNSPEC_VEC_GFMSUM_ACCUM | |
188 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
189 | UNSPEC_VEC_SET | |
190 | ||
191 | UNSPEC_VEC_VSUMG | |
192 | UNSPEC_VEC_VSUMQ | |
193 | UNSPEC_VEC_VSUM | |
194 | UNSPEC_VEC_RL_MASK | |
195 | UNSPEC_VEC_SLL | |
196 | UNSPEC_VEC_SLB | |
ad7a3e39 AK |
197 | UNSPEC_VEC_SLDBYTE |
198 | UNSPEC_VEC_SLDBIT | |
199 | UNSPEC_VEC_SRDBIT | |
3af82a61 AK |
200 | UNSPEC_VEC_SRAL |
201 | UNSPEC_VEC_SRAB | |
202 | UNSPEC_VEC_SRL | |
203 | UNSPEC_VEC_SRLB | |
204 | ||
3af82a61 | 205 | UNSPEC_VEC_SUBC |
3af82a61 AK |
206 | UNSPEC_VEC_SUBE_U128 |
207 | UNSPEC_VEC_SUBEC_U128 | |
208 | ||
209 | UNSPEC_VEC_TEST_MASK | |
210 | ||
211 | UNSPEC_VEC_VFAE | |
212 | UNSPEC_VEC_VFAECC | |
213 | ||
214 | UNSPEC_VEC_VFEE | |
215 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
216 | UNSPEC_VEC_VFENE |
217 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
218 | |
219 | UNSPEC_VEC_VISTR | |
220 | UNSPEC_VEC_VISTRCC | |
221 | ||
222 | UNSPEC_VEC_VSTRC | |
223 | UNSPEC_VEC_VSTRCCC | |
224 | ||
49adc461 AK |
225 | UNSPEC_VEC_VSTRS |
226 | UNSPEC_VEC_VSTRSCC | |
227 | ||
3af82a61 AK |
228 | UNSPEC_VEC_VCDGB |
229 | UNSPEC_VEC_VCDLGB | |
230 | ||
231 | UNSPEC_VEC_VCGDB | |
232 | UNSPEC_VEC_VCLGDB | |
233 | ||
76794c52 | 234 | UNSPEC_VEC_VFI |
3af82a61 | 235 | |
76794c52 AK |
236 | UNSPEC_VEC_VFLL ; vector fp load lengthened |
237 | UNSPEC_VEC_VFLR ; vector fp load rounded | |
3af82a61 | 238 | |
76794c52 AK |
239 | UNSPEC_VEC_VFTCI |
240 | UNSPEC_VEC_VFTCICC | |
241 | ||
242 | UNSPEC_VEC_MSUM | |
243 | ||
244 | UNSPEC_VEC_VFMIN | |
245 | UNSPEC_VEC_VFMAX | |
3278804e AK |
246 | |
247 | UNSPEC_VEC_ELTSWAP | |
085261c8 | 248 | ]) |
fd3cd001 UW |
249 | |
250 | ;; | |
251 | ;; UNSPEC_VOLATILE usage | |
252 | ;; | |
253 | ||
30a49b23 AK |
254 | (define_c_enum "unspecv" [ |
255 | ; Blockage | |
256 | UNSPECV_BLOCKAGE | |
10bbf137 | 257 | |
2f7e5a0d | 258 | ; TPF Support |
30a49b23 AK |
259 | UNSPECV_TPF_PROLOGUE |
260 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 261 | |
10bbf137 | 262 | ; Literal pool |
30a49b23 AK |
263 | UNSPECV_POOL |
264 | UNSPECV_POOL_SECTION | |
265 | UNSPECV_POOL_ALIGN | |
266 | UNSPECV_POOL_ENTRY | |
267 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
268 | |
269 | ; TLS support | |
30a49b23 | 270 | UNSPECV_SET_TP |
e0374221 AS |
271 | |
272 | ; Atomic Support | |
30a49b23 AK |
273 | UNSPECV_CAS |
274 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 275 | |
aad98a61 AK |
276 | ; Non-branch nops used for compare-and-branch adjustments on z10 |
277 | UNSPECV_NOP_LR_0 | |
278 | UNSPECV_NOP_LR_1 | |
279 | ||
f8af0e30 DV |
280 | ; Hotpatching (unremovable NOPs) |
281 | UNSPECV_NOP_2_BYTE | |
282 | UNSPECV_NOP_4_BYTE | |
283 | UNSPECV_NOP_6_BYTE | |
284 | ||
5a3fe9b6 AK |
285 | ; Transactional Execution support |
286 | UNSPECV_TBEGIN | |
2561451d | 287 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
288 | UNSPECV_TBEGINC |
289 | UNSPECV_TEND | |
290 | UNSPECV_TABORT | |
291 | UNSPECV_ETND | |
292 | UNSPECV_NTSTG | |
293 | UNSPECV_PPA | |
004f64e1 AK |
294 | |
295 | ; Set and get floating point control register | |
296 | UNSPECV_SFPC | |
297 | UNSPECV_EFPC | |
4cb4721f MK |
298 | |
299 | ; Split stack support | |
300 | UNSPECV_SPLIT_STACK_CALL | |
301 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
302 | |
303 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
304 | ]) |
305 | ||
ae156f85 AS |
306 | ;; |
307 | ;; Registers | |
308 | ;; | |
309 | ||
35dd9a0e AK |
310 | ; Registers with special meaning |
311 | ||
ae156f85 AS |
312 | (define_constants |
313 | [ | |
314 | ; Sibling call register. | |
315 | (SIBCALL_REGNUM 1) | |
84b4c7b5 AK |
316 | ; A call-clobbered reg which can be used in indirect branch thunks |
317 | (INDIRECT_BRANCH_THUNK_REGNUM 1) | |
ae156f85 AS |
318 | ; Literal pool base register. |
319 | (BASE_REGNUM 13) | |
320 | ; Return address register. | |
321 | (RETURN_REGNUM 14) | |
82c6f58a AK |
322 | ; Stack pointer register. |
323 | (STACK_REGNUM 15) | |
ae156f85 AS |
324 | ; Condition code register. |
325 | (CC_REGNUM 33) | |
f4aa3848 | 326 | ; Thread local storage pointer register. |
ae156f85 AS |
327 | (TP_REGNUM 36) |
328 | ]) | |
329 | ||
35dd9a0e AK |
330 | ; Hardware register names |
331 | ||
332 | (define_constants | |
333 | [ | |
334 | ; General purpose registers | |
335 | (GPR0_REGNUM 0) | |
af344a30 | 336 | (GPR1_REGNUM 1) |
82379bdf AK |
337 | (GPR2_REGNUM 2) |
338 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
339 | ; Floating point registers. |
340 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
341 | (FPR1_REGNUM 20) |
342 | (FPR2_REGNUM 17) | |
343 | (FPR3_REGNUM 21) | |
344 | (FPR4_REGNUM 18) | |
345 | (FPR5_REGNUM 22) | |
346 | (FPR6_REGNUM 19) | |
347 | (FPR7_REGNUM 23) | |
348 | (FPR8_REGNUM 24) | |
349 | (FPR9_REGNUM 28) | |
350 | (FPR10_REGNUM 25) | |
351 | (FPR11_REGNUM 29) | |
352 | (FPR12_REGNUM 26) | |
353 | (FPR13_REGNUM 30) | |
354 | (FPR14_REGNUM 27) | |
355 | (FPR15_REGNUM 31) | |
085261c8 AK |
356 | (VR0_REGNUM 16) |
357 | (VR16_REGNUM 38) | |
358 | (VR23_REGNUM 45) | |
359 | (VR24_REGNUM 46) | |
360 | (VR31_REGNUM 53) | |
35dd9a0e AK |
361 | ]) |
362 | ||
ae8e301e AK |
363 | ; Rounding modes for binary floating point numbers |
364 | (define_constants | |
365 | [(BFP_RND_CURRENT 0) | |
366 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
367 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
368 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
369 | (BFP_RND_TOWARD_0 5) | |
370 | (BFP_RND_TOWARD_INF 6) | |
371 | (BFP_RND_TOWARD_MINF 7)]) | |
372 | ||
373 | ; Rounding modes for decimal floating point numbers | |
374 | ; 1-7 were introduced with the floating point extension facility | |
375 | ; available with z196 | |
376 | ; With these rounding modes (1-7) a quantum exception might occur | |
377 | ; which is suppressed for the other modes. | |
378 | (define_constants | |
379 | [(DFP_RND_CURRENT 0) | |
380 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
381 | (DFP_RND_CURRENT_QUANTEXC 2) | |
382 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
383 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
384 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
385 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
386 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
387 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
388 | (DFP_RND_TOWARD_0 9) | |
389 | (DFP_RND_TOWARD_INF 10) | |
390 | (DFP_RND_TOWARD_MINF 11) | |
391 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
392 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
393 | (DFP_RND_AWAY_FROM_0 14) | |
394 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
395 | ||
35dd9a0e AK |
396 | ;; |
397 | ;; PFPO GPR0 argument format | |
398 | ;; | |
399 | ||
400 | (define_constants | |
401 | [ | |
402 | ; PFPO operation type | |
403 | (PFPO_CONVERT 0x1000000) | |
404 | ; PFPO operand types | |
405 | (PFPO_OP_TYPE_SF 0x5) | |
406 | (PFPO_OP_TYPE_DF 0x6) | |
407 | (PFPO_OP_TYPE_TF 0x7) | |
408 | (PFPO_OP_TYPE_SD 0x8) | |
409 | (PFPO_OP_TYPE_DD 0x9) | |
410 | (PFPO_OP_TYPE_TD 0xa) | |
411 | ; Bitposition of operand types | |
412 | (PFPO_OP0_TYPE_SHIFT 16) | |
413 | (PFPO_OP1_TYPE_SHIFT 8) | |
ced8d882 AK |
414 | ; Decide whether current DFP or BFD rounding mode should be used |
415 | ; for the conversion. | |
416 | (PFPO_RND_MODE_DFP 0) | |
417 | (PFPO_RND_MODE_BFP 1) | |
35dd9a0e AK |
418 | ]) |
419 | ||
291a9e98 AK |
420 | ;; PPA constants |
421 | ||
422 | ; Immediate values which can be used as the third operand to the | |
423 | ; perform processor assist instruction | |
424 | ||
425 | (define_constants | |
426 | [(PPA_TX_ABORT 1) | |
427 | (PPA_OOO_BARRIER 15)]) | |
428 | ||
5a3fe9b6 AK |
429 | ; Immediate operands for tbegin and tbeginc |
430 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
431 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 432 | |
29a74354 UW |
433 | ;; Instruction operand type as used in the Principles of Operation. |
434 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 435 | |
29a74354 | 436 | (define_attr "op_type" |
76794c52 | 437 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" |
b628bd8e | 438 | (const_string "NN")) |
9db1d521 | 439 | |
29a74354 | 440 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 441 | |
077dab3b | 442 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 443 | cs,vs,store,sem,idiv, |
ed0e512a | 444 | imulhi,imulsi,imuldi, |
2cdece44 | 445 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
446 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
447 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 448 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 449 | fmadddf,fmaddsf, |
9381e3f1 WG |
450 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
451 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
452 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
453 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
454 | ftoidfp, other" | |
29a74354 UW |
455 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
456 | (eq_attr "op_type" "SS") (const_string "cs")] | |
457 | (const_string "integer"))) | |
9db1d521 | 458 | |
29a74354 UW |
459 | ;; Another attribute used for scheduling purposes: |
460 | ;; agen: Instruction uses the address generation unit | |
461 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
462 | |
463 | (define_attr "atype" "agen,reg" | |
62d3f261 | 464 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
465 | (const_string "reg") |
466 | (const_string "agen"))) | |
9db1d521 | 467 | |
9381e3f1 WG |
468 | ;; Properties concerning Z10 execution grouping and value forwarding. |
469 | ;; z10_super: instruction is superscalar. | |
470 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
471 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
472 | ;; target register. It can forward this value to a second instruction that reads | |
473 | ;; the same register if that second instruction is issued in the same group. | |
474 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
475 | ;; instruction in the S pipe writes to the register, then the T instruction | |
476 | ;; can immediately read the new value. | |
477 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
478 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
479 | ;; |
480 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
481 | ||
482 | ||
483 | (define_attr "z10prop" "none, | |
484 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
485 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
486 | z10_rec, | |
487 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 488 | z10_c" |
9381e3f1 WG |
489 | (const_string "none")) |
490 | ||
65b1d8ea AK |
491 | ;; Properties concerning Z196 decoding |
492 | ;; z196_alone: must group alone | |
493 | ;; z196_end: ends a group | |
494 | ;; z196_cracked: instruction is cracked or expanded | |
495 | (define_attr "z196prop" "none, | |
496 | z196_alone, z196_ends, | |
497 | z196_cracked" | |
498 | (const_string "none")) | |
9381e3f1 | 499 | |
84b4c7b5 AK |
500 | ; mnemonics which only get defined through if_then_else currently |
501 | ; don't get added to the list values automatically and hence need to | |
502 | ; be listed here. | |
8cc6307c | 503 | (define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 504 | |
9db1d521 HP |
505 | ;; Length in bytes. |
506 | ||
507 | (define_attr "length" "" | |
62d3f261 AK |
508 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
509 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 510 | (const_int 6))) |
9db1d521 | 511 | |
29a74354 UW |
512 | |
513 | ;; Processor type. This attribute must exactly match the processor_type | |
52d4aa4f | 514 | ;; enumeration in s390.h. |
29a74354 | 515 | |
375a6bc6 | 516 | (define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,arch13" |
90c6fd8a | 517 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 518 | |
b5e0425c | 519 | (define_attr "cpu_facility" |
511ea153 | 520 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,arch13,vxe2" |
3af8e996 AK |
521 | (const_string "standard")) |
522 | ||
523 | (define_attr "enabled" "" | |
524 | (cond [(eq_attr "cpu_facility" "standard") | |
525 | (const_int 1) | |
526 | ||
527 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 528 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
529 | (const_int 1) |
530 | ||
531 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 532 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
533 | (const_int 1) |
534 | ||
535 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 536 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
537 | (const_int 1) |
538 | ||
539 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 540 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
541 | (const_int 1) |
542 | ||
543 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 544 | (match_test "TARGET_DFP")) |
93538e8e AK |
545 | (const_int 1) |
546 | ||
8cc6307c | 547 | (eq_attr "cpu_facility" "cpu_zarch") |
b5e0425c AK |
548 | (const_int 1) |
549 | ||
93538e8e | 550 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 551 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
552 | (const_int 1) |
553 | ||
554 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 555 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
556 | (const_int 1) |
557 | ||
558 | (and (eq_attr "cpu_facility" "zEC12") | |
559 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
560 | (const_int 1) |
561 | ||
285363a1 | 562 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 563 | (match_test "TARGET_VX")) |
bf749919 DV |
564 | (const_int 1) |
565 | ||
566 | (and (eq_attr "cpu_facility" "z13") | |
567 | (match_test "TARGET_Z13")) | |
568 | (const_int 1) | |
6654e96f | 569 | |
e9e8efc9 AK |
570 | (and (eq_attr "cpu_facility" "z14") |
571 | (match_test "TARGET_Z14")) | |
6654e96f AK |
572 | (const_int 1) |
573 | ||
574 | (and (eq_attr "cpu_facility" "vxe") | |
575 | (match_test "TARGET_VXE")) | |
576 | (const_int 1) | |
511ea153 AK |
577 | |
578 | (and (eq_attr "cpu_facility" "arch13") | |
579 | (match_test "TARGET_ARCH13")) | |
580 | (const_int 1) | |
581 | ||
582 | (and (eq_attr "cpu_facility" "vxe2") | |
583 | (match_test "TARGET_VXE2")) | |
584 | (const_int 1) | |
bf749919 | 585 | ] |
3af8e996 AK |
586 | (const_int 0))) |
587 | ||
14cfceb7 IL |
588 | ;; Whether an instruction supports relative long addressing. |
589 | ;; Currently this corresponds to RIL-b and RIL-c instruction formats, | |
590 | ;; but having a separate attribute, as opposed to reusing op_type, | |
591 | ;; provides additional flexibility. | |
592 | ||
593 | (define_attr "relative_long" "no,yes" (const_string "no")) | |
594 | ||
52d4aa4f | 595 | ;; Pipeline description for z900. |
29a74354 UW |
596 | (include "2064.md") |
597 | ||
3443392a | 598 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
599 | (include "2084.md") |
600 | ||
9381e3f1 WG |
601 | ;; Pipeline description for z10 |
602 | (include "2097.md") | |
603 | ||
65b1d8ea AK |
604 | ;; Pipeline description for z196 |
605 | (include "2817.md") | |
606 | ||
22ac2c2f AK |
607 | ;; Pipeline description for zEC12 |
608 | (include "2827.md") | |
609 | ||
23902021 AK |
610 | ;; Pipeline description for z13 |
611 | (include "2964.md") | |
612 | ||
ff99338c RD |
613 | ;; Pipeline description for z14 |
614 | (include "3906.md") | |
615 | ||
375a6bc6 RD |
616 | ;; Pipeline description for arch13 |
617 | (include "8561.md") | |
618 | ||
0bfc3f69 AS |
619 | ;; Predicates |
620 | (include "predicates.md") | |
621 | ||
cd8dc1f9 WG |
622 | ;; Constraint definitions |
623 | (include "constraints.md") | |
624 | ||
a8ba31f2 EC |
625 | ;; Other includes |
626 | (include "tpf.md") | |
f52c81dd | 627 | |
3abcb3a7 | 628 | ;; Iterators |
f52c81dd | 629 | |
085261c8 AK |
630 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
631 | ||
3abcb3a7 | 632 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 633 | ;; same template. |
f4aa3848 | 634 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 635 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
636 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
637 | (define_mode_iterator BFP [TF DF SF]) | |
638 | (define_mode_iterator DFP [TD DD]) | |
639 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
640 | (define_mode_iterator DSF [DF SF]) | |
641 | (define_mode_iterator SD_SF [SF SD]) | |
642 | (define_mode_iterator DD_DF [DF DD]) | |
643 | (define_mode_iterator TD_TF [TF TD]) | |
644 | ||
026bfe89 AK |
645 | ; 32 bit int<->fp conversion instructions are available since VXE2 (arch13). |
646 | (define_mode_iterator VX_CONV_BFP [DF (SF "TARGET_VXE2")]) | |
647 | (define_mode_iterator VX_CONV_INT [DI (SI "TARGET_VXE2")]) | |
648 | ||
3abcb3a7 | 649 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 650 | ;; from the same template. |
9602b6a1 | 651 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 652 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 653 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 654 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 655 | |
3abcb3a7 | 656 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 657 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 658 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 659 | |
78ce265b RH |
660 | ;; These macros refer to the actual word_mode of the configuration. |
661 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
662 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
663 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
664 | ||
6e0d70c9 AK |
665 | ;; Used by the umul pattern to express modes having half the size. |
666 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
667 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
668 | ||
3abcb3a7 | 669 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 670 | ;; the same template. |
3abcb3a7 | 671 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 672 | |
3abcb3a7 | 673 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 674 | ;; same template. |
9602b6a1 | 675 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 676 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 677 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 678 | |
3abcb3a7 | 679 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 680 | ;; the same template. |
3abcb3a7 | 681 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 682 | |
d12a76f3 | 683 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
684 | (define_code_iterator IXOR [ior xor]) |
685 | ||
4a9733f3 AK |
686 | ;; This is used for merging the nand/nor and and/or with complement patterns |
687 | (define_code_iterator ANDOR [and ior]) | |
688 | (define_code_attr bitops_name [(and "and") (ior "or")]) | |
689 | (define_code_attr inv_bitops_name [(and "or") (ior "and")]) | |
690 | (define_code_attr inv_no [(and "o") (ior "n")]) | |
691 | ||
d12a76f3 AK |
692 | ;; This iterator is used to expand the patterns for the nearest |
693 | ;; integer functions. | |
694 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
695 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
696 | UNSPEC_FPINT_NEARBYINT]) | |
697 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
698 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
699 | (UNSPEC_FPINT_ROUND "round") | |
700 | (UNSPEC_FPINT_CEIL "ceil") | |
701 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
702 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
703 | (UNSPEC_FPINT_BTRUNC "5") | |
704 | (UNSPEC_FPINT_ROUND "1") | |
705 | (UNSPEC_FPINT_CEIL "6") | |
706 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
707 | ||
3abcb3a7 HPN |
708 | ;; This iterator and attribute allow to combine most atomic operations. |
709 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 710 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 711 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 712 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 713 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 714 | |
f4aa3848 | 715 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 | 716 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
4156b056 | 717 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e") (V4SF "e") (V2DF "d")]) |
f337b930 | 718 | |
f4aa3848 AK |
719 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
720 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
721 | ;; SDmode. |
722 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 723 | |
609e7e80 | 724 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
725 | ;; Likewise for "<RXe>". |
726 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
727 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
728 | ||
609e7e80 | 729 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 730 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
731 | ;; dfp variants in a single insn definition. |
732 | ||
62d3f261 AK |
733 | ;; These mode attributes are supposed to be used in the `enabled' insn |
734 | ;; attribute to disable certain alternatives for certain modes. | |
735 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
736 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
737 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
738 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
739 | (TD "0") (DD "0") (DD "0") | |
740 | (TI "0") (DI "*") (SI "0")]) | |
026bfe89 AK |
741 | (define_mode_attr SFSI [(TF "0") (DF "0") (SF "*") |
742 | (TD "0") (DD "0") (DD "0") | |
743 | (TI "0") (DI "0") (SI "*")]) | |
2de2b3f9 AK |
744 | (define_mode_attr DF [(TF "0") (DF "*") (SF "0") |
745 | (TD "0") (DD "0") (DD "0") | |
746 | (TI "0") (DI "0") (SI "0")]) | |
747 | (define_mode_attr SF [(TF "0") (DF "0") (SF "*") | |
748 | (TD "0") (DD "0") (DD "0") | |
749 | (TI "0") (DI "0") (SI "0")]) | |
f5905b37 | 750 | |
85dae55a AK |
751 | ;; This attribute is used in the operand constraint list |
752 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
753 | ;; TFmode values are represented by a fp register pair. Since the | |
754 | ;; sign bit instructions only handle single source and target fp registers | |
755 | ;; these instructions can only be used for TFmode values if the source and | |
756 | ;; target operand uses the same fp register. | |
757 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
758 | ||
3abcb3a7 | 759 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
760 | ;; within instruction mnemonics. |
761 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
762 | ||
0387c142 WG |
763 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
764 | ;; modes and to an empty string for bfp modes. | |
765 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
766 | ||
1b48c8cc AS |
767 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
768 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
769 | ;; version only operates on one register. | |
770 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
771 | ||
772 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
773 | ;; version only operates on one register. The DImode version needs an additional | |
774 | ;; register for the assembler output. | |
775 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
776 | |
777 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
778 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
779 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
780 | ||
781 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 782 | ;; pattern itself and the corresponding function calls. |
f337b930 | 783 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
784 | |
785 | ;; This attribute handles differences in the instruction 'type' and will result | |
786 | ;; in "RRE" for DImode and "RR" for SImode. | |
787 | (define_mode_attr E [(DI "E") (SI "")]) | |
788 | ||
3298c037 AK |
789 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
790 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
791 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
792 | ||
8006eaa6 AS |
793 | ;; This attribute handles differences in the instruction 'type' and will result |
794 | ;; in "RSE" for TImode and "RS" for DImode. | |
795 | (define_mode_attr TE [(TI "E") (DI "")]) | |
796 | ||
9a91a21f AS |
797 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
798 | ;; and "lcr" in SImode. | |
799 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 800 | |
3298c037 AK |
801 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
802 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
803 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
804 | ;; variant for long displacements. | |
805 | (define_mode_attr y [(DI "g") (SI "y")]) | |
806 | ||
9602b6a1 | 807 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
808 | ;; and "cds" in DImode. |
809 | (define_mode_attr tg [(TI "g") (DI "")]) | |
810 | ||
78ce265b RH |
811 | ;; In TDI templates, a string like "c<d>sg". |
812 | (define_mode_attr td [(TI "d") (DI "")]) | |
813 | ||
2f8f8434 AS |
814 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
815 | ;; and "cfdbr" in SImode. | |
816 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
817 | ||
65b1d8ea AK |
818 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
819 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
820 | ;; 3 operands shift instructions into the existing patterns. | |
821 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
822 | ||
f52c81dd AS |
823 | ;; ICM mask required to load MODE value into the lowest subreg |
824 | ;; of a SImode register. | |
825 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
826 | ||
f6ee577c AS |
827 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
828 | ;; HImode and "llgc" in QImode. | |
829 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
830 | ||
a1aed706 AS |
831 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
832 | ;; in SImode. | |
833 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
834 | ||
609e7e80 AK |
835 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
836 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
837 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
838 | ||
f52c81dd AS |
839 | ;; Maximum unsigned integer that fits in MODE. |
840 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
841 | ||
75ca1b39 RH |
842 | ;; Start and end field computations for RISBG et al. |
843 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
844 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
845 | ||
2542ef05 RH |
846 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
847 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
848 | ;; 64 - bitsize |
849 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
850 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 851 | |
da0dcab1 DV |
852 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
853 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
854 | ||
177bc204 RS |
855 | ;; Allow return and simple_return to be defined from a single template. |
856 | (define_code_iterator ANY_RETURN [return simple_return]) | |
857 | ||
6e5b5de8 AK |
858 | |
859 | ||
860 | ; Condition code modes generated by vector fp comparisons. These will | |
861 | ; be used also in single element mode. | |
862 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
863 | ; Used with VFCMP to expand part of the mnemonic | |
864 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
865 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 866 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 867 | |
191eb16d AK |
868 | ;; Subst pattern definitions |
869 | (include "subst.md") | |
6e5b5de8 | 870 | |
085261c8 AK |
871 | (include "vector.md") |
872 | ||
9db1d521 HP |
873 | ;; |
874 | ;;- Compare instructions. | |
875 | ;; | |
876 | ||
07893d4f | 877 | ; Test-under-Mask instructions |
9db1d521 | 878 | |
07893d4f | 879 | (define_insn "*tmqi_mem" |
ae156f85 | 880 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
881 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
882 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
883 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 884 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 885 | "@ |
fc0ea003 UW |
886 | tm\t%S0,%b1 |
887 | tmy\t%S0,%b1" | |
9381e3f1 | 888 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 889 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 890 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 891 | |
05b9aaaa | 892 | (define_insn "*tmdi_reg" |
ae156f85 | 893 | [(set (reg CC_REGNUM) |
f19a9af7 | 894 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 895 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
896 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
897 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 898 | "TARGET_ZARCH |
3ed99cc9 | 899 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
900 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
901 | "@ | |
902 | tmhh\t%0,%i1 | |
903 | tmhl\t%0,%i1 | |
904 | tmlh\t%0,%i1 | |
905 | tmll\t%0,%i1" | |
9381e3f1 WG |
906 | [(set_attr "op_type" "RI") |
907 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
908 | |
909 | (define_insn "*tmsi_reg" | |
ae156f85 | 910 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
911 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
912 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
913 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 914 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
915 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
916 | "@ | |
917 | tmh\t%0,%i1 | |
918 | tml\t%0,%i1" | |
729e750f WG |
919 | [(set_attr "op_type" "RI") |
920 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 921 | |
f52c81dd | 922 | (define_insn "*tm<mode>_full" |
ae156f85 | 923 | [(set (reg CC_REGNUM) |
f52c81dd AS |
924 | (compare (match_operand:HQI 0 "register_operand" "d") |
925 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 926 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 927 | "tml\t%0,<max_uint>" |
729e750f WG |
928 | [(set_attr "op_type" "RI") |
929 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 930 | |
07893d4f | 931 | |
08a5aaa2 | 932 | ; |
07893d4f | 933 | ; Load-and-Test instructions |
08a5aaa2 AS |
934 | ; |
935 | ||
c0220ea4 | 936 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
937 | |
938 | (define_insn "*tstdi_sign" | |
ae156f85 | 939 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
940 | (compare |
941 | (ashiftrt:DI | |
942 | (ashift:DI | |
3e4be43f | 943 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
944 | (const_int 32)) (const_int 32)) |
945 | (match_operand:DI 1 "const0_operand" ""))) | |
946 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 947 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 948 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
949 | "ltgfr\t%2,%0 |
950 | ltgf\t%2,%0" | |
951 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
952 | (set_attr "cpu_facility" "*,z10") |
953 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 954 | |
43a09b63 | 955 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 956 | (define_insn "*tst<mode>_extimm" |
ec24698e | 957 | [(set (reg CC_REGNUM) |
3e4be43f | 958 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
959 | (match_operand:GPR 1 "const0_operand" ""))) |
960 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 961 | (match_dup 0))] |
08a5aaa2 | 962 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 963 | "@ |
08a5aaa2 AS |
964 | lt<g>r\t%2,%0 |
965 | lt<g>\t%2,%0" | |
9381e3f1 | 966 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 967 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 968 | |
97160c9b DV |
969 | ; Peephole to combine a load-and-test from volatile memory which combine does |
970 | ; not do. | |
971 | (define_peephole2 | |
972 | [(set (match_operand:GPR 0 "register_operand") | |
973 | (match_operand:GPR 2 "memory_operand")) | |
974 | (set (reg CC_REGNUM) | |
975 | (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] | |
976 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM | |
977 | && GENERAL_REG_P (operands[0]) | |
34a249bc IL |
978 | && satisfies_constraint_T (operands[2]) |
979 | && !contains_constant_pool_address_p (operands[2])" | |
97160c9b DV |
980 | [(parallel |
981 | [(set (reg:CCS CC_REGNUM) | |
982 | (compare:CCS (match_dup 2) (match_dup 1))) | |
983 | (set (match_dup 0) (match_dup 2))])]) | |
984 | ||
43a09b63 | 985 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 986 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 987 | [(set (reg CC_REGNUM) |
3e4be43f | 988 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
989 | (match_operand:GPR 1 "const0_operand" ""))) |
990 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
991 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 992 | "@ |
08a5aaa2 AS |
993 | lt<g>r\t%0,%0 |
994 | lt<g>\t%2,%0" | |
9381e3f1 | 995 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 996 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 997 | |
07893d4f | 998 | (define_insn "*tstdi" |
ae156f85 | 999 | [(set (reg CC_REGNUM) |
07893d4f UW |
1000 | (compare (match_operand:DI 0 "register_operand" "d") |
1001 | (match_operand:DI 1 "const0_operand" ""))) | |
1002 | (set (match_operand:DI 2 "register_operand" "=d") | |
1003 | (match_dup 0))] | |
9602b6a1 | 1004 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 1005 | "ltgr\t%2,%0" |
9381e3f1 WG |
1006 | [(set_attr "op_type" "RRE") |
1007 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 1008 | |
07893d4f | 1009 | (define_insn "*tstsi" |
ae156f85 | 1010 | [(set (reg CC_REGNUM) |
d3632d41 | 1011 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 1012 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 1013 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 1014 | (match_dup 0))] |
ec24698e | 1015 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 1016 | "@ |
d40c829f | 1017 | ltr\t%2,%0 |
fc0ea003 UW |
1018 | icm\t%2,15,%S0 |
1019 | icmy\t%2,15,%S0" | |
9381e3f1 | 1020 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 1021 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 1022 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 1023 | |
07893d4f | 1024 | (define_insn "*tstsi_cconly" |
ae156f85 | 1025 | [(set (reg CC_REGNUM) |
d3632d41 | 1026 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 1027 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 1028 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
1029 | "s390_match_ccmode(insn, CCSmode)" |
1030 | "@ | |
d40c829f | 1031 | ltr\t%0,%0 |
fc0ea003 UW |
1032 | icm\t%2,15,%S0 |
1033 | icmy\t%2,15,%S0" | |
9381e3f1 | 1034 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 1035 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 1036 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 1037 | |
08a5aaa2 AS |
1038 | (define_insn "*tstdi_cconly_31" |
1039 | [(set (reg CC_REGNUM) | |
1040 | (compare (match_operand:DI 0 "register_operand" "d") | |
1041 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 1042 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
1043 | "srda\t%0,0" |
1044 | [(set_attr "op_type" "RS") | |
1045 | (set_attr "atype" "reg")]) | |
1046 | ||
43a09b63 | 1047 | ; ltr, ltgr |
08a5aaa2 | 1048 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 1049 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
1050 | (compare (match_operand:GPR 0 "register_operand" "d") |
1051 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 1052 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 1053 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
1054 | [(set_attr "op_type" "RR<E>") |
1055 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 1056 | |
c0220ea4 | 1057 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 1058 | |
f52c81dd | 1059 | (define_insn "*tst<mode>CCT" |
ae156f85 | 1060 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1061 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
1062 | (match_operand:HQI 1 "const0_operand" ""))) | |
1063 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
1064 | (match_dup 0))] |
1065 | "s390_match_ccmode(insn, CCTmode)" | |
1066 | "@ | |
f52c81dd AS |
1067 | icm\t%2,<icm_lo>,%S0 |
1068 | icmy\t%2,<icm_lo>,%S0 | |
1069 | tml\t%0,<max_uint>" | |
9381e3f1 | 1070 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1071 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1072 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
1073 | |
1074 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 1075 | [(set (reg CC_REGNUM) |
d3632d41 | 1076 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 1077 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 1078 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
1079 | "s390_match_ccmode(insn, CCTmode)" |
1080 | "@ | |
fc0ea003 UW |
1081 | icm\t%2,3,%S0 |
1082 | icmy\t%2,3,%S0 | |
d40c829f | 1083 | tml\t%0,65535" |
9381e3f1 | 1084 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1085 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1086 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 1087 | |
3af97654 | 1088 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1089 | [(set (reg CC_REGNUM) |
d3632d41 | 1090 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1091 | (match_operand:QI 1 "const0_operand" "")))] |
1092 | "s390_match_ccmode(insn, CCTmode)" | |
1093 | "@ | |
fc0ea003 UW |
1094 | cli\t%S0,0 |
1095 | cliy\t%S0,0 | |
d40c829f | 1096 | tml\t%0,255" |
9381e3f1 | 1097 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1098 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1099 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1100 | |
f52c81dd | 1101 | (define_insn "*tst<mode>" |
ae156f85 | 1102 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1103 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1104 | (match_operand:HQI 1 "const0_operand" ""))) | |
1105 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1106 | (match_dup 0))] |
1107 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1108 | "@ |
f52c81dd AS |
1109 | icm\t%2,<icm_lo>,%S0 |
1110 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1111 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1112 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1113 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1114 | |
f52c81dd | 1115 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1116 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1117 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1118 | (match_operand:HQI 1 "const0_operand" ""))) | |
1119 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1120 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1121 | "@ |
f52c81dd AS |
1122 | icm\t%2,<icm_lo>,%S0 |
1123 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1124 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1125 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1126 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1127 | |
9db1d521 | 1128 | |
575f7c2b UW |
1129 | ; Compare (equality) instructions |
1130 | ||
1131 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1132 | [(set (reg CC_REGNUM) |
ec24698e | 1133 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1134 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1135 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1136 | "@ |
1137 | cgr\t%0,%1 | |
f4f41b4e | 1138 | cghi\t%0,%h1 |
ec24698e | 1139 | cgfi\t%0,%1 |
575f7c2b | 1140 | cg\t%0,%1 |
19b63d8e | 1141 | #" |
9381e3f1 WG |
1142 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1143 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1144 | |
1145 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1146 | [(set (reg CC_REGNUM) |
ec24698e UW |
1147 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1148 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1149 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1150 | "@ |
1151 | cr\t%0,%1 | |
f4f41b4e | 1152 | chi\t%0,%h1 |
ec24698e | 1153 | cfi\t%0,%1 |
575f7c2b UW |
1154 | c\t%0,%1 |
1155 | cy\t%0,%1 | |
19b63d8e | 1156 | #" |
9381e3f1 | 1157 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1158 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1159 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1160 | |
07893d4f | 1161 | ; Compare (signed) instructions |
4023fb28 | 1162 | |
07893d4f | 1163 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1164 | [(set (reg CC_REGNUM) |
963fc8d0 | 1165 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1166 | "d,T,b")) |
963fc8d0 | 1167 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1168 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1169 | "@ |
d40c829f | 1170 | cgfr\t%0,%1 |
963fc8d0 AK |
1171 | cgf\t%0,%1 |
1172 | cgfrl\t%0,%1" | |
1173 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1174 | (set_attr "z10prop" "z10_c,*,*") |
14cfceb7 IL |
1175 | (set_attr "type" "*,*,larl") |
1176 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 | 1177 | |
9381e3f1 WG |
1178 | |
1179 | ||
07893d4f | 1180 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1181 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1182 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1183 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1184 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1185 | "@ |
d40c829f | 1186 | ch\t%0,%1 |
963fc8d0 AK |
1187 | chy\t%0,%1 |
1188 | chrl\t%0,%1" | |
1189 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1190 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea | 1191 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1192 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked") |
1193 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 AK |
1194 | |
1195 | (define_insn "*cmphi_ccs_z10" | |
1196 | [(set (reg CC_REGNUM) | |
1197 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1198 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1199 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1200 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1201 | [(set_attr "op_type" "SIL") |
1202 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1203 | |
1204 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1205 | [(set (reg CC_REGNUM) | |
3e4be43f | 1206 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1207 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1208 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1209 | "@ | |
1210 | cgh\t%0,%1 | |
1211 | cghrl\t%0,%1" | |
1212 | [(set_attr "op_type" "RXY,RIL") | |
14cfceb7 IL |
1213 | (set_attr "type" "*,larl") |
1214 | (set_attr "relative_long" "*,yes")]) | |
4023fb28 | 1215 | |
963fc8d0 | 1216 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1217 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1218 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1219 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1220 | "d,d,Q, d,d,d,d") | |
1221 | (match_operand:GPR 1 "general_operand" | |
1222 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1223 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1224 | "@ |
3298c037 AK |
1225 | c<g>r\t%0,%1 |
1226 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1227 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1228 | c<g>fi\t%0,%1 |
1229 | c<g>\t%0,%1 | |
963fc8d0 AK |
1230 | c<y>\t%0,%1 |
1231 | c<g>rl\t%0,%1" | |
1232 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1233 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 | 1234 | (set_attr "type" "*,*,*,*,*,*,larl") |
14cfceb7 IL |
1235 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super") |
1236 | (set_attr "relative_long" "*,*,*,*,*,*,yes")]) | |
c7453384 | 1237 | |
07893d4f UW |
1238 | |
1239 | ; Compare (unsigned) instructions | |
9db1d521 | 1240 | |
963fc8d0 AK |
1241 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1242 | [(set (reg CC_REGNUM) | |
1243 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1244 | "larl_operand" "X"))) | |
1245 | (match_operand:SI 0 "register_operand" "d")))] | |
1246 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1247 | "clhrl\t%0,%1" | |
1248 | [(set_attr "op_type" "RIL") | |
729e750f | 1249 | (set_attr "type" "larl") |
14cfceb7 IL |
1250 | (set_attr "z10prop" "z10_super") |
1251 | (set_attr "relative_long" "yes")]) | |
963fc8d0 AK |
1252 | |
1253 | ; clhrl, clghrl | |
1254 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1255 | [(set (reg CC_REGNUM) | |
1256 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1257 | "larl_operand" "X"))) | |
1258 | (match_operand:GPR 0 "register_operand" "d")))] | |
1259 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1260 | "cl<g>hrl\t%0,%1" | |
1261 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1262 | (set_attr "type" "larl") |
14cfceb7 IL |
1263 | (set_attr "z10prop" "z10_super") |
1264 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 1265 | |
07893d4f | 1266 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1267 | [(set (reg CC_REGNUM) |
963fc8d0 | 1268 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1269 | "d,T,b")) |
1270 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1271 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1272 | "@ |
d40c829f | 1273 | clgfr\t%0,%1 |
963fc8d0 AK |
1274 | clgf\t%0,%1 |
1275 | clgfrl\t%0,%1" | |
1276 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1277 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 | 1278 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1279 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super") |
1280 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 1281 | |
07893d4f | 1282 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1283 | [(set (reg CC_REGNUM) |
963fc8d0 | 1284 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1285 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1286 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1287 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1288 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1289 | "@ |
d40c829f | 1290 | clgr\t%0,%1 |
ec24698e | 1291 | clgfi\t%0,%1 |
963fc8d0 AK |
1292 | clgrl\t%0,%1 |
1293 | clghsi\t%0,%x1 | |
575f7c2b | 1294 | clg\t%0,%1 |
e221ef54 | 1295 | # |
19b63d8e | 1296 | #" |
963fc8d0 AK |
1297 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1298 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 | 1299 | (set_attr "type" "*,*,larl,*,*,*,*") |
14cfceb7 IL |
1300 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*") |
1301 | (set_attr "relative_long" "*,*,yes,*,*,*,*")]) | |
9db1d521 | 1302 | |
07893d4f | 1303 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1304 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1305 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1306 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1307 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1308 | "@ |
d40c829f | 1309 | clr\t%0,%1 |
ec24698e | 1310 | clfi\t%0,%o1 |
963fc8d0 AK |
1311 | clrl\t%0,%1 |
1312 | clfhsi\t%0,%x1 | |
d40c829f | 1313 | cl\t%0,%1 |
575f7c2b | 1314 | cly\t%0,%1 |
e221ef54 | 1315 | # |
19b63d8e | 1316 | #" |
963fc8d0 | 1317 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1318 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 | 1319 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
14cfceb7 IL |
1320 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*") |
1321 | (set_attr "relative_long" "*,*,yes,*,*,*,*,*")]) | |
9db1d521 | 1322 | |
07893d4f | 1323 | (define_insn "*cmphi_ccu" |
ae156f85 | 1324 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1325 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1326 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1327 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1328 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1329 | "@ |
fc0ea003 UW |
1330 | clm\t%0,3,%S1 |
1331 | clmy\t%0,3,%S1 | |
963fc8d0 | 1332 | clhhsi\t%0,%1 |
e221ef54 | 1333 | # |
19b63d8e | 1334 | #" |
963fc8d0 | 1335 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1336 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1337 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1338 | |
1339 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1340 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1341 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1342 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1343 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1344 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1345 | "@ |
fc0ea003 UW |
1346 | clm\t%0,1,%S1 |
1347 | clmy\t%0,1,%S1 | |
1348 | cli\t%S0,%b1 | |
1349 | cliy\t%S0,%b1 | |
e221ef54 | 1350 | # |
19b63d8e | 1351 | #" |
9381e3f1 | 1352 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1353 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1354 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1355 | |
1356 | ||
19b63d8e UW |
1357 | ; Block compare (CLC) instruction patterns. |
1358 | ||
1359 | (define_insn "*clc" | |
ae156f85 | 1360 | [(set (reg CC_REGNUM) |
d4f52f0e | 1361 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1362 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1363 | (use (match_operand 2 "const_int_operand" "n"))] | |
1364 | "s390_match_ccmode (insn, CCUmode) | |
1365 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1366 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1367 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1368 | |
1369 | (define_split | |
ae156f85 | 1370 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1371 | (compare (match_operand 0 "memory_operand" "") |
1372 | (match_operand 1 "memory_operand" "")))] | |
1373 | "reload_completed | |
1374 | && s390_match_ccmode (insn, CCUmode) | |
1375 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1376 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1377 | [(parallel | |
1378 | [(set (match_dup 0) (match_dup 1)) | |
1379 | (use (match_dup 2))])] | |
1380 | { | |
1381 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1382 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1383 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1384 | ||
1385 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1386 | operands[0], operands[1]); | |
1387 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1388 | }) | |
1389 | ||
1390 | ||
609e7e80 | 1391 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1392 | |
e325aba2 | 1393 | |
64c8e85a | 1394 | ; FIXME: load and test instructions turn SNaN into QNaN what is not |
e325aba2 AK |
1395 | ; acceptable if the target will be used afterwards. On the other hand |
1396 | ; they are quite convenient for implementing comparisons with 0.0. So | |
64c8e85a AK |
1397 | ; try to enable them via splitter/peephole if the value isn't needed anymore. |
1398 | ; See testcases: load-and-test-fp-1.c and load-and-test-fp-2.c | |
e325aba2 | 1399 | |
609e7e80 | 1400 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1401 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1402 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1403 | (compare (match_operand:FP 0 "register_operand" "f") |
1404 | (match_operand:FP 1 "const0_operand" ""))) | |
1405 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1406 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1407 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1408 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1409 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1410 | |
2de2b3f9 AK |
1411 | ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb |
1412 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb | |
f5905b37 | 1413 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1414 | [(set (reg CC_REGNUM) |
2de2b3f9 AK |
1415 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") |
1416 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
142cd70f | 1417 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1418 | "@ |
609e7e80 | 1419 | c<xde><bt>r\t%0,%1 |
77c585ca | 1420 | c<xde>b\t%0,%1 |
2de2b3f9 AK |
1421 | wfcdb\t%0,%1 |
1422 | wfcsb\t%0,%1" | |
1423 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1424 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1425 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
963fc8d0 AK |
1426 | |
1427 | ; Compare and Branch instructions | |
1428 | ||
1429 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1430 | ; The following instructions do a complementary access of their second |
1431 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1432 | (define_insn "*cmp_and_br_signed_<mode>" |
1433 | [(set (pc) | |
1434 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1435 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1436 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1437 | (label_ref (match_operand 3 "" "")) | |
1438 | (pc))) | |
1439 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1440 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1441 | { |
1442 | if (get_attr_length (insn) == 6) | |
1443 | return which_alternative ? | |
1444 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1445 | else | |
1446 | return which_alternative ? | |
1447 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1448 | } | |
1449 | [(set_attr "op_type" "RIE") | |
1450 | (set_attr "type" "branch") | |
e3cba5e5 | 1451 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1452 | (set (attr "length") |
1453 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1454 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1455 | ; 10 byte for cgr/jg | |
1456 | ||
1457 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1458 | ; The following instructions do a complementary access of their second |
1459 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1460 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1461 | [(set (pc) | |
1462 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1463 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1464 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1465 | (label_ref (match_operand 3 "" "")) | |
1466 | (pc))) | |
1467 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1468 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1469 | { |
1470 | if (get_attr_length (insn) == 6) | |
1471 | return which_alternative ? | |
1472 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1473 | else | |
1474 | return which_alternative ? | |
1475 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1476 | } | |
1477 | [(set_attr "op_type" "RIE") | |
1478 | (set_attr "type" "branch") | |
e3cba5e5 | 1479 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1480 | (set (attr "length") |
1481 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1482 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1483 | ; 10 byte for clgr/jg | |
1484 | ||
b0f86a7e AK |
1485 | ; And now the same two patterns as above but with a negated CC mask. |
1486 | ||
1487 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1488 | ; The following instructions do a complementary access of their second | |
1489 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1490 | (define_insn "*icmp_and_br_signed_<mode>" | |
1491 | [(set (pc) | |
1492 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1493 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1494 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1495 | (pc) | |
1496 | (label_ref (match_operand 3 "" "")))) | |
1497 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1498 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1499 | { |
1500 | if (get_attr_length (insn) == 6) | |
1501 | return which_alternative ? | |
1502 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1503 | else | |
1504 | return which_alternative ? | |
1505 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1506 | } | |
1507 | [(set_attr "op_type" "RIE") | |
1508 | (set_attr "type" "branch") | |
1509 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1510 | (set (attr "length") | |
1511 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1512 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1513 | ; 10 byte for cgr/jg | |
1514 | ||
1515 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1516 | ; The following instructions do a complementary access of their second | |
1517 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1518 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1519 | [(set (pc) | |
1520 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1521 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1522 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1523 | (pc) | |
1524 | (label_ref (match_operand 3 "" "")))) | |
1525 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1526 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1527 | { |
1528 | if (get_attr_length (insn) == 6) | |
1529 | return which_alternative ? | |
1530 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1531 | else | |
1532 | return which_alternative ? | |
1533 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1534 | } | |
1535 | [(set_attr "op_type" "RIE") | |
1536 | (set_attr "type" "branch") | |
1537 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1538 | (set (attr "length") | |
1539 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1540 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1541 | ; 10 byte for clgr/jg | |
1542 | ||
9db1d521 HP |
1543 | ;; |
1544 | ;;- Move instructions. | |
1545 | ;; | |
1546 | ||
1547 | ; | |
1548 | ; movti instruction pattern(s). | |
1549 | ; | |
1550 | ||
3cb9ee2f AK |
1551 | |
1552 | ; Separate out the register pair alternative since constraints (P) are | |
1553 | ; not able to deal with const_wide_int's. But predicates do. | |
1554 | (define_insn "*movti_bigconst" | |
1555 | [(set (match_operand:TI 0 "register_operand" "=d") | |
1556 | (match_operand:TI 1 "reload_const_wide_int_operand" ""))] | |
1557 | "TARGET_ZARCH" | |
1558 | "#") | |
1559 | ||
085261c8 AK |
1560 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1561 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1562 | (define_insn "movti" |
9f3c21d6 AK |
1563 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R,d, d, d, d, d,o") |
1564 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))] | |
9602b6a1 | 1565 | "TARGET_ZARCH" |
4023fb28 | 1566 | "@ |
fc0ea003 UW |
1567 | lmg\t%0,%N0,%S1 |
1568 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1569 | vlr\t%v0,%v1 |
1570 | vzero\t%v0 | |
1571 | vone\t%v0 | |
1572 | vlvgp\t%v0,%1,%N1 | |
1573 | # | |
b8923037 AK |
1574 | vl\t%v0,%1%A1 |
1575 | vst\t%v1,%0%A0 | |
4023fb28 | 1576 | # |
9f3c21d6 AK |
1577 | # |
1578 | # | |
1579 | # | |
1580 | # | |
19b63d8e | 1581 | #" |
9f3c21d6 AK |
1582 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*,*,*,*,*") |
1583 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*,*,*,*,*") | |
1584 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*,*,extimm,*,*")]) | |
4023fb28 UW |
1585 | |
1586 | (define_split | |
1587 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1588 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1589 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1590 | && !s_operand (operands[0], TImode) |
1591 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1592 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1593 | [(set (match_dup 2) (match_dup 4)) |
1594 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1595 | { |
dc65c307 UW |
1596 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1597 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1598 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1599 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1600 | }) | |
1601 | ||
1602 | (define_split | |
1603 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1604 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1605 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1606 | && !s_operand (operands[0], TImode) |
1607 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1608 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1609 | [(set (match_dup 2) (match_dup 4)) | |
1610 | (set (match_dup 3) (match_dup 5))] | |
1611 | { | |
1612 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1613 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1614 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1615 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1616 | }) | |
4023fb28 | 1617 | |
085261c8 AK |
1618 | ; Use part of the TImode target reg to perform the address |
1619 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1620 | ; this splitter is not necessary. | |
4023fb28 UW |
1621 | (define_split |
1622 | [(set (match_operand:TI 0 "register_operand" "") | |
1623 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1624 | "TARGET_ZARCH && reload_completed |
085261c8 | 1625 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1626 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1627 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1628 | { |
1629 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1630 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1631 | s390_load_address (addr, XEXP (operands[1], 0)); |
1632 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1633 | }) |
1634 | ||
833cd70a | 1635 | |
085261c8 AK |
1636 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1637 | ; For the higher order bits we do simply a DImode move while the | |
1638 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1639 | (define_split | |
1640 | [(set (match_operand:TI 0 "register_operand" "") | |
1641 | (match_operand:TI 1 "register_operand" ""))] | |
1642 | "TARGET_VX && reload_completed | |
1643 | && GENERAL_REG_P (operands[0]) | |
1644 | && VECTOR_REG_P (operands[1])" | |
1645 | [(set (match_dup 2) (match_dup 4)) | |
1646 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1647 | UNSPEC_VEC_EXTRACT))] | |
1648 | { | |
1649 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1650 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1651 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1652 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1653 | }) | |
1654 | ||
833cd70a AK |
1655 | ; |
1656 | ; Patterns used for secondary reloads | |
1657 | ; | |
1658 | ||
963fc8d0 AK |
1659 | ; z10 provides move instructions accepting larl memory operands. |
1660 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1661 | ; These patterns are also used for unaligned SI and DI accesses. | |
1662 | ||
085261c8 AK |
1663 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1664 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1665 | (match_operand:ALL 1 "register_operand" "=d") | |
1666 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1667 | "TARGET_Z10" |
1668 | { | |
1669 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1670 | DONE; | |
1671 | }) | |
1672 | ||
085261c8 AK |
1673 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1674 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1675 | (match_operand:ALL 1 "memory_operand" "") | |
1676 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1677 | "TARGET_Z10" |
1678 | { | |
1679 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1680 | DONE; | |
1681 | }) | |
1682 | ||
1683 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1684 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1685 | (match_operand:P 1 "larl_operand" "") | |
1686 | (match_operand:P 2 "register_operand" "=a")])] | |
1687 | "TARGET_Z10" | |
1688 | { | |
1689 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1690 | DONE; | |
1691 | }) | |
1692 | ||
833cd70a AK |
1693 | ; Handles loading a PLUS (load address) expression |
1694 | ||
1695 | (define_expand "reload<mode>_plus" | |
1696 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1697 | (match_operand:P 1 "s390_plus_operand" "") | |
1698 | (match_operand:P 2 "register_operand" "=&a")])] | |
1699 | "" | |
1700 | { | |
1701 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1702 | DONE; | |
1703 | }) | |
1704 | ||
085261c8 AK |
1705 | ; Not all the indirect memory access instructions support the full |
1706 | ; format (long disp + index + base). So whenever a move from/to such | |
1707 | ; an address is required and the instruction cannot deal with it we do | |
1708 | ; a load address into a scratch register first and use this as the new | |
1709 | ; base register. | |
1710 | ; This in particular is used for: | |
1711 | ; - non-offsetable memory accesses for multiword moves | |
1712 | ; - full vector reg moves with long displacements | |
833cd70a | 1713 | |
085261c8 | 1714 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1715 | [(parallel [(match_operand 0 "register_operand" "") |
1716 | (match_operand 1 "" "") | |
1717 | (match_operand:P 2 "register_operand" "=&a")])] | |
1718 | "" | |
1719 | { | |
1720 | gcc_assert (MEM_P (operands[1])); | |
1721 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1722 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1723 | emit_move_insn (operands[0], operands[1]); | |
1724 | DONE; | |
1725 | }) | |
1726 | ||
085261c8 | 1727 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1728 | [(parallel [(match_operand 0 "" "") |
1729 | (match_operand 1 "register_operand" "") | |
1730 | (match_operand:P 2 "register_operand" "=&a")])] | |
1731 | "" | |
dc65c307 | 1732 | { |
9c3c3dcc | 1733 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1734 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1735 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1736 | emit_move_insn (operands[0], operands[1]); | |
1737 | DONE; | |
1738 | }) | |
9db1d521 | 1739 | |
1f9e1fc6 AK |
1740 | (define_expand "reload<mode>_PIC_addr" |
1741 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1742 | (match_operand 1 "larl_operand" "") | |
1743 | (match_operand:P 2 "register_operand" "=a")])] | |
1744 | "" | |
1745 | { | |
0a2aaacc KG |
1746 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1747 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1748 | }) |
1749 | ||
9db1d521 HP |
1750 | ; |
1751 | ; movdi instruction pattern(s). | |
1752 | ; | |
1753 | ||
9db1d521 HP |
1754 | (define_expand "movdi" |
1755 | [(set (match_operand:DI 0 "general_operand" "") | |
1756 | (match_operand:DI 1 "general_operand" ""))] | |
1757 | "" | |
9db1d521 | 1758 | { |
fd3cd001 | 1759 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1760 | if (TARGET_64BIT |
1761 | && (SYMBOLIC_CONST (operands[1]) | |
1762 | || (GET_CODE (operands[1]) == PLUS | |
1763 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1764 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1765 | emit_symbolic_move (operands); |
10bbf137 | 1766 | }) |
9db1d521 | 1767 | |
3af8e996 | 1768 | (define_insn "*movdi_64" |
85dae55a | 1769 | [(set (match_operand:DI 0 "nonimmediate_operand" |
b6f51755 | 1770 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d") |
85dae55a | 1771 | (match_operand:DI 1 "general_operand" |
b6f51755 | 1772 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))] |
9602b6a1 | 1773 | "TARGET_ZARCH" |
85dae55a AK |
1774 | "@ |
1775 | lghi\t%0,%h1 | |
1776 | llihh\t%0,%i1 | |
1777 | llihl\t%0,%i1 | |
1778 | llilh\t%0,%i1 | |
1779 | llill\t%0,%i1 | |
1780 | lgfi\t%0,%1 | |
1781 | llihf\t%0,%k1 | |
1782 | llilf\t%0,%k1 | |
1783 | ldgr\t%0,%1 | |
1784 | lgdr\t%0,%1 | |
1785 | lay\t%0,%a1 | |
963fc8d0 | 1786 | lgrl\t%0,%1 |
85dae55a AK |
1787 | lgr\t%0,%1 |
1788 | lg\t%0,%1 | |
1789 | stg\t%1,%0 | |
1790 | ldr\t%0,%1 | |
1791 | ld\t%0,%1 | |
1792 | ldy\t%0,%1 | |
1793 | std\t%1,%0 | |
1794 | stdy\t%1,%0 | |
963fc8d0 AK |
1795 | stgrl\t%1,%0 |
1796 | mvghi\t%0,%1 | |
85dae55a AK |
1797 | # |
1798 | # | |
1799 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1800 | lam\t%0,%N0,%S1 |
1801 | vleig\t%v0,%h1,0 | |
1802 | vlr\t%v0,%v1 | |
1803 | vlvgg\t%v0,%1,0 | |
1804 | vlgvg\t%0,%v1,0 | |
1805 | vleg\t%v0,%1,0 | |
b6f51755 IL |
1806 | vsteg\t%v1,%0,0 |
1807 | larl\t%0,%1" | |
963fc8d0 | 1808 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
b6f51755 IL |
1809 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS, |
1810 | VRX,VRX,RIL") | |
963fc8d0 | 1811 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 | 1812 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
b6f51755 | 1813 | *,*,*,*,*,*,*,larl") |
3af8e996 | 1814 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1815 | z10,*,*,*,*,*,longdisp,*,longdisp, |
b6f51755 | 1816 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx,*") |
9381e3f1 WG |
1817 | (set_attr "z10prop" "z10_fwd_A1, |
1818 | z10_fwd_E1, | |
1819 | z10_fwd_E1, | |
1820 | z10_fwd_E1, | |
1821 | z10_fwd_E1, | |
1822 | z10_fwd_A1, | |
1823 | z10_fwd_E1, | |
1824 | z10_fwd_E1, | |
1825 | *, | |
1826 | *, | |
1827 | z10_fwd_A1, | |
1828 | z10_fwd_A3, | |
1829 | z10_fr_E1, | |
1830 | z10_fwd_A3, | |
1831 | z10_rec, | |
1832 | *, | |
1833 | *, | |
1834 | *, | |
1835 | *, | |
1836 | *, | |
1837 | z10_rec, | |
1838 | z10_super, | |
1839 | *, | |
1840 | *, | |
1841 | *, | |
b6f51755 IL |
1842 | *,*,*,*,*,*,*, |
1843 | z10_super_A1") | |
14cfceb7 IL |
1844 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*, |
1845 | *,yes,*,*,*,*,*,*,*,*, | |
1846 | yes,*,*,*,*,*,*,*,*,*, | |
1847 | *,*,yes") | |
9381e3f1 | 1848 | ]) |
c5aa1d12 UW |
1849 | |
1850 | (define_split | |
1851 | [(set (match_operand:DI 0 "register_operand" "") | |
1852 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1853 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1854 | [(set (match_dup 2) (match_dup 3)) |
1855 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1856 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1857 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1858 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1859 | ||
1860 | (define_split | |
1861 | [(set (match_operand:DI 0 "register_operand" "") | |
1862 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1863 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1864 | && dead_or_set_p (insn, operands[1])" |
1865 | [(set (match_dup 3) (match_dup 2)) | |
1866 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1867 | (set (match_dup 4) (match_dup 2))] | |
1868 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1869 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1870 | ||
1871 | (define_split | |
1872 | [(set (match_operand:DI 0 "register_operand" "") | |
1873 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1874 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1875 | && !dead_or_set_p (insn, operands[1])" |
1876 | [(set (match_dup 3) (match_dup 2)) | |
1877 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1878 | (set (match_dup 4) (match_dup 2)) | |
1879 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1880 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1881 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1882 | |
1883 | (define_insn "*movdi_31" | |
963fc8d0 | 1884 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1885 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1886 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1887 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1888 | "!TARGET_ZARCH" |
4023fb28 | 1889 | "@ |
fc0ea003 | 1890 | lm\t%0,%N0,%S1 |
c4d50129 | 1891 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1892 | stm\t%1,%N1,%S0 |
c4d50129 | 1893 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1894 | # |
1895 | # | |
d40c829f UW |
1896 | ldr\t%0,%1 |
1897 | ld\t%0,%1 | |
1898 | ldy\t%0,%1 | |
1899 | std\t%1,%0 | |
1900 | stdy\t%1,%0 | |
19b63d8e | 1901 | #" |
f2dc2f86 AK |
1902 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1903 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1904 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1905 | |
1906 | ; For a load from a symbol ref we can use one of the target registers | |
1907 | ; together with larl to load the address. | |
1908 | (define_split | |
1909 | [(set (match_operand:DI 0 "register_operand" "") | |
1910 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1911 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1912 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1913 | [(set (match_dup 2) (match_dup 3)) | |
1914 | (set (match_dup 0) (match_dup 1))] | |
1915 | { | |
1916 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1917 | operands[3] = XEXP (operands[1], 0); | |
1918 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1919 | }) | |
4023fb28 UW |
1920 | |
1921 | (define_split | |
1922 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1923 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1924 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1925 | && !s_operand (operands[0], DImode) |
1926 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1927 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1928 | [(set (match_dup 2) (match_dup 4)) |
1929 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1930 | { |
dc65c307 UW |
1931 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1932 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1933 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1934 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1935 | }) | |
1936 | ||
1937 | (define_split | |
1938 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1939 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1940 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1941 | && !s_operand (operands[0], DImode) |
1942 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1943 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1944 | [(set (match_dup 2) (match_dup 4)) | |
1945 | (set (match_dup 3) (match_dup 5))] | |
1946 | { | |
1947 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1948 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1949 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1950 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1951 | }) | |
9db1d521 | 1952 | |
4023fb28 UW |
1953 | (define_split |
1954 | [(set (match_operand:DI 0 "register_operand" "") | |
1955 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1956 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1957 | && !FP_REG_P (operands[0]) |
4023fb28 | 1958 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1959 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1960 | { |
1961 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1962 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1963 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1964 | }) |
1965 | ||
84817c5d UW |
1966 | (define_peephole2 |
1967 | [(set (match_operand:DI 0 "register_operand" "") | |
1968 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1969 | "TARGET_ZARCH |
84817c5d UW |
1970 | && !FP_REG_P (operands[0]) |
1971 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1972 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1973 | && get_pool_mode (operands[1]) == DImode | |
1974 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1975 | [(set (match_dup 0) (match_dup 2))] | |
1976 | "operands[2] = get_pool_constant (operands[1]);") | |
1977 | ||
7bdff56f UW |
1978 | (define_insn "*la_64" |
1979 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1980 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1981 | "TARGET_64BIT" |
1982 | "@ | |
1983 | la\t%0,%a1 | |
1984 | lay\t%0,%a1" | |
1985 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1986 | (set_attr "type" "la") |
3e4be43f | 1987 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1988 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1989 | |
1990 | (define_peephole2 | |
1991 | [(parallel | |
1992 | [(set (match_operand:DI 0 "register_operand" "") | |
1993 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1994 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1995 | "TARGET_64BIT |
e1d5ee28 | 1996 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1997 | [(set (match_dup 0) (match_dup 1))] |
1998 | "") | |
1999 | ||
2000 | (define_peephole2 | |
2001 | [(set (match_operand:DI 0 "register_operand" "") | |
2002 | (match_operand:DI 1 "register_operand" "")) | |
2003 | (parallel | |
2004 | [(set (match_dup 0) | |
2005 | (plus:DI (match_dup 0) | |
2006 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2007 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2008 | "TARGET_64BIT |
2009 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2010 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2011 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
2012 | "") | |
2013 | ||
9db1d521 HP |
2014 | ; |
2015 | ; movsi instruction pattern(s). | |
2016 | ; | |
2017 | ||
9db1d521 HP |
2018 | (define_expand "movsi" |
2019 | [(set (match_operand:SI 0 "general_operand" "") | |
2020 | (match_operand:SI 1 "general_operand" ""))] | |
2021 | "" | |
9db1d521 | 2022 | { |
fd3cd001 | 2023 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
2024 | if (!TARGET_64BIT |
2025 | && (SYMBOLIC_CONST (operands[1]) | |
2026 | || (GET_CODE (operands[1]) == PLUS | |
2027 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
2028 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 2029 | emit_symbolic_move (operands); |
10bbf137 | 2030 | }) |
9db1d521 | 2031 | |
9e8327e3 UW |
2032 | (define_insn "*movsi_larl" |
2033 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2034 | (match_operand:SI 1 "larl_operand" "X"))] | |
8cc6307c | 2035 | "!TARGET_64BIT |
9e8327e3 UW |
2036 | && !FP_REG_P (operands[0])" |
2037 | "larl\t%0,%1" | |
2038 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 2039 | (set_attr "type" "larl") |
14cfceb7 IL |
2040 | (set_attr "z10prop" "z10_fwd_A1") |
2041 | (set_attr "relative_long" "yes")]) | |
9e8327e3 | 2042 | |
f19a9af7 | 2043 | (define_insn "*movsi_zarch" |
2f7e5a0d | 2044 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 2045 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 2046 | (match_operand:SI 1 "general_operand" |
3e4be43f | 2047 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 2048 | "TARGET_ZARCH" |
9db1d521 | 2049 | "@ |
f19a9af7 AK |
2050 | lhi\t%0,%h1 |
2051 | llilh\t%0,%i1 | |
2052 | llill\t%0,%i1 | |
ec24698e | 2053 | iilf\t%0,%o1 |
f19a9af7 | 2054 | lay\t%0,%a1 |
963fc8d0 | 2055 | lrl\t%0,%1 |
d40c829f UW |
2056 | lr\t%0,%1 |
2057 | l\t%0,%1 | |
2058 | ly\t%0,%1 | |
2059 | st\t%1,%0 | |
2060 | sty\t%1,%0 | |
ae1c6198 | 2061 | ldr\t%0,%1 |
d40c829f | 2062 | ler\t%0,%1 |
085261c8 | 2063 | lde\t%0,%1 |
d40c829f UW |
2064 | le\t%0,%1 |
2065 | ley\t%0,%1 | |
2066 | ste\t%1,%0 | |
2067 | stey\t%1,%0 | |
c5aa1d12 UW |
2068 | ear\t%0,%1 |
2069 | sar\t%0,%1 | |
2070 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
2071 | strl\t%1,%0 |
2072 | mvhi\t%0,%1 | |
085261c8 AK |
2073 | lam\t%0,%0,%S1 |
2074 | vleif\t%v0,%h1,0 | |
2075 | vlr\t%v0,%v1 | |
2076 | vlvgf\t%v0,%1,0 | |
2077 | vlgvf\t%0,%v1,0 | |
2078 | vlef\t%v0,%1,0 | |
2079 | vstef\t%v1,%0,0" | |
963fc8d0 | 2080 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 2081 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
2082 | (set_attr "type" "*, |
2083 | *, | |
2084 | *, | |
2085 | *, | |
2086 | la, | |
2087 | larl, | |
2088 | lr, | |
2089 | load, | |
2090 | load, | |
2091 | store, | |
2092 | store, | |
2093 | floadsf, | |
2094 | floadsf, | |
2095 | floadsf, | |
085261c8 AK |
2096 | floadsf, |
2097 | floadsf, | |
9381e3f1 WG |
2098 | fstoresf, |
2099 | fstoresf, | |
2100 | *, | |
2101 | *, | |
2102 | *, | |
2103 | larl, | |
2104 | *, | |
085261c8 | 2105 | *,*,*,*,*,*,*") |
963fc8d0 | 2106 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2107 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2108 | (set_attr "z10prop" "z10_fwd_A1, |
2109 | z10_fwd_E1, | |
2110 | z10_fwd_E1, | |
2111 | z10_fwd_A1, | |
2112 | z10_fwd_A1, | |
2113 | z10_fwd_A3, | |
2114 | z10_fr_E1, | |
2115 | z10_fwd_A3, | |
2116 | z10_fwd_A3, | |
729e750f | 2117 | z10_rec, |
9381e3f1 WG |
2118 | z10_rec, |
2119 | *, | |
2120 | *, | |
2121 | *, | |
2122 | *, | |
2123 | *, | |
085261c8 AK |
2124 | *, |
2125 | *, | |
9381e3f1 WG |
2126 | z10_super_E1, |
2127 | z10_super, | |
2128 | *, | |
2129 | z10_rec, | |
2130 | z10_super, | |
14cfceb7 IL |
2131 | *,*,*,*,*,*,*") |
2132 | (set_attr "relative_long" "*,*,*,*,*,yes,*,*,*,*, | |
2133 | *,*,*,*,*,*,*,*,*,*, | |
2134 | *,yes,*,*,*,*,*,*,*,*")]) | |
f19a9af7 AK |
2135 | |
2136 | (define_insn "*movsi_esa" | |
085261c8 AK |
2137 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2138 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2139 | "!TARGET_ZARCH" |
2140 | "@ | |
2141 | lhi\t%0,%h1 | |
2142 | lr\t%0,%1 | |
2143 | l\t%0,%1 | |
2144 | st\t%1,%0 | |
ae1c6198 | 2145 | ldr\t%0,%1 |
f19a9af7 | 2146 | ler\t%0,%1 |
085261c8 | 2147 | lde\t%0,%1 |
f19a9af7 AK |
2148 | le\t%0,%1 |
2149 | ste\t%1,%0 | |
c5aa1d12 UW |
2150 | ear\t%0,%1 |
2151 | sar\t%0,%1 | |
2152 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2153 | lam\t%0,%0,%S1" |
ae1c6198 | 2154 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2155 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2156 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2157 | z10_super,*,*") | |
285363a1 | 2158 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2159 | ]) |
9db1d521 | 2160 | |
84817c5d UW |
2161 | (define_peephole2 |
2162 | [(set (match_operand:SI 0 "register_operand" "") | |
2163 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2164 | "!FP_REG_P (operands[0]) | |
2165 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2166 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2167 | && get_pool_mode (operands[1]) == SImode | |
2168 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2169 | [(set (match_dup 0) (match_dup 2))] | |
2170 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2171 | |
7bdff56f UW |
2172 | (define_insn "*la_31" |
2173 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2174 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2175 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2176 | "@ | |
2177 | la\t%0,%a1 | |
2178 | lay\t%0,%a1" | |
2179 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2180 | (set_attr "type" "la") |
3e4be43f | 2181 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2182 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2183 | |
2184 | (define_peephole2 | |
2185 | [(parallel | |
2186 | [(set (match_operand:SI 0 "register_operand" "") | |
2187 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2188 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2189 | "!TARGET_64BIT |
e1d5ee28 | 2190 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2191 | [(set (match_dup 0) (match_dup 1))] |
2192 | "") | |
2193 | ||
2194 | (define_peephole2 | |
2195 | [(set (match_operand:SI 0 "register_operand" "") | |
2196 | (match_operand:SI 1 "register_operand" "")) | |
2197 | (parallel | |
2198 | [(set (match_dup 0) | |
2199 | (plus:SI (match_dup 0) | |
2200 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2201 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2202 | "!TARGET_64BIT |
2203 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2204 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2205 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2206 | "") | |
2207 | ||
2208 | (define_insn "*la_31_and" | |
2209 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2210 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2211 | (const_int 2147483647)))] |
2212 | "!TARGET_64BIT" | |
2213 | "@ | |
2214 | la\t%0,%a1 | |
2215 | lay\t%0,%a1" | |
2216 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2217 | (set_attr "type" "la") |
3e4be43f | 2218 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2219 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2220 | |
2221 | (define_insn_and_split "*la_31_and_cc" | |
2222 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2223 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2224 | (const_int 2147483647))) | |
ae156f85 | 2225 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2226 | "!TARGET_64BIT" |
2227 | "#" | |
2228 | "&& reload_completed" | |
2229 | [(set (match_dup 0) | |
2230 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2231 | "" | |
2232 | [(set_attr "op_type" "RX") | |
2233 | (set_attr "type" "la")]) | |
2234 | ||
2235 | (define_insn "force_la_31" | |
2236 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2237 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2238 | (use (const_int 0))] |
2239 | "!TARGET_64BIT" | |
2240 | "@ | |
2241 | la\t%0,%a1 | |
2242 | lay\t%0,%a1" | |
2243 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2244 | (set_attr "type" "la") |
3e4be43f | 2245 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2246 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2247 | |
9db1d521 HP |
2248 | ; |
2249 | ; movhi instruction pattern(s). | |
2250 | ; | |
2251 | ||
02ed3c5e UW |
2252 | (define_expand "movhi" |
2253 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2254 | (match_operand:HI 1 "general_operand" ""))] | |
2255 | "" | |
2256 | { | |
2f7e5a0d | 2257 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2258 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2259 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2260 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2261 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2262 | { |
2263 | rtx tmp = gen_reg_rtx (SImode); | |
2264 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2265 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2266 | operands[1] = gen_lowpart (HImode, tmp); |
2267 | } | |
2268 | }) | |
2269 | ||
2270 | (define_insn "*movhi" | |
3e4be43f UW |
2271 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2272 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2273 | "" |
2274 | "@ | |
d40c829f UW |
2275 | lr\t%0,%1 |
2276 | lhi\t%0,%h1 | |
2277 | lh\t%0,%1 | |
2278 | lhy\t%0,%1 | |
963fc8d0 | 2279 | lhrl\t%0,%1 |
d40c829f UW |
2280 | sth\t%1,%0 |
2281 | sthy\t%1,%0 | |
963fc8d0 | 2282 | sthrl\t%1,%0 |
085261c8 AK |
2283 | mvhhi\t%0,%1 |
2284 | vleih\t%v0,%h1,0 | |
2285 | vlr\t%v0,%v1 | |
2286 | vlvgh\t%v0,%1,0 | |
2287 | vlgvh\t%0,%v1,0 | |
2288 | vleh\t%v0,%1,0 | |
2289 | vsteh\t%v1,%0,0" | |
2290 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2291 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2292 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2293 | (set_attr "z10prop" "z10_fr_E1, |
2294 | z10_fwd_A1, | |
2295 | z10_super_E1, | |
2296 | z10_super_E1, | |
2297 | z10_super_E1, | |
729e750f | 2298 | z10_rec, |
9381e3f1 WG |
2299 | z10_rec, |
2300 | z10_rec, | |
14cfceb7 IL |
2301 | z10_super,*,*,*,*,*,*") |
2302 | (set_attr "relative_long" "*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*")]) | |
9db1d521 | 2303 | |
84817c5d UW |
2304 | (define_peephole2 |
2305 | [(set (match_operand:HI 0 "register_operand" "") | |
2306 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2307 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2308 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2309 | && get_pool_mode (operands[1]) == HImode | |
2310 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2311 | [(set (match_dup 0) (match_dup 2))] | |
2312 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2313 | |
9db1d521 HP |
2314 | ; |
2315 | ; movqi instruction pattern(s). | |
2316 | ; | |
2317 | ||
02ed3c5e UW |
2318 | (define_expand "movqi" |
2319 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2320 | (match_operand:QI 1 "general_operand" ""))] | |
2321 | "" | |
2322 | { | |
c19ec8f9 | 2323 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2324 | is just as fast as a QImode load. */ |
b3a13419 | 2325 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2326 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2327 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2328 | { |
9602b6a1 AK |
2329 | rtx tmp = gen_reg_rtx (DImode); |
2330 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2331 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2332 | operands[1] = gen_lowpart (QImode, tmp); |
2333 | } | |
2334 | }) | |
4023fb28 | 2335 | |
02ed3c5e | 2336 | (define_insn "*movqi" |
3e4be43f UW |
2337 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2338 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2339 | "" |
2340 | "@ | |
d40c829f UW |
2341 | lr\t%0,%1 |
2342 | lhi\t%0,%b1 | |
2343 | ic\t%0,%1 | |
2344 | icy\t%0,%1 | |
2345 | stc\t%1,%0 | |
2346 | stcy\t%1,%0 | |
fc0ea003 | 2347 | mvi\t%S0,%b1 |
0a88561f | 2348 | mviy\t%S0,%b1 |
085261c8 AK |
2349 | # |
2350 | vleib\t%v0,%b1,0 | |
2351 | vlr\t%v0,%v1 | |
2352 | vlvgb\t%v0,%1,0 | |
2353 | vlgvb\t%0,%v1,0 | |
2354 | vleb\t%v0,%1,0 | |
2355 | vsteb\t%v1,%0,0" | |
2356 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2357 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2358 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2359 | (set_attr "z10prop" "z10_fr_E1, |
2360 | z10_fwd_A1, | |
2361 | z10_super_E1, | |
2362 | z10_super_E1, | |
729e750f | 2363 | z10_rec, |
9381e3f1 WG |
2364 | z10_rec, |
2365 | z10_super, | |
0a88561f | 2366 | z10_super, |
085261c8 | 2367 | *,*,*,*,*,*,*")]) |
9db1d521 | 2368 | |
84817c5d UW |
2369 | (define_peephole2 |
2370 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2371 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2372 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2373 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2374 | && get_pool_mode (operands[1]) == QImode | |
2375 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2376 | [(set (match_dup 0) (match_dup 2))] | |
2377 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2378 | |
9db1d521 | 2379 | ; |
05b9aaaa | 2380 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2381 | ; |
2382 | ||
2383 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2384 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2385 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2386 | "" |
d3632d41 | 2387 | "@ |
d40c829f UW |
2388 | ic\t%0,%1 |
2389 | icy\t%0,%1" | |
9381e3f1 | 2390 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2391 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2392 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2393 | |
2394 | ; | |
2395 | ; movstricthi instruction pattern(s). | |
2396 | ; | |
2397 | ||
2398 | (define_insn "*movstricthi" | |
d3632d41 | 2399 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2400 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2401 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2402 | "" |
d3632d41 | 2403 | "@ |
fc0ea003 UW |
2404 | icm\t%0,3,%S1 |
2405 | icmy\t%0,3,%S1" | |
9381e3f1 | 2406 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2407 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2408 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2409 | |
2410 | ; | |
2411 | ; movstrictsi instruction pattern(s). | |
2412 | ; | |
2413 | ||
05b9aaaa | 2414 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2415 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2416 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2417 | "TARGET_ZARCH" |
9db1d521 | 2418 | "@ |
d40c829f UW |
2419 | lr\t%0,%1 |
2420 | l\t%0,%1 | |
c5aa1d12 UW |
2421 | ly\t%0,%1 |
2422 | ear\t%0,%1" | |
2423 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2424 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2425 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2426 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2427 | |
f61a2c7d | 2428 | ; |
609e7e80 | 2429 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2430 | ; |
2431 | ||
609e7e80 AK |
2432 | (define_expand "mov<mode>" |
2433 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2434 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2435 | "" |
2436 | "") | |
2437 | ||
609e7e80 | 2438 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2439 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2440 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2441 | "TARGET_ZARCH" |
f61a2c7d | 2442 | "@ |
65b1d8ea | 2443 | lzxr\t%0 |
f61a2c7d AK |
2444 | lxr\t%0,%1 |
2445 | # | |
2446 | # | |
2447 | lmg\t%0,%N0,%S1 | |
2448 | stmg\t%1,%N1,%S0 | |
2449 | # | |
f61a2c7d | 2450 | #" |
65b1d8ea AK |
2451 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2452 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2453 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2454 | |
609e7e80 | 2455 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2456 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2457 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2458 | "!TARGET_ZARCH" |
f61a2c7d | 2459 | "@ |
65b1d8ea | 2460 | lzxr\t%0 |
f61a2c7d AK |
2461 | lxr\t%0,%1 |
2462 | # | |
f61a2c7d | 2463 | #" |
65b1d8ea AK |
2464 | [(set_attr "op_type" "RRE,RRE,*,*") |
2465 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2466 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2467 | |
2468 | ; TFmode in GPRs splitters | |
2469 | ||
2470 | (define_split | |
609e7e80 AK |
2471 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2472 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2473 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2474 | && !s_operand (operands[0], <MODE>mode) |
2475 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2476 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2477 | [(set (match_dup 2) (match_dup 4)) |
2478 | (set (match_dup 3) (match_dup 5))] | |
2479 | { | |
609e7e80 AK |
2480 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2481 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2482 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2483 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2484 | }) |
2485 | ||
2486 | (define_split | |
609e7e80 AK |
2487 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2488 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2489 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2490 | && !s_operand (operands[0], <MODE>mode) |
2491 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2492 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2493 | [(set (match_dup 2) (match_dup 4)) |
2494 | (set (match_dup 3) (match_dup 5))] | |
2495 | { | |
609e7e80 AK |
2496 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2497 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2498 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2499 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2500 | }) |
2501 | ||
2502 | (define_split | |
609e7e80 AK |
2503 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2504 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2505 | "TARGET_ZARCH && reload_completed |
085261c8 | 2506 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2507 | && !s_operand (operands[1], VOIDmode)" |
2508 | [(set (match_dup 0) (match_dup 1))] | |
2509 | { | |
609e7e80 | 2510 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2511 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2512 | s390_load_address (addr, XEXP (operands[1], 0)); |
2513 | operands[1] = replace_equiv_address (operands[1], addr); | |
2514 | }) | |
2515 | ||
7b6baae1 | 2516 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2517 | |
2518 | (define_split | |
609e7e80 AK |
2519 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2520 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2521 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2522 | && FP_REG_P (operands[0])" |
2523 | [(set (match_dup 2) (match_dup 4)) | |
2524 | (set (match_dup 3) (match_dup 5))] | |
2525 | { | |
609e7e80 AK |
2526 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2527 | <MODE>mode, 0); | |
2528 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2529 | <MODE>mode, 8); | |
2530 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2531 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2532 | }) |
2533 | ||
2534 | (define_split | |
609e7e80 AK |
2535 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2536 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2537 | "reload_completed && offsettable_memref_p (operands[0]) |
2538 | && FP_REG_P (operands[1])" | |
2539 | [(set (match_dup 2) (match_dup 4)) | |
2540 | (set (match_dup 3) (match_dup 5))] | |
2541 | { | |
609e7e80 AK |
2542 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2543 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2544 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2545 | <MODE>mode, 0); | |
2546 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2547 | <MODE>mode, 8); | |
f61a2c7d AK |
2548 | }) |
2549 | ||
9db1d521 | 2550 | ; |
609e7e80 | 2551 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2552 | ; |
2553 | ||
609e7e80 AK |
2554 | (define_expand "mov<mode>" |
2555 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2556 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2557 | "" |
13c025c1 | 2558 | "") |
9db1d521 | 2559 | |
609e7e80 AK |
2560 | (define_insn "*mov<mode>_64dfp" |
2561 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2562 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2563 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2564 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2565 | "TARGET_DFP" |
85dae55a | 2566 | "@ |
65b1d8ea | 2567 | lzdr\t%0 |
85dae55a AK |
2568 | ldr\t%0,%1 |
2569 | ldgr\t%0,%1 | |
2570 | lgdr\t%0,%1 | |
2571 | ld\t%0,%1 | |
2572 | ldy\t%0,%1 | |
2573 | std\t%1,%0 | |
2574 | stdy\t%1,%0 | |
45e5214c | 2575 | lghi\t%0,0 |
85dae55a | 2576 | lgr\t%0,%1 |
085261c8 | 2577 | lgrl\t%0,%1 |
85dae55a | 2578 | lg\t%0,%1 |
085261c8 AK |
2579 | stgrl\t%1,%0 |
2580 | stg\t%1,%0 | |
2581 | vlr\t%v0,%v1 | |
590961cf | 2582 | vleig\t%v0,0,0 |
085261c8 AK |
2583 | vlvgg\t%v0,%1,0 |
2584 | vlgvg\t%0,%v1,0 | |
2585 | vleg\t%0,%1,0 | |
2586 | vsteg\t%1,%0,0" | |
590961cf | 2587 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2588 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2589 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2590 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2591 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx") |
2592 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,yes,*,*,*,*,*,*,*")]) | |
85dae55a | 2593 | |
609e7e80 | 2594 | (define_insn "*mov<mode>_64" |
590961cf AK |
2595 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2596 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2597 | "TARGET_ZARCH" |
9db1d521 | 2598 | "@ |
65b1d8ea | 2599 | lzdr\t%0 |
d40c829f UW |
2600 | ldr\t%0,%1 |
2601 | ld\t%0,%1 | |
2602 | ldy\t%0,%1 | |
2603 | std\t%1,%0 | |
2604 | stdy\t%1,%0 | |
45e5214c | 2605 | lghi\t%0,0 |
d40c829f | 2606 | lgr\t%0,%1 |
085261c8 | 2607 | lgrl\t%0,%1 |
d40c829f | 2608 | lg\t%0,%1 |
085261c8 | 2609 | stgrl\t%1,%0 |
590961cf AK |
2610 | stg\t%1,%0" |
2611 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2612 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2613 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2614 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
14cfceb7 IL |
2615 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*") |
2616 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")]) | |
609e7e80 AK |
2617 | |
2618 | (define_insn "*mov<mode>_31" | |
2619 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2620 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2621 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2622 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2623 | "!TARGET_ZARCH" |
9db1d521 | 2624 | "@ |
65b1d8ea | 2625 | lzdr\t%0 |
d40c829f UW |
2626 | ldr\t%0,%1 |
2627 | ld\t%0,%1 | |
2628 | ldy\t%0,%1 | |
2629 | std\t%1,%0 | |
2630 | stdy\t%1,%0 | |
fc0ea003 | 2631 | lm\t%0,%N0,%S1 |
c4d50129 | 2632 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2633 | stm\t%1,%N1,%S0 |
c4d50129 | 2634 | stmy\t%1,%N1,%S0 |
4023fb28 | 2635 | # |
19b63d8e | 2636 | #" |
65b1d8ea AK |
2637 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2638 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2639 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2640 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2641 | |
2642 | (define_split | |
609e7e80 AK |
2643 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2644 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2645 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2646 | && !s_operand (operands[0], <MODE>mode) |
2647 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2648 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2649 | [(set (match_dup 2) (match_dup 4)) |
2650 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2651 | { |
609e7e80 AK |
2652 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2653 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2654 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2655 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2656 | }) |
2657 | ||
2658 | (define_split | |
609e7e80 AK |
2659 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2660 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2661 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2662 | && !s_operand (operands[0], <MODE>mode) |
2663 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2664 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2665 | [(set (match_dup 2) (match_dup 4)) |
2666 | (set (match_dup 3) (match_dup 5))] | |
2667 | { | |
609e7e80 AK |
2668 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2669 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2670 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2671 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2672 | }) |
9db1d521 | 2673 | |
4023fb28 | 2674 | (define_split |
609e7e80 AK |
2675 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2676 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2677 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2678 | && !FP_REG_P (operands[0]) |
4023fb28 | 2679 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2680 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2681 | { |
609e7e80 | 2682 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2683 | s390_load_address (addr, XEXP (operands[1], 0)); |
2684 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2685 | }) |
2686 | ||
9db1d521 | 2687 | ; |
609e7e80 | 2688 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2689 | ; |
2690 | ||
609e7e80 AK |
2691 | (define_insn "mov<mode>" |
2692 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2693 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2694 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2695 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2696 | "" |
9db1d521 | 2697 | "@ |
65b1d8ea | 2698 | lzer\t%0 |
ae1c6198 | 2699 | ldr\t%0,%1 |
d40c829f | 2700 | ler\t%0,%1 |
085261c8 | 2701 | lde\t%0,%1 |
d40c829f UW |
2702 | le\t%0,%1 |
2703 | ley\t%0,%1 | |
2704 | ste\t%1,%0 | |
2705 | stey\t%1,%0 | |
45e5214c | 2706 | lhi\t%0,0 |
d40c829f | 2707 | lr\t%0,%1 |
085261c8 | 2708 | lrl\t%0,%1 |
d40c829f UW |
2709 | l\t%0,%1 |
2710 | ly\t%0,%1 | |
085261c8 | 2711 | strl\t%1,%0 |
d40c829f | 2712 | st\t%1,%0 |
085261c8 AK |
2713 | sty\t%1,%0 |
2714 | vlr\t%v0,%v1 | |
298f4647 | 2715 | vleif\t%v0,0,0 |
085261c8 AK |
2716 | vlvgf\t%v0,%1,0 |
2717 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2718 | vlef\t%0,%1,0 |
2719 | vstef\t%1,%0,0" | |
ae1c6198 | 2720 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2721 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2722 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2723 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2724 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx") |
2725 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2726 | |
9dc62c00 AK |
2727 | ; |
2728 | ; movcc instruction pattern | |
2729 | ; | |
2730 | ||
2731 | (define_insn "movcc" | |
2732 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2733 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2734 | "" |
2735 | "@ | |
2736 | lr\t%0,%1 | |
2737 | tmh\t%1,12288 | |
2738 | ipm\t%0 | |
a71f0749 DV |
2739 | l\t%0,%1 |
2740 | ly\t%0,%1 | |
2741 | st\t%1,%0 | |
2742 | sty\t%1,%0" | |
8dd3b235 | 2743 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2744 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2745 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2746 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2747 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2748 | |
19b63d8e UW |
2749 | ; |
2750 | ; Block move (MVC) patterns. | |
2751 | ; | |
2752 | ||
2753 | (define_insn "*mvc" | |
2754 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2755 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2756 | (use (match_operand 2 "const_int_operand" "n"))] | |
2757 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2758 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2759 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2760 | |
0a88561f AK |
2761 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2762 | ; order to have it implemented with mvc. | |
2763 | ||
2764 | (define_split | |
2765 | [(set (match_operand:QI 0 "memory_operand" "") | |
2766 | (match_operand:QI 1 "memory_operand" ""))] | |
2767 | "reload_completed" | |
2768 | [(parallel | |
2769 | [(set (match_dup 0) (match_dup 1)) | |
2770 | (use (const_int 1))])] | |
2771 | { | |
2772 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2773 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2774 | }) | |
2775 | ||
2776 | ||
19b63d8e UW |
2777 | (define_peephole2 |
2778 | [(parallel | |
2779 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2780 | (match_operand:BLK 1 "memory_operand" "")) | |
2781 | (use (match_operand 2 "const_int_operand" ""))]) | |
2782 | (parallel | |
2783 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2784 | (match_operand:BLK 4 "memory_operand" "")) | |
2785 | (use (match_operand 5 "const_int_operand" ""))])] | |
f9dcf14a AK |
2786 | "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) |
2787 | || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) | |
2788 | && s390_offset_p (operands[0], operands[3], operands[2]) | |
19b63d8e | 2789 | && s390_offset_p (operands[1], operands[4], operands[2]) |
9381e3f1 | 2790 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2791 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2792 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2793 | [(parallel | |
2794 | [(set (match_dup 6) (match_dup 7)) | |
2795 | (use (match_dup 8))])] | |
2796 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2797 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2798 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2799 | ||
f9dcf14a AK |
2800 | (define_peephole2 |
2801 | [(parallel | |
2802 | [(set (match_operand:BLK 0 "plus16_Q_operand" "") | |
2803 | (match_operand:BLK 1 "plus16_Q_operand" "")) | |
2804 | (use (match_operand 2 "const_int_operand" ""))])] | |
2805 | "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" | |
2806 | [(parallel | |
2807 | [(set (match_dup 0) (match_dup 1)) | |
2808 | (use (const_int 16))]) | |
2809 | (parallel | |
2810 | [(set (match_dup 3) (match_dup 4)) | |
2811 | (use (match_dup 5))])] | |
2812 | "operands[3] = change_address (operands[0], VOIDmode, | |
2813 | plus_constant (Pmode, XEXP (operands[0], 0), 16)); | |
2814 | operands[4] = change_address (operands[1], VOIDmode, | |
2815 | plus_constant (Pmode, XEXP (operands[1], 0), 16)); | |
2816 | operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") | |
2817 | ||
19b63d8e | 2818 | |
9db1d521 HP |
2819 | ; |
2820 | ; load_multiple pattern(s). | |
2821 | ; | |
22ea6b4f UW |
2822 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2823 | ; we currently support load_multiple/store_multiple only after reload. | |
2824 | ; | |
9db1d521 HP |
2825 | |
2826 | (define_expand "load_multiple" | |
2827 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2828 | (match_operand 1 "" "")) | |
2829 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2830 | "reload_completed" |
9db1d521 | 2831 | { |
ef4bddc2 | 2832 | machine_mode mode; |
9db1d521 HP |
2833 | int regno; |
2834 | int count; | |
2835 | rtx from; | |
4023fb28 | 2836 | int i, off; |
9db1d521 HP |
2837 | |
2838 | /* Support only loading a constant number of fixed-point registers from | |
2839 | memory and only bother with this if more than two */ | |
2840 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2841 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2842 | || INTVAL (operands[2]) > 16 |
2843 | || GET_CODE (operands[1]) != MEM | |
2844 | || GET_CODE (operands[0]) != REG | |
2845 | || REGNO (operands[0]) >= 16) | |
2846 | FAIL; | |
2847 | ||
2848 | count = INTVAL (operands[2]); | |
2849 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2850 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2851 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2852 | FAIL; |
9db1d521 HP |
2853 | |
2854 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2855 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2856 | { |
2857 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2858 | { | |
2859 | from = XEXP (operands[1], 0); | |
2860 | off = 0; | |
2861 | } | |
2862 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2863 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2864 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2865 | { | |
2866 | from = XEXP (XEXP (operands[1], 0), 0); | |
2867 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2868 | } | |
2869 | else | |
2870 | FAIL; | |
4023fb28 UW |
2871 | } |
2872 | else | |
2873 | { | |
2874 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2875 | off = 0; | |
2876 | } | |
9db1d521 HP |
2877 | |
2878 | for (i = 0; i < count; i++) | |
2879 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2880 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2881 | change_address (operands[1], mode, |
0a81f074 RS |
2882 | plus_constant (Pmode, from, |
2883 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2884 | }) |
9db1d521 HP |
2885 | |
2886 | (define_insn "*load_multiple_di" | |
2887 | [(match_parallel 0 "load_multiple_operation" | |
2888 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2889 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2890 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2891 | { |
2892 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2893 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2894 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2895 | } |
d3632d41 | 2896 | [(set_attr "op_type" "RSY") |
4023fb28 | 2897 | (set_attr "type" "lm")]) |
9db1d521 HP |
2898 | |
2899 | (define_insn "*load_multiple_si" | |
2900 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2901 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2902 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2903 | "reload_completed" |
9db1d521 HP |
2904 | { |
2905 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2906 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2907 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2908 | } |
d3632d41 | 2909 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2910 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2911 | (set_attr "type" "lm")]) |
9db1d521 HP |
2912 | |
2913 | ; | |
c7453384 | 2914 | ; store multiple pattern(s). |
9db1d521 HP |
2915 | ; |
2916 | ||
2917 | (define_expand "store_multiple" | |
2918 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2919 | (match_operand 1 "" "")) | |
2920 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2921 | "reload_completed" |
9db1d521 | 2922 | { |
ef4bddc2 | 2923 | machine_mode mode; |
9db1d521 HP |
2924 | int regno; |
2925 | int count; | |
2926 | rtx to; | |
4023fb28 | 2927 | int i, off; |
9db1d521 HP |
2928 | |
2929 | /* Support only storing a constant number of fixed-point registers to | |
2930 | memory and only bother with this if more than two. */ | |
2931 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2932 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2933 | || INTVAL (operands[2]) > 16 |
2934 | || GET_CODE (operands[0]) != MEM | |
2935 | || GET_CODE (operands[1]) != REG | |
2936 | || REGNO (operands[1]) >= 16) | |
2937 | FAIL; | |
2938 | ||
2939 | count = INTVAL (operands[2]); | |
2940 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2941 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2942 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2943 | FAIL; |
9db1d521 HP |
2944 | |
2945 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2946 | |
b3a13419 | 2947 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2948 | { |
2949 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2950 | { | |
2951 | to = XEXP (operands[0], 0); | |
2952 | off = 0; | |
2953 | } | |
2954 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2955 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2956 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2957 | { | |
2958 | to = XEXP (XEXP (operands[0], 0), 0); | |
2959 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2960 | } | |
2961 | else | |
2962 | FAIL; | |
4023fb28 | 2963 | } |
c7453384 | 2964 | else |
4023fb28 UW |
2965 | { |
2966 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2967 | off = 0; | |
2968 | } | |
9db1d521 HP |
2969 | |
2970 | for (i = 0; i < count; i++) | |
2971 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2972 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2973 | plus_constant (Pmode, to, |
2974 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2975 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2976 | }) |
9db1d521 HP |
2977 | |
2978 | (define_insn "*store_multiple_di" | |
2979 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2980 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2981 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2982 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2983 | { |
2984 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2985 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2986 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2987 | } |
d3632d41 | 2988 | [(set_attr "op_type" "RSY") |
4023fb28 | 2989 | (set_attr "type" "stm")]) |
9db1d521 HP |
2990 | |
2991 | ||
2992 | (define_insn "*store_multiple_si" | |
2993 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2994 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2995 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2996 | "reload_completed" |
9db1d521 HP |
2997 | { |
2998 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2999 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 3000 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 3001 | } |
d3632d41 | 3002 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3003 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 3004 | (set_attr "type" "stm")]) |
9db1d521 HP |
3005 | |
3006 | ;; | |
3007 | ;; String instructions. | |
3008 | ;; | |
3009 | ||
963fc8d0 | 3010 | (define_insn "*execute_rl" |
2771c2f9 | 3011 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
3012 | [(unspec [(match_operand 1 "register_operand" "a") |
3013 | (match_operand 2 "" "") | |
3014 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
3015 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
3016 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
3017 | "exrl\t%1,%3" | |
3018 | [(set_attr "op_type" "RIL") | |
14cfceb7 IL |
3019 | (set_attr "type" "cs") |
3020 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 3021 | |
9bb86f41 | 3022 | (define_insn "*execute" |
2771c2f9 | 3023 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
3024 | [(unspec [(match_operand 1 "register_operand" "a") |
3025 | (match_operand:BLK 2 "memory_operand" "R") | |
3026 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
3027 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
3028 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
3029 | "ex\t%1,%2" | |
29a74354 UW |
3030 | [(set_attr "op_type" "RX") |
3031 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
3032 | |
3033 | ||
91d39d71 UW |
3034 | ; |
3035 | ; strlenM instruction pattern(s). | |
3036 | ; | |
3037 | ||
9db2f16d | 3038 | (define_expand "strlen<mode>" |
085261c8 AK |
3039 | [(match_operand:P 0 "register_operand" "") ; result |
3040 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
3041 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
3042 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
3043 | "" | |
3044 | { | |
3045 | if (!TARGET_VX || operands[2] != const0_rtx) | |
3046 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
3047 | operands[2], operands[3])); | |
3048 | else | |
3049 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
3050 | ||
3051 | DONE; | |
3052 | }) | |
3053 | ||
3054 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 3055 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 3056 | (parallel |
91d39d71 | 3057 | [(set (match_dup 4) |
9db2f16d | 3058 | (unspec:P [(const_int 0) |
91d39d71 | 3059 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 3060 | (reg:SI 0) |
91d39d71 | 3061 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3062 | (clobber (scratch:P)) |
ae156f85 | 3063 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 3064 | (parallel |
9db2f16d AS |
3065 | [(set (match_operand:P 0 "register_operand" "") |
3066 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 3067 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 3068 | "" |
91d39d71 | 3069 | { |
9db2f16d AS |
3070 | operands[4] = gen_reg_rtx (Pmode); |
3071 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
3072 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3073 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
3074 | }) | |
3075 | ||
9db2f16d AS |
3076 | (define_insn "*strlen<mode>" |
3077 | [(set (match_operand:P 0 "register_operand" "=a") | |
3078 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
3079 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 3080 | (reg:SI 0) |
91d39d71 | 3081 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3082 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 3083 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 3084 | "" |
91d39d71 | 3085 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
3086 | [(set_attr "length" "8") |
3087 | (set_attr "type" "vs")]) | |
91d39d71 | 3088 | |
ccbdc0d4 AS |
3089 | ; |
3090 | ; cmpstrM instruction pattern(s). | |
3091 | ; | |
3092 | ||
3093 | (define_expand "cmpstrsi" | |
3094 | [(set (reg:SI 0) (const_int 0)) | |
3095 | (parallel | |
3096 | [(clobber (match_operand 3 "" "")) | |
3097 | (clobber (match_dup 4)) | |
3098 | (set (reg:CCU CC_REGNUM) | |
3099 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
3100 | (match_operand:BLK 2 "memory_operand" ""))) | |
3101 | (use (reg:SI 0))]) | |
3102 | (parallel | |
3103 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3104 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
3105 | (clobber (reg:CC CC_REGNUM))])] |
3106 | "" | |
3107 | { | |
3108 | /* As the result of CMPINT is inverted compared to what we need, | |
3109 | we have to swap the operands. */ | |
3110 | rtx op1 = operands[2]; | |
3111 | rtx op2 = operands[1]; | |
3112 | rtx addr1 = gen_reg_rtx (Pmode); | |
3113 | rtx addr2 = gen_reg_rtx (Pmode); | |
3114 | ||
3115 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
3116 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
3117 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
3118 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
3119 | operands[3] = addr1; | |
3120 | operands[4] = addr2; | |
3121 | }) | |
3122 | ||
3123 | (define_insn "*cmpstr<mode>" | |
3124 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3125 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3126 | (set (reg:CCU CC_REGNUM) | |
3127 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3128 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3129 | (use (reg:SI 0))] | |
3130 | "" | |
3131 | "clst\t%0,%1\;jo\t.-4" | |
3132 | [(set_attr "length" "8") | |
3133 | (set_attr "type" "vs")]) | |
9381e3f1 | 3134 | |
742090fc AS |
3135 | ; |
3136 | ; movstr instruction pattern. | |
3137 | ; | |
3138 | ||
3139 | (define_expand "movstr" | |
4a7dec25 DV |
3140 | [(match_operand 0 "register_operand" "") |
3141 | (match_operand 1 "memory_operand" "") | |
3142 | (match_operand 2 "memory_operand" "")] | |
3143 | "" | |
3144 | { | |
3145 | if (TARGET_64BIT) | |
3146 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3147 | else | |
3148 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3149 | DONE; | |
3150 | }) | |
3151 | ||
3152 | (define_expand "movstr<P:mode>" | |
742090fc | 3153 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3154 | (parallel |
742090fc AS |
3155 | [(clobber (match_dup 3)) |
3156 | (set (match_operand:BLK 1 "memory_operand" "") | |
3157 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3158 | (set (match_operand:P 0 "register_operand" "") |
3159 | (unspec:P [(match_dup 1) | |
742090fc AS |
3160 | (match_dup 2) |
3161 | (reg:SI 0)] UNSPEC_MVST)) | |
3162 | (clobber (reg:CC CC_REGNUM))])] | |
3163 | "" | |
3164 | { | |
859a4c0e AK |
3165 | rtx addr1, addr2; |
3166 | ||
3167 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3168 | { | |
3169 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3170 | DONE; | |
3171 | } | |
3172 | ||
3173 | addr1 = gen_reg_rtx (Pmode); | |
3174 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3175 | |
3176 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3177 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3178 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3179 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3180 | operands[3] = addr2; | |
3181 | }) | |
3182 | ||
3183 | (define_insn "*movstr" | |
3184 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3185 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3186 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3187 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3188 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3189 | (mem:BLK (match_dup 3)) |
3190 | (reg:SI 0)] UNSPEC_MVST)) | |
3191 | (clobber (reg:CC CC_REGNUM))] | |
3192 | "" | |
3193 | "mvst\t%1,%2\;jo\t.-4" | |
3194 | [(set_attr "length" "8") | |
3195 | (set_attr "type" "vs")]) | |
9381e3f1 | 3196 | |
742090fc | 3197 | |
9db1d521 | 3198 | ; |
76715c32 | 3199 | ; cpymemM instruction pattern(s). |
9db1d521 HP |
3200 | ; |
3201 | ||
76715c32 | 3202 | (define_expand "cpymem<mode>" |
963fc8d0 AK |
3203 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3204 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3205 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3206 | (match_operand 3 "" "")] |
3207 | "" | |
367d32f3 | 3208 | { |
76715c32 | 3209 | if (s390_expand_cpymem (operands[0], operands[1], operands[2])) |
367d32f3 AK |
3210 | DONE; |
3211 | else | |
3212 | FAIL; | |
3213 | }) | |
9db1d521 | 3214 | |
ecbe845e UW |
3215 | ; Move a block that is up to 256 bytes in length. |
3216 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3217 | |
76715c32 | 3218 | (define_expand "cpymem_short" |
b9404c99 UW |
3219 | [(parallel |
3220 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3221 | (match_operand:BLK 1 "memory_operand" "")) | |
3222 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3223 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3224 | (clobber (match_dup 3))])] |
3225 | "" | |
3226 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3227 | |
76715c32 | 3228 | (define_insn "*cpymem_short" |
963fc8d0 AK |
3229 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3230 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3231 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3232 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3233 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3234 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3235 | "#" |
963fc8d0 | 3236 | [(set_attr "type" "cs") |
b5e0425c | 3237 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3238 | |
9bb86f41 UW |
3239 | (define_split |
3240 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3241 | (match_operand:BLK 1 "memory_operand" "")) | |
3242 | (use (match_operand 2 "const_int_operand" "")) | |
3243 | (use (match_operand 3 "immediate_operand" "")) | |
3244 | (clobber (scratch))] | |
3245 | "reload_completed" | |
3246 | [(parallel | |
3247 | [(set (match_dup 0) (match_dup 1)) | |
3248 | (use (match_dup 2))])] | |
3249 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3250 | |
9bb86f41 UW |
3251 | (define_split |
3252 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3253 | (match_operand:BLK 1 "memory_operand" "")) | |
3254 | (use (match_operand 2 "register_operand" "")) | |
3255 | (use (match_operand 3 "memory_operand" "")) | |
3256 | (clobber (scratch))] | |
3257 | "reload_completed" | |
3258 | [(parallel | |
3259 | [(unspec [(match_dup 2) (match_dup 3) | |
3260 | (const_int 0)] UNSPEC_EXECUTE) | |
3261 | (set (match_dup 0) (match_dup 1)) | |
3262 | (use (const_int 1))])] | |
3263 | "") | |
3264 | ||
963fc8d0 AK |
3265 | (define_split |
3266 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3267 | (match_operand:BLK 1 "memory_operand" "")) | |
3268 | (use (match_operand 2 "register_operand" "")) | |
3269 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3270 | (clobber (scratch))] | |
3271 | "TARGET_Z10 && reload_completed" | |
3272 | [(parallel | |
3273 | [(unspec [(match_dup 2) (const_int 0) | |
3274 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3275 | (set (match_dup 0) (match_dup 1)) | |
3276 | (use (const_int 1))])] | |
3277 | "operands[3] = gen_label_rtx ();") | |
3278 | ||
9bb86f41 UW |
3279 | (define_split |
3280 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3281 | (match_operand:BLK 1 "memory_operand" "")) | |
3282 | (use (match_operand 2 "register_operand" "")) | |
3283 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3284 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3285 | "reload_completed" |
9bb86f41 UW |
3286 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3287 | (parallel | |
9381e3f1 | 3288 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3289 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3290 | (set (match_dup 0) (match_dup 1)) | |
3291 | (use (const_int 1))])] | |
3292 | "operands[4] = gen_label_rtx ();") | |
3293 | ||
a41c6c53 | 3294 | ; Move a block of arbitrary length. |
9db1d521 | 3295 | |
76715c32 | 3296 | (define_expand "cpymem_long" |
b9404c99 UW |
3297 | [(parallel |
3298 | [(clobber (match_dup 2)) | |
3299 | (clobber (match_dup 3)) | |
3300 | (set (match_operand:BLK 0 "memory_operand" "") | |
3301 | (match_operand:BLK 1 "memory_operand" "")) | |
3302 | (use (match_operand 2 "general_operand" "")) | |
3303 | (use (match_dup 3)) | |
ae156f85 | 3304 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3305 | "" |
3306 | { | |
ef4bddc2 RS |
3307 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3308 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3309 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3310 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3311 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3312 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3313 | rtx len0 = gen_lowpart (Pmode, reg0); |
3314 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3315 | ||
c41c1387 | 3316 | emit_clobber (reg0); |
b9404c99 UW |
3317 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3318 | emit_move_insn (len0, operands[2]); | |
3319 | ||
c41c1387 | 3320 | emit_clobber (reg1); |
b9404c99 UW |
3321 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3322 | emit_move_insn (len1, operands[2]); | |
3323 | ||
3324 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3325 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3326 | operands[2] = reg0; | |
3327 | operands[3] = reg1; | |
3328 | }) | |
3329 | ||
76715c32 | 3330 | (define_insn "*cpymem_long" |
a1aed706 AS |
3331 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
3332 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3333 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3334 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3335 | (use (match_dup 2)) |
3336 | (use (match_dup 3)) | |
ae156f85 | 3337 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3338 | "TARGET_64BIT || !TARGET_ZARCH" |
3339 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3340 | [(set_attr "length" "8") | |
3341 | (set_attr "type" "vs")]) | |
3342 | ||
76715c32 | 3343 | (define_insn "*cpymem_long_31z" |
9602b6a1 AK |
3344 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3345 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3346 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3347 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3348 | (use (match_dup 2)) | |
3349 | (use (match_dup 3)) | |
3350 | (clobber (reg:CC CC_REGNUM))] | |
3351 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3352 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3353 | [(set_attr "length" "8") |
3354 | (set_attr "type" "vs")]) | |
9db1d521 | 3355 | |
638e37c2 WG |
3356 | |
3357 | ; | |
3358 | ; Test data class. | |
3359 | ; | |
3360 | ||
0f67fa83 WG |
3361 | (define_expand "signbit<mode>2" |
3362 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3363 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3364 | (match_dup 2)] | |
0f67fa83 WG |
3365 | UNSPEC_TDC_INSN)) |
3366 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3367 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3368 | "TARGET_HARD_FLOAT" |
3369 | { | |
3370 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3371 | }) | |
3372 | ||
638e37c2 WG |
3373 | (define_expand "isinf<mode>2" |
3374 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3375 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3376 | (match_dup 2)] | |
638e37c2 WG |
3377 | UNSPEC_TDC_INSN)) |
3378 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3379 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3380 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3381 | { |
3382 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3383 | }) | |
3384 | ||
085261c8 AK |
3385 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3386 | ; instruction will be issued by reload. The constraint of operand 1 | |
3387 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3388 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3389 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3390 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3391 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3392 | UNSPEC_CC_TO_INT))] | |
3393 | "operands != NULL" | |
3394 | "#" | |
3395 | "reload_completed" | |
3396 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3397 | ||
638e37c2 WG |
3398 | ; This insn is used to generate all variants of the Test Data Class |
3399 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3400 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3401 | ; specifying the required test(s). |
638e37c2 | 3402 | ; |
be5de7a1 | 3403 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3404 | (define_insn "*TDC_insn_<mode>" |
3405 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3406 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3407 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3408 | "TARGET_HARD_FLOAT" |
0387c142 | 3409 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3410 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3411 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3412 | |
638e37c2 WG |
3413 | |
3414 | ||
9db1d521 | 3415 | ; |
57e84f18 | 3416 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3417 | ; |
3418 | ||
57e84f18 | 3419 | (define_expand "setmem<mode>" |
a41c6c53 | 3420 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3421 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3422 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3423 | (match_operand 3 "" "")] |
a41c6c53 | 3424 | "" |
6d057022 | 3425 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3426 | |
a41c6c53 | 3427 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3428 | ; The block length is taken as (operands[1] % 256) + 1. |
3429 | ||
70128ad9 | 3430 | (define_expand "clrmem_short" |
b9404c99 UW |
3431 | [(parallel |
3432 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3433 | (const_int 0)) | |
3434 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3435 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3436 | (clobber (match_dup 2)) |
ae156f85 | 3437 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3438 | "" |
3439 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3440 | |
70128ad9 | 3441 | (define_insn "*clrmem_short" |
963fc8d0 | 3442 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3443 | (const_int 0)) |
963fc8d0 AK |
3444 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3445 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3446 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3447 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3448 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3449 | "#" |
963fc8d0 | 3450 | [(set_attr "type" "cs") |
b5e0425c | 3451 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3452 | |
3453 | (define_split | |
3454 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3455 | (const_int 0)) | |
3456 | (use (match_operand 1 "const_int_operand" "")) | |
3457 | (use (match_operand 2 "immediate_operand" "")) | |
3458 | (clobber (scratch)) | |
ae156f85 | 3459 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3460 | "reload_completed" |
3461 | [(parallel | |
3462 | [(set (match_dup 0) (const_int 0)) | |
3463 | (use (match_dup 1)) | |
ae156f85 | 3464 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3465 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3466 | |
9bb86f41 UW |
3467 | (define_split |
3468 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3469 | (const_int 0)) | |
3470 | (use (match_operand 1 "register_operand" "")) | |
3471 | (use (match_operand 2 "memory_operand" "")) | |
3472 | (clobber (scratch)) | |
ae156f85 | 3473 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3474 | "reload_completed" |
3475 | [(parallel | |
3476 | [(unspec [(match_dup 1) (match_dup 2) | |
3477 | (const_int 0)] UNSPEC_EXECUTE) | |
3478 | (set (match_dup 0) (const_int 0)) | |
3479 | (use (const_int 1)) | |
ae156f85 | 3480 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3481 | "") |
9db1d521 | 3482 | |
963fc8d0 AK |
3483 | (define_split |
3484 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3485 | (const_int 0)) | |
3486 | (use (match_operand 1 "register_operand" "")) | |
3487 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3488 | (clobber (scratch)) | |
3489 | (clobber (reg:CC CC_REGNUM))] | |
3490 | "TARGET_Z10 && reload_completed" | |
3491 | [(parallel | |
3492 | [(unspec [(match_dup 1) (const_int 0) | |
3493 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3494 | (set (match_dup 0) (const_int 0)) | |
3495 | (use (const_int 1)) | |
3496 | (clobber (reg:CC CC_REGNUM))])] | |
3497 | "operands[3] = gen_label_rtx ();") | |
3498 | ||
9bb86f41 UW |
3499 | (define_split |
3500 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3501 | (const_int 0)) | |
3502 | (use (match_operand 1 "register_operand" "")) | |
3503 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3504 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3505 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 3506 | "reload_completed" |
9bb86f41 UW |
3507 | [(set (match_dup 2) (label_ref (match_dup 3))) |
3508 | (parallel | |
9381e3f1 | 3509 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3510 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3511 | (set (match_dup 0) (const_int 0)) | |
3512 | (use (const_int 1)) | |
ae156f85 | 3513 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3514 | "operands[3] = gen_label_rtx ();") |
3515 | ||
9381e3f1 | 3516 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3517 | |
da0dcab1 | 3518 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3519 | [(parallel |
3520 | [(clobber (match_dup 1)) | |
3521 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3522 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3523 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3524 | (use (match_dup 3)) |
ae156f85 | 3525 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3526 | "" |
a41c6c53 | 3527 | { |
ef4bddc2 RS |
3528 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3529 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3530 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3531 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3532 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3533 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3534 | |
c41c1387 | 3535 | emit_clobber (reg0); |
b9404c99 UW |
3536 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3537 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3538 | |
b9404c99 | 3539 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3540 | |
b9404c99 UW |
3541 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3542 | operands[1] = reg0; | |
6d057022 | 3543 | operands[3] = reg1; |
da0dcab1 | 3544 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3545 | }) |
a41c6c53 | 3546 | |
da0dcab1 DV |
3547 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3548 | ||
db340c73 | 3549 | (define_insn "*setmem_long" |
a1aed706 | 3550 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3551 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3552 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3553 | (subreg:P (match_dup 3) <modesize>)] |
3554 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3555 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3556 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3557 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3558 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3559 | [(set_attr "length" "8") |
3560 | (set_attr "type" "vs")]) | |
9db1d521 | 3561 | |
db340c73 AK |
3562 | (define_insn "*setmem_long_and" |
3563 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3564 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3565 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3566 | (subreg:P (match_dup 3) <modesize>)] |
3567 | UNSPEC_REPLICATE_BYTE)) | |
3568 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3569 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3570 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3571 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3572 | [(set_attr "length" "8") | |
3573 | (set_attr "type" "vs")]) | |
3574 | ||
da0dcab1 DV |
3575 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3576 | ; of the SImode subregs. | |
3577 | ||
db340c73 | 3578 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3579 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3580 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3581 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3582 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3583 | (use (match_operand:TI 1 "register_operand" "d")) |
3584 | (clobber (reg:CC CC_REGNUM))] | |
3585 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3586 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3587 | [(set_attr "length" "8") | |
3588 | (set_attr "type" "vs")]) | |
9602b6a1 | 3589 | |
db340c73 AK |
3590 | (define_insn "*setmem_long_and_31z" |
3591 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3592 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3593 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3594 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3595 | (use (match_operand:TI 1 "register_operand" "d")) | |
3596 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3597 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3598 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3599 | [(set_attr "length" "8") | |
3600 | (set_attr "type" "vs")]) | |
3601 | ||
9db1d521 | 3602 | ; |
358b8f01 | 3603 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3604 | ; |
3605 | ||
358b8f01 | 3606 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3607 | [(set (match_operand:SI 0 "register_operand" "") |
3608 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3609 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3610 | (use (match_operand:SI 3 "general_operand" "")) | |
3611 | (use (match_operand:SI 4 "" ""))] | |
3612 | "" | |
367d32f3 AK |
3613 | { |
3614 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3615 | operands[2], operands[3])) | |
3616 | DONE; | |
3617 | else | |
3618 | FAIL; | |
3619 | }) | |
9db1d521 | 3620 | |
a41c6c53 UW |
3621 | ; Compare a block that is up to 256 bytes in length. |
3622 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3623 | |
b9404c99 UW |
3624 | (define_expand "cmpmem_short" |
3625 | [(parallel | |
ae156f85 | 3626 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3627 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3628 | (match_operand:BLK 1 "memory_operand" ""))) |
3629 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3630 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3631 | (clobber (match_dup 3))])] |
3632 | "" | |
3633 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3634 | |
b9404c99 | 3635 | (define_insn "*cmpmem_short" |
ae156f85 | 3636 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3637 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3638 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3639 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3640 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3641 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3642 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3643 | "#" |
963fc8d0 | 3644 | [(set_attr "type" "cs") |
b5e0425c | 3645 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3646 | |
9bb86f41 | 3647 | (define_split |
ae156f85 | 3648 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3649 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3650 | (match_operand:BLK 1 "memory_operand" ""))) | |
3651 | (use (match_operand 2 "const_int_operand" "")) | |
3652 | (use (match_operand 3 "immediate_operand" "")) | |
3653 | (clobber (scratch))] | |
3654 | "reload_completed" | |
3655 | [(parallel | |
ae156f85 | 3656 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3657 | (use (match_dup 2))])] |
3658 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3659 | |
9bb86f41 | 3660 | (define_split |
ae156f85 | 3661 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3662 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3663 | (match_operand:BLK 1 "memory_operand" ""))) | |
3664 | (use (match_operand 2 "register_operand" "")) | |
3665 | (use (match_operand 3 "memory_operand" "")) | |
3666 | (clobber (scratch))] | |
3667 | "reload_completed" | |
3668 | [(parallel | |
3669 | [(unspec [(match_dup 2) (match_dup 3) | |
3670 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3671 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3672 | (use (const_int 1))])] |
3673 | "") | |
3674 | ||
963fc8d0 AK |
3675 | (define_split |
3676 | [(set (reg:CCU CC_REGNUM) | |
3677 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3678 | (match_operand:BLK 1 "memory_operand" ""))) | |
3679 | (use (match_operand 2 "register_operand" "")) | |
3680 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3681 | (clobber (scratch))] | |
3682 | "TARGET_Z10 && reload_completed" | |
3683 | [(parallel | |
3684 | [(unspec [(match_dup 2) (const_int 0) | |
3685 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3686 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3687 | (use (const_int 1))])] | |
3688 | "operands[4] = gen_label_rtx ();") | |
3689 | ||
9bb86f41 | 3690 | (define_split |
ae156f85 | 3691 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3692 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3693 | (match_operand:BLK 1 "memory_operand" ""))) | |
3694 | (use (match_operand 2 "register_operand" "")) | |
3695 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3696 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3697 | "reload_completed" |
9bb86f41 UW |
3698 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3699 | (parallel | |
9381e3f1 | 3700 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3701 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3702 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3703 | (use (const_int 1))])] |
3704 | "operands[4] = gen_label_rtx ();") | |
3705 | ||
a41c6c53 | 3706 | ; Compare a block of arbitrary length. |
9db1d521 | 3707 | |
b9404c99 UW |
3708 | (define_expand "cmpmem_long" |
3709 | [(parallel | |
3710 | [(clobber (match_dup 2)) | |
3711 | (clobber (match_dup 3)) | |
ae156f85 | 3712 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3713 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3714 | (match_operand:BLK 1 "memory_operand" ""))) |
3715 | (use (match_operand 2 "general_operand" "")) | |
3716 | (use (match_dup 3))])] | |
3717 | "" | |
3718 | { | |
ef4bddc2 RS |
3719 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3720 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3721 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3722 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3723 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3724 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3725 | rtx len0 = gen_lowpart (Pmode, reg0); |
3726 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3727 | ||
c41c1387 | 3728 | emit_clobber (reg0); |
b9404c99 UW |
3729 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3730 | emit_move_insn (len0, operands[2]); | |
3731 | ||
c41c1387 | 3732 | emit_clobber (reg1); |
b9404c99 UW |
3733 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3734 | emit_move_insn (len1, operands[2]); | |
3735 | ||
3736 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3737 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3738 | operands[2] = reg0; | |
3739 | operands[3] = reg1; | |
3740 | }) | |
3741 | ||
a1aed706 AS |
3742 | (define_insn "*cmpmem_long" |
3743 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3744 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3745 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3746 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3747 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3748 | (use (match_dup 2)) |
3749 | (use (match_dup 3))] | |
9602b6a1 | 3750 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3751 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3752 | [(set_attr "length" "8") |
3753 | (set_attr "type" "vs")]) | |
9db1d521 | 3754 | |
9602b6a1 AK |
3755 | (define_insn "*cmpmem_long_31z" |
3756 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3757 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3758 | (set (reg:CCU CC_REGNUM) | |
3759 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3760 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3761 | (use (match_dup 2)) | |
3762 | (use (match_dup 3))] | |
3763 | "!TARGET_64BIT && TARGET_ZARCH" | |
3764 | "clcle\t%0,%1,0\;jo\t.-4" | |
3765 | [(set_attr "op_type" "NN") | |
3766 | (set_attr "type" "vs") | |
3767 | (set_attr "length" "8")]) | |
3768 | ||
02887425 UW |
3769 | ; Convert CCUmode condition code to integer. |
3770 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3771 | |
02887425 | 3772 | (define_insn_and_split "cmpint" |
9db1d521 | 3773 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3774 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3775 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3776 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3777 | "" |
02887425 UW |
3778 | "#" |
3779 | "reload_completed" | |
3780 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3781 | (parallel | |
3782 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3783 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3784 | |
3785 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3786 | [(set (reg CC_REGNUM) |
02887425 | 3787 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3788 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3789 | (const_int 0))) |
3790 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3791 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3792 | "s390_match_ccmode (insn, CCSmode)" |
3793 | "#" | |
3794 | "&& reload_completed" | |
3795 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3796 | (parallel | |
3797 | [(set (match_dup 2) (match_dup 3)) | |
3798 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3799 | { |
02887425 UW |
3800 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3801 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3802 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3803 | }) | |
9db1d521 | 3804 | |
02887425 | 3805 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3806 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3807 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3808 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3809 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3810 | "TARGET_ZARCH" |
02887425 UW |
3811 | "#" |
3812 | "&& reload_completed" | |
3813 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3814 | (parallel | |
3815 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3816 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3817 | |
3818 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3819 | [(set (reg CC_REGNUM) |
9381e3f1 | 3820 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3821 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3822 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3823 | (const_int 32)) (const_int 32)) |
3824 | (const_int 0))) | |
3825 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3826 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3827 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3828 | "#" |
3829 | "&& reload_completed" | |
3830 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3831 | (parallel | |
3832 | [(set (match_dup 2) (match_dup 3)) | |
3833 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3834 | { |
02887425 UW |
3835 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3836 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3837 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3838 | }) | |
9db1d521 | 3839 | |
4023fb28 | 3840 | |
9db1d521 HP |
3841 | ;; |
3842 | ;;- Conversion instructions. | |
3843 | ;; | |
3844 | ||
6fa05db6 | 3845 | (define_insn "*sethighpartsi" |
d3632d41 | 3846 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3847 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3848 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3849 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3850 | "" |
d3632d41 | 3851 | "@ |
6fa05db6 AS |
3852 | icm\t%0,%2,%S1 |
3853 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3854 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3855 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3856 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3857 | |
6fa05db6 | 3858 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3859 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3860 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3861 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3862 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3863 | "TARGET_ZARCH" |
6fa05db6 | 3864 | "icmh\t%0,%2,%S1" |
729e750f WG |
3865 | [(set_attr "op_type" "RSY") |
3866 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3867 | |
6fa05db6 | 3868 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3869 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3870 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3871 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3872 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3873 | "!TARGET_ZARCH" |
d3632d41 | 3874 | "@ |
6fa05db6 AS |
3875 | icm\t%0,%2,%S1 |
3876 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3877 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3878 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3879 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3880 | ||
1a2e356e RH |
3881 | ; |
3882 | ; extv instruction patterns | |
3883 | ; | |
3884 | ||
3885 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3886 | ; after resolving some issues with it. | |
3887 | ||
3888 | (define_expand "extzv" | |
3889 | [(parallel | |
3890 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3891 | (zero_extract:DI | |
3892 | (match_operand:DI 1 "register_operand" "d") | |
3893 | (match_operand 2 "const_int_operand" "") ; size | |
3894 | (match_operand 3 "const_int_operand" ""))) ; start | |
3895 | (clobber (reg:CC CC_REGNUM))])] | |
3896 | "TARGET_Z10" | |
3897 | { | |
0f6f72e8 DV |
3898 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3899 | FAIL; | |
1a2e356e RH |
3900 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3901 | if (TARGET_ZEC12) | |
3902 | { | |
3903 | emit_move_insn (operands[0], | |
3904 | gen_rtx_ZERO_EXTRACT (DImode, | |
3905 | operands[1], | |
3906 | operands[2], | |
3907 | operands[3])); | |
3908 | DONE; | |
3909 | } | |
3910 | }) | |
3911 | ||
64c744b9 | 3912 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3913 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3914 | (zero_extract:GPR | |
3915 | (match_operand:GPR 1 "register_operand" "d") | |
3916 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3917 | (match_operand 3 "const_int_operand" ""))) ; start |
3918 | ] | |
0f6f72e8 DV |
3919 | "<z10_or_zEC12_cond> |
3920 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3921 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3922 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3923 | [(set_attr "op_type" "RIE") | |
3924 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3925 | |
64c744b9 DV |
3926 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3927 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3928 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3929 | (match_operand 1 "const_int_operand" "") ; size | |
3930 | (match_operand 2 "const_int_operand" "")) ; start | |
3931 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3932 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3933 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3934 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3935 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3936 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3937 | [(set_attr "op_type" "RIE") | |
3938 | (set_attr "z10prop" "z10_super_E1")]) | |
3939 | ||
3940 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3941 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3942 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3943 | (ior:SI (and:SI | |
3944 | (match_operand:SI 1 "register_operand" "0") | |
3945 | (match_operand:SI 2 "const_int_operand" "")) | |
3946 | (subreg:SI | |
3947 | (zero_extract:DI | |
3948 | (match_operand:DI 3 "register_operand" "d") | |
3949 | (match_operand 4 "const_int_operand" "") ; size | |
3950 | (match_operand 5 "const_int_operand" "")) ; start | |
3951 | 4)))] | |
3952 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3953 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
14653c37 | 3954 | && UINTVAL (operands[2]) == (HOST_WIDE_INT_M1U << UINTVAL (operands[4]))" |
64c744b9 DV |
3955 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" |
3956 | [(set_attr "op_type" "RIE") | |
3957 | (set_attr "z10prop" "z10_super_E1")]) | |
3958 | ||
3959 | ; ((int)foo >> 10) & 1; | |
3960 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3961 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3962 | (ne:DI (zero_extract:DI | |
3963 | (match_operand:DI 1 "register_operand" "d") | |
3964 | (const_int 1) ; size | |
3965 | (match_operand 2 "const_int_operand" "")) ; start | |
3966 | (const_int 0)))] | |
0f6f72e8 DV |
3967 | "<z10_or_zEC12_cond> |
3968 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3969 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3970 | [(set_attr "op_type" "RIE") | |
3971 | (set_attr "z10prop" "z10_super_E1")]) | |
3972 | ||
3973 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3974 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3975 | (and:DI (subreg:DI | |
3976 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3977 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3978 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3979 | "<z10_or_zEC12_cond> | |
14653c37 JJ |
3980 | && (UINTVAL (operands[3]) |
3981 | < (HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)))" | |
64c744b9 DV |
3982 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift |
3983 | [(set_attr "op_type" "RIE") | |
3984 | (set_attr "z10prop" "z10_super_E1")]) | |
3985 | ||
3986 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3987 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3988 | (and:DI (subreg:DI | |
3989 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3990 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3991 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3992 | "<z10_or_zEC12_cond> | |
14653c37 JJ |
3993 | && !(UINTVAL (operands[3]) |
3994 | & ((HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
64c744b9 DV |
3995 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift |
3996 | [(set_attr "op_type" "RIE") | |
3997 | (set_attr "z10prop" "z10_super_E1")]) | |
3998 | ||
3999 | (define_insn "*<risbg_n>_di_and_rot" | |
4000 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4001 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
4002 | (match_operand:DI 2 "const_int_operand" "")) | |
4003 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
4004 | "<z10_or_zEC12_cond>" | |
4005 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
4006 | [(set_attr "op_type" "RIE") |
4007 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 4008 | |
1a2e356e | 4009 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 4010 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 4011 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 4012 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 4013 | (const_int 0))) |
ae156f85 | 4014 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 4015 | "!TARGET_Z10" |
cc7ab9b7 UW |
4016 | "#" |
4017 | "&& reload_completed" | |
4023fb28 | 4018 | [(parallel |
6fa05db6 | 4019 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 4020 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 4021 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 4022 | { |
6fa05db6 AS |
4023 | int bitsize = INTVAL (operands[2]); |
4024 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
14653c37 JJ |
4025 | unsigned HOST_WIDE_INT mask |
4026 | = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
6fa05db6 AS |
4027 | |
4028 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4029 | set_mem_size (operands[1], size); |
2542ef05 | 4030 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 4031 | operands[3] = GEN_INT (mask); |
b628bd8e | 4032 | }) |
4023fb28 | 4033 | |
1a2e356e | 4034 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 4035 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 4036 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 4037 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 4038 | (const_int 0))) |
ae156f85 | 4039 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 4040 | "" |
cc7ab9b7 UW |
4041 | "#" |
4042 | "&& reload_completed" | |
4023fb28 | 4043 | [(parallel |
6fa05db6 | 4044 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 4045 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
4046 | (parallel |
4047 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
4048 | (clobber (reg:CC CC_REGNUM))])] | |
4049 | { | |
4050 | int bitsize = INTVAL (operands[2]); | |
4051 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
14653c37 JJ |
4052 | unsigned HOST_WIDE_INT mask |
4053 | = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
6fa05db6 AS |
4054 | |
4055 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4056 | set_mem_size (operands[1], size); |
2542ef05 | 4057 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
4058 | operands[3] = GEN_INT (mask); |
4059 | }) | |
4060 | ||
4061 | ; | |
4062 | ; insv instruction patterns | |
4063 | ; | |
4064 | ||
4065 | (define_expand "insv" | |
4066 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
4067 | (match_operand 1 "const_int_operand" "") | |
4068 | (match_operand 2 "const_int_operand" "")) | |
4069 | (match_operand 3 "general_operand" ""))] | |
4070 | "" | |
4023fb28 | 4071 | { |
6fa05db6 AS |
4072 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
4073 | DONE; | |
4074 | FAIL; | |
b628bd8e | 4075 | }) |
4023fb28 | 4076 | |
2542ef05 RH |
4077 | |
4078 | ; The normal RTL expansion will never generate a zero_extract where | |
4079 | ; the location operand isn't word mode. However, we do this in the | |
4080 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 4081 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 4082 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
4083 | (match_operand 1 "const_int_operand" "I") ; size |
4084 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 4085 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 4086 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
4087 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
4088 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 4089 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 4090 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
4091 | [(set_attr "op_type" "RIE") |
4092 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4093 | |
22ac2c2f AK |
4094 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
4095 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
4096 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
4097 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
4098 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 4099 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 4100 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 4101 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
4102 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
4103 | "@ | |
4104 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
4105 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
4106 | [(set_attr "op_type" "RIE") | |
4107 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 4108 | |
64c744b9 DV |
4109 | (define_insn "*insv_z10_noshift_cc" |
4110 | [(set (reg CC_REGNUM) | |
4111 | (compare | |
4112 | (ior:DI | |
4113 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4114 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4115 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4116 | (match_operand:DI 4 "const_int_operand" ""))) | |
4117 | (const_int 0))) | |
4118 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
4119 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
4120 | (and:DI (match_dup 3) (match_dup 4))))] | |
4121 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4122 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4123 | "@ | |
4124 | risbg\t%0,%1,%s2,%e2,0 | |
4125 | risbg\t%0,%3,%s4,%e4,0" | |
4126 | [(set_attr "op_type" "RIE") | |
4127 | (set_attr "z10prop" "z10_super_E1")]) | |
4128 | ||
4129 | (define_insn "*insv_z10_noshift_cconly" | |
4130 | [(set | |
4131 | (reg CC_REGNUM) | |
4132 | (compare | |
4133 | (ior:DI | |
4134 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4135 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4136 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4137 | (match_operand:DI 4 "const_int_operand" ""))) | |
4138 | (const_int 0))) | |
4139 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4140 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4141 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4142 | "@ | |
4143 | risbg\t%0,%1,%s2,%e2,0 | |
4144 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4145 | [(set_attr "op_type" "RIE") |
4146 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4147 | |
3d44ff99 AK |
4148 | ; Implement appending Y on the left of S bits of X |
4149 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4150 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4151 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4152 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4153 | (match_operand:GPR 2 "immediate_operand" "")) | |
4154 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4155 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 | 4156 | "<z10_or_zEC12_cond> |
14653c37 | 4157 | && UINTVAL (operands[2]) == (HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1" |
64c744b9 | 4158 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" |
3d44ff99 AK |
4159 | [(set_attr "op_type" "RIE") |
4160 | (set_attr "z10prop" "z10_super_E1")]) | |
4161 | ||
64c744b9 DV |
4162 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4163 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4164 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4165 | (ior:GPR (and:GPR | |
4166 | (match_operand:GPR 1 "register_operand" "0") | |
4167 | (match_operand:GPR 2 "const_int_operand" "")) | |
4168 | (lshiftrt:GPR | |
4169 | (match_operand:GPR 3 "register_operand" "d") | |
4170 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4171 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
14653c37 JJ |
4172 | == (HOST_WIDE_INT_M1U |
4173 | << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
64c744b9 DV |
4174 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" |
4175 | [(set_attr "op_type" "RIE") | |
4176 | (set_attr "z10prop" "z10_super_E1")]) | |
4177 | ||
4178 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4179 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4180 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4181 | (ior:SI (and:SI | |
4182 | (match_operand:SI 1 "register_operand" "0") | |
4183 | (match_operand:SI 2 "const_int_operand" "")) | |
4184 | (subreg:SI | |
4185 | (lshiftrt:DI | |
4186 | (match_operand:DI 3 "register_operand" "d") | |
4187 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4188 | "<z10_or_zEC12_cond> | |
14653c37 | 4189 | && UINTVAL (operands[2]) == ~(HOST_WIDE_INT_M1U >> UINTVAL (operands[4]))" |
64c744b9 DV |
4190 | "<risbg_n>\t%0,%3,%4,63,64-%4" |
4191 | [(set_attr "op_type" "RIE") | |
4192 | (set_attr "z10prop" "z10_super_E1")]) | |
4193 | ||
4194 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4195 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4196 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4197 | (and:SI | |
4198 | (subreg:SI (lshiftrt:DI | |
4199 | (match_operand:DI 1 "register_operand" "d") | |
4200 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4201 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4202 | "<z10_or_zEC12_cond>" | |
4203 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4204 | [(set_attr "op_type" "RIE") |
4205 | (set_attr "z10prop" "z10_super_E1")]) | |
4206 | ||
4207 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4208 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4209 | ; -> z = y >> d; z = risbg; | |
4210 | ||
4211 | (define_split | |
4212 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4213 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4214 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4215 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4216 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4217 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4218 | [(set (match_dup 6) |
3d44ff99 AK |
4219 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4220 | (set (match_dup 0) | |
1d11f7ce | 4221 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4222 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4223 | { | |
14653c37 | 4224 | operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); |
3168e073 | 4225 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4226 | { |
4227 | if (!can_create_pseudo_p ()) | |
4228 | FAIL; | |
4229 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4230 | } | |
4231 | else | |
4232 | operands[6] = operands[0]; | |
3d44ff99 AK |
4233 | }) |
4234 | ||
4235 | (define_split | |
4236 | [(parallel | |
4237 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4238 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4239 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4240 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4241 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4242 | (clobber (reg:CC CC_REGNUM))])] | |
4243 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4244 | [(set (match_dup 6) |
3d44ff99 AK |
4245 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4246 | (parallel | |
4247 | [(set (match_dup 0) | |
1d11f7ce | 4248 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4249 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4250 | (clobber (reg:CC CC_REGNUM))])] | |
4251 | { | |
14653c37 | 4252 | operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); |
3168e073 | 4253 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4254 | { |
4255 | if (!can_create_pseudo_p ()) | |
4256 | FAIL; | |
4257 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4258 | } | |
4259 | else | |
4260 | operands[6] = operands[0]; | |
3d44ff99 AK |
4261 | }) |
4262 | ||
50dc4eed | 4263 | ; rosbg, rxsbg |
571e408a | 4264 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4265 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4266 | (IXOR:GPR |
4267 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4268 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4269 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4270 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4271 | "TARGET_Z10" |
571e408a RH |
4272 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4273 | [(set_attr "op_type" "RIE")]) | |
4274 | ||
50dc4eed | 4275 | ; rosbg, rxsbg |
571e408a RH |
4276 | (define_insn "*r<noxa>sbg_di_rotl" |
4277 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4278 | (IXOR:DI | |
4279 | (and:DI | |
4280 | (rotate:DI | |
4281 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4282 | (match_operand:DI 3 "const_int_operand" "")) | |
4283 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4284 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4285 | (clobber (reg:CC CC_REGNUM))] | |
4286 | "TARGET_Z10" | |
8c21b0d1 | 4287 | "r<noxa>sbg\t%0,%1,%s2,%e2,%b3" |
571e408a RH |
4288 | [(set_attr "op_type" "RIE")]) |
4289 | ||
50dc4eed | 4290 | ; rosbg, rxsbg |
f3d90045 | 4291 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4292 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4293 | (IXOR:GPR | |
4294 | (and:GPR | |
4295 | (lshiftrt:GPR | |
4296 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4297 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4298 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4299 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4300 | (clobber (reg:CC CC_REGNUM))] | |
4301 | "TARGET_Z10 | |
4302 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4303 | INTVAL (operands[2]))" | |
b9789752 | 4304 | { |
290dfd9b JJ |
4305 | operands[3] = GEN_INT (64 - INTVAL (operands[3])); |
4306 | return "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"; | |
b9789752 | 4307 | } |
571e408a RH |
4308 | [(set_attr "op_type" "RIE")]) |
4309 | ||
50dc4eed | 4310 | ; rosbg, rxsbg |
f3d90045 | 4311 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4312 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4313 | (IXOR:GPR | |
4314 | (and:GPR | |
4315 | (ashift:GPR | |
4316 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4317 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4318 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4319 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4320 | (clobber (reg:CC CC_REGNUM))] | |
4321 | "TARGET_Z10 | |
4322 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4323 | INTVAL (operands[2]))" | |
4324 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4325 | [(set_attr "op_type" "RIE")]) |
4326 | ||
f3d90045 DV |
4327 | ;; unsigned {int,long} a, b |
4328 | ;; a = a | (b << const_int) | |
4329 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4330 | ; rosbg, rxsbg |
f3d90045 DV |
4331 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4332 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4333 | (IXOR:GPR | |
4334 | (ashift:GPR | |
4335 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4336 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4337 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4338 | (clobber (reg:CC CC_REGNUM))] | |
4339 | "TARGET_Z10" | |
b9789752 | 4340 | { |
290dfd9b JJ |
4341 | operands[3] = GEN_INT (63 - INTVAL (operands[2])); |
4342 | return "r<noxa>sbg\t%0,%1,<bitoff>,%3,%2"; | |
b9789752 | 4343 | } |
f3d90045 DV |
4344 | [(set_attr "op_type" "RIE")]) |
4345 | ||
4346 | ;; unsigned {int,long} a, b | |
4347 | ;; a = a | (b >> const_int) | |
4348 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4349 | ; rosbg, rxsbg |
f3d90045 DV |
4350 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4351 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4352 | (IXOR:GPR | |
4353 | (lshiftrt:GPR | |
4354 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4355 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4356 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4357 | (clobber (reg:CC CC_REGNUM))] | |
4358 | "TARGET_Z10" | |
b9789752 | 4359 | { |
290dfd9b JJ |
4360 | operands[3] = GEN_INT (64 - INTVAL (operands[2])); |
4361 | operands[2] = GEN_INT (<bitoff_plus> INTVAL (operands[2])); | |
4362 | return "r<noxa>sbg\t%0,%1,%2,63,%3"; | |
b9789752 IL |
4363 | } |
4364 | [(set_attr "op_type" "RIE")]) | |
4365 | ||
4366 | ; rosbg, rxsbg | |
4367 | (define_insn "*r<noxa>sbg_sidi_srl" | |
4368 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
4369 | (IXOR:SI | |
4370 | (subreg:SI | |
4371 | (zero_extract:DI | |
4372 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4373 | (const_int 32) | |
4374 | (match_operand:DI 2 "immediate_operand" "")) | |
4375 | 4) | |
4376 | (match_operand:SI 3 "nonimmediate_operand" "0"))) | |
4377 | (clobber (reg:CC CC_REGNUM))] | |
4378 | "TARGET_Z10" | |
4379 | { | |
290dfd9b JJ |
4380 | operands[2] = GEN_INT (32 + INTVAL (operands[2])); |
4381 | return "r<noxa>sbg\t%0,%1,32,63,%2"; | |
b9789752 | 4382 | } |
f3d90045 DV |
4383 | [(set_attr "op_type" "RIE")]) |
4384 | ||
5bb33936 RH |
4385 | ;; These two are generated by combine for s.bf &= val. |
4386 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4387 | ;; shifts and ands, which results in some truly awful patterns | |
4388 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4389 | ;; Instead of | |
4390 | ;; | |
4391 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4392 | ;; (const_int 24 [0x18]) | |
4393 | ;; (const_int 0 [0])) | |
4394 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4395 | ;; (const_int 40 [0x28])) 4) | |
4396 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4397 | ;; | |
4398 | ;; we should instead generate | |
4399 | ;; | |
4400 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4401 | ;; (const_int 24 [0x18]) | |
4402 | ;; (const_int 0 [0])) | |
4403 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4404 | ;; (const_int 40 [0x28])) | |
4405 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4406 | ;; | |
4407 | ;; by noticing that we can push down the outer paradoxical subreg | |
4408 | ;; into the operation. | |
4409 | ||
4410 | (define_insn "*insv_rnsbg_noshift" | |
4411 | [(set (zero_extract:DI | |
4412 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4413 | (match_operand 1 "const_int_operand" "") | |
4414 | (match_operand 2 "const_int_operand" "")) | |
4415 | (and:DI | |
4416 | (match_dup 0) | |
4417 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4418 | (clobber (reg:CC CC_REGNUM))] | |
4419 | "TARGET_Z10 | |
0f6f72e8 | 4420 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4421 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4422 | "rnsbg\t%0,%3,%2,63,0" | |
4423 | [(set_attr "op_type" "RIE")]) | |
4424 | ||
4425 | (define_insn "*insv_rnsbg_srl" | |
4426 | [(set (zero_extract:DI | |
4427 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4428 | (match_operand 1 "const_int_operand" "") | |
4429 | (match_operand 2 "const_int_operand" "")) | |
4430 | (and:DI | |
4431 | (lshiftrt:DI | |
4432 | (match_dup 0) | |
4433 | (match_operand 3 "const_int_operand" "")) | |
4434 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4435 | (clobber (reg:CC CC_REGNUM))] | |
4436 | "TARGET_Z10 | |
0f6f72e8 | 4437 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4438 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4439 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4440 | [(set_attr "op_type" "RIE")]) | |
4441 | ||
6fa05db6 | 4442 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4443 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4444 | (match_operand 1 "const_int_operand" "n,n") |
4445 | (const_int 0)) | |
9602b6a1 | 4446 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4447 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4448 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4449 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4450 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4451 | { | |
4452 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4453 | ||
14653c37 | 4454 | operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1); |
9381e3f1 | 4455 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4456 | : "stcmy\t%2,%1,%S0"; |
4457 | } | |
9381e3f1 | 4458 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4459 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4460 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4461 | |
4462 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4463 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4464 | (match_operand 1 "const_int_operand" "n") |
4465 | (const_int 0)) | |
4466 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4467 | (const_int 32)))] | |
9602b6a1 | 4468 | "TARGET_ZARCH |
0f6f72e8 | 4469 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4470 | && INTVAL (operands[1]) > 0 |
4471 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4472 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4473 | { | |
4474 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4475 | ||
14653c37 | 4476 | operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1); |
6fa05db6 AS |
4477 | return "stcmh\t%2,%1,%S0"; |
4478 | } | |
9381e3f1 WG |
4479 | [(set_attr "op_type" "RSY") |
4480 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4481 | |
9602b6a1 AK |
4482 | (define_insn "*insvdi_reg_imm" |
4483 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4484 | (const_int 16) | |
4485 | (match_operand 1 "const_int_operand" "n")) | |
4486 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4487 | "TARGET_ZARCH |
0f6f72e8 | 4488 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4489 | && INTVAL (operands[1]) >= 0 |
4490 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4491 | && INTVAL (operands[1]) % 16 == 0" | |
4492 | { | |
4493 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4494 | { | |
4495 | case 64: return "iihh\t%0,%x2"; break; | |
4496 | case 48: return "iihl\t%0,%x2"; break; | |
4497 | case 32: return "iilh\t%0,%x2"; break; | |
4498 | case 16: return "iill\t%0,%x2"; break; | |
4499 | default: gcc_unreachable(); | |
4500 | } | |
4501 | } | |
9381e3f1 WG |
4502 | [(set_attr "op_type" "RI") |
4503 | (set_attr "z10prop" "z10_super_E1")]) | |
4504 | ||
9fec758d WG |
4505 | ; Update the left-most 32 bit of a DI. |
4506 | (define_insn "*insv_h_di_reg_extimm" | |
4507 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4508 | (const_int 32) | |
4509 | (const_int 0)) | |
4510 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4511 | "TARGET_EXTIMM" | |
4512 | "iihf\t%0,%o1" | |
4513 | [(set_attr "op_type" "RIL") | |
4514 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4515 | |
d378b983 RH |
4516 | ; Update the right-most 32 bit of a DI. |
4517 | (define_insn "*insv_l_di_reg_extimm" | |
4518 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4519 | (const_int 32) | |
4520 | (const_int 32)) | |
4521 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4522 | "TARGET_EXTIMM" | |
4523 | "iilf\t%0,%o1" | |
9381e3f1 | 4524 | [(set_attr "op_type" "RIL") |
9fec758d | 4525 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4526 | |
9db1d521 HP |
4527 | ; |
4528 | ; extendsidi2 instruction pattern(s). | |
4529 | ; | |
4530 | ||
4023fb28 UW |
4531 | (define_expand "extendsidi2" |
4532 | [(set (match_operand:DI 0 "register_operand" "") | |
4533 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4534 | "" | |
4023fb28 | 4535 | { |
9602b6a1 | 4536 | if (!TARGET_ZARCH) |
4023fb28 | 4537 | { |
c41c1387 | 4538 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4539 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4540 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4541 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4542 | DONE; |
4543 | } | |
ec24698e | 4544 | }) |
4023fb28 UW |
4545 | |
4546 | (define_insn "*extendsidi2" | |
963fc8d0 | 4547 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4548 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4549 | "TARGET_ZARCH" |
9db1d521 | 4550 | "@ |
d40c829f | 4551 | lgfr\t%0,%1 |
963fc8d0 AK |
4552 | lgf\t%0,%1 |
4553 | lgfrl\t%0,%1" | |
4554 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4555 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4556 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4557 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4558 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4559 | |
9db1d521 | 4560 | ; |
56477c21 | 4561 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4562 | ; |
4563 | ||
56477c21 AS |
4564 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4565 | [(set (match_operand:DSI 0 "register_operand" "") | |
4566 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4567 | "" |
4023fb28 | 4568 | { |
9602b6a1 | 4569 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4570 | { |
4571 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4572 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4573 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4574 | DONE; | |
4575 | } | |
ec24698e | 4576 | else if (!TARGET_EXTIMM) |
4023fb28 | 4577 | { |
2542ef05 | 4578 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4579 | |
4580 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4581 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4582 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4583 | DONE; |
4584 | } | |
ec24698e UW |
4585 | }) |
4586 | ||
56477c21 AS |
4587 | ; |
4588 | ; extendhidi2 instruction pattern(s). | |
4589 | ; | |
4590 | ||
ec24698e | 4591 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4592 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4593 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4594 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4595 | "@ |
4596 | lghr\t%0,%1 | |
963fc8d0 AK |
4597 | lgh\t%0,%1 |
4598 | lghrl\t%0,%1" | |
4599 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4600 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4601 | (set_attr "cpu_facility" "extimm,extimm,z10") |
14cfceb7 IL |
4602 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4603 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 UW |
4604 | |
4605 | (define_insn "*extendhidi2" | |
9db1d521 | 4606 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4607 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4608 | "TARGET_ZARCH" |
d40c829f | 4609 | "lgh\t%0,%1" |
9381e3f1 WG |
4610 | [(set_attr "op_type" "RXY") |
4611 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4612 | |
9db1d521 | 4613 | ; |
56477c21 | 4614 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4615 | ; |
4616 | ||
ec24698e | 4617 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4618 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4619 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4620 | "TARGET_EXTIMM" |
4621 | "@ | |
4622 | lhr\t%0,%1 | |
4623 | lh\t%0,%1 | |
963fc8d0 AK |
4624 | lhy\t%0,%1 |
4625 | lhrl\t%0,%1" | |
4626 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4627 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 | 4628 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
14cfceb7 IL |
4629 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1") |
4630 | (set_attr "relative_long" "*,*,*,yes")]) | |
9db1d521 | 4631 | |
4023fb28 | 4632 | (define_insn "*extendhisi2" |
d3632d41 UW |
4633 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4634 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4635 | "!TARGET_EXTIMM" |
d3632d41 | 4636 | "@ |
d40c829f UW |
4637 | lh\t%0,%1 |
4638 | lhy\t%0,%1" | |
9381e3f1 | 4639 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4640 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4641 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4642 | |
56477c21 AS |
4643 | ; |
4644 | ; extendqi(si|di)2 instruction pattern(s). | |
4645 | ; | |
4646 | ||
43a09b63 | 4647 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4648 | (define_insn "*extendqi<mode>2_extimm" |
4649 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4650 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4651 | "TARGET_EXTIMM" |
4652 | "@ | |
56477c21 AS |
4653 | l<g>br\t%0,%1 |
4654 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4655 | [(set_attr "op_type" "RRE,RXY") |
4656 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4657 | |
43a09b63 | 4658 | ; lb, lgb |
56477c21 AS |
4659 | (define_insn "*extendqi<mode>2" |
4660 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4661 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4662 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4663 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4664 | [(set_attr "op_type" "RXY") |
4665 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4666 | |
56477c21 AS |
4667 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4668 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4669 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4670 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4671 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4672 | "#" |
4673 | "&& reload_completed" | |
4023fb28 | 4674 | [(parallel |
56477c21 | 4675 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4676 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4677 | (parallel |
56477c21 | 4678 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4679 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4680 | { |
4681 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4682 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4683 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4684 | }) |
9db1d521 | 4685 | |
9db1d521 HP |
4686 | ; |
4687 | ; zero_extendsidi2 instruction pattern(s). | |
4688 | ; | |
4689 | ||
4023fb28 UW |
4690 | (define_expand "zero_extendsidi2" |
4691 | [(set (match_operand:DI 0 "register_operand" "") | |
4692 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4693 | "" | |
4023fb28 | 4694 | { |
9602b6a1 | 4695 | if (!TARGET_ZARCH) |
4023fb28 | 4696 | { |
c41c1387 | 4697 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4698 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4699 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4700 | DONE; |
4701 | } | |
ec24698e | 4702 | }) |
4023fb28 UW |
4703 | |
4704 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4705 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4706 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4707 | "TARGET_ZARCH" |
9db1d521 | 4708 | "@ |
d40c829f | 4709 | llgfr\t%0,%1 |
963fc8d0 AK |
4710 | llgf\t%0,%1 |
4711 | llgfrl\t%0,%1" | |
4712 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4713 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4714 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4715 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3") |
4716 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4717 | |
288e517f AK |
4718 | ; |
4719 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4720 | ; | |
4721 | ||
d6083c7d UW |
4722 | (define_insn "*llgt_sidi" |
4723 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4724 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4725 | (const_int 2147483647)))] |
9602b6a1 | 4726 | "TARGET_ZARCH" |
d6083c7d | 4727 | "llgt\t%0,%1" |
9381e3f1 WG |
4728 | [(set_attr "op_type" "RXE") |
4729 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4730 | |
4731 | (define_insn_and_split "*llgt_sidi_split" | |
4732 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4733 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4734 | (const_int 2147483647))) |
ae156f85 | 4735 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4736 | "TARGET_ZARCH" |
d6083c7d UW |
4737 | "#" |
4738 | "&& reload_completed" | |
4739 | [(set (match_dup 0) | |
4740 | (and:DI (subreg:DI (match_dup 1) 0) | |
4741 | (const_int 2147483647)))] | |
4742 | "") | |
4743 | ||
288e517f AK |
4744 | (define_insn "*llgt_sisi" |
4745 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4746 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4747 | (const_int 2147483647)))] |
c4d50129 | 4748 | "TARGET_ZARCH" |
288e517f AK |
4749 | "@ |
4750 | llgtr\t%0,%1 | |
4751 | llgt\t%0,%1" | |
9381e3f1 WG |
4752 | [(set_attr "op_type" "RRE,RXE") |
4753 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4754 | |
288e517f AK |
4755 | (define_insn "*llgt_didi" |
4756 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4757 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4758 | (const_int 2147483647)))] | |
9602b6a1 | 4759 | "TARGET_ZARCH" |
288e517f AK |
4760 | "@ |
4761 | llgtr\t%0,%1 | |
4762 | llgt\t%0,%N1" | |
9381e3f1 WG |
4763 | [(set_attr "op_type" "RRE,RXE") |
4764 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4765 | |
f19a9af7 | 4766 | (define_split |
9602b6a1 AK |
4767 | [(set (match_operand:DSI 0 "register_operand" "") |
4768 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4769 | (const_int 2147483647))) |
ae156f85 | 4770 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4771 | "TARGET_ZARCH && reload_completed" |
288e517f | 4772 | [(set (match_dup 0) |
9602b6a1 | 4773 | (and:DSI (match_dup 1) |
f6ee577c | 4774 | (const_int 2147483647)))] |
288e517f AK |
4775 | "") |
4776 | ||
9db1d521 | 4777 | ; |
56477c21 | 4778 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4779 | ; |
4780 | ||
56477c21 AS |
4781 | (define_expand "zero_extend<mode>di2" |
4782 | [(set (match_operand:DI 0 "register_operand" "") | |
4783 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4784 | "" | |
4785 | { | |
9602b6a1 | 4786 | if (!TARGET_ZARCH) |
56477c21 AS |
4787 | { |
4788 | rtx tmp = gen_reg_rtx (SImode); | |
4789 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4790 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4791 | DONE; | |
4792 | } | |
4793 | else if (!TARGET_EXTIMM) | |
4794 | { | |
2542ef05 | 4795 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4796 | operands[1] = gen_lowpart (DImode, operands[1]); |
4797 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4798 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4799 | DONE; | |
4800 | } | |
4801 | }) | |
4802 | ||
f6ee577c | 4803 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4804 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4805 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4806 | "" |
4023fb28 | 4807 | { |
ec24698e UW |
4808 | if (!TARGET_EXTIMM) |
4809 | { | |
4810 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4811 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4812 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4813 | DONE; |
56477c21 | 4814 | } |
ec24698e UW |
4815 | }) |
4816 | ||
963fc8d0 AK |
4817 | ; llhrl, llghrl |
4818 | (define_insn "*zero_extendhi<mode>2_z10" | |
4819 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4820 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4821 | "TARGET_Z10" |
4822 | "@ | |
4823 | ll<g>hr\t%0,%1 | |
4824 | ll<g>h\t%0,%1 | |
4825 | ll<g>hrl\t%0,%1" | |
4826 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4827 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4828 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4829 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3") |
4830 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 | 4831 | |
43a09b63 | 4832 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4833 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4834 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4835 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4836 | "TARGET_EXTIMM" |
4837 | "@ | |
56477c21 AS |
4838 | ll<g><hc>r\t%0,%1 |
4839 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4840 | [(set_attr "op_type" "RRE,RXY") |
4841 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4842 | |
43a09b63 | 4843 | ; llgh, llgc |
56477c21 AS |
4844 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4845 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4846 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4847 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4848 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4849 | [(set_attr "op_type" "RXY") |
4850 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4851 | |
4852 | (define_insn_and_split "*zero_extendhisi2_31" | |
4853 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4854 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4855 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4856 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4857 | "#" |
4858 | "&& reload_completed" | |
4859 | [(set (match_dup 0) (const_int 0)) | |
4860 | (parallel | |
4861 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4862 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4863 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4864 | |
cc7ab9b7 UW |
4865 | (define_insn_and_split "*zero_extendqisi2_31" |
4866 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4867 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4868 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4869 | "#" |
4870 | "&& reload_completed" | |
4871 | [(set (match_dup 0) (const_int 0)) | |
4872 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4873 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4874 | |
9db1d521 HP |
4875 | ; |
4876 | ; zero_extendqihi2 instruction pattern(s). | |
4877 | ; | |
4878 | ||
9db1d521 HP |
4879 | (define_expand "zero_extendqihi2" |
4880 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4881 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4882 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4883 | { |
4023fb28 UW |
4884 | operands[1] = gen_lowpart (HImode, operands[1]); |
4885 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4886 | DONE; | |
ec24698e | 4887 | }) |
9db1d521 | 4888 | |
4023fb28 | 4889 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4890 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4891 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4892 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4893 | "llgc\t%0,%1" |
9381e3f1 WG |
4894 | [(set_attr "op_type" "RXY") |
4895 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4896 | |
cc7ab9b7 UW |
4897 | (define_insn_and_split "*zero_extendqihi2_31" |
4898 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4899 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4900 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4901 | "#" |
4902 | "&& reload_completed" | |
4903 | [(set (match_dup 0) (const_int 0)) | |
4904 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4905 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4906 | |
609e7e80 | 4907 | ; |
9751ad6e | 4908 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4909 | ; |
4910 | ||
9751ad6e AK |
4911 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4912 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4913 | ; or emits the default pattern otherwise. | |
4914 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4915 | [(parallel |
9751ad6e AK |
4916 | [(set (match_operand:GPR 0 "register_operand" "") |
4917 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4918 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4919 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4920 | "TARGET_HARD_FLOAT" |
609e7e80 | 4921 | { |
65b1d8ea AK |
4922 | if (!TARGET_Z196) |
4923 | { | |
9751ad6e AK |
4924 | /* We don't provide emulation for TD|DD->SI. */ |
4925 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4926 | && <GPR:MODE>mode == SImode) | |
4927 | FAIL; | |
4928 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4929 | operands[1])); | |
65b1d8ea AK |
4930 | DONE; |
4931 | } | |
9751ad6e AK |
4932 | |
4933 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4934 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4935 | else | |
4936 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4937 | }) |
4938 | ||
9751ad6e AK |
4939 | ; (sf|df|tf)->unsigned (si|di) |
4940 | ||
4941 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4942 | ; machines. | |
4943 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4944 | [(parallel | |
4945 | [(set (match_operand:GPR 0 "register_operand" "") | |
4946 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4947 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4948 | (clobber (reg:CC CC_REGNUM))])] | |
4949 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4950 | { | |
4951 | rtx_code_label *label1 = gen_label_rtx (); | |
4952 | rtx_code_label *label2 = gen_label_rtx (); | |
4953 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4954 | REAL_VALUE_TYPE cmp, sub; | |
4955 | ||
4956 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4957 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4958 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4959 | ||
4960 | emit_cmp_and_jump_insns (operands[1], | |
4961 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4962 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4963 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4964 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4965 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4966 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
4967 | emit_jump (label2); | |
4968 | ||
4969 | emit_label (label1); | |
4970 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4971 | operands[1], | |
4972 | GEN_INT (BFP_RND_TOWARD_0))); | |
4973 | emit_label (label2); | |
4974 | DONE; | |
4975 | }) | |
4976 | ||
4977 | ; dd->unsigned di | |
4978 | ||
4979 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4980 | ; machines. | |
4981 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
4982 | [(parallel |
4983 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 4984 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 4985 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4986 | (clobber (reg:CC CC_REGNUM))])] |
4987 | ||
9751ad6e | 4988 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 4989 | { |
9751ad6e AK |
4990 | rtx_code_label *label1 = gen_label_rtx (); |
4991 | rtx_code_label *label2 = gen_label_rtx (); | |
4992 | rtx temp = gen_reg_rtx (TDmode); | |
4993 | REAL_VALUE_TYPE cmp, sub; | |
4994 | ||
4995 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4996 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4997 | ||
4998 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4999 | solution is doing the check and the subtraction in TD mode and using a | |
5000 | TD -> DI convert afterwards. */ | |
5001 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
5002 | temp = force_reg (TDmode, temp); | |
5003 | emit_cmp_and_jump_insns (temp, | |
5004 | const_double_from_real_value (cmp, TDmode), | |
5005 | LT, NULL_RTX, VOIDmode, 0, label1); | |
5006 | emit_insn (gen_subtd3 (temp, temp, | |
5007 | const_double_from_real_value (sub, TDmode))); | |
5008 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
5009 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
5010 | emit_jump (label2); | |
5011 | ||
5012 | emit_label (label1); | |
5013 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
5014 | GEN_INT (DFP_RND_TOWARD_0))); | |
5015 | emit_label (label2); | |
5016 | DONE; | |
609e7e80 | 5017 | }) |
cc7ab9b7 | 5018 | |
9751ad6e | 5019 | ; td->unsigned di |
9db1d521 | 5020 | |
9751ad6e AK |
5021 | ; Emulate the unsigned conversion with the signed version for pre z196 |
5022 | ; machines. | |
5023 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 5024 | [(parallel |
9751ad6e AK |
5025 | [(set (match_operand:DI 0 "register_operand" "") |
5026 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
5027 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 5028 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5029 | |
5030 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 5031 | { |
9751ad6e AK |
5032 | rtx_code_label *label1 = gen_label_rtx (); |
5033 | rtx_code_label *label2 = gen_label_rtx (); | |
5034 | rtx temp = gen_reg_rtx (TDmode); | |
5035 | REAL_VALUE_TYPE cmp, sub; | |
5036 | ||
5037 | operands[1] = force_reg (TDmode, operands[1]); | |
5038 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
5039 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
5040 | ||
5041 | emit_cmp_and_jump_insns (operands[1], | |
5042 | const_double_from_real_value (cmp, TDmode), | |
5043 | LT, NULL_RTX, VOIDmode, 0, label1); | |
5044 | emit_insn (gen_subtd3 (temp, operands[1], | |
5045 | const_double_from_real_value (sub, TDmode))); | |
5046 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
5047 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
5048 | emit_jump (label2); | |
5049 | ||
5050 | emit_label (label1); | |
5051 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
5052 | GEN_INT (DFP_RND_TOWARD_0))); | |
5053 | emit_label (label2); | |
5054 | DONE; | |
10bbf137 | 5055 | }) |
9db1d521 | 5056 | |
9751ad6e AK |
5057 | ; Just a dummy to make the code in the first expander a bit easier. |
5058 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
5059 | [(parallel |
5060 | [(set (match_operand:SI 0 "register_operand" "") | |
5061 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 5062 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 5063 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5064 | |
5065 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
5066 | { | |
5067 | FAIL; | |
5068 | }) | |
5069 | ||
65b1d8ea AK |
5070 | |
5071 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
5072 | ||
026bfe89 AK |
5073 | ; df -> unsigned di, vxe2: sf -> unsigned si |
5074 | ; clgdbr, clfebr, wclgdb, wclfeb | |
5075 | (define_insn "*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13" | |
5076 | [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v") | |
5077 | (unsigned_fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v"))) | |
5078 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
6e5b5de8 | 5079 | (clobber (reg:CC CC_REGNUM))] |
026bfe89 AK |
5080 | "TARGET_VX && TARGET_HARD_FLOAT |
5081 | && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" | |
9751ad6e | 5082 | "@ |
026bfe89 AK |
5083 | cl<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1,0 |
5084 | wcl<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2" | |
9751ad6e AK |
5085 | [(set_attr "op_type" "RRF,VRR") |
5086 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 5087 | |
9751ad6e | 5088 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
5089 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
5090 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
5091 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
5092 | [(set (match_operand:GPR 0 "register_operand" "=d") |
5093 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
5094 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 5095 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 5096 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 5097 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
5098 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
5099 | [(set_attr "op_type" "RRF") | |
5100 | (set_attr "type" "ftoi")]) | |
5101 | ||
b60cb710 AK |
5102 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
5103 | [(set (match_operand:GPR 0 "register_operand" "") | |
5104 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
5105 | "TARGET_HARD_FLOAT" | |
9db1d521 | 5106 | { |
b60cb710 | 5107 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 5108 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 5109 | DONE; |
10bbf137 | 5110 | }) |
9db1d521 | 5111 | |
026bfe89 AK |
5112 | ; df -> signed di, vxe2: sf -> signed si |
5113 | ; cgdbr, cfebr, wcgdb, wcfeb | |
5114 | (define_insn "*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13" | |
5115 | [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v") | |
5116 | (fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v"))) | |
5117 | (unspec:VX_CONV_INT [(match_operand:VX_CONV_INT 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
6e5b5de8 | 5118 | (clobber (reg:CC CC_REGNUM))] |
026bfe89 AK |
5119 | "TARGET_VX && TARGET_HARD_FLOAT |
5120 | && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" | |
6e5b5de8 | 5121 | "@ |
026bfe89 AK |
5122 | c<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1 |
5123 | wc<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2" | |
6e5b5de8 AK |
5124 | [(set_attr "op_type" "RRE,VRR") |
5125 | (set_attr "type" "ftoi")]) | |
5126 | ||
43a09b63 | 5127 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
5128 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5129 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5130 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5131 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 5132 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
5133 | "TARGET_HARD_FLOAT |
5134 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 5135 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 5136 | [(set_attr "op_type" "RRE") |
077dab3b | 5137 | (set_attr "type" "ftoi")]) |
9db1d521 | 5138 | |
6e5b5de8 AK |
5139 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5140 | [(parallel | |
5141 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5142 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5143 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5144 | (clobber (reg:CC CC_REGNUM))])] | |
5145 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
5146 | ; |
5147 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
5148 | ; | |
5149 | ||
99cd7dd0 AK |
5150 | (define_expand "fix_trunc<mode>di2" |
5151 | [(set (match_operand:DI 0 "register_operand" "") | |
5152 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 5153 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
5154 | { |
5155 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
5156 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 5157 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
5158 | DONE; |
5159 | }) | |
5160 | ||
609e7e80 | 5161 | ; cgxtr, cgdtr |
99cd7dd0 | 5162 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
5163 | [(set (match_operand:DI 0 "register_operand" "=d") |
5164 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
5165 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5166 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5167 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5168 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5169 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5170 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5171 | |
5172 | ||
f61a2c7d AK |
5173 | ; |
5174 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5175 | ; | |
5176 | ||
5177 | (define_expand "fix_trunctf<mode>2" | |
5178 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5179 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5180 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5181 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5182 | "TARGET_HARD_FLOAT" |
142cd70f | 5183 | "") |
9db1d521 | 5184 | |
9db1d521 | 5185 | |
9db1d521 | 5186 | ; |
142cd70f | 5187 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5188 | ; |
5189 | ||
609e7e80 | 5190 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5191 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5192 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5193 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5194 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5195 | "@ |
5196 | c<xde>g<bt>r\t%0,%1 | |
5197 | wcdgb\t%v0,%v1,0,0" | |
5198 | [(set_attr "op_type" "RRE,VRR") | |
5199 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5200 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5201 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5202 | |
026bfe89 | 5203 | ; cxfbr, cdfbr, cefbr, wcefb |
142cd70f | 5204 | (define_insn "floatsi<mode>2" |
026bfe89 AK |
5205 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
5206 | (float:BFP (match_operand:SI 1 "register_operand" "d,v")))] | |
142cd70f | 5207 | "TARGET_HARD_FLOAT" |
026bfe89 AK |
5208 | "@ |
5209 | c<xde>fbr\t%0,%1 | |
5210 | wcefb\t%v0,%v1,0,0" | |
5211 | [(set_attr "op_type" "RRE,VRR") | |
5212 | (set_attr "type" "itof<mode>" ) | |
5213 | (set_attr "cpu_facility" "*,vxe2") | |
5214 | (set_attr "enabled" "*,<SFSI>")]) | |
f61a2c7d | 5215 | |
65b1d8ea AK |
5216 | ; cxftr, cdftr |
5217 | (define_insn "floatsi<mode>2" | |
5218 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5219 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5220 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5221 | "c<xde>ftr\t%0,0,%1,0" | |
5222 | [(set_attr "op_type" "RRE") | |
5223 | (set_attr "type" "itof<mode>" )]) | |
5224 | ||
5225 | ; | |
5226 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5227 | ; | |
5228 | ||
026bfe89 AK |
5229 | (define_insn "*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13" |
5230 | [(set (match_operand:VX_CONV_BFP 0 "register_operand" "=f,v") | |
5231 | (unsigned_float:VX_CONV_BFP (match_operand:VX_CONV_INT 1 "register_operand" "d,v")))] | |
5232 | "TARGET_VX && TARGET_HARD_FLOAT | |
5233 | && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" | |
6e5b5de8 | 5234 | "@ |
026bfe89 AK |
5235 | c<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>br\t%0,0,%1,0 |
5236 | wc<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>b\t%v0,%v1,0,0" | |
6e5b5de8 AK |
5237 | [(set_attr "op_type" "RRE,VRR") |
5238 | (set_attr "type" "itofdf")]) | |
5239 | ||
65b1d8ea AK |
5240 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5241 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5242 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5243 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5244 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5245 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5246 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5247 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5248 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5249 | (set_attr "type" "itof<FP:mode>")]) |
5250 | ||
5251 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5252 | [(set (match_operand:FP 0 "register_operand" "") | |
5253 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5254 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5255 | |
9db1d521 HP |
5256 | ; |
5257 | ; truncdfsf2 instruction pattern(s). | |
5258 | ; | |
5259 | ||
142cd70f | 5260 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5261 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5262 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5263 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5264 | "@ |
5265 | ledbr\t%0,%1 | |
5266 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5267 | ; According to BFP rounding mode | |
5268 | [(set_attr "op_type" "RRE,VRR") | |
5269 | (set_attr "type" "ftruncdf") | |
285363a1 | 5270 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5271 | |
f61a2c7d | 5272 | ; |
142cd70f | 5273 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5274 | ; |
5275 | ||
142cd70f AK |
5276 | ; ldxbr, lexbr |
5277 | (define_insn "trunctf<mode>2" | |
5278 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5279 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5280 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5281 | "TARGET_HARD_FLOAT" |
5282 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5283 | [(set_attr "length" "6") |
9381e3f1 | 5284 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5285 | |
609e7e80 AK |
5286 | ; |
5287 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5288 | ; | |
5289 | ||
432d4670 AK |
5290 | |
5291 | (define_expand "trunctddd2" | |
5292 | [(parallel | |
5293 | [(set (match_operand:DD 0 "register_operand" "") | |
5294 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5295 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5296 | (clobber (scratch:TD))])] | |
5297 | "TARGET_HARD_DFP") | |
5298 | ||
5299 | (define_insn "*trunctddd2" | |
609e7e80 | 5300 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5301 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5302 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5303 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5304 | "TARGET_HARD_DFP" |
432d4670 | 5305 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5306 | [(set_attr "length" "6") |
9381e3f1 | 5307 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5308 | |
5309 | (define_insn "truncddsd2" | |
5310 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5311 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5312 | "TARGET_HARD_DFP" |
609e7e80 AK |
5313 | "ledtr\t%0,0,%1,0" |
5314 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5315 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5316 | |
feade5a8 AK |
5317 | (define_expand "trunctdsd2" |
5318 | [(parallel | |
d5a216fa | 5319 | [(set (match_dup 2) |
feade5a8 | 5320 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5321 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5322 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5323 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5324 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5325 | "TARGET_HARD_DFP" |
5326 | { | |
d5a216fa | 5327 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5328 | }) |
5329 | ||
9db1d521 | 5330 | ; |
142cd70f | 5331 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5332 | ; |
5333 | ||
2de2b3f9 | 5334 | ; wflls |
6e5b5de8 AK |
5335 | (define_insn "*extendsfdf2_z13" |
5336 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5337 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5338 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5339 | "@ |
5340 | ldebr\t%0,%1 | |
5341 | ldeb\t%0,%1 | |
5342 | wldeb\t%v0,%v1" | |
5343 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5344 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5345 | ||
142cd70f | 5346 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5347 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5348 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5349 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5350 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5351 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5352 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5353 | "@ |
142cd70f AK |
5354 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5355 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5356 | [(set_attr "op_type" "RRE,RXE") |
5357 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5358 | ||
5359 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5360 | [(set (match_operand:BFP 0 "register_operand" "") | |
5361 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5362 | "TARGET_HARD_FLOAT | |
5363 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5364 | |
609e7e80 AK |
5365 | ; |
5366 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5367 | ; | |
5368 | ||
5369 | (define_insn "extendddtd2" | |
5370 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5371 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5372 | "TARGET_HARD_DFP" |
609e7e80 AK |
5373 | "lxdtr\t%0,%1,0" |
5374 | [(set_attr "op_type" "RRF") | |
5375 | (set_attr "type" "fsimptf")]) | |
5376 | ||
5377 | (define_insn "extendsddd2" | |
5378 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5379 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5380 | "TARGET_HARD_DFP" |
609e7e80 AK |
5381 | "ldetr\t%0,%1,0" |
5382 | [(set_attr "op_type" "RRF") | |
5383 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5384 | |
feade5a8 AK |
5385 | (define_expand "extendsdtd2" |
5386 | [(set (match_dup 2) | |
5387 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5388 | (set (match_operand:TD 0 "register_operand" "") | |
5389 | (float_extend:TD (match_dup 2)))] | |
5390 | "TARGET_HARD_DFP" | |
5391 | { | |
5392 | operands[2] = gen_reg_rtx (DDmode); | |
5393 | }) | |
5394 | ||
d12a76f3 AK |
5395 | ; Binary Floating Point - load fp integer |
5396 | ||
5397 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5398 | ; For all of them the inexact exceptions are suppressed. | |
5399 | ||
5400 | ; fiebra, fidbra, fixbra | |
5401 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5402 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5403 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5404 | FPINT))] | |
5405 | "TARGET_Z196" | |
5406 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5407 | [(set_attr "op_type" "RRF") | |
5408 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5409 | ||
5410 | ; rint is supposed to raise an inexact exception so we can use the | |
5411 | ; older instructions. | |
5412 | ||
5413 | ; fiebr, fidbr, fixbr | |
5414 | (define_insn "rint<BFP:mode>2" | |
5415 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5416 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5417 | UNSPEC_FPINT_RINT))] | |
5418 | "" | |
5419 | "fi<BFP:xde>br\t%0,0,%1" | |
5420 | [(set_attr "op_type" "RRF") | |
5421 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5422 | ||
5423 | ||
5424 | ; Decimal Floating Point - load fp integer | |
5425 | ||
5426 | ; fidtr, fixtr | |
5427 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5428 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5429 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5430 | FPINT))] | |
5431 | "TARGET_HARD_DFP" | |
5432 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5433 | [(set_attr "op_type" "RRF") | |
5434 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5435 | ||
5436 | ; fidtr, fixtr | |
5437 | (define_insn "rint<DFP:mode>2" | |
5438 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5439 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5440 | UNSPEC_FPINT_RINT))] | |
5441 | "TARGET_HARD_DFP" | |
5442 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5443 | [(set_attr "op_type" "RRF") | |
5444 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5445 | ||
5446 | ; | |
35dd9a0e AK |
5447 | ; Binary <-> Decimal floating point trunc patterns |
5448 | ; | |
5449 | ||
5450 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5451 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5452 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5453 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5454 | (clobber (reg:CC CC_REGNUM)) |
5455 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5456 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5457 | "pfpo") |
5458 | ||
5459 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5460 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5461 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5462 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5463 | (clobber (reg:CC CC_REGNUM)) |
5464 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5465 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5466 | "pfpo") |
5467 | ||
5468 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5469 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5470 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5471 | (parallel | |
5472 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5473 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5474 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5475 | (clobber (reg:CC CC_REGNUM)) |
5476 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5477 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5478 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5479 | "TARGET_HARD_DFP |
35dd9a0e AK |
5480 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5481 | { | |
5482 | HOST_WIDE_INT flags; | |
5483 | ||
ced8d882 AK |
5484 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5485 | rounding mode of the target format needs to be used. */ | |
5486 | ||
35dd9a0e AK |
5487 | flags = (PFPO_CONVERT | |
5488 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5489 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5490 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5491 | |
5492 | operands[2] = GEN_INT (flags); | |
5493 | }) | |
5494 | ||
5495 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5496 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5497 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5498 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5499 | (parallel | |
2cf4c39e | 5500 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5501 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5502 | (clobber (reg:CC CC_REGNUM)) |
5503 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5504 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5505 | "TARGET_HARD_DFP |
35dd9a0e AK |
5506 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5507 | { | |
5508 | HOST_WIDE_INT flags; | |
5509 | ||
ced8d882 AK |
5510 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5511 | rounding mode of the target format needs to be used. */ | |
5512 | ||
35dd9a0e AK |
5513 | flags = (PFPO_CONVERT | |
5514 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5515 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5516 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5517 | |
5518 | operands[2] = GEN_INT (flags); | |
5519 | }) | |
5520 | ||
5521 | ; | |
5522 | ; Binary <-> Decimal floating point extend patterns | |
5523 | ; | |
5524 | ||
5525 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5526 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5527 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5528 | (clobber (reg:CC CC_REGNUM)) |
5529 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5530 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5531 | "pfpo") |
5532 | ||
5533 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5534 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5535 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5536 | (clobber (reg:CC CC_REGNUM)) |
5537 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5538 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5539 | "pfpo") |
5540 | ||
5541 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5542 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5543 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5544 | (parallel | |
5545 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5546 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5547 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5548 | (clobber (reg:CC CC_REGNUM)) |
5549 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5550 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5551 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5552 | "TARGET_HARD_DFP |
35dd9a0e AK |
5553 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5554 | { | |
5555 | HOST_WIDE_INT flags; | |
5556 | ||
ced8d882 AK |
5557 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5558 | rounding mode of the target format needs to be used. */ | |
5559 | ||
35dd9a0e AK |
5560 | flags = (PFPO_CONVERT | |
5561 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5562 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5563 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5564 | |
5565 | operands[2] = GEN_INT (flags); | |
5566 | }) | |
5567 | ||
5568 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5569 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5570 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5571 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5572 | (parallel | |
2cf4c39e | 5573 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5574 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5575 | (clobber (reg:CC CC_REGNUM)) |
5576 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5577 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5578 | "TARGET_HARD_DFP |
35dd9a0e AK |
5579 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5580 | { | |
5581 | HOST_WIDE_INT flags; | |
5582 | ||
ced8d882 AK |
5583 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5584 | rounding mode of the target format needs to be used. */ | |
5585 | ||
35dd9a0e AK |
5586 | flags = (PFPO_CONVERT | |
5587 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5588 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5589 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5590 | |
5591 | operands[2] = GEN_INT (flags); | |
5592 | }) | |
5593 | ||
5594 | ||
9db1d521 | 5595 | ;; |
fae778eb | 5596 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5597 | ;; |
fae778eb | 5598 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5599 | ; because of unpredictable Bits in Register for Halfword and Byte |
5600 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5601 | ||
07893d4f UW |
5602 | ;; |
5603 | ;;- Add instructions. | |
5604 | ;; | |
5605 | ||
1c7b1b7e UW |
5606 | ; |
5607 | ; addti3 instruction pattern(s). | |
5608 | ; | |
5609 | ||
085261c8 AK |
5610 | (define_expand "addti3" |
5611 | [(parallel | |
5612 | [(set (match_operand:TI 0 "register_operand" "") | |
5613 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5614 | (match_operand:TI 2 "general_operand" "") ) ) | |
5615 | (clobber (reg:CC CC_REGNUM))])] | |
5616 | "TARGET_ZARCH" | |
5617 | { | |
5618 | /* For z13 we have vaq which doesn't set CC. */ | |
5619 | if (TARGET_VX) | |
5620 | { | |
5621 | emit_insn (gen_rtx_SET (operands[0], | |
5622 | gen_rtx_PLUS (TImode, | |
5623 | copy_to_mode_reg (TImode, operands[1]), | |
5624 | copy_to_mode_reg (TImode, operands[2])))); | |
5625 | DONE; | |
5626 | } | |
5627 | }) | |
5628 | ||
5629 | (define_insn_and_split "*addti3" | |
5630 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5631 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5632 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5633 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5634 | "TARGET_ZARCH" |
1c7b1b7e UW |
5635 | "#" |
5636 | "&& reload_completed" | |
5637 | [(parallel | |
ae156f85 | 5638 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5639 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5640 | (match_dup 7))) | |
5641 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5642 | (parallel | |
a94a76a7 UW |
5643 | [(set (match_dup 3) (plus:DI |
5644 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5645 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5646 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5647 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5648 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5649 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5650 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5651 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5652 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5653 | [(set_attr "op_type" "*") | |
5654 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5655 | |
07893d4f UW |
5656 | ; |
5657 | ; adddi3 instruction pattern(s). | |
5658 | ; | |
5659 | ||
3298c037 AK |
5660 | (define_expand "adddi3" |
5661 | [(parallel | |
963fc8d0 | 5662 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5663 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5664 | (match_operand:DI 2 "general_operand" ""))) | |
5665 | (clobber (reg:CC CC_REGNUM))])] | |
5666 | "" | |
5667 | "") | |
5668 | ||
07893d4f UW |
5669 | (define_insn "*adddi3_sign" |
5670 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5671 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5672 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5673 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5674 | "TARGET_ZARCH" |
07893d4f | 5675 | "@ |
d40c829f UW |
5676 | agfr\t%0,%2 |
5677 | agf\t%0,%2" | |
65b1d8ea AK |
5678 | [(set_attr "op_type" "RRE,RXY") |
5679 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5680 | |
5681 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5682 | [(set (reg CC_REGNUM) |
3e4be43f | 5683 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5684 | (match_operand:DI 1 "register_operand" "0,0")) |
5685 | (const_int 0))) | |
5686 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5687 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5688 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5689 | "@ |
d40c829f UW |
5690 | algfr\t%0,%2 |
5691 | algf\t%0,%2" | |
9381e3f1 WG |
5692 | [(set_attr "op_type" "RRE,RXY") |
5693 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5694 | |
5695 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5696 | [(set (reg CC_REGNUM) |
3e4be43f | 5697 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5698 | (match_operand:DI 1 "register_operand" "0,0")) |
5699 | (const_int 0))) | |
5700 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5701 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5702 | "@ |
d40c829f UW |
5703 | algfr\t%0,%2 |
5704 | algf\t%0,%2" | |
9381e3f1 WG |
5705 | [(set_attr "op_type" "RRE,RXY") |
5706 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5707 | |
5708 | (define_insn "*adddi3_zero" | |
5709 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5710 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5711 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5712 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5713 | "TARGET_ZARCH" |
07893d4f | 5714 | "@ |
d40c829f UW |
5715 | algfr\t%0,%2 |
5716 | algf\t%0,%2" | |
9381e3f1 WG |
5717 | [(set_attr "op_type" "RRE,RXY") |
5718 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5719 | |
e69166de | 5720 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5721 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5722 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5723 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5724 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 5725 | "!TARGET_ZARCH" |
e69166de UW |
5726 | "#" |
5727 | "&& reload_completed" | |
5728 | [(parallel | |
ae156f85 | 5729 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5730 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5731 | (match_dup 7))) | |
5732 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5733 | (parallel | |
a94a76a7 UW |
5734 | [(set (match_dup 3) (plus:SI |
5735 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5736 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5737 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5738 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5739 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5740 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5741 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5742 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5743 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5744 | |
3298c037 AK |
5745 | ; |
5746 | ; addsi3 instruction pattern(s). | |
5747 | ; | |
5748 | ||
5749 | (define_expand "addsi3" | |
07893d4f | 5750 | [(parallel |
963fc8d0 | 5751 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5752 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5753 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5754 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5755 | "" |
07893d4f | 5756 | "") |
9db1d521 | 5757 | |
3298c037 AK |
5758 | (define_insn "*addsi3_sign" |
5759 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5760 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5761 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5762 | (clobber (reg:CC CC_REGNUM))] | |
5763 | "" | |
5764 | "@ | |
5765 | ah\t%0,%2 | |
5766 | ahy\t%0,%2" | |
65b1d8ea | 5767 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5768 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5769 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5770 | |
9db1d521 | 5771 | ; |
3298c037 | 5772 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5773 | ; |
9db1d521 | 5774 | |
65b1d8ea | 5775 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5776 | (define_insn "*add<mode>3" |
3e4be43f UW |
5777 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5778 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5779 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5780 | (clobber (reg:CC CC_REGNUM))] |
5781 | "" | |
ec24698e | 5782 | "@ |
3298c037 | 5783 | a<g>r\t%0,%2 |
65b1d8ea | 5784 | a<g>rk\t%0,%1,%2 |
3298c037 | 5785 | a<g>hi\t%0,%h2 |
65b1d8ea | 5786 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5787 | al<g>fi\t%0,%2 |
5788 | sl<g>fi\t%0,%n2 | |
5789 | a<g>\t%0,%2 | |
963fc8d0 AK |
5790 | a<y>\t%0,%2 |
5791 | a<g>si\t%0,%c2" | |
65b1d8ea | 5792 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5793 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5794 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5795 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5796 | |
65b1d8ea | 5797 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5798 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5799 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5800 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5801 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5802 | (match_dup 1))) |
65b1d8ea | 5803 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5804 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5805 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5806 | "@ |
3298c037 | 5807 | al<g>r\t%0,%2 |
65b1d8ea | 5808 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5809 | al<g>fi\t%0,%2 |
5810 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5811 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5812 | al<g>\t%0,%2 |
963fc8d0 AK |
5813 | al<y>\t%0,%2 |
5814 | al<g>si\t%0,%c2" | |
65b1d8ea | 5815 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5816 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5817 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5818 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5819 | |
65b1d8ea | 5820 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5821 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5822 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5823 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5824 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5825 | (match_dup 1))) |
65b1d8ea | 5826 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5827 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5828 | "@ |
3298c037 | 5829 | al<g>r\t%0,%2 |
65b1d8ea | 5830 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5831 | al<g>\t%0,%2 |
5832 | al<y>\t%0,%2" | |
65b1d8ea | 5833 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5834 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5835 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5836 | |
65b1d8ea | 5837 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5838 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5839 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5840 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5841 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5842 | (match_dup 2))) |
3e4be43f | 5843 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5844 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5845 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5846 | "@ |
3298c037 | 5847 | al<g>r\t%0,%2 |
65b1d8ea | 5848 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5849 | al<g>fi\t%0,%2 |
5850 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5851 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5852 | al<g>\t%0,%2 |
963fc8d0 AK |
5853 | al<y>\t%0,%2 |
5854 | al<g>si\t%0,%c2" | |
65b1d8ea | 5855 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5856 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5857 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5858 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5859 | |
65b1d8ea | 5860 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5861 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5862 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5863 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5864 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5865 | (match_dup 2))) |
65b1d8ea | 5866 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5867 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5868 | "@ |
3298c037 | 5869 | al<g>r\t%0,%2 |
65b1d8ea | 5870 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5871 | al<g>\t%0,%2 |
5872 | al<y>\t%0,%2" | |
65b1d8ea | 5873 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5874 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5875 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5876 | |
65b1d8ea | 5877 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5878 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5879 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5880 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5881 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5882 | (const_int 0))) |
3e4be43f | 5883 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5884 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5885 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5886 | "@ |
3298c037 | 5887 | al<g>r\t%0,%2 |
65b1d8ea | 5888 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5889 | al<g>fi\t%0,%2 |
5890 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5891 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5892 | al<g>\t%0,%2 |
963fc8d0 AK |
5893 | al<y>\t%0,%2 |
5894 | al<g>si\t%0,%c2" | |
65b1d8ea | 5895 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5896 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5897 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5898 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5899 | |
65b1d8ea | 5900 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5901 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5902 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5903 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5904 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5905 | (const_int 0))) |
65b1d8ea | 5906 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5907 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5908 | "@ |
3298c037 | 5909 | al<g>r\t%0,%2 |
65b1d8ea | 5910 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5911 | al<g>\t%0,%2 |
5912 | al<y>\t%0,%2" | |
65b1d8ea | 5913 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5914 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5915 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5916 | |
65b1d8ea | 5917 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5918 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5919 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5920 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5921 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5922 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5923 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5924 | "@ |
3298c037 | 5925 | al<g>r\t%0,%2 |
65b1d8ea | 5926 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5927 | al<g>\t%0,%2 |
5928 | al<y>\t%0,%2" | |
65b1d8ea | 5929 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5930 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5931 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5932 | |
963fc8d0 | 5933 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5934 | (define_insn "*add<mode>3_imm_cc" |
5935 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5936 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5937 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5938 | (const_int 0))) |
3e4be43f | 5939 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5940 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5941 | "s390_match_ccmode (insn, CCAmode) | |
5942 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5943 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5944 | /* Avoid INT32_MIN on 32 bit. */ | |
5945 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5946 | "@ |
3298c037 | 5947 | a<g>hi\t%0,%h2 |
65b1d8ea | 5948 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5949 | a<g>fi\t%0,%2 |
5950 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5951 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5952 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5953 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5954 | |
7d2fd075 AK |
5955 | (define_insn "*adddi3_sign" |
5956 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5957 | (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
5958 | (match_operand:DI 1 "register_operand" "0"))) | |
5959 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 5960 | "TARGET_Z14" |
7d2fd075 AK |
5961 | "agh\t%0,%2" |
5962 | [(set_attr "op_type" "RXY")]) | |
5963 | ||
4caa6bab AK |
5964 | |
5965 | ; Jump to label OP3 if OP1 + OP2 results in a signed overflow | |
5966 | ||
5967 | ; addv_const_operand accepts all constants which can be handled | |
5968 | ; without reloads. These will be handled primarily by | |
5969 | ; "*addv<mode>3_ccoverflow_const" which doesn't provide a register | |
5970 | ; alternative. Hence we have to match the operand exactly. | |
5971 | ; For immediates we have to avoid the SIGN_EXTEND around OP2. | |
5972 | (define_expand "addv<mode>4" | |
5973 | [(parallel | |
5974 | [(set (reg:CCO CC_REGNUM) | |
5975 | (compare:CCO (plus:<DBL> | |
5976 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand")) | |
5977 | (match_dup 4)) | |
5978 | (sign_extend:<DBL> (plus:GPR (match_dup 1) | |
5979 | (match_operand:GPR 2 "general_operand"))))) | |
5980 | (set (match_operand:GPR 0 "nonimmediate_operand") | |
5981 | (plus:GPR (match_dup 1) (match_dup 2)))]) | |
5982 | (set (pc) | |
5983 | (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) | |
5984 | (label_ref (match_operand 3)) | |
5985 | (pc)))] | |
5986 | "" | |
5987 | { | |
5988 | if (CONSTANT_P (operands[2]) | |
5989 | && !addv_const_operand (operands[2], GET_MODE (operands[2]))) | |
5990 | operands[2] = force_reg (<GPR:MODE>mode, operands[2]); | |
5991 | ||
5992 | if (GET_MODE (operands[2]) != VOIDmode) | |
5993 | operands[4] = gen_rtx_SIGN_EXTEND (<DBL>mode, operands[2]); | |
5994 | else | |
5995 | /* This is what CSE does when propagating a constant into the pattern. */ | |
5996 | operands[4] = simplify_unary_operation (SIGN_EXTEND, <GPR:DBL>mode, operands[2], <GPR:MODE>mode); | |
5997 | }) | |
5998 | ||
5999 | ; ark, agrk, ar, ahi, ahik, aghik, a, ay, agr, aghi, ag, asi, agsi | |
6000 | (define_insn "*addv<mode>3_ccoverflow" | |
6001 | [(set (reg CC_REGNUM) | |
6002 | (compare (plus:<DBL> | |
6003 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d,0,0,0")) | |
6004 | (sign_extend:<DBL> (match_operand:GPR 2 "general_operand" " d,d,K,K,R,T,C"))) | |
6005 | (sign_extend:<DBL> (plus:GPR (match_dup 1) (match_dup 2))))) | |
6006 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S") | |
6007 | (plus:GPR (match_dup 1) (match_dup 2)))] | |
6008 | "s390_match_ccmode (insn, CCOmode)" | |
6009 | "@ | |
6010 | a<g>r\t%0,%2 | |
6011 | a<g>rk\t%0,%1,%2 | |
6012 | a<g>hi\t%0,%h2 | |
6013 | a<g>hik\t%0,%1,%h2 | |
6014 | a<g>\t%0,%2 | |
6015 | a<y>\t%0,%2 | |
6016 | a<g>si\t%0,%c2" | |
6017 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RX<Y>,RXY,SIY") | |
6018 | (set_attr "cpu_facility" "*,z196,*,z196,*,longdisp,z10") | |
6019 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*, | |
6020 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
6021 | ||
6022 | ; ahi, aghi, ahik, aghik, asi, agsi | |
6023 | (define_insn "*addv<mode>3_ccoverflow_const" | |
6024 | [(set (reg CC_REGNUM) | |
6025 | (compare (plus:<DBL> | |
6026 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0")) | |
6027 | (match_operand:<DBL> 2 "addv_const_operand" "K,K,C")) | |
6028 | (sign_extend:<DBL> (plus:GPR (match_dup 1) (match_dup 2))))) | |
6029 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,S") | |
6030 | (plus:GPR (match_dup 1) (match_dup 2)))] | |
6031 | "s390_match_ccmode (insn, CCOmode)" | |
6032 | "@ | |
6033 | a<g>hi\t%0,%h2 | |
6034 | a<g>hik\t%0,%1,%h2 | |
6035 | a<g>si\t%0,%c2" | |
6036 | [(set_attr "op_type" "RI,RIE,SIY") | |
6037 | (set_attr "cpu_facility" "*,z196,z10") | |
6038 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
6039 | ||
6040 | ||
9db1d521 | 6041 | ; |
609e7e80 | 6042 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6043 | ; |
6044 | ||
609e7e80 | 6045 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 6046 | ; FIXME: wfadb does not clobber cc |
142cd70f | 6047 | (define_insn "add<mode>3" |
2de2b3f9 AK |
6048 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6049 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
6050 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6051 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6052 | "TARGET_HARD_FLOAT" |
9db1d521 | 6053 | "@ |
62d3f261 AK |
6054 | a<xde>tr\t%0,%1,%2 |
6055 | a<xde>br\t%0,%2 | |
6e5b5de8 | 6056 | a<xde>b\t%0,%2 |
2de2b3f9 AK |
6057 | wfadb\t%v0,%v1,%v2 |
6058 | wfasb\t%v0,%v1,%v2" | |
6059 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6060 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6061 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6062 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6063 | |
609e7e80 | 6064 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 6065 | (define_insn "*add<mode>3_cc" |
ae156f85 | 6066 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6067 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
6068 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6069 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6070 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6071 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6072 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6073 | "@ |
62d3f261 AK |
6074 | a<xde>tr\t%0,%1,%2 |
6075 | a<xde>br\t%0,%2 | |
f61a2c7d | 6076 | a<xde>b\t%0,%2" |
62d3f261 AK |
6077 | [(set_attr "op_type" "RRF,RRE,RXE") |
6078 | (set_attr "type" "fsimp<mode>") | |
6079 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6080 | |
609e7e80 | 6081 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 6082 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 6083 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6084 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
6085 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6086 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6087 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6088 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6089 | "@ |
62d3f261 AK |
6090 | a<xde>tr\t%0,%1,%2 |
6091 | a<xde>br\t%0,%2 | |
f61a2c7d | 6092 | a<xde>b\t%0,%2" |
62d3f261 AK |
6093 | [(set_attr "op_type" "RRF,RRE,RXE") |
6094 | (set_attr "type" "fsimp<mode>") | |
6095 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6096 | |
72a4ddf2 AK |
6097 | ; |
6098 | ; Pointer add instruction patterns | |
6099 | ; | |
6100 | ||
6101 | ; This will match "*la_64" | |
6102 | (define_expand "addptrdi3" | |
6103 | [(set (match_operand:DI 0 "register_operand" "") | |
6104 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
6105 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
6106 | "TARGET_64BIT" | |
6107 | { | |
72a4ddf2 AK |
6108 | if (GET_CODE (operands[2]) == CONST_INT) |
6109 | { | |
357ddc7d TV |
6110 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6111 | ||
72a4ddf2 AK |
6112 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6113 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6114 | { | |
6115 | operands[2] = force_const_mem (DImode, operands[2]); | |
6116 | operands[2] = force_reg (DImode, operands[2]); | |
6117 | } | |
6118 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6119 | operands[2] = force_reg (DImode, operands[2]); | |
6120 | } | |
6121 | }) | |
6122 | ||
6123 | ; For 31 bit we have to prevent the generated pattern from matching | |
6124 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
6125 | ; match "force_la_31". | |
6126 | (define_expand "addptrsi3" | |
6127 | [(parallel | |
6128 | [(set (match_operand:SI 0 "register_operand" "") | |
6129 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
6130 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
6131 | (use (const_int 0))])] | |
6132 | "!TARGET_64BIT" | |
6133 | { | |
72a4ddf2 AK |
6134 | if (GET_CODE (operands[2]) == CONST_INT) |
6135 | { | |
357ddc7d TV |
6136 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6137 | ||
72a4ddf2 AK |
6138 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6139 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6140 | { | |
6141 | operands[2] = force_const_mem (SImode, operands[2]); | |
6142 | operands[2] = force_reg (SImode, operands[2]); | |
6143 | } | |
6144 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6145 | operands[2] = force_reg (SImode, operands[2]); | |
6146 | } | |
6147 | }) | |
9db1d521 HP |
6148 | |
6149 | ;; | |
6150 | ;;- Subtract instructions. | |
6151 | ;; | |
6152 | ||
1c7b1b7e UW |
6153 | ; |
6154 | ; subti3 instruction pattern(s). | |
6155 | ; | |
6156 | ||
085261c8 AK |
6157 | (define_expand "subti3" |
6158 | [(parallel | |
6159 | [(set (match_operand:TI 0 "register_operand" "") | |
6160 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
6161 | (match_operand:TI 2 "general_operand" "") ) ) | |
6162 | (clobber (reg:CC CC_REGNUM))])] | |
6163 | "TARGET_ZARCH" | |
6164 | { | |
2d71f118 | 6165 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
6166 | if (TARGET_VX) |
6167 | { | |
6168 | emit_insn (gen_rtx_SET (operands[0], | |
6169 | gen_rtx_MINUS (TImode, | |
6170 | operands[1], | |
6171 | copy_to_mode_reg (TImode, operands[2])))); | |
6172 | DONE; | |
6173 | } | |
6174 | }) | |
6175 | ||
6176 | (define_insn_and_split "*subti3" | |
6177 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
6178 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
6179 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 6180 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6181 | "TARGET_ZARCH" |
1c7b1b7e UW |
6182 | "#" |
6183 | "&& reload_completed" | |
6184 | [(parallel | |
ae156f85 | 6185 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
6186 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
6187 | (match_dup 7))) | |
6188 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
6189 | (parallel | |
6190 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6191 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6192 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
6193 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
6194 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
6195 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
6196 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
6197 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
6198 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
6199 | [(set_attr "op_type" "*") | |
6200 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 6201 | |
9db1d521 HP |
6202 | ; |
6203 | ; subdi3 instruction pattern(s). | |
6204 | ; | |
6205 | ||
3298c037 AK |
6206 | (define_expand "subdi3" |
6207 | [(parallel | |
6208 | [(set (match_operand:DI 0 "register_operand" "") | |
6209 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
6210 | (match_operand:DI 2 "general_operand" ""))) | |
6211 | (clobber (reg:CC CC_REGNUM))])] | |
6212 | "" | |
6213 | "") | |
6214 | ||
07893d4f UW |
6215 | (define_insn "*subdi3_sign" |
6216 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6217 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6218 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6219 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6220 | "TARGET_ZARCH" |
07893d4f | 6221 | "@ |
d40c829f UW |
6222 | sgfr\t%0,%2 |
6223 | sgf\t%0,%2" | |
9381e3f1 | 6224 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
6225 | (set_attr "z10prop" "z10_c,*") |
6226 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
6227 | |
6228 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 6229 | [(set (reg CC_REGNUM) |
07893d4f | 6230 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6231 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6232 | (const_int 0))) |
6233 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6234 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 6235 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6236 | "@ |
d40c829f UW |
6237 | slgfr\t%0,%2 |
6238 | slgf\t%0,%2" | |
9381e3f1 WG |
6239 | [(set_attr "op_type" "RRE,RXY") |
6240 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6241 | |
6242 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 6243 | [(set (reg CC_REGNUM) |
07893d4f | 6244 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6245 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6246 | (const_int 0))) |
6247 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6248 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6249 | "@ |
d40c829f UW |
6250 | slgfr\t%0,%2 |
6251 | slgf\t%0,%2" | |
9381e3f1 WG |
6252 | [(set_attr "op_type" "RRE,RXY") |
6253 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6254 | |
6255 | (define_insn "*subdi3_zero" | |
6256 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6257 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6258 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6259 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6260 | "TARGET_ZARCH" |
07893d4f | 6261 | "@ |
d40c829f UW |
6262 | slgfr\t%0,%2 |
6263 | slgf\t%0,%2" | |
9381e3f1 WG |
6264 | [(set_attr "op_type" "RRE,RXY") |
6265 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6266 | |
e69166de UW |
6267 | (define_insn_and_split "*subdi3_31z" |
6268 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6269 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6270 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6271 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6272 | "!TARGET_ZARCH" |
e69166de UW |
6273 | "#" |
6274 | "&& reload_completed" | |
6275 | [(parallel | |
ae156f85 | 6276 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6277 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6278 | (match_dup 7))) | |
6279 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6280 | (parallel | |
6281 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6282 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6283 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6284 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6285 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6286 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6287 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6288 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6289 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6290 | |
3298c037 AK |
6291 | ; |
6292 | ; subsi3 instruction pattern(s). | |
6293 | ; | |
6294 | ||
6295 | (define_expand "subsi3" | |
07893d4f | 6296 | [(parallel |
3298c037 AK |
6297 | [(set (match_operand:SI 0 "register_operand" "") |
6298 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6299 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6300 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6301 | "" |
07893d4f | 6302 | "") |
9db1d521 | 6303 | |
3298c037 AK |
6304 | (define_insn "*subsi3_sign" |
6305 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6306 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6307 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6308 | (clobber (reg:CC CC_REGNUM))] | |
6309 | "" | |
6310 | "@ | |
6311 | sh\t%0,%2 | |
6312 | shy\t%0,%2" | |
65b1d8ea | 6313 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6314 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6315 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6316 | |
9db1d521 | 6317 | ; |
3298c037 | 6318 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6319 | ; |
6320 | ||
65b1d8ea | 6321 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6322 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6323 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6324 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6325 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6326 | (clobber (reg:CC CC_REGNUM))] |
6327 | "" | |
6328 | "@ | |
6329 | s<g>r\t%0,%2 | |
65b1d8ea | 6330 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6331 | s<g>\t%0,%2 |
6332 | s<y>\t%0,%2" | |
65b1d8ea | 6333 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6334 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6335 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6336 | |
65b1d8ea | 6337 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6338 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6339 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6340 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6341 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6342 | (match_dup 1))) |
65b1d8ea | 6343 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6344 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6345 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6346 | "@ |
3298c037 | 6347 | sl<g>r\t%0,%2 |
65b1d8ea | 6348 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6349 | sl<g>\t%0,%2 |
6350 | sl<y>\t%0,%2" | |
65b1d8ea | 6351 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6352 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6353 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6354 | |
65b1d8ea | 6355 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6356 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6357 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6358 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6359 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6360 | (match_dup 1))) |
65b1d8ea | 6361 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6362 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6363 | "@ |
3298c037 | 6364 | sl<g>r\t%0,%2 |
65b1d8ea | 6365 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6366 | sl<g>\t%0,%2 |
6367 | sl<y>\t%0,%2" | |
65b1d8ea | 6368 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6369 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6370 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6371 | |
65b1d8ea | 6372 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6373 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6374 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6375 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6376 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6377 | (const_int 0))) |
65b1d8ea | 6378 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6379 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6380 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6381 | "@ |
3298c037 | 6382 | sl<g>r\t%0,%2 |
65b1d8ea | 6383 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6384 | sl<g>\t%0,%2 |
6385 | sl<y>\t%0,%2" | |
65b1d8ea | 6386 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6387 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6388 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6389 | |
65b1d8ea | 6390 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6391 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6392 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6393 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6394 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6395 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6396 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6397 | "s390_match_ccmode (insn, CCL3mode)" |
6398 | "@ | |
3298c037 | 6399 | sl<g>r\t%0,%2 |
65b1d8ea | 6400 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6401 | sl<g>\t%0,%2 |
6402 | sl<y>\t%0,%2" | |
65b1d8ea | 6403 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6404 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6405 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6406 | |
65b1d8ea | 6407 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6408 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6409 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6410 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6411 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6412 | (const_int 0))) |
65b1d8ea | 6413 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6414 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6415 | "@ |
3298c037 | 6416 | sl<g>r\t%0,%2 |
65b1d8ea | 6417 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6418 | sl<g>\t%0,%2 |
6419 | sl<y>\t%0,%2" | |
65b1d8ea | 6420 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6421 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6422 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6423 | |
9db1d521 | 6424 | |
65b1d8ea | 6425 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6426 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6427 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6428 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6429 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6430 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6431 | "s390_match_ccmode (insn, CCL3mode)" |
6432 | "@ | |
3298c037 | 6433 | sl<g>r\t%0,%2 |
65b1d8ea | 6434 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6435 | sl<g>\t%0,%2 |
6436 | sl<y>\t%0,%2" | |
65b1d8ea | 6437 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6438 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6439 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6440 | |
7d2fd075 AK |
6441 | (define_insn "*subdi3_sign" |
6442 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6443 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6444 | (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) | |
6445 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 6446 | "TARGET_Z14" |
7d2fd075 AK |
6447 | "sgh\t%0,%2" |
6448 | [(set_attr "op_type" "RXY")]) | |
6449 | ||
4caa6bab AK |
6450 | ; Jump to label OP3 if OP1 - OP2 results in a signed overflow |
6451 | (define_expand "subv<mode>4" | |
6452 | [(parallel | |
6453 | [(set (reg:CCO CC_REGNUM) | |
6454 | (compare:CCO (minus:<DBL> | |
6455 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand")) | |
6456 | (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand"))) | |
6457 | (sign_extend:<DBL> (minus:GPR (match_dup 1) (match_dup 2))))) | |
6458 | (set (match_operand:GPR 0 "nonimmediate_operand") | |
6459 | (minus:GPR (match_dup 1) (match_dup 2)))]) | |
6460 | (set (pc) | |
6461 | (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) | |
6462 | (label_ref (match_operand 3)) | |
6463 | (pc)))] | |
6464 | "") | |
6465 | ||
6466 | ; sr, s, sy, sgr, sg, srk, sgrk | |
6467 | (define_insn "*subv<mode>3_ccoverflow" | |
6468 | [(set (reg CC_REGNUM) | |
6469 | (compare (minus:<DBL> | |
6470 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "0,d,0,0")) | |
6471 | (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand" "d,d,R,T"))) | |
6472 | (sign_extend:<DBL> (minus:GPR (match_dup 1) (match_dup 2))))) | |
6473 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
6474 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
6475 | "s390_match_ccmode (insn, CCOmode)" | |
6476 | "@ | |
6477 | s<g>r\t%0,%2 | |
6478 | s<g>rk\t%0,%1,%2 | |
6479 | s<g>\t%0,%2 | |
6480 | s<y>\t%0,%2" | |
6481 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") | |
6482 | (set_attr "cpu_facility" "*,z196,*,longdisp") | |
6483 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
6484 | ||
9db1d521 HP |
6485 | |
6486 | ; | |
609e7e80 | 6487 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6488 | ; |
6489 | ||
2de2b3f9 | 6490 | ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? |
d46f24b6 | 6491 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6492 | (define_insn "sub<mode>3" |
2de2b3f9 AK |
6493 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6494 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
6495 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6496 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6497 | "TARGET_HARD_FLOAT" |
9db1d521 | 6498 | "@ |
62d3f261 AK |
6499 | s<xde>tr\t%0,%1,%2 |
6500 | s<xde>br\t%0,%2 | |
6e5b5de8 | 6501 | s<xde>b\t%0,%2 |
2de2b3f9 AK |
6502 | wfsdb\t%v0,%v1,%v2 |
6503 | wfssb\t%v0,%v1,%v2" | |
6504 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6505 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6506 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6507 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6508 | |
d46f24b6 | 6509 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6510 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6511 | [(set (reg CC_REGNUM) |
62d3f261 | 6512 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
2de2b3f9 | 6513 | (match_operand:FP 2 "general_operand" "f,f,R")) |
609e7e80 | 6514 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6515 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6516 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6517 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6518 | "@ |
62d3f261 AK |
6519 | s<xde>tr\t%0,%1,%2 |
6520 | s<xde>br\t%0,%2 | |
f61a2c7d | 6521 | s<xde>b\t%0,%2" |
62d3f261 AK |
6522 | [(set_attr "op_type" "RRF,RRE,RXE") |
6523 | (set_attr "type" "fsimp<mode>") | |
6524 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6525 | |
d46f24b6 | 6526 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6527 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6528 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6529 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6530 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6531 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6532 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6533 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6534 | "@ |
62d3f261 AK |
6535 | s<xde>tr\t%0,%1,%2 |
6536 | s<xde>br\t%0,%2 | |
f61a2c7d | 6537 | s<xde>b\t%0,%2" |
62d3f261 AK |
6538 | [(set_attr "op_type" "RRF,RRE,RXE") |
6539 | (set_attr "type" "fsimp<mode>") | |
6540 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6541 | |
9db1d521 | 6542 | |
e69166de UW |
6543 | ;; |
6544 | ;;- Conditional add/subtract instructions. | |
6545 | ;; | |
6546 | ||
6547 | ; | |
9a91a21f | 6548 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6549 | ; |
6550 | ||
a996720c UW |
6551 | ; the following 4 patterns are used when the result of an add with |
6552 | ; carry is checked for an overflow condition | |
6553 | ||
6554 | ; op1 + op2 + c < op1 | |
6555 | ||
6556 | ; alcr, alc, alcgr, alcg | |
6557 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6558 | [(set (reg CC_REGNUM) | |
6559 | (compare | |
6560 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6561 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6562 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6563 | (match_dup 1))) |
6564 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6565 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6566 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6567 | "@ |
6568 | alc<g>r\t%0,%2 | |
6569 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6570 | [(set_attr "op_type" "RRE,RXY") |
6571 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6572 | |
6573 | ; alcr, alc, alcgr, alcg | |
6574 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6575 | [(set (reg CC_REGNUM) | |
6576 | (compare | |
6577 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6578 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6579 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6580 | (match_dup 1))) |
6581 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6582 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6583 | "@ |
6584 | alc<g>r\t%0,%2 | |
6585 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6586 | [(set_attr "op_type" "RRE,RXY") |
6587 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6588 | |
6589 | ; op1 + op2 + c < op2 | |
6590 | ||
6591 | ; alcr, alc, alcgr, alcg | |
6592 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6593 | [(set (reg CC_REGNUM) | |
6594 | (compare | |
6595 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6596 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6597 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6598 | (match_dup 2))) |
6599 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6600 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6601 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6602 | "@ |
6603 | alc<g>r\t%0,%2 | |
6604 | alc<g>\t%0,%2" | |
6605 | [(set_attr "op_type" "RRE,RXY")]) | |
6606 | ||
6607 | ; alcr, alc, alcgr, alcg | |
6608 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6609 | [(set (reg CC_REGNUM) | |
6610 | (compare | |
6611 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6612 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6613 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6614 | (match_dup 2))) |
6615 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6616 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6617 | "@ |
6618 | alc<g>r\t%0,%2 | |
6619 | alc<g>\t%0,%2" | |
6620 | [(set_attr "op_type" "RRE,RXY")]) | |
6621 | ||
43a09b63 | 6622 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6623 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6624 | [(set (reg CC_REGNUM) |
e69166de | 6625 | (compare |
a94a76a7 UW |
6626 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6627 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6628 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6629 | (const_int 0))) |
9a91a21f | 6630 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6631 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
8cc6307c | 6632 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6633 | "@ |
9a91a21f AS |
6634 | alc<g>r\t%0,%2 |
6635 | alc<g>\t%0,%2" | |
e69166de UW |
6636 | [(set_attr "op_type" "RRE,RXY")]) |
6637 | ||
43a09b63 | 6638 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6639 | (define_insn "*add<mode>3_alc" |
6640 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6641 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6642 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6643 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6644 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6645 | "" |
e69166de | 6646 | "@ |
9a91a21f AS |
6647 | alc<g>r\t%0,%2 |
6648 | alc<g>\t%0,%2" | |
e69166de UW |
6649 | [(set_attr "op_type" "RRE,RXY")]) |
6650 | ||
43a09b63 | 6651 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6652 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6653 | [(set (reg CC_REGNUM) |
e69166de | 6654 | (compare |
9a91a21f | 6655 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6656 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6657 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6658 | (const_int 0))) |
9a91a21f AS |
6659 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6660 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
8cc6307c | 6661 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6662 | "@ |
9a91a21f AS |
6663 | slb<g>r\t%0,%2 |
6664 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6665 | [(set_attr "op_type" "RRE,RXY") |
6666 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6667 | |
43a09b63 | 6668 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6669 | (define_insn "*sub<mode>3_slb" |
6670 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6671 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6672 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6673 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6674 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6675 | "" |
e69166de | 6676 | "@ |
9a91a21f AS |
6677 | slb<g>r\t%0,%2 |
6678 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6679 | [(set_attr "op_type" "RRE,RXY") |
6680 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6681 | |
9a91a21f AS |
6682 | (define_expand "add<mode>cc" |
6683 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6684 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6685 | (match_operand:GPR 2 "register_operand" "") |
6686 | (match_operand:GPR 3 "const_int_operand" "")] | |
8cc6307c | 6687 | "" |
9381e3f1 | 6688 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6689 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6690 | operands[0], operands[2], |
5d880bd2 UW |
6691 | operands[3])) FAIL; DONE;") |
6692 | ||
6693 | ; | |
6694 | ; scond instruction pattern(s). | |
6695 | ; | |
6696 | ||
9a91a21f AS |
6697 | (define_insn_and_split "*scond<mode>" |
6698 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6699 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6700 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6701 | "" |
5d880bd2 UW |
6702 | "#" |
6703 | "&& reload_completed" | |
6704 | [(set (match_dup 0) (const_int 0)) | |
6705 | (parallel | |
a94a76a7 UW |
6706 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6707 | (match_dup 0))) | |
ae156f85 | 6708 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6709 | "") |
5d880bd2 | 6710 | |
9a91a21f AS |
6711 | (define_insn_and_split "*scond<mode>_neg" |
6712 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6713 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6714 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6715 | "" |
5d880bd2 UW |
6716 | "#" |
6717 | "&& reload_completed" | |
6718 | [(set (match_dup 0) (const_int 0)) | |
6719 | (parallel | |
9a91a21f AS |
6720 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6721 | (match_dup 1))) | |
ae156f85 | 6722 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6723 | (parallel |
9a91a21f | 6724 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6725 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6726 | "") |
5d880bd2 | 6727 | |
5d880bd2 | 6728 | |
f90b7a5a | 6729 | (define_expand "cstore<mode>4" |
9a91a21f | 6730 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6731 | (match_operator:SI 1 "s390_scond_operator" |
6732 | [(match_operand:GPR 2 "register_operand" "") | |
6733 | (match_operand:GPR 3 "general_operand" "")]))] | |
8cc6307c | 6734 | "" |
f90b7a5a | 6735 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6736 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6737 | ||
f90b7a5a | 6738 | (define_expand "cstorecc4" |
69950452 | 6739 | [(parallel |
f90b7a5a PB |
6740 | [(set (match_operand:SI 0 "register_operand" "") |
6741 | (match_operator:SI 1 "s390_eqne_operator" | |
3ea685e7 | 6742 | [(match_operand 2 "cc_reg_operand") |
f90b7a5a | 6743 | (match_operand 3 "const0_operand")])) |
69950452 AS |
6744 | (clobber (reg:CC CC_REGNUM))])] |
6745 | "" | |
3ea685e7 DV |
6746 | "machine_mode mode = GET_MODE (operands[2]); |
6747 | if (TARGET_Z196) | |
6748 | { | |
6749 | rtx cond, ite; | |
6750 | ||
6751 | if (GET_CODE (operands[1]) == NE) | |
6752 | cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); | |
6753 | else | |
6754 | cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); | |
6755 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); | |
6756 | emit_insn (gen_rtx_SET (operands[0], ite)); | |
6757 | } | |
6758 | else | |
6759 | { | |
6760 | if (mode != CCZ1mode) | |
6761 | FAIL; | |
6762 | emit_insn (gen_sne (operands[0], operands[2])); | |
6763 | if (GET_CODE (operands[1]) == EQ) | |
6764 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6765 | } | |
f90b7a5a | 6766 | DONE;") |
69950452 | 6767 | |
f90b7a5a | 6768 | (define_insn_and_split "sne" |
69950452 | 6769 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6770 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6771 | (const_int 0))) |
6772 | (clobber (reg:CC CC_REGNUM))] | |
6773 | "" | |
6774 | "#" | |
6775 | "reload_completed" | |
6776 | [(parallel | |
6777 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6778 | (clobber (reg:CC CC_REGNUM))])]) | |
6779 | ||
e69166de | 6780 | |
65b1d8ea AK |
6781 | ;; |
6782 | ;; - Conditional move instructions (introduced with z196) | |
6783 | ;; | |
6784 | ||
6785 | (define_expand "mov<mode>cc" | |
6786 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6787 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
88e845c0 RD |
6788 | (match_operand:GPR 2 "loc_operand" "") |
6789 | (match_operand:GPR 3 "loc_operand" "")))] | |
65b1d8ea | 6790 | "TARGET_Z196" |
7477de01 | 6791 | { |
88e845c0 RD |
6792 | if (!TARGET_Z13 && CONSTANT_P (operands[2])) |
6793 | operands[2] = force_reg (<MODE>mode, operands[2]); | |
6794 | ||
6795 | if (!TARGET_Z13 && CONSTANT_P (operands[3])) | |
6796 | operands[3] = force_reg (<MODE>mode, operands[3]); | |
6797 | ||
7477de01 AK |
6798 | /* Emit the comparison insn in case we do not already have a comparison result. */ |
6799 | if (!s390_comparison (operands[1], VOIDmode)) | |
6800 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6801 | XEXP (operands[1], 0), | |
6802 | XEXP (operands[1], 1)); | |
6803 | }) | |
65b1d8ea | 6804 | |
d8928886 RD |
6805 | ;; |
6806 | ;; - We do not have instructions for QImode or HImode but still | |
6807 | ;; enable load on condition/if conversion for them. | |
6808 | (define_expand "mov<mode>cc" | |
6809 | [(set (match_operand:HQI 0 "nonimmediate_operand" "") | |
6810 | (if_then_else:HQI (match_operand 1 "comparison_operator" "") | |
6811 | (match_operand:HQI 2 "loc_operand" "") | |
6812 | (match_operand:HQI 3 "loc_operand" "")))] | |
6813 | "TARGET_Z196" | |
6814 | { | |
6815 | /* Emit the comparison insn in case we do not already have a comparison | |
6816 | result. */ | |
6817 | if (!s390_comparison (operands[1], VOIDmode)) | |
6818 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6819 | XEXP (operands[1], 0), | |
6820 | XEXP (operands[1], 1)); | |
6821 | ||
6822 | rtx then = operands[2]; | |
6823 | rtx els = operands[3]; | |
6824 | ||
6825 | if ((!TARGET_Z13 && CONSTANT_P (then)) || MEM_P (then)) | |
6826 | then = force_reg (<MODE>mode, then); | |
6827 | if ((!TARGET_Z13 && CONSTANT_P (els)) || MEM_P (els)) | |
6828 | els = force_reg (<MODE>mode, els); | |
6829 | ||
6830 | if (!CONSTANT_P (then)) | |
6831 | then = simplify_gen_subreg (E_SImode, then, <MODE>mode, 0); | |
6832 | if (!CONSTANT_P (els)) | |
6833 | els = simplify_gen_subreg (E_SImode, els, <MODE>mode, 0); | |
6834 | ||
6835 | rtx tmp_target = gen_reg_rtx (E_SImode); | |
6836 | emit_insn (gen_movsicc (tmp_target, operands[1], then, els)); | |
6837 | emit_move_insn (operands[0], gen_lowpart (<MODE>mode, tmp_target)); | |
6838 | DONE; | |
6839 | }) | |
6840 | ||
6841 | ||
6842 | ||
618eef38 | 6843 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi, selr, selgr |
561f6312 | 6844 | (define_insn "*mov<mode>cc" |
618eef38 | 6845 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,S,S") |
65b1d8ea AK |
6846 | (if_then_else:GPR |
6847 | (match_operator 1 "s390_comparison" | |
618eef38 AK |
6848 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c") |
6849 | (match_operand 5 "const_int_operand" "")]) | |
6850 | (match_operand:GPR 3 "loc_operand" " d,0,d,S,0,K,0,d,0") | |
6851 | (match_operand:GPR 4 "loc_operand" " 0,d,d,0,S,0,K,0,d")))] | |
65b1d8ea AK |
6852 | "TARGET_Z196" |
6853 | "@ | |
6854 | loc<g>r%C1\t%0,%3 | |
6855 | loc<g>r%D1\t%0,%4 | |
618eef38 | 6856 | sel<g>r%C1\t%0,%3,%4 |
a6510374 AK |
6857 | loc<g>%C1\t%0,%3 |
6858 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6859 | loc<g>hi%C1\t%0,%h3 |
6860 | loc<g>hi%D1\t%0,%h4 | |
a6510374 | 6861 | stoc<g>%C1\t%3,%0 |
561f6312 | 6862 | stoc<g>%D1\t%4,%0" |
618eef38 AK |
6863 | [(set_attr "op_type" "RRF,RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") |
6864 | (set_attr "cpu_facility" "*,*,arch13,*,*,z13,z13,*,*")]) | |
65b1d8ea | 6865 | |
9db1d521 HP |
6866 | ;; |
6867 | ;;- Multiply instructions. | |
6868 | ;; | |
6869 | ||
4023fb28 UW |
6870 | ; |
6871 | ; muldi3 instruction pattern(s). | |
6872 | ; | |
9db1d521 | 6873 | |
7d2fd075 AK |
6874 | (define_expand "muldi3" |
6875 | [(parallel | |
6876 | [(set (match_operand:DI 0 "register_operand") | |
6877 | (mult:DI (match_operand:DI 1 "nonimmediate_operand") | |
6878 | (match_operand:DI 2 "general_operand"))) | |
6879 | (clobber (reg:CC CC_REGNUM))])] | |
6880 | "TARGET_ZARCH") | |
6881 | ||
07893d4f UW |
6882 | (define_insn "*muldi3_sign" |
6883 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6884 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6885 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6886 | "TARGET_ZARCH" |
07893d4f | 6887 | "@ |
d40c829f UW |
6888 | msgfr\t%0,%2 |
6889 | msgf\t%0,%2" | |
963fc8d0 AK |
6890 | [(set_attr "op_type" "RRE,RXY") |
6891 | (set_attr "type" "imuldi")]) | |
07893d4f | 6892 | |
7d2fd075 AK |
6893 | (define_insn "*muldi3" |
6894 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") | |
6895 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") | |
6896 | (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) | |
6897 | (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] | |
9602b6a1 | 6898 | "TARGET_ZARCH" |
9db1d521 | 6899 | "@ |
d40c829f | 6900 | msgr\t%0,%2 |
7d2fd075 | 6901 | msgrkc\t%0,%1,%2 |
d40c829f | 6902 | mghi\t%0,%h2 |
963fc8d0 AK |
6903 | msg\t%0,%2 |
6904 | msgfi\t%0,%2" | |
7d2fd075 | 6905 | [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") |
963fc8d0 | 6906 | (set_attr "type" "imuldi") |
e9e8efc9 | 6907 | (set_attr "cpu_facility" "*,z14,*,*,z10")]) |
7d2fd075 AK |
6908 | |
6909 | (define_insn "mulditi3" | |
6910 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6911 | (mult:TI (sign_extend:TI | |
6912 | (match_operand:DI 1 "register_operand" "%d,0")) | |
6913 | (sign_extend:TI | |
6914 | (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] | |
e9e8efc9 | 6915 | "TARGET_Z14" |
7d2fd075 AK |
6916 | "@ |
6917 | mgrk\t%0,%1,%2 | |
6918 | mg\t%0,%2" | |
6919 | [(set_attr "op_type" "RRF,RXY")]) | |
6920 | ||
6921 | ; Combine likes op1 and op2 to be swapped sometimes. | |
6922 | (define_insn "mulditi3_2" | |
6923 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6924 | (mult:TI (sign_extend:TI | |
6925 | (match_operand:DI 1 "nonimmediate_operand" "%d,T")) | |
6926 | (sign_extend:TI | |
6927 | (match_operand:DI 2 "register_operand" " d,0"))))] | |
e9e8efc9 | 6928 | "TARGET_Z14" |
7d2fd075 AK |
6929 | "@ |
6930 | mgrk\t%0,%1,%2 | |
6931 | mg\t%0,%1" | |
6932 | [(set_attr "op_type" "RRF,RXY")]) | |
6933 | ||
6934 | (define_insn "*muldi3_sign" | |
6935 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6936 | (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
6937 | (match_operand:DI 1 "register_operand" "0")))] | |
e9e8efc9 | 6938 | "TARGET_Z14" |
7d2fd075 AK |
6939 | "mgh\t%0,%2" |
6940 | [(set_attr "op_type" "RXY")]) | |
6941 | ||
f2d3c02a | 6942 | |
9db1d521 HP |
6943 | ; |
6944 | ; mulsi3 instruction pattern(s). | |
6945 | ; | |
6946 | ||
7d2fd075 AK |
6947 | (define_expand "mulsi3" |
6948 | [(parallel | |
6949 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6950 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6951 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6952 | (clobber (reg:CC CC_REGNUM))])] | |
6953 | "") | |
6954 | ||
f1e77d83 | 6955 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6956 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6957 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6958 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6959 | "" |
963fc8d0 AK |
6960 | "@ |
6961 | mh\t%0,%2 | |
6962 | mhy\t%0,%2" | |
6963 | [(set_attr "op_type" "RX,RXY") | |
6964 | (set_attr "type" "imulhi") | |
6965 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6966 | |
7d2fd075 AK |
6967 | (define_insn "*mulsi3" |
6968 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6969 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6970 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6971 | (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] | |
9db1d521 HP |
6972 | "" |
6973 | "@ | |
d40c829f | 6974 | msr\t%0,%2 |
7d2fd075 | 6975 | msrkc\t%0,%1,%2 |
d40c829f UW |
6976 | mhi\t%0,%h2 |
6977 | ms\t%0,%2 | |
963fc8d0 AK |
6978 | msy\t%0,%2 |
6979 | msfi\t%0,%2" | |
7d2fd075 AK |
6980 | [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") |
6981 | (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") | |
e9e8efc9 | 6982 | (set_attr "cpu_facility" "*,z14,*,*,longdisp,z10")]) |
9db1d521 | 6983 | |
4023fb28 UW |
6984 | ; |
6985 | ; mulsidi3 instruction pattern(s). | |
6986 | ; | |
6987 | ||
f1e77d83 | 6988 | (define_insn "mulsidi3" |
963fc8d0 | 6989 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6990 | (mult:DI (sign_extend:DI |
963fc8d0 | 6991 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6992 | (sign_extend:DI |
963fc8d0 | 6993 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6994 | "!TARGET_ZARCH" |
f1e77d83 UW |
6995 | "@ |
6996 | mr\t%0,%2 | |
963fc8d0 AK |
6997 | m\t%0,%2 |
6998 | mfy\t%0,%2" | |
6999 | [(set_attr "op_type" "RR,RX,RXY") | |
7000 | (set_attr "type" "imulsi") | |
7001 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 7002 | |
4caa6bab AK |
7003 | ; Jump to label OP3 if OP1 * OP2 results in a signed overflow |
7004 | (define_expand "mulv<mode>4" | |
7005 | [(parallel | |
7006 | [(set (reg:CCO CC_REGNUM) | |
7007 | (compare:CCO (mult:<DBL> | |
7008 | (sign_extend:<DBL> (match_operand:GPR 1 "register_operand")) | |
7009 | (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand"))) | |
7010 | (sign_extend:<DBL> (mult:GPR (match_dup 1) (match_dup 2))))) | |
7011 | (set (match_operand:GPR 0 "register_operand") | |
7012 | (mult:GPR (match_dup 1) (match_dup 2)))]) | |
7013 | (set (pc) | |
7014 | (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) | |
7015 | (label_ref (match_operand 3)) | |
7016 | (pc)))] | |
7017 | "TARGET_Z14") | |
7018 | ||
7019 | ; msrkc, msc, msgrkc, msgc | |
7020 | (define_insn "*mulv<mode>3_ccoverflow" | |
7021 | [(set (reg CC_REGNUM) | |
7022 | (compare (mult:<DBL> | |
7023 | (sign_extend:<DBL> (match_operand:GPR 1 "register_operand" "%d,0")) | |
7024 | (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand" " d,T"))) | |
7025 | (sign_extend:<DBL> (mult:GPR (match_dup 1) (match_dup 2))))) | |
7026 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
7027 | (mult:GPR (match_dup 1) (match_dup 2)))] | |
7028 | "s390_match_ccmode (insn, CCOmode) && TARGET_Z14" | |
7029 | "@ | |
7030 | ms<g>rkc\t%0,%1,%2 | |
7031 | ms<g>c\t%0,%2" | |
7032 | [(set_attr "op_type" "RRF,RXY")]) | |
7033 | ||
7034 | ||
f1e77d83 | 7035 | ; |
6e0d70c9 | 7036 | ; umul instruction pattern(s). |
f1e77d83 | 7037 | ; |
c7453384 | 7038 | |
6e0d70c9 AK |
7039 | ; mlr, ml, mlgr, mlg |
7040 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 7041 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 7042 | (mult:DW (zero_extend:DW |
3e4be43f | 7043 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 7044 | (zero_extend:DW |
3e4be43f | 7045 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
8cc6307c | 7046 | "" |
f1e77d83 | 7047 | "@ |
6e0d70c9 AK |
7048 | ml<tg>r\t%0,%2 |
7049 | ml<tg>\t%0,%2" | |
f1e77d83 | 7050 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 7051 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 7052 | |
9db1d521 | 7053 | ; |
609e7e80 | 7054 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
7055 | ; |
7056 | ||
9381e3f1 | 7057 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 7058 | (define_insn "mul<mode>3" |
2de2b3f9 AK |
7059 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7060 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
7061 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7062 | "TARGET_HARD_FLOAT" |
9db1d521 | 7063 | "@ |
62d3f261 AK |
7064 | m<xdee>tr\t%0,%1,%2 |
7065 | m<xdee>br\t%0,%2 | |
6e5b5de8 | 7066 | m<xdee>b\t%0,%2 |
2de2b3f9 AK |
7067 | wfmdb\t%v0,%v1,%v2 |
7068 | wfmsb\t%v0,%v1,%v2" | |
7069 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7070 | (set_attr "type" "fmul<mode>") |
2de2b3f9 AK |
7071 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7072 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7073 | |
9381e3f1 | 7074 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 7075 | (define_insn "fma<mode>4" |
2de2b3f9 AK |
7076 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
7077 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
7078 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
7079 | (match_operand:DSF 3 "register_operand" "0,0,v,v")))] | |
d7ecb504 | 7080 | "TARGET_HARD_FLOAT" |
a1b892b5 | 7081 | "@ |
f61a2c7d | 7082 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 | 7083 | ma<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
7084 | wfmadb\t%v0,%v1,%v2,%v3 |
7085 | wfmasb\t%v0,%v1,%v2,%v3" | |
7086 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7087 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
7088 | (set_attr "cpu_facility" "*,*,vx,vxe") |
7089 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
a1b892b5 | 7090 | |
43a09b63 | 7091 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 7092 | (define_insn "fms<mode>4" |
2de2b3f9 AK |
7093 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
7094 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
7095 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
7096 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] | |
d7ecb504 | 7097 | "TARGET_HARD_FLOAT" |
a1b892b5 | 7098 | "@ |
f61a2c7d | 7099 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 | 7100 | ms<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
7101 | wfmsdb\t%v0,%v1,%v2,%v3 |
7102 | wfmssb\t%v0,%v1,%v2,%v3" | |
7103 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7104 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
7105 | (set_attr "cpu_facility" "*,*,vx,vxe") |
7106 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
9db1d521 HP |
7107 | |
7108 | ;; | |
7109 | ;;- Divide and modulo instructions. | |
7110 | ;; | |
7111 | ||
7112 | ; | |
4023fb28 | 7113 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
7114 | ; |
7115 | ||
4023fb28 UW |
7116 | (define_expand "divmoddi4" |
7117 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 7118 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
7119 | (match_operand:DI 2 "general_operand" ""))) |
7120 | (set (match_operand:DI 3 "general_operand" "") | |
7121 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
7122 | (clobber (match_dup 4))] | |
9602b6a1 | 7123 | "TARGET_ZARCH" |
9db1d521 | 7124 | { |
d8485bdb TS |
7125 | rtx div_equal, mod_equal; |
7126 | rtx_insn *insn; | |
4023fb28 UW |
7127 | |
7128 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
7129 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
7130 | |
7131 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 7132 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
7133 | |
7134 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 7135 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7136 | |
7137 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 7138 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7139 | |
9db1d521 | 7140 | DONE; |
10bbf137 | 7141 | }) |
9db1d521 HP |
7142 | |
7143 | (define_insn "divmodtidi3" | |
4023fb28 UW |
7144 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
7145 | (ior:TI | |
4023fb28 UW |
7146 | (ashift:TI |
7147 | (zero_extend:TI | |
5665e398 | 7148 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 7149 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
7150 | (const_int 64)) |
7151 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 7152 | "TARGET_ZARCH" |
9db1d521 | 7153 | "@ |
d40c829f UW |
7154 | dsgr\t%0,%2 |
7155 | dsg\t%0,%2" | |
d3632d41 | 7156 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7157 | (set_attr "type" "idiv")]) |
9db1d521 | 7158 | |
4023fb28 UW |
7159 | (define_insn "divmodtisi3" |
7160 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
7161 | (ior:TI | |
4023fb28 UW |
7162 | (ashift:TI |
7163 | (zero_extend:TI | |
5665e398 | 7164 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 7165 | (sign_extend:DI |
3e4be43f | 7166 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
7167 | (const_int 64)) |
7168 | (zero_extend:TI | |
7169 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 7170 | "TARGET_ZARCH" |
4023fb28 | 7171 | "@ |
d40c829f UW |
7172 | dsgfr\t%0,%2 |
7173 | dsgf\t%0,%2" | |
d3632d41 | 7174 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7175 | (set_attr "type" "idiv")]) |
9db1d521 | 7176 | |
4023fb28 UW |
7177 | ; |
7178 | ; udivmoddi4 instruction pattern(s). | |
7179 | ; | |
9db1d521 | 7180 | |
4023fb28 UW |
7181 | (define_expand "udivmoddi4" |
7182 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
7183 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
7184 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7185 | (set (match_operand:DI 3 "general_operand" "") | |
7186 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
7187 | (clobber (match_dup 4))] | |
9602b6a1 | 7188 | "TARGET_ZARCH" |
9db1d521 | 7189 | { |
d8485bdb TS |
7190 | rtx div_equal, mod_equal, equal; |
7191 | rtx_insn *insn; | |
4023fb28 UW |
7192 | |
7193 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
7194 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
7195 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
7196 | gen_rtx_ASHIFT (TImode, |
7197 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
7198 | GEN_INT (64)), |
7199 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
7200 | |
7201 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 7202 | emit_clobber (operands[4]); |
4023fb28 UW |
7203 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
7204 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 7205 | |
4023fb28 | 7206 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7207 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7208 | |
7209 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 7210 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7211 | |
7212 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 7213 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7214 | |
9db1d521 | 7215 | DONE; |
10bbf137 | 7216 | }) |
9db1d521 HP |
7217 | |
7218 | (define_insn "udivmodtidi3" | |
4023fb28 | 7219 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 7220 | (ior:TI |
5665e398 UW |
7221 | (ashift:TI |
7222 | (zero_extend:TI | |
7223 | (truncate:DI | |
2f7e5a0d EC |
7224 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
7225 | (zero_extend:TI | |
3e4be43f | 7226 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7227 | (const_int 64)) |
7228 | (zero_extend:TI | |
7229 | (truncate:DI | |
7230 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 7231 | "TARGET_ZARCH" |
9db1d521 | 7232 | "@ |
d40c829f UW |
7233 | dlgr\t%0,%2 |
7234 | dlg\t%0,%2" | |
d3632d41 | 7235 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7236 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7237 | |
7238 | ; | |
4023fb28 | 7239 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
7240 | ; |
7241 | ||
4023fb28 UW |
7242 | (define_expand "divmodsi4" |
7243 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7244 | (div:SI (match_operand:SI 1 "general_operand" "") | |
7245 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7246 | (set (match_operand:SI 3 "general_operand" "") | |
7247 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
7248 | (clobber (match_dup 4))] | |
9602b6a1 | 7249 | "!TARGET_ZARCH" |
9db1d521 | 7250 | { |
d8485bdb TS |
7251 | rtx div_equal, mod_equal, equal; |
7252 | rtx_insn *insn; | |
4023fb28 UW |
7253 | |
7254 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
7255 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
7256 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7257 | gen_rtx_ASHIFT (DImode, |
7258 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7259 | GEN_INT (32)), |
7260 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
7261 | |
7262 | operands[4] = gen_reg_rtx(DImode); | |
7263 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 7264 | |
4023fb28 | 7265 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7266 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7267 | |
7268 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7269 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7270 | |
7271 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7272 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7273 | |
9db1d521 | 7274 | DONE; |
10bbf137 | 7275 | }) |
9db1d521 HP |
7276 | |
7277 | (define_insn "divmoddisi3" | |
4023fb28 | 7278 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 7279 | (ior:DI |
5665e398 UW |
7280 | (ashift:DI |
7281 | (zero_extend:DI | |
7282 | (truncate:SI | |
2f7e5a0d EC |
7283 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
7284 | (sign_extend:DI | |
5665e398 UW |
7285 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
7286 | (const_int 32)) | |
7287 | (zero_extend:DI | |
7288 | (truncate:SI | |
7289 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7290 | "!TARGET_ZARCH" |
9db1d521 | 7291 | "@ |
d40c829f UW |
7292 | dr\t%0,%2 |
7293 | d\t%0,%2" | |
9db1d521 | 7294 | [(set_attr "op_type" "RR,RX") |
077dab3b | 7295 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7296 | |
7297 | ; | |
7298 | ; udivsi3 and umodsi3 instruction pattern(s). | |
7299 | ; | |
7300 | ||
f1e77d83 UW |
7301 | (define_expand "udivmodsi4" |
7302 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7303 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
7304 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7305 | (set (match_operand:SI 3 "general_operand" "") | |
7306 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
7307 | (clobber (match_dup 4))] | |
8cc6307c | 7308 | "!TARGET_ZARCH" |
f1e77d83 | 7309 | { |
d8485bdb TS |
7310 | rtx div_equal, mod_equal, equal; |
7311 | rtx_insn *insn; | |
f1e77d83 UW |
7312 | |
7313 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7314 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7315 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
7316 | gen_rtx_ASHIFT (DImode, |
7317 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7318 | GEN_INT (32)), |
7319 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
7320 | |
7321 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 7322 | emit_clobber (operands[4]); |
f1e77d83 UW |
7323 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
7324 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 7325 | |
f1e77d83 | 7326 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7327 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
7328 | |
7329 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7330 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
7331 | |
7332 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7333 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
7334 | |
7335 | DONE; | |
7336 | }) | |
7337 | ||
7338 | (define_insn "udivmoddisi3" | |
7339 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 7340 | (ior:DI |
5665e398 UW |
7341 | (ashift:DI |
7342 | (zero_extend:DI | |
7343 | (truncate:SI | |
2f7e5a0d EC |
7344 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
7345 | (zero_extend:DI | |
3e4be43f | 7346 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7347 | (const_int 32)) |
7348 | (zero_extend:DI | |
7349 | (truncate:SI | |
7350 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
8cc6307c | 7351 | "!TARGET_ZARCH" |
f1e77d83 UW |
7352 | "@ |
7353 | dlr\t%0,%2 | |
7354 | dl\t%0,%2" | |
7355 | [(set_attr "op_type" "RRE,RXY") | |
7356 | (set_attr "type" "idiv")]) | |
4023fb28 | 7357 | |
9db1d521 | 7358 | ; |
f5905b37 | 7359 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7360 | ; |
7361 | ||
609e7e80 | 7362 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7363 | (define_insn "div<mode>3" |
2de2b3f9 AK |
7364 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7365 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
7366 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7367 | "TARGET_HARD_FLOAT" |
9db1d521 | 7368 | "@ |
62d3f261 AK |
7369 | d<xde>tr\t%0,%1,%2 |
7370 | d<xde>br\t%0,%2 | |
6e5b5de8 | 7371 | d<xde>b\t%0,%2 |
2de2b3f9 AK |
7372 | wfddb\t%v0,%v1,%v2 |
7373 | wfdsb\t%v0,%v1,%v2" | |
7374 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7375 | (set_attr "type" "fdiv<mode>") |
2de2b3f9 AK |
7376 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7377 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7378 | |
9db1d521 HP |
7379 | |
7380 | ;; | |
7381 | ;;- And instructions. | |
7382 | ;; | |
7383 | ||
047d35ed AS |
7384 | (define_expand "and<mode>3" |
7385 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7386 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7387 | (match_operand:INT 2 "general_operand" ""))) | |
7388 | (clobber (reg:CC CC_REGNUM))] | |
7389 | "" | |
7390 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7391 | ||
9db1d521 HP |
7392 | ; |
7393 | ; anddi3 instruction pattern(s). | |
7394 | ; | |
7395 | ||
7396 | (define_insn "*anddi3_cc" | |
ae156f85 | 7397 | [(set (reg CC_REGNUM) |
e3140518 | 7398 | (compare |
3e4be43f | 7399 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7400 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7401 | (const_int 0))) |
3e4be43f | 7402 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7403 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7404 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7405 | "@ |
d40c829f | 7406 | ngr\t%0,%2 |
65b1d8ea | 7407 | ngrk\t%0,%1,%2 |
e3140518 RH |
7408 | ng\t%0,%2 |
7409 | risbg\t%0,%1,%s2,128+%e2,0" | |
7410 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7411 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7412 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7413 | |
7414 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7415 | [(set (reg CC_REGNUM) |
e3140518 | 7416 | (compare |
3e4be43f | 7417 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7418 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7419 | (const_int 0))) |
3e4be43f | 7420 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7421 | "TARGET_ZARCH |
7422 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7423 | /* Do not steal TM patterns. */ |
7424 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7425 | "@ |
d40c829f | 7426 | ngr\t%0,%2 |
65b1d8ea | 7427 | ngrk\t%0,%1,%2 |
e3140518 RH |
7428 | ng\t%0,%2 |
7429 | risbg\t%0,%1,%s2,128+%e2,0" | |
7430 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7431 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7432 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7433 | |
3af8e996 | 7434 | (define_insn "*anddi3" |
65b1d8ea | 7435 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7436 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7437 | (and:DI |
7438 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7439 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7440 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7441 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7442 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7443 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7444 | "@ |
7445 | # | |
7446 | # | |
7447 | nihh\t%0,%j2 | |
7448 | nihl\t%0,%j2 | |
7449 | nilh\t%0,%j2 | |
7450 | nill\t%0,%j2 | |
7451 | nihf\t%0,%m2 | |
7452 | nilf\t%0,%m2 | |
7453 | ngr\t%0,%2 | |
65b1d8ea | 7454 | ngrk\t%0,%1,%2 |
ec24698e | 7455 | ng\t%0,%2 |
e3140518 | 7456 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7457 | # |
7458 | #" | |
e3140518 RH |
7459 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7460 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7461 | (set_attr "z10prop" "*, |
7462 | *, | |
7463 | z10_super_E1, | |
7464 | z10_super_E1, | |
7465 | z10_super_E1, | |
7466 | z10_super_E1, | |
7467 | z10_super_E1, | |
7468 | z10_super_E1, | |
7469 | z10_super_E1, | |
65b1d8ea | 7470 | *, |
9381e3f1 | 7471 | z10_super_E1, |
e3140518 | 7472 | z10_super_E1, |
9381e3f1 WG |
7473 | *, |
7474 | *")]) | |
0dfa6c5e UW |
7475 | |
7476 | (define_split | |
7477 | [(set (match_operand:DI 0 "s_operand" "") | |
7478 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7479 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7480 | "reload_completed" |
7481 | [(parallel | |
7482 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7483 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7484 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7485 | |
1a2e356e | 7486 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7487 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7488 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7489 | (and:GPR (lshiftrt:GPR | |
7490 | (match_operand:GPR 1 "register_operand" "d") | |
7491 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7492 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7493 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7494 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7495 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7496 | INTVAL (operands[3]))" | |
64c744b9 | 7497 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7498 | [(set_attr "op_type" "RIE") |
7499 | (set_attr "z10prop" "z10_super_E1")]) | |
7500 | ||
64c744b9 | 7501 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7502 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7503 | (and:GPR (ashift:GPR | |
7504 | (match_operand:GPR 1 "register_operand" "d") | |
7505 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7506 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7507 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7508 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7509 | INTVAL (operands[3]))" | |
64c744b9 | 7510 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7511 | [(set_attr "op_type" "RIE") |
7512 | (set_attr "z10prop" "z10_super_E1")]) | |
7513 | ||
9db1d521 HP |
7514 | |
7515 | ; | |
7516 | ; andsi3 instruction pattern(s). | |
7517 | ; | |
7518 | ||
7519 | (define_insn "*andsi3_cc" | |
ae156f85 | 7520 | [(set (reg CC_REGNUM) |
e3140518 RH |
7521 | (compare |
7522 | (and:SI | |
7523 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7524 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7525 | (const_int 0))) | |
7526 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7527 | (and:SI (match_dup 1) (match_dup 2)))] |
7528 | "s390_match_ccmode(insn, CCTmode)" | |
7529 | "@ | |
ec24698e | 7530 | nilf\t%0,%o2 |
d40c829f | 7531 | nr\t%0,%2 |
65b1d8ea | 7532 | nrk\t%0,%1,%2 |
d40c829f | 7533 | n\t%0,%2 |
e3140518 RH |
7534 | ny\t%0,%2 |
7535 | risbg\t%0,%1,%t2,128+%f2,0" | |
7536 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7537 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7538 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7539 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7540 | |
7541 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7542 | [(set (reg CC_REGNUM) |
e3140518 RH |
7543 | (compare |
7544 | (and:SI | |
7545 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7546 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7547 | (const_int 0))) | |
7548 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7549 | "s390_match_ccmode(insn, CCTmode) |
7550 | /* Do not steal TM patterns. */ | |
7551 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7552 | "@ |
ec24698e | 7553 | nilf\t%0,%o2 |
d40c829f | 7554 | nr\t%0,%2 |
65b1d8ea | 7555 | nrk\t%0,%1,%2 |
d40c829f | 7556 | n\t%0,%2 |
e3140518 RH |
7557 | ny\t%0,%2 |
7558 | risbg\t%0,%1,%t2,128+%f2,0" | |
7559 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7560 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7561 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7562 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7563 | |
f19a9af7 | 7564 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7565 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7566 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7567 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7568 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7569 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7570 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7571 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7572 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7573 | "@ |
f19a9af7 AK |
7574 | # |
7575 | # | |
7576 | nilh\t%0,%j2 | |
2f7e5a0d | 7577 | nill\t%0,%j2 |
ec24698e | 7578 | nilf\t%0,%o2 |
d40c829f | 7579 | nr\t%0,%2 |
65b1d8ea | 7580 | nrk\t%0,%1,%2 |
d40c829f | 7581 | n\t%0,%2 |
8cb66696 | 7582 | ny\t%0,%2 |
e3140518 | 7583 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7584 | # |
19b63d8e | 7585 | #" |
e3140518 | 7586 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7587 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7588 | (set_attr "z10prop" "*, |
7589 | *, | |
7590 | z10_super_E1, | |
7591 | z10_super_E1, | |
7592 | z10_super_E1, | |
7593 | z10_super_E1, | |
65b1d8ea | 7594 | *, |
9381e3f1 WG |
7595 | z10_super_E1, |
7596 | z10_super_E1, | |
e3140518 | 7597 | z10_super_E1, |
9381e3f1 WG |
7598 | *, |
7599 | *")]) | |
f19a9af7 AK |
7600 | |
7601 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7602 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7603 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7604 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7605 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7606 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7607 | "@ |
7608 | nr\t%0,%2 | |
8cb66696 | 7609 | n\t%0,%2 |
0dfa6c5e | 7610 | # |
19b63d8e | 7611 | #" |
9381e3f1 WG |
7612 | [(set_attr "op_type" "RR,RX,SI,SS") |
7613 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7614 | ||
0dfa6c5e UW |
7615 | |
7616 | (define_split | |
7617 | [(set (match_operand:SI 0 "s_operand" "") | |
7618 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7619 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7620 | "reload_completed" |
7621 | [(parallel | |
7622 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7623 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7624 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7625 | |
9db1d521 HP |
7626 | ; |
7627 | ; andhi3 instruction pattern(s). | |
7628 | ; | |
7629 | ||
8cb66696 | 7630 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7631 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7632 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7633 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7634 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7635 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7636 | "@ |
d40c829f | 7637 | nr\t%0,%2 |
65b1d8ea | 7638 | nrk\t%0,%1,%2 |
8cb66696 | 7639 | nill\t%0,%x2 |
0dfa6c5e | 7640 | # |
19b63d8e | 7641 | #" |
65b1d8ea AK |
7642 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7643 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7644 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7645 | ]) |
8cb66696 UW |
7646 | |
7647 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7648 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7649 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7650 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7651 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7652 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7653 | "@ | |
7654 | nr\t%0,%2 | |
0dfa6c5e | 7655 | # |
19b63d8e | 7656 | #" |
9381e3f1 WG |
7657 | [(set_attr "op_type" "RR,SI,SS") |
7658 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7659 | ]) | |
0dfa6c5e UW |
7660 | |
7661 | (define_split | |
7662 | [(set (match_operand:HI 0 "s_operand" "") | |
7663 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7664 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7665 | "reload_completed" |
7666 | [(parallel | |
7667 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7668 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7669 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7670 | |
9db1d521 HP |
7671 | ; |
7672 | ; andqi3 instruction pattern(s). | |
7673 | ; | |
7674 | ||
8cb66696 | 7675 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7676 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7677 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7678 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7679 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7680 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7681 | "@ |
d40c829f | 7682 | nr\t%0,%2 |
65b1d8ea | 7683 | nrk\t%0,%1,%2 |
8cb66696 | 7684 | nill\t%0,%b2 |
fc0ea003 UW |
7685 | ni\t%S0,%b2 |
7686 | niy\t%S0,%b2 | |
19b63d8e | 7687 | #" |
65b1d8ea | 7688 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7689 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7690 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7691 | |
7692 | (define_insn "*andqi3_esa" | |
7693 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7694 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7695 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7696 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7697 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7698 | "@ |
8cb66696 | 7699 | nr\t%0,%2 |
fc0ea003 | 7700 | ni\t%S0,%b2 |
19b63d8e | 7701 | #" |
9381e3f1 WG |
7702 | [(set_attr "op_type" "RR,SI,SS") |
7703 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7704 | |
deb9351f DV |
7705 | ; |
7706 | ; And with complement | |
7707 | ; | |
7708 | ; c = ~b & a = (b & a) ^ a | |
7709 | ||
7710 | (define_insn_and_split "*andc_split_<mode>" | |
7711 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7712 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7713 | (match_operand:GPR 2 "general_operand" ""))) | |
7714 | (clobber (reg:CC CC_REGNUM))] | |
4a9733f3 AK |
7715 | "!TARGET_ARCH13 |
7716 | && ! reload_completed | |
ad7ab32e DV |
7717 | && (GET_CODE (operands[0]) != MEM |
7718 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7719 | on the split xor if (b & a) is stored into a pseudo. */ | |
7720 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7721 | "#" |
7722 | "&& 1" | |
7723 | [ | |
7724 | (parallel | |
7725 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7726 | (clobber (reg:CC CC_REGNUM))]) | |
7727 | (parallel | |
7728 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7729 | (clobber (reg:CC CC_REGNUM))])] | |
7730 | { | |
7731 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7732 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7733 | else | |
7734 | operands[3] = operands[0]; | |
7735 | }) | |
7736 | ||
19b63d8e UW |
7737 | ; |
7738 | ; Block and (NC) patterns. | |
7739 | ; | |
7740 | ||
7741 | (define_insn "*nc" | |
7742 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7743 | (and:BLK (match_dup 0) | |
7744 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7745 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7746 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7747 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7748 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7749 | [(set_attr "op_type" "SS") |
7750 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7751 | |
7752 | (define_split | |
7753 | [(set (match_operand 0 "memory_operand" "") | |
7754 | (and (match_dup 0) | |
7755 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7756 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7757 | "reload_completed |
7758 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7759 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7760 | [(parallel | |
7761 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7762 | (use (match_dup 2)) | |
ae156f85 | 7763 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7764 | { |
7765 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7766 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7767 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7768 | }) | |
7769 | ||
7770 | (define_peephole2 | |
7771 | [(parallel | |
7772 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7773 | (and:BLK (match_dup 0) | |
7774 | (match_operand:BLK 1 "memory_operand" ""))) | |
7775 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7776 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7777 | (parallel |
7778 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7779 | (and:BLK (match_dup 3) | |
7780 | (match_operand:BLK 4 "memory_operand" ""))) | |
7781 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7782 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7783 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7784 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7785 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7786 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7787 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7788 | [(parallel | |
7789 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7790 | (use (match_dup 8)) | |
ae156f85 | 7791 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7792 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7793 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7794 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7795 | ||
9db1d521 HP |
7796 | |
7797 | ;; | |
7798 | ;;- Bit set (inclusive or) instructions. | |
7799 | ;; | |
7800 | ||
047d35ed AS |
7801 | (define_expand "ior<mode>3" |
7802 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7803 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7804 | (match_operand:INT 2 "general_operand" ""))) | |
7805 | (clobber (reg:CC CC_REGNUM))] | |
7806 | "" | |
7807 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7808 | ||
9db1d521 HP |
7809 | ; |
7810 | ; iordi3 instruction pattern(s). | |
7811 | ; | |
7812 | ||
4023fb28 | 7813 | (define_insn "*iordi3_cc" |
ae156f85 | 7814 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7815 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7816 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7817 | (const_int 0))) |
3e4be43f | 7818 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7819 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7820 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7821 | "@ |
d40c829f | 7822 | ogr\t%0,%2 |
65b1d8ea | 7823 | ogrk\t%0,%1,%2 |
d40c829f | 7824 | og\t%0,%2" |
65b1d8ea AK |
7825 | [(set_attr "op_type" "RRE,RRF,RXY") |
7826 | (set_attr "cpu_facility" "*,z196,*") | |
7827 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7828 | |
7829 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7830 | [(set (reg CC_REGNUM) |
65b1d8ea | 7831 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7832 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7833 | (const_int 0))) |
65b1d8ea | 7834 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7835 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7836 | "@ |
d40c829f | 7837 | ogr\t%0,%2 |
65b1d8ea | 7838 | ogrk\t%0,%1,%2 |
d40c829f | 7839 | og\t%0,%2" |
65b1d8ea AK |
7840 | [(set_attr "op_type" "RRE,RRF,RXY") |
7841 | (set_attr "cpu_facility" "*,z196,*") | |
7842 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7843 | |
3af8e996 | 7844 | (define_insn "*iordi3" |
65b1d8ea | 7845 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7846 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7847 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7848 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7849 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7850 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7851 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7852 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7853 | "@ |
7854 | oihh\t%0,%i2 | |
7855 | oihl\t%0,%i2 | |
7856 | oilh\t%0,%i2 | |
7857 | oill\t%0,%i2 | |
7858 | oihf\t%0,%k2 | |
7859 | oilf\t%0,%k2 | |
7860 | ogr\t%0,%2 | |
65b1d8ea | 7861 | ogrk\t%0,%1,%2 |
ec24698e UW |
7862 | og\t%0,%2 |
7863 | # | |
7864 | #" | |
65b1d8ea AK |
7865 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7866 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7867 | (set_attr "z10prop" "z10_super_E1, |
7868 | z10_super_E1, | |
7869 | z10_super_E1, | |
7870 | z10_super_E1, | |
7871 | z10_super_E1, | |
7872 | z10_super_E1, | |
7873 | z10_super_E1, | |
65b1d8ea | 7874 | *, |
9381e3f1 WG |
7875 | z10_super_E1, |
7876 | *, | |
7877 | *")]) | |
0dfa6c5e UW |
7878 | |
7879 | (define_split | |
7880 | [(set (match_operand:DI 0 "s_operand" "") | |
7881 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7882 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7883 | "reload_completed" |
7884 | [(parallel | |
7885 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7886 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7887 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7888 | |
9db1d521 HP |
7889 | ; |
7890 | ; iorsi3 instruction pattern(s). | |
7891 | ; | |
7892 | ||
4023fb28 | 7893 | (define_insn "*iorsi3_cc" |
ae156f85 | 7894 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7895 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7896 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7897 | (const_int 0))) |
65b1d8ea | 7898 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7899 | (ior:SI (match_dup 1) (match_dup 2)))] |
7900 | "s390_match_ccmode(insn, CCTmode)" | |
7901 | "@ | |
ec24698e | 7902 | oilf\t%0,%o2 |
d40c829f | 7903 | or\t%0,%2 |
65b1d8ea | 7904 | ork\t%0,%1,%2 |
d40c829f UW |
7905 | o\t%0,%2 |
7906 | oy\t%0,%2" | |
65b1d8ea | 7907 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7908 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7909 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7910 | |
7911 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7912 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7913 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7914 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7915 | (const_int 0))) |
65b1d8ea | 7916 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7917 | "s390_match_ccmode(insn, CCTmode)" |
7918 | "@ | |
ec24698e | 7919 | oilf\t%0,%o2 |
d40c829f | 7920 | or\t%0,%2 |
65b1d8ea | 7921 | ork\t%0,%1,%2 |
d40c829f UW |
7922 | o\t%0,%2 |
7923 | oy\t%0,%2" | |
65b1d8ea | 7924 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7925 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7926 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7927 | |
8cb66696 | 7928 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7929 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7930 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7931 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7932 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7933 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7934 | "@ |
f19a9af7 AK |
7935 | oilh\t%0,%i2 |
7936 | oill\t%0,%i2 | |
ec24698e | 7937 | oilf\t%0,%o2 |
d40c829f | 7938 | or\t%0,%2 |
65b1d8ea | 7939 | ork\t%0,%1,%2 |
d40c829f | 7940 | o\t%0,%2 |
8cb66696 | 7941 | oy\t%0,%2 |
0dfa6c5e | 7942 | # |
19b63d8e | 7943 | #" |
65b1d8ea | 7944 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7945 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7946 | (set_attr "z10prop" "z10_super_E1, |
7947 | z10_super_E1, | |
7948 | z10_super_E1, | |
7949 | z10_super_E1, | |
65b1d8ea | 7950 | *, |
9381e3f1 WG |
7951 | z10_super_E1, |
7952 | z10_super_E1, | |
7953 | *, | |
7954 | *")]) | |
8cb66696 UW |
7955 | |
7956 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7957 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7958 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7959 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7960 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7961 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7962 | "@ |
7963 | or\t%0,%2 | |
8cb66696 | 7964 | o\t%0,%2 |
0dfa6c5e | 7965 | # |
19b63d8e | 7966 | #" |
9381e3f1 WG |
7967 | [(set_attr "op_type" "RR,RX,SI,SS") |
7968 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7969 | |
7970 | (define_split | |
7971 | [(set (match_operand:SI 0 "s_operand" "") | |
7972 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7973 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7974 | "reload_completed" |
7975 | [(parallel | |
7976 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7977 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7978 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7979 | |
4023fb28 UW |
7980 | ; |
7981 | ; iorhi3 instruction pattern(s). | |
7982 | ; | |
7983 | ||
8cb66696 | 7984 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7985 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7986 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7987 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7988 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7989 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7990 | "@ |
d40c829f | 7991 | or\t%0,%2 |
65b1d8ea | 7992 | ork\t%0,%1,%2 |
8cb66696 | 7993 | oill\t%0,%x2 |
0dfa6c5e | 7994 | # |
19b63d8e | 7995 | #" |
65b1d8ea AK |
7996 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7997 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7998 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7999 | |
8000 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
8001 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
8002 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
8003 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 8004 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8005 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
8006 | "@ | |
8007 | or\t%0,%2 | |
0dfa6c5e | 8008 | # |
19b63d8e | 8009 | #" |
9381e3f1 WG |
8010 | [(set_attr "op_type" "RR,SI,SS") |
8011 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8012 | |
8013 | (define_split | |
8014 | [(set (match_operand:HI 0 "s_operand" "") | |
8015 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8016 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8017 | "reload_completed" |
8018 | [(parallel | |
8019 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8020 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8021 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 8022 | |
9db1d521 | 8023 | ; |
4023fb28 | 8024 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
8025 | ; |
8026 | ||
8cb66696 | 8027 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
8028 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8029 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
8030 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 8031 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8032 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 8033 | "@ |
d40c829f | 8034 | or\t%0,%2 |
65b1d8ea | 8035 | ork\t%0,%1,%2 |
8cb66696 | 8036 | oill\t%0,%b2 |
fc0ea003 UW |
8037 | oi\t%S0,%b2 |
8038 | oiy\t%S0,%b2 | |
19b63d8e | 8039 | #" |
65b1d8ea | 8040 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 8041 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
8042 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
8043 | z10_super,z10_super,*")]) | |
8cb66696 UW |
8044 | |
8045 | (define_insn "*iorqi3_esa" | |
8046 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
8047 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
8048 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 8049 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8050 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 8051 | "@ |
8cb66696 | 8052 | or\t%0,%2 |
fc0ea003 | 8053 | oi\t%S0,%b2 |
19b63d8e | 8054 | #" |
9381e3f1 WG |
8055 | [(set_attr "op_type" "RR,SI,SS") |
8056 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 8057 | |
4a9733f3 AK |
8058 | ; |
8059 | ; And/Or with complement | |
8060 | ; | |
8061 | ||
8062 | ; ncrk, ncgrk, ocrk, ocgrk | |
8063 | (define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cc" | |
8064 | [(set (reg CC_REGNUM) | |
8065 | (compare | |
8066 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8067 | (match_operand:GPR 2 "register_operand" "d")) | |
8068 | (const_int 0))) | |
8069 | (set (match_operand:GPR 0 "register_operand" "=d") | |
8070 | (ANDOR:GPR (not:GPR (match_dup 1)) | |
8071 | (match_dup 2)))] | |
8072 | "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)" | |
8073 | "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" | |
8074 | [(set_attr "op_type" "RRF")]) | |
8075 | ||
8076 | ; ncrk, ncgrk, ocrk, ocgrk | |
8077 | (define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cconly" | |
8078 | [(set (reg CC_REGNUM) | |
8079 | (compare | |
8080 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8081 | (match_operand:GPR 2 "register_operand" "d")) | |
8082 | (const_int 0))) | |
8083 | (clobber (match_scratch:GPR 0 "=d"))] | |
8084 | "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)" | |
8085 | "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" | |
8086 | [(set_attr "op_type" "RRF")]) | |
8087 | ||
8088 | ; ncrk, ncgrk, ocrk, ocgrk | |
8089 | (define_insn "*<ANDOR:bitops_name>c<GPR:mode>" | |
8090 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8091 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8092 | (match_operand:GPR 2 "register_operand" "d"))) | |
8093 | (clobber (reg:CC CC_REGNUM))] | |
8094 | "TARGET_ARCH13" | |
8095 | "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" | |
8096 | [(set_attr "op_type" "RRF")]) | |
8097 | ||
8098 | ; | |
8099 | ;- Nand/Nor instructions. | |
8100 | ; | |
8101 | ||
8102 | ; nnrk, nngrk, nork, nogrk | |
8103 | (define_insn "*n<ANDOR:inv_bitops_name><GPR:mode>_cc" | |
8104 | [(set (reg CC_REGNUM) | |
8105 | (compare | |
8106 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8107 | (not:GPR (match_operand:GPR 2 "register_operand" "d"))) | |
8108 | (const_int 0))) | |
8109 | (set (match_operand:GPR 0 "register_operand" "=d") | |
8110 | (ANDOR:GPR (not:GPR (match_dup 1)) | |
8111 | (not:GPR (match_dup 2))))] | |
8112 | "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)" | |
8113 | "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" | |
8114 | [(set_attr "op_type" "RRF")]) | |
8115 | ||
8116 | ; nnrk, nngrk, nork, nogrk | |
8117 | (define_insn "*n<ANDOR:inv_bitops_name><mode>_cconly" | |
8118 | [(set (reg CC_REGNUM) | |
8119 | (compare | |
8120 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8121 | (not:GPR (match_operand:GPR 2 "register_operand" "d"))) | |
8122 | (const_int 0))) | |
8123 | (clobber (match_scratch:GPR 0 "=d"))] | |
8124 | "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)" | |
8125 | "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" | |
8126 | [(set_attr "op_type" "RRF")]) | |
8127 | ||
8128 | ; nnrk, nngrk, nork, nogrk | |
8129 | (define_insn "*n<ANDOR:inv_bitops_name><mode>" | |
8130 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8131 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8132 | (not:GPR (match_operand:GPR 2 "register_operand" "d")))) | |
8133 | (clobber (reg:CC CC_REGNUM))] | |
8134 | "TARGET_ARCH13" | |
8135 | "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" | |
8136 | [(set_attr "op_type" "RRF")]) | |
8137 | ||
8138 | ||
19b63d8e UW |
8139 | ; |
8140 | ; Block inclusive or (OC) patterns. | |
8141 | ; | |
8142 | ||
8143 | (define_insn "*oc" | |
8144 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8145 | (ior:BLK (match_dup 0) | |
8146 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8147 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8148 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8149 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8150 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
8151 | [(set_attr "op_type" "SS") |
8152 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8153 | |
8154 | (define_split | |
8155 | [(set (match_operand 0 "memory_operand" "") | |
8156 | (ior (match_dup 0) | |
8157 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8158 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8159 | "reload_completed |
8160 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8161 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8162 | [(parallel | |
8163 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
8164 | (use (match_dup 2)) | |
ae156f85 | 8165 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8166 | { |
8167 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8168 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8169 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8170 | }) | |
8171 | ||
8172 | (define_peephole2 | |
8173 | [(parallel | |
8174 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8175 | (ior:BLK (match_dup 0) | |
8176 | (match_operand:BLK 1 "memory_operand" ""))) | |
8177 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8178 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8179 | (parallel |
8180 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8181 | (ior:BLK (match_dup 3) | |
8182 | (match_operand:BLK 4 "memory_operand" ""))) | |
8183 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8184 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8185 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8186 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8187 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8188 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8189 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8190 | [(parallel | |
8191 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
8192 | (use (match_dup 8)) | |
ae156f85 | 8193 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8194 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8195 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8196 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8197 | ||
9db1d521 HP |
8198 | |
8199 | ;; | |
8200 | ;;- Xor instructions. | |
8201 | ;; | |
8202 | ||
047d35ed AS |
8203 | (define_expand "xor<mode>3" |
8204 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
8205 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
8206 | (match_operand:INT 2 "general_operand" ""))) | |
8207 | (clobber (reg:CC CC_REGNUM))] | |
8208 | "" | |
8209 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
8210 | ||
3c91f126 AK |
8211 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
8212 | ; simplifications. So its better to have something matching. | |
8213 | (define_split | |
8214 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
8215 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
8216 | "" | |
8217 | [(parallel | |
8218 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
8219 | (clobber (reg:CC CC_REGNUM))])] | |
8220 | { | |
8221 | operands[2] = constm1_rtx; | |
8222 | if (!s390_logical_operator_ok_p (operands)) | |
8223 | FAIL; | |
8224 | }) | |
8225 | ||
9db1d521 HP |
8226 | ; |
8227 | ; xordi3 instruction pattern(s). | |
8228 | ; | |
8229 | ||
4023fb28 | 8230 | (define_insn "*xordi3_cc" |
ae156f85 | 8231 | [(set (reg CC_REGNUM) |
3e4be43f UW |
8232 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
8233 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 8234 | (const_int 0))) |
3e4be43f | 8235 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 8236 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 8237 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 8238 | "@ |
d40c829f | 8239 | xgr\t%0,%2 |
65b1d8ea | 8240 | xgrk\t%0,%1,%2 |
d40c829f | 8241 | xg\t%0,%2" |
65b1d8ea | 8242 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 8243 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 8244 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
8245 | |
8246 | (define_insn "*xordi3_cconly" | |
ae156f85 | 8247 | [(set (reg CC_REGNUM) |
3e4be43f UW |
8248 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
8249 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 8250 | (const_int 0))) |
3e4be43f | 8251 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 8252 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 8253 | "@ |
d40c829f | 8254 | xgr\t%0,%2 |
65b1d8ea | 8255 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 8256 | xg\t%0,%2" |
65b1d8ea AK |
8257 | [(set_attr "op_type" "RRE,RRF,RXY") |
8258 | (set_attr "cpu_facility" "*,z196,*") | |
8259 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 8260 | |
3af8e996 | 8261 | (define_insn "*xordi3" |
3e4be43f UW |
8262 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
8263 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
8264 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 8265 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8266 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
8267 | "@ |
8268 | xihf\t%0,%k2 | |
8269 | xilf\t%0,%k2 | |
8270 | xgr\t%0,%2 | |
65b1d8ea | 8271 | xgrk\t%0,%1,%2 |
ec24698e UW |
8272 | xg\t%0,%2 |
8273 | # | |
8274 | #" | |
65b1d8ea AK |
8275 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
8276 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
8277 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
8278 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8279 | |
8280 | (define_split | |
8281 | [(set (match_operand:DI 0 "s_operand" "") | |
8282 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 8283 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8284 | "reload_completed" |
8285 | [(parallel | |
8286 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8287 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8288 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 8289 | |
9db1d521 HP |
8290 | ; |
8291 | ; xorsi3 instruction pattern(s). | |
8292 | ; | |
8293 | ||
4023fb28 | 8294 | (define_insn "*xorsi3_cc" |
ae156f85 | 8295 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8296 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8297 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8298 | (const_int 0))) |
65b1d8ea | 8299 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
8300 | (xor:SI (match_dup 1) (match_dup 2)))] |
8301 | "s390_match_ccmode(insn, CCTmode)" | |
8302 | "@ | |
ec24698e | 8303 | xilf\t%0,%o2 |
d40c829f | 8304 | xr\t%0,%2 |
65b1d8ea | 8305 | xrk\t%0,%1,%2 |
d40c829f UW |
8306 | x\t%0,%2 |
8307 | xy\t%0,%2" | |
65b1d8ea | 8308 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8309 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8310 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8311 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
8312 | |
8313 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 8314 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8315 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8316 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8317 | (const_int 0))) |
65b1d8ea | 8318 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
8319 | "s390_match_ccmode(insn, CCTmode)" |
8320 | "@ | |
ec24698e | 8321 | xilf\t%0,%o2 |
d40c829f | 8322 | xr\t%0,%2 |
65b1d8ea | 8323 | xrk\t%0,%1,%2 |
d40c829f UW |
8324 | x\t%0,%2 |
8325 | xy\t%0,%2" | |
65b1d8ea | 8326 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8327 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8328 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8329 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 8330 | |
8cb66696 | 8331 | (define_insn "*xorsi3" |
65b1d8ea AK |
8332 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
8333 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
8334 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 8335 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8336 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8337 | "@ |
ec24698e | 8338 | xilf\t%0,%o2 |
d40c829f | 8339 | xr\t%0,%2 |
65b1d8ea | 8340 | xrk\t%0,%1,%2 |
d40c829f | 8341 | x\t%0,%2 |
8cb66696 | 8342 | xy\t%0,%2 |
0dfa6c5e | 8343 | # |
19b63d8e | 8344 | #" |
65b1d8ea | 8345 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8346 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8347 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8348 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8349 | |
8350 | (define_split | |
8351 | [(set (match_operand:SI 0 "s_operand" "") | |
8352 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8353 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8354 | "reload_completed" |
8355 | [(parallel | |
8356 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8357 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8358 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8359 | |
9db1d521 HP |
8360 | ; |
8361 | ; xorhi3 instruction pattern(s). | |
8362 | ; | |
8363 | ||
8cb66696 | 8364 | (define_insn "*xorhi3" |
65b1d8ea AK |
8365 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8366 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8367 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8368 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8369 | "s390_logical_operator_ok_p (operands)" |
8370 | "@ | |
ec24698e | 8371 | xilf\t%0,%x2 |
8cb66696 | 8372 | xr\t%0,%2 |
65b1d8ea | 8373 | xrk\t%0,%1,%2 |
0dfa6c5e | 8374 | # |
19b63d8e | 8375 | #" |
65b1d8ea AK |
8376 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8377 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8378 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8379 | |
8380 | (define_split | |
8381 | [(set (match_operand:HI 0 "s_operand" "") | |
8382 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8383 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8384 | "reload_completed" |
8385 | [(parallel | |
8386 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8387 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8388 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8389 | |
9db1d521 HP |
8390 | ; |
8391 | ; xorqi3 instruction pattern(s). | |
8392 | ; | |
8393 | ||
8cb66696 | 8394 | (define_insn "*xorqi3" |
65b1d8ea AK |
8395 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8396 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8397 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8398 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8399 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8400 | "@ |
ec24698e | 8401 | xilf\t%0,%b2 |
8cb66696 | 8402 | xr\t%0,%2 |
65b1d8ea | 8403 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8404 | xi\t%S0,%b2 |
8405 | xiy\t%S0,%b2 | |
19b63d8e | 8406 | #" |
65b1d8ea | 8407 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8408 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8409 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8410 | |
4023fb28 | 8411 | |
19b63d8e UW |
8412 | ; |
8413 | ; Block exclusive or (XC) patterns. | |
8414 | ; | |
8415 | ||
8416 | (define_insn "*xc" | |
8417 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8418 | (xor:BLK (match_dup 0) | |
8419 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8420 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8421 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8422 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8423 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8424 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8425 | |
8426 | (define_split | |
8427 | [(set (match_operand 0 "memory_operand" "") | |
8428 | (xor (match_dup 0) | |
8429 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8430 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8431 | "reload_completed |
8432 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8433 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8434 | [(parallel | |
8435 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8436 | (use (match_dup 2)) | |
ae156f85 | 8437 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8438 | { |
8439 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8440 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8441 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8442 | }) | |
8443 | ||
8444 | (define_peephole2 | |
8445 | [(parallel | |
8446 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8447 | (xor:BLK (match_dup 0) | |
8448 | (match_operand:BLK 1 "memory_operand" ""))) | |
8449 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8450 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8451 | (parallel |
8452 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8453 | (xor:BLK (match_dup 3) | |
8454 | (match_operand:BLK 4 "memory_operand" ""))) | |
8455 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8456 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8457 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8458 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8459 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8460 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8461 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8462 | [(parallel | |
8463 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8464 | (use (match_dup 8)) | |
ae156f85 | 8465 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8466 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8467 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8468 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8469 | ||
8470 | ; | |
8471 | ; Block xor (XC) patterns with src == dest. | |
8472 | ; | |
8473 | ||
8474 | (define_insn "*xc_zero" | |
8475 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8476 | (const_int 0)) | |
8477 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8478 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8479 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8480 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8481 | [(set_attr "op_type" "SS") |
8482 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8483 | |
8484 | (define_peephole2 | |
8485 | [(parallel | |
8486 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8487 | (const_int 0)) | |
8488 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8489 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8490 | (parallel |
8491 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8492 | (const_int 0)) | |
8493 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8494 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8495 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8496 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8497 | [(parallel | |
8498 | [(set (match_dup 4) (const_int 0)) | |
8499 | (use (match_dup 5)) | |
ae156f85 | 8500 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8501 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8502 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8503 | ||
4a9733f3 AK |
8504 | ; |
8505 | ;- Nxor instructions. | |
8506 | ; | |
8507 | ||
8508 | ; nxrk, nxgrk | |
8509 | (define_insn "*nxor<GPR:mode>_cc" | |
8510 | [(set (reg CC_REGNUM) | |
8511 | (compare | |
8512 | (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") | |
8513 | (match_operand:GPR 2 "register_operand" "d"))) | |
8514 | (const_int 0))) | |
8515 | (set (match_operand:GPR 0 "register_operand" "=d") | |
8516 | (xor:GPR (not:GPR (match_dup 1)) | |
8517 | (match_dup 2)))] | |
8518 | "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)" | |
8519 | "nx<GPR:g>rk\t%0,%1,%2" | |
8520 | [(set_attr "op_type" "RRF")]) | |
8521 | ||
8522 | ; nxrk, nxgrk | |
8523 | (define_insn "*nxor<mode>_cconly" | |
8524 | [(set (reg CC_REGNUM) | |
8525 | (compare | |
8526 | (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") | |
8527 | (match_operand:GPR 2 "register_operand" "d"))) | |
8528 | (const_int 0))) | |
8529 | (clobber (match_scratch:GPR 0 "=d"))] | |
8530 | "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)" | |
8531 | "nx<GPR:g>rk\t%0,%1,%2" | |
8532 | [(set_attr "op_type" "RRF")]) | |
8533 | ||
8534 | ; nxrk, nxgrk | |
8535 | (define_insn "*nxor<mode>" | |
8536 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8537 | (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") | |
8538 | (match_operand:GPR 2 "register_operand" "d")))) | |
8539 | (clobber (reg:CC CC_REGNUM))] | |
8540 | "TARGET_ARCH13" | |
8541 | "nx<GPR:g>rk\t%0,%1,%2" | |
8542 | [(set_attr "op_type" "RRF")]) | |
9db1d521 HP |
8543 | |
8544 | ;; | |
8545 | ;;- Negate instructions. | |
8546 | ;; | |
8547 | ||
8548 | ; | |
9a91a21f | 8549 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8550 | ; |
8551 | ||
9a91a21f | 8552 | (define_expand "neg<mode>2" |
9db1d521 | 8553 | [(parallel |
9a91a21f AS |
8554 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8555 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8556 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8557 | "" |
8558 | "") | |
8559 | ||
26a89301 | 8560 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8561 | [(set (reg CC_REGNUM) |
26a89301 UW |
8562 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8563 | (match_operand:SI 1 "register_operand" "d") 0) | |
8564 | (const_int 32)) (const_int 32))) | |
8565 | (const_int 0))) | |
8566 | (set (match_operand:DI 0 "register_operand" "=d") | |
8567 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8568 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8569 | "lcgfr\t%0,%1" |
729e750f WG |
8570 | [(set_attr "op_type" "RRE") |
8571 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8572 | |
26a89301 UW |
8573 | (define_insn "*negdi2_sign" |
8574 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8575 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8576 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8577 | "TARGET_ZARCH" |
26a89301 | 8578 | "lcgfr\t%0,%1" |
729e750f WG |
8579 | [(set_attr "op_type" "RRE") |
8580 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8581 | |
43a09b63 | 8582 | ; lcr, lcgr |
9a91a21f | 8583 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8584 | [(set (reg CC_REGNUM) |
9a91a21f | 8585 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8586 | (const_int 0))) |
9a91a21f AS |
8587 | (set (match_operand:GPR 0 "register_operand" "=d") |
8588 | (neg:GPR (match_dup 1)))] | |
8589 | "s390_match_ccmode (insn, CCAmode)" | |
8590 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8591 | [(set_attr "op_type" "RR<E>") |
8592 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8593 | |
8594 | ; lcr, lcgr | |
9a91a21f | 8595 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8596 | [(set (reg CC_REGNUM) |
9a91a21f | 8597 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8598 | (const_int 0))) |
9a91a21f AS |
8599 | (clobber (match_scratch:GPR 0 "=d"))] |
8600 | "s390_match_ccmode (insn, CCAmode)" | |
8601 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8602 | [(set_attr "op_type" "RR<E>") |
8603 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8604 | |
8605 | ; lcr, lcgr | |
9a91a21f AS |
8606 | (define_insn "*neg<mode>2" |
8607 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8608 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8609 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8610 | "" |
8611 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8612 | [(set_attr "op_type" "RR<E>") |
8613 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8614 | |
b7d19263 | 8615 | (define_insn "*negdi2_31" |
9db1d521 HP |
8616 | [(set (match_operand:DI 0 "register_operand" "=d") |
8617 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8618 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8619 | "!TARGET_ZARCH" |
b7d19263 AK |
8620 | "#") |
8621 | ||
8622 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8623 | ||
8624 | ; Doing the twos complement separately on the SImode parts does an | |
8625 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8626 | ; ... unless the +1 on the low part created an overflow. | |
8627 | ||
8628 | (define_split | |
8629 | [(set (match_operand:DI 0 "register_operand" "") | |
8630 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8631 | (clobber (reg:CC CC_REGNUM))] | |
8632 | "!TARGET_ZARCH | |
8633 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8634 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8635 | && reload_completed" | |
26a89301 UW |
8636 | [(parallel |
8637 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8638 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8639 | (parallel |
ae156f85 | 8640 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8641 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8642 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8643 | (set (pc) | |
ae156f85 | 8644 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8645 | (pc) |
8646 | (label_ref (match_dup 6)))) | |
8647 | (parallel | |
8648 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8649 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8650 | (match_dup 6)] |
8651 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8652 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8653 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8654 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8655 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8656 | |
b7d19263 AK |
8657 | ; Like above but first make a copy of the low part of the src operand |
8658 | ; since it might overlap with the high part of the destination. | |
8659 | ||
8660 | (define_split | |
8661 | [(set (match_operand:DI 0 "register_operand" "") | |
8662 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8663 | (clobber (reg:CC CC_REGNUM))] | |
8664 | "!TARGET_ZARCH | |
8665 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8666 | && reload_completed" | |
8667 | [; Make a backup of op5 first | |
8668 | (set (match_dup 4) (match_dup 5)) | |
8669 | ; Setting op2 here might clobber op5 | |
8670 | (parallel | |
8671 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8672 | (clobber (reg:CC CC_REGNUM))]) | |
8673 | (parallel | |
8674 | [(set (reg:CCAP CC_REGNUM) | |
8675 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8676 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8677 | (set (pc) | |
8678 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8679 | (pc) | |
8680 | (label_ref (match_dup 6)))) | |
8681 | (parallel | |
8682 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8683 | (clobber (reg:CC CC_REGNUM))]) | |
8684 | (match_dup 6)] | |
8685 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8686 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8687 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8688 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8689 | operands[6] = gen_label_rtx ();") | |
8690 | ||
9db1d521 | 8691 | ; |
f5905b37 | 8692 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8693 | ; |
8694 | ||
f5905b37 | 8695 | (define_expand "neg<mode>2" |
9db1d521 | 8696 | [(parallel |
2de2b3f9 AK |
8697 | [(set (match_operand:BFP 0 "register_operand") |
8698 | (neg:BFP (match_operand:BFP 1 "register_operand"))) | |
ae156f85 | 8699 | (clobber (reg:CC CC_REGNUM))])] |
2de2b3f9 | 8700 | "TARGET_HARD_FLOAT") |
9db1d521 | 8701 | |
43a09b63 | 8702 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8703 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8704 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8705 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8706 | (match_operand:BFP 2 "const0_operand" ""))) | |
8707 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8708 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8709 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8710 | "lc<xde>br\t%0,%1" |
26a89301 | 8711 | [(set_attr "op_type" "RRE") |
f5905b37 | 8712 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8713 | |
8714 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8715 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8716 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8717 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8718 | (match_operand:BFP 2 "const0_operand" ""))) | |
8719 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8720 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8721 | "lc<xde>br\t%0,%1" |
26a89301 | 8722 | [(set_attr "op_type" "RRE") |
f5905b37 | 8723 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8724 | |
85dae55a AK |
8725 | ; lcdfr |
8726 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8727 | [(set (match_operand:FP 0 "register_operand" "=f") |
8728 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8729 | "TARGET_DFP" |
85dae55a AK |
8730 | "lcdfr\t%0,%1" |
8731 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8732 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8733 | |
43a09b63 | 8734 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8735 | ; FIXME: wflcdb does not clobber cc |
2de2b3f9 | 8736 | ; FIXME: Does wflcdb ever match here? |
f5905b37 | 8737 | (define_insn "*neg<mode>2" |
2de2b3f9 AK |
8738 | [(set (match_operand:BFP 0 "register_operand" "=f,v,v") |
8739 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) | |
ae156f85 | 8740 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8741 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8742 | "@ |
8743 | lc<xde>br\t%0,%1 | |
2de2b3f9 AK |
8744 | wflcdb\t%0,%1 |
8745 | wflcsb\t%0,%1" | |
8746 | [(set_attr "op_type" "RRE,VRR,VRR") | |
8747 | (set_attr "cpu_facility" "*,vx,vxe") | |
8748 | (set_attr "type" "fsimp<mode>,*,*") | |
8749 | (set_attr "enabled" "*,<DF>,<SF>")]) | |
9db1d521 | 8750 | |
9db1d521 HP |
8751 | |
8752 | ;; | |
8753 | ;;- Absolute value instructions. | |
8754 | ;; | |
8755 | ||
8756 | ; | |
9a91a21f | 8757 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8758 | ; |
8759 | ||
26a89301 | 8760 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8761 | [(set (reg CC_REGNUM) |
26a89301 UW |
8762 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8763 | (match_operand:SI 1 "register_operand" "d") 0) | |
8764 | (const_int 32)) (const_int 32))) | |
8765 | (const_int 0))) | |
8766 | (set (match_operand:DI 0 "register_operand" "=d") | |
8767 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8768 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8769 | "lpgfr\t%0,%1" |
729e750f WG |
8770 | [(set_attr "op_type" "RRE") |
8771 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8772 | |
8773 | (define_insn "*absdi2_sign" | |
8774 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8775 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8776 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8777 | "TARGET_ZARCH" |
26a89301 | 8778 | "lpgfr\t%0,%1" |
729e750f WG |
8779 | [(set_attr "op_type" "RRE") |
8780 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8781 | |
43a09b63 | 8782 | ; lpr, lpgr |
9a91a21f | 8783 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8784 | [(set (reg CC_REGNUM) |
9a91a21f | 8785 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8786 | (const_int 0))) |
9a91a21f AS |
8787 | (set (match_operand:GPR 0 "register_operand" "=d") |
8788 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8789 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8790 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8791 | [(set_attr "op_type" "RR<E>") |
8792 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8793 | |
9381e3f1 | 8794 | ; lpr, lpgr |
9a91a21f | 8795 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8796 | [(set (reg CC_REGNUM) |
9a91a21f | 8797 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8798 | (const_int 0))) |
9a91a21f | 8799 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8800 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8801 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8802 | [(set_attr "op_type" "RR<E>") |
8803 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8804 | |
8805 | ; lpr, lpgr | |
9a91a21f AS |
8806 | (define_insn "abs<mode>2" |
8807 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8808 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8809 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8810 | "" |
9a91a21f | 8811 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8812 | [(set_attr "op_type" "RR<E>") |
8813 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8814 | |
9db1d521 | 8815 | ; |
f5905b37 | 8816 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8817 | ; |
8818 | ||
f5905b37 | 8819 | (define_expand "abs<mode>2" |
9db1d521 | 8820 | [(parallel |
7b6baae1 AK |
8821 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8822 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8823 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8824 | "TARGET_HARD_FLOAT" |
8825 | "") | |
8826 | ||
43a09b63 | 8827 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8828 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8829 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8830 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8831 | (match_operand:BFP 2 "const0_operand" ""))) | |
8832 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8833 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8834 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8835 | "lp<xde>br\t%0,%1" |
26a89301 | 8836 | [(set_attr "op_type" "RRE") |
f5905b37 | 8837 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8838 | |
8839 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8840 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8841 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8842 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8843 | (match_operand:BFP 2 "const0_operand" ""))) | |
8844 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8845 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8846 | "lp<xde>br\t%0,%1" |
26a89301 | 8847 | [(set_attr "op_type" "RRE") |
f5905b37 | 8848 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8849 | |
85dae55a AK |
8850 | ; lpdfr |
8851 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8852 | [(set (match_operand:FP 0 "register_operand" "=f") |
8853 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8854 | "TARGET_DFP" |
85dae55a AK |
8855 | "lpdfr\t%0,%1" |
8856 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8857 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8858 | |
43a09b63 | 8859 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8860 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8861 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8862 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8863 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8864 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8865 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8866 | "@ |
8867 | lp<xde>br\t%0,%1 | |
8868 | wflpdb\t%0,%1" | |
8869 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8870 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8871 | (set_attr "type" "fsimp<mode>,*") |
8872 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8873 | |
9db1d521 | 8874 | |
3ef093a8 AK |
8875 | ;; |
8876 | ;;- Negated absolute value instructions | |
8877 | ;; | |
8878 | ||
8879 | ; | |
8880 | ; Integer | |
8881 | ; | |
8882 | ||
26a89301 | 8883 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8884 | [(set (reg CC_REGNUM) |
26a89301 UW |
8885 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8886 | (match_operand:SI 1 "register_operand" "d") 0) | |
8887 | (const_int 32)) (const_int 32)))) | |
8888 | (const_int 0))) | |
8889 | (set (match_operand:DI 0 "register_operand" "=d") | |
8890 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8891 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8892 | "lngfr\t%0,%1" |
729e750f WG |
8893 | [(set_attr "op_type" "RRE") |
8894 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8895 | |
26a89301 UW |
8896 | (define_insn "*negabsdi2_sign" |
8897 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8898 | (neg:DI (abs:DI (sign_extend:DI | |
8899 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8900 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8901 | "TARGET_ZARCH" |
26a89301 | 8902 | "lngfr\t%0,%1" |
729e750f WG |
8903 | [(set_attr "op_type" "RRE") |
8904 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8905 | |
43a09b63 | 8906 | ; lnr, lngr |
9a91a21f | 8907 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8908 | [(set (reg CC_REGNUM) |
9a91a21f | 8909 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8910 | (const_int 0))) |
9a91a21f AS |
8911 | (set (match_operand:GPR 0 "register_operand" "=d") |
8912 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8913 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8914 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8915 | [(set_attr "op_type" "RR<E>") |
8916 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8917 | |
8918 | ; lnr, lngr | |
9a91a21f | 8919 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8920 | [(set (reg CC_REGNUM) |
9a91a21f | 8921 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8922 | (const_int 0))) |
9a91a21f | 8923 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8924 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8925 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8926 | [(set_attr "op_type" "RR<E>") |
8927 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8928 | |
8929 | ; lnr, lngr | |
9a91a21f AS |
8930 | (define_insn "*negabs<mode>2" |
8931 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8932 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8933 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8934 | "" |
9a91a21f | 8935 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8936 | [(set_attr "op_type" "RR<E>") |
8937 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8938 | |
3ef093a8 AK |
8939 | ; |
8940 | ; Floating point | |
8941 | ; | |
8942 | ||
43a09b63 | 8943 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8944 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8945 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8946 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8947 | (match_operand:BFP 2 "const0_operand" ""))) | |
8948 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8949 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8950 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8951 | "ln<xde>br\t%0,%1" |
26a89301 | 8952 | [(set_attr "op_type" "RRE") |
f5905b37 | 8953 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8954 | |
8955 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8956 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8957 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8958 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8959 | (match_operand:BFP 2 "const0_operand" ""))) | |
8960 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8961 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8962 | "ln<xde>br\t%0,%1" |
26a89301 | 8963 | [(set_attr "op_type" "RRE") |
f5905b37 | 8964 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8965 | |
85dae55a AK |
8966 | ; lndfr |
8967 | (define_insn "*negabs<mode>2_nocc" | |
ef2df516 RS |
8968 | [(set (match_operand:FP 0 "register_operand" "=f") |
8969 | (neg:FP (abs:FP (match_operand:FP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8970 | "TARGET_DFP" |
85dae55a AK |
8971 | "lndfr\t%0,%1" |
8972 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8973 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8974 | |
43a09b63 | 8975 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8976 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8977 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8978 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8979 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8980 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8981 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8982 | "@ |
8983 | ln<xde>br\t%0,%1 | |
8984 | wflndb\t%0,%1" | |
8985 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8986 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8987 | (set_attr "type" "fsimp<mode>,*") |
8988 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8989 | |
4023fb28 UW |
8990 | ;; |
8991 | ;;- Square root instructions. | |
8992 | ;; | |
8993 | ||
8994 | ; | |
f5905b37 | 8995 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8996 | ; |
8997 | ||
9381e3f1 | 8998 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8999 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
9000 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
9001 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 9002 | "TARGET_HARD_FLOAT" |
4023fb28 | 9003 | "@ |
f61a2c7d | 9004 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
9005 | sq<xde>b\t%0,%1 |
9006 | wfsqdb\t%v0,%v1" | |
9007 | [(set_attr "op_type" "RRE,RXE,VRR") | |
9008 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 9009 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 9010 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 9011 | |
9db1d521 HP |
9012 | |
9013 | ;; | |
9014 | ;;- One complement instructions. | |
9015 | ;; | |
9016 | ||
9017 | ; | |
342cf42b | 9018 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 9019 | ; |
c7453384 | 9020 | |
342cf42b | 9021 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 9022 | [(parallel |
342cf42b AS |
9023 | [(set (match_operand:INT 0 "register_operand" "") |
9024 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
9025 | (const_int -1))) | |
ae156f85 | 9026 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 9027 | "" |
4023fb28 | 9028 | "") |
9db1d521 HP |
9029 | |
9030 | ||
ec24698e UW |
9031 | ;; |
9032 | ;; Find leftmost bit instructions. | |
9033 | ;; | |
9034 | ||
9035 | (define_expand "clzdi2" | |
9036 | [(set (match_operand:DI 0 "register_operand" "=d") | |
9037 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 9038 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 9039 | { |
d8485bdb TS |
9040 | rtx_insn *insn; |
9041 | rtx clz_equal; | |
ec24698e | 9042 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 9043 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
9044 | |
9045 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
9046 | ||
9047 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
9048 | ||
9381e3f1 | 9049 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 9050 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
9051 | |
9052 | DONE; | |
9053 | }) | |
9054 | ||
33f3393a AK |
9055 | ; CLZ result is in hard reg op0 - this is the high part of the target operand |
9056 | ; The source with the left-most one bit cleared is in hard reg op0 + 1 - the low part | |
ec24698e UW |
9057 | (define_insn "clztidi2" |
9058 | [(set (match_operand:TI 0 "register_operand" "=d") | |
9059 | (ior:TI | |
33f3393a AK |
9060 | (ashift:TI (zero_extend:TI (clz:DI (match_operand:DI 1 "register_operand" "d"))) |
9061 | (const_int 64)) | |
9062 | (zero_extend:TI | |
9063 | (xor:DI (match_dup 1) | |
9064 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
9065 | (subreg:SI (clz:DI (match_dup 1)) 4)))))) | |
ec24698e | 9066 | (clobber (reg:CC CC_REGNUM))] |
406fde6e | 9067 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 9068 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
9069 | "flogr\t%0,%1" |
9070 | [(set_attr "op_type" "RRE")]) | |
9071 | ||
9072 | ||
9db1d521 HP |
9073 | ;; |
9074 | ;;- Rotate instructions. | |
9075 | ;; | |
9076 | ||
9077 | ; | |
9a91a21f | 9078 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
9079 | ; |
9080 | ||
191eb16d AK |
9081 | (define_expand "rotl<mode>3" |
9082 | [(set (match_operand:GPR 0 "register_operand" "") | |
9083 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
e2839e47 | 9084 | (match_operand:QI 2 "shift_count_operand" "")))] |
8cc6307c | 9085 | "" |
191eb16d | 9086 | "") |
9db1d521 | 9087 | |
43a09b63 | 9088 | ; rll, rllg |
e2839e47 | 9089 | (define_insn "*rotl<mode>3" |
191eb16d AK |
9090 | [(set (match_operand:GPR 0 "register_operand" "=d") |
9091 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
e2839e47 | 9092 | (match_operand:QI 2 "shift_count_operand" "jsc")))] |
8cc6307c | 9093 | "" |
e2839e47 | 9094 | "rll<g>\t%0,%1,%Y2" |
4989e88a | 9095 | [(set_attr "op_type" "RSE") |
9381e3f1 | 9096 | (set_attr "atype" "reg") |
191eb16d | 9097 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 9098 | |
9db1d521 HP |
9099 | |
9100 | ;; | |
f337b930 | 9101 | ;;- Shift instructions. |
9db1d521 | 9102 | ;; |
9db1d521 HP |
9103 | |
9104 | ; | |
1b48c8cc | 9105 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 9106 | ; Left shifts and logical right shifts |
9db1d521 | 9107 | |
1b48c8cc AS |
9108 | (define_expand "<shift><mode>3" |
9109 | [(set (match_operand:DSI 0 "register_operand" "") | |
9110 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
e2839e47 | 9111 | (match_operand:QI 2 "shift_count_operand" "")))] |
9db1d521 HP |
9112 | "" |
9113 | "") | |
9114 | ||
adf22b3f | 9115 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 9116 | ; sldl, srdl |
e2839e47 | 9117 | (define_insn "*<shift>di3_31" |
adf22b3f AK |
9118 | [(set (match_operand:DI 0 "register_operand" "=d") |
9119 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
e2839e47 | 9120 | (match_operand:QI 2 "shift_count_operand" "jsc")))] |
9602b6a1 | 9121 | "!TARGET_ZARCH" |
e2839e47 | 9122 | "s<lr>dl\t%0,%Y2" |
077dab3b | 9123 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
9124 | (set_attr "atype" "reg") |
9125 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9126 | |
adf22b3f AK |
9127 | |
9128 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 9129 | ; sll, srl, sllg, srlg, sllk, srlk |
e2839e47 | 9130 | (define_insn "*<shift><mode>3" |
adf22b3f AK |
9131 | [(set (match_operand:GPR 0 "register_operand" "=d, d") |
9132 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
e2839e47 | 9133 | (match_operand:QI 2 "shift_count_operand" "jsc,jsc")))] |
1b48c8cc | 9134 | "" |
65b1d8ea | 9135 | "@ |
e2839e47 RD |
9136 | s<lr>l<g>\t%0,<1>%Y2 |
9137 | s<lr>l<gk>\t%0,%1,%Y2" | |
65b1d8ea AK |
9138 | [(set_attr "op_type" "RS<E>,RSY") |
9139 | (set_attr "atype" "reg,reg") | |
9140 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 9141 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 9142 | |
e2839e47 | 9143 | |
9db1d521 | 9144 | ; |
1b48c8cc | 9145 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 9146 | ; Arithmetic right shifts |
9db1d521 | 9147 | |
1b48c8cc | 9148 | (define_expand "ashr<mode>3" |
9db1d521 | 9149 | [(parallel |
1b48c8cc AS |
9150 | [(set (match_operand:DSI 0 "register_operand" "") |
9151 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
e2839e47 | 9152 | (match_operand:QI 2 "shift_count_operand" ""))) |
ae156f85 | 9153 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
9154 | "" |
9155 | "") | |
9156 | ||
a9fcf821 AK |
9157 | ; FIXME: The number of alternatives is doubled here to match the fix |
9158 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
9159 | ; The right fix should be to support match_scratch in the output | |
9160 | ; pattern of a define_subst. | |
e2839e47 | 9161 | (define_insn "*ashrdi3_31<setcc><cconly>" |
a9fcf821 AK |
9162 | [(set (match_operand:DI 0 "register_operand" "=d, d") |
9163 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
e2839e47 | 9164 | (match_operand:QI 2 "shift_count_operand" "jsc,jsc"))) |
ae156f85 | 9165 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9166 | "!TARGET_ZARCH" |
65b1d8ea | 9167 | "@ |
e2839e47 RD |
9168 | srda\t%0,%Y2 |
9169 | srda\t%0,%Y2" | |
a9fcf821 AK |
9170 | [(set_attr "op_type" "RS") |
9171 | (set_attr "atype" "reg")]) | |
ecbe845e | 9172 | |
ecbe845e | 9173 | |
43a09b63 | 9174 | ; sra, srag |
e2839e47 | 9175 | (define_insn "*ashr<mode>3<setcc><cconly>" |
a9fcf821 AK |
9176 | [(set (match_operand:GPR 0 "register_operand" "=d, d") |
9177 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
e2839e47 | 9178 | (match_operand:QI 2 "shift_count_operand" "jsc,jsc"))) |
ae156f85 | 9179 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 9180 | "" |
65b1d8ea | 9181 | "@ |
e2839e47 RD |
9182 | sra<g>\t%0,<1>%Y2 |
9183 | sra<gk>\t%0,%1,%Y2" | |
65b1d8ea | 9184 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 9185 | (set_attr "atype" "reg") |
01496eca | 9186 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 9187 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 9188 | |
9db1d521 | 9189 | |
9db1d521 HP |
9190 | ;; |
9191 | ;; Branch instruction patterns. | |
9192 | ;; | |
9193 | ||
f90b7a5a | 9194 | (define_expand "cbranch<mode>4" |
fa77b251 | 9195 | [(set (pc) |
f90b7a5a PB |
9196 | (if_then_else (match_operator 0 "comparison_operator" |
9197 | [(match_operand:GPR 1 "register_operand" "") | |
9198 | (match_operand:GPR 2 "general_operand" "")]) | |
9199 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 9200 | (pc)))] |
ba956982 | 9201 | "" |
f90b7a5a PB |
9202 | "s390_emit_jump (operands[3], |
9203 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
9204 | DONE;") | |
9205 | ||
9206 | (define_expand "cbranch<mode>4" | |
9207 | [(set (pc) | |
9208 | (if_then_else (match_operator 0 "comparison_operator" | |
9209 | [(match_operand:FP 1 "register_operand" "") | |
9210 | (match_operand:FP 2 "general_operand" "")]) | |
9211 | (label_ref (match_operand 3 "" "")) | |
9212 | (pc)))] | |
9213 | "TARGET_HARD_FLOAT" | |
9214 | "s390_emit_jump (operands[3], | |
9215 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
9216 | DONE;") | |
9217 | ||
9218 | (define_expand "cbranchcc4" | |
9219 | [(set (pc) | |
de6fba39 | 9220 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 9221 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 9222 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
9223 | (label_ref (match_operand 3 "" "")) |
9224 | (pc)))] | |
de6fba39 UW |
9225 | "" |
9226 | "") | |
ba956982 | 9227 | |
9db1d521 HP |
9228 | |
9229 | ;; | |
9230 | ;;- Conditional jump instructions. | |
9231 | ;; | |
9232 | ||
6590e19a UW |
9233 | (define_insn "*cjump_64" |
9234 | [(set (pc) | |
9235 | (if_then_else | |
5a3fe9b6 AK |
9236 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
9237 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
9238 | (label_ref (match_operand 0 "" "")) |
9239 | (pc)))] | |
8cc6307c | 9240 | "" |
9db1d521 | 9241 | { |
13e58269 | 9242 | if (get_attr_length (insn) == 4) |
d40c829f | 9243 | return "j%C1\t%l0"; |
6590e19a | 9244 | else |
d40c829f | 9245 | return "jg%C1\t%l0"; |
6590e19a UW |
9246 | } |
9247 | [(set_attr "op_type" "RI") | |
9248 | (set_attr "type" "branch") | |
9249 | (set (attr "length") | |
9250 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9251 | (const_int 4) (const_int 6)))]) | |
9252 | ||
f314b9b1 | 9253 | (define_insn "*cjump_long" |
6590e19a UW |
9254 | [(set (pc) |
9255 | (if_then_else | |
ae156f85 | 9256 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 9257 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 9258 | (pc)))] |
84b4c7b5 | 9259 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9260 | { |
9261 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9262 | return "b%C1r\t%0"; |
f314b9b1 | 9263 | else |
d40c829f | 9264 | return "b%C1\t%a0"; |
10bbf137 | 9265 | } |
c7453384 | 9266 | [(set (attr "op_type") |
f314b9b1 UW |
9267 | (if_then_else (match_operand 0 "register_operand" "") |
9268 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9269 | (set (attr "mnemonic") |
9270 | (if_then_else (match_operand 0 "register_operand" "") | |
9271 | (const_string "bcr") (const_string "bc"))) | |
6590e19a | 9272 | (set_attr "type" "branch") |
077dab3b | 9273 | (set_attr "atype" "agen")]) |
9db1d521 | 9274 | |
177bc204 RS |
9275 | ;; A conditional return instruction. |
9276 | (define_insn "*c<code>" | |
9277 | [(set (pc) | |
9278 | (if_then_else | |
9279 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
9280 | (ANY_RETURN) | |
9281 | (pc)))] | |
9282 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
9283 | { |
9284 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
9285 | { | |
9286 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
9287 | INVALID_REGNUM, | |
9288 | operands[0], | |
9289 | s390_indirect_branch_type_return); | |
9290 | return ""; | |
9291 | } | |
9292 | else | |
9293 | return "b%C0r\t%%r14"; | |
9294 | } | |
9295 | [(set (attr "op_type") | |
9296 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9297 | (const_string "RIL") | |
9298 | (const_string "RR"))) | |
9299 | (set (attr "mnemonic") | |
9300 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9301 | (const_string "brcl") | |
9302 | (const_string "bcr"))) | |
177bc204 RS |
9303 | (set_attr "type" "jsr") |
9304 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
9305 | |
9306 | ;; | |
9307 | ;;- Negated conditional jump instructions. | |
9308 | ;; | |
9309 | ||
6590e19a UW |
9310 | (define_insn "*icjump_64" |
9311 | [(set (pc) | |
9312 | (if_then_else | |
ae156f85 | 9313 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9314 | (pc) |
9315 | (label_ref (match_operand 0 "" ""))))] | |
8cc6307c | 9316 | "" |
c7453384 | 9317 | { |
13e58269 | 9318 | if (get_attr_length (insn) == 4) |
d40c829f | 9319 | return "j%D1\t%l0"; |
6590e19a | 9320 | else |
d40c829f | 9321 | return "jg%D1\t%l0"; |
6590e19a UW |
9322 | } |
9323 | [(set_attr "op_type" "RI") | |
9324 | (set_attr "type" "branch") | |
9325 | (set (attr "length") | |
9326 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9327 | (const_int 4) (const_int 6)))]) | |
9328 | ||
f314b9b1 | 9329 | (define_insn "*icjump_long" |
6590e19a UW |
9330 | [(set (pc) |
9331 | (if_then_else | |
ae156f85 | 9332 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 9333 | (pc) |
4fe6dea8 | 9334 | (match_operand 0 "address_operand" "ZQZR")))] |
84b4c7b5 | 9335 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9336 | { |
9337 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9338 | return "b%D1r\t%0"; |
f314b9b1 | 9339 | else |
d40c829f | 9340 | return "b%D1\t%a0"; |
10bbf137 | 9341 | } |
c7453384 | 9342 | [(set (attr "op_type") |
f314b9b1 UW |
9343 | (if_then_else (match_operand 0 "register_operand" "") |
9344 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9345 | (set (attr "mnemonic") |
9346 | (if_then_else (match_operand 0 "register_operand" "") | |
9347 | (const_string "bcr") (const_string "bc"))) | |
077dab3b HP |
9348 | (set_attr "type" "branch") |
9349 | (set_attr "atype" "agen")]) | |
9db1d521 | 9350 | |
4456530d HP |
9351 | ;; |
9352 | ;;- Trap instructions. | |
9353 | ;; | |
9354 | ||
9355 | (define_insn "trap" | |
9356 | [(trap_if (const_int 1) (const_int 0))] | |
9357 | "" | |
d40c829f | 9358 | "j\t.+2" |
6590e19a | 9359 | [(set_attr "op_type" "RI") |
077dab3b | 9360 | (set_attr "type" "branch")]) |
4456530d | 9361 | |
f90b7a5a PB |
9362 | (define_expand "ctrap<mode>4" |
9363 | [(trap_if (match_operator 0 "comparison_operator" | |
9364 | [(match_operand:GPR 1 "register_operand" "") | |
9365 | (match_operand:GPR 2 "general_operand" "")]) | |
9366 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 9367 | "" |
f90b7a5a PB |
9368 | { |
9369 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9370 | operands[1], operands[2]); | |
9371 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9372 | DONE; | |
9373 | }) | |
9374 | ||
9375 | (define_expand "ctrap<mode>4" | |
9376 | [(trap_if (match_operator 0 "comparison_operator" | |
9377 | [(match_operand:FP 1 "register_operand" "") | |
9378 | (match_operand:FP 2 "general_operand" "")]) | |
9379 | (match_operand 3 "const0_operand" ""))] | |
9380 | "" | |
9381 | { | |
9382 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9383 | operands[1], operands[2]); | |
9384 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9385 | DONE; | |
9386 | }) | |
4456530d | 9387 | |
f90b7a5a PB |
9388 | (define_insn "condtrap" |
9389 | [(trap_if (match_operator 0 "s390_comparison" | |
9390 | [(match_operand 1 "cc_reg_operand" "c") | |
9391 | (const_int 0)]) | |
4456530d HP |
9392 | (const_int 0))] |
9393 | "" | |
d40c829f | 9394 | "j%C0\t.+2"; |
077dab3b HP |
9395 | [(set_attr "op_type" "RI") |
9396 | (set_attr "type" "branch")]) | |
9db1d521 | 9397 | |
963fc8d0 AK |
9398 | ; crt, cgrt, cit, cgit |
9399 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9400 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9401 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9402 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9403 | (const_int 0))] | |
9404 | "TARGET_Z10" | |
9405 | "@ | |
9406 | c<g>rt%C0\t%1,%2 | |
9407 | c<g>it%C0\t%1,%h2" | |
9408 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9409 | (set_attr "type" "branch") |
729e750f | 9410 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9411 | |
22ac2c2f | 9412 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9413 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9414 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9415 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9416 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9417 | (const_int 0))] |
9418 | "TARGET_Z10" | |
9419 | "@ | |
9420 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9421 | cl<gf>it%C0\t%1,%x2 |
9422 | cl<g>t%C0\t%1,%2" | |
9423 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9424 | (set_attr "type" "branch") | |
9425 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9426 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9427 | ||
9428 | ; lat, lgat | |
9429 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9430 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9431 | (const_int 0)) |
9432 | (const_int 0)) | |
9433 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9434 | (match_dup 0))] | |
9435 | "TARGET_ZEC12" | |
9436 | "l<g>at\t%1,%0" | |
9437 | [(set_attr "op_type" "RXY")]) | |
9438 | ||
963fc8d0 | 9439 | |
9db1d521 | 9440 | ;; |
0a3bdf9d | 9441 | ;;- Loop instructions. |
9db1d521 | 9442 | ;; |
0a3bdf9d UW |
9443 | ;; This is all complicated by the fact that since this is a jump insn |
9444 | ;; we must handle our own output reloads. | |
c7453384 | 9445 | |
f1149235 AK |
9446 | ;; branch on index |
9447 | ||
9448 | ; This splitter will be matched by combine and has to add the 2 moves | |
9449 | ; necessary to load the compare and the increment values into a | |
9450 | ; register pair as needed by brxle. | |
9451 | ||
9452 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9453 | [(set (pc) | |
9454 | (if_then_else | |
9455 | (match_operator 6 "s390_brx_operator" | |
9456 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9457 | (match_operand:GPR 2 "general_operand" "")) | |
9458 | (match_operand:GPR 3 "register_operand" "")]) | |
9459 | (label_ref (match_operand 0 "" "")) | |
9460 | (pc))) | |
9461 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9462 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9463 | (clobber (match_scratch:GPR 5 ""))] | |
8cc6307c | 9464 | "" |
f1149235 AK |
9465 | "#" |
9466 | "!reload_completed && !reload_in_progress" | |
9467 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9468 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9469 | (parallel [(set (pc) | |
9470 | (if_then_else | |
9471 | (match_op_dup 6 | |
9472 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9473 | (match_dup 8)]) | |
9474 | (label_ref (match_dup 0)) | |
9475 | (pc))) | |
9476 | (set (match_dup 4) | |
9477 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9478 | (clobber (match_dup 5)) | |
9479 | (clobber (reg:CC CC_REGNUM))])] | |
9480 | { | |
9481 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9482 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9483 | gen_highpart (word_mode, dreg)); | |
9484 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9485 | gen_lowpart (word_mode, dreg)); | |
9486 | }) | |
9487 | ||
9488 | ; brxlg, brxhg | |
9489 | ||
9490 | (define_insn_and_split "*brxg_64bit" | |
9491 | [(set (pc) | |
9492 | (if_then_else | |
9493 | (match_operator 5 "s390_brx_operator" | |
9494 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9495 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9496 | (subreg:DI (match_dup 2) 8)]) | |
9497 | (label_ref (match_operand 0 "" "")) | |
9498 | (pc))) | |
9499 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9500 | (plus:DI (match_dup 1) | |
9501 | (subreg:DI (match_dup 2) 0))) | |
9502 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9503 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9504 | "TARGET_ZARCH" |
f1149235 AK |
9505 | { |
9506 | if (which_alternative != 0) | |
9507 | return "#"; | |
9508 | else if (get_attr_length (insn) == 6) | |
9509 | return "brx%E5g\t%1,%2,%l0"; | |
9510 | else | |
9511 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9512 | } | |
9513 | "&& reload_completed | |
9514 | && (!REG_P (operands[3]) | |
9515 | || !rtx_equal_p (operands[1], operands[3]))" | |
9516 | [(set (match_dup 4) (match_dup 1)) | |
9517 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9518 | (clobber (reg:CC CC_REGNUM))]) | |
9519 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9520 | (set (match_dup 3) (match_dup 4)) | |
9521 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9522 | (label_ref (match_dup 0)) | |
9523 | (pc)))] | |
9524 | "" | |
9525 | [(set_attr "op_type" "RIE") | |
9526 | (set_attr "type" "branch") | |
9527 | (set (attr "length") | |
9528 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9529 | (const_int 6) (const_int 16)))]) | |
9530 | ||
9531 | ; brxle, brxh | |
9532 | ||
9533 | (define_insn_and_split "*brx_64bit" | |
9534 | [(set (pc) | |
9535 | (if_then_else | |
9536 | (match_operator 5 "s390_brx_operator" | |
9537 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9538 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9539 | (subreg:SI (match_dup 2) 12)]) | |
9540 | (label_ref (match_operand 0 "" "")) | |
9541 | (pc))) | |
9542 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9543 | (plus:SI (match_dup 1) | |
9544 | (subreg:SI (match_dup 2) 4))) | |
9545 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9546 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9547 | "TARGET_ZARCH" |
f1149235 AK |
9548 | { |
9549 | if (which_alternative != 0) | |
9550 | return "#"; | |
9551 | else if (get_attr_length (insn) == 6) | |
9552 | return "brx%C5\t%1,%2,%l0"; | |
9553 | else | |
9554 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9555 | } | |
9556 | "&& reload_completed | |
9557 | && (!REG_P (operands[3]) | |
9558 | || !rtx_equal_p (operands[1], operands[3]))" | |
9559 | [(set (match_dup 4) (match_dup 1)) | |
9560 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9561 | (clobber (reg:CC CC_REGNUM))]) | |
9562 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9563 | (set (match_dup 3) (match_dup 4)) | |
9564 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9565 | (label_ref (match_dup 0)) | |
9566 | (pc)))] | |
9567 | "" | |
9568 | [(set_attr "op_type" "RSI") | |
9569 | (set_attr "type" "branch") | |
9570 | (set (attr "length") | |
9571 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9572 | (const_int 6) (const_int 14)))]) | |
9573 | ||
9574 | ; brxle, brxh | |
9575 | ||
9576 | (define_insn_and_split "*brx_31bit" | |
9577 | [(set (pc) | |
9578 | (if_then_else | |
9579 | (match_operator 5 "s390_brx_operator" | |
9580 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9581 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9582 | (subreg:SI (match_dup 2) 4)]) | |
9583 | (label_ref (match_operand 0 "" "")) | |
9584 | (pc))) | |
9585 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9586 | (plus:SI (match_dup 1) | |
9587 | (subreg:SI (match_dup 2) 0))) | |
9588 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9589 | (clobber (reg:CC CC_REGNUM))] | |
8cc6307c | 9590 | "!TARGET_ZARCH" |
f1149235 AK |
9591 | { |
9592 | if (which_alternative != 0) | |
9593 | return "#"; | |
9594 | else if (get_attr_length (insn) == 6) | |
9595 | return "brx%C5\t%1,%2,%l0"; | |
9596 | else | |
9597 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9598 | } | |
9599 | "&& reload_completed | |
9600 | && (!REG_P (operands[3]) | |
9601 | || !rtx_equal_p (operands[1], operands[3]))" | |
9602 | [(set (match_dup 4) (match_dup 1)) | |
9603 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9604 | (clobber (reg:CC CC_REGNUM))]) | |
9605 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9606 | (set (match_dup 3) (match_dup 4)) | |
9607 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9608 | (label_ref (match_dup 0)) | |
9609 | (pc)))] | |
9610 | "" | |
9611 | [(set_attr "op_type" "RSI") | |
9612 | (set_attr "type" "branch") | |
9613 | (set (attr "length") | |
9614 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9615 | (const_int 6) (const_int 14)))]) | |
9616 | ||
9617 | ||
9618 | ;; branch on count | |
9619 | ||
0a3bdf9d UW |
9620 | (define_expand "doloop_end" |
9621 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9622 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9623 | "" |
0a3bdf9d | 9624 | { |
8cc6307c | 9625 | if (GET_MODE (operands[0]) == SImode) |
1d0216c8 | 9626 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9627 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9628 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9629 | else |
9630 | FAIL; | |
9631 | ||
9632 | DONE; | |
10bbf137 | 9633 | }) |
0a3bdf9d | 9634 | |
6590e19a | 9635 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9636 | [(set (pc) |
9637 | (if_then_else | |
7e665d18 | 9638 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9639 | (const_int 1)) |
9640 | (label_ref (match_operand 0 "" "")) | |
9641 | (pc))) | |
7e665d18 | 9642 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9643 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9644 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9645 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 9646 | "" |
0a3bdf9d UW |
9647 | { |
9648 | if (which_alternative != 0) | |
10bbf137 | 9649 | return "#"; |
0a3bdf9d | 9650 | else if (get_attr_length (insn) == 4) |
d40c829f | 9651 | return "brct\t%1,%l0"; |
6590e19a | 9652 | else |
545d16ff | 9653 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9654 | } |
9655 | "&& reload_completed | |
9656 | && (! REG_P (operands[2]) | |
9657 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9658 | [(set (match_dup 3) (match_dup 1)) |
9659 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9660 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9661 | (const_int 0))) | |
9662 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9663 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9664 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9665 | (label_ref (match_dup 0)) |
9666 | (pc)))] | |
9667 | "" | |
9668 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9669 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9670 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9671 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9672 | (set_attr "type" "branch") |
9673 | (set (attr "length") | |
9674 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9675 | (const_int 4) (const_int 10)))]) | |
9676 | ||
6590e19a | 9677 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9678 | [(set (pc) |
9679 | (if_then_else | |
7e665d18 | 9680 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9681 | (const_int 1)) |
9682 | (label_ref (match_operand 0 "" "")) | |
9683 | (pc))) | |
7e665d18 | 9684 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9685 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9686 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9687 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9688 | "TARGET_ZARCH" |
0a3bdf9d UW |
9689 | { |
9690 | if (which_alternative != 0) | |
10bbf137 | 9691 | return "#"; |
0a3bdf9d | 9692 | else if (get_attr_length (insn) == 4) |
d40c829f | 9693 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9694 | else |
545d16ff | 9695 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9696 | } |
6590e19a | 9697 | "&& reload_completed |
0a3bdf9d UW |
9698 | && (! REG_P (operands[2]) |
9699 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9700 | [(set (match_dup 3) (match_dup 1)) |
9701 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9702 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9703 | (const_int 0))) | |
9704 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9705 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9706 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9707 | (label_ref (match_dup 0)) |
0a3bdf9d | 9708 | (pc)))] |
6590e19a UW |
9709 | "" |
9710 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9711 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9712 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9713 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9714 | (set_attr "type" "branch") |
9715 | (set (attr "length") | |
9716 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9717 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9718 | |
9719 | ;; | |
9720 | ;;- Unconditional jump instructions. | |
9721 | ;; | |
9722 | ||
9723 | ; | |
9724 | ; jump instruction pattern(s). | |
9725 | ; | |
9726 | ||
6590e19a UW |
9727 | (define_expand "jump" |
9728 | [(match_operand 0 "" "")] | |
9db1d521 | 9729 | "" |
6590e19a UW |
9730 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9731 | ||
9732 | (define_insn "*jump64" | |
9733 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8cc6307c | 9734 | "" |
9db1d521 | 9735 | { |
13e58269 | 9736 | if (get_attr_length (insn) == 4) |
d40c829f | 9737 | return "j\t%l0"; |
6590e19a | 9738 | else |
d40c829f | 9739 | return "jg\t%l0"; |
6590e19a UW |
9740 | } |
9741 | [(set_attr "op_type" "RI") | |
9742 | (set_attr "type" "branch") | |
9743 | (set (attr "length") | |
9744 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9745 | (const_int 4) (const_int 6)))]) | |
9746 | ||
9db1d521 HP |
9747 | ; |
9748 | ; indirect-jump instruction pattern(s). | |
9749 | ; | |
9750 | ||
2841f550 AK |
9751 | (define_expand "indirect_jump" |
9752 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9753 | "" |
f314b9b1 | 9754 | { |
2841f550 AK |
9755 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9756 | ; | |
e9e8efc9 | 9757 | else if (TARGET_Z14 |
2841f550 AK |
9758 | && GET_MODE (operands[0]) == Pmode |
9759 | && memory_operand (operands[0], Pmode)) | |
9760 | ; | |
f314b9b1 | 9761 | else |
2841f550 | 9762 | operands[0] = force_reg (Pmode, operands[0]); |
84b4c7b5 AK |
9763 | |
9764 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9765 | { | |
9766 | operands[0] = force_reg (Pmode, operands[0]); | |
9767 | if (TARGET_CPU_Z10) | |
9768 | { | |
9769 | if (TARGET_64BIT) | |
9770 | emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); | |
9771 | else | |
9772 | emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); | |
9773 | } | |
9774 | else | |
9775 | { | |
9776 | if (TARGET_64BIT) | |
9777 | emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); | |
9778 | else | |
9779 | emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); | |
9780 | } | |
9781 | DONE; | |
9782 | } | |
9783 | ||
9784 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9785 | { | |
9786 | operands[0] = force_reg (Pmode, operands[0]); | |
9787 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9788 | if (TARGET_CPU_Z10) | |
9789 | { | |
9790 | if (TARGET_64BIT) | |
9791 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], | |
9792 | label_ref)); | |
9793 | else | |
9794 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], | |
9795 | label_ref)); | |
9796 | } | |
9797 | else | |
9798 | { | |
9799 | if (TARGET_64BIT) | |
9800 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], | |
9801 | label_ref, | |
9802 | force_reg (Pmode, label_ref))); | |
9803 | else | |
9804 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], | |
9805 | label_ref, | |
9806 | force_reg (Pmode, label_ref))); | |
9807 | } | |
9808 | DONE; | |
9809 | } | |
2841f550 AK |
9810 | }) |
9811 | ||
9812 | (define_insn "*indirect_jump" | |
9813 | [(set (pc) | |
84b4c7b5 AK |
9814 | (match_operand 0 "address_operand" "ZR"))] |
9815 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9816 | { | |
9817 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9818 | return "br\t%0"; | |
9819 | else | |
9820 | return "b\t%a0"; | |
9821 | } | |
9822 | [(set (attr "op_type") | |
9823 | (if_then_else (match_operand 0 "register_operand" "") | |
9824 | (const_string "RR") (const_string "RX"))) | |
9825 | (set (attr "mnemonic") | |
9826 | (if_then_else (match_operand 0 "register_operand" "") | |
9827 | (const_string "br") (const_string "b"))) | |
2841f550 | 9828 | (set_attr "type" "branch") |
84b4c7b5 AK |
9829 | (set_attr "atype" "agen")]) |
9830 | ||
9831 | (define_insn "indirect_jump_via_thunk<mode>_z10" | |
9832 | [(set (pc) | |
9833 | (match_operand:P 0 "register_operand" "a"))] | |
9834 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9835 | && TARGET_CPU_Z10" | |
9836 | { | |
9837 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9838 | INVALID_REGNUM, | |
9839 | NULL_RTX, | |
9840 | s390_indirect_branch_type_jump); | |
9841 | return ""; | |
9842 | } | |
9843 | [(set_attr "op_type" "RIL") | |
9844 | (set_attr "mnemonic" "jg") | |
9845 | (set_attr "type" "branch") | |
9846 | (set_attr "atype" "agen")]) | |
9847 | ||
9848 | (define_insn "indirect_jump_via_thunk<mode>" | |
9849 | [(set (pc) | |
9850 | (match_operand:P 0 "register_operand" " a")) | |
9851 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9852 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9853 | && !TARGET_CPU_Z10" | |
9854 | { | |
9855 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9856 | INVALID_REGNUM, | |
9857 | NULL_RTX, | |
9858 | s390_indirect_branch_type_jump); | |
9859 | return ""; | |
9860 | } | |
9861 | [(set_attr "op_type" "RIL") | |
9862 | (set_attr "mnemonic" "jg") | |
9863 | (set_attr "type" "branch") | |
9864 | (set_attr "atype" "agen")]) | |
9865 | ||
9866 | ||
9867 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9868 | ; from mark_jump_label. Without this the label_ref would become the | |
9869 | ; ONLY jump target of that jump breaking the control flow graph. | |
9870 | (define_insn "indirect_jump_via_inlinethunk<mode>_z10" | |
9871 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9872 | (const_int 0) | |
9873 | (const_int 0)) | |
9874 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9875 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9876 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9877 | && TARGET_CPU_Z10" | |
9878 | { | |
9879 | s390_indirect_branch_via_inline_thunk (operands[1]); | |
9880 | return ""; | |
9881 | } | |
9882 | [(set_attr "op_type" "RIL") | |
9883 | (set_attr "type" "branch") | |
9884 | (set_attr "length" "10")]) | |
9885 | ||
9886 | (define_insn "indirect_jump_via_inlinethunk<mode>" | |
9887 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9888 | (const_int 0) | |
9889 | (const_int 0)) | |
9890 | (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9891 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9892 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9893 | && !TARGET_CPU_Z10" | |
9894 | { | |
9895 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9896 | return ""; | |
9897 | } | |
9898 | [(set_attr "op_type" "RX") | |
9899 | (set_attr "type" "branch") | |
9900 | (set_attr "length" "8")]) | |
2841f550 AK |
9901 | |
9902 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9903 | ; checked against address constraints like ZR above. So make this a | |
9904 | ; separate pattern for now. | |
9905 | (define_insn "*indirect2_jump" | |
9906 | [(set (pc) | |
9907 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
84b4c7b5 | 9908 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
2841f550 AK |
9909 | "@ |
9910 | br\t%0 | |
9911 | bi\t%0" | |
9912 | [(set_attr "op_type" "RR,RXY") | |
9913 | (set_attr "type" "branch") | |
9914 | (set_attr "atype" "agen") | |
e9e8efc9 | 9915 | (set_attr "cpu_facility" "*,z14")]) |
9db1d521 HP |
9916 | |
9917 | ; | |
f314b9b1 | 9918 | ; casesi instruction pattern(s). |
9db1d521 HP |
9919 | ; |
9920 | ||
84b4c7b5 AK |
9921 | (define_expand "casesi_jump" |
9922 | [(parallel | |
9923 | [(set (pc) (match_operand 0 "address_operand")) | |
9924 | (use (label_ref (match_operand 1 "")))])] | |
9db1d521 | 9925 | "" |
84b4c7b5 AK |
9926 | { |
9927 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9928 | { | |
9929 | operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); | |
9930 | ||
9931 | if (TARGET_CPU_Z10) | |
9932 | { | |
9933 | if (TARGET_64BIT) | |
9934 | emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], | |
9935 | operands[1])); | |
9936 | else | |
9937 | emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], | |
9938 | operands[1])); | |
9939 | } | |
9940 | else | |
9941 | { | |
9942 | if (TARGET_64BIT) | |
9943 | emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], | |
9944 | operands[1])); | |
9945 | else | |
9946 | emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], | |
9947 | operands[1])); | |
9948 | } | |
9949 | DONE; | |
9950 | } | |
9951 | ||
9952 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9953 | { | |
9954 | operands[0] = force_reg (Pmode, operands[0]); | |
9955 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9956 | if (TARGET_CPU_Z10) | |
9957 | { | |
9958 | if (TARGET_64BIT) | |
9959 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], | |
9960 | operands[1], | |
9961 | label_ref)); | |
9962 | else | |
9963 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], | |
9964 | operands[1], | |
9965 | label_ref)); | |
9966 | } | |
9967 | else | |
9968 | { | |
9969 | if (TARGET_64BIT) | |
9970 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], | |
9971 | operands[1], | |
9972 | label_ref, | |
9973 | force_reg (Pmode, label_ref))); | |
9974 | else | |
9975 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], | |
9976 | operands[1], | |
9977 | label_ref, | |
9978 | force_reg (Pmode, label_ref))); | |
9979 | } | |
9980 | DONE; | |
9981 | } | |
9982 | }) | |
9983 | ||
9984 | (define_insn "*casesi_jump" | |
9985 | [(set (pc) (match_operand 0 "address_operand" "ZR")) | |
9986 | (use (label_ref (match_operand 1 "" "")))] | |
9987 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9db1d521 | 9988 | { |
f314b9b1 | 9989 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9990 | return "br\t%0"; |
f314b9b1 | 9991 | else |
d40c829f | 9992 | return "b\t%a0"; |
10bbf137 | 9993 | } |
c7453384 | 9994 | [(set (attr "op_type") |
f314b9b1 UW |
9995 | (if_then_else (match_operand 0 "register_operand" "") |
9996 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9997 | (set (attr "mnemonic") |
9998 | (if_then_else (match_operand 0 "register_operand" "") | |
9999 | (const_string "br") (const_string "b"))) | |
10000 | (set_attr "type" "branch") | |
10001 | (set_attr "atype" "agen")]) | |
10002 | ||
10003 | (define_insn "casesi_jump_via_thunk<mode>_z10" | |
10004 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
10005 | (use (label_ref (match_operand 1 "" "")))] | |
10006 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
10007 | && TARGET_CPU_Z10" | |
10008 | { | |
10009 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10010 | INVALID_REGNUM, | |
10011 | NULL_RTX, | |
10012 | s390_indirect_branch_type_jump); | |
10013 | return ""; | |
10014 | } | |
10015 | [(set_attr "op_type" "RIL") | |
10016 | (set_attr "mnemonic" "jg") | |
10017 | (set_attr "type" "branch") | |
10018 | (set_attr "atype" "agen")]) | |
10019 | ||
10020 | (define_insn "casesi_jump_via_thunk<mode>" | |
10021 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
10022 | (use (label_ref (match_operand 1 "" ""))) | |
10023 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10024 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
10025 | && !TARGET_CPU_Z10" | |
10026 | { | |
10027 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10028 | INVALID_REGNUM, | |
10029 | NULL_RTX, | |
10030 | s390_indirect_branch_type_jump); | |
10031 | return ""; | |
10032 | } | |
10033 | [(set_attr "op_type" "RIL") | |
10034 | (set_attr "mnemonic" "jg") | |
077dab3b HP |
10035 | (set_attr "type" "branch") |
10036 | (set_attr "atype" "agen")]) | |
9db1d521 | 10037 | |
84b4c7b5 AK |
10038 | |
10039 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
10040 | ; from mark_jump_label. Without this the label_ref would become the | |
10041 | ; ONLY jump target of that jump breaking the control flow graph. | |
10042 | (define_insn "casesi_jump_via_inlinethunk<mode>_z10" | |
10043 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
10044 | (const_int 0) | |
10045 | (const_int 0)) | |
10046 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
10047 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
10048 | (use (label_ref (match_operand 1 "" "")))] | |
10049 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
10050 | && TARGET_CPU_Z10" | |
10051 | { | |
10052 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
10053 | return ""; | |
10054 | } | |
10055 | [(set_attr "op_type" "RIL") | |
10056 | (set_attr "type" "cs") | |
10057 | (set_attr "length" "10")]) | |
10058 | ||
10059 | (define_insn "casesi_jump_via_inlinethunk<mode>" | |
10060 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
10061 | (const_int 0) | |
10062 | (const_int 0)) | |
10063 | (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
10064 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
10065 | (use (label_ref (match_operand 1 "" "")))] | |
10066 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
10067 | && !TARGET_CPU_Z10" | |
10068 | { | |
10069 | s390_indirect_branch_via_inline_thunk (operands[3]); | |
10070 | return ""; | |
10071 | } | |
10072 | [(set_attr "op_type" "RX") | |
10073 | (set_attr "type" "cs") | |
10074 | (set_attr "length" "8")]) | |
10075 | ||
f314b9b1 UW |
10076 | (define_expand "casesi" |
10077 | [(match_operand:SI 0 "general_operand" "") | |
10078 | (match_operand:SI 1 "general_operand" "") | |
10079 | (match_operand:SI 2 "general_operand" "") | |
10080 | (label_ref (match_operand 3 "" "")) | |
10081 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 10082 | "" |
f314b9b1 UW |
10083 | { |
10084 | rtx index = gen_reg_rtx (SImode); | |
10085 | rtx base = gen_reg_rtx (Pmode); | |
10086 | rtx target = gen_reg_rtx (Pmode); | |
10087 | ||
10088 | emit_move_insn (index, operands[0]); | |
10089 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
10090 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 10091 | operands[4]); |
f314b9b1 UW |
10092 | |
10093 | if (Pmode != SImode) | |
10094 | index = convert_to_mode (Pmode, index, 1); | |
10095 | if (GET_CODE (index) != REG) | |
10096 | index = copy_to_mode_reg (Pmode, index); | |
10097 | ||
10098 | if (TARGET_64BIT) | |
10099 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
10100 | else | |
a556fd39 | 10101 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 10102 | |
f314b9b1 UW |
10103 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
10104 | ||
542a8afa | 10105 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
10106 | emit_move_insn (target, index); |
10107 | ||
10108 | if (flag_pic) | |
10109 | target = gen_rtx_PLUS (Pmode, base, target); | |
10110 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
10111 | ||
10112 | DONE; | |
10bbf137 | 10113 | }) |
9db1d521 HP |
10114 | |
10115 | ||
10116 | ;; | |
10117 | ;;- Jump to subroutine. | |
10118 | ;; | |
10119 | ;; | |
10120 | ||
10121 | ; | |
10122 | ; untyped call instruction pattern(s). | |
10123 | ; | |
10124 | ||
10125 | ;; Call subroutine returning any type. | |
10126 | (define_expand "untyped_call" | |
10127 | [(parallel [(call (match_operand 0 "" "") | |
10128 | (const_int 0)) | |
10129 | (match_operand 1 "" "") | |
10130 | (match_operand 2 "" "")])] | |
10131 | "" | |
9db1d521 HP |
10132 | { |
10133 | int i; | |
10134 | ||
10135 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
10136 | ||
10137 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10138 | { | |
10139 | rtx set = XVECEXP (operands[2], 0, i); | |
10140 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10141 | } | |
10142 | ||
10143 | /* The optimizer does not know that the call sets the function value | |
10144 | registers we stored in the result block. We avoid problems by | |
10145 | claiming that all hard registers are used and clobbered at this | |
10146 | point. */ | |
10147 | emit_insn (gen_blockage ()); | |
10148 | ||
10149 | DONE; | |
10bbf137 | 10150 | }) |
9db1d521 HP |
10151 | |
10152 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
10153 | ;; all of memory. This blocks insns from being moved across this point. | |
10154 | ||
10155 | (define_insn "blockage" | |
10bbf137 | 10156 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 10157 | "" |
4023fb28 | 10158 | "" |
d5869ca0 UW |
10159 | [(set_attr "type" "none") |
10160 | (set_attr "length" "0")]) | |
4023fb28 | 10161 | |
9db1d521 | 10162 | ; |
ed9676cf | 10163 | ; sibcall patterns |
9db1d521 HP |
10164 | ; |
10165 | ||
ed9676cf | 10166 | (define_expand "sibcall" |
44b8152b | 10167 | [(call (match_operand 0 "" "") |
ed9676cf | 10168 | (match_operand 1 "" ""))] |
9db1d521 | 10169 | "" |
9db1d521 | 10170 | { |
ed9676cf AK |
10171 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
10172 | DONE; | |
10173 | }) | |
9db1d521 | 10174 | |
ed9676cf | 10175 | (define_insn "*sibcall_br" |
ae156f85 | 10176 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 10177 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 10178 | "SIBLING_CALL_P (insn) |
ed9676cf | 10179 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
84b4c7b5 AK |
10180 | { |
10181 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
10182 | { | |
10183 | gcc_assert (TARGET_CPU_Z10); | |
10184 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
10185 | INVALID_REGNUM, | |
10186 | NULL_RTX, | |
10187 | s390_indirect_branch_type_call); | |
10188 | return ""; | |
10189 | } | |
10190 | else | |
10191 | return "br\t%%r1"; | |
10192 | } | |
10193 | [(set (attr "op_type") | |
10194 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10195 | (const_string "RIL") | |
10196 | (const_string "RR"))) | |
10197 | (set (attr "mnemonic") | |
10198 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10199 | (const_string "jg") | |
10200 | (const_string "br"))) | |
ed9676cf AK |
10201 | (set_attr "type" "branch") |
10202 | (set_attr "atype" "agen")]) | |
9db1d521 | 10203 | |
ed9676cf AK |
10204 | (define_insn "*sibcall_brc" |
10205 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10206 | (match_operand 1 "const_int_operand" "n"))] | |
10207 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
10208 | "j\t%0" | |
10209 | [(set_attr "op_type" "RI") | |
10210 | (set_attr "type" "branch")]) | |
9db1d521 | 10211 | |
ed9676cf AK |
10212 | (define_insn "*sibcall_brcl" |
10213 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10214 | (match_operand 1 "const_int_operand" "n"))] | |
8cc6307c | 10215 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
10216 | "jg\t%0" |
10217 | [(set_attr "op_type" "RIL") | |
10218 | (set_attr "type" "branch")]) | |
44b8152b | 10219 | |
ed9676cf AK |
10220 | ; |
10221 | ; sibcall_value patterns | |
10222 | ; | |
9e8327e3 | 10223 | |
ed9676cf AK |
10224 | (define_expand "sibcall_value" |
10225 | [(set (match_operand 0 "" "") | |
10226 | (call (match_operand 1 "" "") | |
10227 | (match_operand 2 "" "")))] | |
10228 | "" | |
10229 | { | |
10230 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 10231 | DONE; |
10bbf137 | 10232 | }) |
9db1d521 | 10233 | |
ed9676cf AK |
10234 | (define_insn "*sibcall_value_br" |
10235 | [(set (match_operand 0 "" "") | |
ae156f85 | 10236 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 10237 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 10238 | "SIBLING_CALL_P (insn) |
ed9676cf | 10239 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
84b4c7b5 AK |
10240 | { |
10241 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
10242 | { | |
10243 | gcc_assert (TARGET_CPU_Z10); | |
10244 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
10245 | INVALID_REGNUM, | |
10246 | NULL_RTX, | |
10247 | s390_indirect_branch_type_call); | |
10248 | return ""; | |
10249 | } | |
10250 | else | |
10251 | return "br\t%%r1"; | |
10252 | } | |
10253 | [(set (attr "op_type") | |
10254 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10255 | (const_string "RIL") | |
10256 | (const_string "RR"))) | |
10257 | (set (attr "mnemonic") | |
10258 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10259 | (const_string "jg") | |
10260 | (const_string "br"))) | |
ed9676cf AK |
10261 | (set_attr "type" "branch") |
10262 | (set_attr "atype" "agen")]) | |
10263 | ||
10264 | (define_insn "*sibcall_value_brc" | |
10265 | [(set (match_operand 0 "" "") | |
10266 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
10267 | (match_operand 2 "const_int_operand" "n")))] | |
10268 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
10269 | "j\t%1" | |
10270 | [(set_attr "op_type" "RI") | |
10271 | (set_attr "type" "branch")]) | |
10272 | ||
10273 | (define_insn "*sibcall_value_brcl" | |
10274 | [(set (match_operand 0 "" "") | |
10275 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
10276 | (match_operand 2 "const_int_operand" "n")))] | |
8cc6307c | 10277 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
10278 | "jg\t%1" |
10279 | [(set_attr "op_type" "RIL") | |
10280 | (set_attr "type" "branch")]) | |
10281 | ||
10282 | ||
10283 | ; | |
10284 | ; call instruction pattern(s). | |
10285 | ; | |
10286 | ||
10287 | (define_expand "call" | |
10288 | [(call (match_operand 0 "" "") | |
10289 | (match_operand 1 "" "")) | |
10290 | (use (match_operand 2 "" ""))] | |
44b8152b | 10291 | "" |
ed9676cf | 10292 | { |
2f7e5a0d | 10293 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
10294 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
10295 | DONE; | |
10296 | }) | |
44b8152b | 10297 | |
9e8327e3 UW |
10298 | (define_insn "*bras" |
10299 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10300 | (match_operand 1 "const_int_operand" "n")) | |
10301 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
10302 | "!SIBLING_CALL_P (insn) |
10303 | && TARGET_SMALL_EXEC | |
ed9676cf | 10304 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 10305 | "bras\t%2,%0" |
9db1d521 | 10306 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10307 | (set_attr "type" "jsr") |
10308 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10309 | |
9e8327e3 UW |
10310 | (define_insn "*brasl" |
10311 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10312 | (match_operand 1 "const_int_operand" "n")) | |
10313 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d | 10314 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10315 | |
ed9676cf | 10316 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
10317 | "brasl\t%2,%0" |
10318 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10319 | (set_attr "type" "jsr") |
14cfceb7 IL |
10320 | (set_attr "z196prop" "z196_cracked") |
10321 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10322 | |
9e8327e3 | 10323 | (define_insn "*basr" |
3e4be43f | 10324 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
10325 | (match_operand 1 "const_int_operand" "n")) |
10326 | (clobber (match_operand 2 "register_operand" "=r"))] | |
84b4c7b5 AK |
10327 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10328 | && !SIBLING_CALL_P (insn) | |
10329 | && GET_MODE (operands[2]) == Pmode" | |
9e8327e3 UW |
10330 | { |
10331 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10332 | return "basr\t%2,%0"; | |
10333 | else | |
10334 | return "bas\t%2,%a0"; | |
10335 | } | |
10336 | [(set (attr "op_type") | |
10337 | (if_then_else (match_operand 0 "register_operand" "") | |
10338 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10339 | (set (attr "mnemonic") |
10340 | (if_then_else (match_operand 0 "register_operand" "") | |
10341 | (const_string "basr") (const_string "bas"))) | |
10342 | (set_attr "type" "jsr") | |
10343 | (set_attr "atype" "agen") | |
10344 | (set_attr "z196prop" "z196_cracked")]) | |
10345 | ||
10346 | (define_insn "*basr_via_thunk<mode>_z10" | |
10347 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10348 | (match_operand 1 "const_int_operand" "n")) | |
10349 | (clobber (match_operand:P 2 "register_operand" "=&r"))] | |
10350 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10351 | && TARGET_CPU_Z10 | |
10352 | && !SIBLING_CALL_P (insn)" | |
10353 | { | |
10354 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10355 | REGNO (operands[2]), | |
10356 | NULL_RTX, | |
10357 | s390_indirect_branch_type_call); | |
10358 | return ""; | |
10359 | } | |
10360 | [(set_attr "op_type" "RIL") | |
10361 | (set_attr "mnemonic" "brasl") | |
10362 | (set_attr "type" "jsr") | |
10363 | (set_attr "atype" "agen") | |
10364 | (set_attr "z196prop" "z196_cracked")]) | |
10365 | ||
10366 | (define_insn "*basr_via_thunk<mode>" | |
10367 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10368 | (match_operand 1 "const_int_operand" "n")) | |
10369 | (clobber (match_operand:P 2 "register_operand" "=&r")) | |
10370 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10371 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10372 | && !TARGET_CPU_Z10 | |
10373 | && !SIBLING_CALL_P (insn)" | |
10374 | { | |
10375 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10376 | REGNO (operands[2]), | |
10377 | NULL_RTX, | |
10378 | s390_indirect_branch_type_call); | |
10379 | return ""; | |
10380 | } | |
10381 | [(set_attr "op_type" "RIL") | |
10382 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10383 | (set_attr "type" "jsr") |
65b1d8ea AK |
10384 | (set_attr "atype" "agen") |
10385 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
10386 | |
10387 | ; | |
10388 | ; call_value instruction pattern(s). | |
10389 | ; | |
10390 | ||
10391 | (define_expand "call_value" | |
44b8152b UW |
10392 | [(set (match_operand 0 "" "") |
10393 | (call (match_operand 1 "" "") | |
10394 | (match_operand 2 "" ""))) | |
10395 | (use (match_operand 3 "" ""))] | |
9db1d521 | 10396 | "" |
9db1d521 | 10397 | { |
2f7e5a0d | 10398 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 10399 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 10400 | DONE; |
10bbf137 | 10401 | }) |
9db1d521 | 10402 | |
9e8327e3 | 10403 | (define_insn "*bras_r" |
c19ec8f9 | 10404 | [(set (match_operand 0 "" "") |
9e8327e3 | 10405 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 10406 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 10407 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
10408 | "!SIBLING_CALL_P (insn) |
10409 | && TARGET_SMALL_EXEC | |
ed9676cf | 10410 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10411 | "bras\t%3,%1" |
9db1d521 | 10412 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10413 | (set_attr "type" "jsr") |
10414 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10415 | |
9e8327e3 | 10416 | (define_insn "*brasl_r" |
c19ec8f9 | 10417 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10418 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10419 | (match_operand 2 "const_int_operand" "n"))) | |
10420 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d | 10421 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10422 | |
ed9676cf | 10423 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10424 | "brasl\t%3,%1" |
10425 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10426 | (set_attr "type" "jsr") |
14cfceb7 IL |
10427 | (set_attr "z196prop" "z196_cracked") |
10428 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10429 | |
9e8327e3 | 10430 | (define_insn "*basr_r" |
c19ec8f9 | 10431 | [(set (match_operand 0 "" "") |
3e4be43f | 10432 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10433 | (match_operand 2 "const_int_operand" "n"))) |
10434 | (clobber (match_operand 3 "register_operand" "=r"))] | |
84b4c7b5 AK |
10435 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10436 | && !SIBLING_CALL_P (insn) | |
10437 | && GET_MODE (operands[3]) == Pmode" | |
9e8327e3 UW |
10438 | { |
10439 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10440 | return "basr\t%3,%1"; | |
10441 | else | |
10442 | return "bas\t%3,%a1"; | |
10443 | } | |
10444 | [(set (attr "op_type") | |
10445 | (if_then_else (match_operand 1 "register_operand" "") | |
10446 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10447 | (set (attr "mnemonic") |
10448 | (if_then_else (match_operand 1 "register_operand" "") | |
10449 | (const_string "basr") (const_string "bas"))) | |
10450 | (set_attr "type" "jsr") | |
10451 | (set_attr "atype" "agen") | |
10452 | (set_attr "z196prop" "z196_cracked")]) | |
10453 | ||
10454 | (define_insn "*basr_r_via_thunk_z10" | |
10455 | [(set (match_operand 0 "" "") | |
10456 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10457 | (match_operand 2 "const_int_operand" "n"))) | |
10458 | (clobber (match_operand 3 "register_operand" "=&r"))] | |
10459 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10460 | && TARGET_CPU_Z10 | |
10461 | && !SIBLING_CALL_P (insn) | |
10462 | && GET_MODE (operands[3]) == Pmode" | |
10463 | { | |
10464 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10465 | REGNO (operands[3]), | |
10466 | NULL_RTX, | |
10467 | s390_indirect_branch_type_call); | |
10468 | return ""; | |
10469 | } | |
10470 | [(set_attr "op_type" "RIL") | |
10471 | (set_attr "mnemonic" "brasl") | |
10472 | (set_attr "type" "jsr") | |
10473 | (set_attr "atype" "agen") | |
10474 | (set_attr "z196prop" "z196_cracked")]) | |
10475 | ||
10476 | (define_insn "*basr_r_via_thunk" | |
10477 | [(set (match_operand 0 "" "") | |
10478 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10479 | (match_operand 2 "const_int_operand" "n"))) | |
10480 | (clobber (match_operand 3 "register_operand" "=&r")) | |
10481 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10482 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10483 | && !TARGET_CPU_Z10 | |
10484 | && !SIBLING_CALL_P (insn) | |
10485 | && GET_MODE (operands[3]) == Pmode" | |
10486 | { | |
10487 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10488 | REGNO (operands[3]), | |
10489 | NULL_RTX, | |
10490 | s390_indirect_branch_type_call); | |
10491 | return ""; | |
10492 | } | |
10493 | [(set_attr "op_type" "RIL") | |
10494 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10495 | (set_attr "type" "jsr") |
65b1d8ea AK |
10496 | (set_attr "atype" "agen") |
10497 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10498 | |
fd3cd001 UW |
10499 | ;; |
10500 | ;;- Thread-local storage support. | |
10501 | ;; | |
10502 | ||
f959607b CLT |
10503 | (define_expand "get_thread_pointer<mode>" |
10504 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
10505 | "" | |
c5aa1d12 | 10506 | "") |
fd3cd001 | 10507 | |
f959607b CLT |
10508 | (define_expand "set_thread_pointer<mode>" |
10509 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
10510 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
10511 | "" | |
c5aa1d12 UW |
10512 | "") |
10513 | ||
10514 | (define_insn "*set_tp" | |
ae156f85 | 10515 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
10516 | "" |
10517 | "" | |
10518 | [(set_attr "type" "none") | |
10519 | (set_attr "length" "0")]) | |
c7453384 | 10520 | |
fd3cd001 UW |
10521 | (define_insn "*tls_load_64" |
10522 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 10523 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
10524 | (match_operand:DI 2 "" "")] |
10525 | UNSPEC_TLS_LOAD))] | |
10526 | "TARGET_64BIT" | |
d40c829f | 10527 | "lg\t%0,%1%J2" |
9381e3f1 WG |
10528 | [(set_attr "op_type" "RXE") |
10529 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
10530 | |
10531 | (define_insn "*tls_load_31" | |
d3632d41 UW |
10532 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10533 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
10534 | (match_operand:SI 2 "" "")] |
10535 | UNSPEC_TLS_LOAD))] | |
10536 | "!TARGET_64BIT" | |
d3632d41 | 10537 | "@ |
d40c829f UW |
10538 | l\t%0,%1%J2 |
10539 | ly\t%0,%1%J2" | |
9381e3f1 | 10540 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 10541 | (set_attr "type" "load") |
3e4be43f | 10542 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 10543 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 10544 | |
9e8327e3 | 10545 | (define_insn "*bras_tls" |
c19ec8f9 | 10546 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10547 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10548 | (match_operand 2 "const_int_operand" "n"))) | |
10549 | (clobber (match_operand 3 "register_operand" "=r")) | |
10550 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10551 | "!SIBLING_CALL_P (insn) |
10552 | && TARGET_SMALL_EXEC | |
ed9676cf | 10553 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10554 | "bras\t%3,%1%J4" |
fd3cd001 | 10555 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10556 | (set_attr "type" "jsr") |
10557 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10558 | |
9e8327e3 | 10559 | (define_insn "*brasl_tls" |
c19ec8f9 | 10560 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10561 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10562 | (match_operand 2 "const_int_operand" "n"))) | |
10563 | (clobber (match_operand 3 "register_operand" "=r")) | |
10564 | (use (match_operand 4 "" ""))] | |
2f7e5a0d | 10565 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10566 | |
ed9676cf | 10567 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10568 | "brasl\t%3,%1%J4" |
10569 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10570 | (set_attr "type" "jsr") |
14cfceb7 IL |
10571 | (set_attr "z196prop" "z196_cracked") |
10572 | (set_attr "relative_long" "yes")]) | |
fd3cd001 | 10573 | |
9e8327e3 | 10574 | (define_insn "*basr_tls" |
c19ec8f9 | 10575 | [(set (match_operand 0 "" "") |
3e4be43f | 10576 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10577 | (match_operand 2 "const_int_operand" "n"))) |
10578 | (clobber (match_operand 3 "register_operand" "=r")) | |
10579 | (use (match_operand 4 "" ""))] | |
ed9676cf | 10580 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10581 | { |
10582 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10583 | return "basr\t%3,%1%J4"; | |
10584 | else | |
10585 | return "bas\t%3,%a1%J4"; | |
10586 | } | |
10587 | [(set (attr "op_type") | |
10588 | (if_then_else (match_operand 1 "register_operand" "") | |
10589 | (const_string "RR") (const_string "RX"))) | |
10590 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10591 | (set_attr "atype" "agen") |
10592 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10593 | |
e0374221 AS |
10594 | ;; |
10595 | ;;- Atomic operations | |
10596 | ;; | |
10597 | ||
10598 | ; | |
78ce265b | 10599 | ; memory barrier patterns. |
e0374221 AS |
10600 | ; |
10601 | ||
78ce265b RH |
10602 | (define_expand "mem_thread_fence" |
10603 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
10604 | "" | |
10605 | { | |
10606 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
10607 | enough not to require barriers of any kind. */ | |
46b35980 | 10608 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
10609 | { |
10610 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
10611 | MEM_VOLATILE_P (mem) = 1; | |
10612 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
10613 | } | |
10614 | DONE; | |
e0374221 AS |
10615 | }) |
10616 | ||
78ce265b RH |
10617 | ; Although bcr is superscalar on Z10, this variant will never |
10618 | ; become part of an execution group. | |
a9cc3f58 AK |
10619 | ; With z196 we can make use of the fast-BCR-serialization facility. |
10620 | ; This allows for a slightly faster sync which is sufficient for our | |
10621 | ; purposes. | |
78ce265b | 10622 | (define_insn "mem_thread_fence_1" |
e0374221 | 10623 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 10624 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 10625 | "" |
a9cc3f58 AK |
10626 | { |
10627 | if (TARGET_Z196) | |
10628 | return "bcr\t14,0"; | |
10629 | else | |
10630 | return "bcr\t15,0"; | |
10631 | } | |
10632 | [(set_attr "op_type" "RR") | |
10633 | (set_attr "mnemonic" "bcr_flush") | |
10634 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10635 | |
78ce265b RH |
10636 | ; |
10637 | ; atomic load/store operations | |
10638 | ; | |
10639 | ||
10640 | ; Atomic loads need not examine the memory model at all. | |
10641 | (define_expand "atomic_load<mode>" | |
10642 | [(match_operand:DINT 0 "register_operand") ;; output | |
10643 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10644 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10645 | "" | |
10646 | { | |
75cc21e2 AK |
10647 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10648 | FAIL; | |
10649 | ||
78ce265b RH |
10650 | if (<MODE>mode == TImode) |
10651 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10652 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10653 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10654 | else | |
10655 | emit_move_insn (operands[0], operands[1]); | |
10656 | DONE; | |
10657 | }) | |
10658 | ||
10659 | ; Different from movdi_31 in that we want no splitters. | |
10660 | (define_insn "atomic_loaddi_1" | |
10661 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10662 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10663 | UNSPEC_MOVA))] | |
10664 | "!TARGET_ZARCH" | |
10665 | "@ | |
10666 | lm\t%0,%M0,%S1 | |
10667 | lmy\t%0,%M0,%S1 | |
10668 | ld\t%0,%1 | |
10669 | ldy\t%0,%1" | |
10670 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10671 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10672 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10673 | ||
10674 | (define_insn "atomic_loadti_1" | |
10675 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10676 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10677 | UNSPEC_MOVA))] |
10678 | "TARGET_ZARCH" | |
10679 | "lpq\t%0,%1" | |
10680 | [(set_attr "op_type" "RXY") | |
10681 | (set_attr "type" "other")]) | |
10682 | ||
10683 | ; Atomic stores must(?) enforce sequential consistency. | |
10684 | (define_expand "atomic_store<mode>" | |
10685 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10686 | (match_operand:DINT 1 "register_operand") ;; input | |
10687 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10688 | "" | |
10689 | { | |
46b35980 | 10690 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10691 | |
75cc21e2 AK |
10692 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10693 | FAIL; | |
10694 | ||
78ce265b RH |
10695 | if (<MODE>mode == TImode) |
10696 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10697 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10698 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10699 | else | |
10700 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10701 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10702 | emit_insn (gen_mem_thread_fence (operands[2])); |
10703 | DONE; | |
10704 | }) | |
10705 | ||
10706 | ; Different from movdi_31 in that we want no splitters. | |
10707 | (define_insn "atomic_storedi_1" | |
10708 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10709 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10710 | UNSPEC_MOVA))] | |
10711 | "!TARGET_ZARCH" | |
10712 | "@ | |
10713 | stm\t%1,%N1,%S0 | |
10714 | stmy\t%1,%N1,%S0 | |
10715 | std %1,%0 | |
10716 | stdy %1,%0" | |
10717 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10718 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10719 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10720 | ||
10721 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10722 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10723 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10724 | UNSPEC_MOVA))] | |
10725 | "TARGET_ZARCH" | |
10726 | "stpq\t%1,%0" | |
10727 | [(set_attr "op_type" "RXY") | |
10728 | (set_attr "type" "other")]) | |
e0374221 AS |
10729 | |
10730 | ; | |
10731 | ; compare and swap patterns. | |
10732 | ; | |
10733 | ||
78ce265b RH |
10734 | (define_expand "atomic_compare_and_swap<mode>" |
10735 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
03db9ab5 DV |
10736 | (match_operand:DINT 1 "nonimmediate_operand");; oldval output |
10737 | (match_operand:DINT 2 "s_operand") ;; memory | |
10738 | (match_operand:DINT 3 "general_operand") ;; expected intput | |
10739 | (match_operand:DINT 4 "general_operand") ;; newval intput | |
78ce265b RH |
10740 | (match_operand:SI 5 "const_int_operand") ;; is_weak |
10741 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10742 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10743 | "" | |
10744 | { | |
03db9ab5 DV |
10745 | if (GET_MODE_BITSIZE (<MODE>mode) >= 16 |
10746 | && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) | |
75cc21e2 AK |
10747 | FAIL; |
10748 | ||
03db9ab5 DV |
10749 | s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], |
10750 | operands[3], operands[4], INTVAL (operands[5])); | |
10751 | DONE;}) | |
3093f076 | 10752 | |
78ce265b RH |
10753 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10754 | [(parallel | |
10755 | [(set (match_operand:DGPR 0 "register_operand") | |
03db9ab5 | 10756 | (match_operand:DGPR 1 "s_operand")) |
78ce265b RH |
10757 | (set (match_dup 1) |
10758 | (unspec_volatile:DGPR | |
10759 | [(match_dup 1) | |
10760 | (match_operand:DGPR 2 "register_operand") | |
10761 | (match_operand:DGPR 3 "register_operand")] | |
10762 | UNSPECV_CAS)) | |
03db9ab5 DV |
10763 | (set (match_operand 4 "cc_reg_operand") |
10764 | (match_dup 5))])] | |
10765 | "GET_MODE (operands[4]) == CCZmode | |
10766 | || GET_MODE (operands[4]) == CCZ1mode" | |
10767 | { | |
10768 | operands[5] | |
10769 | = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); | |
10770 | }) | |
78ce265b RH |
10771 | |
10772 | ; cdsg, csg | |
10773 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10774 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
bdb57bcb | 10775 | (match_operand:TDI 1 "nonsym_memory_operand" "+S")) |
8006eaa6 | 10776 | (set (match_dup 1) |
78ce265b | 10777 | (unspec_volatile:TDI |
8006eaa6 | 10778 | [(match_dup 1) |
78ce265b RH |
10779 | (match_operand:TDI 2 "register_operand" "0") |
10780 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 | 10781 | UNSPECV_CAS)) |
03db9ab5 DV |
10782 | (set (reg CC_REGNUM) |
10783 | (compare (match_dup 1) (match_dup 2)))] | |
10784 | "TARGET_ZARCH | |
10785 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10786 | "c<td>sg\t%0,%3,%S1" |
10787 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10788 | (set_attr "type" "sem")]) |
10789 | ||
78ce265b RH |
10790 | ; cds, cdsy |
10791 | (define_insn "*atomic_compare_and_swapdi_2" | |
10792 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
bdb57bcb | 10793 | (match_operand:DI 1 "nonsym_memory_operand" "+Q,S")) |
e0374221 | 10794 | (set (match_dup 1) |
78ce265b RH |
10795 | (unspec_volatile:DI |
10796 | [(match_dup 1) | |
10797 | (match_operand:DI 2 "register_operand" "0,0") | |
10798 | (match_operand:DI 3 "register_operand" "r,r")] | |
10799 | UNSPECV_CAS)) | |
03db9ab5 DV |
10800 | (set (reg CC_REGNUM) |
10801 | (compare (match_dup 1) (match_dup 2)))] | |
10802 | "!TARGET_ZARCH | |
10803 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10804 | "@ |
10805 | cds\t%0,%3,%S1 | |
10806 | cdsy\t%0,%3,%S1" | |
10807 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10808 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10809 | (set_attr "type" "sem")]) |
10810 | ||
10811 | ; cs, csy | |
10812 | (define_insn "*atomic_compare_and_swapsi_3" | |
10813 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
bdb57bcb | 10814 | (match_operand:SI 1 "nonsym_memory_operand" "+Q,S")) |
78ce265b RH |
10815 | (set (match_dup 1) |
10816 | (unspec_volatile:SI | |
e0374221 | 10817 | [(match_dup 1) |
78ce265b RH |
10818 | (match_operand:SI 2 "register_operand" "0,0") |
10819 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10820 | UNSPECV_CAS)) |
03db9ab5 DV |
10821 | (set (reg CC_REGNUM) |
10822 | (compare (match_dup 1) (match_dup 2)))] | |
10823 | "s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10824 | "@ |
10825 | cs\t%0,%3,%S1 | |
10826 | csy\t%0,%3,%S1" | |
10827 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10828 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10829 | (set_attr "type" "sem")]) |
10830 | ||
45d18331 AS |
10831 | ; |
10832 | ; Other atomic instruction patterns. | |
10833 | ; | |
10834 | ||
65b1d8ea AK |
10835 | ; z196 load and add, xor, or and and instructions |
10836 | ||
78ce265b RH |
10837 | (define_expand "atomic_fetch_<atomic><mode>" |
10838 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10839 | (ATOMIC_Z196:GPR | |
10840 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10841 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10842 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10843 | "TARGET_Z196" |
78ce265b | 10844 | { |
75cc21e2 AK |
10845 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10846 | FAIL; | |
10847 | ||
78ce265b RH |
10848 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10849 | (operands[0], operands[1], operands[2])); | |
10850 | DONE; | |
10851 | }) | |
65b1d8ea AK |
10852 | |
10853 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10854 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10855 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10856 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10857 | (set (match_dup 1) |
10858 | (unspec_volatile:GPR | |
10859 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10860 | (match_operand:GPR 2 "general_operand" "d"))] | |
10861 | UNSPECV_ATOMIC_OP)) | |
10862 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10863 | "TARGET_Z196" |
78ce265b RH |
10864 | "la<noxa><g>\t%0,%2,%1" |
10865 | [(set_attr "op_type" "RSY") | |
10866 | (set_attr "type" "sem")]) | |
65b1d8ea | 10867 | |
78ce265b RH |
10868 | ;; For SImode and larger, the optabs.c code will do just fine in |
10869 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10870 | ;; better by expanding our own loop. | |
65b1d8ea | 10871 | |
78ce265b RH |
10872 | (define_expand "atomic_<atomic><mode>" |
10873 | [(ATOMIC:HQI | |
10874 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10875 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10876 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10877 | "" |
78ce265b RH |
10878 | { |
10879 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10880 | operands[1], false); | |
10881 | DONE; | |
10882 | }) | |
45d18331 | 10883 | |
78ce265b RH |
10884 | (define_expand "atomic_fetch_<atomic><mode>" |
10885 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10886 | (ATOMIC:HQI | |
10887 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10888 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10889 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10890 | "" |
78ce265b RH |
10891 | { |
10892 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10893 | operands[2], false); | |
10894 | DONE; | |
10895 | }) | |
10896 | ||
10897 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10898 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10899 | (ATOMIC:HQI | |
10900 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10901 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10902 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10903 | "" | |
10904 | { | |
10905 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10906 | operands[2], true); | |
10907 | DONE; | |
10908 | }) | |
10909 | ||
03db9ab5 DV |
10910 | ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code |
10911 | ;; generated by the middleend is not good. | |
78ce265b | 10912 | (define_expand "atomic_exchange<mode>" |
03db9ab5 DV |
10913 | [(match_operand:DINT 0 "register_operand") ;; val out |
10914 | (match_operand:DINT 1 "s_operand") ;; memory | |
10915 | (match_operand:DINT 2 "general_operand") ;; val in | |
78ce265b | 10916 | (match_operand:SI 3 "const_int_operand")] ;; model |
45d18331 | 10917 | "" |
78ce265b | 10918 | { |
03db9ab5 DV |
10919 | if (<MODE>mode != QImode |
10920 | && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) | |
10921 | FAIL; | |
10922 | if (<MODE>mode == HImode || <MODE>mode == QImode) | |
10923 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], | |
10924 | false); | |
10925 | else if (<MODE>mode == SImode || TARGET_ZARCH) | |
10926 | s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); | |
10927 | else | |
10928 | FAIL; | |
78ce265b RH |
10929 | DONE; |
10930 | }) | |
45d18331 | 10931 | |
9db1d521 HP |
10932 | ;; |
10933 | ;;- Miscellaneous instructions. | |
10934 | ;; | |
10935 | ||
10936 | ; | |
10937 | ; allocate stack instruction pattern(s). | |
10938 | ; | |
10939 | ||
10940 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10941 | [(match_operand 0 "general_operand" "") |
10942 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10943 | "TARGET_BACKCHAIN" |
9db1d521 | 10944 | { |
ef44a6ff | 10945 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10946 | |
ef44a6ff UW |
10947 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10948 | anti_adjust_stack (operands[1]); | |
10949 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10950 | |
ef44a6ff UW |
10951 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10952 | DONE; | |
10bbf137 | 10953 | }) |
9db1d521 HP |
10954 | |
10955 | ||
10956 | ; | |
43ab026f | 10957 | ; setjmp instruction pattern. |
9db1d521 HP |
10958 | ; |
10959 | ||
9db1d521 | 10960 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10961 | [(match_operand 0 "" "")] |
f314b9b1 | 10962 | "flag_pic" |
9db1d521 | 10963 | { |
585539a1 | 10964 | emit_insn (s390_load_got ()); |
c41c1387 | 10965 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10966 | DONE; |
fd7643fb | 10967 | }) |
9db1d521 | 10968 | |
9db1d521 HP |
10969 | ;; These patterns say how to save and restore the stack pointer. We need not |
10970 | ;; save the stack pointer at function level since we are careful to | |
10971 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10972 | ;; when we restore the stack pointer. | |
10973 | ;; | |
10974 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10975 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10976 | ;; save area is a memory location. | |
10977 | ||
10978 | (define_expand "save_stack_function" | |
10979 | [(match_operand 0 "general_operand" "") | |
10980 | (match_operand 1 "general_operand" "")] | |
10981 | "" | |
10982 | "DONE;") | |
10983 | ||
10984 | (define_expand "restore_stack_function" | |
10985 | [(match_operand 0 "general_operand" "") | |
10986 | (match_operand 1 "general_operand" "")] | |
10987 | "" | |
10988 | "DONE;") | |
10989 | ||
10990 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10991 | [(match_operand 0 "register_operand" "") |
10992 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10993 | "TARGET_BACKCHAIN" |
9db1d521 | 10994 | { |
ef44a6ff UW |
10995 | rtx temp = gen_reg_rtx (Pmode); |
10996 | ||
10997 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10998 | emit_move_insn (operands[0], operands[1]); | |
10999 | emit_move_insn (s390_back_chain_rtx (), temp); | |
11000 | ||
11001 | DONE; | |
10bbf137 | 11002 | }) |
9db1d521 HP |
11003 | |
11004 | (define_expand "save_stack_nonlocal" | |
11005 | [(match_operand 0 "memory_operand" "") | |
11006 | (match_operand 1 "register_operand" "")] | |
11007 | "" | |
9db1d521 | 11008 | { |
ef44a6ff UW |
11009 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
11010 | ||
11011 | /* Copy the backchain to the first word, sp to the second and the | |
11012 | literal pool base to the third. */ | |
11013 | ||
9602b6a1 AK |
11014 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
11015 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
11016 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
11017 | ||
b3d31392 | 11018 | if (TARGET_BACKCHAIN) |
9602b6a1 | 11019 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 11020 | |
9602b6a1 AK |
11021 | emit_move_insn (save_sp, operands[1]); |
11022 | emit_move_insn (save_bp, base); | |
9db1d521 | 11023 | |
9db1d521 | 11024 | DONE; |
10bbf137 | 11025 | }) |
9db1d521 HP |
11026 | |
11027 | (define_expand "restore_stack_nonlocal" | |
11028 | [(match_operand 0 "register_operand" "") | |
11029 | (match_operand 1 "memory_operand" "")] | |
11030 | "" | |
9db1d521 | 11031 | { |
490ceeb4 | 11032 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 11033 | rtx temp = NULL_RTX; |
9db1d521 | 11034 | |
43ab026f | 11035 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 11036 | literal pool base from the third. */ |
43ab026f | 11037 | |
9602b6a1 AK |
11038 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
11039 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
11040 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
11041 | ||
b3d31392 | 11042 | if (TARGET_BACKCHAIN) |
9602b6a1 | 11043 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 11044 | |
9602b6a1 AK |
11045 | emit_move_insn (base, save_bp); |
11046 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
11047 | |
11048 | if (temp) | |
11049 | emit_move_insn (s390_back_chain_rtx (), temp); | |
11050 | ||
c41c1387 | 11051 | emit_use (base); |
9db1d521 | 11052 | DONE; |
10bbf137 | 11053 | }) |
9db1d521 | 11054 | |
7bcebb25 AK |
11055 | (define_expand "exception_receiver" |
11056 | [(const_int 0)] | |
11057 | "" | |
11058 | { | |
11059 | s390_set_has_landing_pad_p (true); | |
11060 | DONE; | |
11061 | }) | |
9db1d521 HP |
11062 | |
11063 | ; | |
11064 | ; nop instruction pattern(s). | |
11065 | ; | |
11066 | ||
11067 | (define_insn "nop" | |
11068 | [(const_int 0)] | |
11069 | "" | |
aad98a61 AK |
11070 | "nopr\t%%r0" |
11071 | [(set_attr "op_type" "RR")]) | |
11072 | ||
11073 | ; non-branch NOPs required for optimizing compare-and-branch patterns | |
11074 | ; on z10 | |
11075 | ||
11076 | (define_insn "nop_lr0" | |
11077 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] | |
11078 | "" | |
d40c829f | 11079 | "lr\t0,0" |
729e750f WG |
11080 | [(set_attr "op_type" "RR") |
11081 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 11082 | |
aad98a61 AK |
11083 | (define_insn "nop_lr1" |
11084 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] | |
d277db6b WG |
11085 | "" |
11086 | "lr\t1,1" | |
11087 | [(set_attr "op_type" "RR")]) | |
11088 | ||
f8af0e30 DV |
11089 | ;;- Undeletable nops (used for hotpatching) |
11090 | ||
11091 | (define_insn "nop_2_byte" | |
11092 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
11093 | "" | |
4bbc8970 | 11094 | "nopr\t%%r0" |
f8af0e30 DV |
11095 | [(set_attr "op_type" "RR")]) |
11096 | ||
11097 | (define_insn "nop_4_byte" | |
11098 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
11099 | "" | |
11100 | "nop\t0" | |
11101 | [(set_attr "op_type" "RX")]) | |
11102 | ||
11103 | (define_insn "nop_6_byte" | |
11104 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
8cc6307c | 11105 | "" |
f8af0e30 | 11106 | "brcl\t0, 0" |
14cfceb7 IL |
11107 | [(set_attr "op_type" "RIL") |
11108 | (set_attr "relative_long" "yes")]) | |
f8af0e30 | 11109 | |
9db1d521 HP |
11110 | |
11111 | ; | |
11112 | ; Special literal pool access instruction pattern(s). | |
11113 | ; | |
11114 | ||
416cf582 UW |
11115 | (define_insn "*pool_entry" |
11116 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
11117 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 11118 | "" |
9db1d521 | 11119 | { |
ef4bddc2 | 11120 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 11121 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 11122 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
11123 | return ""; |
11124 | } | |
b628bd8e | 11125 | [(set (attr "length") |
416cf582 | 11126 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 11127 | |
9bb86f41 UW |
11128 | (define_insn "pool_align" |
11129 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
11130 | UNSPECV_POOL_ALIGN)] | |
11131 | "" | |
11132 | ".align\t%0" | |
b628bd8e | 11133 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 11134 | |
9bb86f41 UW |
11135 | (define_insn "pool_section_start" |
11136 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
11137 | "" | |
b929b470 MK |
11138 | { |
11139 | switch_to_section (targetm.asm_out.function_rodata_section | |
11140 | (current_function_decl)); | |
11141 | return ""; | |
11142 | } | |
b628bd8e | 11143 | [(set_attr "length" "0")]) |
b2ccb744 | 11144 | |
9bb86f41 UW |
11145 | (define_insn "pool_section_end" |
11146 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
11147 | "" | |
b929b470 MK |
11148 | { |
11149 | switch_to_section (current_function_section ()); | |
11150 | return ""; | |
11151 | } | |
b628bd8e | 11152 | [(set_attr "length" "0")]) |
b2ccb744 | 11153 | |
5af2f3d3 | 11154 | (define_insn "main_base_64" |
9e8327e3 UW |
11155 | [(set (match_operand 0 "register_operand" "=a") |
11156 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8cc6307c | 11157 | "GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
11158 | "larl\t%0,%1" |
11159 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 11160 | (set_attr "type" "larl") |
14cfceb7 IL |
11161 | (set_attr "z10prop" "z10_fwd_A1") |
11162 | (set_attr "relative_long" "yes")]) | |
5af2f3d3 UW |
11163 | |
11164 | (define_insn "main_pool" | |
585539a1 UW |
11165 | [(set (match_operand 0 "register_operand" "=a") |
11166 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
11167 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
11168 | { |
11169 | gcc_unreachable (); | |
11170 | } | |
9381e3f1 | 11171 | [(set (attr "type") |
8cc6307c | 11172 | (const_string "larl"))]) |
b2ccb744 | 11173 | |
aee4e0db | 11174 | (define_insn "reload_base_64" |
9e8327e3 UW |
11175 | [(set (match_operand 0 "register_operand" "=a") |
11176 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8cc6307c | 11177 | "GET_MODE (operands[0]) == Pmode" |
d40c829f | 11178 | "larl\t%0,%1" |
aee4e0db | 11179 | [(set_attr "op_type" "RIL") |
9381e3f1 | 11180 | (set_attr "type" "larl") |
729e750f | 11181 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 11182 | |
aee4e0db | 11183 | (define_insn "pool" |
fd7643fb | 11184 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 11185 | "" |
8d933e31 AS |
11186 | { |
11187 | gcc_unreachable (); | |
11188 | } | |
b628bd8e | 11189 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 11190 | |
4023fb28 UW |
11191 | ;; |
11192 | ;; Insns related to generating the function prologue and epilogue. | |
11193 | ;; | |
11194 | ||
11195 | ||
11196 | (define_expand "prologue" | |
11197 | [(use (const_int 0))] | |
11198 | "" | |
10bbf137 | 11199 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
11200 | |
11201 | (define_expand "epilogue" | |
11202 | [(use (const_int 1))] | |
11203 | "" | |
ed9676cf AK |
11204 | "s390_emit_epilogue (false); DONE;") |
11205 | ||
11206 | (define_expand "sibcall_epilogue" | |
11207 | [(use (const_int 0))] | |
11208 | "" | |
11209 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 11210 | |
177bc204 RS |
11211 | ;; A direct return instruction, without using an epilogue. |
11212 | (define_insn "<code>" | |
11213 | [(ANY_RETURN)] | |
11214 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
11215 | { |
11216 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11217 | { | |
11218 | /* The target is always r14 so there is no clobber | |
11219 | of r1 needed for pre z10 targets. */ | |
11220 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
11221 | INVALID_REGNUM, | |
11222 | NULL_RTX, | |
11223 | s390_indirect_branch_type_return); | |
11224 | return ""; | |
11225 | } | |
11226 | else | |
11227 | return "br\t%%r14"; | |
11228 | } | |
11229 | [(set (attr "op_type") | |
11230 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11231 | (const_string "RIL") | |
11232 | (const_string "RR"))) | |
11233 | (set (attr "mnemonic") | |
11234 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11235 | (const_string "jg") | |
11236 | (const_string "br"))) | |
177bc204 RS |
11237 | (set_attr "type" "jsr") |
11238 | (set_attr "atype" "agen")]) | |
11239 | ||
84b4c7b5 AK |
11240 | |
11241 | (define_expand "return_use" | |
11242 | [(parallel | |
11243 | [(return) | |
11244 | (use (match_operand 0 "register_operand" "a"))])] | |
11245 | "" | |
11246 | { | |
11247 | if (!TARGET_CPU_Z10 | |
11248 | && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) | |
11249 | { | |
11250 | if (TARGET_64BIT) | |
11251 | emit_jump_insn (gen_returndi_prez10 (operands[0])); | |
11252 | else | |
11253 | emit_jump_insn (gen_returnsi_prez10 (operands[0])); | |
11254 | DONE; | |
11255 | } | |
11256 | }) | |
11257 | ||
11258 | (define_insn "*return<mode>" | |
4023fb28 | 11259 | [(return) |
84b4c7b5 AK |
11260 | (use (match_operand:P 0 "register_operand" "a"))] |
11261 | "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
11262 | { | |
11263 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11264 | { | |
11265 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
11266 | INVALID_REGNUM, | |
11267 | NULL_RTX, | |
11268 | s390_indirect_branch_type_return); | |
11269 | return ""; | |
11270 | } | |
11271 | else | |
11272 | return "br\t%0"; | |
11273 | } | |
11274 | [(set (attr "op_type") | |
11275 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11276 | (const_string "RIL") | |
11277 | (const_string "RR"))) | |
11278 | (set (attr "mnemonic") | |
11279 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11280 | (const_string "jg") | |
11281 | (const_string "br"))) | |
11282 | (set_attr "type" "jsr") | |
11283 | (set_attr "atype" "agen")]) | |
11284 | ||
11285 | (define_insn "return<mode>_prez10" | |
11286 | [(return) | |
11287 | (use (match_operand:P 0 "register_operand" "a")) | |
11288 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
11289 | "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
11290 | { | |
11291 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11292 | { | |
11293 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
11294 | INVALID_REGNUM, | |
11295 | NULL_RTX, | |
11296 | s390_indirect_branch_type_return); | |
11297 | return ""; | |
11298 | } | |
11299 | else | |
11300 | return "br\t%0"; | |
11301 | } | |
11302 | [(set (attr "op_type") | |
11303 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11304 | (const_string "RIL") | |
11305 | (const_string "RR"))) | |
11306 | (set (attr "mnemonic") | |
11307 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11308 | (const_string "jg") | |
11309 | (const_string "br"))) | |
c7453384 | 11310 | (set_attr "type" "jsr") |
077dab3b | 11311 | (set_attr "atype" "agen")]) |
4023fb28 | 11312 | |
4023fb28 | 11313 | |
c7453384 | 11314 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 11315 | ;; pointer. This is used for compatibility. |
c7453384 EC |
11316 | |
11317 | (define_expand "ptr_extend" | |
11318 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11319 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 11320 | "TARGET_64BIT" |
c7453384 | 11321 | { |
c7453384 EC |
11322 | emit_insn (gen_anddi3 (operands[0], |
11323 | gen_lowpart (DImode, operands[1]), | |
11324 | GEN_INT (0x7fffffff))); | |
c7453384 | 11325 | DONE; |
10bbf137 | 11326 | }) |
4798630c D |
11327 | |
11328 | ;; Instruction definition to expand eh_return macro to support | |
11329 | ;; swapping in special linkage return addresses. | |
11330 | ||
11331 | (define_expand "eh_return" | |
11332 | [(use (match_operand 0 "register_operand" ""))] | |
11333 | "TARGET_TPF" | |
11334 | { | |
11335 | s390_emit_tpf_eh_return (operands[0]); | |
11336 | DONE; | |
11337 | }) | |
11338 | ||
7b8acc34 AK |
11339 | ; |
11340 | ; Stack Protector Patterns | |
11341 | ; | |
11342 | ||
11343 | (define_expand "stack_protect_set" | |
11344 | [(set (match_operand 0 "memory_operand" "") | |
11345 | (match_operand 1 "memory_operand" ""))] | |
11346 | "" | |
11347 | { | |
11348 | #ifdef TARGET_THREAD_SSP_OFFSET | |
11349 | operands[1] | |
11350 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11351 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11352 | #endif | |
11353 | if (TARGET_64BIT) | |
11354 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
11355 | else | |
11356 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
11357 | ||
11358 | DONE; | |
11359 | }) | |
11360 | ||
11361 | (define_insn "stack_protect_set<mode>" | |
11362 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
11363 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
11364 | "" | |
11365 | "mvc\t%O0(%G0,%R0),%S1" | |
11366 | [(set_attr "op_type" "SS")]) | |
11367 | ||
11368 | (define_expand "stack_protect_test" | |
11369 | [(set (reg:CC CC_REGNUM) | |
11370 | (compare (match_operand 0 "memory_operand" "") | |
11371 | (match_operand 1 "memory_operand" ""))) | |
11372 | (match_operand 2 "" "")] | |
11373 | "" | |
11374 | { | |
f90b7a5a | 11375 | rtx cc_reg, test; |
7b8acc34 AK |
11376 | #ifdef TARGET_THREAD_SSP_OFFSET |
11377 | operands[1] | |
11378 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11379 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11380 | #endif | |
7b8acc34 AK |
11381 | if (TARGET_64BIT) |
11382 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
11383 | else | |
11384 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
11385 | ||
f90b7a5a PB |
11386 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
11387 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
11388 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
11389 | DONE; |
11390 | }) | |
11391 | ||
11392 | (define_insn "stack_protect_test<mode>" | |
11393 | [(set (reg:CCZ CC_REGNUM) | |
11394 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
11395 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
11396 | "" | |
11397 | "clc\t%O0(%G0,%R0),%S1" | |
11398 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
11399 | |
11400 | ; This is used in s390_emit_prologue in order to prevent insns | |
11401 | ; adjusting the stack pointer to be moved over insns writing stack | |
11402 | ; slots using a copy of the stack pointer in a different register. | |
11403 | (define_insn "stack_tie" | |
11404 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
11405 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
11406 | "" | |
11407 | "" | |
11408 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
11409 | |
11410 | ||
82c6f58a AK |
11411 | (define_insn "stack_restore_from_fpr" |
11412 | [(set (reg:DI STACK_REGNUM) | |
11413 | (match_operand:DI 0 "register_operand" "f")) | |
11414 | (clobber (mem:BLK (scratch)))] | |
11415 | "TARGET_Z10" | |
11416 | "lgdr\t%%r15,%0" | |
11417 | [(set_attr "op_type" "RRE")]) | |
11418 | ||
963fc8d0 AK |
11419 | ; |
11420 | ; Data prefetch patterns | |
11421 | ; | |
11422 | ||
11423 | (define_insn "prefetch" | |
3e4be43f UW |
11424 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
11425 | (match_operand:SI 1 "const_int_operand" " n,n") | |
11426 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 11427 | "TARGET_Z10" |
963fc8d0 | 11428 | { |
4fe6dea8 AK |
11429 | switch (which_alternative) |
11430 | { | |
11431 | case 0: | |
4fe6dea8 | 11432 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 11433 | case 1: |
4fe6dea8 AK |
11434 | if (larl_operand (operands[0], Pmode)) |
11435 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 11436 | /* fallthrough */ |
4fe6dea8 AK |
11437 | default: |
11438 | ||
11439 | /* This might be reached for symbolic operands with an odd | |
11440 | addend. We simply omit the prefetch for such rare cases. */ | |
11441 | ||
11442 | return ""; | |
11443 | } | |
9381e3f1 | 11444 | } |
22d72dbc AK |
11445 | [(set_attr "type" "load,larl") |
11446 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea | 11447 | (set_attr "z10prop" "z10_super") |
14cfceb7 IL |
11448 | (set_attr "z196prop" "z196_alone") |
11449 | (set_attr "relative_long" "yes")]) | |
07da44ab AK |
11450 | |
11451 | ||
11452 | ; | |
11453 | ; Byte swap instructions | |
11454 | ; | |
11455 | ||
511f5bb1 AK |
11456 | ; FIXME: There is also mvcin but we cannot use it since src and target |
11457 | ; may overlap. | |
50dc4eed | 11458 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 11459 | (define_insn "bswap<mode>2" |
3e4be43f UW |
11460 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
11461 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11462 | "" |
07da44ab AK |
11463 | "@ |
11464 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
11465 | lrv<g>\t%0,%1 |
11466 | strv<g>\t%1,%0" | |
11467 | [(set_attr "type" "*,load,store") | |
11468 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 11469 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11470 | |
511f5bb1 | 11471 | (define_insn "bswaphi2" |
3e4be43f UW |
11472 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
11473 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11474 | "" |
6f5a59d1 AK |
11475 | "@ |
11476 | # | |
11477 | lrvh\t%0,%1 | |
11478 | strvh\t%1,%0" | |
11479 | [(set_attr "type" "*,load,store") | |
11480 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 11481 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11482 | |
6f5a59d1 AK |
11483 | (define_split |
11484 | [(set (match_operand:HI 0 "register_operand" "") | |
11485 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
8cc6307c | 11486 | "" |
6f5a59d1 | 11487 | [(set (match_dup 2) (bswap:SI (match_dup 3))) |
9060e335 | 11488 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 11489 | { |
9060e335 | 11490 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
11491 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
11492 | }) | |
11493 | ||
11494 | ||
65b1d8ea AK |
11495 | ; |
11496 | ; Population count instruction | |
11497 | ; | |
11498 | ||
25cb5165 AK |
11499 | (define_insn "*popcountdi_arch13_cc" |
11500 | [(set (reg CC_REGNUM) | |
11501 | (compare (popcount:DI (match_operand:DI 1 "register_operand" "d")) | |
11502 | (const_int 0))) | |
11503 | (set (match_operand:DI 0 "register_operand" "=d") | |
11504 | (match_dup 1))] | |
11505 | "TARGET_ARCH13 && s390_match_ccmode (insn, CCTmode)" | |
11506 | "popcnt\t%0,%1,8" | |
11507 | [(set_attr "op_type" "RRF")]) | |
11508 | ||
11509 | (define_insn "*popcountdi_arch13_cconly" | |
11510 | [(set (reg CC_REGNUM) | |
11511 | (compare (popcount:DI (match_operand:DI 1 "register_operand" "d")) | |
11512 | (const_int 0))) | |
11513 | (clobber (match_scratch:DI 0 "=d"))] | |
11514 | "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)" | |
11515 | "popcnt\t%0,%1,8" | |
11516 | [(set_attr "op_type" "RRF")]) | |
11517 | ||
11518 | (define_insn "*popcountdi_arch13" | |
11519 | [(set (match_operand:DI 0 "register_operand" "=d") | |
11520 | (popcount:DI (match_operand:DI 1 "register_operand" "d"))) | |
11521 | (clobber (reg:CC CC_REGNUM))] | |
11522 | "TARGET_ARCH13" | |
11523 | "popcnt\t%0,%1,8" | |
11524 | [(set_attr "op_type" "RRF")]) | |
11525 | ||
11526 | ; The pre-arch13 popcount instruction counts the bits of op1 in 8 byte | |
65b1d8ea | 11527 | ; portions and stores the result in the corresponding bytes in op0. |
25cb5165 | 11528 | (define_insn "*popcount<mode>_z196" |
65b1d8ea AK |
11529 | [(set (match_operand:INT 0 "register_operand" "=d") |
11530 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
11531 | (clobber (reg:CC CC_REGNUM))] | |
11532 | "TARGET_Z196" | |
11533 | "popcnt\t%0,%1" | |
11534 | [(set_attr "op_type" "RRE")]) | |
11535 | ||
25cb5165 | 11536 | (define_expand "popcountdi2_z196" |
65b1d8ea AK |
11537 | [; popcnt op0, op1 |
11538 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
11539 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
11540 | UNSPEC_POPCNT)) | |
11541 | (clobber (reg:CC CC_REGNUM))]) | |
11542 | ; sllg op2, op0, 32 | |
11543 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
11544 | ; agr op0, op2 | |
11545 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11546 | (clobber (reg:CC CC_REGNUM))]) | |
11547 | ; sllg op2, op0, 16 | |
17465c6e | 11548 | (set (match_dup 2) |
65b1d8ea AK |
11549 | (ashift:DI (match_dup 0) (const_int 16))) |
11550 | ; agr op0, op2 | |
11551 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11552 | (clobber (reg:CC CC_REGNUM))]) | |
11553 | ; sllg op2, op0, 8 | |
11554 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
11555 | ; agr op0, op2 | |
11556 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11557 | (clobber (reg:CC CC_REGNUM))]) | |
11558 | ; srlg op0, op0, 56 | |
11559 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
25cb5165 | 11560 | "TARGET_Z196" |
65b1d8ea AK |
11561 | "operands[2] = gen_reg_rtx (DImode);") |
11562 | ||
25cb5165 AK |
11563 | (define_expand "popcountdi2" |
11564 | [(parallel | |
11565 | [(set (match_operand:DI 0 "register_operand" "") | |
11566 | (popcount:DI (match_operand:DI 1 "register_operand"))) | |
11567 | (clobber (reg:CC CC_REGNUM))])] | |
11568 | "TARGET_Z196" | |
11569 | { | |
11570 | if (!TARGET_ARCH13) | |
11571 | { | |
11572 | emit_insn (gen_popcountdi2_z196 (operands[0], operands[1])); | |
11573 | DONE; | |
11574 | } | |
11575 | }) | |
11576 | ||
11577 | (define_expand "popcountsi2_z196" | |
65b1d8ea AK |
11578 | [; popcnt op0, op1 |
11579 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
11580 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
11581 | UNSPEC_POPCNT)) | |
11582 | (clobber (reg:CC CC_REGNUM))]) | |
11583 | ; sllk op2, op0, 16 | |
17465c6e | 11584 | (set (match_dup 2) |
65b1d8ea AK |
11585 | (ashift:SI (match_dup 0) (const_int 16))) |
11586 | ; ar op0, op2 | |
11587 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11588 | (clobber (reg:CC CC_REGNUM))]) | |
11589 | ; sllk op2, op0, 8 | |
11590 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
11591 | ; ar op0, op2 | |
11592 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11593 | (clobber (reg:CC CC_REGNUM))]) | |
11594 | ; srl op0, op0, 24 | |
11595 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
11596 | "TARGET_Z196" | |
11597 | "operands[2] = gen_reg_rtx (SImode);") | |
11598 | ||
25cb5165 AK |
11599 | ; popcount always counts on the full 64 bit. With the z196 version |
11600 | ; counting bits per byte we just ignore the upper 4 bytes. With the | |
11601 | ; arch13 version we have to zero out the upper 32 bits first. | |
11602 | (define_expand "popcountsi2" | |
11603 | [(set (match_dup 2) | |
11604 | (zero_extend:DI (match_operand:SI 1 "register_operand"))) | |
11605 | (parallel [(set (match_dup 3) (popcount:DI (match_dup 2))) | |
11606 | (clobber (reg:CC CC_REGNUM))]) | |
11607 | (set (match_operand:SI 0 "register_operand") | |
11608 | (subreg:SI (match_dup 3) 4))] | |
11609 | "TARGET_Z196" | |
11610 | { | |
11611 | if (!TARGET_ARCH13) | |
11612 | { | |
11613 | emit_insn (gen_popcountsi2_z196 (operands[0], operands[1])); | |
11614 | DONE; | |
11615 | } | |
11616 | else | |
11617 | { | |
11618 | operands[2] = gen_reg_rtx (DImode); | |
11619 | operands[3] = gen_reg_rtx (DImode); | |
11620 | } | |
11621 | }) | |
11622 | ||
11623 | (define_expand "popcounthi2_z196" | |
65b1d8ea AK |
11624 | [; popcnt op0, op1 |
11625 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
11626 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
11627 | UNSPEC_POPCNT)) | |
11628 | (clobber (reg:CC CC_REGNUM))]) | |
11629 | ; sllk op2, op0, 8 | |
17465c6e | 11630 | (set (match_dup 2) |
65b1d8ea AK |
11631 | (ashift:SI (match_dup 0) (const_int 8))) |
11632 | ; ar op0, op2 | |
11633 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11634 | (clobber (reg:CC CC_REGNUM))]) | |
11635 | ; srl op0, op0, 8 | |
11636 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
11637 | "TARGET_Z196" | |
11638 | "operands[2] = gen_reg_rtx (SImode);") | |
11639 | ||
25cb5165 AK |
11640 | (define_expand "popcounthi2" |
11641 | [(set (match_dup 2) | |
11642 | (zero_extend:DI (match_operand:HI 1 "register_operand"))) | |
11643 | (parallel [(set (match_dup 3) (popcount:DI (match_dup 2))) | |
11644 | (clobber (reg:CC CC_REGNUM))]) | |
11645 | (set (match_operand:HI 0 "register_operand") | |
11646 | (subreg:HI (match_dup 3) 6))] | |
11647 | "TARGET_Z196" | |
11648 | { | |
11649 | if (!TARGET_ARCH13) | |
11650 | { | |
11651 | emit_insn (gen_popcounthi2_z196 (operands[0], operands[1])); | |
11652 | DONE; | |
11653 | } | |
11654 | else | |
11655 | { | |
11656 | operands[2] = gen_reg_rtx (DImode); | |
11657 | operands[3] = gen_reg_rtx (DImode); | |
11658 | } | |
11659 | }) | |
11660 | ||
11661 | ; For popcount on a single byte the old z196 style popcount | |
11662 | ; instruction is ideal. Since it anyway does a byte-wise popcount we | |
11663 | ; just use it instead of zero extending the QImode input to DImode and | |
11664 | ; using the arch13 popcount variant. | |
65b1d8ea AK |
11665 | (define_expand "popcountqi2" |
11666 | [; popcnt op0, op1 | |
11667 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
11668 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
11669 | UNSPEC_POPCNT)) | |
11670 | (clobber (reg:CC CC_REGNUM))])] | |
11671 | "TARGET_Z196" | |
11672 | "") | |
11673 | ||
11674 | ;; | |
11675 | ;;- Copy sign instructions | |
11676 | ;; | |
11677 | ||
11678 | (define_insn "copysign<mode>3" | |
11679 | [(set (match_operand:FP 0 "register_operand" "=f") | |
11680 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
11681 | (match_operand:FP 2 "register_operand" "f")] | |
11682 | UNSPEC_COPYSIGN))] | |
11683 | "TARGET_Z196" | |
11684 | "cpsdr\t%0,%2,%1" | |
11685 | [(set_attr "op_type" "RRF") | |
11686 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
11687 | |
11688 | ||
11689 | ;; | |
11690 | ;;- Transactional execution instructions | |
11691 | ;; | |
11692 | ||
11693 | ; This splitter helps combine to make use of CC directly when | |
11694 | ; comparing the integer result of a tbegin builtin with a constant. | |
11695 | ; The unspec is already removed by canonicalize_comparison. So this | |
11696 | ; splitters only job is to turn the PARALLEL into separate insns | |
11697 | ; again. Unfortunately this only works with the very first cc/int | |
11698 | ; compare since combine is not able to deal with data flow across | |
11699 | ; basic block boundaries. | |
11700 | ||
11701 | ; It needs to be an insn pattern as well since combine does not apply | |
11702 | ; the splitter directly. Combine would only use it if it actually | |
11703 | ; would reduce the number of instructions. | |
11704 | (define_insn_and_split "*ccraw_to_int" | |
11705 | [(set (pc) | |
11706 | (if_then_else | |
11707 | (match_operator 0 "s390_eqne_operator" | |
11708 | [(reg:CCRAW CC_REGNUM) | |
11709 | (match_operand 1 "const_int_operand" "")]) | |
11710 | (label_ref (match_operand 2 "" "")) | |
11711 | (pc))) | |
11712 | (set (match_operand:SI 3 "register_operand" "=d") | |
11713 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
11714 | "" | |
11715 | "#" | |
11716 | "" | |
11717 | [(set (match_dup 3) | |
11718 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
11719 | (set (pc) | |
11720 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
11721 | (label_ref (match_dup 2)) | |
11722 | (pc)))] | |
11723 | "") | |
11724 | ||
11725 | ; Non-constrained transaction begin | |
11726 | ||
11727 | (define_expand "tbegin" | |
ee163e72 AK |
11728 | [(match_operand:SI 0 "register_operand" "") |
11729 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11730 | "TARGET_HTM" |
11731 | { | |
11732 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
11733 | DONE; | |
11734 | }) | |
11735 | ||
11736 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
11737 | [(match_operand:SI 0 "register_operand" "") |
11738 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11739 | "TARGET_HTM" |
11740 | { | |
11741 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
11742 | DONE; | |
11743 | }) | |
11744 | ||
11745 | (define_expand "tbegin_retry" | |
ee163e72 AK |
11746 | [(match_operand:SI 0 "register_operand" "") |
11747 | (match_operand:BLK 1 "memory_operand" "") | |
11748 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11749 | "TARGET_HTM" |
11750 | { | |
11751 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
11752 | DONE; | |
11753 | }) | |
11754 | ||
11755 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
11756 | [(match_operand:SI 0 "register_operand" "") |
11757 | (match_operand:BLK 1 "memory_operand" "") | |
11758 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11759 | "TARGET_HTM" |
11760 | { | |
11761 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
11762 | DONE; | |
11763 | }) | |
11764 | ||
c914ac45 AK |
11765 | ; Clobber VRs since they don't get restored |
11766 | (define_insn "tbegin_1_z13" | |
11767 | [(set (reg:CCRAW CC_REGNUM) | |
11768 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
11769 | UNSPECV_TBEGIN)) | |
11770 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11771 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
11772 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11773 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11774 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11775 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11776 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11777 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11778 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11779 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11780 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11781 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11782 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11783 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11784 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11785 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11786 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11787 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11788 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11789 | ; not supposed to be used for immediates (see genpreds.c). | |
11790 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11791 | "tbegin\t%1,%x0" | |
11792 | [(set_attr "op_type" "SIL")]) | |
11793 | ||
5a3fe9b6 AK |
11794 | (define_insn "tbegin_1" |
11795 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11796 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11797 | UNSPECV_TBEGIN)) |
2561451d AK |
11798 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11799 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11800 | (clobber (reg:DF 16)) |
11801 | (clobber (reg:DF 17)) | |
11802 | (clobber (reg:DF 18)) | |
11803 | (clobber (reg:DF 19)) | |
11804 | (clobber (reg:DF 20)) | |
11805 | (clobber (reg:DF 21)) | |
11806 | (clobber (reg:DF 22)) | |
11807 | (clobber (reg:DF 23)) | |
11808 | (clobber (reg:DF 24)) | |
11809 | (clobber (reg:DF 25)) | |
11810 | (clobber (reg:DF 26)) | |
11811 | (clobber (reg:DF 27)) | |
11812 | (clobber (reg:DF 28)) | |
11813 | (clobber (reg:DF 29)) | |
11814 | (clobber (reg:DF 30)) | |
11815 | (clobber (reg:DF 31))] | |
11816 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11817 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11818 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11819 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11820 | [(set_attr "op_type" "SIL")]) |
11821 | ||
11822 | ; Same as above but without the FPR clobbers | |
11823 | (define_insn "tbegin_nofloat_1" | |
11824 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11825 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11826 | UNSPECV_TBEGIN)) | |
11827 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11828 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11829 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11830 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11831 | [(set_attr "op_type" "SIL")]) |
11832 | ||
11833 | ||
11834 | ; Constrained transaction begin | |
11835 | ||
11836 | (define_expand "tbeginc" | |
11837 | [(set (reg:CCRAW CC_REGNUM) | |
11838 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11839 | UNSPECV_TBEGINC))] | |
11840 | "TARGET_HTM" | |
11841 | "") | |
11842 | ||
11843 | (define_insn "*tbeginc_1" | |
11844 | [(set (reg:CCRAW CC_REGNUM) | |
11845 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11846 | UNSPECV_TBEGINC))] | |
11847 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11848 | "tbeginc\t0,%x0" | |
11849 | [(set_attr "op_type" "SIL")]) | |
11850 | ||
11851 | ; Transaction end | |
11852 | ||
11853 | (define_expand "tend" | |
11854 | [(set (reg:CCRAW CC_REGNUM) | |
11855 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11856 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11857 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11858 | "TARGET_HTM" | |
11859 | "") | |
11860 | ||
11861 | (define_insn "*tend_1" | |
11862 | [(set (reg:CCRAW CC_REGNUM) | |
11863 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11864 | "TARGET_HTM" | |
11865 | "tend" | |
11866 | [(set_attr "op_type" "S")]) | |
11867 | ||
11868 | ; Transaction abort | |
11869 | ||
11870 | (define_expand "tabort" | |
eae48192 | 11871 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11872 | UNSPECV_TABORT)] |
11873 | "TARGET_HTM && operands != NULL" | |
11874 | { | |
11875 | if (CONST_INT_P (operands[0]) | |
11876 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11877 | { | |
63c79a75 JJ |
11878 | error ("invalid transaction abort code: %wd; values in range 0 " |
11879 | "through 255 are reserved", INTVAL (operands[0])); | |
5a3fe9b6 AK |
11880 | FAIL; |
11881 | } | |
11882 | }) | |
11883 | ||
11884 | (define_insn "*tabort_1" | |
eae48192 | 11885 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11886 | UNSPECV_TABORT)] |
11887 | "TARGET_HTM && operands != NULL" | |
11888 | "tabort\t%Y0" | |
11889 | [(set_attr "op_type" "S")]) | |
11890 | ||
eae48192 AK |
11891 | (define_insn "*tabort_1_plus" |
11892 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11893 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11894 | UNSPECV_TABORT)] | |
11895 | "TARGET_HTM && operands != NULL | |
11896 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11897 | "tabort\t%1(%0)" | |
11898 | [(set_attr "op_type" "S")]) | |
11899 | ||
5a3fe9b6 AK |
11900 | ; Transaction extract nesting depth |
11901 | ||
11902 | (define_insn "etnd" | |
11903 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11904 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11905 | "TARGET_HTM" | |
11906 | "etnd\t%0" | |
11907 | [(set_attr "op_type" "RRE")]) | |
11908 | ||
11909 | ; Non-transactional store | |
11910 | ||
11911 | (define_insn "ntstg" | |
3e4be43f | 11912 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11913 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11914 | UNSPECV_NTSTG))] | |
11915 | "TARGET_HTM" | |
11916 | "ntstg\t%1,%0" | |
11917 | [(set_attr "op_type" "RXY")]) | |
11918 | ||
11919 | ; Transaction perform processor assist | |
11920 | ||
11921 | (define_expand "tx_assist" | |
2561451d AK |
11922 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11923 | (reg:SI GPR0_REGNUM) | |
291a9e98 | 11924 | (const_int PPA_TX_ABORT)] |
5a3fe9b6 AK |
11925 | UNSPECV_PPA)] |
11926 | "TARGET_HTM" | |
2561451d | 11927 | "") |
5a3fe9b6 AK |
11928 | |
11929 | (define_insn "*ppa" | |
11930 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11931 | (match_operand:SI 1 "register_operand" "d") | |
11932 | (match_operand 2 "const_int_operand" "I")] | |
11933 | UNSPECV_PPA)] | |
291a9e98 | 11934 | "(TARGET_ZEC12 || TARGET_HTM) && INTVAL (operands[2]) < 16" |
2561451d | 11935 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11936 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11937 | |
11938 | ||
11939 | ; Set and get floating point control register | |
11940 | ||
3af82a61 | 11941 | (define_insn "sfpc" |
004f64e1 AK |
11942 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11943 | UNSPECV_SFPC)] | |
11944 | "TARGET_HARD_FLOAT" | |
11945 | "sfpc\t%0") | |
11946 | ||
3af82a61 | 11947 | (define_insn "efpc" |
004f64e1 AK |
11948 | [(set (match_operand:SI 0 "register_operand" "=d") |
11949 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11950 | "TARGET_HARD_FLOAT" | |
11951 | "efpc\t%0") | |
3af82a61 AK |
11952 | |
11953 | ||
11954 | ; Load count to block boundary | |
11955 | ||
11956 | (define_insn "lcbb" | |
11957 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11958 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11959 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11960 | (clobber (reg:CC CC_REGNUM))] | |
11961 | "TARGET_Z13" | |
9a36359e | 11962 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11963 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11964 | |
11965 | ; Handle -fsplit-stack. | |
11966 | ||
11967 | (define_expand "split_stack_prologue" | |
11968 | [(const_int 0)] | |
11969 | "" | |
11970 | { | |
11971 | s390_expand_split_stack_prologue (); | |
11972 | DONE; | |
11973 | }) | |
11974 | ||
11975 | ;; If there are operand 0 bytes available on the stack, jump to | |
11976 | ;; operand 1. | |
11977 | ||
11978 | (define_expand "split_stack_space_check" | |
11979 | [(set (pc) (if_then_else | |
11980 | (ltu (minus (reg 15) | |
11981 | (match_operand 0 "register_operand")) | |
11982 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11983 | (label_ref (match_operand 1)) | |
11984 | (pc)))] | |
11985 | "" | |
11986 | { | |
11987 | /* Offset from thread pointer to __private_ss. */ | |
11988 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11989 | rtx tp = s390_get_thread_pointer (); | |
11990 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11991 | rtx reg = gen_reg_rtx (Pmode); | |
11992 | rtx cc; | |
11993 | if (TARGET_64BIT) | |
11994 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11995 | else | |
11996 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11997 | cc = s390_emit_compare (GT, reg, guard); | |
11998 | s390_emit_jump (operands[1], cc); | |
11999 | ||
12000 | DONE; | |
12001 | }) | |
12002 | ||
12003 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
12004 | ;; parameter block label, label to be called by __morestack, frame size, | |
12005 | ;; stack parameter size. | |
12006 | ||
12007 | (define_insn "split_stack_data" | |
12008 | [(unspec_volatile [(match_operand 0 "" "X") | |
12009 | (match_operand 1 "" "X") | |
12010 | (match_operand 2 "const_int_operand" "X") | |
12011 | (match_operand 3 "const_int_operand" "X")] | |
12012 | UNSPECV_SPLIT_STACK_DATA)] | |
8cc6307c | 12013 | "" |
4cb4721f MK |
12014 | { |
12015 | switch_to_section (targetm.asm_out.function_rodata_section | |
12016 | (current_function_decl)); | |
12017 | ||
12018 | if (TARGET_64BIT) | |
12019 | output_asm_insn (".align\t8", operands); | |
12020 | else | |
12021 | output_asm_insn (".align\t4", operands); | |
12022 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
12023 | CODE_LABEL_NUMBER (operands[0])); | |
12024 | if (TARGET_64BIT) | |
12025 | { | |
12026 | output_asm_insn (".quad\t%2", operands); | |
12027 | output_asm_insn (".quad\t%3", operands); | |
12028 | output_asm_insn (".quad\t%1-%0", operands); | |
12029 | } | |
12030 | else | |
12031 | { | |
12032 | output_asm_insn (".long\t%2", operands); | |
12033 | output_asm_insn (".long\t%3", operands); | |
12034 | output_asm_insn (".long\t%1-%0", operands); | |
12035 | } | |
12036 | ||
12037 | switch_to_section (current_function_section ()); | |
12038 | return ""; | |
12039 | } | |
12040 | [(set_attr "length" "0")]) | |
12041 | ||
12042 | ||
12043 | ;; A jg with minimal fuss for use in split stack prologue. | |
12044 | ||
12045 | (define_expand "split_stack_call" | |
12046 | [(match_operand 0 "bras_sym_operand" "X") | |
12047 | (match_operand 1 "" "")] | |
8cc6307c | 12048 | "" |
4cb4721f MK |
12049 | { |
12050 | if (TARGET_64BIT) | |
12051 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
12052 | else | |
12053 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
12054 | DONE; | |
12055 | }) | |
12056 | ||
12057 | (define_insn "split_stack_call_<mode>" | |
12058 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
12059 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
12060 | (reg:P 1)] | |
12061 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 12062 | "" |
4cb4721f MK |
12063 | "jg\t%0" |
12064 | [(set_attr "op_type" "RIL") | |
12065 | (set_attr "type" "branch")]) | |
12066 | ||
12067 | ;; Also a conditional one. | |
12068 | ||
12069 | (define_expand "split_stack_cond_call" | |
12070 | [(match_operand 0 "bras_sym_operand" "X") | |
12071 | (match_operand 1 "" "") | |
12072 | (match_operand 2 "" "")] | |
8cc6307c | 12073 | "" |
4cb4721f MK |
12074 | { |
12075 | if (TARGET_64BIT) | |
12076 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
12077 | else | |
12078 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
12079 | DONE; | |
12080 | }) | |
12081 | ||
12082 | (define_insn "split_stack_cond_call_<mode>" | |
12083 | [(set (pc) | |
12084 | (if_then_else | |
12085 | (match_operand 1 "" "") | |
12086 | (label_ref (match_operand 2 "" "")) | |
12087 | (pc))) | |
12088 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
12089 | (reg:P 1)] | |
12090 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 12091 | "" |
4cb4721f MK |
12092 | "jg%C1\t%0" |
12093 | [(set_attr "op_type" "RIL") | |
12094 | (set_attr "type" "branch")]) | |
539405d5 AK |
12095 | |
12096 | (define_insn "osc_break" | |
12097 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
12098 | "" | |
12099 | "bcr\t7,%%r0" | |
12100 | [(set_attr "op_type" "RR")]) | |
291a9e98 AK |
12101 | |
12102 | (define_expand "speculation_barrier" | |
12103 | [(unspec_volatile [(reg:SI GPR0_REGNUM) | |
12104 | (reg:SI GPR0_REGNUM) | |
12105 | (const_int PPA_OOO_BARRIER)] | |
12106 | UNSPECV_PPA)] | |
12107 | "TARGET_ZEC12" | |
12108 | "") |