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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
85ec4feb | 2 | ;; Copyright (C) 1999-2018 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
77 | UNSPEC_LTREL_OFFSET |
78 | UNSPEC_LTREL_BASE | |
79 | UNSPEC_POOL_OFFSET | |
80 | UNSPEC_GOTENT | |
81 | UNSPEC_GOT | |
82 | UNSPEC_GOTOFF | |
83 | UNSPEC_PLT | |
84 | UNSPEC_PLTOFF | |
fd7643fb UW |
85 | |
86 | ; Literal pool | |
30a49b23 AK |
87 | UNSPEC_RELOAD_BASE |
88 | UNSPEC_MAIN_BASE | |
89 | UNSPEC_LTREF | |
90 | UNSPEC_INSN | |
91 | UNSPEC_EXECUTE | |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
76794c52 | 159 | UNSPEC_VEC_LOAD_LEN_R |
3af82a61 AK |
160 | UNSPEC_VEC_MERGEH |
161 | UNSPEC_VEC_MERGEL | |
162 | UNSPEC_VEC_PACK | |
163 | UNSPEC_VEC_PACK_SATURATE | |
164 | UNSPEC_VEC_PACK_SATURATE_CC | |
165 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
168 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
169 | UNSPEC_VEC_PERM | |
170 | UNSPEC_VEC_PERMI | |
171 | UNSPEC_VEC_EXTEND | |
172 | UNSPEC_VEC_STORE_LEN | |
76794c52 AK |
173 | UNSPEC_VEC_STORE_LEN_R |
174 | UNSPEC_VEC_VBPERM | |
3af82a61 AK |
175 | UNSPEC_VEC_UNPACKH |
176 | UNSPEC_VEC_UNPACKH_L | |
177 | UNSPEC_VEC_UNPACKL | |
178 | UNSPEC_VEC_UNPACKL_L | |
179 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
180 | UNSPEC_VEC_ADDE_U128 |
181 | UNSPEC_VEC_ADDEC_U128 | |
182 | UNSPEC_VEC_AVG | |
183 | UNSPEC_VEC_AVGU | |
184 | UNSPEC_VEC_CHECKSUM | |
185 | UNSPEC_VEC_GFMSUM | |
186 | UNSPEC_VEC_GFMSUM_128 | |
187 | UNSPEC_VEC_GFMSUM_ACCUM | |
188 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
189 | UNSPEC_VEC_SET | |
190 | ||
191 | UNSPEC_VEC_VSUMG | |
192 | UNSPEC_VEC_VSUMQ | |
193 | UNSPEC_VEC_VSUM | |
194 | UNSPEC_VEC_RL_MASK | |
195 | UNSPEC_VEC_SLL | |
196 | UNSPEC_VEC_SLB | |
197 | UNSPEC_VEC_SLDB | |
198 | UNSPEC_VEC_SRAL | |
199 | UNSPEC_VEC_SRAB | |
200 | UNSPEC_VEC_SRL | |
201 | UNSPEC_VEC_SRLB | |
202 | ||
3af82a61 | 203 | UNSPEC_VEC_SUBC |
3af82a61 AK |
204 | UNSPEC_VEC_SUBE_U128 |
205 | UNSPEC_VEC_SUBEC_U128 | |
206 | ||
207 | UNSPEC_VEC_TEST_MASK | |
208 | ||
209 | UNSPEC_VEC_VFAE | |
210 | UNSPEC_VEC_VFAECC | |
211 | ||
212 | UNSPEC_VEC_VFEE | |
213 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
214 | UNSPEC_VEC_VFENE |
215 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
216 | |
217 | UNSPEC_VEC_VISTR | |
218 | UNSPEC_VEC_VISTRCC | |
219 | ||
220 | UNSPEC_VEC_VSTRC | |
221 | UNSPEC_VEC_VSTRCCC | |
222 | ||
223 | UNSPEC_VEC_VCDGB | |
224 | UNSPEC_VEC_VCDLGB | |
225 | ||
226 | UNSPEC_VEC_VCGDB | |
227 | UNSPEC_VEC_VCLGDB | |
228 | ||
76794c52 | 229 | UNSPEC_VEC_VFI |
3af82a61 | 230 | |
76794c52 AK |
231 | UNSPEC_VEC_VFLL ; vector fp load lengthened |
232 | UNSPEC_VEC_VFLR ; vector fp load rounded | |
3af82a61 | 233 | |
76794c52 AK |
234 | UNSPEC_VEC_VFTCI |
235 | UNSPEC_VEC_VFTCICC | |
236 | ||
237 | UNSPEC_VEC_MSUM | |
238 | ||
239 | UNSPEC_VEC_VFMIN | |
240 | UNSPEC_VEC_VFMAX | |
085261c8 | 241 | ]) |
fd3cd001 UW |
242 | |
243 | ;; | |
244 | ;; UNSPEC_VOLATILE usage | |
245 | ;; | |
246 | ||
30a49b23 AK |
247 | (define_c_enum "unspecv" [ |
248 | ; Blockage | |
249 | UNSPECV_BLOCKAGE | |
10bbf137 | 250 | |
2f7e5a0d | 251 | ; TPF Support |
30a49b23 AK |
252 | UNSPECV_TPF_PROLOGUE |
253 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 254 | |
10bbf137 | 255 | ; Literal pool |
30a49b23 AK |
256 | UNSPECV_POOL |
257 | UNSPECV_POOL_SECTION | |
258 | UNSPECV_POOL_ALIGN | |
259 | UNSPECV_POOL_ENTRY | |
260 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
261 | |
262 | ; TLS support | |
30a49b23 | 263 | UNSPECV_SET_TP |
e0374221 AS |
264 | |
265 | ; Atomic Support | |
30a49b23 AK |
266 | UNSPECV_CAS |
267 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 268 | |
f8af0e30 DV |
269 | ; Hotpatching (unremovable NOPs) |
270 | UNSPECV_NOP_2_BYTE | |
271 | UNSPECV_NOP_4_BYTE | |
272 | UNSPECV_NOP_6_BYTE | |
273 | ||
5a3fe9b6 AK |
274 | ; Transactional Execution support |
275 | UNSPECV_TBEGIN | |
2561451d | 276 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
277 | UNSPECV_TBEGINC |
278 | UNSPECV_TEND | |
279 | UNSPECV_TABORT | |
280 | UNSPECV_ETND | |
281 | UNSPECV_NTSTG | |
282 | UNSPECV_PPA | |
004f64e1 AK |
283 | |
284 | ; Set and get floating point control register | |
285 | UNSPECV_SFPC | |
286 | UNSPECV_EFPC | |
4cb4721f MK |
287 | |
288 | ; Split stack support | |
289 | UNSPECV_SPLIT_STACK_CALL | |
290 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
291 | |
292 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
293 | ]) |
294 | ||
ae156f85 AS |
295 | ;; |
296 | ;; Registers | |
297 | ;; | |
298 | ||
35dd9a0e AK |
299 | ; Registers with special meaning |
300 | ||
ae156f85 AS |
301 | (define_constants |
302 | [ | |
303 | ; Sibling call register. | |
304 | (SIBCALL_REGNUM 1) | |
305 | ; Literal pool base register. | |
306 | (BASE_REGNUM 13) | |
307 | ; Return address register. | |
308 | (RETURN_REGNUM 14) | |
82c6f58a AK |
309 | ; Stack pointer register. |
310 | (STACK_REGNUM 15) | |
ae156f85 AS |
311 | ; Condition code register. |
312 | (CC_REGNUM 33) | |
f4aa3848 | 313 | ; Thread local storage pointer register. |
ae156f85 AS |
314 | (TP_REGNUM 36) |
315 | ]) | |
316 | ||
35dd9a0e AK |
317 | ; Hardware register names |
318 | ||
319 | (define_constants | |
320 | [ | |
321 | ; General purpose registers | |
322 | (GPR0_REGNUM 0) | |
af344a30 | 323 | (GPR1_REGNUM 1) |
82379bdf AK |
324 | (GPR2_REGNUM 2) |
325 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
326 | ; Floating point registers. |
327 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
328 | (FPR1_REGNUM 20) |
329 | (FPR2_REGNUM 17) | |
330 | (FPR3_REGNUM 21) | |
331 | (FPR4_REGNUM 18) | |
332 | (FPR5_REGNUM 22) | |
333 | (FPR6_REGNUM 19) | |
334 | (FPR7_REGNUM 23) | |
335 | (FPR8_REGNUM 24) | |
336 | (FPR9_REGNUM 28) | |
337 | (FPR10_REGNUM 25) | |
338 | (FPR11_REGNUM 29) | |
339 | (FPR12_REGNUM 26) | |
340 | (FPR13_REGNUM 30) | |
341 | (FPR14_REGNUM 27) | |
342 | (FPR15_REGNUM 31) | |
085261c8 AK |
343 | (VR0_REGNUM 16) |
344 | (VR16_REGNUM 38) | |
345 | (VR23_REGNUM 45) | |
346 | (VR24_REGNUM 46) | |
347 | (VR31_REGNUM 53) | |
35dd9a0e AK |
348 | ]) |
349 | ||
ae8e301e AK |
350 | ; Rounding modes for binary floating point numbers |
351 | (define_constants | |
352 | [(BFP_RND_CURRENT 0) | |
353 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
354 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
355 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
356 | (BFP_RND_TOWARD_0 5) | |
357 | (BFP_RND_TOWARD_INF 6) | |
358 | (BFP_RND_TOWARD_MINF 7)]) | |
359 | ||
360 | ; Rounding modes for decimal floating point numbers | |
361 | ; 1-7 were introduced with the floating point extension facility | |
362 | ; available with z196 | |
363 | ; With these rounding modes (1-7) a quantum exception might occur | |
364 | ; which is suppressed for the other modes. | |
365 | (define_constants | |
366 | [(DFP_RND_CURRENT 0) | |
367 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
368 | (DFP_RND_CURRENT_QUANTEXC 2) | |
369 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
370 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
371 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
372 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
373 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
374 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
375 | (DFP_RND_TOWARD_0 9) | |
376 | (DFP_RND_TOWARD_INF 10) | |
377 | (DFP_RND_TOWARD_MINF 11) | |
378 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
379 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
380 | (DFP_RND_AWAY_FROM_0 14) | |
381 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
382 | ||
35dd9a0e AK |
383 | ;; |
384 | ;; PFPO GPR0 argument format | |
385 | ;; | |
386 | ||
387 | (define_constants | |
388 | [ | |
389 | ; PFPO operation type | |
390 | (PFPO_CONVERT 0x1000000) | |
391 | ; PFPO operand types | |
392 | (PFPO_OP_TYPE_SF 0x5) | |
393 | (PFPO_OP_TYPE_DF 0x6) | |
394 | (PFPO_OP_TYPE_TF 0x7) | |
395 | (PFPO_OP_TYPE_SD 0x8) | |
396 | (PFPO_OP_TYPE_DD 0x9) | |
397 | (PFPO_OP_TYPE_TD 0xa) | |
398 | ; Bitposition of operand types | |
399 | (PFPO_OP0_TYPE_SHIFT 16) | |
400 | (PFPO_OP1_TYPE_SHIFT 8) | |
401 | ]) | |
402 | ||
5a3fe9b6 AK |
403 | ; Immediate operands for tbegin and tbeginc |
404 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
405 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 406 | |
29a74354 UW |
407 | ;; Instruction operand type as used in the Principles of Operation. |
408 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 409 | |
29a74354 | 410 | (define_attr "op_type" |
76794c52 | 411 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" |
b628bd8e | 412 | (const_string "NN")) |
9db1d521 | 413 | |
29a74354 | 414 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 415 | |
077dab3b | 416 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 417 | cs,vs,store,sem,idiv, |
ed0e512a | 418 | imulhi,imulsi,imuldi, |
2cdece44 | 419 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
420 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
421 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 422 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 423 | fmadddf,fmaddsf, |
9381e3f1 WG |
424 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
425 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
426 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
427 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
428 | ftoidfp, other" | |
29a74354 UW |
429 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
430 | (eq_attr "op_type" "SS") (const_string "cs")] | |
431 | (const_string "integer"))) | |
9db1d521 | 432 | |
29a74354 UW |
433 | ;; Another attribute used for scheduling purposes: |
434 | ;; agen: Instruction uses the address generation unit | |
435 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
436 | |
437 | (define_attr "atype" "agen,reg" | |
62d3f261 | 438 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
439 | (const_string "reg") |
440 | (const_string "agen"))) | |
9db1d521 | 441 | |
9381e3f1 WG |
442 | ;; Properties concerning Z10 execution grouping and value forwarding. |
443 | ;; z10_super: instruction is superscalar. | |
444 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
445 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
446 | ;; target register. It can forward this value to a second instruction that reads | |
447 | ;; the same register if that second instruction is issued in the same group. | |
448 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
449 | ;; instruction in the S pipe writes to the register, then the T instruction | |
450 | ;; can immediately read the new value. | |
451 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
452 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
453 | ;; |
454 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
455 | ||
456 | ||
457 | (define_attr "z10prop" "none, | |
458 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
459 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
460 | z10_rec, | |
461 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 462 | z10_c" |
9381e3f1 WG |
463 | (const_string "none")) |
464 | ||
65b1d8ea AK |
465 | ;; Properties concerning Z196 decoding |
466 | ;; z196_alone: must group alone | |
467 | ;; z196_end: ends a group | |
468 | ;; z196_cracked: instruction is cracked or expanded | |
469 | (define_attr "z196prop" "none, | |
470 | z196_alone, z196_ends, | |
471 | z196_cracked" | |
472 | (const_string "none")) | |
9381e3f1 | 473 | |
a9cc3f58 | 474 | (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 475 | |
9db1d521 HP |
476 | ;; Length in bytes. |
477 | ||
478 | (define_attr "length" "" | |
62d3f261 AK |
479 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
480 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 481 | (const_int 6))) |
9db1d521 | 482 | |
29a74354 UW |
483 | |
484 | ;; Processor type. This attribute must exactly match the processor_type | |
485 | ;; enumeration in s390.h. The current machine description does not | |
486 | ;; distinguish between g5 and g6, but there are differences between the two | |
487 | ;; CPUs could in theory be modeled. | |
488 | ||
6654e96f | 489 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,arch12" |
90c6fd8a | 490 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 491 | |
b5e0425c | 492 | (define_attr "cpu_facility" |
6654e96f | 493 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,arch12,vxe" |
3af8e996 AK |
494 | (const_string "standard")) |
495 | ||
496 | (define_attr "enabled" "" | |
497 | (cond [(eq_attr "cpu_facility" "standard") | |
498 | (const_int 1) | |
499 | ||
500 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 501 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
502 | (const_int 1) |
503 | ||
504 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 505 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
506 | (const_int 1) |
507 | ||
508 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 509 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
510 | (const_int 1) |
511 | ||
512 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 513 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
514 | (const_int 1) |
515 | ||
516 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 517 | (match_test "TARGET_DFP")) |
93538e8e AK |
518 | (const_int 1) |
519 | ||
b5e0425c AK |
520 | (and (eq_attr "cpu_facility" "cpu_zarch") |
521 | (match_test "TARGET_CPU_ZARCH")) | |
522 | (const_int 1) | |
523 | ||
93538e8e | 524 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 525 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
526 | (const_int 1) |
527 | ||
528 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 529 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
530 | (const_int 1) |
531 | ||
532 | (and (eq_attr "cpu_facility" "zEC12") | |
533 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
534 | (const_int 1) |
535 | ||
285363a1 | 536 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 537 | (match_test "TARGET_VX")) |
bf749919 DV |
538 | (const_int 1) |
539 | ||
540 | (and (eq_attr "cpu_facility" "z13") | |
541 | (match_test "TARGET_Z13")) | |
542 | (const_int 1) | |
6654e96f AK |
543 | |
544 | (and (eq_attr "cpu_facility" "arch12") | |
545 | (match_test "TARGET_ARCH12")) | |
546 | (const_int 1) | |
547 | ||
548 | (and (eq_attr "cpu_facility" "vxe") | |
549 | (match_test "TARGET_VXE")) | |
550 | (const_int 1) | |
bf749919 | 551 | ] |
3af8e996 AK |
552 | (const_int 0))) |
553 | ||
29a74354 UW |
554 | ;; Pipeline description for z900. For lack of anything better, |
555 | ;; this description is also used for the g5 and g6. | |
556 | (include "2064.md") | |
557 | ||
3443392a | 558 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
559 | (include "2084.md") |
560 | ||
9381e3f1 WG |
561 | ;; Pipeline description for z10 |
562 | (include "2097.md") | |
563 | ||
65b1d8ea AK |
564 | ;; Pipeline description for z196 |
565 | (include "2817.md") | |
566 | ||
22ac2c2f AK |
567 | ;; Pipeline description for zEC12 |
568 | (include "2827.md") | |
569 | ||
23902021 AK |
570 | ;; Pipeline description for z13 |
571 | (include "2964.md") | |
572 | ||
0bfc3f69 AS |
573 | ;; Predicates |
574 | (include "predicates.md") | |
575 | ||
cd8dc1f9 WG |
576 | ;; Constraint definitions |
577 | (include "constraints.md") | |
578 | ||
a8ba31f2 EC |
579 | ;; Other includes |
580 | (include "tpf.md") | |
f52c81dd | 581 | |
3abcb3a7 | 582 | ;; Iterators |
f52c81dd | 583 | |
085261c8 AK |
584 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
585 | ||
3abcb3a7 | 586 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 587 | ;; same template. |
f4aa3848 | 588 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 589 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
590 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
591 | (define_mode_iterator BFP [TF DF SF]) | |
592 | (define_mode_iterator DFP [TD DD]) | |
593 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
594 | (define_mode_iterator DSF [DF SF]) | |
595 | (define_mode_iterator SD_SF [SF SD]) | |
596 | (define_mode_iterator DD_DF [DF DD]) | |
597 | (define_mode_iterator TD_TF [TF TD]) | |
598 | ||
3abcb3a7 | 599 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 600 | ;; from the same template. |
9602b6a1 | 601 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 602 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 603 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 604 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 605 | |
3abcb3a7 | 606 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 607 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 608 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 609 | |
78ce265b RH |
610 | ;; These macros refer to the actual word_mode of the configuration. |
611 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
612 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
613 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
614 | ||
6e0d70c9 AK |
615 | ;; Used by the umul pattern to express modes having half the size. |
616 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
617 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
618 | ||
3abcb3a7 | 619 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 620 | ;; the same template. |
3abcb3a7 | 621 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 622 | |
3abcb3a7 | 623 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 624 | ;; same template. |
9602b6a1 | 625 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 626 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 627 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 628 | |
3abcb3a7 | 629 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 630 | ;; the same template. |
3abcb3a7 | 631 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 632 | |
d12a76f3 | 633 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
634 | (define_code_iterator IXOR [ior xor]) |
635 | ||
d12a76f3 AK |
636 | ;; This iterator is used to expand the patterns for the nearest |
637 | ;; integer functions. | |
638 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
639 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
640 | UNSPEC_FPINT_NEARBYINT]) | |
641 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
642 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
643 | (UNSPEC_FPINT_ROUND "round") | |
644 | (UNSPEC_FPINT_CEIL "ceil") | |
645 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
646 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
647 | (UNSPEC_FPINT_BTRUNC "5") | |
648 | (UNSPEC_FPINT_ROUND "1") | |
649 | (UNSPEC_FPINT_CEIL "6") | |
650 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
651 | ||
3abcb3a7 HPN |
652 | ;; This iterator and attribute allow to combine most atomic operations. |
653 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 654 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 655 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 656 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 657 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 658 | |
f4aa3848 | 659 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
660 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
661 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 662 | |
f4aa3848 AK |
663 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
664 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
665 | ;; SDmode. |
666 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 667 | |
609e7e80 | 668 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
669 | ;; Likewise for "<RXe>". |
670 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
671 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
672 | ||
609e7e80 | 673 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 674 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
675 | ;; dfp variants in a single insn definition. |
676 | ||
62d3f261 AK |
677 | ;; These mode attributes are supposed to be used in the `enabled' insn |
678 | ;; attribute to disable certain alternatives for certain modes. | |
679 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
680 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
681 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
682 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
683 | (TD "0") (DD "0") (DD "0") | |
684 | (TI "0") (DI "*") (SI "0")]) | |
2de2b3f9 AK |
685 | (define_mode_attr DF [(TF "0") (DF "*") (SF "0") |
686 | (TD "0") (DD "0") (DD "0") | |
687 | (TI "0") (DI "0") (SI "0")]) | |
688 | (define_mode_attr SF [(TF "0") (DF "0") (SF "*") | |
689 | (TD "0") (DD "0") (DD "0") | |
690 | (TI "0") (DI "0") (SI "0")]) | |
f5905b37 | 691 | |
85dae55a AK |
692 | ;; This attribute is used in the operand constraint list |
693 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
694 | ;; TFmode values are represented by a fp register pair. Since the | |
695 | ;; sign bit instructions only handle single source and target fp registers | |
696 | ;; these instructions can only be used for TFmode values if the source and | |
697 | ;; target operand uses the same fp register. | |
698 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
699 | ||
3abcb3a7 | 700 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
701 | ;; within instruction mnemonics. |
702 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
703 | ||
0387c142 WG |
704 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
705 | ;; modes and to an empty string for bfp modes. | |
706 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
707 | ||
1b48c8cc AS |
708 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
709 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
710 | ;; version only operates on one register. | |
711 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
712 | ||
713 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
714 | ;; version only operates on one register. The DImode version needs an additional | |
715 | ;; register for the assembler output. | |
716 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
717 | |
718 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
719 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
720 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
721 | ||
722 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 723 | ;; pattern itself and the corresponding function calls. |
f337b930 | 724 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
725 | |
726 | ;; This attribute handles differences in the instruction 'type' and will result | |
727 | ;; in "RRE" for DImode and "RR" for SImode. | |
728 | (define_mode_attr E [(DI "E") (SI "")]) | |
729 | ||
3298c037 AK |
730 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
731 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
732 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
733 | ||
8006eaa6 AS |
734 | ;; This attribute handles differences in the instruction 'type' and will result |
735 | ;; in "RSE" for TImode and "RS" for DImode. | |
736 | (define_mode_attr TE [(TI "E") (DI "")]) | |
737 | ||
9a91a21f AS |
738 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
739 | ;; and "lcr" in SImode. | |
740 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 741 | |
3298c037 AK |
742 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
743 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
744 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
745 | ;; variant for long displacements. | |
746 | (define_mode_attr y [(DI "g") (SI "y")]) | |
747 | ||
9602b6a1 | 748 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
749 | ;; and "cds" in DImode. |
750 | (define_mode_attr tg [(TI "g") (DI "")]) | |
751 | ||
78ce265b RH |
752 | ;; In TDI templates, a string like "c<d>sg". |
753 | (define_mode_attr td [(TI "d") (DI "")]) | |
754 | ||
2f8f8434 AS |
755 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
756 | ;; and "cfdbr" in SImode. | |
757 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
758 | ||
65b1d8ea AK |
759 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
760 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
761 | ;; 3 operands shift instructions into the existing patterns. | |
762 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
763 | ||
f52c81dd AS |
764 | ;; ICM mask required to load MODE value into the lowest subreg |
765 | ;; of a SImode register. | |
766 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
767 | ||
f6ee577c AS |
768 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
769 | ;; HImode and "llgc" in QImode. | |
770 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
771 | ||
a1aed706 AS |
772 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
773 | ;; in SImode. | |
774 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
775 | ||
609e7e80 AK |
776 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
777 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
778 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
779 | ||
f52c81dd AS |
780 | ;; Maximum unsigned integer that fits in MODE. |
781 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
782 | ||
75ca1b39 RH |
783 | ;; Start and end field computations for RISBG et al. |
784 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
785 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
786 | ||
2542ef05 RH |
787 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
788 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
789 | ;; 64 - bitsize |
790 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
791 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 792 | |
da0dcab1 DV |
793 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
794 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
795 | ||
177bc204 RS |
796 | ;; Allow return and simple_return to be defined from a single template. |
797 | (define_code_iterator ANY_RETURN [return simple_return]) | |
798 | ||
6e5b5de8 AK |
799 | |
800 | ||
801 | ; Condition code modes generated by vector fp comparisons. These will | |
802 | ; be used also in single element mode. | |
803 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
804 | ; Used with VFCMP to expand part of the mnemonic | |
805 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
806 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 807 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 808 | |
191eb16d AK |
809 | ;; Subst pattern definitions |
810 | (include "subst.md") | |
6e5b5de8 | 811 | |
085261c8 AK |
812 | (include "vector.md") |
813 | ||
9db1d521 HP |
814 | ;; |
815 | ;;- Compare instructions. | |
816 | ;; | |
817 | ||
07893d4f | 818 | ; Test-under-Mask instructions |
9db1d521 | 819 | |
07893d4f | 820 | (define_insn "*tmqi_mem" |
ae156f85 | 821 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
822 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
823 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
824 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 825 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 826 | "@ |
fc0ea003 UW |
827 | tm\t%S0,%b1 |
828 | tmy\t%S0,%b1" | |
9381e3f1 | 829 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 830 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 831 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 832 | |
05b9aaaa | 833 | (define_insn "*tmdi_reg" |
ae156f85 | 834 | [(set (reg CC_REGNUM) |
f19a9af7 | 835 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 836 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
837 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
838 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 839 | "TARGET_ZARCH |
3ed99cc9 | 840 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
841 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
842 | "@ | |
843 | tmhh\t%0,%i1 | |
844 | tmhl\t%0,%i1 | |
845 | tmlh\t%0,%i1 | |
846 | tmll\t%0,%i1" | |
9381e3f1 WG |
847 | [(set_attr "op_type" "RI") |
848 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
849 | |
850 | (define_insn "*tmsi_reg" | |
ae156f85 | 851 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
852 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
853 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
854 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 855 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
856 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
857 | "@ | |
858 | tmh\t%0,%i1 | |
859 | tml\t%0,%i1" | |
729e750f WG |
860 | [(set_attr "op_type" "RI") |
861 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 862 | |
f52c81dd | 863 | (define_insn "*tm<mode>_full" |
ae156f85 | 864 | [(set (reg CC_REGNUM) |
f52c81dd AS |
865 | (compare (match_operand:HQI 0 "register_operand" "d") |
866 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 867 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 868 | "tml\t%0,<max_uint>" |
729e750f WG |
869 | [(set_attr "op_type" "RI") |
870 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 871 | |
07893d4f | 872 | |
08a5aaa2 | 873 | ; |
07893d4f | 874 | ; Load-and-Test instructions |
08a5aaa2 AS |
875 | ; |
876 | ||
c0220ea4 | 877 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
878 | |
879 | (define_insn "*tstdi_sign" | |
ae156f85 | 880 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
881 | (compare |
882 | (ashiftrt:DI | |
883 | (ashift:DI | |
3e4be43f | 884 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
885 | (const_int 32)) (const_int 32)) |
886 | (match_operand:DI 1 "const0_operand" ""))) | |
887 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 888 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 889 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
890 | "ltgfr\t%2,%0 |
891 | ltgf\t%2,%0" | |
892 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
893 | (set_attr "cpu_facility" "*,z10") |
894 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 895 | |
43a09b63 | 896 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 897 | (define_insn "*tst<mode>_extimm" |
ec24698e | 898 | [(set (reg CC_REGNUM) |
3e4be43f | 899 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
900 | (match_operand:GPR 1 "const0_operand" ""))) |
901 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 902 | (match_dup 0))] |
08a5aaa2 | 903 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 904 | "@ |
08a5aaa2 AS |
905 | lt<g>r\t%2,%0 |
906 | lt<g>\t%2,%0" | |
9381e3f1 | 907 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 908 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 909 | |
97160c9b DV |
910 | ; Peephole to combine a load-and-test from volatile memory which combine does |
911 | ; not do. | |
912 | (define_peephole2 | |
913 | [(set (match_operand:GPR 0 "register_operand") | |
914 | (match_operand:GPR 2 "memory_operand")) | |
915 | (set (reg CC_REGNUM) | |
916 | (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] | |
917 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM | |
918 | && GENERAL_REG_P (operands[0]) | |
919 | && satisfies_constraint_T (operands[2])" | |
920 | [(parallel | |
921 | [(set (reg:CCS CC_REGNUM) | |
922 | (compare:CCS (match_dup 2) (match_dup 1))) | |
923 | (set (match_dup 0) (match_dup 2))])]) | |
924 | ||
43a09b63 | 925 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 926 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 927 | [(set (reg CC_REGNUM) |
3e4be43f | 928 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
929 | (match_operand:GPR 1 "const0_operand" ""))) |
930 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
931 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 932 | "@ |
08a5aaa2 AS |
933 | lt<g>r\t%0,%0 |
934 | lt<g>\t%2,%0" | |
9381e3f1 | 935 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 936 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 937 | |
07893d4f | 938 | (define_insn "*tstdi" |
ae156f85 | 939 | [(set (reg CC_REGNUM) |
07893d4f UW |
940 | (compare (match_operand:DI 0 "register_operand" "d") |
941 | (match_operand:DI 1 "const0_operand" ""))) | |
942 | (set (match_operand:DI 2 "register_operand" "=d") | |
943 | (match_dup 0))] | |
9602b6a1 | 944 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 945 | "ltgr\t%2,%0" |
9381e3f1 WG |
946 | [(set_attr "op_type" "RRE") |
947 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 948 | |
07893d4f | 949 | (define_insn "*tstsi" |
ae156f85 | 950 | [(set (reg CC_REGNUM) |
d3632d41 | 951 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 952 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 953 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 954 | (match_dup 0))] |
ec24698e | 955 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 956 | "@ |
d40c829f | 957 | ltr\t%2,%0 |
fc0ea003 UW |
958 | icm\t%2,15,%S0 |
959 | icmy\t%2,15,%S0" | |
9381e3f1 | 960 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 961 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 962 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 963 | |
07893d4f | 964 | (define_insn "*tstsi_cconly" |
ae156f85 | 965 | [(set (reg CC_REGNUM) |
d3632d41 | 966 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 967 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 968 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
969 | "s390_match_ccmode(insn, CCSmode)" |
970 | "@ | |
d40c829f | 971 | ltr\t%0,%0 |
fc0ea003 UW |
972 | icm\t%2,15,%S0 |
973 | icmy\t%2,15,%S0" | |
9381e3f1 | 974 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 975 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 976 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 977 | |
08a5aaa2 AS |
978 | (define_insn "*tstdi_cconly_31" |
979 | [(set (reg CC_REGNUM) | |
980 | (compare (match_operand:DI 0 "register_operand" "d") | |
981 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 982 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
983 | "srda\t%0,0" |
984 | [(set_attr "op_type" "RS") | |
985 | (set_attr "atype" "reg")]) | |
986 | ||
43a09b63 | 987 | ; ltr, ltgr |
08a5aaa2 | 988 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 989 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
990 | (compare (match_operand:GPR 0 "register_operand" "d") |
991 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 992 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 993 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
994 | [(set_attr "op_type" "RR<E>") |
995 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 996 | |
c0220ea4 | 997 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 998 | |
f52c81dd | 999 | (define_insn "*tst<mode>CCT" |
ae156f85 | 1000 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1001 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
1002 | (match_operand:HQI 1 "const0_operand" ""))) | |
1003 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
1004 | (match_dup 0))] |
1005 | "s390_match_ccmode(insn, CCTmode)" | |
1006 | "@ | |
f52c81dd AS |
1007 | icm\t%2,<icm_lo>,%S0 |
1008 | icmy\t%2,<icm_lo>,%S0 | |
1009 | tml\t%0,<max_uint>" | |
9381e3f1 | 1010 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1011 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1012 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
1013 | |
1014 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 1015 | [(set (reg CC_REGNUM) |
d3632d41 | 1016 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 1017 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 1018 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
1019 | "s390_match_ccmode(insn, CCTmode)" |
1020 | "@ | |
fc0ea003 UW |
1021 | icm\t%2,3,%S0 |
1022 | icmy\t%2,3,%S0 | |
d40c829f | 1023 | tml\t%0,65535" |
9381e3f1 | 1024 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1025 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1026 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 1027 | |
3af97654 | 1028 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1029 | [(set (reg CC_REGNUM) |
d3632d41 | 1030 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1031 | (match_operand:QI 1 "const0_operand" "")))] |
1032 | "s390_match_ccmode(insn, CCTmode)" | |
1033 | "@ | |
fc0ea003 UW |
1034 | cli\t%S0,0 |
1035 | cliy\t%S0,0 | |
d40c829f | 1036 | tml\t%0,255" |
9381e3f1 | 1037 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1038 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1039 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1040 | |
f52c81dd | 1041 | (define_insn "*tst<mode>" |
ae156f85 | 1042 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1043 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1044 | (match_operand:HQI 1 "const0_operand" ""))) | |
1045 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1046 | (match_dup 0))] |
1047 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1048 | "@ |
f52c81dd AS |
1049 | icm\t%2,<icm_lo>,%S0 |
1050 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1051 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1052 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1053 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1054 | |
f52c81dd | 1055 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1056 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1057 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1058 | (match_operand:HQI 1 "const0_operand" ""))) | |
1059 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1060 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1061 | "@ |
f52c81dd AS |
1062 | icm\t%2,<icm_lo>,%S0 |
1063 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1064 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1065 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1066 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1067 | |
9db1d521 | 1068 | |
575f7c2b UW |
1069 | ; Compare (equality) instructions |
1070 | ||
1071 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1072 | [(set (reg CC_REGNUM) |
ec24698e | 1073 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1074 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1075 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1076 | "@ |
1077 | cgr\t%0,%1 | |
f4f41b4e | 1078 | cghi\t%0,%h1 |
ec24698e | 1079 | cgfi\t%0,%1 |
575f7c2b | 1080 | cg\t%0,%1 |
19b63d8e | 1081 | #" |
9381e3f1 WG |
1082 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1083 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1084 | |
1085 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1086 | [(set (reg CC_REGNUM) |
ec24698e UW |
1087 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1088 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1089 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1090 | "@ |
1091 | cr\t%0,%1 | |
f4f41b4e | 1092 | chi\t%0,%h1 |
ec24698e | 1093 | cfi\t%0,%1 |
575f7c2b UW |
1094 | c\t%0,%1 |
1095 | cy\t%0,%1 | |
19b63d8e | 1096 | #" |
9381e3f1 | 1097 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1098 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1099 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1100 | |
07893d4f | 1101 | ; Compare (signed) instructions |
4023fb28 | 1102 | |
07893d4f | 1103 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1104 | [(set (reg CC_REGNUM) |
963fc8d0 | 1105 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1106 | "d,T,b")) |
963fc8d0 | 1107 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1108 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1109 | "@ |
d40c829f | 1110 | cgfr\t%0,%1 |
963fc8d0 AK |
1111 | cgf\t%0,%1 |
1112 | cgfrl\t%0,%1" | |
1113 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1114 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1115 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1116 | |
9381e3f1 WG |
1117 | |
1118 | ||
07893d4f | 1119 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1120 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1121 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1122 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1123 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1124 | "@ |
d40c829f | 1125 | ch\t%0,%1 |
963fc8d0 AK |
1126 | chy\t%0,%1 |
1127 | chrl\t%0,%1" | |
1128 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1129 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea AK |
1130 | (set_attr "type" "*,*,larl") |
1131 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1132 | |
1133 | (define_insn "*cmphi_ccs_z10" | |
1134 | [(set (reg CC_REGNUM) | |
1135 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1136 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1137 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1138 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1139 | [(set_attr "op_type" "SIL") |
1140 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1141 | |
1142 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1143 | [(set (reg CC_REGNUM) | |
3e4be43f | 1144 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1145 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1146 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1147 | "@ | |
1148 | cgh\t%0,%1 | |
1149 | cghrl\t%0,%1" | |
1150 | [(set_attr "op_type" "RXY,RIL") | |
1151 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1152 | |
963fc8d0 | 1153 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1154 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1155 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1156 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1157 | "d,d,Q, d,d,d,d") | |
1158 | (match_operand:GPR 1 "general_operand" | |
1159 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1160 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1161 | "@ |
3298c037 AK |
1162 | c<g>r\t%0,%1 |
1163 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1164 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1165 | c<g>fi\t%0,%1 |
1166 | c<g>\t%0,%1 | |
963fc8d0 AK |
1167 | c<y>\t%0,%1 |
1168 | c<g>rl\t%0,%1" | |
1169 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1170 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 WG |
1171 | (set_attr "type" "*,*,*,*,*,*,larl") |
1172 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1173 | |
07893d4f UW |
1174 | |
1175 | ; Compare (unsigned) instructions | |
9db1d521 | 1176 | |
963fc8d0 AK |
1177 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1178 | [(set (reg CC_REGNUM) | |
1179 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1180 | "larl_operand" "X"))) | |
1181 | (match_operand:SI 0 "register_operand" "d")))] | |
1182 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1183 | "clhrl\t%0,%1" | |
1184 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1185 | (set_attr "type" "larl") |
1186 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1187 | |
1188 | ; clhrl, clghrl | |
1189 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1190 | [(set (reg CC_REGNUM) | |
1191 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1192 | "larl_operand" "X"))) | |
1193 | (match_operand:GPR 0 "register_operand" "d")))] | |
1194 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1195 | "cl<g>hrl\t%0,%1" | |
1196 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1197 | (set_attr "type" "larl") |
1198 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1199 | |
07893d4f | 1200 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1201 | [(set (reg CC_REGNUM) |
963fc8d0 | 1202 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1203 | "d,T,b")) |
1204 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1205 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1206 | "@ |
d40c829f | 1207 | clgfr\t%0,%1 |
963fc8d0 AK |
1208 | clgf\t%0,%1 |
1209 | clgfrl\t%0,%1" | |
1210 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1211 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1212 | (set_attr "type" "*,*,larl") |
1213 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1214 | |
07893d4f | 1215 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1216 | [(set (reg CC_REGNUM) |
963fc8d0 | 1217 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1218 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1219 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1220 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1221 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1222 | "@ |
d40c829f | 1223 | clgr\t%0,%1 |
ec24698e | 1224 | clgfi\t%0,%1 |
963fc8d0 AK |
1225 | clgrl\t%0,%1 |
1226 | clghsi\t%0,%x1 | |
575f7c2b | 1227 | clg\t%0,%1 |
e221ef54 | 1228 | # |
19b63d8e | 1229 | #" |
963fc8d0 AK |
1230 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1231 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1232 | (set_attr "type" "*,*,larl,*,*,*,*") |
1233 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1234 | |
07893d4f | 1235 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1236 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1237 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1238 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1239 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1240 | "@ |
d40c829f | 1241 | clr\t%0,%1 |
ec24698e | 1242 | clfi\t%0,%o1 |
963fc8d0 AK |
1243 | clrl\t%0,%1 |
1244 | clfhsi\t%0,%x1 | |
d40c829f | 1245 | cl\t%0,%1 |
575f7c2b | 1246 | cly\t%0,%1 |
e221ef54 | 1247 | # |
19b63d8e | 1248 | #" |
963fc8d0 | 1249 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1250 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 WG |
1251 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1252 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1253 | |
07893d4f | 1254 | (define_insn "*cmphi_ccu" |
ae156f85 | 1255 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1256 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1257 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1258 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1259 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1260 | "@ |
fc0ea003 UW |
1261 | clm\t%0,3,%S1 |
1262 | clmy\t%0,3,%S1 | |
963fc8d0 | 1263 | clhhsi\t%0,%1 |
e221ef54 | 1264 | # |
19b63d8e | 1265 | #" |
963fc8d0 | 1266 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1267 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1268 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1269 | |
1270 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1271 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1272 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1273 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1274 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1275 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1276 | "@ |
fc0ea003 UW |
1277 | clm\t%0,1,%S1 |
1278 | clmy\t%0,1,%S1 | |
1279 | cli\t%S0,%b1 | |
1280 | cliy\t%S0,%b1 | |
e221ef54 | 1281 | # |
19b63d8e | 1282 | #" |
9381e3f1 | 1283 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1284 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1285 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1286 | |
1287 | ||
19b63d8e UW |
1288 | ; Block compare (CLC) instruction patterns. |
1289 | ||
1290 | (define_insn "*clc" | |
ae156f85 | 1291 | [(set (reg CC_REGNUM) |
d4f52f0e | 1292 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1293 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1294 | (use (match_operand 2 "const_int_operand" "n"))] | |
1295 | "s390_match_ccmode (insn, CCUmode) | |
1296 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1297 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1298 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1299 | |
1300 | (define_split | |
ae156f85 | 1301 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1302 | (compare (match_operand 0 "memory_operand" "") |
1303 | (match_operand 1 "memory_operand" "")))] | |
1304 | "reload_completed | |
1305 | && s390_match_ccmode (insn, CCUmode) | |
1306 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1307 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1308 | [(parallel | |
1309 | [(set (match_dup 0) (match_dup 1)) | |
1310 | (use (match_dup 2))])] | |
1311 | { | |
1312 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1313 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1314 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1315 | ||
1316 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1317 | operands[0], operands[1]); | |
1318 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1319 | }) | |
1320 | ||
1321 | ||
609e7e80 | 1322 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1323 | |
e325aba2 AK |
1324 | |
1325 | ; load and test instructions turn SNaN into QNaN what is not | |
1326 | ; acceptable if the target will be used afterwards. On the other hand | |
1327 | ; they are quite convenient for implementing comparisons with 0.0. So | |
1328 | ; try to enable them via splitter if the value isn't needed anymore. | |
1329 | ||
609e7e80 | 1330 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1331 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1332 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1333 | (compare (match_operand:FP 0 "register_operand" "f") |
1334 | (match_operand:FP 1 "const0_operand" ""))) | |
1335 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1336 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1337 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1338 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1339 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1340 | |
e325aba2 AK |
1341 | (define_split |
1342 | [(set (match_operand 0 "cc_reg_operand") | |
1343 | (compare (match_operand:FP 1 "register_operand") | |
1344 | (match_operand:FP 2 "const0_operand")))] | |
1345 | "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])" | |
1346 | [(parallel | |
1347 | [(set (match_dup 0) (match_dup 3)) | |
1348 | (clobber (match_dup 1))])] | |
1349 | { | |
1350 | /* s390_match_ccmode requires the compare to have the same CC mode | |
1351 | as the CC destination register. */ | |
1352 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]), | |
1353 | operands[1], operands[2]); | |
1354 | }) | |
1355 | ||
1356 | ||
2de2b3f9 AK |
1357 | ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb |
1358 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb | |
f5905b37 | 1359 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1360 | [(set (reg CC_REGNUM) |
2de2b3f9 AK |
1361 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") |
1362 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
142cd70f | 1363 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1364 | "@ |
609e7e80 | 1365 | c<xde><bt>r\t%0,%1 |
77c585ca | 1366 | c<xde>b\t%0,%1 |
2de2b3f9 AK |
1367 | wfcdb\t%0,%1 |
1368 | wfcsb\t%0,%1" | |
1369 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1370 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1371 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
963fc8d0 AK |
1372 | |
1373 | ; Compare and Branch instructions | |
1374 | ||
1375 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1376 | ; The following instructions do a complementary access of their second |
1377 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1378 | (define_insn "*cmp_and_br_signed_<mode>" |
1379 | [(set (pc) | |
1380 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1381 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1382 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1383 | (label_ref (match_operand 3 "" "")) | |
1384 | (pc))) | |
1385 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1386 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1387 | { |
1388 | if (get_attr_length (insn) == 6) | |
1389 | return which_alternative ? | |
1390 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1391 | else | |
1392 | return which_alternative ? | |
1393 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1394 | } | |
1395 | [(set_attr "op_type" "RIE") | |
1396 | (set_attr "type" "branch") | |
e3cba5e5 | 1397 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1398 | (set (attr "length") |
1399 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1400 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1401 | ; 10 byte for cgr/jg | |
1402 | ||
1403 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1404 | ; The following instructions do a complementary access of their second |
1405 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1406 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1407 | [(set (pc) | |
1408 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1409 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1410 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1411 | (label_ref (match_operand 3 "" "")) | |
1412 | (pc))) | |
1413 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1414 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1415 | { |
1416 | if (get_attr_length (insn) == 6) | |
1417 | return which_alternative ? | |
1418 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1419 | else | |
1420 | return which_alternative ? | |
1421 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1422 | } | |
1423 | [(set_attr "op_type" "RIE") | |
1424 | (set_attr "type" "branch") | |
e3cba5e5 | 1425 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1426 | (set (attr "length") |
1427 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1428 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1429 | ; 10 byte for clgr/jg | |
1430 | ||
b0f86a7e AK |
1431 | ; And now the same two patterns as above but with a negated CC mask. |
1432 | ||
1433 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1434 | ; The following instructions do a complementary access of their second | |
1435 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1436 | (define_insn "*icmp_and_br_signed_<mode>" | |
1437 | [(set (pc) | |
1438 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1439 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1440 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1441 | (pc) | |
1442 | (label_ref (match_operand 3 "" "")))) | |
1443 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1444 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1445 | { |
1446 | if (get_attr_length (insn) == 6) | |
1447 | return which_alternative ? | |
1448 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1449 | else | |
1450 | return which_alternative ? | |
1451 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1452 | } | |
1453 | [(set_attr "op_type" "RIE") | |
1454 | (set_attr "type" "branch") | |
1455 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1456 | (set (attr "length") | |
1457 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1458 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1459 | ; 10 byte for cgr/jg | |
1460 | ||
1461 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1462 | ; The following instructions do a complementary access of their second | |
1463 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1464 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1465 | [(set (pc) | |
1466 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1467 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1468 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1469 | (pc) | |
1470 | (label_ref (match_operand 3 "" "")))) | |
1471 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1472 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1473 | { |
1474 | if (get_attr_length (insn) == 6) | |
1475 | return which_alternative ? | |
1476 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1477 | else | |
1478 | return which_alternative ? | |
1479 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1480 | } | |
1481 | [(set_attr "op_type" "RIE") | |
1482 | (set_attr "type" "branch") | |
1483 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1484 | (set (attr "length") | |
1485 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1486 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1487 | ; 10 byte for clgr/jg | |
1488 | ||
9db1d521 HP |
1489 | ;; |
1490 | ;;- Move instructions. | |
1491 | ;; | |
1492 | ||
1493 | ; | |
1494 | ; movti instruction pattern(s). | |
1495 | ; | |
1496 | ||
3cb9ee2f AK |
1497 | |
1498 | ; Separate out the register pair alternative since constraints (P) are | |
1499 | ; not able to deal with const_wide_int's. But predicates do. | |
1500 | (define_insn "*movti_bigconst" | |
1501 | [(set (match_operand:TI 0 "register_operand" "=d") | |
1502 | (match_operand:TI 1 "reload_const_wide_int_operand" ""))] | |
1503 | "TARGET_ZARCH" | |
1504 | "#") | |
1505 | ||
085261c8 AK |
1506 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1507 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1508 | (define_insn "movti" |
3cb9ee2f AK |
1509 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o") |
1510 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dT,d"))] | |
9602b6a1 | 1511 | "TARGET_ZARCH" |
4023fb28 | 1512 | "@ |
fc0ea003 UW |
1513 | lmg\t%0,%N0,%S1 |
1514 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1515 | vlr\t%v0,%v1 |
1516 | vzero\t%v0 | |
1517 | vone\t%v0 | |
1518 | vlvgp\t%v0,%1,%N1 | |
1519 | # | |
1520 | vl\t%v0,%1 | |
1521 | vst\t%v1,%0 | |
4023fb28 | 1522 | # |
19b63d8e | 1523 | #" |
085261c8 AK |
1524 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1525 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
285363a1 | 1526 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")]) |
4023fb28 UW |
1527 | |
1528 | (define_split | |
1529 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1530 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1531 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1532 | && !s_operand (operands[0], TImode) |
1533 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1534 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1535 | [(set (match_dup 2) (match_dup 4)) |
1536 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1537 | { |
dc65c307 UW |
1538 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1539 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1540 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1541 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1542 | }) | |
1543 | ||
1544 | (define_split | |
1545 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1546 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1547 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1548 | && !s_operand (operands[0], TImode) |
1549 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1550 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1551 | [(set (match_dup 2) (match_dup 4)) | |
1552 | (set (match_dup 3) (match_dup 5))] | |
1553 | { | |
1554 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1555 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1556 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1557 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1558 | }) | |
4023fb28 | 1559 | |
085261c8 AK |
1560 | ; Use part of the TImode target reg to perform the address |
1561 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1562 | ; this splitter is not necessary. | |
4023fb28 UW |
1563 | (define_split |
1564 | [(set (match_operand:TI 0 "register_operand" "") | |
1565 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1566 | "TARGET_ZARCH && reload_completed |
085261c8 | 1567 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1568 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1569 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1570 | { |
1571 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1572 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1573 | s390_load_address (addr, XEXP (operands[1], 0)); |
1574 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1575 | }) |
1576 | ||
833cd70a | 1577 | |
085261c8 AK |
1578 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1579 | ; For the higher order bits we do simply a DImode move while the | |
1580 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1581 | (define_split | |
1582 | [(set (match_operand:TI 0 "register_operand" "") | |
1583 | (match_operand:TI 1 "register_operand" ""))] | |
1584 | "TARGET_VX && reload_completed | |
1585 | && GENERAL_REG_P (operands[0]) | |
1586 | && VECTOR_REG_P (operands[1])" | |
1587 | [(set (match_dup 2) (match_dup 4)) | |
1588 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1589 | UNSPEC_VEC_EXTRACT))] | |
1590 | { | |
1591 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1592 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1593 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1594 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1595 | }) | |
1596 | ||
833cd70a AK |
1597 | ; |
1598 | ; Patterns used for secondary reloads | |
1599 | ; | |
1600 | ||
963fc8d0 AK |
1601 | ; z10 provides move instructions accepting larl memory operands. |
1602 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1603 | ; These patterns are also used for unaligned SI and DI accesses. | |
1604 | ||
085261c8 AK |
1605 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1606 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1607 | (match_operand:ALL 1 "register_operand" "=d") | |
1608 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1609 | "TARGET_Z10" |
1610 | { | |
1611 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1612 | DONE; | |
1613 | }) | |
1614 | ||
085261c8 AK |
1615 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1616 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1617 | (match_operand:ALL 1 "memory_operand" "") | |
1618 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1619 | "TARGET_Z10" |
1620 | { | |
1621 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1622 | DONE; | |
1623 | }) | |
1624 | ||
1625 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1626 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1627 | (match_operand:P 1 "larl_operand" "") | |
1628 | (match_operand:P 2 "register_operand" "=a")])] | |
1629 | "TARGET_Z10" | |
1630 | { | |
1631 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1632 | DONE; | |
1633 | }) | |
1634 | ||
833cd70a AK |
1635 | ; Handles loading a PLUS (load address) expression |
1636 | ||
1637 | (define_expand "reload<mode>_plus" | |
1638 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1639 | (match_operand:P 1 "s390_plus_operand" "") | |
1640 | (match_operand:P 2 "register_operand" "=&a")])] | |
1641 | "" | |
1642 | { | |
1643 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1644 | DONE; | |
1645 | }) | |
1646 | ||
085261c8 AK |
1647 | ; Not all the indirect memory access instructions support the full |
1648 | ; format (long disp + index + base). So whenever a move from/to such | |
1649 | ; an address is required and the instruction cannot deal with it we do | |
1650 | ; a load address into a scratch register first and use this as the new | |
1651 | ; base register. | |
1652 | ; This in particular is used for: | |
1653 | ; - non-offsetable memory accesses for multiword moves | |
1654 | ; - full vector reg moves with long displacements | |
833cd70a | 1655 | |
085261c8 | 1656 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1657 | [(parallel [(match_operand 0 "register_operand" "") |
1658 | (match_operand 1 "" "") | |
1659 | (match_operand:P 2 "register_operand" "=&a")])] | |
1660 | "" | |
1661 | { | |
1662 | gcc_assert (MEM_P (operands[1])); | |
1663 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1664 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1665 | emit_move_insn (operands[0], operands[1]); | |
1666 | DONE; | |
1667 | }) | |
1668 | ||
085261c8 | 1669 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1670 | [(parallel [(match_operand 0 "" "") |
1671 | (match_operand 1 "register_operand" "") | |
1672 | (match_operand:P 2 "register_operand" "=&a")])] | |
1673 | "" | |
dc65c307 | 1674 | { |
9c3c3dcc | 1675 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1676 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1677 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1678 | emit_move_insn (operands[0], operands[1]); | |
1679 | DONE; | |
1680 | }) | |
9db1d521 | 1681 | |
1f9e1fc6 AK |
1682 | (define_expand "reload<mode>_PIC_addr" |
1683 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1684 | (match_operand 1 "larl_operand" "") | |
1685 | (match_operand:P 2 "register_operand" "=a")])] | |
1686 | "" | |
1687 | { | |
0a2aaacc KG |
1688 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1689 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1690 | }) |
1691 | ||
9db1d521 HP |
1692 | ; |
1693 | ; movdi instruction pattern(s). | |
1694 | ; | |
1695 | ||
9db1d521 HP |
1696 | (define_expand "movdi" |
1697 | [(set (match_operand:DI 0 "general_operand" "") | |
1698 | (match_operand:DI 1 "general_operand" ""))] | |
1699 | "" | |
9db1d521 | 1700 | { |
fd3cd001 | 1701 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1702 | if (TARGET_64BIT |
1703 | && (SYMBOLIC_CONST (operands[1]) | |
1704 | || (GET_CODE (operands[1]) == PLUS | |
1705 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1706 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1707 | emit_symbolic_move (operands); |
10bbf137 | 1708 | }) |
9db1d521 | 1709 | |
4023fb28 UW |
1710 | (define_insn "*movdi_larl" |
1711 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1712 | (match_operand:DI 1 "larl_operand" "X"))] | |
1713 | "TARGET_64BIT | |
8e509cf9 | 1714 | && !FP_REG_P (operands[0])" |
d40c829f | 1715 | "larl\t%0,%1" |
4023fb28 | 1716 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1717 | (set_attr "type" "larl") |
1718 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1719 | |
3af8e996 | 1720 | (define_insn "*movdi_64" |
85dae55a | 1721 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1722 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R") |
85dae55a | 1723 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1724 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))] |
9602b6a1 | 1725 | "TARGET_ZARCH" |
85dae55a AK |
1726 | "@ |
1727 | lghi\t%0,%h1 | |
1728 | llihh\t%0,%i1 | |
1729 | llihl\t%0,%i1 | |
1730 | llilh\t%0,%i1 | |
1731 | llill\t%0,%i1 | |
1732 | lgfi\t%0,%1 | |
1733 | llihf\t%0,%k1 | |
1734 | llilf\t%0,%k1 | |
1735 | ldgr\t%0,%1 | |
1736 | lgdr\t%0,%1 | |
1737 | lay\t%0,%a1 | |
963fc8d0 | 1738 | lgrl\t%0,%1 |
85dae55a AK |
1739 | lgr\t%0,%1 |
1740 | lg\t%0,%1 | |
1741 | stg\t%1,%0 | |
1742 | ldr\t%0,%1 | |
1743 | ld\t%0,%1 | |
1744 | ldy\t%0,%1 | |
1745 | std\t%1,%0 | |
1746 | stdy\t%1,%0 | |
963fc8d0 AK |
1747 | stgrl\t%1,%0 |
1748 | mvghi\t%0,%1 | |
85dae55a AK |
1749 | # |
1750 | # | |
1751 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1752 | lam\t%0,%N0,%S1 |
1753 | vleig\t%v0,%h1,0 | |
1754 | vlr\t%v0,%v1 | |
1755 | vlvgg\t%v0,%1,0 | |
1756 | vlgvg\t%0,%v1,0 | |
1757 | vleg\t%v0,%1,0 | |
1758 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1759 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1760 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1761 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1762 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1763 | *,*,*,*,*,*,*") | |
3af8e996 | 1764 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1765 | z10,*,*,*,*,*,longdisp,*,longdisp, |
285363a1 | 1766 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
1767 | (set_attr "z10prop" "z10_fwd_A1, |
1768 | z10_fwd_E1, | |
1769 | z10_fwd_E1, | |
1770 | z10_fwd_E1, | |
1771 | z10_fwd_E1, | |
1772 | z10_fwd_A1, | |
1773 | z10_fwd_E1, | |
1774 | z10_fwd_E1, | |
1775 | *, | |
1776 | *, | |
1777 | z10_fwd_A1, | |
1778 | z10_fwd_A3, | |
1779 | z10_fr_E1, | |
1780 | z10_fwd_A3, | |
1781 | z10_rec, | |
1782 | *, | |
1783 | *, | |
1784 | *, | |
1785 | *, | |
1786 | *, | |
1787 | z10_rec, | |
1788 | z10_super, | |
1789 | *, | |
1790 | *, | |
1791 | *, | |
085261c8 | 1792 | *,*,*,*,*,*,*") |
9381e3f1 | 1793 | ]) |
c5aa1d12 UW |
1794 | |
1795 | (define_split | |
1796 | [(set (match_operand:DI 0 "register_operand" "") | |
1797 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1798 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1799 | [(set (match_dup 2) (match_dup 3)) |
1800 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1801 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1802 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1803 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1804 | ||
1805 | (define_split | |
1806 | [(set (match_operand:DI 0 "register_operand" "") | |
1807 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1808 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1809 | && dead_or_set_p (insn, operands[1])" |
1810 | [(set (match_dup 3) (match_dup 2)) | |
1811 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1812 | (set (match_dup 4) (match_dup 2))] | |
1813 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1814 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1815 | ||
1816 | (define_split | |
1817 | [(set (match_operand:DI 0 "register_operand" "") | |
1818 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1819 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1820 | && !dead_or_set_p (insn, operands[1])" |
1821 | [(set (match_dup 3) (match_dup 2)) | |
1822 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1823 | (set (match_dup 4) (match_dup 2)) | |
1824 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1825 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1826 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1827 | |
1828 | (define_insn "*movdi_31" | |
963fc8d0 | 1829 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1830 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1831 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1832 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1833 | "!TARGET_ZARCH" |
4023fb28 | 1834 | "@ |
fc0ea003 | 1835 | lm\t%0,%N0,%S1 |
c4d50129 | 1836 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1837 | stm\t%1,%N1,%S0 |
c4d50129 | 1838 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1839 | # |
1840 | # | |
d40c829f UW |
1841 | ldr\t%0,%1 |
1842 | ld\t%0,%1 | |
1843 | ldy\t%0,%1 | |
1844 | std\t%1,%0 | |
1845 | stdy\t%1,%0 | |
19b63d8e | 1846 | #" |
f2dc2f86 AK |
1847 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1848 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1849 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1850 | |
1851 | ; For a load from a symbol ref we can use one of the target registers | |
1852 | ; together with larl to load the address. | |
1853 | (define_split | |
1854 | [(set (match_operand:DI 0 "register_operand" "") | |
1855 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1856 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1857 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1858 | [(set (match_dup 2) (match_dup 3)) | |
1859 | (set (match_dup 0) (match_dup 1))] | |
1860 | { | |
1861 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1862 | operands[3] = XEXP (operands[1], 0); | |
1863 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1864 | }) | |
4023fb28 UW |
1865 | |
1866 | (define_split | |
1867 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1868 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1869 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1870 | && !s_operand (operands[0], DImode) |
1871 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1872 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1873 | [(set (match_dup 2) (match_dup 4)) |
1874 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1875 | { |
dc65c307 UW |
1876 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1877 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1878 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1879 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1880 | }) | |
1881 | ||
1882 | (define_split | |
1883 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1884 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1885 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1886 | && !s_operand (operands[0], DImode) |
1887 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1888 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1889 | [(set (match_dup 2) (match_dup 4)) | |
1890 | (set (match_dup 3) (match_dup 5))] | |
1891 | { | |
1892 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1893 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1894 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1895 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1896 | }) | |
9db1d521 | 1897 | |
4023fb28 UW |
1898 | (define_split |
1899 | [(set (match_operand:DI 0 "register_operand" "") | |
1900 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1901 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1902 | && !FP_REG_P (operands[0]) |
4023fb28 | 1903 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1904 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1905 | { |
1906 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1907 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1908 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1909 | }) |
1910 | ||
84817c5d UW |
1911 | (define_peephole2 |
1912 | [(set (match_operand:DI 0 "register_operand" "") | |
1913 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1914 | "TARGET_ZARCH |
84817c5d UW |
1915 | && !FP_REG_P (operands[0]) |
1916 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1917 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1918 | && get_pool_mode (operands[1]) == DImode | |
1919 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1920 | [(set (match_dup 0) (match_dup 2))] | |
1921 | "operands[2] = get_pool_constant (operands[1]);") | |
1922 | ||
7bdff56f UW |
1923 | (define_insn "*la_64" |
1924 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1925 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1926 | "TARGET_64BIT" |
1927 | "@ | |
1928 | la\t%0,%a1 | |
1929 | lay\t%0,%a1" | |
1930 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1931 | (set_attr "type" "la") |
3e4be43f | 1932 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1933 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1934 | |
1935 | (define_peephole2 | |
1936 | [(parallel | |
1937 | [(set (match_operand:DI 0 "register_operand" "") | |
1938 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1939 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1940 | "TARGET_64BIT |
e1d5ee28 | 1941 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1942 | [(set (match_dup 0) (match_dup 1))] |
1943 | "") | |
1944 | ||
1945 | (define_peephole2 | |
1946 | [(set (match_operand:DI 0 "register_operand" "") | |
1947 | (match_operand:DI 1 "register_operand" "")) | |
1948 | (parallel | |
1949 | [(set (match_dup 0) | |
1950 | (plus:DI (match_dup 0) | |
1951 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1952 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1953 | "TARGET_64BIT |
1954 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1955 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1956 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1957 | "") | |
1958 | ||
9db1d521 HP |
1959 | ; |
1960 | ; movsi instruction pattern(s). | |
1961 | ; | |
1962 | ||
9db1d521 HP |
1963 | (define_expand "movsi" |
1964 | [(set (match_operand:SI 0 "general_operand" "") | |
1965 | (match_operand:SI 1 "general_operand" ""))] | |
1966 | "" | |
9db1d521 | 1967 | { |
fd3cd001 | 1968 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1969 | if (!TARGET_64BIT |
1970 | && (SYMBOLIC_CONST (operands[1]) | |
1971 | || (GET_CODE (operands[1]) == PLUS | |
1972 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1973 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1974 | emit_symbolic_move (operands); |
10bbf137 | 1975 | }) |
9db1d521 | 1976 | |
9e8327e3 UW |
1977 | (define_insn "*movsi_larl" |
1978 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1979 | (match_operand:SI 1 "larl_operand" "X"))] | |
1980 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1981 | && !FP_REG_P (operands[0])" | |
1982 | "larl\t%0,%1" | |
1983 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1984 | (set_attr "type" "larl") |
729e750f | 1985 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1986 | |
f19a9af7 | 1987 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1988 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 1989 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 1990 | (match_operand:SI 1 "general_operand" |
3e4be43f | 1991 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 1992 | "TARGET_ZARCH" |
9db1d521 | 1993 | "@ |
f19a9af7 AK |
1994 | lhi\t%0,%h1 |
1995 | llilh\t%0,%i1 | |
1996 | llill\t%0,%i1 | |
ec24698e | 1997 | iilf\t%0,%o1 |
f19a9af7 | 1998 | lay\t%0,%a1 |
963fc8d0 | 1999 | lrl\t%0,%1 |
d40c829f UW |
2000 | lr\t%0,%1 |
2001 | l\t%0,%1 | |
2002 | ly\t%0,%1 | |
2003 | st\t%1,%0 | |
2004 | sty\t%1,%0 | |
ae1c6198 | 2005 | ldr\t%0,%1 |
d40c829f | 2006 | ler\t%0,%1 |
085261c8 | 2007 | lde\t%0,%1 |
d40c829f UW |
2008 | le\t%0,%1 |
2009 | ley\t%0,%1 | |
2010 | ste\t%1,%0 | |
2011 | stey\t%1,%0 | |
c5aa1d12 UW |
2012 | ear\t%0,%1 |
2013 | sar\t%0,%1 | |
2014 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
2015 | strl\t%1,%0 |
2016 | mvhi\t%0,%1 | |
085261c8 AK |
2017 | lam\t%0,%0,%S1 |
2018 | vleif\t%v0,%h1,0 | |
2019 | vlr\t%v0,%v1 | |
2020 | vlvgf\t%v0,%1,0 | |
2021 | vlgvf\t%0,%v1,0 | |
2022 | vlef\t%v0,%1,0 | |
2023 | vstef\t%v1,%0,0" | |
963fc8d0 | 2024 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 2025 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
2026 | (set_attr "type" "*, |
2027 | *, | |
2028 | *, | |
2029 | *, | |
2030 | la, | |
2031 | larl, | |
2032 | lr, | |
2033 | load, | |
2034 | load, | |
2035 | store, | |
2036 | store, | |
2037 | floadsf, | |
2038 | floadsf, | |
2039 | floadsf, | |
085261c8 AK |
2040 | floadsf, |
2041 | floadsf, | |
9381e3f1 WG |
2042 | fstoresf, |
2043 | fstoresf, | |
2044 | *, | |
2045 | *, | |
2046 | *, | |
2047 | larl, | |
2048 | *, | |
085261c8 | 2049 | *,*,*,*,*,*,*") |
963fc8d0 | 2050 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2051 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2052 | (set_attr "z10prop" "z10_fwd_A1, |
2053 | z10_fwd_E1, | |
2054 | z10_fwd_E1, | |
2055 | z10_fwd_A1, | |
2056 | z10_fwd_A1, | |
2057 | z10_fwd_A3, | |
2058 | z10_fr_E1, | |
2059 | z10_fwd_A3, | |
2060 | z10_fwd_A3, | |
729e750f | 2061 | z10_rec, |
9381e3f1 WG |
2062 | z10_rec, |
2063 | *, | |
2064 | *, | |
2065 | *, | |
2066 | *, | |
2067 | *, | |
085261c8 AK |
2068 | *, |
2069 | *, | |
9381e3f1 WG |
2070 | z10_super_E1, |
2071 | z10_super, | |
2072 | *, | |
2073 | z10_rec, | |
2074 | z10_super, | |
085261c8 | 2075 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
2076 | |
2077 | (define_insn "*movsi_esa" | |
085261c8 AK |
2078 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2079 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2080 | "!TARGET_ZARCH" |
2081 | "@ | |
2082 | lhi\t%0,%h1 | |
2083 | lr\t%0,%1 | |
2084 | l\t%0,%1 | |
2085 | st\t%1,%0 | |
ae1c6198 | 2086 | ldr\t%0,%1 |
f19a9af7 | 2087 | ler\t%0,%1 |
085261c8 | 2088 | lde\t%0,%1 |
f19a9af7 AK |
2089 | le\t%0,%1 |
2090 | ste\t%1,%0 | |
c5aa1d12 UW |
2091 | ear\t%0,%1 |
2092 | sar\t%0,%1 | |
2093 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2094 | lam\t%0,%0,%S1" |
ae1c6198 | 2095 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2096 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2097 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2098 | z10_super,*,*") | |
285363a1 | 2099 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2100 | ]) |
9db1d521 | 2101 | |
84817c5d UW |
2102 | (define_peephole2 |
2103 | [(set (match_operand:SI 0 "register_operand" "") | |
2104 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2105 | "!FP_REG_P (operands[0]) | |
2106 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2107 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2108 | && get_pool_mode (operands[1]) == SImode | |
2109 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2110 | [(set (match_dup 0) (match_dup 2))] | |
2111 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2112 | |
7bdff56f UW |
2113 | (define_insn "*la_31" |
2114 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2115 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2116 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2117 | "@ | |
2118 | la\t%0,%a1 | |
2119 | lay\t%0,%a1" | |
2120 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2121 | (set_attr "type" "la") |
3e4be43f | 2122 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2123 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2124 | |
2125 | (define_peephole2 | |
2126 | [(parallel | |
2127 | [(set (match_operand:SI 0 "register_operand" "") | |
2128 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2129 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2130 | "!TARGET_64BIT |
e1d5ee28 | 2131 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2132 | [(set (match_dup 0) (match_dup 1))] |
2133 | "") | |
2134 | ||
2135 | (define_peephole2 | |
2136 | [(set (match_operand:SI 0 "register_operand" "") | |
2137 | (match_operand:SI 1 "register_operand" "")) | |
2138 | (parallel | |
2139 | [(set (match_dup 0) | |
2140 | (plus:SI (match_dup 0) | |
2141 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2142 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2143 | "!TARGET_64BIT |
2144 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2145 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2146 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2147 | "") | |
2148 | ||
2149 | (define_insn "*la_31_and" | |
2150 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2151 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2152 | (const_int 2147483647)))] |
2153 | "!TARGET_64BIT" | |
2154 | "@ | |
2155 | la\t%0,%a1 | |
2156 | lay\t%0,%a1" | |
2157 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2158 | (set_attr "type" "la") |
3e4be43f | 2159 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2160 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2161 | |
2162 | (define_insn_and_split "*la_31_and_cc" | |
2163 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2164 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2165 | (const_int 2147483647))) | |
ae156f85 | 2166 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2167 | "!TARGET_64BIT" |
2168 | "#" | |
2169 | "&& reload_completed" | |
2170 | [(set (match_dup 0) | |
2171 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2172 | "" | |
2173 | [(set_attr "op_type" "RX") | |
2174 | (set_attr "type" "la")]) | |
2175 | ||
2176 | (define_insn "force_la_31" | |
2177 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2178 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2179 | (use (const_int 0))] |
2180 | "!TARGET_64BIT" | |
2181 | "@ | |
2182 | la\t%0,%a1 | |
2183 | lay\t%0,%a1" | |
2184 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2185 | (set_attr "type" "la") |
3e4be43f | 2186 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2187 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2188 | |
9db1d521 HP |
2189 | ; |
2190 | ; movhi instruction pattern(s). | |
2191 | ; | |
2192 | ||
02ed3c5e UW |
2193 | (define_expand "movhi" |
2194 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2195 | (match_operand:HI 1 "general_operand" ""))] | |
2196 | "" | |
2197 | { | |
2f7e5a0d | 2198 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2199 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2200 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2201 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2202 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2203 | { |
2204 | rtx tmp = gen_reg_rtx (SImode); | |
2205 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2206 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2207 | operands[1] = gen_lowpart (HImode, tmp); |
2208 | } | |
2209 | }) | |
2210 | ||
2211 | (define_insn "*movhi" | |
3e4be43f UW |
2212 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2213 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2214 | "" |
2215 | "@ | |
d40c829f UW |
2216 | lr\t%0,%1 |
2217 | lhi\t%0,%h1 | |
2218 | lh\t%0,%1 | |
2219 | lhy\t%0,%1 | |
963fc8d0 | 2220 | lhrl\t%0,%1 |
d40c829f UW |
2221 | sth\t%1,%0 |
2222 | sthy\t%1,%0 | |
963fc8d0 | 2223 | sthrl\t%1,%0 |
085261c8 AK |
2224 | mvhhi\t%0,%1 |
2225 | vleih\t%v0,%h1,0 | |
2226 | vlr\t%v0,%v1 | |
2227 | vlvgh\t%v0,%1,0 | |
2228 | vlgvh\t%0,%v1,0 | |
2229 | vleh\t%v0,%1,0 | |
2230 | vsteh\t%v1,%0,0" | |
2231 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2232 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2233 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2234 | (set_attr "z10prop" "z10_fr_E1, |
2235 | z10_fwd_A1, | |
2236 | z10_super_E1, | |
2237 | z10_super_E1, | |
2238 | z10_super_E1, | |
729e750f | 2239 | z10_rec, |
9381e3f1 WG |
2240 | z10_rec, |
2241 | z10_rec, | |
085261c8 | 2242 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2243 | |
84817c5d UW |
2244 | (define_peephole2 |
2245 | [(set (match_operand:HI 0 "register_operand" "") | |
2246 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2247 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2248 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2249 | && get_pool_mode (operands[1]) == HImode | |
2250 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2251 | [(set (match_dup 0) (match_dup 2))] | |
2252 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2253 | |
9db1d521 HP |
2254 | ; |
2255 | ; movqi instruction pattern(s). | |
2256 | ; | |
2257 | ||
02ed3c5e UW |
2258 | (define_expand "movqi" |
2259 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2260 | (match_operand:QI 1 "general_operand" ""))] | |
2261 | "" | |
2262 | { | |
c19ec8f9 | 2263 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2264 | is just as fast as a QImode load. */ |
b3a13419 | 2265 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2266 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2267 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2268 | { |
9602b6a1 AK |
2269 | rtx tmp = gen_reg_rtx (DImode); |
2270 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2271 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2272 | operands[1] = gen_lowpart (QImode, tmp); |
2273 | } | |
2274 | }) | |
4023fb28 | 2275 | |
02ed3c5e | 2276 | (define_insn "*movqi" |
3e4be43f UW |
2277 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2278 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2279 | "" |
2280 | "@ | |
d40c829f UW |
2281 | lr\t%0,%1 |
2282 | lhi\t%0,%b1 | |
2283 | ic\t%0,%1 | |
2284 | icy\t%0,%1 | |
2285 | stc\t%1,%0 | |
2286 | stcy\t%1,%0 | |
fc0ea003 | 2287 | mvi\t%S0,%b1 |
0a88561f | 2288 | mviy\t%S0,%b1 |
085261c8 AK |
2289 | # |
2290 | vleib\t%v0,%b1,0 | |
2291 | vlr\t%v0,%v1 | |
2292 | vlvgb\t%v0,%1,0 | |
2293 | vlgvb\t%0,%v1,0 | |
2294 | vleb\t%v0,%1,0 | |
2295 | vsteb\t%v1,%0,0" | |
2296 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2297 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2298 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2299 | (set_attr "z10prop" "z10_fr_E1, |
2300 | z10_fwd_A1, | |
2301 | z10_super_E1, | |
2302 | z10_super_E1, | |
729e750f | 2303 | z10_rec, |
9381e3f1 WG |
2304 | z10_rec, |
2305 | z10_super, | |
0a88561f | 2306 | z10_super, |
085261c8 | 2307 | *,*,*,*,*,*,*")]) |
9db1d521 | 2308 | |
84817c5d UW |
2309 | (define_peephole2 |
2310 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2311 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2312 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2313 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2314 | && get_pool_mode (operands[1]) == QImode | |
2315 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2316 | [(set (match_dup 0) (match_dup 2))] | |
2317 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2318 | |
9db1d521 | 2319 | ; |
05b9aaaa | 2320 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2321 | ; |
2322 | ||
2323 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2324 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2325 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2326 | "" |
d3632d41 | 2327 | "@ |
d40c829f UW |
2328 | ic\t%0,%1 |
2329 | icy\t%0,%1" | |
9381e3f1 | 2330 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2331 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2332 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2333 | |
2334 | ; | |
2335 | ; movstricthi instruction pattern(s). | |
2336 | ; | |
2337 | ||
2338 | (define_insn "*movstricthi" | |
d3632d41 | 2339 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2340 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2341 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2342 | "" |
d3632d41 | 2343 | "@ |
fc0ea003 UW |
2344 | icm\t%0,3,%S1 |
2345 | icmy\t%0,3,%S1" | |
9381e3f1 | 2346 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2347 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2348 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2349 | |
2350 | ; | |
2351 | ; movstrictsi instruction pattern(s). | |
2352 | ; | |
2353 | ||
05b9aaaa | 2354 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2355 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2356 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2357 | "TARGET_ZARCH" |
9db1d521 | 2358 | "@ |
d40c829f UW |
2359 | lr\t%0,%1 |
2360 | l\t%0,%1 | |
c5aa1d12 UW |
2361 | ly\t%0,%1 |
2362 | ear\t%0,%1" | |
2363 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2364 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2365 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2366 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2367 | |
f61a2c7d | 2368 | ; |
609e7e80 | 2369 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2370 | ; |
2371 | ||
609e7e80 AK |
2372 | (define_expand "mov<mode>" |
2373 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2374 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2375 | "" |
2376 | "") | |
2377 | ||
609e7e80 | 2378 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2379 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2380 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2381 | "TARGET_ZARCH" |
f61a2c7d | 2382 | "@ |
65b1d8ea | 2383 | lzxr\t%0 |
f61a2c7d AK |
2384 | lxr\t%0,%1 |
2385 | # | |
2386 | # | |
2387 | lmg\t%0,%N0,%S1 | |
2388 | stmg\t%1,%N1,%S0 | |
2389 | # | |
f61a2c7d | 2390 | #" |
65b1d8ea AK |
2391 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2392 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2393 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2394 | |
609e7e80 | 2395 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2396 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2397 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2398 | "!TARGET_ZARCH" |
f61a2c7d | 2399 | "@ |
65b1d8ea | 2400 | lzxr\t%0 |
f61a2c7d AK |
2401 | lxr\t%0,%1 |
2402 | # | |
f61a2c7d | 2403 | #" |
65b1d8ea AK |
2404 | [(set_attr "op_type" "RRE,RRE,*,*") |
2405 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2406 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2407 | |
2408 | ; TFmode in GPRs splitters | |
2409 | ||
2410 | (define_split | |
609e7e80 AK |
2411 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2412 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2413 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2414 | && !s_operand (operands[0], <MODE>mode) |
2415 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2416 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2417 | [(set (match_dup 2) (match_dup 4)) |
2418 | (set (match_dup 3) (match_dup 5))] | |
2419 | { | |
609e7e80 AK |
2420 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2421 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2422 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2423 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2424 | }) |
2425 | ||
2426 | (define_split | |
609e7e80 AK |
2427 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2428 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2429 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2430 | && !s_operand (operands[0], <MODE>mode) |
2431 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2432 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2433 | [(set (match_dup 2) (match_dup 4)) |
2434 | (set (match_dup 3) (match_dup 5))] | |
2435 | { | |
609e7e80 AK |
2436 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2437 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2438 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2439 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2440 | }) |
2441 | ||
2442 | (define_split | |
609e7e80 AK |
2443 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2444 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2445 | "TARGET_ZARCH && reload_completed |
085261c8 | 2446 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2447 | && !s_operand (operands[1], VOIDmode)" |
2448 | [(set (match_dup 0) (match_dup 1))] | |
2449 | { | |
609e7e80 | 2450 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2451 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2452 | s390_load_address (addr, XEXP (operands[1], 0)); |
2453 | operands[1] = replace_equiv_address (operands[1], addr); | |
2454 | }) | |
2455 | ||
7b6baae1 | 2456 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2457 | |
2458 | (define_split | |
609e7e80 AK |
2459 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2460 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2461 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2462 | && FP_REG_P (operands[0])" |
2463 | [(set (match_dup 2) (match_dup 4)) | |
2464 | (set (match_dup 3) (match_dup 5))] | |
2465 | { | |
609e7e80 AK |
2466 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2467 | <MODE>mode, 0); | |
2468 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2469 | <MODE>mode, 8); | |
2470 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2471 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2472 | }) |
2473 | ||
2474 | (define_split | |
609e7e80 AK |
2475 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2476 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2477 | "reload_completed && offsettable_memref_p (operands[0]) |
2478 | && FP_REG_P (operands[1])" | |
2479 | [(set (match_dup 2) (match_dup 4)) | |
2480 | (set (match_dup 3) (match_dup 5))] | |
2481 | { | |
609e7e80 AK |
2482 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2483 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2484 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2485 | <MODE>mode, 0); | |
2486 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2487 | <MODE>mode, 8); | |
f61a2c7d AK |
2488 | }) |
2489 | ||
9db1d521 | 2490 | ; |
609e7e80 | 2491 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2492 | ; |
2493 | ||
609e7e80 AK |
2494 | (define_expand "mov<mode>" |
2495 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2496 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2497 | "" |
13c025c1 | 2498 | "") |
9db1d521 | 2499 | |
609e7e80 AK |
2500 | (define_insn "*mov<mode>_64dfp" |
2501 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2502 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2503 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2504 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2505 | "TARGET_DFP" |
85dae55a | 2506 | "@ |
65b1d8ea | 2507 | lzdr\t%0 |
85dae55a AK |
2508 | ldr\t%0,%1 |
2509 | ldgr\t%0,%1 | |
2510 | lgdr\t%0,%1 | |
2511 | ld\t%0,%1 | |
2512 | ldy\t%0,%1 | |
2513 | std\t%1,%0 | |
2514 | stdy\t%1,%0 | |
45e5214c | 2515 | lghi\t%0,0 |
85dae55a | 2516 | lgr\t%0,%1 |
085261c8 | 2517 | lgrl\t%0,%1 |
85dae55a | 2518 | lg\t%0,%1 |
085261c8 AK |
2519 | stgrl\t%1,%0 |
2520 | stg\t%1,%0 | |
2521 | vlr\t%v0,%v1 | |
590961cf | 2522 | vleig\t%v0,0,0 |
085261c8 AK |
2523 | vlvgg\t%v0,%1,0 |
2524 | vlgvg\t%0,%v1,0 | |
2525 | vleg\t%0,%1,0 | |
2526 | vsteg\t%1,%0,0" | |
590961cf | 2527 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2528 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2529 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2530 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
2531 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")]) | |
85dae55a | 2532 | |
609e7e80 | 2533 | (define_insn "*mov<mode>_64" |
590961cf AK |
2534 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2535 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2536 | "TARGET_ZARCH" |
9db1d521 | 2537 | "@ |
65b1d8ea | 2538 | lzdr\t%0 |
d40c829f UW |
2539 | ldr\t%0,%1 |
2540 | ld\t%0,%1 | |
2541 | ldy\t%0,%1 | |
2542 | std\t%1,%0 | |
2543 | stdy\t%1,%0 | |
45e5214c | 2544 | lghi\t%0,0 |
d40c829f | 2545 | lgr\t%0,%1 |
085261c8 | 2546 | lgrl\t%0,%1 |
d40c829f | 2547 | lg\t%0,%1 |
085261c8 | 2548 | stgrl\t%1,%0 |
590961cf AK |
2549 | stg\t%1,%0" |
2550 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2551 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2552 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2553 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2554 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")]) | |
609e7e80 AK |
2555 | |
2556 | (define_insn "*mov<mode>_31" | |
2557 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2558 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2559 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2560 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2561 | "!TARGET_ZARCH" |
9db1d521 | 2562 | "@ |
65b1d8ea | 2563 | lzdr\t%0 |
d40c829f UW |
2564 | ldr\t%0,%1 |
2565 | ld\t%0,%1 | |
2566 | ldy\t%0,%1 | |
2567 | std\t%1,%0 | |
2568 | stdy\t%1,%0 | |
fc0ea003 | 2569 | lm\t%0,%N0,%S1 |
c4d50129 | 2570 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2571 | stm\t%1,%N1,%S0 |
c4d50129 | 2572 | stmy\t%1,%N1,%S0 |
4023fb28 | 2573 | # |
19b63d8e | 2574 | #" |
65b1d8ea AK |
2575 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2576 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2577 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2578 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2579 | |
2580 | (define_split | |
609e7e80 AK |
2581 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2582 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2583 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2584 | && !s_operand (operands[0], <MODE>mode) |
2585 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2586 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2587 | [(set (match_dup 2) (match_dup 4)) |
2588 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2589 | { |
609e7e80 AK |
2590 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2591 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2592 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2593 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2594 | }) |
2595 | ||
2596 | (define_split | |
609e7e80 AK |
2597 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2598 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2599 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2600 | && !s_operand (operands[0], <MODE>mode) |
2601 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2602 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2603 | [(set (match_dup 2) (match_dup 4)) |
2604 | (set (match_dup 3) (match_dup 5))] | |
2605 | { | |
609e7e80 AK |
2606 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2607 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2608 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2609 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2610 | }) |
9db1d521 | 2611 | |
4023fb28 | 2612 | (define_split |
609e7e80 AK |
2613 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2614 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2615 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2616 | && !FP_REG_P (operands[0]) |
4023fb28 | 2617 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2618 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2619 | { |
609e7e80 | 2620 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2621 | s390_load_address (addr, XEXP (operands[1], 0)); |
2622 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2623 | }) |
2624 | ||
9db1d521 | 2625 | ; |
609e7e80 | 2626 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2627 | ; |
2628 | ||
609e7e80 AK |
2629 | (define_insn "mov<mode>" |
2630 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2631 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2632 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2633 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2634 | "" |
9db1d521 | 2635 | "@ |
65b1d8ea | 2636 | lzer\t%0 |
ae1c6198 | 2637 | ldr\t%0,%1 |
d40c829f | 2638 | ler\t%0,%1 |
085261c8 | 2639 | lde\t%0,%1 |
d40c829f UW |
2640 | le\t%0,%1 |
2641 | ley\t%0,%1 | |
2642 | ste\t%1,%0 | |
2643 | stey\t%1,%0 | |
45e5214c | 2644 | lhi\t%0,0 |
d40c829f | 2645 | lr\t%0,%1 |
085261c8 | 2646 | lrl\t%0,%1 |
d40c829f UW |
2647 | l\t%0,%1 |
2648 | ly\t%0,%1 | |
085261c8 | 2649 | strl\t%1,%0 |
d40c829f | 2650 | st\t%1,%0 |
085261c8 AK |
2651 | sty\t%1,%0 |
2652 | vlr\t%v0,%v1 | |
298f4647 | 2653 | vleif\t%v0,0,0 |
085261c8 AK |
2654 | vlvgf\t%v0,%1,0 |
2655 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2656 | vlef\t%0,%1,0 |
2657 | vstef\t%1,%0,0" | |
ae1c6198 | 2658 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2659 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2660 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2661 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
285363a1 | 2662 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")]) |
4023fb28 | 2663 | |
9dc62c00 AK |
2664 | ; |
2665 | ; movcc instruction pattern | |
2666 | ; | |
2667 | ||
2668 | (define_insn "movcc" | |
2669 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2670 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2671 | "" |
2672 | "@ | |
2673 | lr\t%0,%1 | |
2674 | tmh\t%1,12288 | |
2675 | ipm\t%0 | |
a71f0749 DV |
2676 | l\t%0,%1 |
2677 | ly\t%0,%1 | |
2678 | st\t%1,%0 | |
2679 | sty\t%1,%0" | |
8dd3b235 | 2680 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2681 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2682 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2683 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2684 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2685 | |
19b63d8e UW |
2686 | ; |
2687 | ; Block move (MVC) patterns. | |
2688 | ; | |
2689 | ||
2690 | (define_insn "*mvc" | |
2691 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2692 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2693 | (use (match_operand 2 "const_int_operand" "n"))] | |
2694 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2695 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2696 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2697 | |
0a88561f AK |
2698 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2699 | ; order to have it implemented with mvc. | |
2700 | ||
2701 | (define_split | |
2702 | [(set (match_operand:QI 0 "memory_operand" "") | |
2703 | (match_operand:QI 1 "memory_operand" ""))] | |
2704 | "reload_completed" | |
2705 | [(parallel | |
2706 | [(set (match_dup 0) (match_dup 1)) | |
2707 | (use (const_int 1))])] | |
2708 | { | |
2709 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2710 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2711 | }) | |
2712 | ||
2713 | ||
19b63d8e UW |
2714 | (define_peephole2 |
2715 | [(parallel | |
2716 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2717 | (match_operand:BLK 1 "memory_operand" "")) | |
2718 | (use (match_operand 2 "const_int_operand" ""))]) | |
2719 | (parallel | |
2720 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2721 | (match_operand:BLK 4 "memory_operand" "")) | |
2722 | (use (match_operand 5 "const_int_operand" ""))])] | |
f9dcf14a AK |
2723 | "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) |
2724 | || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) | |
2725 | && s390_offset_p (operands[0], operands[3], operands[2]) | |
19b63d8e | 2726 | && s390_offset_p (operands[1], operands[4], operands[2]) |
9381e3f1 | 2727 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2728 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2729 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2730 | [(parallel | |
2731 | [(set (match_dup 6) (match_dup 7)) | |
2732 | (use (match_dup 8))])] | |
2733 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2734 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2735 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2736 | ||
f9dcf14a AK |
2737 | (define_peephole2 |
2738 | [(parallel | |
2739 | [(set (match_operand:BLK 0 "plus16_Q_operand" "") | |
2740 | (match_operand:BLK 1 "plus16_Q_operand" "")) | |
2741 | (use (match_operand 2 "const_int_operand" ""))])] | |
2742 | "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" | |
2743 | [(parallel | |
2744 | [(set (match_dup 0) (match_dup 1)) | |
2745 | (use (const_int 16))]) | |
2746 | (parallel | |
2747 | [(set (match_dup 3) (match_dup 4)) | |
2748 | (use (match_dup 5))])] | |
2749 | "operands[3] = change_address (operands[0], VOIDmode, | |
2750 | plus_constant (Pmode, XEXP (operands[0], 0), 16)); | |
2751 | operands[4] = change_address (operands[1], VOIDmode, | |
2752 | plus_constant (Pmode, XEXP (operands[1], 0), 16)); | |
2753 | operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") | |
2754 | ||
19b63d8e | 2755 | |
9db1d521 HP |
2756 | ; |
2757 | ; load_multiple pattern(s). | |
2758 | ; | |
22ea6b4f UW |
2759 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2760 | ; we currently support load_multiple/store_multiple only after reload. | |
2761 | ; | |
9db1d521 HP |
2762 | |
2763 | (define_expand "load_multiple" | |
2764 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2765 | (match_operand 1 "" "")) | |
2766 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2767 | "reload_completed" |
9db1d521 | 2768 | { |
ef4bddc2 | 2769 | machine_mode mode; |
9db1d521 HP |
2770 | int regno; |
2771 | int count; | |
2772 | rtx from; | |
4023fb28 | 2773 | int i, off; |
9db1d521 HP |
2774 | |
2775 | /* Support only loading a constant number of fixed-point registers from | |
2776 | memory and only bother with this if more than two */ | |
2777 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2778 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2779 | || INTVAL (operands[2]) > 16 |
2780 | || GET_CODE (operands[1]) != MEM | |
2781 | || GET_CODE (operands[0]) != REG | |
2782 | || REGNO (operands[0]) >= 16) | |
2783 | FAIL; | |
2784 | ||
2785 | count = INTVAL (operands[2]); | |
2786 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2787 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2788 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2789 | FAIL; |
9db1d521 HP |
2790 | |
2791 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2792 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2793 | { |
2794 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2795 | { | |
2796 | from = XEXP (operands[1], 0); | |
2797 | off = 0; | |
2798 | } | |
2799 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2800 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2801 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2802 | { | |
2803 | from = XEXP (XEXP (operands[1], 0), 0); | |
2804 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2805 | } | |
2806 | else | |
2807 | FAIL; | |
4023fb28 UW |
2808 | } |
2809 | else | |
2810 | { | |
2811 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2812 | off = 0; | |
2813 | } | |
9db1d521 HP |
2814 | |
2815 | for (i = 0; i < count; i++) | |
2816 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2817 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2818 | change_address (operands[1], mode, |
0a81f074 RS |
2819 | plus_constant (Pmode, from, |
2820 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2821 | }) |
9db1d521 HP |
2822 | |
2823 | (define_insn "*load_multiple_di" | |
2824 | [(match_parallel 0 "load_multiple_operation" | |
2825 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2826 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2827 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2828 | { |
2829 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2830 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2831 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2832 | } |
d3632d41 | 2833 | [(set_attr "op_type" "RSY") |
4023fb28 | 2834 | (set_attr "type" "lm")]) |
9db1d521 HP |
2835 | |
2836 | (define_insn "*load_multiple_si" | |
2837 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2838 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2839 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2840 | "reload_completed" |
9db1d521 HP |
2841 | { |
2842 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2843 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2844 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2845 | } |
d3632d41 | 2846 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2847 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2848 | (set_attr "type" "lm")]) |
9db1d521 HP |
2849 | |
2850 | ; | |
c7453384 | 2851 | ; store multiple pattern(s). |
9db1d521 HP |
2852 | ; |
2853 | ||
2854 | (define_expand "store_multiple" | |
2855 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2856 | (match_operand 1 "" "")) | |
2857 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2858 | "reload_completed" |
9db1d521 | 2859 | { |
ef4bddc2 | 2860 | machine_mode mode; |
9db1d521 HP |
2861 | int regno; |
2862 | int count; | |
2863 | rtx to; | |
4023fb28 | 2864 | int i, off; |
9db1d521 HP |
2865 | |
2866 | /* Support only storing a constant number of fixed-point registers to | |
2867 | memory and only bother with this if more than two. */ | |
2868 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2869 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2870 | || INTVAL (operands[2]) > 16 |
2871 | || GET_CODE (operands[0]) != MEM | |
2872 | || GET_CODE (operands[1]) != REG | |
2873 | || REGNO (operands[1]) >= 16) | |
2874 | FAIL; | |
2875 | ||
2876 | count = INTVAL (operands[2]); | |
2877 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2878 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2879 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2880 | FAIL; |
9db1d521 HP |
2881 | |
2882 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2883 | |
b3a13419 | 2884 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2885 | { |
2886 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2887 | { | |
2888 | to = XEXP (operands[0], 0); | |
2889 | off = 0; | |
2890 | } | |
2891 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2892 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2893 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2894 | { | |
2895 | to = XEXP (XEXP (operands[0], 0), 0); | |
2896 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2897 | } | |
2898 | else | |
2899 | FAIL; | |
4023fb28 | 2900 | } |
c7453384 | 2901 | else |
4023fb28 UW |
2902 | { |
2903 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2904 | off = 0; | |
2905 | } | |
9db1d521 HP |
2906 | |
2907 | for (i = 0; i < count; i++) | |
2908 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2909 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2910 | plus_constant (Pmode, to, |
2911 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2912 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2913 | }) |
9db1d521 HP |
2914 | |
2915 | (define_insn "*store_multiple_di" | |
2916 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2917 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2918 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2919 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2920 | { |
2921 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2922 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2923 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2924 | } |
d3632d41 | 2925 | [(set_attr "op_type" "RSY") |
4023fb28 | 2926 | (set_attr "type" "stm")]) |
9db1d521 HP |
2927 | |
2928 | ||
2929 | (define_insn "*store_multiple_si" | |
2930 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2931 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2932 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2933 | "reload_completed" |
9db1d521 HP |
2934 | { |
2935 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2936 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2937 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2938 | } |
d3632d41 | 2939 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2940 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2941 | (set_attr "type" "stm")]) |
9db1d521 HP |
2942 | |
2943 | ;; | |
2944 | ;; String instructions. | |
2945 | ;; | |
2946 | ||
963fc8d0 | 2947 | (define_insn "*execute_rl" |
2771c2f9 | 2948 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2949 | [(unspec [(match_operand 1 "register_operand" "a") |
2950 | (match_operand 2 "" "") | |
2951 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2952 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2953 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2954 | "exrl\t%1,%3" | |
2955 | [(set_attr "op_type" "RIL") | |
2956 | (set_attr "type" "cs")]) | |
2957 | ||
9bb86f41 | 2958 | (define_insn "*execute" |
2771c2f9 | 2959 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2960 | [(unspec [(match_operand 1 "register_operand" "a") |
2961 | (match_operand:BLK 2 "memory_operand" "R") | |
2962 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2963 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2964 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2965 | "ex\t%1,%2" | |
29a74354 UW |
2966 | [(set_attr "op_type" "RX") |
2967 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2968 | |
2969 | ||
91d39d71 UW |
2970 | ; |
2971 | ; strlenM instruction pattern(s). | |
2972 | ; | |
2973 | ||
9db2f16d | 2974 | (define_expand "strlen<mode>" |
085261c8 AK |
2975 | [(match_operand:P 0 "register_operand" "") ; result |
2976 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2977 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2978 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2979 | "" | |
2980 | { | |
2981 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2982 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2983 | operands[2], operands[3])); | |
2984 | else | |
2985 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2986 | ||
2987 | DONE; | |
2988 | }) | |
2989 | ||
2990 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 2991 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2992 | (parallel |
91d39d71 | 2993 | [(set (match_dup 4) |
9db2f16d | 2994 | (unspec:P [(const_int 0) |
91d39d71 | 2995 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2996 | (reg:SI 0) |
91d39d71 | 2997 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2998 | (clobber (scratch:P)) |
ae156f85 | 2999 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 3000 | (parallel |
9db2f16d AS |
3001 | [(set (match_operand:P 0 "register_operand" "") |
3002 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 3003 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 3004 | "" |
91d39d71 | 3005 | { |
9db2f16d AS |
3006 | operands[4] = gen_reg_rtx (Pmode); |
3007 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
3008 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3009 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
3010 | }) | |
3011 | ||
9db2f16d AS |
3012 | (define_insn "*strlen<mode>" |
3013 | [(set (match_operand:P 0 "register_operand" "=a") | |
3014 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
3015 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 3016 | (reg:SI 0) |
91d39d71 | 3017 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3018 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 3019 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 3020 | "" |
91d39d71 | 3021 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
3022 | [(set_attr "length" "8") |
3023 | (set_attr "type" "vs")]) | |
91d39d71 | 3024 | |
ccbdc0d4 AS |
3025 | ; |
3026 | ; cmpstrM instruction pattern(s). | |
3027 | ; | |
3028 | ||
3029 | (define_expand "cmpstrsi" | |
3030 | [(set (reg:SI 0) (const_int 0)) | |
3031 | (parallel | |
3032 | [(clobber (match_operand 3 "" "")) | |
3033 | (clobber (match_dup 4)) | |
3034 | (set (reg:CCU CC_REGNUM) | |
3035 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
3036 | (match_operand:BLK 2 "memory_operand" ""))) | |
3037 | (use (reg:SI 0))]) | |
3038 | (parallel | |
3039 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3040 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
3041 | (clobber (reg:CC CC_REGNUM))])] |
3042 | "" | |
3043 | { | |
3044 | /* As the result of CMPINT is inverted compared to what we need, | |
3045 | we have to swap the operands. */ | |
3046 | rtx op1 = operands[2]; | |
3047 | rtx op2 = operands[1]; | |
3048 | rtx addr1 = gen_reg_rtx (Pmode); | |
3049 | rtx addr2 = gen_reg_rtx (Pmode); | |
3050 | ||
3051 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
3052 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
3053 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
3054 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
3055 | operands[3] = addr1; | |
3056 | operands[4] = addr2; | |
3057 | }) | |
3058 | ||
3059 | (define_insn "*cmpstr<mode>" | |
3060 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3061 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3062 | (set (reg:CCU CC_REGNUM) | |
3063 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3064 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3065 | (use (reg:SI 0))] | |
3066 | "" | |
3067 | "clst\t%0,%1\;jo\t.-4" | |
3068 | [(set_attr "length" "8") | |
3069 | (set_attr "type" "vs")]) | |
9381e3f1 | 3070 | |
742090fc AS |
3071 | ; |
3072 | ; movstr instruction pattern. | |
3073 | ; | |
3074 | ||
3075 | (define_expand "movstr" | |
4a7dec25 DV |
3076 | [(match_operand 0 "register_operand" "") |
3077 | (match_operand 1 "memory_operand" "") | |
3078 | (match_operand 2 "memory_operand" "")] | |
3079 | "" | |
3080 | { | |
3081 | if (TARGET_64BIT) | |
3082 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3083 | else | |
3084 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3085 | DONE; | |
3086 | }) | |
3087 | ||
3088 | (define_expand "movstr<P:mode>" | |
742090fc | 3089 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3090 | (parallel |
742090fc AS |
3091 | [(clobber (match_dup 3)) |
3092 | (set (match_operand:BLK 1 "memory_operand" "") | |
3093 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3094 | (set (match_operand:P 0 "register_operand" "") |
3095 | (unspec:P [(match_dup 1) | |
742090fc AS |
3096 | (match_dup 2) |
3097 | (reg:SI 0)] UNSPEC_MVST)) | |
3098 | (clobber (reg:CC CC_REGNUM))])] | |
3099 | "" | |
3100 | { | |
859a4c0e AK |
3101 | rtx addr1, addr2; |
3102 | ||
3103 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3104 | { | |
3105 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3106 | DONE; | |
3107 | } | |
3108 | ||
3109 | addr1 = gen_reg_rtx (Pmode); | |
3110 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3111 | |
3112 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3113 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3114 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3115 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3116 | operands[3] = addr2; | |
3117 | }) | |
3118 | ||
3119 | (define_insn "*movstr" | |
3120 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3121 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3122 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3123 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3124 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3125 | (mem:BLK (match_dup 3)) |
3126 | (reg:SI 0)] UNSPEC_MVST)) | |
3127 | (clobber (reg:CC CC_REGNUM))] | |
3128 | "" | |
3129 | "mvst\t%1,%2\;jo\t.-4" | |
3130 | [(set_attr "length" "8") | |
3131 | (set_attr "type" "vs")]) | |
9381e3f1 | 3132 | |
742090fc | 3133 | |
9db1d521 | 3134 | ; |
70128ad9 | 3135 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3136 | ; |
3137 | ||
9db2f16d | 3138 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3139 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3140 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3141 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3142 | (match_operand 3 "" "")] |
3143 | "" | |
367d32f3 AK |
3144 | { |
3145 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3146 | DONE; | |
3147 | else | |
3148 | FAIL; | |
3149 | }) | |
9db1d521 | 3150 | |
ecbe845e UW |
3151 | ; Move a block that is up to 256 bytes in length. |
3152 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3153 | |
70128ad9 | 3154 | (define_expand "movmem_short" |
b9404c99 UW |
3155 | [(parallel |
3156 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3157 | (match_operand:BLK 1 "memory_operand" "")) | |
3158 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3159 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3160 | (clobber (match_dup 3))])] |
3161 | "" | |
3162 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3163 | |
70128ad9 | 3164 | (define_insn "*movmem_short" |
963fc8d0 AK |
3165 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3166 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3167 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3168 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3169 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3170 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3171 | "#" |
963fc8d0 | 3172 | [(set_attr "type" "cs") |
b5e0425c | 3173 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3174 | |
9bb86f41 UW |
3175 | (define_split |
3176 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3177 | (match_operand:BLK 1 "memory_operand" "")) | |
3178 | (use (match_operand 2 "const_int_operand" "")) | |
3179 | (use (match_operand 3 "immediate_operand" "")) | |
3180 | (clobber (scratch))] | |
3181 | "reload_completed" | |
3182 | [(parallel | |
3183 | [(set (match_dup 0) (match_dup 1)) | |
3184 | (use (match_dup 2))])] | |
3185 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3186 | |
9bb86f41 UW |
3187 | (define_split |
3188 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3189 | (match_operand:BLK 1 "memory_operand" "")) | |
3190 | (use (match_operand 2 "register_operand" "")) | |
3191 | (use (match_operand 3 "memory_operand" "")) | |
3192 | (clobber (scratch))] | |
3193 | "reload_completed" | |
3194 | [(parallel | |
3195 | [(unspec [(match_dup 2) (match_dup 3) | |
3196 | (const_int 0)] UNSPEC_EXECUTE) | |
3197 | (set (match_dup 0) (match_dup 1)) | |
3198 | (use (const_int 1))])] | |
3199 | "") | |
3200 | ||
963fc8d0 AK |
3201 | (define_split |
3202 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3203 | (match_operand:BLK 1 "memory_operand" "")) | |
3204 | (use (match_operand 2 "register_operand" "")) | |
3205 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3206 | (clobber (scratch))] | |
3207 | "TARGET_Z10 && reload_completed" | |
3208 | [(parallel | |
3209 | [(unspec [(match_dup 2) (const_int 0) | |
3210 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3211 | (set (match_dup 0) (match_dup 1)) | |
3212 | (use (const_int 1))])] | |
3213 | "operands[3] = gen_label_rtx ();") | |
3214 | ||
9bb86f41 UW |
3215 | (define_split |
3216 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3217 | (match_operand:BLK 1 "memory_operand" "")) | |
3218 | (use (match_operand 2 "register_operand" "")) | |
3219 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3220 | (clobber (match_operand 3 "register_operand" ""))] | |
3221 | "reload_completed && TARGET_CPU_ZARCH" | |
3222 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3223 | (parallel | |
9381e3f1 | 3224 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3225 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3226 | (set (match_dup 0) (match_dup 1)) | |
3227 | (use (const_int 1))])] | |
3228 | "operands[4] = gen_label_rtx ();") | |
3229 | ||
a41c6c53 | 3230 | ; Move a block of arbitrary length. |
9db1d521 | 3231 | |
70128ad9 | 3232 | (define_expand "movmem_long" |
b9404c99 UW |
3233 | [(parallel |
3234 | [(clobber (match_dup 2)) | |
3235 | (clobber (match_dup 3)) | |
3236 | (set (match_operand:BLK 0 "memory_operand" "") | |
3237 | (match_operand:BLK 1 "memory_operand" "")) | |
3238 | (use (match_operand 2 "general_operand" "")) | |
3239 | (use (match_dup 3)) | |
ae156f85 | 3240 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3241 | "" |
3242 | { | |
ef4bddc2 RS |
3243 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3244 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3245 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3246 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3247 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3248 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3249 | rtx len0 = gen_lowpart (Pmode, reg0); |
3250 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3251 | ||
c41c1387 | 3252 | emit_clobber (reg0); |
b9404c99 UW |
3253 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3254 | emit_move_insn (len0, operands[2]); | |
3255 | ||
c41c1387 | 3256 | emit_clobber (reg1); |
b9404c99 UW |
3257 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3258 | emit_move_insn (len1, operands[2]); | |
3259 | ||
3260 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3261 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3262 | operands[2] = reg0; | |
3263 | operands[3] = reg1; | |
3264 | }) | |
3265 | ||
a1aed706 AS |
3266 | (define_insn "*movmem_long" |
3267 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3268 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3269 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3270 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3271 | (use (match_dup 2)) |
3272 | (use (match_dup 3)) | |
ae156f85 | 3273 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3274 | "TARGET_64BIT || !TARGET_ZARCH" |
3275 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3276 | [(set_attr "length" "8") | |
3277 | (set_attr "type" "vs")]) | |
3278 | ||
3279 | (define_insn "*movmem_long_31z" | |
3280 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3281 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3282 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3283 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3284 | (use (match_dup 2)) | |
3285 | (use (match_dup 3)) | |
3286 | (clobber (reg:CC CC_REGNUM))] | |
3287 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3288 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3289 | [(set_attr "length" "8") |
3290 | (set_attr "type" "vs")]) | |
9db1d521 | 3291 | |
638e37c2 WG |
3292 | |
3293 | ; | |
3294 | ; Test data class. | |
3295 | ; | |
3296 | ||
0f67fa83 WG |
3297 | (define_expand "signbit<mode>2" |
3298 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3299 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3300 | (match_dup 2)] | |
0f67fa83 WG |
3301 | UNSPEC_TDC_INSN)) |
3302 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3303 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3304 | "TARGET_HARD_FLOAT" |
3305 | { | |
3306 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3307 | }) | |
3308 | ||
638e37c2 WG |
3309 | (define_expand "isinf<mode>2" |
3310 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3311 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3312 | (match_dup 2)] | |
638e37c2 WG |
3313 | UNSPEC_TDC_INSN)) |
3314 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3315 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3316 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3317 | { |
3318 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3319 | }) | |
3320 | ||
085261c8 AK |
3321 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3322 | ; instruction will be issued by reload. The constraint of operand 1 | |
3323 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3324 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3325 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3326 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3327 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3328 | UNSPEC_CC_TO_INT))] | |
3329 | "operands != NULL" | |
3330 | "#" | |
3331 | "reload_completed" | |
3332 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3333 | ||
638e37c2 WG |
3334 | ; This insn is used to generate all variants of the Test Data Class |
3335 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3336 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3337 | ; specifying the required test(s). |
638e37c2 | 3338 | ; |
be5de7a1 | 3339 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3340 | (define_insn "*TDC_insn_<mode>" |
3341 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3342 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3343 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3344 | "TARGET_HARD_FLOAT" |
0387c142 | 3345 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3346 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3347 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3348 | |
638e37c2 WG |
3349 | |
3350 | ||
9db1d521 | 3351 | ; |
57e84f18 | 3352 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3353 | ; |
3354 | ||
57e84f18 | 3355 | (define_expand "setmem<mode>" |
a41c6c53 | 3356 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3357 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3358 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3359 | (match_operand 3 "" "")] |
a41c6c53 | 3360 | "" |
6d057022 | 3361 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3362 | |
a41c6c53 | 3363 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3364 | ; The block length is taken as (operands[1] % 256) + 1. |
3365 | ||
70128ad9 | 3366 | (define_expand "clrmem_short" |
b9404c99 UW |
3367 | [(parallel |
3368 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3369 | (const_int 0)) | |
3370 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3371 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3372 | (clobber (match_dup 2)) |
ae156f85 | 3373 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3374 | "" |
3375 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3376 | |
70128ad9 | 3377 | (define_insn "*clrmem_short" |
963fc8d0 | 3378 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3379 | (const_int 0)) |
963fc8d0 AK |
3380 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3381 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3382 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3383 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3384 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3385 | "#" |
963fc8d0 | 3386 | [(set_attr "type" "cs") |
b5e0425c | 3387 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3388 | |
3389 | (define_split | |
3390 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3391 | (const_int 0)) | |
3392 | (use (match_operand 1 "const_int_operand" "")) | |
3393 | (use (match_operand 2 "immediate_operand" "")) | |
3394 | (clobber (scratch)) | |
ae156f85 | 3395 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3396 | "reload_completed" |
3397 | [(parallel | |
3398 | [(set (match_dup 0) (const_int 0)) | |
3399 | (use (match_dup 1)) | |
ae156f85 | 3400 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3401 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3402 | |
9bb86f41 UW |
3403 | (define_split |
3404 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3405 | (const_int 0)) | |
3406 | (use (match_operand 1 "register_operand" "")) | |
3407 | (use (match_operand 2 "memory_operand" "")) | |
3408 | (clobber (scratch)) | |
ae156f85 | 3409 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3410 | "reload_completed" |
3411 | [(parallel | |
3412 | [(unspec [(match_dup 1) (match_dup 2) | |
3413 | (const_int 0)] UNSPEC_EXECUTE) | |
3414 | (set (match_dup 0) (const_int 0)) | |
3415 | (use (const_int 1)) | |
ae156f85 | 3416 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3417 | "") |
9db1d521 | 3418 | |
963fc8d0 AK |
3419 | (define_split |
3420 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3421 | (const_int 0)) | |
3422 | (use (match_operand 1 "register_operand" "")) | |
3423 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3424 | (clobber (scratch)) | |
3425 | (clobber (reg:CC CC_REGNUM))] | |
3426 | "TARGET_Z10 && reload_completed" | |
3427 | [(parallel | |
3428 | [(unspec [(match_dup 1) (const_int 0) | |
3429 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3430 | (set (match_dup 0) (const_int 0)) | |
3431 | (use (const_int 1)) | |
3432 | (clobber (reg:CC CC_REGNUM))])] | |
3433 | "operands[3] = gen_label_rtx ();") | |
3434 | ||
9bb86f41 UW |
3435 | (define_split |
3436 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3437 | (const_int 0)) | |
3438 | (use (match_operand 1 "register_operand" "")) | |
3439 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3440 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3441 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3442 | "reload_completed && TARGET_CPU_ZARCH" |
3443 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3444 | (parallel | |
9381e3f1 | 3445 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3446 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3447 | (set (match_dup 0) (const_int 0)) | |
3448 | (use (const_int 1)) | |
ae156f85 | 3449 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3450 | "operands[3] = gen_label_rtx ();") |
3451 | ||
9381e3f1 | 3452 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3453 | |
da0dcab1 | 3454 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3455 | [(parallel |
3456 | [(clobber (match_dup 1)) | |
3457 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3458 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3459 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3460 | (use (match_dup 3)) |
ae156f85 | 3461 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3462 | "" |
a41c6c53 | 3463 | { |
ef4bddc2 RS |
3464 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3465 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3466 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3467 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3468 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3469 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3470 | |
c41c1387 | 3471 | emit_clobber (reg0); |
b9404c99 UW |
3472 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3473 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3474 | |
b9404c99 | 3475 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3476 | |
b9404c99 UW |
3477 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3478 | operands[1] = reg0; | |
6d057022 | 3479 | operands[3] = reg1; |
da0dcab1 | 3480 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3481 | }) |
a41c6c53 | 3482 | |
da0dcab1 DV |
3483 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3484 | ||
db340c73 | 3485 | (define_insn "*setmem_long" |
a1aed706 | 3486 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3487 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3488 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3489 | (subreg:P (match_dup 3) <modesize>)] |
3490 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3491 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3492 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3493 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3494 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3495 | [(set_attr "length" "8") |
3496 | (set_attr "type" "vs")]) | |
9db1d521 | 3497 | |
db340c73 AK |
3498 | (define_insn "*setmem_long_and" |
3499 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3500 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3501 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3502 | (subreg:P (match_dup 3) <modesize>)] |
3503 | UNSPEC_REPLICATE_BYTE)) | |
3504 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3505 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3506 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3507 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3508 | [(set_attr "length" "8") | |
3509 | (set_attr "type" "vs")]) | |
3510 | ||
da0dcab1 DV |
3511 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3512 | ; of the SImode subregs. | |
3513 | ||
db340c73 | 3514 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3515 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3516 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3517 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3518 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3519 | (use (match_operand:TI 1 "register_operand" "d")) |
3520 | (clobber (reg:CC CC_REGNUM))] | |
3521 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3522 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3523 | [(set_attr "length" "8") | |
3524 | (set_attr "type" "vs")]) | |
9602b6a1 | 3525 | |
db340c73 AK |
3526 | (define_insn "*setmem_long_and_31z" |
3527 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3528 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3529 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3530 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3531 | (use (match_operand:TI 1 "register_operand" "d")) | |
3532 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3533 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3534 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3535 | [(set_attr "length" "8") | |
3536 | (set_attr "type" "vs")]) | |
3537 | ||
9db1d521 | 3538 | ; |
358b8f01 | 3539 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3540 | ; |
3541 | ||
358b8f01 | 3542 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3543 | [(set (match_operand:SI 0 "register_operand" "") |
3544 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3545 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3546 | (use (match_operand:SI 3 "general_operand" "")) | |
3547 | (use (match_operand:SI 4 "" ""))] | |
3548 | "" | |
367d32f3 AK |
3549 | { |
3550 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3551 | operands[2], operands[3])) | |
3552 | DONE; | |
3553 | else | |
3554 | FAIL; | |
3555 | }) | |
9db1d521 | 3556 | |
a41c6c53 UW |
3557 | ; Compare a block that is up to 256 bytes in length. |
3558 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3559 | |
b9404c99 UW |
3560 | (define_expand "cmpmem_short" |
3561 | [(parallel | |
ae156f85 | 3562 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3563 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3564 | (match_operand:BLK 1 "memory_operand" ""))) |
3565 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3566 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3567 | (clobber (match_dup 3))])] |
3568 | "" | |
3569 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3570 | |
b9404c99 | 3571 | (define_insn "*cmpmem_short" |
ae156f85 | 3572 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3573 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3574 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3575 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3576 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3577 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3578 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3579 | "#" |
963fc8d0 | 3580 | [(set_attr "type" "cs") |
b5e0425c | 3581 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3582 | |
9bb86f41 | 3583 | (define_split |
ae156f85 | 3584 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3585 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3586 | (match_operand:BLK 1 "memory_operand" ""))) | |
3587 | (use (match_operand 2 "const_int_operand" "")) | |
3588 | (use (match_operand 3 "immediate_operand" "")) | |
3589 | (clobber (scratch))] | |
3590 | "reload_completed" | |
3591 | [(parallel | |
ae156f85 | 3592 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3593 | (use (match_dup 2))])] |
3594 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3595 | |
9bb86f41 | 3596 | (define_split |
ae156f85 | 3597 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3598 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3599 | (match_operand:BLK 1 "memory_operand" ""))) | |
3600 | (use (match_operand 2 "register_operand" "")) | |
3601 | (use (match_operand 3 "memory_operand" "")) | |
3602 | (clobber (scratch))] | |
3603 | "reload_completed" | |
3604 | [(parallel | |
3605 | [(unspec [(match_dup 2) (match_dup 3) | |
3606 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3607 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3608 | (use (const_int 1))])] |
3609 | "") | |
3610 | ||
963fc8d0 AK |
3611 | (define_split |
3612 | [(set (reg:CCU CC_REGNUM) | |
3613 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3614 | (match_operand:BLK 1 "memory_operand" ""))) | |
3615 | (use (match_operand 2 "register_operand" "")) | |
3616 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3617 | (clobber (scratch))] | |
3618 | "TARGET_Z10 && reload_completed" | |
3619 | [(parallel | |
3620 | [(unspec [(match_dup 2) (const_int 0) | |
3621 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3622 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3623 | (use (const_int 1))])] | |
3624 | "operands[4] = gen_label_rtx ();") | |
3625 | ||
9bb86f41 | 3626 | (define_split |
ae156f85 | 3627 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3628 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3629 | (match_operand:BLK 1 "memory_operand" ""))) | |
3630 | (use (match_operand 2 "register_operand" "")) | |
3631 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3632 | (clobber (match_operand 3 "register_operand" ""))] | |
3633 | "reload_completed && TARGET_CPU_ZARCH" | |
3634 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3635 | (parallel | |
9381e3f1 | 3636 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3637 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3638 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3639 | (use (const_int 1))])] |
3640 | "operands[4] = gen_label_rtx ();") | |
3641 | ||
a41c6c53 | 3642 | ; Compare a block of arbitrary length. |
9db1d521 | 3643 | |
b9404c99 UW |
3644 | (define_expand "cmpmem_long" |
3645 | [(parallel | |
3646 | [(clobber (match_dup 2)) | |
3647 | (clobber (match_dup 3)) | |
ae156f85 | 3648 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3649 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3650 | (match_operand:BLK 1 "memory_operand" ""))) |
3651 | (use (match_operand 2 "general_operand" "")) | |
3652 | (use (match_dup 3))])] | |
3653 | "" | |
3654 | { | |
ef4bddc2 RS |
3655 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3656 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3657 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3658 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3659 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3660 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3661 | rtx len0 = gen_lowpart (Pmode, reg0); |
3662 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3663 | ||
c41c1387 | 3664 | emit_clobber (reg0); |
b9404c99 UW |
3665 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3666 | emit_move_insn (len0, operands[2]); | |
3667 | ||
c41c1387 | 3668 | emit_clobber (reg1); |
b9404c99 UW |
3669 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3670 | emit_move_insn (len1, operands[2]); | |
3671 | ||
3672 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3673 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3674 | operands[2] = reg0; | |
3675 | operands[3] = reg1; | |
3676 | }) | |
3677 | ||
a1aed706 AS |
3678 | (define_insn "*cmpmem_long" |
3679 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3680 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3681 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3682 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3683 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3684 | (use (match_dup 2)) |
3685 | (use (match_dup 3))] | |
9602b6a1 | 3686 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3687 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3688 | [(set_attr "length" "8") |
3689 | (set_attr "type" "vs")]) | |
9db1d521 | 3690 | |
9602b6a1 AK |
3691 | (define_insn "*cmpmem_long_31z" |
3692 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3693 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3694 | (set (reg:CCU CC_REGNUM) | |
3695 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3696 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3697 | (use (match_dup 2)) | |
3698 | (use (match_dup 3))] | |
3699 | "!TARGET_64BIT && TARGET_ZARCH" | |
3700 | "clcle\t%0,%1,0\;jo\t.-4" | |
3701 | [(set_attr "op_type" "NN") | |
3702 | (set_attr "type" "vs") | |
3703 | (set_attr "length" "8")]) | |
3704 | ||
02887425 UW |
3705 | ; Convert CCUmode condition code to integer. |
3706 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3707 | |
02887425 | 3708 | (define_insn_and_split "cmpint" |
9db1d521 | 3709 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3710 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3711 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3712 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3713 | "" |
02887425 UW |
3714 | "#" |
3715 | "reload_completed" | |
3716 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3717 | (parallel | |
3718 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3719 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3720 | |
3721 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3722 | [(set (reg CC_REGNUM) |
02887425 | 3723 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3724 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3725 | (const_int 0))) |
3726 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3727 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3728 | "s390_match_ccmode (insn, CCSmode)" |
3729 | "#" | |
3730 | "&& reload_completed" | |
3731 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3732 | (parallel | |
3733 | [(set (match_dup 2) (match_dup 3)) | |
3734 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3735 | { |
02887425 UW |
3736 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3737 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3738 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3739 | }) | |
9db1d521 | 3740 | |
02887425 | 3741 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3742 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3743 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3744 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3745 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3746 | "TARGET_ZARCH" |
02887425 UW |
3747 | "#" |
3748 | "&& reload_completed" | |
3749 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3750 | (parallel | |
3751 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3752 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3753 | |
3754 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3755 | [(set (reg CC_REGNUM) |
9381e3f1 | 3756 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3757 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3758 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3759 | (const_int 32)) (const_int 32)) |
3760 | (const_int 0))) | |
3761 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3762 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3763 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3764 | "#" |
3765 | "&& reload_completed" | |
3766 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3767 | (parallel | |
3768 | [(set (match_dup 2) (match_dup 3)) | |
3769 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3770 | { |
02887425 UW |
3771 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3772 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3773 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3774 | }) | |
9db1d521 | 3775 | |
4023fb28 | 3776 | |
9db1d521 HP |
3777 | ;; |
3778 | ;;- Conversion instructions. | |
3779 | ;; | |
3780 | ||
6fa05db6 | 3781 | (define_insn "*sethighpartsi" |
d3632d41 | 3782 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3783 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3784 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3785 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3786 | "" |
d3632d41 | 3787 | "@ |
6fa05db6 AS |
3788 | icm\t%0,%2,%S1 |
3789 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3790 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3791 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3792 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3793 | |
6fa05db6 | 3794 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3795 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3796 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3797 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3798 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3799 | "TARGET_ZARCH" |
6fa05db6 | 3800 | "icmh\t%0,%2,%S1" |
729e750f WG |
3801 | [(set_attr "op_type" "RSY") |
3802 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3803 | |
6fa05db6 | 3804 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3805 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3806 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3807 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3808 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3809 | "!TARGET_ZARCH" |
d3632d41 | 3810 | "@ |
6fa05db6 AS |
3811 | icm\t%0,%2,%S1 |
3812 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3813 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3814 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3815 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3816 | ||
1a2e356e RH |
3817 | ; |
3818 | ; extv instruction patterns | |
3819 | ; | |
3820 | ||
3821 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3822 | ; after resolving some issues with it. | |
3823 | ||
3824 | (define_expand "extzv" | |
3825 | [(parallel | |
3826 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3827 | (zero_extract:DI | |
3828 | (match_operand:DI 1 "register_operand" "d") | |
3829 | (match_operand 2 "const_int_operand" "") ; size | |
3830 | (match_operand 3 "const_int_operand" ""))) ; start | |
3831 | (clobber (reg:CC CC_REGNUM))])] | |
3832 | "TARGET_Z10" | |
3833 | { | |
0f6f72e8 DV |
3834 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3835 | FAIL; | |
1a2e356e RH |
3836 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3837 | if (TARGET_ZEC12) | |
3838 | { | |
3839 | emit_move_insn (operands[0], | |
3840 | gen_rtx_ZERO_EXTRACT (DImode, | |
3841 | operands[1], | |
3842 | operands[2], | |
3843 | operands[3])); | |
3844 | DONE; | |
3845 | } | |
3846 | }) | |
3847 | ||
64c744b9 | 3848 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3849 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3850 | (zero_extract:GPR | |
3851 | (match_operand:GPR 1 "register_operand" "d") | |
3852 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3853 | (match_operand 3 "const_int_operand" ""))) ; start |
3854 | ] | |
0f6f72e8 DV |
3855 | "<z10_or_zEC12_cond> |
3856 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3857 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3858 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3859 | [(set_attr "op_type" "RIE") | |
3860 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3861 | |
64c744b9 DV |
3862 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3863 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3864 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3865 | (match_operand 1 "const_int_operand" "") ; size | |
3866 | (match_operand 2 "const_int_operand" "")) ; start | |
3867 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3868 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3869 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3870 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3871 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3872 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3873 | [(set_attr "op_type" "RIE") | |
3874 | (set_attr "z10prop" "z10_super_E1")]) | |
3875 | ||
3876 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3877 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3878 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3879 | (ior:SI (and:SI | |
3880 | (match_operand:SI 1 "register_operand" "0") | |
3881 | (match_operand:SI 2 "const_int_operand" "")) | |
3882 | (subreg:SI | |
3883 | (zero_extract:DI | |
3884 | (match_operand:DI 3 "register_operand" "d") | |
3885 | (match_operand 4 "const_int_operand" "") ; size | |
3886 | (match_operand 5 "const_int_operand" "")) ; start | |
3887 | 4)))] | |
3888 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3889 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
64c744b9 DV |
3890 | && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))" |
3891 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" | |
3892 | [(set_attr "op_type" "RIE") | |
3893 | (set_attr "z10prop" "z10_super_E1")]) | |
3894 | ||
3895 | ; ((int)foo >> 10) & 1; | |
3896 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3897 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3898 | (ne:DI (zero_extract:DI | |
3899 | (match_operand:DI 1 "register_operand" "d") | |
3900 | (const_int 1) ; size | |
3901 | (match_operand 2 "const_int_operand" "")) ; start | |
3902 | (const_int 0)))] | |
0f6f72e8 DV |
3903 | "<z10_or_zEC12_cond> |
3904 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3905 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3906 | [(set_attr "op_type" "RIE") | |
3907 | (set_attr "z10prop" "z10_super_E1")]) | |
3908 | ||
3909 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3910 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3911 | (and:DI (subreg:DI | |
3912 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3913 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3914 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3915 | "<z10_or_zEC12_cond> | |
3916 | && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))" | |
3917 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift | |
3918 | [(set_attr "op_type" "RIE") | |
3919 | (set_attr "z10prop" "z10_super_E1")]) | |
3920 | ||
3921 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3922 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3923 | (and:DI (subreg:DI | |
3924 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3925 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3926 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3927 | "<z10_or_zEC12_cond> | |
3928 | && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
3929 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
3930 | [(set_attr "op_type" "RIE") | |
3931 | (set_attr "z10prop" "z10_super_E1")]) | |
3932 | ||
3933 | (define_insn "*<risbg_n>_di_and_rot" | |
3934 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3935 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
3936 | (match_operand:DI 2 "const_int_operand" "")) | |
3937 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3938 | "<z10_or_zEC12_cond>" | |
3939 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
3940 | [(set_attr "op_type" "RIE") |
3941 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3942 | |
1a2e356e | 3943 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 3944 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3945 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3946 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3947 | (const_int 0))) |
ae156f85 | 3948 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3949 | "!TARGET_Z10" |
cc7ab9b7 UW |
3950 | "#" |
3951 | "&& reload_completed" | |
4023fb28 | 3952 | [(parallel |
6fa05db6 | 3953 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3954 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3955 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3956 | { |
6fa05db6 AS |
3957 | int bitsize = INTVAL (operands[2]); |
3958 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3959 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3960 | ||
3961 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3962 | set_mem_size (operands[1], size); |
2542ef05 | 3963 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3964 | operands[3] = GEN_INT (mask); |
b628bd8e | 3965 | }) |
4023fb28 | 3966 | |
1a2e356e | 3967 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 3968 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3969 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3970 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3971 | (const_int 0))) |
ae156f85 | 3972 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3973 | "" |
cc7ab9b7 UW |
3974 | "#" |
3975 | "&& reload_completed" | |
4023fb28 | 3976 | [(parallel |
6fa05db6 | 3977 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3978 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3979 | (parallel |
3980 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3981 | (clobber (reg:CC CC_REGNUM))])] | |
3982 | { | |
3983 | int bitsize = INTVAL (operands[2]); | |
3984 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3985 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3986 | ||
3987 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3988 | set_mem_size (operands[1], size); |
2542ef05 | 3989 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3990 | operands[3] = GEN_INT (mask); |
3991 | }) | |
3992 | ||
3993 | ; | |
3994 | ; insv instruction patterns | |
3995 | ; | |
3996 | ||
3997 | (define_expand "insv" | |
3998 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3999 | (match_operand 1 "const_int_operand" "") | |
4000 | (match_operand 2 "const_int_operand" "")) | |
4001 | (match_operand 3 "general_operand" ""))] | |
4002 | "" | |
4023fb28 | 4003 | { |
6fa05db6 AS |
4004 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
4005 | DONE; | |
4006 | FAIL; | |
b628bd8e | 4007 | }) |
4023fb28 | 4008 | |
2542ef05 RH |
4009 | |
4010 | ; The normal RTL expansion will never generate a zero_extract where | |
4011 | ; the location operand isn't word mode. However, we do this in the | |
4012 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 4013 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 4014 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
4015 | (match_operand 1 "const_int_operand" "I") ; size |
4016 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 4017 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 4018 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
4019 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
4020 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 4021 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 4022 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
4023 | [(set_attr "op_type" "RIE") |
4024 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4025 | |
22ac2c2f AK |
4026 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
4027 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
4028 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
4029 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
4030 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 4031 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 4032 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 4033 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
4034 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
4035 | "@ | |
4036 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
4037 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
4038 | [(set_attr "op_type" "RIE") | |
4039 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 4040 | |
64c744b9 DV |
4041 | (define_insn "*insv_z10_noshift_cc" |
4042 | [(set (reg CC_REGNUM) | |
4043 | (compare | |
4044 | (ior:DI | |
4045 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4046 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4047 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4048 | (match_operand:DI 4 "const_int_operand" ""))) | |
4049 | (const_int 0))) | |
4050 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
4051 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
4052 | (and:DI (match_dup 3) (match_dup 4))))] | |
4053 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4054 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4055 | "@ | |
4056 | risbg\t%0,%1,%s2,%e2,0 | |
4057 | risbg\t%0,%3,%s4,%e4,0" | |
4058 | [(set_attr "op_type" "RIE") | |
4059 | (set_attr "z10prop" "z10_super_E1")]) | |
4060 | ||
4061 | (define_insn "*insv_z10_noshift_cconly" | |
4062 | [(set | |
4063 | (reg CC_REGNUM) | |
4064 | (compare | |
4065 | (ior:DI | |
4066 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4067 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4068 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4069 | (match_operand:DI 4 "const_int_operand" ""))) | |
4070 | (const_int 0))) | |
4071 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4072 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4073 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4074 | "@ | |
4075 | risbg\t%0,%1,%s2,%e2,0 | |
4076 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4077 | [(set_attr "op_type" "RIE") |
4078 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4079 | |
3d44ff99 AK |
4080 | ; Implement appending Y on the left of S bits of X |
4081 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4082 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4083 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4084 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4085 | (match_operand:GPR 2 "immediate_operand" "")) | |
4086 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4087 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 DV |
4088 | "<z10_or_zEC12_cond> |
4089 | && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
4090 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" | |
3d44ff99 AK |
4091 | [(set_attr "op_type" "RIE") |
4092 | (set_attr "z10prop" "z10_super_E1")]) | |
4093 | ||
64c744b9 DV |
4094 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4095 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4096 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4097 | (ior:GPR (and:GPR | |
4098 | (match_operand:GPR 1 "register_operand" "0") | |
4099 | (match_operand:GPR 2 "const_int_operand" "")) | |
4100 | (lshiftrt:GPR | |
4101 | (match_operand:GPR 3 "register_operand" "d") | |
4102 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4103 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
4104 | == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
4105 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" | |
4106 | [(set_attr "op_type" "RIE") | |
4107 | (set_attr "z10prop" "z10_super_E1")]) | |
4108 | ||
4109 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4110 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4111 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4112 | (ior:SI (and:SI | |
4113 | (match_operand:SI 1 "register_operand" "0") | |
4114 | (match_operand:SI 2 "const_int_operand" "")) | |
4115 | (subreg:SI | |
4116 | (lshiftrt:DI | |
4117 | (match_operand:DI 3 "register_operand" "d") | |
4118 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4119 | "<z10_or_zEC12_cond> | |
4120 | && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))" | |
4121 | "<risbg_n>\t%0,%3,%4,63,64-%4" | |
4122 | [(set_attr "op_type" "RIE") | |
4123 | (set_attr "z10prop" "z10_super_E1")]) | |
4124 | ||
4125 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4126 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4127 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4128 | (and:SI | |
4129 | (subreg:SI (lshiftrt:DI | |
4130 | (match_operand:DI 1 "register_operand" "d") | |
4131 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4132 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4133 | "<z10_or_zEC12_cond>" | |
4134 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4135 | [(set_attr "op_type" "RIE") |
4136 | (set_attr "z10prop" "z10_super_E1")]) | |
4137 | ||
4138 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4139 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4140 | ; -> z = y >> d; z = risbg; | |
4141 | ||
4142 | (define_split | |
4143 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4144 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4145 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4146 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4147 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4148 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4149 | [(set (match_dup 6) |
3d44ff99 AK |
4150 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4151 | (set (match_dup 0) | |
1d11f7ce | 4152 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4153 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4154 | { | |
4155 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4156 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4157 | { |
4158 | if (!can_create_pseudo_p ()) | |
4159 | FAIL; | |
4160 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4161 | } | |
4162 | else | |
4163 | operands[6] = operands[0]; | |
3d44ff99 AK |
4164 | }) |
4165 | ||
4166 | (define_split | |
4167 | [(parallel | |
4168 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4169 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4170 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4171 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4172 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4173 | (clobber (reg:CC CC_REGNUM))])] | |
4174 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4175 | [(set (match_dup 6) |
3d44ff99 AK |
4176 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4177 | (parallel | |
4178 | [(set (match_dup 0) | |
1d11f7ce | 4179 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4180 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4181 | (clobber (reg:CC CC_REGNUM))])] | |
4182 | { | |
4183 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4184 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4185 | { |
4186 | if (!can_create_pseudo_p ()) | |
4187 | FAIL; | |
4188 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4189 | } | |
4190 | else | |
4191 | operands[6] = operands[0]; | |
3d44ff99 AK |
4192 | }) |
4193 | ||
50dc4eed | 4194 | ; rosbg, rxsbg |
571e408a | 4195 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4196 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4197 | (IXOR:GPR |
4198 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4199 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4200 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4201 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4202 | "TARGET_Z10" |
571e408a RH |
4203 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4204 | [(set_attr "op_type" "RIE")]) | |
4205 | ||
50dc4eed | 4206 | ; rosbg, rxsbg |
571e408a RH |
4207 | (define_insn "*r<noxa>sbg_di_rotl" |
4208 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4209 | (IXOR:DI | |
4210 | (and:DI | |
4211 | (rotate:DI | |
4212 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4213 | (match_operand:DI 3 "const_int_operand" "")) | |
4214 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4215 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4216 | (clobber (reg:CC CC_REGNUM))] | |
4217 | "TARGET_Z10" | |
4218 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
4219 | [(set_attr "op_type" "RIE")]) | |
4220 | ||
50dc4eed | 4221 | ; rosbg, rxsbg |
f3d90045 | 4222 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4223 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4224 | (IXOR:GPR | |
4225 | (and:GPR | |
4226 | (lshiftrt:GPR | |
4227 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4228 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4229 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4230 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4231 | (clobber (reg:CC CC_REGNUM))] | |
4232 | "TARGET_Z10 | |
4233 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4234 | INTVAL (operands[2]))" | |
4235 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
4236 | [(set_attr "op_type" "RIE")]) | |
4237 | ||
50dc4eed | 4238 | ; rosbg, rxsbg |
f3d90045 | 4239 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4240 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4241 | (IXOR:GPR | |
4242 | (and:GPR | |
4243 | (ashift:GPR | |
4244 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4245 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4246 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4247 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4248 | (clobber (reg:CC CC_REGNUM))] | |
4249 | "TARGET_Z10 | |
4250 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4251 | INTVAL (operands[2]))" | |
4252 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4253 | [(set_attr "op_type" "RIE")]) |
4254 | ||
f3d90045 DV |
4255 | ;; unsigned {int,long} a, b |
4256 | ;; a = a | (b << const_int) | |
4257 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4258 | ; rosbg, rxsbg |
f3d90045 DV |
4259 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4260 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4261 | (IXOR:GPR | |
4262 | (ashift:GPR | |
4263 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4264 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4265 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4266 | (clobber (reg:CC CC_REGNUM))] | |
4267 | "TARGET_Z10" | |
576987fc | 4268 | "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2" |
f3d90045 DV |
4269 | [(set_attr "op_type" "RIE")]) |
4270 | ||
4271 | ;; unsigned {int,long} a, b | |
4272 | ;; a = a | (b >> const_int) | |
4273 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4274 | ; rosbg, rxsbg |
f3d90045 DV |
4275 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4276 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4277 | (IXOR:GPR | |
4278 | (lshiftrt:GPR | |
4279 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4280 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4281 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4282 | (clobber (reg:CC CC_REGNUM))] | |
4283 | "TARGET_Z10" | |
576987fc | 4284 | "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2" |
f3d90045 DV |
4285 | [(set_attr "op_type" "RIE")]) |
4286 | ||
5bb33936 RH |
4287 | ;; These two are generated by combine for s.bf &= val. |
4288 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4289 | ;; shifts and ands, which results in some truly awful patterns | |
4290 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4291 | ;; Instead of | |
4292 | ;; | |
4293 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4294 | ;; (const_int 24 [0x18]) | |
4295 | ;; (const_int 0 [0])) | |
4296 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4297 | ;; (const_int 40 [0x28])) 4) | |
4298 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4299 | ;; | |
4300 | ;; we should instead generate | |
4301 | ;; | |
4302 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4303 | ;; (const_int 24 [0x18]) | |
4304 | ;; (const_int 0 [0])) | |
4305 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4306 | ;; (const_int 40 [0x28])) | |
4307 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4308 | ;; | |
4309 | ;; by noticing that we can push down the outer paradoxical subreg | |
4310 | ;; into the operation. | |
4311 | ||
4312 | (define_insn "*insv_rnsbg_noshift" | |
4313 | [(set (zero_extract:DI | |
4314 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4315 | (match_operand 1 "const_int_operand" "") | |
4316 | (match_operand 2 "const_int_operand" "")) | |
4317 | (and:DI | |
4318 | (match_dup 0) | |
4319 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4320 | (clobber (reg:CC CC_REGNUM))] | |
4321 | "TARGET_Z10 | |
0f6f72e8 | 4322 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4323 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4324 | "rnsbg\t%0,%3,%2,63,0" | |
4325 | [(set_attr "op_type" "RIE")]) | |
4326 | ||
4327 | (define_insn "*insv_rnsbg_srl" | |
4328 | [(set (zero_extract:DI | |
4329 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4330 | (match_operand 1 "const_int_operand" "") | |
4331 | (match_operand 2 "const_int_operand" "")) | |
4332 | (and:DI | |
4333 | (lshiftrt:DI | |
4334 | (match_dup 0) | |
4335 | (match_operand 3 "const_int_operand" "")) | |
4336 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4337 | (clobber (reg:CC CC_REGNUM))] | |
4338 | "TARGET_Z10 | |
0f6f72e8 | 4339 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4340 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4341 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4342 | [(set_attr "op_type" "RIE")]) | |
4343 | ||
6fa05db6 | 4344 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4345 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4346 | (match_operand 1 "const_int_operand" "n,n") |
4347 | (const_int 0)) | |
9602b6a1 | 4348 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4349 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4350 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4351 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4352 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4353 | { | |
4354 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4355 | ||
4356 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4357 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4358 | : "stcmy\t%2,%1,%S0"; |
4359 | } | |
9381e3f1 | 4360 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4361 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4362 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4363 | |
4364 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4365 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4366 | (match_operand 1 "const_int_operand" "n") |
4367 | (const_int 0)) | |
4368 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4369 | (const_int 32)))] | |
9602b6a1 | 4370 | "TARGET_ZARCH |
0f6f72e8 | 4371 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4372 | && INTVAL (operands[1]) > 0 |
4373 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4374 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4375 | { | |
4376 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4377 | ||
4378 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4379 | return "stcmh\t%2,%1,%S0"; | |
4380 | } | |
9381e3f1 WG |
4381 | [(set_attr "op_type" "RSY") |
4382 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4383 | |
9602b6a1 AK |
4384 | (define_insn "*insvdi_reg_imm" |
4385 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4386 | (const_int 16) | |
4387 | (match_operand 1 "const_int_operand" "n")) | |
4388 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4389 | "TARGET_ZARCH |
0f6f72e8 | 4390 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4391 | && INTVAL (operands[1]) >= 0 |
4392 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4393 | && INTVAL (operands[1]) % 16 == 0" | |
4394 | { | |
4395 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4396 | { | |
4397 | case 64: return "iihh\t%0,%x2"; break; | |
4398 | case 48: return "iihl\t%0,%x2"; break; | |
4399 | case 32: return "iilh\t%0,%x2"; break; | |
4400 | case 16: return "iill\t%0,%x2"; break; | |
4401 | default: gcc_unreachable(); | |
4402 | } | |
4403 | } | |
9381e3f1 WG |
4404 | [(set_attr "op_type" "RI") |
4405 | (set_attr "z10prop" "z10_super_E1")]) | |
4406 | ||
9fec758d WG |
4407 | ; Update the left-most 32 bit of a DI. |
4408 | (define_insn "*insv_h_di_reg_extimm" | |
4409 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4410 | (const_int 32) | |
4411 | (const_int 0)) | |
4412 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4413 | "TARGET_EXTIMM" | |
4414 | "iihf\t%0,%o1" | |
4415 | [(set_attr "op_type" "RIL") | |
4416 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4417 | |
d378b983 RH |
4418 | ; Update the right-most 32 bit of a DI. |
4419 | (define_insn "*insv_l_di_reg_extimm" | |
4420 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4421 | (const_int 32) | |
4422 | (const_int 32)) | |
4423 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4424 | "TARGET_EXTIMM" | |
4425 | "iilf\t%0,%o1" | |
9381e3f1 | 4426 | [(set_attr "op_type" "RIL") |
9fec758d | 4427 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4428 | |
9db1d521 HP |
4429 | ; |
4430 | ; extendsidi2 instruction pattern(s). | |
4431 | ; | |
4432 | ||
4023fb28 UW |
4433 | (define_expand "extendsidi2" |
4434 | [(set (match_operand:DI 0 "register_operand" "") | |
4435 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4436 | "" | |
4023fb28 | 4437 | { |
9602b6a1 | 4438 | if (!TARGET_ZARCH) |
4023fb28 | 4439 | { |
c41c1387 | 4440 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4441 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4442 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4443 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4444 | DONE; |
4445 | } | |
ec24698e | 4446 | }) |
4023fb28 UW |
4447 | |
4448 | (define_insn "*extendsidi2" | |
963fc8d0 | 4449 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4450 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4451 | "TARGET_ZARCH" |
9db1d521 | 4452 | "@ |
d40c829f | 4453 | lgfr\t%0,%1 |
963fc8d0 AK |
4454 | lgf\t%0,%1 |
4455 | lgfrl\t%0,%1" | |
4456 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4457 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4458 | (set_attr "cpu_facility" "*,*,z10") |
4459 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4460 | |
9db1d521 | 4461 | ; |
56477c21 | 4462 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4463 | ; |
4464 | ||
56477c21 AS |
4465 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4466 | [(set (match_operand:DSI 0 "register_operand" "") | |
4467 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4468 | "" |
4023fb28 | 4469 | { |
9602b6a1 | 4470 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4471 | { |
4472 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4473 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4474 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4475 | DONE; | |
4476 | } | |
ec24698e | 4477 | else if (!TARGET_EXTIMM) |
4023fb28 | 4478 | { |
2542ef05 | 4479 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4480 | |
4481 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4482 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4483 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4484 | DONE; |
4485 | } | |
ec24698e UW |
4486 | }) |
4487 | ||
56477c21 AS |
4488 | ; |
4489 | ; extendhidi2 instruction pattern(s). | |
4490 | ; | |
4491 | ||
ec24698e | 4492 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4493 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4494 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4495 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4496 | "@ |
4497 | lghr\t%0,%1 | |
963fc8d0 AK |
4498 | lgh\t%0,%1 |
4499 | lghrl\t%0,%1" | |
4500 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4501 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4502 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4503 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4504 | |
4505 | (define_insn "*extendhidi2" | |
9db1d521 | 4506 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4507 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4508 | "TARGET_ZARCH" |
d40c829f | 4509 | "lgh\t%0,%1" |
9381e3f1 WG |
4510 | [(set_attr "op_type" "RXY") |
4511 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4512 | |
9db1d521 | 4513 | ; |
56477c21 | 4514 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4515 | ; |
4516 | ||
ec24698e | 4517 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4518 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4519 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4520 | "TARGET_EXTIMM" |
4521 | "@ | |
4522 | lhr\t%0,%1 | |
4523 | lh\t%0,%1 | |
963fc8d0 AK |
4524 | lhy\t%0,%1 |
4525 | lhrl\t%0,%1" | |
4526 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4527 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4528 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4529 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4530 | |
4023fb28 | 4531 | (define_insn "*extendhisi2" |
d3632d41 UW |
4532 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4533 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4534 | "!TARGET_EXTIMM" |
d3632d41 | 4535 | "@ |
d40c829f UW |
4536 | lh\t%0,%1 |
4537 | lhy\t%0,%1" | |
9381e3f1 | 4538 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4539 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4540 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4541 | |
56477c21 AS |
4542 | ; |
4543 | ; extendqi(si|di)2 instruction pattern(s). | |
4544 | ; | |
4545 | ||
43a09b63 | 4546 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4547 | (define_insn "*extendqi<mode>2_extimm" |
4548 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4549 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4550 | "TARGET_EXTIMM" |
4551 | "@ | |
56477c21 AS |
4552 | l<g>br\t%0,%1 |
4553 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4554 | [(set_attr "op_type" "RRE,RXY") |
4555 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4556 | |
43a09b63 | 4557 | ; lb, lgb |
56477c21 AS |
4558 | (define_insn "*extendqi<mode>2" |
4559 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4560 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4561 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4562 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4563 | [(set_attr "op_type" "RXY") |
4564 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4565 | |
56477c21 AS |
4566 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4567 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4568 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4569 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4570 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4571 | "#" |
4572 | "&& reload_completed" | |
4023fb28 | 4573 | [(parallel |
56477c21 | 4574 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4575 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4576 | (parallel |
56477c21 | 4577 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4578 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4579 | { |
4580 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4581 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4582 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4583 | }) |
9db1d521 | 4584 | |
9db1d521 HP |
4585 | ; |
4586 | ; zero_extendsidi2 instruction pattern(s). | |
4587 | ; | |
4588 | ||
4023fb28 UW |
4589 | (define_expand "zero_extendsidi2" |
4590 | [(set (match_operand:DI 0 "register_operand" "") | |
4591 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4592 | "" | |
4023fb28 | 4593 | { |
9602b6a1 | 4594 | if (!TARGET_ZARCH) |
4023fb28 | 4595 | { |
c41c1387 | 4596 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4597 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4598 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4599 | DONE; |
4600 | } | |
ec24698e | 4601 | }) |
4023fb28 UW |
4602 | |
4603 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4604 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4605 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4606 | "TARGET_ZARCH" |
9db1d521 | 4607 | "@ |
d40c829f | 4608 | llgfr\t%0,%1 |
963fc8d0 AK |
4609 | llgf\t%0,%1 |
4610 | llgfrl\t%0,%1" | |
4611 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4612 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4613 | (set_attr "cpu_facility" "*,*,z10") |
4614 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4615 | |
288e517f AK |
4616 | ; |
4617 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4618 | ; | |
4619 | ||
d6083c7d UW |
4620 | (define_insn "*llgt_sidi" |
4621 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4622 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4623 | (const_int 2147483647)))] |
9602b6a1 | 4624 | "TARGET_ZARCH" |
d6083c7d | 4625 | "llgt\t%0,%1" |
9381e3f1 WG |
4626 | [(set_attr "op_type" "RXE") |
4627 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4628 | |
4629 | (define_insn_and_split "*llgt_sidi_split" | |
4630 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4631 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4632 | (const_int 2147483647))) |
ae156f85 | 4633 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4634 | "TARGET_ZARCH" |
d6083c7d UW |
4635 | "#" |
4636 | "&& reload_completed" | |
4637 | [(set (match_dup 0) | |
4638 | (and:DI (subreg:DI (match_dup 1) 0) | |
4639 | (const_int 2147483647)))] | |
4640 | "") | |
4641 | ||
288e517f AK |
4642 | (define_insn "*llgt_sisi" |
4643 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4644 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4645 | (const_int 2147483647)))] |
c4d50129 | 4646 | "TARGET_ZARCH" |
288e517f AK |
4647 | "@ |
4648 | llgtr\t%0,%1 | |
4649 | llgt\t%0,%1" | |
9381e3f1 WG |
4650 | [(set_attr "op_type" "RRE,RXE") |
4651 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4652 | |
288e517f AK |
4653 | (define_insn "*llgt_didi" |
4654 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4655 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4656 | (const_int 2147483647)))] | |
9602b6a1 | 4657 | "TARGET_ZARCH" |
288e517f AK |
4658 | "@ |
4659 | llgtr\t%0,%1 | |
4660 | llgt\t%0,%N1" | |
9381e3f1 WG |
4661 | [(set_attr "op_type" "RRE,RXE") |
4662 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4663 | |
f19a9af7 | 4664 | (define_split |
9602b6a1 AK |
4665 | [(set (match_operand:DSI 0 "register_operand" "") |
4666 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4667 | (const_int 2147483647))) |
ae156f85 | 4668 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4669 | "TARGET_ZARCH && reload_completed" |
288e517f | 4670 | [(set (match_dup 0) |
9602b6a1 | 4671 | (and:DSI (match_dup 1) |
f6ee577c | 4672 | (const_int 2147483647)))] |
288e517f AK |
4673 | "") |
4674 | ||
9db1d521 | 4675 | ; |
56477c21 | 4676 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4677 | ; |
4678 | ||
56477c21 AS |
4679 | (define_expand "zero_extend<mode>di2" |
4680 | [(set (match_operand:DI 0 "register_operand" "") | |
4681 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4682 | "" | |
4683 | { | |
9602b6a1 | 4684 | if (!TARGET_ZARCH) |
56477c21 AS |
4685 | { |
4686 | rtx tmp = gen_reg_rtx (SImode); | |
4687 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4688 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4689 | DONE; | |
4690 | } | |
4691 | else if (!TARGET_EXTIMM) | |
4692 | { | |
2542ef05 | 4693 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4694 | operands[1] = gen_lowpart (DImode, operands[1]); |
4695 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4696 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4697 | DONE; | |
4698 | } | |
4699 | }) | |
4700 | ||
f6ee577c | 4701 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4702 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4703 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4704 | "" |
4023fb28 | 4705 | { |
ec24698e UW |
4706 | if (!TARGET_EXTIMM) |
4707 | { | |
4708 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4709 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4710 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4711 | DONE; |
56477c21 | 4712 | } |
ec24698e UW |
4713 | }) |
4714 | ||
963fc8d0 AK |
4715 | ; llhrl, llghrl |
4716 | (define_insn "*zero_extendhi<mode>2_z10" | |
4717 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4718 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4719 | "TARGET_Z10" |
4720 | "@ | |
4721 | ll<g>hr\t%0,%1 | |
4722 | ll<g>h\t%0,%1 | |
4723 | ll<g>hrl\t%0,%1" | |
4724 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4725 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4726 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4727 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4728 | |
43a09b63 | 4729 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4730 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4731 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4732 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4733 | "TARGET_EXTIMM" |
4734 | "@ | |
56477c21 AS |
4735 | ll<g><hc>r\t%0,%1 |
4736 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4737 | [(set_attr "op_type" "RRE,RXY") |
4738 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4739 | |
43a09b63 | 4740 | ; llgh, llgc |
56477c21 AS |
4741 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4742 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4743 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4744 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4745 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4746 | [(set_attr "op_type" "RXY") |
4747 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4748 | |
4749 | (define_insn_and_split "*zero_extendhisi2_31" | |
4750 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4751 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4752 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4753 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4754 | "#" |
4755 | "&& reload_completed" | |
4756 | [(set (match_dup 0) (const_int 0)) | |
4757 | (parallel | |
4758 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4759 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4760 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4761 | |
cc7ab9b7 UW |
4762 | (define_insn_and_split "*zero_extendqisi2_31" |
4763 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4764 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4765 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4766 | "#" |
4767 | "&& reload_completed" | |
4768 | [(set (match_dup 0) (const_int 0)) | |
4769 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4770 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4771 | |
9db1d521 HP |
4772 | ; |
4773 | ; zero_extendqihi2 instruction pattern(s). | |
4774 | ; | |
4775 | ||
9db1d521 HP |
4776 | (define_expand "zero_extendqihi2" |
4777 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4778 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4779 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4780 | { |
4023fb28 UW |
4781 | operands[1] = gen_lowpart (HImode, operands[1]); |
4782 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4783 | DONE; | |
ec24698e | 4784 | }) |
9db1d521 | 4785 | |
4023fb28 | 4786 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4787 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4788 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4789 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4790 | "llgc\t%0,%1" |
9381e3f1 WG |
4791 | [(set_attr "op_type" "RXY") |
4792 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4793 | |
cc7ab9b7 UW |
4794 | (define_insn_and_split "*zero_extendqihi2_31" |
4795 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4796 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4797 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4798 | "#" |
4799 | "&& reload_completed" | |
4800 | [(set (match_dup 0) (const_int 0)) | |
4801 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4802 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4803 | |
609e7e80 | 4804 | ; |
9751ad6e | 4805 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4806 | ; |
4807 | ||
9751ad6e AK |
4808 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4809 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4810 | ; or emits the default pattern otherwise. | |
4811 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4812 | [(parallel |
9751ad6e AK |
4813 | [(set (match_operand:GPR 0 "register_operand" "") |
4814 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4815 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4816 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4817 | "TARGET_HARD_FLOAT" |
609e7e80 | 4818 | { |
65b1d8ea AK |
4819 | if (!TARGET_Z196) |
4820 | { | |
9751ad6e AK |
4821 | /* We don't provide emulation for TD|DD->SI. */ |
4822 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4823 | && <GPR:MODE>mode == SImode) | |
4824 | FAIL; | |
4825 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4826 | operands[1])); | |
65b1d8ea AK |
4827 | DONE; |
4828 | } | |
9751ad6e AK |
4829 | |
4830 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4831 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4832 | else | |
4833 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4834 | }) |
4835 | ||
9751ad6e AK |
4836 | ; (sf|df|tf)->unsigned (si|di) |
4837 | ||
4838 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4839 | ; machines. | |
4840 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4841 | [(parallel | |
4842 | [(set (match_operand:GPR 0 "register_operand" "") | |
4843 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4844 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4845 | (clobber (reg:CC CC_REGNUM))])] | |
4846 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4847 | { | |
4848 | rtx_code_label *label1 = gen_label_rtx (); | |
4849 | rtx_code_label *label2 = gen_label_rtx (); | |
4850 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4851 | REAL_VALUE_TYPE cmp, sub; | |
4852 | ||
4853 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4854 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4855 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4856 | ||
4857 | emit_cmp_and_jump_insns (operands[1], | |
4858 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4859 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4860 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4861 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4862 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4863 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
4864 | emit_jump (label2); | |
4865 | ||
4866 | emit_label (label1); | |
4867 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4868 | operands[1], | |
4869 | GEN_INT (BFP_RND_TOWARD_0))); | |
4870 | emit_label (label2); | |
4871 | DONE; | |
4872 | }) | |
4873 | ||
4874 | ; dd->unsigned di | |
4875 | ||
4876 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4877 | ; machines. | |
4878 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
4879 | [(parallel |
4880 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 4881 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 4882 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4883 | (clobber (reg:CC CC_REGNUM))])] |
4884 | ||
9751ad6e | 4885 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 4886 | { |
9751ad6e AK |
4887 | rtx_code_label *label1 = gen_label_rtx (); |
4888 | rtx_code_label *label2 = gen_label_rtx (); | |
4889 | rtx temp = gen_reg_rtx (TDmode); | |
4890 | REAL_VALUE_TYPE cmp, sub; | |
4891 | ||
4892 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4893 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4894 | ||
4895 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4896 | solution is doing the check and the subtraction in TD mode and using a | |
4897 | TD -> DI convert afterwards. */ | |
4898 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4899 | temp = force_reg (TDmode, temp); | |
4900 | emit_cmp_and_jump_insns (temp, | |
4901 | const_double_from_real_value (cmp, TDmode), | |
4902 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4903 | emit_insn (gen_subtd3 (temp, temp, | |
4904 | const_double_from_real_value (sub, TDmode))); | |
4905 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4906 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4907 | emit_jump (label2); | |
4908 | ||
4909 | emit_label (label1); | |
4910 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
4911 | GEN_INT (DFP_RND_TOWARD_0))); | |
4912 | emit_label (label2); | |
4913 | DONE; | |
609e7e80 | 4914 | }) |
cc7ab9b7 | 4915 | |
9751ad6e | 4916 | ; td->unsigned di |
9db1d521 | 4917 | |
9751ad6e AK |
4918 | ; Emulate the unsigned conversion with the signed version for pre z196 |
4919 | ; machines. | |
4920 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 4921 | [(parallel |
9751ad6e AK |
4922 | [(set (match_operand:DI 0 "register_operand" "") |
4923 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4924 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 4925 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4926 | |
4927 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 4928 | { |
9751ad6e AK |
4929 | rtx_code_label *label1 = gen_label_rtx (); |
4930 | rtx_code_label *label2 = gen_label_rtx (); | |
4931 | rtx temp = gen_reg_rtx (TDmode); | |
4932 | REAL_VALUE_TYPE cmp, sub; | |
4933 | ||
4934 | operands[1] = force_reg (TDmode, operands[1]); | |
4935 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4936 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4937 | ||
4938 | emit_cmp_and_jump_insns (operands[1], | |
4939 | const_double_from_real_value (cmp, TDmode), | |
4940 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4941 | emit_insn (gen_subtd3 (temp, operands[1], | |
4942 | const_double_from_real_value (sub, TDmode))); | |
4943 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4944 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4945 | emit_jump (label2); | |
4946 | ||
4947 | emit_label (label1); | |
4948 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
4949 | GEN_INT (DFP_RND_TOWARD_0))); | |
4950 | emit_label (label2); | |
4951 | DONE; | |
10bbf137 | 4952 | }) |
9db1d521 | 4953 | |
9751ad6e AK |
4954 | ; Just a dummy to make the code in the first expander a bit easier. |
4955 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
4956 | [(parallel |
4957 | [(set (match_operand:SI 0 "register_operand" "") | |
4958 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 4959 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4960 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4961 | |
4962 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
4963 | { | |
4964 | FAIL; | |
4965 | }) | |
4966 | ||
65b1d8ea AK |
4967 | |
4968 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4969 | ||
9751ad6e AK |
4970 | ; df -> unsigned di |
4971 | (define_insn "*fixuns_truncdfdi2_vx" | |
6e5b5de8 AK |
4972 | [(set (match_operand:DI 0 "register_operand" "=d,v") |
4973 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4974 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4975 | (clobber (reg:CC CC_REGNUM))] | |
9751ad6e AK |
4976 | "TARGET_VX && TARGET_HARD_FLOAT" |
4977 | "@ | |
4978 | clgdbr\t%0,%h2,%1,0 | |
4979 | wclgdb\t%v0,%v1,0,%h2" | |
4980 | [(set_attr "op_type" "RRF,VRR") | |
4981 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 4982 | |
9751ad6e | 4983 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
4984 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4985 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4986 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4987 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4988 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4989 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 4990 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 4991 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 4992 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
4993 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
4994 | [(set_attr "op_type" "RRF") | |
4995 | (set_attr "type" "ftoi")]) | |
4996 | ||
b60cb710 AK |
4997 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4998 | [(set (match_operand:GPR 0 "register_operand" "") | |
4999 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
5000 | "TARGET_HARD_FLOAT" | |
9db1d521 | 5001 | { |
b60cb710 | 5002 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 5003 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 5004 | DONE; |
10bbf137 | 5005 | }) |
9db1d521 | 5006 | |
6e5b5de8 AK |
5007 | (define_insn "*fix_truncdfdi2_bfp_z13" |
5008 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
5009 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5010 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5011 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 5012 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5013 | "@ |
5014 | cgdbr\t%0,%h2,%1 | |
5015 | wcgdb\t%v0,%v1,0,%h2" | |
5016 | [(set_attr "op_type" "RRE,VRR") | |
5017 | (set_attr "type" "ftoi")]) | |
5018 | ||
43a09b63 | 5019 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
5020 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5021 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5022 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5023 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 5024 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
5025 | "TARGET_HARD_FLOAT |
5026 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 5027 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 5028 | [(set_attr "op_type" "RRE") |
077dab3b | 5029 | (set_attr "type" "ftoi")]) |
9db1d521 | 5030 | |
6e5b5de8 AK |
5031 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5032 | [(parallel | |
5033 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5034 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5035 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5036 | (clobber (reg:CC CC_REGNUM))])] | |
5037 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
5038 | ; |
5039 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
5040 | ; | |
5041 | ||
99cd7dd0 AK |
5042 | (define_expand "fix_trunc<mode>di2" |
5043 | [(set (match_operand:DI 0 "register_operand" "") | |
5044 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 5045 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
5046 | { |
5047 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
5048 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 5049 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
5050 | DONE; |
5051 | }) | |
5052 | ||
609e7e80 | 5053 | ; cgxtr, cgdtr |
99cd7dd0 | 5054 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
5055 | [(set (match_operand:DI 0 "register_operand" "=d") |
5056 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
5057 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5058 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5059 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5060 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5061 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5062 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5063 | |
5064 | ||
f61a2c7d AK |
5065 | ; |
5066 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5067 | ; | |
5068 | ||
5069 | (define_expand "fix_trunctf<mode>2" | |
5070 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5071 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5072 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5073 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5074 | "TARGET_HARD_FLOAT" |
142cd70f | 5075 | "") |
9db1d521 | 5076 | |
9db1d521 | 5077 | |
9db1d521 | 5078 | ; |
142cd70f | 5079 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5080 | ; |
5081 | ||
609e7e80 | 5082 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5083 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5084 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5085 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5086 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5087 | "@ |
5088 | c<xde>g<bt>r\t%0,%1 | |
5089 | wcdgb\t%v0,%v1,0,0" | |
5090 | [(set_attr "op_type" "RRE,VRR") | |
5091 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5092 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5093 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5094 | |
43a09b63 | 5095 | ; cxfbr, cdfbr, cefbr |
142cd70f | 5096 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
5097 | [(set (match_operand:BFP 0 "register_operand" "=f") |
5098 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 5099 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
5100 | "c<xde>fbr\t%0,%1" |
5101 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 5102 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 5103 | |
65b1d8ea AK |
5104 | ; cxftr, cdftr |
5105 | (define_insn "floatsi<mode>2" | |
5106 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5107 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5108 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5109 | "c<xde>ftr\t%0,0,%1,0" | |
5110 | [(set_attr "op_type" "RRE") | |
5111 | (set_attr "type" "itof<mode>" )]) | |
5112 | ||
5113 | ; | |
5114 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5115 | ; | |
5116 | ||
6e5b5de8 AK |
5117 | (define_insn "*floatunsdidf2_z13" |
5118 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
5119 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
a579871b | 5120 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5121 | "@ |
5122 | cdlgbr\t%0,0,%1,0 | |
5123 | wcdlgb\t%v0,%v1,0,0" | |
5124 | [(set_attr "op_type" "RRE,VRR") | |
5125 | (set_attr "type" "itofdf")]) | |
5126 | ||
65b1d8ea AK |
5127 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5128 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5129 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5130 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5131 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5132 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5133 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5134 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5135 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5136 | (set_attr "type" "itof<FP:mode>")]) |
5137 | ||
5138 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5139 | [(set (match_operand:FP 0 "register_operand" "") | |
5140 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5141 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5142 | |
9db1d521 HP |
5143 | ; |
5144 | ; truncdfsf2 instruction pattern(s). | |
5145 | ; | |
5146 | ||
142cd70f | 5147 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5148 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5149 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5150 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5151 | "@ |
5152 | ledbr\t%0,%1 | |
5153 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5154 | ; According to BFP rounding mode | |
5155 | [(set_attr "op_type" "RRE,VRR") | |
5156 | (set_attr "type" "ftruncdf") | |
285363a1 | 5157 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5158 | |
f61a2c7d | 5159 | ; |
142cd70f | 5160 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5161 | ; |
5162 | ||
142cd70f AK |
5163 | ; ldxbr, lexbr |
5164 | (define_insn "trunctf<mode>2" | |
5165 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5166 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5167 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5168 | "TARGET_HARD_FLOAT" |
5169 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5170 | [(set_attr "length" "6") |
9381e3f1 | 5171 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5172 | |
609e7e80 AK |
5173 | ; |
5174 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5175 | ; | |
5176 | ||
432d4670 AK |
5177 | |
5178 | (define_expand "trunctddd2" | |
5179 | [(parallel | |
5180 | [(set (match_operand:DD 0 "register_operand" "") | |
5181 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5182 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5183 | (clobber (scratch:TD))])] | |
5184 | "TARGET_HARD_DFP") | |
5185 | ||
5186 | (define_insn "*trunctddd2" | |
609e7e80 | 5187 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5188 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5189 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5190 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5191 | "TARGET_HARD_DFP" |
432d4670 | 5192 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5193 | [(set_attr "length" "6") |
9381e3f1 | 5194 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5195 | |
5196 | (define_insn "truncddsd2" | |
5197 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5198 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5199 | "TARGET_HARD_DFP" |
609e7e80 AK |
5200 | "ledtr\t%0,0,%1,0" |
5201 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5202 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5203 | |
feade5a8 AK |
5204 | (define_expand "trunctdsd2" |
5205 | [(parallel | |
d5a216fa | 5206 | [(set (match_dup 2) |
feade5a8 | 5207 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5208 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5209 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5210 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5211 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5212 | "TARGET_HARD_DFP" |
5213 | { | |
d5a216fa | 5214 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5215 | }) |
5216 | ||
9db1d521 | 5217 | ; |
142cd70f | 5218 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5219 | ; |
5220 | ||
2de2b3f9 | 5221 | ; wflls |
6e5b5de8 AK |
5222 | (define_insn "*extendsfdf2_z13" |
5223 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5224 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5225 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5226 | "@ |
5227 | ldebr\t%0,%1 | |
5228 | ldeb\t%0,%1 | |
5229 | wldeb\t%v0,%v1" | |
5230 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5231 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5232 | ||
142cd70f | 5233 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5234 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5235 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5236 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5237 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5238 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5239 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5240 | "@ |
142cd70f AK |
5241 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5242 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5243 | [(set_attr "op_type" "RRE,RXE") |
5244 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5245 | ||
5246 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5247 | [(set (match_operand:BFP 0 "register_operand" "") | |
5248 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5249 | "TARGET_HARD_FLOAT | |
5250 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5251 | |
609e7e80 AK |
5252 | ; |
5253 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5254 | ; | |
5255 | ||
5256 | (define_insn "extendddtd2" | |
5257 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5258 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5259 | "TARGET_HARD_DFP" |
609e7e80 AK |
5260 | "lxdtr\t%0,%1,0" |
5261 | [(set_attr "op_type" "RRF") | |
5262 | (set_attr "type" "fsimptf")]) | |
5263 | ||
5264 | (define_insn "extendsddd2" | |
5265 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5266 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5267 | "TARGET_HARD_DFP" |
609e7e80 AK |
5268 | "ldetr\t%0,%1,0" |
5269 | [(set_attr "op_type" "RRF") | |
5270 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5271 | |
feade5a8 AK |
5272 | (define_expand "extendsdtd2" |
5273 | [(set (match_dup 2) | |
5274 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5275 | (set (match_operand:TD 0 "register_operand" "") | |
5276 | (float_extend:TD (match_dup 2)))] | |
5277 | "TARGET_HARD_DFP" | |
5278 | { | |
5279 | operands[2] = gen_reg_rtx (DDmode); | |
5280 | }) | |
5281 | ||
d12a76f3 AK |
5282 | ; Binary Floating Point - load fp integer |
5283 | ||
5284 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5285 | ; For all of them the inexact exceptions are suppressed. | |
5286 | ||
5287 | ; fiebra, fidbra, fixbra | |
5288 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5289 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5290 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5291 | FPINT))] | |
5292 | "TARGET_Z196" | |
5293 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5294 | [(set_attr "op_type" "RRF") | |
5295 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5296 | ||
5297 | ; rint is supposed to raise an inexact exception so we can use the | |
5298 | ; older instructions. | |
5299 | ||
5300 | ; fiebr, fidbr, fixbr | |
5301 | (define_insn "rint<BFP:mode>2" | |
5302 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5303 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5304 | UNSPEC_FPINT_RINT))] | |
5305 | "" | |
5306 | "fi<BFP:xde>br\t%0,0,%1" | |
5307 | [(set_attr "op_type" "RRF") | |
5308 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5309 | ||
5310 | ||
5311 | ; Decimal Floating Point - load fp integer | |
5312 | ||
5313 | ; fidtr, fixtr | |
5314 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5315 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5316 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5317 | FPINT))] | |
5318 | "TARGET_HARD_DFP" | |
5319 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5320 | [(set_attr "op_type" "RRF") | |
5321 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5322 | ||
5323 | ; fidtr, fixtr | |
5324 | (define_insn "rint<DFP:mode>2" | |
5325 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5326 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5327 | UNSPEC_FPINT_RINT))] | |
5328 | "TARGET_HARD_DFP" | |
5329 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5330 | [(set_attr "op_type" "RRF") | |
5331 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5332 | ||
5333 | ; | |
35dd9a0e AK |
5334 | ; Binary <-> Decimal floating point trunc patterns |
5335 | ; | |
5336 | ||
5337 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5338 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5339 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5340 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5341 | (clobber (reg:CC CC_REGNUM)) |
5342 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5343 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5344 | "pfpo") |
5345 | ||
5346 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5347 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5348 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5349 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5350 | (clobber (reg:CC CC_REGNUM)) |
5351 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5352 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5353 | "pfpo") |
5354 | ||
5355 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5356 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5357 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5358 | (parallel | |
5359 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5360 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5361 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5362 | (clobber (reg:CC CC_REGNUM)) |
5363 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5364 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5365 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5366 | "TARGET_HARD_DFP |
35dd9a0e AK |
5367 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5368 | { | |
5369 | HOST_WIDE_INT flags; | |
5370 | ||
5371 | flags = (PFPO_CONVERT | | |
5372 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5373 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5374 | ||
5375 | operands[2] = GEN_INT (flags); | |
5376 | }) | |
5377 | ||
5378 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5379 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5380 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5381 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5382 | (parallel | |
2cf4c39e | 5383 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5384 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5385 | (clobber (reg:CC CC_REGNUM)) |
5386 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5387 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5388 | "TARGET_HARD_DFP |
35dd9a0e AK |
5389 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5390 | { | |
5391 | HOST_WIDE_INT flags; | |
5392 | ||
5393 | flags = (PFPO_CONVERT | | |
5394 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5395 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5396 | ||
5397 | operands[2] = GEN_INT (flags); | |
5398 | }) | |
5399 | ||
5400 | ; | |
5401 | ; Binary <-> Decimal floating point extend patterns | |
5402 | ; | |
5403 | ||
5404 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5405 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5406 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5407 | (clobber (reg:CC CC_REGNUM)) |
5408 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5409 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5410 | "pfpo") |
5411 | ||
5412 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5413 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5414 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5415 | (clobber (reg:CC CC_REGNUM)) |
5416 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5417 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5418 | "pfpo") |
5419 | ||
5420 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5421 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5422 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5423 | (parallel | |
5424 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5425 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5426 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5427 | (clobber (reg:CC CC_REGNUM)) |
5428 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5429 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5430 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5431 | "TARGET_HARD_DFP |
35dd9a0e AK |
5432 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5433 | { | |
5434 | HOST_WIDE_INT flags; | |
5435 | ||
5436 | flags = (PFPO_CONVERT | | |
5437 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5438 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5439 | ||
5440 | operands[2] = GEN_INT (flags); | |
5441 | }) | |
5442 | ||
5443 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5444 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5445 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5446 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5447 | (parallel | |
2cf4c39e | 5448 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5449 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5450 | (clobber (reg:CC CC_REGNUM)) |
5451 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5452 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5453 | "TARGET_HARD_DFP |
35dd9a0e AK |
5454 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5455 | { | |
5456 | HOST_WIDE_INT flags; | |
5457 | ||
5458 | flags = (PFPO_CONVERT | | |
5459 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5460 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5461 | ||
5462 | operands[2] = GEN_INT (flags); | |
5463 | }) | |
5464 | ||
5465 | ||
9db1d521 | 5466 | ;; |
fae778eb | 5467 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5468 | ;; |
fae778eb | 5469 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5470 | ; because of unpredictable Bits in Register for Halfword and Byte |
5471 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5472 | ||
07893d4f UW |
5473 | ;; |
5474 | ;;- Add instructions. | |
5475 | ;; | |
5476 | ||
1c7b1b7e UW |
5477 | ; |
5478 | ; addti3 instruction pattern(s). | |
5479 | ; | |
5480 | ||
085261c8 AK |
5481 | (define_expand "addti3" |
5482 | [(parallel | |
5483 | [(set (match_operand:TI 0 "register_operand" "") | |
5484 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5485 | (match_operand:TI 2 "general_operand" "") ) ) | |
5486 | (clobber (reg:CC CC_REGNUM))])] | |
5487 | "TARGET_ZARCH" | |
5488 | { | |
5489 | /* For z13 we have vaq which doesn't set CC. */ | |
5490 | if (TARGET_VX) | |
5491 | { | |
5492 | emit_insn (gen_rtx_SET (operands[0], | |
5493 | gen_rtx_PLUS (TImode, | |
5494 | copy_to_mode_reg (TImode, operands[1]), | |
5495 | copy_to_mode_reg (TImode, operands[2])))); | |
5496 | DONE; | |
5497 | } | |
5498 | }) | |
5499 | ||
5500 | (define_insn_and_split "*addti3" | |
5501 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5502 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5503 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5504 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5505 | "TARGET_ZARCH" |
1c7b1b7e UW |
5506 | "#" |
5507 | "&& reload_completed" | |
5508 | [(parallel | |
ae156f85 | 5509 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5510 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5511 | (match_dup 7))) | |
5512 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5513 | (parallel | |
a94a76a7 UW |
5514 | [(set (match_dup 3) (plus:DI |
5515 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5516 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5517 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5518 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5519 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5520 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5521 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5522 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5523 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5524 | [(set_attr "op_type" "*") | |
5525 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5526 | |
07893d4f UW |
5527 | ; |
5528 | ; adddi3 instruction pattern(s). | |
5529 | ; | |
5530 | ||
3298c037 AK |
5531 | (define_expand "adddi3" |
5532 | [(parallel | |
963fc8d0 | 5533 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5534 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5535 | (match_operand:DI 2 "general_operand" ""))) | |
5536 | (clobber (reg:CC CC_REGNUM))])] | |
5537 | "" | |
5538 | "") | |
5539 | ||
07893d4f UW |
5540 | (define_insn "*adddi3_sign" |
5541 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5542 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5543 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5544 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5545 | "TARGET_ZARCH" |
07893d4f | 5546 | "@ |
d40c829f UW |
5547 | agfr\t%0,%2 |
5548 | agf\t%0,%2" | |
65b1d8ea AK |
5549 | [(set_attr "op_type" "RRE,RXY") |
5550 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5551 | |
5552 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5553 | [(set (reg CC_REGNUM) |
3e4be43f | 5554 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5555 | (match_operand:DI 1 "register_operand" "0,0")) |
5556 | (const_int 0))) | |
5557 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5558 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5559 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5560 | "@ |
d40c829f UW |
5561 | algfr\t%0,%2 |
5562 | algf\t%0,%2" | |
9381e3f1 WG |
5563 | [(set_attr "op_type" "RRE,RXY") |
5564 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5565 | |
5566 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5567 | [(set (reg CC_REGNUM) |
3e4be43f | 5568 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5569 | (match_operand:DI 1 "register_operand" "0,0")) |
5570 | (const_int 0))) | |
5571 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5572 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5573 | "@ |
d40c829f UW |
5574 | algfr\t%0,%2 |
5575 | algf\t%0,%2" | |
9381e3f1 WG |
5576 | [(set_attr "op_type" "RRE,RXY") |
5577 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5578 | |
5579 | (define_insn "*adddi3_zero" | |
5580 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5581 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5582 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5583 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5584 | "TARGET_ZARCH" |
07893d4f | 5585 | "@ |
d40c829f UW |
5586 | algfr\t%0,%2 |
5587 | algf\t%0,%2" | |
9381e3f1 WG |
5588 | [(set_attr "op_type" "RRE,RXY") |
5589 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5590 | |
e69166de | 5591 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5592 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5593 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5594 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5595 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5596 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5597 | "#" |
5598 | "&& reload_completed" | |
5599 | [(parallel | |
ae156f85 | 5600 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5601 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5602 | (match_dup 7))) | |
5603 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5604 | (parallel | |
a94a76a7 UW |
5605 | [(set (match_dup 3) (plus:SI |
5606 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5607 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5608 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5609 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5610 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5611 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5612 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5613 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5614 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5615 | |
07893d4f | 5616 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 5617 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 5618 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 5619 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5620 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5621 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5622 | "#" |
5623 | "&& reload_completed" | |
5624 | [(parallel | |
5625 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5626 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5627 | (parallel |
ae156f85 | 5628 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
5629 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5630 | (match_dup 7))) | |
5631 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5632 | (set (pc) | |
ae156f85 | 5633 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5634 | (pc) |
5635 | (label_ref (match_dup 9)))) | |
5636 | (parallel | |
5637 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 5638 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5639 | (match_dup 9)] |
97c6f7ad UW |
5640 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5641 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5642 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5643 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5644 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5645 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5646 | operands[9] = gen_label_rtx ();") |
9db1d521 | 5647 | |
3298c037 AK |
5648 | ; |
5649 | ; addsi3 instruction pattern(s). | |
5650 | ; | |
5651 | ||
5652 | (define_expand "addsi3" | |
07893d4f | 5653 | [(parallel |
963fc8d0 | 5654 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5655 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5656 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5657 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5658 | "" |
07893d4f | 5659 | "") |
9db1d521 | 5660 | |
3298c037 AK |
5661 | (define_insn "*addsi3_sign" |
5662 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5663 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5664 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5665 | (clobber (reg:CC CC_REGNUM))] | |
5666 | "" | |
5667 | "@ | |
5668 | ah\t%0,%2 | |
5669 | ahy\t%0,%2" | |
65b1d8ea | 5670 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5671 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5672 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5673 | |
9db1d521 | 5674 | ; |
3298c037 | 5675 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5676 | ; |
9db1d521 | 5677 | |
65b1d8ea | 5678 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5679 | (define_insn "*add<mode>3" |
3e4be43f UW |
5680 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5681 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5682 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5683 | (clobber (reg:CC CC_REGNUM))] |
5684 | "" | |
ec24698e | 5685 | "@ |
3298c037 | 5686 | a<g>r\t%0,%2 |
65b1d8ea | 5687 | a<g>rk\t%0,%1,%2 |
3298c037 | 5688 | a<g>hi\t%0,%h2 |
65b1d8ea | 5689 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5690 | al<g>fi\t%0,%2 |
5691 | sl<g>fi\t%0,%n2 | |
5692 | a<g>\t%0,%2 | |
963fc8d0 AK |
5693 | a<y>\t%0,%2 |
5694 | a<g>si\t%0,%c2" | |
65b1d8ea | 5695 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5696 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5697 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5698 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5699 | |
65b1d8ea | 5700 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5701 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5702 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5703 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5704 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5705 | (match_dup 1))) |
65b1d8ea | 5706 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5707 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5708 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5709 | "@ |
3298c037 | 5710 | al<g>r\t%0,%2 |
65b1d8ea | 5711 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5712 | al<g>fi\t%0,%2 |
5713 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5714 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5715 | al<g>\t%0,%2 |
963fc8d0 AK |
5716 | al<y>\t%0,%2 |
5717 | al<g>si\t%0,%c2" | |
65b1d8ea | 5718 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5719 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5720 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5721 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5722 | |
65b1d8ea | 5723 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5724 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5725 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5726 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5727 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5728 | (match_dup 1))) |
65b1d8ea | 5729 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5730 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5731 | "@ |
3298c037 | 5732 | al<g>r\t%0,%2 |
65b1d8ea | 5733 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5734 | al<g>\t%0,%2 |
5735 | al<y>\t%0,%2" | |
65b1d8ea | 5736 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5737 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5738 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5739 | |
65b1d8ea | 5740 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5741 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5742 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5743 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5744 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5745 | (match_dup 2))) |
3e4be43f | 5746 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5747 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5748 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5749 | "@ |
3298c037 | 5750 | al<g>r\t%0,%2 |
65b1d8ea | 5751 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5752 | al<g>fi\t%0,%2 |
5753 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5754 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5755 | al<g>\t%0,%2 |
963fc8d0 AK |
5756 | al<y>\t%0,%2 |
5757 | al<g>si\t%0,%c2" | |
65b1d8ea | 5758 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5759 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5760 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5761 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5762 | |
65b1d8ea | 5763 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5764 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5765 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5766 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5767 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5768 | (match_dup 2))) |
65b1d8ea | 5769 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5770 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5771 | "@ |
3298c037 | 5772 | al<g>r\t%0,%2 |
65b1d8ea | 5773 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5774 | al<g>\t%0,%2 |
5775 | al<y>\t%0,%2" | |
65b1d8ea | 5776 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5777 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5778 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5779 | |
65b1d8ea | 5780 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5781 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5782 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5783 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5784 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5785 | (const_int 0))) |
3e4be43f | 5786 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5787 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5788 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5789 | "@ |
3298c037 | 5790 | al<g>r\t%0,%2 |
65b1d8ea | 5791 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5792 | al<g>fi\t%0,%2 |
5793 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5794 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5795 | al<g>\t%0,%2 |
963fc8d0 AK |
5796 | al<y>\t%0,%2 |
5797 | al<g>si\t%0,%c2" | |
65b1d8ea | 5798 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5799 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5800 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5801 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5802 | |
65b1d8ea | 5803 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5804 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5805 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5806 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5807 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5808 | (const_int 0))) |
65b1d8ea | 5809 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5810 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5811 | "@ |
3298c037 | 5812 | al<g>r\t%0,%2 |
65b1d8ea | 5813 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5814 | al<g>\t%0,%2 |
5815 | al<y>\t%0,%2" | |
65b1d8ea | 5816 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5817 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5818 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5819 | |
65b1d8ea | 5820 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5821 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5822 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5823 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5824 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5825 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5826 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5827 | "@ |
3298c037 | 5828 | al<g>r\t%0,%2 |
65b1d8ea | 5829 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5830 | al<g>\t%0,%2 |
5831 | al<y>\t%0,%2" | |
65b1d8ea | 5832 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5833 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5834 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5835 | |
963fc8d0 | 5836 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5837 | (define_insn "*add<mode>3_imm_cc" |
5838 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5839 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5840 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5841 | (const_int 0))) |
3e4be43f | 5842 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5843 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5844 | "s390_match_ccmode (insn, CCAmode) | |
5845 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5846 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5847 | /* Avoid INT32_MIN on 32 bit. */ | |
5848 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5849 | "@ |
3298c037 | 5850 | a<g>hi\t%0,%h2 |
65b1d8ea | 5851 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5852 | a<g>fi\t%0,%2 |
5853 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5854 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5855 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5856 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5857 | |
7d2fd075 AK |
5858 | (define_insn "*adddi3_sign" |
5859 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5860 | (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
5861 | (match_operand:DI 1 "register_operand" "0"))) | |
5862 | (clobber (reg:CC CC_REGNUM))] | |
5863 | "TARGET_ARCH12" | |
5864 | "agh\t%0,%2" | |
5865 | [(set_attr "op_type" "RXY")]) | |
5866 | ||
9db1d521 | 5867 | ; |
609e7e80 | 5868 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5869 | ; |
5870 | ||
609e7e80 | 5871 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5872 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5873 | (define_insn "add<mode>3" |
2de2b3f9 AK |
5874 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
5875 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
5876 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 5877 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5878 | "TARGET_HARD_FLOAT" |
9db1d521 | 5879 | "@ |
62d3f261 AK |
5880 | a<xde>tr\t%0,%1,%2 |
5881 | a<xde>br\t%0,%2 | |
6e5b5de8 | 5882 | a<xde>b\t%0,%2 |
2de2b3f9 AK |
5883 | wfadb\t%v0,%v1,%v2 |
5884 | wfasb\t%v0,%v1,%v2" | |
5885 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 5886 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
5887 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
5888 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 5889 | |
609e7e80 | 5890 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5891 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5892 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5893 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5894 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5895 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5896 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5897 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5898 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5899 | "@ |
62d3f261 AK |
5900 | a<xde>tr\t%0,%1,%2 |
5901 | a<xde>br\t%0,%2 | |
f61a2c7d | 5902 | a<xde>b\t%0,%2" |
62d3f261 AK |
5903 | [(set_attr "op_type" "RRF,RRE,RXE") |
5904 | (set_attr "type" "fsimp<mode>") | |
5905 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5906 | |
609e7e80 | 5907 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5908 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5909 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5910 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5911 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5912 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5913 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5914 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5915 | "@ |
62d3f261 AK |
5916 | a<xde>tr\t%0,%1,%2 |
5917 | a<xde>br\t%0,%2 | |
f61a2c7d | 5918 | a<xde>b\t%0,%2" |
62d3f261 AK |
5919 | [(set_attr "op_type" "RRF,RRE,RXE") |
5920 | (set_attr "type" "fsimp<mode>") | |
5921 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5922 | |
72a4ddf2 AK |
5923 | ; |
5924 | ; Pointer add instruction patterns | |
5925 | ; | |
5926 | ||
5927 | ; This will match "*la_64" | |
5928 | (define_expand "addptrdi3" | |
5929 | [(set (match_operand:DI 0 "register_operand" "") | |
5930 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5931 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5932 | "TARGET_64BIT" | |
5933 | { | |
72a4ddf2 AK |
5934 | if (GET_CODE (operands[2]) == CONST_INT) |
5935 | { | |
357ddc7d TV |
5936 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5937 | ||
72a4ddf2 AK |
5938 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5939 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5940 | { | |
5941 | operands[2] = force_const_mem (DImode, operands[2]); | |
5942 | operands[2] = force_reg (DImode, operands[2]); | |
5943 | } | |
5944 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5945 | operands[2] = force_reg (DImode, operands[2]); | |
5946 | } | |
5947 | }) | |
5948 | ||
5949 | ; For 31 bit we have to prevent the generated pattern from matching | |
5950 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5951 | ; match "force_la_31". | |
5952 | (define_expand "addptrsi3" | |
5953 | [(parallel | |
5954 | [(set (match_operand:SI 0 "register_operand" "") | |
5955 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5956 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5957 | (use (const_int 0))])] | |
5958 | "!TARGET_64BIT" | |
5959 | { | |
72a4ddf2 AK |
5960 | if (GET_CODE (operands[2]) == CONST_INT) |
5961 | { | |
357ddc7d TV |
5962 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5963 | ||
72a4ddf2 AK |
5964 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5965 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5966 | { | |
5967 | operands[2] = force_const_mem (SImode, operands[2]); | |
5968 | operands[2] = force_reg (SImode, operands[2]); | |
5969 | } | |
5970 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5971 | operands[2] = force_reg (SImode, operands[2]); | |
5972 | } | |
5973 | }) | |
9db1d521 HP |
5974 | |
5975 | ;; | |
5976 | ;;- Subtract instructions. | |
5977 | ;; | |
5978 | ||
1c7b1b7e UW |
5979 | ; |
5980 | ; subti3 instruction pattern(s). | |
5981 | ; | |
5982 | ||
085261c8 AK |
5983 | (define_expand "subti3" |
5984 | [(parallel | |
5985 | [(set (match_operand:TI 0 "register_operand" "") | |
5986 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5987 | (match_operand:TI 2 "general_operand" "") ) ) | |
5988 | (clobber (reg:CC CC_REGNUM))])] | |
5989 | "TARGET_ZARCH" | |
5990 | { | |
2d71f118 | 5991 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
5992 | if (TARGET_VX) |
5993 | { | |
5994 | emit_insn (gen_rtx_SET (operands[0], | |
5995 | gen_rtx_MINUS (TImode, | |
5996 | operands[1], | |
5997 | copy_to_mode_reg (TImode, operands[2])))); | |
5998 | DONE; | |
5999 | } | |
6000 | }) | |
6001 | ||
6002 | (define_insn_and_split "*subti3" | |
6003 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
6004 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
6005 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 6006 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6007 | "TARGET_ZARCH" |
1c7b1b7e UW |
6008 | "#" |
6009 | "&& reload_completed" | |
6010 | [(parallel | |
ae156f85 | 6011 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
6012 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
6013 | (match_dup 7))) | |
6014 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
6015 | (parallel | |
6016 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6017 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6018 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
6019 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
6020 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
6021 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
6022 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
6023 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
6024 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
6025 | [(set_attr "op_type" "*") | |
6026 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 6027 | |
9db1d521 HP |
6028 | ; |
6029 | ; subdi3 instruction pattern(s). | |
6030 | ; | |
6031 | ||
3298c037 AK |
6032 | (define_expand "subdi3" |
6033 | [(parallel | |
6034 | [(set (match_operand:DI 0 "register_operand" "") | |
6035 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
6036 | (match_operand:DI 2 "general_operand" ""))) | |
6037 | (clobber (reg:CC CC_REGNUM))])] | |
6038 | "" | |
6039 | "") | |
6040 | ||
07893d4f UW |
6041 | (define_insn "*subdi3_sign" |
6042 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6043 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6044 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6045 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6046 | "TARGET_ZARCH" |
07893d4f | 6047 | "@ |
d40c829f UW |
6048 | sgfr\t%0,%2 |
6049 | sgf\t%0,%2" | |
9381e3f1 | 6050 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
6051 | (set_attr "z10prop" "z10_c,*") |
6052 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
6053 | |
6054 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 6055 | [(set (reg CC_REGNUM) |
07893d4f | 6056 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6057 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6058 | (const_int 0))) |
6059 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6060 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 6061 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6062 | "@ |
d40c829f UW |
6063 | slgfr\t%0,%2 |
6064 | slgf\t%0,%2" | |
9381e3f1 WG |
6065 | [(set_attr "op_type" "RRE,RXY") |
6066 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6067 | |
6068 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 6069 | [(set (reg CC_REGNUM) |
07893d4f | 6070 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6071 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6072 | (const_int 0))) |
6073 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6074 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6075 | "@ |
d40c829f UW |
6076 | slgfr\t%0,%2 |
6077 | slgf\t%0,%2" | |
9381e3f1 WG |
6078 | [(set_attr "op_type" "RRE,RXY") |
6079 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6080 | |
6081 | (define_insn "*subdi3_zero" | |
6082 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6083 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6084 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6085 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6086 | "TARGET_ZARCH" |
07893d4f | 6087 | "@ |
d40c829f UW |
6088 | slgfr\t%0,%2 |
6089 | slgf\t%0,%2" | |
9381e3f1 WG |
6090 | [(set_attr "op_type" "RRE,RXY") |
6091 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6092 | |
e69166de UW |
6093 | (define_insn_and_split "*subdi3_31z" |
6094 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6095 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6096 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6097 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6098 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
6099 | "#" |
6100 | "&& reload_completed" | |
6101 | [(parallel | |
ae156f85 | 6102 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6103 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6104 | (match_dup 7))) | |
6105 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6106 | (parallel | |
6107 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6108 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6109 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6110 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6111 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6112 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6113 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6114 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6115 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6116 | |
07893d4f UW |
6117 | (define_insn_and_split "*subdi3_31" |
6118 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6119 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 6120 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 6121 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 6122 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
6123 | "#" |
6124 | "&& reload_completed" | |
6125 | [(parallel | |
6126 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 6127 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 6128 | (parallel |
ae156f85 | 6129 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
6130 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6131 | (match_dup 7))) | |
6132 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6133 | (set (pc) | |
ae156f85 | 6134 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
6135 | (pc) |
6136 | (label_ref (match_dup 9)))) | |
6137 | (parallel | |
6138 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 6139 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 6140 | (match_dup 9)] |
97c6f7ad UW |
6141 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6142 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6143 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6144 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6145 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
6146 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 6147 | operands[9] = gen_label_rtx ();") |
07893d4f | 6148 | |
3298c037 AK |
6149 | ; |
6150 | ; subsi3 instruction pattern(s). | |
6151 | ; | |
6152 | ||
6153 | (define_expand "subsi3" | |
07893d4f | 6154 | [(parallel |
3298c037 AK |
6155 | [(set (match_operand:SI 0 "register_operand" "") |
6156 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6157 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6158 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6159 | "" |
07893d4f | 6160 | "") |
9db1d521 | 6161 | |
3298c037 AK |
6162 | (define_insn "*subsi3_sign" |
6163 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6164 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6165 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6166 | (clobber (reg:CC CC_REGNUM))] | |
6167 | "" | |
6168 | "@ | |
6169 | sh\t%0,%2 | |
6170 | shy\t%0,%2" | |
65b1d8ea | 6171 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6172 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6173 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6174 | |
9db1d521 | 6175 | ; |
3298c037 | 6176 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6177 | ; |
6178 | ||
65b1d8ea | 6179 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6180 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6181 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6182 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6183 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6184 | (clobber (reg:CC CC_REGNUM))] |
6185 | "" | |
6186 | "@ | |
6187 | s<g>r\t%0,%2 | |
65b1d8ea | 6188 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6189 | s<g>\t%0,%2 |
6190 | s<y>\t%0,%2" | |
65b1d8ea | 6191 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6192 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6193 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6194 | |
65b1d8ea | 6195 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6196 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6197 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6198 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6199 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6200 | (match_dup 1))) |
65b1d8ea | 6201 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6202 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6203 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6204 | "@ |
3298c037 | 6205 | sl<g>r\t%0,%2 |
65b1d8ea | 6206 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6207 | sl<g>\t%0,%2 |
6208 | sl<y>\t%0,%2" | |
65b1d8ea | 6209 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6210 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6211 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6212 | |
65b1d8ea | 6213 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6214 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6215 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6216 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6217 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6218 | (match_dup 1))) |
65b1d8ea | 6219 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6220 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6221 | "@ |
3298c037 | 6222 | sl<g>r\t%0,%2 |
65b1d8ea | 6223 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6224 | sl<g>\t%0,%2 |
6225 | sl<y>\t%0,%2" | |
65b1d8ea | 6226 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6227 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6228 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6229 | |
65b1d8ea | 6230 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6231 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6232 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6233 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6234 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6235 | (const_int 0))) |
65b1d8ea | 6236 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6237 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6238 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6239 | "@ |
3298c037 | 6240 | sl<g>r\t%0,%2 |
65b1d8ea | 6241 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6242 | sl<g>\t%0,%2 |
6243 | sl<y>\t%0,%2" | |
65b1d8ea | 6244 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6245 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6246 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6247 | |
65b1d8ea | 6248 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6249 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6250 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6251 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6252 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6253 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6254 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6255 | "s390_match_ccmode (insn, CCL3mode)" |
6256 | "@ | |
3298c037 | 6257 | sl<g>r\t%0,%2 |
65b1d8ea | 6258 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6259 | sl<g>\t%0,%2 |
6260 | sl<y>\t%0,%2" | |
65b1d8ea | 6261 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6262 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6263 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6264 | |
65b1d8ea | 6265 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6266 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6267 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6268 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6269 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6270 | (const_int 0))) |
65b1d8ea | 6271 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6272 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6273 | "@ |
3298c037 | 6274 | sl<g>r\t%0,%2 |
65b1d8ea | 6275 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6276 | sl<g>\t%0,%2 |
6277 | sl<y>\t%0,%2" | |
65b1d8ea | 6278 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6279 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6280 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6281 | |
9db1d521 | 6282 | |
65b1d8ea | 6283 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6284 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6285 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6286 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6287 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6288 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6289 | "s390_match_ccmode (insn, CCL3mode)" |
6290 | "@ | |
3298c037 | 6291 | sl<g>r\t%0,%2 |
65b1d8ea | 6292 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6293 | sl<g>\t%0,%2 |
6294 | sl<y>\t%0,%2" | |
65b1d8ea | 6295 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6296 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6297 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6298 | |
7d2fd075 AK |
6299 | (define_insn "*subdi3_sign" |
6300 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6301 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6302 | (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) | |
6303 | (clobber (reg:CC CC_REGNUM))] | |
6304 | "TARGET_ARCH12" | |
6305 | "sgh\t%0,%2" | |
6306 | [(set_attr "op_type" "RXY")]) | |
6307 | ||
9db1d521 HP |
6308 | |
6309 | ; | |
609e7e80 | 6310 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6311 | ; |
6312 | ||
2de2b3f9 | 6313 | ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? |
d46f24b6 | 6314 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6315 | (define_insn "sub<mode>3" |
2de2b3f9 AK |
6316 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6317 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
6318 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6319 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6320 | "TARGET_HARD_FLOAT" |
9db1d521 | 6321 | "@ |
62d3f261 AK |
6322 | s<xde>tr\t%0,%1,%2 |
6323 | s<xde>br\t%0,%2 | |
6e5b5de8 | 6324 | s<xde>b\t%0,%2 |
2de2b3f9 AK |
6325 | wfsdb\t%v0,%v1,%v2 |
6326 | wfssb\t%v0,%v1,%v2" | |
6327 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6328 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6329 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6330 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6331 | |
d46f24b6 | 6332 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6333 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6334 | [(set (reg CC_REGNUM) |
62d3f261 | 6335 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
2de2b3f9 | 6336 | (match_operand:FP 2 "general_operand" "f,f,R")) |
609e7e80 | 6337 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6338 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6339 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6340 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6341 | "@ |
62d3f261 AK |
6342 | s<xde>tr\t%0,%1,%2 |
6343 | s<xde>br\t%0,%2 | |
f61a2c7d | 6344 | s<xde>b\t%0,%2" |
62d3f261 AK |
6345 | [(set_attr "op_type" "RRF,RRE,RXE") |
6346 | (set_attr "type" "fsimp<mode>") | |
6347 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6348 | |
d46f24b6 | 6349 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6350 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6351 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6352 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6353 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6354 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6355 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6356 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6357 | "@ |
62d3f261 AK |
6358 | s<xde>tr\t%0,%1,%2 |
6359 | s<xde>br\t%0,%2 | |
f61a2c7d | 6360 | s<xde>b\t%0,%2" |
62d3f261 AK |
6361 | [(set_attr "op_type" "RRF,RRE,RXE") |
6362 | (set_attr "type" "fsimp<mode>") | |
6363 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6364 | |
9db1d521 | 6365 | |
e69166de UW |
6366 | ;; |
6367 | ;;- Conditional add/subtract instructions. | |
6368 | ;; | |
6369 | ||
6370 | ; | |
9a91a21f | 6371 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6372 | ; |
6373 | ||
a996720c UW |
6374 | ; the following 4 patterns are used when the result of an add with |
6375 | ; carry is checked for an overflow condition | |
6376 | ||
6377 | ; op1 + op2 + c < op1 | |
6378 | ||
6379 | ; alcr, alc, alcgr, alcg | |
6380 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6381 | [(set (reg CC_REGNUM) | |
6382 | (compare | |
6383 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6384 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6385 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6386 | (match_dup 1))) |
6387 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6388 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6389 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6390 | "@ | |
6391 | alc<g>r\t%0,%2 | |
6392 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6393 | [(set_attr "op_type" "RRE,RXY") |
6394 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6395 | |
6396 | ; alcr, alc, alcgr, alcg | |
6397 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6398 | [(set (reg CC_REGNUM) | |
6399 | (compare | |
6400 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6401 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6402 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6403 | (match_dup 1))) |
6404 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6405 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6406 | "@ | |
6407 | alc<g>r\t%0,%2 | |
6408 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6409 | [(set_attr "op_type" "RRE,RXY") |
6410 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6411 | |
6412 | ; op1 + op2 + c < op2 | |
6413 | ||
6414 | ; alcr, alc, alcgr, alcg | |
6415 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6416 | [(set (reg CC_REGNUM) | |
6417 | (compare | |
6418 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6419 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6420 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6421 | (match_dup 2))) |
6422 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6423 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6424 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6425 | "@ | |
6426 | alc<g>r\t%0,%2 | |
6427 | alc<g>\t%0,%2" | |
6428 | [(set_attr "op_type" "RRE,RXY")]) | |
6429 | ||
6430 | ; alcr, alc, alcgr, alcg | |
6431 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6432 | [(set (reg CC_REGNUM) | |
6433 | (compare | |
6434 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6435 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6436 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6437 | (match_dup 2))) |
6438 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6439 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6440 | "@ | |
6441 | alc<g>r\t%0,%2 | |
6442 | alc<g>\t%0,%2" | |
6443 | [(set_attr "op_type" "RRE,RXY")]) | |
6444 | ||
43a09b63 | 6445 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6446 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6447 | [(set (reg CC_REGNUM) |
e69166de | 6448 | (compare |
a94a76a7 UW |
6449 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6450 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6451 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6452 | (const_int 0))) |
9a91a21f | 6453 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6454 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 6455 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6456 | "@ |
9a91a21f AS |
6457 | alc<g>r\t%0,%2 |
6458 | alc<g>\t%0,%2" | |
e69166de UW |
6459 | [(set_attr "op_type" "RRE,RXY")]) |
6460 | ||
43a09b63 | 6461 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6462 | (define_insn "*add<mode>3_alc" |
6463 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6464 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6465 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6466 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6467 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6468 | "TARGET_CPU_ZARCH" |
e69166de | 6469 | "@ |
9a91a21f AS |
6470 | alc<g>r\t%0,%2 |
6471 | alc<g>\t%0,%2" | |
e69166de UW |
6472 | [(set_attr "op_type" "RRE,RXY")]) |
6473 | ||
43a09b63 | 6474 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6475 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6476 | [(set (reg CC_REGNUM) |
e69166de | 6477 | (compare |
9a91a21f | 6478 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6479 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6480 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6481 | (const_int 0))) |
9a91a21f AS |
6482 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6483 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 6484 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6485 | "@ |
9a91a21f AS |
6486 | slb<g>r\t%0,%2 |
6487 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6488 | [(set_attr "op_type" "RRE,RXY") |
6489 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6490 | |
43a09b63 | 6491 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6492 | (define_insn "*sub<mode>3_slb" |
6493 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6494 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6495 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6496 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6497 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6498 | "TARGET_CPU_ZARCH" |
e69166de | 6499 | "@ |
9a91a21f AS |
6500 | slb<g>r\t%0,%2 |
6501 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6502 | [(set_attr "op_type" "RRE,RXY") |
6503 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6504 | |
9a91a21f AS |
6505 | (define_expand "add<mode>cc" |
6506 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6507 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6508 | (match_operand:GPR 2 "register_operand" "") |
6509 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 6510 | "TARGET_CPU_ZARCH" |
9381e3f1 | 6511 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6512 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6513 | operands[0], operands[2], |
5d880bd2 UW |
6514 | operands[3])) FAIL; DONE;") |
6515 | ||
6516 | ; | |
6517 | ; scond instruction pattern(s). | |
6518 | ; | |
6519 | ||
9a91a21f AS |
6520 | (define_insn_and_split "*scond<mode>" |
6521 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6522 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6523 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6524 | "TARGET_CPU_ZARCH" |
6525 | "#" | |
6526 | "&& reload_completed" | |
6527 | [(set (match_dup 0) (const_int 0)) | |
6528 | (parallel | |
a94a76a7 UW |
6529 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6530 | (match_dup 0))) | |
ae156f85 | 6531 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6532 | "") |
5d880bd2 | 6533 | |
9a91a21f AS |
6534 | (define_insn_and_split "*scond<mode>_neg" |
6535 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6536 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6537 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6538 | "TARGET_CPU_ZARCH" |
6539 | "#" | |
6540 | "&& reload_completed" | |
6541 | [(set (match_dup 0) (const_int 0)) | |
6542 | (parallel | |
9a91a21f AS |
6543 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6544 | (match_dup 1))) | |
ae156f85 | 6545 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6546 | (parallel |
9a91a21f | 6547 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6548 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6549 | "") |
5d880bd2 | 6550 | |
5d880bd2 | 6551 | |
f90b7a5a | 6552 | (define_expand "cstore<mode>4" |
9a91a21f | 6553 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6554 | (match_operator:SI 1 "s390_scond_operator" |
6555 | [(match_operand:GPR 2 "register_operand" "") | |
6556 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 6557 | "TARGET_CPU_ZARCH" |
f90b7a5a | 6558 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6559 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6560 | ||
f90b7a5a | 6561 | (define_expand "cstorecc4" |
69950452 | 6562 | [(parallel |
f90b7a5a PB |
6563 | [(set (match_operand:SI 0 "register_operand" "") |
6564 | (match_operator:SI 1 "s390_eqne_operator" | |
3ea685e7 | 6565 | [(match_operand 2 "cc_reg_operand") |
f90b7a5a | 6566 | (match_operand 3 "const0_operand")])) |
69950452 AS |
6567 | (clobber (reg:CC CC_REGNUM))])] |
6568 | "" | |
3ea685e7 DV |
6569 | "machine_mode mode = GET_MODE (operands[2]); |
6570 | if (TARGET_Z196) | |
6571 | { | |
6572 | rtx cond, ite; | |
6573 | ||
6574 | if (GET_CODE (operands[1]) == NE) | |
6575 | cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); | |
6576 | else | |
6577 | cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); | |
6578 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); | |
6579 | emit_insn (gen_rtx_SET (operands[0], ite)); | |
6580 | } | |
6581 | else | |
6582 | { | |
6583 | if (mode != CCZ1mode) | |
6584 | FAIL; | |
6585 | emit_insn (gen_sne (operands[0], operands[2])); | |
6586 | if (GET_CODE (operands[1]) == EQ) | |
6587 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6588 | } | |
f90b7a5a | 6589 | DONE;") |
69950452 | 6590 | |
f90b7a5a | 6591 | (define_insn_and_split "sne" |
69950452 | 6592 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6593 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6594 | (const_int 0))) |
6595 | (clobber (reg:CC CC_REGNUM))] | |
6596 | "" | |
6597 | "#" | |
6598 | "reload_completed" | |
6599 | [(parallel | |
6600 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6601 | (clobber (reg:CC CC_REGNUM))])]) | |
6602 | ||
e69166de | 6603 | |
65b1d8ea AK |
6604 | ;; |
6605 | ;; - Conditional move instructions (introduced with z196) | |
6606 | ;; | |
6607 | ||
6608 | (define_expand "mov<mode>cc" | |
6609 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6610 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6611 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6612 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6613 | "TARGET_Z196" | |
7477de01 AK |
6614 | { |
6615 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6616 | if (!s390_comparison (operands[1], VOIDmode)) | |
6617 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6618 | XEXP (operands[1], 0), | |
6619 | XEXP (operands[1], 1)); | |
6620 | }) | |
65b1d8ea | 6621 | |
bf749919 | 6622 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi |
561f6312 AK |
6623 | (define_insn "*mov<mode>cc" |
6624 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S") | |
65b1d8ea AK |
6625 | (if_then_else:GPR |
6626 | (match_operator 1 "s390_comparison" | |
561f6312 | 6627 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c") |
5a3fe9b6 | 6628 | (match_operand 5 "const_int_operand" "")]) |
561f6312 AK |
6629 | (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0") |
6630 | (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))] | |
65b1d8ea AK |
6631 | "TARGET_Z196" |
6632 | "@ | |
6633 | loc<g>r%C1\t%0,%3 | |
6634 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6635 | loc<g>%C1\t%0,%3 |
6636 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6637 | loc<g>hi%C1\t%0,%h3 |
6638 | loc<g>hi%D1\t%0,%h4 | |
a6510374 | 6639 | stoc<g>%C1\t%3,%0 |
561f6312 AK |
6640 | stoc<g>%D1\t%4,%0" |
6641 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") | |
6642 | (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")]) | |
65b1d8ea | 6643 | |
9db1d521 HP |
6644 | ;; |
6645 | ;;- Multiply instructions. | |
6646 | ;; | |
6647 | ||
4023fb28 UW |
6648 | ; |
6649 | ; muldi3 instruction pattern(s). | |
6650 | ; | |
9db1d521 | 6651 | |
7d2fd075 AK |
6652 | (define_expand "muldi3" |
6653 | [(parallel | |
6654 | [(set (match_operand:DI 0 "register_operand") | |
6655 | (mult:DI (match_operand:DI 1 "nonimmediate_operand") | |
6656 | (match_operand:DI 2 "general_operand"))) | |
6657 | (clobber (reg:CC CC_REGNUM))])] | |
6658 | "TARGET_ZARCH") | |
6659 | ||
07893d4f UW |
6660 | (define_insn "*muldi3_sign" |
6661 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6662 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6663 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6664 | "TARGET_ZARCH" |
07893d4f | 6665 | "@ |
d40c829f UW |
6666 | msgfr\t%0,%2 |
6667 | msgf\t%0,%2" | |
963fc8d0 AK |
6668 | [(set_attr "op_type" "RRE,RXY") |
6669 | (set_attr "type" "imuldi")]) | |
07893d4f | 6670 | |
7d2fd075 AK |
6671 | (define_insn "*muldi3" |
6672 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") | |
6673 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") | |
6674 | (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) | |
6675 | (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] | |
9602b6a1 | 6676 | "TARGET_ZARCH" |
9db1d521 | 6677 | "@ |
d40c829f | 6678 | msgr\t%0,%2 |
7d2fd075 | 6679 | msgrkc\t%0,%1,%2 |
d40c829f | 6680 | mghi\t%0,%h2 |
963fc8d0 AK |
6681 | msg\t%0,%2 |
6682 | msgfi\t%0,%2" | |
7d2fd075 | 6683 | [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") |
963fc8d0 | 6684 | (set_attr "type" "imuldi") |
7d2fd075 AK |
6685 | (set_attr "cpu_facility" "*,arch12,*,*,z10")]) |
6686 | ||
6687 | (define_insn "mulditi3" | |
6688 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6689 | (mult:TI (sign_extend:TI | |
6690 | (match_operand:DI 1 "register_operand" "%d,0")) | |
6691 | (sign_extend:TI | |
6692 | (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] | |
6693 | "TARGET_ARCH12" | |
6694 | "@ | |
6695 | mgrk\t%0,%1,%2 | |
6696 | mg\t%0,%2" | |
6697 | [(set_attr "op_type" "RRF,RXY")]) | |
6698 | ||
6699 | ; Combine likes op1 and op2 to be swapped sometimes. | |
6700 | (define_insn "mulditi3_2" | |
6701 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6702 | (mult:TI (sign_extend:TI | |
6703 | (match_operand:DI 1 "nonimmediate_operand" "%d,T")) | |
6704 | (sign_extend:TI | |
6705 | (match_operand:DI 2 "register_operand" " d,0"))))] | |
6706 | "TARGET_ARCH12" | |
6707 | "@ | |
6708 | mgrk\t%0,%1,%2 | |
6709 | mg\t%0,%1" | |
6710 | [(set_attr "op_type" "RRF,RXY")]) | |
6711 | ||
6712 | (define_insn "*muldi3_sign" | |
6713 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6714 | (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
6715 | (match_operand:DI 1 "register_operand" "0")))] | |
6716 | "TARGET_ARCH12" | |
6717 | "mgh\t%0,%2" | |
6718 | [(set_attr "op_type" "RXY")]) | |
6719 | ||
f2d3c02a | 6720 | |
9db1d521 HP |
6721 | ; |
6722 | ; mulsi3 instruction pattern(s). | |
6723 | ; | |
6724 | ||
7d2fd075 AK |
6725 | (define_expand "mulsi3" |
6726 | [(parallel | |
6727 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6728 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6729 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6730 | (clobber (reg:CC CC_REGNUM))])] | |
6731 | "") | |
6732 | ||
f1e77d83 | 6733 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6734 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6735 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6736 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6737 | "" |
963fc8d0 AK |
6738 | "@ |
6739 | mh\t%0,%2 | |
6740 | mhy\t%0,%2" | |
6741 | [(set_attr "op_type" "RX,RXY") | |
6742 | (set_attr "type" "imulhi") | |
6743 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6744 | |
7d2fd075 AK |
6745 | (define_insn "*mulsi3" |
6746 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6747 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6748 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6749 | (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] | |
9db1d521 HP |
6750 | "" |
6751 | "@ | |
d40c829f | 6752 | msr\t%0,%2 |
7d2fd075 | 6753 | msrkc\t%0,%1,%2 |
d40c829f UW |
6754 | mhi\t%0,%h2 |
6755 | ms\t%0,%2 | |
963fc8d0 AK |
6756 | msy\t%0,%2 |
6757 | msfi\t%0,%2" | |
7d2fd075 AK |
6758 | [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") |
6759 | (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") | |
6760 | (set_attr "cpu_facility" "*,arch12,*,*,longdisp,z10")]) | |
9db1d521 | 6761 | |
4023fb28 UW |
6762 | ; |
6763 | ; mulsidi3 instruction pattern(s). | |
6764 | ; | |
6765 | ||
f1e77d83 | 6766 | (define_insn "mulsidi3" |
963fc8d0 | 6767 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6768 | (mult:DI (sign_extend:DI |
963fc8d0 | 6769 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6770 | (sign_extend:DI |
963fc8d0 | 6771 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6772 | "!TARGET_ZARCH" |
f1e77d83 UW |
6773 | "@ |
6774 | mr\t%0,%2 | |
963fc8d0 AK |
6775 | m\t%0,%2 |
6776 | mfy\t%0,%2" | |
6777 | [(set_attr "op_type" "RR,RX,RXY") | |
6778 | (set_attr "type" "imulsi") | |
6779 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6780 | |
f1e77d83 | 6781 | ; |
6e0d70c9 | 6782 | ; umul instruction pattern(s). |
f1e77d83 | 6783 | ; |
c7453384 | 6784 | |
6e0d70c9 AK |
6785 | ; mlr, ml, mlgr, mlg |
6786 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 6787 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 6788 | (mult:DW (zero_extend:DW |
3e4be43f | 6789 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 6790 | (zero_extend:DW |
3e4be43f | 6791 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
6e0d70c9 | 6792 | "TARGET_CPU_ZARCH" |
f1e77d83 | 6793 | "@ |
6e0d70c9 AK |
6794 | ml<tg>r\t%0,%2 |
6795 | ml<tg>\t%0,%2" | |
f1e77d83 | 6796 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6797 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6798 | |
9db1d521 | 6799 | ; |
609e7e80 | 6800 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6801 | ; |
6802 | ||
9381e3f1 | 6803 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6804 | (define_insn "mul<mode>3" |
2de2b3f9 AK |
6805 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6806 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
6807 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 6808 | "TARGET_HARD_FLOAT" |
9db1d521 | 6809 | "@ |
62d3f261 AK |
6810 | m<xdee>tr\t%0,%1,%2 |
6811 | m<xdee>br\t%0,%2 | |
6e5b5de8 | 6812 | m<xdee>b\t%0,%2 |
2de2b3f9 AK |
6813 | wfmdb\t%v0,%v1,%v2 |
6814 | wfmsb\t%v0,%v1,%v2" | |
6815 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6816 | (set_attr "type" "fmul<mode>") |
2de2b3f9 AK |
6817 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6818 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6819 | |
9381e3f1 | 6820 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6821 | (define_insn "fma<mode>4" |
2de2b3f9 AK |
6822 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6823 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6824 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6825 | (match_operand:DSF 3 "register_operand" "0,0,v,v")))] | |
d7ecb504 | 6826 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6827 | "@ |
f61a2c7d | 6828 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 | 6829 | ma<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6830 | wfmadb\t%v0,%v1,%v2,%v3 |
6831 | wfmasb\t%v0,%v1,%v2,%v3" | |
6832 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6833 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6834 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6835 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
a1b892b5 | 6836 | |
43a09b63 | 6837 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6838 | (define_insn "fms<mode>4" |
2de2b3f9 AK |
6839 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6840 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6841 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6842 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] | |
d7ecb504 | 6843 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6844 | "@ |
f61a2c7d | 6845 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 | 6846 | ms<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6847 | wfmsdb\t%v0,%v1,%v2,%v3 |
6848 | wfmssb\t%v0,%v1,%v2,%v3" | |
6849 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6850 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6851 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6852 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
9db1d521 HP |
6853 | |
6854 | ;; | |
6855 | ;;- Divide and modulo instructions. | |
6856 | ;; | |
6857 | ||
6858 | ; | |
4023fb28 | 6859 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6860 | ; |
6861 | ||
4023fb28 UW |
6862 | (define_expand "divmoddi4" |
6863 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6864 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6865 | (match_operand:DI 2 "general_operand" ""))) |
6866 | (set (match_operand:DI 3 "general_operand" "") | |
6867 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6868 | (clobber (match_dup 4))] | |
9602b6a1 | 6869 | "TARGET_ZARCH" |
9db1d521 | 6870 | { |
d8485bdb TS |
6871 | rtx div_equal, mod_equal; |
6872 | rtx_insn *insn; | |
4023fb28 UW |
6873 | |
6874 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6875 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6876 | |
6877 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6878 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6879 | |
6880 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6881 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6882 | |
6883 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6884 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6885 | |
9db1d521 | 6886 | DONE; |
10bbf137 | 6887 | }) |
9db1d521 HP |
6888 | |
6889 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6890 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6891 | (ior:TI | |
4023fb28 UW |
6892 | (ashift:TI |
6893 | (zero_extend:TI | |
5665e398 | 6894 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6895 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
6896 | (const_int 64)) |
6897 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6898 | "TARGET_ZARCH" |
9db1d521 | 6899 | "@ |
d40c829f UW |
6900 | dsgr\t%0,%2 |
6901 | dsg\t%0,%2" | |
d3632d41 | 6902 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6903 | (set_attr "type" "idiv")]) |
9db1d521 | 6904 | |
4023fb28 UW |
6905 | (define_insn "divmodtisi3" |
6906 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6907 | (ior:TI | |
4023fb28 UW |
6908 | (ashift:TI |
6909 | (zero_extend:TI | |
5665e398 | 6910 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6911 | (sign_extend:DI |
3e4be43f | 6912 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
6913 | (const_int 64)) |
6914 | (zero_extend:TI | |
6915 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6916 | "TARGET_ZARCH" |
4023fb28 | 6917 | "@ |
d40c829f UW |
6918 | dsgfr\t%0,%2 |
6919 | dsgf\t%0,%2" | |
d3632d41 | 6920 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6921 | (set_attr "type" "idiv")]) |
9db1d521 | 6922 | |
4023fb28 UW |
6923 | ; |
6924 | ; udivmoddi4 instruction pattern(s). | |
6925 | ; | |
9db1d521 | 6926 | |
4023fb28 UW |
6927 | (define_expand "udivmoddi4" |
6928 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6929 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6930 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6931 | (set (match_operand:DI 3 "general_operand" "") | |
6932 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6933 | (clobber (match_dup 4))] | |
9602b6a1 | 6934 | "TARGET_ZARCH" |
9db1d521 | 6935 | { |
d8485bdb TS |
6936 | rtx div_equal, mod_equal, equal; |
6937 | rtx_insn *insn; | |
4023fb28 UW |
6938 | |
6939 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6940 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6941 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6942 | gen_rtx_ASHIFT (TImode, |
6943 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6944 | GEN_INT (64)), |
6945 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6946 | |
6947 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6948 | emit_clobber (operands[4]); |
4023fb28 UW |
6949 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6950 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6951 | |
4023fb28 | 6952 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6953 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6954 | |
6955 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6956 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6957 | |
6958 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6959 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6960 | |
9db1d521 | 6961 | DONE; |
10bbf137 | 6962 | }) |
9db1d521 HP |
6963 | |
6964 | (define_insn "udivmodtidi3" | |
4023fb28 | 6965 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6966 | (ior:TI |
5665e398 UW |
6967 | (ashift:TI |
6968 | (zero_extend:TI | |
6969 | (truncate:DI | |
2f7e5a0d EC |
6970 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6971 | (zero_extend:TI | |
3e4be43f | 6972 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
6973 | (const_int 64)) |
6974 | (zero_extend:TI | |
6975 | (truncate:DI | |
6976 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6977 | "TARGET_ZARCH" |
9db1d521 | 6978 | "@ |
d40c829f UW |
6979 | dlgr\t%0,%2 |
6980 | dlg\t%0,%2" | |
d3632d41 | 6981 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6982 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6983 | |
6984 | ; | |
4023fb28 | 6985 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6986 | ; |
6987 | ||
4023fb28 UW |
6988 | (define_expand "divmodsi4" |
6989 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6990 | (div:SI (match_operand:SI 1 "general_operand" "") | |
6991 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6992 | (set (match_operand:SI 3 "general_operand" "") | |
6993 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
6994 | (clobber (match_dup 4))] | |
9602b6a1 | 6995 | "!TARGET_ZARCH" |
9db1d521 | 6996 | { |
d8485bdb TS |
6997 | rtx div_equal, mod_equal, equal; |
6998 | rtx_insn *insn; | |
4023fb28 UW |
6999 | |
7000 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
7001 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
7002 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7003 | gen_rtx_ASHIFT (DImode, |
7004 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7005 | GEN_INT (32)), |
7006 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
7007 | |
7008 | operands[4] = gen_reg_rtx(DImode); | |
7009 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 7010 | |
4023fb28 | 7011 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7012 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7013 | |
7014 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7015 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7016 | |
7017 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7018 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7019 | |
9db1d521 | 7020 | DONE; |
10bbf137 | 7021 | }) |
9db1d521 HP |
7022 | |
7023 | (define_insn "divmoddisi3" | |
4023fb28 | 7024 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 7025 | (ior:DI |
5665e398 UW |
7026 | (ashift:DI |
7027 | (zero_extend:DI | |
7028 | (truncate:SI | |
2f7e5a0d EC |
7029 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
7030 | (sign_extend:DI | |
5665e398 UW |
7031 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
7032 | (const_int 32)) | |
7033 | (zero_extend:DI | |
7034 | (truncate:SI | |
7035 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7036 | "!TARGET_ZARCH" |
9db1d521 | 7037 | "@ |
d40c829f UW |
7038 | dr\t%0,%2 |
7039 | d\t%0,%2" | |
9db1d521 | 7040 | [(set_attr "op_type" "RR,RX") |
077dab3b | 7041 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7042 | |
7043 | ; | |
7044 | ; udivsi3 and umodsi3 instruction pattern(s). | |
7045 | ; | |
7046 | ||
f1e77d83 UW |
7047 | (define_expand "udivmodsi4" |
7048 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7049 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
7050 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7051 | (set (match_operand:SI 3 "general_operand" "") | |
7052 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
7053 | (clobber (match_dup 4))] | |
9602b6a1 | 7054 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 | 7055 | { |
d8485bdb TS |
7056 | rtx div_equal, mod_equal, equal; |
7057 | rtx_insn *insn; | |
f1e77d83 UW |
7058 | |
7059 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7060 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7061 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
7062 | gen_rtx_ASHIFT (DImode, |
7063 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7064 | GEN_INT (32)), |
7065 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
7066 | |
7067 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 7068 | emit_clobber (operands[4]); |
f1e77d83 UW |
7069 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
7070 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 7071 | |
f1e77d83 | 7072 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7073 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
7074 | |
7075 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7076 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
7077 | |
7078 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7079 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
7080 | |
7081 | DONE; | |
7082 | }) | |
7083 | ||
7084 | (define_insn "udivmoddisi3" | |
7085 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 7086 | (ior:DI |
5665e398 UW |
7087 | (ashift:DI |
7088 | (zero_extend:DI | |
7089 | (truncate:SI | |
2f7e5a0d EC |
7090 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
7091 | (zero_extend:DI | |
3e4be43f | 7092 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7093 | (const_int 32)) |
7094 | (zero_extend:DI | |
7095 | (truncate:SI | |
7096 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7097 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
7098 | "@ |
7099 | dlr\t%0,%2 | |
7100 | dl\t%0,%2" | |
7101 | [(set_attr "op_type" "RRE,RXY") | |
7102 | (set_attr "type" "idiv")]) | |
4023fb28 | 7103 | |
9db1d521 HP |
7104 | (define_expand "udivsi3" |
7105 | [(set (match_operand:SI 0 "register_operand" "=d") | |
7106 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
7107 | (match_operand:SI 2 "general_operand" ""))) |
7108 | (clobber (match_dup 3))] | |
9602b6a1 | 7109 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 7110 | { |
d8485bdb TS |
7111 | rtx udiv_equal, umod_equal, equal; |
7112 | rtx_insn *insn; | |
4023fb28 UW |
7113 | |
7114 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7115 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7116 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7117 | gen_rtx_ASHIFT (DImode, |
7118 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
7119 | GEN_INT (32)), |
7120 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 7121 | |
4023fb28 | 7122 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
7123 | |
7124 | if (CONSTANT_P (operands[2])) | |
7125 | { | |
7126 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
7127 | { | |
19f8b229 | 7128 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 7129 | |
4023fb28 UW |
7130 | operands[1] = make_safe_from (operands[1], operands[0]); |
7131 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
7132 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
7133 | SImode, 1, label1); | |
4023fb28 | 7134 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
7135 | emit_label (label1); |
7136 | } | |
7137 | else | |
7138 | { | |
c7453384 EC |
7139 | operands[2] = force_reg (SImode, operands[2]); |
7140 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7141 | |
7142 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
7143 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7144 | operands[2])); | |
bd94cb6e | 7145 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7146 | |
7147 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7148 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 7149 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
7150 | } |
7151 | } | |
7152 | else | |
c7453384 | 7153 | { |
19f8b229 TS |
7154 | rtx_code_label *label1 = gen_label_rtx (); |
7155 | rtx_code_label *label2 = gen_label_rtx (); | |
7156 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 7157 | |
c7453384 EC |
7158 | operands[1] = force_reg (SImode, operands[1]); |
7159 | operands[1] = make_safe_from (operands[1], operands[0]); | |
7160 | operands[2] = force_reg (SImode, operands[2]); | |
7161 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7162 | |
7163 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
7164 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
7165 | SImode, 1, label3); | |
7166 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
7167 | SImode, 0, label2); | |
7168 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
7169 | SImode, 0, label1); | |
4023fb28 UW |
7170 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
7171 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7172 | operands[2])); | |
bd94cb6e | 7173 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7174 | |
7175 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7176 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
7177 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
7178 | ||
f314b9b1 | 7179 | emit_jump (label3); |
9db1d521 | 7180 | emit_label (label1); |
4023fb28 | 7181 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 7182 | emit_jump (label3); |
9db1d521 | 7183 | emit_label (label2); |
4023fb28 | 7184 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
7185 | emit_label (label3); |
7186 | } | |
c7453384 | 7187 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 7188 | DONE; |
10bbf137 | 7189 | }) |
9db1d521 HP |
7190 | |
7191 | (define_expand "umodsi3" | |
7192 | [(set (match_operand:SI 0 "register_operand" "=d") | |
7193 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
7194 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
7195 | (clobber (match_dup 3))] | |
9602b6a1 | 7196 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 7197 | { |
d8485bdb TS |
7198 | rtx udiv_equal, umod_equal, equal; |
7199 | rtx_insn *insn; | |
4023fb28 UW |
7200 | |
7201 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7202 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7203 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7204 | gen_rtx_ASHIFT (DImode, |
7205 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
7206 | GEN_INT (32)), |
7207 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 7208 | |
4023fb28 | 7209 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
7210 | |
7211 | if (CONSTANT_P (operands[2])) | |
7212 | { | |
7213 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
7214 | { | |
19f8b229 | 7215 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 7216 | |
4023fb28 UW |
7217 | operands[1] = make_safe_from (operands[1], operands[0]); |
7218 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
7219 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
7220 | SImode, 1, label1); | |
4023fb28 UW |
7221 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
7222 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
7223 | emit_label (label1); |
7224 | } | |
7225 | else | |
7226 | { | |
c7453384 EC |
7227 | operands[2] = force_reg (SImode, operands[2]); |
7228 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7229 | |
7230 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
7231 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7232 | operands[2])); | |
bd94cb6e | 7233 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7234 | |
7235 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7236 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 7237 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
7238 | } |
7239 | } | |
7240 | else | |
7241 | { | |
19f8b229 TS |
7242 | rtx_code_label *label1 = gen_label_rtx (); |
7243 | rtx_code_label *label2 = gen_label_rtx (); | |
7244 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 7245 | |
c7453384 EC |
7246 | operands[1] = force_reg (SImode, operands[1]); |
7247 | operands[1] = make_safe_from (operands[1], operands[0]); | |
7248 | operands[2] = force_reg (SImode, operands[2]); | |
7249 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 7250 | |
c7453384 | 7251 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
7252 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
7253 | SImode, 1, label3); | |
7254 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
7255 | SImode, 0, label2); | |
7256 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
7257 | SImode, 0, label1); | |
4023fb28 UW |
7258 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
7259 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7260 | operands[2])); | |
bd94cb6e | 7261 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7262 | |
7263 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7264 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
7265 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
7266 | ||
f314b9b1 | 7267 | emit_jump (label3); |
9db1d521 | 7268 | emit_label (label1); |
4023fb28 | 7269 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 7270 | emit_jump (label3); |
9db1d521 | 7271 | emit_label (label2); |
4023fb28 | 7272 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
7273 | emit_label (label3); |
7274 | } | |
9db1d521 | 7275 | DONE; |
10bbf137 | 7276 | }) |
9db1d521 HP |
7277 | |
7278 | ; | |
f5905b37 | 7279 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7280 | ; |
7281 | ||
609e7e80 | 7282 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7283 | (define_insn "div<mode>3" |
2de2b3f9 AK |
7284 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7285 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
7286 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7287 | "TARGET_HARD_FLOAT" |
9db1d521 | 7288 | "@ |
62d3f261 AK |
7289 | d<xde>tr\t%0,%1,%2 |
7290 | d<xde>br\t%0,%2 | |
6e5b5de8 | 7291 | d<xde>b\t%0,%2 |
2de2b3f9 AK |
7292 | wfddb\t%v0,%v1,%v2 |
7293 | wfdsb\t%v0,%v1,%v2" | |
7294 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7295 | (set_attr "type" "fdiv<mode>") |
2de2b3f9 AK |
7296 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7297 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7298 | |
9db1d521 HP |
7299 | |
7300 | ;; | |
7301 | ;;- And instructions. | |
7302 | ;; | |
7303 | ||
047d35ed AS |
7304 | (define_expand "and<mode>3" |
7305 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7306 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7307 | (match_operand:INT 2 "general_operand" ""))) | |
7308 | (clobber (reg:CC CC_REGNUM))] | |
7309 | "" | |
7310 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7311 | ||
9db1d521 HP |
7312 | ; |
7313 | ; anddi3 instruction pattern(s). | |
7314 | ; | |
7315 | ||
7316 | (define_insn "*anddi3_cc" | |
ae156f85 | 7317 | [(set (reg CC_REGNUM) |
e3140518 | 7318 | (compare |
3e4be43f | 7319 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7320 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7321 | (const_int 0))) |
3e4be43f | 7322 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7323 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7324 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7325 | "@ |
d40c829f | 7326 | ngr\t%0,%2 |
65b1d8ea | 7327 | ngrk\t%0,%1,%2 |
e3140518 RH |
7328 | ng\t%0,%2 |
7329 | risbg\t%0,%1,%s2,128+%e2,0" | |
7330 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7331 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7332 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7333 | |
7334 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7335 | [(set (reg CC_REGNUM) |
e3140518 | 7336 | (compare |
3e4be43f | 7337 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7338 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7339 | (const_int 0))) |
3e4be43f | 7340 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7341 | "TARGET_ZARCH |
7342 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7343 | /* Do not steal TM patterns. */ |
7344 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7345 | "@ |
d40c829f | 7346 | ngr\t%0,%2 |
65b1d8ea | 7347 | ngrk\t%0,%1,%2 |
e3140518 RH |
7348 | ng\t%0,%2 |
7349 | risbg\t%0,%1,%s2,128+%e2,0" | |
7350 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7351 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7352 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7353 | |
3af8e996 | 7354 | (define_insn "*anddi3" |
65b1d8ea | 7355 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7356 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7357 | (and:DI |
7358 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7359 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7360 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7361 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7362 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7363 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7364 | "@ |
7365 | # | |
7366 | # | |
7367 | nihh\t%0,%j2 | |
7368 | nihl\t%0,%j2 | |
7369 | nilh\t%0,%j2 | |
7370 | nill\t%0,%j2 | |
7371 | nihf\t%0,%m2 | |
7372 | nilf\t%0,%m2 | |
7373 | ngr\t%0,%2 | |
65b1d8ea | 7374 | ngrk\t%0,%1,%2 |
ec24698e | 7375 | ng\t%0,%2 |
e3140518 | 7376 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7377 | # |
7378 | #" | |
e3140518 RH |
7379 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7380 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7381 | (set_attr "z10prop" "*, |
7382 | *, | |
7383 | z10_super_E1, | |
7384 | z10_super_E1, | |
7385 | z10_super_E1, | |
7386 | z10_super_E1, | |
7387 | z10_super_E1, | |
7388 | z10_super_E1, | |
7389 | z10_super_E1, | |
65b1d8ea | 7390 | *, |
9381e3f1 | 7391 | z10_super_E1, |
e3140518 | 7392 | z10_super_E1, |
9381e3f1 WG |
7393 | *, |
7394 | *")]) | |
0dfa6c5e UW |
7395 | |
7396 | (define_split | |
7397 | [(set (match_operand:DI 0 "s_operand" "") | |
7398 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7399 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7400 | "reload_completed" |
7401 | [(parallel | |
7402 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7403 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7404 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7405 | |
1a2e356e | 7406 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7407 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7408 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7409 | (and:GPR (lshiftrt:GPR | |
7410 | (match_operand:GPR 1 "register_operand" "d") | |
7411 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7412 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7413 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7414 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7415 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7416 | INTVAL (operands[3]))" | |
64c744b9 | 7417 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7418 | [(set_attr "op_type" "RIE") |
7419 | (set_attr "z10prop" "z10_super_E1")]) | |
7420 | ||
64c744b9 | 7421 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7422 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7423 | (and:GPR (ashift:GPR | |
7424 | (match_operand:GPR 1 "register_operand" "d") | |
7425 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7426 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7427 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7428 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7429 | INTVAL (operands[3]))" | |
64c744b9 | 7430 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7431 | [(set_attr "op_type" "RIE") |
7432 | (set_attr "z10prop" "z10_super_E1")]) | |
7433 | ||
9db1d521 HP |
7434 | |
7435 | ; | |
7436 | ; andsi3 instruction pattern(s). | |
7437 | ; | |
7438 | ||
7439 | (define_insn "*andsi3_cc" | |
ae156f85 | 7440 | [(set (reg CC_REGNUM) |
e3140518 RH |
7441 | (compare |
7442 | (and:SI | |
7443 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7444 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7445 | (const_int 0))) | |
7446 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7447 | (and:SI (match_dup 1) (match_dup 2)))] |
7448 | "s390_match_ccmode(insn, CCTmode)" | |
7449 | "@ | |
ec24698e | 7450 | nilf\t%0,%o2 |
d40c829f | 7451 | nr\t%0,%2 |
65b1d8ea | 7452 | nrk\t%0,%1,%2 |
d40c829f | 7453 | n\t%0,%2 |
e3140518 RH |
7454 | ny\t%0,%2 |
7455 | risbg\t%0,%1,%t2,128+%f2,0" | |
7456 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7457 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7458 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7459 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7460 | |
7461 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7462 | [(set (reg CC_REGNUM) |
e3140518 RH |
7463 | (compare |
7464 | (and:SI | |
7465 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7466 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7467 | (const_int 0))) | |
7468 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7469 | "s390_match_ccmode(insn, CCTmode) |
7470 | /* Do not steal TM patterns. */ | |
7471 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7472 | "@ |
ec24698e | 7473 | nilf\t%0,%o2 |
d40c829f | 7474 | nr\t%0,%2 |
65b1d8ea | 7475 | nrk\t%0,%1,%2 |
d40c829f | 7476 | n\t%0,%2 |
e3140518 RH |
7477 | ny\t%0,%2 |
7478 | risbg\t%0,%1,%t2,128+%f2,0" | |
7479 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7480 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7481 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7482 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7483 | |
f19a9af7 | 7484 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7485 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7486 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7487 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7488 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7489 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7490 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7491 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7492 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7493 | "@ |
f19a9af7 AK |
7494 | # |
7495 | # | |
7496 | nilh\t%0,%j2 | |
2f7e5a0d | 7497 | nill\t%0,%j2 |
ec24698e | 7498 | nilf\t%0,%o2 |
d40c829f | 7499 | nr\t%0,%2 |
65b1d8ea | 7500 | nrk\t%0,%1,%2 |
d40c829f | 7501 | n\t%0,%2 |
8cb66696 | 7502 | ny\t%0,%2 |
e3140518 | 7503 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7504 | # |
19b63d8e | 7505 | #" |
e3140518 | 7506 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7507 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7508 | (set_attr "z10prop" "*, |
7509 | *, | |
7510 | z10_super_E1, | |
7511 | z10_super_E1, | |
7512 | z10_super_E1, | |
7513 | z10_super_E1, | |
65b1d8ea | 7514 | *, |
9381e3f1 WG |
7515 | z10_super_E1, |
7516 | z10_super_E1, | |
e3140518 | 7517 | z10_super_E1, |
9381e3f1 WG |
7518 | *, |
7519 | *")]) | |
f19a9af7 AK |
7520 | |
7521 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7522 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7523 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7524 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7525 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7526 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7527 | "@ |
7528 | nr\t%0,%2 | |
8cb66696 | 7529 | n\t%0,%2 |
0dfa6c5e | 7530 | # |
19b63d8e | 7531 | #" |
9381e3f1 WG |
7532 | [(set_attr "op_type" "RR,RX,SI,SS") |
7533 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7534 | ||
0dfa6c5e UW |
7535 | |
7536 | (define_split | |
7537 | [(set (match_operand:SI 0 "s_operand" "") | |
7538 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7539 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7540 | "reload_completed" |
7541 | [(parallel | |
7542 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7543 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7544 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7545 | |
9db1d521 HP |
7546 | ; |
7547 | ; andhi3 instruction pattern(s). | |
7548 | ; | |
7549 | ||
8cb66696 | 7550 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7551 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7552 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7553 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7554 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7555 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7556 | "@ |
d40c829f | 7557 | nr\t%0,%2 |
65b1d8ea | 7558 | nrk\t%0,%1,%2 |
8cb66696 | 7559 | nill\t%0,%x2 |
0dfa6c5e | 7560 | # |
19b63d8e | 7561 | #" |
65b1d8ea AK |
7562 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7563 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7564 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7565 | ]) |
8cb66696 UW |
7566 | |
7567 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7568 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7569 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7570 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7571 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7572 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7573 | "@ | |
7574 | nr\t%0,%2 | |
0dfa6c5e | 7575 | # |
19b63d8e | 7576 | #" |
9381e3f1 WG |
7577 | [(set_attr "op_type" "RR,SI,SS") |
7578 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7579 | ]) | |
0dfa6c5e UW |
7580 | |
7581 | (define_split | |
7582 | [(set (match_operand:HI 0 "s_operand" "") | |
7583 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7584 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7585 | "reload_completed" |
7586 | [(parallel | |
7587 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7588 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7589 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7590 | |
9db1d521 HP |
7591 | ; |
7592 | ; andqi3 instruction pattern(s). | |
7593 | ; | |
7594 | ||
8cb66696 | 7595 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7596 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7597 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7598 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7599 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7600 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7601 | "@ |
d40c829f | 7602 | nr\t%0,%2 |
65b1d8ea | 7603 | nrk\t%0,%1,%2 |
8cb66696 | 7604 | nill\t%0,%b2 |
fc0ea003 UW |
7605 | ni\t%S0,%b2 |
7606 | niy\t%S0,%b2 | |
19b63d8e | 7607 | #" |
65b1d8ea | 7608 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7609 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7610 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7611 | |
7612 | (define_insn "*andqi3_esa" | |
7613 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7614 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7615 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7616 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7617 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7618 | "@ |
8cb66696 | 7619 | nr\t%0,%2 |
fc0ea003 | 7620 | ni\t%S0,%b2 |
19b63d8e | 7621 | #" |
9381e3f1 WG |
7622 | [(set_attr "op_type" "RR,SI,SS") |
7623 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7624 | |
deb9351f DV |
7625 | ; |
7626 | ; And with complement | |
7627 | ; | |
7628 | ; c = ~b & a = (b & a) ^ a | |
7629 | ||
7630 | (define_insn_and_split "*andc_split_<mode>" | |
7631 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7632 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7633 | (match_operand:GPR 2 "general_operand" ""))) | |
7634 | (clobber (reg:CC CC_REGNUM))] | |
ad7ab32e DV |
7635 | "! reload_completed |
7636 | && (GET_CODE (operands[0]) != MEM | |
7637 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7638 | on the split xor if (b & a) is stored into a pseudo. */ | |
7639 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7640 | "#" |
7641 | "&& 1" | |
7642 | [ | |
7643 | (parallel | |
7644 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7645 | (clobber (reg:CC CC_REGNUM))]) | |
7646 | (parallel | |
7647 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7648 | (clobber (reg:CC CC_REGNUM))])] | |
7649 | { | |
7650 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7651 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7652 | else | |
7653 | operands[3] = operands[0]; | |
7654 | }) | |
7655 | ||
19b63d8e UW |
7656 | ; |
7657 | ; Block and (NC) patterns. | |
7658 | ; | |
7659 | ||
7660 | (define_insn "*nc" | |
7661 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7662 | (and:BLK (match_dup 0) | |
7663 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7664 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7665 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7666 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7667 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7668 | [(set_attr "op_type" "SS") |
7669 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7670 | |
7671 | (define_split | |
7672 | [(set (match_operand 0 "memory_operand" "") | |
7673 | (and (match_dup 0) | |
7674 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7675 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7676 | "reload_completed |
7677 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7678 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7679 | [(parallel | |
7680 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7681 | (use (match_dup 2)) | |
ae156f85 | 7682 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7683 | { |
7684 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7685 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7686 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7687 | }) | |
7688 | ||
7689 | (define_peephole2 | |
7690 | [(parallel | |
7691 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7692 | (and:BLK (match_dup 0) | |
7693 | (match_operand:BLK 1 "memory_operand" ""))) | |
7694 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7695 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7696 | (parallel |
7697 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7698 | (and:BLK (match_dup 3) | |
7699 | (match_operand:BLK 4 "memory_operand" ""))) | |
7700 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7701 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7702 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7703 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7704 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7705 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7706 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7707 | [(parallel | |
7708 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7709 | (use (match_dup 8)) | |
ae156f85 | 7710 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7711 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7712 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7713 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7714 | ||
9db1d521 HP |
7715 | |
7716 | ;; | |
7717 | ;;- Bit set (inclusive or) instructions. | |
7718 | ;; | |
7719 | ||
047d35ed AS |
7720 | (define_expand "ior<mode>3" |
7721 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7722 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7723 | (match_operand:INT 2 "general_operand" ""))) | |
7724 | (clobber (reg:CC CC_REGNUM))] | |
7725 | "" | |
7726 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7727 | ||
9db1d521 HP |
7728 | ; |
7729 | ; iordi3 instruction pattern(s). | |
7730 | ; | |
7731 | ||
4023fb28 | 7732 | (define_insn "*iordi3_cc" |
ae156f85 | 7733 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7734 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7735 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7736 | (const_int 0))) |
3e4be43f | 7737 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7738 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7739 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7740 | "@ |
d40c829f | 7741 | ogr\t%0,%2 |
65b1d8ea | 7742 | ogrk\t%0,%1,%2 |
d40c829f | 7743 | og\t%0,%2" |
65b1d8ea AK |
7744 | [(set_attr "op_type" "RRE,RRF,RXY") |
7745 | (set_attr "cpu_facility" "*,z196,*") | |
7746 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7747 | |
7748 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7749 | [(set (reg CC_REGNUM) |
65b1d8ea | 7750 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7751 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7752 | (const_int 0))) |
65b1d8ea | 7753 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7754 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7755 | "@ |
d40c829f | 7756 | ogr\t%0,%2 |
65b1d8ea | 7757 | ogrk\t%0,%1,%2 |
d40c829f | 7758 | og\t%0,%2" |
65b1d8ea AK |
7759 | [(set_attr "op_type" "RRE,RRF,RXY") |
7760 | (set_attr "cpu_facility" "*,z196,*") | |
7761 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7762 | |
3af8e996 | 7763 | (define_insn "*iordi3" |
65b1d8ea | 7764 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7765 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7766 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7767 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7768 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7769 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7770 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7771 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7772 | "@ |
7773 | oihh\t%0,%i2 | |
7774 | oihl\t%0,%i2 | |
7775 | oilh\t%0,%i2 | |
7776 | oill\t%0,%i2 | |
7777 | oihf\t%0,%k2 | |
7778 | oilf\t%0,%k2 | |
7779 | ogr\t%0,%2 | |
65b1d8ea | 7780 | ogrk\t%0,%1,%2 |
ec24698e UW |
7781 | og\t%0,%2 |
7782 | # | |
7783 | #" | |
65b1d8ea AK |
7784 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7785 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7786 | (set_attr "z10prop" "z10_super_E1, |
7787 | z10_super_E1, | |
7788 | z10_super_E1, | |
7789 | z10_super_E1, | |
7790 | z10_super_E1, | |
7791 | z10_super_E1, | |
7792 | z10_super_E1, | |
65b1d8ea | 7793 | *, |
9381e3f1 WG |
7794 | z10_super_E1, |
7795 | *, | |
7796 | *")]) | |
0dfa6c5e UW |
7797 | |
7798 | (define_split | |
7799 | [(set (match_operand:DI 0 "s_operand" "") | |
7800 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7801 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7802 | "reload_completed" |
7803 | [(parallel | |
7804 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7805 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7806 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7807 | |
9db1d521 HP |
7808 | ; |
7809 | ; iorsi3 instruction pattern(s). | |
7810 | ; | |
7811 | ||
4023fb28 | 7812 | (define_insn "*iorsi3_cc" |
ae156f85 | 7813 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7814 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7815 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7816 | (const_int 0))) |
65b1d8ea | 7817 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7818 | (ior:SI (match_dup 1) (match_dup 2)))] |
7819 | "s390_match_ccmode(insn, CCTmode)" | |
7820 | "@ | |
ec24698e | 7821 | oilf\t%0,%o2 |
d40c829f | 7822 | or\t%0,%2 |
65b1d8ea | 7823 | ork\t%0,%1,%2 |
d40c829f UW |
7824 | o\t%0,%2 |
7825 | oy\t%0,%2" | |
65b1d8ea | 7826 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7827 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7828 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7829 | |
7830 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7831 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7832 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7833 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7834 | (const_int 0))) |
65b1d8ea | 7835 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7836 | "s390_match_ccmode(insn, CCTmode)" |
7837 | "@ | |
ec24698e | 7838 | oilf\t%0,%o2 |
d40c829f | 7839 | or\t%0,%2 |
65b1d8ea | 7840 | ork\t%0,%1,%2 |
d40c829f UW |
7841 | o\t%0,%2 |
7842 | oy\t%0,%2" | |
65b1d8ea | 7843 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7844 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7845 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7846 | |
8cb66696 | 7847 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7848 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7849 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7850 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7851 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7852 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7853 | "@ |
f19a9af7 AK |
7854 | oilh\t%0,%i2 |
7855 | oill\t%0,%i2 | |
ec24698e | 7856 | oilf\t%0,%o2 |
d40c829f | 7857 | or\t%0,%2 |
65b1d8ea | 7858 | ork\t%0,%1,%2 |
d40c829f | 7859 | o\t%0,%2 |
8cb66696 | 7860 | oy\t%0,%2 |
0dfa6c5e | 7861 | # |
19b63d8e | 7862 | #" |
65b1d8ea | 7863 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7864 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7865 | (set_attr "z10prop" "z10_super_E1, |
7866 | z10_super_E1, | |
7867 | z10_super_E1, | |
7868 | z10_super_E1, | |
65b1d8ea | 7869 | *, |
9381e3f1 WG |
7870 | z10_super_E1, |
7871 | z10_super_E1, | |
7872 | *, | |
7873 | *")]) | |
8cb66696 UW |
7874 | |
7875 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7876 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7877 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7878 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7879 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7880 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7881 | "@ |
7882 | or\t%0,%2 | |
8cb66696 | 7883 | o\t%0,%2 |
0dfa6c5e | 7884 | # |
19b63d8e | 7885 | #" |
9381e3f1 WG |
7886 | [(set_attr "op_type" "RR,RX,SI,SS") |
7887 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7888 | |
7889 | (define_split | |
7890 | [(set (match_operand:SI 0 "s_operand" "") | |
7891 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7892 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7893 | "reload_completed" |
7894 | [(parallel | |
7895 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7896 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7897 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7898 | |
4023fb28 UW |
7899 | ; |
7900 | ; iorhi3 instruction pattern(s). | |
7901 | ; | |
7902 | ||
8cb66696 | 7903 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7904 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7905 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7906 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7907 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7908 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7909 | "@ |
d40c829f | 7910 | or\t%0,%2 |
65b1d8ea | 7911 | ork\t%0,%1,%2 |
8cb66696 | 7912 | oill\t%0,%x2 |
0dfa6c5e | 7913 | # |
19b63d8e | 7914 | #" |
65b1d8ea AK |
7915 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7916 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7917 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7918 | |
7919 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7920 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7921 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7922 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7923 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7924 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7925 | "@ | |
7926 | or\t%0,%2 | |
0dfa6c5e | 7927 | # |
19b63d8e | 7928 | #" |
9381e3f1 WG |
7929 | [(set_attr "op_type" "RR,SI,SS") |
7930 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7931 | |
7932 | (define_split | |
7933 | [(set (match_operand:HI 0 "s_operand" "") | |
7934 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7935 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7936 | "reload_completed" |
7937 | [(parallel | |
7938 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7939 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7940 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7941 | |
9db1d521 | 7942 | ; |
4023fb28 | 7943 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7944 | ; |
7945 | ||
8cb66696 | 7946 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7947 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7948 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7949 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7950 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7951 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7952 | "@ |
d40c829f | 7953 | or\t%0,%2 |
65b1d8ea | 7954 | ork\t%0,%1,%2 |
8cb66696 | 7955 | oill\t%0,%b2 |
fc0ea003 UW |
7956 | oi\t%S0,%b2 |
7957 | oiy\t%S0,%b2 | |
19b63d8e | 7958 | #" |
65b1d8ea | 7959 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7960 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
7961 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
7962 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7963 | |
7964 | (define_insn "*iorqi3_esa" | |
7965 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7966 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7967 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7968 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7969 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7970 | "@ |
8cb66696 | 7971 | or\t%0,%2 |
fc0ea003 | 7972 | oi\t%S0,%b2 |
19b63d8e | 7973 | #" |
9381e3f1 WG |
7974 | [(set_attr "op_type" "RR,SI,SS") |
7975 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7976 | |
19b63d8e UW |
7977 | ; |
7978 | ; Block inclusive or (OC) patterns. | |
7979 | ; | |
7980 | ||
7981 | (define_insn "*oc" | |
7982 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7983 | (ior:BLK (match_dup 0) | |
7984 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7985 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7986 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7987 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7988 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7989 | [(set_attr "op_type" "SS") |
7990 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7991 | |
7992 | (define_split | |
7993 | [(set (match_operand 0 "memory_operand" "") | |
7994 | (ior (match_dup 0) | |
7995 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7996 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7997 | "reload_completed |
7998 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7999 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8000 | [(parallel | |
8001 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
8002 | (use (match_dup 2)) | |
ae156f85 | 8003 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8004 | { |
8005 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8006 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8007 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8008 | }) | |
8009 | ||
8010 | (define_peephole2 | |
8011 | [(parallel | |
8012 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8013 | (ior:BLK (match_dup 0) | |
8014 | (match_operand:BLK 1 "memory_operand" ""))) | |
8015 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8016 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8017 | (parallel |
8018 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8019 | (ior:BLK (match_dup 3) | |
8020 | (match_operand:BLK 4 "memory_operand" ""))) | |
8021 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8022 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8023 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8024 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8025 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8026 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8027 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8028 | [(parallel | |
8029 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
8030 | (use (match_dup 8)) | |
ae156f85 | 8031 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8032 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8033 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8034 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8035 | ||
9db1d521 HP |
8036 | |
8037 | ;; | |
8038 | ;;- Xor instructions. | |
8039 | ;; | |
8040 | ||
047d35ed AS |
8041 | (define_expand "xor<mode>3" |
8042 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
8043 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
8044 | (match_operand:INT 2 "general_operand" ""))) | |
8045 | (clobber (reg:CC CC_REGNUM))] | |
8046 | "" | |
8047 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
8048 | ||
3c91f126 AK |
8049 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
8050 | ; simplifications. So its better to have something matching. | |
8051 | (define_split | |
8052 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
8053 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
8054 | "" | |
8055 | [(parallel | |
8056 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
8057 | (clobber (reg:CC CC_REGNUM))])] | |
8058 | { | |
8059 | operands[2] = constm1_rtx; | |
8060 | if (!s390_logical_operator_ok_p (operands)) | |
8061 | FAIL; | |
8062 | }) | |
8063 | ||
9db1d521 HP |
8064 | ; |
8065 | ; xordi3 instruction pattern(s). | |
8066 | ; | |
8067 | ||
4023fb28 | 8068 | (define_insn "*xordi3_cc" |
ae156f85 | 8069 | [(set (reg CC_REGNUM) |
3e4be43f UW |
8070 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
8071 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 8072 | (const_int 0))) |
3e4be43f | 8073 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 8074 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 8075 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 8076 | "@ |
d40c829f | 8077 | xgr\t%0,%2 |
65b1d8ea | 8078 | xgrk\t%0,%1,%2 |
d40c829f | 8079 | xg\t%0,%2" |
65b1d8ea | 8080 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 8081 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 8082 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
8083 | |
8084 | (define_insn "*xordi3_cconly" | |
ae156f85 | 8085 | [(set (reg CC_REGNUM) |
3e4be43f UW |
8086 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
8087 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 8088 | (const_int 0))) |
3e4be43f | 8089 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 8090 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 8091 | "@ |
d40c829f | 8092 | xgr\t%0,%2 |
65b1d8ea | 8093 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 8094 | xg\t%0,%2" |
65b1d8ea AK |
8095 | [(set_attr "op_type" "RRE,RRF,RXY") |
8096 | (set_attr "cpu_facility" "*,z196,*") | |
8097 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 8098 | |
3af8e996 | 8099 | (define_insn "*xordi3" |
3e4be43f UW |
8100 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
8101 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
8102 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 8103 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8104 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
8105 | "@ |
8106 | xihf\t%0,%k2 | |
8107 | xilf\t%0,%k2 | |
8108 | xgr\t%0,%2 | |
65b1d8ea | 8109 | xgrk\t%0,%1,%2 |
ec24698e UW |
8110 | xg\t%0,%2 |
8111 | # | |
8112 | #" | |
65b1d8ea AK |
8113 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
8114 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
8115 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
8116 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8117 | |
8118 | (define_split | |
8119 | [(set (match_operand:DI 0 "s_operand" "") | |
8120 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 8121 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8122 | "reload_completed" |
8123 | [(parallel | |
8124 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8125 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8126 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 8127 | |
9db1d521 HP |
8128 | ; |
8129 | ; xorsi3 instruction pattern(s). | |
8130 | ; | |
8131 | ||
4023fb28 | 8132 | (define_insn "*xorsi3_cc" |
ae156f85 | 8133 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8134 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8135 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8136 | (const_int 0))) |
65b1d8ea | 8137 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
8138 | (xor:SI (match_dup 1) (match_dup 2)))] |
8139 | "s390_match_ccmode(insn, CCTmode)" | |
8140 | "@ | |
ec24698e | 8141 | xilf\t%0,%o2 |
d40c829f | 8142 | xr\t%0,%2 |
65b1d8ea | 8143 | xrk\t%0,%1,%2 |
d40c829f UW |
8144 | x\t%0,%2 |
8145 | xy\t%0,%2" | |
65b1d8ea | 8146 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8147 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8148 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8149 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
8150 | |
8151 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 8152 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8153 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8154 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8155 | (const_int 0))) |
65b1d8ea | 8156 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
8157 | "s390_match_ccmode(insn, CCTmode)" |
8158 | "@ | |
ec24698e | 8159 | xilf\t%0,%o2 |
d40c829f | 8160 | xr\t%0,%2 |
65b1d8ea | 8161 | xrk\t%0,%1,%2 |
d40c829f UW |
8162 | x\t%0,%2 |
8163 | xy\t%0,%2" | |
65b1d8ea | 8164 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8165 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8166 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8167 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 8168 | |
8cb66696 | 8169 | (define_insn "*xorsi3" |
65b1d8ea AK |
8170 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
8171 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
8172 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 8173 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8174 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8175 | "@ |
ec24698e | 8176 | xilf\t%0,%o2 |
d40c829f | 8177 | xr\t%0,%2 |
65b1d8ea | 8178 | xrk\t%0,%1,%2 |
d40c829f | 8179 | x\t%0,%2 |
8cb66696 | 8180 | xy\t%0,%2 |
0dfa6c5e | 8181 | # |
19b63d8e | 8182 | #" |
65b1d8ea | 8183 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8184 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8185 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8186 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8187 | |
8188 | (define_split | |
8189 | [(set (match_operand:SI 0 "s_operand" "") | |
8190 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8191 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8192 | "reload_completed" |
8193 | [(parallel | |
8194 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8195 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8196 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8197 | |
9db1d521 HP |
8198 | ; |
8199 | ; xorhi3 instruction pattern(s). | |
8200 | ; | |
8201 | ||
8cb66696 | 8202 | (define_insn "*xorhi3" |
65b1d8ea AK |
8203 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8204 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8205 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8206 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8207 | "s390_logical_operator_ok_p (operands)" |
8208 | "@ | |
ec24698e | 8209 | xilf\t%0,%x2 |
8cb66696 | 8210 | xr\t%0,%2 |
65b1d8ea | 8211 | xrk\t%0,%1,%2 |
0dfa6c5e | 8212 | # |
19b63d8e | 8213 | #" |
65b1d8ea AK |
8214 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8215 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8216 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8217 | |
8218 | (define_split | |
8219 | [(set (match_operand:HI 0 "s_operand" "") | |
8220 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8221 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8222 | "reload_completed" |
8223 | [(parallel | |
8224 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8225 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8226 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8227 | |
9db1d521 HP |
8228 | ; |
8229 | ; xorqi3 instruction pattern(s). | |
8230 | ; | |
8231 | ||
8cb66696 | 8232 | (define_insn "*xorqi3" |
65b1d8ea AK |
8233 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8234 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8235 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8236 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8237 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8238 | "@ |
ec24698e | 8239 | xilf\t%0,%b2 |
8cb66696 | 8240 | xr\t%0,%2 |
65b1d8ea | 8241 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8242 | xi\t%S0,%b2 |
8243 | xiy\t%S0,%b2 | |
19b63d8e | 8244 | #" |
65b1d8ea | 8245 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8246 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8247 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8248 | |
4023fb28 | 8249 | |
19b63d8e UW |
8250 | ; |
8251 | ; Block exclusive or (XC) patterns. | |
8252 | ; | |
8253 | ||
8254 | (define_insn "*xc" | |
8255 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8256 | (xor:BLK (match_dup 0) | |
8257 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8258 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8259 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8260 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8261 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8262 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8263 | |
8264 | (define_split | |
8265 | [(set (match_operand 0 "memory_operand" "") | |
8266 | (xor (match_dup 0) | |
8267 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8268 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8269 | "reload_completed |
8270 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8271 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8272 | [(parallel | |
8273 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8274 | (use (match_dup 2)) | |
ae156f85 | 8275 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8276 | { |
8277 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8278 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8279 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8280 | }) | |
8281 | ||
8282 | (define_peephole2 | |
8283 | [(parallel | |
8284 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8285 | (xor:BLK (match_dup 0) | |
8286 | (match_operand:BLK 1 "memory_operand" ""))) | |
8287 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8288 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8289 | (parallel |
8290 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8291 | (xor:BLK (match_dup 3) | |
8292 | (match_operand:BLK 4 "memory_operand" ""))) | |
8293 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8294 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8295 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8296 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8297 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8298 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8299 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8300 | [(parallel | |
8301 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8302 | (use (match_dup 8)) | |
ae156f85 | 8303 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8304 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8305 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8306 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8307 | ||
8308 | ; | |
8309 | ; Block xor (XC) patterns with src == dest. | |
8310 | ; | |
8311 | ||
8312 | (define_insn "*xc_zero" | |
8313 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8314 | (const_int 0)) | |
8315 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8316 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8317 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8318 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8319 | [(set_attr "op_type" "SS") |
8320 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8321 | |
8322 | (define_peephole2 | |
8323 | [(parallel | |
8324 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8325 | (const_int 0)) | |
8326 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8327 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8328 | (parallel |
8329 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8330 | (const_int 0)) | |
8331 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8332 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8333 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8334 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8335 | [(parallel | |
8336 | [(set (match_dup 4) (const_int 0)) | |
8337 | (use (match_dup 5)) | |
ae156f85 | 8338 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8339 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8340 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8341 | ||
9db1d521 HP |
8342 | |
8343 | ;; | |
8344 | ;;- Negate instructions. | |
8345 | ;; | |
8346 | ||
8347 | ; | |
9a91a21f | 8348 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8349 | ; |
8350 | ||
9a91a21f | 8351 | (define_expand "neg<mode>2" |
9db1d521 | 8352 | [(parallel |
9a91a21f AS |
8353 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8354 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8355 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8356 | "" |
8357 | "") | |
8358 | ||
26a89301 | 8359 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8360 | [(set (reg CC_REGNUM) |
26a89301 UW |
8361 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8362 | (match_operand:SI 1 "register_operand" "d") 0) | |
8363 | (const_int 32)) (const_int 32))) | |
8364 | (const_int 0))) | |
8365 | (set (match_operand:DI 0 "register_operand" "=d") | |
8366 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8367 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8368 | "lcgfr\t%0,%1" |
729e750f WG |
8369 | [(set_attr "op_type" "RRE") |
8370 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8371 | |
26a89301 UW |
8372 | (define_insn "*negdi2_sign" |
8373 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8374 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8375 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8376 | "TARGET_ZARCH" |
26a89301 | 8377 | "lcgfr\t%0,%1" |
729e750f WG |
8378 | [(set_attr "op_type" "RRE") |
8379 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8380 | |
43a09b63 | 8381 | ; lcr, lcgr |
9a91a21f | 8382 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8383 | [(set (reg CC_REGNUM) |
9a91a21f | 8384 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8385 | (const_int 0))) |
9a91a21f AS |
8386 | (set (match_operand:GPR 0 "register_operand" "=d") |
8387 | (neg:GPR (match_dup 1)))] | |
8388 | "s390_match_ccmode (insn, CCAmode)" | |
8389 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8390 | [(set_attr "op_type" "RR<E>") |
8391 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8392 | |
8393 | ; lcr, lcgr | |
9a91a21f | 8394 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8395 | [(set (reg CC_REGNUM) |
9a91a21f | 8396 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8397 | (const_int 0))) |
9a91a21f AS |
8398 | (clobber (match_scratch:GPR 0 "=d"))] |
8399 | "s390_match_ccmode (insn, CCAmode)" | |
8400 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8401 | [(set_attr "op_type" "RR<E>") |
8402 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8403 | |
8404 | ; lcr, lcgr | |
9a91a21f AS |
8405 | (define_insn "*neg<mode>2" |
8406 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8407 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8408 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8409 | "" |
8410 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8411 | [(set_attr "op_type" "RR<E>") |
8412 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8413 | |
b7d19263 | 8414 | (define_insn "*negdi2_31" |
9db1d521 HP |
8415 | [(set (match_operand:DI 0 "register_operand" "=d") |
8416 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8417 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8418 | "!TARGET_ZARCH" |
b7d19263 AK |
8419 | "#") |
8420 | ||
8421 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8422 | ||
8423 | ; Doing the twos complement separately on the SImode parts does an | |
8424 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8425 | ; ... unless the +1 on the low part created an overflow. | |
8426 | ||
8427 | (define_split | |
8428 | [(set (match_operand:DI 0 "register_operand" "") | |
8429 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8430 | (clobber (reg:CC CC_REGNUM))] | |
8431 | "!TARGET_ZARCH | |
8432 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8433 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8434 | && reload_completed" | |
26a89301 UW |
8435 | [(parallel |
8436 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8437 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8438 | (parallel |
ae156f85 | 8439 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8440 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8441 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8442 | (set (pc) | |
ae156f85 | 8443 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8444 | (pc) |
8445 | (label_ref (match_dup 6)))) | |
8446 | (parallel | |
8447 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8448 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8449 | (match_dup 6)] |
8450 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8451 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8452 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8453 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8454 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8455 | |
b7d19263 AK |
8456 | ; Like above but first make a copy of the low part of the src operand |
8457 | ; since it might overlap with the high part of the destination. | |
8458 | ||
8459 | (define_split | |
8460 | [(set (match_operand:DI 0 "register_operand" "") | |
8461 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8462 | (clobber (reg:CC CC_REGNUM))] | |
8463 | "!TARGET_ZARCH | |
8464 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8465 | && reload_completed" | |
8466 | [; Make a backup of op5 first | |
8467 | (set (match_dup 4) (match_dup 5)) | |
8468 | ; Setting op2 here might clobber op5 | |
8469 | (parallel | |
8470 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8471 | (clobber (reg:CC CC_REGNUM))]) | |
8472 | (parallel | |
8473 | [(set (reg:CCAP CC_REGNUM) | |
8474 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8475 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8476 | (set (pc) | |
8477 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8478 | (pc) | |
8479 | (label_ref (match_dup 6)))) | |
8480 | (parallel | |
8481 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8482 | (clobber (reg:CC CC_REGNUM))]) | |
8483 | (match_dup 6)] | |
8484 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8485 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8486 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8487 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8488 | operands[6] = gen_label_rtx ();") | |
8489 | ||
9db1d521 | 8490 | ; |
f5905b37 | 8491 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8492 | ; |
8493 | ||
f5905b37 | 8494 | (define_expand "neg<mode>2" |
9db1d521 | 8495 | [(parallel |
2de2b3f9 AK |
8496 | [(set (match_operand:BFP 0 "register_operand") |
8497 | (neg:BFP (match_operand:BFP 1 "register_operand"))) | |
ae156f85 | 8498 | (clobber (reg:CC CC_REGNUM))])] |
2de2b3f9 | 8499 | "TARGET_HARD_FLOAT") |
9db1d521 | 8500 | |
43a09b63 | 8501 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8502 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8503 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8504 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8505 | (match_operand:BFP 2 "const0_operand" ""))) | |
8506 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8507 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8508 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8509 | "lc<xde>br\t%0,%1" |
26a89301 | 8510 | [(set_attr "op_type" "RRE") |
f5905b37 | 8511 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8512 | |
8513 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8514 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8515 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8516 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8517 | (match_operand:BFP 2 "const0_operand" ""))) | |
8518 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8519 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8520 | "lc<xde>br\t%0,%1" |
26a89301 | 8521 | [(set_attr "op_type" "RRE") |
f5905b37 | 8522 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8523 | |
85dae55a AK |
8524 | ; lcdfr |
8525 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8526 | [(set (match_operand:FP 0 "register_operand" "=f") |
8527 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8528 | "TARGET_DFP" |
85dae55a AK |
8529 | "lcdfr\t%0,%1" |
8530 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8531 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8532 | |
43a09b63 | 8533 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8534 | ; FIXME: wflcdb does not clobber cc |
2de2b3f9 | 8535 | ; FIXME: Does wflcdb ever match here? |
f5905b37 | 8536 | (define_insn "*neg<mode>2" |
2de2b3f9 AK |
8537 | [(set (match_operand:BFP 0 "register_operand" "=f,v,v") |
8538 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) | |
ae156f85 | 8539 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8540 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8541 | "@ |
8542 | lc<xde>br\t%0,%1 | |
2de2b3f9 AK |
8543 | wflcdb\t%0,%1 |
8544 | wflcsb\t%0,%1" | |
8545 | [(set_attr "op_type" "RRE,VRR,VRR") | |
8546 | (set_attr "cpu_facility" "*,vx,vxe") | |
8547 | (set_attr "type" "fsimp<mode>,*,*") | |
8548 | (set_attr "enabled" "*,<DF>,<SF>")]) | |
9db1d521 | 8549 | |
9db1d521 HP |
8550 | |
8551 | ;; | |
8552 | ;;- Absolute value instructions. | |
8553 | ;; | |
8554 | ||
8555 | ; | |
9a91a21f | 8556 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8557 | ; |
8558 | ||
26a89301 | 8559 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8560 | [(set (reg CC_REGNUM) |
26a89301 UW |
8561 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8562 | (match_operand:SI 1 "register_operand" "d") 0) | |
8563 | (const_int 32)) (const_int 32))) | |
8564 | (const_int 0))) | |
8565 | (set (match_operand:DI 0 "register_operand" "=d") | |
8566 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8567 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8568 | "lpgfr\t%0,%1" |
729e750f WG |
8569 | [(set_attr "op_type" "RRE") |
8570 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8571 | |
8572 | (define_insn "*absdi2_sign" | |
8573 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8574 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8575 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8576 | "TARGET_ZARCH" |
26a89301 | 8577 | "lpgfr\t%0,%1" |
729e750f WG |
8578 | [(set_attr "op_type" "RRE") |
8579 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8580 | |
43a09b63 | 8581 | ; lpr, lpgr |
9a91a21f | 8582 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8583 | [(set (reg CC_REGNUM) |
9a91a21f | 8584 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8585 | (const_int 0))) |
9a91a21f AS |
8586 | (set (match_operand:GPR 0 "register_operand" "=d") |
8587 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8588 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8589 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8590 | [(set_attr "op_type" "RR<E>") |
8591 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8592 | |
9381e3f1 | 8593 | ; lpr, lpgr |
9a91a21f | 8594 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8595 | [(set (reg CC_REGNUM) |
9a91a21f | 8596 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8597 | (const_int 0))) |
9a91a21f | 8598 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8599 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8600 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8601 | [(set_attr "op_type" "RR<E>") |
8602 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8603 | |
8604 | ; lpr, lpgr | |
9a91a21f AS |
8605 | (define_insn "abs<mode>2" |
8606 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8607 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8608 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8609 | "" |
9a91a21f | 8610 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8611 | [(set_attr "op_type" "RR<E>") |
8612 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8613 | |
9db1d521 | 8614 | ; |
f5905b37 | 8615 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8616 | ; |
8617 | ||
f5905b37 | 8618 | (define_expand "abs<mode>2" |
9db1d521 | 8619 | [(parallel |
7b6baae1 AK |
8620 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8621 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8622 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8623 | "TARGET_HARD_FLOAT" |
8624 | "") | |
8625 | ||
43a09b63 | 8626 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8627 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8628 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8629 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8630 | (match_operand:BFP 2 "const0_operand" ""))) | |
8631 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8632 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8633 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8634 | "lp<xde>br\t%0,%1" |
26a89301 | 8635 | [(set_attr "op_type" "RRE") |
f5905b37 | 8636 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8637 | |
8638 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8639 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8640 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8641 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8642 | (match_operand:BFP 2 "const0_operand" ""))) | |
8643 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8644 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8645 | "lp<xde>br\t%0,%1" |
26a89301 | 8646 | [(set_attr "op_type" "RRE") |
f5905b37 | 8647 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8648 | |
85dae55a AK |
8649 | ; lpdfr |
8650 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8651 | [(set (match_operand:FP 0 "register_operand" "=f") |
8652 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8653 | "TARGET_DFP" |
85dae55a AK |
8654 | "lpdfr\t%0,%1" |
8655 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8656 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8657 | |
43a09b63 | 8658 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8659 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8660 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8661 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8662 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8663 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8664 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8665 | "@ |
8666 | lp<xde>br\t%0,%1 | |
8667 | wflpdb\t%0,%1" | |
8668 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8669 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8670 | (set_attr "type" "fsimp<mode>,*") |
8671 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8672 | |
9db1d521 | 8673 | |
3ef093a8 AK |
8674 | ;; |
8675 | ;;- Negated absolute value instructions | |
8676 | ;; | |
8677 | ||
8678 | ; | |
8679 | ; Integer | |
8680 | ; | |
8681 | ||
26a89301 | 8682 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8683 | [(set (reg CC_REGNUM) |
26a89301 UW |
8684 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8685 | (match_operand:SI 1 "register_operand" "d") 0) | |
8686 | (const_int 32)) (const_int 32)))) | |
8687 | (const_int 0))) | |
8688 | (set (match_operand:DI 0 "register_operand" "=d") | |
8689 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8690 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8691 | "lngfr\t%0,%1" |
729e750f WG |
8692 | [(set_attr "op_type" "RRE") |
8693 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8694 | |
26a89301 UW |
8695 | (define_insn "*negabsdi2_sign" |
8696 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8697 | (neg:DI (abs:DI (sign_extend:DI | |
8698 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8699 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8700 | "TARGET_ZARCH" |
26a89301 | 8701 | "lngfr\t%0,%1" |
729e750f WG |
8702 | [(set_attr "op_type" "RRE") |
8703 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8704 | |
43a09b63 | 8705 | ; lnr, lngr |
9a91a21f | 8706 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8707 | [(set (reg CC_REGNUM) |
9a91a21f | 8708 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8709 | (const_int 0))) |
9a91a21f AS |
8710 | (set (match_operand:GPR 0 "register_operand" "=d") |
8711 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8712 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8713 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8714 | [(set_attr "op_type" "RR<E>") |
8715 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8716 | |
8717 | ; lnr, lngr | |
9a91a21f | 8718 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8719 | [(set (reg CC_REGNUM) |
9a91a21f | 8720 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8721 | (const_int 0))) |
9a91a21f | 8722 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8723 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8724 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8725 | [(set_attr "op_type" "RR<E>") |
8726 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8727 | |
8728 | ; lnr, lngr | |
9a91a21f AS |
8729 | (define_insn "*negabs<mode>2" |
8730 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8731 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8732 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8733 | "" |
9a91a21f | 8734 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8735 | [(set_attr "op_type" "RR<E>") |
8736 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8737 | |
3ef093a8 AK |
8738 | ; |
8739 | ; Floating point | |
8740 | ; | |
8741 | ||
43a09b63 | 8742 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8743 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8744 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8745 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8746 | (match_operand:BFP 2 "const0_operand" ""))) | |
8747 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8748 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8749 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8750 | "ln<xde>br\t%0,%1" |
26a89301 | 8751 | [(set_attr "op_type" "RRE") |
f5905b37 | 8752 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8753 | |
8754 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8755 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8756 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8757 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8758 | (match_operand:BFP 2 "const0_operand" ""))) | |
8759 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8760 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8761 | "ln<xde>br\t%0,%1" |
26a89301 | 8762 | [(set_attr "op_type" "RRE") |
f5905b37 | 8763 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8764 | |
85dae55a AK |
8765 | ; lndfr |
8766 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8767 | [(set (match_operand:FP 0 "register_operand" "=f") |
8768 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8769 | "TARGET_DFP" |
85dae55a AK |
8770 | "lndfr\t%0,%1" |
8771 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8772 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8773 | |
43a09b63 | 8774 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8775 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8776 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8777 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8778 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8779 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8780 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8781 | "@ |
8782 | ln<xde>br\t%0,%1 | |
8783 | wflndb\t%0,%1" | |
8784 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8785 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8786 | (set_attr "type" "fsimp<mode>,*") |
8787 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8788 | |
4023fb28 UW |
8789 | ;; |
8790 | ;;- Square root instructions. | |
8791 | ;; | |
8792 | ||
8793 | ; | |
f5905b37 | 8794 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8795 | ; |
8796 | ||
9381e3f1 | 8797 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8798 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8799 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8800 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8801 | "TARGET_HARD_FLOAT" |
4023fb28 | 8802 | "@ |
f61a2c7d | 8803 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8804 | sq<xde>b\t%0,%1 |
8805 | wfsqdb\t%v0,%v1" | |
8806 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8807 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 8808 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 8809 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 8810 | |
9db1d521 HP |
8811 | |
8812 | ;; | |
8813 | ;;- One complement instructions. | |
8814 | ;; | |
8815 | ||
8816 | ; | |
342cf42b | 8817 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8818 | ; |
c7453384 | 8819 | |
342cf42b | 8820 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8821 | [(parallel |
342cf42b AS |
8822 | [(set (match_operand:INT 0 "register_operand" "") |
8823 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8824 | (const_int -1))) | |
ae156f85 | 8825 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8826 | "" |
4023fb28 | 8827 | "") |
9db1d521 HP |
8828 | |
8829 | ||
ec24698e UW |
8830 | ;; |
8831 | ;; Find leftmost bit instructions. | |
8832 | ;; | |
8833 | ||
8834 | (define_expand "clzdi2" | |
8835 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8836 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8837 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 8838 | { |
d8485bdb TS |
8839 | rtx_insn *insn; |
8840 | rtx clz_equal; | |
ec24698e | 8841 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 8842 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
8843 | |
8844 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8845 | ||
8846 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8847 | ||
9381e3f1 | 8848 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8849 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8850 | |
8851 | DONE; | |
8852 | }) | |
8853 | ||
8854 | (define_insn "clztidi2" | |
8855 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8856 | (ior:TI | |
9381e3f1 WG |
8857 | (ashift:TI |
8858 | (zero_extend:TI | |
ec24698e UW |
8859 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8860 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8861 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8862 | |
ec24698e UW |
8863 | (const_int 64)) |
8864 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8865 | (clobber (reg:CC CC_REGNUM))] | |
406fde6e | 8866 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 8867 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8868 | "flogr\t%0,%1" |
8869 | [(set_attr "op_type" "RRE")]) | |
8870 | ||
8871 | ||
9db1d521 HP |
8872 | ;; |
8873 | ;;- Rotate instructions. | |
8874 | ;; | |
8875 | ||
8876 | ; | |
9a91a21f | 8877 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8878 | ; |
8879 | ||
191eb16d AK |
8880 | (define_expand "rotl<mode>3" |
8881 | [(set (match_operand:GPR 0 "register_operand" "") | |
8882 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8883 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
9e8327e3 | 8884 | "TARGET_CPU_ZARCH" |
191eb16d | 8885 | "") |
9db1d521 | 8886 | |
43a09b63 | 8887 | ; rll, rllg |
191eb16d AK |
8888 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8889 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8890 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8891 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8892 | "TARGET_CPU_ZARCH" | |
8893 | "rll<g>\t%0,%1,<addr_style_op_ops>" | |
4989e88a | 8894 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8895 | (set_attr "atype" "reg") |
191eb16d | 8896 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8897 | |
9db1d521 HP |
8898 | |
8899 | ;; | |
f337b930 | 8900 | ;;- Shift instructions. |
9db1d521 | 8901 | ;; |
9db1d521 HP |
8902 | |
8903 | ; | |
1b48c8cc | 8904 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8905 | ; Left shifts and logical right shifts |
9db1d521 | 8906 | |
1b48c8cc AS |
8907 | (define_expand "<shift><mode>3" |
8908 | [(set (match_operand:DSI 0 "register_operand" "") | |
8909 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8910 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8911 | "" |
8912 | "") | |
8913 | ||
adf22b3f | 8914 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8915 | ; sldl, srdl |
adf22b3f AK |
8916 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8917 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8918 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8919 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8920 | "!TARGET_ZARCH" |
adf22b3f | 8921 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8922 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8923 | (set_attr "atype" "reg") |
8924 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8925 | |
adf22b3f AK |
8926 | |
8927 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8928 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8929 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8930 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8931 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8932 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8933 | "" |
65b1d8ea | 8934 | "@ |
adf22b3f AK |
8935 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8936 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8937 | [(set_attr "op_type" "RS<E>,RSY") |
8938 | (set_attr "atype" "reg,reg") | |
8939 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8940 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8941 | |
9db1d521 | 8942 | ; |
1b48c8cc | 8943 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8944 | ; Arithmetic right shifts |
9db1d521 | 8945 | |
1b48c8cc | 8946 | (define_expand "ashr<mode>3" |
9db1d521 | 8947 | [(parallel |
1b48c8cc AS |
8948 | [(set (match_operand:DSI 0 "register_operand" "") |
8949 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8950 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8951 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8952 | "" |
8953 | "") | |
8954 | ||
a9fcf821 AK |
8955 | ; FIXME: The number of alternatives is doubled here to match the fix |
8956 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8957 | ; The right fix should be to support match_scratch in the output | |
8958 | ; pattern of a define_subst. | |
8959 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8960 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8961 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8962 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8963 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8964 | "!TARGET_ZARCH" |
65b1d8ea | 8965 | "@ |
a9fcf821 AK |
8966 | srda\t%0,<addr_style_op_cc_ops> |
8967 | srda\t%0,<addr_style_op_cc_ops>" | |
8968 | [(set_attr "op_type" "RS") | |
8969 | (set_attr "atype" "reg")]) | |
ecbe845e | 8970 | |
ecbe845e | 8971 | |
43a09b63 | 8972 | ; sra, srag |
a9fcf821 AK |
8973 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8974 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8975 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8976 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8977 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8978 | "" |
65b1d8ea | 8979 | "@ |
a9fcf821 AK |
8980 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8981 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8982 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8983 | (set_attr "atype" "reg") |
01496eca | 8984 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8985 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8986 | |
9db1d521 | 8987 | |
9db1d521 HP |
8988 | ;; |
8989 | ;; Branch instruction patterns. | |
8990 | ;; | |
8991 | ||
f90b7a5a | 8992 | (define_expand "cbranch<mode>4" |
fa77b251 | 8993 | [(set (pc) |
f90b7a5a PB |
8994 | (if_then_else (match_operator 0 "comparison_operator" |
8995 | [(match_operand:GPR 1 "register_operand" "") | |
8996 | (match_operand:GPR 2 "general_operand" "")]) | |
8997 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8998 | (pc)))] |
ba956982 | 8999 | "" |
f90b7a5a PB |
9000 | "s390_emit_jump (operands[3], |
9001 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
9002 | DONE;") | |
9003 | ||
9004 | (define_expand "cbranch<mode>4" | |
9005 | [(set (pc) | |
9006 | (if_then_else (match_operator 0 "comparison_operator" | |
9007 | [(match_operand:FP 1 "register_operand" "") | |
9008 | (match_operand:FP 2 "general_operand" "")]) | |
9009 | (label_ref (match_operand 3 "" "")) | |
9010 | (pc)))] | |
9011 | "TARGET_HARD_FLOAT" | |
9012 | "s390_emit_jump (operands[3], | |
9013 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
9014 | DONE;") | |
9015 | ||
9016 | (define_expand "cbranchcc4" | |
9017 | [(set (pc) | |
de6fba39 | 9018 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 9019 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 9020 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
9021 | (label_ref (match_operand 3 "" "")) |
9022 | (pc)))] | |
de6fba39 UW |
9023 | "" |
9024 | "") | |
ba956982 | 9025 | |
9db1d521 HP |
9026 | |
9027 | ;; | |
9028 | ;;- Conditional jump instructions. | |
9029 | ;; | |
9030 | ||
6590e19a UW |
9031 | (define_insn "*cjump_64" |
9032 | [(set (pc) | |
9033 | (if_then_else | |
5a3fe9b6 AK |
9034 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
9035 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
9036 | (label_ref (match_operand 0 "" "")) |
9037 | (pc)))] | |
9038 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9039 | { |
13e58269 | 9040 | if (get_attr_length (insn) == 4) |
d40c829f | 9041 | return "j%C1\t%l0"; |
6590e19a | 9042 | else |
d40c829f | 9043 | return "jg%C1\t%l0"; |
6590e19a UW |
9044 | } |
9045 | [(set_attr "op_type" "RI") | |
9046 | (set_attr "type" "branch") | |
9047 | (set (attr "length") | |
9048 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9049 | (const_int 4) (const_int 6)))]) | |
9050 | ||
9051 | (define_insn "*cjump_31" | |
9052 | [(set (pc) | |
9053 | (if_then_else | |
5a3fe9b6 AK |
9054 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
9055 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
9056 | (label_ref (match_operand 0 "" "")) |
9057 | (pc)))] | |
9058 | "!TARGET_CPU_ZARCH" | |
9059 | { | |
8d933e31 AS |
9060 | gcc_assert (get_attr_length (insn) == 4); |
9061 | return "j%C1\t%l0"; | |
10bbf137 | 9062 | } |
9db1d521 | 9063 | [(set_attr "op_type" "RI") |
077dab3b | 9064 | (set_attr "type" "branch") |
13e58269 | 9065 | (set (attr "length") |
d7f99b2c | 9066 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9067 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9068 | (const_int 4) (const_int 6)) | |
9069 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9070 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9071 | |
f314b9b1 | 9072 | (define_insn "*cjump_long" |
6590e19a UW |
9073 | [(set (pc) |
9074 | (if_then_else | |
ae156f85 | 9075 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 9076 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 9077 | (pc)))] |
9db1d521 | 9078 | "" |
f314b9b1 UW |
9079 | { |
9080 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9081 | return "b%C1r\t%0"; |
f314b9b1 | 9082 | else |
d40c829f | 9083 | return "b%C1\t%a0"; |
10bbf137 | 9084 | } |
c7453384 | 9085 | [(set (attr "op_type") |
f314b9b1 UW |
9086 | (if_then_else (match_operand 0 "register_operand" "") |
9087 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 9088 | (set_attr "type" "branch") |
077dab3b | 9089 | (set_attr "atype" "agen")]) |
9db1d521 | 9090 | |
177bc204 RS |
9091 | ;; A conditional return instruction. |
9092 | (define_insn "*c<code>" | |
9093 | [(set (pc) | |
9094 | (if_then_else | |
9095 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
9096 | (ANY_RETURN) | |
9097 | (pc)))] | |
9098 | "s390_can_use_<code>_insn ()" | |
9099 | "b%C0r\t%%r14" | |
9100 | [(set_attr "op_type" "RR") | |
9101 | (set_attr "type" "jsr") | |
9102 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
9103 | |
9104 | ;; | |
9105 | ;;- Negated conditional jump instructions. | |
9106 | ;; | |
9107 | ||
6590e19a UW |
9108 | (define_insn "*icjump_64" |
9109 | [(set (pc) | |
9110 | (if_then_else | |
ae156f85 | 9111 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9112 | (pc) |
9113 | (label_ref (match_operand 0 "" ""))))] | |
9114 | "TARGET_CPU_ZARCH" | |
c7453384 | 9115 | { |
13e58269 | 9116 | if (get_attr_length (insn) == 4) |
d40c829f | 9117 | return "j%D1\t%l0"; |
6590e19a | 9118 | else |
d40c829f | 9119 | return "jg%D1\t%l0"; |
6590e19a UW |
9120 | } |
9121 | [(set_attr "op_type" "RI") | |
9122 | (set_attr "type" "branch") | |
9123 | (set (attr "length") | |
9124 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9125 | (const_int 4) (const_int 6)))]) | |
9126 | ||
9127 | (define_insn "*icjump_31" | |
9128 | [(set (pc) | |
9129 | (if_then_else | |
ae156f85 | 9130 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9131 | (pc) |
9132 | (label_ref (match_operand 0 "" ""))))] | |
9133 | "!TARGET_CPU_ZARCH" | |
9134 | { | |
8d933e31 AS |
9135 | gcc_assert (get_attr_length (insn) == 4); |
9136 | return "j%D1\t%l0"; | |
10bbf137 | 9137 | } |
9db1d521 | 9138 | [(set_attr "op_type" "RI") |
077dab3b | 9139 | (set_attr "type" "branch") |
13e58269 | 9140 | (set (attr "length") |
d7f99b2c | 9141 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9142 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9143 | (const_int 4) (const_int 6)) | |
9144 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9145 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9146 | |
f314b9b1 | 9147 | (define_insn "*icjump_long" |
6590e19a UW |
9148 | [(set (pc) |
9149 | (if_then_else | |
ae156f85 | 9150 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 9151 | (pc) |
4fe6dea8 | 9152 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 9153 | "" |
f314b9b1 UW |
9154 | { |
9155 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9156 | return "b%D1r\t%0"; |
f314b9b1 | 9157 | else |
d40c829f | 9158 | return "b%D1\t%a0"; |
10bbf137 | 9159 | } |
c7453384 | 9160 | [(set (attr "op_type") |
f314b9b1 UW |
9161 | (if_then_else (match_operand 0 "register_operand" "") |
9162 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9163 | (set_attr "type" "branch") |
9164 | (set_attr "atype" "agen")]) | |
9db1d521 | 9165 | |
4456530d HP |
9166 | ;; |
9167 | ;;- Trap instructions. | |
9168 | ;; | |
9169 | ||
9170 | (define_insn "trap" | |
9171 | [(trap_if (const_int 1) (const_int 0))] | |
9172 | "" | |
d40c829f | 9173 | "j\t.+2" |
6590e19a | 9174 | [(set_attr "op_type" "RI") |
077dab3b | 9175 | (set_attr "type" "branch")]) |
4456530d | 9176 | |
f90b7a5a PB |
9177 | (define_expand "ctrap<mode>4" |
9178 | [(trap_if (match_operator 0 "comparison_operator" | |
9179 | [(match_operand:GPR 1 "register_operand" "") | |
9180 | (match_operand:GPR 2 "general_operand" "")]) | |
9181 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 9182 | "" |
f90b7a5a PB |
9183 | { |
9184 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9185 | operands[1], operands[2]); | |
9186 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9187 | DONE; | |
9188 | }) | |
9189 | ||
9190 | (define_expand "ctrap<mode>4" | |
9191 | [(trap_if (match_operator 0 "comparison_operator" | |
9192 | [(match_operand:FP 1 "register_operand" "") | |
9193 | (match_operand:FP 2 "general_operand" "")]) | |
9194 | (match_operand 3 "const0_operand" ""))] | |
9195 | "" | |
9196 | { | |
9197 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9198 | operands[1], operands[2]); | |
9199 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9200 | DONE; | |
9201 | }) | |
4456530d | 9202 | |
f90b7a5a PB |
9203 | (define_insn "condtrap" |
9204 | [(trap_if (match_operator 0 "s390_comparison" | |
9205 | [(match_operand 1 "cc_reg_operand" "c") | |
9206 | (const_int 0)]) | |
4456530d HP |
9207 | (const_int 0))] |
9208 | "" | |
d40c829f | 9209 | "j%C0\t.+2"; |
077dab3b HP |
9210 | [(set_attr "op_type" "RI") |
9211 | (set_attr "type" "branch")]) | |
9db1d521 | 9212 | |
963fc8d0 AK |
9213 | ; crt, cgrt, cit, cgit |
9214 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9215 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9216 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9217 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9218 | (const_int 0))] | |
9219 | "TARGET_Z10" | |
9220 | "@ | |
9221 | c<g>rt%C0\t%1,%2 | |
9222 | c<g>it%C0\t%1,%h2" | |
9223 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9224 | (set_attr "type" "branch") |
729e750f | 9225 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9226 | |
22ac2c2f | 9227 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9228 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9229 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9230 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9231 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9232 | (const_int 0))] |
9233 | "TARGET_Z10" | |
9234 | "@ | |
9235 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9236 | cl<gf>it%C0\t%1,%x2 |
9237 | cl<g>t%C0\t%1,%2" | |
9238 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9239 | (set_attr "type" "branch") | |
9240 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9241 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9242 | ||
9243 | ; lat, lgat | |
9244 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9245 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9246 | (const_int 0)) |
9247 | (const_int 0)) | |
9248 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9249 | (match_dup 0))] | |
9250 | "TARGET_ZEC12" | |
9251 | "l<g>at\t%1,%0" | |
9252 | [(set_attr "op_type" "RXY")]) | |
9253 | ||
963fc8d0 | 9254 | |
9db1d521 | 9255 | ;; |
0a3bdf9d | 9256 | ;;- Loop instructions. |
9db1d521 | 9257 | ;; |
0a3bdf9d UW |
9258 | ;; This is all complicated by the fact that since this is a jump insn |
9259 | ;; we must handle our own output reloads. | |
c7453384 | 9260 | |
f1149235 AK |
9261 | ;; branch on index |
9262 | ||
9263 | ; This splitter will be matched by combine and has to add the 2 moves | |
9264 | ; necessary to load the compare and the increment values into a | |
9265 | ; register pair as needed by brxle. | |
9266 | ||
9267 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9268 | [(set (pc) | |
9269 | (if_then_else | |
9270 | (match_operator 6 "s390_brx_operator" | |
9271 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9272 | (match_operand:GPR 2 "general_operand" "")) | |
9273 | (match_operand:GPR 3 "register_operand" "")]) | |
9274 | (label_ref (match_operand 0 "" "")) | |
9275 | (pc))) | |
9276 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9277 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9278 | (clobber (match_scratch:GPR 5 ""))] | |
9279 | "TARGET_CPU_ZARCH" | |
9280 | "#" | |
9281 | "!reload_completed && !reload_in_progress" | |
9282 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9283 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9284 | (parallel [(set (pc) | |
9285 | (if_then_else | |
9286 | (match_op_dup 6 | |
9287 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9288 | (match_dup 8)]) | |
9289 | (label_ref (match_dup 0)) | |
9290 | (pc))) | |
9291 | (set (match_dup 4) | |
9292 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9293 | (clobber (match_dup 5)) | |
9294 | (clobber (reg:CC CC_REGNUM))])] | |
9295 | { | |
9296 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9297 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9298 | gen_highpart (word_mode, dreg)); | |
9299 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9300 | gen_lowpart (word_mode, dreg)); | |
9301 | }) | |
9302 | ||
9303 | ; brxlg, brxhg | |
9304 | ||
9305 | (define_insn_and_split "*brxg_64bit" | |
9306 | [(set (pc) | |
9307 | (if_then_else | |
9308 | (match_operator 5 "s390_brx_operator" | |
9309 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9310 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9311 | (subreg:DI (match_dup 2) 8)]) | |
9312 | (label_ref (match_operand 0 "" "")) | |
9313 | (pc))) | |
9314 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9315 | (plus:DI (match_dup 1) | |
9316 | (subreg:DI (match_dup 2) 0))) | |
9317 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9318 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9319 | "TARGET_ZARCH" |
f1149235 AK |
9320 | { |
9321 | if (which_alternative != 0) | |
9322 | return "#"; | |
9323 | else if (get_attr_length (insn) == 6) | |
9324 | return "brx%E5g\t%1,%2,%l0"; | |
9325 | else | |
9326 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9327 | } | |
9328 | "&& reload_completed | |
9329 | && (!REG_P (operands[3]) | |
9330 | || !rtx_equal_p (operands[1], operands[3]))" | |
9331 | [(set (match_dup 4) (match_dup 1)) | |
9332 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9333 | (clobber (reg:CC CC_REGNUM))]) | |
9334 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9335 | (set (match_dup 3) (match_dup 4)) | |
9336 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9337 | (label_ref (match_dup 0)) | |
9338 | (pc)))] | |
9339 | "" | |
9340 | [(set_attr "op_type" "RIE") | |
9341 | (set_attr "type" "branch") | |
9342 | (set (attr "length") | |
9343 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9344 | (const_int 6) (const_int 16)))]) | |
9345 | ||
9346 | ; brxle, brxh | |
9347 | ||
9348 | (define_insn_and_split "*brx_64bit" | |
9349 | [(set (pc) | |
9350 | (if_then_else | |
9351 | (match_operator 5 "s390_brx_operator" | |
9352 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9353 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9354 | (subreg:SI (match_dup 2) 12)]) | |
9355 | (label_ref (match_operand 0 "" "")) | |
9356 | (pc))) | |
9357 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9358 | (plus:SI (match_dup 1) | |
9359 | (subreg:SI (match_dup 2) 4))) | |
9360 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9361 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9362 | "TARGET_ZARCH" |
f1149235 AK |
9363 | { |
9364 | if (which_alternative != 0) | |
9365 | return "#"; | |
9366 | else if (get_attr_length (insn) == 6) | |
9367 | return "brx%C5\t%1,%2,%l0"; | |
9368 | else | |
9369 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9370 | } | |
9371 | "&& reload_completed | |
9372 | && (!REG_P (operands[3]) | |
9373 | || !rtx_equal_p (operands[1], operands[3]))" | |
9374 | [(set (match_dup 4) (match_dup 1)) | |
9375 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9376 | (clobber (reg:CC CC_REGNUM))]) | |
9377 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9378 | (set (match_dup 3) (match_dup 4)) | |
9379 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9380 | (label_ref (match_dup 0)) | |
9381 | (pc)))] | |
9382 | "" | |
9383 | [(set_attr "op_type" "RSI") | |
9384 | (set_attr "type" "branch") | |
9385 | (set (attr "length") | |
9386 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9387 | (const_int 6) (const_int 14)))]) | |
9388 | ||
9389 | ; brxle, brxh | |
9390 | ||
9391 | (define_insn_and_split "*brx_31bit" | |
9392 | [(set (pc) | |
9393 | (if_then_else | |
9394 | (match_operator 5 "s390_brx_operator" | |
9395 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9396 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9397 | (subreg:SI (match_dup 2) 4)]) | |
9398 | (label_ref (match_operand 0 "" "")) | |
9399 | (pc))) | |
9400 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9401 | (plus:SI (match_dup 1) | |
9402 | (subreg:SI (match_dup 2) 0))) | |
9403 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9404 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9405 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
9406 | { |
9407 | if (which_alternative != 0) | |
9408 | return "#"; | |
9409 | else if (get_attr_length (insn) == 6) | |
9410 | return "brx%C5\t%1,%2,%l0"; | |
9411 | else | |
9412 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9413 | } | |
9414 | "&& reload_completed | |
9415 | && (!REG_P (operands[3]) | |
9416 | || !rtx_equal_p (operands[1], operands[3]))" | |
9417 | [(set (match_dup 4) (match_dup 1)) | |
9418 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9419 | (clobber (reg:CC CC_REGNUM))]) | |
9420 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9421 | (set (match_dup 3) (match_dup 4)) | |
9422 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9423 | (label_ref (match_dup 0)) | |
9424 | (pc)))] | |
9425 | "" | |
9426 | [(set_attr "op_type" "RSI") | |
9427 | (set_attr "type" "branch") | |
9428 | (set (attr "length") | |
9429 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9430 | (const_int 6) (const_int 14)))]) | |
9431 | ||
9432 | ||
9433 | ;; branch on count | |
9434 | ||
0a3bdf9d UW |
9435 | (define_expand "doloop_end" |
9436 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9437 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9438 | "" |
0a3bdf9d | 9439 | { |
6590e19a | 9440 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 9441 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 9442 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 9443 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9444 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9445 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9446 | else |
9447 | FAIL; | |
9448 | ||
9449 | DONE; | |
10bbf137 | 9450 | }) |
0a3bdf9d | 9451 | |
6590e19a | 9452 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9453 | [(set (pc) |
9454 | (if_then_else | |
7e665d18 | 9455 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9456 | (const_int 1)) |
9457 | (label_ref (match_operand 0 "" "")) | |
9458 | (pc))) | |
7e665d18 | 9459 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9460 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9461 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9462 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9463 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9464 | { |
9465 | if (which_alternative != 0) | |
10bbf137 | 9466 | return "#"; |
0a3bdf9d | 9467 | else if (get_attr_length (insn) == 4) |
d40c829f | 9468 | return "brct\t%1,%l0"; |
6590e19a | 9469 | else |
545d16ff | 9470 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9471 | } |
9472 | "&& reload_completed | |
9473 | && (! REG_P (operands[2]) | |
9474 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9475 | [(set (match_dup 3) (match_dup 1)) |
9476 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9477 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9478 | (const_int 0))) | |
9479 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9480 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9481 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9482 | (label_ref (match_dup 0)) |
9483 | (pc)))] | |
9484 | "" | |
9485 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9486 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9487 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9488 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9489 | (set_attr "type" "branch") |
9490 | (set (attr "length") | |
9491 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9492 | (const_int 4) (const_int 10)))]) | |
9493 | ||
9494 | (define_insn_and_split "doloop_si31" | |
9495 | [(set (pc) | |
9496 | (if_then_else | |
7e665d18 | 9497 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
9498 | (const_int 1)) |
9499 | (label_ref (match_operand 0 "" "")) | |
9500 | (pc))) | |
7e665d18 | 9501 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 9502 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9503 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9504 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
9505 | "!TARGET_CPU_ZARCH" |
9506 | { | |
9507 | if (which_alternative != 0) | |
9508 | return "#"; | |
9509 | else if (get_attr_length (insn) == 4) | |
9510 | return "brct\t%1,%l0"; | |
0a3bdf9d | 9511 | else |
8d933e31 | 9512 | gcc_unreachable (); |
10bbf137 | 9513 | } |
6590e19a UW |
9514 | "&& reload_completed |
9515 | && (! REG_P (operands[2]) | |
9516 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9517 | [(set (match_dup 3) (match_dup 1)) |
9518 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9519 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9520 | (const_int 0))) | |
9521 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9522 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9523 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9524 | (label_ref (match_dup 0)) |
9525 | (pc)))] | |
9526 | "" | |
0a3bdf9d | 9527 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
9528 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9529 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9530 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 9531 | (set_attr "type" "branch") |
0a3bdf9d | 9532 | (set (attr "length") |
d7f99b2c | 9533 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9534 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9535 | (const_int 4) (const_int 6)) | |
9536 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9537 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9538 | |
0a3bdf9d UW |
9539 | (define_insn "*doloop_si_long" |
9540 | [(set (pc) | |
9541 | (if_then_else | |
7e665d18 | 9542 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 9543 | (const_int 1)) |
3e4be43f | 9544 | (match_operand 0 "address_operand" "ZR") |
0a3bdf9d | 9545 | (pc))) |
7e665d18 | 9546 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 9547 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9548 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 9549 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9550 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9551 | { |
9552 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9553 | return "bctr\t%1,%0"; |
0a3bdf9d | 9554 | else |
d40c829f | 9555 | return "bct\t%1,%a0"; |
10bbf137 | 9556 | } |
c7453384 | 9557 | [(set (attr "op_type") |
0a3bdf9d UW |
9558 | (if_then_else (match_operand 0 "register_operand" "") |
9559 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9560 | (set_attr "type" "branch") |
729e750f | 9561 | (set_attr "atype" "agen") |
65b1d8ea AK |
9562 | (set_attr "z10prop" "z10_c") |
9563 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 9564 | |
6590e19a | 9565 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9566 | [(set (pc) |
9567 | (if_then_else | |
7e665d18 | 9568 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9569 | (const_int 1)) |
9570 | (label_ref (match_operand 0 "" "")) | |
9571 | (pc))) | |
7e665d18 | 9572 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9573 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9574 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9575 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9576 | "TARGET_ZARCH" |
0a3bdf9d UW |
9577 | { |
9578 | if (which_alternative != 0) | |
10bbf137 | 9579 | return "#"; |
0a3bdf9d | 9580 | else if (get_attr_length (insn) == 4) |
d40c829f | 9581 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9582 | else |
545d16ff | 9583 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9584 | } |
6590e19a | 9585 | "&& reload_completed |
0a3bdf9d UW |
9586 | && (! REG_P (operands[2]) |
9587 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9588 | [(set (match_dup 3) (match_dup 1)) |
9589 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9590 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9591 | (const_int 0))) | |
9592 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9593 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9594 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9595 | (label_ref (match_dup 0)) |
0a3bdf9d | 9596 | (pc)))] |
6590e19a UW |
9597 | "" |
9598 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9599 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9600 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9601 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9602 | (set_attr "type" "branch") |
9603 | (set (attr "length") | |
9604 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9605 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9606 | |
9607 | ;; | |
9608 | ;;- Unconditional jump instructions. | |
9609 | ;; | |
9610 | ||
9611 | ; | |
9612 | ; jump instruction pattern(s). | |
9613 | ; | |
9614 | ||
6590e19a UW |
9615 | (define_expand "jump" |
9616 | [(match_operand 0 "" "")] | |
9db1d521 | 9617 | "" |
6590e19a UW |
9618 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9619 | ||
9620 | (define_insn "*jump64" | |
9621 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9622 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9623 | { |
13e58269 | 9624 | if (get_attr_length (insn) == 4) |
d40c829f | 9625 | return "j\t%l0"; |
6590e19a | 9626 | else |
d40c829f | 9627 | return "jg\t%l0"; |
6590e19a UW |
9628 | } |
9629 | [(set_attr "op_type" "RI") | |
9630 | (set_attr "type" "branch") | |
9631 | (set (attr "length") | |
9632 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9633 | (const_int 4) (const_int 6)))]) | |
9634 | ||
9635 | (define_insn "*jump31" | |
9636 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9637 | "!TARGET_CPU_ZARCH" | |
9638 | { | |
8d933e31 AS |
9639 | gcc_assert (get_attr_length (insn) == 4); |
9640 | return "j\t%l0"; | |
10bbf137 | 9641 | } |
9db1d521 | 9642 | [(set_attr "op_type" "RI") |
077dab3b | 9643 | (set_attr "type" "branch") |
13e58269 | 9644 | (set (attr "length") |
d7f99b2c | 9645 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9646 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9647 | (const_int 4) (const_int 6)) | |
9648 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9649 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
9650 | |
9651 | ; | |
9652 | ; indirect-jump instruction pattern(s). | |
9653 | ; | |
9654 | ||
2841f550 AK |
9655 | (define_expand "indirect_jump" |
9656 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9657 | "" |
f314b9b1 | 9658 | { |
2841f550 AK |
9659 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9660 | ; | |
9661 | else if (TARGET_ARCH12 | |
9662 | && GET_MODE (operands[0]) == Pmode | |
9663 | && memory_operand (operands[0], Pmode)) | |
9664 | ; | |
f314b9b1 | 9665 | else |
2841f550 AK |
9666 | operands[0] = force_reg (Pmode, operands[0]); |
9667 | }) | |
9668 | ||
00e0af8d AK |
9669 | ; The first constraint must be an "extra address constraint" in order |
9670 | ; to trigger address reloading in LRA/reload | |
2841f550 AK |
9671 | (define_insn "*indirect_jump" |
9672 | [(set (pc) | |
00e0af8d | 9673 | (match_operand 0 "address_operand" "ZR,a"))] |
2841f550 AK |
9674 | "" |
9675 | "@ | |
00e0af8d AK |
9676 | b\t%a0 |
9677 | br\t%0" | |
9678 | [(set_attr "op_type" "RX,RR") | |
2841f550 AK |
9679 | (set_attr "type" "branch") |
9680 | (set_attr "atype" "agen") | |
9681 | (set_attr "cpu_facility" "*")]) | |
9682 | ||
9683 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9684 | ; checked against address constraints like ZR above. So make this a | |
9685 | ; separate pattern for now. | |
9686 | (define_insn "*indirect2_jump" | |
9687 | [(set (pc) | |
9688 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
9689 | "" | |
9690 | "@ | |
9691 | br\t%0 | |
9692 | bi\t%0" | |
9693 | [(set_attr "op_type" "RR,RXY") | |
9694 | (set_attr "type" "branch") | |
9695 | (set_attr "atype" "agen") | |
9696 | (set_attr "cpu_facility" "*,arch12")]) | |
9db1d521 HP |
9697 | |
9698 | ; | |
f314b9b1 | 9699 | ; casesi instruction pattern(s). |
9db1d521 HP |
9700 | ; |
9701 | ||
f314b9b1 | 9702 | (define_insn "casesi_jump" |
3e4be43f | 9703 | [(set (pc) (match_operand 0 "address_operand" "ZR")) |
f314b9b1 | 9704 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 9705 | "" |
9db1d521 | 9706 | { |
f314b9b1 | 9707 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9708 | return "br\t%0"; |
f314b9b1 | 9709 | else |
d40c829f | 9710 | return "b\t%a0"; |
10bbf137 | 9711 | } |
c7453384 | 9712 | [(set (attr "op_type") |
f314b9b1 UW |
9713 | (if_then_else (match_operand 0 "register_operand" "") |
9714 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9715 | (set_attr "type" "branch") |
9716 | (set_attr "atype" "agen")]) | |
9db1d521 | 9717 | |
f314b9b1 UW |
9718 | (define_expand "casesi" |
9719 | [(match_operand:SI 0 "general_operand" "") | |
9720 | (match_operand:SI 1 "general_operand" "") | |
9721 | (match_operand:SI 2 "general_operand" "") | |
9722 | (label_ref (match_operand 3 "" "")) | |
9723 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9724 | "" |
f314b9b1 UW |
9725 | { |
9726 | rtx index = gen_reg_rtx (SImode); | |
9727 | rtx base = gen_reg_rtx (Pmode); | |
9728 | rtx target = gen_reg_rtx (Pmode); | |
9729 | ||
9730 | emit_move_insn (index, operands[0]); | |
9731 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9732 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9733 | operands[4]); |
f314b9b1 UW |
9734 | |
9735 | if (Pmode != SImode) | |
9736 | index = convert_to_mode (Pmode, index, 1); | |
9737 | if (GET_CODE (index) != REG) | |
9738 | index = copy_to_mode_reg (Pmode, index); | |
9739 | ||
9740 | if (TARGET_64BIT) | |
9741 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9742 | else | |
a556fd39 | 9743 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9744 | |
f314b9b1 UW |
9745 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9746 | ||
542a8afa | 9747 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9748 | emit_move_insn (target, index); |
9749 | ||
9750 | if (flag_pic) | |
9751 | target = gen_rtx_PLUS (Pmode, base, target); | |
9752 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9753 | ||
9754 | DONE; | |
10bbf137 | 9755 | }) |
9db1d521 HP |
9756 | |
9757 | ||
9758 | ;; | |
9759 | ;;- Jump to subroutine. | |
9760 | ;; | |
9761 | ;; | |
9762 | ||
9763 | ; | |
9764 | ; untyped call instruction pattern(s). | |
9765 | ; | |
9766 | ||
9767 | ;; Call subroutine returning any type. | |
9768 | (define_expand "untyped_call" | |
9769 | [(parallel [(call (match_operand 0 "" "") | |
9770 | (const_int 0)) | |
9771 | (match_operand 1 "" "") | |
9772 | (match_operand 2 "" "")])] | |
9773 | "" | |
9db1d521 HP |
9774 | { |
9775 | int i; | |
9776 | ||
9777 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9778 | ||
9779 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9780 | { | |
9781 | rtx set = XVECEXP (operands[2], 0, i); | |
9782 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9783 | } | |
9784 | ||
9785 | /* The optimizer does not know that the call sets the function value | |
9786 | registers we stored in the result block. We avoid problems by | |
9787 | claiming that all hard registers are used and clobbered at this | |
9788 | point. */ | |
9789 | emit_insn (gen_blockage ()); | |
9790 | ||
9791 | DONE; | |
10bbf137 | 9792 | }) |
9db1d521 HP |
9793 | |
9794 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9795 | ;; all of memory. This blocks insns from being moved across this point. | |
9796 | ||
9797 | (define_insn "blockage" | |
10bbf137 | 9798 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9799 | "" |
4023fb28 | 9800 | "" |
d5869ca0 UW |
9801 | [(set_attr "type" "none") |
9802 | (set_attr "length" "0")]) | |
4023fb28 | 9803 | |
9db1d521 | 9804 | ; |
ed9676cf | 9805 | ; sibcall patterns |
9db1d521 HP |
9806 | ; |
9807 | ||
ed9676cf | 9808 | (define_expand "sibcall" |
44b8152b | 9809 | [(call (match_operand 0 "" "") |
ed9676cf | 9810 | (match_operand 1 "" ""))] |
9db1d521 | 9811 | "" |
9db1d521 | 9812 | { |
ed9676cf AK |
9813 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9814 | DONE; | |
9815 | }) | |
9db1d521 | 9816 | |
ed9676cf | 9817 | (define_insn "*sibcall_br" |
ae156f85 | 9818 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9819 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9820 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9821 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
9822 | "br\t%%r1" | |
9823 | [(set_attr "op_type" "RR") | |
9824 | (set_attr "type" "branch") | |
9825 | (set_attr "atype" "agen")]) | |
9db1d521 | 9826 | |
ed9676cf AK |
9827 | (define_insn "*sibcall_brc" |
9828 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9829 | (match_operand 1 "const_int_operand" "n"))] | |
9830 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9831 | "j\t%0" | |
9832 | [(set_attr "op_type" "RI") | |
9833 | (set_attr "type" "branch")]) | |
9db1d521 | 9834 | |
ed9676cf AK |
9835 | (define_insn "*sibcall_brcl" |
9836 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9837 | (match_operand 1 "const_int_operand" "n"))] | |
9838 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9839 | "jg\t%0" | |
9840 | [(set_attr "op_type" "RIL") | |
9841 | (set_attr "type" "branch")]) | |
44b8152b | 9842 | |
ed9676cf AK |
9843 | ; |
9844 | ; sibcall_value patterns | |
9845 | ; | |
9e8327e3 | 9846 | |
ed9676cf AK |
9847 | (define_expand "sibcall_value" |
9848 | [(set (match_operand 0 "" "") | |
9849 | (call (match_operand 1 "" "") | |
9850 | (match_operand 2 "" "")))] | |
9851 | "" | |
9852 | { | |
9853 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9854 | DONE; |
10bbf137 | 9855 | }) |
9db1d521 | 9856 | |
ed9676cf AK |
9857 | (define_insn "*sibcall_value_br" |
9858 | [(set (match_operand 0 "" "") | |
ae156f85 | 9859 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9860 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9861 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9862 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
9863 | "br\t%%r1" | |
9864 | [(set_attr "op_type" "RR") | |
9865 | (set_attr "type" "branch") | |
9866 | (set_attr "atype" "agen")]) | |
9867 | ||
9868 | (define_insn "*sibcall_value_brc" | |
9869 | [(set (match_operand 0 "" "") | |
9870 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9871 | (match_operand 2 "const_int_operand" "n")))] | |
9872 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9873 | "j\t%1" | |
9874 | [(set_attr "op_type" "RI") | |
9875 | (set_attr "type" "branch")]) | |
9876 | ||
9877 | (define_insn "*sibcall_value_brcl" | |
9878 | [(set (match_operand 0 "" "") | |
9879 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9880 | (match_operand 2 "const_int_operand" "n")))] | |
9881 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9882 | "jg\t%1" | |
9883 | [(set_attr "op_type" "RIL") | |
9884 | (set_attr "type" "branch")]) | |
9885 | ||
9886 | ||
9887 | ; | |
9888 | ; call instruction pattern(s). | |
9889 | ; | |
9890 | ||
9891 | (define_expand "call" | |
9892 | [(call (match_operand 0 "" "") | |
9893 | (match_operand 1 "" "")) | |
9894 | (use (match_operand 2 "" ""))] | |
44b8152b | 9895 | "" |
ed9676cf | 9896 | { |
2f7e5a0d | 9897 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9898 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9899 | DONE; | |
9900 | }) | |
44b8152b | 9901 | |
9e8327e3 UW |
9902 | (define_insn "*bras" |
9903 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9904 | (match_operand 1 "const_int_operand" "n")) | |
9905 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9906 | "!SIBLING_CALL_P (insn) |
9907 | && TARGET_SMALL_EXEC | |
ed9676cf | 9908 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9909 | "bras\t%2,%0" |
9db1d521 | 9910 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9911 | (set_attr "type" "jsr") |
9912 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9913 | |
9e8327e3 UW |
9914 | (define_insn "*brasl" |
9915 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9916 | (match_operand 1 "const_int_operand" "n")) | |
9917 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9918 | "!SIBLING_CALL_P (insn) |
9919 | && TARGET_CPU_ZARCH | |
ed9676cf | 9920 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9921 | "brasl\t%2,%0" |
9922 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9923 | (set_attr "type" "jsr") |
9924 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9925 | |
9e8327e3 | 9926 | (define_insn "*basr" |
3e4be43f | 9927 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
9928 | (match_operand 1 "const_int_operand" "n")) |
9929 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 9930 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9931 | { |
9932 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9933 | return "basr\t%2,%0"; | |
9934 | else | |
9935 | return "bas\t%2,%a0"; | |
9936 | } | |
9937 | [(set (attr "op_type") | |
9938 | (if_then_else (match_operand 0 "register_operand" "") | |
9939 | (const_string "RR") (const_string "RX"))) | |
9940 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9941 | (set_attr "atype" "agen") |
9942 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
9943 | |
9944 | ; | |
9945 | ; call_value instruction pattern(s). | |
9946 | ; | |
9947 | ||
9948 | (define_expand "call_value" | |
44b8152b UW |
9949 | [(set (match_operand 0 "" "") |
9950 | (call (match_operand 1 "" "") | |
9951 | (match_operand 2 "" ""))) | |
9952 | (use (match_operand 3 "" ""))] | |
9db1d521 | 9953 | "" |
9db1d521 | 9954 | { |
2f7e5a0d | 9955 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 9956 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 9957 | DONE; |
10bbf137 | 9958 | }) |
9db1d521 | 9959 | |
9e8327e3 | 9960 | (define_insn "*bras_r" |
c19ec8f9 | 9961 | [(set (match_operand 0 "" "") |
9e8327e3 | 9962 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 9963 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 9964 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
9965 | "!SIBLING_CALL_P (insn) |
9966 | && TARGET_SMALL_EXEC | |
ed9676cf | 9967 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9968 | "bras\t%3,%1" |
9db1d521 | 9969 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9970 | (set_attr "type" "jsr") |
9971 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9972 | |
9e8327e3 | 9973 | (define_insn "*brasl_r" |
c19ec8f9 | 9974 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9975 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9976 | (match_operand 2 "const_int_operand" "n"))) | |
9977 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
9978 | "!SIBLING_CALL_P (insn) |
9979 | && TARGET_CPU_ZARCH | |
ed9676cf | 9980 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9981 | "brasl\t%3,%1" |
9982 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9983 | (set_attr "type" "jsr") |
9984 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9985 | |
9e8327e3 | 9986 | (define_insn "*basr_r" |
c19ec8f9 | 9987 | [(set (match_operand 0 "" "") |
3e4be43f | 9988 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
9989 | (match_operand 2 "const_int_operand" "n"))) |
9990 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 9991 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9992 | { |
9993 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9994 | return "basr\t%3,%1"; | |
9995 | else | |
9996 | return "bas\t%3,%a1"; | |
9997 | } | |
9998 | [(set (attr "op_type") | |
9999 | (if_then_else (match_operand 1 "register_operand" "") | |
10000 | (const_string "RR") (const_string "RX"))) | |
10001 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10002 | (set_attr "atype" "agen") |
10003 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10004 | |
fd3cd001 UW |
10005 | ;; |
10006 | ;;- Thread-local storage support. | |
10007 | ;; | |
10008 | ||
f959607b CLT |
10009 | (define_expand "get_thread_pointer<mode>" |
10010 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
10011 | "" | |
c5aa1d12 | 10012 | "") |
fd3cd001 | 10013 | |
f959607b CLT |
10014 | (define_expand "set_thread_pointer<mode>" |
10015 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
10016 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
10017 | "" | |
c5aa1d12 UW |
10018 | "") |
10019 | ||
10020 | (define_insn "*set_tp" | |
ae156f85 | 10021 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
10022 | "" |
10023 | "" | |
10024 | [(set_attr "type" "none") | |
10025 | (set_attr "length" "0")]) | |
c7453384 | 10026 | |
fd3cd001 UW |
10027 | (define_insn "*tls_load_64" |
10028 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 10029 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
10030 | (match_operand:DI 2 "" "")] |
10031 | UNSPEC_TLS_LOAD))] | |
10032 | "TARGET_64BIT" | |
d40c829f | 10033 | "lg\t%0,%1%J2" |
9381e3f1 WG |
10034 | [(set_attr "op_type" "RXE") |
10035 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
10036 | |
10037 | (define_insn "*tls_load_31" | |
d3632d41 UW |
10038 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10039 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
10040 | (match_operand:SI 2 "" "")] |
10041 | UNSPEC_TLS_LOAD))] | |
10042 | "!TARGET_64BIT" | |
d3632d41 | 10043 | "@ |
d40c829f UW |
10044 | l\t%0,%1%J2 |
10045 | ly\t%0,%1%J2" | |
9381e3f1 | 10046 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 10047 | (set_attr "type" "load") |
3e4be43f | 10048 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 10049 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 10050 | |
9e8327e3 | 10051 | (define_insn "*bras_tls" |
c19ec8f9 | 10052 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10053 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10054 | (match_operand 2 "const_int_operand" "n"))) | |
10055 | (clobber (match_operand 3 "register_operand" "=r")) | |
10056 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10057 | "!SIBLING_CALL_P (insn) |
10058 | && TARGET_SMALL_EXEC | |
ed9676cf | 10059 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10060 | "bras\t%3,%1%J4" |
fd3cd001 | 10061 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10062 | (set_attr "type" "jsr") |
10063 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10064 | |
9e8327e3 | 10065 | (define_insn "*brasl_tls" |
c19ec8f9 | 10066 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10067 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10068 | (match_operand 2 "const_int_operand" "n"))) | |
10069 | (clobber (match_operand 3 "register_operand" "=r")) | |
10070 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10071 | "!SIBLING_CALL_P (insn) |
10072 | && TARGET_CPU_ZARCH | |
ed9676cf | 10073 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10074 | "brasl\t%3,%1%J4" |
10075 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
10076 | (set_attr "type" "jsr") |
10077 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10078 | |
9e8327e3 | 10079 | (define_insn "*basr_tls" |
c19ec8f9 | 10080 | [(set (match_operand 0 "" "") |
3e4be43f | 10081 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10082 | (match_operand 2 "const_int_operand" "n"))) |
10083 | (clobber (match_operand 3 "register_operand" "=r")) | |
10084 | (use (match_operand 4 "" ""))] | |
ed9676cf | 10085 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10086 | { |
10087 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10088 | return "basr\t%3,%1%J4"; | |
10089 | else | |
10090 | return "bas\t%3,%a1%J4"; | |
10091 | } | |
10092 | [(set (attr "op_type") | |
10093 | (if_then_else (match_operand 1 "register_operand" "") | |
10094 | (const_string "RR") (const_string "RX"))) | |
10095 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10096 | (set_attr "atype" "agen") |
10097 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10098 | |
e0374221 AS |
10099 | ;; |
10100 | ;;- Atomic operations | |
10101 | ;; | |
10102 | ||
10103 | ; | |
78ce265b | 10104 | ; memory barrier patterns. |
e0374221 AS |
10105 | ; |
10106 | ||
78ce265b RH |
10107 | (define_expand "mem_thread_fence" |
10108 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
10109 | "" | |
10110 | { | |
10111 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
10112 | enough not to require barriers of any kind. */ | |
46b35980 | 10113 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
10114 | { |
10115 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
10116 | MEM_VOLATILE_P (mem) = 1; | |
10117 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
10118 | } | |
10119 | DONE; | |
e0374221 AS |
10120 | }) |
10121 | ||
78ce265b RH |
10122 | ; Although bcr is superscalar on Z10, this variant will never |
10123 | ; become part of an execution group. | |
a9cc3f58 AK |
10124 | ; With z196 we can make use of the fast-BCR-serialization facility. |
10125 | ; This allows for a slightly faster sync which is sufficient for our | |
10126 | ; purposes. | |
78ce265b | 10127 | (define_insn "mem_thread_fence_1" |
e0374221 | 10128 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 10129 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 10130 | "" |
a9cc3f58 AK |
10131 | { |
10132 | if (TARGET_Z196) | |
10133 | return "bcr\t14,0"; | |
10134 | else | |
10135 | return "bcr\t15,0"; | |
10136 | } | |
10137 | [(set_attr "op_type" "RR") | |
10138 | (set_attr "mnemonic" "bcr_flush") | |
10139 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10140 | |
78ce265b RH |
10141 | ; |
10142 | ; atomic load/store operations | |
10143 | ; | |
10144 | ||
10145 | ; Atomic loads need not examine the memory model at all. | |
10146 | (define_expand "atomic_load<mode>" | |
10147 | [(match_operand:DINT 0 "register_operand") ;; output | |
10148 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10149 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10150 | "" | |
10151 | { | |
75cc21e2 AK |
10152 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10153 | FAIL; | |
10154 | ||
78ce265b RH |
10155 | if (<MODE>mode == TImode) |
10156 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10157 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10158 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10159 | else | |
10160 | emit_move_insn (operands[0], operands[1]); | |
10161 | DONE; | |
10162 | }) | |
10163 | ||
10164 | ; Different from movdi_31 in that we want no splitters. | |
10165 | (define_insn "atomic_loaddi_1" | |
10166 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10167 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10168 | UNSPEC_MOVA))] | |
10169 | "!TARGET_ZARCH" | |
10170 | "@ | |
10171 | lm\t%0,%M0,%S1 | |
10172 | lmy\t%0,%M0,%S1 | |
10173 | ld\t%0,%1 | |
10174 | ldy\t%0,%1" | |
10175 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10176 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10177 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10178 | ||
10179 | (define_insn "atomic_loadti_1" | |
10180 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10181 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10182 | UNSPEC_MOVA))] |
10183 | "TARGET_ZARCH" | |
10184 | "lpq\t%0,%1" | |
10185 | [(set_attr "op_type" "RXY") | |
10186 | (set_attr "type" "other")]) | |
10187 | ||
10188 | ; Atomic stores must(?) enforce sequential consistency. | |
10189 | (define_expand "atomic_store<mode>" | |
10190 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10191 | (match_operand:DINT 1 "register_operand") ;; input | |
10192 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10193 | "" | |
10194 | { | |
46b35980 | 10195 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10196 | |
75cc21e2 AK |
10197 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10198 | FAIL; | |
10199 | ||
78ce265b RH |
10200 | if (<MODE>mode == TImode) |
10201 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10202 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10203 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10204 | else | |
10205 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10206 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10207 | emit_insn (gen_mem_thread_fence (operands[2])); |
10208 | DONE; | |
10209 | }) | |
10210 | ||
10211 | ; Different from movdi_31 in that we want no splitters. | |
10212 | (define_insn "atomic_storedi_1" | |
10213 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10214 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10215 | UNSPEC_MOVA))] | |
10216 | "!TARGET_ZARCH" | |
10217 | "@ | |
10218 | stm\t%1,%N1,%S0 | |
10219 | stmy\t%1,%N1,%S0 | |
10220 | std %1,%0 | |
10221 | stdy %1,%0" | |
10222 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10223 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10224 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10225 | ||
10226 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10227 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10228 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10229 | UNSPEC_MOVA))] | |
10230 | "TARGET_ZARCH" | |
10231 | "stpq\t%1,%0" | |
10232 | [(set_attr "op_type" "RXY") | |
10233 | (set_attr "type" "other")]) | |
e0374221 AS |
10234 | |
10235 | ; | |
10236 | ; compare and swap patterns. | |
10237 | ; | |
10238 | ||
78ce265b RH |
10239 | (define_expand "atomic_compare_and_swap<mode>" |
10240 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
03db9ab5 DV |
10241 | (match_operand:DINT 1 "nonimmediate_operand");; oldval output |
10242 | (match_operand:DINT 2 "s_operand") ;; memory | |
10243 | (match_operand:DINT 3 "general_operand") ;; expected intput | |
10244 | (match_operand:DINT 4 "general_operand") ;; newval intput | |
78ce265b RH |
10245 | (match_operand:SI 5 "const_int_operand") ;; is_weak |
10246 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10247 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10248 | "" | |
10249 | { | |
03db9ab5 DV |
10250 | if (GET_MODE_BITSIZE (<MODE>mode) >= 16 |
10251 | && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) | |
75cc21e2 AK |
10252 | FAIL; |
10253 | ||
03db9ab5 DV |
10254 | s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], |
10255 | operands[3], operands[4], INTVAL (operands[5])); | |
10256 | DONE;}) | |
3093f076 | 10257 | |
78ce265b RH |
10258 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10259 | [(parallel | |
10260 | [(set (match_operand:DGPR 0 "register_operand") | |
03db9ab5 | 10261 | (match_operand:DGPR 1 "s_operand")) |
78ce265b RH |
10262 | (set (match_dup 1) |
10263 | (unspec_volatile:DGPR | |
10264 | [(match_dup 1) | |
10265 | (match_operand:DGPR 2 "register_operand") | |
10266 | (match_operand:DGPR 3 "register_operand")] | |
10267 | UNSPECV_CAS)) | |
03db9ab5 DV |
10268 | (set (match_operand 4 "cc_reg_operand") |
10269 | (match_dup 5))])] | |
10270 | "GET_MODE (operands[4]) == CCZmode | |
10271 | || GET_MODE (operands[4]) == CCZ1mode" | |
10272 | { | |
10273 | operands[5] | |
10274 | = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); | |
10275 | }) | |
78ce265b RH |
10276 | |
10277 | ; cdsg, csg | |
10278 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10279 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
58814c76 | 10280 | (match_operand:TDI 1 "memory_operand" "+S")) |
8006eaa6 | 10281 | (set (match_dup 1) |
78ce265b | 10282 | (unspec_volatile:TDI |
8006eaa6 | 10283 | [(match_dup 1) |
78ce265b RH |
10284 | (match_operand:TDI 2 "register_operand" "0") |
10285 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 | 10286 | UNSPECV_CAS)) |
03db9ab5 DV |
10287 | (set (reg CC_REGNUM) |
10288 | (compare (match_dup 1) (match_dup 2)))] | |
10289 | "TARGET_ZARCH | |
10290 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10291 | "c<td>sg\t%0,%3,%S1" |
10292 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10293 | (set_attr "type" "sem")]) |
10294 | ||
78ce265b RH |
10295 | ; cds, cdsy |
10296 | (define_insn "*atomic_compare_and_swapdi_2" | |
10297 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
58814c76 | 10298 | (match_operand:DI 1 "memory_operand" "+Q,S")) |
e0374221 | 10299 | (set (match_dup 1) |
78ce265b RH |
10300 | (unspec_volatile:DI |
10301 | [(match_dup 1) | |
10302 | (match_operand:DI 2 "register_operand" "0,0") | |
10303 | (match_operand:DI 3 "register_operand" "r,r")] | |
10304 | UNSPECV_CAS)) | |
03db9ab5 DV |
10305 | (set (reg CC_REGNUM) |
10306 | (compare (match_dup 1) (match_dup 2)))] | |
10307 | "!TARGET_ZARCH | |
10308 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10309 | "@ |
10310 | cds\t%0,%3,%S1 | |
10311 | cdsy\t%0,%3,%S1" | |
10312 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10313 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10314 | (set_attr "type" "sem")]) |
10315 | ||
10316 | ; cs, csy | |
10317 | (define_insn "*atomic_compare_and_swapsi_3" | |
10318 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
58814c76 | 10319 | (match_operand:SI 1 "memory_operand" "+Q,S")) |
78ce265b RH |
10320 | (set (match_dup 1) |
10321 | (unspec_volatile:SI | |
e0374221 | 10322 | [(match_dup 1) |
78ce265b RH |
10323 | (match_operand:SI 2 "register_operand" "0,0") |
10324 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10325 | UNSPECV_CAS)) |
03db9ab5 DV |
10326 | (set (reg CC_REGNUM) |
10327 | (compare (match_dup 1) (match_dup 2)))] | |
10328 | "s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10329 | "@ |
10330 | cs\t%0,%3,%S1 | |
10331 | csy\t%0,%3,%S1" | |
10332 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10333 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10334 | (set_attr "type" "sem")]) |
10335 | ||
45d18331 AS |
10336 | ; |
10337 | ; Other atomic instruction patterns. | |
10338 | ; | |
10339 | ||
65b1d8ea AK |
10340 | ; z196 load and add, xor, or and and instructions |
10341 | ||
78ce265b RH |
10342 | (define_expand "atomic_fetch_<atomic><mode>" |
10343 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10344 | (ATOMIC_Z196:GPR | |
10345 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10346 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10347 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10348 | "TARGET_Z196" |
78ce265b | 10349 | { |
75cc21e2 AK |
10350 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10351 | FAIL; | |
10352 | ||
78ce265b RH |
10353 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10354 | (operands[0], operands[1], operands[2])); | |
10355 | DONE; | |
10356 | }) | |
65b1d8ea AK |
10357 | |
10358 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10359 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10360 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10361 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10362 | (set (match_dup 1) |
10363 | (unspec_volatile:GPR | |
10364 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10365 | (match_operand:GPR 2 "general_operand" "d"))] | |
10366 | UNSPECV_ATOMIC_OP)) | |
10367 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10368 | "TARGET_Z196" |
78ce265b RH |
10369 | "la<noxa><g>\t%0,%2,%1" |
10370 | [(set_attr "op_type" "RSY") | |
10371 | (set_attr "type" "sem")]) | |
65b1d8ea | 10372 | |
78ce265b RH |
10373 | ;; For SImode and larger, the optabs.c code will do just fine in |
10374 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10375 | ;; better by expanding our own loop. | |
65b1d8ea | 10376 | |
78ce265b RH |
10377 | (define_expand "atomic_<atomic><mode>" |
10378 | [(ATOMIC:HQI | |
10379 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10380 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10381 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10382 | "" |
78ce265b RH |
10383 | { |
10384 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10385 | operands[1], false); | |
10386 | DONE; | |
10387 | }) | |
45d18331 | 10388 | |
78ce265b RH |
10389 | (define_expand "atomic_fetch_<atomic><mode>" |
10390 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10391 | (ATOMIC:HQI | |
10392 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10393 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10394 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10395 | "" |
78ce265b RH |
10396 | { |
10397 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10398 | operands[2], false); | |
10399 | DONE; | |
10400 | }) | |
10401 | ||
10402 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10403 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10404 | (ATOMIC:HQI | |
10405 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10406 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10407 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10408 | "" | |
10409 | { | |
10410 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10411 | operands[2], true); | |
10412 | DONE; | |
10413 | }) | |
10414 | ||
03db9ab5 DV |
10415 | ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code |
10416 | ;; generated by the middleend is not good. | |
78ce265b | 10417 | (define_expand "atomic_exchange<mode>" |
03db9ab5 DV |
10418 | [(match_operand:DINT 0 "register_operand") ;; val out |
10419 | (match_operand:DINT 1 "s_operand") ;; memory | |
10420 | (match_operand:DINT 2 "general_operand") ;; val in | |
78ce265b | 10421 | (match_operand:SI 3 "const_int_operand")] ;; model |
45d18331 | 10422 | "" |
78ce265b | 10423 | { |
03db9ab5 DV |
10424 | if (<MODE>mode != QImode |
10425 | && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) | |
10426 | FAIL; | |
10427 | if (<MODE>mode == HImode || <MODE>mode == QImode) | |
10428 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], | |
10429 | false); | |
10430 | else if (<MODE>mode == SImode || TARGET_ZARCH) | |
10431 | s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); | |
10432 | else | |
10433 | FAIL; | |
78ce265b RH |
10434 | DONE; |
10435 | }) | |
45d18331 | 10436 | |
9db1d521 HP |
10437 | ;; |
10438 | ;;- Miscellaneous instructions. | |
10439 | ;; | |
10440 | ||
10441 | ; | |
10442 | ; allocate stack instruction pattern(s). | |
10443 | ; | |
10444 | ||
10445 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10446 | [(match_operand 0 "general_operand" "") |
10447 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10448 | "TARGET_BACKCHAIN" |
9db1d521 | 10449 | { |
ef44a6ff | 10450 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10451 | |
ef44a6ff UW |
10452 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10453 | anti_adjust_stack (operands[1]); | |
10454 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10455 | |
ef44a6ff UW |
10456 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10457 | DONE; | |
10bbf137 | 10458 | }) |
9db1d521 HP |
10459 | |
10460 | ||
10461 | ; | |
43ab026f | 10462 | ; setjmp instruction pattern. |
9db1d521 HP |
10463 | ; |
10464 | ||
9db1d521 | 10465 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10466 | [(match_operand 0 "" "")] |
f314b9b1 | 10467 | "flag_pic" |
9db1d521 | 10468 | { |
585539a1 | 10469 | emit_insn (s390_load_got ()); |
c41c1387 | 10470 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10471 | DONE; |
fd7643fb | 10472 | }) |
9db1d521 | 10473 | |
9db1d521 HP |
10474 | ;; These patterns say how to save and restore the stack pointer. We need not |
10475 | ;; save the stack pointer at function level since we are careful to | |
10476 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10477 | ;; when we restore the stack pointer. | |
10478 | ;; | |
10479 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10480 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10481 | ;; save area is a memory location. | |
10482 | ||
10483 | (define_expand "save_stack_function" | |
10484 | [(match_operand 0 "general_operand" "") | |
10485 | (match_operand 1 "general_operand" "")] | |
10486 | "" | |
10487 | "DONE;") | |
10488 | ||
10489 | (define_expand "restore_stack_function" | |
10490 | [(match_operand 0 "general_operand" "") | |
10491 | (match_operand 1 "general_operand" "")] | |
10492 | "" | |
10493 | "DONE;") | |
10494 | ||
10495 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10496 | [(match_operand 0 "register_operand" "") |
10497 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10498 | "TARGET_BACKCHAIN" |
9db1d521 | 10499 | { |
ef44a6ff UW |
10500 | rtx temp = gen_reg_rtx (Pmode); |
10501 | ||
10502 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10503 | emit_move_insn (operands[0], operands[1]); | |
10504 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10505 | ||
10506 | DONE; | |
10bbf137 | 10507 | }) |
9db1d521 HP |
10508 | |
10509 | (define_expand "save_stack_nonlocal" | |
10510 | [(match_operand 0 "memory_operand" "") | |
10511 | (match_operand 1 "register_operand" "")] | |
10512 | "" | |
9db1d521 | 10513 | { |
ef44a6ff UW |
10514 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10515 | ||
10516 | /* Copy the backchain to the first word, sp to the second and the | |
10517 | literal pool base to the third. */ | |
10518 | ||
9602b6a1 AK |
10519 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10520 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10521 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10522 | ||
b3d31392 | 10523 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10524 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10525 | |
9602b6a1 AK |
10526 | emit_move_insn (save_sp, operands[1]); |
10527 | emit_move_insn (save_bp, base); | |
9db1d521 | 10528 | |
9db1d521 | 10529 | DONE; |
10bbf137 | 10530 | }) |
9db1d521 HP |
10531 | |
10532 | (define_expand "restore_stack_nonlocal" | |
10533 | [(match_operand 0 "register_operand" "") | |
10534 | (match_operand 1 "memory_operand" "")] | |
10535 | "" | |
9db1d521 | 10536 | { |
490ceeb4 | 10537 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10538 | rtx temp = NULL_RTX; |
9db1d521 | 10539 | |
43ab026f | 10540 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10541 | literal pool base from the third. */ |
43ab026f | 10542 | |
9602b6a1 AK |
10543 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10544 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10545 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10546 | ||
b3d31392 | 10547 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10548 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10549 | |
9602b6a1 AK |
10550 | emit_move_insn (base, save_bp); |
10551 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10552 | |
10553 | if (temp) | |
10554 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10555 | ||
c41c1387 | 10556 | emit_use (base); |
9db1d521 | 10557 | DONE; |
10bbf137 | 10558 | }) |
9db1d521 | 10559 | |
7bcebb25 AK |
10560 | (define_expand "exception_receiver" |
10561 | [(const_int 0)] | |
10562 | "" | |
10563 | { | |
10564 | s390_set_has_landing_pad_p (true); | |
10565 | DONE; | |
10566 | }) | |
9db1d521 HP |
10567 | |
10568 | ; | |
10569 | ; nop instruction pattern(s). | |
10570 | ; | |
10571 | ||
10572 | (define_insn "nop" | |
10573 | [(const_int 0)] | |
10574 | "" | |
d40c829f | 10575 | "lr\t0,0" |
729e750f WG |
10576 | [(set_attr "op_type" "RR") |
10577 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10578 | |
d277db6b WG |
10579 | (define_insn "nop1" |
10580 | [(const_int 1)] | |
10581 | "" | |
10582 | "lr\t1,1" | |
10583 | [(set_attr "op_type" "RR")]) | |
10584 | ||
f8af0e30 DV |
10585 | ;;- Undeletable nops (used for hotpatching) |
10586 | ||
10587 | (define_insn "nop_2_byte" | |
10588 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10589 | "" | |
4bbc8970 | 10590 | "nopr\t%%r0" |
f8af0e30 DV |
10591 | [(set_attr "op_type" "RR")]) |
10592 | ||
10593 | (define_insn "nop_4_byte" | |
10594 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10595 | "" | |
10596 | "nop\t0" | |
10597 | [(set_attr "op_type" "RX")]) | |
10598 | ||
10599 | (define_insn "nop_6_byte" | |
10600 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
10601 | "TARGET_CPU_ZARCH" | |
10602 | "brcl\t0, 0" | |
10603 | [(set_attr "op_type" "RIL")]) | |
10604 | ||
9db1d521 HP |
10605 | |
10606 | ; | |
10607 | ; Special literal pool access instruction pattern(s). | |
10608 | ; | |
10609 | ||
416cf582 UW |
10610 | (define_insn "*pool_entry" |
10611 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10612 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10613 | "" |
9db1d521 | 10614 | { |
ef4bddc2 | 10615 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10616 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10617 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10618 | return ""; |
10619 | } | |
b628bd8e | 10620 | [(set (attr "length") |
416cf582 | 10621 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10622 | |
9bb86f41 UW |
10623 | (define_insn "pool_align" |
10624 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10625 | UNSPECV_POOL_ALIGN)] | |
10626 | "" | |
10627 | ".align\t%0" | |
b628bd8e | 10628 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10629 | |
9bb86f41 UW |
10630 | (define_insn "pool_section_start" |
10631 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10632 | "" | |
b929b470 MK |
10633 | { |
10634 | switch_to_section (targetm.asm_out.function_rodata_section | |
10635 | (current_function_decl)); | |
10636 | return ""; | |
10637 | } | |
b628bd8e | 10638 | [(set_attr "length" "0")]) |
b2ccb744 | 10639 | |
9bb86f41 UW |
10640 | (define_insn "pool_section_end" |
10641 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10642 | "" | |
b929b470 MK |
10643 | { |
10644 | switch_to_section (current_function_section ()); | |
10645 | return ""; | |
10646 | } | |
b628bd8e | 10647 | [(set_attr "length" "0")]) |
b2ccb744 | 10648 | |
5af2f3d3 | 10649 | (define_insn "main_base_31_small" |
9e8327e3 UW |
10650 | [(set (match_operand 0 "register_operand" "=a") |
10651 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10652 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10653 | "basr\t%0,0" |
10654 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
10655 | (set_attr "type" "la") |
10656 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10657 | |
10658 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
10659 | [(set (match_operand 0 "register_operand" "=a") |
10660 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 10661 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 10662 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 10663 | "bras\t%0,%2" |
65b1d8ea AK |
10664 | [(set_attr "op_type" "RI") |
10665 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10666 | |
10667 | (define_insn "main_base_64" | |
9e8327e3 UW |
10668 | [(set (match_operand 0 "register_operand" "=a") |
10669 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10670 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10671 | "larl\t%0,%1" |
10672 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10673 | (set_attr "type" "larl") |
729e750f | 10674 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
10675 | |
10676 | (define_insn "main_pool" | |
585539a1 UW |
10677 | [(set (match_operand 0 "register_operand" "=a") |
10678 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10679 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10680 | { |
10681 | gcc_unreachable (); | |
10682 | } | |
9381e3f1 | 10683 | [(set (attr "type") |
d7f99b2c | 10684 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 10685 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 10686 | |
aee4e0db | 10687 | (define_insn "reload_base_31" |
9e8327e3 UW |
10688 | [(set (match_operand 0 "register_operand" "=a") |
10689 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10690 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10691 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 10692 | [(set_attr "length" "6") |
65b1d8ea AK |
10693 | (set_attr "type" "la") |
10694 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 10695 | |
aee4e0db | 10696 | (define_insn "reload_base_64" |
9e8327e3 UW |
10697 | [(set (match_operand 0 "register_operand" "=a") |
10698 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10699 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10700 | "larl\t%0,%1" |
aee4e0db | 10701 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10702 | (set_attr "type" "larl") |
729e750f | 10703 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10704 | |
aee4e0db | 10705 | (define_insn "pool" |
fd7643fb | 10706 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10707 | "" |
8d933e31 AS |
10708 | { |
10709 | gcc_unreachable (); | |
10710 | } | |
b628bd8e | 10711 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10712 | |
4023fb28 UW |
10713 | ;; |
10714 | ;; Insns related to generating the function prologue and epilogue. | |
10715 | ;; | |
10716 | ||
10717 | ||
10718 | (define_expand "prologue" | |
10719 | [(use (const_int 0))] | |
10720 | "" | |
10bbf137 | 10721 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10722 | |
10723 | (define_expand "epilogue" | |
10724 | [(use (const_int 1))] | |
10725 | "" | |
ed9676cf AK |
10726 | "s390_emit_epilogue (false); DONE;") |
10727 | ||
10728 | (define_expand "sibcall_epilogue" | |
10729 | [(use (const_int 0))] | |
10730 | "" | |
10731 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10732 | |
177bc204 RS |
10733 | ;; A direct return instruction, without using an epilogue. |
10734 | (define_insn "<code>" | |
10735 | [(ANY_RETURN)] | |
10736 | "s390_can_use_<code>_insn ()" | |
10737 | "br\t%%r14" | |
10738 | [(set_attr "op_type" "RR") | |
10739 | (set_attr "type" "jsr") | |
10740 | (set_attr "atype" "agen")]) | |
10741 | ||
9e8327e3 | 10742 | (define_insn "*return" |
4023fb28 | 10743 | [(return) |
9e8327e3 UW |
10744 | (use (match_operand 0 "register_operand" "a"))] |
10745 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10746 | "br\t%0" |
4023fb28 | 10747 | [(set_attr "op_type" "RR") |
c7453384 | 10748 | (set_attr "type" "jsr") |
077dab3b | 10749 | (set_attr "atype" "agen")]) |
4023fb28 | 10750 | |
4023fb28 | 10751 | |
c7453384 | 10752 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 10753 | ;; pointer. This is used for compatibility. |
c7453384 EC |
10754 | |
10755 | (define_expand "ptr_extend" | |
10756 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10757 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 10758 | "TARGET_64BIT" |
c7453384 | 10759 | { |
c7453384 EC |
10760 | emit_insn (gen_anddi3 (operands[0], |
10761 | gen_lowpart (DImode, operands[1]), | |
10762 | GEN_INT (0x7fffffff))); | |
c7453384 | 10763 | DONE; |
10bbf137 | 10764 | }) |
4798630c D |
10765 | |
10766 | ;; Instruction definition to expand eh_return macro to support | |
10767 | ;; swapping in special linkage return addresses. | |
10768 | ||
10769 | (define_expand "eh_return" | |
10770 | [(use (match_operand 0 "register_operand" ""))] | |
10771 | "TARGET_TPF" | |
10772 | { | |
10773 | s390_emit_tpf_eh_return (operands[0]); | |
10774 | DONE; | |
10775 | }) | |
10776 | ||
7b8acc34 AK |
10777 | ; |
10778 | ; Stack Protector Patterns | |
10779 | ; | |
10780 | ||
10781 | (define_expand "stack_protect_set" | |
10782 | [(set (match_operand 0 "memory_operand" "") | |
10783 | (match_operand 1 "memory_operand" ""))] | |
10784 | "" | |
10785 | { | |
10786 | #ifdef TARGET_THREAD_SSP_OFFSET | |
10787 | operands[1] | |
10788 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10789 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10790 | #endif | |
10791 | if (TARGET_64BIT) | |
10792 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10793 | else | |
10794 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10795 | ||
10796 | DONE; | |
10797 | }) | |
10798 | ||
10799 | (define_insn "stack_protect_set<mode>" | |
10800 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
10801 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
10802 | "" | |
10803 | "mvc\t%O0(%G0,%R0),%S1" | |
10804 | [(set_attr "op_type" "SS")]) | |
10805 | ||
10806 | (define_expand "stack_protect_test" | |
10807 | [(set (reg:CC CC_REGNUM) | |
10808 | (compare (match_operand 0 "memory_operand" "") | |
10809 | (match_operand 1 "memory_operand" ""))) | |
10810 | (match_operand 2 "" "")] | |
10811 | "" | |
10812 | { | |
f90b7a5a | 10813 | rtx cc_reg, test; |
7b8acc34 AK |
10814 | #ifdef TARGET_THREAD_SSP_OFFSET |
10815 | operands[1] | |
10816 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10817 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10818 | #endif | |
7b8acc34 AK |
10819 | if (TARGET_64BIT) |
10820 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
10821 | else | |
10822 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
10823 | ||
f90b7a5a PB |
10824 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
10825 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
10826 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
10827 | DONE; |
10828 | }) | |
10829 | ||
10830 | (define_insn "stack_protect_test<mode>" | |
10831 | [(set (reg:CCZ CC_REGNUM) | |
10832 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
10833 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
10834 | "" | |
10835 | "clc\t%O0(%G0,%R0),%S1" | |
10836 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
10837 | |
10838 | ; This is used in s390_emit_prologue in order to prevent insns | |
10839 | ; adjusting the stack pointer to be moved over insns writing stack | |
10840 | ; slots using a copy of the stack pointer in a different register. | |
10841 | (define_insn "stack_tie" | |
10842 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
10843 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
10844 | "" | |
10845 | "" | |
10846 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
10847 | |
10848 | ||
82c6f58a AK |
10849 | (define_insn "stack_restore_from_fpr" |
10850 | [(set (reg:DI STACK_REGNUM) | |
10851 | (match_operand:DI 0 "register_operand" "f")) | |
10852 | (clobber (mem:BLK (scratch)))] | |
10853 | "TARGET_Z10" | |
10854 | "lgdr\t%%r15,%0" | |
10855 | [(set_attr "op_type" "RRE")]) | |
10856 | ||
963fc8d0 AK |
10857 | ; |
10858 | ; Data prefetch patterns | |
10859 | ; | |
10860 | ||
10861 | (define_insn "prefetch" | |
3e4be43f UW |
10862 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
10863 | (match_operand:SI 1 "const_int_operand" " n,n") | |
10864 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 10865 | "TARGET_Z10" |
963fc8d0 | 10866 | { |
4fe6dea8 AK |
10867 | switch (which_alternative) |
10868 | { | |
10869 | case 0: | |
4fe6dea8 | 10870 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 10871 | case 1: |
4fe6dea8 AK |
10872 | if (larl_operand (operands[0], Pmode)) |
10873 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 10874 | /* fallthrough */ |
4fe6dea8 AK |
10875 | default: |
10876 | ||
10877 | /* This might be reached for symbolic operands with an odd | |
10878 | addend. We simply omit the prefetch for such rare cases. */ | |
10879 | ||
10880 | return ""; | |
10881 | } | |
9381e3f1 | 10882 | } |
22d72dbc AK |
10883 | [(set_attr "type" "load,larl") |
10884 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
10885 | (set_attr "z10prop" "z10_super") |
10886 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
10887 | |
10888 | ||
10889 | ; | |
10890 | ; Byte swap instructions | |
10891 | ; | |
10892 | ||
511f5bb1 AK |
10893 | ; FIXME: There is also mvcin but we cannot use it since src and target |
10894 | ; may overlap. | |
50dc4eed | 10895 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 10896 | (define_insn "bswap<mode>2" |
3e4be43f UW |
10897 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
10898 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
677fbff4 | 10899 | "TARGET_CPU_ZARCH" |
07da44ab AK |
10900 | "@ |
10901 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
10902 | lrv<g>\t%0,%1 |
10903 | strv<g>\t%1,%0" | |
10904 | [(set_attr "type" "*,load,store") | |
10905 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 10906 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10907 | |
511f5bb1 | 10908 | (define_insn "bswaphi2" |
3e4be43f UW |
10909 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
10910 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
511f5bb1 | 10911 | "TARGET_CPU_ZARCH" |
6f5a59d1 AK |
10912 | "@ |
10913 | # | |
10914 | lrvh\t%0,%1 | |
10915 | strvh\t%1,%0" | |
10916 | [(set_attr "type" "*,load,store") | |
10917 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 10918 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10919 | |
6f5a59d1 AK |
10920 | (define_split |
10921 | [(set (match_operand:HI 0 "register_operand" "") | |
10922 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
10923 | "TARGET_CPU_ZARCH" | |
10924 | [(set (match_dup 2) (bswap:SI (match_dup 3))) | |
9060e335 | 10925 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 10926 | { |
9060e335 | 10927 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
10928 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
10929 | }) | |
10930 | ||
10931 | ||
65b1d8ea AK |
10932 | ; |
10933 | ; Population count instruction | |
10934 | ; | |
10935 | ||
10936 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
10937 | ; portions and stores the result in the corresponding bytes in op0. | |
10938 | (define_insn "*popcount<mode>" | |
10939 | [(set (match_operand:INT 0 "register_operand" "=d") | |
10940 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
10941 | (clobber (reg:CC CC_REGNUM))] | |
10942 | "TARGET_Z196" | |
10943 | "popcnt\t%0,%1" | |
10944 | [(set_attr "op_type" "RRE")]) | |
10945 | ||
10946 | (define_expand "popcountdi2" | |
10947 | [; popcnt op0, op1 | |
10948 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
10949 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
10950 | UNSPEC_POPCNT)) | |
10951 | (clobber (reg:CC CC_REGNUM))]) | |
10952 | ; sllg op2, op0, 32 | |
10953 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
10954 | ; agr op0, op2 | |
10955 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10956 | (clobber (reg:CC CC_REGNUM))]) | |
10957 | ; sllg op2, op0, 16 | |
17465c6e | 10958 | (set (match_dup 2) |
65b1d8ea AK |
10959 | (ashift:DI (match_dup 0) (const_int 16))) |
10960 | ; agr op0, op2 | |
10961 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10962 | (clobber (reg:CC CC_REGNUM))]) | |
10963 | ; sllg op2, op0, 8 | |
10964 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
10965 | ; agr op0, op2 | |
10966 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10967 | (clobber (reg:CC CC_REGNUM))]) | |
10968 | ; srlg op0, op0, 56 | |
10969 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
10970 | "TARGET_Z196 && TARGET_64BIT" | |
10971 | "operands[2] = gen_reg_rtx (DImode);") | |
10972 | ||
10973 | (define_expand "popcountsi2" | |
10974 | [; popcnt op0, op1 | |
10975 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
10976 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
10977 | UNSPEC_POPCNT)) | |
10978 | (clobber (reg:CC CC_REGNUM))]) | |
10979 | ; sllk op2, op0, 16 | |
17465c6e | 10980 | (set (match_dup 2) |
65b1d8ea AK |
10981 | (ashift:SI (match_dup 0) (const_int 16))) |
10982 | ; ar op0, op2 | |
10983 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10984 | (clobber (reg:CC CC_REGNUM))]) | |
10985 | ; sllk op2, op0, 8 | |
10986 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
10987 | ; ar op0, op2 | |
10988 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10989 | (clobber (reg:CC CC_REGNUM))]) | |
10990 | ; srl op0, op0, 24 | |
10991 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
10992 | "TARGET_Z196" | |
10993 | "operands[2] = gen_reg_rtx (SImode);") | |
10994 | ||
10995 | (define_expand "popcounthi2" | |
10996 | [; popcnt op0, op1 | |
10997 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
10998 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
10999 | UNSPEC_POPCNT)) | |
11000 | (clobber (reg:CC CC_REGNUM))]) | |
11001 | ; sllk op2, op0, 8 | |
17465c6e | 11002 | (set (match_dup 2) |
65b1d8ea AK |
11003 | (ashift:SI (match_dup 0) (const_int 8))) |
11004 | ; ar op0, op2 | |
11005 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11006 | (clobber (reg:CC CC_REGNUM))]) | |
11007 | ; srl op0, op0, 8 | |
11008 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
11009 | "TARGET_Z196" | |
11010 | "operands[2] = gen_reg_rtx (SImode);") | |
11011 | ||
11012 | (define_expand "popcountqi2" | |
11013 | [; popcnt op0, op1 | |
11014 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
11015 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
11016 | UNSPEC_POPCNT)) | |
11017 | (clobber (reg:CC CC_REGNUM))])] | |
11018 | "TARGET_Z196" | |
11019 | "") | |
11020 | ||
11021 | ;; | |
11022 | ;;- Copy sign instructions | |
11023 | ;; | |
11024 | ||
11025 | (define_insn "copysign<mode>3" | |
11026 | [(set (match_operand:FP 0 "register_operand" "=f") | |
11027 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
11028 | (match_operand:FP 2 "register_operand" "f")] | |
11029 | UNSPEC_COPYSIGN))] | |
11030 | "TARGET_Z196" | |
11031 | "cpsdr\t%0,%2,%1" | |
11032 | [(set_attr "op_type" "RRF") | |
11033 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
11034 | |
11035 | ||
11036 | ;; | |
11037 | ;;- Transactional execution instructions | |
11038 | ;; | |
11039 | ||
11040 | ; This splitter helps combine to make use of CC directly when | |
11041 | ; comparing the integer result of a tbegin builtin with a constant. | |
11042 | ; The unspec is already removed by canonicalize_comparison. So this | |
11043 | ; splitters only job is to turn the PARALLEL into separate insns | |
11044 | ; again. Unfortunately this only works with the very first cc/int | |
11045 | ; compare since combine is not able to deal with data flow across | |
11046 | ; basic block boundaries. | |
11047 | ||
11048 | ; It needs to be an insn pattern as well since combine does not apply | |
11049 | ; the splitter directly. Combine would only use it if it actually | |
11050 | ; would reduce the number of instructions. | |
11051 | (define_insn_and_split "*ccraw_to_int" | |
11052 | [(set (pc) | |
11053 | (if_then_else | |
11054 | (match_operator 0 "s390_eqne_operator" | |
11055 | [(reg:CCRAW CC_REGNUM) | |
11056 | (match_operand 1 "const_int_operand" "")]) | |
11057 | (label_ref (match_operand 2 "" "")) | |
11058 | (pc))) | |
11059 | (set (match_operand:SI 3 "register_operand" "=d") | |
11060 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
11061 | "" | |
11062 | "#" | |
11063 | "" | |
11064 | [(set (match_dup 3) | |
11065 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
11066 | (set (pc) | |
11067 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
11068 | (label_ref (match_dup 2)) | |
11069 | (pc)))] | |
11070 | "") | |
11071 | ||
11072 | ; Non-constrained transaction begin | |
11073 | ||
11074 | (define_expand "tbegin" | |
ee163e72 AK |
11075 | [(match_operand:SI 0 "register_operand" "") |
11076 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11077 | "TARGET_HTM" |
11078 | { | |
11079 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
11080 | DONE; | |
11081 | }) | |
11082 | ||
11083 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
11084 | [(match_operand:SI 0 "register_operand" "") |
11085 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11086 | "TARGET_HTM" |
11087 | { | |
11088 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
11089 | DONE; | |
11090 | }) | |
11091 | ||
11092 | (define_expand "tbegin_retry" | |
ee163e72 AK |
11093 | [(match_operand:SI 0 "register_operand" "") |
11094 | (match_operand:BLK 1 "memory_operand" "") | |
11095 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11096 | "TARGET_HTM" |
11097 | { | |
11098 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
11099 | DONE; | |
11100 | }) | |
11101 | ||
11102 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
11103 | [(match_operand:SI 0 "register_operand" "") |
11104 | (match_operand:BLK 1 "memory_operand" "") | |
11105 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11106 | "TARGET_HTM" |
11107 | { | |
11108 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
11109 | DONE; | |
11110 | }) | |
11111 | ||
c914ac45 AK |
11112 | ; Clobber VRs since they don't get restored |
11113 | (define_insn "tbegin_1_z13" | |
11114 | [(set (reg:CCRAW CC_REGNUM) | |
11115 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
11116 | UNSPECV_TBEGIN)) | |
11117 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11118 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
11119 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11120 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11121 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11122 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11123 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11124 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11125 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11126 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11127 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11128 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11129 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11130 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11131 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11132 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11133 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11134 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11135 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11136 | ; not supposed to be used for immediates (see genpreds.c). | |
11137 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11138 | "tbegin\t%1,%x0" | |
11139 | [(set_attr "op_type" "SIL")]) | |
11140 | ||
5a3fe9b6 AK |
11141 | (define_insn "tbegin_1" |
11142 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11143 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11144 | UNSPECV_TBEGIN)) |
2561451d AK |
11145 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11146 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11147 | (clobber (reg:DF 16)) |
11148 | (clobber (reg:DF 17)) | |
11149 | (clobber (reg:DF 18)) | |
11150 | (clobber (reg:DF 19)) | |
11151 | (clobber (reg:DF 20)) | |
11152 | (clobber (reg:DF 21)) | |
11153 | (clobber (reg:DF 22)) | |
11154 | (clobber (reg:DF 23)) | |
11155 | (clobber (reg:DF 24)) | |
11156 | (clobber (reg:DF 25)) | |
11157 | (clobber (reg:DF 26)) | |
11158 | (clobber (reg:DF 27)) | |
11159 | (clobber (reg:DF 28)) | |
11160 | (clobber (reg:DF 29)) | |
11161 | (clobber (reg:DF 30)) | |
11162 | (clobber (reg:DF 31))] | |
11163 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11164 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11165 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11166 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11167 | [(set_attr "op_type" "SIL")]) |
11168 | ||
11169 | ; Same as above but without the FPR clobbers | |
11170 | (define_insn "tbegin_nofloat_1" | |
11171 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11172 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11173 | UNSPECV_TBEGIN)) | |
11174 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11175 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11176 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11177 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11178 | [(set_attr "op_type" "SIL")]) |
11179 | ||
11180 | ||
11181 | ; Constrained transaction begin | |
11182 | ||
11183 | (define_expand "tbeginc" | |
11184 | [(set (reg:CCRAW CC_REGNUM) | |
11185 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11186 | UNSPECV_TBEGINC))] | |
11187 | "TARGET_HTM" | |
11188 | "") | |
11189 | ||
11190 | (define_insn "*tbeginc_1" | |
11191 | [(set (reg:CCRAW CC_REGNUM) | |
11192 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11193 | UNSPECV_TBEGINC))] | |
11194 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11195 | "tbeginc\t0,%x0" | |
11196 | [(set_attr "op_type" "SIL")]) | |
11197 | ||
11198 | ; Transaction end | |
11199 | ||
11200 | (define_expand "tend" | |
11201 | [(set (reg:CCRAW CC_REGNUM) | |
11202 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11203 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11204 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11205 | "TARGET_HTM" | |
11206 | "") | |
11207 | ||
11208 | (define_insn "*tend_1" | |
11209 | [(set (reg:CCRAW CC_REGNUM) | |
11210 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11211 | "TARGET_HTM" | |
11212 | "tend" | |
11213 | [(set_attr "op_type" "S")]) | |
11214 | ||
11215 | ; Transaction abort | |
11216 | ||
11217 | (define_expand "tabort" | |
eae48192 | 11218 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11219 | UNSPECV_TABORT)] |
11220 | "TARGET_HTM && operands != NULL" | |
11221 | { | |
11222 | if (CONST_INT_P (operands[0]) | |
11223 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11224 | { | |
f3981e7e | 11225 | error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC |
5a3fe9b6 AK |
11226 | ". Values in range 0 through 255 are reserved.", |
11227 | INTVAL (operands[0])); | |
11228 | FAIL; | |
11229 | } | |
11230 | }) | |
11231 | ||
11232 | (define_insn "*tabort_1" | |
eae48192 | 11233 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11234 | UNSPECV_TABORT)] |
11235 | "TARGET_HTM && operands != NULL" | |
11236 | "tabort\t%Y0" | |
11237 | [(set_attr "op_type" "S")]) | |
11238 | ||
eae48192 AK |
11239 | (define_insn "*tabort_1_plus" |
11240 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11241 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11242 | UNSPECV_TABORT)] | |
11243 | "TARGET_HTM && operands != NULL | |
11244 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11245 | "tabort\t%1(%0)" | |
11246 | [(set_attr "op_type" "S")]) | |
11247 | ||
5a3fe9b6 AK |
11248 | ; Transaction extract nesting depth |
11249 | ||
11250 | (define_insn "etnd" | |
11251 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11252 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11253 | "TARGET_HTM" | |
11254 | "etnd\t%0" | |
11255 | [(set_attr "op_type" "RRE")]) | |
11256 | ||
11257 | ; Non-transactional store | |
11258 | ||
11259 | (define_insn "ntstg" | |
3e4be43f | 11260 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11261 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11262 | UNSPECV_NTSTG))] | |
11263 | "TARGET_HTM" | |
11264 | "ntstg\t%1,%0" | |
11265 | [(set_attr "op_type" "RXY")]) | |
11266 | ||
11267 | ; Transaction perform processor assist | |
11268 | ||
11269 | (define_expand "tx_assist" | |
2561451d AK |
11270 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11271 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
11272 | (const_int 1)] |
11273 | UNSPECV_PPA)] | |
11274 | "TARGET_HTM" | |
2561451d | 11275 | "") |
5a3fe9b6 AK |
11276 | |
11277 | (define_insn "*ppa" | |
11278 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11279 | (match_operand:SI 1 "register_operand" "d") | |
11280 | (match_operand 2 "const_int_operand" "I")] | |
11281 | UNSPECV_PPA)] | |
11282 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 11283 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11284 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11285 | |
11286 | ||
11287 | ; Set and get floating point control register | |
11288 | ||
3af82a61 | 11289 | (define_insn "sfpc" |
004f64e1 AK |
11290 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11291 | UNSPECV_SFPC)] | |
11292 | "TARGET_HARD_FLOAT" | |
11293 | "sfpc\t%0") | |
11294 | ||
3af82a61 | 11295 | (define_insn "efpc" |
004f64e1 AK |
11296 | [(set (match_operand:SI 0 "register_operand" "=d") |
11297 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11298 | "TARGET_HARD_FLOAT" | |
11299 | "efpc\t%0") | |
3af82a61 AK |
11300 | |
11301 | ||
11302 | ; Load count to block boundary | |
11303 | ||
11304 | (define_insn "lcbb" | |
11305 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11306 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11307 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11308 | (clobber (reg:CC CC_REGNUM))] | |
11309 | "TARGET_Z13" | |
9a36359e | 11310 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11311 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11312 | |
11313 | ; Handle -fsplit-stack. | |
11314 | ||
11315 | (define_expand "split_stack_prologue" | |
11316 | [(const_int 0)] | |
11317 | "" | |
11318 | { | |
11319 | s390_expand_split_stack_prologue (); | |
11320 | DONE; | |
11321 | }) | |
11322 | ||
11323 | ;; If there are operand 0 bytes available on the stack, jump to | |
11324 | ;; operand 1. | |
11325 | ||
11326 | (define_expand "split_stack_space_check" | |
11327 | [(set (pc) (if_then_else | |
11328 | (ltu (minus (reg 15) | |
11329 | (match_operand 0 "register_operand")) | |
11330 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11331 | (label_ref (match_operand 1)) | |
11332 | (pc)))] | |
11333 | "" | |
11334 | { | |
11335 | /* Offset from thread pointer to __private_ss. */ | |
11336 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11337 | rtx tp = s390_get_thread_pointer (); | |
11338 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11339 | rtx reg = gen_reg_rtx (Pmode); | |
11340 | rtx cc; | |
11341 | if (TARGET_64BIT) | |
11342 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11343 | else | |
11344 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11345 | cc = s390_emit_compare (GT, reg, guard); | |
11346 | s390_emit_jump (operands[1], cc); | |
11347 | ||
11348 | DONE; | |
11349 | }) | |
11350 | ||
11351 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
11352 | ;; parameter block label, label to be called by __morestack, frame size, | |
11353 | ;; stack parameter size. | |
11354 | ||
11355 | (define_insn "split_stack_data" | |
11356 | [(unspec_volatile [(match_operand 0 "" "X") | |
11357 | (match_operand 1 "" "X") | |
11358 | (match_operand 2 "const_int_operand" "X") | |
11359 | (match_operand 3 "const_int_operand" "X")] | |
11360 | UNSPECV_SPLIT_STACK_DATA)] | |
11361 | "TARGET_CPU_ZARCH" | |
11362 | { | |
11363 | switch_to_section (targetm.asm_out.function_rodata_section | |
11364 | (current_function_decl)); | |
11365 | ||
11366 | if (TARGET_64BIT) | |
11367 | output_asm_insn (".align\t8", operands); | |
11368 | else | |
11369 | output_asm_insn (".align\t4", operands); | |
11370 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11371 | CODE_LABEL_NUMBER (operands[0])); | |
11372 | if (TARGET_64BIT) | |
11373 | { | |
11374 | output_asm_insn (".quad\t%2", operands); | |
11375 | output_asm_insn (".quad\t%3", operands); | |
11376 | output_asm_insn (".quad\t%1-%0", operands); | |
11377 | } | |
11378 | else | |
11379 | { | |
11380 | output_asm_insn (".long\t%2", operands); | |
11381 | output_asm_insn (".long\t%3", operands); | |
11382 | output_asm_insn (".long\t%1-%0", operands); | |
11383 | } | |
11384 | ||
11385 | switch_to_section (current_function_section ()); | |
11386 | return ""; | |
11387 | } | |
11388 | [(set_attr "length" "0")]) | |
11389 | ||
11390 | ||
11391 | ;; A jg with minimal fuss for use in split stack prologue. | |
11392 | ||
11393 | (define_expand "split_stack_call" | |
11394 | [(match_operand 0 "bras_sym_operand" "X") | |
11395 | (match_operand 1 "" "")] | |
11396 | "TARGET_CPU_ZARCH" | |
11397 | { | |
11398 | if (TARGET_64BIT) | |
11399 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11400 | else | |
11401 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11402 | DONE; | |
11403 | }) | |
11404 | ||
11405 | (define_insn "split_stack_call_<mode>" | |
11406 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11407 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11408 | (reg:P 1)] | |
11409 | UNSPECV_SPLIT_STACK_CALL))] | |
11410 | "TARGET_CPU_ZARCH" | |
11411 | "jg\t%0" | |
11412 | [(set_attr "op_type" "RIL") | |
11413 | (set_attr "type" "branch")]) | |
11414 | ||
11415 | ;; Also a conditional one. | |
11416 | ||
11417 | (define_expand "split_stack_cond_call" | |
11418 | [(match_operand 0 "bras_sym_operand" "X") | |
11419 | (match_operand 1 "" "") | |
11420 | (match_operand 2 "" "")] | |
11421 | "TARGET_CPU_ZARCH" | |
11422 | { | |
11423 | if (TARGET_64BIT) | |
11424 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11425 | else | |
11426 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11427 | DONE; | |
11428 | }) | |
11429 | ||
11430 | (define_insn "split_stack_cond_call_<mode>" | |
11431 | [(set (pc) | |
11432 | (if_then_else | |
11433 | (match_operand 1 "" "") | |
11434 | (label_ref (match_operand 2 "" "")) | |
11435 | (pc))) | |
11436 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11437 | (reg:P 1)] | |
11438 | UNSPECV_SPLIT_STACK_CALL))] | |
11439 | "TARGET_CPU_ZARCH" | |
11440 | "jg%C1\t%0" | |
11441 | [(set_attr "op_type" "RIL") | |
11442 | (set_attr "type" "branch")]) | |
539405d5 AK |
11443 | |
11444 | (define_insn "osc_break" | |
11445 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
11446 | "" | |
11447 | "bcr\t7,%%r0" | |
11448 | [(set_attr "op_type" "RR")]) |