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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
9c3c3dcc | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a UW |
20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
21 | ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | ;; 02111-1307, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
9dc62c00 | 28 | ;; c -- Condition code register 33. |
9db1d521 HP |
29 | ;; d -- Any register from 0 to 15. |
30 | ;; I -- An 8-bit constant (0..255). | |
31 | ;; J -- A 12-bit constant (0..4095). | |
32 | ;; K -- A 16-bit constant (-32768..32767). | |
2f7e5a0d | 33 | ;; L -- Value appropriate as displacement. |
f19a9af7 AK |
34 | ;; (0..4095) for short displacement |
35 | ;; (-524288..524287) for long displacement | |
36 | ;; M -- Constant integer with a value of 0x7fffffff. | |
37 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
0dfa6c5e UW |
38 | ;; 0..9,x: number of the part counting from most to least significant |
39 | ;; H,Q: mode of the part | |
40 | ;; D,S,H: mode of the containing operand | |
41 | ;; 0,F: value of the other parts (F - all bits set) | |
2f7e5a0d | 42 | ;; |
f19a9af7 | 43 | ;; The constraint matches if the specified part of a constant |
0dfa6c5e UW |
44 | ;; has a value different from its other parts. If the letter x |
45 | ;; is specified instead of a part number, the constraint matches | |
46 | ;; if there is any single part with non-default value. | |
f19a9af7 AK |
47 | ;; Q -- Memory reference without index register and with short displacement. |
48 | ;; R -- Memory reference with index register and short displacement. | |
49 | ;; S -- Memory reference without index register but with long displacement. | |
50 | ;; T -- Memory reference with index register and long displacement. | |
0dfa6c5e UW |
51 | ;; A -- Multiple letter constraint followed by Q, R, S, or T: |
52 | ;; Offsettable memory reference of type specified by second letter. | |
e221ef54 UW |
53 | ;; B -- Multiple letter constraint followed by Q, R, S, or T: |
54 | ;; Memory reference of the type specified by second letter that | |
55 | ;; does *not* refer to a literal pool entry. | |
f19a9af7 AK |
56 | ;; U -- Pointer with short displacement. |
57 | ;; W -- Pointer with long displacement. | |
58 | ;; Y -- Shift count operand. | |
9db1d521 HP |
59 | ;; |
60 | ;; Special formats used for outputting 390 instructions. | |
61 | ;; | |
f19a9af7 AK |
62 | ;; %C: print opcode suffix for branch condition. |
63 | ;; %D: print opcode suffix for inverse branch condition. | |
64 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
65 | ;; %O: print only the displacement of a memory reference. | |
66 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 67 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
68 | ;; %N: print the second word of a DImode operand. |
69 | ;; %M: print the second word of a TImode operand. | |
70 | ||
71 | ;; %b: print integer X as if it's an unsigned byte. | |
72 | ;; %x: print integer X as if it's an unsigned word. | |
73 | ;; %h: print integer X as if it's a signed word. | |
74 | ;; %i: print the first nonzero HImode part of X | |
75 | ;; %j: print the first HImode part unequal to 0xffff of X | |
76 | ||
9db1d521 HP |
77 | ;; |
78 | ;; We have a special constraint for pattern matching. | |
79 | ;; | |
80 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
81 | ;; | |
9db1d521 | 82 | |
fd3cd001 UW |
83 | ;; |
84 | ;; UNSPEC usage | |
85 | ;; | |
86 | ||
87 | (define_constants | |
10bbf137 UW |
88 | [; Miscellaneous |
89 | (UNSPEC_ROUND 1) | |
5b022de5 | 90 | (UNSPEC_CMPINT 2) |
10bbf137 UW |
91 | (UNSPEC_SETHIGH 10) |
92 | ||
93 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
94 | (UNSPEC_LTREL_OFFSET 100) |
95 | (UNSPEC_LTREL_BASE 101) | |
96 | (UNSPEC_GOTENT 110) | |
97 | (UNSPEC_GOT 111) | |
98 | (UNSPEC_GOTOFF 112) | |
99 | (UNSPEC_PLT 113) | |
100 | (UNSPEC_PLTOFF 114) | |
101 | ||
102 | ; Literal pool | |
103 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 104 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 105 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
106 | (UNSPEC_INSN 213) |
107 | (UNSPEC_EXECUTE 214) | |
fd7643fb UW |
108 | |
109 | ; TLS relocation specifiers | |
fd3cd001 UW |
110 | (UNSPEC_TLSGD 500) |
111 | (UNSPEC_TLSLDM 501) | |
112 | (UNSPEC_NTPOFF 502) | |
113 | (UNSPEC_DTPOFF 503) | |
114 | (UNSPEC_GOTNTPOFF 504) | |
115 | (UNSPEC_INDNTPOFF 505) | |
116 | ||
117 | ; TLS support | |
fd3cd001 UW |
118 | (UNSPEC_TLSLDM_NTPOFF 511) |
119 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
120 | |
121 | ; String Functions | |
122 | (UNSPEC_SRST 600) | |
fd3cd001 UW |
123 | ]) |
124 | ||
125 | ;; | |
126 | ;; UNSPEC_VOLATILE usage | |
127 | ;; | |
128 | ||
129 | (define_constants | |
10bbf137 UW |
130 | [; Blockage |
131 | (UNSPECV_BLOCKAGE 0) | |
132 | ||
2f7e5a0d EC |
133 | ; TPF Support |
134 | (UNSPECV_TPF_PROLOGUE 20) | |
135 | (UNSPECV_TPF_EPILOGUE 21) | |
136 | ||
10bbf137 | 137 | ; Literal pool |
fd7643fb | 138 | (UNSPECV_POOL 200) |
9bb86f41 UW |
139 | (UNSPECV_POOL_SECTION 201) |
140 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 141 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
142 | (UNSPECV_MAIN_POOL 300) |
143 | ||
144 | ; TLS support | |
fd3cd001 UW |
145 | (UNSPECV_SET_TP 500) |
146 | ]) | |
147 | ||
148 | ||
29a74354 UW |
149 | ;; Instruction operand type as used in the Principles of Operation. |
150 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 151 | |
29a74354 UW |
152 | (define_attr "op_type" |
153 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" | |
b628bd8e | 154 | (const_string "NN")) |
9db1d521 | 155 | |
29a74354 | 156 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 157 | |
077dab3b | 158 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
ed0e512a AK |
159 | cs,vs,store,idiv, |
160 | imulhi,imulsi,imuldi, | |
077dab3b HP |
161 | branch,jsr,fsimpd,fsimps, |
162 | floadd,floads,fstored, fstores, | |
163 | fmuld,fmuls,fdivd,fdivs, | |
164 | ftoi,itof,fsqrtd,fsqrts, | |
a036c6f7 | 165 | other" |
29a74354 UW |
166 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
167 | (eq_attr "op_type" "SS") (const_string "cs")] | |
168 | (const_string "integer"))) | |
9db1d521 | 169 | |
29a74354 UW |
170 | ;; Another attribute used for scheduling purposes: |
171 | ;; agen: Instruction uses the address generation unit | |
172 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
173 | |
174 | (define_attr "atype" "agen,reg" | |
b628bd8e | 175 | (cond [(eq_attr "op_type" "E") (const_string "reg") |
077dab3b HP |
176 | (eq_attr "op_type" "RR") (const_string "reg") |
177 | (eq_attr "op_type" "RX") (const_string "agen") | |
178 | (eq_attr "op_type" "RI") (const_string "reg") | |
179 | (eq_attr "op_type" "RRE") (const_string "reg") | |
180 | (eq_attr "op_type" "RS") (const_string "agen") | |
181 | (eq_attr "op_type" "RSI") (const_string "agen") | |
182 | (eq_attr "op_type" "S") (const_string "agen") | |
183 | (eq_attr "op_type" "SI") (const_string "agen") | |
184 | (eq_attr "op_type" "SS") (const_string "agen") | |
185 | (eq_attr "op_type" "SSE") (const_string "agen") | |
186 | (eq_attr "op_type" "RXE") (const_string "agen") | |
187 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
188 | (eq_attr "op_type" "RIL") (const_string "agen") |
189 | (eq_attr "op_type" "RXY") (const_string "agen") | |
190 | (eq_attr "op_type" "RSY") (const_string "agen") | |
191 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
b628bd8e | 192 | (const_string "agen"))) |
9db1d521 | 193 | |
9db1d521 HP |
194 | ;; Length in bytes. |
195 | ||
196 | (define_attr "length" "" | |
b628bd8e | 197 | (cond [(eq_attr "op_type" "E") (const_int 2) |
9db1d521 HP |
198 | (eq_attr "op_type" "RR") (const_int 2) |
199 | (eq_attr "op_type" "RX") (const_int 4) | |
200 | (eq_attr "op_type" "RI") (const_int 4) | |
201 | (eq_attr "op_type" "RRE") (const_int 4) | |
202 | (eq_attr "op_type" "RS") (const_int 4) | |
203 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
204 | (eq_attr "op_type" "S") (const_int 4) |
205 | (eq_attr "op_type" "SI") (const_int 4) | |
206 | (eq_attr "op_type" "SS") (const_int 6) | |
207 | (eq_attr "op_type" "SSE") (const_int 6) | |
208 | (eq_attr "op_type" "RXE") (const_int 6) | |
209 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
210 | (eq_attr "op_type" "RIL") (const_int 6) |
211 | (eq_attr "op_type" "RXY") (const_int 6) | |
212 | (eq_attr "op_type" "RSY") (const_int 6) | |
213 | (eq_attr "op_type" "SIY") (const_int 6)] | |
b628bd8e | 214 | (const_int 6))) |
9db1d521 | 215 | |
29a74354 UW |
216 | |
217 | ;; Processor type. This attribute must exactly match the processor_type | |
218 | ;; enumeration in s390.h. The current machine description does not | |
219 | ;; distinguish between g5 and g6, but there are differences between the two | |
220 | ;; CPUs could in theory be modeled. | |
221 | ||
222 | (define_attr "cpu" "g5,g6,z900,z990" | |
223 | (const (symbol_ref "s390_tune"))) | |
224 | ||
225 | ;; Pipeline description for z900. For lack of anything better, | |
226 | ;; this description is also used for the g5 and g6. | |
227 | (include "2064.md") | |
228 | ||
229 | ;; Pipeline description for z990. | |
230 | (include "2084.md") | |
231 | ||
0bfc3f69 AS |
232 | ;; Predicates |
233 | (include "predicates.md") | |
234 | ||
f52c81dd AS |
235 | |
236 | ;; Macros | |
237 | ||
9a91a21f | 238 | ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d AS |
239 | ;; from the same template. |
240 | (define_mode_macro GPR [(DI "TARGET_64BIT") SI]) | |
9a91a21f | 241 | (define_mode_macro DSI [DI SI]) |
9db2f16d AS |
242 | |
243 | ;; This mode macro allows :P to be used for patterns that operate on | |
244 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
245 | (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) | |
246 | ||
f52c81dd AS |
247 | ;; This mode macro allows the QI and HI patterns to be defined from |
248 | ;; the same template. | |
249 | (define_mode_macro HQI [HI QI]) | |
250 | ||
342cf42b AS |
251 | ;; This mode macro allows the integer patterns to be defined from the |
252 | ;; same template. | |
253 | (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI]) | |
254 | ||
fa77b251 AS |
255 | ;; This macro allows to unify all 'bCOND' expander patterns. |
256 | (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered | |
257 | ordered uneq unlt ungt unle unge ltgt]) | |
258 | ||
9a91a21f AS |
259 | ;; This macro allows to unify all 'sCOND' patterns. |
260 | (define_code_macro SCOND [ltu gtu leu geu]) | |
261 | ||
262 | ||
263 | ;; This attribute handles differences in the instruction 'type' and will result | |
264 | ;; in "RRE" for DImode and "RR" for SImode. | |
265 | (define_mode_attr E [(DI "E") (SI "")]) | |
266 | ||
267 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode | |
268 | ;; and "lcr" in SImode. | |
269 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd AS |
270 | |
271 | ;; ICM mask required to load MODE value into the highest subreg | |
272 | ;; of a SImode register. | |
273 | (define_mode_attr icm_hi [(HI "12") (QI "8")]) | |
274 | ||
275 | ;; ICM mask required to load MODE value into the lowest subreg | |
276 | ;; of a SImode register. | |
277 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
278 | ||
f6ee577c AS |
279 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
280 | ;; HImode and "llgc" in QImode. | |
281 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
282 | ||
f52c81dd AS |
283 | ;; Maximum unsigned integer that fits in MODE. |
284 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
285 | ||
286 | ||
9db1d521 HP |
287 | ;; |
288 | ;;- Compare instructions. | |
289 | ;; | |
290 | ||
9db2f16d | 291 | (define_expand "cmp<mode>" |
9db1d521 | 292 | [(set (reg:CC 33) |
9db2f16d AS |
293 | (compare:CC (match_operand:GPR 0 "register_operand" "") |
294 | (match_operand:GPR 1 "general_operand" "")))] | |
9db1d521 | 295 | "" |
9db1d521 HP |
296 | { |
297 | s390_compare_op0 = operands[0]; | |
298 | s390_compare_op1 = operands[1]; | |
299 | DONE; | |
10bbf137 | 300 | }) |
9db1d521 | 301 | |
9db1d521 HP |
302 | (define_expand "cmpdf" |
303 | [(set (reg:CC 33) | |
304 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
305 | (match_operand:DF 1 "general_operand" "")))] | |
306 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
307 | { |
308 | s390_compare_op0 = operands[0]; | |
309 | s390_compare_op1 = operands[1]; | |
310 | DONE; | |
10bbf137 | 311 | }) |
9db1d521 HP |
312 | |
313 | (define_expand "cmpsf" | |
314 | [(set (reg:CC 33) | |
315 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
316 | (match_operand:SF 1 "general_operand" "")))] | |
317 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
318 | { |
319 | s390_compare_op0 = operands[0]; | |
320 | s390_compare_op1 = operands[1]; | |
321 | DONE; | |
10bbf137 | 322 | }) |
9db1d521 HP |
323 | |
324 | ||
07893d4f | 325 | ; Test-under-Mask instructions |
9db1d521 | 326 | |
07893d4f | 327 | (define_insn "*tmqi_mem" |
9db1d521 | 328 | [(set (reg 33) |
68f9c5e2 UW |
329 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
330 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
331 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
07893d4f | 332 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" |
d3632d41 | 333 | "@ |
fc0ea003 UW |
334 | tm\t%S0,%b1 |
335 | tmy\t%S0,%b1" | |
d3632d41 | 336 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 337 | |
05b9aaaa UW |
338 | (define_insn "*tmdi_reg" |
339 | [(set (reg 33) | |
f19a9af7 | 340 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 341 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
342 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
343 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa UW |
344 | "TARGET_64BIT |
345 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
f19a9af7 AK |
346 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
347 | "@ | |
348 | tmhh\t%0,%i1 | |
349 | tmhl\t%0,%i1 | |
350 | tmlh\t%0,%i1 | |
351 | tmll\t%0,%i1" | |
05b9aaaa UW |
352 | [(set_attr "op_type" "RI")]) |
353 | ||
354 | (define_insn "*tmsi_reg" | |
355 | [(set (reg 33) | |
f19a9af7 AK |
356 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
357 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
358 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
05b9aaaa | 359 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) |
f19a9af7 AK |
360 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
361 | "@ | |
362 | tmh\t%0,%i1 | |
363 | tml\t%0,%i1" | |
05b9aaaa UW |
364 | [(set_attr "op_type" "RI")]) |
365 | ||
f52c81dd | 366 | (define_insn "*tm<mode>_full" |
9db1d521 | 367 | [(set (reg 33) |
f52c81dd AS |
368 | (compare (match_operand:HQI 0 "register_operand" "d") |
369 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
a556fd39 | 370 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
f52c81dd | 371 | "tml\t%0,<max_uint>" |
07893d4f | 372 | [(set_attr "op_type" "RI")]) |
9db1d521 | 373 | |
07893d4f UW |
374 | |
375 | ; Load-and-Test instructions | |
376 | ||
377 | (define_insn "*tstdi_sign" | |
9db1d521 | 378 | [(set (reg 33) |
07893d4f UW |
379 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
380 | (const_int 32)) (const_int 32)) | |
381 | (match_operand:DI 1 "const0_operand" ""))) | |
382 | (set (match_operand:DI 2 "register_operand" "=d") | |
383 | (sign_extend:DI (match_dup 0)))] | |
384 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 385 | "ltgfr\t%2,%0" |
07893d4f UW |
386 | [(set_attr "op_type" "RRE")]) |
387 | ||
388 | (define_insn "*tstdi" | |
9db1d521 | 389 | [(set (reg 33) |
07893d4f UW |
390 | (compare (match_operand:DI 0 "register_operand" "d") |
391 | (match_operand:DI 1 "const0_operand" ""))) | |
392 | (set (match_operand:DI 2 "register_operand" "=d") | |
393 | (match_dup 0))] | |
394 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 395 | "ltgr\t%2,%0" |
07893d4f | 396 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 397 | |
07893d4f | 398 | (define_insn "*tstdi_cconly" |
9db1d521 | 399 | [(set (reg 33) |
07893d4f UW |
400 | (compare (match_operand:DI 0 "register_operand" "d") |
401 | (match_operand:DI 1 "const0_operand" "")))] | |
402 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 403 | "ltgr\t%0,%0" |
07893d4f | 404 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 405 | |
07893d4f UW |
406 | (define_insn "*tstdi_cconly_31" |
407 | [(set (reg 33) | |
408 | (compare (match_operand:DI 0 "register_operand" "d") | |
409 | (match_operand:DI 1 "const0_operand" "")))] | |
410 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 411 | "srda\t%0,0" |
077dab3b HP |
412 | [(set_attr "op_type" "RS") |
413 | (set_attr "atype" "reg")]) | |
414 | ||
4023fb28 | 415 | |
07893d4f UW |
416 | (define_insn "*tstsi" |
417 | [(set (reg 33) | |
d3632d41 | 418 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 419 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 420 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f UW |
421 | (match_dup 0))] |
422 | "s390_match_ccmode(insn, CCSmode)" | |
423 | "@ | |
d40c829f | 424 | ltr\t%2,%0 |
fc0ea003 UW |
425 | icm\t%2,15,%S0 |
426 | icmy\t%2,15,%S0" | |
d3632d41 | 427 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 428 | |
07893d4f | 429 | (define_insn "*tstsi_cconly" |
4023fb28 | 430 | [(set (reg 33) |
d3632d41 | 431 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 432 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 433 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
434 | "s390_match_ccmode(insn, CCSmode)" |
435 | "@ | |
d40c829f | 436 | ltr\t%0,%0 |
fc0ea003 UW |
437 | icm\t%2,15,%S0 |
438 | icmy\t%2,15,%S0" | |
d3632d41 | 439 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 440 | |
07893d4f UW |
441 | (define_insn "*tstsi_cconly2" |
442 | [(set (reg 33) | |
443 | (compare (match_operand:SI 0 "register_operand" "d") | |
444 | (match_operand:SI 1 "const0_operand" "")))] | |
445 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 446 | "ltr\t%0,%0" |
07893d4f | 447 | [(set_attr "op_type" "RR")]) |
4023fb28 | 448 | |
f52c81dd | 449 | (define_insn "*tst<mode>CCT" |
3af97654 | 450 | [(set (reg 33) |
f52c81dd AS |
451 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
452 | (match_operand:HQI 1 "const0_operand" ""))) | |
453 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
454 | (match_dup 0))] |
455 | "s390_match_ccmode(insn, CCTmode)" | |
456 | "@ | |
f52c81dd AS |
457 | icm\t%2,<icm_lo>,%S0 |
458 | icmy\t%2,<icm_lo>,%S0 | |
459 | tml\t%0,<max_uint>" | |
d3632d41 | 460 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
461 | |
462 | (define_insn "*tsthiCCT_cconly" | |
463 | [(set (reg 33) | |
d3632d41 | 464 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 465 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 466 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
467 | "s390_match_ccmode(insn, CCTmode)" |
468 | "@ | |
fc0ea003 UW |
469 | icm\t%2,3,%S0 |
470 | icmy\t%2,3,%S0 | |
d40c829f | 471 | tml\t%0,65535" |
d3632d41 | 472 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 473 | |
3af97654 UW |
474 | (define_insn "*tstqiCCT_cconly" |
475 | [(set (reg 33) | |
d3632d41 | 476 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
477 | (match_operand:QI 1 "const0_operand" "")))] |
478 | "s390_match_ccmode(insn, CCTmode)" | |
479 | "@ | |
fc0ea003 UW |
480 | cli\t%S0,0 |
481 | cliy\t%S0,0 | |
d40c829f | 482 | tml\t%0,255" |
d3632d41 | 483 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 484 | |
f52c81dd | 485 | (define_insn "*tst<mode>" |
9db1d521 | 486 | [(set (reg 33) |
f52c81dd AS |
487 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
488 | (match_operand:HQI 1 "const0_operand" ""))) | |
489 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
490 | (match_dup 0))] |
491 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 492 | "@ |
f52c81dd AS |
493 | icm\t%2,<icm_lo>,%S0 |
494 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 | 495 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 496 | |
f52c81dd | 497 | (define_insn "*tst<mode>_cconly" |
9db1d521 | 498 | [(set (reg 33) |
f52c81dd AS |
499 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
500 | (match_operand:HQI 1 "const0_operand" ""))) | |
501 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 502 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 503 | "@ |
f52c81dd AS |
504 | icm\t%2,<icm_lo>,%S0 |
505 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 UW |
506 | [(set_attr "op_type" "RS,RSY")]) |
507 | ||
9db1d521 | 508 | |
575f7c2b UW |
509 | ; Compare (equality) instructions |
510 | ||
511 | (define_insn "*cmpdi_cct" | |
512 | [(set (reg 33) | |
e221ef54 UW |
513 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q") |
514 | (match_operand:DI 1 "general_operand" "d,K,m,BQ")))] | |
515 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" | |
575f7c2b UW |
516 | "@ |
517 | cgr\t%0,%1 | |
f4f41b4e | 518 | cghi\t%0,%h1 |
575f7c2b | 519 | cg\t%0,%1 |
19b63d8e | 520 | #" |
e221ef54 | 521 | [(set_attr "op_type" "RRE,RI,RXY,SS")]) |
575f7c2b UW |
522 | |
523 | (define_insn "*cmpsi_cct" | |
524 | [(set (reg 33) | |
e221ef54 UW |
525 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
526 | (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))] | |
527 | "s390_match_ccmode (insn, CCTmode)" | |
575f7c2b UW |
528 | "@ |
529 | cr\t%0,%1 | |
f4f41b4e | 530 | chi\t%0,%h1 |
575f7c2b UW |
531 | c\t%0,%1 |
532 | cy\t%0,%1 | |
19b63d8e | 533 | #" |
e221ef54 | 534 | [(set_attr "op_type" "RR,RI,RX,RXY,SS")]) |
575f7c2b UW |
535 | |
536 | ||
07893d4f | 537 | ; Compare (signed) instructions |
4023fb28 | 538 | |
07893d4f | 539 | (define_insn "*cmpdi_ccs_sign" |
4023fb28 | 540 | [(set (reg 33) |
07893d4f UW |
541 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
542 | (match_operand:DI 0 "register_operand" "d,d")))] | |
543 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 544 | "@ |
d40c829f UW |
545 | cgfr\t%0,%1 |
546 | cgf\t%0,%1" | |
d3632d41 | 547 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 548 | |
07893d4f | 549 | (define_insn "*cmpdi_ccs" |
4023fb28 | 550 | [(set (reg 33) |
07893d4f UW |
551 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
552 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
553 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
554 | "@ | |
d40c829f | 555 | cgr\t%0,%1 |
f4f41b4e | 556 | cghi\t%0,%h1 |
d40c829f | 557 | cg\t%0,%1" |
d3632d41 | 558 | [(set_attr "op_type" "RRE,RI,RXY")]) |
c7453384 | 559 | |
07893d4f UW |
560 | (define_insn "*cmpsi_ccs_sign" |
561 | [(set (reg 33) | |
d3632d41 UW |
562 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
563 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 564 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 565 | "@ |
d40c829f UW |
566 | ch\t%0,%1 |
567 | chy\t%0,%1" | |
d3632d41 | 568 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 569 | |
07893d4f | 570 | (define_insn "*cmpsi_ccs" |
9db1d521 | 571 | [(set (reg 33) |
d3632d41 UW |
572 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
573 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
9db1d521 | 574 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 575 | "@ |
d40c829f | 576 | cr\t%0,%1 |
f4f41b4e | 577 | chi\t%0,%h1 |
d40c829f UW |
578 | c\t%0,%1 |
579 | cy\t%0,%1" | |
d3632d41 | 580 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
c7453384 | 581 | |
07893d4f UW |
582 | |
583 | ; Compare (unsigned) instructions | |
9db1d521 | 584 | |
07893d4f | 585 | (define_insn "*cmpdi_ccu_zero" |
9db1d521 | 586 | [(set (reg 33) |
07893d4f UW |
587 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
588 | (match_operand:DI 0 "register_operand" "d,d")))] | |
575f7c2b | 589 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 590 | "@ |
d40c829f UW |
591 | clgfr\t%0,%1 |
592 | clgf\t%0,%1" | |
d3632d41 | 593 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 594 | |
07893d4f | 595 | (define_insn "*cmpdi_ccu" |
9db1d521 | 596 | [(set (reg 33) |
e221ef54 UW |
597 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ") |
598 | (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))] | |
599 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" | |
07893d4f | 600 | "@ |
d40c829f | 601 | clgr\t%0,%1 |
575f7c2b | 602 | clg\t%0,%1 |
e221ef54 | 603 | # |
19b63d8e | 604 | #" |
e221ef54 | 605 | [(set_attr "op_type" "RRE,RXY,SS,SS")]) |
9db1d521 | 606 | |
07893d4f | 607 | (define_insn "*cmpsi_ccu" |
9db1d521 | 608 | [(set (reg 33) |
e221ef54 UW |
609 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ") |
610 | (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))] | |
611 | "s390_match_ccmode (insn, CCUmode)" | |
07893d4f | 612 | "@ |
d40c829f UW |
613 | clr\t%0,%1 |
614 | cl\t%0,%1 | |
575f7c2b | 615 | cly\t%0,%1 |
e221ef54 | 616 | # |
19b63d8e | 617 | #" |
e221ef54 | 618 | [(set_attr "op_type" "RR,RX,RXY,SS,SS")]) |
9db1d521 | 619 | |
07893d4f | 620 | (define_insn "*cmphi_ccu" |
9db1d521 | 621 | [(set (reg 33) |
e221ef54 UW |
622 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") |
623 | (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] | |
575f7c2b | 624 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 625 | && !register_operand (operands[1], HImode)" |
d3632d41 | 626 | "@ |
fc0ea003 UW |
627 | clm\t%0,3,%S1 |
628 | clmy\t%0,3,%S1 | |
e221ef54 | 629 | # |
19b63d8e | 630 | #" |
e221ef54 | 631 | [(set_attr "op_type" "RS,RSY,SS,SS")]) |
9db1d521 HP |
632 | |
633 | (define_insn "*cmpqi_ccu" | |
634 | [(set (reg 33) | |
e221ef54 UW |
635 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
636 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 637 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 638 | && !register_operand (operands[1], QImode)" |
d3632d41 | 639 | "@ |
fc0ea003 UW |
640 | clm\t%0,1,%S1 |
641 | clmy\t%0,1,%S1 | |
642 | cli\t%S0,%b1 | |
643 | cliy\t%S0,%b1 | |
e221ef54 | 644 | # |
19b63d8e | 645 | #" |
e221ef54 | 646 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) |
9db1d521 HP |
647 | |
648 | ||
19b63d8e UW |
649 | ; Block compare (CLC) instruction patterns. |
650 | ||
651 | (define_insn "*clc" | |
652 | [(set (reg 33) | |
d4f52f0e | 653 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
654 | (match_operand:BLK 1 "memory_operand" "Q"))) |
655 | (use (match_operand 2 "const_int_operand" "n"))] | |
656 | "s390_match_ccmode (insn, CCUmode) | |
657 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 658 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 659 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
660 | |
661 | (define_split | |
662 | [(set (reg 33) | |
663 | (compare (match_operand 0 "memory_operand" "") | |
664 | (match_operand 1 "memory_operand" "")))] | |
665 | "reload_completed | |
666 | && s390_match_ccmode (insn, CCUmode) | |
667 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
668 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
669 | [(parallel | |
670 | [(set (match_dup 0) (match_dup 1)) | |
671 | (use (match_dup 2))])] | |
672 | { | |
673 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
674 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
675 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
676 | ||
677 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
678 | operands[0], operands[1]); | |
679 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
680 | }) | |
681 | ||
682 | ||
9db1d521 HP |
683 | ; DF instructions |
684 | ||
685 | (define_insn "*cmpdf_ccs_0" | |
686 | [(set (reg 33) | |
687 | (compare (match_operand:DF 0 "register_operand" "f") | |
688 | (match_operand:DF 1 "const0_operand" "")))] | |
689 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 690 | "ltdbr\t%0,%0" |
077dab3b HP |
691 | [(set_attr "op_type" "RRE") |
692 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
693 | |
694 | (define_insn "*cmpdf_ccs_0_ibm" | |
695 | [(set (reg 33) | |
696 | (compare (match_operand:DF 0 "register_operand" "f") | |
697 | (match_operand:DF 1 "const0_operand" "")))] | |
698 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 699 | "ltdr\t%0,%0" |
077dab3b HP |
700 | [(set_attr "op_type" "RR") |
701 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
702 | |
703 | (define_insn "*cmpdf_ccs" | |
704 | [(set (reg 33) | |
705 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 706 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
707 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
708 | "@ | |
d40c829f UW |
709 | cdbr\t%0,%1 |
710 | cdb\t%0,%1" | |
ce50cae8 | 711 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 712 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
713 | |
714 | (define_insn "*cmpdf_ccs_ibm" | |
715 | [(set (reg 33) | |
716 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 717 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
718 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
719 | "@ | |
d40c829f UW |
720 | cdr\t%0,%1 |
721 | cd\t%0,%1" | |
9db1d521 | 722 | [(set_attr "op_type" "RR,RX") |
077dab3b | 723 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
724 | |
725 | ||
726 | ; SF instructions | |
727 | ||
728 | (define_insn "*cmpsf_ccs_0" | |
729 | [(set (reg 33) | |
730 | (compare (match_operand:SF 0 "register_operand" "f") | |
731 | (match_operand:SF 1 "const0_operand" "")))] | |
732 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 733 | "ltebr\t%0,%0" |
077dab3b HP |
734 | [(set_attr "op_type" "RRE") |
735 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
736 | |
737 | (define_insn "*cmpsf_ccs_0_ibm" | |
738 | [(set (reg 33) | |
739 | (compare (match_operand:SF 0 "register_operand" "f") | |
740 | (match_operand:SF 1 "const0_operand" "")))] | |
741 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 742 | "lter\t%0,%0" |
077dab3b HP |
743 | [(set_attr "op_type" "RR") |
744 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
745 | |
746 | (define_insn "*cmpsf_ccs" | |
747 | [(set (reg 33) | |
748 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 749 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
750 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
751 | "@ | |
d40c829f UW |
752 | cebr\t%0,%1 |
753 | ceb\t%0,%1" | |
077dab3b HP |
754 | [(set_attr "op_type" "RRE,RXE") |
755 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
756 | |
757 | (define_insn "*cmpsf_ccs" | |
758 | [(set (reg 33) | |
759 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 760 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
761 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
762 | "@ | |
d40c829f UW |
763 | cer\t%0,%1 |
764 | ce\t%0,%1" | |
077dab3b HP |
765 | [(set_attr "op_type" "RR,RX") |
766 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
767 | |
768 | ||
769 | ;; | |
770 | ;;- Move instructions. | |
771 | ;; | |
772 | ||
773 | ; | |
774 | ; movti instruction pattern(s). | |
775 | ; | |
776 | ||
777 | (define_insn "movti" | |
d3632d41 UW |
778 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
779 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
9db1d521 | 780 | "TARGET_64BIT" |
4023fb28 | 781 | "@ |
fc0ea003 UW |
782 | lmg\t%0,%N0,%S1 |
783 | stmg\t%1,%N1,%S0 | |
4023fb28 | 784 | # |
9b7c75b9 | 785 | # |
19b63d8e | 786 | #" |
b628bd8e UW |
787 | [(set_attr "op_type" "RSY,RSY,*,*,SS") |
788 | (set_attr "type" "lm,stm,*,*,*")]) | |
4023fb28 UW |
789 | |
790 | (define_split | |
791 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
792 | (match_operand:TI 1 "general_operand" ""))] | |
793 | "TARGET_64BIT && reload_completed | |
dc65c307 | 794 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
795 | [(set (match_dup 2) (match_dup 4)) |
796 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 797 | { |
dc65c307 UW |
798 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
799 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
800 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
801 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
802 | }) | |
803 | ||
804 | (define_split | |
805 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
806 | (match_operand:TI 1 "general_operand" ""))] | |
807 | "TARGET_64BIT && reload_completed | |
808 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
809 | [(set (match_dup 2) (match_dup 4)) | |
810 | (set (match_dup 3) (match_dup 5))] | |
811 | { | |
812 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
813 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
814 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
815 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
816 | }) | |
4023fb28 UW |
817 | |
818 | (define_split | |
819 | [(set (match_operand:TI 0 "register_operand" "") | |
820 | (match_operand:TI 1 "memory_operand" ""))] | |
821 | "TARGET_64BIT && reload_completed | |
822 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 823 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
824 | { |
825 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
826 | s390_load_address (addr, XEXP (operands[1], 0)); | |
827 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
828 | }) |
829 | ||
830 | (define_expand "reload_outti" | |
9c3c3dcc | 831 | [(parallel [(match_operand:TI 0 "" "") |
dc65c307 UW |
832 | (match_operand:TI 1 "register_operand" "d") |
833 | (match_operand:DI 2 "register_operand" "=&a")])] | |
834 | "TARGET_64BIT" | |
835 | { | |
9c3c3dcc | 836 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 837 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
838 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
839 | emit_move_insn (operands[0], operands[1]); | |
840 | DONE; | |
841 | }) | |
9db1d521 HP |
842 | |
843 | ; | |
844 | ; movdi instruction pattern(s). | |
845 | ; | |
846 | ||
9db1d521 HP |
847 | (define_expand "movdi" |
848 | [(set (match_operand:DI 0 "general_operand" "") | |
849 | (match_operand:DI 1 "general_operand" ""))] | |
850 | "" | |
9db1d521 | 851 | { |
fd3cd001 UW |
852 | /* Handle symbolic constants. */ |
853 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
854 | emit_symbolic_move (operands); | |
10bbf137 | 855 | }) |
9db1d521 | 856 | |
4023fb28 UW |
857 | (define_insn "*movdi_larl" |
858 | [(set (match_operand:DI 0 "register_operand" "=d") | |
859 | (match_operand:DI 1 "larl_operand" "X"))] | |
860 | "TARGET_64BIT | |
8e509cf9 | 861 | && !FP_REG_P (operands[0])" |
d40c829f | 862 | "larl\t%0,%1" |
4023fb28 | 863 | [(set_attr "op_type" "RIL") |
077dab3b | 864 | (set_attr "type" "larl")]) |
4023fb28 | 865 | |
9db1d521 | 866 | (define_insn "*movdi_64" |
2f7e5a0d | 867 | [(set (match_operand:DI 0 "nonimmediate_operand" |
c5aa1d12 | 868 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 869 | (match_operand:DI 1 "general_operand" |
c5aa1d12 | 870 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
9db1d521 HP |
871 | "TARGET_64BIT" |
872 | "@ | |
f19a9af7 AK |
873 | lghi\t%0,%h1 |
874 | llihh\t%0,%i1 | |
875 | llihl\t%0,%i1 | |
876 | llilh\t%0,%i1 | |
877 | llill\t%0,%i1 | |
878 | lay\t%0,%a1 | |
d40c829f UW |
879 | lgr\t%0,%1 |
880 | lg\t%0,%1 | |
881 | stg\t%1,%0 | |
882 | ldr\t%0,%1 | |
883 | ld\t%0,%1 | |
884 | ldy\t%0,%1 | |
885 | std\t%1,%0 | |
886 | stdy\t%1,%0 | |
c5aa1d12 UW |
887 | # |
888 | # | |
889 | stam\t%1,%N1,%S0 | |
890 | lam\t%0,%N0,%S1 | |
19b63d8e | 891 | #" |
b628bd8e UW |
892 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, |
893 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
894 | (set_attr "type" "*,*,*,*,*,la,lr,load,store, | |
895 | floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")]) | |
c5aa1d12 UW |
896 | |
897 | (define_split | |
898 | [(set (match_operand:DI 0 "register_operand" "") | |
899 | (match_operand:DI 1 "register_operand" ""))] | |
900 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
901 | [(set (match_dup 2) (match_dup 3)) | |
902 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
903 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
904 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
905 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
906 | ||
907 | (define_split | |
908 | [(set (match_operand:DI 0 "register_operand" "") | |
909 | (match_operand:DI 1 "register_operand" ""))] | |
910 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
911 | && dead_or_set_p (insn, operands[1])" | |
912 | [(set (match_dup 3) (match_dup 2)) | |
913 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
914 | (set (match_dup 4) (match_dup 2))] | |
915 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
916 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
917 | ||
918 | (define_split | |
919 | [(set (match_operand:DI 0 "register_operand" "") | |
920 | (match_operand:DI 1 "register_operand" ""))] | |
921 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
922 | && !dead_or_set_p (insn, operands[1])" | |
923 | [(set (match_dup 3) (match_dup 2)) | |
924 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
925 | (set (match_dup 4) (match_dup 2)) | |
926 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
927 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
928 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
929 | |
930 | (define_insn "*movdi_31" | |
d3632d41 UW |
931 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
932 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
9db1d521 | 933 | "!TARGET_64BIT" |
4023fb28 | 934 | "@ |
fc0ea003 UW |
935 | lm\t%0,%N0,%S1 |
936 | stm\t%1,%N1,%S0 | |
4023fb28 UW |
937 | # |
938 | # | |
d40c829f UW |
939 | ldr\t%0,%1 |
940 | ld\t%0,%1 | |
941 | ldy\t%0,%1 | |
942 | std\t%1,%0 | |
943 | stdy\t%1,%0 | |
19b63d8e | 944 | #" |
b628bd8e UW |
945 | [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS") |
946 | (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")]) | |
4023fb28 UW |
947 | |
948 | (define_split | |
949 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
950 | (match_operand:DI 1 "general_operand" ""))] | |
951 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 952 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
953 | [(set (match_dup 2) (match_dup 4)) |
954 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 955 | { |
dc65c307 UW |
956 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
957 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
958 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
959 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
960 | }) | |
961 | ||
962 | (define_split | |
963 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
964 | (match_operand:DI 1 "general_operand" ""))] | |
965 | "!TARGET_64BIT && reload_completed | |
966 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
967 | [(set (match_dup 2) (match_dup 4)) | |
968 | (set (match_dup 3) (match_dup 5))] | |
969 | { | |
970 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
971 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
972 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
973 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
974 | }) | |
9db1d521 | 975 | |
4023fb28 UW |
976 | (define_split |
977 | [(set (match_operand:DI 0 "register_operand" "") | |
978 | (match_operand:DI 1 "memory_operand" ""))] | |
979 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 980 | && !FP_REG_P (operands[0]) |
4023fb28 | 981 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 982 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
983 | { |
984 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
985 | s390_load_address (addr, XEXP (operands[1], 0)); | |
986 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
987 | }) |
988 | ||
989 | (define_expand "reload_outdi" | |
9c3c3dcc | 990 | [(parallel [(match_operand:DI 0 "" "") |
dc65c307 UW |
991 | (match_operand:DI 1 "register_operand" "d") |
992 | (match_operand:SI 2 "register_operand" "=&a")])] | |
993 | "!TARGET_64BIT" | |
994 | { | |
9c3c3dcc | 995 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 996 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
997 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
998 | emit_move_insn (operands[0], operands[1]); | |
999 | DONE; | |
1000 | }) | |
9db1d521 | 1001 | |
84817c5d UW |
1002 | (define_peephole2 |
1003 | [(set (match_operand:DI 0 "register_operand" "") | |
1004 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1005 | "TARGET_64BIT | |
1006 | && !FP_REG_P (operands[0]) | |
1007 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1008 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1009 | && get_pool_mode (operands[1]) == DImode | |
1010 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1011 | [(set (match_dup 0) (match_dup 2))] | |
1012 | "operands[2] = get_pool_constant (operands[1]);") | |
1013 | ||
7bdff56f UW |
1014 | (define_insn "*la_64" |
1015 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1016 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1017 | "TARGET_64BIT" | |
1018 | "@ | |
1019 | la\t%0,%a1 | |
1020 | lay\t%0,%a1" | |
1021 | [(set_attr "op_type" "RX,RXY") | |
1022 | (set_attr "type" "la")]) | |
1023 | ||
1024 | (define_peephole2 | |
1025 | [(parallel | |
1026 | [(set (match_operand:DI 0 "register_operand" "") | |
1027 | (match_operand:QI 1 "address_operand" "")) | |
1028 | (clobber (reg:CC 33))])] | |
1029 | "TARGET_64BIT | |
e1d5ee28 | 1030 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1031 | [(set (match_dup 0) (match_dup 1))] |
1032 | "") | |
1033 | ||
1034 | (define_peephole2 | |
1035 | [(set (match_operand:DI 0 "register_operand" "") | |
1036 | (match_operand:DI 1 "register_operand" "")) | |
1037 | (parallel | |
1038 | [(set (match_dup 0) | |
1039 | (plus:DI (match_dup 0) | |
1040 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
1041 | (clobber (reg:CC 33))])] | |
1042 | "TARGET_64BIT | |
1043 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1044 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1045 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1046 | "") | |
1047 | ||
1048 | (define_expand "reload_indi" | |
1049 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1050 | (match_operand:DI 1 "s390_plus_operand" "") | |
1051 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1052 | "TARGET_64BIT" | |
1053 | { | |
1054 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1055 | DONE; | |
1056 | }) | |
1057 | ||
9db1d521 HP |
1058 | ; |
1059 | ; movsi instruction pattern(s). | |
1060 | ; | |
1061 | ||
9db1d521 HP |
1062 | (define_expand "movsi" |
1063 | [(set (match_operand:SI 0 "general_operand" "") | |
1064 | (match_operand:SI 1 "general_operand" ""))] | |
1065 | "" | |
9db1d521 | 1066 | { |
fd3cd001 UW |
1067 | /* Handle symbolic constants. */ |
1068 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1069 | emit_symbolic_move (operands); | |
10bbf137 | 1070 | }) |
9db1d521 | 1071 | |
9e8327e3 UW |
1072 | (define_insn "*movsi_larl" |
1073 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1074 | (match_operand:SI 1 "larl_operand" "X"))] | |
1075 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1076 | && !FP_REG_P (operands[0])" | |
1077 | "larl\t%0,%1" | |
1078 | [(set_attr "op_type" "RIL") | |
1079 | (set_attr "type" "larl")]) | |
1080 | ||
f19a9af7 | 1081 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1082 | [(set (match_operand:SI 0 "nonimmediate_operand" |
c5aa1d12 | 1083 | "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 1084 | (match_operand:SI 1 "general_operand" |
c5aa1d12 | 1085 | "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
f19a9af7 | 1086 | "TARGET_ZARCH" |
9db1d521 | 1087 | "@ |
f19a9af7 AK |
1088 | lhi\t%0,%h1 |
1089 | llilh\t%0,%i1 | |
1090 | llill\t%0,%i1 | |
1091 | lay\t%0,%a1 | |
d40c829f UW |
1092 | lr\t%0,%1 |
1093 | l\t%0,%1 | |
1094 | ly\t%0,%1 | |
1095 | st\t%1,%0 | |
1096 | sty\t%1,%0 | |
1097 | ler\t%0,%1 | |
1098 | le\t%0,%1 | |
1099 | ley\t%0,%1 | |
1100 | ste\t%1,%0 | |
1101 | stey\t%1,%0 | |
c5aa1d12 UW |
1102 | ear\t%0,%1 |
1103 | sar\t%0,%1 | |
1104 | stam\t%1,%1,%S0 | |
1105 | lam\t%0,%0,%S1 | |
19b63d8e | 1106 | #" |
b628bd8e UW |
1107 | [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY, |
1108 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") | |
1109 | (set_attr "type" "*,*,*,la,lr,load,load,store,store, | |
1110 | floads,floads,floads,fstores,fstores,*,*,*,*,*")]) | |
f19a9af7 AK |
1111 | |
1112 | (define_insn "*movsi_esa" | |
c5aa1d12 UW |
1113 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") |
1114 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))] | |
f19a9af7 AK |
1115 | "!TARGET_ZARCH" |
1116 | "@ | |
1117 | lhi\t%0,%h1 | |
1118 | lr\t%0,%1 | |
1119 | l\t%0,%1 | |
1120 | st\t%1,%0 | |
1121 | ler\t%0,%1 | |
1122 | le\t%0,%1 | |
1123 | ste\t%1,%0 | |
c5aa1d12 UW |
1124 | ear\t%0,%1 |
1125 | sar\t%0,%1 | |
1126 | stam\t%1,%1,%S0 | |
1127 | lam\t%0,%0,%S1 | |
19b63d8e | 1128 | #" |
c5aa1d12 | 1129 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") |
b628bd8e | 1130 | (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")]) |
9db1d521 | 1131 | |
84817c5d UW |
1132 | (define_peephole2 |
1133 | [(set (match_operand:SI 0 "register_operand" "") | |
1134 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1135 | "!FP_REG_P (operands[0]) | |
1136 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1137 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1138 | && get_pool_mode (operands[1]) == SImode | |
1139 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1140 | [(set (match_dup 0) (match_dup 2))] | |
1141 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1142 | |
7bdff56f UW |
1143 | (define_insn "*la_31" |
1144 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1145 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1146 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1147 | "@ | |
1148 | la\t%0,%a1 | |
1149 | lay\t%0,%a1" | |
1150 | [(set_attr "op_type" "RX,RXY") | |
1151 | (set_attr "type" "la")]) | |
1152 | ||
1153 | (define_peephole2 | |
1154 | [(parallel | |
1155 | [(set (match_operand:SI 0 "register_operand" "") | |
1156 | (match_operand:QI 1 "address_operand" "")) | |
1157 | (clobber (reg:CC 33))])] | |
1158 | "!TARGET_64BIT | |
e1d5ee28 | 1159 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1160 | [(set (match_dup 0) (match_dup 1))] |
1161 | "") | |
1162 | ||
1163 | (define_peephole2 | |
1164 | [(set (match_operand:SI 0 "register_operand" "") | |
1165 | (match_operand:SI 1 "register_operand" "")) | |
1166 | (parallel | |
1167 | [(set (match_dup 0) | |
1168 | (plus:SI (match_dup 0) | |
1169 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
1170 | (clobber (reg:CC 33))])] | |
1171 | "!TARGET_64BIT | |
1172 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1173 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1174 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1175 | "") | |
1176 | ||
1177 | (define_insn "*la_31_and" | |
1178 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1179 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1180 | (const_int 2147483647)))] | |
1181 | "!TARGET_64BIT" | |
1182 | "@ | |
1183 | la\t%0,%a1 | |
1184 | lay\t%0,%a1" | |
1185 | [(set_attr "op_type" "RX,RXY") | |
1186 | (set_attr "type" "la")]) | |
1187 | ||
1188 | (define_insn_and_split "*la_31_and_cc" | |
1189 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1190 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1191 | (const_int 2147483647))) | |
1192 | (clobber (reg:CC 33))] | |
1193 | "!TARGET_64BIT" | |
1194 | "#" | |
1195 | "&& reload_completed" | |
1196 | [(set (match_dup 0) | |
1197 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1198 | "" | |
1199 | [(set_attr "op_type" "RX") | |
1200 | (set_attr "type" "la")]) | |
1201 | ||
1202 | (define_insn "force_la_31" | |
1203 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1204 | (match_operand:QI 1 "address_operand" "U,W")) | |
1205 | (use (const_int 0))] | |
1206 | "!TARGET_64BIT" | |
1207 | "@ | |
1208 | la\t%0,%a1 | |
1209 | lay\t%0,%a1" | |
1210 | [(set_attr "op_type" "RX") | |
1211 | (set_attr "type" "la")]) | |
1212 | ||
1213 | (define_expand "reload_insi" | |
1214 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1215 | (match_operand:SI 1 "s390_plus_operand" "") | |
1216 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1217 | "!TARGET_64BIT" | |
1218 | { | |
1219 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1220 | DONE; | |
1221 | }) | |
1222 | ||
9db1d521 HP |
1223 | ; |
1224 | ; movhi instruction pattern(s). | |
1225 | ; | |
1226 | ||
02ed3c5e UW |
1227 | (define_expand "movhi" |
1228 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1229 | (match_operand:HI 1 "general_operand" ""))] | |
1230 | "" | |
1231 | { | |
2f7e5a0d | 1232 | /* Make it explicit that loading a register from memory |
02ed3c5e UW |
1233 | always sign-extends (at least) to SImode. */ |
1234 | if (optimize && !no_new_pseudos | |
1235 | && register_operand (operands[0], VOIDmode) | |
8fff4fc1 | 1236 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1237 | { |
1238 | rtx tmp = gen_reg_rtx (SImode); | |
1239 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1240 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1241 | operands[1] = gen_lowpart (HImode, tmp); | |
1242 | } | |
1243 | }) | |
1244 | ||
1245 | (define_insn "*movhi" | |
d3632d41 UW |
1246 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1247 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1248 | "" |
1249 | "@ | |
d40c829f UW |
1250 | lr\t%0,%1 |
1251 | lhi\t%0,%h1 | |
1252 | lh\t%0,%1 | |
1253 | lhy\t%0,%1 | |
1254 | sth\t%1,%0 | |
1255 | sthy\t%1,%0 | |
19b63d8e | 1256 | #" |
d3632d41 | 1257 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
b628bd8e | 1258 | (set_attr "type" "lr,*,*,*,store,store,*")]) |
9db1d521 | 1259 | |
84817c5d UW |
1260 | (define_peephole2 |
1261 | [(set (match_operand:HI 0 "register_operand" "") | |
1262 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1263 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1264 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1265 | && get_pool_mode (operands[1]) == HImode | |
1266 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1267 | [(set (match_dup 0) (match_dup 2))] | |
1268 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1269 | |
9db1d521 HP |
1270 | ; |
1271 | ; movqi instruction pattern(s). | |
1272 | ; | |
1273 | ||
02ed3c5e UW |
1274 | (define_expand "movqi" |
1275 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1276 | (match_operand:QI 1 "general_operand" ""))] | |
1277 | "" | |
1278 | { | |
c19ec8f9 | 1279 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1280 | is just as fast as a QImode load. */ |
c19ec8f9 | 1281 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1282 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1283 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1284 | { |
c19ec8f9 UW |
1285 | rtx tmp = gen_reg_rtx (word_mode); |
1286 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1287 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1288 | operands[1] = gen_lowpart (QImode, tmp); | |
1289 | } | |
1290 | }) | |
4023fb28 | 1291 | |
02ed3c5e | 1292 | (define_insn "*movqi" |
d3632d41 UW |
1293 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1294 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1295 | "" |
1296 | "@ | |
d40c829f UW |
1297 | lr\t%0,%1 |
1298 | lhi\t%0,%b1 | |
1299 | ic\t%0,%1 | |
1300 | icy\t%0,%1 | |
1301 | stc\t%1,%0 | |
1302 | stcy\t%1,%0 | |
fc0ea003 UW |
1303 | mvi\t%S0,%b1 |
1304 | mviy\t%S0,%b1 | |
19b63d8e | 1305 | #" |
d3632d41 | 1306 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
b628bd8e | 1307 | (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) |
9db1d521 | 1308 | |
84817c5d UW |
1309 | (define_peephole2 |
1310 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1311 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1312 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1313 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1314 | && get_pool_mode (operands[1]) == QImode | |
1315 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1316 | [(set (match_dup 0) (match_dup 2))] | |
1317 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1318 | |
9db1d521 | 1319 | ; |
05b9aaaa | 1320 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1321 | ; |
1322 | ||
1323 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1324 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1325 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1326 | "" |
d3632d41 | 1327 | "@ |
d40c829f UW |
1328 | ic\t%0,%1 |
1329 | icy\t%0,%1" | |
d3632d41 | 1330 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1331 | |
1332 | ; | |
1333 | ; movstricthi instruction pattern(s). | |
1334 | ; | |
1335 | ||
1336 | (define_insn "*movstricthi" | |
d3632d41 | 1337 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1338 | (match_operand:HI 1 "memory_operand" "Q,S")) |
9db1d521 HP |
1339 | (clobber (reg:CC 33))] |
1340 | "" | |
d3632d41 | 1341 | "@ |
fc0ea003 UW |
1342 | icm\t%0,3,%S1 |
1343 | icmy\t%0,3,%S1" | |
d3632d41 | 1344 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1345 | |
1346 | ; | |
1347 | ; movstrictsi instruction pattern(s). | |
1348 | ; | |
1349 | ||
05b9aaaa | 1350 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1351 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1352 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1353 | "TARGET_64BIT" |
1354 | "@ | |
d40c829f UW |
1355 | lr\t%0,%1 |
1356 | l\t%0,%1 | |
c5aa1d12 UW |
1357 | ly\t%0,%1 |
1358 | ear\t%0,%1" | |
1359 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
1360 | (set_attr "type" "lr,load,load,*")]) | |
9db1d521 HP |
1361 | |
1362 | ; | |
1363 | ; movdf instruction pattern(s). | |
1364 | ; | |
1365 | ||
1366 | (define_expand "movdf" | |
1367 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1368 | (match_operand:DF 1 "general_operand" ""))] | |
1369 | "" | |
13c025c1 | 1370 | "") |
9db1d521 HP |
1371 | |
1372 | (define_insn "*movdf_64" | |
d3632d41 UW |
1373 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") |
1374 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1375 | "TARGET_64BIT" |
9db1d521 | 1376 | "@ |
d40c829f UW |
1377 | ldr\t%0,%1 |
1378 | ld\t%0,%1 | |
1379 | ldy\t%0,%1 | |
1380 | std\t%1,%0 | |
1381 | stdy\t%1,%0 | |
1382 | lgr\t%0,%1 | |
1383 | lg\t%0,%1 | |
1384 | stg\t%1,%0 | |
19b63d8e | 1385 | #" |
d3632d41 | 1386 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
b628bd8e | 1387 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")]) |
9db1d521 HP |
1388 | |
1389 | (define_insn "*movdf_31" | |
d3632d41 UW |
1390 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") |
1391 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] | |
4023fb28 | 1392 | "!TARGET_64BIT" |
9db1d521 | 1393 | "@ |
d40c829f UW |
1394 | ldr\t%0,%1 |
1395 | ld\t%0,%1 | |
1396 | ldy\t%0,%1 | |
1397 | std\t%1,%0 | |
1398 | stdy\t%1,%0 | |
fc0ea003 UW |
1399 | lm\t%0,%N0,%S1 |
1400 | stm\t%1,%N1,%S0 | |
4023fb28 | 1401 | # |
9b7c75b9 | 1402 | # |
19b63d8e | 1403 | #" |
b628bd8e UW |
1404 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS") |
1405 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")]) | |
4023fb28 UW |
1406 | |
1407 | (define_split | |
1408 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1409 | (match_operand:DF 1 "general_operand" ""))] | |
1410 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1411 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1412 | [(set (match_dup 2) (match_dup 4)) |
1413 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1414 | { |
dc65c307 UW |
1415 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1416 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1417 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1418 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1419 | }) | |
1420 | ||
1421 | (define_split | |
1422 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1423 | (match_operand:DF 1 "general_operand" ""))] | |
1424 | "!TARGET_64BIT && reload_completed | |
1425 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1426 | [(set (match_dup 2) (match_dup 4)) | |
1427 | (set (match_dup 3) (match_dup 5))] | |
1428 | { | |
1429 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1430 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1431 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1432 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1433 | }) | |
9db1d521 | 1434 | |
4023fb28 UW |
1435 | (define_split |
1436 | [(set (match_operand:DF 0 "register_operand" "") | |
1437 | (match_operand:DF 1 "memory_operand" ""))] | |
1438 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1439 | && !FP_REG_P (operands[0]) |
4023fb28 | 1440 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1441 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1442 | { |
1443 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1444 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1445 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1446 | }) |
1447 | ||
1448 | (define_expand "reload_outdf" | |
9c3c3dcc | 1449 | [(parallel [(match_operand:DF 0 "" "") |
dc65c307 UW |
1450 | (match_operand:DF 1 "register_operand" "d") |
1451 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1452 | "!TARGET_64BIT" | |
1453 | { | |
9c3c3dcc | 1454 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1455 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1456 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1457 | emit_move_insn (operands[0], operands[1]); | |
1458 | DONE; | |
1459 | }) | |
9db1d521 HP |
1460 | |
1461 | ; | |
1462 | ; movsf instruction pattern(s). | |
1463 | ; | |
1464 | ||
13c025c1 | 1465 | (define_insn "movsf" |
d3632d41 UW |
1466 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") |
1467 | (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1468 | "" |
9db1d521 | 1469 | "@ |
d40c829f UW |
1470 | ler\t%0,%1 |
1471 | le\t%0,%1 | |
1472 | ley\t%0,%1 | |
1473 | ste\t%1,%0 | |
1474 | stey\t%1,%0 | |
1475 | lr\t%0,%1 | |
1476 | l\t%0,%1 | |
1477 | ly\t%0,%1 | |
1478 | st\t%1,%0 | |
1479 | sty\t%1,%0 | |
19b63d8e | 1480 | #" |
d3632d41 | 1481 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
b628bd8e UW |
1482 | (set_attr "type" "floads,floads,floads,fstores,fstores, |
1483 | lr,load,load,store,store,*")]) | |
4023fb28 | 1484 | |
9dc62c00 AK |
1485 | ; |
1486 | ; movcc instruction pattern | |
1487 | ; | |
1488 | ||
1489 | (define_insn "movcc" | |
1490 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
1491 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
1492 | "" | |
1493 | "@ | |
1494 | lr\t%0,%1 | |
1495 | tmh\t%1,12288 | |
1496 | ipm\t%0 | |
1497 | st\t%0,%1 | |
1498 | sty\t%0,%1 | |
1499 | l\t%1,%0 | |
1500 | ly\t%1,%0" | |
8dd3b235 AK |
1501 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
1502 | (set_attr "type" "lr,*,*,store,store,load,load")]) | |
9dc62c00 | 1503 | |
19b63d8e UW |
1504 | ; |
1505 | ; Block move (MVC) patterns. | |
1506 | ; | |
1507 | ||
1508 | (define_insn "*mvc" | |
1509 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
1510 | (match_operand:BLK 1 "memory_operand" "Q")) | |
1511 | (use (match_operand 2 "const_int_operand" "n"))] | |
1512 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1513 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 1514 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1515 | |
1516 | (define_split | |
1517 | [(set (match_operand 0 "memory_operand" "") | |
1518 | (match_operand 1 "memory_operand" ""))] | |
1519 | "reload_completed | |
1520 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1521 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1522 | [(parallel | |
1523 | [(set (match_dup 0) (match_dup 1)) | |
1524 | (use (match_dup 2))])] | |
1525 | { | |
1526 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1527 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1528 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1529 | }) | |
1530 | ||
1531 | (define_peephole2 | |
1532 | [(parallel | |
1533 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1534 | (match_operand:BLK 1 "memory_operand" "")) | |
1535 | (use (match_operand 2 "const_int_operand" ""))]) | |
1536 | (parallel | |
1537 | [(set (match_operand:BLK 3 "memory_operand" "") | |
1538 | (match_operand:BLK 4 "memory_operand" "")) | |
1539 | (use (match_operand 5 "const_int_operand" ""))])] | |
1540 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
1541 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
1542 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
1543 | [(parallel | |
1544 | [(set (match_dup 6) (match_dup 7)) | |
1545 | (use (match_dup 8))])] | |
1546 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
1547 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
1548 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
1549 | ||
1550 | ||
9db1d521 HP |
1551 | ; |
1552 | ; load_multiple pattern(s). | |
1553 | ; | |
22ea6b4f UW |
1554 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1555 | ; we currently support load_multiple/store_multiple only after reload. | |
1556 | ; | |
9db1d521 HP |
1557 | |
1558 | (define_expand "load_multiple" | |
1559 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1560 | (match_operand 1 "" "")) | |
1561 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1562 | "reload_completed" |
9db1d521 | 1563 | { |
c19ec8f9 | 1564 | enum machine_mode mode; |
9db1d521 HP |
1565 | int regno; |
1566 | int count; | |
1567 | rtx from; | |
4023fb28 | 1568 | int i, off; |
9db1d521 HP |
1569 | |
1570 | /* Support only loading a constant number of fixed-point registers from | |
1571 | memory and only bother with this if more than two */ | |
1572 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1573 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1574 | || INTVAL (operands[2]) > 16 |
1575 | || GET_CODE (operands[1]) != MEM | |
1576 | || GET_CODE (operands[0]) != REG | |
1577 | || REGNO (operands[0]) >= 16) | |
1578 | FAIL; | |
1579 | ||
1580 | count = INTVAL (operands[2]); | |
1581 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1582 | mode = GET_MODE (operands[0]); |
1583 | if (mode != SImode && mode != word_mode) | |
1584 | FAIL; | |
9db1d521 HP |
1585 | |
1586 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1587 | if (no_new_pseudos) |
1588 | { | |
1589 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1590 | { | |
1591 | from = XEXP (operands[1], 0); | |
1592 | off = 0; | |
1593 | } | |
1594 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1595 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1596 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1597 | { | |
1598 | from = XEXP (XEXP (operands[1], 0), 0); | |
1599 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1600 | } | |
1601 | else | |
1602 | FAIL; | |
4023fb28 UW |
1603 | } |
1604 | else | |
1605 | { | |
1606 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1607 | off = 0; | |
1608 | } | |
9db1d521 HP |
1609 | |
1610 | for (i = 0; i < count; i++) | |
1611 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1612 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1613 | change_address (operands[1], mode, | |
1614 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1615 | }) |
9db1d521 HP |
1616 | |
1617 | (define_insn "*load_multiple_di" | |
1618 | [(match_parallel 0 "load_multiple_operation" | |
1619 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1620 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1621 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1622 | { |
1623 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1624 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1625 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 1626 | } |
d3632d41 | 1627 | [(set_attr "op_type" "RSY") |
4023fb28 | 1628 | (set_attr "type" "lm")]) |
9db1d521 HP |
1629 | |
1630 | (define_insn "*load_multiple_si" | |
1631 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1632 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1633 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1634 | "reload_completed" |
9db1d521 HP |
1635 | { |
1636 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1637 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1638 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 1639 | } |
d3632d41 | 1640 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1641 | (set_attr "type" "lm")]) |
9db1d521 HP |
1642 | |
1643 | ; | |
c7453384 | 1644 | ; store multiple pattern(s). |
9db1d521 HP |
1645 | ; |
1646 | ||
1647 | (define_expand "store_multiple" | |
1648 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1649 | (match_operand 1 "" "")) | |
1650 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1651 | "reload_completed" |
9db1d521 | 1652 | { |
c19ec8f9 | 1653 | enum machine_mode mode; |
9db1d521 HP |
1654 | int regno; |
1655 | int count; | |
1656 | rtx to; | |
4023fb28 | 1657 | int i, off; |
9db1d521 HP |
1658 | |
1659 | /* Support only storing a constant number of fixed-point registers to | |
1660 | memory and only bother with this if more than two. */ | |
1661 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1662 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1663 | || INTVAL (operands[2]) > 16 |
1664 | || GET_CODE (operands[0]) != MEM | |
1665 | || GET_CODE (operands[1]) != REG | |
1666 | || REGNO (operands[1]) >= 16) | |
1667 | FAIL; | |
1668 | ||
1669 | count = INTVAL (operands[2]); | |
1670 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1671 | mode = GET_MODE (operands[1]); |
1672 | if (mode != SImode && mode != word_mode) | |
1673 | FAIL; | |
9db1d521 HP |
1674 | |
1675 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1676 | |
1677 | if (no_new_pseudos) | |
1678 | { | |
1679 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1680 | { | |
1681 | to = XEXP (operands[0], 0); | |
1682 | off = 0; | |
1683 | } | |
1684 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1685 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1686 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1687 | { | |
1688 | to = XEXP (XEXP (operands[0], 0), 0); | |
1689 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1690 | } | |
1691 | else | |
1692 | FAIL; | |
4023fb28 | 1693 | } |
c7453384 | 1694 | else |
4023fb28 UW |
1695 | { |
1696 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1697 | off = 0; | |
1698 | } | |
9db1d521 HP |
1699 | |
1700 | for (i = 0; i < count; i++) | |
1701 | XVECEXP (operands[3], 0, i) | |
1702 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1703 | change_address (operands[0], mode, |
1704 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1705 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1706 | }) |
9db1d521 HP |
1707 | |
1708 | (define_insn "*store_multiple_di" | |
1709 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1710 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1711 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1712 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1713 | { |
1714 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1715 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1716 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 1717 | } |
d3632d41 | 1718 | [(set_attr "op_type" "RSY") |
4023fb28 | 1719 | (set_attr "type" "stm")]) |
9db1d521 HP |
1720 | |
1721 | ||
1722 | (define_insn "*store_multiple_si" | |
1723 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1724 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1725 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1726 | "reload_completed" |
9db1d521 HP |
1727 | { |
1728 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1729 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1730 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 1731 | } |
d3632d41 | 1732 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1733 | (set_attr "type" "stm")]) |
9db1d521 HP |
1734 | |
1735 | ;; | |
1736 | ;; String instructions. | |
1737 | ;; | |
1738 | ||
9bb86f41 UW |
1739 | (define_insn "*execute" |
1740 | [(match_parallel 0 "" | |
1741 | [(unspec [(match_operand 1 "register_operand" "a") | |
1742 | (match_operand:BLK 2 "memory_operand" "R") | |
1743 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
1744 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
1745 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
1746 | "ex\t%1,%2" | |
29a74354 UW |
1747 | [(set_attr "op_type" "RX") |
1748 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
1749 | |
1750 | ||
91d39d71 UW |
1751 | ; |
1752 | ; strlenM instruction pattern(s). | |
1753 | ; | |
1754 | ||
9db2f16d | 1755 | (define_expand "strlen<mode>" |
91d39d71 | 1756 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) |
2f7e5a0d | 1757 | (parallel |
91d39d71 | 1758 | [(set (match_dup 4) |
9db2f16d | 1759 | (unspec:P [(const_int 0) |
91d39d71 UW |
1760 | (match_operand:BLK 1 "memory_operand" "") |
1761 | (reg:QI 0) | |
1762 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
9db2f16d | 1763 | (clobber (scratch:P)) |
91d39d71 UW |
1764 | (clobber (reg:CC 33))]) |
1765 | (parallel | |
9db2f16d AS |
1766 | [(set (match_operand:P 0 "register_operand" "") |
1767 | (minus:P (match_dup 4) (match_dup 5))) | |
91d39d71 | 1768 | (clobber (reg:CC 33))])] |
9db2f16d | 1769 | "" |
91d39d71 | 1770 | { |
9db2f16d AS |
1771 | operands[4] = gen_reg_rtx (Pmode); |
1772 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
1773 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
1774 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1775 | }) | |
1776 | ||
9db2f16d AS |
1777 | (define_insn "*strlen<mode>" |
1778 | [(set (match_operand:P 0 "register_operand" "=a") | |
1779 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
1780 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
91d39d71 UW |
1781 | (reg:QI 0) |
1782 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
9db2f16d | 1783 | (clobber (match_scratch:P 1 "=a")) |
2f7e5a0d | 1784 | (clobber (reg:CC 33))] |
9db2f16d | 1785 | "" |
91d39d71 | 1786 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
1787 | [(set_attr "length" "8") |
1788 | (set_attr "type" "vs")]) | |
91d39d71 | 1789 | |
9db1d521 | 1790 | ; |
70128ad9 | 1791 | ; movmemM instruction pattern(s). |
9db1d521 HP |
1792 | ; |
1793 | ||
9db2f16d | 1794 | (define_expand "movmem<mode>" |
a41c6c53 UW |
1795 | [(set (match_operand:BLK 0 "memory_operand" "") |
1796 | (match_operand:BLK 1 "memory_operand" "")) | |
9db2f16d | 1797 | (use (match_operand:GPR 2 "general_operand" "")) |
a41c6c53 UW |
1798 | (match_operand 3 "" "")] |
1799 | "" | |
70128ad9 | 1800 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 1801 | |
ecbe845e UW |
1802 | ; Move a block that is up to 256 bytes in length. |
1803 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1804 | |
70128ad9 | 1805 | (define_expand "movmem_short" |
b9404c99 UW |
1806 | [(parallel |
1807 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1808 | (match_operand:BLK 1 "memory_operand" "")) | |
1809 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 1810 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
1811 | (clobber (match_dup 3))])] |
1812 | "" | |
1813 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 1814 | |
70128ad9 | 1815 | (define_insn "*movmem_short" |
9bb86f41 UW |
1816 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
1817 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) | |
1818 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
1819 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
1820 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 1821 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
1822 | && GET_MODE (operands[4]) == Pmode" |
1823 | "#" | |
b628bd8e | 1824 | [(set_attr "type" "cs")]) |
ecbe845e | 1825 | |
9bb86f41 UW |
1826 | (define_split |
1827 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1828 | (match_operand:BLK 1 "memory_operand" "")) | |
1829 | (use (match_operand 2 "const_int_operand" "")) | |
1830 | (use (match_operand 3 "immediate_operand" "")) | |
1831 | (clobber (scratch))] | |
1832 | "reload_completed" | |
1833 | [(parallel | |
1834 | [(set (match_dup 0) (match_dup 1)) | |
1835 | (use (match_dup 2))])] | |
1836 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 1837 | |
9bb86f41 UW |
1838 | (define_split |
1839 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1840 | (match_operand:BLK 1 "memory_operand" "")) | |
1841 | (use (match_operand 2 "register_operand" "")) | |
1842 | (use (match_operand 3 "memory_operand" "")) | |
1843 | (clobber (scratch))] | |
1844 | "reload_completed" | |
1845 | [(parallel | |
1846 | [(unspec [(match_dup 2) (match_dup 3) | |
1847 | (const_int 0)] UNSPEC_EXECUTE) | |
1848 | (set (match_dup 0) (match_dup 1)) | |
1849 | (use (const_int 1))])] | |
1850 | "") | |
1851 | ||
1852 | (define_split | |
1853 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1854 | (match_operand:BLK 1 "memory_operand" "")) | |
1855 | (use (match_operand 2 "register_operand" "")) | |
1856 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
1857 | (clobber (match_operand 3 "register_operand" ""))] | |
1858 | "reload_completed && TARGET_CPU_ZARCH" | |
1859 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
1860 | (parallel | |
1861 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
1862 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
1863 | (set (match_dup 0) (match_dup 1)) | |
1864 | (use (const_int 1))])] | |
1865 | "operands[4] = gen_label_rtx ();") | |
1866 | ||
a41c6c53 | 1867 | ; Move a block of arbitrary length. |
9db1d521 | 1868 | |
70128ad9 | 1869 | (define_expand "movmem_long" |
b9404c99 UW |
1870 | [(parallel |
1871 | [(clobber (match_dup 2)) | |
1872 | (clobber (match_dup 3)) | |
1873 | (set (match_operand:BLK 0 "memory_operand" "") | |
1874 | (match_operand:BLK 1 "memory_operand" "")) | |
1875 | (use (match_operand 2 "general_operand" "")) | |
1876 | (use (match_dup 3)) | |
1877 | (clobber (reg:CC 33))])] | |
1878 | "" | |
1879 | { | |
1880 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
1881 | rtx reg0 = gen_reg_rtx (dword_mode); | |
1882 | rtx reg1 = gen_reg_rtx (dword_mode); | |
1883 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
1884 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
1885 | rtx len0 = gen_lowpart (Pmode, reg0); | |
1886 | rtx len1 = gen_lowpart (Pmode, reg1); | |
1887 | ||
1888 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
1889 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
1890 | emit_move_insn (len0, operands[2]); | |
1891 | ||
1892 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
1893 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1894 | emit_move_insn (len1, operands[2]); | |
1895 | ||
1896 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
1897 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
1898 | operands[2] = reg0; | |
1899 | operands[3] = reg1; | |
1900 | }) | |
1901 | ||
70128ad9 | 1902 | (define_insn "*movmem_long_64" |
b9404c99 UW |
1903 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
1904 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
1905 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
1906 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) | |
1907 | (use (match_dup 2)) | |
1908 | (use (match_dup 3)) | |
9db1d521 | 1909 | (clobber (reg:CC 33))] |
9f37ccb1 | 1910 | "TARGET_64BIT" |
d40c829f | 1911 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
1912 | [(set_attr "length" "8") |
1913 | (set_attr "type" "vs")]) | |
9db1d521 | 1914 | |
70128ad9 | 1915 | (define_insn "*movmem_long_31" |
b9404c99 UW |
1916 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
1917 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
1918 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
1919 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) | |
1920 | (use (match_dup 2)) | |
1921 | (use (match_dup 3)) | |
9db1d521 | 1922 | (clobber (reg:CC 33))] |
9f37ccb1 | 1923 | "!TARGET_64BIT" |
d40c829f | 1924 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
1925 | [(set_attr "length" "8") |
1926 | (set_attr "type" "vs")]) | |
9db1d521 HP |
1927 | |
1928 | ; | |
70128ad9 | 1929 | ; clrmemM instruction pattern(s). |
9db1d521 HP |
1930 | ; |
1931 | ||
9db2f16d | 1932 | (define_expand "clrmem<mode>" |
a41c6c53 | 1933 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 | 1934 | (const_int 0)) |
9db2f16d | 1935 | (use (match_operand:GPR 1 "general_operand" "")) |
9db1d521 | 1936 | (match_operand 2 "" "")] |
a41c6c53 | 1937 | "" |
70128ad9 | 1938 | "s390_expand_clrmem (operands[0], operands[1]); DONE;") |
9db1d521 | 1939 | |
a41c6c53 | 1940 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
1941 | ; The block length is taken as (operands[1] % 256) + 1. |
1942 | ||
70128ad9 | 1943 | (define_expand "clrmem_short" |
b9404c99 UW |
1944 | [(parallel |
1945 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1946 | (const_int 0)) | |
1947 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 1948 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
1949 | (clobber (match_dup 2)) |
1950 | (clobber (reg:CC 33))])] | |
1951 | "" | |
1952 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 1953 | |
70128ad9 | 1954 | (define_insn "*clrmem_short" |
9bb86f41 | 1955 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
a41c6c53 | 1956 | (const_int 0)) |
9bb86f41 UW |
1957 | (use (match_operand 1 "nonmemory_operand" "n,a,a")) |
1958 | (use (match_operand 2 "immediate_operand" "X,R,X")) | |
1959 | (clobber (match_scratch 3 "=X,X,&a")) | |
a41c6c53 | 1960 | (clobber (reg:CC 33))] |
b9404c99 | 1961 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
1962 | && GET_MODE (operands[3]) == Pmode" |
1963 | "#" | |
b628bd8e | 1964 | [(set_attr "type" "cs")]) |
9bb86f41 UW |
1965 | |
1966 | (define_split | |
1967 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1968 | (const_int 0)) | |
1969 | (use (match_operand 1 "const_int_operand" "")) | |
1970 | (use (match_operand 2 "immediate_operand" "")) | |
1971 | (clobber (scratch)) | |
1972 | (clobber (reg:CC 33))] | |
1973 | "reload_completed" | |
1974 | [(parallel | |
1975 | [(set (match_dup 0) (const_int 0)) | |
1976 | (use (match_dup 1)) | |
1977 | (clobber (reg:CC 33))])] | |
1978 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") | |
9db1d521 | 1979 | |
9bb86f41 UW |
1980 | (define_split |
1981 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1982 | (const_int 0)) | |
1983 | (use (match_operand 1 "register_operand" "")) | |
1984 | (use (match_operand 2 "memory_operand" "")) | |
1985 | (clobber (scratch)) | |
1986 | (clobber (reg:CC 33))] | |
1987 | "reload_completed" | |
1988 | [(parallel | |
1989 | [(unspec [(match_dup 1) (match_dup 2) | |
1990 | (const_int 0)] UNSPEC_EXECUTE) | |
1991 | (set (match_dup 0) (const_int 0)) | |
1992 | (use (const_int 1)) | |
1993 | (clobber (reg:CC 33))])] | |
1994 | "") | |
9db1d521 | 1995 | |
9bb86f41 UW |
1996 | (define_split |
1997 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1998 | (const_int 0)) | |
1999 | (use (match_operand 1 "register_operand" "")) | |
2000 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2001 | (clobber (match_operand 2 "register_operand" "")) | |
2002 | (clobber (reg:CC 33))] | |
2003 | "reload_completed && TARGET_CPU_ZARCH" | |
2004 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2005 | (parallel | |
2006 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
2007 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2008 | (set (match_dup 0) (const_int 0)) | |
2009 | (use (const_int 1)) | |
2010 | (clobber (reg:CC 33))])] | |
2011 | "operands[3] = gen_label_rtx ();") | |
2012 | ||
b9404c99 UW |
2013 | ; Clear a block of arbitrary length. |
2014 | ||
70128ad9 | 2015 | (define_expand "clrmem_long" |
b9404c99 UW |
2016 | [(parallel |
2017 | [(clobber (match_dup 1)) | |
2018 | (set (match_operand:BLK 0 "memory_operand" "") | |
2019 | (const_int 0)) | |
2020 | (use (match_operand 1 "general_operand" "")) | |
2021 | (use (match_dup 2)) | |
2022 | (clobber (reg:CC 33))])] | |
2023 | "" | |
a41c6c53 | 2024 | { |
b9404c99 UW |
2025 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2026 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2027 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2028 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2029 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2030 | |
b9404c99 UW |
2031 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2032 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2033 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2034 | |
b9404c99 | 2035 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2036 | |
b9404c99 UW |
2037 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2038 | operands[1] = reg0; | |
2039 | operands[2] = reg1; | |
2040 | }) | |
a41c6c53 | 2041 | |
70128ad9 | 2042 | (define_insn "*clrmem_long_64" |
b9404c99 UW |
2043 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2044 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
9db1d521 | 2045 | (const_int 0)) |
b9404c99 | 2046 | (use (match_dup 2)) |
9f37ccb1 | 2047 | (use (match_operand:TI 1 "register_operand" "d")) |
9db1d521 HP |
2048 | (clobber (reg:CC 33))] |
2049 | "TARGET_64BIT" | |
d40c829f | 2050 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2051 | [(set_attr "length" "8") |
2052 | (set_attr "type" "vs")]) | |
9db1d521 | 2053 | |
70128ad9 | 2054 | (define_insn "*clrmem_long_31" |
b9404c99 UW |
2055 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2056 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
9db1d521 | 2057 | (const_int 0)) |
b9404c99 | 2058 | (use (match_dup 2)) |
9f37ccb1 | 2059 | (use (match_operand:DI 1 "register_operand" "d")) |
9db1d521 HP |
2060 | (clobber (reg:CC 33))] |
2061 | "!TARGET_64BIT" | |
d40c829f | 2062 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2063 | [(set_attr "length" "8") |
2064 | (set_attr "type" "vs")]) | |
9db1d521 HP |
2065 | |
2066 | ; | |
358b8f01 | 2067 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2068 | ; |
2069 | ||
358b8f01 | 2070 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2071 | [(set (match_operand:SI 0 "register_operand" "") |
2072 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2073 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2074 | (use (match_operand:SI 3 "general_operand" "")) | |
2075 | (use (match_operand:SI 4 "" ""))] | |
2076 | "" | |
c7453384 | 2077 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2078 | operands[2], operands[3]); DONE;") |
9db1d521 | 2079 | |
a41c6c53 UW |
2080 | ; Compare a block that is up to 256 bytes in length. |
2081 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2082 | |
b9404c99 UW |
2083 | (define_expand "cmpmem_short" |
2084 | [(parallel | |
5b022de5 UW |
2085 | [(set (reg:CCU 33) |
2086 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
b9404c99 UW |
2087 | (match_operand:BLK 1 "memory_operand" ""))) |
2088 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2089 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2090 | (clobber (match_dup 3))])] |
2091 | "" | |
2092 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2093 | |
b9404c99 | 2094 | (define_insn "*cmpmem_short" |
5b022de5 | 2095 | [(set (reg:CCU 33) |
d4f52f0e | 2096 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") |
9bb86f41 UW |
2097 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) |
2098 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2099 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2100 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2101 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2102 | && GET_MODE (operands[4]) == Pmode" |
2103 | "#" | |
b628bd8e | 2104 | [(set_attr "type" "cs")]) |
9db1d521 | 2105 | |
9bb86f41 UW |
2106 | (define_split |
2107 | [(set (reg:CCU 33) | |
2108 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2109 | (match_operand:BLK 1 "memory_operand" ""))) | |
2110 | (use (match_operand 2 "const_int_operand" "")) | |
2111 | (use (match_operand 3 "immediate_operand" "")) | |
2112 | (clobber (scratch))] | |
2113 | "reload_completed" | |
2114 | [(parallel | |
2115 | [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2116 | (use (match_dup 2))])] | |
2117 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2118 | |
9bb86f41 UW |
2119 | (define_split |
2120 | [(set (reg:CCU 33) | |
2121 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2122 | (match_operand:BLK 1 "memory_operand" ""))) | |
2123 | (use (match_operand 2 "register_operand" "")) | |
2124 | (use (match_operand 3 "memory_operand" "")) | |
2125 | (clobber (scratch))] | |
2126 | "reload_completed" | |
2127 | [(parallel | |
2128 | [(unspec [(match_dup 2) (match_dup 3) | |
2129 | (const_int 0)] UNSPEC_EXECUTE) | |
2130 | (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2131 | (use (const_int 1))])] | |
2132 | "") | |
2133 | ||
2134 | (define_split | |
2135 | [(set (reg:CCU 33) | |
2136 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2137 | (match_operand:BLK 1 "memory_operand" ""))) | |
2138 | (use (match_operand 2 "register_operand" "")) | |
2139 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2140 | (clobber (match_operand 3 "register_operand" ""))] | |
2141 | "reload_completed && TARGET_CPU_ZARCH" | |
2142 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2143 | (parallel | |
2144 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2145 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2146 | (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2147 | (use (const_int 1))])] | |
2148 | "operands[4] = gen_label_rtx ();") | |
2149 | ||
a41c6c53 | 2150 | ; Compare a block of arbitrary length. |
9db1d521 | 2151 | |
b9404c99 UW |
2152 | (define_expand "cmpmem_long" |
2153 | [(parallel | |
2154 | [(clobber (match_dup 2)) | |
2155 | (clobber (match_dup 3)) | |
5b022de5 UW |
2156 | (set (reg:CCU 33) |
2157 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
b9404c99 UW |
2158 | (match_operand:BLK 1 "memory_operand" ""))) |
2159 | (use (match_operand 2 "general_operand" "")) | |
2160 | (use (match_dup 3))])] | |
2161 | "" | |
2162 | { | |
2163 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2164 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2165 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2166 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2167 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2168 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2169 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2170 | ||
2171 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2172 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2173 | emit_move_insn (len0, operands[2]); | |
2174 | ||
2175 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2176 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2177 | emit_move_insn (len1, operands[2]); | |
2178 | ||
2179 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2180 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2181 | operands[2] = reg0; | |
2182 | operands[3] = reg1; | |
2183 | }) | |
2184 | ||
2185 | (define_insn "*cmpmem_long_64" | |
4023fb28 UW |
2186 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2187 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
5b022de5 UW |
2188 | (set (reg:CCU 33) |
2189 | (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2190 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
2191 | (use (match_dup 2)) | |
2192 | (use (match_dup 3))] | |
9db1d521 | 2193 | "TARGET_64BIT" |
287ff198 | 2194 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2195 | [(set_attr "length" "8") |
2196 | (set_attr "type" "vs")]) | |
9db1d521 | 2197 | |
b9404c99 | 2198 | (define_insn "*cmpmem_long_31" |
4023fb28 UW |
2199 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2200 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
5b022de5 UW |
2201 | (set (reg:CCU 33) |
2202 | (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2203 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
2204 | (use (match_dup 2)) | |
2205 | (use (match_dup 3))] | |
9db1d521 | 2206 | "!TARGET_64BIT" |
287ff198 | 2207 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2208 | [(set_attr "length" "8") |
2209 | (set_attr "type" "vs")]) | |
9db1d521 | 2210 | |
02887425 UW |
2211 | ; Convert CCUmode condition code to integer. |
2212 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 2213 | |
02887425 | 2214 | (define_insn_and_split "cmpint" |
9db1d521 | 2215 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 UW |
2216 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2217 | UNSPEC_CMPINT)) | |
2218 | (clobber (reg:CC 33))] | |
9db1d521 | 2219 | "" |
02887425 UW |
2220 | "#" |
2221 | "reload_completed" | |
2222 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2223 | (parallel | |
2224 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
2225 | (clobber (reg:CC 33))])]) | |
2226 | ||
2227 | (define_insn_and_split "*cmpint_cc" | |
2228 | [(set (reg 33) | |
2229 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2230 | UNSPEC_CMPINT) | |
2231 | (const_int 0))) | |
2232 | (set (match_operand:SI 0 "register_operand" "=d") | |
2233 | (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))] | |
2234 | "s390_match_ccmode (insn, CCSmode)" | |
2235 | "#" | |
2236 | "&& reload_completed" | |
2237 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2238 | (parallel | |
2239 | [(set (match_dup 2) (match_dup 3)) | |
2240 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 2241 | { |
02887425 UW |
2242 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
2243 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2244 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2245 | }) | |
9db1d521 | 2246 | |
02887425 | 2247 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 2248 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 UW |
2249 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2250 | UNSPEC_CMPINT))) | |
2251 | (clobber (reg:CC 33))] | |
9db1d521 | 2252 | "TARGET_64BIT" |
02887425 UW |
2253 | "#" |
2254 | "&& reload_completed" | |
2255 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2256 | (parallel | |
2257 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
2258 | (clobber (reg:CC 33))])]) | |
2259 | ||
2260 | (define_insn_and_split "*cmpint_sign_cc" | |
2261 | [(set (reg 33) | |
2262 | (compare (ashiftrt:DI (ashift:DI (subreg:DI | |
2263 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2264 | UNSPEC_CMPINT) 0) | |
2265 | (const_int 32)) (const_int 32)) | |
2266 | (const_int 0))) | |
2267 | (set (match_operand:DI 0 "register_operand" "=d") | |
2268 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))] | |
2269 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" | |
2270 | "#" | |
2271 | "&& reload_completed" | |
2272 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2273 | (parallel | |
2274 | [(set (match_dup 2) (match_dup 3)) | |
2275 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 2276 | { |
02887425 UW |
2277 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
2278 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2279 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2280 | }) | |
9db1d521 | 2281 | |
4023fb28 | 2282 | |
9db1d521 HP |
2283 | ;; |
2284 | ;;- Conversion instructions. | |
2285 | ;; | |
2286 | ||
4023fb28 | 2287 | |
f52c81dd | 2288 | (define_insn "*sethigh<mode>si" |
d3632d41 | 2289 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f52c81dd | 2290 | (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2291 | (clobber (reg:CC 33))] |
2292 | "" | |
d3632d41 | 2293 | "@ |
f52c81dd AS |
2294 | icm\t%0,<icm_hi>,%S1 |
2295 | icmy\t%0,<icm_hi>,%S1" | |
d3632d41 | 2296 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2297 | |
2298 | (define_insn "*sethighqidi_64" | |
2299 | [(set (match_operand:DI 0 "register_operand" "=d") | |
10bbf137 | 2300 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2301 | (clobber (reg:CC 33))] |
2302 | "TARGET_64BIT" | |
fc0ea003 | 2303 | "icmh\t%0,8,%S1" |
d3632d41 | 2304 | [(set_attr "op_type" "RSY")]) |
4023fb28 UW |
2305 | |
2306 | (define_insn "*sethighqidi_31" | |
d3632d41 | 2307 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
10bbf137 | 2308 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2309 | (clobber (reg:CC 33))] |
2310 | "!TARGET_64BIT" | |
d3632d41 | 2311 | "@ |
fc0ea003 UW |
2312 | icm\t%0,8,%S1 |
2313 | icmy\t%0,8,%S1" | |
d3632d41 | 2314 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2315 | |
cc7ab9b7 UW |
2316 | (define_insn_and_split "*extractqi" |
2317 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2318 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2319 | (match_operand 2 "const_int_operand" "n") | |
2320 | (const_int 0))) | |
2321 | (clobber (reg:CC 33))] | |
2322 | "!TARGET_64BIT | |
4023fb28 | 2323 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
cc7ab9b7 UW |
2324 | "#" |
2325 | "&& reload_completed" | |
4023fb28 | 2326 | [(parallel |
10bbf137 | 2327 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2328 | (clobber (reg:CC 33))]) |
2329 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2330 | { |
2331 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2332 | operands[1] = change_address (operands[1], QImode, 0); | |
b628bd8e | 2333 | }) |
4023fb28 | 2334 | |
cc7ab9b7 UW |
2335 | (define_insn_and_split "*extracthi" |
2336 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2337 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2338 | (match_operand 2 "const_int_operand" "n") | |
2339 | (const_int 0))) | |
2340 | (clobber (reg:CC 33))] | |
2341 | "!TARGET_64BIT | |
4023fb28 | 2342 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
cc7ab9b7 UW |
2343 | "#" |
2344 | "&& reload_completed" | |
4023fb28 | 2345 | [(parallel |
10bbf137 | 2346 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2347 | (clobber (reg:CC 33))]) |
2348 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2349 | { |
2350 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2351 | operands[1] = change_address (operands[1], HImode, 0); | |
b628bd8e | 2352 | }) |
4023fb28 | 2353 | |
9db1d521 HP |
2354 | ; |
2355 | ; extendsidi2 instruction pattern(s). | |
2356 | ; | |
2357 | ||
4023fb28 UW |
2358 | (define_expand "extendsidi2" |
2359 | [(set (match_operand:DI 0 "register_operand" "") | |
2360 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2361 | "" | |
2362 | " | |
2363 | { | |
2364 | if (!TARGET_64BIT) | |
2365 | { | |
9f37ccb1 UW |
2366 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2367 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2368 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2369 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2370 | DONE; |
2371 | } | |
2372 | } | |
2373 | ") | |
2374 | ||
2375 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2376 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2377 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2378 | "TARGET_64BIT" | |
2379 | "@ | |
d40c829f UW |
2380 | lgfr\t%0,%1 |
2381 | lgf\t%0,%1" | |
d3632d41 | 2382 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2383 | |
9db1d521 | 2384 | ; |
f6ee577c | 2385 | ; extend(hi|qi)di2 instruction pattern(s). |
9db1d521 HP |
2386 | ; |
2387 | ||
f6ee577c | 2388 | (define_expand "extend<mode>di2" |
4023fb28 | 2389 | [(set (match_operand:DI 0 "register_operand" "") |
f6ee577c | 2390 | (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))] |
4023fb28 UW |
2391 | "" |
2392 | " | |
2393 | { | |
2394 | if (!TARGET_64BIT) | |
2395 | { | |
2396 | rtx tmp = gen_reg_rtx (SImode); | |
f6ee577c | 2397 | emit_insn (gen_extend<mode>si2 (tmp, operands[1])); |
4023fb28 UW |
2398 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
2399 | DONE; | |
2400 | } | |
2401 | else | |
2402 | { | |
f6ee577c AS |
2403 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) - |
2404 | GET_MODE_BITSIZE (<MODE>mode)); | |
4023fb28 | 2405 | operands[1] = gen_lowpart (DImode, operands[1]); |
f6ee577c AS |
2406 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); |
2407 | emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2408 | DONE; |
2409 | } | |
2410 | } | |
2411 | ") | |
2412 | ||
2413 | (define_insn "*extendhidi2" | |
9db1d521 | 2414 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2415 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2416 | "TARGET_64BIT" |
d40c829f | 2417 | "lgh\t%0,%1" |
d3632d41 | 2418 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2419 | |
d3632d41 UW |
2420 | (define_insn "*extendqidi2" |
2421 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2422 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2423 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2424 | "lgb\t%0,%1" |
d3632d41 UW |
2425 | [(set_attr "op_type" "RXY")]) |
2426 | ||
19796784 AK |
2427 | (define_insn_and_split "*extendqidi2_short_displ" |
2428 | [(set (match_operand:DI 0 "register_operand" "=d") | |
59f8a8be UW |
2429 | (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) |
2430 | (clobber (reg:CC 33))] | |
19796784 AK |
2431 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" |
2432 | "#" | |
2433 | "&& reload_completed" | |
4023fb28 | 2434 | [(parallel |
10bbf137 | 2435 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2436 | (clobber (reg:CC 33))]) |
2437 | (parallel | |
2438 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
2439 | (clobber (reg:CC 33))])] | |
2440 | "") | |
9db1d521 HP |
2441 | |
2442 | ; | |
f6ee577c | 2443 | ; extend(hi|qi)si2 instruction pattern(s). |
9db1d521 HP |
2444 | ; |
2445 | ||
f6ee577c | 2446 | (define_expand "extend<mode>si2" |
4023fb28 | 2447 | [(set (match_operand:SI 0 "register_operand" "") |
f6ee577c | 2448 | (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))] |
9db1d521 | 2449 | "" |
4023fb28 UW |
2450 | " |
2451 | { | |
f6ee577c AS |
2452 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) - |
2453 | GET_MODE_BITSIZE(<MODE>mode)); | |
4023fb28 | 2454 | operands[1] = gen_lowpart (SImode, operands[1]); |
f6ee577c AS |
2455 | emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount)); |
2456 | emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2457 | DONE; |
2458 | } | |
2459 | ") | |
9db1d521 | 2460 | |
4023fb28 | 2461 | (define_insn "*extendhisi2" |
d3632d41 UW |
2462 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2463 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
4023fb28 | 2464 | "" |
d3632d41 | 2465 | "@ |
d40c829f UW |
2466 | lh\t%0,%1 |
2467 | lhy\t%0,%1" | |
d3632d41 | 2468 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 | 2469 | |
d3632d41 UW |
2470 | (define_insn "*extendqisi2" |
2471 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2472 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2473 | "TARGET_LONG_DISPLACEMENT" |
d40c829f | 2474 | "lb\t%0,%1" |
d3632d41 UW |
2475 | [(set_attr "op_type" "RXY")]) |
2476 | ||
eb457a7a | 2477 | (define_insn_and_split "*extendqisi2_short_displ" |
19796784 | 2478 | [(set (match_operand:SI 0 "register_operand" "=d") |
59f8a8be UW |
2479 | (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) |
2480 | (clobber (reg:CC 33))] | |
19796784 AK |
2481 | "!TARGET_LONG_DISPLACEMENT" |
2482 | "#" | |
2483 | "&& reload_completed" | |
4023fb28 | 2484 | [(parallel |
10bbf137 | 2485 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2486 | (clobber (reg:CC 33))]) |
2487 | (parallel | |
2488 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
2489 | (clobber (reg:CC 33))])] | |
2490 | "") | |
9db1d521 HP |
2491 | |
2492 | ; | |
2493 | ; extendqihi2 instruction pattern(s). | |
2494 | ; | |
2495 | ||
9db1d521 HP |
2496 | |
2497 | ; | |
2498 | ; zero_extendsidi2 instruction pattern(s). | |
2499 | ; | |
2500 | ||
4023fb28 UW |
2501 | (define_expand "zero_extendsidi2" |
2502 | [(set (match_operand:DI 0 "register_operand" "") | |
2503 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2504 | "" | |
2505 | " | |
2506 | { | |
2507 | if (!TARGET_64BIT) | |
2508 | { | |
9f37ccb1 UW |
2509 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2510 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2511 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2512 | DONE; |
2513 | } | |
2514 | } | |
2515 | ") | |
2516 | ||
2517 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2518 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2519 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2520 | "TARGET_64BIT" | |
2521 | "@ | |
d40c829f UW |
2522 | llgfr\t%0,%1 |
2523 | llgf\t%0,%1" | |
d3632d41 | 2524 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2525 | |
9db1d521 | 2526 | ; |
f6ee577c | 2527 | ; zero_extend(hi|qi)di2 instruction pattern(s). |
9db1d521 HP |
2528 | ; |
2529 | ||
f6ee577c | 2530 | (define_expand "zero_extend<mode>di2" |
4023fb28 | 2531 | [(set (match_operand:DI 0 "register_operand" "") |
f6ee577c | 2532 | (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))] |
4023fb28 UW |
2533 | "" |
2534 | " | |
2535 | { | |
2536 | if (!TARGET_64BIT) | |
2537 | { | |
2538 | rtx tmp = gen_reg_rtx (SImode); | |
f6ee577c | 2539 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); |
4023fb28 UW |
2540 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); |
2541 | DONE; | |
2542 | } | |
2543 | else | |
2544 | { | |
f6ee577c AS |
2545 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - |
2546 | GET_MODE_BITSIZE(<MODE>mode)); | |
4023fb28 | 2547 | operands[1] = gen_lowpart (DImode, operands[1]); |
f6ee577c AS |
2548 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); |
2549 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2550 | DONE; |
2551 | } | |
2552 | } | |
2553 | ") | |
9db1d521 | 2554 | |
f6ee577c | 2555 | (define_insn "*zero_extend<mode>di2" |
4023fb28 | 2556 | [(set (match_operand:DI 0 "register_operand" "=d") |
f6ee577c | 2557 | (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))] |
9db1d521 | 2558 | "TARGET_64BIT" |
f6ee577c | 2559 | "llg<hc>\t%0,%1" |
d3632d41 | 2560 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2561 | |
288e517f AK |
2562 | ; |
2563 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2564 | ; | |
2565 | ||
d6083c7d UW |
2566 | (define_insn "*llgt_sidi" |
2567 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2568 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2569 | (const_int 2147483647)))] | |
2570 | "TARGET_64BIT" | |
2571 | "llgt\t%0,%1" | |
2572 | [(set_attr "op_type" "RXE")]) | |
2573 | ||
2574 | (define_insn_and_split "*llgt_sidi_split" | |
2575 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2576 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2577 | (const_int 2147483647))) | |
2578 | (clobber (reg:CC 33))] | |
2579 | "TARGET_64BIT" | |
2580 | "#" | |
2581 | "&& reload_completed" | |
2582 | [(set (match_dup 0) | |
2583 | (and:DI (subreg:DI (match_dup 1) 0) | |
2584 | (const_int 2147483647)))] | |
2585 | "") | |
2586 | ||
288e517f AK |
2587 | (define_insn "*llgt_sisi" |
2588 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2589 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2590 | (const_int 2147483647)))] | |
2591 | "TARGET_64BIT" | |
2592 | "@ | |
2593 | llgtr\t%0,%1 | |
2594 | llgt\t%0,%1" | |
2595 | [(set_attr "op_type" "RRE,RXE")]) | |
2596 | ||
288e517f AK |
2597 | (define_insn "*llgt_didi" |
2598 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2599 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2600 | (const_int 2147483647)))] | |
2601 | "TARGET_64BIT" | |
2602 | "@ | |
2603 | llgtr\t%0,%1 | |
2604 | llgt\t%0,%N1" | |
2605 | [(set_attr "op_type" "RRE,RXE")]) | |
2606 | ||
f19a9af7 | 2607 | (define_split |
f6ee577c AS |
2608 | [(set (match_operand:GPR 0 "register_operand" "") |
2609 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
2610 | (const_int 2147483647))) | |
288e517f | 2611 | (clobber (reg:CC 33))] |
f19a9af7 | 2612 | "TARGET_64BIT && reload_completed" |
288e517f | 2613 | [(set (match_dup 0) |
f6ee577c AS |
2614 | (and:GPR (match_dup 1) |
2615 | (const_int 2147483647)))] | |
288e517f AK |
2616 | "") |
2617 | ||
9db1d521 | 2618 | ; |
f6ee577c | 2619 | ; zero_extend(hi|qi)si2 instruction pattern(s). |
9db1d521 HP |
2620 | ; |
2621 | ||
f6ee577c | 2622 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 2623 | [(set (match_operand:SI 0 "register_operand" "") |
f6ee577c | 2624 | (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))] |
9db1d521 | 2625 | "" |
4023fb28 UW |
2626 | " |
2627 | { | |
2628 | operands[1] = gen_lowpart (SImode, operands[1]); | |
f6ee577c AS |
2629 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2630 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); | |
4023fb28 UW |
2631 | DONE; |
2632 | } | |
2633 | ") | |
9db1d521 | 2634 | |
f6ee577c | 2635 | (define_insn "*zero_extend<mode>si2_64" |
9db1d521 | 2636 | [(set (match_operand:SI 0 "register_operand" "=d") |
f6ee577c | 2637 | (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))] |
f4f41b4e | 2638 | "TARGET_ZARCH" |
f6ee577c | 2639 | "llg<hc>\t%0,%1" |
d3632d41 | 2640 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2641 | |
2642 | (define_insn_and_split "*zero_extendhisi2_31" | |
2643 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2644 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
cc7ab9b7 | 2645 | (clobber (reg:CC 33))] |
f4f41b4e | 2646 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2647 | "#" |
2648 | "&& reload_completed" | |
2649 | [(set (match_dup 0) (const_int 0)) | |
2650 | (parallel | |
2651 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
2652 | (clobber (reg:CC 33))])] | |
b628bd8e | 2653 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 2654 | |
cc7ab9b7 UW |
2655 | (define_insn_and_split "*zero_extendqisi2_31" |
2656 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2657 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2658 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2659 | "#" |
2660 | "&& reload_completed" | |
2661 | [(set (match_dup 0) (const_int 0)) | |
2662 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2663 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 2664 | |
9db1d521 HP |
2665 | ; |
2666 | ; zero_extendqihi2 instruction pattern(s). | |
2667 | ; | |
2668 | ||
9db1d521 HP |
2669 | (define_expand "zero_extendqihi2" |
2670 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2671 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
9e8327e3 | 2672 | "TARGET_ZARCH" |
9db1d521 HP |
2673 | " |
2674 | { | |
4023fb28 UW |
2675 | operands[1] = gen_lowpart (HImode, operands[1]); |
2676 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2677 | DONE; | |
2678 | } | |
2679 | ") | |
9db1d521 | 2680 | |
4023fb28 | 2681 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2682 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2683 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
9e8327e3 | 2684 | "TARGET_ZARCH" |
d40c829f | 2685 | "llgc\t%0,%1" |
d3632d41 | 2686 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2687 | |
cc7ab9b7 UW |
2688 | (define_insn_and_split "*zero_extendqihi2_31" |
2689 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2690 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2691 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2692 | "#" |
2693 | "&& reload_completed" | |
2694 | [(set (match_dup 0) (const_int 0)) | |
2695 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2696 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 UW |
2697 | |
2698 | ||
9db1d521 HP |
2699 | ; |
2700 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
2701 | ; | |
2702 | ||
2703 | (define_expand "fixuns_truncdfdi2" | |
2704 | [(set (match_operand:DI 0 "register_operand" "") | |
2705 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
2706 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2707 | { |
2708 | rtx label1 = gen_label_rtx (); | |
2709 | rtx label2 = gen_label_rtx (); | |
2710 | rtx temp = gen_reg_rtx (DFmode); | |
2711 | operands[1] = force_reg (DFmode, operands[1]); | |
2712 | ||
c7453384 | 2713 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2714 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2715 | REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); |
9db1d521 | 2716 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2717 | emit_insn (gen_subdf3 (temp, operands[1], |
2718 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2719 | REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); |
9db1d521 | 2720 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2721 | emit_jump (label2); |
9db1d521 HP |
2722 | |
2723 | emit_label (label1); | |
2724 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2725 | emit_label (label2); | |
2726 | DONE; | |
10bbf137 | 2727 | }) |
9db1d521 HP |
2728 | |
2729 | (define_expand "fix_truncdfdi2" | |
2730 | [(set (match_operand:DI 0 "register_operand" "") | |
2731 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2732 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2733 | { |
2734 | operands[1] = force_reg (DFmode, operands[1]); | |
2735 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2736 | DONE; | |
10bbf137 | 2737 | }) |
9db1d521 HP |
2738 | |
2739 | (define_insn "fix_truncdfdi2_ieee" | |
2740 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2741 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2742 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2743 | (clobber (reg:CC 33))] |
2744 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2745 | "cgdbr\t%0,%h2,%1" |
9db1d521 | 2746 | [(set_attr "op_type" "RRE") |
077dab3b | 2747 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2748 | |
2749 | ; | |
2750 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
2751 | ; | |
2752 | ||
2753 | (define_expand "fixuns_truncdfsi2" | |
2754 | [(set (match_operand:SI 0 "register_operand" "") | |
2755 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
2756 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2757 | { |
2758 | rtx label1 = gen_label_rtx (); | |
2759 | rtx label2 = gen_label_rtx (); | |
2760 | rtx temp = gen_reg_rtx (DFmode); | |
2761 | ||
2762 | operands[1] = force_reg (DFmode,operands[1]); | |
c7453384 | 2763 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2764 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2765 | REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); |
9db1d521 | 2766 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2767 | emit_insn (gen_subdf3 (temp, operands[1], |
2768 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2769 | REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); |
9db1d521 | 2770 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2771 | emit_jump (label2); |
9db1d521 HP |
2772 | |
2773 | emit_label (label1); | |
2774 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2775 | emit_label (label2); | |
2776 | DONE; | |
10bbf137 | 2777 | }) |
9db1d521 HP |
2778 | |
2779 | (define_expand "fix_truncdfsi2" | |
2780 | [(set (match_operand:SI 0 "register_operand" "") | |
2781 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2782 | "TARGET_HARD_FLOAT" | |
9db1d521 | 2783 | { |
c7453384 | 2784 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2785 | { |
2786 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2787 | ||
c19ec8f9 | 2788 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
2789 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2790 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
2791 | |
2792 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 2793 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 2794 | two31r, two32, temp)); |
c7453384 EC |
2795 | } |
2796 | else | |
9db1d521 HP |
2797 | { |
2798 | operands[1] = force_reg (DFmode, operands[1]); | |
2799 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2800 | } | |
2801 | ||
2802 | DONE; | |
10bbf137 | 2803 | }) |
9db1d521 HP |
2804 | |
2805 | (define_insn "fix_truncdfsi2_ieee" | |
2806 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2807 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2808 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2809 | (clobber (reg:CC 33))] |
2810 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2811 | "cfdbr\t%0,%h2,%1" |
9db1d521 | 2812 | [(set_attr "op_type" "RRE") |
a036c6f7 | 2813 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2814 | |
2815 | (define_insn "fix_truncdfsi2_ibm" | |
2816 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2817 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
2818 | (use (match_operand:DI 2 "immediate_operand" "m")) |
2819 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 HP |
2820 | (use (match_operand:BLK 4 "memory_operand" "m")) |
2821 | (clobber (reg:CC 33))] | |
2822 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 2823 | { |
d40c829f UW |
2824 | output_asm_insn ("sd\t%1,%2", operands); |
2825 | output_asm_insn ("aw\t%1,%3", operands); | |
2826 | output_asm_insn ("std\t%1,%4", operands); | |
2827 | output_asm_insn ("xi\t%N4,128", operands); | |
2828 | return "l\t%0,%N4"; | |
10bbf137 | 2829 | } |
b628bd8e | 2830 | [(set_attr "length" "20")]) |
9db1d521 HP |
2831 | |
2832 | ; | |
2833 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
2834 | ; | |
2835 | ||
2836 | (define_expand "fixuns_truncsfdi2" | |
2837 | [(set (match_operand:DI 0 "register_operand" "") | |
2838 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
2839 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2840 | { |
2841 | rtx label1 = gen_label_rtx (); | |
2842 | rtx label2 = gen_label_rtx (); | |
2843 | rtx temp = gen_reg_rtx (SFmode); | |
2844 | ||
2845 | operands[1] = force_reg (SFmode, operands[1]); | |
c7453384 | 2846 | emit_insn (gen_cmpsf (operands[1], |
4023fb28 | 2847 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2848 | REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); |
9db1d521 HP |
2849 | emit_jump_insn (gen_blt (label1)); |
2850 | ||
4023fb28 UW |
2851 | emit_insn (gen_subsf3 (temp, operands[1], |
2852 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2853 | REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); |
9db1d521 | 2854 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2855 | emit_jump (label2); |
9db1d521 HP |
2856 | |
2857 | emit_label (label1); | |
2858 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2859 | emit_label (label2); | |
2860 | DONE; | |
10bbf137 | 2861 | }) |
9db1d521 HP |
2862 | |
2863 | (define_expand "fix_truncsfdi2" | |
2864 | [(set (match_operand:DI 0 "register_operand" "") | |
2865 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2866 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2867 | { |
2868 | operands[1] = force_reg (SFmode, operands[1]); | |
2869 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2870 | DONE; | |
10bbf137 | 2871 | }) |
9db1d521 HP |
2872 | |
2873 | (define_insn "fix_truncsfdi2_ieee" | |
2874 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2875 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 2876 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2877 | (clobber (reg:CC 33))] |
2878 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2879 | "cgebr\t%0,%h2,%1" |
9db1d521 | 2880 | [(set_attr "op_type" "RRE") |
077dab3b | 2881 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2882 | |
2883 | ; | |
2884 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
2885 | ; | |
2886 | ||
2887 | (define_expand "fixuns_truncsfsi2" | |
2888 | [(set (match_operand:SI 0 "register_operand" "") | |
2889 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
2890 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2891 | { |
2892 | rtx label1 = gen_label_rtx (); | |
2893 | rtx label2 = gen_label_rtx (); | |
2894 | rtx temp = gen_reg_rtx (SFmode); | |
2895 | ||
2896 | operands[1] = force_reg (SFmode, operands[1]); | |
4023fb28 UW |
2897 | emit_insn (gen_cmpsf (operands[1], |
2898 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2899 | REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); |
9db1d521 | 2900 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2901 | emit_insn (gen_subsf3 (temp, operands[1], |
2902 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2903 | REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); |
9db1d521 | 2904 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2905 | emit_jump (label2); |
9db1d521 HP |
2906 | |
2907 | emit_label (label1); | |
2908 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2909 | emit_label (label2); | |
2910 | DONE; | |
10bbf137 | 2911 | }) |
9db1d521 HP |
2912 | |
2913 | (define_expand "fix_truncsfsi2" | |
2914 | [(set (match_operand:SI 0 "register_operand" "") | |
2915 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2916 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
2917 | { |
2918 | if (TARGET_IBM_FLOAT) | |
2919 | { | |
2920 | /* Convert to DFmode and then use the POP algorithm. */ | |
2921 | rtx temp = gen_reg_rtx (DFmode); | |
2922 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
2923 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
2924 | } | |
2925 | else | |
2926 | { | |
2927 | operands[1] = force_reg (SFmode, operands[1]); | |
2928 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2929 | } | |
2930 | ||
2931 | DONE; | |
10bbf137 | 2932 | }) |
9db1d521 HP |
2933 | |
2934 | (define_insn "fix_truncsfsi2_ieee" | |
2935 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2936 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 2937 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2938 | (clobber (reg:CC 33))] |
2939 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2940 | "cfebr\t%0,%h2,%1" |
9db1d521 | 2941 | [(set_attr "op_type" "RRE") |
077dab3b | 2942 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2943 | |
2944 | ; | |
2945 | ; floatdidf2 instruction pattern(s). | |
2946 | ; | |
2947 | ||
2948 | (define_insn "floatdidf2" | |
2949 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 2950 | (float:DF (match_operand:DI 1 "register_operand" "d")))] |
9db1d521 | 2951 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2952 | "cdgbr\t%0,%1" |
9db1d521 | 2953 | [(set_attr "op_type" "RRE") |
f0bf1270 | 2954 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2955 | |
2956 | ; | |
2957 | ; floatdisf2 instruction pattern(s). | |
2958 | ; | |
2959 | ||
2960 | (define_insn "floatdisf2" | |
2961 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 2962 | (float:SF (match_operand:DI 1 "register_operand" "d")))] |
9db1d521 | 2963 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2964 | "cegbr\t%0,%1" |
9db1d521 | 2965 | [(set_attr "op_type" "RRE") |
077dab3b | 2966 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2967 | |
2968 | ; | |
2969 | ; floatsidf2 instruction pattern(s). | |
2970 | ; | |
2971 | ||
2972 | (define_expand "floatsidf2" | |
a036c6f7 UW |
2973 | [(set (match_operand:DF 0 "register_operand" "") |
2974 | (float:DF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 2975 | "TARGET_HARD_FLOAT" |
9db1d521 | 2976 | { |
c7453384 | 2977 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2978 | { |
2979 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
2980 | ||
c19ec8f9 | 2981 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 2982 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
2983 | |
2984 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
2985 | DONE; | |
2986 | } | |
10bbf137 | 2987 | }) |
9db1d521 HP |
2988 | |
2989 | (define_insn "floatsidf2_ieee" | |
2990 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 2991 | (float:DF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 2992 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2993 | "cdfbr\t%0,%1" |
9db1d521 | 2994 | [(set_attr "op_type" "RRE") |
077dab3b | 2995 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2996 | |
2997 | (define_insn "floatsidf2_ibm" | |
2998 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2999 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3000 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 HP |
3001 | (use (match_operand:BLK 3 "memory_operand" "m")) |
3002 | (clobber (reg:CC 33))] | |
3003 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 3004 | { |
d40c829f UW |
3005 | output_asm_insn ("st\t%1,%N3", operands); |
3006 | output_asm_insn ("xi\t%N3,128", operands); | |
3007 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3008 | output_asm_insn ("ld\t%0,%3", operands); | |
3009 | return "sd\t%0,%2"; | |
10bbf137 | 3010 | } |
b628bd8e | 3011 | [(set_attr "length" "20")]) |
9db1d521 HP |
3012 | |
3013 | ; | |
3014 | ; floatsisf2 instruction pattern(s). | |
3015 | ; | |
3016 | ||
3017 | (define_expand "floatsisf2" | |
a036c6f7 UW |
3018 | [(set (match_operand:SF 0 "register_operand" "") |
3019 | (float:SF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3020 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3021 | { |
3022 | if (TARGET_IBM_FLOAT) | |
3023 | { | |
3024 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3025 | rtx temp = gen_reg_rtx (DFmode); | |
3026 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3027 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3028 | DONE; | |
3029 | } | |
10bbf137 | 3030 | }) |
9db1d521 HP |
3031 | |
3032 | (define_insn "floatsisf2_ieee" | |
3033 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3034 | (float:SF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3035 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3036 | "cefbr\t%0,%1" |
9db1d521 | 3037 | [(set_attr "op_type" "RRE") |
077dab3b | 3038 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3039 | |
3040 | ; | |
3041 | ; truncdfsf2 instruction pattern(s). | |
3042 | ; | |
3043 | ||
3044 | (define_expand "truncdfsf2" | |
3045 | [(set (match_operand:SF 0 "register_operand" "") | |
a036c6f7 | 3046 | (float_truncate:SF (match_operand:DF 1 "register_operand" "")))] |
9db1d521 | 3047 | "TARGET_HARD_FLOAT" |
4023fb28 | 3048 | "") |
9db1d521 HP |
3049 | |
3050 | (define_insn "truncdfsf2_ieee" | |
3051 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3052 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
9db1d521 | 3053 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3054 | "ledbr\t%0,%1" |
ce50cae8 | 3055 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
3056 | |
3057 | (define_insn "truncdfsf2_ibm" | |
3058 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
a036c6f7 | 3059 | (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3060 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3061 | "@ | |
a036c6f7 | 3062 | ler\t%0,%1 |
d40c829f | 3063 | le\t%0,%1" |
4023fb28 | 3064 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3065 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3066 | |
3067 | ; | |
3068 | ; extendsfdf2 instruction pattern(s). | |
3069 | ; | |
3070 | ||
3071 | (define_expand "extendsfdf2" | |
3072 | [(set (match_operand:DF 0 "register_operand" "") | |
3073 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3074 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3075 | { |
3076 | if (TARGET_IBM_FLOAT) | |
3077 | { | |
3078 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3079 | DONE; | |
3080 | } | |
10bbf137 | 3081 | }) |
9db1d521 HP |
3082 | |
3083 | (define_insn "extendsfdf2_ieee" | |
3084 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3085 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3086 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3087 | "@ | |
d40c829f UW |
3088 | ldebr\t%0,%1 |
3089 | ldeb\t%0,%1" | |
077dab3b HP |
3090 | [(set_attr "op_type" "RRE,RXE") |
3091 | (set_attr "type" "floads,floads")]) | |
9db1d521 HP |
3092 | |
3093 | (define_insn "extendsfdf2_ibm" | |
3094 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3095 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
9db1d521 HP |
3096 | (clobber (reg:CC 33))] |
3097 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3098 | "@ | |
d40c829f UW |
3099 | sdr\t%0,%0\;ler\t%0,%1 |
3100 | sdr\t%0,%0\;le\t%0,%1" | |
b628bd8e | 3101 | [(set_attr "length" "4,6") |
a036c6f7 | 3102 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3103 | |
3104 | ||
3105 | ;; | |
fae778eb | 3106 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3107 | ;; |
fae778eb | 3108 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3109 | ; because of unpredictable Bits in Register for Halfword and Byte |
3110 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3111 | ||
07893d4f UW |
3112 | ;; |
3113 | ;;- Add instructions. | |
3114 | ;; | |
3115 | ||
1c7b1b7e UW |
3116 | ; |
3117 | ; addti3 instruction pattern(s). | |
3118 | ; | |
3119 | ||
3120 | (define_insn_and_split "addti3" | |
3121 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3122 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
3123 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3124 | (clobber (reg:CC 33))] | |
3125 | "TARGET_64BIT" | |
3126 | "#" | |
3127 | "&& reload_completed" | |
3128 | [(parallel | |
3129 | [(set (reg:CCL1 33) | |
3130 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) | |
3131 | (match_dup 7))) | |
3132 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
3133 | (parallel | |
3134 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
3135 | (ltu:DI (reg:CCL1 33) (const_int 0)))) | |
3136 | (clobber (reg:CC 33))])] | |
3137 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3138 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3139 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3140 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3141 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3142 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3143 | |
07893d4f UW |
3144 | ; |
3145 | ; adddi3 instruction pattern(s). | |
3146 | ; | |
3147 | ||
07893d4f UW |
3148 | (define_insn "*adddi3_sign" |
3149 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3150 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3151 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3152 | (clobber (reg:CC 33))] | |
3153 | "TARGET_64BIT" | |
3154 | "@ | |
d40c829f UW |
3155 | agfr\t%0,%2 |
3156 | agf\t%0,%2" | |
d3632d41 | 3157 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3158 | |
3159 | (define_insn "*adddi3_zero_cc" | |
c7453384 | 3160 | [(set (reg 33) |
07893d4f UW |
3161 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3162 | (match_operand:DI 1 "register_operand" "0,0")) | |
3163 | (const_int 0))) | |
3164 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3165 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3166 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3167 | "@ | |
d40c829f UW |
3168 | algfr\t%0,%2 |
3169 | algf\t%0,%2" | |
d3632d41 | 3170 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3171 | |
3172 | (define_insn "*adddi3_zero_cconly" | |
c7453384 | 3173 | [(set (reg 33) |
07893d4f UW |
3174 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3175 | (match_operand:DI 1 "register_operand" "0,0")) | |
3176 | (const_int 0))) | |
3177 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3178 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3179 | "@ | |
d40c829f UW |
3180 | algfr\t%0,%2 |
3181 | algf\t%0,%2" | |
d3632d41 | 3182 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3183 | |
3184 | (define_insn "*adddi3_zero" | |
3185 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3186 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3187 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3188 | (clobber (reg:CC 33))] | |
3189 | "TARGET_64BIT" | |
3190 | "@ | |
d40c829f UW |
3191 | algfr\t%0,%2 |
3192 | algf\t%0,%2" | |
d3632d41 | 3193 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3194 | |
0a3bdf9d | 3195 | (define_insn "*adddi3_imm_cc" |
c7453384 | 3196 | [(set (reg 33) |
0a3bdf9d UW |
3197 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
3198 | (match_operand:DI 2 "const_int_operand" "K")) | |
3199 | (const_int 0))) | |
3200 | (set (match_operand:DI 0 "register_operand" "=d") | |
3201 | (plus:DI (match_dup 1) (match_dup 2)))] | |
c7453384 EC |
3202 | "TARGET_64BIT |
3203 | && s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3204 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3205 | "aghi\t%0,%h2" |
077dab3b | 3206 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3207 | |
b2ba71ca UW |
3208 | (define_insn "*adddi3_carry1_cc" |
3209 | [(set (reg 33) | |
3210 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3211 | (match_operand:DI 2 "general_operand" "d,m")) | |
3212 | (match_dup 1))) | |
3213 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3214 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3215 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3216 | "@ | |
3217 | algr\t%0,%2 | |
3218 | alg\t%0,%2" | |
3219 | [(set_attr "op_type" "RRE,RXY")]) | |
3220 | ||
3221 | (define_insn "*adddi3_carry1_cconly" | |
3222 | [(set (reg 33) | |
3223 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3224 | (match_operand:DI 2 "general_operand" "d,m")) | |
3225 | (match_dup 1))) | |
3226 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3227 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3228 | "@ | |
3229 | algr\t%0,%2 | |
3230 | alg\t%0,%2" | |
3231 | [(set_attr "op_type" "RRE,RXY")]) | |
3232 | ||
3233 | (define_insn "*adddi3_carry2_cc" | |
3234 | [(set (reg 33) | |
3235 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3236 | (match_operand:DI 2 "general_operand" "d,m")) | |
3237 | (match_dup 2))) | |
3238 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3239 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3240 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3241 | "@ | |
3242 | algr\t%0,%2 | |
3243 | alg\t%0,%2" | |
3244 | [(set_attr "op_type" "RRE,RXY")]) | |
3245 | ||
3246 | (define_insn "*adddi3_carry2_cconly" | |
3247 | [(set (reg 33) | |
3248 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3249 | (match_operand:DI 2 "general_operand" "d,m")) | |
3250 | (match_dup 2))) | |
3251 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3252 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3253 | "@ | |
3254 | algr\t%0,%2 | |
3255 | alg\t%0,%2" | |
3256 | [(set_attr "op_type" "RRE,RXY")]) | |
3257 | ||
07893d4f | 3258 | (define_insn "*adddi3_cc" |
c7453384 | 3259 | [(set (reg 33) |
96fd3851 | 3260 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3261 | (match_operand:DI 2 "general_operand" "d,m")) |
3262 | (const_int 0))) | |
3263 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3264 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3265 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3266 | "@ | |
d40c829f UW |
3267 | algr\t%0,%2 |
3268 | alg\t%0,%2" | |
d3632d41 | 3269 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3270 | |
07893d4f | 3271 | (define_insn "*adddi3_cconly" |
c7453384 | 3272 | [(set (reg 33) |
96fd3851 | 3273 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3274 | (match_operand:DI 2 "general_operand" "d,m")) |
3275 | (const_int 0))) | |
3276 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3277 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3278 | "@ | |
d40c829f UW |
3279 | algr\t%0,%2 |
3280 | alg\t%0,%2" | |
d3632d41 | 3281 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3282 | |
07893d4f | 3283 | (define_insn "*adddi3_cconly2" |
c7453384 | 3284 | [(set (reg 33) |
96fd3851 | 3285 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3286 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3287 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3288 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3289 | "@ |
d40c829f UW |
3290 | algr\t%0,%2 |
3291 | alg\t%0,%2" | |
d3632d41 | 3292 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3293 | |
07893d4f | 3294 | (define_insn "*adddi3_64" |
9db1d521 | 3295 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3296 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
9db1d521 HP |
3297 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
3298 | (clobber (reg:CC 33))] | |
3299 | "TARGET_64BIT" | |
3300 | "@ | |
d40c829f UW |
3301 | agr\t%0,%2 |
3302 | aghi\t%0,%h2 | |
3303 | ag\t%0,%2" | |
d3632d41 | 3304 | [(set_attr "op_type" "RRE,RI,RXY")]) |
9db1d521 | 3305 | |
e69166de UW |
3306 | (define_insn_and_split "*adddi3_31z" |
3307 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3308 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3309 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3310 | (clobber (reg:CC 33))] | |
3311 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3312 | "#" | |
3313 | "&& reload_completed" | |
3314 | [(parallel | |
3315 | [(set (reg:CCL1 33) | |
3316 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3317 | (match_dup 7))) | |
3318 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3319 | (parallel | |
3320 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
3321 | (ltu:SI (reg:CCL1 33) (const_int 0)))) | |
3322 | (clobber (reg:CC 33))])] | |
3323 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3324 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3325 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3326 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3327 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3328 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3329 | |
07893d4f UW |
3330 | (define_insn_and_split "*adddi3_31" |
3331 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3332 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3333 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3334 | (clobber (reg:CC 33))] |
e69166de | 3335 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3336 | "#" |
3337 | "&& reload_completed" | |
3338 | [(parallel | |
3339 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
3340 | (clobber (reg:CC 33))]) | |
3341 | (parallel | |
3342 | [(set (reg:CCL1 33) | |
3343 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3344 | (match_dup 7))) | |
3345 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3346 | (set (pc) | |
3347 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
3348 | (pc) | |
3349 | (label_ref (match_dup 9)))) | |
3350 | (parallel | |
3351 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
3352 | (clobber (reg:CC 33))]) | |
3353 | (match_dup 9)] | |
97c6f7ad UW |
3354 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3355 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3356 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3357 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3358 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3359 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3360 | operands[9] = gen_label_rtx ();") |
9db1d521 HP |
3361 | |
3362 | (define_expand "adddi3" | |
07893d4f UW |
3363 | [(parallel |
3364 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3365 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f UW |
3366 | (match_operand:DI 2 "general_operand" ""))) |
3367 | (clobber (reg:CC 33))])] | |
9db1d521 | 3368 | "" |
07893d4f | 3369 | "") |
9db1d521 | 3370 | |
9db1d521 HP |
3371 | ; |
3372 | ; addsi3 instruction pattern(s). | |
3373 | ; | |
9db1d521 | 3374 | |
0a3bdf9d | 3375 | (define_insn "*addsi3_imm_cc" |
c7453384 | 3376 | [(set (reg 33) |
0a3bdf9d UW |
3377 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3378 | (match_operand:SI 2 "const_int_operand" "K")) | |
3379 | (const_int 0))) | |
3380 | (set (match_operand:SI 0 "register_operand" "=d") | |
3381 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3382 | "s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3383 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3384 | "ahi\t%0,%h2" |
077dab3b | 3385 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3386 | |
07893d4f | 3387 | (define_insn "*addsi3_carry1_cc" |
c7453384 | 3388 | [(set (reg 33) |
d3632d41 UW |
3389 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3390 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3391 | (match_dup 1))) |
d3632d41 | 3392 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3393 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3394 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3395 | "@ |
d40c829f UW |
3396 | alr\t%0,%2 |
3397 | al\t%0,%2 | |
3398 | aly\t%0,%2" | |
d3632d41 | 3399 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3400 | |
3401 | (define_insn "*addsi3_carry1_cconly" | |
c7453384 | 3402 | [(set (reg 33) |
d3632d41 UW |
3403 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3404 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3405 | (match_dup 1))) |
d3632d41 | 3406 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3407 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3408 | "@ |
d40c829f UW |
3409 | alr\t%0,%2 |
3410 | al\t%0,%2 | |
3411 | aly\t%0,%2" | |
d3632d41 | 3412 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3413 | |
3414 | (define_insn "*addsi3_carry2_cc" | |
c7453384 | 3415 | [(set (reg 33) |
d3632d41 UW |
3416 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3417 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3418 | (match_dup 2))) |
d3632d41 | 3419 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3420 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3421 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3422 | "@ |
d40c829f UW |
3423 | alr\t%0,%2 |
3424 | al\t%0,%2 | |
3425 | aly\t%0,%2" | |
d3632d41 | 3426 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3427 | |
3428 | (define_insn "*addsi3_carry2_cconly" | |
c7453384 | 3429 | [(set (reg 33) |
d3632d41 UW |
3430 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3431 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3432 | (match_dup 2))) |
d3632d41 | 3433 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3434 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3435 | "@ |
d40c829f UW |
3436 | alr\t%0,%2 |
3437 | al\t%0,%2 | |
3438 | aly\t%0,%2" | |
d3632d41 | 3439 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3440 | |
9db1d521 | 3441 | (define_insn "*addsi3_cc" |
c7453384 | 3442 | [(set (reg 33) |
d3632d41 UW |
3443 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3444 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3445 | (const_int 0))) |
d3632d41 | 3446 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3447 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3448 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3449 | "@ |
d40c829f UW |
3450 | alr\t%0,%2 |
3451 | al\t%0,%2 | |
3452 | aly\t%0,%2" | |
d3632d41 | 3453 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3454 | |
3455 | (define_insn "*addsi3_cconly" | |
c7453384 | 3456 | [(set (reg 33) |
d3632d41 UW |
3457 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3458 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3459 | (const_int 0))) |
d3632d41 | 3460 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3461 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3462 | "@ |
d40c829f UW |
3463 | alr\t%0,%2 |
3464 | al\t%0,%2 | |
3465 | aly\t%0,%2" | |
d3632d41 | 3466 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3467 | |
3468 | (define_insn "*addsi3_cconly2" | |
c7453384 | 3469 | [(set (reg 33) |
d3632d41 UW |
3470 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3471 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3472 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3473 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3474 | "@ |
d40c829f UW |
3475 | alr\t%0,%2 |
3476 | al\t%0,%2 | |
3477 | aly\t%0,%2" | |
d3632d41 | 3478 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3479 | |
07893d4f | 3480 | (define_insn "*addsi3_sign" |
d3632d41 | 3481 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f0ad121f UW |
3482 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) |
3483 | (match_operand:SI 1 "register_operand" "0,0"))) | |
07893d4f UW |
3484 | (clobber (reg:CC 33))] |
3485 | "" | |
d3632d41 | 3486 | "@ |
d40c829f UW |
3487 | ah\t%0,%2 |
3488 | ahy\t%0,%2" | |
d3632d41 | 3489 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3490 | |
9db1d521 | 3491 | (define_insn "addsi3" |
d3632d41 UW |
3492 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3493 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3494 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
9db1d521 HP |
3495 | (clobber (reg:CC 33))] |
3496 | "" | |
3497 | "@ | |
d40c829f UW |
3498 | ar\t%0,%2 |
3499 | ahi\t%0,%h2 | |
3500 | a\t%0,%2 | |
3501 | ay\t%0,%2" | |
d3632d41 | 3502 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
9db1d521 | 3503 | |
9db1d521 HP |
3504 | ; |
3505 | ; adddf3 instruction pattern(s). | |
3506 | ; | |
3507 | ||
3508 | (define_expand "adddf3" | |
3509 | [(parallel | |
3510 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3511 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3512 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3513 | (clobber (reg:CC 33))])] |
3514 | "TARGET_HARD_FLOAT" | |
3515 | "") | |
3516 | ||
3517 | (define_insn "*adddf3" | |
3518 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3519 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3520 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3521 | (clobber (reg:CC 33))] |
3522 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3523 | "@ | |
d40c829f UW |
3524 | adbr\t%0,%2 |
3525 | adb\t%0,%2" | |
ce50cae8 | 3526 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3527 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3528 | |
3ef093a8 AK |
3529 | (define_insn "*adddf3_cc" |
3530 | [(set (reg 33) | |
3531 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3532 | (match_operand:DF 2 "general_operand" "f,R")) | |
3533 | (match_operand:DF 3 "const0_operand" ""))) | |
3534 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
3535 | (plus:DF (match_dup 1) (match_dup 2)))] | |
3536 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3537 | "@ | |
d40c829f UW |
3538 | adbr\t%0,%2 |
3539 | adb\t%0,%2" | |
3ef093a8 AK |
3540 | [(set_attr "op_type" "RRE,RXE") |
3541 | (set_attr "type" "fsimpd,fsimpd")]) | |
3542 | ||
3543 | (define_insn "*adddf3_cconly" | |
3544 | [(set (reg 33) | |
3545 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3546 | (match_operand:DF 2 "general_operand" "f,R")) | |
3547 | (match_operand:DF 3 "const0_operand" ""))) | |
3548 | (clobber (match_scratch:DF 0 "=f,f"))] | |
3549 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3550 | "@ | |
d40c829f UW |
3551 | adbr\t%0,%2 |
3552 | adb\t%0,%2" | |
3ef093a8 AK |
3553 | [(set_attr "op_type" "RRE,RXE") |
3554 | (set_attr "type" "fsimpd,fsimpd")]) | |
3555 | ||
9db1d521 HP |
3556 | (define_insn "*adddf3_ibm" |
3557 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3558 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3559 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3560 | (clobber (reg:CC 33))] |
3561 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3562 | "@ | |
d40c829f UW |
3563 | adr\t%0,%2 |
3564 | ad\t%0,%2" | |
9db1d521 | 3565 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3566 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
3567 | |
3568 | ; | |
3569 | ; addsf3 instruction pattern(s). | |
3570 | ; | |
3571 | ||
3572 | (define_expand "addsf3" | |
3573 | [(parallel | |
3574 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3575 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3576 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3577 | (clobber (reg:CC 33))])] |
3578 | "TARGET_HARD_FLOAT" | |
3579 | "") | |
3580 | ||
3581 | (define_insn "*addsf3" | |
3582 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3583 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3584 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3585 | (clobber (reg:CC 33))] |
3586 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3587 | "@ | |
d40c829f UW |
3588 | aebr\t%0,%2 |
3589 | aeb\t%0,%2" | |
ce50cae8 | 3590 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3591 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 3592 | |
3ef093a8 AK |
3593 | (define_insn "*addsf3_cc" |
3594 | [(set (reg 33) | |
3595 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3596 | (match_operand:SF 2 "general_operand" "f,R")) | |
3597 | (match_operand:SF 3 "const0_operand" ""))) | |
3598 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
3599 | (plus:SF (match_dup 1) (match_dup 2)))] | |
3600 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3601 | "@ | |
d40c829f UW |
3602 | aebr\t%0,%2 |
3603 | aeb\t%0,%2" | |
3ef093a8 AK |
3604 | [(set_attr "op_type" "RRE,RXE") |
3605 | (set_attr "type" "fsimps,fsimps")]) | |
3606 | ||
3607 | (define_insn "*addsf3_cconly" | |
3608 | [(set (reg 33) | |
3609 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3610 | (match_operand:SF 2 "general_operand" "f,R")) | |
3611 | (match_operand:SF 3 "const0_operand" ""))) | |
3612 | (clobber (match_scratch:SF 0 "=f,f"))] | |
3613 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3614 | "@ | |
d40c829f UW |
3615 | aebr\t%0,%2 |
3616 | aeb\t%0,%2" | |
3ef093a8 AK |
3617 | [(set_attr "op_type" "RRE,RXE") |
3618 | (set_attr "type" "fsimps,fsimps")]) | |
3619 | ||
9db1d521 HP |
3620 | (define_insn "*addsf3" |
3621 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3622 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3623 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3624 | (clobber (reg:CC 33))] |
3625 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3626 | "@ | |
d40c829f UW |
3627 | aer\t%0,%2 |
3628 | ae\t%0,%2" | |
9db1d521 | 3629 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3630 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
3631 | |
3632 | ||
3633 | ;; | |
3634 | ;;- Subtract instructions. | |
3635 | ;; | |
3636 | ||
1c7b1b7e UW |
3637 | ; |
3638 | ; subti3 instruction pattern(s). | |
3639 | ; | |
3640 | ||
3641 | (define_insn_and_split "subti3" | |
3642 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3643 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3644 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3645 | (clobber (reg:CC 33))] | |
3646 | "TARGET_64BIT" | |
3647 | "#" | |
3648 | "&& reload_completed" | |
3649 | [(parallel | |
3650 | [(set (reg:CCL2 33) | |
3651 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) | |
3652 | (match_dup 7))) | |
3653 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3654 | (parallel | |
3655 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
3656 | (gtu:DI (reg:CCL2 33) (const_int 0)))) | |
3657 | (clobber (reg:CC 33))])] | |
3658 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3659 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3660 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3661 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3662 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3663 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3664 | |
9db1d521 HP |
3665 | ; |
3666 | ; subdi3 instruction pattern(s). | |
3667 | ; | |
3668 | ||
07893d4f UW |
3669 | (define_insn "*subdi3_sign" |
3670 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3671 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3672 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3673 | (clobber (reg:CC 33))] | |
3674 | "TARGET_64BIT" | |
3675 | "@ | |
d40c829f UW |
3676 | sgfr\t%0,%2 |
3677 | sgf\t%0,%2" | |
d3632d41 | 3678 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3679 | |
3680 | (define_insn "*subdi3_zero_cc" | |
c7453384 | 3681 | [(set (reg 33) |
07893d4f UW |
3682 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3683 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3684 | (const_int 0))) | |
3685 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3686 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3687 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3688 | "@ | |
d40c829f UW |
3689 | slgfr\t%0,%2 |
3690 | slgf\t%0,%2" | |
d3632d41 | 3691 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3692 | |
3693 | (define_insn "*subdi3_zero_cconly" | |
c7453384 | 3694 | [(set (reg 33) |
07893d4f UW |
3695 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3696 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3697 | (const_int 0))) | |
3698 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3699 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3700 | "@ | |
d40c829f UW |
3701 | slgfr\t%0,%2 |
3702 | slgf\t%0,%2" | |
d3632d41 | 3703 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3704 | |
3705 | (define_insn "*subdi3_zero" | |
3706 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3707 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3708 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3709 | (clobber (reg:CC 33))] | |
3710 | "TARGET_64BIT" | |
3711 | "@ | |
d40c829f UW |
3712 | slgfr\t%0,%2 |
3713 | slgf\t%0,%2" | |
d3632d41 | 3714 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3715 | |
b2ba71ca UW |
3716 | (define_insn "*subdi3_borrow_cc" |
3717 | [(set (reg 33) | |
3718 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3719 | (match_operand:DI 2 "general_operand" "d,m")) | |
3720 | (match_dup 1))) | |
3721 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3722 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3723 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3724 | "@ | |
3725 | slgr\t%0,%2 | |
3726 | slg\t%0,%2" | |
3727 | [(set_attr "op_type" "RRE,RXY")]) | |
3728 | ||
3729 | (define_insn "*subdi3_borrow_cconly" | |
3730 | [(set (reg 33) | |
3731 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3732 | (match_operand:DI 2 "general_operand" "d,m")) | |
3733 | (match_dup 1))) | |
3734 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3735 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3736 | "@ | |
3737 | slgr\t%0,%2 | |
3738 | slg\t%0,%2" | |
3739 | [(set_attr "op_type" "RRE,RXY")]) | |
3740 | ||
07893d4f UW |
3741 | (define_insn "*subdi3_cc" |
3742 | [(set (reg 33) | |
3743 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3744 | (match_operand:DI 2 "general_operand" "d,m")) | |
3745 | (const_int 0))) | |
3746 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3747 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3748 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3749 | "@ |
d40c829f UW |
3750 | slgr\t%0,%2 |
3751 | slg\t%0,%2" | |
d3632d41 | 3752 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3753 | |
5d880bd2 UW |
3754 | (define_insn "*subdi3_cc2" |
3755 | [(set (reg 33) | |
3756 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
3757 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3758 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3759 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3760 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3761 | "@ | |
3762 | slgr\t%0,%2 | |
3763 | slg\t%0,%2" | |
3764 | [(set_attr "op_type" "RRE,RXY")]) | |
3765 | ||
07893d4f UW |
3766 | (define_insn "*subdi3_cconly" |
3767 | [(set (reg 33) | |
3768 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3769 | (match_operand:DI 2 "general_operand" "d,m")) | |
3770 | (const_int 0))) | |
3771 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3772 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3773 | "@ |
d40c829f UW |
3774 | slgr\t%0,%2 |
3775 | slg\t%0,%2" | |
d3632d41 | 3776 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3777 | |
5d880bd2 UW |
3778 | (define_insn "*subdi3_cconly2" |
3779 | [(set (reg 33) | |
3780 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
3781 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3782 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3783 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3784 | "@ | |
3785 | slgr\t%0,%2 | |
3786 | slg\t%0,%2" | |
3787 | [(set_attr "op_type" "RRE,RXY")]) | |
3788 | ||
9db1d521 HP |
3789 | (define_insn "*subdi3_64" |
3790 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3791 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3792 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
3793 | (clobber (reg:CC 33))] | |
3794 | "TARGET_64BIT" | |
3795 | "@ | |
d40c829f UW |
3796 | sgr\t%0,%2 |
3797 | sg\t%0,%2" | |
077dab3b | 3798 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3799 | |
e69166de UW |
3800 | (define_insn_and_split "*subdi3_31z" |
3801 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3802 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3803 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3804 | (clobber (reg:CC 33))] | |
3805 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3806 | "#" | |
3807 | "&& reload_completed" | |
3808 | [(parallel | |
3809 | [(set (reg:CCL2 33) | |
3810 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3811 | (match_dup 7))) | |
3812 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3813 | (parallel | |
3814 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
3815 | (gtu:SI (reg:CCL2 33) (const_int 0)))) | |
3816 | (clobber (reg:CC 33))])] | |
3817 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3818 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3819 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3820 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3821 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3822 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3823 | |
07893d4f UW |
3824 | (define_insn_and_split "*subdi3_31" |
3825 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3826 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3827 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3828 | (clobber (reg:CC 33))] |
e69166de | 3829 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3830 | "#" |
3831 | "&& reload_completed" | |
3832 | [(parallel | |
3833 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
3834 | (clobber (reg:CC 33))]) | |
3835 | (parallel | |
3836 | [(set (reg:CCL2 33) | |
3837 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3838 | (match_dup 7))) | |
3839 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3840 | (set (pc) | |
3841 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
3842 | (pc) | |
3843 | (label_ref (match_dup 9)))) | |
3844 | (parallel | |
3845 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
3846 | (clobber (reg:CC 33))]) | |
3847 | (match_dup 9)] | |
97c6f7ad UW |
3848 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3849 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3850 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3851 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3852 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3853 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3854 | operands[9] = gen_label_rtx ();") |
07893d4f UW |
3855 | |
3856 | (define_expand "subdi3" | |
3857 | [(parallel | |
3858 | [(set (match_operand:DI 0 "register_operand" "") | |
3859 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3860 | (match_operand:DI 2 "general_operand" ""))) | |
3861 | (clobber (reg:CC 33))])] | |
9db1d521 | 3862 | "" |
07893d4f | 3863 | "") |
9db1d521 HP |
3864 | |
3865 | ; | |
3866 | ; subsi3 instruction pattern(s). | |
3867 | ; | |
3868 | ||
07893d4f UW |
3869 | (define_insn "*subsi3_borrow_cc" |
3870 | [(set (reg 33) | |
d3632d41 UW |
3871 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3872 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3873 | (match_dup 1))) |
d3632d41 | 3874 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3875 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3876 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3877 | "@ |
d40c829f UW |
3878 | slr\t%0,%2 |
3879 | sl\t%0,%2 | |
3880 | sly\t%0,%2" | |
d3632d41 | 3881 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3882 | |
3883 | (define_insn "*subsi3_borrow_cconly" | |
3884 | [(set (reg 33) | |
d3632d41 UW |
3885 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3886 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3887 | (match_dup 1))) |
d3632d41 | 3888 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 3889 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3890 | "@ |
d40c829f UW |
3891 | slr\t%0,%2 |
3892 | sl\t%0,%2 | |
3893 | sly\t%0,%2" | |
b2ba71ca | 3894 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3895 | |
9db1d521 HP |
3896 | (define_insn "*subsi3_cc" |
3897 | [(set (reg 33) | |
d3632d41 UW |
3898 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3899 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3900 | (const_int 0))) |
d3632d41 | 3901 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3902 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3903 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3904 | "@ |
d40c829f UW |
3905 | slr\t%0,%2 |
3906 | sl\t%0,%2 | |
3907 | sly\t%0,%2" | |
d3632d41 | 3908 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3909 | |
5d880bd2 UW |
3910 | (define_insn "*subsi3_cc2" |
3911 | [(set (reg 33) | |
3912 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
3913 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
3914 | (set (match_operand:SI 0 "register_operand" "=d,d,d") | |
3915 | (minus:SI (match_dup 1) (match_dup 2)))] | |
3916 | "s390_match_ccmode (insn, CCL3mode)" | |
3917 | "@ | |
3918 | slr\t%0,%2 | |
3919 | sl\t%0,%2 | |
3920 | sly\t%0,%2" | |
3921 | [(set_attr "op_type" "RR,RX,RXY")]) | |
3922 | ||
9db1d521 HP |
3923 | (define_insn "*subsi3_cconly" |
3924 | [(set (reg 33) | |
d3632d41 UW |
3925 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3926 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3927 | (const_int 0))) |
d3632d41 | 3928 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 3929 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3930 | "@ |
d40c829f UW |
3931 | slr\t%0,%2 |
3932 | sl\t%0,%2 | |
3933 | sly\t%0,%2" | |
d3632d41 | 3934 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3935 | |
5d880bd2 UW |
3936 | (define_insn "*subsi3_cconly2" |
3937 | [(set (reg 33) | |
3938 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
3939 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
3940 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
3941 | "s390_match_ccmode (insn, CCL3mode)" | |
3942 | "@ | |
3943 | slr\t%0,%2 | |
3944 | sl\t%0,%2 | |
3945 | sly\t%0,%2" | |
3946 | [(set_attr "op_type" "RR,RX,RXY")]) | |
3947 | ||
07893d4f | 3948 | (define_insn "*subsi3_sign" |
d3632d41 UW |
3949 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3950 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3951 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
3952 | (clobber (reg:CC 33))] |
3953 | "" | |
d3632d41 | 3954 | "@ |
d40c829f UW |
3955 | sh\t%0,%2 |
3956 | shy\t%0,%2" | |
d3632d41 | 3957 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3958 | |
9db1d521 | 3959 | (define_insn "subsi3" |
d3632d41 UW |
3960 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
3961 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
3962 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
3963 | (clobber (reg:CC 33))] |
3964 | "" | |
3965 | "@ | |
d40c829f UW |
3966 | sr\t%0,%2 |
3967 | s\t%0,%2 | |
3968 | sy\t%0,%2" | |
d3632d41 | 3969 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3970 | |
9db1d521 HP |
3971 | |
3972 | ; | |
3973 | ; subdf3 instruction pattern(s). | |
3974 | ; | |
3975 | ||
3976 | (define_expand "subdf3" | |
3977 | [(parallel | |
3978 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
3979 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 3980 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3981 | (clobber (reg:CC 33))])] |
3982 | "TARGET_HARD_FLOAT" | |
3983 | "") | |
3984 | ||
3985 | (define_insn "*subdf3" | |
3986 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
3987 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 3988 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3989 | (clobber (reg:CC 33))] |
3990 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3991 | "@ | |
d40c829f UW |
3992 | sdbr\t%0,%2 |
3993 | sdb\t%0,%2" | |
ce50cae8 | 3994 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3995 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3996 | |
3ef093a8 AK |
3997 | (define_insn "*subdf3_cc" |
3998 | [(set (reg 33) | |
4dbb5970 | 3999 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4000 | (match_operand:DF 2 "general_operand" "f,R")) |
4001 | (match_operand:DF 3 "const0_operand" ""))) | |
4002 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
db09b5b6 | 4003 | (minus:DF (match_dup 1) (match_dup 2)))] |
3ef093a8 AK |
4004 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4005 | "@ | |
d40c829f UW |
4006 | sdbr\t%0,%2 |
4007 | sdb\t%0,%2" | |
3ef093a8 AK |
4008 | [(set_attr "op_type" "RRE,RXE") |
4009 | (set_attr "type" "fsimpd,fsimpd")]) | |
4010 | ||
4011 | (define_insn "*subdf3_cconly" | |
4012 | [(set (reg 33) | |
4dbb5970 | 4013 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4014 | (match_operand:DF 2 "general_operand" "f,R")) |
4015 | (match_operand:DF 3 "const0_operand" ""))) | |
4016 | (clobber (match_scratch:DF 0 "=f,f"))] | |
4017 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4018 | "@ | |
d40c829f UW |
4019 | sdbr\t%0,%2 |
4020 | sdb\t%0,%2" | |
3ef093a8 AK |
4021 | [(set_attr "op_type" "RRE,RXE") |
4022 | (set_attr "type" "fsimpd,fsimpd")]) | |
4023 | ||
9db1d521 HP |
4024 | (define_insn "*subdf3_ibm" |
4025 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4026 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4027 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4028 | (clobber (reg:CC 33))] |
4029 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4030 | "@ | |
d40c829f UW |
4031 | sdr\t%0,%2 |
4032 | sd\t%0,%2" | |
9db1d521 | 4033 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4034 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
4035 | |
4036 | ; | |
4037 | ; subsf3 instruction pattern(s). | |
4038 | ; | |
4039 | ||
4040 | (define_expand "subsf3" | |
4041 | [(parallel | |
4042 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4043 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4044 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4045 | (clobber (reg:CC 33))])] |
4046 | "TARGET_HARD_FLOAT" | |
4047 | "") | |
4048 | ||
4049 | (define_insn "*subsf3" | |
4050 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4051 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4052 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4053 | (clobber (reg:CC 33))] |
4054 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4055 | "@ | |
d40c829f UW |
4056 | sebr\t%0,%2 |
4057 | seb\t%0,%2" | |
ce50cae8 | 4058 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4059 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 4060 | |
3ef093a8 AK |
4061 | (define_insn "*subsf3_cc" |
4062 | [(set (reg 33) | |
4dbb5970 | 4063 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4064 | (match_operand:SF 2 "general_operand" "f,R")) |
4065 | (match_operand:SF 3 "const0_operand" ""))) | |
4066 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
4067 | (minus:SF (match_dup 1) (match_dup 2)))] | |
4068 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4069 | "@ | |
d40c829f UW |
4070 | sebr\t%0,%2 |
4071 | seb\t%0,%2" | |
3ef093a8 AK |
4072 | [(set_attr "op_type" "RRE,RXE") |
4073 | (set_attr "type" "fsimps,fsimps")]) | |
4074 | ||
4075 | (define_insn "*subsf3_cconly" | |
4076 | [(set (reg 33) | |
4dbb5970 | 4077 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4078 | (match_operand:SF 2 "general_operand" "f,R")) |
4079 | (match_operand:SF 3 "const0_operand" ""))) | |
4080 | (clobber (match_scratch:SF 0 "=f,f"))] | |
4081 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4082 | "@ | |
d40c829f UW |
4083 | sebr\t%0,%2 |
4084 | seb\t%0,%2" | |
3ef093a8 AK |
4085 | [(set_attr "op_type" "RRE,RXE") |
4086 | (set_attr "type" "fsimps,fsimps")]) | |
4087 | ||
9db1d521 HP |
4088 | (define_insn "*subsf3_ibm" |
4089 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4090 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4091 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4092 | (clobber (reg:CC 33))] |
4093 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4094 | "@ | |
d40c829f UW |
4095 | ser\t%0,%2 |
4096 | se\t%0,%2" | |
9db1d521 | 4097 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4098 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
4099 | |
4100 | ||
e69166de UW |
4101 | ;; |
4102 | ;;- Conditional add/subtract instructions. | |
4103 | ;; | |
4104 | ||
4105 | ; | |
9a91a21f | 4106 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
4107 | ; |
4108 | ||
9a91a21f | 4109 | (define_insn "*add<mode>3_alc_cc" |
2f7e5a0d | 4110 | [(set (reg 33) |
e69166de | 4111 | (compare |
9a91a21f AS |
4112 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") |
4113 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4114 | (match_operand:GPR 3 "s390_alc_comparison" "")) | |
e69166de | 4115 | (const_int 0))) |
9a91a21f AS |
4116 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
4117 | (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4118 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4119 | "@ |
9a91a21f AS |
4120 | alc<g>r\t%0,%2 |
4121 | alc<g>\t%0,%2" | |
e69166de UW |
4122 | [(set_attr "op_type" "RRE,RXY")]) |
4123 | ||
9a91a21f AS |
4124 | (define_insn "*add<mode>3_alc" |
4125 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
4126 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") | |
4127 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4128 | (match_operand:GPR 3 "s390_alc_comparison" ""))) | |
e69166de | 4129 | (clobber (reg:CC 33))] |
2f7e5a0d | 4130 | "TARGET_CPU_ZARCH" |
e69166de | 4131 | "@ |
9a91a21f AS |
4132 | alc<g>r\t%0,%2 |
4133 | alc<g>\t%0,%2" | |
e69166de UW |
4134 | [(set_attr "op_type" "RRE,RXY")]) |
4135 | ||
9a91a21f | 4136 | (define_insn "*sub<mode>3_slb_cc" |
2f7e5a0d | 4137 | [(set (reg 33) |
e69166de | 4138 | (compare |
9a91a21f AS |
4139 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
4140 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4141 | (match_operand:GPR 3 "s390_slb_comparison" "")) | |
e69166de | 4142 | (const_int 0))) |
9a91a21f AS |
4143 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
4144 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4145 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4146 | "@ |
9a91a21f AS |
4147 | slb<g>r\t%0,%2 |
4148 | slb<g>\t%0,%2" | |
e69166de UW |
4149 | [(set_attr "op_type" "RRE,RXY")]) |
4150 | ||
9a91a21f AS |
4151 | (define_insn "*sub<mode>3_slb" |
4152 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
4153 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
4154 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4155 | (match_operand:GPR 3 "s390_slb_comparison" ""))) | |
2f7e5a0d EC |
4156 | (clobber (reg:CC 33))] |
4157 | "TARGET_CPU_ZARCH" | |
e69166de | 4158 | "@ |
9a91a21f AS |
4159 | slb<g>r\t%0,%2 |
4160 | slb<g>\t%0,%2" | |
e69166de UW |
4161 | [(set_attr "op_type" "RRE,RXY")]) |
4162 | ||
9a91a21f AS |
4163 | (define_expand "add<mode>cc" |
4164 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 4165 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
4166 | (match_operand:GPR 2 "register_operand" "") |
4167 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 UW |
4168 | "TARGET_CPU_ZARCH" |
4169 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4170 | s390_compare_op0, s390_compare_op1, | |
4171 | operands[0], operands[2], | |
4172 | operands[3])) FAIL; DONE;") | |
4173 | ||
4174 | ; | |
4175 | ; scond instruction pattern(s). | |
4176 | ; | |
4177 | ||
9a91a21f AS |
4178 | (define_insn_and_split "*scond<mode>" |
4179 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
4180 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
5d880bd2 UW |
4181 | (clobber (reg:CC 33))] |
4182 | "TARGET_CPU_ZARCH" | |
4183 | "#" | |
4184 | "&& reload_completed" | |
4185 | [(set (match_dup 0) (const_int 0)) | |
4186 | (parallel | |
9a91a21f | 4187 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0)) |
5d880bd2 | 4188 | (match_dup 1))) |
5d880bd2 | 4189 | (clobber (reg:CC 33))])] |
b628bd8e | 4190 | "") |
5d880bd2 | 4191 | |
9a91a21f AS |
4192 | (define_insn_and_split "*scond<mode>_neg" |
4193 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
4194 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
5d880bd2 UW |
4195 | (clobber (reg:CC 33))] |
4196 | "TARGET_CPU_ZARCH" | |
4197 | "#" | |
4198 | "&& reload_completed" | |
4199 | [(set (match_dup 0) (const_int 0)) | |
4200 | (parallel | |
9a91a21f AS |
4201 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
4202 | (match_dup 1))) | |
5d880bd2 UW |
4203 | (clobber (reg:CC 33))]) |
4204 | (parallel | |
9a91a21f | 4205 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
5d880bd2 | 4206 | (clobber (reg:CC 33))])] |
b628bd8e | 4207 | "") |
5d880bd2 | 4208 | |
5d880bd2 | 4209 | |
9a91a21f AS |
4210 | (define_expand "s<code>" |
4211 | [(set (match_operand:SI 0 "register_operand" "") | |
4212 | (SCOND (match_dup 0) | |
4213 | (match_dup 0)))] | |
5d880bd2 | 4214 | "TARGET_CPU_ZARCH" |
9a91a21f | 4215 | "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1, |
5d880bd2 UW |
4216 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
4217 | ||
e69166de | 4218 | |
9db1d521 HP |
4219 | ;; |
4220 | ;;- Multiply instructions. | |
4221 | ;; | |
4222 | ||
4023fb28 UW |
4223 | ; |
4224 | ; muldi3 instruction pattern(s). | |
4225 | ; | |
9db1d521 | 4226 | |
07893d4f UW |
4227 | (define_insn "*muldi3_sign" |
4228 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4229 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4230 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4231 | "TARGET_64BIT" | |
4232 | "@ | |
d40c829f UW |
4233 | msgfr\t%0,%2 |
4234 | msgf\t%0,%2" | |
d3632d41 | 4235 | [(set_attr "op_type" "RRE,RXY") |
ed0e512a | 4236 | (set_attr "type" "imuldi")]) |
07893d4f | 4237 | |
4023fb28 | 4238 | (define_insn "muldi3" |
9db1d521 | 4239 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4240 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4241 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4242 | "TARGET_64BIT" |
4243 | "@ | |
d40c829f UW |
4244 | msgr\t%0,%2 |
4245 | mghi\t%0,%h2 | |
4246 | msg\t%0,%2" | |
d3632d41 | 4247 | [(set_attr "op_type" "RRE,RI,RXY") |
ed0e512a | 4248 | (set_attr "type" "imuldi")]) |
f2d3c02a | 4249 | |
9db1d521 HP |
4250 | ; |
4251 | ; mulsi3 instruction pattern(s). | |
4252 | ; | |
4253 | ||
f1e77d83 UW |
4254 | (define_insn "*mulsi3_sign" |
4255 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4256 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4257 | (match_operand:SI 1 "register_operand" "0")))] | |
4258 | "" | |
4259 | "mh\t%0,%2" | |
4260 | [(set_attr "op_type" "RX") | |
ed0e512a | 4261 | (set_attr "type" "imulhi")]) |
f1e77d83 | 4262 | |
9db1d521 | 4263 | (define_insn "mulsi3" |
d3632d41 UW |
4264 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4265 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4266 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4267 | "" |
4268 | "@ | |
d40c829f UW |
4269 | msr\t%0,%2 |
4270 | mhi\t%0,%h2 | |
4271 | ms\t%0,%2 | |
4272 | msy\t%0,%2" | |
d3632d41 | 4273 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
ed0e512a | 4274 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi")]) |
9db1d521 | 4275 | |
4023fb28 UW |
4276 | ; |
4277 | ; mulsidi3 instruction pattern(s). | |
4278 | ; | |
4279 | ||
f1e77d83 UW |
4280 | (define_insn "mulsidi3" |
4281 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4282 | (mult:DI (sign_extend:DI | |
4283 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4284 | (sign_extend:DI | |
4285 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4286 | "!TARGET_64BIT" |
f1e77d83 UW |
4287 | "@ |
4288 | mr\t%0,%2 | |
4289 | m\t%0,%2" | |
4290 | [(set_attr "op_type" "RR,RX") | |
ed0e512a | 4291 | (set_attr "type" "imulsi")]) |
4023fb28 | 4292 | |
f1e77d83 UW |
4293 | ; |
4294 | ; umulsidi3 instruction pattern(s). | |
4295 | ; | |
c7453384 | 4296 | |
f1e77d83 UW |
4297 | (define_insn "umulsidi3" |
4298 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4299 | (mult:DI (zero_extend:DI | |
4300 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4301 | (zero_extend:DI | |
4302 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4303 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4304 | "@ | |
4305 | mlr\t%0,%2 | |
4306 | ml\t%0,%2" | |
4307 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 4308 | (set_attr "type" "imulsi")]) |
c7453384 | 4309 | |
9db1d521 HP |
4310 | ; |
4311 | ; muldf3 instruction pattern(s). | |
4312 | ; | |
4313 | ||
4314 | (define_expand "muldf3" | |
553e5ce9 UW |
4315 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4316 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
4317 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4318 | "TARGET_HARD_FLOAT" |
4319 | "") | |
4320 | ||
4321 | (define_insn "*muldf3" | |
4322 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4323 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4324 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4325 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4326 | "@ | |
d40c829f UW |
4327 | mdbr\t%0,%2 |
4328 | mdb\t%0,%2" | |
ce50cae8 | 4329 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4330 | (set_attr "type" "fmuld")]) |
9db1d521 HP |
4331 | |
4332 | (define_insn "*muldf3_ibm" | |
4333 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4334 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4335 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4336 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4337 | "@ | |
d40c829f UW |
4338 | mdr\t%0,%2 |
4339 | md\t%0,%2" | |
9db1d521 | 4340 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4341 | (set_attr "type" "fmuld")]) |
9db1d521 | 4342 | |
a1b892b5 AK |
4343 | (define_insn "*fmadddf" |
4344 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4345 | (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") | |
4346 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4347 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4348 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4349 | "@ |
4350 | madbr\t%0,%1,%2 | |
4351 | madb\t%0,%1,%2" | |
4352 | [(set_attr "op_type" "RRE,RXE") | |
4353 | (set_attr "type" "fmuld")]) | |
4354 | ||
4355 | (define_insn "*fmsubdf" | |
4356 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4357 | (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") | |
4358 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4359 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4360 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4361 | "@ |
4362 | msdbr\t%0,%1,%2 | |
4363 | msdb\t%0,%1,%2" | |
4364 | [(set_attr "op_type" "RRE,RXE") | |
4365 | (set_attr "type" "fmuld")]) | |
4366 | ||
9db1d521 HP |
4367 | ; |
4368 | ; mulsf3 instruction pattern(s). | |
4369 | ; | |
4370 | ||
4371 | (define_expand "mulsf3" | |
553e5ce9 UW |
4372 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4373 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
4374 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4375 | "TARGET_HARD_FLOAT" |
4376 | "") | |
4377 | ||
4378 | (define_insn "*mulsf3" | |
4379 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4380 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4381 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4382 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4383 | "@ | |
d40c829f UW |
4384 | meebr\t%0,%2 |
4385 | meeb\t%0,%2" | |
ce50cae8 | 4386 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4387 | (set_attr "type" "fmuls")]) |
9db1d521 HP |
4388 | |
4389 | (define_insn "*mulsf3_ibm" | |
4390 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4391 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4392 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4393 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4394 | "@ | |
d40c829f UW |
4395 | mer\t%0,%2 |
4396 | me\t%0,%2" | |
9db1d521 | 4397 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4398 | (set_attr "type" "fmuls")]) |
9db1d521 | 4399 | |
a1b892b5 AK |
4400 | (define_insn "*fmaddsf" |
4401 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4402 | (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") | |
4403 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4404 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4405 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4406 | "@ |
4407 | maebr\t%0,%1,%2 | |
4408 | maeb\t%0,%1,%2" | |
4409 | [(set_attr "op_type" "RRE,RXE") | |
4410 | (set_attr "type" "fmuls")]) | |
4411 | ||
4412 | (define_insn "*fmsubsf" | |
4413 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4414 | (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") | |
4415 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4416 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4417 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4418 | "@ |
4419 | msebr\t%0,%1,%2 | |
4420 | mseb\t%0,%1,%2" | |
4421 | [(set_attr "op_type" "RRE,RXE") | |
4422 | (set_attr "type" "fmuls")]) | |
9db1d521 HP |
4423 | |
4424 | ;; | |
4425 | ;;- Divide and modulo instructions. | |
4426 | ;; | |
4427 | ||
4428 | ; | |
4023fb28 | 4429 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4430 | ; |
4431 | ||
4023fb28 UW |
4432 | (define_expand "divmoddi4" |
4433 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4434 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4435 | (match_operand:DI 2 "general_operand" ""))) |
4436 | (set (match_operand:DI 3 "general_operand" "") | |
4437 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4438 | (clobber (match_dup 4))] | |
9db1d521 | 4439 | "TARGET_64BIT" |
9db1d521 | 4440 | { |
f1e77d83 | 4441 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4442 | |
4443 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4444 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4445 | |
4446 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4447 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4448 | |
4449 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4450 | REG_NOTES (insn) = | |
4451 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4452 | ||
4453 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4454 | REG_NOTES (insn) = | |
4455 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4456 | |
9db1d521 | 4457 | DONE; |
10bbf137 | 4458 | }) |
9db1d521 HP |
4459 | |
4460 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4461 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4462 | (ior:TI | |
4023fb28 UW |
4463 | (ashift:TI |
4464 | (zero_extend:TI | |
5665e398 UW |
4465 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4466 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4467 | (const_int 64)) | |
4468 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4469 | "TARGET_64BIT" |
4470 | "@ | |
d40c829f UW |
4471 | dsgr\t%0,%2 |
4472 | dsg\t%0,%2" | |
d3632d41 | 4473 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4474 | (set_attr "type" "idiv")]) |
9db1d521 | 4475 | |
4023fb28 UW |
4476 | (define_insn "divmodtisi3" |
4477 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4478 | (ior:TI | |
4023fb28 UW |
4479 | (ashift:TI |
4480 | (zero_extend:TI | |
5665e398 | 4481 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 4482 | (sign_extend:DI |
5665e398 UW |
4483 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4484 | (const_int 64)) | |
4485 | (zero_extend:TI | |
4486 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4487 | "TARGET_64BIT" |
4023fb28 | 4488 | "@ |
d40c829f UW |
4489 | dsgfr\t%0,%2 |
4490 | dsgf\t%0,%2" | |
d3632d41 | 4491 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4492 | (set_attr "type" "idiv")]) |
9db1d521 | 4493 | |
4023fb28 UW |
4494 | ; |
4495 | ; udivmoddi4 instruction pattern(s). | |
4496 | ; | |
9db1d521 | 4497 | |
4023fb28 UW |
4498 | (define_expand "udivmoddi4" |
4499 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4500 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4501 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4502 | (set (match_operand:DI 3 "general_operand" "") | |
4503 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4504 | (clobber (match_dup 4))] | |
9db1d521 | 4505 | "TARGET_64BIT" |
9db1d521 | 4506 | { |
4023fb28 UW |
4507 | rtx insn, div_equal, mod_equal, equal; |
4508 | ||
4509 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4510 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4511 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4512 | gen_rtx_ASHIFT (TImode, |
4513 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4514 | GEN_INT (64)), |
4515 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4516 | |
4517 | operands[4] = gen_reg_rtx(TImode); | |
4518 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4519 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4520 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4521 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4522 | REG_NOTES (insn) = | |
4523 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4524 | ||
4525 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4526 | REG_NOTES (insn) = | |
4527 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4528 | ||
4529 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4530 | REG_NOTES (insn) = | |
4531 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4532 | |
9db1d521 | 4533 | DONE; |
10bbf137 | 4534 | }) |
9db1d521 HP |
4535 | |
4536 | (define_insn "udivmodtidi3" | |
4023fb28 | 4537 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 4538 | (ior:TI |
5665e398 UW |
4539 | (ashift:TI |
4540 | (zero_extend:TI | |
4541 | (truncate:DI | |
2f7e5a0d EC |
4542 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
4543 | (zero_extend:TI | |
5665e398 UW |
4544 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
4545 | (const_int 64)) | |
4546 | (zero_extend:TI | |
4547 | (truncate:DI | |
4548 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4549 | "TARGET_64BIT" |
4550 | "@ | |
d40c829f UW |
4551 | dlgr\t%0,%2 |
4552 | dlg\t%0,%2" | |
d3632d41 | 4553 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4554 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4555 | |
4556 | ; | |
4023fb28 | 4557 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4558 | ; |
4559 | ||
4023fb28 UW |
4560 | (define_expand "divmodsi4" |
4561 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4562 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4563 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4564 | (set (match_operand:SI 3 "general_operand" "") | |
4565 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4566 | (clobber (match_dup 4))] | |
9db1d521 | 4567 | "!TARGET_64BIT" |
9db1d521 | 4568 | { |
4023fb28 UW |
4569 | rtx insn, div_equal, mod_equal, equal; |
4570 | ||
4571 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4572 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4573 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4574 | gen_rtx_ASHIFT (DImode, |
4575 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4576 | GEN_INT (32)), |
4577 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4578 | |
4579 | operands[4] = gen_reg_rtx(DImode); | |
4580 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4581 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4582 | REG_NOTES (insn) = | |
4583 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4584 | ||
4585 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4586 | REG_NOTES (insn) = | |
4587 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4588 | ||
4589 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4590 | REG_NOTES (insn) = | |
4591 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4592 | |
9db1d521 | 4593 | DONE; |
10bbf137 | 4594 | }) |
9db1d521 HP |
4595 | |
4596 | (define_insn "divmoddisi3" | |
4023fb28 | 4597 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 4598 | (ior:DI |
5665e398 UW |
4599 | (ashift:DI |
4600 | (zero_extend:DI | |
4601 | (truncate:SI | |
2f7e5a0d EC |
4602 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4603 | (sign_extend:DI | |
5665e398 UW |
4604 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4605 | (const_int 32)) | |
4606 | (zero_extend:DI | |
4607 | (truncate:SI | |
4608 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4609 | "!TARGET_64BIT" |
4610 | "@ | |
d40c829f UW |
4611 | dr\t%0,%2 |
4612 | d\t%0,%2" | |
9db1d521 | 4613 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4614 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4615 | |
4616 | ; | |
4617 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4618 | ; | |
4619 | ||
f1e77d83 UW |
4620 | (define_expand "udivmodsi4" |
4621 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4622 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4623 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4624 | (set (match_operand:SI 3 "general_operand" "") | |
4625 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4626 | (clobber (match_dup 4))] | |
4627 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4628 | { | |
4629 | rtx insn, div_equal, mod_equal, equal; | |
4630 | ||
4631 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4632 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4633 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4634 | gen_rtx_ASHIFT (DImode, |
4635 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4636 | GEN_INT (32)), |
4637 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4638 | |
4639 | operands[4] = gen_reg_rtx(DImode); | |
4640 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4641 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4642 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4643 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4644 | REG_NOTES (insn) = | |
4645 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4646 | ||
4647 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4648 | REG_NOTES (insn) = | |
4649 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4650 | ||
4651 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4652 | REG_NOTES (insn) = | |
4653 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4654 | ||
4655 | DONE; | |
4656 | }) | |
4657 | ||
4658 | (define_insn "udivmoddisi3" | |
4659 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 4660 | (ior:DI |
5665e398 UW |
4661 | (ashift:DI |
4662 | (zero_extend:DI | |
4663 | (truncate:SI | |
2f7e5a0d EC |
4664 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
4665 | (zero_extend:DI | |
5665e398 UW |
4666 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
4667 | (const_int 32)) | |
4668 | (zero_extend:DI | |
4669 | (truncate:SI | |
4670 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4671 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4672 | "@ | |
4673 | dlr\t%0,%2 | |
4674 | dl\t%0,%2" | |
4675 | [(set_attr "op_type" "RRE,RXY") | |
4676 | (set_attr "type" "idiv")]) | |
4023fb28 | 4677 | |
9db1d521 HP |
4678 | (define_expand "udivsi3" |
4679 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4680 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4681 | (match_operand:SI 2 "general_operand" ""))) |
4682 | (clobber (match_dup 3))] | |
f1e77d83 | 4683 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4684 | { |
4023fb28 UW |
4685 | rtx insn, udiv_equal, umod_equal, equal; |
4686 | ||
4687 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4688 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4689 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4690 | gen_rtx_ASHIFT (DImode, |
4691 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4692 | GEN_INT (32)), |
4693 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4694 | |
4023fb28 | 4695 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4696 | |
4697 | if (CONSTANT_P (operands[2])) | |
4698 | { | |
4699 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4700 | { | |
4701 | rtx label1 = gen_label_rtx (); | |
4702 | ||
4023fb28 UW |
4703 | operands[1] = make_safe_from (operands[1], operands[0]); |
4704 | emit_move_insn (operands[0], const0_rtx); | |
4705 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4706 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4707 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4708 | emit_label (label1); |
4709 | } | |
4710 | else | |
4711 | { | |
c7453384 EC |
4712 | operands[2] = force_reg (SImode, operands[2]); |
4713 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4714 | |
4715 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4716 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4717 | operands[2])); | |
4718 | REG_NOTES (insn) = | |
4719 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4720 | |
4721 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4722 | gen_lowpart (SImode, operands[3])); |
4723 | REG_NOTES (insn) = | |
c7453384 | 4724 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4725 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4726 | } |
4727 | } | |
4728 | else | |
c7453384 | 4729 | { |
9db1d521 HP |
4730 | rtx label1 = gen_label_rtx (); |
4731 | rtx label2 = gen_label_rtx (); | |
4732 | rtx label3 = gen_label_rtx (); | |
4733 | ||
c7453384 EC |
4734 | operands[1] = force_reg (SImode, operands[1]); |
4735 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4736 | operands[2] = force_reg (SImode, operands[2]); | |
4737 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4738 | |
4739 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4740 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4741 | emit_jump_insn (gen_bgtu (label3)); | |
220a826e | 4742 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4743 | emit_jump_insn (gen_blt (label2)); |
4744 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4745 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4746 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4747 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4748 | operands[2])); | |
4749 | REG_NOTES (insn) = | |
4750 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4751 | |
4752 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4753 | gen_lowpart (SImode, operands[3])); |
4754 | REG_NOTES (insn) = | |
c7453384 | 4755 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4756 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4757 | emit_jump (label3); |
9db1d521 | 4758 | emit_label (label1); |
4023fb28 | 4759 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4760 | emit_jump (label3); |
9db1d521 | 4761 | emit_label (label2); |
4023fb28 | 4762 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4763 | emit_label (label3); |
4764 | } | |
c7453384 | 4765 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4766 | DONE; |
10bbf137 | 4767 | }) |
9db1d521 HP |
4768 | |
4769 | (define_expand "umodsi3" | |
4770 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4771 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4772 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4773 | (clobber (match_dup 3))] | |
f1e77d83 | 4774 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4775 | { |
4023fb28 UW |
4776 | rtx insn, udiv_equal, umod_equal, equal; |
4777 | ||
4778 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4779 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4780 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4781 | gen_rtx_ASHIFT (DImode, |
4782 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4783 | GEN_INT (32)), |
4784 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4785 | |
4023fb28 | 4786 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4787 | |
4788 | if (CONSTANT_P (operands[2])) | |
4789 | { | |
4790 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4791 | { | |
4792 | rtx label1 = gen_label_rtx (); | |
4793 | ||
4023fb28 UW |
4794 | operands[1] = make_safe_from (operands[1], operands[0]); |
4795 | emit_move_insn (operands[0], operands[1]); | |
4796 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 4797 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
4798 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4799 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
4800 | emit_label (label1); |
4801 | } | |
4802 | else | |
4803 | { | |
c7453384 EC |
4804 | operands[2] = force_reg (SImode, operands[2]); |
4805 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4806 | |
4807 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4808 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4809 | operands[2])); | |
4810 | REG_NOTES (insn) = | |
4811 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4812 | |
4813 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4814 | gen_highpart (SImode, operands[3])); |
4815 | REG_NOTES (insn) = | |
c7453384 | 4816 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4817 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
4818 | } |
4819 | } | |
4820 | else | |
4821 | { | |
4822 | rtx label1 = gen_label_rtx (); | |
4823 | rtx label2 = gen_label_rtx (); | |
4824 | rtx label3 = gen_label_rtx (); | |
4825 | ||
c7453384 EC |
4826 | operands[1] = force_reg (SImode, operands[1]); |
4827 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4828 | operands[2] = force_reg (SImode, operands[2]); | |
4829 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 4830 | |
c7453384 | 4831 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 4832 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 | 4833 | emit_jump_insn (gen_bgtu (label3)); |
220a826e | 4834 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4835 | emit_jump_insn (gen_blt (label2)); |
4836 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4837 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4838 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4839 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4840 | operands[2])); | |
4841 | REG_NOTES (insn) = | |
4842 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4843 | |
4844 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4845 | gen_highpart (SImode, operands[3])); |
4846 | REG_NOTES (insn) = | |
c7453384 | 4847 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4848 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 4849 | emit_jump (label3); |
9db1d521 | 4850 | emit_label (label1); |
4023fb28 | 4851 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 4852 | emit_jump (label3); |
9db1d521 | 4853 | emit_label (label2); |
4023fb28 | 4854 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
4855 | emit_label (label3); |
4856 | } | |
9db1d521 | 4857 | DONE; |
10bbf137 | 4858 | }) |
9db1d521 HP |
4859 | |
4860 | ; | |
4861 | ; divdf3 instruction pattern(s). | |
4862 | ; | |
4863 | ||
4864 | (define_expand "divdf3" | |
553e5ce9 UW |
4865 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4866 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
4867 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4868 | "TARGET_HARD_FLOAT" |
4869 | "") | |
4870 | ||
4871 | (define_insn "*divdf3" | |
4023fb28 UW |
4872 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4873 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 4874 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4875 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4876 | "@ | |
d40c829f UW |
4877 | ddbr\t%0,%2 |
4878 | ddb\t%0,%2" | |
ce50cae8 | 4879 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4880 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
4881 | |
4882 | (define_insn "*divdf3_ibm" | |
4023fb28 UW |
4883 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4884 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 4885 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4886 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4887 | "@ | |
d40c829f UW |
4888 | ddr\t%0,%2 |
4889 | dd\t%0,%2" | |
9db1d521 | 4890 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4891 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
4892 | |
4893 | ; | |
4894 | ; divsf3 instruction pattern(s). | |
4895 | ; | |
4896 | ||
4897 | (define_expand "divsf3" | |
553e5ce9 UW |
4898 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4899 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
4900 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4901 | "TARGET_HARD_FLOAT" |
4902 | "") | |
4903 | ||
4904 | (define_insn "*divsf3" | |
4023fb28 UW |
4905 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4906 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 4907 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4908 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4909 | "@ | |
d40c829f UW |
4910 | debr\t%0,%2 |
4911 | deb\t%0,%2" | |
ce50cae8 | 4912 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4913 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
4914 | |
4915 | (define_insn "*divsf3" | |
4023fb28 UW |
4916 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4917 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 4918 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4919 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4920 | "@ | |
d40c829f UW |
4921 | der\t%0,%2 |
4922 | de\t%0,%2" | |
9db1d521 | 4923 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4924 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
4925 | |
4926 | ||
4927 | ;; | |
4928 | ;;- And instructions. | |
4929 | ;; | |
4930 | ||
4931 | ; | |
4932 | ; anddi3 instruction pattern(s). | |
4933 | ; | |
4934 | ||
4935 | (define_insn "*anddi3_cc" | |
4936 | [(set (reg 33) | |
96fd3851 | 4937 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4938 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 4939 | (const_int 0))) |
4023fb28 | 4940 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
4941 | (and:DI (match_dup 1) (match_dup 2)))] |
4942 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4943 | "@ | |
d40c829f UW |
4944 | ngr\t%0,%2 |
4945 | ng\t%0,%2" | |
d3632d41 | 4946 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
4947 | |
4948 | (define_insn "*anddi3_cconly" | |
4949 | [(set (reg 33) | |
96fd3851 | 4950 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4951 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
4952 | (const_int 0))) |
4953 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
4954 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
4955 | /* Do not steal TM patterns. */ | |
4956 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 4957 | "@ |
d40c829f UW |
4958 | ngr\t%0,%2 |
4959 | ng\t%0,%2" | |
d3632d41 | 4960 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 4961 | |
8cb66696 | 4962 | (define_insn "*anddi3" |
0dfa6c5e | 4963 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
8cb66696 | 4964 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
0dfa6c5e | 4965 | "%d,o,0,0,0,0,0,0,0,0") |
8cb66696 | 4966 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 4967 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) |
4023fb28 | 4968 | (clobber (reg:CC 33))] |
8cb66696 UW |
4969 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
4970 | "@ | |
4971 | # | |
4972 | # | |
4973 | nihh\t%0,%j2 | |
4974 | nihl\t%0,%j2 | |
4975 | nilh\t%0,%j2 | |
4976 | nill\t%0,%j2 | |
4977 | ngr\t%0,%2 | |
4978 | ng\t%0,%2 | |
0dfa6c5e | 4979 | # |
19b63d8e | 4980 | #" |
0dfa6c5e UW |
4981 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
4982 | ||
4983 | (define_split | |
4984 | [(set (match_operand:DI 0 "s_operand" "") | |
4985 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
4986 | (clobber (reg:CC 33))] | |
4987 | "reload_completed" | |
4988 | [(parallel | |
4989 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
4990 | (clobber (reg:CC 33))])] | |
4991 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
4023fb28 | 4992 | |
8cb66696 UW |
4993 | (define_expand "anddi3" |
4994 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
4995 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
4996 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 4997 | (clobber (reg:CC 33))] |
8cb66696 UW |
4998 | "TARGET_64BIT" |
4999 | "s390_expand_logical_operator (AND, DImode, operands); DONE;") | |
9db1d521 HP |
5000 | |
5001 | ; | |
5002 | ; andsi3 instruction pattern(s). | |
5003 | ; | |
5004 | ||
5005 | (define_insn "*andsi3_cc" | |
5006 | [(set (reg 33) | |
d3632d41 UW |
5007 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5008 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5009 | (const_int 0))) |
d3632d41 | 5010 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 HP |
5011 | (and:SI (match_dup 1) (match_dup 2)))] |
5012 | "s390_match_ccmode(insn, CCTmode)" | |
5013 | "@ | |
d40c829f UW |
5014 | nr\t%0,%2 |
5015 | n\t%0,%2 | |
5016 | ny\t%0,%2" | |
d3632d41 | 5017 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
5018 | |
5019 | (define_insn "*andsi3_cconly" | |
5020 | [(set (reg 33) | |
d3632d41 UW |
5021 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5022 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5023 | (const_int 0))) |
d3632d41 | 5024 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
68f9c5e2 UW |
5025 | "s390_match_ccmode(insn, CCTmode) |
5026 | /* Do not steal TM patterns. */ | |
5027 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 5028 | "@ |
d40c829f UW |
5029 | nr\t%0,%2 |
5030 | n\t%0,%2 | |
5031 | ny\t%0,%2" | |
d3632d41 | 5032 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5033 | |
f19a9af7 | 5034 | (define_insn "*andsi3_zarch" |
0dfa6c5e UW |
5035 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q") |
5036 | (and:SI (match_operand:SI 1 "nonimmediate_operand" | |
5037 | "%d,o,0,0,0,0,0,0,0") | |
5038 | (match_operand:SI 2 "general_operand" | |
5039 | "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q"))) | |
9db1d521 | 5040 | (clobber (reg:CC 33))] |
8cb66696 | 5041 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5042 | "@ |
f19a9af7 AK |
5043 | # |
5044 | # | |
5045 | nilh\t%0,%j2 | |
2f7e5a0d | 5046 | nill\t%0,%j2 |
d40c829f UW |
5047 | nr\t%0,%2 |
5048 | n\t%0,%2 | |
8cb66696 | 5049 | ny\t%0,%2 |
0dfa6c5e | 5050 | # |
19b63d8e | 5051 | #" |
0dfa6c5e | 5052 | [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")]) |
f19a9af7 AK |
5053 | |
5054 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
5055 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5056 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5057 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
f19a9af7 | 5058 | (clobber (reg:CC 33))] |
8cb66696 | 5059 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5060 | "@ |
5061 | nr\t%0,%2 | |
8cb66696 | 5062 | n\t%0,%2 |
0dfa6c5e | 5063 | # |
19b63d8e | 5064 | #" |
0dfa6c5e UW |
5065 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5066 | ||
5067 | (define_split | |
5068 | [(set (match_operand:SI 0 "s_operand" "") | |
5069 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5070 | (clobber (reg:CC 33))] | |
5071 | "reload_completed" | |
5072 | [(parallel | |
5073 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5074 | (clobber (reg:CC 33))])] | |
5075 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
4023fb28 | 5076 | |
8cb66696 UW |
5077 | (define_expand "andsi3" |
5078 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5079 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5080 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5081 | (clobber (reg:CC 33))] |
5082 | "" | |
8cb66696 | 5083 | "s390_expand_logical_operator (AND, SImode, operands); DONE;") |
9db1d521 HP |
5084 | |
5085 | ; | |
5086 | ; andhi3 instruction pattern(s). | |
5087 | ; | |
5088 | ||
8cb66696 | 5089 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
5090 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5091 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5092 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
4023fb28 | 5093 | (clobber (reg:CC 33))] |
8cb66696 | 5094 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5095 | "@ |
d40c829f | 5096 | nr\t%0,%2 |
8cb66696 | 5097 | nill\t%0,%x2 |
0dfa6c5e | 5098 | # |
19b63d8e | 5099 | #" |
0dfa6c5e | 5100 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5101 | |
5102 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
5103 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5104 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5105 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
4023fb28 | 5106 | (clobber (reg:CC 33))] |
8cb66696 UW |
5107 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5108 | "@ | |
5109 | nr\t%0,%2 | |
0dfa6c5e | 5110 | # |
19b63d8e | 5111 | #" |
0dfa6c5e UW |
5112 | [(set_attr "op_type" "RR,SI,SS")]) |
5113 | ||
5114 | (define_split | |
5115 | [(set (match_operand:HI 0 "s_operand" "") | |
5116 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5117 | (clobber (reg:CC 33))] | |
5118 | "reload_completed" | |
5119 | [(parallel | |
5120 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5121 | (clobber (reg:CC 33))])] | |
5122 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
9db1d521 | 5123 | |
8cb66696 UW |
5124 | (define_expand "andhi3" |
5125 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5126 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5127 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5128 | (clobber (reg:CC 33))] |
5129 | "" | |
8cb66696 | 5130 | "s390_expand_logical_operator (AND, HImode, operands); DONE;") |
9db1d521 HP |
5131 | |
5132 | ; | |
5133 | ; andqi3 instruction pattern(s). | |
5134 | ; | |
5135 | ||
8cb66696 UW |
5136 | (define_insn "*andqi3_zarch" |
5137 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5138 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5139 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
4023fb28 | 5140 | (clobber (reg:CC 33))] |
8cb66696 | 5141 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5142 | "@ |
d40c829f | 5143 | nr\t%0,%2 |
8cb66696 | 5144 | nill\t%0,%b2 |
fc0ea003 UW |
5145 | ni\t%S0,%b2 |
5146 | niy\t%S0,%b2 | |
19b63d8e | 5147 | #" |
8cb66696 UW |
5148 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5149 | ||
5150 | (define_insn "*andqi3_esa" | |
5151 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5152 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5153 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
9db1d521 | 5154 | (clobber (reg:CC 33))] |
8cb66696 | 5155 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5156 | "@ |
8cb66696 | 5157 | nr\t%0,%2 |
fc0ea003 | 5158 | ni\t%S0,%b2 |
19b63d8e | 5159 | #" |
8cb66696 | 5160 | [(set_attr "op_type" "RR,SI,SS")]) |
4023fb28 | 5161 | |
8cb66696 UW |
5162 | (define_expand "andqi3" |
5163 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5164 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5165 | (match_operand:QI 2 "general_operand" ""))) | |
4023fb28 UW |
5166 | (clobber (reg:CC 33))] |
5167 | "" | |
8cb66696 | 5168 | "s390_expand_logical_operator (AND, QImode, operands); DONE;") |
9db1d521 | 5169 | |
19b63d8e UW |
5170 | ; |
5171 | ; Block and (NC) patterns. | |
5172 | ; | |
5173 | ||
5174 | (define_insn "*nc" | |
5175 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5176 | (and:BLK (match_dup 0) | |
5177 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5178 | (use (match_operand 2 "const_int_operand" "n")) | |
5179 | (clobber (reg:CC 33))] | |
5180 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5181 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 5182 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5183 | |
5184 | (define_split | |
5185 | [(set (match_operand 0 "memory_operand" "") | |
5186 | (and (match_dup 0) | |
5187 | (match_operand 1 "memory_operand" ""))) | |
5188 | (clobber (reg:CC 33))] | |
5189 | "reload_completed | |
5190 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5191 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5192 | [(parallel | |
5193 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
5194 | (use (match_dup 2)) | |
5195 | (clobber (reg:CC 33))])] | |
5196 | { | |
5197 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5198 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5199 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5200 | }) | |
5201 | ||
5202 | (define_peephole2 | |
5203 | [(parallel | |
5204 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5205 | (and:BLK (match_dup 0) | |
5206 | (match_operand:BLK 1 "memory_operand" ""))) | |
5207 | (use (match_operand 2 "const_int_operand" "")) | |
5208 | (clobber (reg:CC 33))]) | |
5209 | (parallel | |
5210 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5211 | (and:BLK (match_dup 3) | |
5212 | (match_operand:BLK 4 "memory_operand" ""))) | |
5213 | (use (match_operand 5 "const_int_operand" "")) | |
5214 | (clobber (reg:CC 33))])] | |
5215 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
5216 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5217 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5218 | [(parallel | |
5219 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
5220 | (use (match_dup 8)) | |
5221 | (clobber (reg:CC 33))])] | |
5222 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5223 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5224 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5225 | ||
9db1d521 HP |
5226 | |
5227 | ;; | |
5228 | ;;- Bit set (inclusive or) instructions. | |
5229 | ;; | |
5230 | ||
5231 | ; | |
5232 | ; iordi3 instruction pattern(s). | |
5233 | ; | |
5234 | ||
4023fb28 UW |
5235 | (define_insn "*iordi3_cc" |
5236 | [(set (reg 33) | |
96fd3851 | 5237 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5238 | (match_operand:DI 2 "general_operand" "d,m")) |
5239 | (const_int 0))) | |
5240 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5241 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5242 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5243 | "@ | |
d40c829f UW |
5244 | ogr\t%0,%2 |
5245 | og\t%0,%2" | |
d3632d41 | 5246 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5247 | |
5248 | (define_insn "*iordi3_cconly" | |
5249 | [(set (reg 33) | |
96fd3851 | 5250 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5251 | (match_operand:DI 2 "general_operand" "d,m")) |
5252 | (const_int 0))) | |
5253 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5254 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5255 | "@ | |
d40c829f UW |
5256 | ogr\t%0,%2 |
5257 | og\t%0,%2" | |
d3632d41 | 5258 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5259 | |
8cb66696 | 5260 | (define_insn "*iordi3" |
0dfa6c5e | 5261 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
bad82153 | 5262 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") |
8cb66696 | 5263 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5264 | "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) |
9db1d521 | 5265 | (clobber (reg:CC 33))] |
8cb66696 | 5266 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5267 | "@ |
f19a9af7 AK |
5268 | oihh\t%0,%i2 |
5269 | oihl\t%0,%i2 | |
5270 | oilh\t%0,%i2 | |
5271 | oill\t%0,%i2 | |
d40c829f | 5272 | ogr\t%0,%2 |
8cb66696 | 5273 | og\t%0,%2 |
0dfa6c5e | 5274 | # |
19b63d8e | 5275 | #" |
0dfa6c5e UW |
5276 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5277 | ||
5278 | (define_split | |
5279 | [(set (match_operand:DI 0 "s_operand" "") | |
5280 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5281 | (clobber (reg:CC 33))] | |
5282 | "reload_completed" | |
5283 | [(parallel | |
5284 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5285 | (clobber (reg:CC 33))])] | |
5286 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
4023fb28 | 5287 | |
8cb66696 UW |
5288 | (define_expand "iordi3" |
5289 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5290 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5291 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 5292 | (clobber (reg:CC 33))] |
8cb66696 UW |
5293 | "TARGET_64BIT" |
5294 | "s390_expand_logical_operator (IOR, DImode, operands); DONE;") | |
9db1d521 HP |
5295 | |
5296 | ; | |
5297 | ; iorsi3 instruction pattern(s). | |
5298 | ; | |
5299 | ||
4023fb28 UW |
5300 | (define_insn "*iorsi3_cc" |
5301 | [(set (reg 33) | |
d3632d41 UW |
5302 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5303 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5304 | (const_int 0))) |
d3632d41 | 5305 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5306 | (ior:SI (match_dup 1) (match_dup 2)))] |
5307 | "s390_match_ccmode(insn, CCTmode)" | |
5308 | "@ | |
d40c829f UW |
5309 | or\t%0,%2 |
5310 | o\t%0,%2 | |
5311 | oy\t%0,%2" | |
d3632d41 | 5312 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5313 | |
5314 | (define_insn "*iorsi3_cconly" | |
5315 | [(set (reg 33) | |
d3632d41 UW |
5316 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5317 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5318 | (const_int 0))) |
d3632d41 | 5319 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5320 | "s390_match_ccmode(insn, CCTmode)" |
5321 | "@ | |
d40c829f UW |
5322 | or\t%0,%2 |
5323 | o\t%0,%2 | |
5324 | oy\t%0,%2" | |
d3632d41 | 5325 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 | 5326 | |
8cb66696 | 5327 | (define_insn "*iorsi3_zarch" |
0dfa6c5e | 5328 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q") |
bad82153 | 5329 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") |
0dfa6c5e | 5330 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q"))) |
4023fb28 | 5331 | (clobber (reg:CC 33))] |
8cb66696 | 5332 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5333 | "@ |
f19a9af7 AK |
5334 | oilh\t%0,%i2 |
5335 | oill\t%0,%i2 | |
d40c829f UW |
5336 | or\t%0,%2 |
5337 | o\t%0,%2 | |
8cb66696 | 5338 | oy\t%0,%2 |
0dfa6c5e | 5339 | # |
19b63d8e | 5340 | #" |
0dfa6c5e | 5341 | [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")]) |
8cb66696 UW |
5342 | |
5343 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 5344 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 5345 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 5346 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
f19a9af7 | 5347 | (clobber (reg:CC 33))] |
8cb66696 | 5348 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5349 | "@ |
5350 | or\t%0,%2 | |
8cb66696 | 5351 | o\t%0,%2 |
0dfa6c5e | 5352 | # |
19b63d8e | 5353 | #" |
0dfa6c5e UW |
5354 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5355 | ||
5356 | (define_split | |
5357 | [(set (match_operand:SI 0 "s_operand" "") | |
5358 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5359 | (clobber (reg:CC 33))] | |
5360 | "reload_completed" | |
5361 | [(parallel | |
5362 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5363 | (clobber (reg:CC 33))])] | |
5364 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
4023fb28 | 5365 | |
8cb66696 UW |
5366 | (define_expand "iorsi3" |
5367 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5368 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5369 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5370 | (clobber (reg:CC 33))] |
5371 | "" | |
8cb66696 | 5372 | "s390_expand_logical_operator (IOR, SImode, operands); DONE;") |
4023fb28 UW |
5373 | |
5374 | ; | |
5375 | ; iorhi3 instruction pattern(s). | |
5376 | ; | |
5377 | ||
8cb66696 | 5378 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
5379 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5380 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5381 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
4023fb28 | 5382 | (clobber (reg:CC 33))] |
8cb66696 | 5383 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5384 | "@ |
d40c829f | 5385 | or\t%0,%2 |
8cb66696 | 5386 | oill\t%0,%x2 |
0dfa6c5e | 5387 | # |
19b63d8e | 5388 | #" |
0dfa6c5e | 5389 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5390 | |
5391 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
5392 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5393 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5394 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
4023fb28 | 5395 | (clobber (reg:CC 33))] |
8cb66696 UW |
5396 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5397 | "@ | |
5398 | or\t%0,%2 | |
0dfa6c5e | 5399 | # |
19b63d8e | 5400 | #" |
0dfa6c5e UW |
5401 | [(set_attr "op_type" "RR,SI,SS")]) |
5402 | ||
5403 | (define_split | |
5404 | [(set (match_operand:HI 0 "s_operand" "") | |
5405 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5406 | (clobber (reg:CC 33))] | |
5407 | "reload_completed" | |
5408 | [(parallel | |
5409 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5410 | (clobber (reg:CC 33))])] | |
5411 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
9db1d521 | 5412 | |
8cb66696 UW |
5413 | (define_expand "iorhi3" |
5414 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5415 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5416 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5417 | (clobber (reg:CC 33))] |
5418 | "" | |
8cb66696 | 5419 | "s390_expand_logical_operator (IOR, HImode, operands); DONE;") |
9db1d521 HP |
5420 | |
5421 | ; | |
4023fb28 | 5422 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5423 | ; |
5424 | ||
8cb66696 UW |
5425 | (define_insn "*iorqi3_zarch" |
5426 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5427 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5428 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
4023fb28 | 5429 | (clobber (reg:CC 33))] |
8cb66696 | 5430 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5431 | "@ |
d40c829f | 5432 | or\t%0,%2 |
8cb66696 | 5433 | oill\t%0,%b2 |
fc0ea003 UW |
5434 | oi\t%S0,%b2 |
5435 | oiy\t%S0,%b2 | |
19b63d8e | 5436 | #" |
8cb66696 UW |
5437 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5438 | ||
5439 | (define_insn "*iorqi3_esa" | |
5440 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5441 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5442 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
4023fb28 | 5443 | (clobber (reg:CC 33))] |
8cb66696 | 5444 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5445 | "@ |
8cb66696 | 5446 | or\t%0,%2 |
fc0ea003 | 5447 | oi\t%S0,%b2 |
19b63d8e | 5448 | #" |
8cb66696 | 5449 | [(set_attr "op_type" "RR,SI,SS")]) |
9db1d521 | 5450 | |
8cb66696 UW |
5451 | (define_expand "iorqi3" |
5452 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5453 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5454 | (match_operand:QI 2 "general_operand" ""))) | |
9db1d521 HP |
5455 | (clobber (reg:CC 33))] |
5456 | "" | |
8cb66696 | 5457 | "s390_expand_logical_operator (IOR, QImode, operands); DONE;") |
9db1d521 | 5458 | |
19b63d8e UW |
5459 | ; |
5460 | ; Block inclusive or (OC) patterns. | |
5461 | ; | |
5462 | ||
5463 | (define_insn "*oc" | |
5464 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5465 | (ior:BLK (match_dup 0) | |
5466 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5467 | (use (match_operand 2 "const_int_operand" "n")) | |
5468 | (clobber (reg:CC 33))] | |
5469 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5470 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 5471 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5472 | |
5473 | (define_split | |
5474 | [(set (match_operand 0 "memory_operand" "") | |
5475 | (ior (match_dup 0) | |
5476 | (match_operand 1 "memory_operand" ""))) | |
5477 | (clobber (reg:CC 33))] | |
5478 | "reload_completed | |
5479 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5480 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5481 | [(parallel | |
5482 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
5483 | (use (match_dup 2)) | |
5484 | (clobber (reg:CC 33))])] | |
5485 | { | |
5486 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5487 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5488 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5489 | }) | |
5490 | ||
5491 | (define_peephole2 | |
5492 | [(parallel | |
5493 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5494 | (ior:BLK (match_dup 0) | |
5495 | (match_operand:BLK 1 "memory_operand" ""))) | |
5496 | (use (match_operand 2 "const_int_operand" "")) | |
5497 | (clobber (reg:CC 33))]) | |
5498 | (parallel | |
5499 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5500 | (ior:BLK (match_dup 3) | |
5501 | (match_operand:BLK 4 "memory_operand" ""))) | |
5502 | (use (match_operand 5 "const_int_operand" "")) | |
5503 | (clobber (reg:CC 33))])] | |
5504 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
5505 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5506 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5507 | [(parallel | |
5508 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
5509 | (use (match_dup 8)) | |
5510 | (clobber (reg:CC 33))])] | |
5511 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5512 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5513 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5514 | ||
9db1d521 HP |
5515 | |
5516 | ;; | |
5517 | ;;- Xor instructions. | |
5518 | ;; | |
5519 | ||
5520 | ; | |
5521 | ; xordi3 instruction pattern(s). | |
5522 | ; | |
5523 | ||
4023fb28 UW |
5524 | (define_insn "*xordi3_cc" |
5525 | [(set (reg 33) | |
96fd3851 | 5526 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5527 | (match_operand:DI 2 "general_operand" "d,m")) |
5528 | (const_int 0))) | |
5529 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5530 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5531 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5532 | "@ | |
d40c829f UW |
5533 | xgr\t%0,%2 |
5534 | xg\t%0,%2" | |
d3632d41 | 5535 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5536 | |
5537 | (define_insn "*xordi3_cconly" | |
5538 | [(set (reg 33) | |
96fd3851 | 5539 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5540 | (match_operand:DI 2 "general_operand" "d,m")) |
5541 | (const_int 0))) | |
5542 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5543 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5544 | "@ | |
d40c829f UW |
5545 | xgr\t%0,%2 |
5546 | xr\t%0,%2" | |
d3632d41 | 5547 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5548 | |
8cb66696 | 5549 | (define_insn "*xordi3" |
0dfa6c5e UW |
5550 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5551 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5552 | (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) | |
9db1d521 | 5553 | (clobber (reg:CC 33))] |
8cb66696 | 5554 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5555 | "@ |
d40c829f | 5556 | xgr\t%0,%2 |
8cb66696 | 5557 | xg\t%0,%2 |
0dfa6c5e | 5558 | # |
19b63d8e | 5559 | #" |
0dfa6c5e UW |
5560 | [(set_attr "op_type" "RRE,RXY,SI,SS")]) |
5561 | ||
5562 | (define_split | |
5563 | [(set (match_operand:DI 0 "s_operand" "") | |
5564 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5565 | (clobber (reg:CC 33))] | |
5566 | "reload_completed" | |
5567 | [(parallel | |
5568 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5569 | (clobber (reg:CC 33))])] | |
5570 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
4023fb28 | 5571 | |
8cb66696 UW |
5572 | (define_expand "xordi3" |
5573 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5574 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5575 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 5576 | (clobber (reg:CC 33))] |
8cb66696 UW |
5577 | "TARGET_64BIT" |
5578 | "s390_expand_logical_operator (XOR, DImode, operands); DONE;") | |
9db1d521 HP |
5579 | |
5580 | ; | |
5581 | ; xorsi3 instruction pattern(s). | |
5582 | ; | |
5583 | ||
4023fb28 UW |
5584 | (define_insn "*xorsi3_cc" |
5585 | [(set (reg 33) | |
d3632d41 UW |
5586 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5587 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5588 | (const_int 0))) |
d3632d41 | 5589 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5590 | (xor:SI (match_dup 1) (match_dup 2)))] |
5591 | "s390_match_ccmode(insn, CCTmode)" | |
5592 | "@ | |
d40c829f UW |
5593 | xr\t%0,%2 |
5594 | x\t%0,%2 | |
5595 | xy\t%0,%2" | |
d3632d41 | 5596 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5597 | |
5598 | (define_insn "*xorsi3_cconly" | |
5599 | [(set (reg 33) | |
d3632d41 UW |
5600 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5601 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5602 | (const_int 0))) |
d3632d41 | 5603 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5604 | "s390_match_ccmode(insn, CCTmode)" |
5605 | "@ | |
d40c829f UW |
5606 | xr\t%0,%2 |
5607 | x\t%0,%2 | |
5608 | xy\t%0,%2" | |
d3632d41 | 5609 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5610 | |
8cb66696 | 5611 | (define_insn "*xorsi3" |
0dfa6c5e UW |
5612 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q") |
5613 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5614 | (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q"))) | |
9db1d521 | 5615 | (clobber (reg:CC 33))] |
8cb66696 | 5616 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5617 | "@ |
d40c829f UW |
5618 | xr\t%0,%2 |
5619 | x\t%0,%2 | |
8cb66696 | 5620 | xy\t%0,%2 |
0dfa6c5e | 5621 | # |
19b63d8e | 5622 | #" |
0dfa6c5e UW |
5623 | [(set_attr "op_type" "RR,RX,RXY,SI,SS")]) |
5624 | ||
5625 | (define_split | |
5626 | [(set (match_operand:SI 0 "s_operand" "") | |
5627 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5628 | (clobber (reg:CC 33))] | |
5629 | "reload_completed" | |
5630 | [(parallel | |
5631 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5632 | (clobber (reg:CC 33))])] | |
5633 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
8cb66696 UW |
5634 | |
5635 | (define_expand "xorsi3" | |
5636 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5637 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5638 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5639 | (clobber (reg:CC 33))] |
5640 | "" | |
8cb66696 | 5641 | "s390_expand_logical_operator (XOR, SImode, operands); DONE;") |
9db1d521 HP |
5642 | |
5643 | ; | |
5644 | ; xorhi3 instruction pattern(s). | |
5645 | ; | |
5646 | ||
8cb66696 | 5647 | (define_insn "*xorhi3" |
0dfa6c5e UW |
5648 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5649 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5650 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
4023fb28 | 5651 | (clobber (reg:CC 33))] |
8cb66696 UW |
5652 | "s390_logical_operator_ok_p (operands)" |
5653 | "@ | |
5654 | xr\t%0,%2 | |
0dfa6c5e | 5655 | # |
19b63d8e | 5656 | #" |
0dfa6c5e UW |
5657 | [(set_attr "op_type" "RR,SI,SS")]) |
5658 | ||
5659 | (define_split | |
5660 | [(set (match_operand:HI 0 "s_operand" "") | |
5661 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5662 | (clobber (reg:CC 33))] | |
5663 | "reload_completed" | |
5664 | [(parallel | |
5665 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5666 | (clobber (reg:CC 33))])] | |
5667 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
9db1d521 | 5668 | |
8cb66696 UW |
5669 | (define_expand "xorhi3" |
5670 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5671 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5672 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5673 | (clobber (reg:CC 33))] |
5674 | "" | |
8cb66696 | 5675 | "s390_expand_logical_operator (XOR, HImode, operands); DONE;") |
9db1d521 HP |
5676 | |
5677 | ; | |
5678 | ; xorqi3 instruction pattern(s). | |
5679 | ; | |
5680 | ||
8cb66696 UW |
5681 | (define_insn "*xorqi3" |
5682 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q") | |
5683 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0") | |
5684 | (match_operand:QI 2 "general_operand" "d,n,n,Q"))) | |
4023fb28 | 5685 | (clobber (reg:CC 33))] |
8cb66696 | 5686 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5687 | "@ |
8cb66696 | 5688 | xr\t%0,%2 |
fc0ea003 UW |
5689 | xi\t%S0,%b2 |
5690 | xiy\t%S0,%b2 | |
19b63d8e | 5691 | #" |
8cb66696 | 5692 | [(set_attr "op_type" "RR,SI,SIY,SS")]) |
4023fb28 | 5693 | |
8cb66696 UW |
5694 | (define_expand "xorqi3" |
5695 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5696 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5697 | (match_operand:QI 2 "general_operand" ""))) | |
4023fb28 UW |
5698 | (clobber (reg:CC 33))] |
5699 | "" | |
8cb66696 | 5700 | "s390_expand_logical_operator (XOR, QImode, operands); DONE;") |
9db1d521 | 5701 | |
19b63d8e UW |
5702 | ; |
5703 | ; Block exclusive or (XC) patterns. | |
5704 | ; | |
5705 | ||
5706 | (define_insn "*xc" | |
5707 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5708 | (xor:BLK (match_dup 0) | |
5709 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5710 | (use (match_operand 2 "const_int_operand" "n")) | |
5711 | (clobber (reg:CC 33))] | |
5712 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5713 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 5714 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5715 | |
5716 | (define_split | |
5717 | [(set (match_operand 0 "memory_operand" "") | |
5718 | (xor (match_dup 0) | |
5719 | (match_operand 1 "memory_operand" ""))) | |
5720 | (clobber (reg:CC 33))] | |
5721 | "reload_completed | |
5722 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5723 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5724 | [(parallel | |
5725 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
5726 | (use (match_dup 2)) | |
5727 | (clobber (reg:CC 33))])] | |
5728 | { | |
5729 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5730 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5731 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5732 | }) | |
5733 | ||
5734 | (define_peephole2 | |
5735 | [(parallel | |
5736 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5737 | (xor:BLK (match_dup 0) | |
5738 | (match_operand:BLK 1 "memory_operand" ""))) | |
5739 | (use (match_operand 2 "const_int_operand" "")) | |
5740 | (clobber (reg:CC 33))]) | |
5741 | (parallel | |
5742 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5743 | (xor:BLK (match_dup 3) | |
5744 | (match_operand:BLK 4 "memory_operand" ""))) | |
5745 | (use (match_operand 5 "const_int_operand" "")) | |
5746 | (clobber (reg:CC 33))])] | |
5747 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
5748 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5749 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5750 | [(parallel | |
5751 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
5752 | (use (match_dup 8)) | |
5753 | (clobber (reg:CC 33))])] | |
5754 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5755 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5756 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5757 | ||
5758 | ; | |
5759 | ; Block xor (XC) patterns with src == dest. | |
5760 | ; | |
5761 | ||
5762 | (define_insn "*xc_zero" | |
5763 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5764 | (const_int 0)) | |
5765 | (use (match_operand 1 "const_int_operand" "n")) | |
5766 | (clobber (reg:CC 33))] | |
5767 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" | |
fc0ea003 | 5768 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 5769 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5770 | |
5771 | (define_peephole2 | |
5772 | [(parallel | |
5773 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5774 | (const_int 0)) | |
5775 | (use (match_operand 1 "const_int_operand" "")) | |
5776 | (clobber (reg:CC 33))]) | |
5777 | (parallel | |
5778 | [(set (match_operand:BLK 2 "memory_operand" "") | |
5779 | (const_int 0)) | |
5780 | (use (match_operand 3 "const_int_operand" "")) | |
5781 | (clobber (reg:CC 33))])] | |
5782 | "s390_offset_p (operands[0], operands[2], operands[1]) | |
5783 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
5784 | [(parallel | |
5785 | [(set (match_dup 4) (const_int 0)) | |
5786 | (use (match_dup 5)) | |
5787 | (clobber (reg:CC 33))])] | |
5788 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5789 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
5790 | ||
9db1d521 HP |
5791 | |
5792 | ;; | |
5793 | ;;- Negate instructions. | |
5794 | ;; | |
5795 | ||
5796 | ; | |
9a91a21f | 5797 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
5798 | ; |
5799 | ||
9a91a21f | 5800 | (define_expand "neg<mode>2" |
9db1d521 | 5801 | [(parallel |
9a91a21f AS |
5802 | [(set (match_operand:DSI 0 "register_operand" "=d") |
5803 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
9db1d521 HP |
5804 | (clobber (reg:CC 33))])] |
5805 | "" | |
5806 | "") | |
5807 | ||
26a89301 UW |
5808 | (define_insn "*negdi2_sign_cc" |
5809 | [(set (reg 33) | |
5810 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
5811 | (match_operand:SI 1 "register_operand" "d") 0) | |
5812 | (const_int 32)) (const_int 32))) | |
5813 | (const_int 0))) | |
5814 | (set (match_operand:DI 0 "register_operand" "=d") | |
5815 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
5816 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5817 | "lcgfr\t%0,%1" | |
5818 | [(set_attr "op_type" "RRE")]) | |
5819 | ||
5820 | (define_insn "*negdi2_sign" | |
5821 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5822 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
5823 | (clobber (reg:CC 33))] | |
5824 | "TARGET_64BIT" | |
5825 | "lcgfr\t%0,%1" | |
5826 | [(set_attr "op_type" "RRE")]) | |
5827 | ||
9a91a21f | 5828 | (define_insn "*neg<mode>2_cc" |
26a89301 | 5829 | [(set (reg 33) |
9a91a21f | 5830 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5831 | (const_int 0))) |
9a91a21f AS |
5832 | (set (match_operand:GPR 0 "register_operand" "=d") |
5833 | (neg:GPR (match_dup 1)))] | |
5834 | "s390_match_ccmode (insn, CCAmode)" | |
5835 | "lc<g>r\t%0,%1" | |
5836 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5837 | |
9a91a21f | 5838 | (define_insn "*neg<mode>2_cconly" |
26a89301 | 5839 | [(set (reg 33) |
9a91a21f | 5840 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5841 | (const_int 0))) |
9a91a21f AS |
5842 | (clobber (match_scratch:GPR 0 "=d"))] |
5843 | "s390_match_ccmode (insn, CCAmode)" | |
5844 | "lc<g>r\t%0,%1" | |
5845 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5846 | |
9a91a21f AS |
5847 | (define_insn "*neg<mode>2" |
5848 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5849 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
9db1d521 | 5850 | (clobber (reg:CC 33))] |
9a91a21f AS |
5851 | "" |
5852 | "lc<g>r\t%0,%1" | |
5853 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 5854 | |
26a89301 | 5855 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
5856 | [(set (match_operand:DI 0 "register_operand" "=d") |
5857 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5858 | (clobber (reg:CC 33))] | |
5859 | "!TARGET_64BIT" | |
26a89301 UW |
5860 | "#" |
5861 | "&& reload_completed" | |
5862 | [(parallel | |
5863 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
5864 | (clobber (reg:CC 33))]) | |
5865 | (parallel | |
5866 | [(set (reg:CCAP 33) | |
5867 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) | |
5868 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
5869 | (set (pc) | |
5870 | (if_then_else (ne (reg:CCAP 33) (const_int 0)) | |
5871 | (pc) | |
5872 | (label_ref (match_dup 6)))) | |
5873 | (parallel | |
5874 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
5875 | (clobber (reg:CC 33))]) | |
5876 | (match_dup 6)] | |
5877 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
5878 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
5879 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
5880 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
5881 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 5882 | |
9db1d521 HP |
5883 | ; |
5884 | ; negdf2 instruction pattern(s). | |
5885 | ; | |
5886 | ||
5887 | (define_expand "negdf2" | |
5888 | [(parallel | |
5889 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5890 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5891 | (clobber (reg:CC 33))])] | |
5892 | "TARGET_HARD_FLOAT" | |
5893 | "") | |
5894 | ||
26a89301 UW |
5895 | (define_insn "*negdf2_cc" |
5896 | [(set (reg 33) | |
5897 | (compare (neg:DF (match_operand:DF 1 "register_operand" "f")) | |
5898 | (match_operand:DF 2 "const0_operand" ""))) | |
5899 | (set (match_operand:DF 0 "register_operand" "=f") | |
5900 | (neg:DF (match_dup 1)))] | |
5901 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5902 | "lcdbr\t%0,%1" | |
5903 | [(set_attr "op_type" "RRE") | |
5904 | (set_attr "type" "fsimpd")]) | |
5905 | ||
5906 | (define_insn "*negdf2_cconly" | |
5907 | [(set (reg 33) | |
5908 | (compare (neg:DF (match_operand:DF 1 "register_operand" "f")) | |
5909 | (match_operand:DF 2 "const0_operand" ""))) | |
5910 | (clobber (match_scratch:DF 0 "=f"))] | |
5911 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5912 | "lcdbr\t%0,%1" | |
5913 | [(set_attr "op_type" "RRE") | |
5914 | (set_attr "type" "fsimpd")]) | |
5915 | ||
9db1d521 HP |
5916 | (define_insn "*negdf2" |
5917 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5918 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5919 | (clobber (reg:CC 33))] | |
5920 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5921 | "lcdbr\t%0,%1" |
077dab3b HP |
5922 | [(set_attr "op_type" "RRE") |
5923 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5924 | |
5925 | (define_insn "*negdf2_ibm" | |
5926 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5927 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5928 | (clobber (reg:CC 33))] | |
5929 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5930 | "lcdr\t%0,%1" |
077dab3b HP |
5931 | [(set_attr "op_type" "RR") |
5932 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5933 | |
5934 | ; | |
5935 | ; negsf2 instruction pattern(s). | |
5936 | ; | |
5937 | ||
5938 | (define_expand "negsf2" | |
5939 | [(parallel | |
5940 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5941 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5942 | (clobber (reg:CC 33))])] | |
5943 | "TARGET_HARD_FLOAT" | |
5944 | "") | |
5945 | ||
26a89301 UW |
5946 | (define_insn "*negsf2_cc" |
5947 | [(set (reg 33) | |
5948 | (compare (neg:SF (match_operand:SF 1 "register_operand" "f")) | |
5949 | (match_operand:SF 2 "const0_operand" ""))) | |
5950 | (set (match_operand:SF 0 "register_operand" "=f") | |
5951 | (neg:SF (match_dup 1)))] | |
5952 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5953 | "lcebr\t%0,%1" | |
5954 | [(set_attr "op_type" "RRE") | |
5955 | (set_attr "type" "fsimps")]) | |
5956 | ||
5957 | (define_insn "*negsf2_cconly" | |
5958 | [(set (reg 33) | |
5959 | (compare (neg:SF (match_operand:SF 1 "register_operand" "f")) | |
5960 | (match_operand:SF 2 "const0_operand" ""))) | |
5961 | (clobber (match_scratch:SF 0 "=f"))] | |
5962 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
5963 | "lcebr\t%0,%1" | |
5964 | [(set_attr "op_type" "RRE") | |
5965 | (set_attr "type" "fsimps")]) | |
5966 | ||
9db1d521 HP |
5967 | (define_insn "*negsf2" |
5968 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5969 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5970 | (clobber (reg:CC 33))] | |
5971 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5972 | "lcebr\t%0,%1" |
077dab3b HP |
5973 | [(set_attr "op_type" "RRE") |
5974 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5975 | |
5976 | (define_insn "*negsf2" | |
5977 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5978 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5979 | (clobber (reg:CC 33))] | |
5980 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5981 | "lcer\t%0,%1" |
077dab3b HP |
5982 | [(set_attr "op_type" "RR") |
5983 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5984 | |
5985 | ||
5986 | ;; | |
5987 | ;;- Absolute value instructions. | |
5988 | ;; | |
5989 | ||
5990 | ; | |
9a91a21f | 5991 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
5992 | ; |
5993 | ||
26a89301 UW |
5994 | (define_insn "*absdi2_sign_cc" |
5995 | [(set (reg 33) | |
5996 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
5997 | (match_operand:SI 1 "register_operand" "d") 0) | |
5998 | (const_int 32)) (const_int 32))) | |
5999 | (const_int 0))) | |
6000 | (set (match_operand:DI 0 "register_operand" "=d") | |
6001 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
6002 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6003 | "lpgfr\t%0,%1" | |
6004 | [(set_attr "op_type" "RRE")]) | |
6005 | ||
6006 | (define_insn "*absdi2_sign" | |
6007 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6008 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
6009 | (clobber (reg:CC 33))] | |
6010 | "TARGET_64BIT" | |
6011 | "lpgfr\t%0,%1" | |
6012 | [(set_attr "op_type" "RRE")]) | |
6013 | ||
9a91a21f | 6014 | (define_insn "*abs<mode>2_cc" |
26a89301 | 6015 | [(set (reg 33) |
9a91a21f | 6016 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 6017 | (const_int 0))) |
9a91a21f AS |
6018 | (set (match_operand:GPR 0 "register_operand" "=d") |
6019 | (abs:GPR (match_dup 1)))] | |
26a89301 | 6020 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6021 | "lp<g>r\t%0,%1" |
6022 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6023 | |
9a91a21f | 6024 | (define_insn "*abs<mode>2_cconly" |
26a89301 | 6025 | [(set (reg 33) |
9a91a21f | 6026 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6027 | (const_int 0))) |
9a91a21f | 6028 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6029 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6030 | "lp<g>r\t%0,%1" |
6031 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6032 | |
9a91a21f AS |
6033 | (define_insn "abs<mode>2" |
6034 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6035 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
9db1d521 HP |
6036 | (clobber (reg:CC 33))] |
6037 | "" | |
9a91a21f AS |
6038 | "lp<g>r\t%0,%1" |
6039 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 6040 | |
9db1d521 HP |
6041 | ; |
6042 | ; absdf2 instruction pattern(s). | |
6043 | ; | |
6044 | ||
6045 | (define_expand "absdf2" | |
6046 | [(parallel | |
6047 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6048 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6049 | (clobber (reg:CC 33))])] | |
6050 | "TARGET_HARD_FLOAT" | |
6051 | "") | |
6052 | ||
26a89301 UW |
6053 | (define_insn "*absdf2_cc" |
6054 | [(set (reg 33) | |
6055 | (compare (abs:DF (match_operand:DF 1 "register_operand" "f")) | |
6056 | (match_operand:DF 2 "const0_operand" ""))) | |
6057 | (set (match_operand:DF 0 "register_operand" "=f") | |
6058 | (abs:DF (match_dup 1)))] | |
6059 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6060 | "lpdbr\t%0,%1" | |
6061 | [(set_attr "op_type" "RRE") | |
6062 | (set_attr "type" "fsimpd")]) | |
6063 | ||
6064 | (define_insn "*absdf2_cconly" | |
6065 | [(set (reg 33) | |
6066 | (compare (abs:DF (match_operand:DF 1 "register_operand" "f")) | |
6067 | (match_operand:DF 2 "const0_operand" ""))) | |
6068 | (clobber (match_scratch:DF 0 "=f"))] | |
6069 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6070 | "lpdbr\t%0,%1" | |
6071 | [(set_attr "op_type" "RRE") | |
6072 | (set_attr "type" "fsimpd")]) | |
6073 | ||
9db1d521 HP |
6074 | (define_insn "*absdf2" |
6075 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6076 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6077 | (clobber (reg:CC 33))] | |
6078 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6079 | "lpdbr\t%0,%1" |
077dab3b HP |
6080 | [(set_attr "op_type" "RRE") |
6081 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6082 | |
6083 | (define_insn "*absdf2_ibm" | |
6084 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6085 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6086 | (clobber (reg:CC 33))] | |
6087 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6088 | "lpdr\t%0,%1" |
077dab3b HP |
6089 | [(set_attr "op_type" "RR") |
6090 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6091 | |
6092 | ; | |
6093 | ; abssf2 instruction pattern(s). | |
6094 | ; | |
6095 | ||
6096 | (define_expand "abssf2" | |
6097 | [(parallel | |
6098 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6099 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6100 | (clobber (reg:CC 33))])] | |
6101 | "TARGET_HARD_FLOAT" | |
6102 | "") | |
6103 | ||
26a89301 UW |
6104 | (define_insn "*abssf2_cc" |
6105 | [(set (reg 33) | |
6106 | (compare (abs:SF (match_operand:SF 1 "register_operand" "f")) | |
6107 | (match_operand:SF 2 "const0_operand" ""))) | |
6108 | (set (match_operand:SF 0 "register_operand" "=f") | |
6109 | (abs:SF (match_dup 1)))] | |
6110 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6111 | "lpebr\t%0,%1" | |
6112 | [(set_attr "op_type" "RRE") | |
6113 | (set_attr "type" "fsimps")]) | |
6114 | ||
6115 | (define_insn "*abssf2_cconly" | |
6116 | [(set (reg 33) | |
6117 | (compare (abs:SF (match_operand:SF 1 "register_operand" "f")) | |
6118 | (match_operand:SF 2 "const0_operand" ""))) | |
6119 | (clobber (match_scratch:SF 0 "=f"))] | |
6120 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6121 | "lpebr\t%0,%1" | |
6122 | [(set_attr "op_type" "RRE") | |
6123 | (set_attr "type" "fsimps")]) | |
6124 | ||
9db1d521 HP |
6125 | (define_insn "*abssf2" |
6126 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6127 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6128 | (clobber (reg:CC 33))] | |
6129 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6130 | "lpebr\t%0,%1" |
077dab3b HP |
6131 | [(set_attr "op_type" "RRE") |
6132 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
6133 | |
6134 | (define_insn "*abssf2_ibm" | |
6135 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6136 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6137 | (clobber (reg:CC 33))] | |
6138 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6139 | "lper\t%0,%1" |
077dab3b HP |
6140 | [(set_attr "op_type" "RR") |
6141 | (set_attr "type" "fsimps")]) | |
9db1d521 | 6142 | |
3ef093a8 AK |
6143 | ;; |
6144 | ;;- Negated absolute value instructions | |
6145 | ;; | |
6146 | ||
6147 | ; | |
6148 | ; Integer | |
6149 | ; | |
6150 | ||
26a89301 UW |
6151 | (define_insn "*negabsdi2_sign_cc" |
6152 | [(set (reg 33) | |
6153 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6154 | (match_operand:SI 1 "register_operand" "d") 0) | |
6155 | (const_int 32)) (const_int 32)))) | |
6156 | (const_int 0))) | |
6157 | (set (match_operand:DI 0 "register_operand" "=d") | |
6158 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6159 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6160 | "lngfr\t%0,%1" | |
6161 | [(set_attr "op_type" "RRE")]) | |
6162 | ||
6163 | (define_insn "*negabsdi2_sign" | |
6164 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6165 | (neg:DI (abs:DI (sign_extend:DI | |
6166 | (match_operand:SI 1 "register_operand" "d"))))) | |
3ef093a8 | 6167 | (clobber (reg:CC 33))] |
26a89301 UW |
6168 | "TARGET_64BIT" |
6169 | "lngfr\t%0,%1" | |
6170 | [(set_attr "op_type" "RRE")]) | |
3ef093a8 | 6171 | |
9a91a21f | 6172 | (define_insn "*negabs<mode>2_cc" |
26a89301 | 6173 | [(set (reg 33) |
9a91a21f | 6174 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6175 | (const_int 0))) |
9a91a21f AS |
6176 | (set (match_operand:GPR 0 "register_operand" "=d") |
6177 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 6178 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6179 | "ln<g>r\t%0,%1" |
6180 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6181 | |
9a91a21f | 6182 | (define_insn "*negabs<mode>2_cconly" |
26a89301 | 6183 | [(set (reg 33) |
9a91a21f | 6184 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6185 | (const_int 0))) |
9a91a21f | 6186 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6187 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6188 | "ln<g>r\t%0,%1" |
6189 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6190 | |
9a91a21f AS |
6191 | (define_insn "*negabs<mode>2" |
6192 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6193 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
26a89301 UW |
6194 | (clobber (reg:CC 33))] |
6195 | "" | |
9a91a21f AS |
6196 | "ln<g>r\t%0,%1" |
6197 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6198 | |
3ef093a8 AK |
6199 | ; |
6200 | ; Floating point | |
6201 | ; | |
6202 | ||
26a89301 UW |
6203 | (define_insn "*negabsdf2_cc" |
6204 | [(set (reg 33) | |
6205 | (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6206 | (match_operand:DF 2 "const0_operand" ""))) | |
6207 | (set (match_operand:DF 0 "register_operand" "=f") | |
6208 | (neg:DF (abs:DF (match_dup 1))))] | |
6209 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6210 | "lndbr\t%0,%1" | |
3ef093a8 | 6211 | [(set_attr "op_type" "RRE") |
26a89301 UW |
6212 | (set_attr "type" "fsimpd")]) |
6213 | ||
6214 | (define_insn "*negabsdf2_cconly" | |
6215 | [(set (reg 33) | |
6216 | (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6217 | (match_operand:DF 2 "const0_operand" ""))) | |
6218 | (clobber (match_scratch:DF 0 "=f"))] | |
6219 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6220 | "lndbr\t%0,%1" | |
6221 | [(set_attr "op_type" "RRE") | |
6222 | (set_attr "type" "fsimpd")]) | |
6223 | ||
3ef093a8 AK |
6224 | (define_insn "*negabsdf2" |
6225 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6226 | (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) | |
6227 | (clobber (reg:CC 33))] | |
6228 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6229 | "lndbr\t%0,%1" |
3ef093a8 AK |
6230 | [(set_attr "op_type" "RRE") |
6231 | (set_attr "type" "fsimpd")]) | |
6232 | ||
26a89301 UW |
6233 | (define_insn "*negabssf2_cc" |
6234 | [(set (reg 33) | |
6235 | (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6236 | (match_operand:SF 2 "const0_operand" ""))) | |
6237 | (set (match_operand:SF 0 "register_operand" "=f") | |
6238 | (neg:SF (abs:SF (match_dup 1))))] | |
6239 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6240 | "lnebr\t%0,%1" | |
6241 | [(set_attr "op_type" "RRE") | |
6242 | (set_attr "type" "fsimps")]) | |
6243 | ||
6244 | (define_insn "*negabssf2_cconly" | |
6245 | [(set (reg 33) | |
6246 | (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6247 | (match_operand:SF 2 "const0_operand" ""))) | |
6248 | (clobber (match_scratch:SF 0 "=f"))] | |
6249 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6250 | "lnebr\t%0,%1" | |
6251 | [(set_attr "op_type" "RRE") | |
6252 | (set_attr "type" "fsimps")]) | |
6253 | ||
6254 | (define_insn "*negabssf2" | |
6255 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6256 | (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) | |
6257 | (clobber (reg:CC 33))] | |
6258 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6259 | "lnebr\t%0,%1" | |
6260 | [(set_attr "op_type" "RRE") | |
6261 | (set_attr "type" "fsimps")]) | |
6262 | ||
4023fb28 UW |
6263 | ;; |
6264 | ;;- Square root instructions. | |
6265 | ;; | |
6266 | ||
6267 | ; | |
6268 | ; sqrtdf2 instruction pattern(s). | |
6269 | ; | |
6270 | ||
6271 | (define_insn "sqrtdf2" | |
6272 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 6273 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6274 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6275 | "@ | |
d40c829f UW |
6276 | sqdbr\t%0,%1 |
6277 | sqdb\t%0,%1" | |
a036c6f7 UW |
6278 | [(set_attr "op_type" "RRE,RXE") |
6279 | (set_attr "type" "fsqrtd")]) | |
4023fb28 UW |
6280 | |
6281 | ; | |
6282 | ; sqrtsf2 instruction pattern(s). | |
6283 | ; | |
6284 | ||
6285 | (define_insn "sqrtsf2" | |
6286 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 6287 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6288 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6289 | "@ | |
d40c829f UW |
6290 | sqebr\t%0,%1 |
6291 | sqeb\t%0,%1" | |
a036c6f7 UW |
6292 | [(set_attr "op_type" "RRE,RXE") |
6293 | (set_attr "type" "fsqrts")]) | |
9db1d521 HP |
6294 | |
6295 | ;; | |
6296 | ;;- One complement instructions. | |
6297 | ;; | |
6298 | ||
6299 | ; | |
342cf42b | 6300 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 6301 | ; |
c7453384 | 6302 | |
342cf42b | 6303 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 6304 | [(parallel |
342cf42b AS |
6305 | [(set (match_operand:INT 0 "register_operand" "") |
6306 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
6307 | (const_int -1))) | |
4023fb28 | 6308 | (clobber (reg:CC 33))])] |
9db1d521 | 6309 | "" |
4023fb28 | 6310 | "") |
9db1d521 HP |
6311 | |
6312 | ||
6313 | ;; | |
6314 | ;;- Rotate instructions. | |
6315 | ;; | |
6316 | ||
6317 | ; | |
9a91a21f | 6318 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
6319 | ; |
6320 | ||
9a91a21f AS |
6321 | (define_insn "rotl<mode>3" |
6322 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6323 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
6324 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9e8327e3 | 6325 | "TARGET_CPU_ZARCH" |
9a91a21f | 6326 | "rll<g>\t%0,%1,%Y2" |
077dab3b HP |
6327 | [(set_attr "op_type" "RSE") |
6328 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6329 | |
6330 | ||
6331 | ;; | |
6332 | ;;- Arithmetic shift instructions. | |
6333 | ;; | |
9db1d521 HP |
6334 | |
6335 | ; | |
6336 | ; ashldi3 instruction pattern(s). | |
6337 | ; | |
6338 | ||
6339 | (define_expand "ashldi3" | |
ecbe845e UW |
6340 | [(set (match_operand:DI 0 "register_operand" "") |
6341 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6342 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6343 | "" |
6344 | "") | |
6345 | ||
6346 | (define_insn "*ashldi3_31" | |
ac32b25e UW |
6347 | [(set (match_operand:DI 0 "register_operand" "=d") |
6348 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
6349 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6350 | "!TARGET_64BIT" |
ac32b25e | 6351 | "sldl\t%0,%Y2" |
077dab3b HP |
6352 | [(set_attr "op_type" "RS") |
6353 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6354 | |
6355 | (define_insn "*ashldi3_64" | |
ac32b25e UW |
6356 | [(set (match_operand:DI 0 "register_operand" "=d") |
6357 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
6358 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6359 | "TARGET_64BIT" |
ac32b25e | 6360 | "sllg\t%0,%1,%Y2" |
077dab3b HP |
6361 | [(set_attr "op_type" "RSE") |
6362 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6363 | |
6364 | ; | |
6365 | ; ashrdi3 instruction pattern(s). | |
6366 | ; | |
6367 | ||
6368 | (define_expand "ashrdi3" | |
6369 | [(parallel | |
6370 | [(set (match_operand:DI 0 "register_operand" "") | |
6371 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6372 | (match_operand:SI 2 "shift_count_operand" ""))) |
9db1d521 HP |
6373 | (clobber (reg:CC 33))])] |
6374 | "" | |
6375 | "") | |
6376 | ||
ecbe845e UW |
6377 | (define_insn "*ashrdi3_cc_31" |
6378 | [(set (reg 33) | |
ac32b25e UW |
6379 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6380 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6381 | (const_int 0))) |
ac32b25e | 6382 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6383 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6384 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6385 | "srda\t%0,%Y2" |
077dab3b HP |
6386 | [(set_attr "op_type" "RS") |
6387 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6388 | |
6389 | (define_insn "*ashrdi3_cconly_31" | |
6390 | [(set (reg 33) | |
ac32b25e UW |
6391 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6392 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6393 | (const_int 0))) |
ac32b25e | 6394 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6395 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6396 | "srda\t%0,%Y2" |
077dab3b HP |
6397 | [(set_attr "op_type" "RS") |
6398 | (set_attr "atype" "reg")]) | |
ecbe845e | 6399 | |
9db1d521 | 6400 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6401 | [(set (match_operand:DI 0 "register_operand" "=d") |
6402 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6403 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6404 | (clobber (reg:CC 33))] |
6405 | "!TARGET_64BIT" | |
ac32b25e | 6406 | "srda\t%0,%Y2" |
077dab3b HP |
6407 | [(set_attr "op_type" "RS") |
6408 | (set_attr "atype" "reg")]) | |
c7453384 | 6409 | |
ecbe845e UW |
6410 | (define_insn "*ashrdi3_cc_64" |
6411 | [(set (reg 33) | |
ac32b25e UW |
6412 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6413 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6414 | (const_int 0))) |
ac32b25e | 6415 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6416 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6417 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
ac32b25e | 6418 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6419 | [(set_attr "op_type" "RSE") |
6420 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6421 | |
6422 | (define_insn "*ashrdi3_cconly_64" | |
6423 | [(set (reg 33) | |
ac32b25e UW |
6424 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6425 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6426 | (const_int 0))) |
ac32b25e | 6427 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6428 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
ac32b25e | 6429 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6430 | [(set_attr "op_type" "RSE") |
6431 | (set_attr "atype" "reg")]) | |
ecbe845e | 6432 | |
9db1d521 | 6433 | (define_insn "*ashrdi3_64" |
ac32b25e UW |
6434 | [(set (match_operand:DI 0 "register_operand" "=d") |
6435 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6436 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6437 | (clobber (reg:CC 33))] |
6438 | "TARGET_64BIT" | |
ac32b25e | 6439 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6440 | [(set_attr "op_type" "RSE") |
6441 | (set_attr "atype" "reg")]) | |
6442 | ||
9db1d521 HP |
6443 | |
6444 | ; | |
6445 | ; ashlsi3 instruction pattern(s). | |
6446 | ; | |
9db1d521 HP |
6447 | |
6448 | (define_insn "ashlsi3" | |
ac32b25e UW |
6449 | [(set (match_operand:SI 0 "register_operand" "=d") |
6450 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
6451 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6452 | "" |
ac32b25e | 6453 | "sll\t%0,%Y2" |
077dab3b HP |
6454 | [(set_attr "op_type" "RS") |
6455 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6456 | |
6457 | ; | |
6458 | ; ashrsi3 instruction pattern(s). | |
6459 | ; | |
6460 | ||
ecbe845e UW |
6461 | (define_insn "*ashrsi3_cc" |
6462 | [(set (reg 33) | |
ac32b25e UW |
6463 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6464 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6465 | (const_int 0))) |
ac32b25e | 6466 | (set (match_operand:SI 0 "register_operand" "=d") |
ecbe845e UW |
6467 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
6468 | "s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6469 | "sra\t%0,%Y2" |
077dab3b HP |
6470 | [(set_attr "op_type" "RS") |
6471 | (set_attr "atype" "reg")]) | |
6472 | ||
ecbe845e UW |
6473 | |
6474 | (define_insn "*ashrsi3_cconly" | |
6475 | [(set (reg 33) | |
ac32b25e UW |
6476 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6477 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6478 | (const_int 0))) |
ac32b25e | 6479 | (clobber (match_scratch:SI 0 "=d"))] |
ecbe845e | 6480 | "s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6481 | "sra\t%0,%Y2" |
077dab3b HP |
6482 | [(set_attr "op_type" "RS") |
6483 | (set_attr "atype" "reg")]) | |
ecbe845e | 6484 | |
9db1d521 | 6485 | (define_insn "ashrsi3" |
ac32b25e UW |
6486 | [(set (match_operand:SI 0 "register_operand" "=d") |
6487 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6488 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6489 | (clobber (reg:CC 33))] |
6490 | "" | |
ac32b25e | 6491 | "sra\t%0,%Y2" |
077dab3b HP |
6492 | [(set_attr "op_type" "RS") |
6493 | (set_attr "atype" "reg")]) | |
9db1d521 | 6494 | |
9db1d521 HP |
6495 | |
6496 | ;; | |
6497 | ;;- logical shift instructions. | |
6498 | ;; | |
6499 | ||
6500 | ; | |
6501 | ; lshrdi3 instruction pattern(s). | |
6502 | ; | |
6503 | ||
6504 | (define_expand "lshrdi3" | |
ecbe845e UW |
6505 | [(set (match_operand:DI 0 "register_operand" "") |
6506 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6507 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6508 | "" |
6509 | "") | |
6510 | ||
6511 | (define_insn "*lshrdi3_31" | |
ac32b25e UW |
6512 | [(set (match_operand:DI 0 "register_operand" "=d") |
6513 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6514 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6515 | "!TARGET_64BIT" |
ac32b25e UW |
6516 | "srdl\t%0,%Y2" |
6517 | [(set_attr "op_type" "RS") | |
077dab3b | 6518 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6519 | |
6520 | (define_insn "*lshrdi3_64" | |
ac32b25e UW |
6521 | [(set (match_operand:DI 0 "register_operand" "=d") |
6522 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6523 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6524 | "TARGET_64BIT" |
ac32b25e UW |
6525 | "srlg\t%0,%1,%Y2" |
6526 | [(set_attr "op_type" "RSE") | |
077dab3b | 6527 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6528 | |
6529 | ; | |
6530 | ; lshrsi3 instruction pattern(s). | |
6531 | ; | |
6532 | ||
6533 | (define_insn "lshrsi3" | |
ac32b25e UW |
6534 | [(set (match_operand:SI 0 "register_operand" "=d") |
6535 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6536 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6537 | "" |
ac32b25e | 6538 | "srl\t%0,%Y2" |
077dab3b HP |
6539 | [(set_attr "op_type" "RS") |
6540 | (set_attr "atype" "reg")]) | |
9db1d521 | 6541 | |
9db1d521 HP |
6542 | |
6543 | ;; | |
6544 | ;; Branch instruction patterns. | |
6545 | ;; | |
6546 | ||
fa77b251 AS |
6547 | (define_expand "b<code>" |
6548 | [(set (pc) | |
6549 | (if_then_else (COMPARE (match_operand 0 "" "") | |
6550 | (const_int 0)) | |
6551 | (match_dup 0) | |
6552 | (pc)))] | |
ba956982 | 6553 | "" |
6590e19a | 6554 | "s390_emit_jump (operands[0], |
fa77b251 | 6555 | s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;") |
ba956982 | 6556 | |
9db1d521 HP |
6557 | |
6558 | ;; | |
6559 | ;;- Conditional jump instructions. | |
6560 | ;; | |
6561 | ||
6590e19a UW |
6562 | (define_insn "*cjump_64" |
6563 | [(set (pc) | |
6564 | (if_then_else | |
5b022de5 | 6565 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6566 | (label_ref (match_operand 0 "" "")) |
6567 | (pc)))] | |
6568 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6569 | { |
13e58269 | 6570 | if (get_attr_length (insn) == 4) |
d40c829f | 6571 | return "j%C1\t%l0"; |
6590e19a | 6572 | else |
d40c829f | 6573 | return "jg%C1\t%l0"; |
6590e19a UW |
6574 | } |
6575 | [(set_attr "op_type" "RI") | |
6576 | (set_attr "type" "branch") | |
6577 | (set (attr "length") | |
6578 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6579 | (const_int 4) (const_int 6)))]) | |
6580 | ||
6581 | (define_insn "*cjump_31" | |
6582 | [(set (pc) | |
6583 | (if_then_else | |
5b022de5 | 6584 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6585 | (label_ref (match_operand 0 "" "")) |
6586 | (pc)))] | |
6587 | "!TARGET_CPU_ZARCH" | |
6588 | { | |
6589 | if (get_attr_length (insn) == 4) | |
6590 | return "j%C1\t%l0"; | |
9db1d521 | 6591 | else |
13e58269 | 6592 | abort (); |
10bbf137 | 6593 | } |
9db1d521 | 6594 | [(set_attr "op_type" "RI") |
077dab3b | 6595 | (set_attr "type" "branch") |
13e58269 | 6596 | (set (attr "length") |
6590e19a UW |
6597 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6598 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6599 | (const_int 4) (const_int 6)) | |
6600 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6601 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6602 | |
f314b9b1 | 6603 | (define_insn "*cjump_long" |
6590e19a UW |
6604 | [(set (pc) |
6605 | (if_then_else | |
5b022de5 | 6606 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6607 | (match_operand 0 "address_operand" "U") |
6608 | (pc)))] | |
9db1d521 | 6609 | "" |
f314b9b1 UW |
6610 | { |
6611 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6612 | return "b%C1r\t%0"; |
f314b9b1 | 6613 | else |
d40c829f | 6614 | return "b%C1\t%a0"; |
10bbf137 | 6615 | } |
c7453384 | 6616 | [(set (attr "op_type") |
f314b9b1 UW |
6617 | (if_then_else (match_operand 0 "register_operand" "") |
6618 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 6619 | (set_attr "type" "branch") |
077dab3b | 6620 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6621 | |
6622 | ||
6623 | ;; | |
6624 | ;;- Negated conditional jump instructions. | |
6625 | ;; | |
6626 | ||
6590e19a UW |
6627 | (define_insn "*icjump_64" |
6628 | [(set (pc) | |
6629 | (if_then_else | |
5b022de5 | 6630 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6631 | (pc) |
6632 | (label_ref (match_operand 0 "" ""))))] | |
6633 | "TARGET_CPU_ZARCH" | |
c7453384 | 6634 | { |
13e58269 | 6635 | if (get_attr_length (insn) == 4) |
d40c829f | 6636 | return "j%D1\t%l0"; |
6590e19a | 6637 | else |
d40c829f | 6638 | return "jg%D1\t%l0"; |
6590e19a UW |
6639 | } |
6640 | [(set_attr "op_type" "RI") | |
6641 | (set_attr "type" "branch") | |
6642 | (set (attr "length") | |
6643 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6644 | (const_int 4) (const_int 6)))]) | |
6645 | ||
6646 | (define_insn "*icjump_31" | |
6647 | [(set (pc) | |
6648 | (if_then_else | |
5b022de5 | 6649 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6650 | (pc) |
6651 | (label_ref (match_operand 0 "" ""))))] | |
6652 | "!TARGET_CPU_ZARCH" | |
6653 | { | |
6654 | if (get_attr_length (insn) == 4) | |
6655 | return "j%D1\t%l0"; | |
9db1d521 | 6656 | else |
13e58269 | 6657 | abort (); |
10bbf137 | 6658 | } |
9db1d521 | 6659 | [(set_attr "op_type" "RI") |
077dab3b | 6660 | (set_attr "type" "branch") |
13e58269 | 6661 | (set (attr "length") |
6590e19a UW |
6662 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6663 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6664 | (const_int 4) (const_int 6)) | |
6665 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6666 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6667 | |
f314b9b1 | 6668 | (define_insn "*icjump_long" |
6590e19a UW |
6669 | [(set (pc) |
6670 | (if_then_else | |
5b022de5 | 6671 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6672 | (pc) |
6673 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 6674 | "" |
f314b9b1 UW |
6675 | { |
6676 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6677 | return "b%D1r\t%0"; |
f314b9b1 | 6678 | else |
d40c829f | 6679 | return "b%D1\t%a0"; |
10bbf137 | 6680 | } |
c7453384 | 6681 | [(set (attr "op_type") |
f314b9b1 UW |
6682 | (if_then_else (match_operand 0 "register_operand" "") |
6683 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6684 | (set_attr "type" "branch") |
6685 | (set_attr "atype" "agen")]) | |
9db1d521 | 6686 | |
4456530d HP |
6687 | ;; |
6688 | ;;- Trap instructions. | |
6689 | ;; | |
6690 | ||
6691 | (define_insn "trap" | |
6692 | [(trap_if (const_int 1) (const_int 0))] | |
6693 | "" | |
d40c829f | 6694 | "j\t.+2" |
6590e19a | 6695 | [(set_attr "op_type" "RI") |
077dab3b | 6696 | (set_attr "type" "branch")]) |
4456530d HP |
6697 | |
6698 | (define_expand "conditional_trap" | |
6590e19a UW |
6699 | [(trap_if (match_operand 0 "comparison_operator" "") |
6700 | (match_operand 1 "general_operand" ""))] | |
4456530d | 6701 | "" |
4456530d | 6702 | { |
6590e19a UW |
6703 | if (operands[1] != const0_rtx) FAIL; |
6704 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
6705 | s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6706 | }) |
4456530d HP |
6707 | |
6708 | (define_insn "*trap" | |
5b022de5 | 6709 | [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)]) |
4456530d HP |
6710 | (const_int 0))] |
6711 | "" | |
d40c829f | 6712 | "j%C0\t.+2"; |
077dab3b HP |
6713 | [(set_attr "op_type" "RI") |
6714 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6715 | |
6716 | ;; | |
0a3bdf9d | 6717 | ;;- Loop instructions. |
9db1d521 | 6718 | ;; |
0a3bdf9d UW |
6719 | ;; This is all complicated by the fact that since this is a jump insn |
6720 | ;; we must handle our own output reloads. | |
c7453384 | 6721 | |
0a3bdf9d UW |
6722 | (define_expand "doloop_end" |
6723 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6724 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6725 | (use (match_operand 2 "" "")) ; max iterations | |
6726 | (use (match_operand 3 "" "")) ; loop level | |
6727 | (use (match_operand 4 "" ""))] ; label | |
6728 | "" | |
0a3bdf9d | 6729 | { |
6590e19a UW |
6730 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
6731 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
6732 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
6733 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
6734 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
6735 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6736 | else | |
6737 | FAIL; | |
6738 | ||
6739 | DONE; | |
10bbf137 | 6740 | }) |
0a3bdf9d | 6741 | |
6590e19a | 6742 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
6743 | [(set (pc) |
6744 | (if_then_else | |
6745 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6746 | (const_int 1)) | |
6747 | (label_ref (match_operand 0 "" "")) | |
6748 | (pc))) | |
bd446804 | 6749 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 6750 | (plus:SI (match_dup 1) (const_int -1))) |
eb862a88 | 6751 | (clobber (match_scratch:SI 3 "=X,&1")) |
0a3bdf9d | 6752 | (clobber (reg:CC 33))] |
6590e19a | 6753 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6754 | { |
6755 | if (which_alternative != 0) | |
10bbf137 | 6756 | return "#"; |
0a3bdf9d | 6757 | else if (get_attr_length (insn) == 4) |
d40c829f | 6758 | return "brct\t%1,%l0"; |
6590e19a | 6759 | else |
545d16ff | 6760 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
6761 | } |
6762 | "&& reload_completed | |
6763 | && (! REG_P (operands[2]) | |
6764 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 6765 | [(parallel [(set (reg:CCAN 33) |
6590e19a UW |
6766 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6767 | (const_int 0))) | |
6768 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6769 | (set (match_dup 2) (match_dup 3)) | |
6770 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6771 | (label_ref (match_dup 0)) | |
6772 | (pc)))] | |
6773 | "" | |
6774 | [(set_attr "op_type" "RI") | |
6775 | (set_attr "type" "branch") | |
6776 | (set (attr "length") | |
6777 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6778 | (const_int 4) (const_int 10)))]) | |
6779 | ||
6780 | (define_insn_and_split "doloop_si31" | |
6781 | [(set (pc) | |
6782 | (if_then_else | |
6783 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6784 | (const_int 1)) | |
6785 | (label_ref (match_operand 0 "" "")) | |
6786 | (pc))) | |
6787 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") | |
6788 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 6789 | (clobber (match_scratch:SI 3 "=X,&1")) |
6590e19a UW |
6790 | (clobber (reg:CC 33))] |
6791 | "!TARGET_CPU_ZARCH" | |
6792 | { | |
6793 | if (which_alternative != 0) | |
6794 | return "#"; | |
6795 | else if (get_attr_length (insn) == 4) | |
6796 | return "brct\t%1,%l0"; | |
0a3bdf9d UW |
6797 | else |
6798 | abort (); | |
10bbf137 | 6799 | } |
6590e19a UW |
6800 | "&& reload_completed |
6801 | && (! REG_P (operands[2]) | |
6802 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 6803 | [(parallel [(set (reg:CCAN 33) |
6590e19a UW |
6804 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6805 | (const_int 0))) | |
6806 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6807 | (set (match_dup 2) (match_dup 3)) | |
6808 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6809 | (label_ref (match_dup 0)) | |
6810 | (pc)))] | |
6811 | "" | |
0a3bdf9d | 6812 | [(set_attr "op_type" "RI") |
077dab3b | 6813 | (set_attr "type" "branch") |
0a3bdf9d | 6814 | (set (attr "length") |
6590e19a UW |
6815 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6816 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6817 | (const_int 4) (const_int 6)) | |
6818 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6819 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6820 | |
0a3bdf9d UW |
6821 | (define_insn "*doloop_si_long" |
6822 | [(set (pc) | |
6823 | (if_then_else | |
6824 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6825 | (const_int 1)) | |
d3632d41 | 6826 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6827 | (pc))) |
6828 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6829 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 6830 | (clobber (match_scratch:SI 3 "=X,&1")) |
0a3bdf9d | 6831 | (clobber (reg:CC 33))] |
6590e19a | 6832 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6833 | { |
6834 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6835 | return "bctr\t%1,%0"; |
0a3bdf9d | 6836 | else |
d40c829f | 6837 | return "bct\t%1,%a0"; |
10bbf137 | 6838 | } |
c7453384 | 6839 | [(set (attr "op_type") |
0a3bdf9d UW |
6840 | (if_then_else (match_operand 0 "register_operand" "") |
6841 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6842 | (set_attr "type" "branch") |
6843 | (set_attr "atype" "agen")]) | |
0a3bdf9d | 6844 | |
6590e19a | 6845 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
6846 | [(set (pc) |
6847 | (if_then_else | |
6848 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6849 | (const_int 1)) | |
6850 | (label_ref (match_operand 0 "" "")) | |
6851 | (pc))) | |
eb862a88 | 6852 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 6853 | (plus:DI (match_dup 1) (const_int -1))) |
eb862a88 | 6854 | (clobber (match_scratch:DI 3 "=X,&1")) |
0a3bdf9d UW |
6855 | (clobber (reg:CC 33))] |
6856 | "TARGET_64BIT" | |
0a3bdf9d UW |
6857 | { |
6858 | if (which_alternative != 0) | |
10bbf137 | 6859 | return "#"; |
0a3bdf9d | 6860 | else if (get_attr_length (insn) == 4) |
d40c829f | 6861 | return "brctg\t%1,%l0"; |
0a3bdf9d | 6862 | else |
545d16ff | 6863 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 6864 | } |
6590e19a | 6865 | "&& reload_completed |
0a3bdf9d UW |
6866 | && (! REG_P (operands[2]) |
6867 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 6868 | [(parallel [(set (reg:CCAN 33) |
0a3bdf9d UW |
6869 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
6870 | (const_int 0))) | |
6871 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6872 | (set (match_dup 2) (match_dup 3)) | |
6873 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6590e19a | 6874 | (label_ref (match_dup 0)) |
0a3bdf9d | 6875 | (pc)))] |
6590e19a UW |
6876 | "" |
6877 | [(set_attr "op_type" "RI") | |
6878 | (set_attr "type" "branch") | |
6879 | (set (attr "length") | |
6880 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6881 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
6882 | |
6883 | ;; | |
6884 | ;;- Unconditional jump instructions. | |
6885 | ;; | |
6886 | ||
6887 | ; | |
6888 | ; jump instruction pattern(s). | |
6889 | ; | |
6890 | ||
6590e19a UW |
6891 | (define_expand "jump" |
6892 | [(match_operand 0 "" "")] | |
9db1d521 | 6893 | "" |
6590e19a UW |
6894 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
6895 | ||
6896 | (define_insn "*jump64" | |
6897 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6898 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6899 | { |
13e58269 | 6900 | if (get_attr_length (insn) == 4) |
d40c829f | 6901 | return "j\t%l0"; |
6590e19a | 6902 | else |
d40c829f | 6903 | return "jg\t%l0"; |
6590e19a UW |
6904 | } |
6905 | [(set_attr "op_type" "RI") | |
6906 | (set_attr "type" "branch") | |
6907 | (set (attr "length") | |
6908 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6909 | (const_int 4) (const_int 6)))]) | |
6910 | ||
6911 | (define_insn "*jump31" | |
6912 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6913 | "!TARGET_CPU_ZARCH" | |
6914 | { | |
6915 | if (get_attr_length (insn) == 4) | |
6916 | return "j\t%l0"; | |
9db1d521 | 6917 | else |
13e58269 | 6918 | abort (); |
10bbf137 | 6919 | } |
9db1d521 | 6920 | [(set_attr "op_type" "RI") |
077dab3b | 6921 | (set_attr "type" "branch") |
13e58269 | 6922 | (set (attr "length") |
6590e19a UW |
6923 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6924 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6925 | (const_int 4) (const_int 6)) | |
6926 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6927 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
6928 | |
6929 | ; | |
6930 | ; indirect-jump instruction pattern(s). | |
6931 | ; | |
6932 | ||
6933 | (define_insn "indirect_jump" | |
d3632d41 | 6934 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6935 | "" |
f314b9b1 UW |
6936 | { |
6937 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6938 | return "br\t%0"; |
f314b9b1 | 6939 | else |
d40c829f | 6940 | return "b\t%a0"; |
10bbf137 | 6941 | } |
c7453384 | 6942 | [(set (attr "op_type") |
f314b9b1 UW |
6943 | (if_then_else (match_operand 0 "register_operand" "") |
6944 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6945 | (set_attr "type" "branch") |
6946 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6947 | |
6948 | ; | |
f314b9b1 | 6949 | ; casesi instruction pattern(s). |
9db1d521 HP |
6950 | ; |
6951 | ||
f314b9b1 | 6952 | (define_insn "casesi_jump" |
d3632d41 | 6953 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 6954 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 6955 | "" |
9db1d521 | 6956 | { |
f314b9b1 | 6957 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 6958 | return "br\t%0"; |
f314b9b1 | 6959 | else |
d40c829f | 6960 | return "b\t%a0"; |
10bbf137 | 6961 | } |
c7453384 | 6962 | [(set (attr "op_type") |
f314b9b1 UW |
6963 | (if_then_else (match_operand 0 "register_operand" "") |
6964 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6965 | (set_attr "type" "branch") |
6966 | (set_attr "atype" "agen")]) | |
9db1d521 | 6967 | |
f314b9b1 UW |
6968 | (define_expand "casesi" |
6969 | [(match_operand:SI 0 "general_operand" "") | |
6970 | (match_operand:SI 1 "general_operand" "") | |
6971 | (match_operand:SI 2 "general_operand" "") | |
6972 | (label_ref (match_operand 3 "" "")) | |
6973 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 6974 | "" |
f314b9b1 UW |
6975 | { |
6976 | rtx index = gen_reg_rtx (SImode); | |
6977 | rtx base = gen_reg_rtx (Pmode); | |
6978 | rtx target = gen_reg_rtx (Pmode); | |
6979 | ||
6980 | emit_move_insn (index, operands[0]); | |
6981 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6982 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 6983 | operands[4]); |
f314b9b1 UW |
6984 | |
6985 | if (Pmode != SImode) | |
6986 | index = convert_to_mode (Pmode, index, 1); | |
6987 | if (GET_CODE (index) != REG) | |
6988 | index = copy_to_mode_reg (Pmode, index); | |
6989 | ||
6990 | if (TARGET_64BIT) | |
6991 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6992 | else | |
a556fd39 | 6993 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 6994 | |
f314b9b1 UW |
6995 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6996 | ||
542a8afa | 6997 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
6998 | emit_move_insn (target, index); |
6999 | ||
7000 | if (flag_pic) | |
7001 | target = gen_rtx_PLUS (Pmode, base, target); | |
7002 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
7003 | ||
7004 | DONE; | |
10bbf137 | 7005 | }) |
9db1d521 HP |
7006 | |
7007 | ||
7008 | ;; | |
7009 | ;;- Jump to subroutine. | |
7010 | ;; | |
7011 | ;; | |
7012 | ||
7013 | ; | |
7014 | ; untyped call instruction pattern(s). | |
7015 | ; | |
7016 | ||
7017 | ;; Call subroutine returning any type. | |
7018 | (define_expand "untyped_call" | |
7019 | [(parallel [(call (match_operand 0 "" "") | |
7020 | (const_int 0)) | |
7021 | (match_operand 1 "" "") | |
7022 | (match_operand 2 "" "")])] | |
7023 | "" | |
9db1d521 HP |
7024 | { |
7025 | int i; | |
7026 | ||
7027 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
7028 | ||
7029 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7030 | { | |
7031 | rtx set = XVECEXP (operands[2], 0, i); | |
7032 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7033 | } | |
7034 | ||
7035 | /* The optimizer does not know that the call sets the function value | |
7036 | registers we stored in the result block. We avoid problems by | |
7037 | claiming that all hard registers are used and clobbered at this | |
7038 | point. */ | |
7039 | emit_insn (gen_blockage ()); | |
7040 | ||
7041 | DONE; | |
10bbf137 | 7042 | }) |
9db1d521 HP |
7043 | |
7044 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7045 | ;; all of memory. This blocks insns from being moved across this point. | |
7046 | ||
7047 | (define_insn "blockage" | |
10bbf137 | 7048 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 7049 | "" |
4023fb28 | 7050 | "" |
d5869ca0 UW |
7051 | [(set_attr "type" "none") |
7052 | (set_attr "length" "0")]) | |
4023fb28 | 7053 | |
9db1d521 | 7054 | ; |
ed9676cf | 7055 | ; sibcall patterns |
9db1d521 HP |
7056 | ; |
7057 | ||
ed9676cf | 7058 | (define_expand "sibcall" |
44b8152b | 7059 | [(call (match_operand 0 "" "") |
ed9676cf | 7060 | (match_operand 1 "" ""))] |
9db1d521 | 7061 | "" |
9db1d521 | 7062 | { |
ed9676cf AK |
7063 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
7064 | DONE; | |
7065 | }) | |
9db1d521 | 7066 | |
ed9676cf AK |
7067 | (define_insn "*sibcall_br" |
7068 | [(call (mem:QI (reg 1)) | |
7069 | (match_operand 0 "const_int_operand" "n"))] | |
2f7e5a0d | 7070 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7071 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
7072 | "br\t%%r1" | |
7073 | [(set_attr "op_type" "RR") | |
7074 | (set_attr "type" "branch") | |
7075 | (set_attr "atype" "agen")]) | |
9db1d521 | 7076 | |
ed9676cf AK |
7077 | (define_insn "*sibcall_brc" |
7078 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7079 | (match_operand 1 "const_int_operand" "n"))] | |
7080 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7081 | "j\t%0" | |
7082 | [(set_attr "op_type" "RI") | |
7083 | (set_attr "type" "branch")]) | |
9db1d521 | 7084 | |
ed9676cf AK |
7085 | (define_insn "*sibcall_brcl" |
7086 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7087 | (match_operand 1 "const_int_operand" "n"))] | |
7088 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7089 | "jg\t%0" | |
7090 | [(set_attr "op_type" "RIL") | |
7091 | (set_attr "type" "branch")]) | |
44b8152b | 7092 | |
ed9676cf AK |
7093 | ; |
7094 | ; sibcall_value patterns | |
7095 | ; | |
9e8327e3 | 7096 | |
ed9676cf AK |
7097 | (define_expand "sibcall_value" |
7098 | [(set (match_operand 0 "" "") | |
7099 | (call (match_operand 1 "" "") | |
7100 | (match_operand 2 "" "")))] | |
7101 | "" | |
7102 | { | |
7103 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 7104 | DONE; |
10bbf137 | 7105 | }) |
9db1d521 | 7106 | |
ed9676cf AK |
7107 | (define_insn "*sibcall_value_br" |
7108 | [(set (match_operand 0 "" "") | |
7109 | (call (mem:QI (reg 1)) | |
7110 | (match_operand 1 "const_int_operand" "n")))] | |
2f7e5a0d | 7111 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7112 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
7113 | "br\t%%r1" | |
7114 | [(set_attr "op_type" "RR") | |
7115 | (set_attr "type" "branch") | |
7116 | (set_attr "atype" "agen")]) | |
7117 | ||
7118 | (define_insn "*sibcall_value_brc" | |
7119 | [(set (match_operand 0 "" "") | |
7120 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7121 | (match_operand 2 "const_int_operand" "n")))] | |
7122 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7123 | "j\t%1" | |
7124 | [(set_attr "op_type" "RI") | |
7125 | (set_attr "type" "branch")]) | |
7126 | ||
7127 | (define_insn "*sibcall_value_brcl" | |
7128 | [(set (match_operand 0 "" "") | |
7129 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7130 | (match_operand 2 "const_int_operand" "n")))] | |
7131 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7132 | "jg\t%1" | |
7133 | [(set_attr "op_type" "RIL") | |
7134 | (set_attr "type" "branch")]) | |
7135 | ||
7136 | ||
7137 | ; | |
7138 | ; call instruction pattern(s). | |
7139 | ; | |
7140 | ||
7141 | (define_expand "call" | |
7142 | [(call (match_operand 0 "" "") | |
7143 | (match_operand 1 "" "")) | |
7144 | (use (match_operand 2 "" ""))] | |
44b8152b | 7145 | "" |
ed9676cf | 7146 | { |
2f7e5a0d | 7147 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
7148 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
7149 | DONE; | |
7150 | }) | |
44b8152b | 7151 | |
9e8327e3 UW |
7152 | (define_insn "*bras" |
7153 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7154 | (match_operand 1 "const_int_operand" "n")) | |
7155 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7156 | "!SIBLING_CALL_P (insn) |
7157 | && TARGET_SMALL_EXEC | |
ed9676cf | 7158 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 7159 | "bras\t%2,%0" |
9db1d521 | 7160 | [(set_attr "op_type" "RI") |
4023fb28 | 7161 | (set_attr "type" "jsr")]) |
9db1d521 | 7162 | |
9e8327e3 UW |
7163 | (define_insn "*brasl" |
7164 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7165 | (match_operand 1 "const_int_operand" "n")) | |
7166 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7167 | "!SIBLING_CALL_P (insn) |
7168 | && TARGET_CPU_ZARCH | |
ed9676cf | 7169 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7170 | "brasl\t%2,%0" |
7171 | [(set_attr "op_type" "RIL") | |
077dab3b | 7172 | (set_attr "type" "jsr")]) |
9db1d521 | 7173 | |
9e8327e3 UW |
7174 | (define_insn "*basr" |
7175 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
7176 | (match_operand 1 "const_int_operand" "n")) | |
7177 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 7178 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7179 | { |
7180 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7181 | return "basr\t%2,%0"; | |
7182 | else | |
7183 | return "bas\t%2,%a0"; | |
7184 | } | |
7185 | [(set (attr "op_type") | |
7186 | (if_then_else (match_operand 0 "register_operand" "") | |
7187 | (const_string "RR") (const_string "RX"))) | |
7188 | (set_attr "type" "jsr") | |
7189 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7190 | |
7191 | ; | |
7192 | ; call_value instruction pattern(s). | |
7193 | ; | |
7194 | ||
7195 | (define_expand "call_value" | |
44b8152b UW |
7196 | [(set (match_operand 0 "" "") |
7197 | (call (match_operand 1 "" "") | |
7198 | (match_operand 2 "" ""))) | |
7199 | (use (match_operand 3 "" ""))] | |
9db1d521 | 7200 | "" |
9db1d521 | 7201 | { |
2f7e5a0d | 7202 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 7203 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 7204 | DONE; |
10bbf137 | 7205 | }) |
9db1d521 | 7206 | |
9e8327e3 | 7207 | (define_insn "*bras_r" |
c19ec8f9 | 7208 | [(set (match_operand 0 "" "") |
9e8327e3 | 7209 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7210 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 7211 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
7212 | "!SIBLING_CALL_P (insn) |
7213 | && TARGET_SMALL_EXEC | |
ed9676cf | 7214 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7215 | "bras\t%3,%1" |
9db1d521 | 7216 | [(set_attr "op_type" "RI") |
f2d3c02a | 7217 | (set_attr "type" "jsr")]) |
9db1d521 | 7218 | |
9e8327e3 | 7219 | (define_insn "*brasl_r" |
c19ec8f9 | 7220 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7221 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7222 | (match_operand 2 "const_int_operand" "n"))) | |
7223 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
7224 | "!SIBLING_CALL_P (insn) |
7225 | && TARGET_CPU_ZARCH | |
ed9676cf | 7226 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7227 | "brasl\t%3,%1" |
7228 | [(set_attr "op_type" "RIL") | |
077dab3b | 7229 | (set_attr "type" "jsr")]) |
9db1d521 | 7230 | |
9e8327e3 | 7231 | (define_insn "*basr_r" |
c19ec8f9 | 7232 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7233 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7234 | (match_operand 2 "const_int_operand" "n"))) | |
7235 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 7236 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7237 | { |
7238 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7239 | return "basr\t%3,%1"; | |
7240 | else | |
7241 | return "bas\t%3,%a1"; | |
7242 | } | |
7243 | [(set (attr "op_type") | |
7244 | (if_then_else (match_operand 1 "register_operand" "") | |
7245 | (const_string "RR") (const_string "RX"))) | |
7246 | (set_attr "type" "jsr") | |
7247 | (set_attr "atype" "agen")]) | |
9db1d521 | 7248 | |
fd3cd001 UW |
7249 | ;; |
7250 | ;;- Thread-local storage support. | |
7251 | ;; | |
7252 | ||
c5aa1d12 UW |
7253 | (define_expand "get_tp_64" |
7254 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))] | |
fd3cd001 | 7255 | "TARGET_64BIT" |
c5aa1d12 | 7256 | "") |
fd3cd001 | 7257 | |
c5aa1d12 UW |
7258 | (define_expand "get_tp_31" |
7259 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))] | |
fd3cd001 | 7260 | "!TARGET_64BIT" |
c5aa1d12 | 7261 | "") |
fd3cd001 | 7262 | |
c5aa1d12 UW |
7263 | (define_expand "set_tp_64" |
7264 | [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" "")) | |
ca11b3fb | 7265 | (set (reg:DI 36) (unspec_volatile:DI [(reg:DI 36)] UNSPECV_SET_TP))] |
fd3cd001 | 7266 | "TARGET_64BIT" |
c5aa1d12 | 7267 | "") |
fd3cd001 | 7268 | |
c5aa1d12 UW |
7269 | (define_expand "set_tp_31" |
7270 | [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" "")) | |
ca11b3fb | 7271 | (set (reg:SI 36) (unspec_volatile:SI [(reg:SI 36)] UNSPECV_SET_TP))] |
fd3cd001 | 7272 | "!TARGET_64BIT" |
c5aa1d12 UW |
7273 | "") |
7274 | ||
7275 | (define_insn "*set_tp" | |
ca11b3fb | 7276 | [(set (reg 36) (unspec_volatile [(reg 36)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
7277 | "" |
7278 | "" | |
7279 | [(set_attr "type" "none") | |
7280 | (set_attr "length" "0")]) | |
c7453384 | 7281 | |
fd3cd001 UW |
7282 | (define_insn "*tls_load_64" |
7283 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7284 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7285 | (match_operand:DI 2 "" "")] | |
7286 | UNSPEC_TLS_LOAD))] | |
7287 | "TARGET_64BIT" | |
d40c829f | 7288 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7289 | [(set_attr "op_type" "RXE")]) |
7290 | ||
7291 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7292 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7293 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7294 | (match_operand:SI 2 "" "")] |
7295 | UNSPEC_TLS_LOAD))] | |
7296 | "!TARGET_64BIT" | |
d3632d41 | 7297 | "@ |
d40c829f UW |
7298 | l\t%0,%1%J2 |
7299 | ly\t%0,%1%J2" | |
d3632d41 | 7300 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 | 7301 | |
9e8327e3 | 7302 | (define_insn "*bras_tls" |
c19ec8f9 | 7303 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7304 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7305 | (match_operand 2 "const_int_operand" "n"))) | |
7306 | (clobber (match_operand 3 "register_operand" "=r")) | |
7307 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7308 | "!SIBLING_CALL_P (insn) |
7309 | && TARGET_SMALL_EXEC | |
ed9676cf | 7310 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7311 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7312 | [(set_attr "op_type" "RI") |
7313 | (set_attr "type" "jsr")]) | |
7314 | ||
9e8327e3 | 7315 | (define_insn "*brasl_tls" |
c19ec8f9 | 7316 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7317 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7318 | (match_operand 2 "const_int_operand" "n"))) | |
7319 | (clobber (match_operand 3 "register_operand" "=r")) | |
7320 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7321 | "!SIBLING_CALL_P (insn) |
7322 | && TARGET_CPU_ZARCH | |
ed9676cf | 7323 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7324 | "brasl\t%3,%1%J4" |
7325 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7326 | (set_attr "type" "jsr")]) |
7327 | ||
9e8327e3 | 7328 | (define_insn "*basr_tls" |
c19ec8f9 | 7329 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7330 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7331 | (match_operand 2 "const_int_operand" "n"))) | |
7332 | (clobber (match_operand 3 "register_operand" "=r")) | |
7333 | (use (match_operand 4 "" ""))] | |
ed9676cf | 7334 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7335 | { |
7336 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7337 | return "basr\t%3,%1%J4"; | |
7338 | else | |
7339 | return "bas\t%3,%a1%J4"; | |
7340 | } | |
7341 | [(set (attr "op_type") | |
7342 | (if_then_else (match_operand 1 "register_operand" "") | |
7343 | (const_string "RR") (const_string "RX"))) | |
7344 | (set_attr "type" "jsr") | |
7345 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7346 | |
9db1d521 HP |
7347 | ;; |
7348 | ;;- Miscellaneous instructions. | |
7349 | ;; | |
7350 | ||
7351 | ; | |
7352 | ; allocate stack instruction pattern(s). | |
7353 | ; | |
7354 | ||
7355 | (define_expand "allocate_stack" | |
ef44a6ff UW |
7356 | [(match_operand 0 "general_operand" "") |
7357 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 7358 | "TARGET_BACKCHAIN" |
9db1d521 | 7359 | { |
ef44a6ff | 7360 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 7361 | |
ef44a6ff UW |
7362 | emit_move_insn (temp, s390_back_chain_rtx ()); |
7363 | anti_adjust_stack (operands[1]); | |
7364 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 7365 | |
ef44a6ff UW |
7366 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
7367 | DONE; | |
10bbf137 | 7368 | }) |
9db1d521 HP |
7369 | |
7370 | ||
7371 | ; | |
43ab026f | 7372 | ; setjmp instruction pattern. |
9db1d521 HP |
7373 | ; |
7374 | ||
9db1d521 | 7375 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7376 | [(match_operand 0 "" "")] |
f314b9b1 | 7377 | "flag_pic" |
9db1d521 | 7378 | { |
585539a1 | 7379 | emit_insn (s390_load_got ()); |
fd7643fb | 7380 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
9db1d521 | 7381 | DONE; |
fd7643fb | 7382 | }) |
9db1d521 | 7383 | |
9db1d521 HP |
7384 | ;; These patterns say how to save and restore the stack pointer. We need not |
7385 | ;; save the stack pointer at function level since we are careful to | |
7386 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7387 | ;; when we restore the stack pointer. | |
7388 | ;; | |
7389 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7390 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7391 | ;; save area is a memory location. | |
7392 | ||
7393 | (define_expand "save_stack_function" | |
7394 | [(match_operand 0 "general_operand" "") | |
7395 | (match_operand 1 "general_operand" "")] | |
7396 | "" | |
7397 | "DONE;") | |
7398 | ||
7399 | (define_expand "restore_stack_function" | |
7400 | [(match_operand 0 "general_operand" "") | |
7401 | (match_operand 1 "general_operand" "")] | |
7402 | "" | |
7403 | "DONE;") | |
7404 | ||
7405 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
7406 | [(match_operand 0 "register_operand" "") |
7407 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 7408 | "TARGET_BACKCHAIN" |
9db1d521 | 7409 | { |
ef44a6ff UW |
7410 | rtx temp = gen_reg_rtx (Pmode); |
7411 | ||
7412 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
7413 | emit_move_insn (operands[0], operands[1]); | |
7414 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7415 | ||
7416 | DONE; | |
10bbf137 | 7417 | }) |
9db1d521 HP |
7418 | |
7419 | (define_expand "save_stack_nonlocal" | |
7420 | [(match_operand 0 "memory_operand" "") | |
7421 | (match_operand 1 "register_operand" "")] | |
7422 | "" | |
9db1d521 | 7423 | { |
ef44a6ff UW |
7424 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
7425 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
7426 | ||
7427 | /* Copy the backchain to the first word, sp to the second and the | |
7428 | literal pool base to the third. */ | |
7429 | ||
b3d31392 | 7430 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7431 | { |
7432 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
7433 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
7434 | } | |
7435 | ||
7436 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
7437 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 7438 | |
9db1d521 | 7439 | DONE; |
10bbf137 | 7440 | }) |
9db1d521 HP |
7441 | |
7442 | (define_expand "restore_stack_nonlocal" | |
7443 | [(match_operand 0 "register_operand" "") | |
7444 | (match_operand 1 "memory_operand" "")] | |
7445 | "" | |
9db1d521 | 7446 | { |
ef44a6ff | 7447 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 7448 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 7449 | rtx temp = NULL_RTX; |
9db1d521 | 7450 | |
43ab026f | 7451 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 7452 | literal pool base from the third. */ |
43ab026f | 7453 | |
b3d31392 | 7454 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7455 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
7456 | ||
7457 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
7458 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
7459 | ||
7460 | if (temp) | |
7461 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7462 | ||
7463 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
9db1d521 | 7464 | DONE; |
10bbf137 | 7465 | }) |
9db1d521 HP |
7466 | |
7467 | ||
7468 | ; | |
7469 | ; nop instruction pattern(s). | |
7470 | ; | |
7471 | ||
7472 | (define_insn "nop" | |
7473 | [(const_int 0)] | |
7474 | "" | |
d40c829f | 7475 | "lr\t0,0" |
9db1d521 HP |
7476 | [(set_attr "op_type" "RR")]) |
7477 | ||
7478 | ||
7479 | ; | |
7480 | ; Special literal pool access instruction pattern(s). | |
7481 | ; | |
7482 | ||
416cf582 UW |
7483 | (define_insn "*pool_entry" |
7484 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7485 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7486 | "" |
9db1d521 | 7487 | { |
416cf582 UW |
7488 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7489 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 7490 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
7491 | return ""; |
7492 | } | |
b628bd8e | 7493 | [(set (attr "length") |
416cf582 | 7494 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 7495 | |
9bb86f41 UW |
7496 | (define_insn "pool_align" |
7497 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
7498 | UNSPECV_POOL_ALIGN)] | |
7499 | "" | |
7500 | ".align\t%0" | |
b628bd8e | 7501 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 7502 | |
9bb86f41 UW |
7503 | (define_insn "pool_section_start" |
7504 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
7505 | "" | |
7506 | ".section\t.rodata" | |
b628bd8e | 7507 | [(set_attr "length" "0")]) |
b2ccb744 | 7508 | |
9bb86f41 UW |
7509 | (define_insn "pool_section_end" |
7510 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
7511 | "" | |
b2ccb744 | 7512 | ".previous" |
b628bd8e | 7513 | [(set_attr "length" "0")]) |
b2ccb744 | 7514 | |
5af2f3d3 | 7515 | (define_insn "main_base_31_small" |
9e8327e3 UW |
7516 | [(set (match_operand 0 "register_operand" "=a") |
7517 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7518 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7519 | "basr\t%0,0" |
7520 | [(set_attr "op_type" "RR") | |
7521 | (set_attr "type" "la")]) | |
7522 | ||
7523 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
7524 | [(set (match_operand 0 "register_operand" "=a") |
7525 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 7526 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 7527 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
7528 | "bras\t%0,%2" |
7529 | [(set_attr "op_type" "RI")]) | |
7530 | ||
7531 | (define_insn "main_base_64" | |
9e8327e3 UW |
7532 | [(set (match_operand 0 "register_operand" "=a") |
7533 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7534 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7535 | "larl\t%0,%1" |
7536 | [(set_attr "op_type" "RIL") | |
7537 | (set_attr "type" "larl")]) | |
7538 | ||
7539 | (define_insn "main_pool" | |
585539a1 UW |
7540 | [(set (match_operand 0 "register_operand" "=a") |
7541 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
7542 | "GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 | 7543 | "* abort ();" |
b628bd8e | 7544 | [(set (attr "type") |
ea77e738 UW |
7545 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
7546 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 7547 | |
aee4e0db | 7548 | (define_insn "reload_base_31" |
9e8327e3 UW |
7549 | [(set (match_operand 0 "register_operand" "=a") |
7550 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7551 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7552 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
7553 | [(set_attr "length" "6") |
7554 | (set_attr "type" "la")]) | |
b2ccb744 | 7555 | |
aee4e0db | 7556 | (define_insn "reload_base_64" |
9e8327e3 UW |
7557 | [(set (match_operand 0 "register_operand" "=a") |
7558 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7559 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7560 | "larl\t%0,%1" |
aee4e0db | 7561 | [(set_attr "op_type" "RIL") |
077dab3b | 7562 | (set_attr "type" "larl")]) |
aee4e0db | 7563 | |
aee4e0db | 7564 | (define_insn "pool" |
fd7643fb | 7565 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db UW |
7566 | "" |
7567 | "* abort ();" | |
b628bd8e | 7568 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 7569 | |
4023fb28 UW |
7570 | ;; |
7571 | ;; Insns related to generating the function prologue and epilogue. | |
7572 | ;; | |
7573 | ||
7574 | ||
7575 | (define_expand "prologue" | |
7576 | [(use (const_int 0))] | |
7577 | "" | |
10bbf137 | 7578 | "s390_emit_prologue (); DONE;") |
4023fb28 | 7579 | |
2f7e5a0d EC |
7580 | (define_insn "prologue_tpf" |
7581 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE) | |
7582 | (clobber (reg:DI 1))] | |
3839e36a | 7583 | "TARGET_TPF_PROFILING" |
9e811ecd JT |
7584 | "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064" |
7585 | [(set_attr "length" "14")]) | |
2f7e5a0d | 7586 | |
4023fb28 UW |
7587 | (define_expand "epilogue" |
7588 | [(use (const_int 1))] | |
7589 | "" | |
ed9676cf AK |
7590 | "s390_emit_epilogue (false); DONE;") |
7591 | ||
2f7e5a0d EC |
7592 | (define_insn "epilogue_tpf" |
7593 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE) | |
7594 | (clobber (reg:DI 1))] | |
3839e36a | 7595 | "TARGET_TPF_PROFILING" |
9e811ecd JT |
7596 | "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070" |
7597 | [(set_attr "length" "14")]) | |
2f7e5a0d | 7598 | |
ed9676cf AK |
7599 | (define_expand "sibcall_epilogue" |
7600 | [(use (const_int 0))] | |
7601 | "" | |
7602 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 7603 | |
9e8327e3 | 7604 | (define_insn "*return" |
4023fb28 | 7605 | [(return) |
9e8327e3 UW |
7606 | (use (match_operand 0 "register_operand" "a"))] |
7607 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7608 | "br\t%0" |
4023fb28 | 7609 | [(set_attr "op_type" "RR") |
c7453384 | 7610 | (set_attr "type" "jsr") |
077dab3b | 7611 | (set_attr "atype" "agen")]) |
4023fb28 | 7612 | |
4023fb28 | 7613 | |
c7453384 | 7614 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 7615 | ;; pointer. This is used for compatibility. |
c7453384 EC |
7616 | |
7617 | (define_expand "ptr_extend" | |
7618 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7619 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7620 | "TARGET_64BIT" |
c7453384 | 7621 | { |
c7453384 EC |
7622 | emit_insn (gen_anddi3 (operands[0], |
7623 | gen_lowpart (DImode, operands[1]), | |
7624 | GEN_INT (0x7fffffff))); | |
c7453384 | 7625 | DONE; |
10bbf137 | 7626 | }) |
4798630c D |
7627 | |
7628 | ;; Instruction definition to expand eh_return macro to support | |
7629 | ;; swapping in special linkage return addresses. | |
7630 | ||
7631 | (define_expand "eh_return" | |
7632 | [(use (match_operand 0 "register_operand" ""))] | |
7633 | "TARGET_TPF" | |
7634 | { | |
7635 | s390_emit_tpf_eh_return (operands[0]); | |
7636 | DONE; | |
7637 | }) | |
7638 |