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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
66647d44 JJ |
2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
3 | ;; 2009 Free Software Foundation, Inc. | |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
5 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
6 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 7 | |
58add37a UW |
8 | ;; This file is part of GCC. |
9 | ||
10 | ;; GCC is free software; you can redistribute it and/or modify it under | |
11 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
13 | ;; version. |
14 | ||
15 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | ;; for more details. | |
9db1d521 HP |
19 | |
20 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | ;; along with GCC; see the file COPYING3. If not see |
22 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
23 | |
24 | ;; | |
cd8dc1f9 | 25 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 26 | ;; |
cd8dc1f9 | 27 | |
9db1d521 HP |
28 | ;; Special formats used for outputting 390 instructions. |
29 | ;; | |
f19a9af7 AK |
30 | ;; %C: print opcode suffix for branch condition. |
31 | ;; %D: print opcode suffix for inverse branch condition. | |
32 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 33 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
34 | ;; %O: print only the displacement of a memory reference. |
35 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 36 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
37 | ;; %N: print the second word of a DImode operand. |
38 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 39 | ;; %Y: print shift count operand. |
f4aa3848 | 40 | ;; |
f19a9af7 | 41 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 42 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
43 | ;; %x: print integer X as if it's an unsigned halfword. |
44 | ;; %h: print integer X as if it's a signed halfword. | |
45 | ;; %i: print the first nonzero HImode part of X. | |
46 | ;; %j: print the first HImode part unequal to -1 of X. | |
47 | ;; %k: print the first nonzero SImode part of X. | |
48 | ;; %m: print the first SImode part unequal to -1 of X. | |
49 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
50 | ;; |
51 | ;; We have a special constraint for pattern matching. | |
52 | ;; | |
53 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
54 | ;; | |
9db1d521 | 55 | |
fd3cd001 UW |
56 | ;; |
57 | ;; UNSPEC usage | |
58 | ;; | |
59 | ||
60 | (define_constants | |
10bbf137 UW |
61 | [; Miscellaneous |
62 | (UNSPEC_ROUND 1) | |
638e37c2 WG |
63 | (UNSPEC_CCU_TO_INT 2) |
64 | (UNSPEC_CCZ_TO_INT 3) | |
6fa05db6 | 65 | (UNSPEC_ICM 10) |
12959abe | 66 | (UNSPEC_TIE 11) |
10bbf137 UW |
67 | |
68 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
69 | (UNSPEC_LTREL_OFFSET 100) |
70 | (UNSPEC_LTREL_BASE 101) | |
dc66391d | 71 | (UNSPEC_POOL_OFFSET 102) |
fd7643fb UW |
72 | (UNSPEC_GOTENT 110) |
73 | (UNSPEC_GOT 111) | |
74 | (UNSPEC_GOTOFF 112) | |
75 | (UNSPEC_PLT 113) | |
76 | (UNSPEC_PLTOFF 114) | |
77 | ||
78 | ; Literal pool | |
79 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 80 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 81 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
82 | (UNSPEC_INSN 213) |
83 | (UNSPEC_EXECUTE 214) | |
fd7643fb | 84 | |
1a8c13b3 UB |
85 | ; Atomic Support |
86 | (UNSPEC_MB 400) | |
87 | ||
fd7643fb | 88 | ; TLS relocation specifiers |
fd3cd001 UW |
89 | (UNSPEC_TLSGD 500) |
90 | (UNSPEC_TLSLDM 501) | |
91 | (UNSPEC_NTPOFF 502) | |
92 | (UNSPEC_DTPOFF 503) | |
93 | (UNSPEC_GOTNTPOFF 504) | |
94 | (UNSPEC_INDNTPOFF 505) | |
95 | ||
96 | ; TLS support | |
fd3cd001 UW |
97 | (UNSPEC_TLSLDM_NTPOFF 511) |
98 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
99 | |
100 | ; String Functions | |
7b8acc34 | 101 | (UNSPEC_SRST 600) |
742090fc | 102 | (UNSPEC_MVST 601) |
638e37c2 | 103 | |
7b8acc34 AK |
104 | ; Stack Smashing Protector |
105 | (UNSPEC_SP_SET 700) | |
106 | (UNSPEC_SP_TEST 701) | |
85dae55a AK |
107 | |
108 | ; Copy sign instructions | |
109 | (UNSPEC_COPYSIGN 800) | |
638e37c2 WG |
110 | |
111 | ; Test Data Class (TDC) | |
112 | (UNSPEC_TDC_INSN 900) | |
fd3cd001 UW |
113 | ]) |
114 | ||
115 | ;; | |
116 | ;; UNSPEC_VOLATILE usage | |
117 | ;; | |
118 | ||
119 | (define_constants | |
10bbf137 UW |
120 | [; Blockage |
121 | (UNSPECV_BLOCKAGE 0) | |
122 | ||
2f7e5a0d EC |
123 | ; TPF Support |
124 | (UNSPECV_TPF_PROLOGUE 20) | |
125 | (UNSPECV_TPF_EPILOGUE 21) | |
126 | ||
10bbf137 | 127 | ; Literal pool |
fd7643fb | 128 | (UNSPECV_POOL 200) |
9bb86f41 UW |
129 | (UNSPECV_POOL_SECTION 201) |
130 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 131 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
132 | (UNSPECV_MAIN_POOL 300) |
133 | ||
134 | ; TLS support | |
fd3cd001 | 135 | (UNSPECV_SET_TP 500) |
e0374221 AS |
136 | |
137 | ; Atomic Support | |
1a8c13b3 | 138 | (UNSPECV_CAS 700) |
fd3cd001 UW |
139 | ]) |
140 | ||
ae156f85 AS |
141 | ;; |
142 | ;; Registers | |
143 | ;; | |
144 | ||
35dd9a0e AK |
145 | ; Registers with special meaning |
146 | ||
ae156f85 AS |
147 | (define_constants |
148 | [ | |
149 | ; Sibling call register. | |
150 | (SIBCALL_REGNUM 1) | |
151 | ; Literal pool base register. | |
152 | (BASE_REGNUM 13) | |
153 | ; Return address register. | |
154 | (RETURN_REGNUM 14) | |
155 | ; Condition code register. | |
156 | (CC_REGNUM 33) | |
f4aa3848 | 157 | ; Thread local storage pointer register. |
ae156f85 AS |
158 | (TP_REGNUM 36) |
159 | ]) | |
160 | ||
35dd9a0e AK |
161 | ; Hardware register names |
162 | ||
163 | (define_constants | |
164 | [ | |
165 | ; General purpose registers | |
166 | (GPR0_REGNUM 0) | |
167 | ; Floating point registers. | |
168 | (FPR0_REGNUM 16) | |
169 | (FPR2_REGNUM 18) | |
170 | ]) | |
171 | ||
172 | ;; | |
173 | ;; PFPO GPR0 argument format | |
174 | ;; | |
175 | ||
176 | (define_constants | |
177 | [ | |
178 | ; PFPO operation type | |
179 | (PFPO_CONVERT 0x1000000) | |
180 | ; PFPO operand types | |
181 | (PFPO_OP_TYPE_SF 0x5) | |
182 | (PFPO_OP_TYPE_DF 0x6) | |
183 | (PFPO_OP_TYPE_TF 0x7) | |
184 | (PFPO_OP_TYPE_SD 0x8) | |
185 | (PFPO_OP_TYPE_DD 0x9) | |
186 | (PFPO_OP_TYPE_TD 0xa) | |
187 | ; Bitposition of operand types | |
188 | (PFPO_OP0_TYPE_SHIFT 16) | |
189 | (PFPO_OP1_TYPE_SHIFT 8) | |
190 | ]) | |
191 | ||
fd3cd001 | 192 | |
29a74354 UW |
193 | ;; Instruction operand type as used in the Principles of Operation. |
194 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 195 | |
29a74354 | 196 | (define_attr "op_type" |
963fc8d0 | 197 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" |
b628bd8e | 198 | (const_string "NN")) |
9db1d521 | 199 | |
29a74354 | 200 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 201 | |
077dab3b | 202 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 203 | cs,vs,store,sem,idiv, |
ed0e512a | 204 | imulhi,imulsi,imuldi, |
f61a2c7d AK |
205 | branch,jsr,fsimptf,fsimpdf,fsimpsf, |
206 | floadtf,floaddf,floadsf,fstoredf,fstoresf, | |
207 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 WG |
208 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
209 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, | |
210 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
211 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
212 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
213 | ftoidfp, other" | |
29a74354 UW |
214 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
215 | (eq_attr "op_type" "SS") (const_string "cs")] | |
216 | (const_string "integer"))) | |
9db1d521 | 217 | |
29a74354 UW |
218 | ;; Another attribute used for scheduling purposes: |
219 | ;; agen: Instruction uses the address generation unit | |
220 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
221 | |
222 | (define_attr "atype" "agen,reg" | |
f4aa3848 | 223 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE") |
0101708c AS |
224 | (const_string "reg") |
225 | (const_string "agen"))) | |
9db1d521 | 226 | |
9381e3f1 WG |
227 | ;; Properties concerning Z10 execution grouping and value forwarding. |
228 | ;; z10_super: instruction is superscalar. | |
229 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
230 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
231 | ;; target register. It can forward this value to a second instruction that reads | |
232 | ;; the same register if that second instruction is issued in the same group. | |
233 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
234 | ;; instruction in the S pipe writes to the register, then the T instruction | |
235 | ;; can immediately read the new value. | |
236 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
237 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
238 | ;; |
239 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
240 | ||
241 | ||
242 | (define_attr "z10prop" "none, | |
243 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
244 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
245 | z10_rec, | |
246 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 247 | z10_c" |
9381e3f1 WG |
248 | (const_string "none")) |
249 | ||
250 | ||
9db1d521 HP |
251 | ;; Length in bytes. |
252 | ||
253 | (define_attr "length" "" | |
963fc8d0 AK |
254 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
255 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 256 | (const_int 6))) |
9db1d521 | 257 | |
29a74354 UW |
258 | |
259 | ;; Processor type. This attribute must exactly match the processor_type | |
260 | ;; enumeration in s390.h. The current machine description does not | |
261 | ;; distinguish between g5 and g6, but there are differences between the two | |
262 | ;; CPUs could in theory be modeled. | |
263 | ||
93538e8e | 264 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10" |
90c6fd8a | 265 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 266 | |
93538e8e | 267 | (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10" |
3af8e996 AK |
268 | (const_string "standard")) |
269 | ||
270 | (define_attr "enabled" "" | |
271 | (cond [(eq_attr "cpu_facility" "standard") | |
272 | (const_int 1) | |
273 | ||
274 | (and (eq_attr "cpu_facility" "ieee") | |
275 | (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0))) | |
276 | (const_int 1) | |
277 | ||
278 | (and (eq_attr "cpu_facility" "zarch") | |
279 | (ne (symbol_ref "TARGET_ZARCH") (const_int 0))) | |
280 | (const_int 1) | |
281 | ||
282 | (and (eq_attr "cpu_facility" "longdisp") | |
283 | (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0))) | |
284 | (const_int 1) | |
285 | ||
286 | (and (eq_attr "cpu_facility" "extimm") | |
287 | (ne (symbol_ref "TARGET_EXTIMM") (const_int 0))) | |
288 | (const_int 1) | |
289 | ||
290 | (and (eq_attr "cpu_facility" "dfp") | |
291 | (ne (symbol_ref "TARGET_DFP") (const_int 0))) | |
93538e8e AK |
292 | (const_int 1) |
293 | ||
294 | (and (eq_attr "cpu_facility" "z10") | |
295 | (ne (symbol_ref "TARGET_Z10") (const_int 0))) | |
3af8e996 AK |
296 | (const_int 1)] |
297 | (const_int 0))) | |
298 | ||
29a74354 UW |
299 | ;; Pipeline description for z900. For lack of anything better, |
300 | ;; this description is also used for the g5 and g6. | |
301 | (include "2064.md") | |
302 | ||
3443392a | 303 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
304 | (include "2084.md") |
305 | ||
9381e3f1 WG |
306 | ;; Pipeline description for z10 |
307 | (include "2097.md") | |
308 | ||
0bfc3f69 AS |
309 | ;; Predicates |
310 | (include "predicates.md") | |
311 | ||
cd8dc1f9 WG |
312 | ;; Constraint definitions |
313 | (include "constraints.md") | |
314 | ||
a8ba31f2 EC |
315 | ;; Other includes |
316 | (include "tpf.md") | |
f52c81dd | 317 | |
3abcb3a7 | 318 | ;; Iterators |
f52c81dd | 319 | |
3abcb3a7 | 320 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 321 | ;; same template. |
f4aa3848 | 322 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 323 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 | 324 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
963fc8d0 | 325 | (define_mode_iterator FPALL [TF DF SF TD DD SD]) |
3abcb3a7 HPN |
326 | (define_mode_iterator BFP [TF DF SF]) |
327 | (define_mode_iterator DFP [TD DD]) | |
328 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
329 | (define_mode_iterator DSF [DF SF]) | |
330 | (define_mode_iterator SD_SF [SF SD]) | |
331 | (define_mode_iterator DD_DF [DF DD]) | |
332 | (define_mode_iterator TD_TF [TF TD]) | |
333 | ||
334 | ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated | |
8006eaa6 | 335 | ;; from the same template. |
3abcb3a7 | 336 | (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI]) |
8006eaa6 | 337 | |
3abcb3a7 | 338 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 339 | ;; from the same template. |
3abcb3a7 HPN |
340 | (define_mode_iterator GPR [(DI "TARGET_64BIT") SI]) |
341 | (define_mode_iterator DSI [DI SI]) | |
9db2f16d | 342 | |
3abcb3a7 | 343 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 344 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 HPN |
345 | (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")]) |
346 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) | |
9db2f16d | 347 | |
3abcb3a7 | 348 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 349 | ;; the same template. |
3abcb3a7 | 350 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 351 | |
3abcb3a7 | 352 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 353 | ;; same template. |
3abcb3a7 | 354 | (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI]) |
963fc8d0 | 355 | (define_mode_iterator INTALL [TI DI SI HI QI]) |
342cf42b | 356 | |
3abcb3a7 | 357 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 358 | ;; the same template. |
3abcb3a7 | 359 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 360 | |
3abcb3a7 HPN |
361 | ;; This iterator and attribute allow to combine most atomic operations. |
362 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
f4aa3848 | 363 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") |
45d18331 AS |
364 | (plus "add") (minus "sub") (mult "nand")]) |
365 | ||
f4aa3848 | 366 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
367 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
368 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 369 | |
f4aa3848 AK |
370 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
371 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
372 | ;; SDmode. |
373 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 374 | |
609e7e80 | 375 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
376 | ;; Likewise for "<RXe>". |
377 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
378 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
379 | ||
609e7e80 | 380 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 381 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
382 | ;; dfp variants in a single insn definition. |
383 | ||
3abcb3a7 | 384 | ;; This attribute is used to set op_type accordingly. |
f4aa3848 | 385 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
609e7e80 AK |
386 | (DD "RRR") (SD "RRR")]) |
387 | ||
f4aa3848 | 388 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
389 | ;; first and the second operand match for bfp modes. |
390 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
391 | ||
f4aa3848 | 392 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
393 | ;; additional operand for the dfp instructions. |
394 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
395 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
396 | ||
f5905b37 | 397 | |
85dae55a AK |
398 | ;; This attribute is used in the operand constraint list |
399 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
400 | ;; TFmode values are represented by a fp register pair. Since the | |
401 | ;; sign bit instructions only handle single source and target fp registers | |
402 | ;; these instructions can only be used for TFmode values if the source and | |
403 | ;; target operand uses the same fp register. | |
404 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
405 | ||
609e7e80 AK |
406 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
407 | ;; This is used to disable the memory alternative in TFmode patterns. | |
408 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
409 | ||
3abcb3a7 | 410 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
411 | ;; within instruction mnemonics. |
412 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
413 | ||
0387c142 WG |
414 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
415 | ;; modes and to an empty string for bfp modes. | |
416 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
417 | ||
1b48c8cc AS |
418 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
419 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
420 | ;; version only operates on one register. | |
421 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
422 | ||
423 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
424 | ;; version only operates on one register. The DImode version needs an additional | |
425 | ;; register for the assembler output. | |
426 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
427 | |
428 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
429 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
430 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
431 | ||
432 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 433 | ;; pattern itself and the corresponding function calls. |
f337b930 | 434 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
435 | |
436 | ;; This attribute handles differences in the instruction 'type' and will result | |
437 | ;; in "RRE" for DImode and "RR" for SImode. | |
438 | (define_mode_attr E [(DI "E") (SI "")]) | |
439 | ||
3298c037 AK |
440 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
441 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
442 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
443 | ||
8006eaa6 AS |
444 | ;; This attribute handles differences in the instruction 'type' and will result |
445 | ;; in "RSE" for TImode and "RS" for DImode. | |
446 | (define_mode_attr TE [(TI "E") (DI "")]) | |
447 | ||
9a91a21f AS |
448 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
449 | ;; and "lcr" in SImode. | |
450 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 451 | |
3298c037 AK |
452 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
453 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
454 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
455 | ;; variant for long displacements. | |
456 | (define_mode_attr y [(DI "g") (SI "y")]) | |
457 | ||
8006eaa6 AS |
458 | ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode |
459 | ;; and "cds" in DImode. | |
460 | (define_mode_attr tg [(TI "g") (DI "")]) | |
461 | ||
2f8f8434 AS |
462 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
463 | ;; and "cfdbr" in SImode. | |
464 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
465 | ||
f52c81dd AS |
466 | ;; ICM mask required to load MODE value into the lowest subreg |
467 | ;; of a SImode register. | |
468 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
469 | ||
f6ee577c AS |
470 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
471 | ;; HImode and "llgc" in QImode. | |
472 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
473 | ||
a1aed706 AS |
474 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
475 | ;; in SImode. | |
476 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
477 | ||
609e7e80 AK |
478 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
479 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
480 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
481 | ||
f52c81dd AS |
482 | ;; Maximum unsigned integer that fits in MODE. |
483 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
484 | ||
9db1d521 HP |
485 | ;; |
486 | ;;- Compare instructions. | |
487 | ;; | |
488 | ||
07893d4f | 489 | ; Test-under-Mask instructions |
9db1d521 | 490 | |
07893d4f | 491 | (define_insn "*tmqi_mem" |
ae156f85 | 492 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
493 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
494 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
495 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 496 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 497 | "@ |
fc0ea003 UW |
498 | tm\t%S0,%b1 |
499 | tmy\t%S0,%b1" | |
9381e3f1 WG |
500 | [(set_attr "op_type" "SI,SIY") |
501 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 502 | |
05b9aaaa | 503 | (define_insn "*tmdi_reg" |
ae156f85 | 504 | [(set (reg CC_REGNUM) |
f19a9af7 | 505 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 506 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
507 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
508 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa | 509 | "TARGET_64BIT |
3ed99cc9 | 510 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
511 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
512 | "@ | |
513 | tmhh\t%0,%i1 | |
514 | tmhl\t%0,%i1 | |
515 | tmlh\t%0,%i1 | |
516 | tmll\t%0,%i1" | |
9381e3f1 WG |
517 | [(set_attr "op_type" "RI") |
518 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
519 | |
520 | (define_insn "*tmsi_reg" | |
ae156f85 | 521 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
522 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
523 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
524 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 525 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
526 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
527 | "@ | |
528 | tmh\t%0,%i1 | |
529 | tml\t%0,%i1" | |
729e750f WG |
530 | [(set_attr "op_type" "RI") |
531 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 532 | |
f52c81dd | 533 | (define_insn "*tm<mode>_full" |
ae156f85 | 534 | [(set (reg CC_REGNUM) |
f52c81dd AS |
535 | (compare (match_operand:HQI 0 "register_operand" "d") |
536 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 537 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 538 | "tml\t%0,<max_uint>" |
729e750f WG |
539 | [(set_attr "op_type" "RI") |
540 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 541 | |
07893d4f | 542 | |
08a5aaa2 | 543 | ; |
07893d4f | 544 | ; Load-and-Test instructions |
08a5aaa2 AS |
545 | ; |
546 | ||
c0220ea4 | 547 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
548 | |
549 | (define_insn "*tstdi_sign" | |
ae156f85 | 550 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
551 | (compare |
552 | (ashiftrt:DI | |
553 | (ashift:DI | |
554 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
555 | (const_int 32)) (const_int 32)) | |
556 | (match_operand:DI 1 "const0_operand" ""))) | |
557 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f UW |
558 | (sign_extend:DI (match_dup 0)))] |
559 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
963fc8d0 AK |
560 | "ltgfr\t%2,%0 |
561 | ltgf\t%2,%0" | |
562 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
563 | (set_attr "cpu_facility" "*,z10") |
564 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 565 | |
43a09b63 | 566 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 567 | (define_insn "*tst<mode>_extimm" |
ec24698e | 568 | [(set (reg CC_REGNUM) |
fb492564 | 569 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
570 | (match_operand:GPR 1 "const0_operand" ""))) |
571 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 572 | (match_dup 0))] |
08a5aaa2 | 573 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 574 | "@ |
08a5aaa2 AS |
575 | lt<g>r\t%2,%0 |
576 | lt<g>\t%2,%0" | |
9381e3f1 | 577 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 578 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 579 | |
43a09b63 | 580 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 581 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 582 | [(set (reg CC_REGNUM) |
fb492564 | 583 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
584 | (match_operand:GPR 1 "const0_operand" ""))) |
585 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
586 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 587 | "@ |
08a5aaa2 AS |
588 | lt<g>r\t%0,%0 |
589 | lt<g>\t%2,%0" | |
9381e3f1 | 590 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 591 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 592 | |
07893d4f | 593 | (define_insn "*tstdi" |
ae156f85 | 594 | [(set (reg CC_REGNUM) |
07893d4f UW |
595 | (compare (match_operand:DI 0 "register_operand" "d") |
596 | (match_operand:DI 1 "const0_operand" ""))) | |
597 | (set (match_operand:DI 2 "register_operand" "=d") | |
598 | (match_dup 0))] | |
ec24698e | 599 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" |
d40c829f | 600 | "ltgr\t%2,%0" |
9381e3f1 WG |
601 | [(set_attr "op_type" "RRE") |
602 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 603 | |
07893d4f | 604 | (define_insn "*tstsi" |
ae156f85 | 605 | [(set (reg CC_REGNUM) |
d3632d41 | 606 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 607 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 608 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 609 | (match_dup 0))] |
ec24698e | 610 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 611 | "@ |
d40c829f | 612 | ltr\t%2,%0 |
fc0ea003 UW |
613 | icm\t%2,15,%S0 |
614 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
615 | [(set_attr "op_type" "RR,RS,RSY") |
616 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 617 | |
07893d4f | 618 | (define_insn "*tstsi_cconly" |
ae156f85 | 619 | [(set (reg CC_REGNUM) |
d3632d41 | 620 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 621 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 622 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
623 | "s390_match_ccmode(insn, CCSmode)" |
624 | "@ | |
d40c829f | 625 | ltr\t%0,%0 |
fc0ea003 UW |
626 | icm\t%2,15,%S0 |
627 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
628 | [(set_attr "op_type" "RR,RS,RSY") |
629 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 630 | |
08a5aaa2 AS |
631 | (define_insn "*tstdi_cconly_31" |
632 | [(set (reg CC_REGNUM) | |
633 | (compare (match_operand:DI 0 "register_operand" "d") | |
634 | (match_operand:DI 1 "const0_operand" "")))] | |
635 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
636 | "srda\t%0,0" | |
637 | [(set_attr "op_type" "RS") | |
638 | (set_attr "atype" "reg")]) | |
639 | ||
43a09b63 | 640 | ; ltr, ltgr |
08a5aaa2 | 641 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 642 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
643 | (compare (match_operand:GPR 0 "register_operand" "d") |
644 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 645 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 646 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
647 | [(set_attr "op_type" "RR<E>") |
648 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 649 | |
c0220ea4 | 650 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 651 | |
f52c81dd | 652 | (define_insn "*tst<mode>CCT" |
ae156f85 | 653 | [(set (reg CC_REGNUM) |
f52c81dd AS |
654 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
655 | (match_operand:HQI 1 "const0_operand" ""))) | |
656 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
657 | (match_dup 0))] |
658 | "s390_match_ccmode(insn, CCTmode)" | |
659 | "@ | |
f52c81dd AS |
660 | icm\t%2,<icm_lo>,%S0 |
661 | icmy\t%2,<icm_lo>,%S0 | |
662 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
663 | [(set_attr "op_type" "RS,RSY,RI") |
664 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
665 | |
666 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 667 | [(set (reg CC_REGNUM) |
d3632d41 | 668 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 669 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 670 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
671 | "s390_match_ccmode(insn, CCTmode)" |
672 | "@ | |
fc0ea003 UW |
673 | icm\t%2,3,%S0 |
674 | icmy\t%2,3,%S0 | |
d40c829f | 675 | tml\t%0,65535" |
9381e3f1 WG |
676 | [(set_attr "op_type" "RS,RSY,RI") |
677 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 678 | |
3af97654 | 679 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 680 | [(set (reg CC_REGNUM) |
d3632d41 | 681 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
682 | (match_operand:QI 1 "const0_operand" "")))] |
683 | "s390_match_ccmode(insn, CCTmode)" | |
684 | "@ | |
fc0ea003 UW |
685 | cli\t%S0,0 |
686 | cliy\t%S0,0 | |
d40c829f | 687 | tml\t%0,255" |
9381e3f1 | 688 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 689 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 690 | |
f52c81dd | 691 | (define_insn "*tst<mode>" |
ae156f85 | 692 | [(set (reg CC_REGNUM) |
f52c81dd AS |
693 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
694 | (match_operand:HQI 1 "const0_operand" ""))) | |
695 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
696 | (match_dup 0))] |
697 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 698 | "@ |
f52c81dd AS |
699 | icm\t%2,<icm_lo>,%S0 |
700 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
701 | [(set_attr "op_type" "RS,RSY") |
702 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 703 | |
f52c81dd | 704 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 705 | [(set (reg CC_REGNUM) |
f52c81dd AS |
706 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
707 | (match_operand:HQI 1 "const0_operand" ""))) | |
708 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 709 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 710 | "@ |
f52c81dd AS |
711 | icm\t%2,<icm_lo>,%S0 |
712 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
713 | [(set_attr "op_type" "RS,RSY") |
714 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 715 | |
9db1d521 | 716 | |
575f7c2b UW |
717 | ; Compare (equality) instructions |
718 | ||
719 | (define_insn "*cmpdi_cct" | |
ae156f85 | 720 | [(set (reg CC_REGNUM) |
ec24698e | 721 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 722 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
e221ef54 | 723 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" |
575f7c2b UW |
724 | "@ |
725 | cgr\t%0,%1 | |
f4f41b4e | 726 | cghi\t%0,%h1 |
ec24698e | 727 | cgfi\t%0,%1 |
575f7c2b | 728 | cg\t%0,%1 |
19b63d8e | 729 | #" |
9381e3f1 WG |
730 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
731 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
732 | |
733 | (define_insn "*cmpsi_cct" | |
ae156f85 | 734 | [(set (reg CC_REGNUM) |
ec24698e UW |
735 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
736 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 737 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
738 | "@ |
739 | cr\t%0,%1 | |
f4f41b4e | 740 | chi\t%0,%h1 |
ec24698e | 741 | cfi\t%0,%1 |
575f7c2b UW |
742 | c\t%0,%1 |
743 | cy\t%0,%1 | |
19b63d8e | 744 | #" |
9381e3f1 | 745 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 746 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 747 | |
07893d4f | 748 | ; Compare (signed) instructions |
4023fb28 | 749 | |
07893d4f | 750 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 751 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
752 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
753 | "d,RT,b")) | |
754 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
07893d4f | 755 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" |
4023fb28 | 756 | "@ |
d40c829f | 757 | cgfr\t%0,%1 |
963fc8d0 AK |
758 | cgf\t%0,%1 |
759 | cgfrl\t%0,%1" | |
760 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 761 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 762 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 763 | |
9381e3f1 WG |
764 | |
765 | ||
07893d4f | 766 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 767 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
768 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
769 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 770 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 771 | "@ |
d40c829f | 772 | ch\t%0,%1 |
963fc8d0 AK |
773 | chy\t%0,%1 |
774 | chrl\t%0,%1" | |
775 | [(set_attr "op_type" "RX,RXY,RIL") | |
776 | (set_attr "cpu_facility" "*,*,z10") | |
777 | (set_attr "type" "*,*,larl")]) | |
778 | ||
779 | (define_insn "*cmphi_ccs_z10" | |
780 | [(set (reg CC_REGNUM) | |
781 | (compare (match_operand:HI 0 "s_operand" "Q") | |
782 | (match_operand:HI 1 "immediate_operand" "K")))] | |
783 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
784 | "chhsi\t%0,%1" | |
785 | [(set_attr "op_type" "SIL")]) | |
786 | ||
787 | (define_insn "*cmpdi_ccs_signhi_rl" | |
788 | [(set (reg CC_REGNUM) | |
789 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
790 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
791 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
792 | "@ | |
793 | cgh\t%0,%1 | |
794 | cghrl\t%0,%1" | |
795 | [(set_attr "op_type" "RXY,RIL") | |
796 | (set_attr "type" "*,larl")]) | |
4023fb28 | 797 | |
963fc8d0 | 798 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 799 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 800 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
801 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
802 | "d,d,Q, d,d,d,d") | |
803 | (match_operand:GPR 1 "general_operand" | |
804 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 805 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 806 | "@ |
3298c037 AK |
807 | c<g>r\t%0,%1 |
808 | c<g>hi\t%0,%h1 | |
963fc8d0 | 809 | c<g>hsi\t%0,%h1 |
3298c037 AK |
810 | c<g>fi\t%0,%1 |
811 | c<g>\t%0,%1 | |
963fc8d0 AK |
812 | c<y>\t%0,%1 |
813 | c<g>rl\t%0,%1" | |
814 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
815 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
816 | (set_attr "type" "*,*,*,*,*,*,larl") |
817 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 818 | |
07893d4f UW |
819 | |
820 | ; Compare (unsigned) instructions | |
9db1d521 | 821 | |
963fc8d0 AK |
822 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
823 | [(set (reg CC_REGNUM) | |
824 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
825 | "larl_operand" "X"))) | |
826 | (match_operand:SI 0 "register_operand" "d")))] | |
827 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
828 | "clhrl\t%0,%1" | |
829 | [(set_attr "op_type" "RIL") | |
729e750f WG |
830 | (set_attr "type" "larl") |
831 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
832 | |
833 | ; clhrl, clghrl | |
834 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
835 | [(set (reg CC_REGNUM) | |
836 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
837 | "larl_operand" "X"))) | |
838 | (match_operand:GPR 0 "register_operand" "d")))] | |
839 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
840 | "cl<g>hrl\t%0,%1" | |
841 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
842 | (set_attr "type" "larl") |
843 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 844 | |
07893d4f | 845 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 846 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
847 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
848 | "d,RT,b")) | |
849 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
575f7c2b | 850 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 851 | "@ |
d40c829f | 852 | clgfr\t%0,%1 |
963fc8d0 AK |
853 | clgf\t%0,%1 |
854 | clgfrl\t%0,%1" | |
855 | [(set_attr "op_type" "RRE,RXY,RIL") | |
856 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
857 | (set_attr "type" "*,*,larl") |
858 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 859 | |
07893d4f | 860 | (define_insn "*cmpdi_ccu" |
ae156f85 | 861 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
862 | (compare (match_operand:DI 0 "nonimmediate_operand" |
863 | "d, d,d,Q, d, Q,BQ") | |
864 | (match_operand:DI 1 "general_operand" | |
865 | "d,Op,b,D,RT,BQ,Q")))] | |
e221ef54 | 866 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" |
07893d4f | 867 | "@ |
d40c829f | 868 | clgr\t%0,%1 |
ec24698e | 869 | clgfi\t%0,%1 |
963fc8d0 AK |
870 | clgrl\t%0,%1 |
871 | clghsi\t%0,%x1 | |
575f7c2b | 872 | clg\t%0,%1 |
e221ef54 | 873 | # |
19b63d8e | 874 | #" |
963fc8d0 AK |
875 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
876 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
877 | (set_attr "type" "*,*,larl,*,*,*,*") |
878 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 879 | |
07893d4f | 880 | (define_insn "*cmpsi_ccu" |
ae156f85 | 881 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
882 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
883 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 884 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 885 | "@ |
d40c829f | 886 | clr\t%0,%1 |
ec24698e | 887 | clfi\t%0,%o1 |
963fc8d0 AK |
888 | clrl\t%0,%1 |
889 | clfhsi\t%0,%x1 | |
d40c829f | 890 | cl\t%0,%1 |
575f7c2b | 891 | cly\t%0,%1 |
e221ef54 | 892 | # |
19b63d8e | 893 | #" |
963fc8d0 AK |
894 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
895 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
896 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
897 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 898 | |
07893d4f | 899 | (define_insn "*cmphi_ccu" |
ae156f85 | 900 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
901 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
902 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 903 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 904 | && !register_operand (operands[1], HImode)" |
d3632d41 | 905 | "@ |
fc0ea003 UW |
906 | clm\t%0,3,%S1 |
907 | clmy\t%0,3,%S1 | |
963fc8d0 | 908 | clhhsi\t%0,%1 |
e221ef54 | 909 | # |
19b63d8e | 910 | #" |
963fc8d0 | 911 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
912 | (set_attr "cpu_facility" "*,*,z10,*,*") |
913 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
914 | |
915 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 916 | [(set (reg CC_REGNUM) |
e221ef54 UW |
917 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
918 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 919 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 920 | && !register_operand (operands[1], QImode)" |
d3632d41 | 921 | "@ |
fc0ea003 UW |
922 | clm\t%0,1,%S1 |
923 | clmy\t%0,1,%S1 | |
924 | cli\t%S0,%b1 | |
925 | cliy\t%S0,%b1 | |
e221ef54 | 926 | # |
19b63d8e | 927 | #" |
9381e3f1 WG |
928 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
929 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
930 | |
931 | ||
19b63d8e UW |
932 | ; Block compare (CLC) instruction patterns. |
933 | ||
934 | (define_insn "*clc" | |
ae156f85 | 935 | [(set (reg CC_REGNUM) |
d4f52f0e | 936 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
937 | (match_operand:BLK 1 "memory_operand" "Q"))) |
938 | (use (match_operand 2 "const_int_operand" "n"))] | |
939 | "s390_match_ccmode (insn, CCUmode) | |
940 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 941 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 942 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
943 | |
944 | (define_split | |
ae156f85 | 945 | [(set (reg CC_REGNUM) |
19b63d8e UW |
946 | (compare (match_operand 0 "memory_operand" "") |
947 | (match_operand 1 "memory_operand" "")))] | |
948 | "reload_completed | |
949 | && s390_match_ccmode (insn, CCUmode) | |
950 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
951 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
952 | [(parallel | |
953 | [(set (match_dup 0) (match_dup 1)) | |
954 | (use (match_dup 2))])] | |
955 | { | |
956 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
957 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
958 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
959 | ||
960 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
961 | operands[0], operands[1]); | |
962 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
963 | }) | |
964 | ||
965 | ||
609e7e80 | 966 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 967 | |
609e7e80 | 968 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 969 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 970 | [(set (reg CC_REGNUM) |
609e7e80 AK |
971 | (compare (match_operand:FP 0 "register_operand" "f") |
972 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 973 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 974 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 975 | [(set_attr "op_type" "RRE") |
9381e3f1 | 976 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 977 | |
d46f24b6 | 978 | ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr |
f5905b37 | 979 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 980 | [(set (reg CC_REGNUM) |
609e7e80 AK |
981 | (compare (match_operand:FP 0 "register_operand" "f,f") |
982 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 983 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 984 | "@ |
609e7e80 | 985 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 986 | c<xde>b\t%0,%1" |
077dab3b | 987 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 988 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 989 | |
963fc8d0 AK |
990 | |
991 | ; Compare and Branch instructions | |
992 | ||
993 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
994 | ; The following instructions do a complementary access of their second |
995 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
996 | (define_insn "*cmp_and_br_signed_<mode>" |
997 | [(set (pc) | |
998 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
999 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1000 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1001 | (label_ref (match_operand 3 "" "")) | |
1002 | (pc))) | |
1003 | (clobber (reg:CC CC_REGNUM))] | |
1004 | "TARGET_Z10" | |
1005 | { | |
1006 | if (get_attr_length (insn) == 6) | |
1007 | return which_alternative ? | |
1008 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1009 | else | |
1010 | return which_alternative ? | |
1011 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1012 | } | |
1013 | [(set_attr "op_type" "RIE") | |
1014 | (set_attr "type" "branch") | |
e3cba5e5 | 1015 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1016 | (set (attr "length") |
1017 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1018 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1019 | ; 10 byte for cgr/jg | |
1020 | ||
1021 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1022 | ; The following instructions do a complementary access of their second |
1023 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1024 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1025 | [(set (pc) | |
1026 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1027 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1028 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1029 | (label_ref (match_operand 3 "" "")) | |
1030 | (pc))) | |
1031 | (clobber (reg:CC CC_REGNUM))] | |
1032 | "TARGET_Z10" | |
1033 | { | |
1034 | if (get_attr_length (insn) == 6) | |
1035 | return which_alternative ? | |
1036 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1037 | else | |
1038 | return which_alternative ? | |
1039 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1040 | } | |
1041 | [(set_attr "op_type" "RIE") | |
1042 | (set_attr "type" "branch") | |
e3cba5e5 | 1043 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1044 | (set (attr "length") |
1045 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1046 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1047 | ; 10 byte for clgr/jg | |
1048 | ||
9db1d521 HP |
1049 | ;; |
1050 | ;;- Move instructions. | |
1051 | ;; | |
1052 | ||
1053 | ; | |
1054 | ; movti instruction pattern(s). | |
1055 | ; | |
1056 | ||
1057 | (define_insn "movti" | |
f2dc2f86 AK |
1058 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") |
1059 | (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] | |
9db1d521 | 1060 | "TARGET_64BIT" |
4023fb28 | 1061 | "@ |
fc0ea003 UW |
1062 | lmg\t%0,%N0,%S1 |
1063 | stmg\t%1,%N1,%S0 | |
4023fb28 | 1064 | # |
19b63d8e | 1065 | #" |
f2dc2f86 AK |
1066 | [(set_attr "op_type" "RSY,RSY,*,*") |
1067 | (set_attr "type" "lm,stm,*,*")]) | |
4023fb28 UW |
1068 | |
1069 | (define_split | |
1070 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1071 | (match_operand:TI 1 "general_operand" ""))] | |
1072 | "TARGET_64BIT && reload_completed | |
dc65c307 | 1073 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1074 | [(set (match_dup 2) (match_dup 4)) |
1075 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1076 | { |
dc65c307 UW |
1077 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1078 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1079 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1080 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1081 | }) | |
1082 | ||
1083 | (define_split | |
1084 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1085 | (match_operand:TI 1 "general_operand" ""))] | |
1086 | "TARGET_64BIT && reload_completed | |
1087 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
1088 | [(set (match_dup 2) (match_dup 4)) | |
1089 | (set (match_dup 3) (match_dup 5))] | |
1090 | { | |
1091 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1092 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1093 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1094 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1095 | }) | |
4023fb28 UW |
1096 | |
1097 | (define_split | |
1098 | [(set (match_operand:TI 0 "register_operand" "") | |
1099 | (match_operand:TI 1 "memory_operand" ""))] | |
1100 | "TARGET_64BIT && reload_completed | |
1101 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 1102 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1103 | { |
1104 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
1105 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1106 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1107 | }) |
1108 | ||
833cd70a AK |
1109 | |
1110 | ; | |
1111 | ; Patterns used for secondary reloads | |
1112 | ; | |
1113 | ||
963fc8d0 AK |
1114 | ; z10 provides move instructions accepting larl memory operands. |
1115 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1116 | ; These patterns are also used for unaligned SI and DI accesses. | |
1117 | ||
1118 | (define_expand "reload<INTALL:mode><P:mode>_tomem_z10" | |
1119 | [(parallel [(match_operand:INTALL 0 "memory_operand" "") | |
1120 | (match_operand:INTALL 1 "register_operand" "=d") | |
1121 | (match_operand:P 2 "register_operand" "=&a")])] | |
1122 | "TARGET_Z10" | |
1123 | { | |
1124 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1125 | DONE; | |
1126 | }) | |
1127 | ||
1128 | (define_expand "reload<INTALL:mode><P:mode>_toreg_z10" | |
1129 | [(parallel [(match_operand:INTALL 0 "register_operand" "=d") | |
1130 | (match_operand:INTALL 1 "memory_operand" "") | |
1131 | (match_operand:P 2 "register_operand" "=a")])] | |
1132 | "TARGET_Z10" | |
1133 | { | |
1134 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1135 | DONE; | |
1136 | }) | |
1137 | ||
1138 | (define_expand "reload<FPALL:mode><P:mode>_tomem_z10" | |
1139 | [(parallel [(match_operand:FPALL 0 "memory_operand" "") | |
1140 | (match_operand:FPALL 1 "register_operand" "=d") | |
1141 | (match_operand:P 2 "register_operand" "=&a")])] | |
1142 | "TARGET_Z10" | |
1143 | { | |
1144 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1145 | DONE; | |
1146 | }) | |
1147 | ||
1148 | (define_expand "reload<FPALL:mode><P:mode>_toreg_z10" | |
1149 | [(parallel [(match_operand:FPALL 0 "register_operand" "=d") | |
1150 | (match_operand:FPALL 1 "memory_operand" "") | |
1151 | (match_operand:P 2 "register_operand" "=a")])] | |
1152 | "TARGET_Z10" | |
1153 | { | |
1154 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1155 | DONE; | |
1156 | }) | |
1157 | ||
1158 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1159 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1160 | (match_operand:P 1 "larl_operand" "") | |
1161 | (match_operand:P 2 "register_operand" "=a")])] | |
1162 | "TARGET_Z10" | |
1163 | { | |
1164 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1165 | DONE; | |
1166 | }) | |
1167 | ||
833cd70a AK |
1168 | ; Handles loading a PLUS (load address) expression |
1169 | ||
1170 | (define_expand "reload<mode>_plus" | |
1171 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1172 | (match_operand:P 1 "s390_plus_operand" "") | |
1173 | (match_operand:P 2 "register_operand" "=&a")])] | |
1174 | "" | |
1175 | { | |
1176 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1177 | DONE; | |
1178 | }) | |
1179 | ||
1180 | ; Handles assessing a non-offsetable memory address | |
1181 | ||
1182 | (define_expand "reload<mode>_nonoffmem_in" | |
1183 | [(parallel [(match_operand 0 "register_operand" "") | |
1184 | (match_operand 1 "" "") | |
1185 | (match_operand:P 2 "register_operand" "=&a")])] | |
1186 | "" | |
1187 | { | |
1188 | gcc_assert (MEM_P (operands[1])); | |
1189 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1190 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1191 | emit_move_insn (operands[0], operands[1]); | |
1192 | DONE; | |
1193 | }) | |
1194 | ||
1195 | (define_expand "reload<mode>_nonoffmem_out" | |
1196 | [(parallel [(match_operand 0 "" "") | |
1197 | (match_operand 1 "register_operand" "") | |
1198 | (match_operand:P 2 "register_operand" "=&a")])] | |
1199 | "" | |
dc65c307 | 1200 | { |
9c3c3dcc | 1201 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1202 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1203 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1204 | emit_move_insn (operands[0], operands[1]); | |
1205 | DONE; | |
1206 | }) | |
9db1d521 | 1207 | |
1f9e1fc6 AK |
1208 | (define_expand "reload<mode>_PIC_addr" |
1209 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1210 | (match_operand 1 "larl_operand" "") | |
1211 | (match_operand:P 2 "register_operand" "=a")])] | |
1212 | "" | |
1213 | { | |
0a2aaacc KG |
1214 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1215 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1216 | }) |
1217 | ||
9db1d521 HP |
1218 | ; |
1219 | ; movdi instruction pattern(s). | |
1220 | ; | |
1221 | ||
9db1d521 HP |
1222 | (define_expand "movdi" |
1223 | [(set (match_operand:DI 0 "general_operand" "") | |
1224 | (match_operand:DI 1 "general_operand" ""))] | |
1225 | "" | |
9db1d521 | 1226 | { |
fd3cd001 | 1227 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1228 | if (TARGET_64BIT |
1229 | && (SYMBOLIC_CONST (operands[1]) | |
1230 | || (GET_CODE (operands[1]) == PLUS | |
1231 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1232 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1233 | emit_symbolic_move (operands); |
10bbf137 | 1234 | }) |
9db1d521 | 1235 | |
4023fb28 UW |
1236 | (define_insn "*movdi_larl" |
1237 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1238 | (match_operand:DI 1 "larl_operand" "X"))] | |
1239 | "TARGET_64BIT | |
8e509cf9 | 1240 | && !FP_REG_P (operands[0])" |
d40c829f | 1241 | "larl\t%0,%1" |
4023fb28 | 1242 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1243 | (set_attr "type" "larl") |
1244 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1245 | |
3af8e996 | 1246 | (define_insn "*movdi_64" |
85dae55a | 1247 | [(set (match_operand:DI 0 "nonimmediate_operand" |
963fc8d0 | 1248 | "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, |
f2dc2f86 | 1249 | RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") |
85dae55a | 1250 | (match_operand:DI 1 "general_operand" |
963fc8d0 | 1251 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, |
f2dc2f86 | 1252 | d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] |
3af8e996 | 1253 | "TARGET_64BIT" |
85dae55a AK |
1254 | "@ |
1255 | lghi\t%0,%h1 | |
1256 | llihh\t%0,%i1 | |
1257 | llihl\t%0,%i1 | |
1258 | llilh\t%0,%i1 | |
1259 | llill\t%0,%i1 | |
1260 | lgfi\t%0,%1 | |
1261 | llihf\t%0,%k1 | |
1262 | llilf\t%0,%k1 | |
1263 | ldgr\t%0,%1 | |
1264 | lgdr\t%0,%1 | |
1265 | lay\t%0,%a1 | |
963fc8d0 | 1266 | lgrl\t%0,%1 |
85dae55a AK |
1267 | lgr\t%0,%1 |
1268 | lg\t%0,%1 | |
1269 | stg\t%1,%0 | |
1270 | ldr\t%0,%1 | |
1271 | ld\t%0,%1 | |
1272 | ldy\t%0,%1 | |
1273 | std\t%1,%0 | |
1274 | stdy\t%1,%0 | |
963fc8d0 AK |
1275 | stgrl\t%1,%0 |
1276 | mvghi\t%0,%1 | |
85dae55a AK |
1277 | # |
1278 | # | |
1279 | stam\t%1,%N1,%S0 | |
f2dc2f86 | 1280 | lam\t%0,%N0,%S1" |
963fc8d0 | 1281 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
f2dc2f86 | 1282 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS") |
963fc8d0 AK |
1283 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
1284 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, | |
f2dc2f86 | 1285 | *,*") |
3af8e996 | 1286 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1287 | z10,*,*,*,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1288 | z10,z10,*,*,*,*") |
9381e3f1 WG |
1289 | (set_attr "z10prop" "z10_fwd_A1, |
1290 | z10_fwd_E1, | |
1291 | z10_fwd_E1, | |
1292 | z10_fwd_E1, | |
1293 | z10_fwd_E1, | |
1294 | z10_fwd_A1, | |
1295 | z10_fwd_E1, | |
1296 | z10_fwd_E1, | |
1297 | *, | |
1298 | *, | |
1299 | z10_fwd_A1, | |
1300 | z10_fwd_A3, | |
1301 | z10_fr_E1, | |
1302 | z10_fwd_A3, | |
1303 | z10_rec, | |
1304 | *, | |
1305 | *, | |
1306 | *, | |
1307 | *, | |
1308 | *, | |
1309 | z10_rec, | |
1310 | z10_super, | |
1311 | *, | |
1312 | *, | |
1313 | *, | |
9381e3f1 WG |
1314 | *") |
1315 | ]) | |
c5aa1d12 UW |
1316 | |
1317 | (define_split | |
1318 | [(set (match_operand:DI 0 "register_operand" "") | |
1319 | (match_operand:DI 1 "register_operand" ""))] | |
1320 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
1321 | [(set (match_dup 2) (match_dup 3)) | |
1322 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1323 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1324 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1325 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1326 | ||
1327 | (define_split | |
1328 | [(set (match_operand:DI 0 "register_operand" "") | |
1329 | (match_operand:DI 1 "register_operand" ""))] | |
1330 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1331 | && dead_or_set_p (insn, operands[1])" | |
1332 | [(set (match_dup 3) (match_dup 2)) | |
1333 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1334 | (set (match_dup 4) (match_dup 2))] | |
1335 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1336 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1337 | ||
1338 | (define_split | |
1339 | [(set (match_operand:DI 0 "register_operand" "") | |
1340 | (match_operand:DI 1 "register_operand" ""))] | |
1341 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1342 | && !dead_or_set_p (insn, operands[1])" | |
1343 | [(set (match_dup 3) (match_dup 2)) | |
1344 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1345 | (set (match_dup 4) (match_dup 2)) | |
1346 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1347 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1348 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1349 | |
1350 | (define_insn "*movdi_31" | |
963fc8d0 | 1351 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1352 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1353 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1354 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9db1d521 | 1355 | "!TARGET_64BIT" |
4023fb28 | 1356 | "@ |
fc0ea003 | 1357 | lm\t%0,%N0,%S1 |
c4d50129 | 1358 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1359 | stm\t%1,%N1,%S0 |
c4d50129 | 1360 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1361 | # |
1362 | # | |
d40c829f UW |
1363 | ldr\t%0,%1 |
1364 | ld\t%0,%1 | |
1365 | ldy\t%0,%1 | |
1366 | std\t%1,%0 | |
1367 | stdy\t%1,%0 | |
19b63d8e | 1368 | #" |
f2dc2f86 AK |
1369 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1370 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1371 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1372 | |
1373 | ; For a load from a symbol ref we can use one of the target registers | |
1374 | ; together with larl to load the address. | |
1375 | (define_split | |
1376 | [(set (match_operand:DI 0 "register_operand" "") | |
1377 | (match_operand:DI 1 "memory_operand" ""))] | |
1378 | "!TARGET_64BIT && reload_completed && TARGET_Z10 | |
1379 | && larl_operand (XEXP (operands[1], 0), SImode)" | |
1380 | [(set (match_dup 2) (match_dup 3)) | |
1381 | (set (match_dup 0) (match_dup 1))] | |
1382 | { | |
1383 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1384 | operands[3] = XEXP (operands[1], 0); | |
1385 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1386 | }) | |
4023fb28 UW |
1387 | |
1388 | (define_split | |
1389 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1390 | (match_operand:DI 1 "general_operand" ""))] | |
1391 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1392 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1393 | [(set (match_dup 2) (match_dup 4)) |
1394 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1395 | { |
dc65c307 UW |
1396 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1397 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1398 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1399 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1400 | }) | |
1401 | ||
1402 | (define_split | |
1403 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1404 | (match_operand:DI 1 "general_operand" ""))] | |
1405 | "!TARGET_64BIT && reload_completed | |
1406 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1407 | [(set (match_dup 2) (match_dup 4)) | |
1408 | (set (match_dup 3) (match_dup 5))] | |
1409 | { | |
1410 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1411 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1412 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1413 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1414 | }) | |
9db1d521 | 1415 | |
4023fb28 UW |
1416 | (define_split |
1417 | [(set (match_operand:DI 0 "register_operand" "") | |
1418 | (match_operand:DI 1 "memory_operand" ""))] | |
1419 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1420 | && !FP_REG_P (operands[0]) |
4023fb28 | 1421 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1422 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1423 | { |
1424 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1425 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1426 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1427 | }) |
1428 | ||
84817c5d UW |
1429 | (define_peephole2 |
1430 | [(set (match_operand:DI 0 "register_operand" "") | |
1431 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1432 | "TARGET_64BIT | |
1433 | && !FP_REG_P (operands[0]) | |
1434 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1435 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1436 | && get_pool_mode (operands[1]) == DImode | |
1437 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1438 | [(set (match_dup 0) (match_dup 2))] | |
1439 | "operands[2] = get_pool_constant (operands[1]);") | |
1440 | ||
7bdff56f UW |
1441 | (define_insn "*la_64" |
1442 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1443 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1444 | "TARGET_64BIT" |
1445 | "@ | |
1446 | la\t%0,%a1 | |
1447 | lay\t%0,%a1" | |
1448 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1449 | (set_attr "type" "la") |
1450 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1451 | |
1452 | (define_peephole2 | |
1453 | [(parallel | |
1454 | [(set (match_operand:DI 0 "register_operand" "") | |
1455 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1456 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1457 | "TARGET_64BIT |
e1d5ee28 | 1458 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1459 | [(set (match_dup 0) (match_dup 1))] |
1460 | "") | |
1461 | ||
1462 | (define_peephole2 | |
1463 | [(set (match_operand:DI 0 "register_operand" "") | |
1464 | (match_operand:DI 1 "register_operand" "")) | |
1465 | (parallel | |
1466 | [(set (match_dup 0) | |
1467 | (plus:DI (match_dup 0) | |
1468 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1469 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1470 | "TARGET_64BIT |
1471 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1472 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1473 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1474 | "") | |
1475 | ||
9db1d521 HP |
1476 | ; |
1477 | ; movsi instruction pattern(s). | |
1478 | ; | |
1479 | ||
9db1d521 HP |
1480 | (define_expand "movsi" |
1481 | [(set (match_operand:SI 0 "general_operand" "") | |
1482 | (match_operand:SI 1 "general_operand" ""))] | |
1483 | "" | |
9db1d521 | 1484 | { |
fd3cd001 | 1485 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1486 | if (!TARGET_64BIT |
1487 | && (SYMBOLIC_CONST (operands[1]) | |
1488 | || (GET_CODE (operands[1]) == PLUS | |
1489 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1490 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1491 | emit_symbolic_move (operands); |
10bbf137 | 1492 | }) |
9db1d521 | 1493 | |
9e8327e3 UW |
1494 | (define_insn "*movsi_larl" |
1495 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1496 | (match_operand:SI 1 "larl_operand" "X"))] | |
1497 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1498 | && !FP_REG_P (operands[0])" | |
1499 | "larl\t%0,%1" | |
1500 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1501 | (set_attr "type" "larl") |
729e750f | 1502 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1503 | |
f19a9af7 | 1504 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1505 | [(set (match_operand:SI 0 "nonimmediate_operand" |
f2dc2f86 | 1506 | "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t") |
2f7e5a0d | 1507 | (match_operand:SI 1 "general_operand" |
f2dc2f86 | 1508 | "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))] |
f19a9af7 | 1509 | "TARGET_ZARCH" |
9db1d521 | 1510 | "@ |
f19a9af7 AK |
1511 | lhi\t%0,%h1 |
1512 | llilh\t%0,%i1 | |
1513 | llill\t%0,%i1 | |
ec24698e | 1514 | iilf\t%0,%o1 |
f19a9af7 | 1515 | lay\t%0,%a1 |
963fc8d0 | 1516 | lrl\t%0,%1 |
d40c829f UW |
1517 | lr\t%0,%1 |
1518 | l\t%0,%1 | |
1519 | ly\t%0,%1 | |
1520 | st\t%1,%0 | |
1521 | sty\t%1,%0 | |
1522 | ler\t%0,%1 | |
1523 | le\t%0,%1 | |
1524 | ley\t%0,%1 | |
1525 | ste\t%1,%0 | |
1526 | stey\t%1,%0 | |
c5aa1d12 UW |
1527 | ear\t%0,%1 |
1528 | sar\t%0,%1 | |
1529 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1530 | strl\t%1,%0 |
1531 | mvhi\t%0,%1 | |
f2dc2f86 | 1532 | lam\t%0,%0,%S1" |
963fc8d0 | 1533 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
f2dc2f86 | 1534 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS") |
9381e3f1 WG |
1535 | (set_attr "type" "*, |
1536 | *, | |
1537 | *, | |
1538 | *, | |
1539 | la, | |
1540 | larl, | |
1541 | lr, | |
1542 | load, | |
1543 | load, | |
1544 | store, | |
1545 | store, | |
1546 | floadsf, | |
1547 | floadsf, | |
1548 | floadsf, | |
1549 | fstoresf, | |
1550 | fstoresf, | |
1551 | *, | |
1552 | *, | |
1553 | *, | |
1554 | larl, | |
1555 | *, | |
9381e3f1 | 1556 | *") |
963fc8d0 | 1557 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1558 | *,*,longdisp,*,longdisp,*,*,*,z10,z10,*") |
9381e3f1 WG |
1559 | (set_attr "z10prop" "z10_fwd_A1, |
1560 | z10_fwd_E1, | |
1561 | z10_fwd_E1, | |
1562 | z10_fwd_A1, | |
1563 | z10_fwd_A1, | |
1564 | z10_fwd_A3, | |
1565 | z10_fr_E1, | |
1566 | z10_fwd_A3, | |
1567 | z10_fwd_A3, | |
729e750f | 1568 | z10_rec, |
9381e3f1 WG |
1569 | z10_rec, |
1570 | *, | |
1571 | *, | |
1572 | *, | |
1573 | *, | |
1574 | *, | |
1575 | z10_super_E1, | |
1576 | z10_super, | |
1577 | *, | |
1578 | z10_rec, | |
1579 | z10_super, | |
9381e3f1 | 1580 | *")]) |
f19a9af7 AK |
1581 | |
1582 | (define_insn "*movsi_esa" | |
f2dc2f86 AK |
1583 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t") |
1584 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1585 | "!TARGET_ZARCH" |
1586 | "@ | |
1587 | lhi\t%0,%h1 | |
1588 | lr\t%0,%1 | |
1589 | l\t%0,%1 | |
1590 | st\t%1,%0 | |
1591 | ler\t%0,%1 | |
1592 | le\t%0,%1 | |
1593 | ste\t%1,%0 | |
c5aa1d12 UW |
1594 | ear\t%0,%1 |
1595 | sar\t%0,%1 | |
1596 | stam\t%1,%1,%S0 | |
f2dc2f86 AK |
1597 | lam\t%0,%0,%S1" |
1598 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS") | |
1599 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*") | |
9381e3f1 WG |
1600 | (set_attr "z10prop" "z10_fwd_A1, |
1601 | z10_fr_E1, | |
1602 | z10_fwd_A3, | |
729e750f | 1603 | z10_rec, |
9381e3f1 WG |
1604 | *, |
1605 | *, | |
1606 | *, | |
1607 | z10_super_E1, | |
1608 | z10_super, | |
1609 | *, | |
9381e3f1 WG |
1610 | *") |
1611 | ]) | |
9db1d521 | 1612 | |
84817c5d UW |
1613 | (define_peephole2 |
1614 | [(set (match_operand:SI 0 "register_operand" "") | |
1615 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1616 | "!FP_REG_P (operands[0]) | |
1617 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1618 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1619 | && get_pool_mode (operands[1]) == SImode | |
1620 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1621 | [(set (match_dup 0) (match_dup 2))] | |
1622 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1623 | |
7bdff56f UW |
1624 | (define_insn "*la_31" |
1625 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1626 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1627 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1628 | "@ | |
1629 | la\t%0,%a1 | |
1630 | lay\t%0,%a1" | |
1631 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1632 | (set_attr "type" "la") |
1633 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1634 | |
1635 | (define_peephole2 | |
1636 | [(parallel | |
1637 | [(set (match_operand:SI 0 "register_operand" "") | |
1638 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1639 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1640 | "!TARGET_64BIT |
e1d5ee28 | 1641 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1642 | [(set (match_dup 0) (match_dup 1))] |
1643 | "") | |
1644 | ||
1645 | (define_peephole2 | |
1646 | [(set (match_operand:SI 0 "register_operand" "") | |
1647 | (match_operand:SI 1 "register_operand" "")) | |
1648 | (parallel | |
1649 | [(set (match_dup 0) | |
1650 | (plus:SI (match_dup 0) | |
1651 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1652 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1653 | "!TARGET_64BIT |
1654 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1655 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1656 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1657 | "") | |
1658 | ||
1659 | (define_insn "*la_31_and" | |
1660 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1661 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
1662 | (const_int 2147483647)))] |
1663 | "!TARGET_64BIT" | |
1664 | "@ | |
1665 | la\t%0,%a1 | |
1666 | lay\t%0,%a1" | |
1667 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1668 | (set_attr "type" "la") |
1669 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1670 | |
1671 | (define_insn_and_split "*la_31_and_cc" | |
1672 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1673 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1674 | (const_int 2147483647))) | |
ae156f85 | 1675 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1676 | "!TARGET_64BIT" |
1677 | "#" | |
1678 | "&& reload_completed" | |
1679 | [(set (match_dup 0) | |
1680 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1681 | "" | |
1682 | [(set_attr "op_type" "RX") | |
1683 | (set_attr "type" "la")]) | |
1684 | ||
1685 | (define_insn "force_la_31" | |
1686 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1687 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
1688 | (use (const_int 0))] |
1689 | "!TARGET_64BIT" | |
1690 | "@ | |
1691 | la\t%0,%a1 | |
1692 | lay\t%0,%a1" | |
1693 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
1694 | (set_attr "type" "la") |
1695 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 1696 | |
9db1d521 HP |
1697 | ; |
1698 | ; movhi instruction pattern(s). | |
1699 | ; | |
1700 | ||
02ed3c5e UW |
1701 | (define_expand "movhi" |
1702 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1703 | (match_operand:HI 1 "general_operand" ""))] | |
1704 | "" | |
1705 | { | |
2f7e5a0d | 1706 | /* Make it explicit that loading a register from memory |
02ed3c5e | 1707 | always sign-extends (at least) to SImode. */ |
b3a13419 | 1708 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 1709 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1710 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1711 | { |
1712 | rtx tmp = gen_reg_rtx (SImode); | |
1713 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1714 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1715 | operands[1] = gen_lowpart (HImode, tmp); | |
1716 | } | |
1717 | }) | |
1718 | ||
1719 | (define_insn "*movhi" | |
f2dc2f86 AK |
1720 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q") |
1721 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))] | |
9db1d521 HP |
1722 | "" |
1723 | "@ | |
d40c829f UW |
1724 | lr\t%0,%1 |
1725 | lhi\t%0,%h1 | |
1726 | lh\t%0,%1 | |
1727 | lhy\t%0,%1 | |
963fc8d0 | 1728 | lhrl\t%0,%1 |
d40c829f UW |
1729 | sth\t%1,%0 |
1730 | sthy\t%1,%0 | |
963fc8d0 | 1731 | sthrl\t%1,%0 |
f2dc2f86 AK |
1732 | mvhhi\t%0,%1" |
1733 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL") | |
1734 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*") | |
1735 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10") | |
9381e3f1 WG |
1736 | (set_attr "z10prop" "z10_fr_E1, |
1737 | z10_fwd_A1, | |
1738 | z10_super_E1, | |
1739 | z10_super_E1, | |
1740 | z10_super_E1, | |
729e750f | 1741 | z10_rec, |
9381e3f1 WG |
1742 | z10_rec, |
1743 | z10_rec, | |
f2dc2f86 | 1744 | z10_super")]) |
9db1d521 | 1745 | |
84817c5d UW |
1746 | (define_peephole2 |
1747 | [(set (match_operand:HI 0 "register_operand" "") | |
1748 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1749 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1750 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1751 | && get_pool_mode (operands[1]) == HImode | |
1752 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1753 | [(set (match_dup 0) (match_dup 2))] | |
1754 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1755 | |
9db1d521 HP |
1756 | ; |
1757 | ; movqi instruction pattern(s). | |
1758 | ; | |
1759 | ||
02ed3c5e UW |
1760 | (define_expand "movqi" |
1761 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1762 | (match_operand:QI 1 "general_operand" ""))] | |
1763 | "" | |
1764 | { | |
c19ec8f9 | 1765 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1766 | is just as fast as a QImode load. */ |
b3a13419 | 1767 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 1768 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1769 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1770 | { |
c19ec8f9 UW |
1771 | rtx tmp = gen_reg_rtx (word_mode); |
1772 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1773 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1774 | operands[1] = gen_lowpart (QImode, tmp); | |
1775 | } | |
1776 | }) | |
4023fb28 | 1777 | |
02ed3c5e | 1778 | (define_insn "*movqi" |
f2dc2f86 AK |
1779 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S") |
1780 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))] | |
9db1d521 HP |
1781 | "" |
1782 | "@ | |
d40c829f UW |
1783 | lr\t%0,%1 |
1784 | lhi\t%0,%b1 | |
1785 | ic\t%0,%1 | |
1786 | icy\t%0,%1 | |
1787 | stc\t%1,%0 | |
1788 | stcy\t%1,%0 | |
fc0ea003 | 1789 | mvi\t%S0,%b1 |
f2dc2f86 AK |
1790 | mviy\t%S0,%b1" |
1791 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY") | |
1792 | (set_attr "type" "lr,*,*,*,store,store,store,store") | |
9381e3f1 WG |
1793 | (set_attr "z10prop" "z10_fr_E1, |
1794 | z10_fwd_A1, | |
1795 | z10_super_E1, | |
1796 | z10_super_E1, | |
729e750f | 1797 | z10_rec, |
9381e3f1 WG |
1798 | z10_rec, |
1799 | z10_super, | |
f2dc2f86 | 1800 | z10_super")]) |
9db1d521 | 1801 | |
84817c5d UW |
1802 | (define_peephole2 |
1803 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1804 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1805 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1806 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1807 | && get_pool_mode (operands[1]) == QImode | |
1808 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1809 | [(set (match_dup 0) (match_dup 2))] | |
1810 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1811 | |
9db1d521 | 1812 | ; |
05b9aaaa | 1813 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1814 | ; |
1815 | ||
1816 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1817 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1818 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1819 | "" |
d3632d41 | 1820 | "@ |
d40c829f UW |
1821 | ic\t%0,%1 |
1822 | icy\t%0,%1" | |
9381e3f1 | 1823 | [(set_attr "op_type" "RX,RXY") |
729e750f | 1824 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
1825 | |
1826 | ; | |
1827 | ; movstricthi instruction pattern(s). | |
1828 | ; | |
1829 | ||
1830 | (define_insn "*movstricthi" | |
d3632d41 | 1831 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1832 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1833 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1834 | "" |
d3632d41 | 1835 | "@ |
fc0ea003 UW |
1836 | icm\t%0,3,%S1 |
1837 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
1838 | [(set_attr "op_type" "RS,RSY") |
1839 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
1840 | |
1841 | ; | |
1842 | ; movstrictsi instruction pattern(s). | |
1843 | ; | |
1844 | ||
05b9aaaa | 1845 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1846 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1847 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1848 | "TARGET_64BIT" |
1849 | "@ | |
d40c829f UW |
1850 | lr\t%0,%1 |
1851 | l\t%0,%1 | |
c5aa1d12 UW |
1852 | ly\t%0,%1 |
1853 | ear\t%0,%1" | |
1854 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
1855 | (set_attr "type" "lr,load,load,*") |
1856 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 1857 | |
f61a2c7d | 1858 | ; |
609e7e80 | 1859 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
1860 | ; |
1861 | ||
609e7e80 AK |
1862 | (define_expand "mov<mode>" |
1863 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
1864 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
1865 | "" |
1866 | "") | |
1867 | ||
609e7e80 | 1868 | (define_insn "*mov<mode>_64" |
f2dc2f86 AK |
1869 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
1870 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
f61a2c7d AK |
1871 | "TARGET_64BIT" |
1872 | "@ | |
1873 | lzxr\t%0 | |
1874 | lxr\t%0,%1 | |
1875 | # | |
1876 | # | |
1877 | lmg\t%0,%N0,%S1 | |
1878 | stmg\t%1,%N1,%S0 | |
1879 | # | |
f61a2c7d | 1880 | #" |
f2dc2f86 AK |
1881 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
1882 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")]) | |
f61a2c7d | 1883 | |
609e7e80 | 1884 | (define_insn "*mov<mode>_31" |
f2dc2f86 AK |
1885 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
1886 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
f61a2c7d AK |
1887 | "!TARGET_64BIT" |
1888 | "@ | |
1889 | lzxr\t%0 | |
1890 | lxr\t%0,%1 | |
1891 | # | |
f61a2c7d | 1892 | #" |
f2dc2f86 AK |
1893 | [(set_attr "op_type" "RRE,RRE,*,*") |
1894 | (set_attr "type" "fsimptf,fsimptf,*,*")]) | |
f61a2c7d AK |
1895 | |
1896 | ; TFmode in GPRs splitters | |
1897 | ||
1898 | (define_split | |
609e7e80 AK |
1899 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
1900 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d | 1901 | "TARGET_64BIT && reload_completed |
609e7e80 | 1902 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
1903 | [(set (match_dup 2) (match_dup 4)) |
1904 | (set (match_dup 3) (match_dup 5))] | |
1905 | { | |
609e7e80 AK |
1906 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
1907 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
1908 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
1909 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
1910 | }) |
1911 | ||
1912 | (define_split | |
609e7e80 AK |
1913 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
1914 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d | 1915 | "TARGET_64BIT && reload_completed |
609e7e80 | 1916 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
1917 | [(set (match_dup 2) (match_dup 4)) |
1918 | (set (match_dup 3) (match_dup 5))] | |
1919 | { | |
609e7e80 AK |
1920 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
1921 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
1922 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
1923 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
1924 | }) |
1925 | ||
1926 | (define_split | |
609e7e80 AK |
1927 | [(set (match_operand:TD_TF 0 "register_operand" "") |
1928 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
f61a2c7d AK |
1929 | "TARGET_64BIT && reload_completed |
1930 | && !FP_REG_P (operands[0]) | |
1931 | && !s_operand (operands[1], VOIDmode)" | |
1932 | [(set (match_dup 0) (match_dup 1))] | |
1933 | { | |
609e7e80 | 1934 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
f61a2c7d AK |
1935 | s390_load_address (addr, XEXP (operands[1], 0)); |
1936 | operands[1] = replace_equiv_address (operands[1], addr); | |
1937 | }) | |
1938 | ||
7b6baae1 | 1939 | ; TFmode in BFPs splitters |
f61a2c7d AK |
1940 | |
1941 | (define_split | |
609e7e80 AK |
1942 | [(set (match_operand:TD_TF 0 "register_operand" "") |
1943 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 1944 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
1945 | && FP_REG_P (operands[0])" |
1946 | [(set (match_dup 2) (match_dup 4)) | |
1947 | (set (match_dup 3) (match_dup 5))] | |
1948 | { | |
609e7e80 AK |
1949 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
1950 | <MODE>mode, 0); | |
1951 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
1952 | <MODE>mode, 8); | |
1953 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
1954 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
1955 | }) |
1956 | ||
1957 | (define_split | |
609e7e80 AK |
1958 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
1959 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
1960 | "reload_completed && offsettable_memref_p (operands[0]) |
1961 | && FP_REG_P (operands[1])" | |
1962 | [(set (match_dup 2) (match_dup 4)) | |
1963 | (set (match_dup 3) (match_dup 5))] | |
1964 | { | |
609e7e80 AK |
1965 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
1966 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
1967 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
1968 | <MODE>mode, 0); | |
1969 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
1970 | <MODE>mode, 8); | |
f61a2c7d AK |
1971 | }) |
1972 | ||
9db1d521 | 1973 | ; |
609e7e80 | 1974 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
1975 | ; |
1976 | ||
609e7e80 AK |
1977 | (define_expand "mov<mode>" |
1978 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
1979 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 1980 | "" |
13c025c1 | 1981 | "") |
9db1d521 | 1982 | |
609e7e80 AK |
1983 | (define_insn "*mov<mode>_64dfp" |
1984 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
f2dc2f86 | 1985 | "=f,f,f,d,f,f,R,T,d, d,RT") |
609e7e80 | 1986 | (match_operand:DD_DF 1 "general_operand" |
f2dc2f86 | 1987 | " G,f,d,f,R,T,f,f,d,RT, d"))] |
85dae55a AK |
1988 | "TARGET_64BIT && TARGET_DFP" |
1989 | "@ | |
1990 | lzdr\t%0 | |
1991 | ldr\t%0,%1 | |
1992 | ldgr\t%0,%1 | |
1993 | lgdr\t%0,%1 | |
1994 | ld\t%0,%1 | |
1995 | ldy\t%0,%1 | |
1996 | std\t%1,%0 | |
1997 | stdy\t%1,%0 | |
1998 | lgr\t%0,%1 | |
1999 | lg\t%0,%1 | |
f2dc2f86 AK |
2000 | stg\t%1,%0" |
2001 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY") | |
85dae55a | 2002 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
f2dc2f86 | 2003 | fstoredf,fstoredf,lr,load,store") |
9381e3f1 WG |
2004 | (set_attr "z10prop" "*, |
2005 | *, | |
2006 | *, | |
2007 | *, | |
2008 | *, | |
2009 | *, | |
2010 | *, | |
2011 | *, | |
2012 | z10_fr_E1, | |
2013 | z10_fwd_A3, | |
f2dc2f86 | 2014 | z10_rec") |
9381e3f1 | 2015 | ]) |
85dae55a | 2016 | |
609e7e80 | 2017 | (define_insn "*mov<mode>_64" |
f2dc2f86 AK |
2018 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT") |
2019 | (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))] | |
4023fb28 | 2020 | "TARGET_64BIT" |
9db1d521 | 2021 | "@ |
d096725d | 2022 | lzdr\t%0 |
d40c829f UW |
2023 | ldr\t%0,%1 |
2024 | ld\t%0,%1 | |
2025 | ldy\t%0,%1 | |
2026 | std\t%1,%0 | |
2027 | stdy\t%1,%0 | |
2028 | lgr\t%0,%1 | |
2029 | lg\t%0,%1 | |
f2dc2f86 AK |
2030 | stg\t%1,%0" |
2031 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY") | |
9381e3f1 | 2032 | (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, |
f2dc2f86 | 2033 | fstore<mode>,fstore<mode>,lr,load,store") |
9381e3f1 WG |
2034 | (set_attr "z10prop" "*, |
2035 | *, | |
2036 | *, | |
2037 | *, | |
2038 | *, | |
2039 | *, | |
2040 | z10_fr_E1, | |
2041 | z10_fwd_A3, | |
f2dc2f86 | 2042 | z10_rec")]) |
609e7e80 AK |
2043 | |
2044 | (define_insn "*mov<mode>_31" | |
2045 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
f2dc2f86 | 2046 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2047 | (match_operand:DD_DF 1 "general_operand" |
f2dc2f86 | 2048 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
4023fb28 | 2049 | "!TARGET_64BIT" |
9db1d521 | 2050 | "@ |
d096725d | 2051 | lzdr\t%0 |
d40c829f UW |
2052 | ldr\t%0,%1 |
2053 | ld\t%0,%1 | |
2054 | ldy\t%0,%1 | |
2055 | std\t%1,%0 | |
2056 | stdy\t%1,%0 | |
fc0ea003 | 2057 | lm\t%0,%N0,%S1 |
c4d50129 | 2058 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2059 | stm\t%1,%N1,%S0 |
c4d50129 | 2060 | stmy\t%1,%N1,%S0 |
4023fb28 | 2061 | # |
19b63d8e | 2062 | #" |
f2dc2f86 | 2063 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
9381e3f1 | 2064 | (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, |
f2dc2f86 | 2065 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")]) |
4023fb28 UW |
2066 | |
2067 | (define_split | |
609e7e80 AK |
2068 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2069 | (match_operand:DD_DF 1 "general_operand" ""))] | |
4023fb28 | 2070 | "!TARGET_64BIT && reload_completed |
609e7e80 | 2071 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2072 | [(set (match_dup 2) (match_dup 4)) |
2073 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2074 | { |
609e7e80 AK |
2075 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2076 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2077 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2078 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2079 | }) |
2080 | ||
2081 | (define_split | |
609e7e80 AK |
2082 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2083 | (match_operand:DD_DF 1 "general_operand" ""))] | |
dc65c307 | 2084 | "!TARGET_64BIT && reload_completed |
609e7e80 | 2085 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2086 | [(set (match_dup 2) (match_dup 4)) |
2087 | (set (match_dup 3) (match_dup 5))] | |
2088 | { | |
609e7e80 AK |
2089 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2090 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2091 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2092 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2093 | }) |
9db1d521 | 2094 | |
4023fb28 | 2095 | (define_split |
609e7e80 AK |
2096 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2097 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
4023fb28 | 2098 | "!TARGET_64BIT && reload_completed |
8e509cf9 | 2099 | && !FP_REG_P (operands[0]) |
4023fb28 | 2100 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2101 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2102 | { |
609e7e80 | 2103 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2104 | s390_load_address (addr, XEXP (operands[1], 0)); |
2105 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2106 | }) |
2107 | ||
9db1d521 | 2108 | ; |
609e7e80 | 2109 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2110 | ; |
2111 | ||
609e7e80 AK |
2112 | (define_insn "mov<mode>" |
2113 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
f2dc2f86 | 2114 | "=f,f,f,f,R,T,d,d,d,R,T") |
609e7e80 | 2115 | (match_operand:SD_SF 1 "general_operand" |
f2dc2f86 | 2116 | " G,f,R,T,f,f,d,R,T,d,d"))] |
4023fb28 | 2117 | "" |
9db1d521 | 2118 | "@ |
d096725d | 2119 | lzer\t%0 |
d40c829f UW |
2120 | ler\t%0,%1 |
2121 | le\t%0,%1 | |
2122 | ley\t%0,%1 | |
2123 | ste\t%1,%0 | |
2124 | stey\t%1,%0 | |
2125 | lr\t%0,%1 | |
2126 | l\t%0,%1 | |
2127 | ly\t%0,%1 | |
2128 | st\t%1,%0 | |
f2dc2f86 AK |
2129 | sty\t%1,%0" |
2130 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY") | |
9381e3f1 | 2131 | (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, |
f2dc2f86 | 2132 | fstore<mode>,fstore<mode>,lr,load,load,store,store") |
9381e3f1 WG |
2133 | (set_attr "z10prop" "*, |
2134 | *, | |
2135 | *, | |
2136 | *, | |
2137 | *, | |
2138 | *, | |
2139 | z10_fr_E1, | |
2140 | z10_fwd_A3, | |
2141 | z10_fwd_A3, | |
729e750f | 2142 | z10_rec, |
f2dc2f86 | 2143 | z10_rec")]) |
4023fb28 | 2144 | |
9dc62c00 AK |
2145 | ; |
2146 | ; movcc instruction pattern | |
2147 | ; | |
2148 | ||
2149 | (define_insn "movcc" | |
2150 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
2151 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
2152 | "" | |
2153 | "@ | |
2154 | lr\t%0,%1 | |
2155 | tmh\t%1,12288 | |
2156 | ipm\t%0 | |
2157 | st\t%0,%1 | |
2158 | sty\t%0,%1 | |
2159 | l\t%1,%0 | |
2160 | ly\t%1,%0" | |
8dd3b235 | 2161 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
9381e3f1 | 2162 | (set_attr "type" "lr,*,*,store,store,load,load") |
729e750f | 2163 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")]) |
9dc62c00 | 2164 | |
19b63d8e UW |
2165 | ; |
2166 | ; Block move (MVC) patterns. | |
2167 | ; | |
2168 | ||
2169 | (define_insn "*mvc" | |
2170 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2171 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2172 | (use (match_operand 2 "const_int_operand" "n"))] | |
2173 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2174 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2175 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2176 | |
19b63d8e UW |
2177 | (define_peephole2 |
2178 | [(parallel | |
2179 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2180 | (match_operand:BLK 1 "memory_operand" "")) | |
2181 | (use (match_operand 2 "const_int_operand" ""))]) | |
2182 | (parallel | |
2183 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2184 | (match_operand:BLK 4 "memory_operand" "")) | |
2185 | (use (match_operand 5 "const_int_operand" ""))])] | |
2186 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2187 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2188 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2189 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2190 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2191 | [(parallel | |
2192 | [(set (match_dup 6) (match_dup 7)) | |
2193 | (use (match_dup 8))])] | |
2194 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2195 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2196 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2197 | ||
2198 | ||
9db1d521 HP |
2199 | ; |
2200 | ; load_multiple pattern(s). | |
2201 | ; | |
22ea6b4f UW |
2202 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2203 | ; we currently support load_multiple/store_multiple only after reload. | |
2204 | ; | |
9db1d521 HP |
2205 | |
2206 | (define_expand "load_multiple" | |
2207 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2208 | (match_operand 1 "" "")) | |
2209 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2210 | "reload_completed" |
9db1d521 | 2211 | { |
c19ec8f9 | 2212 | enum machine_mode mode; |
9db1d521 HP |
2213 | int regno; |
2214 | int count; | |
2215 | rtx from; | |
4023fb28 | 2216 | int i, off; |
9db1d521 HP |
2217 | |
2218 | /* Support only loading a constant number of fixed-point registers from | |
2219 | memory and only bother with this if more than two */ | |
2220 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2221 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2222 | || INTVAL (operands[2]) > 16 |
2223 | || GET_CODE (operands[1]) != MEM | |
2224 | || GET_CODE (operands[0]) != REG | |
2225 | || REGNO (operands[0]) >= 16) | |
2226 | FAIL; | |
2227 | ||
2228 | count = INTVAL (operands[2]); | |
2229 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
2230 | mode = GET_MODE (operands[0]); |
2231 | if (mode != SImode && mode != word_mode) | |
2232 | FAIL; | |
9db1d521 HP |
2233 | |
2234 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2235 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2236 | { |
2237 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2238 | { | |
2239 | from = XEXP (operands[1], 0); | |
2240 | off = 0; | |
2241 | } | |
2242 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2243 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2244 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2245 | { | |
2246 | from = XEXP (XEXP (operands[1], 0), 0); | |
2247 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2248 | } | |
2249 | else | |
2250 | FAIL; | |
4023fb28 UW |
2251 | } |
2252 | else | |
2253 | { | |
2254 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2255 | off = 0; | |
2256 | } | |
9db1d521 HP |
2257 | |
2258 | for (i = 0; i < count; i++) | |
2259 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
2260 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
2261 | change_address (operands[1], mode, | |
2262 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2263 | }) |
9db1d521 HP |
2264 | |
2265 | (define_insn "*load_multiple_di" | |
2266 | [(match_parallel 0 "load_multiple_operation" | |
2267 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2268 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 2269 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
2270 | { |
2271 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2272 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2273 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2274 | } |
d3632d41 | 2275 | [(set_attr "op_type" "RSY") |
4023fb28 | 2276 | (set_attr "type" "lm")]) |
9db1d521 HP |
2277 | |
2278 | (define_insn "*load_multiple_si" | |
2279 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2280 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2281 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2282 | "reload_completed" |
9db1d521 HP |
2283 | { |
2284 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2285 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2286 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2287 | } |
d3632d41 | 2288 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2289 | (set_attr "type" "lm")]) |
9db1d521 HP |
2290 | |
2291 | ; | |
c7453384 | 2292 | ; store multiple pattern(s). |
9db1d521 HP |
2293 | ; |
2294 | ||
2295 | (define_expand "store_multiple" | |
2296 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2297 | (match_operand 1 "" "")) | |
2298 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2299 | "reload_completed" |
9db1d521 | 2300 | { |
c19ec8f9 | 2301 | enum machine_mode mode; |
9db1d521 HP |
2302 | int regno; |
2303 | int count; | |
2304 | rtx to; | |
4023fb28 | 2305 | int i, off; |
9db1d521 HP |
2306 | |
2307 | /* Support only storing a constant number of fixed-point registers to | |
2308 | memory and only bother with this if more than two. */ | |
2309 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2310 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2311 | || INTVAL (operands[2]) > 16 |
2312 | || GET_CODE (operands[0]) != MEM | |
2313 | || GET_CODE (operands[1]) != REG | |
2314 | || REGNO (operands[1]) >= 16) | |
2315 | FAIL; | |
2316 | ||
2317 | count = INTVAL (operands[2]); | |
2318 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
2319 | mode = GET_MODE (operands[1]); |
2320 | if (mode != SImode && mode != word_mode) | |
2321 | FAIL; | |
9db1d521 HP |
2322 | |
2323 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2324 | |
b3a13419 | 2325 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2326 | { |
2327 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2328 | { | |
2329 | to = XEXP (operands[0], 0); | |
2330 | off = 0; | |
2331 | } | |
2332 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2333 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2334 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2335 | { | |
2336 | to = XEXP (XEXP (operands[0], 0), 0); | |
2337 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2338 | } | |
2339 | else | |
2340 | FAIL; | |
4023fb28 | 2341 | } |
c7453384 | 2342 | else |
4023fb28 UW |
2343 | { |
2344 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2345 | off = 0; | |
2346 | } | |
9db1d521 HP |
2347 | |
2348 | for (i = 0; i < count; i++) | |
2349 | XVECEXP (operands[3], 0, i) | |
2350 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
2351 | change_address (operands[0], mode, |
2352 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
2353 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 2354 | }) |
9db1d521 HP |
2355 | |
2356 | (define_insn "*store_multiple_di" | |
2357 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2358 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2359 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 2360 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
2361 | { |
2362 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2363 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2364 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2365 | } |
d3632d41 | 2366 | [(set_attr "op_type" "RSY") |
4023fb28 | 2367 | (set_attr "type" "stm")]) |
9db1d521 HP |
2368 | |
2369 | ||
2370 | (define_insn "*store_multiple_si" | |
2371 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2372 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2373 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2374 | "reload_completed" |
9db1d521 HP |
2375 | { |
2376 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2377 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2378 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2379 | } |
d3632d41 | 2380 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2381 | (set_attr "type" "stm")]) |
9db1d521 HP |
2382 | |
2383 | ;; | |
2384 | ;; String instructions. | |
2385 | ;; | |
2386 | ||
963fc8d0 AK |
2387 | (define_insn "*execute_rl" |
2388 | [(match_parallel 0 "" | |
2389 | [(unspec [(match_operand 1 "register_operand" "a") | |
2390 | (match_operand 2 "" "") | |
2391 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2392 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2393 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2394 | "exrl\t%1,%3" | |
2395 | [(set_attr "op_type" "RIL") | |
2396 | (set_attr "type" "cs")]) | |
2397 | ||
9bb86f41 UW |
2398 | (define_insn "*execute" |
2399 | [(match_parallel 0 "" | |
2400 | [(unspec [(match_operand 1 "register_operand" "a") | |
2401 | (match_operand:BLK 2 "memory_operand" "R") | |
2402 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2403 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2404 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2405 | "ex\t%1,%2" | |
29a74354 UW |
2406 | [(set_attr "op_type" "RX") |
2407 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2408 | |
2409 | ||
91d39d71 UW |
2410 | ; |
2411 | ; strlenM instruction pattern(s). | |
2412 | ; | |
2413 | ||
9db2f16d | 2414 | (define_expand "strlen<mode>" |
ccbdc0d4 | 2415 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2416 | (parallel |
91d39d71 | 2417 | [(set (match_dup 4) |
9db2f16d | 2418 | (unspec:P [(const_int 0) |
91d39d71 | 2419 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2420 | (reg:SI 0) |
91d39d71 | 2421 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2422 | (clobber (scratch:P)) |
ae156f85 | 2423 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2424 | (parallel |
9db2f16d AS |
2425 | [(set (match_operand:P 0 "register_operand" "") |
2426 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2427 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2428 | "" |
91d39d71 | 2429 | { |
9db2f16d AS |
2430 | operands[4] = gen_reg_rtx (Pmode); |
2431 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2432 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2433 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2434 | }) | |
2435 | ||
9db2f16d AS |
2436 | (define_insn "*strlen<mode>" |
2437 | [(set (match_operand:P 0 "register_operand" "=a") | |
2438 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2439 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2440 | (reg:SI 0) |
91d39d71 | 2441 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2442 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2443 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2444 | "" |
91d39d71 | 2445 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2446 | [(set_attr "length" "8") |
2447 | (set_attr "type" "vs")]) | |
91d39d71 | 2448 | |
ccbdc0d4 AS |
2449 | ; |
2450 | ; cmpstrM instruction pattern(s). | |
2451 | ; | |
2452 | ||
2453 | (define_expand "cmpstrsi" | |
2454 | [(set (reg:SI 0) (const_int 0)) | |
2455 | (parallel | |
2456 | [(clobber (match_operand 3 "" "")) | |
2457 | (clobber (match_dup 4)) | |
2458 | (set (reg:CCU CC_REGNUM) | |
2459 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2460 | (match_operand:BLK 2 "memory_operand" ""))) | |
2461 | (use (reg:SI 0))]) | |
2462 | (parallel | |
2463 | [(set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 2464 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT)) |
ccbdc0d4 AS |
2465 | (clobber (reg:CC CC_REGNUM))])] |
2466 | "" | |
2467 | { | |
2468 | /* As the result of CMPINT is inverted compared to what we need, | |
2469 | we have to swap the operands. */ | |
2470 | rtx op1 = operands[2]; | |
2471 | rtx op2 = operands[1]; | |
2472 | rtx addr1 = gen_reg_rtx (Pmode); | |
2473 | rtx addr2 = gen_reg_rtx (Pmode); | |
2474 | ||
2475 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2476 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2477 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2478 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2479 | operands[3] = addr1; | |
2480 | operands[4] = addr2; | |
2481 | }) | |
2482 | ||
2483 | (define_insn "*cmpstr<mode>" | |
2484 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2485 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2486 | (set (reg:CCU CC_REGNUM) | |
2487 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2488 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2489 | (use (reg:SI 0))] | |
2490 | "" | |
2491 | "clst\t%0,%1\;jo\t.-4" | |
2492 | [(set_attr "length" "8") | |
2493 | (set_attr "type" "vs")]) | |
9381e3f1 | 2494 | |
742090fc AS |
2495 | ; |
2496 | ; movstr instruction pattern. | |
2497 | ; | |
2498 | ||
2499 | (define_expand "movstr" | |
2500 | [(set (reg:SI 0) (const_int 0)) | |
9381e3f1 | 2501 | (parallel |
742090fc AS |
2502 | [(clobber (match_dup 3)) |
2503 | (set (match_operand:BLK 1 "memory_operand" "") | |
2504 | (match_operand:BLK 2 "memory_operand" "")) | |
2505 | (set (match_operand 0 "register_operand" "") | |
9381e3f1 | 2506 | (unspec [(match_dup 1) |
742090fc AS |
2507 | (match_dup 2) |
2508 | (reg:SI 0)] UNSPEC_MVST)) | |
2509 | (clobber (reg:CC CC_REGNUM))])] | |
2510 | "" | |
2511 | { | |
2512 | rtx addr1 = gen_reg_rtx (Pmode); | |
2513 | rtx addr2 = gen_reg_rtx (Pmode); | |
2514 | ||
2515 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2516 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2517 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2518 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2519 | operands[3] = addr2; | |
2520 | }) | |
2521 | ||
2522 | (define_insn "*movstr" | |
2523 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2524 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2525 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2526 | (set (match_operand:P 0 "register_operand" "=d") | |
9381e3f1 | 2527 | (unspec [(mem:BLK (match_dup 1)) |
742090fc AS |
2528 | (mem:BLK (match_dup 3)) |
2529 | (reg:SI 0)] UNSPEC_MVST)) | |
2530 | (clobber (reg:CC CC_REGNUM))] | |
2531 | "" | |
2532 | "mvst\t%1,%2\;jo\t.-4" | |
2533 | [(set_attr "length" "8") | |
2534 | (set_attr "type" "vs")]) | |
9381e3f1 | 2535 | |
742090fc | 2536 | |
9db1d521 | 2537 | ; |
70128ad9 | 2538 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2539 | ; |
2540 | ||
9db2f16d | 2541 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2542 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2543 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2544 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2545 | (match_operand 3 "" "")] |
2546 | "" | |
70128ad9 | 2547 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2548 | |
ecbe845e UW |
2549 | ; Move a block that is up to 256 bytes in length. |
2550 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2551 | |
70128ad9 | 2552 | (define_expand "movmem_short" |
b9404c99 UW |
2553 | [(parallel |
2554 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2555 | (match_operand:BLK 1 "memory_operand" "")) | |
2556 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2557 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2558 | (clobber (match_dup 3))])] |
2559 | "" | |
2560 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2561 | |
70128ad9 | 2562 | (define_insn "*movmem_short" |
963fc8d0 AK |
2563 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
2564 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2565 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2566 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
2567 | (clobber (match_scratch 4 "=X,X,X,&a"))] | |
b9404c99 | 2568 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2569 | && GET_MODE (operands[4]) == Pmode" |
2570 | "#" | |
963fc8d0 AK |
2571 | [(set_attr "type" "cs") |
2572 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
ecbe845e | 2573 | |
9bb86f41 UW |
2574 | (define_split |
2575 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2576 | (match_operand:BLK 1 "memory_operand" "")) | |
2577 | (use (match_operand 2 "const_int_operand" "")) | |
2578 | (use (match_operand 3 "immediate_operand" "")) | |
2579 | (clobber (scratch))] | |
2580 | "reload_completed" | |
2581 | [(parallel | |
2582 | [(set (match_dup 0) (match_dup 1)) | |
2583 | (use (match_dup 2))])] | |
2584 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2585 | |
9bb86f41 UW |
2586 | (define_split |
2587 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2588 | (match_operand:BLK 1 "memory_operand" "")) | |
2589 | (use (match_operand 2 "register_operand" "")) | |
2590 | (use (match_operand 3 "memory_operand" "")) | |
2591 | (clobber (scratch))] | |
2592 | "reload_completed" | |
2593 | [(parallel | |
2594 | [(unspec [(match_dup 2) (match_dup 3) | |
2595 | (const_int 0)] UNSPEC_EXECUTE) | |
2596 | (set (match_dup 0) (match_dup 1)) | |
2597 | (use (const_int 1))])] | |
2598 | "") | |
2599 | ||
963fc8d0 AK |
2600 | (define_split |
2601 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2602 | (match_operand:BLK 1 "memory_operand" "")) | |
2603 | (use (match_operand 2 "register_operand" "")) | |
2604 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2605 | (clobber (scratch))] | |
2606 | "TARGET_Z10 && reload_completed" | |
2607 | [(parallel | |
2608 | [(unspec [(match_dup 2) (const_int 0) | |
2609 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2610 | (set (match_dup 0) (match_dup 1)) | |
2611 | (use (const_int 1))])] | |
2612 | "operands[3] = gen_label_rtx ();") | |
2613 | ||
9bb86f41 UW |
2614 | (define_split |
2615 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2616 | (match_operand:BLK 1 "memory_operand" "")) | |
2617 | (use (match_operand 2 "register_operand" "")) | |
2618 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2619 | (clobber (match_operand 3 "register_operand" ""))] | |
2620 | "reload_completed && TARGET_CPU_ZARCH" | |
2621 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2622 | (parallel | |
9381e3f1 | 2623 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
2624 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
2625 | (set (match_dup 0) (match_dup 1)) | |
2626 | (use (const_int 1))])] | |
2627 | "operands[4] = gen_label_rtx ();") | |
2628 | ||
a41c6c53 | 2629 | ; Move a block of arbitrary length. |
9db1d521 | 2630 | |
70128ad9 | 2631 | (define_expand "movmem_long" |
b9404c99 UW |
2632 | [(parallel |
2633 | [(clobber (match_dup 2)) | |
2634 | (clobber (match_dup 3)) | |
2635 | (set (match_operand:BLK 0 "memory_operand" "") | |
2636 | (match_operand:BLK 1 "memory_operand" "")) | |
2637 | (use (match_operand 2 "general_operand" "")) | |
2638 | (use (match_dup 3)) | |
ae156f85 | 2639 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2640 | "" |
2641 | { | |
2642 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2643 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2644 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2645 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2646 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2647 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2648 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2649 | ||
c41c1387 | 2650 | emit_clobber (reg0); |
b9404c99 UW |
2651 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2652 | emit_move_insn (len0, operands[2]); | |
2653 | ||
c41c1387 | 2654 | emit_clobber (reg1); |
b9404c99 UW |
2655 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2656 | emit_move_insn (len1, operands[2]); | |
2657 | ||
2658 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2659 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2660 | operands[2] = reg0; | |
2661 | operands[3] = reg1; | |
2662 | }) | |
2663 | ||
a1aed706 AS |
2664 | (define_insn "*movmem_long" |
2665 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2666 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2667 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2668 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2669 | (use (match_dup 2)) |
2670 | (use (match_dup 3)) | |
ae156f85 | 2671 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2672 | "" |
d40c829f | 2673 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2674 | [(set_attr "length" "8") |
2675 | (set_attr "type" "vs")]) | |
9db1d521 | 2676 | |
638e37c2 WG |
2677 | |
2678 | ; | |
2679 | ; Test data class. | |
2680 | ; | |
2681 | ||
0f67fa83 WG |
2682 | (define_expand "signbit<mode>2" |
2683 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2684 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2685 | (match_dup 2)] | |
0f67fa83 WG |
2686 | UNSPEC_TDC_INSN)) |
2687 | (set (match_operand:SI 0 "register_operand" "=d") | |
2688 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
2689 | "TARGET_HARD_FLOAT" | |
2690 | { | |
2691 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
2692 | }) | |
2693 | ||
638e37c2 WG |
2694 | (define_expand "isinf<mode>2" |
2695 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2696 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2697 | (match_dup 2)] | |
638e37c2 WG |
2698 | UNSPEC_TDC_INSN)) |
2699 | (set (match_operand:SI 0 "register_operand" "=d") | |
2700 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
142cd70f | 2701 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
2702 | { |
2703 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
2704 | }) | |
2705 | ||
2706 | ; This insn is used to generate all variants of the Test Data Class | |
2707 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
2708 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 2709 | ; specifying the required test(s). |
638e37c2 WG |
2710 | ; |
2711 | (define_insn "*TDC_insn_<mode>" | |
2712 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 2713 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 2714 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 2715 | "TARGET_HARD_FLOAT" |
0387c142 | 2716 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 2717 | [(set_attr "op_type" "RXE") |
9381e3f1 | 2718 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 WG |
2719 | |
2720 | (define_insn_and_split "*ccz_to_int" | |
2721 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2722 | (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")] | |
2723 | UNSPEC_CCZ_TO_INT))] | |
2724 | "" | |
2725 | "#" | |
2726 | "reload_completed" | |
2727 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
2728 | ||
2729 | ||
9db1d521 | 2730 | ; |
57e84f18 | 2731 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2732 | ; |
2733 | ||
57e84f18 | 2734 | (define_expand "setmem<mode>" |
a41c6c53 | 2735 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2736 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2737 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2738 | (match_operand 3 "" "")] |
a41c6c53 | 2739 | "" |
6d057022 | 2740 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2741 | |
a41c6c53 | 2742 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2743 | ; The block length is taken as (operands[1] % 256) + 1. |
2744 | ||
70128ad9 | 2745 | (define_expand "clrmem_short" |
b9404c99 UW |
2746 | [(parallel |
2747 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2748 | (const_int 0)) | |
2749 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2750 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2751 | (clobber (match_dup 2)) |
ae156f85 | 2752 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2753 | "" |
2754 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2755 | |
70128ad9 | 2756 | (define_insn "*clrmem_short" |
963fc8d0 | 2757 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 2758 | (const_int 0)) |
963fc8d0 AK |
2759 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
2760 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
2761 | (clobber (match_scratch 3 "=X,X,X,&a")) | |
ae156f85 | 2762 | (clobber (reg:CC CC_REGNUM))] |
b9404c99 | 2763 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
2764 | && GET_MODE (operands[3]) == Pmode" |
2765 | "#" | |
963fc8d0 AK |
2766 | [(set_attr "type" "cs") |
2767 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9bb86f41 UW |
2768 | |
2769 | (define_split | |
2770 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2771 | (const_int 0)) | |
2772 | (use (match_operand 1 "const_int_operand" "")) | |
2773 | (use (match_operand 2 "immediate_operand" "")) | |
2774 | (clobber (scratch)) | |
ae156f85 | 2775 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2776 | "reload_completed" |
2777 | [(parallel | |
2778 | [(set (match_dup 0) (const_int 0)) | |
2779 | (use (match_dup 1)) | |
ae156f85 | 2780 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2781 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2782 | |
9bb86f41 UW |
2783 | (define_split |
2784 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2785 | (const_int 0)) | |
2786 | (use (match_operand 1 "register_operand" "")) | |
2787 | (use (match_operand 2 "memory_operand" "")) | |
2788 | (clobber (scratch)) | |
ae156f85 | 2789 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2790 | "reload_completed" |
2791 | [(parallel | |
2792 | [(unspec [(match_dup 1) (match_dup 2) | |
2793 | (const_int 0)] UNSPEC_EXECUTE) | |
2794 | (set (match_dup 0) (const_int 0)) | |
2795 | (use (const_int 1)) | |
ae156f85 | 2796 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2797 | "") |
9db1d521 | 2798 | |
963fc8d0 AK |
2799 | (define_split |
2800 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2801 | (const_int 0)) | |
2802 | (use (match_operand 1 "register_operand" "")) | |
2803 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2804 | (clobber (scratch)) | |
2805 | (clobber (reg:CC CC_REGNUM))] | |
2806 | "TARGET_Z10 && reload_completed" | |
2807 | [(parallel | |
2808 | [(unspec [(match_dup 1) (const_int 0) | |
2809 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2810 | (set (match_dup 0) (const_int 0)) | |
2811 | (use (const_int 1)) | |
2812 | (clobber (reg:CC CC_REGNUM))])] | |
2813 | "operands[3] = gen_label_rtx ();") | |
2814 | ||
9bb86f41 UW |
2815 | (define_split |
2816 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2817 | (const_int 0)) | |
2818 | (use (match_operand 1 "register_operand" "")) | |
2819 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2820 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2821 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2822 | "reload_completed && TARGET_CPU_ZARCH" |
2823 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2824 | (parallel | |
9381e3f1 | 2825 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
2826 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
2827 | (set (match_dup 0) (const_int 0)) | |
2828 | (use (const_int 1)) | |
ae156f85 | 2829 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2830 | "operands[3] = gen_label_rtx ();") |
2831 | ||
9381e3f1 | 2832 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2833 | |
6d057022 | 2834 | (define_expand "setmem_long" |
b9404c99 UW |
2835 | [(parallel |
2836 | [(clobber (match_dup 1)) | |
2837 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 2838 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 2839 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2840 | (use (match_dup 3)) |
ae156f85 | 2841 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2842 | "" |
a41c6c53 | 2843 | { |
b9404c99 UW |
2844 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2845 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2846 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2847 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2848 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2849 | |
c41c1387 | 2850 | emit_clobber (reg0); |
b9404c99 UW |
2851 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2852 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2853 | |
b9404c99 | 2854 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2855 | |
b9404c99 UW |
2856 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2857 | operands[1] = reg0; | |
6d057022 | 2858 | operands[3] = reg1; |
b9404c99 | 2859 | }) |
a41c6c53 | 2860 | |
6d057022 | 2861 | (define_insn "*setmem_long" |
a1aed706 | 2862 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 2863 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 2864 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 2865 | (use (match_dup 3)) |
a1aed706 | 2866 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2867 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2868 | "" |
6d057022 | 2869 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
2870 | [(set_attr "length" "8") |
2871 | (set_attr "type" "vs")]) | |
9db1d521 | 2872 | |
4989e88a AK |
2873 | (define_insn "*setmem_long_and" |
2874 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2875 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
2876 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
2877 | (match_operand 4 "const_int_operand" "n"))) | |
2878 | (use (match_dup 3)) | |
2879 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
2880 | (clobber (reg:CC CC_REGNUM))] | |
2881 | "(INTVAL (operands[4]) & 255) == 255" | |
2882 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
2883 | [(set_attr "length" "8") | |
2884 | (set_attr "type" "vs")]) | |
9db1d521 | 2885 | ; |
358b8f01 | 2886 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2887 | ; |
2888 | ||
358b8f01 | 2889 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2890 | [(set (match_operand:SI 0 "register_operand" "") |
2891 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2892 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2893 | (use (match_operand:SI 3 "general_operand" "")) | |
2894 | (use (match_operand:SI 4 "" ""))] | |
2895 | "" | |
c7453384 | 2896 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2897 | operands[2], operands[3]); DONE;") |
9db1d521 | 2898 | |
a41c6c53 UW |
2899 | ; Compare a block that is up to 256 bytes in length. |
2900 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2901 | |
b9404c99 UW |
2902 | (define_expand "cmpmem_short" |
2903 | [(parallel | |
ae156f85 | 2904 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 2905 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2906 | (match_operand:BLK 1 "memory_operand" ""))) |
2907 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2908 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2909 | (clobber (match_dup 3))])] |
2910 | "" | |
2911 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2912 | |
b9404c99 | 2913 | (define_insn "*cmpmem_short" |
ae156f85 | 2914 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
2915 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
2916 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
2917 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2918 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
2919 | (clobber (match_scratch 4 "=X,X,X,&a"))] | |
b9404c99 | 2920 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2921 | && GET_MODE (operands[4]) == Pmode" |
2922 | "#" | |
963fc8d0 AK |
2923 | [(set_attr "type" "cs") |
2924 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9db1d521 | 2925 | |
9bb86f41 | 2926 | (define_split |
ae156f85 | 2927 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2928 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2929 | (match_operand:BLK 1 "memory_operand" ""))) | |
2930 | (use (match_operand 2 "const_int_operand" "")) | |
2931 | (use (match_operand 3 "immediate_operand" "")) | |
2932 | (clobber (scratch))] | |
2933 | "reload_completed" | |
2934 | [(parallel | |
ae156f85 | 2935 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2936 | (use (match_dup 2))])] |
2937 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2938 | |
9bb86f41 | 2939 | (define_split |
ae156f85 | 2940 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2941 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2942 | (match_operand:BLK 1 "memory_operand" ""))) | |
2943 | (use (match_operand 2 "register_operand" "")) | |
2944 | (use (match_operand 3 "memory_operand" "")) | |
2945 | (clobber (scratch))] | |
2946 | "reload_completed" | |
2947 | [(parallel | |
2948 | [(unspec [(match_dup 2) (match_dup 3) | |
2949 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 2950 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2951 | (use (const_int 1))])] |
2952 | "") | |
2953 | ||
963fc8d0 AK |
2954 | (define_split |
2955 | [(set (reg:CCU CC_REGNUM) | |
2956 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2957 | (match_operand:BLK 1 "memory_operand" ""))) | |
2958 | (use (match_operand 2 "register_operand" "")) | |
2959 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2960 | (clobber (scratch))] | |
2961 | "TARGET_Z10 && reload_completed" | |
2962 | [(parallel | |
2963 | [(unspec [(match_dup 2) (const_int 0) | |
2964 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2965 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
2966 | (use (const_int 1))])] | |
2967 | "operands[4] = gen_label_rtx ();") | |
2968 | ||
9bb86f41 | 2969 | (define_split |
ae156f85 | 2970 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2971 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2972 | (match_operand:BLK 1 "memory_operand" ""))) | |
2973 | (use (match_operand 2 "register_operand" "")) | |
2974 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2975 | (clobber (match_operand 3 "register_operand" ""))] | |
2976 | "reload_completed && TARGET_CPU_ZARCH" | |
2977 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2978 | (parallel | |
9381e3f1 | 2979 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 2980 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 2981 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2982 | (use (const_int 1))])] |
2983 | "operands[4] = gen_label_rtx ();") | |
2984 | ||
a41c6c53 | 2985 | ; Compare a block of arbitrary length. |
9db1d521 | 2986 | |
b9404c99 UW |
2987 | (define_expand "cmpmem_long" |
2988 | [(parallel | |
2989 | [(clobber (match_dup 2)) | |
2990 | (clobber (match_dup 3)) | |
ae156f85 | 2991 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 2992 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2993 | (match_operand:BLK 1 "memory_operand" ""))) |
2994 | (use (match_operand 2 "general_operand" "")) | |
2995 | (use (match_dup 3))])] | |
2996 | "" | |
2997 | { | |
2998 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2999 | rtx reg0 = gen_reg_rtx (dword_mode); | |
3000 | rtx reg1 = gen_reg_rtx (dword_mode); | |
3001 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
3002 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
3003 | rtx len0 = gen_lowpart (Pmode, reg0); | |
3004 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3005 | ||
c41c1387 | 3006 | emit_clobber (reg0); |
b9404c99 UW |
3007 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3008 | emit_move_insn (len0, operands[2]); | |
3009 | ||
c41c1387 | 3010 | emit_clobber (reg1); |
b9404c99 UW |
3011 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3012 | emit_move_insn (len1, operands[2]); | |
3013 | ||
3014 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3015 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3016 | operands[2] = reg0; | |
3017 | operands[3] = reg1; | |
3018 | }) | |
3019 | ||
a1aed706 AS |
3020 | (define_insn "*cmpmem_long" |
3021 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3022 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3023 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3024 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3025 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3026 | (use (match_dup 2)) |
3027 | (use (match_dup 3))] | |
a1aed706 | 3028 | "" |
287ff198 | 3029 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3030 | [(set_attr "length" "8") |
3031 | (set_attr "type" "vs")]) | |
9db1d521 | 3032 | |
02887425 UW |
3033 | ; Convert CCUmode condition code to integer. |
3034 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3035 | |
02887425 | 3036 | (define_insn_and_split "cmpint" |
9db1d521 | 3037 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3038 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3039 | UNSPEC_CCU_TO_INT)) |
ae156f85 | 3040 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3041 | "" |
02887425 UW |
3042 | "#" |
3043 | "reload_completed" | |
3044 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3045 | (parallel | |
3046 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3047 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3048 | |
3049 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3050 | [(set (reg CC_REGNUM) |
02887425 | 3051 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3052 | UNSPEC_CCU_TO_INT) |
02887425 UW |
3053 | (const_int 0))) |
3054 | (set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 3055 | (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))] |
02887425 UW |
3056 | "s390_match_ccmode (insn, CCSmode)" |
3057 | "#" | |
3058 | "&& reload_completed" | |
3059 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3060 | (parallel | |
3061 | [(set (match_dup 2) (match_dup 3)) | |
3062 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3063 | { |
02887425 UW |
3064 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3065 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3066 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3067 | }) | |
9db1d521 | 3068 | |
02887425 | 3069 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3070 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3071 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3072 | UNSPEC_CCU_TO_INT))) |
ae156f85 | 3073 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3074 | "TARGET_64BIT" |
02887425 UW |
3075 | "#" |
3076 | "&& reload_completed" | |
3077 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3078 | (parallel | |
3079 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3080 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3081 | |
3082 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3083 | [(set (reg CC_REGNUM) |
9381e3f1 | 3084 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3085 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3086 | UNSPEC_CCU_TO_INT) 0) |
02887425 UW |
3087 | (const_int 32)) (const_int 32)) |
3088 | (const_int 0))) | |
3089 | (set (match_operand:DI 0 "register_operand" "=d") | |
638e37c2 | 3090 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] |
02887425 UW |
3091 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" |
3092 | "#" | |
3093 | "&& reload_completed" | |
3094 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3095 | (parallel | |
3096 | [(set (match_dup 2) (match_dup 3)) | |
3097 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3098 | { |
02887425 UW |
3099 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3100 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3101 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3102 | }) | |
9db1d521 | 3103 | |
4023fb28 | 3104 | |
9db1d521 HP |
3105 | ;; |
3106 | ;;- Conversion instructions. | |
3107 | ;; | |
3108 | ||
6fa05db6 | 3109 | (define_insn "*sethighpartsi" |
d3632d41 | 3110 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3111 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3112 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3113 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3114 | "" |
d3632d41 | 3115 | "@ |
6fa05db6 AS |
3116 | icm\t%0,%2,%S1 |
3117 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3118 | [(set_attr "op_type" "RS,RSY") |
3119 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3120 | |
6fa05db6 | 3121 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3122 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3123 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3124 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3125 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3126 | "TARGET_64BIT" |
6fa05db6 | 3127 | "icmh\t%0,%2,%S1" |
729e750f WG |
3128 | [(set_attr "op_type" "RSY") |
3129 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3130 | |
6fa05db6 | 3131 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3132 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3133 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3134 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3135 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3136 | "!TARGET_64BIT" |
d3632d41 | 3137 | "@ |
6fa05db6 AS |
3138 | icm\t%0,%2,%S1 |
3139 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3140 | [(set_attr "op_type" "RS,RSY") |
3141 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3142 | ||
4023fb28 | 3143 | |
6fa05db6 AS |
3144 | (define_insn_and_split "*extzv<mode>" |
3145 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3146 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3147 | (match_operand 2 "const_int_operand" "n") | |
3148 | (const_int 0))) | |
ae156f85 | 3149 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3150 | "INTVAL (operands[2]) > 0 |
3151 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3152 | "#" |
3153 | "&& reload_completed" | |
4023fb28 | 3154 | [(parallel |
6fa05db6 | 3155 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3156 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3157 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3158 | { |
6fa05db6 AS |
3159 | int bitsize = INTVAL (operands[2]); |
3160 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3161 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3162 | ||
3163 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3164 | set_mem_size (operands[1], GEN_INT (size)); | |
3165 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
3166 | operands[3] = GEN_INT (mask); | |
b628bd8e | 3167 | }) |
4023fb28 | 3168 | |
6fa05db6 AS |
3169 | (define_insn_and_split "*extv<mode>" |
3170 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3171 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3172 | (match_operand 2 "const_int_operand" "n") | |
3173 | (const_int 0))) | |
ae156f85 | 3174 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3175 | "INTVAL (operands[2]) > 0 |
3176 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3177 | "#" |
3178 | "&& reload_completed" | |
4023fb28 | 3179 | [(parallel |
6fa05db6 | 3180 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3181 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3182 | (parallel |
3183 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3184 | (clobber (reg:CC CC_REGNUM))])] | |
3185 | { | |
3186 | int bitsize = INTVAL (operands[2]); | |
3187 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3188 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3189 | ||
3190 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3191 | set_mem_size (operands[1], GEN_INT (size)); | |
3192 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
3193 | operands[3] = GEN_INT (mask); | |
3194 | }) | |
3195 | ||
3196 | ; | |
3197 | ; insv instruction patterns | |
3198 | ; | |
3199 | ||
3200 | (define_expand "insv" | |
3201 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3202 | (match_operand 1 "const_int_operand" "") | |
3203 | (match_operand 2 "const_int_operand" "")) | |
3204 | (match_operand 3 "general_operand" ""))] | |
3205 | "" | |
4023fb28 | 3206 | { |
6fa05db6 AS |
3207 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3208 | DONE; | |
3209 | FAIL; | |
b628bd8e | 3210 | }) |
4023fb28 | 3211 | |
963fc8d0 AK |
3212 | (define_insn "*insv<mode>_z10" |
3213 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
3214 | (match_operand 1 "const_int_operand" "I") | |
3215 | (match_operand 2 "const_int_operand" "I")) | |
3216 | (match_operand:GPR 3 "nonimmediate_operand" "d")) | |
3217 | (clobber (reg:CC CC_REGNUM))] | |
3218 | "TARGET_Z10 | |
3219 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= | |
3220 | GET_MODE_BITSIZE (<MODE>mode)" | |
3221 | { | |
3222 | int start = INTVAL (operands[2]); | |
3223 | int size = INTVAL (operands[1]); | |
3224 | int offset = 64 - GET_MODE_BITSIZE (<MODE>mode); | |
3225 | ||
3226 | operands[2] = GEN_INT (offset + start); /* start bit position */ | |
3227 | operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ | |
3228 | operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - | |
3229 | start - size); /* left shift count */ | |
3230 | ||
3231 | return "risbg\t%0,%3,%b2,%b1,%b4"; | |
3232 | } | |
9381e3f1 WG |
3233 | [(set_attr "op_type" "RIE") |
3234 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3235 | |
3236 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3237 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3238 | (define_insn "*insv<mode>_z10_noshift" | |
3239 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3240 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3241 | (match_operand 2 "const_int_operand" "n")) | |
3242 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") | |
3243 | (match_operand 4 "const_int_operand" "n")))) | |
3244 | (clobber (reg:CC CC_REGNUM))] | |
3245 | "TARGET_Z10 | |
3246 | && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3247 | GET_MODE_BITSIZE (<MODE>mode), NULL, NULL) | |
3248 | && INTVAL (operands[2]) == ~(INTVAL (operands[4]))" | |
3249 | ||
3250 | { | |
3251 | int start; | |
3252 | int size; | |
3253 | ||
3254 | s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3255 | GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3256 | ||
3257 | operands[5] = GEN_INT (64 - start - size); /* start bit position */ | |
3258 | operands[6] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3259 | operands[7] = const0_rtx; /* left shift count */ | |
3260 | ||
3261 | return "risbg\t%0,%1,%b5,%b6,%b7"; | |
3262 | } | |
9381e3f1 WG |
3263 | [(set_attr "op_type" "RIE") |
3264 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3265 | |
3266 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3267 | (define_insn "*insv<mode>_or_z10_noshift" | |
3268 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3269 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3270 | (match_operand 2 "const_int_operand" "n")) | |
3271 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
3272 | (clobber (reg:CC CC_REGNUM))] | |
3273 | "TARGET_Z10 | |
3274 | && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3275 | GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)" | |
3276 | { | |
3277 | int start; | |
3278 | int size; | |
3279 | ||
3280 | s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3281 | GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3282 | ||
3283 | operands[4] = GEN_INT (64 - start - size); /* start bit position */ | |
3284 | operands[5] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3285 | operands[6] = const0_rtx; /* left shift count */ | |
3286 | ||
3287 | return "rosbg\t%0,%1,%b4,%b5,%b6"; | |
3288 | } | |
3289 | [(set_attr "op_type" "RIE")]) | |
3290 | ||
6fa05db6 AS |
3291 | (define_insn "*insv<mode>_mem_reg" |
3292 | [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") | |
3293 | (match_operand 1 "const_int_operand" "n,n") | |
3294 | (const_int 0)) | |
3295 | (match_operand:P 2 "register_operand" "d,d"))] | |
3296 | "INTVAL (operands[1]) > 0 | |
3297 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3298 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3299 | { | |
3300 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3301 | ||
3302 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 3303 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
3304 | : "stcmy\t%2,%1,%S0"; |
3305 | } | |
9381e3f1 WG |
3306 | [(set_attr "op_type" "RS,RSY") |
3307 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
3308 | |
3309 | (define_insn "*insvdi_mem_reghigh" | |
3310 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3311 | (match_operand 1 "const_int_operand" "n") | |
3312 | (const_int 0)) | |
3313 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3314 | (const_int 32)))] | |
3315 | "TARGET_64BIT | |
3316 | && INTVAL (operands[1]) > 0 | |
3317 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3318 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3319 | { | |
3320 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3321 | ||
3322 | operands[1] = GEN_INT ((1ul << size) - 1); | |
3323 | return "stcmh\t%2,%1,%S0"; | |
3324 | } | |
9381e3f1 WG |
3325 | [(set_attr "op_type" "RSY") |
3326 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 AS |
3327 | |
3328 | (define_insn "*insv<mode>_reg_imm" | |
3329 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
3330 | (const_int 16) | |
3331 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 3332 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 AS |
3333 | "TARGET_ZARCH |
3334 | && INTVAL (operands[1]) >= 0 | |
3335 | && INTVAL (operands[1]) < BITS_PER_WORD | |
3336 | && INTVAL (operands[1]) % 16 == 0" | |
3337 | { | |
3338 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3339 | { | |
3340 | case 64: return "iihh\t%0,%x2"; break; | |
3341 | case 48: return "iihl\t%0,%x2"; break; | |
3342 | case 32: return "iilh\t%0,%x2"; break; | |
3343 | case 16: return "iill\t%0,%x2"; break; | |
3344 | default: gcc_unreachable(); | |
3345 | } | |
3346 | } | |
9381e3f1 WG |
3347 | [(set_attr "op_type" "RI") |
3348 | (set_attr "z10prop" "z10_super_E1")]) | |
3349 | ||
9fec758d WG |
3350 | ; Update the left-most 32 bit of a DI. |
3351 | (define_insn "*insv_h_di_reg_extimm" | |
3352 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3353 | (const_int 32) | |
3354 | (const_int 0)) | |
3355 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3356 | "TARGET_EXTIMM" | |
3357 | "iihf\t%0,%o1" | |
3358 | [(set_attr "op_type" "RIL") | |
3359 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 3360 | |
9fec758d WG |
3361 | ; Update the right-most 32 bit of a DI, or the whole of a SI. |
3362 | (define_insn "*insv_l<mode>_reg_extimm" | |
6fa05db6 AS |
3363 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") |
3364 | (const_int 32) | |
3365 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 3366 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 | 3367 | "TARGET_EXTIMM |
9fec758d WG |
3368 | && BITS_PER_WORD - INTVAL (operands[1]) == 32" |
3369 | "iilf\t%0,%o2" | |
9381e3f1 | 3370 | [(set_attr "op_type" "RIL") |
9fec758d | 3371 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 3372 | |
9db1d521 HP |
3373 | ; |
3374 | ; extendsidi2 instruction pattern(s). | |
3375 | ; | |
3376 | ||
4023fb28 UW |
3377 | (define_expand "extendsidi2" |
3378 | [(set (match_operand:DI 0 "register_operand" "") | |
3379 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3380 | "" | |
4023fb28 UW |
3381 | { |
3382 | if (!TARGET_64BIT) | |
3383 | { | |
c41c1387 | 3384 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3385 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
3386 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
3387 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
3388 | DONE; |
3389 | } | |
ec24698e | 3390 | }) |
4023fb28 UW |
3391 | |
3392 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
3393 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3394 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9db1d521 HP |
3395 | "TARGET_64BIT" |
3396 | "@ | |
d40c829f | 3397 | lgfr\t%0,%1 |
963fc8d0 AK |
3398 | lgf\t%0,%1 |
3399 | lgfrl\t%0,%1" | |
3400 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3401 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3402 | (set_attr "cpu_facility" "*,*,z10") |
3403 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3404 | |
9db1d521 | 3405 | ; |
56477c21 | 3406 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3407 | ; |
3408 | ||
56477c21 AS |
3409 | (define_expand "extend<HQI:mode><DSI:mode>2" |
3410 | [(set (match_operand:DSI 0 "register_operand" "") | |
3411 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 3412 | "" |
4023fb28 | 3413 | { |
56477c21 | 3414 | if (<DSI:MODE>mode == DImode && !TARGET_64BIT) |
4023fb28 UW |
3415 | { |
3416 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 3417 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
3418 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
3419 | DONE; | |
3420 | } | |
ec24698e | 3421 | else if (!TARGET_EXTIMM) |
4023fb28 | 3422 | { |
56477c21 AS |
3423 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - |
3424 | GET_MODE_BITSIZE (<HQI:MODE>mode)); | |
3425 | ||
3426 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
3427 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
3428 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
3429 | DONE; |
3430 | } | |
ec24698e UW |
3431 | }) |
3432 | ||
56477c21 AS |
3433 | ; |
3434 | ; extendhidi2 instruction pattern(s). | |
3435 | ; | |
3436 | ||
ec24698e | 3437 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
3438 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3439 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
ec24698e UW |
3440 | "TARGET_64BIT && TARGET_EXTIMM" |
3441 | "@ | |
3442 | lghr\t%0,%1 | |
963fc8d0 AK |
3443 | lgh\t%0,%1 |
3444 | lghrl\t%0,%1" | |
3445 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3446 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3447 | (set_attr "cpu_facility" "extimm,extimm,z10") |
3448 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
3449 | |
3450 | (define_insn "*extendhidi2" | |
9db1d521 | 3451 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 3452 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9db1d521 | 3453 | "TARGET_64BIT" |
d40c829f | 3454 | "lgh\t%0,%1" |
9381e3f1 WG |
3455 | [(set_attr "op_type" "RXY") |
3456 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 3457 | |
9db1d521 | 3458 | ; |
56477c21 | 3459 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
3460 | ; |
3461 | ||
ec24698e | 3462 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
3463 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3464 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
3465 | "TARGET_EXTIMM" |
3466 | "@ | |
3467 | lhr\t%0,%1 | |
3468 | lh\t%0,%1 | |
963fc8d0 AK |
3469 | lhy\t%0,%1 |
3470 | lhrl\t%0,%1" | |
3471 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
3472 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
3473 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
3474 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3475 | |
4023fb28 | 3476 | (define_insn "*extendhisi2" |
d3632d41 UW |
3477 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3478 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 3479 | "!TARGET_EXTIMM" |
d3632d41 | 3480 | "@ |
d40c829f UW |
3481 | lh\t%0,%1 |
3482 | lhy\t%0,%1" | |
9381e3f1 WG |
3483 | [(set_attr "op_type" "RX,RXY") |
3484 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3485 | |
56477c21 AS |
3486 | ; |
3487 | ; extendqi(si|di)2 instruction pattern(s). | |
3488 | ; | |
3489 | ||
43a09b63 | 3490 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
3491 | (define_insn "*extendqi<mode>2_extimm" |
3492 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3493 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3494 | "TARGET_EXTIMM" |
3495 | "@ | |
56477c21 AS |
3496 | l<g>br\t%0,%1 |
3497 | l<g>b\t%0,%1" | |
9381e3f1 WG |
3498 | [(set_attr "op_type" "RRE,RXY") |
3499 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 3500 | |
43a09b63 | 3501 | ; lb, lgb |
56477c21 AS |
3502 | (define_insn "*extendqi<mode>2" |
3503 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3504 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
3505 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
3506 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
3507 | [(set_attr "op_type" "RXY") |
3508 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 3509 | |
56477c21 AS |
3510 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
3511 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3512 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 3513 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 3514 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
3515 | "#" |
3516 | "&& reload_completed" | |
4023fb28 | 3517 | [(parallel |
56477c21 | 3518 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 3519 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 3520 | (parallel |
56477c21 | 3521 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 3522 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
3523 | { |
3524 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3525 | set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); | |
56477c21 AS |
3526 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) |
3527 | - GET_MODE_BITSIZE (QImode)); | |
6fa05db6 | 3528 | }) |
9db1d521 | 3529 | |
9db1d521 HP |
3530 | ; |
3531 | ; zero_extendsidi2 instruction pattern(s). | |
3532 | ; | |
3533 | ||
4023fb28 UW |
3534 | (define_expand "zero_extendsidi2" |
3535 | [(set (match_operand:DI 0 "register_operand" "") | |
3536 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3537 | "" | |
4023fb28 UW |
3538 | { |
3539 | if (!TARGET_64BIT) | |
3540 | { | |
c41c1387 | 3541 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3542 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
3543 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
3544 | DONE; |
3545 | } | |
ec24698e | 3546 | }) |
4023fb28 UW |
3547 | |
3548 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
3549 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3550 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9db1d521 HP |
3551 | "TARGET_64BIT" |
3552 | "@ | |
d40c829f | 3553 | llgfr\t%0,%1 |
963fc8d0 AK |
3554 | llgf\t%0,%1 |
3555 | llgfrl\t%0,%1" | |
3556 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3557 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3558 | (set_attr "cpu_facility" "*,*,z10") |
3559 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 3560 | |
288e517f AK |
3561 | ; |
3562 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
3563 | ; | |
3564 | ||
d6083c7d UW |
3565 | (define_insn "*llgt_sidi" |
3566 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3567 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d UW |
3568 | (const_int 2147483647)))] |
3569 | "TARGET_64BIT" | |
3570 | "llgt\t%0,%1" | |
9381e3f1 WG |
3571 | [(set_attr "op_type" "RXE") |
3572 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
3573 | |
3574 | (define_insn_and_split "*llgt_sidi_split" | |
3575 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3576 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3577 | (const_int 2147483647))) |
ae156f85 | 3578 | (clobber (reg:CC CC_REGNUM))] |
d6083c7d UW |
3579 | "TARGET_64BIT" |
3580 | "#" | |
3581 | "&& reload_completed" | |
3582 | [(set (match_dup 0) | |
3583 | (and:DI (subreg:DI (match_dup 1) 0) | |
3584 | (const_int 2147483647)))] | |
3585 | "") | |
3586 | ||
288e517f AK |
3587 | (define_insn "*llgt_sisi" |
3588 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 3589 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 3590 | (const_int 2147483647)))] |
c4d50129 | 3591 | "TARGET_ZARCH" |
288e517f AK |
3592 | "@ |
3593 | llgtr\t%0,%1 | |
3594 | llgt\t%0,%1" | |
9381e3f1 WG |
3595 | [(set_attr "op_type" "RRE,RXE") |
3596 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3597 | |
288e517f AK |
3598 | (define_insn "*llgt_didi" |
3599 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3600 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
3601 | (const_int 2147483647)))] | |
3602 | "TARGET_64BIT" | |
3603 | "@ | |
3604 | llgtr\t%0,%1 | |
3605 | llgt\t%0,%N1" | |
9381e3f1 WG |
3606 | [(set_attr "op_type" "RRE,RXE") |
3607 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3608 | |
f19a9af7 | 3609 | (define_split |
f6ee577c AS |
3610 | [(set (match_operand:GPR 0 "register_operand" "") |
3611 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3612 | (const_int 2147483647))) | |
ae156f85 | 3613 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 3614 | "TARGET_ZARCH && reload_completed" |
288e517f | 3615 | [(set (match_dup 0) |
f6ee577c AS |
3616 | (and:GPR (match_dup 1) |
3617 | (const_int 2147483647)))] | |
288e517f AK |
3618 | "") |
3619 | ||
9db1d521 | 3620 | ; |
56477c21 | 3621 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3622 | ; |
3623 | ||
56477c21 AS |
3624 | (define_expand "zero_extend<mode>di2" |
3625 | [(set (match_operand:DI 0 "register_operand" "") | |
3626 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3627 | "" | |
3628 | { | |
3629 | if (!TARGET_64BIT) | |
3630 | { | |
3631 | rtx tmp = gen_reg_rtx (SImode); | |
3632 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3633 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3634 | DONE; | |
3635 | } | |
3636 | else if (!TARGET_EXTIMM) | |
3637 | { | |
9381e3f1 | 3638 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - |
56477c21 AS |
3639 | GET_MODE_BITSIZE(<MODE>mode)); |
3640 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3641 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
3642 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
3643 | DONE; | |
3644 | } | |
3645 | }) | |
3646 | ||
f6ee577c | 3647 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 3648 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 3649 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 3650 | "" |
4023fb28 | 3651 | { |
ec24698e UW |
3652 | if (!TARGET_EXTIMM) |
3653 | { | |
3654 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 3655 | emit_insn (gen_andsi3 (operands[0], operands[1], |
ec24698e UW |
3656 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); |
3657 | DONE; | |
56477c21 | 3658 | } |
ec24698e UW |
3659 | }) |
3660 | ||
963fc8d0 AK |
3661 | ; llhrl, llghrl |
3662 | (define_insn "*zero_extendhi<mode>2_z10" | |
3663 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3664 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
3665 | "TARGET_Z10" | |
3666 | "@ | |
3667 | ll<g>hr\t%0,%1 | |
3668 | ll<g>h\t%0,%1 | |
3669 | ll<g>hrl\t%0,%1" | |
3670 | [(set_attr "op_type" "RXY,RRE,RIL") | |
3671 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 3672 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 3673 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 3674 | |
43a09b63 | 3675 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
3676 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
3677 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3678 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3679 | "TARGET_EXTIMM" |
3680 | "@ | |
56477c21 AS |
3681 | ll<g><hc>r\t%0,%1 |
3682 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
3683 | [(set_attr "op_type" "RRE,RXY") |
3684 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 3685 | |
43a09b63 | 3686 | ; llgh, llgc |
56477c21 AS |
3687 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
3688 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3689 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 3690 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 3691 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
3692 | [(set_attr "op_type" "RXY") |
3693 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
3694 | |
3695 | (define_insn_and_split "*zero_extendhisi2_31" | |
3696 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 3697 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 3698 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 3699 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3700 | "#" |
3701 | "&& reload_completed" | |
3702 | [(set (match_dup 0) (const_int 0)) | |
3703 | (parallel | |
3704 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 3705 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 3706 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 3707 | |
cc7ab9b7 UW |
3708 | (define_insn_and_split "*zero_extendqisi2_31" |
3709 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 3710 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3711 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3712 | "#" |
3713 | "&& reload_completed" | |
3714 | [(set (match_dup 0) (const_int 0)) | |
3715 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3716 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 3717 | |
9db1d521 HP |
3718 | ; |
3719 | ; zero_extendqihi2 instruction pattern(s). | |
3720 | ; | |
3721 | ||
9db1d521 HP |
3722 | (define_expand "zero_extendqihi2" |
3723 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 3724 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 3725 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 3726 | { |
4023fb28 UW |
3727 | operands[1] = gen_lowpart (HImode, operands[1]); |
3728 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
3729 | DONE; | |
ec24698e | 3730 | }) |
9db1d521 | 3731 | |
4023fb28 | 3732 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 3733 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 3734 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 3735 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 3736 | "llgc\t%0,%1" |
9381e3f1 WG |
3737 | [(set_attr "op_type" "RXY") |
3738 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 3739 | |
cc7ab9b7 UW |
3740 | (define_insn_and_split "*zero_extendqihi2_31" |
3741 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 3742 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3743 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3744 | "#" |
3745 | "&& reload_completed" | |
3746 | [(set (match_dup 0) (const_int 0)) | |
3747 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3748 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 3749 | |
609e7e80 AK |
3750 | ; |
3751 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
3752 | ; | |
3753 | ||
3754 | (define_expand "fixuns_truncdddi2" | |
3755 | [(parallel | |
3756 | [(set (match_operand:DI 0 "register_operand" "") | |
3757 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
3758 | (clobber (match_scratch:TD 2 "=f"))])] | |
9381e3f1 | 3759 | |
fb068247 | 3760 | "TARGET_HARD_DFP" |
609e7e80 AK |
3761 | { |
3762 | rtx label1 = gen_label_rtx (); | |
3763 | rtx label2 = gen_label_rtx (); | |
3764 | rtx temp = gen_reg_rtx (TDmode); | |
3765 | REAL_VALUE_TYPE cmp, sub; | |
3766 | ||
3767 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3768 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3769 | ||
3770 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
9381e3f1 | 3771 | solution is doing the check and the subtraction in TD mode and using a |
609e7e80 AK |
3772 | TD -> DI convert afterwards. */ |
3773 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
3774 | temp = force_reg (TDmode, temp); | |
f90b7a5a PB |
3775 | emit_cmp_and_jump_insns (temp, |
3776 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
3777 | LT, NULL_RTX, VOIDmode, 0, label1); | |
609e7e80 AK |
3778 | emit_insn (gen_subtd3 (temp, temp, |
3779 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
99cd7dd0 | 3780 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
609e7e80 AK |
3781 | emit_jump (label2); |
3782 | ||
3783 | emit_label (label1); | |
99cd7dd0 | 3784 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); |
609e7e80 AK |
3785 | emit_label (label2); |
3786 | DONE; | |
3787 | }) | |
3788 | ||
3789 | (define_expand "fixuns_trunctddi2" | |
3790 | [(set (match_operand:DI 0 "register_operand" "") | |
3791 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))] | |
fb068247 | 3792 | "TARGET_HARD_DFP" |
609e7e80 AK |
3793 | { |
3794 | rtx label1 = gen_label_rtx (); | |
3795 | rtx label2 = gen_label_rtx (); | |
3796 | rtx temp = gen_reg_rtx (TDmode); | |
3797 | REAL_VALUE_TYPE cmp, sub; | |
9381e3f1 | 3798 | |
609e7e80 AK |
3799 | operands[1] = force_reg (TDmode, operands[1]); |
3800 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3801 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
9381e3f1 | 3802 | |
f90b7a5a PB |
3803 | emit_cmp_and_jump_insns (operands[1], |
3804 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
3805 | LT, NULL_RTX, VOIDmode, 0, label1); | |
609e7e80 AK |
3806 | emit_insn (gen_subtd3 (temp, operands[1], |
3807 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
99cd7dd0 | 3808 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
609e7e80 AK |
3809 | emit_jump (label2); |
3810 | ||
3811 | emit_label (label1); | |
99cd7dd0 | 3812 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); |
609e7e80 AK |
3813 | emit_label (label2); |
3814 | DONE; | |
3815 | }) | |
cc7ab9b7 | 3816 | |
9db1d521 | 3817 | ; |
9381e3f1 | 3818 | ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 |
609e7e80 | 3819 | ; instruction pattern(s). |
9db1d521 HP |
3820 | ; |
3821 | ||
7b6baae1 | 3822 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
2f8f8434 | 3823 | [(set (match_operand:GPR 0 "register_operand" "") |
7b6baae1 | 3824 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))] |
142cd70f | 3825 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3826 | { |
3827 | rtx label1 = gen_label_rtx (); | |
3828 | rtx label2 = gen_label_rtx (); | |
7b6baae1 | 3829 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); |
2f8f8434 | 3830 | REAL_VALUE_TYPE cmp, sub; |
9381e3f1 | 3831 | |
7b6baae1 | 3832 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); |
9e8c0677 AK |
3833 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); |
3834 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); | |
9381e3f1 | 3835 | |
f90b7a5a PB |
3836 | emit_cmp_and_jump_insns (operands[1], |
3837 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), | |
3838 | LT, NULL_RTX, VOIDmode, 0, label1); | |
7b6baae1 AK |
3839 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], |
3840 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); | |
142cd70f | 3841 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, |
99cd7dd0 | 3842 | GEN_INT (7))); |
f314b9b1 | 3843 | emit_jump (label2); |
9db1d521 HP |
3844 | |
3845 | emit_label (label1); | |
142cd70f | 3846 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], |
99cd7dd0 | 3847 | operands[1], GEN_INT (5))); |
9db1d521 HP |
3848 | emit_label (label2); |
3849 | DONE; | |
10bbf137 | 3850 | }) |
9db1d521 | 3851 | |
b60cb710 AK |
3852 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
3853 | [(set (match_operand:GPR 0 "register_operand" "") | |
3854 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
3855 | "TARGET_HARD_FLOAT" | |
9db1d521 | 3856 | { |
b60cb710 AK |
3857 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
3858 | GEN_INT (5))); | |
9db1d521 | 3859 | DONE; |
10bbf137 | 3860 | }) |
9db1d521 | 3861 | |
43a09b63 | 3862 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
142cd70f | 3863 | (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
2f8f8434 | 3864 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7b6baae1 | 3865 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) |
2f8f8434 | 3866 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) |
ae156f85 | 3867 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 3868 | "TARGET_HARD_FLOAT" |
7b6baae1 | 3869 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 3870 | [(set_attr "op_type" "RRE") |
077dab3b | 3871 | (set_attr "type" "ftoi")]) |
9db1d521 | 3872 | |
609e7e80 AK |
3873 | |
3874 | ; | |
3875 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
3876 | ; | |
3877 | ||
99cd7dd0 AK |
3878 | (define_expand "fix_trunc<mode>di2" |
3879 | [(set (match_operand:DI 0 "register_operand" "") | |
3880 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
fb068247 | 3881 | "TARGET_64BIT && TARGET_HARD_DFP" |
99cd7dd0 AK |
3882 | { |
3883 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
3884 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
3885 | GEN_INT (9))); | |
3886 | DONE; | |
3887 | }) | |
3888 | ||
609e7e80 | 3889 | ; cgxtr, cgdtr |
99cd7dd0 | 3890 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
3891 | [(set (match_operand:DI 0 "register_operand" "=d") |
3892 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
3893 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
3894 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 3895 | "TARGET_64BIT && TARGET_HARD_DFP" |
609e7e80 AK |
3896 | "cg<DFP:xde>tr\t%0,%h2,%1" |
3897 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 3898 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
3899 | |
3900 | ||
f61a2c7d AK |
3901 | ; |
3902 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
3903 | ; | |
3904 | ||
3905 | (define_expand "fix_trunctf<mode>2" | |
3906 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
3907 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
3908 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
3909 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 3910 | "TARGET_HARD_FLOAT" |
142cd70f | 3911 | "") |
9db1d521 | 3912 | |
9db1d521 | 3913 | |
9db1d521 | 3914 | ; |
142cd70f | 3915 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
3916 | ; |
3917 | ||
609e7e80 | 3918 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 3919 | (define_insn "floatdi<mode>2" |
609e7e80 AK |
3920 | [(set (match_operand:FP 0 "register_operand" "=f") |
3921 | (float:FP (match_operand:DI 1 "register_operand" "d")))] | |
142cd70f | 3922 | "TARGET_64BIT && TARGET_HARD_FLOAT" |
609e7e80 | 3923 | "c<xde>g<bt>r\t%0,%1" |
9db1d521 | 3924 | [(set_attr "op_type" "RRE") |
9381e3f1 | 3925 | (set_attr "type" "itof<mode>" )]) |
9db1d521 | 3926 | |
43a09b63 | 3927 | ; cxfbr, cdfbr, cefbr |
142cd70f | 3928 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
3929 | [(set (match_operand:BFP 0 "register_operand" "=f") |
3930 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 3931 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
3932 | "c<xde>fbr\t%0,%1" |
3933 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 3934 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d AK |
3935 | |
3936 | ||
9db1d521 HP |
3937 | ; |
3938 | ; truncdfsf2 instruction pattern(s). | |
3939 | ; | |
3940 | ||
142cd70f | 3941 | (define_insn "truncdfsf2" |
9db1d521 | 3942 | [(set (match_operand:SF 0 "register_operand" "=f") |
a036c6f7 | 3943 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
142cd70f | 3944 | "TARGET_HARD_FLOAT" |
d40c829f | 3945 | "ledbr\t%0,%1" |
f61a2c7d AK |
3946 | [(set_attr "op_type" "RRE") |
3947 | (set_attr "type" "ftruncdf")]) | |
9db1d521 | 3948 | |
f61a2c7d | 3949 | ; |
142cd70f | 3950 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
3951 | ; |
3952 | ||
142cd70f AK |
3953 | ; ldxbr, lexbr |
3954 | (define_insn "trunctf<mode>2" | |
3955 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
3956 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 3957 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
3958 | "TARGET_HARD_FLOAT" |
3959 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 3960 | [(set_attr "length" "6") |
9381e3f1 | 3961 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 3962 | |
609e7e80 AK |
3963 | ; |
3964 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
3965 | ; | |
3966 | ||
3967 | (define_insn "trunctddd2" | |
3968 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
3969 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
3970 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 3971 | "TARGET_HARD_DFP" |
bf259a77 AK |
3972 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
3973 | [(set_attr "length" "6") | |
9381e3f1 | 3974 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
3975 | |
3976 | (define_insn "truncddsd2" | |
3977 | [(set (match_operand:SD 0 "register_operand" "=f") | |
3978 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 3979 | "TARGET_HARD_DFP" |
609e7e80 AK |
3980 | "ledtr\t%0,0,%1,0" |
3981 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 3982 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 3983 | |
9db1d521 | 3984 | ; |
142cd70f | 3985 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
3986 | ; |
3987 | ||
142cd70f AK |
3988 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
3989 | (define_insn "extend<DSF:mode><BFP:mode>2" | |
3990 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
3991 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] | |
3992 | "TARGET_HARD_FLOAT | |
3993 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)" | |
f61a2c7d | 3994 | "@ |
142cd70f AK |
3995 | l<BFP:xde><DSF:xde>br\t%0,%1 |
3996 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
f61a2c7d | 3997 | [(set_attr "op_type" "RRE,RXE") |
142cd70f | 3998 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) |
f61a2c7d | 3999 | |
609e7e80 AK |
4000 | ; |
4001 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4002 | ; | |
4003 | ||
4004 | (define_insn "extendddtd2" | |
4005 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4006 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4007 | "TARGET_HARD_DFP" |
609e7e80 AK |
4008 | "lxdtr\t%0,%1,0" |
4009 | [(set_attr "op_type" "RRF") | |
4010 | (set_attr "type" "fsimptf")]) | |
4011 | ||
4012 | (define_insn "extendsddd2" | |
4013 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4014 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4015 | "TARGET_HARD_DFP" |
609e7e80 AK |
4016 | "ldetr\t%0,%1,0" |
4017 | [(set_attr "op_type" "RRF") | |
4018 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4019 | |
35dd9a0e AK |
4020 | ; Binary <-> Decimal floating point trunc patterns |
4021 | ; | |
4022 | ||
4023 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4024 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4025 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4026 | (use (reg:SI GPR0_REGNUM)) | |
4027 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4028 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4029 | "pfpo") |
4030 | ||
4031 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4032 | [(set (reg:BFP FPR0_REGNUM) | |
4033 | (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4034 | (use (reg:SI GPR0_REGNUM)) | |
4035 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4036 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4037 | "pfpo") |
4038 | ||
4039 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
4040 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4041 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4042 | (parallel | |
4043 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4044 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4045 | (use (reg:SI GPR0_REGNUM)) | |
4046 | (clobber (reg:CC CC_REGNUM))]) | |
4047 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4048 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4049 | "TARGET_HARD_DFP |
35dd9a0e AK |
4050 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4051 | { | |
4052 | HOST_WIDE_INT flags; | |
4053 | ||
4054 | flags = (PFPO_CONVERT | | |
4055 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4056 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4057 | ||
4058 | operands[2] = GEN_INT (flags); | |
4059 | }) | |
4060 | ||
4061 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
4062 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4063 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4064 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4065 | (parallel | |
4066 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4067 | (use (reg:SI GPR0_REGNUM)) | |
4068 | (clobber (reg:CC CC_REGNUM))]) | |
4069 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4070 | "TARGET_HARD_DFP |
35dd9a0e AK |
4071 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
4072 | { | |
4073 | HOST_WIDE_INT flags; | |
4074 | ||
4075 | flags = (PFPO_CONVERT | | |
4076 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4077 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4078 | ||
4079 | operands[2] = GEN_INT (flags); | |
4080 | }) | |
4081 | ||
4082 | ; | |
4083 | ; Binary <-> Decimal floating point extend patterns | |
4084 | ; | |
4085 | ||
4086 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
4087 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4088 | (use (reg:SI GPR0_REGNUM)) | |
4089 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4090 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4091 | "pfpo") |
4092 | ||
4093 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
4094 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4095 | (use (reg:SI GPR0_REGNUM)) | |
4096 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4097 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4098 | "pfpo") |
4099 | ||
4100 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
4101 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4102 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4103 | (parallel | |
4104 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4105 | (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4106 | (use (reg:SI GPR0_REGNUM)) | |
4107 | (clobber (reg:CC CC_REGNUM))]) | |
4108 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4109 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4110 | "TARGET_HARD_DFP |
35dd9a0e AK |
4111 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4112 | { | |
4113 | HOST_WIDE_INT flags; | |
4114 | ||
4115 | flags = (PFPO_CONVERT | | |
4116 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4117 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4118 | ||
4119 | operands[2] = GEN_INT (flags); | |
4120 | }) | |
4121 | ||
4122 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
4123 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4124 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4125 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4126 | (parallel | |
4127 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4128 | (use (reg:SI GPR0_REGNUM)) | |
4129 | (clobber (reg:CC CC_REGNUM))]) | |
4130 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4131 | "TARGET_HARD_DFP |
35dd9a0e AK |
4132 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
4133 | { | |
4134 | HOST_WIDE_INT flags; | |
4135 | ||
4136 | flags = (PFPO_CONVERT | | |
4137 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4138 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4139 | ||
4140 | operands[2] = GEN_INT (flags); | |
4141 | }) | |
4142 | ||
4143 | ||
9db1d521 | 4144 | ;; |
fae778eb | 4145 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 4146 | ;; |
fae778eb | 4147 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
4148 | ; because of unpredictable Bits in Register for Halfword and Byte |
4149 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
4150 | ||
07893d4f UW |
4151 | ;; |
4152 | ;;- Add instructions. | |
4153 | ;; | |
4154 | ||
1c7b1b7e UW |
4155 | ; |
4156 | ; addti3 instruction pattern(s). | |
4157 | ; | |
4158 | ||
4159 | (define_insn_and_split "addti3" | |
4160 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4161 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
4162 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4163 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
4164 | "TARGET_64BIT" |
4165 | "#" | |
4166 | "&& reload_completed" | |
4167 | [(parallel | |
ae156f85 | 4168 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
4169 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
4170 | (match_dup 7))) | |
4171 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
4172 | (parallel | |
a94a76a7 UW |
4173 | [(set (match_dup 3) (plus:DI |
4174 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4175 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4176 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
4177 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4178 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4179 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4180 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4181 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4182 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4183 | |
07893d4f UW |
4184 | ; |
4185 | ; adddi3 instruction pattern(s). | |
4186 | ; | |
4187 | ||
3298c037 AK |
4188 | (define_expand "adddi3" |
4189 | [(parallel | |
963fc8d0 | 4190 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
4191 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
4192 | (match_operand:DI 2 "general_operand" ""))) | |
4193 | (clobber (reg:CC CC_REGNUM))])] | |
4194 | "" | |
4195 | "") | |
4196 | ||
07893d4f UW |
4197 | (define_insn "*adddi3_sign" |
4198 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4199 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4200 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4201 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4202 | "TARGET_64BIT" |
4203 | "@ | |
d40c829f UW |
4204 | agfr\t%0,%2 |
4205 | agf\t%0,%2" | |
d3632d41 | 4206 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
4207 | |
4208 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 4209 | [(set (reg CC_REGNUM) |
fb492564 | 4210 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4211 | (match_operand:DI 1 "register_operand" "0,0")) |
4212 | (const_int 0))) | |
4213 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4214 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
4215 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4216 | "@ | |
d40c829f UW |
4217 | algfr\t%0,%2 |
4218 | algf\t%0,%2" | |
9381e3f1 WG |
4219 | [(set_attr "op_type" "RRE,RXY") |
4220 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4221 | |
4222 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 4223 | [(set (reg CC_REGNUM) |
fb492564 | 4224 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4225 | (match_operand:DI 1 "register_operand" "0,0")) |
4226 | (const_int 0))) | |
4227 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4228 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4229 | "@ | |
d40c829f UW |
4230 | algfr\t%0,%2 |
4231 | algf\t%0,%2" | |
9381e3f1 WG |
4232 | [(set_attr "op_type" "RRE,RXY") |
4233 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4234 | |
4235 | (define_insn "*adddi3_zero" | |
4236 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4237 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4238 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4239 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4240 | "TARGET_64BIT" |
4241 | "@ | |
d40c829f UW |
4242 | algfr\t%0,%2 |
4243 | algf\t%0,%2" | |
9381e3f1 WG |
4244 | [(set_attr "op_type" "RRE,RXY") |
4245 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 4246 | |
e69166de | 4247 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 4248 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
4249 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
4250 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4251 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
4252 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4253 | "#" | |
4254 | "&& reload_completed" | |
4255 | [(parallel | |
ae156f85 | 4256 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
4257 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4258 | (match_dup 7))) | |
4259 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4260 | (parallel | |
a94a76a7 UW |
4261 | [(set (match_dup 3) (plus:SI |
4262 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4263 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4264 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
4265 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4266 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4267 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4268 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4269 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4270 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4271 | |
07893d4f | 4272 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 4273 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 4274 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 4275 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4276 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4277 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4278 | "#" |
4279 | "&& reload_completed" | |
4280 | [(parallel | |
4281 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4282 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4283 | (parallel |
ae156f85 | 4284 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
4285 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4286 | (match_dup 7))) | |
4287 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4288 | (set (pc) | |
ae156f85 | 4289 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4290 | (pc) |
4291 | (label_ref (match_dup 9)))) | |
4292 | (parallel | |
4293 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 4294 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4295 | (match_dup 9)] |
97c6f7ad UW |
4296 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4297 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4298 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4299 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4300 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4301 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4302 | operands[9] = gen_label_rtx ();") |
9db1d521 | 4303 | |
3298c037 AK |
4304 | ; |
4305 | ; addsi3 instruction pattern(s). | |
4306 | ; | |
4307 | ||
4308 | (define_expand "addsi3" | |
07893d4f | 4309 | [(parallel |
963fc8d0 | 4310 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
4311 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
4312 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4313 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4314 | "" |
07893d4f | 4315 | "") |
9db1d521 | 4316 | |
3298c037 AK |
4317 | (define_insn "*addsi3_sign" |
4318 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4319 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
4320 | (match_operand:SI 1 "register_operand" "0,0"))) | |
4321 | (clobber (reg:CC CC_REGNUM))] | |
4322 | "" | |
4323 | "@ | |
4324 | ah\t%0,%2 | |
4325 | ahy\t%0,%2" | |
4326 | [(set_attr "op_type" "RX,RXY")]) | |
4327 | ||
9db1d521 | 4328 | ; |
3298c037 | 4329 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 4330 | ; |
9db1d521 | 4331 | |
963fc8d0 | 4332 | ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 4333 | (define_insn "*add<mode>3" |
963fc8d0 AK |
4334 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS") |
4335 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") | |
4336 | (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
4337 | (clobber (reg:CC CC_REGNUM))] |
4338 | "" | |
ec24698e | 4339 | "@ |
3298c037 AK |
4340 | a<g>r\t%0,%2 |
4341 | a<g>hi\t%0,%h2 | |
4342 | al<g>fi\t%0,%2 | |
4343 | sl<g>fi\t%0,%n2 | |
4344 | a<g>\t%0,%2 | |
963fc8d0 AK |
4345 | a<y>\t%0,%2 |
4346 | a<g>si\t%0,%c2" | |
4347 | [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") | |
9381e3f1 WG |
4348 | (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10") |
4349 | (set_attr "z10prop" "z10_super_E1, | |
4350 | z10_super_E1, | |
4351 | z10_super_E1, | |
4352 | z10_super_E1, | |
4353 | z10_super_E1, | |
4354 | z10_super_E1, | |
4355 | z10_super_E1")]) | |
0a3bdf9d | 4356 | |
963fc8d0 | 4357 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi |
3298c037 | 4358 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 4359 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
4360 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") |
4361 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
07893d4f | 4362 | (match_dup 1))) |
963fc8d0 | 4363 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d") |
3298c037 | 4364 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4365 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4366 | "@ |
3298c037 AK |
4367 | al<g>r\t%0,%2 |
4368 | al<g>fi\t%0,%2 | |
4369 | sl<g>fi\t%0,%n2 | |
4370 | al<g>\t%0,%2 | |
963fc8d0 AK |
4371 | al<y>\t%0,%2 |
4372 | al<g>si\t%0,%c2" | |
4373 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
9381e3f1 WG |
4374 | (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") |
4375 | (set_attr "z10prop" "z10_super_E1, | |
4376 | z10_super_E1, | |
4377 | z10_super_E1, | |
4378 | z10_super_E1, | |
4379 | z10_super_E1, | |
4380 | z10_super_E1")]) | |
07893d4f | 4381 | |
43a09b63 | 4382 | ; alr, al, aly, algr, alg |
3298c037 | 4383 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 4384 | [(set (reg CC_REGNUM) |
3298c037 AK |
4385 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
4386 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4387 | (match_dup 1))) |
3298c037 | 4388 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 4389 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4390 | "@ |
3298c037 AK |
4391 | al<g>r\t%0,%2 |
4392 | al<g>\t%0,%2 | |
4393 | al<y>\t%0,%2" | |
9381e3f1 WG |
4394 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4395 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4396 | |
963fc8d0 | 4397 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi |
3298c037 | 4398 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 4399 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
4400 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") |
4401 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
07893d4f | 4402 | (match_dup 2))) |
963fc8d0 | 4403 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") |
3298c037 | 4404 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4405 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4406 | "@ |
3298c037 AK |
4407 | al<g>r\t%0,%2 |
4408 | al<g>fi\t%0,%2 | |
4409 | sl<g>fi\t%0,%n2 | |
4410 | al<g>\t%0,%2 | |
963fc8d0 AK |
4411 | al<y>\t%0,%2 |
4412 | al<g>si\t%0,%c2" | |
4413 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
9381e3f1 WG |
4414 | (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") |
4415 | (set_attr "z10prop" "z10_super_E1, | |
4416 | z10_super_E1, | |
4417 | z10_super_E1, | |
4418 | z10_super_E1, | |
4419 | z10_super_E1, | |
4420 | z10_super_E1")]) | |
07893d4f | 4421 | |
43a09b63 | 4422 | ; alr, al, aly, algr, alg |
3298c037 | 4423 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 4424 | [(set (reg CC_REGNUM) |
3298c037 AK |
4425 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
4426 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4427 | (match_dup 2))) |
3298c037 | 4428 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 4429 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4430 | "@ |
3298c037 AK |
4431 | al<g>r\t%0,%2 |
4432 | al<g>\t%0,%2 | |
4433 | al<y>\t%0,%2" | |
9381e3f1 WG |
4434 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4435 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4436 | |
963fc8d0 | 4437 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi |
3298c037 | 4438 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4439 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
4440 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") |
4441 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
9db1d521 | 4442 | (const_int 0))) |
963fc8d0 | 4443 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") |
3298c037 | 4444 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4445 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4446 | "@ |
3298c037 AK |
4447 | al<g>r\t%0,%2 |
4448 | al<g>fi\t%0,%2 | |
4449 | sl<g>fi\t%0,%n2 | |
4450 | al<g>\t%0,%2 | |
963fc8d0 AK |
4451 | al<y>\t%0,%2 |
4452 | al<g>si\t%0,%c2" | |
4453 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
9381e3f1 WG |
4454 | (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") |
4455 | (set_attr "z10prop" "z10_super_E1, | |
4456 | z10_super_E1, | |
4457 | z10_super_E1, | |
4458 | z10_super_E1, | |
4459 | z10_super_E1, | |
4460 | z10_super_E1")]) | |
9db1d521 | 4461 | |
43a09b63 | 4462 | ; alr, al, aly, algr, alg |
3298c037 | 4463 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4464 | [(set (reg CC_REGNUM) |
3298c037 AK |
4465 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
4466 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 4467 | (const_int 0))) |
3298c037 | 4468 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 4469 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4470 | "@ |
3298c037 AK |
4471 | al<g>r\t%0,%2 |
4472 | al<g>\t%0,%2 | |
4473 | al<y>\t%0,%2" | |
9381e3f1 WG |
4474 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4475 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4476 | |
43a09b63 | 4477 | ; alr, al, aly, algr, alg |
3298c037 | 4478 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 4479 | [(set (reg CC_REGNUM) |
3298c037 AK |
4480 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
4481 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T")))) | |
4482 | (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4483 | "s390_match_ccmode(insn, CCLmode)" | |
d3632d41 | 4484 | "@ |
3298c037 AK |
4485 | al<g>r\t%0,%2 |
4486 | al<g>\t%0,%2 | |
4487 | al<y>\t%0,%2" | |
9381e3f1 WG |
4488 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4489 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4490 | |
963fc8d0 | 4491 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
4492 | (define_insn "*add<mode>3_imm_cc" |
4493 | [(set (reg CC_REGNUM) | |
963fc8d0 AK |
4494 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0") |
4495 | (match_operand:GPR 2 "const_int_operand" "K,Os,C")) | |
3298c037 | 4496 | (const_int 0))) |
963fc8d0 | 4497 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS") |
3298c037 AK |
4498 | (plus:GPR (match_dup 1) (match_dup 2)))] |
4499 | "s390_match_ccmode (insn, CCAmode) | |
4500 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
963fc8d0 AK |
4501 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
4502 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) | |
3298c037 | 4503 | && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" |
9db1d521 | 4504 | "@ |
3298c037 | 4505 | a<g>hi\t%0,%h2 |
963fc8d0 AK |
4506 | a<g>fi\t%0,%2 |
4507 | a<g>si\t%0,%c2" | |
4508 | [(set_attr "op_type" "RI,RIL,SIY") | |
9381e3f1 WG |
4509 | (set_attr "cpu_facility" "*,extimm,z10") |
4510 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4511 | |
9db1d521 | 4512 | ; |
609e7e80 | 4513 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4514 | ; |
4515 | ||
609e7e80 | 4516 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
142cd70f | 4517 | (define_insn "add<mode>3" |
609e7e80 AK |
4518 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4519 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4520 | (match_operand:FP 2 "general_operand" " f,<Rf>"))) | |
ae156f85 | 4521 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4522 | "TARGET_HARD_FLOAT" |
9db1d521 | 4523 | "@ |
609e7e80 | 4524 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4525 | a<xde>b\t%0,%2" |
609e7e80 | 4526 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4527 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4528 | |
609e7e80 | 4529 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4530 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4531 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4532 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4533 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4534 | (match_operand:FP 3 "const0_operand" ""))) | |
4535 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
4536 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 4537 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4538 | "@ |
609e7e80 | 4539 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4540 | a<xde>b\t%0,%2" |
609e7e80 | 4541 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4542 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4543 | |
609e7e80 | 4544 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4545 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4546 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4547 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4548 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4549 | (match_operand:FP 3 "const0_operand" ""))) | |
4550 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 4551 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4552 | "@ |
609e7e80 | 4553 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4554 | a<xde>b\t%0,%2" |
609e7e80 | 4555 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4556 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4557 | |
9db1d521 HP |
4558 | |
4559 | ;; | |
4560 | ;;- Subtract instructions. | |
4561 | ;; | |
4562 | ||
1c7b1b7e UW |
4563 | ; |
4564 | ; subti3 instruction pattern(s). | |
4565 | ; | |
4566 | ||
4567 | (define_insn_and_split "subti3" | |
4568 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4569 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
4570 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4571 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
4572 | "TARGET_64BIT" |
4573 | "#" | |
4574 | "&& reload_completed" | |
4575 | [(parallel | |
ae156f85 | 4576 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
4577 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
4578 | (match_dup 7))) | |
4579 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
4580 | (parallel | |
4581 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4582 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4583 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
4584 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4585 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4586 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4587 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4588 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4589 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4590 | |
9db1d521 HP |
4591 | ; |
4592 | ; subdi3 instruction pattern(s). | |
4593 | ; | |
4594 | ||
3298c037 AK |
4595 | (define_expand "subdi3" |
4596 | [(parallel | |
4597 | [(set (match_operand:DI 0 "register_operand" "") | |
4598 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4599 | (match_operand:DI 2 "general_operand" ""))) | |
4600 | (clobber (reg:CC CC_REGNUM))])] | |
4601 | "" | |
4602 | "") | |
4603 | ||
07893d4f UW |
4604 | (define_insn "*subdi3_sign" |
4605 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4606 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4607 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4608 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4609 | "TARGET_64BIT" |
4610 | "@ | |
d40c829f UW |
4611 | sgfr\t%0,%2 |
4612 | sgf\t%0,%2" | |
9381e3f1 WG |
4613 | [(set_attr "op_type" "RRE,RXY") |
4614 | (set_attr "z10prop" "z10_c,*")]) | |
07893d4f UW |
4615 | |
4616 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 4617 | [(set (reg CC_REGNUM) |
07893d4f | 4618 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4619 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4620 | (const_int 0))) |
4621 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4622 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
4623 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4624 | "@ | |
d40c829f UW |
4625 | slgfr\t%0,%2 |
4626 | slgf\t%0,%2" | |
9381e3f1 WG |
4627 | [(set_attr "op_type" "RRE,RXY") |
4628 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4629 | |
4630 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 4631 | [(set (reg CC_REGNUM) |
07893d4f | 4632 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4633 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4634 | (const_int 0))) |
4635 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4636 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4637 | "@ | |
d40c829f UW |
4638 | slgfr\t%0,%2 |
4639 | slgf\t%0,%2" | |
9381e3f1 WG |
4640 | [(set_attr "op_type" "RRE,RXY") |
4641 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4642 | |
4643 | (define_insn "*subdi3_zero" | |
4644 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4645 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4646 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4647 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4648 | "TARGET_64BIT" |
4649 | "@ | |
d40c829f UW |
4650 | slgfr\t%0,%2 |
4651 | slgf\t%0,%2" | |
9381e3f1 WG |
4652 | [(set_attr "op_type" "RRE,RXY") |
4653 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 4654 | |
e69166de UW |
4655 | (define_insn_and_split "*subdi3_31z" |
4656 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4657 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4658 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4659 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
4660 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4661 | "#" | |
4662 | "&& reload_completed" | |
4663 | [(parallel | |
ae156f85 | 4664 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
4665 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4666 | (match_dup 7))) | |
4667 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4668 | (parallel | |
4669 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4670 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4671 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
4672 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4673 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4674 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4675 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4676 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4677 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4678 | |
07893d4f UW |
4679 | (define_insn_and_split "*subdi3_31" |
4680 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4681 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 4682 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4683 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4684 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4685 | "#" |
4686 | "&& reload_completed" | |
4687 | [(parallel | |
4688 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4689 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4690 | (parallel |
ae156f85 | 4691 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
4692 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4693 | (match_dup 7))) | |
4694 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4695 | (set (pc) | |
ae156f85 | 4696 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4697 | (pc) |
4698 | (label_ref (match_dup 9)))) | |
4699 | (parallel | |
4700 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 4701 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4702 | (match_dup 9)] |
97c6f7ad UW |
4703 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4704 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4705 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4706 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4707 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4708 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4709 | operands[9] = gen_label_rtx ();") |
07893d4f | 4710 | |
3298c037 AK |
4711 | ; |
4712 | ; subsi3 instruction pattern(s). | |
4713 | ; | |
4714 | ||
4715 | (define_expand "subsi3" | |
07893d4f | 4716 | [(parallel |
3298c037 AK |
4717 | [(set (match_operand:SI 0 "register_operand" "") |
4718 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
4719 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4720 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4721 | "" |
07893d4f | 4722 | "") |
9db1d521 | 4723 | |
3298c037 AK |
4724 | (define_insn "*subsi3_sign" |
4725 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4726 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4727 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
4728 | (clobber (reg:CC CC_REGNUM))] | |
4729 | "" | |
4730 | "@ | |
4731 | sh\t%0,%2 | |
4732 | shy\t%0,%2" | |
4733 | [(set_attr "op_type" "RX,RXY")]) | |
4734 | ||
9db1d521 | 4735 | ; |
3298c037 | 4736 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
4737 | ; |
4738 | ||
43a09b63 | 4739 | ; sr, s, sy, sgr, sg |
3298c037 AK |
4740 | (define_insn "*sub<mode>3" |
4741 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4742 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") | |
4743 | (match_operand:GPR 2 "general_operand" "d,R,T") ) ) | |
4744 | (clobber (reg:CC CC_REGNUM))] | |
4745 | "" | |
4746 | "@ | |
4747 | s<g>r\t%0,%2 | |
4748 | s<g>\t%0,%2 | |
4749 | s<y>\t%0,%2" | |
9381e3f1 WG |
4750 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4751 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
3298c037 | 4752 | |
43a09b63 | 4753 | ; slr, sl, sly, slgr, slg |
3298c037 | 4754 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 4755 | [(set (reg CC_REGNUM) |
3298c037 AK |
4756 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4757 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4758 | (match_dup 1))) |
3298c037 AK |
4759 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") |
4760 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 4761 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4762 | "@ |
3298c037 AK |
4763 | sl<g>r\t%0,%2 |
4764 | sl<g>\t%0,%2 | |
4765 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4766 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4767 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4768 | |
43a09b63 | 4769 | ; slr, sl, sly, slgr, slg |
3298c037 | 4770 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 4771 | [(set (reg CC_REGNUM) |
3298c037 AK |
4772 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4773 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4774 | (match_dup 1))) |
3298c037 | 4775 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
b2ba71ca | 4776 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4777 | "@ |
3298c037 AK |
4778 | sl<g>r\t%0,%2 |
4779 | sl<g>\t%0,%2 | |
4780 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4781 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4782 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4783 | |
43a09b63 | 4784 | ; slr, sl, sly, slgr, slg |
3298c037 | 4785 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4786 | [(set (reg CC_REGNUM) |
3298c037 AK |
4787 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4788 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 4789 | (const_int 0))) |
3298c037 AK |
4790 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") |
4791 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 4792 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4793 | "@ |
3298c037 AK |
4794 | sl<g>r\t%0,%2 |
4795 | sl<g>\t%0,%2 | |
4796 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4797 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4798 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4799 | |
43a09b63 | 4800 | ; slr, sl, sly, slgr, slg |
3298c037 | 4801 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 4802 | [(set (reg CC_REGNUM) |
3298c037 AK |
4803 | (compare (match_operand:GPR 1 "register_operand" "0,0,0") |
4804 | (match_operand:GPR 2 "general_operand" "d,R,T"))) | |
4805 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4806 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
5d880bd2 UW |
4807 | "s390_match_ccmode (insn, CCL3mode)" |
4808 | "@ | |
3298c037 AK |
4809 | sl<g>r\t%0,%2 |
4810 | sl<g>\t%0,%2 | |
4811 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4812 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4813 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 4814 | |
43a09b63 | 4815 | ; slr, sl, sly, slgr, slg |
3298c037 | 4816 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 4817 | [(set (reg CC_REGNUM) |
3298c037 AK |
4818 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4819 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 4820 | (const_int 0))) |
3298c037 | 4821 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
b2ba71ca | 4822 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4823 | "@ |
3298c037 AK |
4824 | sl<g>r\t%0,%2 |
4825 | sl<g>\t%0,%2 | |
4826 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4827 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4828 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4829 | ||
9db1d521 | 4830 | |
43a09b63 | 4831 | ; slr, sl, sly, slgr, slg |
3298c037 | 4832 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 4833 | [(set (reg CC_REGNUM) |
3298c037 AK |
4834 | (compare (match_operand:GPR 1 "register_operand" "0,0,0") |
4835 | (match_operand:GPR 2 "general_operand" "d,R,T"))) | |
4836 | (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
5d880bd2 UW |
4837 | "s390_match_ccmode (insn, CCL3mode)" |
4838 | "@ | |
3298c037 AK |
4839 | sl<g>r\t%0,%2 |
4840 | sl<g>\t%0,%2 | |
4841 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4842 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4843 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4844 | ||
9db1d521 HP |
4845 | |
4846 | ; | |
609e7e80 | 4847 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4848 | ; |
4849 | ||
d46f24b6 | 4850 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 4851 | (define_insn "sub<mode>3" |
609e7e80 AK |
4852 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4853 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
142cd70f | 4854 | (match_operand:FP 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 4855 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4856 | "TARGET_HARD_FLOAT" |
9db1d521 | 4857 | "@ |
609e7e80 | 4858 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4859 | s<xde>b\t%0,%2" |
609e7e80 | 4860 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4861 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4862 | |
d46f24b6 | 4863 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 4864 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4865 | [(set (reg CC_REGNUM) |
609e7e80 | 4866 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 4867 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
4868 | (match_operand:FP 3 "const0_operand" ""))) |
4869 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
4870 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 4871 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4872 | "@ |
609e7e80 | 4873 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4874 | s<xde>b\t%0,%2" |
609e7e80 | 4875 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4876 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4877 | |
d46f24b6 | 4878 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 4879 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 4880 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4881 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
4882 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
4883 | (match_operand:FP 3 "const0_operand" ""))) | |
4884 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 4885 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4886 | "@ |
609e7e80 | 4887 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4888 | s<xde>b\t%0,%2" |
609e7e80 | 4889 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4890 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4891 | |
9db1d521 | 4892 | |
e69166de UW |
4893 | ;; |
4894 | ;;- Conditional add/subtract instructions. | |
4895 | ;; | |
4896 | ||
4897 | ; | |
9a91a21f | 4898 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
4899 | ; |
4900 | ||
a996720c UW |
4901 | ; the following 4 patterns are used when the result of an add with |
4902 | ; carry is checked for an overflow condition | |
4903 | ||
4904 | ; op1 + op2 + c < op1 | |
4905 | ||
4906 | ; alcr, alc, alcgr, alcg | |
4907 | (define_insn "*add<mode>3_alc_carry1_cc" | |
4908 | [(set (reg CC_REGNUM) | |
4909 | (compare | |
4910 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4911 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4912 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
4913 | (match_dup 1))) |
4914 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
4915 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
4916 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4917 | "@ | |
4918 | alc<g>r\t%0,%2 | |
4919 | alc<g>\t%0,%2" | |
4920 | [(set_attr "op_type" "RRE,RXY")]) | |
4921 | ||
4922 | ; alcr, alc, alcgr, alcg | |
4923 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
4924 | [(set (reg CC_REGNUM) | |
4925 | (compare | |
4926 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4927 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4928 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
4929 | (match_dup 1))) |
4930 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
4931 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4932 | "@ | |
4933 | alc<g>r\t%0,%2 | |
4934 | alc<g>\t%0,%2" | |
4935 | [(set_attr "op_type" "RRE,RXY")]) | |
4936 | ||
4937 | ; op1 + op2 + c < op2 | |
4938 | ||
4939 | ; alcr, alc, alcgr, alcg | |
4940 | (define_insn "*add<mode>3_alc_carry2_cc" | |
4941 | [(set (reg CC_REGNUM) | |
4942 | (compare | |
4943 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4944 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4945 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
4946 | (match_dup 2))) |
4947 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
4948 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
4949 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4950 | "@ | |
4951 | alc<g>r\t%0,%2 | |
4952 | alc<g>\t%0,%2" | |
4953 | [(set_attr "op_type" "RRE,RXY")]) | |
4954 | ||
4955 | ; alcr, alc, alcgr, alcg | |
4956 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
4957 | [(set (reg CC_REGNUM) | |
4958 | (compare | |
4959 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4960 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4961 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
4962 | (match_dup 2))) |
4963 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
4964 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4965 | "@ | |
4966 | alc<g>r\t%0,%2 | |
4967 | alc<g>\t%0,%2" | |
4968 | [(set_attr "op_type" "RRE,RXY")]) | |
4969 | ||
43a09b63 | 4970 | ; alcr, alc, alcgr, alcg |
9a91a21f | 4971 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 4972 | [(set (reg CC_REGNUM) |
e69166de | 4973 | (compare |
a94a76a7 UW |
4974 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
4975 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4976 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 4977 | (const_int 0))) |
9a91a21f | 4978 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 4979 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 4980 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4981 | "@ |
9a91a21f AS |
4982 | alc<g>r\t%0,%2 |
4983 | alc<g>\t%0,%2" | |
e69166de UW |
4984 | [(set_attr "op_type" "RRE,RXY")]) |
4985 | ||
43a09b63 | 4986 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
4987 | (define_insn "*add<mode>3_alc" |
4988 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
4989 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
4990 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4991 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 4992 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 4993 | "TARGET_CPU_ZARCH" |
e69166de | 4994 | "@ |
9a91a21f AS |
4995 | alc<g>r\t%0,%2 |
4996 | alc<g>\t%0,%2" | |
e69166de UW |
4997 | [(set_attr "op_type" "RRE,RXY")]) |
4998 | ||
43a09b63 | 4999 | ; slbr, slb, slbgr, slbg |
9a91a21f | 5000 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 5001 | [(set (reg CC_REGNUM) |
e69166de | 5002 | (compare |
9a91a21f | 5003 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 5004 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5005 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 5006 | (const_int 0))) |
9a91a21f AS |
5007 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
5008 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 5009 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5010 | "@ |
9a91a21f AS |
5011 | slb<g>r\t%0,%2 |
5012 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5013 | [(set_attr "op_type" "RRE,RXY") |
5014 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5015 | |
43a09b63 | 5016 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
5017 | (define_insn "*sub<mode>3_slb" |
5018 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5019 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 5020 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5021 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 5022 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5023 | "TARGET_CPU_ZARCH" |
e69166de | 5024 | "@ |
9a91a21f AS |
5025 | slb<g>r\t%0,%2 |
5026 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5027 | [(set_attr "op_type" "RRE,RXY") |
5028 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5029 | |
9a91a21f AS |
5030 | (define_expand "add<mode>cc" |
5031 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 5032 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
5033 | (match_operand:GPR 2 "register_operand" "") |
5034 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 5035 | "TARGET_CPU_ZARCH" |
9381e3f1 | 5036 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 5037 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 5038 | operands[0], operands[2], |
5d880bd2 UW |
5039 | operands[3])) FAIL; DONE;") |
5040 | ||
5041 | ; | |
5042 | ; scond instruction pattern(s). | |
5043 | ; | |
5044 | ||
9a91a21f AS |
5045 | (define_insn_and_split "*scond<mode>" |
5046 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5047 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 5048 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5049 | "TARGET_CPU_ZARCH" |
5050 | "#" | |
5051 | "&& reload_completed" | |
5052 | [(set (match_dup 0) (const_int 0)) | |
5053 | (parallel | |
a94a76a7 UW |
5054 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
5055 | (match_dup 0))) | |
ae156f85 | 5056 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5057 | "") |
5d880bd2 | 5058 | |
9a91a21f AS |
5059 | (define_insn_and_split "*scond<mode>_neg" |
5060 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5061 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 5062 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5063 | "TARGET_CPU_ZARCH" |
5064 | "#" | |
5065 | "&& reload_completed" | |
5066 | [(set (match_dup 0) (const_int 0)) | |
5067 | (parallel | |
9a91a21f AS |
5068 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
5069 | (match_dup 1))) | |
ae156f85 | 5070 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 5071 | (parallel |
9a91a21f | 5072 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 5073 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5074 | "") |
5d880bd2 | 5075 | |
5d880bd2 | 5076 | |
f90b7a5a | 5077 | (define_expand "cstore<mode>4" |
9a91a21f | 5078 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
5079 | (match_operator:SI 1 "s390_scond_operator" |
5080 | [(match_operand:GPR 2 "register_operand" "") | |
5081 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 5082 | "TARGET_CPU_ZARCH" |
f90b7a5a | 5083 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
5084 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
5085 | ||
f90b7a5a | 5086 | (define_expand "cstorecc4" |
69950452 | 5087 | [(parallel |
f90b7a5a PB |
5088 | [(set (match_operand:SI 0 "register_operand" "") |
5089 | (match_operator:SI 1 "s390_eqne_operator" | |
5090 | [(match_operand:CCZ1 2 "register_operand") | |
5091 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
5092 | (clobber (reg:CC CC_REGNUM))])] |
5093 | "" | |
f90b7a5a PB |
5094 | "emit_insn (gen_sne (operands[0], operands[2])); |
5095 | if (GET_CODE (operands[1]) == EQ) | |
5096 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
5097 | DONE;") | |
69950452 | 5098 | |
f90b7a5a | 5099 | (define_insn_and_split "sne" |
69950452 | 5100 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 5101 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
5102 | (const_int 0))) |
5103 | (clobber (reg:CC CC_REGNUM))] | |
5104 | "" | |
5105 | "#" | |
5106 | "reload_completed" | |
5107 | [(parallel | |
5108 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
5109 | (clobber (reg:CC CC_REGNUM))])]) | |
5110 | ||
e69166de | 5111 | |
9db1d521 HP |
5112 | ;; |
5113 | ;;- Multiply instructions. | |
5114 | ;; | |
5115 | ||
4023fb28 UW |
5116 | ; |
5117 | ; muldi3 instruction pattern(s). | |
5118 | ; | |
9db1d521 | 5119 | |
07893d4f UW |
5120 | (define_insn "*muldi3_sign" |
5121 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 5122 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5123 | (match_operand:DI 1 "register_operand" "0,0")))] |
5124 | "TARGET_64BIT" | |
5125 | "@ | |
d40c829f UW |
5126 | msgfr\t%0,%2 |
5127 | msgf\t%0,%2" | |
963fc8d0 AK |
5128 | [(set_attr "op_type" "RRE,RXY") |
5129 | (set_attr "type" "imuldi")]) | |
07893d4f | 5130 | |
4023fb28 | 5131 | (define_insn "muldi3" |
963fc8d0 AK |
5132 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
5133 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5134 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9db1d521 HP |
5135 | "TARGET_64BIT" |
5136 | "@ | |
d40c829f UW |
5137 | msgr\t%0,%2 |
5138 | mghi\t%0,%h2 | |
963fc8d0 AK |
5139 | msg\t%0,%2 |
5140 | msgfi\t%0,%2" | |
5141 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
5142 | (set_attr "type" "imuldi") | |
5143 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 5144 | |
9db1d521 HP |
5145 | ; |
5146 | ; mulsi3 instruction pattern(s). | |
5147 | ; | |
5148 | ||
f1e77d83 | 5149 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
5150 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
5151 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5152 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 5153 | "" |
963fc8d0 AK |
5154 | "@ |
5155 | mh\t%0,%2 | |
5156 | mhy\t%0,%2" | |
5157 | [(set_attr "op_type" "RX,RXY") | |
5158 | (set_attr "type" "imulhi") | |
5159 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 5160 | |
9db1d521 | 5161 | (define_insn "mulsi3" |
963fc8d0 AK |
5162 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
5163 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5164 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
5165 | "" |
5166 | "@ | |
d40c829f UW |
5167 | msr\t%0,%2 |
5168 | mhi\t%0,%h2 | |
5169 | ms\t%0,%2 | |
963fc8d0 AK |
5170 | msy\t%0,%2 |
5171 | msfi\t%0,%2" | |
5172 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
5173 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
5174 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 5175 | |
4023fb28 UW |
5176 | ; |
5177 | ; mulsidi3 instruction pattern(s). | |
5178 | ; | |
5179 | ||
f1e77d83 | 5180 | (define_insn "mulsidi3" |
963fc8d0 | 5181 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 5182 | (mult:DI (sign_extend:DI |
963fc8d0 | 5183 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 5184 | (sign_extend:DI |
963fc8d0 | 5185 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
4023fb28 | 5186 | "!TARGET_64BIT" |
f1e77d83 UW |
5187 | "@ |
5188 | mr\t%0,%2 | |
963fc8d0 AK |
5189 | m\t%0,%2 |
5190 | mfy\t%0,%2" | |
5191 | [(set_attr "op_type" "RR,RX,RXY") | |
5192 | (set_attr "type" "imulsi") | |
5193 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 5194 | |
f1e77d83 UW |
5195 | ; |
5196 | ; umulsidi3 instruction pattern(s). | |
5197 | ; | |
c7453384 | 5198 | |
f1e77d83 UW |
5199 | (define_insn "umulsidi3" |
5200 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5201 | (mult:DI (zero_extend:DI | |
5202 | (match_operand:SI 1 "register_operand" "%0,0")) | |
5203 | (zero_extend:DI | |
fb492564 | 5204 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))] |
f1e77d83 UW |
5205 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
5206 | "@ | |
5207 | mlr\t%0,%2 | |
5208 | ml\t%0,%2" | |
5209 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 5210 | (set_attr "type" "imulsi")]) |
c7453384 | 5211 | |
9db1d521 | 5212 | ; |
609e7e80 | 5213 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5214 | ; |
5215 | ||
9381e3f1 | 5216 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 5217 | (define_insn "mul<mode>3" |
609e7e80 AK |
5218 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5219 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
5220 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5221 | "TARGET_HARD_FLOAT" |
9db1d521 | 5222 | "@ |
609e7e80 | 5223 | m<xdee><bt>r\t%0,<op1>%2 |
f61a2c7d | 5224 | m<xdee>b\t%0,%2" |
609e7e80 | 5225 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5226 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 5227 | |
9381e3f1 | 5228 | ; madbr, maebr, maxb, madb, maeb |
f5905b37 | 5229 | (define_insn "*fmadd<mode>" |
f61a2c7d AK |
5230 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
5231 | (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f") | |
5232 | (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
5233 | (match_operand:DSF 3 "register_operand" "0,0")))] | |
142cd70f | 5234 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 5235 | "@ |
f61a2c7d AK |
5236 | ma<xde>br\t%0,%1,%2 |
5237 | ma<xde>b\t%0,%1,%2" | |
a1b892b5 | 5238 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 5239 | (set_attr "type" "fmul<mode>")]) |
a1b892b5 | 5240 | |
43a09b63 | 5241 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
f5905b37 | 5242 | (define_insn "*fmsub<mode>" |
f61a2c7d AK |
5243 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
5244 | (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f") | |
5245 | (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
5246 | (match_operand:DSF 3 "register_operand" "0,0")))] | |
142cd70f | 5247 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 5248 | "@ |
f61a2c7d AK |
5249 | ms<xde>br\t%0,%1,%2 |
5250 | ms<xde>b\t%0,%1,%2" | |
ce50cae8 | 5251 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 5252 | (set_attr "type" "fmul<mode>")]) |
9db1d521 HP |
5253 | |
5254 | ;; | |
5255 | ;;- Divide and modulo instructions. | |
5256 | ;; | |
5257 | ||
5258 | ; | |
4023fb28 | 5259 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
5260 | ; |
5261 | ||
4023fb28 UW |
5262 | (define_expand "divmoddi4" |
5263 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 5264 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
5265 | (match_operand:DI 2 "general_operand" ""))) |
5266 | (set (match_operand:DI 3 "general_operand" "") | |
5267 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
5268 | (clobber (match_dup 4))] | |
9db1d521 | 5269 | "TARGET_64BIT" |
9db1d521 | 5270 | { |
f1e77d83 | 5271 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
5272 | |
5273 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
5274 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
5275 | |
5276 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 5277 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
5278 | |
5279 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5280 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5281 | |
5282 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5283 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5284 | |
9db1d521 | 5285 | DONE; |
10bbf137 | 5286 | }) |
9db1d521 HP |
5287 | |
5288 | (define_insn "divmodtidi3" | |
4023fb28 UW |
5289 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
5290 | (ior:TI | |
4023fb28 UW |
5291 | (ashift:TI |
5292 | (zero_extend:TI | |
5665e398 | 5293 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5294 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
5295 | (const_int 64)) |
5296 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
5297 | "TARGET_64BIT" |
5298 | "@ | |
d40c829f UW |
5299 | dsgr\t%0,%2 |
5300 | dsg\t%0,%2" | |
d3632d41 | 5301 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5302 | (set_attr "type" "idiv")]) |
9db1d521 | 5303 | |
4023fb28 UW |
5304 | (define_insn "divmodtisi3" |
5305 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5306 | (ior:TI | |
4023fb28 UW |
5307 | (ashift:TI |
5308 | (zero_extend:TI | |
5665e398 | 5309 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 5310 | (sign_extend:DI |
fb492564 | 5311 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
5312 | (const_int 64)) |
5313 | (zero_extend:TI | |
5314 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 5315 | "TARGET_64BIT" |
4023fb28 | 5316 | "@ |
d40c829f UW |
5317 | dsgfr\t%0,%2 |
5318 | dsgf\t%0,%2" | |
d3632d41 | 5319 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5320 | (set_attr "type" "idiv")]) |
9db1d521 | 5321 | |
4023fb28 UW |
5322 | ; |
5323 | ; udivmoddi4 instruction pattern(s). | |
5324 | ; | |
9db1d521 | 5325 | |
4023fb28 UW |
5326 | (define_expand "udivmoddi4" |
5327 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5328 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
5329 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
5330 | (set (match_operand:DI 3 "general_operand" "") | |
5331 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
5332 | (clobber (match_dup 4))] | |
9db1d521 | 5333 | "TARGET_64BIT" |
9db1d521 | 5334 | { |
4023fb28 UW |
5335 | rtx insn, div_equal, mod_equal, equal; |
5336 | ||
5337 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
5338 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
5339 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
5340 | gen_rtx_ASHIFT (TImode, |
5341 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
5342 | GEN_INT (64)), |
5343 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
5344 | |
5345 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 5346 | emit_clobber (operands[4]); |
4023fb28 UW |
5347 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
5348 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 5349 | |
4023fb28 | 5350 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5351 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5352 | |
5353 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5354 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5355 | |
5356 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5357 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5358 | |
9db1d521 | 5359 | DONE; |
10bbf137 | 5360 | }) |
9db1d521 HP |
5361 | |
5362 | (define_insn "udivmodtidi3" | |
4023fb28 | 5363 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 5364 | (ior:TI |
5665e398 UW |
5365 | (ashift:TI |
5366 | (zero_extend:TI | |
5367 | (truncate:DI | |
2f7e5a0d EC |
5368 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
5369 | (zero_extend:TI | |
fb492564 | 5370 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5371 | (const_int 64)) |
5372 | (zero_extend:TI | |
5373 | (truncate:DI | |
5374 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
5375 | "TARGET_64BIT" |
5376 | "@ | |
d40c829f UW |
5377 | dlgr\t%0,%2 |
5378 | dlg\t%0,%2" | |
d3632d41 | 5379 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5380 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5381 | |
5382 | ; | |
4023fb28 | 5383 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
5384 | ; |
5385 | ||
4023fb28 UW |
5386 | (define_expand "divmodsi4" |
5387 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5388 | (div:SI (match_operand:SI 1 "general_operand" "") | |
5389 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5390 | (set (match_operand:SI 3 "general_operand" "") | |
5391 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
5392 | (clobber (match_dup 4))] | |
9db1d521 | 5393 | "!TARGET_64BIT" |
9db1d521 | 5394 | { |
4023fb28 UW |
5395 | rtx insn, div_equal, mod_equal, equal; |
5396 | ||
5397 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
5398 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
5399 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5400 | gen_rtx_ASHIFT (DImode, |
5401 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5402 | GEN_INT (32)), |
5403 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
5404 | |
5405 | operands[4] = gen_reg_rtx(DImode); | |
5406 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 5407 | |
4023fb28 | 5408 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5409 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5410 | |
5411 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5412 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5413 | |
5414 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5415 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5416 | |
9db1d521 | 5417 | DONE; |
10bbf137 | 5418 | }) |
9db1d521 HP |
5419 | |
5420 | (define_insn "divmoddisi3" | |
4023fb28 | 5421 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 5422 | (ior:DI |
5665e398 UW |
5423 | (ashift:DI |
5424 | (zero_extend:DI | |
5425 | (truncate:SI | |
2f7e5a0d EC |
5426 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
5427 | (sign_extend:DI | |
5665e398 UW |
5428 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
5429 | (const_int 32)) | |
5430 | (zero_extend:DI | |
5431 | (truncate:SI | |
5432 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
5433 | "!TARGET_64BIT" |
5434 | "@ | |
d40c829f UW |
5435 | dr\t%0,%2 |
5436 | d\t%0,%2" | |
9db1d521 | 5437 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5438 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5439 | |
5440 | ; | |
5441 | ; udivsi3 and umodsi3 instruction pattern(s). | |
5442 | ; | |
5443 | ||
f1e77d83 UW |
5444 | (define_expand "udivmodsi4" |
5445 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5446 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5447 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5448 | (set (match_operand:SI 3 "general_operand" "") | |
5449 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
5450 | (clobber (match_dup 4))] | |
5451 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
5452 | { | |
5453 | rtx insn, div_equal, mod_equal, equal; | |
5454 | ||
5455 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5456 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5457 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
5458 | gen_rtx_ASHIFT (DImode, |
5459 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5460 | GEN_INT (32)), |
5461 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
5462 | |
5463 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 5464 | emit_clobber (operands[4]); |
f1e77d83 UW |
5465 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
5466 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 5467 | |
f1e77d83 | 5468 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5469 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
5470 | |
5471 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5472 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
5473 | |
5474 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5475 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
5476 | |
5477 | DONE; | |
5478 | }) | |
5479 | ||
5480 | (define_insn "udivmoddisi3" | |
5481 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 5482 | (ior:DI |
5665e398 UW |
5483 | (ashift:DI |
5484 | (zero_extend:DI | |
5485 | (truncate:SI | |
2f7e5a0d EC |
5486 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
5487 | (zero_extend:DI | |
fb492564 | 5488 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5489 | (const_int 32)) |
5490 | (zero_extend:DI | |
5491 | (truncate:SI | |
5492 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
5493 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
5494 | "@ | |
5495 | dlr\t%0,%2 | |
5496 | dl\t%0,%2" | |
5497 | [(set_attr "op_type" "RRE,RXY") | |
5498 | (set_attr "type" "idiv")]) | |
4023fb28 | 5499 | |
9db1d521 HP |
5500 | (define_expand "udivsi3" |
5501 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5502 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
5503 | (match_operand:SI 2 "general_operand" ""))) |
5504 | (clobber (match_dup 3))] | |
f1e77d83 | 5505 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 5506 | { |
4023fb28 UW |
5507 | rtx insn, udiv_equal, umod_equal, equal; |
5508 | ||
5509 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5510 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5511 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5512 | gen_rtx_ASHIFT (DImode, |
5513 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5514 | GEN_INT (32)), |
5515 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5516 | |
4023fb28 | 5517 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5518 | |
5519 | if (CONSTANT_P (operands[2])) | |
5520 | { | |
5521 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
5522 | { | |
5523 | rtx label1 = gen_label_rtx (); | |
5524 | ||
4023fb28 UW |
5525 | operands[1] = make_safe_from (operands[1], operands[0]); |
5526 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5527 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
5528 | SImode, 1, label1); | |
4023fb28 | 5529 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5530 | emit_label (label1); |
5531 | } | |
5532 | else | |
5533 | { | |
c7453384 EC |
5534 | operands[2] = force_reg (SImode, operands[2]); |
5535 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5536 | |
5537 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5538 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5539 | operands[2])); | |
bd94cb6e | 5540 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5541 | |
5542 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5543 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 5544 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
5545 | } |
5546 | } | |
5547 | else | |
c7453384 | 5548 | { |
9db1d521 HP |
5549 | rtx label1 = gen_label_rtx (); |
5550 | rtx label2 = gen_label_rtx (); | |
5551 | rtx label3 = gen_label_rtx (); | |
5552 | ||
c7453384 EC |
5553 | operands[1] = force_reg (SImode, operands[1]); |
5554 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5555 | operands[2] = force_reg (SImode, operands[2]); | |
5556 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5557 | |
5558 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5559 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
5560 | SImode, 1, label3); | |
5561 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
5562 | SImode, 0, label2); | |
5563 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
5564 | SImode, 0, label1); | |
4023fb28 UW |
5565 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5566 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5567 | operands[2])); | |
bd94cb6e | 5568 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5569 | |
5570 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5571 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
5572 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
5573 | ||
f314b9b1 | 5574 | emit_jump (label3); |
9db1d521 | 5575 | emit_label (label1); |
4023fb28 | 5576 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 5577 | emit_jump (label3); |
9db1d521 | 5578 | emit_label (label2); |
4023fb28 | 5579 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5580 | emit_label (label3); |
5581 | } | |
c7453384 | 5582 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 5583 | DONE; |
10bbf137 | 5584 | }) |
9db1d521 HP |
5585 | |
5586 | (define_expand "umodsi3" | |
5587 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5588 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
5589 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
5590 | (clobber (match_dup 3))] | |
f1e77d83 | 5591 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 5592 | { |
4023fb28 UW |
5593 | rtx insn, udiv_equal, umod_equal, equal; |
5594 | ||
5595 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5596 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5597 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5598 | gen_rtx_ASHIFT (DImode, |
5599 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5600 | GEN_INT (32)), |
5601 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5602 | |
4023fb28 | 5603 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5604 | |
5605 | if (CONSTANT_P (operands[2])) | |
5606 | { | |
5607 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
5608 | { | |
5609 | rtx label1 = gen_label_rtx (); | |
5610 | ||
4023fb28 UW |
5611 | operands[1] = make_safe_from (operands[1], operands[0]); |
5612 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
5613 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
5614 | SImode, 1, label1); | |
4023fb28 UW |
5615 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
5616 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
5617 | emit_label (label1); |
5618 | } | |
5619 | else | |
5620 | { | |
c7453384 EC |
5621 | operands[2] = force_reg (SImode, operands[2]); |
5622 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5623 | |
5624 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5625 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5626 | operands[2])); | |
bd94cb6e | 5627 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5628 | |
5629 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5630 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 5631 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
5632 | } |
5633 | } | |
5634 | else | |
5635 | { | |
5636 | rtx label1 = gen_label_rtx (); | |
5637 | rtx label2 = gen_label_rtx (); | |
5638 | rtx label3 = gen_label_rtx (); | |
5639 | ||
c7453384 EC |
5640 | operands[1] = force_reg (SImode, operands[1]); |
5641 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5642 | operands[2] = force_reg (SImode, operands[2]); | |
5643 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5644 | |
c7453384 | 5645 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
5646 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
5647 | SImode, 1, label3); | |
5648 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
5649 | SImode, 0, label2); | |
5650 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
5651 | SImode, 0, label1); | |
4023fb28 UW |
5652 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5653 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5654 | operands[2])); | |
bd94cb6e | 5655 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5656 | |
5657 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5658 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
5659 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
5660 | ||
f314b9b1 | 5661 | emit_jump (label3); |
9db1d521 | 5662 | emit_label (label1); |
4023fb28 | 5663 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5664 | emit_jump (label3); |
9db1d521 | 5665 | emit_label (label2); |
4023fb28 | 5666 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5667 | emit_label (label3); |
5668 | } | |
9db1d521 | 5669 | DONE; |
10bbf137 | 5670 | }) |
9db1d521 HP |
5671 | |
5672 | ; | |
f5905b37 | 5673 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
5674 | ; |
5675 | ||
609e7e80 | 5676 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 5677 | (define_insn "div<mode>3" |
609e7e80 AK |
5678 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5679 | (div:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
5680 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5681 | "TARGET_HARD_FLOAT" |
9db1d521 | 5682 | "@ |
609e7e80 | 5683 | d<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5684 | d<xde>b\t%0,%2" |
609e7e80 | 5685 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5686 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 5687 | |
9db1d521 HP |
5688 | |
5689 | ;; | |
5690 | ;;- And instructions. | |
5691 | ;; | |
5692 | ||
047d35ed AS |
5693 | (define_expand "and<mode>3" |
5694 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5695 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5696 | (match_operand:INT 2 "general_operand" ""))) | |
5697 | (clobber (reg:CC CC_REGNUM))] | |
5698 | "" | |
5699 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
5700 | ||
9db1d521 HP |
5701 | ; |
5702 | ; anddi3 instruction pattern(s). | |
5703 | ; | |
5704 | ||
5705 | (define_insn "*anddi3_cc" | |
ae156f85 | 5706 | [(set (reg CC_REGNUM) |
96fd3851 | 5707 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 5708 | (match_operand:DI 2 "general_operand" "d,RT")) |
9db1d521 | 5709 | (const_int 0))) |
4023fb28 | 5710 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
5711 | (and:DI (match_dup 1) (match_dup 2)))] |
5712 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5713 | "@ | |
d40c829f UW |
5714 | ngr\t%0,%2 |
5715 | ng\t%0,%2" | |
9381e3f1 WG |
5716 | [(set_attr "op_type" "RRE,RXY") |
5717 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
5718 | |
5719 | (define_insn "*anddi3_cconly" | |
ae156f85 | 5720 | [(set (reg CC_REGNUM) |
96fd3851 | 5721 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 5722 | (match_operand:DI 2 "general_operand" "d,RT")) |
9db1d521 HP |
5723 | (const_int 0))) |
5724 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
5725 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
5726 | /* Do not steal TM patterns. */ | |
5727 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 5728 | "@ |
d40c829f UW |
5729 | ngr\t%0,%2 |
5730 | ng\t%0,%2" | |
9381e3f1 WG |
5731 | [(set_attr "op_type" "RRE,RXY") |
5732 | (set_attr "z10prop" "z10_super_E1, z10_super_E1")]) | |
9db1d521 | 5733 | |
3af8e996 | 5734 | (define_insn "*anddi3" |
ec24698e UW |
5735 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") |
5736 | (and:DI (match_operand:DI 1 "nonimmediate_operand" | |
5737 | "%d,o,0,0,0,0,0,0,0,0,0,0") | |
5738 | (match_operand:DI 2 "general_operand" | |
fb492564 | 5739 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) |
ec24698e | 5740 | (clobber (reg:CC CC_REGNUM))] |
3af8e996 | 5741 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
5742 | "@ |
5743 | # | |
5744 | # | |
5745 | nihh\t%0,%j2 | |
5746 | nihl\t%0,%j2 | |
5747 | nilh\t%0,%j2 | |
5748 | nill\t%0,%j2 | |
5749 | nihf\t%0,%m2 | |
5750 | nilf\t%0,%m2 | |
5751 | ngr\t%0,%2 | |
5752 | ng\t%0,%2 | |
5753 | # | |
5754 | #" | |
3af8e996 | 5755 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") |
9381e3f1 WG |
5756 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*") |
5757 | (set_attr "z10prop" "*, | |
5758 | *, | |
5759 | z10_super_E1, | |
5760 | z10_super_E1, | |
5761 | z10_super_E1, | |
5762 | z10_super_E1, | |
5763 | z10_super_E1, | |
5764 | z10_super_E1, | |
5765 | z10_super_E1, | |
5766 | z10_super_E1, | |
5767 | *, | |
5768 | *")]) | |
0dfa6c5e UW |
5769 | |
5770 | (define_split | |
5771 | [(set (match_operand:DI 0 "s_operand" "") | |
5772 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5773 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5774 | "reload_completed" |
5775 | [(parallel | |
5776 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5777 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5778 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5779 | |
9db1d521 HP |
5780 | |
5781 | ; | |
5782 | ; andsi3 instruction pattern(s). | |
5783 | ; | |
5784 | ||
5785 | (define_insn "*andsi3_cc" | |
ae156f85 | 5786 | [(set (reg CC_REGNUM) |
ec24698e UW |
5787 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5788 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5789 | (const_int 0))) |
ec24698e | 5790 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
9db1d521 HP |
5791 | (and:SI (match_dup 1) (match_dup 2)))] |
5792 | "s390_match_ccmode(insn, CCTmode)" | |
5793 | "@ | |
ec24698e | 5794 | nilf\t%0,%o2 |
d40c829f UW |
5795 | nr\t%0,%2 |
5796 | n\t%0,%2 | |
5797 | ny\t%0,%2" | |
9381e3f1 WG |
5798 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
5799 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
5800 | |
5801 | (define_insn "*andsi3_cconly" | |
ae156f85 | 5802 | [(set (reg CC_REGNUM) |
ec24698e UW |
5803 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5804 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5805 | (const_int 0))) |
ec24698e | 5806 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
68f9c5e2 UW |
5807 | "s390_match_ccmode(insn, CCTmode) |
5808 | /* Do not steal TM patterns. */ | |
5809 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 5810 | "@ |
ec24698e | 5811 | nilf\t%0,%o2 |
d40c829f UW |
5812 | nr\t%0,%2 |
5813 | n\t%0,%2 | |
5814 | ny\t%0,%2" | |
9381e3f1 WG |
5815 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
5816 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5817 | |
f19a9af7 | 5818 | (define_insn "*andsi3_zarch" |
ec24698e | 5819 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
0dfa6c5e | 5820 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
ec24698e | 5821 | "%d,o,0,0,0,0,0,0,0,0") |
0dfa6c5e | 5822 | (match_operand:SI 2 "general_operand" |
ec24698e | 5823 | "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q"))) |
ae156f85 | 5824 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5825 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5826 | "@ |
f19a9af7 AK |
5827 | # |
5828 | # | |
5829 | nilh\t%0,%j2 | |
2f7e5a0d | 5830 | nill\t%0,%j2 |
ec24698e | 5831 | nilf\t%0,%o2 |
d40c829f UW |
5832 | nr\t%0,%2 |
5833 | n\t%0,%2 | |
8cb66696 | 5834 | ny\t%0,%2 |
0dfa6c5e | 5835 | # |
19b63d8e | 5836 | #" |
9381e3f1 WG |
5837 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS") |
5838 | (set_attr "z10prop" "*, | |
5839 | *, | |
5840 | z10_super_E1, | |
5841 | z10_super_E1, | |
5842 | z10_super_E1, | |
5843 | z10_super_E1, | |
5844 | z10_super_E1, | |
5845 | z10_super_E1, | |
5846 | *, | |
5847 | *")]) | |
f19a9af7 AK |
5848 | |
5849 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
5850 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5851 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5852 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
ae156f85 | 5853 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5854 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5855 | "@ |
5856 | nr\t%0,%2 | |
8cb66696 | 5857 | n\t%0,%2 |
0dfa6c5e | 5858 | # |
19b63d8e | 5859 | #" |
9381e3f1 WG |
5860 | [(set_attr "op_type" "RR,RX,SI,SS") |
5861 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
5862 | ||
0dfa6c5e UW |
5863 | |
5864 | (define_split | |
5865 | [(set (match_operand:SI 0 "s_operand" "") | |
5866 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5867 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5868 | "reload_completed" |
5869 | [(parallel | |
5870 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5871 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5872 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5873 | |
9db1d521 HP |
5874 | ; |
5875 | ; andhi3 instruction pattern(s). | |
5876 | ; | |
5877 | ||
8cb66696 | 5878 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
5879 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5880 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5881 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
ae156f85 | 5882 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5883 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5884 | "@ |
d40c829f | 5885 | nr\t%0,%2 |
8cb66696 | 5886 | nill\t%0,%x2 |
0dfa6c5e | 5887 | # |
19b63d8e | 5888 | #" |
9381e3f1 WG |
5889 | [(set_attr "op_type" "RR,RI,SI,SS") |
5890 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*") | |
5891 | ]) | |
8cb66696 UW |
5892 | |
5893 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
5894 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5895 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5896 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 5897 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5898 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5899 | "@ | |
5900 | nr\t%0,%2 | |
0dfa6c5e | 5901 | # |
19b63d8e | 5902 | #" |
9381e3f1 WG |
5903 | [(set_attr "op_type" "RR,SI,SS") |
5904 | (set_attr "z10prop" "z10_super_E1,*,*") | |
5905 | ]) | |
0dfa6c5e UW |
5906 | |
5907 | (define_split | |
5908 | [(set (match_operand:HI 0 "s_operand" "") | |
5909 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5910 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5911 | "reload_completed" |
5912 | [(parallel | |
5913 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5914 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5915 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 5916 | |
9db1d521 HP |
5917 | ; |
5918 | ; andqi3 instruction pattern(s). | |
5919 | ; | |
5920 | ||
8cb66696 UW |
5921 | (define_insn "*andqi3_zarch" |
5922 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5923 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5924 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5925 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5926 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5927 | "@ |
d40c829f | 5928 | nr\t%0,%2 |
8cb66696 | 5929 | nill\t%0,%b2 |
fc0ea003 UW |
5930 | ni\t%S0,%b2 |
5931 | niy\t%S0,%b2 | |
19b63d8e | 5932 | #" |
9381e3f1 WG |
5933 | [(set_attr "op_type" "RR,RI,SI,SIY,SS") |
5934 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
5935 | |
5936 | (define_insn "*andqi3_esa" | |
5937 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5938 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5939 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5940 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5941 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5942 | "@ |
8cb66696 | 5943 | nr\t%0,%2 |
fc0ea003 | 5944 | ni\t%S0,%b2 |
19b63d8e | 5945 | #" |
9381e3f1 WG |
5946 | [(set_attr "op_type" "RR,SI,SS") |
5947 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 5948 | |
19b63d8e UW |
5949 | ; |
5950 | ; Block and (NC) patterns. | |
5951 | ; | |
5952 | ||
5953 | (define_insn "*nc" | |
5954 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5955 | (and:BLK (match_dup 0) | |
5956 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5957 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5958 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5959 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5960 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 5961 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5962 | |
5963 | (define_split | |
5964 | [(set (match_operand 0 "memory_operand" "") | |
5965 | (and (match_dup 0) | |
5966 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5967 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5968 | "reload_completed |
5969 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5970 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5971 | [(parallel | |
5972 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
5973 | (use (match_dup 2)) | |
ae156f85 | 5974 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5975 | { |
5976 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5977 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5978 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5979 | }) | |
5980 | ||
5981 | (define_peephole2 | |
5982 | [(parallel | |
5983 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5984 | (and:BLK (match_dup 0) | |
5985 | (match_operand:BLK 1 "memory_operand" ""))) | |
5986 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5987 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5988 | (parallel |
5989 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5990 | (and:BLK (match_dup 3) | |
5991 | (match_operand:BLK 4 "memory_operand" ""))) | |
5992 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5993 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5994 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5995 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 5996 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 5997 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
5998 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5999 | [(parallel | |
6000 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
6001 | (use (match_dup 8)) | |
ae156f85 | 6002 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6003 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6004 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6005 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6006 | ||
9db1d521 HP |
6007 | |
6008 | ;; | |
6009 | ;;- Bit set (inclusive or) instructions. | |
6010 | ;; | |
6011 | ||
047d35ed AS |
6012 | (define_expand "ior<mode>3" |
6013 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6014 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6015 | (match_operand:INT 2 "general_operand" ""))) | |
6016 | (clobber (reg:CC CC_REGNUM))] | |
6017 | "" | |
6018 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
6019 | ||
9db1d521 HP |
6020 | ; |
6021 | ; iordi3 instruction pattern(s). | |
6022 | ; | |
6023 | ||
4023fb28 | 6024 | (define_insn "*iordi3_cc" |
ae156f85 | 6025 | [(set (reg CC_REGNUM) |
96fd3851 | 6026 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 6027 | (match_operand:DI 2 "general_operand" "d,RT")) |
4023fb28 UW |
6028 | (const_int 0))) |
6029 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6030 | (ior:DI (match_dup 1) (match_dup 2)))] | |
6031 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6032 | "@ | |
d40c829f UW |
6033 | ogr\t%0,%2 |
6034 | og\t%0,%2" | |
9381e3f1 WG |
6035 | [(set_attr "op_type" "RRE,RXY") |
6036 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6037 | |
6038 | (define_insn "*iordi3_cconly" | |
ae156f85 | 6039 | [(set (reg CC_REGNUM) |
96fd3851 | 6040 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 6041 | (match_operand:DI 2 "general_operand" "d,RT")) |
4023fb28 UW |
6042 | (const_int 0))) |
6043 | (clobber (match_scratch:DI 0 "=d,d"))] | |
6044 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6045 | "@ | |
d40c829f UW |
6046 | ogr\t%0,%2 |
6047 | og\t%0,%2" | |
9381e3f1 WG |
6048 | [(set_attr "op_type" "RRE,RXY") |
6049 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6050 | |
3af8e996 | 6051 | (define_insn "*iordi3" |
ec24698e UW |
6052 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
6053 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") | |
6054 | (match_operand:DI 2 "general_operand" | |
fb492564 | 6055 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) |
ec24698e | 6056 | (clobber (reg:CC CC_REGNUM))] |
3af8e996 | 6057 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6058 | "@ |
6059 | oihh\t%0,%i2 | |
6060 | oihl\t%0,%i2 | |
6061 | oilh\t%0,%i2 | |
6062 | oill\t%0,%i2 | |
6063 | oihf\t%0,%k2 | |
6064 | oilf\t%0,%k2 | |
6065 | ogr\t%0,%2 | |
6066 | og\t%0,%2 | |
6067 | # | |
6068 | #" | |
3af8e996 | 6069 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") |
9381e3f1 WG |
6070 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*") |
6071 | (set_attr "z10prop" "z10_super_E1, | |
6072 | z10_super_E1, | |
6073 | z10_super_E1, | |
6074 | z10_super_E1, | |
6075 | z10_super_E1, | |
6076 | z10_super_E1, | |
6077 | z10_super_E1, | |
6078 | z10_super_E1, | |
6079 | *, | |
6080 | *")]) | |
0dfa6c5e UW |
6081 | |
6082 | (define_split | |
6083 | [(set (match_operand:DI 0 "s_operand" "") | |
6084 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6085 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6086 | "reload_completed" |
6087 | [(parallel | |
6088 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6089 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6090 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6091 | |
9db1d521 HP |
6092 | ; |
6093 | ; iorsi3 instruction pattern(s). | |
6094 | ; | |
6095 | ||
4023fb28 | 6096 | (define_insn "*iorsi3_cc" |
ae156f85 | 6097 | [(set (reg CC_REGNUM) |
ec24698e UW |
6098 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
6099 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 6100 | (const_int 0))) |
ec24698e | 6101 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
6102 | (ior:SI (match_dup 1) (match_dup 2)))] |
6103 | "s390_match_ccmode(insn, CCTmode)" | |
6104 | "@ | |
ec24698e | 6105 | oilf\t%0,%o2 |
d40c829f UW |
6106 | or\t%0,%2 |
6107 | o\t%0,%2 | |
6108 | oy\t%0,%2" | |
9381e3f1 WG |
6109 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
6110 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6111 | |
6112 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 6113 | [(set (reg CC_REGNUM) |
ec24698e UW |
6114 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
6115 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 6116 | (const_int 0))) |
ec24698e | 6117 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
6118 | "s390_match_ccmode(insn, CCTmode)" |
6119 | "@ | |
ec24698e | 6120 | oilf\t%0,%o2 |
d40c829f UW |
6121 | or\t%0,%2 |
6122 | o\t%0,%2 | |
6123 | oy\t%0,%2" | |
9381e3f1 WG |
6124 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
6125 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6126 | |
8cb66696 | 6127 | (define_insn "*iorsi3_zarch" |
ec24698e UW |
6128 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
6129 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") | |
6130 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6131 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6132 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6133 | "@ |
f19a9af7 AK |
6134 | oilh\t%0,%i2 |
6135 | oill\t%0,%i2 | |
ec24698e | 6136 | oilf\t%0,%o2 |
d40c829f UW |
6137 | or\t%0,%2 |
6138 | o\t%0,%2 | |
8cb66696 | 6139 | oy\t%0,%2 |
0dfa6c5e | 6140 | # |
19b63d8e | 6141 | #" |
9381e3f1 WG |
6142 | [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS") |
6143 | (set_attr "z10prop" "z10_super_E1, | |
6144 | z10_super_E1, | |
6145 | z10_super_E1, | |
6146 | z10_super_E1, | |
6147 | z10_super_E1, | |
6148 | z10_super_E1, | |
6149 | *, | |
6150 | *")]) | |
8cb66696 UW |
6151 | |
6152 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 6153 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 6154 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 6155 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 6156 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6157 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6158 | "@ |
6159 | or\t%0,%2 | |
8cb66696 | 6160 | o\t%0,%2 |
0dfa6c5e | 6161 | # |
19b63d8e | 6162 | #" |
9381e3f1 WG |
6163 | [(set_attr "op_type" "RR,RX,SI,SS") |
6164 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6165 | |
6166 | (define_split | |
6167 | [(set (match_operand:SI 0 "s_operand" "") | |
6168 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6169 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6170 | "reload_completed" |
6171 | [(parallel | |
6172 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6173 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6174 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6175 | |
4023fb28 UW |
6176 | ; |
6177 | ; iorhi3 instruction pattern(s). | |
6178 | ; | |
6179 | ||
8cb66696 | 6180 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
6181 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
6182 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
6183 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
ae156f85 | 6184 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6185 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6186 | "@ |
d40c829f | 6187 | or\t%0,%2 |
8cb66696 | 6188 | oill\t%0,%x2 |
0dfa6c5e | 6189 | # |
19b63d8e | 6190 | #" |
9381e3f1 WG |
6191 | [(set_attr "op_type" "RR,RI,SI,SS") |
6192 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
8cb66696 UW |
6193 | |
6194 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
6195 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6196 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6197 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 6198 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6199 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6200 | "@ | |
6201 | or\t%0,%2 | |
0dfa6c5e | 6202 | # |
19b63d8e | 6203 | #" |
9381e3f1 WG |
6204 | [(set_attr "op_type" "RR,SI,SS") |
6205 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6206 | |
6207 | (define_split | |
6208 | [(set (match_operand:HI 0 "s_operand" "") | |
6209 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6210 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6211 | "reload_completed" |
6212 | [(parallel | |
6213 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6214 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6215 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 6216 | |
9db1d521 | 6217 | ; |
4023fb28 | 6218 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
6219 | ; |
6220 | ||
8cb66696 UW |
6221 | (define_insn "*iorqi3_zarch" |
6222 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
6223 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6224 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 6225 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6226 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6227 | "@ |
d40c829f | 6228 | or\t%0,%2 |
8cb66696 | 6229 | oill\t%0,%b2 |
fc0ea003 UW |
6230 | oi\t%S0,%b2 |
6231 | oiy\t%S0,%b2 | |
19b63d8e | 6232 | #" |
9381e3f1 WG |
6233 | [(set_attr "op_type" "RR,RI,SI,SIY,SS") |
6234 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
6235 | |
6236 | (define_insn "*iorqi3_esa" | |
6237 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6238 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6239 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6240 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6241 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6242 | "@ |
8cb66696 | 6243 | or\t%0,%2 |
fc0ea003 | 6244 | oi\t%S0,%b2 |
19b63d8e | 6245 | #" |
9381e3f1 WG |
6246 | [(set_attr "op_type" "RR,SI,SS") |
6247 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 6248 | |
19b63d8e UW |
6249 | ; |
6250 | ; Block inclusive or (OC) patterns. | |
6251 | ; | |
6252 | ||
6253 | (define_insn "*oc" | |
6254 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6255 | (ior:BLK (match_dup 0) | |
6256 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6257 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6258 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6259 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6260 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 6261 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6262 | |
6263 | (define_split | |
6264 | [(set (match_operand 0 "memory_operand" "") | |
6265 | (ior (match_dup 0) | |
6266 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6267 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6268 | "reload_completed |
6269 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6270 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6271 | [(parallel | |
6272 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
6273 | (use (match_dup 2)) | |
ae156f85 | 6274 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6275 | { |
6276 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6277 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6278 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6279 | }) | |
6280 | ||
6281 | (define_peephole2 | |
6282 | [(parallel | |
6283 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6284 | (ior:BLK (match_dup 0) | |
6285 | (match_operand:BLK 1 "memory_operand" ""))) | |
6286 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6287 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6288 | (parallel |
6289 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6290 | (ior:BLK (match_dup 3) | |
6291 | (match_operand:BLK 4 "memory_operand" ""))) | |
6292 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6293 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6294 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6295 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6296 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6297 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6298 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6299 | [(parallel | |
6300 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
6301 | (use (match_dup 8)) | |
ae156f85 | 6302 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6303 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6304 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6305 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6306 | ||
9db1d521 HP |
6307 | |
6308 | ;; | |
6309 | ;;- Xor instructions. | |
6310 | ;; | |
6311 | ||
047d35ed AS |
6312 | (define_expand "xor<mode>3" |
6313 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6314 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6315 | (match_operand:INT 2 "general_operand" ""))) | |
6316 | (clobber (reg:CC CC_REGNUM))] | |
6317 | "" | |
6318 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
6319 | ||
9db1d521 HP |
6320 | ; |
6321 | ; xordi3 instruction pattern(s). | |
6322 | ; | |
6323 | ||
4023fb28 | 6324 | (define_insn "*xordi3_cc" |
ae156f85 | 6325 | [(set (reg CC_REGNUM) |
96fd3851 | 6326 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 6327 | (match_operand:DI 2 "general_operand" "d,RT")) |
4023fb28 UW |
6328 | (const_int 0))) |
6329 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6330 | (xor:DI (match_dup 1) (match_dup 2)))] | |
6331 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6332 | "@ | |
d40c829f UW |
6333 | xgr\t%0,%2 |
6334 | xg\t%0,%2" | |
9381e3f1 WG |
6335 | [(set_attr "op_type" "RRE,RXY") |
6336 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6337 | |
6338 | (define_insn "*xordi3_cconly" | |
ae156f85 | 6339 | [(set (reg CC_REGNUM) |
96fd3851 | 6340 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 6341 | (match_operand:DI 2 "general_operand" "d,RT")) |
4023fb28 UW |
6342 | (const_int 0))) |
6343 | (clobber (match_scratch:DI 0 "=d,d"))] | |
6344 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6345 | "@ | |
d40c829f | 6346 | xgr\t%0,%2 |
c7fd8cd8 | 6347 | xg\t%0,%2" |
9381e3f1 WG |
6348 | [(set_attr "op_type" "RRE,RXY") |
6349 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6350 | |
3af8e996 | 6351 | (define_insn "*xordi3" |
ec24698e UW |
6352 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") |
6353 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
fb492564 | 6354 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) |
ec24698e | 6355 | (clobber (reg:CC CC_REGNUM))] |
3af8e996 | 6356 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6357 | "@ |
6358 | xihf\t%0,%k2 | |
6359 | xilf\t%0,%k2 | |
6360 | xgr\t%0,%2 | |
6361 | xg\t%0,%2 | |
6362 | # | |
6363 | #" | |
3af8e996 | 6364 | [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS") |
9381e3f1 WG |
6365 | (set_attr "cpu_facility" "extimm,extimm,*,*,*,*") |
6366 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6367 | |
6368 | (define_split | |
6369 | [(set (match_operand:DI 0 "s_operand" "") | |
6370 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6371 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6372 | "reload_completed" |
6373 | [(parallel | |
6374 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6375 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6376 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 6377 | |
9db1d521 HP |
6378 | ; |
6379 | ; xorsi3 instruction pattern(s). | |
6380 | ; | |
6381 | ||
4023fb28 | 6382 | (define_insn "*xorsi3_cc" |
ae156f85 | 6383 | [(set (reg CC_REGNUM) |
ec24698e UW |
6384 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
6385 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 6386 | (const_int 0))) |
ec24698e | 6387 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
6388 | (xor:SI (match_dup 1) (match_dup 2)))] |
6389 | "s390_match_ccmode(insn, CCTmode)" | |
6390 | "@ | |
ec24698e | 6391 | xilf\t%0,%o2 |
d40c829f UW |
6392 | xr\t%0,%2 |
6393 | x\t%0,%2 | |
6394 | xy\t%0,%2" | |
9381e3f1 WG |
6395 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
6396 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6397 | |
6398 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 6399 | [(set (reg CC_REGNUM) |
ec24698e UW |
6400 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
6401 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 6402 | (const_int 0))) |
ec24698e | 6403 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
6404 | "s390_match_ccmode(insn, CCTmode)" |
6405 | "@ | |
ec24698e | 6406 | xilf\t%0,%o2 |
d40c829f UW |
6407 | xr\t%0,%2 |
6408 | x\t%0,%2 | |
6409 | xy\t%0,%2" | |
9381e3f1 WG |
6410 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
6411 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6412 | |
8cb66696 | 6413 | (define_insn "*xorsi3" |
ec24698e UW |
6414 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") |
6415 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
6416 | (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6417 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6418 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6419 | "@ |
ec24698e | 6420 | xilf\t%0,%o2 |
d40c829f UW |
6421 | xr\t%0,%2 |
6422 | x\t%0,%2 | |
8cb66696 | 6423 | xy\t%0,%2 |
0dfa6c5e | 6424 | # |
19b63d8e | 6425 | #" |
9381e3f1 WG |
6426 | [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS") |
6427 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6428 | |
6429 | (define_split | |
6430 | [(set (match_operand:SI 0 "s_operand" "") | |
6431 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6432 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6433 | "reload_completed" |
6434 | [(parallel | |
6435 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6436 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6437 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 6438 | |
9db1d521 HP |
6439 | ; |
6440 | ; xorhi3 instruction pattern(s). | |
6441 | ; | |
6442 | ||
8cb66696 | 6443 | (define_insn "*xorhi3" |
ec24698e UW |
6444 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
6445 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
6446 | (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q"))) | |
ae156f85 | 6447 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6448 | "s390_logical_operator_ok_p (operands)" |
6449 | "@ | |
ec24698e | 6450 | xilf\t%0,%x2 |
8cb66696 | 6451 | xr\t%0,%2 |
0dfa6c5e | 6452 | # |
19b63d8e | 6453 | #" |
9381e3f1 WG |
6454 | [(set_attr "op_type" "RIL,RR,SI,SS") |
6455 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6456 | |
6457 | (define_split | |
6458 | [(set (match_operand:HI 0 "s_operand" "") | |
6459 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6460 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6461 | "reload_completed" |
6462 | [(parallel | |
6463 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6464 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6465 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 6466 | |
9db1d521 HP |
6467 | ; |
6468 | ; xorqi3 instruction pattern(s). | |
6469 | ; | |
6470 | ||
8cb66696 | 6471 | (define_insn "*xorqi3" |
ec24698e UW |
6472 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") |
6473 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6474 | (match_operand:QI 2 "general_operand" "Os,d,n,n,Q"))) | |
ae156f85 | 6475 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6476 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6477 | "@ |
ec24698e | 6478 | xilf\t%0,%b2 |
8cb66696 | 6479 | xr\t%0,%2 |
fc0ea003 UW |
6480 | xi\t%S0,%b2 |
6481 | xiy\t%S0,%b2 | |
19b63d8e | 6482 | #" |
9381e3f1 WG |
6483 | [(set_attr "op_type" "RIL,RR,SI,SIY,SS") |
6484 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
6485 | ||
4023fb28 | 6486 | |
19b63d8e UW |
6487 | ; |
6488 | ; Block exclusive or (XC) patterns. | |
6489 | ; | |
6490 | ||
6491 | (define_insn "*xc" | |
6492 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6493 | (xor:BLK (match_dup 0) | |
6494 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6495 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6496 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6497 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6498 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 6499 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6500 | |
6501 | (define_split | |
6502 | [(set (match_operand 0 "memory_operand" "") | |
6503 | (xor (match_dup 0) | |
6504 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6505 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6506 | "reload_completed |
6507 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6508 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6509 | [(parallel | |
6510 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
6511 | (use (match_dup 2)) | |
ae156f85 | 6512 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6513 | { |
6514 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6515 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6516 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6517 | }) | |
6518 | ||
6519 | (define_peephole2 | |
6520 | [(parallel | |
6521 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6522 | (xor:BLK (match_dup 0) | |
6523 | (match_operand:BLK 1 "memory_operand" ""))) | |
6524 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6525 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6526 | (parallel |
6527 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6528 | (xor:BLK (match_dup 3) | |
6529 | (match_operand:BLK 4 "memory_operand" ""))) | |
6530 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6531 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6532 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6533 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6534 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6535 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6536 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6537 | [(parallel | |
6538 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
6539 | (use (match_dup 8)) | |
ae156f85 | 6540 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6541 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6542 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6543 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6544 | ||
6545 | ; | |
6546 | ; Block xor (XC) patterns with src == dest. | |
6547 | ; | |
6548 | ||
6549 | (define_insn "*xc_zero" | |
6550 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6551 | (const_int 0)) | |
6552 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 6553 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6554 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 6555 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 6556 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6557 | |
6558 | (define_peephole2 | |
6559 | [(parallel | |
6560 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6561 | (const_int 0)) | |
6562 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 6563 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6564 | (parallel |
6565 | [(set (match_operand:BLK 2 "memory_operand" "") | |
6566 | (const_int 0)) | |
6567 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 6568 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6569 | "s390_offset_p (operands[0], operands[2], operands[1]) |
6570 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
6571 | [(parallel | |
6572 | [(set (match_dup 4) (const_int 0)) | |
6573 | (use (match_dup 5)) | |
ae156f85 | 6574 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6575 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6576 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
6577 | ||
9db1d521 HP |
6578 | |
6579 | ;; | |
6580 | ;;- Negate instructions. | |
6581 | ;; | |
6582 | ||
6583 | ; | |
9a91a21f | 6584 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
6585 | ; |
6586 | ||
9a91a21f | 6587 | (define_expand "neg<mode>2" |
9db1d521 | 6588 | [(parallel |
9a91a21f AS |
6589 | [(set (match_operand:DSI 0 "register_operand" "=d") |
6590 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 6591 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6592 | "" |
6593 | "") | |
6594 | ||
26a89301 | 6595 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 6596 | [(set (reg CC_REGNUM) |
26a89301 UW |
6597 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6598 | (match_operand:SI 1 "register_operand" "d") 0) | |
6599 | (const_int 32)) (const_int 32))) | |
6600 | (const_int 0))) | |
6601 | (set (match_operand:DI 0 "register_operand" "=d") | |
6602 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
6603 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6604 | "lcgfr\t%0,%1" | |
729e750f WG |
6605 | [(set_attr "op_type" "RRE") |
6606 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 6607 | |
26a89301 UW |
6608 | (define_insn "*negdi2_sign" |
6609 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6610 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 6611 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6612 | "TARGET_64BIT" |
6613 | "lcgfr\t%0,%1" | |
729e750f WG |
6614 | [(set_attr "op_type" "RRE") |
6615 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6616 | |
43a09b63 | 6617 | ; lcr, lcgr |
9a91a21f | 6618 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 6619 | [(set (reg CC_REGNUM) |
9a91a21f | 6620 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6621 | (const_int 0))) |
9a91a21f AS |
6622 | (set (match_operand:GPR 0 "register_operand" "=d") |
6623 | (neg:GPR (match_dup 1)))] | |
6624 | "s390_match_ccmode (insn, CCAmode)" | |
6625 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6626 | [(set_attr "op_type" "RR<E>") |
6627 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6628 | |
6629 | ; lcr, lcgr | |
9a91a21f | 6630 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 6631 | [(set (reg CC_REGNUM) |
9a91a21f | 6632 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6633 | (const_int 0))) |
9a91a21f AS |
6634 | (clobber (match_scratch:GPR 0 "=d"))] |
6635 | "s390_match_ccmode (insn, CCAmode)" | |
6636 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6637 | [(set_attr "op_type" "RR<E>") |
6638 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6639 | |
6640 | ; lcr, lcgr | |
9a91a21f AS |
6641 | (define_insn "*neg<mode>2" |
6642 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6643 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 6644 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
6645 | "" |
6646 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6647 | [(set_attr "op_type" "RR<E>") |
6648 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 6649 | |
26a89301 | 6650 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
6651 | [(set (match_operand:DI 0 "register_operand" "=d") |
6652 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 6653 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6654 | "!TARGET_64BIT" |
26a89301 UW |
6655 | "#" |
6656 | "&& reload_completed" | |
6657 | [(parallel | |
6658 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 6659 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 6660 | (parallel |
ae156f85 | 6661 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
6662 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
6663 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
6664 | (set (pc) | |
ae156f85 | 6665 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
6666 | (pc) |
6667 | (label_ref (match_dup 6)))) | |
6668 | (parallel | |
6669 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 6670 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
6671 | (match_dup 6)] |
6672 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
6673 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
6674 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
6675 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
6676 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 6677 | |
9db1d521 | 6678 | ; |
f5905b37 | 6679 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
6680 | ; |
6681 | ||
f5905b37 | 6682 | (define_expand "neg<mode>2" |
9db1d521 | 6683 | [(parallel |
7b6baae1 AK |
6684 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6685 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 6686 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6687 | "TARGET_HARD_FLOAT" |
6688 | "") | |
6689 | ||
43a09b63 | 6690 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 6691 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 6692 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6693 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
6694 | (match_operand:BFP 2 "const0_operand" ""))) | |
6695 | (set (match_operand:BFP 0 "register_operand" "=f") | |
6696 | (neg:BFP (match_dup 1)))] | |
142cd70f | 6697 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6698 | "lc<xde>br\t%0,%1" |
26a89301 | 6699 | [(set_attr "op_type" "RRE") |
f5905b37 | 6700 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6701 | |
6702 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 6703 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 6704 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6705 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
6706 | (match_operand:BFP 2 "const0_operand" ""))) | |
6707 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 6708 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6709 | "lc<xde>br\t%0,%1" |
26a89301 | 6710 | [(set_attr "op_type" "RRE") |
f5905b37 | 6711 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 6712 | |
85dae55a AK |
6713 | ; lcdfr |
6714 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
6715 | [(set (match_operand:FP 0 "register_operand" "=f") |
6716 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 6717 | "TARGET_DFP" |
85dae55a AK |
6718 | "lcdfr\t%0,%1" |
6719 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 6720 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 6721 | |
43a09b63 | 6722 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 6723 | (define_insn "*neg<mode>2" |
7b6baae1 AK |
6724 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6725 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 6726 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6727 | "TARGET_HARD_FLOAT" |
f61a2c7d | 6728 | "lc<xde>br\t%0,%1" |
077dab3b | 6729 | [(set_attr "op_type" "RRE") |
f5905b37 | 6730 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6731 | |
9db1d521 HP |
6732 | |
6733 | ;; | |
6734 | ;;- Absolute value instructions. | |
6735 | ;; | |
6736 | ||
6737 | ; | |
9a91a21f | 6738 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
6739 | ; |
6740 | ||
26a89301 | 6741 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 6742 | [(set (reg CC_REGNUM) |
26a89301 UW |
6743 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6744 | (match_operand:SI 1 "register_operand" "d") 0) | |
6745 | (const_int 32)) (const_int 32))) | |
6746 | (const_int 0))) | |
6747 | (set (match_operand:DI 0 "register_operand" "=d") | |
6748 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
6749 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6750 | "lpgfr\t%0,%1" | |
729e750f WG |
6751 | [(set_attr "op_type" "RRE") |
6752 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
6753 | |
6754 | (define_insn "*absdi2_sign" | |
6755 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6756 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 6757 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6758 | "TARGET_64BIT" |
6759 | "lpgfr\t%0,%1" | |
729e750f WG |
6760 | [(set_attr "op_type" "RRE") |
6761 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6762 | |
43a09b63 | 6763 | ; lpr, lpgr |
9a91a21f | 6764 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 6765 | [(set (reg CC_REGNUM) |
9a91a21f | 6766 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 6767 | (const_int 0))) |
9a91a21f AS |
6768 | (set (match_operand:GPR 0 "register_operand" "=d") |
6769 | (abs:GPR (match_dup 1)))] | |
26a89301 | 6770 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 6771 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
6772 | [(set_attr "op_type" "RR<E>") |
6773 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 6774 | |
9381e3f1 | 6775 | ; lpr, lpgr |
9a91a21f | 6776 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 6777 | [(set (reg CC_REGNUM) |
9a91a21f | 6778 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6779 | (const_int 0))) |
9a91a21f | 6780 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6781 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 6782 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
6783 | [(set_attr "op_type" "RR<E>") |
6784 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
6785 | |
6786 | ; lpr, lpgr | |
9a91a21f AS |
6787 | (define_insn "abs<mode>2" |
6788 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6789 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 6790 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6791 | "" |
9a91a21f | 6792 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
6793 | [(set_attr "op_type" "RR<E>") |
6794 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 6795 | |
9db1d521 | 6796 | ; |
f5905b37 | 6797 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
6798 | ; |
6799 | ||
f5905b37 | 6800 | (define_expand "abs<mode>2" |
9db1d521 | 6801 | [(parallel |
7b6baae1 AK |
6802 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6803 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 6804 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6805 | "TARGET_HARD_FLOAT" |
6806 | "") | |
6807 | ||
43a09b63 | 6808 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 6809 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 6810 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6811 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
6812 | (match_operand:BFP 2 "const0_operand" ""))) | |
6813 | (set (match_operand:BFP 0 "register_operand" "=f") | |
6814 | (abs:BFP (match_dup 1)))] | |
142cd70f | 6815 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6816 | "lp<xde>br\t%0,%1" |
26a89301 | 6817 | [(set_attr "op_type" "RRE") |
f5905b37 | 6818 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6819 | |
6820 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 6821 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 6822 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6823 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
6824 | (match_operand:BFP 2 "const0_operand" ""))) | |
6825 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 6826 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6827 | "lp<xde>br\t%0,%1" |
26a89301 | 6828 | [(set_attr "op_type" "RRE") |
f5905b37 | 6829 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 6830 | |
85dae55a AK |
6831 | ; lpdfr |
6832 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
6833 | [(set (match_operand:FP 0 "register_operand" "=f") |
6834 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 6835 | "TARGET_DFP" |
85dae55a AK |
6836 | "lpdfr\t%0,%1" |
6837 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 6838 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 6839 | |
43a09b63 | 6840 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 6841 | (define_insn "*abs<mode>2" |
7b6baae1 AK |
6842 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6843 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 6844 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6845 | "TARGET_HARD_FLOAT" |
f61a2c7d | 6846 | "lp<xde>br\t%0,%1" |
077dab3b | 6847 | [(set_attr "op_type" "RRE") |
f5905b37 | 6848 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6849 | |
9db1d521 | 6850 | |
3ef093a8 AK |
6851 | ;; |
6852 | ;;- Negated absolute value instructions | |
6853 | ;; | |
6854 | ||
6855 | ; | |
6856 | ; Integer | |
6857 | ; | |
6858 | ||
26a89301 | 6859 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 6860 | [(set (reg CC_REGNUM) |
26a89301 UW |
6861 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6862 | (match_operand:SI 1 "register_operand" "d") 0) | |
6863 | (const_int 32)) (const_int 32)))) | |
6864 | (const_int 0))) | |
6865 | (set (match_operand:DI 0 "register_operand" "=d") | |
6866 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6867 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6868 | "lngfr\t%0,%1" | |
729e750f WG |
6869 | [(set_attr "op_type" "RRE") |
6870 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 6871 | |
26a89301 UW |
6872 | (define_insn "*negabsdi2_sign" |
6873 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6874 | (neg:DI (abs:DI (sign_extend:DI | |
6875 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 6876 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6877 | "TARGET_64BIT" |
6878 | "lngfr\t%0,%1" | |
729e750f WG |
6879 | [(set_attr "op_type" "RRE") |
6880 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 6881 | |
43a09b63 | 6882 | ; lnr, lngr |
9a91a21f | 6883 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6884 | [(set (reg CC_REGNUM) |
9a91a21f | 6885 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6886 | (const_int 0))) |
9a91a21f AS |
6887 | (set (match_operand:GPR 0 "register_operand" "=d") |
6888 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 6889 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 6890 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
6891 | [(set_attr "op_type" "RR<E>") |
6892 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
6893 | |
6894 | ; lnr, lngr | |
9a91a21f | 6895 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6896 | [(set (reg CC_REGNUM) |
9a91a21f | 6897 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6898 | (const_int 0))) |
9a91a21f | 6899 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6900 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 6901 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
6902 | [(set_attr "op_type" "RR<E>") |
6903 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
6904 | |
6905 | ; lnr, lngr | |
9a91a21f AS |
6906 | (define_insn "*negabs<mode>2" |
6907 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6908 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 6909 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 6910 | "" |
9a91a21f | 6911 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
6912 | [(set_attr "op_type" "RR<E>") |
6913 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6914 | |
3ef093a8 AK |
6915 | ; |
6916 | ; Floating point | |
6917 | ; | |
6918 | ||
43a09b63 | 6919 | ; lnxbr, lndbr, lnebr |
f5905b37 | 6920 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6921 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6922 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
6923 | (match_operand:BFP 2 "const0_operand" ""))) | |
6924 | (set (match_operand:BFP 0 "register_operand" "=f") | |
6925 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 6926 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6927 | "ln<xde>br\t%0,%1" |
26a89301 | 6928 | [(set_attr "op_type" "RRE") |
f5905b37 | 6929 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6930 | |
6931 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 6932 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6933 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6934 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
6935 | (match_operand:BFP 2 "const0_operand" ""))) | |
6936 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 6937 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6938 | "ln<xde>br\t%0,%1" |
26a89301 | 6939 | [(set_attr "op_type" "RRE") |
f5905b37 | 6940 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 6941 | |
85dae55a AK |
6942 | ; lndfr |
6943 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
6944 | [(set (match_operand:FP 0 "register_operand" "=f") |
6945 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 6946 | "TARGET_DFP" |
85dae55a AK |
6947 | "lndfr\t%0,%1" |
6948 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 6949 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 6950 | |
43a09b63 | 6951 | ; lnxbr, lndbr, lnebr |
f5905b37 | 6952 | (define_insn "*negabs<mode>2" |
7b6baae1 AK |
6953 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6954 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))) | |
ae156f85 | 6955 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6956 | "TARGET_HARD_FLOAT" |
f61a2c7d | 6957 | "ln<xde>br\t%0,%1" |
26a89301 | 6958 | [(set_attr "op_type" "RRE") |
f5905b37 | 6959 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6960 | |
85dae55a AK |
6961 | ;; |
6962 | ;;- Copy sign instructions | |
6963 | ;; | |
6964 | ||
6965 | ; cpsdr | |
6966 | (define_insn "copysign<mode>3" | |
609e7e80 AK |
6967 | [(set (match_operand:FP 0 "register_operand" "=f") |
6968 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
9381e3f1 | 6969 | (match_operand:FP 2 "register_operand" "f")] |
85dae55a | 6970 | UNSPEC_COPYSIGN))] |
fb068247 | 6971 | "TARGET_DFP" |
85dae55a AK |
6972 | "cpsdr\t%0,%2,%1" |
6973 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 6974 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 6975 | |
4023fb28 UW |
6976 | ;; |
6977 | ;;- Square root instructions. | |
6978 | ;; | |
6979 | ||
6980 | ; | |
f5905b37 | 6981 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
6982 | ; |
6983 | ||
9381e3f1 | 6984 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 6985 | (define_insn "sqrt<mode>2" |
7b6baae1 AK |
6986 | [(set (match_operand:BFP 0 "register_operand" "=f,f") |
6987 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 6988 | "TARGET_HARD_FLOAT" |
4023fb28 | 6989 | "@ |
f61a2c7d AK |
6990 | sq<xde>br\t%0,%1 |
6991 | sq<xde>b\t%0,%1" | |
a036c6f7 | 6992 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 6993 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 6994 | |
9db1d521 HP |
6995 | |
6996 | ;; | |
6997 | ;;- One complement instructions. | |
6998 | ;; | |
6999 | ||
7000 | ; | |
342cf42b | 7001 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 7002 | ; |
c7453384 | 7003 | |
342cf42b | 7004 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 7005 | [(parallel |
342cf42b AS |
7006 | [(set (match_operand:INT 0 "register_operand" "") |
7007 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
7008 | (const_int -1))) | |
ae156f85 | 7009 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 7010 | "" |
4023fb28 | 7011 | "") |
9db1d521 HP |
7012 | |
7013 | ||
ec24698e UW |
7014 | ;; |
7015 | ;; Find leftmost bit instructions. | |
7016 | ;; | |
7017 | ||
7018 | (define_expand "clzdi2" | |
7019 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7020 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
7021 | "TARGET_EXTIMM && TARGET_64BIT" | |
7022 | { | |
7023 | rtx insn, clz_equal; | |
7024 | rtx wide_reg = gen_reg_rtx (TImode); | |
7025 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
7026 | ||
7027 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
7028 | ||
7029 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
7030 | ||
9381e3f1 | 7031 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 7032 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
7033 | |
7034 | DONE; | |
7035 | }) | |
7036 | ||
7037 | (define_insn "clztidi2" | |
7038 | [(set (match_operand:TI 0 "register_operand" "=d") | |
7039 | (ior:TI | |
9381e3f1 WG |
7040 | (ashift:TI |
7041 | (zero_extend:TI | |
ec24698e UW |
7042 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
7043 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
7044 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 7045 | |
ec24698e UW |
7046 | (const_int 64)) |
7047 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
7048 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 7049 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e UW |
7050 | == (unsigned HOST_WIDE_INT) 1 << 63 |
7051 | && TARGET_EXTIMM && TARGET_64BIT" | |
7052 | "flogr\t%0,%1" | |
7053 | [(set_attr "op_type" "RRE")]) | |
7054 | ||
7055 | ||
9db1d521 HP |
7056 | ;; |
7057 | ;;- Rotate instructions. | |
7058 | ;; | |
7059 | ||
7060 | ; | |
9a91a21f | 7061 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
7062 | ; |
7063 | ||
43a09b63 | 7064 | ; rll, rllg |
9a91a21f AS |
7065 | (define_insn "rotl<mode>3" |
7066 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7067 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 7068 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 7069 | "TARGET_CPU_ZARCH" |
9a91a21f | 7070 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 7071 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
7072 | (set_attr "atype" "reg") |
7073 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7074 | |
43a09b63 | 7075 | ; rll, rllg |
4989e88a AK |
7076 | (define_insn "*rotl<mode>3_and" |
7077 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7078 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7079 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7080 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7081 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
7082 | "rll<g>\t%0,%1,%Y2" | |
7083 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
7084 | (set_attr "atype" "reg") |
7085 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7086 | |
9db1d521 HP |
7087 | |
7088 | ;; | |
f337b930 | 7089 | ;;- Shift instructions. |
9db1d521 | 7090 | ;; |
9db1d521 HP |
7091 | |
7092 | ; | |
1b48c8cc | 7093 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
9db1d521 HP |
7094 | ; |
7095 | ||
1b48c8cc AS |
7096 | (define_expand "<shift><mode>3" |
7097 | [(set (match_operand:DSI 0 "register_operand" "") | |
7098 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
7099 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
7100 | "" |
7101 | "") | |
7102 | ||
43a09b63 | 7103 | ; sldl, srdl |
f337b930 | 7104 | (define_insn "*<shift>di3_31" |
ac32b25e | 7105 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 7106 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7107 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9db1d521 | 7108 | "!TARGET_64BIT" |
f337b930 | 7109 | "s<lr>dl\t%0,%Y2" |
077dab3b HP |
7110 | [(set_attr "op_type" "RS") |
7111 | (set_attr "atype" "reg")]) | |
9db1d521 | 7112 | |
43a09b63 | 7113 | ; sll, srl, sllg, srlg |
1b48c8cc AS |
7114 | (define_insn "*<shift><mode>3" |
7115 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7116 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7117 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] | |
7118 | "" | |
7119 | "s<lr>l<g>\t%0,<1>%Y2" | |
7120 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7121 | (set_attr "atype" "reg") |
7122 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7123 | |
43a09b63 | 7124 | ; sldl, srdl |
4989e88a AK |
7125 | (define_insn "*<shift>di3_31_and" |
7126 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7127 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7128 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7129 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7130 | "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
7131 | "s<lr>dl\t%0,%Y2" | |
7132 | [(set_attr "op_type" "RS") | |
7133 | (set_attr "atype" "reg")]) | |
7134 | ||
43a09b63 | 7135 | ; sll, srl, sllg, srlg |
1b48c8cc AS |
7136 | (define_insn "*<shift><mode>3_and" |
7137 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7138 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7139 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7140 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7141 | "(INTVAL (operands[3]) & 63) == 63" | |
7142 | "s<lr>l<g>\t%0,<1>%Y2" | |
7143 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7144 | (set_attr "atype" "reg") |
7145 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7146 | |
9db1d521 | 7147 | ; |
1b48c8cc | 7148 | ; ashr(di|si)3 instruction pattern(s). |
9db1d521 HP |
7149 | ; |
7150 | ||
1b48c8cc | 7151 | (define_expand "ashr<mode>3" |
9db1d521 | 7152 | [(parallel |
1b48c8cc AS |
7153 | [(set (match_operand:DSI 0 "register_operand" "") |
7154 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
7155 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 7156 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7157 | "" |
7158 | "") | |
7159 | ||
ecbe845e | 7160 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 7161 | [(set (reg CC_REGNUM) |
ac32b25e | 7162 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7163 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7164 | (const_int 0))) |
ac32b25e | 7165 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
7166 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
7167 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 7168 | "srda\t%0,%Y2" |
077dab3b HP |
7169 | [(set_attr "op_type" "RS") |
7170 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
7171 | |
7172 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 7173 | [(set (reg CC_REGNUM) |
ac32b25e | 7174 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7175 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7176 | (const_int 0))) |
ac32b25e | 7177 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 7178 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7179 | "srda\t%0,%Y2" |
077dab3b HP |
7180 | [(set_attr "op_type" "RS") |
7181 | (set_attr "atype" "reg")]) | |
ecbe845e | 7182 | |
9db1d521 | 7183 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
7184 | [(set (match_operand:DI 0 "register_operand" "=d") |
7185 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 7186 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 7187 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 7188 | "!TARGET_64BIT" |
ac32b25e | 7189 | "srda\t%0,%Y2" |
077dab3b HP |
7190 | [(set_attr "op_type" "RS") |
7191 | (set_attr "atype" "reg")]) | |
c7453384 | 7192 | |
43a09b63 | 7193 | ; sra, srag |
1b48c8cc | 7194 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 7195 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
7196 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
7197 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
ecbe845e | 7198 | (const_int 0))) |
1b48c8cc AS |
7199 | (set (match_operand:GPR 0 "register_operand" "=d") |
7200 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] | |
7201 | "s390_match_ccmode(insn, CCSmode)" | |
7202 | "sra<g>\t%0,<1>%Y2" | |
7203 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7204 | (set_attr "atype" "reg") |
7205 | (set_attr "z10prop" "z10_super_E1")]) | |
ecbe845e | 7206 | |
43a09b63 | 7207 | ; sra, srag |
1b48c8cc | 7208 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 7209 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
7210 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
7211 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
ecbe845e | 7212 | (const_int 0))) |
1b48c8cc AS |
7213 | (clobber (match_scratch:GPR 0 "=d"))] |
7214 | "s390_match_ccmode(insn, CCSmode)" | |
7215 | "sra<g>\t%0,<1>%Y2" | |
7216 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7217 | (set_attr "atype" "reg") |
7218 | (set_attr "z10prop" "z10_super_E1")]) | |
ecbe845e | 7219 | |
43a09b63 | 7220 | ; sra, srag |
1b48c8cc AS |
7221 | (define_insn "*ashr<mode>3" |
7222 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7223 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7224 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) | |
ae156f85 | 7225 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc AS |
7226 | "" |
7227 | "sra<g>\t%0,<1>%Y2" | |
7228 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7229 | (set_attr "atype" "reg") |
7230 | (set_attr "z10prop" "z10_super_E1")]) | |
077dab3b | 7231 | |
9db1d521 | 7232 | |
4989e88a AK |
7233 | ; shift pattern with implicit ANDs |
7234 | ||
7235 | (define_insn "*ashrdi3_cc_31_and" | |
7236 | [(set (reg CC_REGNUM) | |
7237 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7238 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7239 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7240 | (const_int 0))) | |
7241 | (set (match_operand:DI 0 "register_operand" "=d") | |
7242 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
7243 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
7244 | && (INTVAL (operands[3]) & 63) == 63" | |
7245 | "srda\t%0,%Y2" | |
7246 | [(set_attr "op_type" "RS") | |
7247 | (set_attr "atype" "reg")]) | |
7248 | ||
7249 | (define_insn "*ashrdi3_cconly_31_and" | |
7250 | [(set (reg CC_REGNUM) | |
7251 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7252 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7253 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7254 | (const_int 0))) | |
7255 | (clobber (match_scratch:DI 0 "=d"))] | |
7256 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
7257 | && (INTVAL (operands[3]) & 63) == 63" | |
7258 | "srda\t%0,%Y2" | |
7259 | [(set_attr "op_type" "RS") | |
7260 | (set_attr "atype" "reg")]) | |
7261 | ||
7262 | (define_insn "*ashrdi3_31_and" | |
7263 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7264 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7265 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7266 | (match_operand:SI 3 "const_int_operand" "n")))) | |
7267 | (clobber (reg:CC CC_REGNUM))] | |
7268 | "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
7269 | "srda\t%0,%Y2" | |
7270 | [(set_attr "op_type" "RS") | |
7271 | (set_attr "atype" "reg")]) | |
7272 | ||
43a09b63 | 7273 | ; sra, srag |
1b48c8cc | 7274 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 7275 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
7276 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
7277 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7278 | (match_operand:SI 3 "const_int_operand" "n"))) | |
4989e88a | 7279 | (const_int 0))) |
1b48c8cc AS |
7280 | (set (match_operand:GPR 0 "register_operand" "=d") |
7281 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
4989e88a | 7282 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
1b48c8cc AS |
7283 | "sra<g>\t%0,<1>%Y2" |
7284 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7285 | (set_attr "atype" "reg") |
7286 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7287 | |
43a09b63 | 7288 | ; sra, srag |
1b48c8cc | 7289 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 7290 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
7291 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
7292 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7293 | (match_operand:SI 3 "const_int_operand" "n"))) | |
4989e88a | 7294 | (const_int 0))) |
1b48c8cc | 7295 | (clobber (match_scratch:GPR 0 "=d"))] |
4989e88a | 7296 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
1b48c8cc AS |
7297 | "sra<g>\t%0,<1>%Y2" |
7298 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7299 | (set_attr "atype" "reg") |
7300 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7301 | |
43a09b63 | 7302 | ; sra, srag |
1b48c8cc AS |
7303 | (define_insn "*ashr<mode>3_and" |
7304 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7305 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7306 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7307 | (match_operand:SI 3 "const_int_operand" "n")))) | |
4989e88a AK |
7308 | (clobber (reg:CC CC_REGNUM))] |
7309 | "(INTVAL (operands[3]) & 63) == 63" | |
1b48c8cc AS |
7310 | "sra<g>\t%0,<1>%Y2" |
7311 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7312 | (set_attr "atype" "reg") |
7313 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7314 | |
9db1d521 | 7315 | |
9db1d521 HP |
7316 | ;; |
7317 | ;; Branch instruction patterns. | |
7318 | ;; | |
7319 | ||
f90b7a5a | 7320 | (define_expand "cbranch<mode>4" |
fa77b251 | 7321 | [(set (pc) |
f90b7a5a PB |
7322 | (if_then_else (match_operator 0 "comparison_operator" |
7323 | [(match_operand:GPR 1 "register_operand" "") | |
7324 | (match_operand:GPR 2 "general_operand" "")]) | |
7325 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 7326 | (pc)))] |
ba956982 | 7327 | "" |
f90b7a5a PB |
7328 | "s390_emit_jump (operands[3], |
7329 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7330 | DONE;") | |
7331 | ||
7332 | (define_expand "cbranch<mode>4" | |
7333 | [(set (pc) | |
7334 | (if_then_else (match_operator 0 "comparison_operator" | |
7335 | [(match_operand:FP 1 "register_operand" "") | |
7336 | (match_operand:FP 2 "general_operand" "")]) | |
7337 | (label_ref (match_operand 3 "" "")) | |
7338 | (pc)))] | |
7339 | "TARGET_HARD_FLOAT" | |
7340 | "s390_emit_jump (operands[3], | |
7341 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7342 | DONE;") | |
7343 | ||
7344 | (define_expand "cbranchcc4" | |
7345 | [(set (pc) | |
7346 | (if_then_else (match_operator 0 "s390_eqne_operator" | |
7347 | [(match_operand 1 "cc_reg_operand" "") | |
7348 | (match_operand 2 "const0_operand" "")]) | |
7349 | (label_ref (match_operand 3 "" "")) | |
7350 | (pc)))] | |
7351 | "TARGET_HARD_FLOAT" | |
7352 | "s390_emit_jump (operands[3], | |
7353 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7354 | DONE;") | |
7355 | ||
ba956982 | 7356 | |
9db1d521 HP |
7357 | |
7358 | ;; | |
7359 | ;;- Conditional jump instructions. | |
7360 | ;; | |
7361 | ||
6590e19a UW |
7362 | (define_insn "*cjump_64" |
7363 | [(set (pc) | |
7364 | (if_then_else | |
ae156f85 | 7365 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7366 | (label_ref (match_operand 0 "" "")) |
7367 | (pc)))] | |
7368 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7369 | { |
13e58269 | 7370 | if (get_attr_length (insn) == 4) |
d40c829f | 7371 | return "j%C1\t%l0"; |
6590e19a | 7372 | else |
d40c829f | 7373 | return "jg%C1\t%l0"; |
6590e19a UW |
7374 | } |
7375 | [(set_attr "op_type" "RI") | |
7376 | (set_attr "type" "branch") | |
7377 | (set (attr "length") | |
7378 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7379 | (const_int 4) (const_int 6)))]) | |
7380 | ||
7381 | (define_insn "*cjump_31" | |
7382 | [(set (pc) | |
7383 | (if_then_else | |
ae156f85 | 7384 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7385 | (label_ref (match_operand 0 "" "")) |
7386 | (pc)))] | |
7387 | "!TARGET_CPU_ZARCH" | |
7388 | { | |
8d933e31 AS |
7389 | gcc_assert (get_attr_length (insn) == 4); |
7390 | return "j%C1\t%l0"; | |
10bbf137 | 7391 | } |
9db1d521 | 7392 | [(set_attr "op_type" "RI") |
077dab3b | 7393 | (set_attr "type" "branch") |
13e58269 | 7394 | (set (attr "length") |
6590e19a UW |
7395 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7396 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7397 | (const_int 4) (const_int 6)) | |
7398 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7399 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7400 | |
f314b9b1 | 7401 | (define_insn "*cjump_long" |
6590e19a UW |
7402 | [(set (pc) |
7403 | (if_then_else | |
ae156f85 | 7404 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 7405 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 7406 | (pc)))] |
9db1d521 | 7407 | "" |
f314b9b1 UW |
7408 | { |
7409 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7410 | return "b%C1r\t%0"; |
f314b9b1 | 7411 | else |
d40c829f | 7412 | return "b%C1\t%a0"; |
10bbf137 | 7413 | } |
c7453384 | 7414 | [(set (attr "op_type") |
f314b9b1 UW |
7415 | (if_then_else (match_operand 0 "register_operand" "") |
7416 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 7417 | (set_attr "type" "branch") |
077dab3b | 7418 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7419 | |
7420 | ||
7421 | ;; | |
7422 | ;;- Negated conditional jump instructions. | |
7423 | ;; | |
7424 | ||
6590e19a UW |
7425 | (define_insn "*icjump_64" |
7426 | [(set (pc) | |
7427 | (if_then_else | |
ae156f85 | 7428 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7429 | (pc) |
7430 | (label_ref (match_operand 0 "" ""))))] | |
7431 | "TARGET_CPU_ZARCH" | |
c7453384 | 7432 | { |
13e58269 | 7433 | if (get_attr_length (insn) == 4) |
d40c829f | 7434 | return "j%D1\t%l0"; |
6590e19a | 7435 | else |
d40c829f | 7436 | return "jg%D1\t%l0"; |
6590e19a UW |
7437 | } |
7438 | [(set_attr "op_type" "RI") | |
7439 | (set_attr "type" "branch") | |
7440 | (set (attr "length") | |
7441 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7442 | (const_int 4) (const_int 6)))]) | |
7443 | ||
7444 | (define_insn "*icjump_31" | |
7445 | [(set (pc) | |
7446 | (if_then_else | |
ae156f85 | 7447 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7448 | (pc) |
7449 | (label_ref (match_operand 0 "" ""))))] | |
7450 | "!TARGET_CPU_ZARCH" | |
7451 | { | |
8d933e31 AS |
7452 | gcc_assert (get_attr_length (insn) == 4); |
7453 | return "j%D1\t%l0"; | |
10bbf137 | 7454 | } |
9db1d521 | 7455 | [(set_attr "op_type" "RI") |
077dab3b | 7456 | (set_attr "type" "branch") |
13e58269 | 7457 | (set (attr "length") |
6590e19a UW |
7458 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7459 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7460 | (const_int 4) (const_int 6)) | |
7461 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7462 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7463 | |
f314b9b1 | 7464 | (define_insn "*icjump_long" |
6590e19a UW |
7465 | [(set (pc) |
7466 | (if_then_else | |
ae156f85 | 7467 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 7468 | (pc) |
4fe6dea8 | 7469 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 7470 | "" |
f314b9b1 UW |
7471 | { |
7472 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7473 | return "b%D1r\t%0"; |
f314b9b1 | 7474 | else |
d40c829f | 7475 | return "b%D1\t%a0"; |
10bbf137 | 7476 | } |
c7453384 | 7477 | [(set (attr "op_type") |
f314b9b1 UW |
7478 | (if_then_else (match_operand 0 "register_operand" "") |
7479 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7480 | (set_attr "type" "branch") |
7481 | (set_attr "atype" "agen")]) | |
9db1d521 | 7482 | |
4456530d HP |
7483 | ;; |
7484 | ;;- Trap instructions. | |
7485 | ;; | |
7486 | ||
7487 | (define_insn "trap" | |
7488 | [(trap_if (const_int 1) (const_int 0))] | |
7489 | "" | |
d40c829f | 7490 | "j\t.+2" |
6590e19a | 7491 | [(set_attr "op_type" "RI") |
077dab3b | 7492 | (set_attr "type" "branch")]) |
4456530d | 7493 | |
f90b7a5a PB |
7494 | (define_expand "ctrap<mode>4" |
7495 | [(trap_if (match_operator 0 "comparison_operator" | |
7496 | [(match_operand:GPR 1 "register_operand" "") | |
7497 | (match_operand:GPR 2 "general_operand" "")]) | |
7498 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 7499 | "" |
f90b7a5a PB |
7500 | { |
7501 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
7502 | operands[1], operands[2]); | |
7503 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
7504 | DONE; | |
7505 | }) | |
7506 | ||
7507 | (define_expand "ctrap<mode>4" | |
7508 | [(trap_if (match_operator 0 "comparison_operator" | |
7509 | [(match_operand:FP 1 "register_operand" "") | |
7510 | (match_operand:FP 2 "general_operand" "")]) | |
7511 | (match_operand 3 "const0_operand" ""))] | |
7512 | "" | |
7513 | { | |
7514 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
7515 | operands[1], operands[2]); | |
7516 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
7517 | DONE; | |
7518 | }) | |
4456530d | 7519 | |
f90b7a5a PB |
7520 | (define_insn "condtrap" |
7521 | [(trap_if (match_operator 0 "s390_comparison" | |
7522 | [(match_operand 1 "cc_reg_operand" "c") | |
7523 | (const_int 0)]) | |
4456530d HP |
7524 | (const_int 0))] |
7525 | "" | |
d40c829f | 7526 | "j%C0\t.+2"; |
077dab3b HP |
7527 | [(set_attr "op_type" "RI") |
7528 | (set_attr "type" "branch")]) | |
9db1d521 | 7529 | |
963fc8d0 AK |
7530 | ; crt, cgrt, cit, cgit |
7531 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
7532 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
7533 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7534 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
7535 | (const_int 0))] | |
7536 | "TARGET_Z10" | |
7537 | "@ | |
7538 | c<g>rt%C0\t%1,%2 | |
7539 | c<g>it%C0\t%1,%h2" | |
7540 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7541 | (set_attr "type" "branch") |
729e750f | 7542 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 AK |
7543 | |
7544 | ; clrt, clgrt, clfit, clgit | |
7545 | (define_insn "*cmp_and_trap_unsigned_int<mode>" | |
7546 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
7547 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7548 | (match_operand:GPR 2 "nonmemory_operand" "d,D")]) | |
7549 | (const_int 0))] | |
7550 | "TARGET_Z10" | |
7551 | "@ | |
7552 | cl<g>rt%C0\t%1,%2 | |
7553 | cl<gf>it%C0\t%1,%x2" | |
7554 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7555 | (set_attr "type" "branch") |
729e750f | 7556 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 7557 | |
9db1d521 | 7558 | ;; |
0a3bdf9d | 7559 | ;;- Loop instructions. |
9db1d521 | 7560 | ;; |
0a3bdf9d UW |
7561 | ;; This is all complicated by the fact that since this is a jump insn |
7562 | ;; we must handle our own output reloads. | |
c7453384 | 7563 | |
0a3bdf9d UW |
7564 | (define_expand "doloop_end" |
7565 | [(use (match_operand 0 "" "")) ; loop pseudo | |
7566 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
7567 | (use (match_operand 2 "" "")) ; max iterations | |
7568 | (use (match_operand 3 "" "")) ; loop level | |
7569 | (use (match_operand 4 "" ""))] ; label | |
7570 | "" | |
0a3bdf9d | 7571 | { |
6590e19a UW |
7572 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
7573 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
7574 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
7575 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
7576 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
7577 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
7578 | else | |
7579 | FAIL; | |
7580 | ||
7581 | DONE; | |
10bbf137 | 7582 | }) |
0a3bdf9d | 7583 | |
6590e19a | 7584 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
7585 | [(set (pc) |
7586 | (if_then_else | |
7e665d18 | 7587 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
7588 | (const_int 1)) |
7589 | (label_ref (match_operand 0 "" "")) | |
7590 | (pc))) | |
7e665d18 | 7591 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 7592 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 7593 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 7594 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 7595 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
7596 | { |
7597 | if (which_alternative != 0) | |
10bbf137 | 7598 | return "#"; |
0a3bdf9d | 7599 | else if (get_attr_length (insn) == 4) |
d40c829f | 7600 | return "brct\t%1,%l0"; |
6590e19a | 7601 | else |
545d16ff | 7602 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
7603 | } |
7604 | "&& reload_completed | |
7605 | && (! REG_P (operands[2]) | |
7606 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
7607 | [(set (match_dup 3) (match_dup 1)) |
7608 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
7609 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
7610 | (const_int 0))) | |
7611 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7612 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 7613 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
7614 | (label_ref (match_dup 0)) |
7615 | (pc)))] | |
7616 | "" | |
7617 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
7618 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
7619 | ; hurt us in the (rare) case of ahi. | |
729e750f | 7620 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
7621 | (set_attr "type" "branch") |
7622 | (set (attr "length") | |
7623 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7624 | (const_int 4) (const_int 10)))]) | |
7625 | ||
7626 | (define_insn_and_split "doloop_si31" | |
7627 | [(set (pc) | |
7628 | (if_then_else | |
7e665d18 | 7629 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
7630 | (const_int 1)) |
7631 | (label_ref (match_operand 0 "" "")) | |
7632 | (pc))) | |
7e665d18 | 7633 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 7634 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 7635 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 7636 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
7637 | "!TARGET_CPU_ZARCH" |
7638 | { | |
7639 | if (which_alternative != 0) | |
7640 | return "#"; | |
7641 | else if (get_attr_length (insn) == 4) | |
7642 | return "brct\t%1,%l0"; | |
0a3bdf9d | 7643 | else |
8d933e31 | 7644 | gcc_unreachable (); |
10bbf137 | 7645 | } |
6590e19a UW |
7646 | "&& reload_completed |
7647 | && (! REG_P (operands[2]) | |
7648 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
7649 | [(set (match_dup 3) (match_dup 1)) |
7650 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
7651 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
7652 | (const_int 0))) | |
7653 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7654 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 7655 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
7656 | (label_ref (match_dup 0)) |
7657 | (pc)))] | |
7658 | "" | |
0a3bdf9d | 7659 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
7660 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
7661 | ; hurt us in the (rare) case of ahi. | |
729e750f | 7662 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 7663 | (set_attr "type" "branch") |
0a3bdf9d | 7664 | (set (attr "length") |
6590e19a UW |
7665 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7666 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7667 | (const_int 4) (const_int 6)) | |
7668 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7669 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7670 | |
0a3bdf9d UW |
7671 | (define_insn "*doloop_si_long" |
7672 | [(set (pc) | |
7673 | (if_then_else | |
7e665d18 | 7674 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 7675 | (const_int 1)) |
4fe6dea8 | 7676 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 7677 | (pc))) |
7e665d18 | 7678 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 7679 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 7680 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 7681 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 7682 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
7683 | { |
7684 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7685 | return "bctr\t%1,%0"; |
0a3bdf9d | 7686 | else |
d40c829f | 7687 | return "bct\t%1,%a0"; |
10bbf137 | 7688 | } |
c7453384 | 7689 | [(set (attr "op_type") |
0a3bdf9d UW |
7690 | (if_then_else (match_operand 0 "register_operand" "") |
7691 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 7692 | (set_attr "type" "branch") |
729e750f | 7693 | (set_attr "atype" "agen") |
e3cba5e5 | 7694 | (set_attr "z10prop" "z10_c")]) |
0a3bdf9d | 7695 | |
6590e19a | 7696 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
7697 | [(set (pc) |
7698 | (if_then_else | |
7e665d18 | 7699 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
7700 | (const_int 1)) |
7701 | (label_ref (match_operand 0 "" "")) | |
7702 | (pc))) | |
7e665d18 | 7703 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 7704 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 7705 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 7706 | (clobber (reg:CC CC_REGNUM))] |
0a3bdf9d | 7707 | "TARGET_64BIT" |
0a3bdf9d UW |
7708 | { |
7709 | if (which_alternative != 0) | |
10bbf137 | 7710 | return "#"; |
0a3bdf9d | 7711 | else if (get_attr_length (insn) == 4) |
d40c829f | 7712 | return "brctg\t%1,%l0"; |
0a3bdf9d | 7713 | else |
545d16ff | 7714 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 7715 | } |
6590e19a | 7716 | "&& reload_completed |
0a3bdf9d UW |
7717 | && (! REG_P (operands[2]) |
7718 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
7719 | [(set (match_dup 3) (match_dup 1)) |
7720 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
7721 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
7722 | (const_int 0))) | |
7723 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
7724 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 7725 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 7726 | (label_ref (match_dup 0)) |
0a3bdf9d | 7727 | (pc)))] |
6590e19a UW |
7728 | "" |
7729 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
7730 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
7731 | ; hurt us in the (rare) case of ahi. | |
729e750f | 7732 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
7733 | (set_attr "type" "branch") |
7734 | (set (attr "length") | |
7735 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7736 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
7737 | |
7738 | ;; | |
7739 | ;;- Unconditional jump instructions. | |
7740 | ;; | |
7741 | ||
7742 | ; | |
7743 | ; jump instruction pattern(s). | |
7744 | ; | |
7745 | ||
6590e19a UW |
7746 | (define_expand "jump" |
7747 | [(match_operand 0 "" "")] | |
9db1d521 | 7748 | "" |
6590e19a UW |
7749 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
7750 | ||
7751 | (define_insn "*jump64" | |
7752 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7753 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7754 | { |
13e58269 | 7755 | if (get_attr_length (insn) == 4) |
d40c829f | 7756 | return "j\t%l0"; |
6590e19a | 7757 | else |
d40c829f | 7758 | return "jg\t%l0"; |
6590e19a UW |
7759 | } |
7760 | [(set_attr "op_type" "RI") | |
7761 | (set_attr "type" "branch") | |
7762 | (set (attr "length") | |
7763 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7764 | (const_int 4) (const_int 6)))]) | |
7765 | ||
7766 | (define_insn "*jump31" | |
7767 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7768 | "!TARGET_CPU_ZARCH" | |
7769 | { | |
8d933e31 AS |
7770 | gcc_assert (get_attr_length (insn) == 4); |
7771 | return "j\t%l0"; | |
10bbf137 | 7772 | } |
9db1d521 | 7773 | [(set_attr "op_type" "RI") |
077dab3b | 7774 | (set_attr "type" "branch") |
13e58269 | 7775 | (set (attr "length") |
6590e19a UW |
7776 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7777 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7778 | (const_int 4) (const_int 6)) | |
7779 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7780 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
7781 | |
7782 | ; | |
7783 | ; indirect-jump instruction pattern(s). | |
7784 | ; | |
7785 | ||
7786 | (define_insn "indirect_jump" | |
4fe6dea8 | 7787 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 7788 | "" |
f314b9b1 UW |
7789 | { |
7790 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7791 | return "br\t%0"; |
f314b9b1 | 7792 | else |
d40c829f | 7793 | return "b\t%a0"; |
10bbf137 | 7794 | } |
c7453384 | 7795 | [(set (attr "op_type") |
f314b9b1 UW |
7796 | (if_then_else (match_operand 0 "register_operand" "") |
7797 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 7798 | (set_attr "type" "branch") |
729e750f | 7799 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7800 | |
7801 | ; | |
f314b9b1 | 7802 | ; casesi instruction pattern(s). |
9db1d521 HP |
7803 | ; |
7804 | ||
f314b9b1 | 7805 | (define_insn "casesi_jump" |
4fe6dea8 | 7806 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 7807 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 7808 | "" |
9db1d521 | 7809 | { |
f314b9b1 | 7810 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 7811 | return "br\t%0"; |
f314b9b1 | 7812 | else |
d40c829f | 7813 | return "b\t%a0"; |
10bbf137 | 7814 | } |
c7453384 | 7815 | [(set (attr "op_type") |
f314b9b1 UW |
7816 | (if_then_else (match_operand 0 "register_operand" "") |
7817 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7818 | (set_attr "type" "branch") |
7819 | (set_attr "atype" "agen")]) | |
9db1d521 | 7820 | |
f314b9b1 UW |
7821 | (define_expand "casesi" |
7822 | [(match_operand:SI 0 "general_operand" "") | |
7823 | (match_operand:SI 1 "general_operand" "") | |
7824 | (match_operand:SI 2 "general_operand" "") | |
7825 | (label_ref (match_operand 3 "" "")) | |
7826 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 7827 | "" |
f314b9b1 UW |
7828 | { |
7829 | rtx index = gen_reg_rtx (SImode); | |
7830 | rtx base = gen_reg_rtx (Pmode); | |
7831 | rtx target = gen_reg_rtx (Pmode); | |
7832 | ||
7833 | emit_move_insn (index, operands[0]); | |
7834 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
7835 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 7836 | operands[4]); |
f314b9b1 UW |
7837 | |
7838 | if (Pmode != SImode) | |
7839 | index = convert_to_mode (Pmode, index, 1); | |
7840 | if (GET_CODE (index) != REG) | |
7841 | index = copy_to_mode_reg (Pmode, index); | |
7842 | ||
7843 | if (TARGET_64BIT) | |
7844 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
7845 | else | |
a556fd39 | 7846 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 7847 | |
f314b9b1 UW |
7848 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
7849 | ||
542a8afa | 7850 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
7851 | emit_move_insn (target, index); |
7852 | ||
7853 | if (flag_pic) | |
7854 | target = gen_rtx_PLUS (Pmode, base, target); | |
7855 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
7856 | ||
7857 | DONE; | |
10bbf137 | 7858 | }) |
9db1d521 HP |
7859 | |
7860 | ||
7861 | ;; | |
7862 | ;;- Jump to subroutine. | |
7863 | ;; | |
7864 | ;; | |
7865 | ||
7866 | ; | |
7867 | ; untyped call instruction pattern(s). | |
7868 | ; | |
7869 | ||
7870 | ;; Call subroutine returning any type. | |
7871 | (define_expand "untyped_call" | |
7872 | [(parallel [(call (match_operand 0 "" "") | |
7873 | (const_int 0)) | |
7874 | (match_operand 1 "" "") | |
7875 | (match_operand 2 "" "")])] | |
7876 | "" | |
9db1d521 HP |
7877 | { |
7878 | int i; | |
7879 | ||
7880 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
7881 | ||
7882 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7883 | { | |
7884 | rtx set = XVECEXP (operands[2], 0, i); | |
7885 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7886 | } | |
7887 | ||
7888 | /* The optimizer does not know that the call sets the function value | |
7889 | registers we stored in the result block. We avoid problems by | |
7890 | claiming that all hard registers are used and clobbered at this | |
7891 | point. */ | |
7892 | emit_insn (gen_blockage ()); | |
7893 | ||
7894 | DONE; | |
10bbf137 | 7895 | }) |
9db1d521 HP |
7896 | |
7897 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7898 | ;; all of memory. This blocks insns from being moved across this point. | |
7899 | ||
7900 | (define_insn "blockage" | |
10bbf137 | 7901 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 7902 | "" |
4023fb28 | 7903 | "" |
d5869ca0 UW |
7904 | [(set_attr "type" "none") |
7905 | (set_attr "length" "0")]) | |
4023fb28 | 7906 | |
9db1d521 | 7907 | ; |
ed9676cf | 7908 | ; sibcall patterns |
9db1d521 HP |
7909 | ; |
7910 | ||
ed9676cf | 7911 | (define_expand "sibcall" |
44b8152b | 7912 | [(call (match_operand 0 "" "") |
ed9676cf | 7913 | (match_operand 1 "" ""))] |
9db1d521 | 7914 | "" |
9db1d521 | 7915 | { |
ed9676cf AK |
7916 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
7917 | DONE; | |
7918 | }) | |
9db1d521 | 7919 | |
ed9676cf | 7920 | (define_insn "*sibcall_br" |
ae156f85 | 7921 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 7922 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 7923 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7924 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
7925 | "br\t%%r1" | |
7926 | [(set_attr "op_type" "RR") | |
7927 | (set_attr "type" "branch") | |
7928 | (set_attr "atype" "agen")]) | |
9db1d521 | 7929 | |
ed9676cf AK |
7930 | (define_insn "*sibcall_brc" |
7931 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7932 | (match_operand 1 "const_int_operand" "n"))] | |
7933 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7934 | "j\t%0" | |
7935 | [(set_attr "op_type" "RI") | |
7936 | (set_attr "type" "branch")]) | |
9db1d521 | 7937 | |
ed9676cf AK |
7938 | (define_insn "*sibcall_brcl" |
7939 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7940 | (match_operand 1 "const_int_operand" "n"))] | |
7941 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7942 | "jg\t%0" | |
7943 | [(set_attr "op_type" "RIL") | |
7944 | (set_attr "type" "branch")]) | |
44b8152b | 7945 | |
ed9676cf AK |
7946 | ; |
7947 | ; sibcall_value patterns | |
7948 | ; | |
9e8327e3 | 7949 | |
ed9676cf AK |
7950 | (define_expand "sibcall_value" |
7951 | [(set (match_operand 0 "" "") | |
7952 | (call (match_operand 1 "" "") | |
7953 | (match_operand 2 "" "")))] | |
7954 | "" | |
7955 | { | |
7956 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 7957 | DONE; |
10bbf137 | 7958 | }) |
9db1d521 | 7959 | |
ed9676cf AK |
7960 | (define_insn "*sibcall_value_br" |
7961 | [(set (match_operand 0 "" "") | |
ae156f85 | 7962 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 7963 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 7964 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7965 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
7966 | "br\t%%r1" | |
7967 | [(set_attr "op_type" "RR") | |
7968 | (set_attr "type" "branch") | |
7969 | (set_attr "atype" "agen")]) | |
7970 | ||
7971 | (define_insn "*sibcall_value_brc" | |
7972 | [(set (match_operand 0 "" "") | |
7973 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7974 | (match_operand 2 "const_int_operand" "n")))] | |
7975 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7976 | "j\t%1" | |
7977 | [(set_attr "op_type" "RI") | |
7978 | (set_attr "type" "branch")]) | |
7979 | ||
7980 | (define_insn "*sibcall_value_brcl" | |
7981 | [(set (match_operand 0 "" "") | |
7982 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7983 | (match_operand 2 "const_int_operand" "n")))] | |
7984 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7985 | "jg\t%1" | |
7986 | [(set_attr "op_type" "RIL") | |
7987 | (set_attr "type" "branch")]) | |
7988 | ||
7989 | ||
7990 | ; | |
7991 | ; call instruction pattern(s). | |
7992 | ; | |
7993 | ||
7994 | (define_expand "call" | |
7995 | [(call (match_operand 0 "" "") | |
7996 | (match_operand 1 "" "")) | |
7997 | (use (match_operand 2 "" ""))] | |
44b8152b | 7998 | "" |
ed9676cf | 7999 | { |
2f7e5a0d | 8000 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
8001 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
8002 | DONE; | |
8003 | }) | |
44b8152b | 8004 | |
9e8327e3 UW |
8005 | (define_insn "*bras" |
8006 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8007 | (match_operand 1 "const_int_operand" "n")) | |
8008 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8009 | "!SIBLING_CALL_P (insn) |
8010 | && TARGET_SMALL_EXEC | |
ed9676cf | 8011 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 8012 | "bras\t%2,%0" |
9db1d521 | 8013 | [(set_attr "op_type" "RI") |
4023fb28 | 8014 | (set_attr "type" "jsr")]) |
9db1d521 | 8015 | |
9e8327e3 UW |
8016 | (define_insn "*brasl" |
8017 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8018 | (match_operand 1 "const_int_operand" "n")) | |
8019 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8020 | "!SIBLING_CALL_P (insn) |
8021 | && TARGET_CPU_ZARCH | |
ed9676cf | 8022 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8023 | "brasl\t%2,%0" |
8024 | [(set_attr "op_type" "RIL") | |
077dab3b | 8025 | (set_attr "type" "jsr")]) |
9db1d521 | 8026 | |
9e8327e3 | 8027 | (define_insn "*basr" |
4fe6dea8 | 8028 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
8029 | (match_operand 1 "const_int_operand" "n")) |
8030 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 8031 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8032 | { |
8033 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8034 | return "basr\t%2,%0"; | |
8035 | else | |
8036 | return "bas\t%2,%a0"; | |
8037 | } | |
8038 | [(set (attr "op_type") | |
8039 | (if_then_else (match_operand 0 "register_operand" "") | |
8040 | (const_string "RR") (const_string "RX"))) | |
8041 | (set_attr "type" "jsr") | |
8042 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8043 | |
8044 | ; | |
8045 | ; call_value instruction pattern(s). | |
8046 | ; | |
8047 | ||
8048 | (define_expand "call_value" | |
44b8152b UW |
8049 | [(set (match_operand 0 "" "") |
8050 | (call (match_operand 1 "" "") | |
8051 | (match_operand 2 "" ""))) | |
8052 | (use (match_operand 3 "" ""))] | |
9db1d521 | 8053 | "" |
9db1d521 | 8054 | { |
2f7e5a0d | 8055 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 8056 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 8057 | DONE; |
10bbf137 | 8058 | }) |
9db1d521 | 8059 | |
9e8327e3 | 8060 | (define_insn "*bras_r" |
c19ec8f9 | 8061 | [(set (match_operand 0 "" "") |
9e8327e3 | 8062 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 8063 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 8064 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
8065 | "!SIBLING_CALL_P (insn) |
8066 | && TARGET_SMALL_EXEC | |
ed9676cf | 8067 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8068 | "bras\t%3,%1" |
9db1d521 | 8069 | [(set_attr "op_type" "RI") |
f2d3c02a | 8070 | (set_attr "type" "jsr")]) |
9db1d521 | 8071 | |
9e8327e3 | 8072 | (define_insn "*brasl_r" |
c19ec8f9 | 8073 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8074 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8075 | (match_operand 2 "const_int_operand" "n"))) | |
8076 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
8077 | "!SIBLING_CALL_P (insn) |
8078 | && TARGET_CPU_ZARCH | |
ed9676cf | 8079 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8080 | "brasl\t%3,%1" |
8081 | [(set_attr "op_type" "RIL") | |
077dab3b | 8082 | (set_attr "type" "jsr")]) |
9db1d521 | 8083 | |
9e8327e3 | 8084 | (define_insn "*basr_r" |
c19ec8f9 | 8085 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8086 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8087 | (match_operand 2 "const_int_operand" "n"))) |
8088 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 8089 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8090 | { |
8091 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8092 | return "basr\t%3,%1"; | |
8093 | else | |
8094 | return "bas\t%3,%a1"; | |
8095 | } | |
8096 | [(set (attr "op_type") | |
8097 | (if_then_else (match_operand 1 "register_operand" "") | |
8098 | (const_string "RR") (const_string "RX"))) | |
8099 | (set_attr "type" "jsr") | |
8100 | (set_attr "atype" "agen")]) | |
9db1d521 | 8101 | |
fd3cd001 UW |
8102 | ;; |
8103 | ;;- Thread-local storage support. | |
8104 | ;; | |
8105 | ||
c5aa1d12 | 8106 | (define_expand "get_tp_64" |
ae156f85 | 8107 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] |
fd3cd001 | 8108 | "TARGET_64BIT" |
c5aa1d12 | 8109 | "") |
fd3cd001 | 8110 | |
c5aa1d12 | 8111 | (define_expand "get_tp_31" |
ae156f85 | 8112 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] |
fd3cd001 | 8113 | "!TARGET_64BIT" |
c5aa1d12 | 8114 | "") |
fd3cd001 | 8115 | |
c5aa1d12 | 8116 | (define_expand "set_tp_64" |
ae156f85 AS |
8117 | [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) |
8118 | (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 8119 | "TARGET_64BIT" |
c5aa1d12 | 8120 | "") |
fd3cd001 | 8121 | |
c5aa1d12 | 8122 | (define_expand "set_tp_31" |
ae156f85 AS |
8123 | [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) |
8124 | (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 8125 | "!TARGET_64BIT" |
c5aa1d12 UW |
8126 | "") |
8127 | ||
8128 | (define_insn "*set_tp" | |
ae156f85 | 8129 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
8130 | "" |
8131 | "" | |
8132 | [(set_attr "type" "none") | |
8133 | (set_attr "length" "0")]) | |
c7453384 | 8134 | |
fd3cd001 UW |
8135 | (define_insn "*tls_load_64" |
8136 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 8137 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
8138 | (match_operand:DI 2 "" "")] |
8139 | UNSPEC_TLS_LOAD))] | |
8140 | "TARGET_64BIT" | |
d40c829f | 8141 | "lg\t%0,%1%J2" |
9381e3f1 WG |
8142 | [(set_attr "op_type" "RXE") |
8143 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
8144 | |
8145 | (define_insn "*tls_load_31" | |
d3632d41 UW |
8146 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
8147 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
8148 | (match_operand:SI 2 "" "")] |
8149 | UNSPEC_TLS_LOAD))] | |
8150 | "!TARGET_64BIT" | |
d3632d41 | 8151 | "@ |
d40c829f UW |
8152 | l\t%0,%1%J2 |
8153 | ly\t%0,%1%J2" | |
9381e3f1 | 8154 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 8155 | (set_attr "type" "load") |
9381e3f1 | 8156 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 8157 | |
9e8327e3 | 8158 | (define_insn "*bras_tls" |
c19ec8f9 | 8159 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8160 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8161 | (match_operand 2 "const_int_operand" "n"))) | |
8162 | (clobber (match_operand 3 "register_operand" "=r")) | |
8163 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8164 | "!SIBLING_CALL_P (insn) |
8165 | && TARGET_SMALL_EXEC | |
ed9676cf | 8166 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8167 | "bras\t%3,%1%J4" |
fd3cd001 UW |
8168 | [(set_attr "op_type" "RI") |
8169 | (set_attr "type" "jsr")]) | |
8170 | ||
9e8327e3 | 8171 | (define_insn "*brasl_tls" |
c19ec8f9 | 8172 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8173 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8174 | (match_operand 2 "const_int_operand" "n"))) | |
8175 | (clobber (match_operand 3 "register_operand" "=r")) | |
8176 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8177 | "!SIBLING_CALL_P (insn) |
8178 | && TARGET_CPU_ZARCH | |
ed9676cf | 8179 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8180 | "brasl\t%3,%1%J4" |
8181 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
8182 | (set_attr "type" "jsr")]) |
8183 | ||
9e8327e3 | 8184 | (define_insn "*basr_tls" |
c19ec8f9 | 8185 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8186 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8187 | (match_operand 2 "const_int_operand" "n"))) |
8188 | (clobber (match_operand 3 "register_operand" "=r")) | |
8189 | (use (match_operand 4 "" ""))] | |
ed9676cf | 8190 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8191 | { |
8192 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8193 | return "basr\t%3,%1%J4"; | |
8194 | else | |
8195 | return "bas\t%3,%a1%J4"; | |
8196 | } | |
8197 | [(set (attr "op_type") | |
8198 | (if_then_else (match_operand 1 "register_operand" "") | |
8199 | (const_string "RR") (const_string "RX"))) | |
8200 | (set_attr "type" "jsr") | |
8201 | (set_attr "atype" "agen")]) | |
fd3cd001 | 8202 | |
e0374221 AS |
8203 | ;; |
8204 | ;;- Atomic operations | |
8205 | ;; | |
8206 | ||
8207 | ; | |
8208 | ; memory barrier pattern. | |
8209 | ; | |
8210 | ||
8211 | (define_expand "memory_barrier" | |
1a8c13b3 UB |
8212 | [(set (match_dup 0) |
8213 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] | |
e0374221 AS |
8214 | "" |
8215 | { | |
1a8c13b3 | 8216 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); |
e0374221 AS |
8217 | MEM_VOLATILE_P (operands[0]) = 1; |
8218 | }) | |
8219 | ||
8220 | (define_insn "*memory_barrier" | |
8221 | [(set (match_operand:BLK 0 "" "") | |
1a8c13b3 | 8222 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 AS |
8223 | "" |
8224 | "bcr\t15,0" | |
8225 | [(set_attr "op_type" "RR")]) | |
1a8c13b3 | 8226 | |
9381e3f1 WG |
8227 | ; Although bcr is superscalar on Z10, this variant will never become part of |
8228 | ; an execution group. | |
e0374221 AS |
8229 | |
8230 | ; | |
8231 | ; compare and swap patterns. | |
8232 | ; | |
8233 | ||
8006eaa6 AS |
8234 | (define_expand "sync_compare_and_swap<mode>" |
8235 | [(parallel | |
8236 | [(set (match_operand:TDSI 0 "register_operand" "") | |
8237 | (match_operand:TDSI 1 "memory_operand" "")) | |
8238 | (set (match_dup 1) | |
8239 | (unspec_volatile:TDSI | |
8240 | [(match_dup 1) | |
8241 | (match_operand:TDSI 2 "register_operand" "") | |
8242 | (match_operand:TDSI 3 "register_operand" "")] | |
8243 | UNSPECV_CAS)) | |
8244 | (set (reg:CCZ1 CC_REGNUM) | |
8245 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8246 | "") | |
e0374221 | 8247 | |
3093f076 AS |
8248 | (define_expand "sync_compare_and_swap<mode>" |
8249 | [(parallel | |
8250 | [(set (match_operand:HQI 0 "register_operand" "") | |
8251 | (match_operand:HQI 1 "memory_operand" "")) | |
8252 | (set (match_dup 1) | |
8253 | (unspec_volatile:HQI | |
8254 | [(match_dup 1) | |
8255 | (match_operand:HQI 2 "general_operand" "") | |
8256 | (match_operand:HQI 3 "general_operand" "")] | |
8257 | UNSPECV_CAS)) | |
4a77c72b | 8258 | (clobber (reg:CC CC_REGNUM))])] |
3093f076 | 8259 | "" |
9381e3f1 | 8260 | "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], |
3093f076 AS |
8261 | operands[2], operands[3]); DONE;") |
8262 | ||
43a09b63 | 8263 | ; cds, cdsg |
8006eaa6 AS |
8264 | (define_insn "*sync_compare_and_swap<mode>" |
8265 | [(set (match_operand:DP 0 "register_operand" "=r") | |
8266 | (match_operand:DP 1 "memory_operand" "+Q")) | |
8267 | (set (match_dup 1) | |
8268 | (unspec_volatile:DP | |
8269 | [(match_dup 1) | |
8270 | (match_operand:DP 2 "register_operand" "0") | |
8271 | (match_operand:DP 3 "register_operand" "r")] | |
8272 | UNSPECV_CAS)) | |
8273 | (set (reg:CCZ1 CC_REGNUM) | |
8274 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
8275 | "" | |
8276 | "cds<tg>\t%0,%3,%S1" | |
8277 | [(set_attr "op_type" "RS<TE>") | |
8278 | (set_attr "type" "sem")]) | |
8279 | ||
43a09b63 | 8280 | ; cs, csg |
8006eaa6 | 8281 | (define_insn "*sync_compare_and_swap<mode>" |
e0374221 AS |
8282 | [(set (match_operand:GPR 0 "register_operand" "=r") |
8283 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
8284 | (set (match_dup 1) | |
8285 | (unspec_volatile:GPR | |
8286 | [(match_dup 1) | |
8287 | (match_operand:GPR 2 "register_operand" "0") | |
8288 | (match_operand:GPR 3 "register_operand" "r")] | |
8289 | UNSPECV_CAS)) | |
69950452 AS |
8290 | (set (reg:CCZ1 CC_REGNUM) |
8291 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 8292 | "" |
e0374221 AS |
8293 | "cs<g>\t%0,%3,%S1" |
8294 | [(set_attr "op_type" "RS<E>") | |
8295 | (set_attr "type" "sem")]) | |
8296 | ||
8297 | ||
45d18331 AS |
8298 | ; |
8299 | ; Other atomic instruction patterns. | |
8300 | ; | |
8301 | ||
8302 | (define_expand "sync_lock_test_and_set<mode>" | |
8303 | [(match_operand:HQI 0 "register_operand") | |
8304 | (match_operand:HQI 1 "memory_operand") | |
8305 | (match_operand:HQI 2 "general_operand")] | |
8306 | "" | |
9381e3f1 | 8307 | "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], |
45d18331 AS |
8308 | operands[2], false); DONE;") |
8309 | ||
8310 | (define_expand "sync_<atomic><mode>" | |
8311 | [(set (match_operand:HQI 0 "memory_operand") | |
8312 | (ATOMIC:HQI (match_dup 0) | |
8313 | (match_operand:HQI 1 "general_operand")))] | |
8314 | "" | |
9381e3f1 | 8315 | "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], |
45d18331 AS |
8316 | operands[1], false); DONE;") |
8317 | ||
8318 | (define_expand "sync_old_<atomic><mode>" | |
8319 | [(set (match_operand:HQI 0 "register_operand") | |
8320 | (match_operand:HQI 1 "memory_operand")) | |
8321 | (set (match_dup 1) | |
8322 | (ATOMIC:HQI (match_dup 1) | |
8323 | (match_operand:HQI 2 "general_operand")))] | |
8324 | "" | |
9381e3f1 | 8325 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], |
45d18331 AS |
8326 | operands[2], false); DONE;") |
8327 | ||
8328 | (define_expand "sync_new_<atomic><mode>" | |
8329 | [(set (match_operand:HQI 0 "register_operand") | |
8330 | (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") | |
9381e3f1 | 8331 | (match_operand:HQI 2 "general_operand"))) |
45d18331 AS |
8332 | (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] |
8333 | "" | |
9381e3f1 | 8334 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], |
45d18331 AS |
8335 | operands[2], true); DONE;") |
8336 | ||
9db1d521 HP |
8337 | ;; |
8338 | ;;- Miscellaneous instructions. | |
8339 | ;; | |
8340 | ||
8341 | ; | |
8342 | ; allocate stack instruction pattern(s). | |
8343 | ; | |
8344 | ||
8345 | (define_expand "allocate_stack" | |
ef44a6ff UW |
8346 | [(match_operand 0 "general_operand" "") |
8347 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 8348 | "TARGET_BACKCHAIN" |
9db1d521 | 8349 | { |
ef44a6ff | 8350 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 8351 | |
ef44a6ff UW |
8352 | emit_move_insn (temp, s390_back_chain_rtx ()); |
8353 | anti_adjust_stack (operands[1]); | |
8354 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 8355 | |
ef44a6ff UW |
8356 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
8357 | DONE; | |
10bbf137 | 8358 | }) |
9db1d521 HP |
8359 | |
8360 | ||
8361 | ; | |
43ab026f | 8362 | ; setjmp instruction pattern. |
9db1d521 HP |
8363 | ; |
8364 | ||
9db1d521 | 8365 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 8366 | [(match_operand 0 "" "")] |
f314b9b1 | 8367 | "flag_pic" |
9db1d521 | 8368 | { |
585539a1 | 8369 | emit_insn (s390_load_got ()); |
c41c1387 | 8370 | emit_use (pic_offset_table_rtx); |
9db1d521 | 8371 | DONE; |
fd7643fb | 8372 | }) |
9db1d521 | 8373 | |
9db1d521 HP |
8374 | ;; These patterns say how to save and restore the stack pointer. We need not |
8375 | ;; save the stack pointer at function level since we are careful to | |
8376 | ;; preserve the backchain. At block level, we have to restore the backchain | |
8377 | ;; when we restore the stack pointer. | |
8378 | ;; | |
8379 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
8380 | ;; backchain and restore both. Note that in the nonlocal case, the | |
8381 | ;; save area is a memory location. | |
8382 | ||
8383 | (define_expand "save_stack_function" | |
8384 | [(match_operand 0 "general_operand" "") | |
8385 | (match_operand 1 "general_operand" "")] | |
8386 | "" | |
8387 | "DONE;") | |
8388 | ||
8389 | (define_expand "restore_stack_function" | |
8390 | [(match_operand 0 "general_operand" "") | |
8391 | (match_operand 1 "general_operand" "")] | |
8392 | "" | |
8393 | "DONE;") | |
8394 | ||
8395 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
8396 | [(match_operand 0 "register_operand" "") |
8397 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 8398 | "TARGET_BACKCHAIN" |
9db1d521 | 8399 | { |
ef44a6ff UW |
8400 | rtx temp = gen_reg_rtx (Pmode); |
8401 | ||
8402 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
8403 | emit_move_insn (operands[0], operands[1]); | |
8404 | emit_move_insn (s390_back_chain_rtx (), temp); | |
8405 | ||
8406 | DONE; | |
10bbf137 | 8407 | }) |
9db1d521 HP |
8408 | |
8409 | (define_expand "save_stack_nonlocal" | |
8410 | [(match_operand 0 "memory_operand" "") | |
8411 | (match_operand 1 "register_operand" "")] | |
8412 | "" | |
9db1d521 | 8413 | { |
ef44a6ff UW |
8414 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
8415 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
8416 | ||
8417 | /* Copy the backchain to the first word, sp to the second and the | |
8418 | literal pool base to the third. */ | |
8419 | ||
b3d31392 | 8420 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
8421 | { |
8422 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
8423 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
8424 | } | |
8425 | ||
8426 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
8427 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 8428 | |
9db1d521 | 8429 | DONE; |
10bbf137 | 8430 | }) |
9db1d521 HP |
8431 | |
8432 | (define_expand "restore_stack_nonlocal" | |
8433 | [(match_operand 0 "register_operand" "") | |
8434 | (match_operand 1 "memory_operand" "")] | |
8435 | "" | |
9db1d521 | 8436 | { |
ef44a6ff | 8437 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 8438 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 8439 | rtx temp = NULL_RTX; |
9db1d521 | 8440 | |
43ab026f | 8441 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 8442 | literal pool base from the third. */ |
43ab026f | 8443 | |
b3d31392 | 8444 | if (TARGET_BACKCHAIN) |
ef44a6ff | 8445 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
9381e3f1 | 8446 | |
ef44a6ff UW |
8447 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); |
8448 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
8449 | ||
8450 | if (temp) | |
8451 | emit_move_insn (s390_back_chain_rtx (), temp); | |
8452 | ||
c41c1387 | 8453 | emit_use (base); |
9db1d521 | 8454 | DONE; |
10bbf137 | 8455 | }) |
9db1d521 | 8456 | |
7bcebb25 AK |
8457 | (define_expand "exception_receiver" |
8458 | [(const_int 0)] | |
8459 | "" | |
8460 | { | |
8461 | s390_set_has_landing_pad_p (true); | |
8462 | DONE; | |
8463 | }) | |
9db1d521 HP |
8464 | |
8465 | ; | |
8466 | ; nop instruction pattern(s). | |
8467 | ; | |
8468 | ||
8469 | (define_insn "nop" | |
8470 | [(const_int 0)] | |
8471 | "" | |
d40c829f | 8472 | "lr\t0,0" |
729e750f WG |
8473 | [(set_attr "op_type" "RR") |
8474 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 8475 | |
d277db6b WG |
8476 | (define_insn "nop1" |
8477 | [(const_int 1)] | |
8478 | "" | |
8479 | "lr\t1,1" | |
8480 | [(set_attr "op_type" "RR")]) | |
8481 | ||
9db1d521 HP |
8482 | |
8483 | ; | |
8484 | ; Special literal pool access instruction pattern(s). | |
8485 | ; | |
8486 | ||
416cf582 UW |
8487 | (define_insn "*pool_entry" |
8488 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
8489 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 8490 | "" |
9db1d521 | 8491 | { |
416cf582 UW |
8492 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
8493 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 8494 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
8495 | return ""; |
8496 | } | |
b628bd8e | 8497 | [(set (attr "length") |
416cf582 | 8498 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 8499 | |
9bb86f41 UW |
8500 | (define_insn "pool_align" |
8501 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
8502 | UNSPECV_POOL_ALIGN)] | |
8503 | "" | |
8504 | ".align\t%0" | |
b628bd8e | 8505 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 8506 | |
9bb86f41 UW |
8507 | (define_insn "pool_section_start" |
8508 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
8509 | "" | |
8510 | ".section\t.rodata" | |
b628bd8e | 8511 | [(set_attr "length" "0")]) |
b2ccb744 | 8512 | |
9bb86f41 UW |
8513 | (define_insn "pool_section_end" |
8514 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
8515 | "" | |
b2ccb744 | 8516 | ".previous" |
b628bd8e | 8517 | [(set_attr "length" "0")]) |
b2ccb744 | 8518 | |
5af2f3d3 | 8519 | (define_insn "main_base_31_small" |
9e8327e3 UW |
8520 | [(set (match_operand 0 "register_operand" "=a") |
8521 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8522 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
8523 | "basr\t%0,0" |
8524 | [(set_attr "op_type" "RR") | |
8525 | (set_attr "type" "la")]) | |
8526 | ||
8527 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
8528 | [(set (match_operand 0 "register_operand" "=a") |
8529 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 8530 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 8531 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
8532 | "bras\t%0,%2" |
8533 | [(set_attr "op_type" "RI")]) | |
8534 | ||
8535 | (define_insn "main_base_64" | |
9e8327e3 UW |
8536 | [(set (match_operand 0 "register_operand" "=a") |
8537 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8538 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
8539 | "larl\t%0,%1" |
8540 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 8541 | (set_attr "type" "larl") |
729e750f | 8542 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
8543 | |
8544 | (define_insn "main_pool" | |
585539a1 UW |
8545 | [(set (match_operand 0 "register_operand" "=a") |
8546 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
8547 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
8548 | { |
8549 | gcc_unreachable (); | |
8550 | } | |
9381e3f1 | 8551 | [(set (attr "type") |
ea77e738 UW |
8552 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
8553 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 8554 | |
aee4e0db | 8555 | (define_insn "reload_base_31" |
9e8327e3 UW |
8556 | [(set (match_operand 0 "register_operand" "=a") |
8557 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8558 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8559 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
8560 | [(set_attr "length" "6") |
8561 | (set_attr "type" "la")]) | |
b2ccb744 | 8562 | |
aee4e0db | 8563 | (define_insn "reload_base_64" |
9e8327e3 UW |
8564 | [(set (match_operand 0 "register_operand" "=a") |
8565 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8566 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8567 | "larl\t%0,%1" |
aee4e0db | 8568 | [(set_attr "op_type" "RIL") |
9381e3f1 | 8569 | (set_attr "type" "larl") |
729e750f | 8570 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 8571 | |
aee4e0db | 8572 | (define_insn "pool" |
fd7643fb | 8573 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 8574 | "" |
8d933e31 AS |
8575 | { |
8576 | gcc_unreachable (); | |
8577 | } | |
b628bd8e | 8578 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 8579 | |
4023fb28 UW |
8580 | ;; |
8581 | ;; Insns related to generating the function prologue and epilogue. | |
8582 | ;; | |
8583 | ||
8584 | ||
8585 | (define_expand "prologue" | |
8586 | [(use (const_int 0))] | |
8587 | "" | |
10bbf137 | 8588 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
8589 | |
8590 | (define_expand "epilogue" | |
8591 | [(use (const_int 1))] | |
8592 | "" | |
ed9676cf AK |
8593 | "s390_emit_epilogue (false); DONE;") |
8594 | ||
8595 | (define_expand "sibcall_epilogue" | |
8596 | [(use (const_int 0))] | |
8597 | "" | |
8598 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 8599 | |
9e8327e3 | 8600 | (define_insn "*return" |
4023fb28 | 8601 | [(return) |
9e8327e3 UW |
8602 | (use (match_operand 0 "register_operand" "a"))] |
8603 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8604 | "br\t%0" |
4023fb28 | 8605 | [(set_attr "op_type" "RR") |
c7453384 | 8606 | (set_attr "type" "jsr") |
077dab3b | 8607 | (set_attr "atype" "agen")]) |
4023fb28 | 8608 | |
4023fb28 | 8609 | |
c7453384 | 8610 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 8611 | ;; pointer. This is used for compatibility. |
c7453384 EC |
8612 | |
8613 | (define_expand "ptr_extend" | |
8614 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8615 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 8616 | "TARGET_64BIT" |
c7453384 | 8617 | { |
c7453384 EC |
8618 | emit_insn (gen_anddi3 (operands[0], |
8619 | gen_lowpart (DImode, operands[1]), | |
8620 | GEN_INT (0x7fffffff))); | |
c7453384 | 8621 | DONE; |
10bbf137 | 8622 | }) |
4798630c D |
8623 | |
8624 | ;; Instruction definition to expand eh_return macro to support | |
8625 | ;; swapping in special linkage return addresses. | |
8626 | ||
8627 | (define_expand "eh_return" | |
8628 | [(use (match_operand 0 "register_operand" ""))] | |
8629 | "TARGET_TPF" | |
8630 | { | |
8631 | s390_emit_tpf_eh_return (operands[0]); | |
8632 | DONE; | |
8633 | }) | |
8634 | ||
7b8acc34 AK |
8635 | ; |
8636 | ; Stack Protector Patterns | |
8637 | ; | |
8638 | ||
8639 | (define_expand "stack_protect_set" | |
8640 | [(set (match_operand 0 "memory_operand" "") | |
8641 | (match_operand 1 "memory_operand" ""))] | |
8642 | "" | |
8643 | { | |
8644 | #ifdef TARGET_THREAD_SSP_OFFSET | |
8645 | operands[1] | |
8646 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
8647 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
8648 | #endif | |
8649 | if (TARGET_64BIT) | |
8650 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
8651 | else | |
8652 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
8653 | ||
8654 | DONE; | |
8655 | }) | |
8656 | ||
8657 | (define_insn "stack_protect_set<mode>" | |
8658 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
8659 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
8660 | "" | |
8661 | "mvc\t%O0(%G0,%R0),%S1" | |
8662 | [(set_attr "op_type" "SS")]) | |
8663 | ||
8664 | (define_expand "stack_protect_test" | |
8665 | [(set (reg:CC CC_REGNUM) | |
8666 | (compare (match_operand 0 "memory_operand" "") | |
8667 | (match_operand 1 "memory_operand" ""))) | |
8668 | (match_operand 2 "" "")] | |
8669 | "" | |
8670 | { | |
f90b7a5a | 8671 | rtx cc_reg, test; |
7b8acc34 AK |
8672 | #ifdef TARGET_THREAD_SSP_OFFSET |
8673 | operands[1] | |
8674 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
8675 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
8676 | #endif | |
7b8acc34 AK |
8677 | if (TARGET_64BIT) |
8678 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
8679 | else | |
8680 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
8681 | ||
f90b7a5a PB |
8682 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
8683 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
8684 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
8685 | DONE; |
8686 | }) | |
8687 | ||
8688 | (define_insn "stack_protect_test<mode>" | |
8689 | [(set (reg:CCZ CC_REGNUM) | |
8690 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
8691 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
8692 | "" | |
8693 | "clc\t%O0(%G0,%R0),%S1" | |
8694 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
8695 | |
8696 | ; This is used in s390_emit_prologue in order to prevent insns | |
8697 | ; adjusting the stack pointer to be moved over insns writing stack | |
8698 | ; slots using a copy of the stack pointer in a different register. | |
8699 | (define_insn "stack_tie" | |
8700 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
8701 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
8702 | "" | |
8703 | "" | |
8704 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
8705 | |
8706 | ||
8707 | ; | |
8708 | ; Data prefetch patterns | |
8709 | ; | |
8710 | ||
8711 | (define_insn "prefetch" | |
4fe6dea8 AK |
8712 | [(prefetch (match_operand 0 "address_operand" "ZQZS,ZRZT,X") |
8713 | (match_operand:SI 1 "const_int_operand" " n, n,n") | |
8714 | (match_operand:SI 2 "const_int_operand" " n, n,n"))] | |
8715 | "TARGET_ZARCH && s390_tune == PROCESSOR_2097_Z10" | |
963fc8d0 | 8716 | { |
4fe6dea8 AK |
8717 | switch (which_alternative) |
8718 | { | |
8719 | case 0: | |
8720 | return INTVAL (operands[1]) == 1 ? "stcmh\t2,0,%a0" : "stcmh\t1,0,%a0"; | |
8721 | case 1: | |
8722 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; | |
8723 | case 2: | |
8724 | if (larl_operand (operands[0], Pmode)) | |
8725 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
8726 | default: | |
8727 | ||
8728 | /* This might be reached for symbolic operands with an odd | |
8729 | addend. We simply omit the prefetch for such rare cases. */ | |
8730 | ||
8731 | return ""; | |
8732 | } | |
9381e3f1 | 8733 | } |
4fe6dea8 AK |
8734 | [(set_attr "type" "store,load,larl") |
8735 | (set_attr "op_type" "RSY,RXY,RIL") | |
8736 | (set_attr "z10prop" "z10_super") | |
8737 | (set_attr "cpu_facility" "*,z10,z10")]) | |
07da44ab AK |
8738 | |
8739 | ||
8740 | ; | |
8741 | ; Byte swap instructions | |
8742 | ; | |
8743 | ||
8744 | (define_insn "bswap<mode>2" | |
8745 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8746 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] | |
677fbff4 | 8747 | "TARGET_CPU_ZARCH" |
07da44ab AK |
8748 | "@ |
8749 | lrv<g>r\t%0,%1 | |
8750 | lrv<g>\t%0,%1" | |
8751 | [(set_attr "type" "*,load") | |
8752 | (set_attr "op_type" "RRE,RXY") | |
8753 | (set_attr "z10prop" "z10_super")]) |