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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
963fc8d0 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
5 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
6 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 7 | |
58add37a UW |
8 | ;; This file is part of GCC. |
9 | ||
10 | ;; GCC is free software; you can redistribute it and/or modify it under | |
11 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
13 | ;; version. |
14 | ||
15 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | ;; for more details. | |
9db1d521 HP |
19 | |
20 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | ;; along with GCC; see the file COPYING3. If not see |
22 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
23 | |
24 | ;; | |
cd8dc1f9 | 25 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 26 | ;; |
cd8dc1f9 | 27 | |
9db1d521 HP |
28 | ;; Special formats used for outputting 390 instructions. |
29 | ;; | |
f19a9af7 AK |
30 | ;; %C: print opcode suffix for branch condition. |
31 | ;; %D: print opcode suffix for inverse branch condition. | |
32 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 33 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
34 | ;; %O: print only the displacement of a memory reference. |
35 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 36 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
37 | ;; %N: print the second word of a DImode operand. |
38 | ;; %M: print the second word of a TImode operand. | |
da48f5ec AK |
39 | ;; %Y: print shift count operand. |
40 | ;; | |
f19a9af7 | 41 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 42 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
43 | ;; %x: print integer X as if it's an unsigned halfword. |
44 | ;; %h: print integer X as if it's a signed halfword. | |
45 | ;; %i: print the first nonzero HImode part of X. | |
46 | ;; %j: print the first HImode part unequal to -1 of X. | |
47 | ;; %k: print the first nonzero SImode part of X. | |
48 | ;; %m: print the first SImode part unequal to -1 of X. | |
49 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
50 | ;; |
51 | ;; We have a special constraint for pattern matching. | |
52 | ;; | |
53 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
54 | ;; | |
9db1d521 | 55 | |
fd3cd001 UW |
56 | ;; |
57 | ;; UNSPEC usage | |
58 | ;; | |
59 | ||
60 | (define_constants | |
10bbf137 UW |
61 | [; Miscellaneous |
62 | (UNSPEC_ROUND 1) | |
638e37c2 WG |
63 | (UNSPEC_CCU_TO_INT 2) |
64 | (UNSPEC_CCZ_TO_INT 3) | |
6fa05db6 | 65 | (UNSPEC_ICM 10) |
12959abe | 66 | (UNSPEC_TIE 11) |
10bbf137 UW |
67 | |
68 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
69 | (UNSPEC_LTREL_OFFSET 100) |
70 | (UNSPEC_LTREL_BASE 101) | |
dc66391d | 71 | (UNSPEC_POOL_OFFSET 102) |
fd7643fb UW |
72 | (UNSPEC_GOTENT 110) |
73 | (UNSPEC_GOT 111) | |
74 | (UNSPEC_GOTOFF 112) | |
75 | (UNSPEC_PLT 113) | |
76 | (UNSPEC_PLTOFF 114) | |
77 | ||
78 | ; Literal pool | |
79 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 80 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 81 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
82 | (UNSPEC_INSN 213) |
83 | (UNSPEC_EXECUTE 214) | |
fd7643fb | 84 | |
1a8c13b3 UB |
85 | ; Atomic Support |
86 | (UNSPEC_MB 400) | |
87 | ||
fd7643fb | 88 | ; TLS relocation specifiers |
fd3cd001 UW |
89 | (UNSPEC_TLSGD 500) |
90 | (UNSPEC_TLSLDM 501) | |
91 | (UNSPEC_NTPOFF 502) | |
92 | (UNSPEC_DTPOFF 503) | |
93 | (UNSPEC_GOTNTPOFF 504) | |
94 | (UNSPEC_INDNTPOFF 505) | |
95 | ||
96 | ; TLS support | |
fd3cd001 UW |
97 | (UNSPEC_TLSLDM_NTPOFF 511) |
98 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
99 | |
100 | ; String Functions | |
7b8acc34 | 101 | (UNSPEC_SRST 600) |
742090fc | 102 | (UNSPEC_MVST 601) |
638e37c2 | 103 | |
7b8acc34 AK |
104 | ; Stack Smashing Protector |
105 | (UNSPEC_SP_SET 700) | |
106 | (UNSPEC_SP_TEST 701) | |
85dae55a AK |
107 | |
108 | ; Copy sign instructions | |
109 | (UNSPEC_COPYSIGN 800) | |
638e37c2 WG |
110 | |
111 | ; Test Data Class (TDC) | |
112 | (UNSPEC_TDC_INSN 900) | |
fd3cd001 UW |
113 | ]) |
114 | ||
115 | ;; | |
116 | ;; UNSPEC_VOLATILE usage | |
117 | ;; | |
118 | ||
119 | (define_constants | |
10bbf137 UW |
120 | [; Blockage |
121 | (UNSPECV_BLOCKAGE 0) | |
122 | ||
2f7e5a0d EC |
123 | ; TPF Support |
124 | (UNSPECV_TPF_PROLOGUE 20) | |
125 | (UNSPECV_TPF_EPILOGUE 21) | |
126 | ||
10bbf137 | 127 | ; Literal pool |
fd7643fb | 128 | (UNSPECV_POOL 200) |
9bb86f41 UW |
129 | (UNSPECV_POOL_SECTION 201) |
130 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 131 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
132 | (UNSPECV_MAIN_POOL 300) |
133 | ||
134 | ; TLS support | |
fd3cd001 | 135 | (UNSPECV_SET_TP 500) |
e0374221 AS |
136 | |
137 | ; Atomic Support | |
1a8c13b3 | 138 | (UNSPECV_CAS 700) |
fd3cd001 UW |
139 | ]) |
140 | ||
ae156f85 AS |
141 | ;; |
142 | ;; Registers | |
143 | ;; | |
144 | ||
35dd9a0e AK |
145 | ; Registers with special meaning |
146 | ||
ae156f85 AS |
147 | (define_constants |
148 | [ | |
149 | ; Sibling call register. | |
150 | (SIBCALL_REGNUM 1) | |
151 | ; Literal pool base register. | |
152 | (BASE_REGNUM 13) | |
153 | ; Return address register. | |
154 | (RETURN_REGNUM 14) | |
155 | ; Condition code register. | |
156 | (CC_REGNUM 33) | |
157 | ; Thread local storage pointer register. | |
158 | (TP_REGNUM 36) | |
159 | ]) | |
160 | ||
35dd9a0e AK |
161 | ; Hardware register names |
162 | ||
163 | (define_constants | |
164 | [ | |
165 | ; General purpose registers | |
166 | (GPR0_REGNUM 0) | |
167 | ; Floating point registers. | |
168 | (FPR0_REGNUM 16) | |
169 | (FPR2_REGNUM 18) | |
170 | ]) | |
171 | ||
172 | ;; | |
173 | ;; PFPO GPR0 argument format | |
174 | ;; | |
175 | ||
176 | (define_constants | |
177 | [ | |
178 | ; PFPO operation type | |
179 | (PFPO_CONVERT 0x1000000) | |
180 | ; PFPO operand types | |
181 | (PFPO_OP_TYPE_SF 0x5) | |
182 | (PFPO_OP_TYPE_DF 0x6) | |
183 | (PFPO_OP_TYPE_TF 0x7) | |
184 | (PFPO_OP_TYPE_SD 0x8) | |
185 | (PFPO_OP_TYPE_DD 0x9) | |
186 | (PFPO_OP_TYPE_TD 0xa) | |
187 | ; Bitposition of operand types | |
188 | (PFPO_OP0_TYPE_SHIFT 16) | |
189 | (PFPO_OP1_TYPE_SHIFT 8) | |
190 | ]) | |
191 | ||
fd3cd001 | 192 | |
29a74354 UW |
193 | ;; Instruction operand type as used in the Principles of Operation. |
194 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 195 | |
29a74354 | 196 | (define_attr "op_type" |
963fc8d0 | 197 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" |
b628bd8e | 198 | (const_string "NN")) |
9db1d521 | 199 | |
29a74354 | 200 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 201 | |
077dab3b | 202 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 203 | cs,vs,store,sem,idiv, |
ed0e512a | 204 | imulhi,imulsi,imuldi, |
f61a2c7d AK |
205 | branch,jsr,fsimptf,fsimpdf,fsimpsf, |
206 | floadtf,floaddf,floadsf,fstoredf,fstoresf, | |
207 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 WG |
208 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
209 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, | |
210 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
211 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
212 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
213 | ftoidfp, other" | |
29a74354 UW |
214 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
215 | (eq_attr "op_type" "SS") (const_string "cs")] | |
216 | (const_string "integer"))) | |
9db1d521 | 217 | |
29a74354 UW |
218 | ;; Another attribute used for scheduling purposes: |
219 | ;; agen: Instruction uses the address generation unit | |
220 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
221 | |
222 | (define_attr "atype" "agen,reg" | |
0101708c AS |
223 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE") |
224 | (const_string "reg") | |
225 | (const_string "agen"))) | |
9db1d521 | 226 | |
9381e3f1 WG |
227 | ;; Properties concerning Z10 execution grouping and value forwarding. |
228 | ;; z10_super: instruction is superscalar. | |
229 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
230 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
231 | ;; target register. It can forward this value to a second instruction that reads | |
232 | ;; the same register if that second instruction is issued in the same group. | |
233 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
234 | ;; instruction in the S pipe writes to the register, then the T instruction | |
235 | ;; can immediately read the new value. | |
236 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
237 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
238 | ;; z10_cobra: its a compare and branch instruction | |
239 | ;; | |
240 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
241 | ||
242 | ||
243 | (define_attr "z10prop" "none, | |
244 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
245 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
246 | z10_rec, | |
247 | z10_fr, z10_fr_A3, z10_fr_E1, | |
248 | z10_c, z10_cobra" | |
249 | (const_string "none")) | |
250 | ||
251 | ||
9db1d521 HP |
252 | ;; Length in bytes. |
253 | ||
254 | (define_attr "length" "" | |
963fc8d0 AK |
255 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
256 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 257 | (const_int 6))) |
9db1d521 | 258 | |
29a74354 UW |
259 | |
260 | ;; Processor type. This attribute must exactly match the processor_type | |
261 | ;; enumeration in s390.h. The current machine description does not | |
262 | ;; distinguish between g5 and g6, but there are differences between the two | |
263 | ;; CPUs could in theory be modeled. | |
264 | ||
93538e8e | 265 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10" |
29a74354 UW |
266 | (const (symbol_ref "s390_tune"))) |
267 | ||
93538e8e | 268 | (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10" |
3af8e996 AK |
269 | (const_string "standard")) |
270 | ||
271 | (define_attr "enabled" "" | |
272 | (cond [(eq_attr "cpu_facility" "standard") | |
273 | (const_int 1) | |
274 | ||
275 | (and (eq_attr "cpu_facility" "ieee") | |
276 | (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0))) | |
277 | (const_int 1) | |
278 | ||
279 | (and (eq_attr "cpu_facility" "zarch") | |
280 | (ne (symbol_ref "TARGET_ZARCH") (const_int 0))) | |
281 | (const_int 1) | |
282 | ||
283 | (and (eq_attr "cpu_facility" "longdisp") | |
284 | (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0))) | |
285 | (const_int 1) | |
286 | ||
287 | (and (eq_attr "cpu_facility" "extimm") | |
288 | (ne (symbol_ref "TARGET_EXTIMM") (const_int 0))) | |
289 | (const_int 1) | |
290 | ||
291 | (and (eq_attr "cpu_facility" "dfp") | |
292 | (ne (symbol_ref "TARGET_DFP") (const_int 0))) | |
93538e8e AK |
293 | (const_int 1) |
294 | ||
295 | (and (eq_attr "cpu_facility" "z10") | |
296 | (ne (symbol_ref "TARGET_Z10") (const_int 0))) | |
3af8e996 AK |
297 | (const_int 1)] |
298 | (const_int 0))) | |
299 | ||
29a74354 UW |
300 | ;; Pipeline description for z900. For lack of anything better, |
301 | ;; this description is also used for the g5 and g6. | |
302 | (include "2064.md") | |
303 | ||
3443392a | 304 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
305 | (include "2084.md") |
306 | ||
9381e3f1 WG |
307 | ;; Pipeline description for z10 |
308 | (include "2097.md") | |
309 | ||
0bfc3f69 AS |
310 | ;; Predicates |
311 | (include "predicates.md") | |
312 | ||
cd8dc1f9 WG |
313 | ;; Constraint definitions |
314 | (include "constraints.md") | |
315 | ||
a8ba31f2 EC |
316 | ;; Other includes |
317 | (include "tpf.md") | |
f52c81dd | 318 | |
3abcb3a7 | 319 | ;; Iterators |
f52c81dd | 320 | |
3abcb3a7 | 321 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 322 | ;; same template. |
0387c142 WG |
323 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
324 | (SD "TARGET_HARD_DFP")]) | |
3abcb3a7 | 325 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
963fc8d0 | 326 | (define_mode_iterator FPALL [TF DF SF TD DD SD]) |
3abcb3a7 HPN |
327 | (define_mode_iterator BFP [TF DF SF]) |
328 | (define_mode_iterator DFP [TD DD]) | |
329 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
330 | (define_mode_iterator DSF [DF SF]) | |
331 | (define_mode_iterator SD_SF [SF SD]) | |
332 | (define_mode_iterator DD_DF [DF DD]) | |
333 | (define_mode_iterator TD_TF [TF TD]) | |
334 | ||
335 | ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated | |
8006eaa6 | 336 | ;; from the same template. |
3abcb3a7 | 337 | (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI]) |
8006eaa6 | 338 | |
3abcb3a7 | 339 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 340 | ;; from the same template. |
3abcb3a7 HPN |
341 | (define_mode_iterator GPR [(DI "TARGET_64BIT") SI]) |
342 | (define_mode_iterator DSI [DI SI]) | |
9db2f16d | 343 | |
3abcb3a7 | 344 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 345 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 HPN |
346 | (define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")]) |
347 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) | |
9db2f16d | 348 | |
3abcb3a7 | 349 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 350 | ;; the same template. |
3abcb3a7 | 351 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 352 | |
3abcb3a7 | 353 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 354 | ;; same template. |
3abcb3a7 | 355 | (define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI]) |
963fc8d0 | 356 | (define_mode_iterator INTALL [TI DI SI HI QI]) |
342cf42b | 357 | |
3abcb3a7 HPN |
358 | ;; This iterator allows to unify all 'bCOND' expander patterns. |
359 | (define_code_iterator COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered | |
fa77b251 AS |
360 | ordered uneq unlt ungt unle unge ltgt]) |
361 | ||
3abcb3a7 HPN |
362 | ;; This iterator allows to unify all 'sCOND' patterns. |
363 | (define_code_iterator SCOND [ltu gtu leu geu]) | |
9a91a21f | 364 | |
3abcb3a7 | 365 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 366 | ;; the same template. |
3abcb3a7 | 367 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 368 | |
3abcb3a7 HPN |
369 | ;; This iterator and attribute allow to combine most atomic operations. |
370 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
45d18331 AS |
371 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") |
372 | (plus "add") (minus "sub") (mult "nand")]) | |
373 | ||
609e7e80 AK |
374 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
375 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. | |
376 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 377 | |
609e7e80 AK |
378 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
379 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
380 | ;; SDmode. | |
381 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 382 | |
609e7e80 | 383 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
384 | ;; Likewise for "<RXe>". |
385 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
386 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
387 | ||
609e7e80 | 388 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 389 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
390 | ;; dfp variants in a single insn definition. |
391 | ||
3abcb3a7 | 392 | ;; This attribute is used to set op_type accordingly. |
609e7e80 AK |
393 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
394 | (DD "RRR") (SD "RRR")]) | |
395 | ||
3abcb3a7 | 396 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
397 | ;; first and the second operand match for bfp modes. |
398 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
399 | ||
3abcb3a7 | 400 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
401 | ;; additional operand for the dfp instructions. |
402 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
403 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
404 | ||
f5905b37 | 405 | |
85dae55a AK |
406 | ;; This attribute is used in the operand constraint list |
407 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
408 | ;; TFmode values are represented by a fp register pair. Since the | |
409 | ;; sign bit instructions only handle single source and target fp registers | |
410 | ;; these instructions can only be used for TFmode values if the source and | |
411 | ;; target operand uses the same fp register. | |
412 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
413 | ||
609e7e80 AK |
414 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
415 | ;; This is used to disable the memory alternative in TFmode patterns. | |
416 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
417 | ||
3abcb3a7 | 418 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
419 | ;; within instruction mnemonics. |
420 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
421 | ||
0387c142 WG |
422 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
423 | ;; modes and to an empty string for bfp modes. | |
424 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
425 | ||
1b48c8cc AS |
426 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
427 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
428 | ;; version only operates on one register. | |
429 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
430 | ||
431 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
432 | ;; version only operates on one register. The DImode version needs an additional | |
433 | ;; register for the assembler output. | |
434 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
435 | |
436 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
437 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
438 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
439 | ||
440 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 441 | ;; pattern itself and the corresponding function calls. |
f337b930 | 442 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
443 | |
444 | ;; This attribute handles differences in the instruction 'type' and will result | |
445 | ;; in "RRE" for DImode and "RR" for SImode. | |
446 | (define_mode_attr E [(DI "E") (SI "")]) | |
447 | ||
3298c037 AK |
448 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
449 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
450 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
451 | ||
8006eaa6 AS |
452 | ;; This attribute handles differences in the instruction 'type' and will result |
453 | ;; in "RSE" for TImode and "RS" for DImode. | |
454 | (define_mode_attr TE [(TI "E") (DI "")]) | |
455 | ||
9a91a21f AS |
456 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
457 | ;; and "lcr" in SImode. | |
458 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 459 | |
3298c037 AK |
460 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
461 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
462 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
463 | ;; variant for long displacements. | |
464 | (define_mode_attr y [(DI "g") (SI "y")]) | |
465 | ||
8006eaa6 AS |
466 | ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode |
467 | ;; and "cds" in DImode. | |
468 | (define_mode_attr tg [(TI "g") (DI "")]) | |
469 | ||
2f8f8434 AS |
470 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
471 | ;; and "cfdbr" in SImode. | |
472 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
473 | ||
f52c81dd AS |
474 | ;; ICM mask required to load MODE value into the lowest subreg |
475 | ;; of a SImode register. | |
476 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
477 | ||
f6ee577c AS |
478 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
479 | ;; HImode and "llgc" in QImode. | |
480 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
481 | ||
a1aed706 AS |
482 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
483 | ;; in SImode. | |
484 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
485 | ||
609e7e80 AK |
486 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
487 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
488 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
489 | ||
f52c81dd AS |
490 | ;; Maximum unsigned integer that fits in MODE. |
491 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
492 | ||
9db1d521 HP |
493 | ;; |
494 | ;;- Compare instructions. | |
495 | ;; | |
496 | ||
9db2f16d | 497 | (define_expand "cmp<mode>" |
ae156f85 | 498 | [(set (reg:CC CC_REGNUM) |
9db2f16d AS |
499 | (compare:CC (match_operand:GPR 0 "register_operand" "") |
500 | (match_operand:GPR 1 "general_operand" "")))] | |
9db1d521 | 501 | "" |
9db1d521 HP |
502 | { |
503 | s390_compare_op0 = operands[0]; | |
504 | s390_compare_op1 = operands[1]; | |
505 | DONE; | |
10bbf137 | 506 | }) |
9db1d521 | 507 | |
f5905b37 | 508 | (define_expand "cmp<mode>" |
ae156f85 | 509 | [(set (reg:CC CC_REGNUM) |
609e7e80 AK |
510 | (compare:CC (match_operand:FP 0 "register_operand" "") |
511 | (match_operand:FP 1 "general_operand" "")))] | |
9db1d521 | 512 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
513 | { |
514 | s390_compare_op0 = operands[0]; | |
515 | s390_compare_op1 = operands[1]; | |
516 | DONE; | |
10bbf137 | 517 | }) |
9db1d521 HP |
518 | |
519 | ||
07893d4f | 520 | ; Test-under-Mask instructions |
9db1d521 | 521 | |
07893d4f | 522 | (define_insn "*tmqi_mem" |
ae156f85 | 523 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
524 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
525 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
526 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 527 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 528 | "@ |
fc0ea003 UW |
529 | tm\t%S0,%b1 |
530 | tmy\t%S0,%b1" | |
9381e3f1 WG |
531 | [(set_attr "op_type" "SI,SIY") |
532 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 533 | |
05b9aaaa | 534 | (define_insn "*tmdi_reg" |
ae156f85 | 535 | [(set (reg CC_REGNUM) |
f19a9af7 | 536 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 537 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
538 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
539 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa | 540 | "TARGET_64BIT |
3ed99cc9 | 541 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
542 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
543 | "@ | |
544 | tmhh\t%0,%i1 | |
545 | tmhl\t%0,%i1 | |
546 | tmlh\t%0,%i1 | |
547 | tmll\t%0,%i1" | |
9381e3f1 WG |
548 | [(set_attr "op_type" "RI") |
549 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
550 | |
551 | (define_insn "*tmsi_reg" | |
ae156f85 | 552 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
553 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
554 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
555 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 556 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
557 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
558 | "@ | |
559 | tmh\t%0,%i1 | |
560 | tml\t%0,%i1" | |
729e750f WG |
561 | [(set_attr "op_type" "RI") |
562 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 563 | |
f52c81dd | 564 | (define_insn "*tm<mode>_full" |
ae156f85 | 565 | [(set (reg CC_REGNUM) |
f52c81dd AS |
566 | (compare (match_operand:HQI 0 "register_operand" "d") |
567 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 568 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 569 | "tml\t%0,<max_uint>" |
729e750f WG |
570 | [(set_attr "op_type" "RI") |
571 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 572 | |
07893d4f | 573 | |
08a5aaa2 | 574 | ; |
07893d4f | 575 | ; Load-and-Test instructions |
08a5aaa2 AS |
576 | ; |
577 | ||
c0220ea4 | 578 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
579 | |
580 | (define_insn "*tstdi_sign" | |
ae156f85 | 581 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
582 | (compare |
583 | (ashiftrt:DI | |
584 | (ashift:DI | |
585 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
586 | (const_int 32)) (const_int 32)) | |
587 | (match_operand:DI 1 "const0_operand" ""))) | |
588 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f UW |
589 | (sign_extend:DI (match_dup 0)))] |
590 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
963fc8d0 AK |
591 | "ltgfr\t%2,%0 |
592 | ltgf\t%2,%0" | |
593 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
594 | (set_attr "cpu_facility" "*,z10") |
595 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 596 | |
43a09b63 | 597 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 598 | (define_insn "*tst<mode>_extimm" |
ec24698e | 599 | [(set (reg CC_REGNUM) |
fb492564 | 600 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
601 | (match_operand:GPR 1 "const0_operand" ""))) |
602 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 603 | (match_dup 0))] |
08a5aaa2 | 604 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 605 | "@ |
08a5aaa2 AS |
606 | lt<g>r\t%2,%0 |
607 | lt<g>\t%2,%0" | |
9381e3f1 | 608 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 609 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 610 | |
43a09b63 | 611 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 612 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 613 | [(set (reg CC_REGNUM) |
fb492564 | 614 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
615 | (match_operand:GPR 1 "const0_operand" ""))) |
616 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
617 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 618 | "@ |
08a5aaa2 AS |
619 | lt<g>r\t%0,%0 |
620 | lt<g>\t%2,%0" | |
9381e3f1 | 621 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 622 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 623 | |
07893d4f | 624 | (define_insn "*tstdi" |
ae156f85 | 625 | [(set (reg CC_REGNUM) |
07893d4f UW |
626 | (compare (match_operand:DI 0 "register_operand" "d") |
627 | (match_operand:DI 1 "const0_operand" ""))) | |
628 | (set (match_operand:DI 2 "register_operand" "=d") | |
629 | (match_dup 0))] | |
ec24698e | 630 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" |
d40c829f | 631 | "ltgr\t%2,%0" |
9381e3f1 WG |
632 | [(set_attr "op_type" "RRE") |
633 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 634 | |
07893d4f | 635 | (define_insn "*tstsi" |
ae156f85 | 636 | [(set (reg CC_REGNUM) |
d3632d41 | 637 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 638 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 639 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 640 | (match_dup 0))] |
ec24698e | 641 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 642 | "@ |
d40c829f | 643 | ltr\t%2,%0 |
fc0ea003 UW |
644 | icm\t%2,15,%S0 |
645 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
646 | [(set_attr "op_type" "RR,RS,RSY") |
647 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 648 | |
07893d4f | 649 | (define_insn "*tstsi_cconly" |
ae156f85 | 650 | [(set (reg CC_REGNUM) |
d3632d41 | 651 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 652 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 653 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
654 | "s390_match_ccmode(insn, CCSmode)" |
655 | "@ | |
d40c829f | 656 | ltr\t%0,%0 |
fc0ea003 UW |
657 | icm\t%2,15,%S0 |
658 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
659 | [(set_attr "op_type" "RR,RS,RSY") |
660 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 661 | |
08a5aaa2 AS |
662 | (define_insn "*tstdi_cconly_31" |
663 | [(set (reg CC_REGNUM) | |
664 | (compare (match_operand:DI 0 "register_operand" "d") | |
665 | (match_operand:DI 1 "const0_operand" "")))] | |
666 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
667 | "srda\t%0,0" | |
668 | [(set_attr "op_type" "RS") | |
669 | (set_attr "atype" "reg")]) | |
670 | ||
43a09b63 | 671 | ; ltr, ltgr |
08a5aaa2 | 672 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 673 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
674 | (compare (match_operand:GPR 0 "register_operand" "d") |
675 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 676 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 677 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
678 | [(set_attr "op_type" "RR<E>") |
679 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 680 | |
c0220ea4 | 681 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 682 | |
f52c81dd | 683 | (define_insn "*tst<mode>CCT" |
ae156f85 | 684 | [(set (reg CC_REGNUM) |
f52c81dd AS |
685 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
686 | (match_operand:HQI 1 "const0_operand" ""))) | |
687 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
688 | (match_dup 0))] |
689 | "s390_match_ccmode(insn, CCTmode)" | |
690 | "@ | |
f52c81dd AS |
691 | icm\t%2,<icm_lo>,%S0 |
692 | icmy\t%2,<icm_lo>,%S0 | |
693 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
694 | [(set_attr "op_type" "RS,RSY,RI") |
695 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
696 | |
697 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 698 | [(set (reg CC_REGNUM) |
d3632d41 | 699 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 700 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 701 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
702 | "s390_match_ccmode(insn, CCTmode)" |
703 | "@ | |
fc0ea003 UW |
704 | icm\t%2,3,%S0 |
705 | icmy\t%2,3,%S0 | |
d40c829f | 706 | tml\t%0,65535" |
9381e3f1 WG |
707 | [(set_attr "op_type" "RS,RSY,RI") |
708 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 709 | |
3af97654 | 710 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 711 | [(set (reg CC_REGNUM) |
d3632d41 | 712 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
713 | (match_operand:QI 1 "const0_operand" "")))] |
714 | "s390_match_ccmode(insn, CCTmode)" | |
715 | "@ | |
fc0ea003 UW |
716 | cli\t%S0,0 |
717 | cliy\t%S0,0 | |
d40c829f | 718 | tml\t%0,255" |
9381e3f1 | 719 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 720 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 721 | |
f52c81dd | 722 | (define_insn "*tst<mode>" |
ae156f85 | 723 | [(set (reg CC_REGNUM) |
f52c81dd AS |
724 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
725 | (match_operand:HQI 1 "const0_operand" ""))) | |
726 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
727 | (match_dup 0))] |
728 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 729 | "@ |
f52c81dd AS |
730 | icm\t%2,<icm_lo>,%S0 |
731 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
732 | [(set_attr "op_type" "RS,RSY") |
733 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 734 | |
f52c81dd | 735 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 736 | [(set (reg CC_REGNUM) |
f52c81dd AS |
737 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
738 | (match_operand:HQI 1 "const0_operand" ""))) | |
739 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 740 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 741 | "@ |
f52c81dd AS |
742 | icm\t%2,<icm_lo>,%S0 |
743 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
744 | [(set_attr "op_type" "RS,RSY") |
745 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 746 | |
9db1d521 | 747 | |
575f7c2b UW |
748 | ; Compare (equality) instructions |
749 | ||
750 | (define_insn "*cmpdi_cct" | |
ae156f85 | 751 | [(set (reg CC_REGNUM) |
ec24698e | 752 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 753 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
e221ef54 | 754 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" |
575f7c2b UW |
755 | "@ |
756 | cgr\t%0,%1 | |
f4f41b4e | 757 | cghi\t%0,%h1 |
ec24698e | 758 | cgfi\t%0,%1 |
575f7c2b | 759 | cg\t%0,%1 |
19b63d8e | 760 | #" |
9381e3f1 WG |
761 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
762 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
763 | |
764 | (define_insn "*cmpsi_cct" | |
ae156f85 | 765 | [(set (reg CC_REGNUM) |
ec24698e UW |
766 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
767 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 768 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
769 | "@ |
770 | cr\t%0,%1 | |
f4f41b4e | 771 | chi\t%0,%h1 |
ec24698e | 772 | cfi\t%0,%1 |
575f7c2b UW |
773 | c\t%0,%1 |
774 | cy\t%0,%1 | |
19b63d8e | 775 | #" |
9381e3f1 WG |
776 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
777 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super,z10_super,*")]) | |
575f7c2b | 778 | |
07893d4f | 779 | ; Compare (signed) instructions |
4023fb28 | 780 | |
07893d4f | 781 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 782 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
783 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
784 | "d,RT,b")) | |
785 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
07893d4f | 786 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" |
4023fb28 | 787 | "@ |
d40c829f | 788 | cgfr\t%0,%1 |
963fc8d0 AK |
789 | cgf\t%0,%1 |
790 | cgfrl\t%0,%1" | |
791 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 792 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 793 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 794 | |
9381e3f1 WG |
795 | |
796 | ||
07893d4f | 797 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 798 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
799 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
800 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 801 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 802 | "@ |
d40c829f | 803 | ch\t%0,%1 |
963fc8d0 AK |
804 | chy\t%0,%1 |
805 | chrl\t%0,%1" | |
806 | [(set_attr "op_type" "RX,RXY,RIL") | |
807 | (set_attr "cpu_facility" "*,*,z10") | |
808 | (set_attr "type" "*,*,larl")]) | |
809 | ||
810 | (define_insn "*cmphi_ccs_z10" | |
811 | [(set (reg CC_REGNUM) | |
812 | (compare (match_operand:HI 0 "s_operand" "Q") | |
813 | (match_operand:HI 1 "immediate_operand" "K")))] | |
814 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
815 | "chhsi\t%0,%1" | |
816 | [(set_attr "op_type" "SIL")]) | |
817 | ||
818 | (define_insn "*cmpdi_ccs_signhi_rl" | |
819 | [(set (reg CC_REGNUM) | |
820 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
821 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
822 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
823 | "@ | |
824 | cgh\t%0,%1 | |
825 | cghrl\t%0,%1" | |
826 | [(set_attr "op_type" "RXY,RIL") | |
827 | (set_attr "type" "*,larl")]) | |
4023fb28 | 828 | |
963fc8d0 | 829 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 830 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 831 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
832 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
833 | "d,d,Q, d,d,d,d") | |
834 | (match_operand:GPR 1 "general_operand" | |
835 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 836 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 837 | "@ |
3298c037 AK |
838 | c<g>r\t%0,%1 |
839 | c<g>hi\t%0,%h1 | |
963fc8d0 | 840 | c<g>hsi\t%0,%h1 |
3298c037 AK |
841 | c<g>fi\t%0,%1 |
842 | c<g>\t%0,%1 | |
963fc8d0 AK |
843 | c<y>\t%0,%1 |
844 | c<g>rl\t%0,%1" | |
845 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
846 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
847 | (set_attr "type" "*,*,*,*,*,*,larl") |
848 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 849 | |
07893d4f UW |
850 | |
851 | ; Compare (unsigned) instructions | |
9db1d521 | 852 | |
963fc8d0 AK |
853 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
854 | [(set (reg CC_REGNUM) | |
855 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
856 | "larl_operand" "X"))) | |
857 | (match_operand:SI 0 "register_operand" "d")))] | |
858 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
859 | "clhrl\t%0,%1" | |
860 | [(set_attr "op_type" "RIL") | |
729e750f WG |
861 | (set_attr "type" "larl") |
862 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
863 | |
864 | ; clhrl, clghrl | |
865 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
866 | [(set (reg CC_REGNUM) | |
867 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
868 | "larl_operand" "X"))) | |
869 | (match_operand:GPR 0 "register_operand" "d")))] | |
870 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
871 | "cl<g>hrl\t%0,%1" | |
872 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
873 | (set_attr "type" "larl") |
874 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 875 | |
07893d4f | 876 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 877 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
878 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
879 | "d,RT,b")) | |
880 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
575f7c2b | 881 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 882 | "@ |
d40c829f | 883 | clgfr\t%0,%1 |
963fc8d0 AK |
884 | clgf\t%0,%1 |
885 | clgfrl\t%0,%1" | |
886 | [(set_attr "op_type" "RRE,RXY,RIL") | |
887 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
888 | (set_attr "type" "*,*,larl") |
889 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 890 | |
07893d4f | 891 | (define_insn "*cmpdi_ccu" |
ae156f85 | 892 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
893 | (compare (match_operand:DI 0 "nonimmediate_operand" |
894 | "d, d,d,Q, d, Q,BQ") | |
895 | (match_operand:DI 1 "general_operand" | |
896 | "d,Op,b,D,RT,BQ,Q")))] | |
e221ef54 | 897 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" |
07893d4f | 898 | "@ |
d40c829f | 899 | clgr\t%0,%1 |
ec24698e | 900 | clgfi\t%0,%1 |
963fc8d0 AK |
901 | clgrl\t%0,%1 |
902 | clghsi\t%0,%x1 | |
575f7c2b | 903 | clg\t%0,%1 |
e221ef54 | 904 | # |
19b63d8e | 905 | #" |
963fc8d0 AK |
906 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
907 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
908 | (set_attr "type" "*,*,larl,*,*,*,*") |
909 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 910 | |
07893d4f | 911 | (define_insn "*cmpsi_ccu" |
ae156f85 | 912 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
913 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
914 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 915 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 916 | "@ |
d40c829f | 917 | clr\t%0,%1 |
ec24698e | 918 | clfi\t%0,%o1 |
963fc8d0 AK |
919 | clrl\t%0,%1 |
920 | clfhsi\t%0,%x1 | |
d40c829f | 921 | cl\t%0,%1 |
575f7c2b | 922 | cly\t%0,%1 |
e221ef54 | 923 | # |
19b63d8e | 924 | #" |
963fc8d0 AK |
925 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
926 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
927 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
928 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 929 | |
07893d4f | 930 | (define_insn "*cmphi_ccu" |
ae156f85 | 931 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
932 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
933 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 934 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 935 | && !register_operand (operands[1], HImode)" |
d3632d41 | 936 | "@ |
fc0ea003 UW |
937 | clm\t%0,3,%S1 |
938 | clmy\t%0,3,%S1 | |
963fc8d0 | 939 | clhhsi\t%0,%1 |
e221ef54 | 940 | # |
19b63d8e | 941 | #" |
963fc8d0 | 942 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
943 | (set_attr "cpu_facility" "*,*,z10,*,*") |
944 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
945 | |
946 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 947 | [(set (reg CC_REGNUM) |
e221ef54 UW |
948 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
949 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 950 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 951 | && !register_operand (operands[1], QImode)" |
d3632d41 | 952 | "@ |
fc0ea003 UW |
953 | clm\t%0,1,%S1 |
954 | clmy\t%0,1,%S1 | |
955 | cli\t%S0,%b1 | |
956 | cliy\t%S0,%b1 | |
e221ef54 | 957 | # |
19b63d8e | 958 | #" |
9381e3f1 WG |
959 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
960 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
961 | |
962 | ||
19b63d8e UW |
963 | ; Block compare (CLC) instruction patterns. |
964 | ||
965 | (define_insn "*clc" | |
ae156f85 | 966 | [(set (reg CC_REGNUM) |
d4f52f0e | 967 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
968 | (match_operand:BLK 1 "memory_operand" "Q"))) |
969 | (use (match_operand 2 "const_int_operand" "n"))] | |
970 | "s390_match_ccmode (insn, CCUmode) | |
971 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 972 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 973 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
974 | |
975 | (define_split | |
ae156f85 | 976 | [(set (reg CC_REGNUM) |
19b63d8e UW |
977 | (compare (match_operand 0 "memory_operand" "") |
978 | (match_operand 1 "memory_operand" "")))] | |
979 | "reload_completed | |
980 | && s390_match_ccmode (insn, CCUmode) | |
981 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
982 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
983 | [(parallel | |
984 | [(set (match_dup 0) (match_dup 1)) | |
985 | (use (match_dup 2))])] | |
986 | { | |
987 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
988 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
989 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
990 | ||
991 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
992 | operands[0], operands[1]); | |
993 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
994 | }) | |
995 | ||
996 | ||
609e7e80 | 997 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 998 | |
609e7e80 | 999 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1000 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1001 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1002 | (compare (match_operand:FP 0 "register_operand" "f") |
1003 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1004 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1005 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1006 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1007 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1008 | |
d46f24b6 | 1009 | ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr |
f5905b37 | 1010 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1011 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1012 | (compare (match_operand:FP 0 "register_operand" "f,f") |
1013 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 1014 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1015 | "@ |
609e7e80 | 1016 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1017 | c<xde>b\t%0,%1" |
077dab3b | 1018 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 1019 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1020 | |
963fc8d0 AK |
1021 | |
1022 | ; Compare and Branch instructions | |
1023 | ||
1024 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1025 | ; The following instructions do a complementary access of their second |
1026 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1027 | (define_insn "*cmp_and_br_signed_<mode>" |
1028 | [(set (pc) | |
1029 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1030 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1031 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1032 | (label_ref (match_operand 3 "" "")) | |
1033 | (pc))) | |
1034 | (clobber (reg:CC CC_REGNUM))] | |
1035 | "TARGET_Z10" | |
1036 | { | |
1037 | if (get_attr_length (insn) == 6) | |
1038 | return which_alternative ? | |
1039 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1040 | else | |
1041 | return which_alternative ? | |
1042 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1043 | } | |
1044 | [(set_attr "op_type" "RIE") | |
1045 | (set_attr "type" "branch") | |
9381e3f1 | 1046 | (set_attr "z10prop" "z10_cobra,z10_super") |
963fc8d0 AK |
1047 | (set (attr "length") |
1048 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1049 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1050 | ; 10 byte for cgr/jg | |
1051 | ||
1052 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1053 | ; The following instructions do a complementary access of their second |
1054 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1055 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1056 | [(set (pc) | |
1057 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1058 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1059 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1060 | (label_ref (match_operand 3 "" "")) | |
1061 | (pc))) | |
1062 | (clobber (reg:CC CC_REGNUM))] | |
1063 | "TARGET_Z10" | |
1064 | { | |
1065 | if (get_attr_length (insn) == 6) | |
1066 | return which_alternative ? | |
1067 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1068 | else | |
1069 | return which_alternative ? | |
1070 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1071 | } | |
1072 | [(set_attr "op_type" "RIE") | |
1073 | (set_attr "type" "branch") | |
9381e3f1 | 1074 | (set_attr "z10prop" "z10_cobra,z10_super") |
963fc8d0 AK |
1075 | (set (attr "length") |
1076 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1077 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1078 | ; 10 byte for clgr/jg | |
1079 | ||
9db1d521 HP |
1080 | ;; |
1081 | ;;- Move instructions. | |
1082 | ;; | |
1083 | ||
1084 | ; | |
1085 | ; movti instruction pattern(s). | |
1086 | ; | |
1087 | ||
1088 | (define_insn "movti" | |
f2dc2f86 AK |
1089 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") |
1090 | (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] | |
9db1d521 | 1091 | "TARGET_64BIT" |
4023fb28 | 1092 | "@ |
fc0ea003 UW |
1093 | lmg\t%0,%N0,%S1 |
1094 | stmg\t%1,%N1,%S0 | |
4023fb28 | 1095 | # |
19b63d8e | 1096 | #" |
f2dc2f86 AK |
1097 | [(set_attr "op_type" "RSY,RSY,*,*") |
1098 | (set_attr "type" "lm,stm,*,*")]) | |
4023fb28 UW |
1099 | |
1100 | (define_split | |
1101 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1102 | (match_operand:TI 1 "general_operand" ""))] | |
1103 | "TARGET_64BIT && reload_completed | |
dc65c307 | 1104 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1105 | [(set (match_dup 2) (match_dup 4)) |
1106 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1107 | { |
dc65c307 UW |
1108 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1109 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1110 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1111 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1112 | }) | |
1113 | ||
1114 | (define_split | |
1115 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1116 | (match_operand:TI 1 "general_operand" ""))] | |
1117 | "TARGET_64BIT && reload_completed | |
1118 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
1119 | [(set (match_dup 2) (match_dup 4)) | |
1120 | (set (match_dup 3) (match_dup 5))] | |
1121 | { | |
1122 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1123 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1124 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1125 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1126 | }) | |
4023fb28 UW |
1127 | |
1128 | (define_split | |
1129 | [(set (match_operand:TI 0 "register_operand" "") | |
1130 | (match_operand:TI 1 "memory_operand" ""))] | |
1131 | "TARGET_64BIT && reload_completed | |
1132 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 1133 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1134 | { |
1135 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
1136 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1137 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1138 | }) |
1139 | ||
833cd70a AK |
1140 | |
1141 | ; | |
1142 | ; Patterns used for secondary reloads | |
1143 | ; | |
1144 | ||
963fc8d0 AK |
1145 | ; z10 provides move instructions accepting larl memory operands. |
1146 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1147 | ; These patterns are also used for unaligned SI and DI accesses. | |
1148 | ||
1149 | (define_expand "reload<INTALL:mode><P:mode>_tomem_z10" | |
1150 | [(parallel [(match_operand:INTALL 0 "memory_operand" "") | |
1151 | (match_operand:INTALL 1 "register_operand" "=d") | |
1152 | (match_operand:P 2 "register_operand" "=&a")])] | |
1153 | "TARGET_Z10" | |
1154 | { | |
1155 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1156 | DONE; | |
1157 | }) | |
1158 | ||
1159 | (define_expand "reload<INTALL:mode><P:mode>_toreg_z10" | |
1160 | [(parallel [(match_operand:INTALL 0 "register_operand" "=d") | |
1161 | (match_operand:INTALL 1 "memory_operand" "") | |
1162 | (match_operand:P 2 "register_operand" "=a")])] | |
1163 | "TARGET_Z10" | |
1164 | { | |
1165 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1166 | DONE; | |
1167 | }) | |
1168 | ||
1169 | (define_expand "reload<FPALL:mode><P:mode>_tomem_z10" | |
1170 | [(parallel [(match_operand:FPALL 0 "memory_operand" "") | |
1171 | (match_operand:FPALL 1 "register_operand" "=d") | |
1172 | (match_operand:P 2 "register_operand" "=&a")])] | |
1173 | "TARGET_Z10" | |
1174 | { | |
1175 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1176 | DONE; | |
1177 | }) | |
1178 | ||
1179 | (define_expand "reload<FPALL:mode><P:mode>_toreg_z10" | |
1180 | [(parallel [(match_operand:FPALL 0 "register_operand" "=d") | |
1181 | (match_operand:FPALL 1 "memory_operand" "") | |
1182 | (match_operand:P 2 "register_operand" "=a")])] | |
1183 | "TARGET_Z10" | |
1184 | { | |
1185 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1186 | DONE; | |
1187 | }) | |
1188 | ||
1189 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1190 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1191 | (match_operand:P 1 "larl_operand" "") | |
1192 | (match_operand:P 2 "register_operand" "=a")])] | |
1193 | "TARGET_Z10" | |
1194 | { | |
1195 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1196 | DONE; | |
1197 | }) | |
1198 | ||
833cd70a AK |
1199 | ; Handles loading a PLUS (load address) expression |
1200 | ||
1201 | (define_expand "reload<mode>_plus" | |
1202 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1203 | (match_operand:P 1 "s390_plus_operand" "") | |
1204 | (match_operand:P 2 "register_operand" "=&a")])] | |
1205 | "" | |
1206 | { | |
1207 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1208 | DONE; | |
1209 | }) | |
1210 | ||
1211 | ; Handles assessing a non-offsetable memory address | |
1212 | ||
1213 | (define_expand "reload<mode>_nonoffmem_in" | |
1214 | [(parallel [(match_operand 0 "register_operand" "") | |
1215 | (match_operand 1 "" "") | |
1216 | (match_operand:P 2 "register_operand" "=&a")])] | |
1217 | "" | |
1218 | { | |
1219 | gcc_assert (MEM_P (operands[1])); | |
1220 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1221 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1222 | emit_move_insn (operands[0], operands[1]); | |
1223 | DONE; | |
1224 | }) | |
1225 | ||
1226 | (define_expand "reload<mode>_nonoffmem_out" | |
1227 | [(parallel [(match_operand 0 "" "") | |
1228 | (match_operand 1 "register_operand" "") | |
1229 | (match_operand:P 2 "register_operand" "=&a")])] | |
1230 | "" | |
dc65c307 | 1231 | { |
9c3c3dcc | 1232 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1233 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1234 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1235 | emit_move_insn (operands[0], operands[1]); | |
1236 | DONE; | |
1237 | }) | |
9db1d521 | 1238 | |
1f9e1fc6 AK |
1239 | (define_expand "reload<mode>_PIC_addr" |
1240 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1241 | (match_operand 1 "larl_operand" "") | |
1242 | (match_operand:P 2 "register_operand" "=a")])] | |
1243 | "" | |
1244 | { | |
0a2aaacc KG |
1245 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1246 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1247 | }) |
1248 | ||
9db1d521 HP |
1249 | ; |
1250 | ; movdi instruction pattern(s). | |
1251 | ; | |
1252 | ||
9db1d521 HP |
1253 | (define_expand "movdi" |
1254 | [(set (match_operand:DI 0 "general_operand" "") | |
1255 | (match_operand:DI 1 "general_operand" ""))] | |
1256 | "" | |
9db1d521 | 1257 | { |
fd3cd001 | 1258 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1259 | if (TARGET_64BIT |
1260 | && (SYMBOLIC_CONST (operands[1]) | |
1261 | || (GET_CODE (operands[1]) == PLUS | |
1262 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1263 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1264 | emit_symbolic_move (operands); |
10bbf137 | 1265 | }) |
9db1d521 | 1266 | |
4023fb28 UW |
1267 | (define_insn "*movdi_larl" |
1268 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1269 | (match_operand:DI 1 "larl_operand" "X"))] | |
1270 | "TARGET_64BIT | |
8e509cf9 | 1271 | && !FP_REG_P (operands[0])" |
d40c829f | 1272 | "larl\t%0,%1" |
4023fb28 | 1273 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1274 | (set_attr "type" "larl") |
1275 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1276 | |
3af8e996 | 1277 | (define_insn "*movdi_64" |
85dae55a | 1278 | [(set (match_operand:DI 0 "nonimmediate_operand" |
963fc8d0 | 1279 | "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, |
f2dc2f86 | 1280 | RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") |
85dae55a | 1281 | (match_operand:DI 1 "general_operand" |
963fc8d0 | 1282 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, |
f2dc2f86 | 1283 | d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] |
3af8e996 | 1284 | "TARGET_64BIT" |
85dae55a AK |
1285 | "@ |
1286 | lghi\t%0,%h1 | |
1287 | llihh\t%0,%i1 | |
1288 | llihl\t%0,%i1 | |
1289 | llilh\t%0,%i1 | |
1290 | llill\t%0,%i1 | |
1291 | lgfi\t%0,%1 | |
1292 | llihf\t%0,%k1 | |
1293 | llilf\t%0,%k1 | |
1294 | ldgr\t%0,%1 | |
1295 | lgdr\t%0,%1 | |
1296 | lay\t%0,%a1 | |
963fc8d0 | 1297 | lgrl\t%0,%1 |
85dae55a AK |
1298 | lgr\t%0,%1 |
1299 | lg\t%0,%1 | |
1300 | stg\t%1,%0 | |
1301 | ldr\t%0,%1 | |
1302 | ld\t%0,%1 | |
1303 | ldy\t%0,%1 | |
1304 | std\t%1,%0 | |
1305 | stdy\t%1,%0 | |
963fc8d0 AK |
1306 | stgrl\t%1,%0 |
1307 | mvghi\t%0,%1 | |
85dae55a AK |
1308 | # |
1309 | # | |
1310 | stam\t%1,%N1,%S0 | |
f2dc2f86 | 1311 | lam\t%0,%N0,%S1" |
963fc8d0 | 1312 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
f2dc2f86 | 1313 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS") |
963fc8d0 AK |
1314 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
1315 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, | |
f2dc2f86 | 1316 | *,*") |
3af8e996 | 1317 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1318 | z10,*,*,*,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1319 | z10,z10,*,*,*,*") |
9381e3f1 WG |
1320 | (set_attr "z10prop" "z10_fwd_A1, |
1321 | z10_fwd_E1, | |
1322 | z10_fwd_E1, | |
1323 | z10_fwd_E1, | |
1324 | z10_fwd_E1, | |
1325 | z10_fwd_A1, | |
1326 | z10_fwd_E1, | |
1327 | z10_fwd_E1, | |
1328 | *, | |
1329 | *, | |
1330 | z10_fwd_A1, | |
1331 | z10_fwd_A3, | |
1332 | z10_fr_E1, | |
1333 | z10_fwd_A3, | |
1334 | z10_rec, | |
1335 | *, | |
1336 | *, | |
1337 | *, | |
1338 | *, | |
1339 | *, | |
1340 | z10_rec, | |
1341 | z10_super, | |
1342 | *, | |
1343 | *, | |
1344 | *, | |
9381e3f1 WG |
1345 | *") |
1346 | ]) | |
c5aa1d12 UW |
1347 | |
1348 | (define_split | |
1349 | [(set (match_operand:DI 0 "register_operand" "") | |
1350 | (match_operand:DI 1 "register_operand" ""))] | |
1351 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
1352 | [(set (match_dup 2) (match_dup 3)) | |
1353 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1354 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1355 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1356 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1357 | ||
1358 | (define_split | |
1359 | [(set (match_operand:DI 0 "register_operand" "") | |
1360 | (match_operand:DI 1 "register_operand" ""))] | |
1361 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1362 | && dead_or_set_p (insn, operands[1])" | |
1363 | [(set (match_dup 3) (match_dup 2)) | |
1364 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1365 | (set (match_dup 4) (match_dup 2))] | |
1366 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1367 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1368 | ||
1369 | (define_split | |
1370 | [(set (match_operand:DI 0 "register_operand" "") | |
1371 | (match_operand:DI 1 "register_operand" ""))] | |
1372 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1373 | && !dead_or_set_p (insn, operands[1])" | |
1374 | [(set (match_dup 3) (match_dup 2)) | |
1375 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1376 | (set (match_dup 4) (match_dup 2)) | |
1377 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1378 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1379 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1380 | |
1381 | (define_insn "*movdi_31" | |
963fc8d0 | 1382 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1383 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1384 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1385 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9db1d521 | 1386 | "!TARGET_64BIT" |
4023fb28 | 1387 | "@ |
fc0ea003 | 1388 | lm\t%0,%N0,%S1 |
c4d50129 | 1389 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1390 | stm\t%1,%N1,%S0 |
c4d50129 | 1391 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1392 | # |
1393 | # | |
d40c829f UW |
1394 | ldr\t%0,%1 |
1395 | ld\t%0,%1 | |
1396 | ldy\t%0,%1 | |
1397 | std\t%1,%0 | |
1398 | stdy\t%1,%0 | |
19b63d8e | 1399 | #" |
f2dc2f86 AK |
1400 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1401 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1402 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1403 | |
1404 | ; For a load from a symbol ref we can use one of the target registers | |
1405 | ; together with larl to load the address. | |
1406 | (define_split | |
1407 | [(set (match_operand:DI 0 "register_operand" "") | |
1408 | (match_operand:DI 1 "memory_operand" ""))] | |
1409 | "!TARGET_64BIT && reload_completed && TARGET_Z10 | |
1410 | && larl_operand (XEXP (operands[1], 0), SImode)" | |
1411 | [(set (match_dup 2) (match_dup 3)) | |
1412 | (set (match_dup 0) (match_dup 1))] | |
1413 | { | |
1414 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1415 | operands[3] = XEXP (operands[1], 0); | |
1416 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1417 | }) | |
4023fb28 UW |
1418 | |
1419 | (define_split | |
1420 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1421 | (match_operand:DI 1 "general_operand" ""))] | |
1422 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1423 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1424 | [(set (match_dup 2) (match_dup 4)) |
1425 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1426 | { |
dc65c307 UW |
1427 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1428 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1429 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1430 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1431 | }) | |
1432 | ||
1433 | (define_split | |
1434 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1435 | (match_operand:DI 1 "general_operand" ""))] | |
1436 | "!TARGET_64BIT && reload_completed | |
1437 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1438 | [(set (match_dup 2) (match_dup 4)) | |
1439 | (set (match_dup 3) (match_dup 5))] | |
1440 | { | |
1441 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1442 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1443 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1444 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1445 | }) | |
9db1d521 | 1446 | |
4023fb28 UW |
1447 | (define_split |
1448 | [(set (match_operand:DI 0 "register_operand" "") | |
1449 | (match_operand:DI 1 "memory_operand" ""))] | |
1450 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1451 | && !FP_REG_P (operands[0]) |
4023fb28 | 1452 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1453 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1454 | { |
1455 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1456 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1457 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1458 | }) |
1459 | ||
84817c5d UW |
1460 | (define_peephole2 |
1461 | [(set (match_operand:DI 0 "register_operand" "") | |
1462 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1463 | "TARGET_64BIT | |
1464 | && !FP_REG_P (operands[0]) | |
1465 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1466 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1467 | && get_pool_mode (operands[1]) == DImode | |
1468 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1469 | [(set (match_dup 0) (match_dup 2))] | |
1470 | "operands[2] = get_pool_constant (operands[1]);") | |
1471 | ||
7bdff56f UW |
1472 | (define_insn "*la_64" |
1473 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1474 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1475 | "TARGET_64BIT" | |
1476 | "@ | |
1477 | la\t%0,%a1 | |
1478 | lay\t%0,%a1" | |
1479 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1480 | (set_attr "type" "la") |
1481 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1482 | |
1483 | (define_peephole2 | |
1484 | [(parallel | |
1485 | [(set (match_operand:DI 0 "register_operand" "") | |
1486 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1487 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1488 | "TARGET_64BIT |
e1d5ee28 | 1489 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1490 | [(set (match_dup 0) (match_dup 1))] |
1491 | "") | |
1492 | ||
1493 | (define_peephole2 | |
1494 | [(set (match_operand:DI 0 "register_operand" "") | |
1495 | (match_operand:DI 1 "register_operand" "")) | |
1496 | (parallel | |
1497 | [(set (match_dup 0) | |
1498 | (plus:DI (match_dup 0) | |
1499 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1500 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1501 | "TARGET_64BIT |
1502 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1503 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1504 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1505 | "") | |
1506 | ||
9db1d521 HP |
1507 | ; |
1508 | ; movsi instruction pattern(s). | |
1509 | ; | |
1510 | ||
9db1d521 HP |
1511 | (define_expand "movsi" |
1512 | [(set (match_operand:SI 0 "general_operand" "") | |
1513 | (match_operand:SI 1 "general_operand" ""))] | |
1514 | "" | |
9db1d521 | 1515 | { |
fd3cd001 | 1516 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1517 | if (!TARGET_64BIT |
1518 | && (SYMBOLIC_CONST (operands[1]) | |
1519 | || (GET_CODE (operands[1]) == PLUS | |
1520 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1521 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1522 | emit_symbolic_move (operands); |
10bbf137 | 1523 | }) |
9db1d521 | 1524 | |
9e8327e3 UW |
1525 | (define_insn "*movsi_larl" |
1526 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1527 | (match_operand:SI 1 "larl_operand" "X"))] | |
1528 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1529 | && !FP_REG_P (operands[0])" | |
1530 | "larl\t%0,%1" | |
1531 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1532 | (set_attr "type" "larl") |
729e750f | 1533 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1534 | |
f19a9af7 | 1535 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1536 | [(set (match_operand:SI 0 "nonimmediate_operand" |
f2dc2f86 | 1537 | "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t") |
2f7e5a0d | 1538 | (match_operand:SI 1 "general_operand" |
f2dc2f86 | 1539 | "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))] |
f19a9af7 | 1540 | "TARGET_ZARCH" |
9db1d521 | 1541 | "@ |
f19a9af7 AK |
1542 | lhi\t%0,%h1 |
1543 | llilh\t%0,%i1 | |
1544 | llill\t%0,%i1 | |
ec24698e | 1545 | iilf\t%0,%o1 |
f19a9af7 | 1546 | lay\t%0,%a1 |
963fc8d0 | 1547 | lrl\t%0,%1 |
d40c829f UW |
1548 | lr\t%0,%1 |
1549 | l\t%0,%1 | |
1550 | ly\t%0,%1 | |
1551 | st\t%1,%0 | |
1552 | sty\t%1,%0 | |
1553 | ler\t%0,%1 | |
1554 | le\t%0,%1 | |
1555 | ley\t%0,%1 | |
1556 | ste\t%1,%0 | |
1557 | stey\t%1,%0 | |
c5aa1d12 UW |
1558 | ear\t%0,%1 |
1559 | sar\t%0,%1 | |
1560 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1561 | strl\t%1,%0 |
1562 | mvhi\t%0,%1 | |
f2dc2f86 | 1563 | lam\t%0,%0,%S1" |
963fc8d0 | 1564 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
f2dc2f86 | 1565 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS") |
9381e3f1 WG |
1566 | (set_attr "type" "*, |
1567 | *, | |
1568 | *, | |
1569 | *, | |
1570 | la, | |
1571 | larl, | |
1572 | lr, | |
1573 | load, | |
1574 | load, | |
1575 | store, | |
1576 | store, | |
1577 | floadsf, | |
1578 | floadsf, | |
1579 | floadsf, | |
1580 | fstoresf, | |
1581 | fstoresf, | |
1582 | *, | |
1583 | *, | |
1584 | *, | |
1585 | larl, | |
1586 | *, | |
9381e3f1 | 1587 | *") |
963fc8d0 | 1588 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1589 | *,*,longdisp,*,longdisp,*,*,*,z10,z10,*") |
9381e3f1 WG |
1590 | (set_attr "z10prop" "z10_fwd_A1, |
1591 | z10_fwd_E1, | |
1592 | z10_fwd_E1, | |
1593 | z10_fwd_A1, | |
1594 | z10_fwd_A1, | |
1595 | z10_fwd_A3, | |
1596 | z10_fr_E1, | |
1597 | z10_fwd_A3, | |
1598 | z10_fwd_A3, | |
729e750f | 1599 | z10_rec, |
9381e3f1 WG |
1600 | z10_rec, |
1601 | *, | |
1602 | *, | |
1603 | *, | |
1604 | *, | |
1605 | *, | |
1606 | z10_super_E1, | |
1607 | z10_super, | |
1608 | *, | |
1609 | z10_rec, | |
1610 | z10_super, | |
9381e3f1 | 1611 | *")]) |
f19a9af7 AK |
1612 | |
1613 | (define_insn "*movsi_esa" | |
f2dc2f86 AK |
1614 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t") |
1615 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1616 | "!TARGET_ZARCH" |
1617 | "@ | |
1618 | lhi\t%0,%h1 | |
1619 | lr\t%0,%1 | |
1620 | l\t%0,%1 | |
1621 | st\t%1,%0 | |
1622 | ler\t%0,%1 | |
1623 | le\t%0,%1 | |
1624 | ste\t%1,%0 | |
c5aa1d12 UW |
1625 | ear\t%0,%1 |
1626 | sar\t%0,%1 | |
1627 | stam\t%1,%1,%S0 | |
f2dc2f86 AK |
1628 | lam\t%0,%0,%S1" |
1629 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS") | |
1630 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*") | |
9381e3f1 WG |
1631 | (set_attr "z10prop" "z10_fwd_A1, |
1632 | z10_fr_E1, | |
1633 | z10_fwd_A3, | |
729e750f | 1634 | z10_rec, |
9381e3f1 WG |
1635 | *, |
1636 | *, | |
1637 | *, | |
1638 | z10_super_E1, | |
1639 | z10_super, | |
1640 | *, | |
9381e3f1 WG |
1641 | *") |
1642 | ]) | |
9db1d521 | 1643 | |
84817c5d UW |
1644 | (define_peephole2 |
1645 | [(set (match_operand:SI 0 "register_operand" "") | |
1646 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1647 | "!FP_REG_P (operands[0]) | |
1648 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1649 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1650 | && get_pool_mode (operands[1]) == SImode | |
1651 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1652 | [(set (match_dup 0) (match_dup 2))] | |
1653 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1654 | |
7bdff56f UW |
1655 | (define_insn "*la_31" |
1656 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1657 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1658 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1659 | "@ | |
1660 | la\t%0,%a1 | |
1661 | lay\t%0,%a1" | |
1662 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1663 | (set_attr "type" "la") |
1664 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1665 | |
1666 | (define_peephole2 | |
1667 | [(parallel | |
1668 | [(set (match_operand:SI 0 "register_operand" "") | |
1669 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1670 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1671 | "!TARGET_64BIT |
e1d5ee28 | 1672 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1673 | [(set (match_dup 0) (match_dup 1))] |
1674 | "") | |
1675 | ||
1676 | (define_peephole2 | |
1677 | [(set (match_operand:SI 0 "register_operand" "") | |
1678 | (match_operand:SI 1 "register_operand" "")) | |
1679 | (parallel | |
1680 | [(set (match_dup 0) | |
1681 | (plus:SI (match_dup 0) | |
1682 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1683 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1684 | "!TARGET_64BIT |
1685 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1686 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1687 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1688 | "") | |
1689 | ||
1690 | (define_insn "*la_31_and" | |
1691 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1692 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1693 | (const_int 2147483647)))] | |
1694 | "!TARGET_64BIT" | |
1695 | "@ | |
1696 | la\t%0,%a1 | |
1697 | lay\t%0,%a1" | |
1698 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1699 | (set_attr "type" "la") |
1700 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1701 | |
1702 | (define_insn_and_split "*la_31_and_cc" | |
1703 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1704 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1705 | (const_int 2147483647))) | |
ae156f85 | 1706 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1707 | "!TARGET_64BIT" |
1708 | "#" | |
1709 | "&& reload_completed" | |
1710 | [(set (match_dup 0) | |
1711 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1712 | "" | |
1713 | [(set_attr "op_type" "RX") | |
1714 | (set_attr "type" "la")]) | |
1715 | ||
1716 | (define_insn "force_la_31" | |
1717 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1718 | (match_operand:QI 1 "address_operand" "U,W")) | |
1719 | (use (const_int 0))] | |
1720 | "!TARGET_64BIT" | |
1721 | "@ | |
1722 | la\t%0,%a1 | |
1723 | lay\t%0,%a1" | |
1724 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
1725 | (set_attr "type" "la") |
1726 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 1727 | |
9db1d521 HP |
1728 | ; |
1729 | ; movhi instruction pattern(s). | |
1730 | ; | |
1731 | ||
02ed3c5e UW |
1732 | (define_expand "movhi" |
1733 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1734 | (match_operand:HI 1 "general_operand" ""))] | |
1735 | "" | |
1736 | { | |
2f7e5a0d | 1737 | /* Make it explicit that loading a register from memory |
02ed3c5e | 1738 | always sign-extends (at least) to SImode. */ |
b3a13419 | 1739 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 1740 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1741 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1742 | { |
1743 | rtx tmp = gen_reg_rtx (SImode); | |
1744 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1745 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1746 | operands[1] = gen_lowpart (HImode, tmp); | |
1747 | } | |
1748 | }) | |
1749 | ||
1750 | (define_insn "*movhi" | |
f2dc2f86 AK |
1751 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q") |
1752 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))] | |
9db1d521 HP |
1753 | "" |
1754 | "@ | |
d40c829f UW |
1755 | lr\t%0,%1 |
1756 | lhi\t%0,%h1 | |
1757 | lh\t%0,%1 | |
1758 | lhy\t%0,%1 | |
963fc8d0 | 1759 | lhrl\t%0,%1 |
d40c829f UW |
1760 | sth\t%1,%0 |
1761 | sthy\t%1,%0 | |
963fc8d0 | 1762 | sthrl\t%1,%0 |
f2dc2f86 AK |
1763 | mvhhi\t%0,%1" |
1764 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL") | |
1765 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*") | |
1766 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10") | |
9381e3f1 WG |
1767 | (set_attr "z10prop" "z10_fr_E1, |
1768 | z10_fwd_A1, | |
1769 | z10_super_E1, | |
1770 | z10_super_E1, | |
1771 | z10_super_E1, | |
729e750f | 1772 | z10_rec, |
9381e3f1 WG |
1773 | z10_rec, |
1774 | z10_rec, | |
f2dc2f86 | 1775 | z10_super")]) |
9db1d521 | 1776 | |
84817c5d UW |
1777 | (define_peephole2 |
1778 | [(set (match_operand:HI 0 "register_operand" "") | |
1779 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1780 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1781 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1782 | && get_pool_mode (operands[1]) == HImode | |
1783 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1784 | [(set (match_dup 0) (match_dup 2))] | |
1785 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1786 | |
9db1d521 HP |
1787 | ; |
1788 | ; movqi instruction pattern(s). | |
1789 | ; | |
1790 | ||
02ed3c5e UW |
1791 | (define_expand "movqi" |
1792 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1793 | (match_operand:QI 1 "general_operand" ""))] | |
1794 | "" | |
1795 | { | |
c19ec8f9 | 1796 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1797 | is just as fast as a QImode load. */ |
b3a13419 | 1798 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 1799 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1800 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1801 | { |
c19ec8f9 UW |
1802 | rtx tmp = gen_reg_rtx (word_mode); |
1803 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1804 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1805 | operands[1] = gen_lowpart (QImode, tmp); | |
1806 | } | |
1807 | }) | |
4023fb28 | 1808 | |
02ed3c5e | 1809 | (define_insn "*movqi" |
f2dc2f86 AK |
1810 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S") |
1811 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))] | |
9db1d521 HP |
1812 | "" |
1813 | "@ | |
d40c829f UW |
1814 | lr\t%0,%1 |
1815 | lhi\t%0,%b1 | |
1816 | ic\t%0,%1 | |
1817 | icy\t%0,%1 | |
1818 | stc\t%1,%0 | |
1819 | stcy\t%1,%0 | |
fc0ea003 | 1820 | mvi\t%S0,%b1 |
f2dc2f86 AK |
1821 | mviy\t%S0,%b1" |
1822 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY") | |
1823 | (set_attr "type" "lr,*,*,*,store,store,store,store") | |
9381e3f1 WG |
1824 | (set_attr "z10prop" "z10_fr_E1, |
1825 | z10_fwd_A1, | |
1826 | z10_super_E1, | |
1827 | z10_super_E1, | |
729e750f | 1828 | z10_rec, |
9381e3f1 WG |
1829 | z10_rec, |
1830 | z10_super, | |
f2dc2f86 | 1831 | z10_super")]) |
9db1d521 | 1832 | |
84817c5d UW |
1833 | (define_peephole2 |
1834 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1835 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1836 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1837 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1838 | && get_pool_mode (operands[1]) == QImode | |
1839 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1840 | [(set (match_dup 0) (match_dup 2))] | |
1841 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1842 | |
9db1d521 | 1843 | ; |
05b9aaaa | 1844 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1845 | ; |
1846 | ||
1847 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1848 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1849 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1850 | "" |
d3632d41 | 1851 | "@ |
d40c829f UW |
1852 | ic\t%0,%1 |
1853 | icy\t%0,%1" | |
9381e3f1 | 1854 | [(set_attr "op_type" "RX,RXY") |
729e750f | 1855 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
1856 | |
1857 | ; | |
1858 | ; movstricthi instruction pattern(s). | |
1859 | ; | |
1860 | ||
1861 | (define_insn "*movstricthi" | |
d3632d41 | 1862 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1863 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1864 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1865 | "" |
d3632d41 | 1866 | "@ |
fc0ea003 UW |
1867 | icm\t%0,3,%S1 |
1868 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
1869 | [(set_attr "op_type" "RS,RSY") |
1870 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
1871 | |
1872 | ; | |
1873 | ; movstrictsi instruction pattern(s). | |
1874 | ; | |
1875 | ||
05b9aaaa | 1876 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1877 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1878 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1879 | "TARGET_64BIT" |
1880 | "@ | |
d40c829f UW |
1881 | lr\t%0,%1 |
1882 | l\t%0,%1 | |
c5aa1d12 UW |
1883 | ly\t%0,%1 |
1884 | ear\t%0,%1" | |
1885 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
1886 | (set_attr "type" "lr,load,load,*") |
1887 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 1888 | |
f61a2c7d | 1889 | ; |
609e7e80 | 1890 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
1891 | ; |
1892 | ||
609e7e80 AK |
1893 | (define_expand "mov<mode>" |
1894 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
1895 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
1896 | "" |
1897 | "") | |
1898 | ||
609e7e80 | 1899 | (define_insn "*mov<mode>_64" |
f2dc2f86 AK |
1900 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
1901 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
f61a2c7d AK |
1902 | "TARGET_64BIT" |
1903 | "@ | |
1904 | lzxr\t%0 | |
1905 | lxr\t%0,%1 | |
1906 | # | |
1907 | # | |
1908 | lmg\t%0,%N0,%S1 | |
1909 | stmg\t%1,%N1,%S0 | |
1910 | # | |
f61a2c7d | 1911 | #" |
f2dc2f86 AK |
1912 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
1913 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")]) | |
f61a2c7d | 1914 | |
609e7e80 | 1915 | (define_insn "*mov<mode>_31" |
f2dc2f86 AK |
1916 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
1917 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
f61a2c7d AK |
1918 | "!TARGET_64BIT" |
1919 | "@ | |
1920 | lzxr\t%0 | |
1921 | lxr\t%0,%1 | |
1922 | # | |
f61a2c7d | 1923 | #" |
f2dc2f86 AK |
1924 | [(set_attr "op_type" "RRE,RRE,*,*") |
1925 | (set_attr "type" "fsimptf,fsimptf,*,*")]) | |
f61a2c7d AK |
1926 | |
1927 | ; TFmode in GPRs splitters | |
1928 | ||
1929 | (define_split | |
609e7e80 AK |
1930 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
1931 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d | 1932 | "TARGET_64BIT && reload_completed |
609e7e80 | 1933 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
1934 | [(set (match_dup 2) (match_dup 4)) |
1935 | (set (match_dup 3) (match_dup 5))] | |
1936 | { | |
609e7e80 AK |
1937 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
1938 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
1939 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
1940 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
1941 | }) |
1942 | ||
1943 | (define_split | |
609e7e80 AK |
1944 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
1945 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d | 1946 | "TARGET_64BIT && reload_completed |
609e7e80 | 1947 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
1948 | [(set (match_dup 2) (match_dup 4)) |
1949 | (set (match_dup 3) (match_dup 5))] | |
1950 | { | |
609e7e80 AK |
1951 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
1952 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
1953 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
1954 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
1955 | }) |
1956 | ||
1957 | (define_split | |
609e7e80 AK |
1958 | [(set (match_operand:TD_TF 0 "register_operand" "") |
1959 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
f61a2c7d AK |
1960 | "TARGET_64BIT && reload_completed |
1961 | && !FP_REG_P (operands[0]) | |
1962 | && !s_operand (operands[1], VOIDmode)" | |
1963 | [(set (match_dup 0) (match_dup 1))] | |
1964 | { | |
609e7e80 | 1965 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
f61a2c7d AK |
1966 | s390_load_address (addr, XEXP (operands[1], 0)); |
1967 | operands[1] = replace_equiv_address (operands[1], addr); | |
1968 | }) | |
1969 | ||
7b6baae1 | 1970 | ; TFmode in BFPs splitters |
f61a2c7d AK |
1971 | |
1972 | (define_split | |
609e7e80 AK |
1973 | [(set (match_operand:TD_TF 0 "register_operand" "") |
1974 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 1975 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
1976 | && FP_REG_P (operands[0])" |
1977 | [(set (match_dup 2) (match_dup 4)) | |
1978 | (set (match_dup 3) (match_dup 5))] | |
1979 | { | |
609e7e80 AK |
1980 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
1981 | <MODE>mode, 0); | |
1982 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
1983 | <MODE>mode, 8); | |
1984 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
1985 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
1986 | }) |
1987 | ||
1988 | (define_split | |
609e7e80 AK |
1989 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
1990 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
1991 | "reload_completed && offsettable_memref_p (operands[0]) |
1992 | && FP_REG_P (operands[1])" | |
1993 | [(set (match_dup 2) (match_dup 4)) | |
1994 | (set (match_dup 3) (match_dup 5))] | |
1995 | { | |
609e7e80 AK |
1996 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
1997 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
1998 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
1999 | <MODE>mode, 0); | |
2000 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2001 | <MODE>mode, 8); | |
f61a2c7d AK |
2002 | }) |
2003 | ||
9db1d521 | 2004 | ; |
609e7e80 | 2005 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2006 | ; |
2007 | ||
609e7e80 AK |
2008 | (define_expand "mov<mode>" |
2009 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2010 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2011 | "" |
13c025c1 | 2012 | "") |
9db1d521 | 2013 | |
609e7e80 AK |
2014 | (define_insn "*mov<mode>_64dfp" |
2015 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
f2dc2f86 | 2016 | "=f,f,f,d,f,f,R,T,d, d,RT") |
609e7e80 | 2017 | (match_operand:DD_DF 1 "general_operand" |
f2dc2f86 | 2018 | " G,f,d,f,R,T,f,f,d,RT, d"))] |
85dae55a AK |
2019 | "TARGET_64BIT && TARGET_DFP" |
2020 | "@ | |
2021 | lzdr\t%0 | |
2022 | ldr\t%0,%1 | |
2023 | ldgr\t%0,%1 | |
2024 | lgdr\t%0,%1 | |
2025 | ld\t%0,%1 | |
2026 | ldy\t%0,%1 | |
2027 | std\t%1,%0 | |
2028 | stdy\t%1,%0 | |
2029 | lgr\t%0,%1 | |
2030 | lg\t%0,%1 | |
f2dc2f86 AK |
2031 | stg\t%1,%0" |
2032 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY") | |
85dae55a | 2033 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
f2dc2f86 | 2034 | fstoredf,fstoredf,lr,load,store") |
9381e3f1 WG |
2035 | (set_attr "z10prop" "*, |
2036 | *, | |
2037 | *, | |
2038 | *, | |
2039 | *, | |
2040 | *, | |
2041 | *, | |
2042 | *, | |
2043 | z10_fr_E1, | |
2044 | z10_fwd_A3, | |
f2dc2f86 | 2045 | z10_rec") |
9381e3f1 | 2046 | ]) |
85dae55a | 2047 | |
609e7e80 | 2048 | (define_insn "*mov<mode>_64" |
f2dc2f86 AK |
2049 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT") |
2050 | (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))] | |
4023fb28 | 2051 | "TARGET_64BIT" |
9db1d521 | 2052 | "@ |
d096725d | 2053 | lzdr\t%0 |
d40c829f UW |
2054 | ldr\t%0,%1 |
2055 | ld\t%0,%1 | |
2056 | ldy\t%0,%1 | |
2057 | std\t%1,%0 | |
2058 | stdy\t%1,%0 | |
2059 | lgr\t%0,%1 | |
2060 | lg\t%0,%1 | |
f2dc2f86 AK |
2061 | stg\t%1,%0" |
2062 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY") | |
9381e3f1 | 2063 | (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, |
f2dc2f86 | 2064 | fstore<mode>,fstore<mode>,lr,load,store") |
9381e3f1 WG |
2065 | (set_attr "z10prop" "*, |
2066 | *, | |
2067 | *, | |
2068 | *, | |
2069 | *, | |
2070 | *, | |
2071 | z10_fr_E1, | |
2072 | z10_fwd_A3, | |
f2dc2f86 | 2073 | z10_rec")]) |
609e7e80 AK |
2074 | |
2075 | (define_insn "*mov<mode>_31" | |
2076 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
f2dc2f86 | 2077 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2078 | (match_operand:DD_DF 1 "general_operand" |
f2dc2f86 | 2079 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
4023fb28 | 2080 | "!TARGET_64BIT" |
9db1d521 | 2081 | "@ |
d096725d | 2082 | lzdr\t%0 |
d40c829f UW |
2083 | ldr\t%0,%1 |
2084 | ld\t%0,%1 | |
2085 | ldy\t%0,%1 | |
2086 | std\t%1,%0 | |
2087 | stdy\t%1,%0 | |
fc0ea003 | 2088 | lm\t%0,%N0,%S1 |
c4d50129 | 2089 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2090 | stm\t%1,%N1,%S0 |
c4d50129 | 2091 | stmy\t%1,%N1,%S0 |
4023fb28 | 2092 | # |
19b63d8e | 2093 | #" |
f2dc2f86 | 2094 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
9381e3f1 | 2095 | (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, |
f2dc2f86 | 2096 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")]) |
4023fb28 UW |
2097 | |
2098 | (define_split | |
609e7e80 AK |
2099 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2100 | (match_operand:DD_DF 1 "general_operand" ""))] | |
4023fb28 | 2101 | "!TARGET_64BIT && reload_completed |
609e7e80 | 2102 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2103 | [(set (match_dup 2) (match_dup 4)) |
2104 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2105 | { |
609e7e80 AK |
2106 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2107 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2108 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2109 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2110 | }) |
2111 | ||
2112 | (define_split | |
609e7e80 AK |
2113 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2114 | (match_operand:DD_DF 1 "general_operand" ""))] | |
dc65c307 | 2115 | "!TARGET_64BIT && reload_completed |
609e7e80 | 2116 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2117 | [(set (match_dup 2) (match_dup 4)) |
2118 | (set (match_dup 3) (match_dup 5))] | |
2119 | { | |
609e7e80 AK |
2120 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2121 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2122 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2123 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2124 | }) |
9db1d521 | 2125 | |
4023fb28 | 2126 | (define_split |
609e7e80 AK |
2127 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2128 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
4023fb28 | 2129 | "!TARGET_64BIT && reload_completed |
8e509cf9 | 2130 | && !FP_REG_P (operands[0]) |
4023fb28 | 2131 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2132 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2133 | { |
609e7e80 | 2134 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2135 | s390_load_address (addr, XEXP (operands[1], 0)); |
2136 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2137 | }) |
2138 | ||
9db1d521 | 2139 | ; |
609e7e80 | 2140 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2141 | ; |
2142 | ||
609e7e80 AK |
2143 | (define_insn "mov<mode>" |
2144 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
f2dc2f86 | 2145 | "=f,f,f,f,R,T,d,d,d,R,T") |
609e7e80 | 2146 | (match_operand:SD_SF 1 "general_operand" |
f2dc2f86 | 2147 | " G,f,R,T,f,f,d,R,T,d,d"))] |
4023fb28 | 2148 | "" |
9db1d521 | 2149 | "@ |
d096725d | 2150 | lzer\t%0 |
d40c829f UW |
2151 | ler\t%0,%1 |
2152 | le\t%0,%1 | |
2153 | ley\t%0,%1 | |
2154 | ste\t%1,%0 | |
2155 | stey\t%1,%0 | |
2156 | lr\t%0,%1 | |
2157 | l\t%0,%1 | |
2158 | ly\t%0,%1 | |
2159 | st\t%1,%0 | |
f2dc2f86 AK |
2160 | sty\t%1,%0" |
2161 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY") | |
9381e3f1 | 2162 | (set_attr "type" "fsimp<mode>,fload<mode>,fload<mode>,fload<mode>, |
f2dc2f86 | 2163 | fstore<mode>,fstore<mode>,lr,load,load,store,store") |
9381e3f1 WG |
2164 | (set_attr "z10prop" "*, |
2165 | *, | |
2166 | *, | |
2167 | *, | |
2168 | *, | |
2169 | *, | |
2170 | z10_fr_E1, | |
2171 | z10_fwd_A3, | |
2172 | z10_fwd_A3, | |
729e750f | 2173 | z10_rec, |
f2dc2f86 | 2174 | z10_rec")]) |
4023fb28 | 2175 | |
9dc62c00 AK |
2176 | ; |
2177 | ; movcc instruction pattern | |
2178 | ; | |
2179 | ||
2180 | (define_insn "movcc" | |
2181 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
2182 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
2183 | "" | |
2184 | "@ | |
2185 | lr\t%0,%1 | |
2186 | tmh\t%1,12288 | |
2187 | ipm\t%0 | |
2188 | st\t%0,%1 | |
2189 | sty\t%0,%1 | |
2190 | l\t%1,%0 | |
2191 | ly\t%1,%0" | |
8dd3b235 | 2192 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
9381e3f1 | 2193 | (set_attr "type" "lr,*,*,store,store,load,load") |
729e750f | 2194 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")]) |
9dc62c00 | 2195 | |
19b63d8e UW |
2196 | ; |
2197 | ; Block move (MVC) patterns. | |
2198 | ; | |
2199 | ||
2200 | (define_insn "*mvc" | |
2201 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2202 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2203 | (use (match_operand 2 "const_int_operand" "n"))] | |
2204 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2205 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2206 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2207 | |
19b63d8e UW |
2208 | (define_peephole2 |
2209 | [(parallel | |
2210 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2211 | (match_operand:BLK 1 "memory_operand" "")) | |
2212 | (use (match_operand 2 "const_int_operand" ""))]) | |
2213 | (parallel | |
2214 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2215 | (match_operand:BLK 4 "memory_operand" "")) | |
2216 | (use (match_operand 5 "const_int_operand" ""))])] | |
2217 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2218 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2219 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2220 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2221 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2222 | [(parallel | |
2223 | [(set (match_dup 6) (match_dup 7)) | |
2224 | (use (match_dup 8))])] | |
2225 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2226 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2227 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2228 | ||
2229 | ||
9db1d521 HP |
2230 | ; |
2231 | ; load_multiple pattern(s). | |
2232 | ; | |
22ea6b4f UW |
2233 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2234 | ; we currently support load_multiple/store_multiple only after reload. | |
2235 | ; | |
9db1d521 HP |
2236 | |
2237 | (define_expand "load_multiple" | |
2238 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2239 | (match_operand 1 "" "")) | |
2240 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2241 | "reload_completed" |
9db1d521 | 2242 | { |
c19ec8f9 | 2243 | enum machine_mode mode; |
9db1d521 HP |
2244 | int regno; |
2245 | int count; | |
2246 | rtx from; | |
4023fb28 | 2247 | int i, off; |
9db1d521 HP |
2248 | |
2249 | /* Support only loading a constant number of fixed-point registers from | |
2250 | memory and only bother with this if more than two */ | |
2251 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2252 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2253 | || INTVAL (operands[2]) > 16 |
2254 | || GET_CODE (operands[1]) != MEM | |
2255 | || GET_CODE (operands[0]) != REG | |
2256 | || REGNO (operands[0]) >= 16) | |
2257 | FAIL; | |
2258 | ||
2259 | count = INTVAL (operands[2]); | |
2260 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
2261 | mode = GET_MODE (operands[0]); |
2262 | if (mode != SImode && mode != word_mode) | |
2263 | FAIL; | |
9db1d521 HP |
2264 | |
2265 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2266 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2267 | { |
2268 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2269 | { | |
2270 | from = XEXP (operands[1], 0); | |
2271 | off = 0; | |
2272 | } | |
2273 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2274 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2275 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2276 | { | |
2277 | from = XEXP (XEXP (operands[1], 0), 0); | |
2278 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2279 | } | |
2280 | else | |
2281 | FAIL; | |
4023fb28 UW |
2282 | } |
2283 | else | |
2284 | { | |
2285 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2286 | off = 0; | |
2287 | } | |
9db1d521 HP |
2288 | |
2289 | for (i = 0; i < count; i++) | |
2290 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
2291 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
2292 | change_address (operands[1], mode, | |
2293 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2294 | }) |
9db1d521 HP |
2295 | |
2296 | (define_insn "*load_multiple_di" | |
2297 | [(match_parallel 0 "load_multiple_operation" | |
2298 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2299 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 2300 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
2301 | { |
2302 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2303 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2304 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2305 | } |
d3632d41 | 2306 | [(set_attr "op_type" "RSY") |
4023fb28 | 2307 | (set_attr "type" "lm")]) |
9db1d521 HP |
2308 | |
2309 | (define_insn "*load_multiple_si" | |
2310 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2311 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2312 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2313 | "reload_completed" |
9db1d521 HP |
2314 | { |
2315 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2316 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2317 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2318 | } |
d3632d41 | 2319 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2320 | (set_attr "type" "lm")]) |
9db1d521 HP |
2321 | |
2322 | ; | |
c7453384 | 2323 | ; store multiple pattern(s). |
9db1d521 HP |
2324 | ; |
2325 | ||
2326 | (define_expand "store_multiple" | |
2327 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2328 | (match_operand 1 "" "")) | |
2329 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2330 | "reload_completed" |
9db1d521 | 2331 | { |
c19ec8f9 | 2332 | enum machine_mode mode; |
9db1d521 HP |
2333 | int regno; |
2334 | int count; | |
2335 | rtx to; | |
4023fb28 | 2336 | int i, off; |
9db1d521 HP |
2337 | |
2338 | /* Support only storing a constant number of fixed-point registers to | |
2339 | memory and only bother with this if more than two. */ | |
2340 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2341 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2342 | || INTVAL (operands[2]) > 16 |
2343 | || GET_CODE (operands[0]) != MEM | |
2344 | || GET_CODE (operands[1]) != REG | |
2345 | || REGNO (operands[1]) >= 16) | |
2346 | FAIL; | |
2347 | ||
2348 | count = INTVAL (operands[2]); | |
2349 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
2350 | mode = GET_MODE (operands[1]); |
2351 | if (mode != SImode && mode != word_mode) | |
2352 | FAIL; | |
9db1d521 HP |
2353 | |
2354 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2355 | |
b3a13419 | 2356 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2357 | { |
2358 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2359 | { | |
2360 | to = XEXP (operands[0], 0); | |
2361 | off = 0; | |
2362 | } | |
2363 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2364 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2365 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2366 | { | |
2367 | to = XEXP (XEXP (operands[0], 0), 0); | |
2368 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2369 | } | |
2370 | else | |
2371 | FAIL; | |
4023fb28 | 2372 | } |
c7453384 | 2373 | else |
4023fb28 UW |
2374 | { |
2375 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2376 | off = 0; | |
2377 | } | |
9db1d521 HP |
2378 | |
2379 | for (i = 0; i < count; i++) | |
2380 | XVECEXP (operands[3], 0, i) | |
2381 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
2382 | change_address (operands[0], mode, |
2383 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
2384 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 2385 | }) |
9db1d521 HP |
2386 | |
2387 | (define_insn "*store_multiple_di" | |
2388 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2389 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2390 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 2391 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
2392 | { |
2393 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2394 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2395 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2396 | } |
d3632d41 | 2397 | [(set_attr "op_type" "RSY") |
4023fb28 | 2398 | (set_attr "type" "stm")]) |
9db1d521 HP |
2399 | |
2400 | ||
2401 | (define_insn "*store_multiple_si" | |
2402 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2403 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2404 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2405 | "reload_completed" |
9db1d521 HP |
2406 | { |
2407 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2408 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2409 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2410 | } |
d3632d41 | 2411 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2412 | (set_attr "type" "stm")]) |
9db1d521 HP |
2413 | |
2414 | ;; | |
2415 | ;; String instructions. | |
2416 | ;; | |
2417 | ||
963fc8d0 AK |
2418 | (define_insn "*execute_rl" |
2419 | [(match_parallel 0 "" | |
2420 | [(unspec [(match_operand 1 "register_operand" "a") | |
2421 | (match_operand 2 "" "") | |
2422 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2423 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2424 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2425 | "exrl\t%1,%3" | |
2426 | [(set_attr "op_type" "RIL") | |
2427 | (set_attr "type" "cs")]) | |
2428 | ||
9bb86f41 UW |
2429 | (define_insn "*execute" |
2430 | [(match_parallel 0 "" | |
2431 | [(unspec [(match_operand 1 "register_operand" "a") | |
2432 | (match_operand:BLK 2 "memory_operand" "R") | |
2433 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2434 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2435 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2436 | "ex\t%1,%2" | |
29a74354 UW |
2437 | [(set_attr "op_type" "RX") |
2438 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2439 | |
2440 | ||
91d39d71 UW |
2441 | ; |
2442 | ; strlenM instruction pattern(s). | |
2443 | ; | |
2444 | ||
9db2f16d | 2445 | (define_expand "strlen<mode>" |
ccbdc0d4 | 2446 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2447 | (parallel |
91d39d71 | 2448 | [(set (match_dup 4) |
9db2f16d | 2449 | (unspec:P [(const_int 0) |
91d39d71 | 2450 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2451 | (reg:SI 0) |
91d39d71 | 2452 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2453 | (clobber (scratch:P)) |
ae156f85 | 2454 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2455 | (parallel |
9db2f16d AS |
2456 | [(set (match_operand:P 0 "register_operand" "") |
2457 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2458 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2459 | "" |
91d39d71 | 2460 | { |
9db2f16d AS |
2461 | operands[4] = gen_reg_rtx (Pmode); |
2462 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2463 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2464 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2465 | }) | |
2466 | ||
9db2f16d AS |
2467 | (define_insn "*strlen<mode>" |
2468 | [(set (match_operand:P 0 "register_operand" "=a") | |
2469 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2470 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2471 | (reg:SI 0) |
91d39d71 | 2472 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2473 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2474 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2475 | "" |
91d39d71 | 2476 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2477 | [(set_attr "length" "8") |
2478 | (set_attr "type" "vs")]) | |
91d39d71 | 2479 | |
ccbdc0d4 AS |
2480 | ; |
2481 | ; cmpstrM instruction pattern(s). | |
2482 | ; | |
2483 | ||
2484 | (define_expand "cmpstrsi" | |
2485 | [(set (reg:SI 0) (const_int 0)) | |
2486 | (parallel | |
2487 | [(clobber (match_operand 3 "" "")) | |
2488 | (clobber (match_dup 4)) | |
2489 | (set (reg:CCU CC_REGNUM) | |
2490 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2491 | (match_operand:BLK 2 "memory_operand" ""))) | |
2492 | (use (reg:SI 0))]) | |
2493 | (parallel | |
2494 | [(set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 2495 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT)) |
ccbdc0d4 AS |
2496 | (clobber (reg:CC CC_REGNUM))])] |
2497 | "" | |
2498 | { | |
2499 | /* As the result of CMPINT is inverted compared to what we need, | |
2500 | we have to swap the operands. */ | |
2501 | rtx op1 = operands[2]; | |
2502 | rtx op2 = operands[1]; | |
2503 | rtx addr1 = gen_reg_rtx (Pmode); | |
2504 | rtx addr2 = gen_reg_rtx (Pmode); | |
2505 | ||
2506 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2507 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2508 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2509 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2510 | operands[3] = addr1; | |
2511 | operands[4] = addr2; | |
2512 | }) | |
2513 | ||
2514 | (define_insn "*cmpstr<mode>" | |
2515 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2516 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2517 | (set (reg:CCU CC_REGNUM) | |
2518 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2519 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2520 | (use (reg:SI 0))] | |
2521 | "" | |
2522 | "clst\t%0,%1\;jo\t.-4" | |
2523 | [(set_attr "length" "8") | |
2524 | (set_attr "type" "vs")]) | |
9381e3f1 | 2525 | |
742090fc AS |
2526 | ; |
2527 | ; movstr instruction pattern. | |
2528 | ; | |
2529 | ||
2530 | (define_expand "movstr" | |
2531 | [(set (reg:SI 0) (const_int 0)) | |
9381e3f1 | 2532 | (parallel |
742090fc AS |
2533 | [(clobber (match_dup 3)) |
2534 | (set (match_operand:BLK 1 "memory_operand" "") | |
2535 | (match_operand:BLK 2 "memory_operand" "")) | |
2536 | (set (match_operand 0 "register_operand" "") | |
9381e3f1 | 2537 | (unspec [(match_dup 1) |
742090fc AS |
2538 | (match_dup 2) |
2539 | (reg:SI 0)] UNSPEC_MVST)) | |
2540 | (clobber (reg:CC CC_REGNUM))])] | |
2541 | "" | |
2542 | { | |
2543 | rtx addr1 = gen_reg_rtx (Pmode); | |
2544 | rtx addr2 = gen_reg_rtx (Pmode); | |
2545 | ||
2546 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2547 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2548 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2549 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2550 | operands[3] = addr2; | |
2551 | }) | |
2552 | ||
2553 | (define_insn "*movstr" | |
2554 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2555 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2556 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2557 | (set (match_operand:P 0 "register_operand" "=d") | |
9381e3f1 | 2558 | (unspec [(mem:BLK (match_dup 1)) |
742090fc AS |
2559 | (mem:BLK (match_dup 3)) |
2560 | (reg:SI 0)] UNSPEC_MVST)) | |
2561 | (clobber (reg:CC CC_REGNUM))] | |
2562 | "" | |
2563 | "mvst\t%1,%2\;jo\t.-4" | |
2564 | [(set_attr "length" "8") | |
2565 | (set_attr "type" "vs")]) | |
9381e3f1 | 2566 | |
742090fc | 2567 | |
9db1d521 | 2568 | ; |
70128ad9 | 2569 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2570 | ; |
2571 | ||
9db2f16d | 2572 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2573 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2574 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2575 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2576 | (match_operand 3 "" "")] |
2577 | "" | |
70128ad9 | 2578 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2579 | |
ecbe845e UW |
2580 | ; Move a block that is up to 256 bytes in length. |
2581 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2582 | |
70128ad9 | 2583 | (define_expand "movmem_short" |
b9404c99 UW |
2584 | [(parallel |
2585 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2586 | (match_operand:BLK 1 "memory_operand" "")) | |
2587 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2588 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2589 | (clobber (match_dup 3))])] |
2590 | "" | |
2591 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2592 | |
70128ad9 | 2593 | (define_insn "*movmem_short" |
963fc8d0 AK |
2594 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
2595 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2596 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2597 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
2598 | (clobber (match_scratch 4 "=X,X,X,&a"))] | |
b9404c99 | 2599 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2600 | && GET_MODE (operands[4]) == Pmode" |
2601 | "#" | |
963fc8d0 AK |
2602 | [(set_attr "type" "cs") |
2603 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
ecbe845e | 2604 | |
9bb86f41 UW |
2605 | (define_split |
2606 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2607 | (match_operand:BLK 1 "memory_operand" "")) | |
2608 | (use (match_operand 2 "const_int_operand" "")) | |
2609 | (use (match_operand 3 "immediate_operand" "")) | |
2610 | (clobber (scratch))] | |
2611 | "reload_completed" | |
2612 | [(parallel | |
2613 | [(set (match_dup 0) (match_dup 1)) | |
2614 | (use (match_dup 2))])] | |
2615 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2616 | |
9bb86f41 UW |
2617 | (define_split |
2618 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2619 | (match_operand:BLK 1 "memory_operand" "")) | |
2620 | (use (match_operand 2 "register_operand" "")) | |
2621 | (use (match_operand 3 "memory_operand" "")) | |
2622 | (clobber (scratch))] | |
2623 | "reload_completed" | |
2624 | [(parallel | |
2625 | [(unspec [(match_dup 2) (match_dup 3) | |
2626 | (const_int 0)] UNSPEC_EXECUTE) | |
2627 | (set (match_dup 0) (match_dup 1)) | |
2628 | (use (const_int 1))])] | |
2629 | "") | |
2630 | ||
963fc8d0 AK |
2631 | (define_split |
2632 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2633 | (match_operand:BLK 1 "memory_operand" "")) | |
2634 | (use (match_operand 2 "register_operand" "")) | |
2635 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2636 | (clobber (scratch))] | |
2637 | "TARGET_Z10 && reload_completed" | |
2638 | [(parallel | |
2639 | [(unspec [(match_dup 2) (const_int 0) | |
2640 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2641 | (set (match_dup 0) (match_dup 1)) | |
2642 | (use (const_int 1))])] | |
2643 | "operands[3] = gen_label_rtx ();") | |
2644 | ||
9bb86f41 UW |
2645 | (define_split |
2646 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2647 | (match_operand:BLK 1 "memory_operand" "")) | |
2648 | (use (match_operand 2 "register_operand" "")) | |
2649 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2650 | (clobber (match_operand 3 "register_operand" ""))] | |
2651 | "reload_completed && TARGET_CPU_ZARCH" | |
2652 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2653 | (parallel | |
9381e3f1 | 2654 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
2655 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
2656 | (set (match_dup 0) (match_dup 1)) | |
2657 | (use (const_int 1))])] | |
2658 | "operands[4] = gen_label_rtx ();") | |
2659 | ||
a41c6c53 | 2660 | ; Move a block of arbitrary length. |
9db1d521 | 2661 | |
70128ad9 | 2662 | (define_expand "movmem_long" |
b9404c99 UW |
2663 | [(parallel |
2664 | [(clobber (match_dup 2)) | |
2665 | (clobber (match_dup 3)) | |
2666 | (set (match_operand:BLK 0 "memory_operand" "") | |
2667 | (match_operand:BLK 1 "memory_operand" "")) | |
2668 | (use (match_operand 2 "general_operand" "")) | |
2669 | (use (match_dup 3)) | |
ae156f85 | 2670 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2671 | "" |
2672 | { | |
2673 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2674 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2675 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2676 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2677 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2678 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2679 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2680 | ||
c41c1387 | 2681 | emit_clobber (reg0); |
b9404c99 UW |
2682 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2683 | emit_move_insn (len0, operands[2]); | |
2684 | ||
c41c1387 | 2685 | emit_clobber (reg1); |
b9404c99 UW |
2686 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2687 | emit_move_insn (len1, operands[2]); | |
2688 | ||
2689 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2690 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2691 | operands[2] = reg0; | |
2692 | operands[3] = reg1; | |
2693 | }) | |
2694 | ||
a1aed706 AS |
2695 | (define_insn "*movmem_long" |
2696 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2697 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2698 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2699 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2700 | (use (match_dup 2)) |
2701 | (use (match_dup 3)) | |
ae156f85 | 2702 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2703 | "" |
d40c829f | 2704 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2705 | [(set_attr "length" "8") |
2706 | (set_attr "type" "vs")]) | |
9db1d521 | 2707 | |
638e37c2 WG |
2708 | |
2709 | ; | |
2710 | ; Test data class. | |
2711 | ; | |
2712 | ||
0f67fa83 WG |
2713 | (define_expand "signbit<mode>2" |
2714 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2715 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2716 | (match_dup 2)] | |
0f67fa83 WG |
2717 | UNSPEC_TDC_INSN)) |
2718 | (set (match_operand:SI 0 "register_operand" "=d") | |
2719 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
2720 | "TARGET_HARD_FLOAT" | |
2721 | { | |
2722 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
2723 | }) | |
2724 | ||
638e37c2 WG |
2725 | (define_expand "isinf<mode>2" |
2726 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2727 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2728 | (match_dup 2)] | |
638e37c2 WG |
2729 | UNSPEC_TDC_INSN)) |
2730 | (set (match_operand:SI 0 "register_operand" "=d") | |
2731 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
142cd70f | 2732 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
2733 | { |
2734 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
2735 | }) | |
2736 | ||
2737 | ; This insn is used to generate all variants of the Test Data Class | |
2738 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
2739 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 2740 | ; specifying the required test(s). |
638e37c2 WG |
2741 | ; |
2742 | (define_insn "*TDC_insn_<mode>" | |
2743 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 2744 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 2745 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 2746 | "TARGET_HARD_FLOAT" |
0387c142 | 2747 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 2748 | [(set_attr "op_type" "RXE") |
9381e3f1 | 2749 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 WG |
2750 | |
2751 | (define_insn_and_split "*ccz_to_int" | |
2752 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2753 | (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")] | |
2754 | UNSPEC_CCZ_TO_INT))] | |
2755 | "" | |
2756 | "#" | |
2757 | "reload_completed" | |
2758 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
2759 | ||
2760 | ||
9db1d521 | 2761 | ; |
57e84f18 | 2762 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2763 | ; |
2764 | ||
57e84f18 | 2765 | (define_expand "setmem<mode>" |
a41c6c53 | 2766 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2767 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2768 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2769 | (match_operand 3 "" "")] |
a41c6c53 | 2770 | "" |
6d057022 | 2771 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2772 | |
a41c6c53 | 2773 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2774 | ; The block length is taken as (operands[1] % 256) + 1. |
2775 | ||
70128ad9 | 2776 | (define_expand "clrmem_short" |
b9404c99 UW |
2777 | [(parallel |
2778 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2779 | (const_int 0)) | |
2780 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2781 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2782 | (clobber (match_dup 2)) |
ae156f85 | 2783 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2784 | "" |
2785 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2786 | |
70128ad9 | 2787 | (define_insn "*clrmem_short" |
963fc8d0 | 2788 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 2789 | (const_int 0)) |
963fc8d0 AK |
2790 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
2791 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
2792 | (clobber (match_scratch 3 "=X,X,X,&a")) | |
ae156f85 | 2793 | (clobber (reg:CC CC_REGNUM))] |
b9404c99 | 2794 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
2795 | && GET_MODE (operands[3]) == Pmode" |
2796 | "#" | |
963fc8d0 AK |
2797 | [(set_attr "type" "cs") |
2798 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9bb86f41 UW |
2799 | |
2800 | (define_split | |
2801 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2802 | (const_int 0)) | |
2803 | (use (match_operand 1 "const_int_operand" "")) | |
2804 | (use (match_operand 2 "immediate_operand" "")) | |
2805 | (clobber (scratch)) | |
ae156f85 | 2806 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2807 | "reload_completed" |
2808 | [(parallel | |
2809 | [(set (match_dup 0) (const_int 0)) | |
2810 | (use (match_dup 1)) | |
ae156f85 | 2811 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2812 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2813 | |
9bb86f41 UW |
2814 | (define_split |
2815 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2816 | (const_int 0)) | |
2817 | (use (match_operand 1 "register_operand" "")) | |
2818 | (use (match_operand 2 "memory_operand" "")) | |
2819 | (clobber (scratch)) | |
ae156f85 | 2820 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2821 | "reload_completed" |
2822 | [(parallel | |
2823 | [(unspec [(match_dup 1) (match_dup 2) | |
2824 | (const_int 0)] UNSPEC_EXECUTE) | |
2825 | (set (match_dup 0) (const_int 0)) | |
2826 | (use (const_int 1)) | |
ae156f85 | 2827 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2828 | "") |
9db1d521 | 2829 | |
963fc8d0 AK |
2830 | (define_split |
2831 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2832 | (const_int 0)) | |
2833 | (use (match_operand 1 "register_operand" "")) | |
2834 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2835 | (clobber (scratch)) | |
2836 | (clobber (reg:CC CC_REGNUM))] | |
2837 | "TARGET_Z10 && reload_completed" | |
2838 | [(parallel | |
2839 | [(unspec [(match_dup 1) (const_int 0) | |
2840 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2841 | (set (match_dup 0) (const_int 0)) | |
2842 | (use (const_int 1)) | |
2843 | (clobber (reg:CC CC_REGNUM))])] | |
2844 | "operands[3] = gen_label_rtx ();") | |
2845 | ||
9bb86f41 UW |
2846 | (define_split |
2847 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2848 | (const_int 0)) | |
2849 | (use (match_operand 1 "register_operand" "")) | |
2850 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2851 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2852 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2853 | "reload_completed && TARGET_CPU_ZARCH" |
2854 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2855 | (parallel | |
9381e3f1 | 2856 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
2857 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
2858 | (set (match_dup 0) (const_int 0)) | |
2859 | (use (const_int 1)) | |
ae156f85 | 2860 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2861 | "operands[3] = gen_label_rtx ();") |
2862 | ||
9381e3f1 | 2863 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2864 | |
6d057022 | 2865 | (define_expand "setmem_long" |
b9404c99 UW |
2866 | [(parallel |
2867 | [(clobber (match_dup 1)) | |
2868 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 2869 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 2870 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2871 | (use (match_dup 3)) |
ae156f85 | 2872 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2873 | "" |
a41c6c53 | 2874 | { |
b9404c99 UW |
2875 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2876 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2877 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2878 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2879 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2880 | |
c41c1387 | 2881 | emit_clobber (reg0); |
b9404c99 UW |
2882 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2883 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2884 | |
b9404c99 | 2885 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2886 | |
b9404c99 UW |
2887 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2888 | operands[1] = reg0; | |
6d057022 | 2889 | operands[3] = reg1; |
b9404c99 | 2890 | }) |
a41c6c53 | 2891 | |
6d057022 | 2892 | (define_insn "*setmem_long" |
a1aed706 | 2893 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 2894 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 2895 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 2896 | (use (match_dup 3)) |
a1aed706 | 2897 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2898 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2899 | "" |
6d057022 | 2900 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
2901 | [(set_attr "length" "8") |
2902 | (set_attr "type" "vs")]) | |
9db1d521 | 2903 | |
4989e88a AK |
2904 | (define_insn "*setmem_long_and" |
2905 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2906 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
2907 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
2908 | (match_operand 4 "const_int_operand" "n"))) | |
2909 | (use (match_dup 3)) | |
2910 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
2911 | (clobber (reg:CC CC_REGNUM))] | |
2912 | "(INTVAL (operands[4]) & 255) == 255" | |
2913 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
2914 | [(set_attr "length" "8") | |
2915 | (set_attr "type" "vs")]) | |
9db1d521 | 2916 | ; |
358b8f01 | 2917 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2918 | ; |
2919 | ||
358b8f01 | 2920 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2921 | [(set (match_operand:SI 0 "register_operand" "") |
2922 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2923 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2924 | (use (match_operand:SI 3 "general_operand" "")) | |
2925 | (use (match_operand:SI 4 "" ""))] | |
2926 | "" | |
c7453384 | 2927 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2928 | operands[2], operands[3]); DONE;") |
9db1d521 | 2929 | |
a41c6c53 UW |
2930 | ; Compare a block that is up to 256 bytes in length. |
2931 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2932 | |
b9404c99 UW |
2933 | (define_expand "cmpmem_short" |
2934 | [(parallel | |
ae156f85 | 2935 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 2936 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2937 | (match_operand:BLK 1 "memory_operand" ""))) |
2938 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2939 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2940 | (clobber (match_dup 3))])] |
2941 | "" | |
2942 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2943 | |
b9404c99 | 2944 | (define_insn "*cmpmem_short" |
ae156f85 | 2945 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
2946 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
2947 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
2948 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2949 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
2950 | (clobber (match_scratch 4 "=X,X,X,&a"))] | |
b9404c99 | 2951 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2952 | && GET_MODE (operands[4]) == Pmode" |
2953 | "#" | |
963fc8d0 AK |
2954 | [(set_attr "type" "cs") |
2955 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9db1d521 | 2956 | |
9bb86f41 | 2957 | (define_split |
ae156f85 | 2958 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2959 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2960 | (match_operand:BLK 1 "memory_operand" ""))) | |
2961 | (use (match_operand 2 "const_int_operand" "")) | |
2962 | (use (match_operand 3 "immediate_operand" "")) | |
2963 | (clobber (scratch))] | |
2964 | "reload_completed" | |
2965 | [(parallel | |
ae156f85 | 2966 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2967 | (use (match_dup 2))])] |
2968 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2969 | |
9bb86f41 | 2970 | (define_split |
ae156f85 | 2971 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2972 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2973 | (match_operand:BLK 1 "memory_operand" ""))) | |
2974 | (use (match_operand 2 "register_operand" "")) | |
2975 | (use (match_operand 3 "memory_operand" "")) | |
2976 | (clobber (scratch))] | |
2977 | "reload_completed" | |
2978 | [(parallel | |
2979 | [(unspec [(match_dup 2) (match_dup 3) | |
2980 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 2981 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2982 | (use (const_int 1))])] |
2983 | "") | |
2984 | ||
963fc8d0 AK |
2985 | (define_split |
2986 | [(set (reg:CCU CC_REGNUM) | |
2987 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2988 | (match_operand:BLK 1 "memory_operand" ""))) | |
2989 | (use (match_operand 2 "register_operand" "")) | |
2990 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2991 | (clobber (scratch))] | |
2992 | "TARGET_Z10 && reload_completed" | |
2993 | [(parallel | |
2994 | [(unspec [(match_dup 2) (const_int 0) | |
2995 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2996 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
2997 | (use (const_int 1))])] | |
2998 | "operands[4] = gen_label_rtx ();") | |
2999 | ||
9bb86f41 | 3000 | (define_split |
ae156f85 | 3001 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3002 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3003 | (match_operand:BLK 1 "memory_operand" ""))) | |
3004 | (use (match_operand 2 "register_operand" "")) | |
3005 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3006 | (clobber (match_operand 3 "register_operand" ""))] | |
3007 | "reload_completed && TARGET_CPU_ZARCH" | |
3008 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3009 | (parallel | |
9381e3f1 | 3010 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3011 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3012 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3013 | (use (const_int 1))])] |
3014 | "operands[4] = gen_label_rtx ();") | |
3015 | ||
a41c6c53 | 3016 | ; Compare a block of arbitrary length. |
9db1d521 | 3017 | |
b9404c99 UW |
3018 | (define_expand "cmpmem_long" |
3019 | [(parallel | |
3020 | [(clobber (match_dup 2)) | |
3021 | (clobber (match_dup 3)) | |
ae156f85 | 3022 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3023 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3024 | (match_operand:BLK 1 "memory_operand" ""))) |
3025 | (use (match_operand 2 "general_operand" "")) | |
3026 | (use (match_dup 3))])] | |
3027 | "" | |
3028 | { | |
3029 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
3030 | rtx reg0 = gen_reg_rtx (dword_mode); | |
3031 | rtx reg1 = gen_reg_rtx (dword_mode); | |
3032 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
3033 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
3034 | rtx len0 = gen_lowpart (Pmode, reg0); | |
3035 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3036 | ||
c41c1387 | 3037 | emit_clobber (reg0); |
b9404c99 UW |
3038 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3039 | emit_move_insn (len0, operands[2]); | |
3040 | ||
c41c1387 | 3041 | emit_clobber (reg1); |
b9404c99 UW |
3042 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3043 | emit_move_insn (len1, operands[2]); | |
3044 | ||
3045 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3046 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3047 | operands[2] = reg0; | |
3048 | operands[3] = reg1; | |
3049 | }) | |
3050 | ||
a1aed706 AS |
3051 | (define_insn "*cmpmem_long" |
3052 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3053 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3054 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3055 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3056 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3057 | (use (match_dup 2)) |
3058 | (use (match_dup 3))] | |
a1aed706 | 3059 | "" |
287ff198 | 3060 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3061 | [(set_attr "length" "8") |
3062 | (set_attr "type" "vs")]) | |
9db1d521 | 3063 | |
02887425 UW |
3064 | ; Convert CCUmode condition code to integer. |
3065 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3066 | |
02887425 | 3067 | (define_insn_and_split "cmpint" |
9db1d521 | 3068 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3069 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3070 | UNSPEC_CCU_TO_INT)) |
ae156f85 | 3071 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3072 | "" |
02887425 UW |
3073 | "#" |
3074 | "reload_completed" | |
3075 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3076 | (parallel | |
3077 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3078 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3079 | |
3080 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3081 | [(set (reg CC_REGNUM) |
02887425 | 3082 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3083 | UNSPEC_CCU_TO_INT) |
02887425 UW |
3084 | (const_int 0))) |
3085 | (set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 3086 | (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))] |
02887425 UW |
3087 | "s390_match_ccmode (insn, CCSmode)" |
3088 | "#" | |
3089 | "&& reload_completed" | |
3090 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3091 | (parallel | |
3092 | [(set (match_dup 2) (match_dup 3)) | |
3093 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3094 | { |
02887425 UW |
3095 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3096 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3097 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3098 | }) | |
9db1d521 | 3099 | |
02887425 | 3100 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3101 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3102 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3103 | UNSPEC_CCU_TO_INT))) |
ae156f85 | 3104 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3105 | "TARGET_64BIT" |
02887425 UW |
3106 | "#" |
3107 | "&& reload_completed" | |
3108 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3109 | (parallel | |
3110 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3111 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3112 | |
3113 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3114 | [(set (reg CC_REGNUM) |
9381e3f1 | 3115 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3116 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3117 | UNSPEC_CCU_TO_INT) 0) |
02887425 UW |
3118 | (const_int 32)) (const_int 32)) |
3119 | (const_int 0))) | |
3120 | (set (match_operand:DI 0 "register_operand" "=d") | |
638e37c2 | 3121 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] |
02887425 UW |
3122 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" |
3123 | "#" | |
3124 | "&& reload_completed" | |
3125 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3126 | (parallel | |
3127 | [(set (match_dup 2) (match_dup 3)) | |
3128 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3129 | { |
02887425 UW |
3130 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3131 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3132 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3133 | }) | |
9db1d521 | 3134 | |
4023fb28 | 3135 | |
9db1d521 HP |
3136 | ;; |
3137 | ;;- Conversion instructions. | |
3138 | ;; | |
3139 | ||
6fa05db6 | 3140 | (define_insn "*sethighpartsi" |
d3632d41 | 3141 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3142 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3143 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3144 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3145 | "" |
d3632d41 | 3146 | "@ |
6fa05db6 AS |
3147 | icm\t%0,%2,%S1 |
3148 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3149 | [(set_attr "op_type" "RS,RSY") |
3150 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3151 | |
6fa05db6 | 3152 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3153 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3154 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3155 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3156 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3157 | "TARGET_64BIT" |
6fa05db6 | 3158 | "icmh\t%0,%2,%S1" |
729e750f WG |
3159 | [(set_attr "op_type" "RSY") |
3160 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3161 | |
6fa05db6 | 3162 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3163 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3164 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3165 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3166 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3167 | "!TARGET_64BIT" |
d3632d41 | 3168 | "@ |
6fa05db6 AS |
3169 | icm\t%0,%2,%S1 |
3170 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3171 | [(set_attr "op_type" "RS,RSY") |
3172 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3173 | ||
4023fb28 | 3174 | |
6fa05db6 AS |
3175 | (define_insn_and_split "*extzv<mode>" |
3176 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3177 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3178 | (match_operand 2 "const_int_operand" "n") | |
3179 | (const_int 0))) | |
ae156f85 | 3180 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3181 | "INTVAL (operands[2]) > 0 |
3182 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3183 | "#" |
3184 | "&& reload_completed" | |
4023fb28 | 3185 | [(parallel |
6fa05db6 | 3186 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3187 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3188 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3189 | { |
6fa05db6 AS |
3190 | int bitsize = INTVAL (operands[2]); |
3191 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3192 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3193 | ||
3194 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3195 | set_mem_size (operands[1], GEN_INT (size)); | |
3196 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
3197 | operands[3] = GEN_INT (mask); | |
b628bd8e | 3198 | }) |
4023fb28 | 3199 | |
6fa05db6 AS |
3200 | (define_insn_and_split "*extv<mode>" |
3201 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3202 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3203 | (match_operand 2 "const_int_operand" "n") | |
3204 | (const_int 0))) | |
ae156f85 | 3205 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3206 | "INTVAL (operands[2]) > 0 |
3207 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3208 | "#" |
3209 | "&& reload_completed" | |
4023fb28 | 3210 | [(parallel |
6fa05db6 | 3211 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3212 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3213 | (parallel |
3214 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3215 | (clobber (reg:CC CC_REGNUM))])] | |
3216 | { | |
3217 | int bitsize = INTVAL (operands[2]); | |
3218 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3219 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3220 | ||
3221 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3222 | set_mem_size (operands[1], GEN_INT (size)); | |
3223 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
3224 | operands[3] = GEN_INT (mask); | |
3225 | }) | |
3226 | ||
3227 | ; | |
3228 | ; insv instruction patterns | |
3229 | ; | |
3230 | ||
3231 | (define_expand "insv" | |
3232 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3233 | (match_operand 1 "const_int_operand" "") | |
3234 | (match_operand 2 "const_int_operand" "")) | |
3235 | (match_operand 3 "general_operand" ""))] | |
3236 | "" | |
4023fb28 | 3237 | { |
6fa05db6 AS |
3238 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3239 | DONE; | |
3240 | FAIL; | |
b628bd8e | 3241 | }) |
4023fb28 | 3242 | |
963fc8d0 AK |
3243 | (define_insn "*insv<mode>_z10" |
3244 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
3245 | (match_operand 1 "const_int_operand" "I") | |
3246 | (match_operand 2 "const_int_operand" "I")) | |
3247 | (match_operand:GPR 3 "nonimmediate_operand" "d")) | |
3248 | (clobber (reg:CC CC_REGNUM))] | |
3249 | "TARGET_Z10 | |
3250 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= | |
3251 | GET_MODE_BITSIZE (<MODE>mode)" | |
3252 | { | |
3253 | int start = INTVAL (operands[2]); | |
3254 | int size = INTVAL (operands[1]); | |
3255 | int offset = 64 - GET_MODE_BITSIZE (<MODE>mode); | |
3256 | ||
3257 | operands[2] = GEN_INT (offset + start); /* start bit position */ | |
3258 | operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ | |
3259 | operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - | |
3260 | start - size); /* left shift count */ | |
3261 | ||
3262 | return "risbg\t%0,%3,%b2,%b1,%b4"; | |
3263 | } | |
9381e3f1 WG |
3264 | [(set_attr "op_type" "RIE") |
3265 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3266 | |
3267 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3268 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3269 | (define_insn "*insv<mode>_z10_noshift" | |
3270 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3271 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3272 | (match_operand 2 "const_int_operand" "n")) | |
3273 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") | |
3274 | (match_operand 4 "const_int_operand" "n")))) | |
3275 | (clobber (reg:CC CC_REGNUM))] | |
3276 | "TARGET_Z10 | |
3277 | && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3278 | GET_MODE_BITSIZE (<MODE>mode), NULL, NULL) | |
3279 | && INTVAL (operands[2]) == ~(INTVAL (operands[4]))" | |
3280 | ||
3281 | { | |
3282 | int start; | |
3283 | int size; | |
3284 | ||
3285 | s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3286 | GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3287 | ||
3288 | operands[5] = GEN_INT (64 - start - size); /* start bit position */ | |
3289 | operands[6] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3290 | operands[7] = const0_rtx; /* left shift count */ | |
3291 | ||
3292 | return "risbg\t%0,%1,%b5,%b6,%b7"; | |
3293 | } | |
9381e3f1 WG |
3294 | [(set_attr "op_type" "RIE") |
3295 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3296 | |
3297 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3298 | (define_insn "*insv<mode>_or_z10_noshift" | |
3299 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3300 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3301 | (match_operand 2 "const_int_operand" "n")) | |
3302 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
3303 | (clobber (reg:CC CC_REGNUM))] | |
3304 | "TARGET_Z10 | |
3305 | && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3306 | GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)" | |
3307 | { | |
3308 | int start; | |
3309 | int size; | |
3310 | ||
3311 | s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3312 | GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3313 | ||
3314 | operands[4] = GEN_INT (64 - start - size); /* start bit position */ | |
3315 | operands[5] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3316 | operands[6] = const0_rtx; /* left shift count */ | |
3317 | ||
3318 | return "rosbg\t%0,%1,%b4,%b5,%b6"; | |
3319 | } | |
3320 | [(set_attr "op_type" "RIE")]) | |
3321 | ||
6fa05db6 AS |
3322 | (define_insn "*insv<mode>_mem_reg" |
3323 | [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") | |
3324 | (match_operand 1 "const_int_operand" "n,n") | |
3325 | (const_int 0)) | |
3326 | (match_operand:P 2 "register_operand" "d,d"))] | |
3327 | "INTVAL (operands[1]) > 0 | |
3328 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3329 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3330 | { | |
3331 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3332 | ||
3333 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 3334 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
3335 | : "stcmy\t%2,%1,%S0"; |
3336 | } | |
9381e3f1 WG |
3337 | [(set_attr "op_type" "RS,RSY") |
3338 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
3339 | |
3340 | (define_insn "*insvdi_mem_reghigh" | |
3341 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3342 | (match_operand 1 "const_int_operand" "n") | |
3343 | (const_int 0)) | |
3344 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3345 | (const_int 32)))] | |
3346 | "TARGET_64BIT | |
3347 | && INTVAL (operands[1]) > 0 | |
3348 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3349 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3350 | { | |
3351 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3352 | ||
3353 | operands[1] = GEN_INT ((1ul << size) - 1); | |
3354 | return "stcmh\t%2,%1,%S0"; | |
3355 | } | |
9381e3f1 WG |
3356 | [(set_attr "op_type" "RSY") |
3357 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 AS |
3358 | |
3359 | (define_insn "*insv<mode>_reg_imm" | |
3360 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
3361 | (const_int 16) | |
3362 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 3363 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 AS |
3364 | "TARGET_ZARCH |
3365 | && INTVAL (operands[1]) >= 0 | |
3366 | && INTVAL (operands[1]) < BITS_PER_WORD | |
3367 | && INTVAL (operands[1]) % 16 == 0" | |
3368 | { | |
3369 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3370 | { | |
3371 | case 64: return "iihh\t%0,%x2"; break; | |
3372 | case 48: return "iihl\t%0,%x2"; break; | |
3373 | case 32: return "iilh\t%0,%x2"; break; | |
3374 | case 16: return "iill\t%0,%x2"; break; | |
3375 | default: gcc_unreachable(); | |
3376 | } | |
3377 | } | |
9381e3f1 WG |
3378 | [(set_attr "op_type" "RI") |
3379 | (set_attr "z10prop" "z10_super_E1")]) | |
3380 | ||
6fa05db6 AS |
3381 | |
3382 | (define_insn "*insv<mode>_reg_extimm" | |
3383 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
3384 | (const_int 32) | |
3385 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 3386 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 AS |
3387 | "TARGET_EXTIMM |
3388 | && INTVAL (operands[1]) >= 0 | |
3389 | && INTVAL (operands[1]) < BITS_PER_WORD | |
3390 | && INTVAL (operands[1]) % 32 == 0" | |
3391 | { | |
3392 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3393 | { | |
3394 | case 64: return "iihf\t%0,%o2"; break; | |
3395 | case 32: return "iilf\t%0,%o2"; break; | |
3396 | default: gcc_unreachable(); | |
3397 | } | |
3398 | } | |
9381e3f1 WG |
3399 | [(set_attr "op_type" "RIL") |
3400 | (set_attr "z10prop" "z10_fwd_E1")]) | |
3401 | ||
6fa05db6 | 3402 | |
9db1d521 HP |
3403 | ; |
3404 | ; extendsidi2 instruction pattern(s). | |
3405 | ; | |
3406 | ||
4023fb28 UW |
3407 | (define_expand "extendsidi2" |
3408 | [(set (match_operand:DI 0 "register_operand" "") | |
3409 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3410 | "" | |
4023fb28 UW |
3411 | { |
3412 | if (!TARGET_64BIT) | |
3413 | { | |
c41c1387 | 3414 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3415 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
3416 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
3417 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
3418 | DONE; |
3419 | } | |
ec24698e | 3420 | }) |
4023fb28 UW |
3421 | |
3422 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
3423 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3424 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9db1d521 HP |
3425 | "TARGET_64BIT" |
3426 | "@ | |
d40c829f | 3427 | lgfr\t%0,%1 |
963fc8d0 AK |
3428 | lgf\t%0,%1 |
3429 | lgfrl\t%0,%1" | |
3430 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3431 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3432 | (set_attr "cpu_facility" "*,*,z10") |
3433 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3434 | |
9db1d521 | 3435 | ; |
56477c21 | 3436 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3437 | ; |
3438 | ||
56477c21 AS |
3439 | (define_expand "extend<HQI:mode><DSI:mode>2" |
3440 | [(set (match_operand:DSI 0 "register_operand" "") | |
3441 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 3442 | "" |
4023fb28 | 3443 | { |
56477c21 | 3444 | if (<DSI:MODE>mode == DImode && !TARGET_64BIT) |
4023fb28 UW |
3445 | { |
3446 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 3447 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
3448 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
3449 | DONE; | |
3450 | } | |
ec24698e | 3451 | else if (!TARGET_EXTIMM) |
4023fb28 | 3452 | { |
56477c21 AS |
3453 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - |
3454 | GET_MODE_BITSIZE (<HQI:MODE>mode)); | |
3455 | ||
3456 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
3457 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
3458 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
3459 | DONE; |
3460 | } | |
ec24698e UW |
3461 | }) |
3462 | ||
56477c21 AS |
3463 | ; |
3464 | ; extendhidi2 instruction pattern(s). | |
3465 | ; | |
3466 | ||
ec24698e | 3467 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
3468 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3469 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
ec24698e UW |
3470 | "TARGET_64BIT && TARGET_EXTIMM" |
3471 | "@ | |
3472 | lghr\t%0,%1 | |
963fc8d0 AK |
3473 | lgh\t%0,%1 |
3474 | lghrl\t%0,%1" | |
3475 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3476 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3477 | (set_attr "cpu_facility" "extimm,extimm,z10") |
3478 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
3479 | |
3480 | (define_insn "*extendhidi2" | |
9db1d521 | 3481 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 3482 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9db1d521 | 3483 | "TARGET_64BIT" |
d40c829f | 3484 | "lgh\t%0,%1" |
9381e3f1 WG |
3485 | [(set_attr "op_type" "RXY") |
3486 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 3487 | |
9db1d521 | 3488 | ; |
56477c21 | 3489 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
3490 | ; |
3491 | ||
ec24698e | 3492 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
3493 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3494 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
3495 | "TARGET_EXTIMM" |
3496 | "@ | |
3497 | lhr\t%0,%1 | |
3498 | lh\t%0,%1 | |
963fc8d0 AK |
3499 | lhy\t%0,%1 |
3500 | lhrl\t%0,%1" | |
3501 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
3502 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
3503 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
3504 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3505 | |
4023fb28 | 3506 | (define_insn "*extendhisi2" |
d3632d41 UW |
3507 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3508 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 3509 | "!TARGET_EXTIMM" |
d3632d41 | 3510 | "@ |
d40c829f UW |
3511 | lh\t%0,%1 |
3512 | lhy\t%0,%1" | |
9381e3f1 WG |
3513 | [(set_attr "op_type" "RX,RXY") |
3514 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3515 | |
56477c21 AS |
3516 | ; |
3517 | ; extendqi(si|di)2 instruction pattern(s). | |
3518 | ; | |
3519 | ||
43a09b63 | 3520 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
3521 | (define_insn "*extendqi<mode>2_extimm" |
3522 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3523 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3524 | "TARGET_EXTIMM" |
3525 | "@ | |
56477c21 AS |
3526 | l<g>br\t%0,%1 |
3527 | l<g>b\t%0,%1" | |
9381e3f1 WG |
3528 | [(set_attr "op_type" "RRE,RXY") |
3529 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 3530 | |
43a09b63 | 3531 | ; lb, lgb |
56477c21 AS |
3532 | (define_insn "*extendqi<mode>2" |
3533 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3534 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
3535 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
3536 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
3537 | [(set_attr "op_type" "RXY") |
3538 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 3539 | |
56477c21 AS |
3540 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
3541 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3542 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 3543 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 3544 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
3545 | "#" |
3546 | "&& reload_completed" | |
4023fb28 | 3547 | [(parallel |
56477c21 | 3548 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 3549 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 3550 | (parallel |
56477c21 | 3551 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 3552 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
3553 | { |
3554 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3555 | set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); | |
56477c21 AS |
3556 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) |
3557 | - GET_MODE_BITSIZE (QImode)); | |
6fa05db6 | 3558 | }) |
9db1d521 | 3559 | |
9db1d521 HP |
3560 | ; |
3561 | ; zero_extendsidi2 instruction pattern(s). | |
3562 | ; | |
3563 | ||
4023fb28 UW |
3564 | (define_expand "zero_extendsidi2" |
3565 | [(set (match_operand:DI 0 "register_operand" "") | |
3566 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3567 | "" | |
4023fb28 UW |
3568 | { |
3569 | if (!TARGET_64BIT) | |
3570 | { | |
c41c1387 | 3571 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3572 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
3573 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
3574 | DONE; |
3575 | } | |
ec24698e | 3576 | }) |
4023fb28 UW |
3577 | |
3578 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
3579 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3580 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9db1d521 HP |
3581 | "TARGET_64BIT" |
3582 | "@ | |
d40c829f | 3583 | llgfr\t%0,%1 |
963fc8d0 AK |
3584 | llgf\t%0,%1 |
3585 | llgfrl\t%0,%1" | |
3586 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3587 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3588 | (set_attr "cpu_facility" "*,*,z10") |
3589 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 3590 | |
288e517f AK |
3591 | ; |
3592 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
3593 | ; | |
3594 | ||
d6083c7d UW |
3595 | (define_insn "*llgt_sidi" |
3596 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3597 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d UW |
3598 | (const_int 2147483647)))] |
3599 | "TARGET_64BIT" | |
3600 | "llgt\t%0,%1" | |
9381e3f1 WG |
3601 | [(set_attr "op_type" "RXE") |
3602 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
3603 | |
3604 | (define_insn_and_split "*llgt_sidi_split" | |
3605 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3606 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3607 | (const_int 2147483647))) |
ae156f85 | 3608 | (clobber (reg:CC CC_REGNUM))] |
d6083c7d UW |
3609 | "TARGET_64BIT" |
3610 | "#" | |
3611 | "&& reload_completed" | |
3612 | [(set (match_dup 0) | |
3613 | (and:DI (subreg:DI (match_dup 1) 0) | |
3614 | (const_int 2147483647)))] | |
3615 | "") | |
3616 | ||
288e517f AK |
3617 | (define_insn "*llgt_sisi" |
3618 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 3619 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 3620 | (const_int 2147483647)))] |
c4d50129 | 3621 | "TARGET_ZARCH" |
288e517f AK |
3622 | "@ |
3623 | llgtr\t%0,%1 | |
3624 | llgt\t%0,%1" | |
9381e3f1 WG |
3625 | [(set_attr "op_type" "RRE,RXE") |
3626 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3627 | |
288e517f AK |
3628 | (define_insn "*llgt_didi" |
3629 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3630 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
3631 | (const_int 2147483647)))] | |
3632 | "TARGET_64BIT" | |
3633 | "@ | |
3634 | llgtr\t%0,%1 | |
3635 | llgt\t%0,%N1" | |
9381e3f1 WG |
3636 | [(set_attr "op_type" "RRE,RXE") |
3637 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3638 | |
f19a9af7 | 3639 | (define_split |
f6ee577c AS |
3640 | [(set (match_operand:GPR 0 "register_operand" "") |
3641 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3642 | (const_int 2147483647))) | |
ae156f85 | 3643 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 3644 | "TARGET_ZARCH && reload_completed" |
288e517f | 3645 | [(set (match_dup 0) |
f6ee577c AS |
3646 | (and:GPR (match_dup 1) |
3647 | (const_int 2147483647)))] | |
288e517f AK |
3648 | "") |
3649 | ||
9db1d521 | 3650 | ; |
56477c21 | 3651 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3652 | ; |
3653 | ||
56477c21 AS |
3654 | (define_expand "zero_extend<mode>di2" |
3655 | [(set (match_operand:DI 0 "register_operand" "") | |
3656 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3657 | "" | |
3658 | { | |
3659 | if (!TARGET_64BIT) | |
3660 | { | |
3661 | rtx tmp = gen_reg_rtx (SImode); | |
3662 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3663 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3664 | DONE; | |
3665 | } | |
3666 | else if (!TARGET_EXTIMM) | |
3667 | { | |
9381e3f1 | 3668 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - |
56477c21 AS |
3669 | GET_MODE_BITSIZE(<MODE>mode)); |
3670 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3671 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
3672 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
3673 | DONE; | |
3674 | } | |
3675 | }) | |
3676 | ||
f6ee577c | 3677 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 3678 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 3679 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 3680 | "" |
4023fb28 | 3681 | { |
ec24698e UW |
3682 | if (!TARGET_EXTIMM) |
3683 | { | |
3684 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 3685 | emit_insn (gen_andsi3 (operands[0], operands[1], |
ec24698e UW |
3686 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); |
3687 | DONE; | |
56477c21 | 3688 | } |
ec24698e UW |
3689 | }) |
3690 | ||
963fc8d0 AK |
3691 | ; llhrl, llghrl |
3692 | (define_insn "*zero_extendhi<mode>2_z10" | |
3693 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3694 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
3695 | "TARGET_Z10" | |
3696 | "@ | |
3697 | ll<g>hr\t%0,%1 | |
3698 | ll<g>h\t%0,%1 | |
3699 | ll<g>hrl\t%0,%1" | |
3700 | [(set_attr "op_type" "RXY,RRE,RIL") | |
3701 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 3702 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 3703 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 3704 | |
43a09b63 | 3705 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
3706 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
3707 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3708 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3709 | "TARGET_EXTIMM" |
3710 | "@ | |
56477c21 AS |
3711 | ll<g><hc>r\t%0,%1 |
3712 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
3713 | [(set_attr "op_type" "RRE,RXY") |
3714 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 3715 | |
43a09b63 | 3716 | ; llgh, llgc |
56477c21 AS |
3717 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
3718 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3719 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 3720 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 3721 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
3722 | [(set_attr "op_type" "RXY") |
3723 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
3724 | |
3725 | (define_insn_and_split "*zero_extendhisi2_31" | |
3726 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 3727 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 3728 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 3729 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3730 | "#" |
3731 | "&& reload_completed" | |
3732 | [(set (match_dup 0) (const_int 0)) | |
3733 | (parallel | |
3734 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 3735 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 3736 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 3737 | |
cc7ab9b7 UW |
3738 | (define_insn_and_split "*zero_extendqisi2_31" |
3739 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 3740 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3741 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3742 | "#" |
3743 | "&& reload_completed" | |
3744 | [(set (match_dup 0) (const_int 0)) | |
3745 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3746 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 3747 | |
9db1d521 HP |
3748 | ; |
3749 | ; zero_extendqihi2 instruction pattern(s). | |
3750 | ; | |
3751 | ||
9db1d521 HP |
3752 | (define_expand "zero_extendqihi2" |
3753 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 3754 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 3755 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 3756 | { |
4023fb28 UW |
3757 | operands[1] = gen_lowpart (HImode, operands[1]); |
3758 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
3759 | DONE; | |
ec24698e | 3760 | }) |
9db1d521 | 3761 | |
4023fb28 | 3762 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 3763 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 3764 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 3765 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 3766 | "llgc\t%0,%1" |
9381e3f1 WG |
3767 | [(set_attr "op_type" "RXY") |
3768 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 3769 | |
cc7ab9b7 UW |
3770 | (define_insn_and_split "*zero_extendqihi2_31" |
3771 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 3772 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3773 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3774 | "#" |
3775 | "&& reload_completed" | |
3776 | [(set (match_dup 0) (const_int 0)) | |
3777 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3778 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 3779 | |
609e7e80 AK |
3780 | ; |
3781 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
3782 | ; | |
3783 | ||
3784 | (define_expand "fixuns_truncdddi2" | |
3785 | [(parallel | |
3786 | [(set (match_operand:DI 0 "register_operand" "") | |
3787 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
3788 | (clobber (match_scratch:TD 2 "=f"))])] | |
9381e3f1 | 3789 | |
fb068247 | 3790 | "TARGET_HARD_DFP" |
609e7e80 AK |
3791 | { |
3792 | rtx label1 = gen_label_rtx (); | |
3793 | rtx label2 = gen_label_rtx (); | |
3794 | rtx temp = gen_reg_rtx (TDmode); | |
3795 | REAL_VALUE_TYPE cmp, sub; | |
3796 | ||
3797 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3798 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3799 | ||
3800 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
9381e3f1 | 3801 | solution is doing the check and the subtraction in TD mode and using a |
609e7e80 AK |
3802 | TD -> DI convert afterwards. */ |
3803 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
3804 | temp = force_reg (TDmode, temp); | |
3805 | emit_insn (gen_cmptd (temp, | |
3806 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); | |
3807 | emit_jump_insn (gen_blt (label1)); | |
3808 | emit_insn (gen_subtd3 (temp, temp, | |
3809 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
99cd7dd0 | 3810 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
609e7e80 AK |
3811 | emit_jump (label2); |
3812 | ||
3813 | emit_label (label1); | |
99cd7dd0 | 3814 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); |
609e7e80 AK |
3815 | emit_label (label2); |
3816 | DONE; | |
3817 | }) | |
3818 | ||
3819 | (define_expand "fixuns_trunctddi2" | |
3820 | [(set (match_operand:DI 0 "register_operand" "") | |
3821 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))] | |
fb068247 | 3822 | "TARGET_HARD_DFP" |
609e7e80 AK |
3823 | { |
3824 | rtx label1 = gen_label_rtx (); | |
3825 | rtx label2 = gen_label_rtx (); | |
3826 | rtx temp = gen_reg_rtx (TDmode); | |
3827 | REAL_VALUE_TYPE cmp, sub; | |
9381e3f1 | 3828 | |
609e7e80 AK |
3829 | operands[1] = force_reg (TDmode, operands[1]); |
3830 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3831 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
9381e3f1 | 3832 | |
609e7e80 AK |
3833 | emit_insn (gen_cmptd (operands[1], |
3834 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode))); | |
3835 | emit_jump_insn (gen_blt (label1)); | |
3836 | emit_insn (gen_subtd3 (temp, operands[1], | |
3837 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
99cd7dd0 | 3838 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
609e7e80 AK |
3839 | emit_jump (label2); |
3840 | ||
3841 | emit_label (label1); | |
99cd7dd0 | 3842 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); |
609e7e80 AK |
3843 | emit_label (label2); |
3844 | DONE; | |
3845 | }) | |
cc7ab9b7 | 3846 | |
9db1d521 | 3847 | ; |
9381e3f1 | 3848 | ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 |
609e7e80 | 3849 | ; instruction pattern(s). |
9db1d521 HP |
3850 | ; |
3851 | ||
7b6baae1 | 3852 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
2f8f8434 | 3853 | [(set (match_operand:GPR 0 "register_operand" "") |
7b6baae1 | 3854 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))] |
142cd70f | 3855 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3856 | { |
3857 | rtx label1 = gen_label_rtx (); | |
3858 | rtx label2 = gen_label_rtx (); | |
7b6baae1 | 3859 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); |
2f8f8434 | 3860 | REAL_VALUE_TYPE cmp, sub; |
9381e3f1 | 3861 | |
7b6baae1 | 3862 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); |
9e8c0677 AK |
3863 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); |
3864 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); | |
9381e3f1 | 3865 | |
7b6baae1 AK |
3866 | emit_insn (gen_cmp<BFP:mode> (operands[1], |
3867 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode))); | |
9db1d521 | 3868 | emit_jump_insn (gen_blt (label1)); |
7b6baae1 AK |
3869 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], |
3870 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); | |
142cd70f | 3871 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, |
99cd7dd0 | 3872 | GEN_INT (7))); |
f314b9b1 | 3873 | emit_jump (label2); |
9db1d521 HP |
3874 | |
3875 | emit_label (label1); | |
142cd70f | 3876 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], |
99cd7dd0 | 3877 | operands[1], GEN_INT (5))); |
9db1d521 HP |
3878 | emit_label (label2); |
3879 | DONE; | |
10bbf137 | 3880 | }) |
9db1d521 | 3881 | |
b60cb710 AK |
3882 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
3883 | [(set (match_operand:GPR 0 "register_operand" "") | |
3884 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
3885 | "TARGET_HARD_FLOAT" | |
9db1d521 | 3886 | { |
b60cb710 AK |
3887 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
3888 | GEN_INT (5))); | |
9db1d521 | 3889 | DONE; |
10bbf137 | 3890 | }) |
9db1d521 | 3891 | |
43a09b63 | 3892 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
142cd70f | 3893 | (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
2f8f8434 | 3894 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7b6baae1 | 3895 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) |
2f8f8434 | 3896 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) |
ae156f85 | 3897 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 3898 | "TARGET_HARD_FLOAT" |
7b6baae1 | 3899 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 3900 | [(set_attr "op_type" "RRE") |
077dab3b | 3901 | (set_attr "type" "ftoi")]) |
9db1d521 | 3902 | |
609e7e80 AK |
3903 | |
3904 | ; | |
3905 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
3906 | ; | |
3907 | ||
99cd7dd0 AK |
3908 | (define_expand "fix_trunc<mode>di2" |
3909 | [(set (match_operand:DI 0 "register_operand" "") | |
3910 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
fb068247 | 3911 | "TARGET_64BIT && TARGET_HARD_DFP" |
99cd7dd0 AK |
3912 | { |
3913 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
3914 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
3915 | GEN_INT (9))); | |
3916 | DONE; | |
3917 | }) | |
3918 | ||
609e7e80 | 3919 | ; cgxtr, cgdtr |
99cd7dd0 | 3920 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
3921 | [(set (match_operand:DI 0 "register_operand" "=d") |
3922 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
3923 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
3924 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 3925 | "TARGET_64BIT && TARGET_HARD_DFP" |
609e7e80 AK |
3926 | "cg<DFP:xde>tr\t%0,%h2,%1" |
3927 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 3928 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
3929 | |
3930 | ||
f61a2c7d AK |
3931 | ; |
3932 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
3933 | ; | |
3934 | ||
3935 | (define_expand "fix_trunctf<mode>2" | |
3936 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
3937 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
3938 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
3939 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 3940 | "TARGET_HARD_FLOAT" |
142cd70f | 3941 | "") |
9db1d521 | 3942 | |
9db1d521 | 3943 | |
9db1d521 | 3944 | ; |
142cd70f | 3945 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
3946 | ; |
3947 | ||
609e7e80 | 3948 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 3949 | (define_insn "floatdi<mode>2" |
609e7e80 AK |
3950 | [(set (match_operand:FP 0 "register_operand" "=f") |
3951 | (float:FP (match_operand:DI 1 "register_operand" "d")))] | |
142cd70f | 3952 | "TARGET_64BIT && TARGET_HARD_FLOAT" |
609e7e80 | 3953 | "c<xde>g<bt>r\t%0,%1" |
9db1d521 | 3954 | [(set_attr "op_type" "RRE") |
9381e3f1 | 3955 | (set_attr "type" "itof<mode>" )]) |
9db1d521 | 3956 | |
43a09b63 | 3957 | ; cxfbr, cdfbr, cefbr |
142cd70f | 3958 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
3959 | [(set (match_operand:BFP 0 "register_operand" "=f") |
3960 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 3961 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
3962 | "c<xde>fbr\t%0,%1" |
3963 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 3964 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d AK |
3965 | |
3966 | ||
9db1d521 HP |
3967 | ; |
3968 | ; truncdfsf2 instruction pattern(s). | |
3969 | ; | |
3970 | ||
142cd70f | 3971 | (define_insn "truncdfsf2" |
9db1d521 | 3972 | [(set (match_operand:SF 0 "register_operand" "=f") |
a036c6f7 | 3973 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
142cd70f | 3974 | "TARGET_HARD_FLOAT" |
d40c829f | 3975 | "ledbr\t%0,%1" |
f61a2c7d AK |
3976 | [(set_attr "op_type" "RRE") |
3977 | (set_attr "type" "ftruncdf")]) | |
9db1d521 | 3978 | |
f61a2c7d | 3979 | ; |
142cd70f | 3980 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
3981 | ; |
3982 | ||
142cd70f AK |
3983 | ; ldxbr, lexbr |
3984 | (define_insn "trunctf<mode>2" | |
3985 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
3986 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 3987 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
3988 | "TARGET_HARD_FLOAT" |
3989 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 3990 | [(set_attr "length" "6") |
9381e3f1 | 3991 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 3992 | |
609e7e80 AK |
3993 | ; |
3994 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
3995 | ; | |
3996 | ||
3997 | (define_insn "trunctddd2" | |
3998 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
3999 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4000 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4001 | "TARGET_HARD_DFP" |
bf259a77 AK |
4002 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4003 | [(set_attr "length" "6") | |
9381e3f1 | 4004 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4005 | |
4006 | (define_insn "truncddsd2" | |
4007 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4008 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4009 | "TARGET_HARD_DFP" |
609e7e80 AK |
4010 | "ledtr\t%0,0,%1,0" |
4011 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4012 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4013 | |
9db1d521 | 4014 | ; |
142cd70f | 4015 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4016 | ; |
4017 | ||
142cd70f AK |
4018 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
4019 | (define_insn "extend<DSF:mode><BFP:mode>2" | |
4020 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
4021 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] | |
4022 | "TARGET_HARD_FLOAT | |
4023 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)" | |
f61a2c7d | 4024 | "@ |
142cd70f AK |
4025 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4026 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
f61a2c7d | 4027 | [(set_attr "op_type" "RRE,RXE") |
142cd70f | 4028 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) |
f61a2c7d | 4029 | |
609e7e80 AK |
4030 | ; |
4031 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4032 | ; | |
4033 | ||
4034 | (define_insn "extendddtd2" | |
4035 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4036 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4037 | "TARGET_HARD_DFP" |
609e7e80 AK |
4038 | "lxdtr\t%0,%1,0" |
4039 | [(set_attr "op_type" "RRF") | |
4040 | (set_attr "type" "fsimptf")]) | |
4041 | ||
4042 | (define_insn "extendsddd2" | |
4043 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4044 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4045 | "TARGET_HARD_DFP" |
609e7e80 AK |
4046 | "ldetr\t%0,%1,0" |
4047 | [(set_attr "op_type" "RRF") | |
4048 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4049 | |
35dd9a0e AK |
4050 | ; Binary <-> Decimal floating point trunc patterns |
4051 | ; | |
4052 | ||
4053 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4054 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4055 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4056 | (use (reg:SI GPR0_REGNUM)) | |
4057 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4058 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4059 | "pfpo") |
4060 | ||
4061 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4062 | [(set (reg:BFP FPR0_REGNUM) | |
4063 | (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4064 | (use (reg:SI GPR0_REGNUM)) | |
4065 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4066 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4067 | "pfpo") |
4068 | ||
4069 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
4070 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4071 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4072 | (parallel | |
4073 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4074 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4075 | (use (reg:SI GPR0_REGNUM)) | |
4076 | (clobber (reg:CC CC_REGNUM))]) | |
4077 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4078 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4079 | "TARGET_HARD_DFP |
35dd9a0e AK |
4080 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4081 | { | |
4082 | HOST_WIDE_INT flags; | |
4083 | ||
4084 | flags = (PFPO_CONVERT | | |
4085 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4086 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4087 | ||
4088 | operands[2] = GEN_INT (flags); | |
4089 | }) | |
4090 | ||
4091 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
4092 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4093 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4094 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4095 | (parallel | |
4096 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4097 | (use (reg:SI GPR0_REGNUM)) | |
4098 | (clobber (reg:CC CC_REGNUM))]) | |
4099 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4100 | "TARGET_HARD_DFP |
35dd9a0e AK |
4101 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
4102 | { | |
4103 | HOST_WIDE_INT flags; | |
4104 | ||
4105 | flags = (PFPO_CONVERT | | |
4106 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4107 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4108 | ||
4109 | operands[2] = GEN_INT (flags); | |
4110 | }) | |
4111 | ||
4112 | ; | |
4113 | ; Binary <-> Decimal floating point extend patterns | |
4114 | ; | |
4115 | ||
4116 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
4117 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4118 | (use (reg:SI GPR0_REGNUM)) | |
4119 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4120 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4121 | "pfpo") |
4122 | ||
4123 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
4124 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4125 | (use (reg:SI GPR0_REGNUM)) | |
4126 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4127 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4128 | "pfpo") |
4129 | ||
4130 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
4131 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4132 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4133 | (parallel | |
4134 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4135 | (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4136 | (use (reg:SI GPR0_REGNUM)) | |
4137 | (clobber (reg:CC CC_REGNUM))]) | |
4138 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4139 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4140 | "TARGET_HARD_DFP |
35dd9a0e AK |
4141 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4142 | { | |
4143 | HOST_WIDE_INT flags; | |
4144 | ||
4145 | flags = (PFPO_CONVERT | | |
4146 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4147 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4148 | ||
4149 | operands[2] = GEN_INT (flags); | |
4150 | }) | |
4151 | ||
4152 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
4153 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4154 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4155 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4156 | (parallel | |
4157 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4158 | (use (reg:SI GPR0_REGNUM)) | |
4159 | (clobber (reg:CC CC_REGNUM))]) | |
4160 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4161 | "TARGET_HARD_DFP |
35dd9a0e AK |
4162 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
4163 | { | |
4164 | HOST_WIDE_INT flags; | |
4165 | ||
4166 | flags = (PFPO_CONVERT | | |
4167 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4168 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4169 | ||
4170 | operands[2] = GEN_INT (flags); | |
4171 | }) | |
4172 | ||
4173 | ||
9db1d521 | 4174 | ;; |
fae778eb | 4175 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 4176 | ;; |
fae778eb | 4177 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
4178 | ; because of unpredictable Bits in Register for Halfword and Byte |
4179 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
4180 | ||
07893d4f UW |
4181 | ;; |
4182 | ;;- Add instructions. | |
4183 | ;; | |
4184 | ||
1c7b1b7e UW |
4185 | ; |
4186 | ; addti3 instruction pattern(s). | |
4187 | ; | |
4188 | ||
4189 | (define_insn_and_split "addti3" | |
4190 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4191 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
4192 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4193 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
4194 | "TARGET_64BIT" |
4195 | "#" | |
4196 | "&& reload_completed" | |
4197 | [(parallel | |
ae156f85 | 4198 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
4199 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
4200 | (match_dup 7))) | |
4201 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
4202 | (parallel | |
a94a76a7 UW |
4203 | [(set (match_dup 3) (plus:DI |
4204 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4205 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4206 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
4207 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4208 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4209 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4210 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4211 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4212 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4213 | |
07893d4f UW |
4214 | ; |
4215 | ; adddi3 instruction pattern(s). | |
4216 | ; | |
4217 | ||
3298c037 AK |
4218 | (define_expand "adddi3" |
4219 | [(parallel | |
963fc8d0 | 4220 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
4221 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
4222 | (match_operand:DI 2 "general_operand" ""))) | |
4223 | (clobber (reg:CC CC_REGNUM))])] | |
4224 | "" | |
4225 | "") | |
4226 | ||
07893d4f UW |
4227 | (define_insn "*adddi3_sign" |
4228 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4229 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4230 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4231 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4232 | "TARGET_64BIT" |
4233 | "@ | |
d40c829f UW |
4234 | agfr\t%0,%2 |
4235 | agf\t%0,%2" | |
d3632d41 | 4236 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
4237 | |
4238 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 4239 | [(set (reg CC_REGNUM) |
fb492564 | 4240 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4241 | (match_operand:DI 1 "register_operand" "0,0")) |
4242 | (const_int 0))) | |
4243 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4244 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
4245 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4246 | "@ | |
d40c829f UW |
4247 | algfr\t%0,%2 |
4248 | algf\t%0,%2" | |
9381e3f1 WG |
4249 | [(set_attr "op_type" "RRE,RXY") |
4250 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4251 | |
4252 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 4253 | [(set (reg CC_REGNUM) |
fb492564 | 4254 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4255 | (match_operand:DI 1 "register_operand" "0,0")) |
4256 | (const_int 0))) | |
4257 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4258 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4259 | "@ | |
d40c829f UW |
4260 | algfr\t%0,%2 |
4261 | algf\t%0,%2" | |
9381e3f1 WG |
4262 | [(set_attr "op_type" "RRE,RXY") |
4263 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4264 | |
4265 | (define_insn "*adddi3_zero" | |
4266 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4267 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4268 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4269 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4270 | "TARGET_64BIT" |
4271 | "@ | |
d40c829f UW |
4272 | algfr\t%0,%2 |
4273 | algf\t%0,%2" | |
9381e3f1 WG |
4274 | [(set_attr "op_type" "RRE,RXY") |
4275 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 4276 | |
e69166de | 4277 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 4278 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
4279 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
4280 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4281 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
4282 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4283 | "#" | |
4284 | "&& reload_completed" | |
4285 | [(parallel | |
ae156f85 | 4286 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
4287 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4288 | (match_dup 7))) | |
4289 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4290 | (parallel | |
a94a76a7 UW |
4291 | [(set (match_dup 3) (plus:SI |
4292 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4293 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4294 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
4295 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4296 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4297 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4298 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4299 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4300 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4301 | |
07893d4f | 4302 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 4303 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 4304 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 4305 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4306 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4307 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4308 | "#" |
4309 | "&& reload_completed" | |
4310 | [(parallel | |
4311 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4312 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4313 | (parallel |
ae156f85 | 4314 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
4315 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4316 | (match_dup 7))) | |
4317 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4318 | (set (pc) | |
ae156f85 | 4319 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4320 | (pc) |
4321 | (label_ref (match_dup 9)))) | |
4322 | (parallel | |
4323 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 4324 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4325 | (match_dup 9)] |
97c6f7ad UW |
4326 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4327 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4328 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4329 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4330 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4331 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4332 | operands[9] = gen_label_rtx ();") |
9db1d521 | 4333 | |
3298c037 AK |
4334 | ; |
4335 | ; addsi3 instruction pattern(s). | |
4336 | ; | |
4337 | ||
4338 | (define_expand "addsi3" | |
07893d4f | 4339 | [(parallel |
963fc8d0 | 4340 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
4341 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
4342 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4343 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4344 | "" |
07893d4f | 4345 | "") |
9db1d521 | 4346 | |
3298c037 AK |
4347 | (define_insn "*addsi3_sign" |
4348 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4349 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
4350 | (match_operand:SI 1 "register_operand" "0,0"))) | |
4351 | (clobber (reg:CC CC_REGNUM))] | |
4352 | "" | |
4353 | "@ | |
4354 | ah\t%0,%2 | |
4355 | ahy\t%0,%2" | |
4356 | [(set_attr "op_type" "RX,RXY")]) | |
4357 | ||
9db1d521 | 4358 | ; |
3298c037 | 4359 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 4360 | ; |
9db1d521 | 4361 | |
963fc8d0 | 4362 | ; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 4363 | (define_insn "*add<mode>3" |
963fc8d0 AK |
4364 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS") |
4365 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") | |
4366 | (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
4367 | (clobber (reg:CC CC_REGNUM))] |
4368 | "" | |
ec24698e | 4369 | "@ |
3298c037 AK |
4370 | a<g>r\t%0,%2 |
4371 | a<g>hi\t%0,%h2 | |
4372 | al<g>fi\t%0,%2 | |
4373 | sl<g>fi\t%0,%n2 | |
4374 | a<g>\t%0,%2 | |
963fc8d0 AK |
4375 | a<y>\t%0,%2 |
4376 | a<g>si\t%0,%c2" | |
4377 | [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY") | |
9381e3f1 WG |
4378 | (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10") |
4379 | (set_attr "z10prop" "z10_super_E1, | |
4380 | z10_super_E1, | |
4381 | z10_super_E1, | |
4382 | z10_super_E1, | |
4383 | z10_super_E1, | |
4384 | z10_super_E1, | |
4385 | z10_super_E1")]) | |
0a3bdf9d | 4386 | |
963fc8d0 | 4387 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi |
3298c037 | 4388 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 4389 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
4390 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") |
4391 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
07893d4f | 4392 | (match_dup 1))) |
963fc8d0 | 4393 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d") |
3298c037 | 4394 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4395 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4396 | "@ |
3298c037 AK |
4397 | al<g>r\t%0,%2 |
4398 | al<g>fi\t%0,%2 | |
4399 | sl<g>fi\t%0,%n2 | |
4400 | al<g>\t%0,%2 | |
963fc8d0 AK |
4401 | al<y>\t%0,%2 |
4402 | al<g>si\t%0,%c2" | |
4403 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
9381e3f1 WG |
4404 | (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") |
4405 | (set_attr "z10prop" "z10_super_E1, | |
4406 | z10_super_E1, | |
4407 | z10_super_E1, | |
4408 | z10_super_E1, | |
4409 | z10_super_E1, | |
4410 | z10_super_E1")]) | |
07893d4f | 4411 | |
43a09b63 | 4412 | ; alr, al, aly, algr, alg |
3298c037 | 4413 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 4414 | [(set (reg CC_REGNUM) |
3298c037 AK |
4415 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
4416 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4417 | (match_dup 1))) |
3298c037 | 4418 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 4419 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4420 | "@ |
3298c037 AK |
4421 | al<g>r\t%0,%2 |
4422 | al<g>\t%0,%2 | |
4423 | al<y>\t%0,%2" | |
9381e3f1 WG |
4424 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4425 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4426 | |
963fc8d0 | 4427 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi |
3298c037 | 4428 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 4429 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
4430 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") |
4431 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
07893d4f | 4432 | (match_dup 2))) |
963fc8d0 | 4433 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") |
3298c037 | 4434 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4435 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4436 | "@ |
3298c037 AK |
4437 | al<g>r\t%0,%2 |
4438 | al<g>fi\t%0,%2 | |
4439 | sl<g>fi\t%0,%n2 | |
4440 | al<g>\t%0,%2 | |
963fc8d0 AK |
4441 | al<y>\t%0,%2 |
4442 | al<g>si\t%0,%c2" | |
4443 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
9381e3f1 WG |
4444 | (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") |
4445 | (set_attr "z10prop" "z10_super_E1, | |
4446 | z10_super_E1, | |
4447 | z10_super_E1, | |
4448 | z10_super_E1, | |
4449 | z10_super_E1, | |
4450 | z10_super_E1")]) | |
07893d4f | 4451 | |
43a09b63 | 4452 | ; alr, al, aly, algr, alg |
3298c037 | 4453 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 4454 | [(set (reg CC_REGNUM) |
3298c037 AK |
4455 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
4456 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4457 | (match_dup 2))) |
3298c037 | 4458 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 4459 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4460 | "@ |
3298c037 AK |
4461 | al<g>r\t%0,%2 |
4462 | al<g>\t%0,%2 | |
4463 | al<y>\t%0,%2" | |
9381e3f1 WG |
4464 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4465 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4466 | |
963fc8d0 | 4467 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi |
3298c037 | 4468 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4469 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
4470 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0") |
4471 | (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C")) | |
9db1d521 | 4472 | (const_int 0))) |
963fc8d0 | 4473 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS") |
3298c037 | 4474 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4475 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4476 | "@ |
3298c037 AK |
4477 | al<g>r\t%0,%2 |
4478 | al<g>fi\t%0,%2 | |
4479 | sl<g>fi\t%0,%n2 | |
4480 | al<g>\t%0,%2 | |
963fc8d0 AK |
4481 | al<y>\t%0,%2 |
4482 | al<g>si\t%0,%c2" | |
4483 | [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY") | |
9381e3f1 WG |
4484 | (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10") |
4485 | (set_attr "z10prop" "z10_super_E1, | |
4486 | z10_super_E1, | |
4487 | z10_super_E1, | |
4488 | z10_super_E1, | |
4489 | z10_super_E1, | |
4490 | z10_super_E1")]) | |
9db1d521 | 4491 | |
43a09b63 | 4492 | ; alr, al, aly, algr, alg |
3298c037 | 4493 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4494 | [(set (reg CC_REGNUM) |
3298c037 AK |
4495 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
4496 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 4497 | (const_int 0))) |
3298c037 | 4498 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
c7453384 | 4499 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4500 | "@ |
3298c037 AK |
4501 | al<g>r\t%0,%2 |
4502 | al<g>\t%0,%2 | |
4503 | al<y>\t%0,%2" | |
9381e3f1 WG |
4504 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4505 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4506 | |
43a09b63 | 4507 | ; alr, al, aly, algr, alg |
3298c037 | 4508 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 4509 | [(set (reg CC_REGNUM) |
3298c037 AK |
4510 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0") |
4511 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T")))) | |
4512 | (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
4513 | "s390_match_ccmode(insn, CCLmode)" | |
d3632d41 | 4514 | "@ |
3298c037 AK |
4515 | al<g>r\t%0,%2 |
4516 | al<g>\t%0,%2 | |
4517 | al<y>\t%0,%2" | |
9381e3f1 WG |
4518 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4519 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4520 | |
963fc8d0 | 4521 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
4522 | (define_insn "*add<mode>3_imm_cc" |
4523 | [(set (reg CC_REGNUM) | |
963fc8d0 AK |
4524 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0") |
4525 | (match_operand:GPR 2 "const_int_operand" "K,Os,C")) | |
3298c037 | 4526 | (const_int 0))) |
963fc8d0 | 4527 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS") |
3298c037 AK |
4528 | (plus:GPR (match_dup 1) (match_dup 2)))] |
4529 | "s390_match_ccmode (insn, CCAmode) | |
4530 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
963fc8d0 AK |
4531 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
4532 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) | |
3298c037 | 4533 | && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" |
9db1d521 | 4534 | "@ |
3298c037 | 4535 | a<g>hi\t%0,%h2 |
963fc8d0 AK |
4536 | a<g>fi\t%0,%2 |
4537 | a<g>si\t%0,%c2" | |
4538 | [(set_attr "op_type" "RI,RIL,SIY") | |
9381e3f1 WG |
4539 | (set_attr "cpu_facility" "*,extimm,z10") |
4540 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4541 | |
9db1d521 | 4542 | ; |
609e7e80 | 4543 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4544 | ; |
4545 | ||
609e7e80 | 4546 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
142cd70f | 4547 | (define_insn "add<mode>3" |
609e7e80 AK |
4548 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4549 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4550 | (match_operand:FP 2 "general_operand" " f,<Rf>"))) | |
ae156f85 | 4551 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4552 | "TARGET_HARD_FLOAT" |
9db1d521 | 4553 | "@ |
609e7e80 | 4554 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4555 | a<xde>b\t%0,%2" |
609e7e80 | 4556 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4557 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4558 | |
609e7e80 | 4559 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4560 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4561 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4562 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4563 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4564 | (match_operand:FP 3 "const0_operand" ""))) | |
4565 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
4566 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 4567 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4568 | "@ |
609e7e80 | 4569 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4570 | a<xde>b\t%0,%2" |
609e7e80 | 4571 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4572 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4573 | |
609e7e80 | 4574 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4575 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4576 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4577 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4578 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4579 | (match_operand:FP 3 "const0_operand" ""))) | |
4580 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 4581 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4582 | "@ |
609e7e80 | 4583 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4584 | a<xde>b\t%0,%2" |
609e7e80 | 4585 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4586 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4587 | |
9db1d521 HP |
4588 | |
4589 | ;; | |
4590 | ;;- Subtract instructions. | |
4591 | ;; | |
4592 | ||
1c7b1b7e UW |
4593 | ; |
4594 | ; subti3 instruction pattern(s). | |
4595 | ; | |
4596 | ||
4597 | (define_insn_and_split "subti3" | |
4598 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4599 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
4600 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4601 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
4602 | "TARGET_64BIT" |
4603 | "#" | |
4604 | "&& reload_completed" | |
4605 | [(parallel | |
ae156f85 | 4606 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
4607 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
4608 | (match_dup 7))) | |
4609 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
4610 | (parallel | |
4611 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4612 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4613 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
4614 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4615 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4616 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4617 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4618 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4619 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4620 | |
9db1d521 HP |
4621 | ; |
4622 | ; subdi3 instruction pattern(s). | |
4623 | ; | |
4624 | ||
3298c037 AK |
4625 | (define_expand "subdi3" |
4626 | [(parallel | |
4627 | [(set (match_operand:DI 0 "register_operand" "") | |
4628 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4629 | (match_operand:DI 2 "general_operand" ""))) | |
4630 | (clobber (reg:CC CC_REGNUM))])] | |
4631 | "" | |
4632 | "") | |
4633 | ||
07893d4f UW |
4634 | (define_insn "*subdi3_sign" |
4635 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4636 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4637 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4638 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4639 | "TARGET_64BIT" |
4640 | "@ | |
d40c829f UW |
4641 | sgfr\t%0,%2 |
4642 | sgf\t%0,%2" | |
9381e3f1 WG |
4643 | [(set_attr "op_type" "RRE,RXY") |
4644 | (set_attr "z10prop" "z10_c,*")]) | |
07893d4f UW |
4645 | |
4646 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 4647 | [(set (reg CC_REGNUM) |
07893d4f | 4648 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4649 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4650 | (const_int 0))) |
4651 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4652 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
4653 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4654 | "@ | |
d40c829f UW |
4655 | slgfr\t%0,%2 |
4656 | slgf\t%0,%2" | |
9381e3f1 WG |
4657 | [(set_attr "op_type" "RRE,RXY") |
4658 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4659 | |
4660 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 4661 | [(set (reg CC_REGNUM) |
07893d4f | 4662 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4663 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4664 | (const_int 0))) |
4665 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4666 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4667 | "@ | |
d40c829f UW |
4668 | slgfr\t%0,%2 |
4669 | slgf\t%0,%2" | |
9381e3f1 WG |
4670 | [(set_attr "op_type" "RRE,RXY") |
4671 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4672 | |
4673 | (define_insn "*subdi3_zero" | |
4674 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4675 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4676 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4677 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
4678 | "TARGET_64BIT" |
4679 | "@ | |
d40c829f UW |
4680 | slgfr\t%0,%2 |
4681 | slgf\t%0,%2" | |
9381e3f1 WG |
4682 | [(set_attr "op_type" "RRE,RXY") |
4683 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 4684 | |
e69166de UW |
4685 | (define_insn_and_split "*subdi3_31z" |
4686 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4687 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4688 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4689 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
4690 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4691 | "#" | |
4692 | "&& reload_completed" | |
4693 | [(parallel | |
ae156f85 | 4694 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
4695 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4696 | (match_dup 7))) | |
4697 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4698 | (parallel | |
4699 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4700 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4701 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
4702 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4703 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4704 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4705 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4706 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4707 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4708 | |
07893d4f UW |
4709 | (define_insn_and_split "*subdi3_31" |
4710 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4711 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 4712 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4713 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4714 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4715 | "#" |
4716 | "&& reload_completed" | |
4717 | [(parallel | |
4718 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4719 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4720 | (parallel |
ae156f85 | 4721 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
4722 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4723 | (match_dup 7))) | |
4724 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4725 | (set (pc) | |
ae156f85 | 4726 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4727 | (pc) |
4728 | (label_ref (match_dup 9)))) | |
4729 | (parallel | |
4730 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 4731 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4732 | (match_dup 9)] |
97c6f7ad UW |
4733 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4734 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4735 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4736 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4737 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4738 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4739 | operands[9] = gen_label_rtx ();") |
07893d4f | 4740 | |
3298c037 AK |
4741 | ; |
4742 | ; subsi3 instruction pattern(s). | |
4743 | ; | |
4744 | ||
4745 | (define_expand "subsi3" | |
07893d4f | 4746 | [(parallel |
3298c037 AK |
4747 | [(set (match_operand:SI 0 "register_operand" "") |
4748 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
4749 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4750 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4751 | "" |
07893d4f | 4752 | "") |
9db1d521 | 4753 | |
3298c037 AK |
4754 | (define_insn "*subsi3_sign" |
4755 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4756 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4757 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
4758 | (clobber (reg:CC CC_REGNUM))] | |
4759 | "" | |
4760 | "@ | |
4761 | sh\t%0,%2 | |
4762 | shy\t%0,%2" | |
4763 | [(set_attr "op_type" "RX,RXY")]) | |
4764 | ||
9db1d521 | 4765 | ; |
3298c037 | 4766 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
4767 | ; |
4768 | ||
43a09b63 | 4769 | ; sr, s, sy, sgr, sg |
3298c037 AK |
4770 | (define_insn "*sub<mode>3" |
4771 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4772 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") | |
4773 | (match_operand:GPR 2 "general_operand" "d,R,T") ) ) | |
4774 | (clobber (reg:CC CC_REGNUM))] | |
4775 | "" | |
4776 | "@ | |
4777 | s<g>r\t%0,%2 | |
4778 | s<g>\t%0,%2 | |
4779 | s<y>\t%0,%2" | |
9381e3f1 WG |
4780 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4781 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
3298c037 | 4782 | |
43a09b63 | 4783 | ; slr, sl, sly, slgr, slg |
3298c037 | 4784 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 4785 | [(set (reg CC_REGNUM) |
3298c037 AK |
4786 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4787 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4788 | (match_dup 1))) |
3298c037 AK |
4789 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") |
4790 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 4791 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4792 | "@ |
3298c037 AK |
4793 | sl<g>r\t%0,%2 |
4794 | sl<g>\t%0,%2 | |
4795 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4796 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4797 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4798 | |
43a09b63 | 4799 | ; slr, sl, sly, slgr, slg |
3298c037 | 4800 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 4801 | [(set (reg CC_REGNUM) |
3298c037 AK |
4802 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4803 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
07893d4f | 4804 | (match_dup 1))) |
3298c037 | 4805 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
b2ba71ca | 4806 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4807 | "@ |
3298c037 AK |
4808 | sl<g>r\t%0,%2 |
4809 | sl<g>\t%0,%2 | |
4810 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4811 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4812 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4813 | |
43a09b63 | 4814 | ; slr, sl, sly, slgr, slg |
3298c037 | 4815 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4816 | [(set (reg CC_REGNUM) |
3298c037 AK |
4817 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4818 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 4819 | (const_int 0))) |
3298c037 AK |
4820 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") |
4821 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 4822 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4823 | "@ |
3298c037 AK |
4824 | sl<g>r\t%0,%2 |
4825 | sl<g>\t%0,%2 | |
4826 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4827 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4828 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4829 | |
43a09b63 | 4830 | ; slr, sl, sly, slgr, slg |
3298c037 | 4831 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 4832 | [(set (reg CC_REGNUM) |
3298c037 AK |
4833 | (compare (match_operand:GPR 1 "register_operand" "0,0,0") |
4834 | (match_operand:GPR 2 "general_operand" "d,R,T"))) | |
4835 | (set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4836 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
5d880bd2 UW |
4837 | "s390_match_ccmode (insn, CCL3mode)" |
4838 | "@ | |
3298c037 AK |
4839 | sl<g>r\t%0,%2 |
4840 | sl<g>\t%0,%2 | |
4841 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4842 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4843 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 4844 | |
43a09b63 | 4845 | ; slr, sl, sly, slgr, slg |
3298c037 | 4846 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 4847 | [(set (reg CC_REGNUM) |
3298c037 AK |
4848 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0") |
4849 | (match_operand:GPR 2 "general_operand" "d,R,T")) | |
9db1d521 | 4850 | (const_int 0))) |
3298c037 | 4851 | (clobber (match_scratch:GPR 0 "=d,d,d"))] |
b2ba71ca | 4852 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4853 | "@ |
3298c037 AK |
4854 | sl<g>r\t%0,%2 |
4855 | sl<g>\t%0,%2 | |
4856 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4857 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4858 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4859 | ||
9db1d521 | 4860 | |
43a09b63 | 4861 | ; slr, sl, sly, slgr, slg |
3298c037 | 4862 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 4863 | [(set (reg CC_REGNUM) |
3298c037 AK |
4864 | (compare (match_operand:GPR 1 "register_operand" "0,0,0") |
4865 | (match_operand:GPR 2 "general_operand" "d,R,T"))) | |
4866 | (clobber (match_scratch:GPR 0 "=d,d,d"))] | |
5d880bd2 UW |
4867 | "s390_match_ccmode (insn, CCL3mode)" |
4868 | "@ | |
3298c037 AK |
4869 | sl<g>r\t%0,%2 |
4870 | sl<g>\t%0,%2 | |
4871 | sl<y>\t%0,%2" | |
9381e3f1 WG |
4872 | [(set_attr "op_type" "RR<E>,RX<Y>,RXY") |
4873 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")]) | |
4874 | ||
9db1d521 HP |
4875 | |
4876 | ; | |
609e7e80 | 4877 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4878 | ; |
4879 | ||
d46f24b6 | 4880 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 4881 | (define_insn "sub<mode>3" |
609e7e80 AK |
4882 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4883 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
142cd70f | 4884 | (match_operand:FP 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 4885 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4886 | "TARGET_HARD_FLOAT" |
9db1d521 | 4887 | "@ |
609e7e80 | 4888 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4889 | s<xde>b\t%0,%2" |
609e7e80 | 4890 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4891 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4892 | |
d46f24b6 | 4893 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 4894 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4895 | [(set (reg CC_REGNUM) |
609e7e80 | 4896 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 4897 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
4898 | (match_operand:FP 3 "const0_operand" ""))) |
4899 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
4900 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 4901 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4902 | "@ |
609e7e80 | 4903 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4904 | s<xde>b\t%0,%2" |
609e7e80 | 4905 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4906 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4907 | |
d46f24b6 | 4908 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 4909 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 4910 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4911 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
4912 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
4913 | (match_operand:FP 3 "const0_operand" ""))) | |
4914 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 4915 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4916 | "@ |
609e7e80 | 4917 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4918 | s<xde>b\t%0,%2" |
609e7e80 | 4919 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4920 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4921 | |
9db1d521 | 4922 | |
e69166de UW |
4923 | ;; |
4924 | ;;- Conditional add/subtract instructions. | |
4925 | ;; | |
4926 | ||
4927 | ; | |
9a91a21f | 4928 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
4929 | ; |
4930 | ||
a996720c UW |
4931 | ; the following 4 patterns are used when the result of an add with |
4932 | ; carry is checked for an overflow condition | |
4933 | ||
4934 | ; op1 + op2 + c < op1 | |
4935 | ||
4936 | ; alcr, alc, alcgr, alcg | |
4937 | (define_insn "*add<mode>3_alc_carry1_cc" | |
4938 | [(set (reg CC_REGNUM) | |
4939 | (compare | |
4940 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4941 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4942 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
4943 | (match_dup 1))) |
4944 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
4945 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
4946 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4947 | "@ | |
4948 | alc<g>r\t%0,%2 | |
4949 | alc<g>\t%0,%2" | |
4950 | [(set_attr "op_type" "RRE,RXY")]) | |
4951 | ||
4952 | ; alcr, alc, alcgr, alcg | |
4953 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
4954 | [(set (reg CC_REGNUM) | |
4955 | (compare | |
4956 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4957 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4958 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
4959 | (match_dup 1))) |
4960 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
4961 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4962 | "@ | |
4963 | alc<g>r\t%0,%2 | |
4964 | alc<g>\t%0,%2" | |
4965 | [(set_attr "op_type" "RRE,RXY")]) | |
4966 | ||
4967 | ; op1 + op2 + c < op2 | |
4968 | ||
4969 | ; alcr, alc, alcgr, alcg | |
4970 | (define_insn "*add<mode>3_alc_carry2_cc" | |
4971 | [(set (reg CC_REGNUM) | |
4972 | (compare | |
4973 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4974 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4975 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
4976 | (match_dup 2))) |
4977 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
4978 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
4979 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4980 | "@ | |
4981 | alc<g>r\t%0,%2 | |
4982 | alc<g>\t%0,%2" | |
4983 | [(set_attr "op_type" "RRE,RXY")]) | |
4984 | ||
4985 | ; alcr, alc, alcgr, alcg | |
4986 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
4987 | [(set (reg CC_REGNUM) | |
4988 | (compare | |
4989 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
4990 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 4991 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
4992 | (match_dup 2))) |
4993 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
4994 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
4995 | "@ | |
4996 | alc<g>r\t%0,%2 | |
4997 | alc<g>\t%0,%2" | |
4998 | [(set_attr "op_type" "RRE,RXY")]) | |
4999 | ||
43a09b63 | 5000 | ; alcr, alc, alcgr, alcg |
9a91a21f | 5001 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 5002 | [(set (reg CC_REGNUM) |
e69166de | 5003 | (compare |
a94a76a7 UW |
5004 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5005 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5006 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 5007 | (const_int 0))) |
9a91a21f | 5008 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 5009 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 5010 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5011 | "@ |
9a91a21f AS |
5012 | alc<g>r\t%0,%2 |
5013 | alc<g>\t%0,%2" | |
e69166de UW |
5014 | [(set_attr "op_type" "RRE,RXY")]) |
5015 | ||
43a09b63 | 5016 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
5017 | (define_insn "*add<mode>3_alc" |
5018 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
5019 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5020 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5021 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 5022 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5023 | "TARGET_CPU_ZARCH" |
e69166de | 5024 | "@ |
9a91a21f AS |
5025 | alc<g>r\t%0,%2 |
5026 | alc<g>\t%0,%2" | |
e69166de UW |
5027 | [(set_attr "op_type" "RRE,RXY")]) |
5028 | ||
43a09b63 | 5029 | ; slbr, slb, slbgr, slbg |
9a91a21f | 5030 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 5031 | [(set (reg CC_REGNUM) |
e69166de | 5032 | (compare |
9a91a21f | 5033 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 5034 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5035 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 5036 | (const_int 0))) |
9a91a21f AS |
5037 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
5038 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 5039 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5040 | "@ |
9a91a21f AS |
5041 | slb<g>r\t%0,%2 |
5042 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5043 | [(set_attr "op_type" "RRE,RXY") |
5044 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5045 | |
43a09b63 | 5046 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
5047 | (define_insn "*sub<mode>3_slb" |
5048 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5049 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 5050 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5051 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 5052 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5053 | "TARGET_CPU_ZARCH" |
e69166de | 5054 | "@ |
9a91a21f AS |
5055 | slb<g>r\t%0,%2 |
5056 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5057 | [(set_attr "op_type" "RRE,RXY") |
5058 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5059 | |
9a91a21f AS |
5060 | (define_expand "add<mode>cc" |
5061 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 5062 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
5063 | (match_operand:GPR 2 "register_operand" "") |
5064 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 5065 | "TARGET_CPU_ZARCH" |
9381e3f1 WG |
5066 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
5067 | s390_compare_op0, s390_compare_op1, | |
5068 | operands[0], operands[2], | |
5d880bd2 UW |
5069 | operands[3])) FAIL; DONE;") |
5070 | ||
5071 | ; | |
5072 | ; scond instruction pattern(s). | |
5073 | ; | |
5074 | ||
9a91a21f AS |
5075 | (define_insn_and_split "*scond<mode>" |
5076 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5077 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 5078 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5079 | "TARGET_CPU_ZARCH" |
5080 | "#" | |
5081 | "&& reload_completed" | |
5082 | [(set (match_dup 0) (const_int 0)) | |
5083 | (parallel | |
a94a76a7 UW |
5084 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
5085 | (match_dup 0))) | |
ae156f85 | 5086 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5087 | "") |
5d880bd2 | 5088 | |
9a91a21f AS |
5089 | (define_insn_and_split "*scond<mode>_neg" |
5090 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5091 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 5092 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5093 | "TARGET_CPU_ZARCH" |
5094 | "#" | |
5095 | "&& reload_completed" | |
5096 | [(set (match_dup 0) (const_int 0)) | |
5097 | (parallel | |
9a91a21f AS |
5098 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
5099 | (match_dup 1))) | |
ae156f85 | 5100 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 5101 | (parallel |
9a91a21f | 5102 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 5103 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5104 | "") |
5d880bd2 | 5105 | |
5d880bd2 | 5106 | |
9a91a21f AS |
5107 | (define_expand "s<code>" |
5108 | [(set (match_operand:SI 0 "register_operand" "") | |
5109 | (SCOND (match_dup 0) | |
5110 | (match_dup 0)))] | |
5d880bd2 | 5111 | "TARGET_CPU_ZARCH" |
9a91a21f | 5112 | "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1, |
5d880bd2 UW |
5113 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
5114 | ||
69950452 AS |
5115 | (define_expand "seq" |
5116 | [(parallel | |
5117 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5118 | (match_dup 1)) | |
5119 | (clobber (reg:CC CC_REGNUM))]) | |
5120 | (parallel | |
5121 | [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) | |
5122 | (clobber (reg:CC CC_REGNUM))])] | |
5123 | "" | |
9381e3f1 | 5124 | { |
69950452 AS |
5125 | if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) |
5126 | FAIL; | |
5127 | operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); | |
5128 | PUT_MODE (operands[1], SImode); | |
5129 | }) | |
5130 | ||
5131 | (define_insn_and_split "*sne" | |
5132 | [(set (match_operand:SI 0 "register_operand" "=d") | |
9381e3f1 | 5133 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
5134 | (const_int 0))) |
5135 | (clobber (reg:CC CC_REGNUM))] | |
5136 | "" | |
5137 | "#" | |
5138 | "reload_completed" | |
5139 | [(parallel | |
5140 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
5141 | (clobber (reg:CC CC_REGNUM))])]) | |
5142 | ||
e69166de | 5143 | |
9db1d521 HP |
5144 | ;; |
5145 | ;;- Multiply instructions. | |
5146 | ;; | |
5147 | ||
4023fb28 UW |
5148 | ; |
5149 | ; muldi3 instruction pattern(s). | |
5150 | ; | |
9db1d521 | 5151 | |
07893d4f UW |
5152 | (define_insn "*muldi3_sign" |
5153 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 5154 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5155 | (match_operand:DI 1 "register_operand" "0,0")))] |
5156 | "TARGET_64BIT" | |
5157 | "@ | |
d40c829f UW |
5158 | msgfr\t%0,%2 |
5159 | msgf\t%0,%2" | |
963fc8d0 AK |
5160 | [(set_attr "op_type" "RRE,RXY") |
5161 | (set_attr "type" "imuldi")]) | |
07893d4f | 5162 | |
4023fb28 | 5163 | (define_insn "muldi3" |
963fc8d0 AK |
5164 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
5165 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5166 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9db1d521 HP |
5167 | "TARGET_64BIT" |
5168 | "@ | |
d40c829f UW |
5169 | msgr\t%0,%2 |
5170 | mghi\t%0,%h2 | |
963fc8d0 AK |
5171 | msg\t%0,%2 |
5172 | msgfi\t%0,%2" | |
5173 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
5174 | (set_attr "type" "imuldi") | |
5175 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 5176 | |
9db1d521 HP |
5177 | ; |
5178 | ; mulsi3 instruction pattern(s). | |
5179 | ; | |
5180 | ||
f1e77d83 | 5181 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
5182 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
5183 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5184 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 5185 | "" |
963fc8d0 AK |
5186 | "@ |
5187 | mh\t%0,%2 | |
5188 | mhy\t%0,%2" | |
5189 | [(set_attr "op_type" "RX,RXY") | |
5190 | (set_attr "type" "imulhi") | |
5191 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 5192 | |
9db1d521 | 5193 | (define_insn "mulsi3" |
963fc8d0 AK |
5194 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
5195 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5196 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
5197 | "" |
5198 | "@ | |
d40c829f UW |
5199 | msr\t%0,%2 |
5200 | mhi\t%0,%h2 | |
5201 | ms\t%0,%2 | |
963fc8d0 AK |
5202 | msy\t%0,%2 |
5203 | msfi\t%0,%2" | |
5204 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
5205 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
5206 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 5207 | |
4023fb28 UW |
5208 | ; |
5209 | ; mulsidi3 instruction pattern(s). | |
5210 | ; | |
5211 | ||
f1e77d83 | 5212 | (define_insn "mulsidi3" |
963fc8d0 | 5213 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 5214 | (mult:DI (sign_extend:DI |
963fc8d0 | 5215 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 5216 | (sign_extend:DI |
963fc8d0 | 5217 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
4023fb28 | 5218 | "!TARGET_64BIT" |
f1e77d83 UW |
5219 | "@ |
5220 | mr\t%0,%2 | |
963fc8d0 AK |
5221 | m\t%0,%2 |
5222 | mfy\t%0,%2" | |
5223 | [(set_attr "op_type" "RR,RX,RXY") | |
5224 | (set_attr "type" "imulsi") | |
5225 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 5226 | |
f1e77d83 UW |
5227 | ; |
5228 | ; umulsidi3 instruction pattern(s). | |
5229 | ; | |
c7453384 | 5230 | |
f1e77d83 UW |
5231 | (define_insn "umulsidi3" |
5232 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5233 | (mult:DI (zero_extend:DI | |
5234 | (match_operand:SI 1 "register_operand" "%0,0")) | |
5235 | (zero_extend:DI | |
fb492564 | 5236 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))] |
f1e77d83 UW |
5237 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
5238 | "@ | |
5239 | mlr\t%0,%2 | |
5240 | ml\t%0,%2" | |
5241 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 5242 | (set_attr "type" "imulsi")]) |
c7453384 | 5243 | |
9db1d521 | 5244 | ; |
609e7e80 | 5245 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5246 | ; |
5247 | ||
9381e3f1 | 5248 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 5249 | (define_insn "mul<mode>3" |
609e7e80 AK |
5250 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5251 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
5252 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5253 | "TARGET_HARD_FLOAT" |
9db1d521 | 5254 | "@ |
609e7e80 | 5255 | m<xdee><bt>r\t%0,<op1>%2 |
f61a2c7d | 5256 | m<xdee>b\t%0,%2" |
609e7e80 | 5257 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5258 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 5259 | |
9381e3f1 | 5260 | ; madbr, maebr, maxb, madb, maeb |
f5905b37 | 5261 | (define_insn "*fmadd<mode>" |
f61a2c7d AK |
5262 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
5263 | (plus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "%f,f") | |
5264 | (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
5265 | (match_operand:DSF 3 "register_operand" "0,0")))] | |
142cd70f | 5266 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 5267 | "@ |
f61a2c7d AK |
5268 | ma<xde>br\t%0,%1,%2 |
5269 | ma<xde>b\t%0,%1,%2" | |
a1b892b5 | 5270 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 5271 | (set_attr "type" "fmul<mode>")]) |
a1b892b5 | 5272 | |
43a09b63 | 5273 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
f5905b37 | 5274 | (define_insn "*fmsub<mode>" |
f61a2c7d AK |
5275 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
5276 | (minus:DSF (mult:DSF (match_operand:DSF 1 "register_operand" "f,f") | |
5277 | (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
5278 | (match_operand:DSF 3 "register_operand" "0,0")))] | |
142cd70f | 5279 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 5280 | "@ |
f61a2c7d AK |
5281 | ms<xde>br\t%0,%1,%2 |
5282 | ms<xde>b\t%0,%1,%2" | |
ce50cae8 | 5283 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 5284 | (set_attr "type" "fmul<mode>")]) |
9db1d521 HP |
5285 | |
5286 | ;; | |
5287 | ;;- Divide and modulo instructions. | |
5288 | ;; | |
5289 | ||
5290 | ; | |
4023fb28 | 5291 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
5292 | ; |
5293 | ||
4023fb28 UW |
5294 | (define_expand "divmoddi4" |
5295 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 5296 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
5297 | (match_operand:DI 2 "general_operand" ""))) |
5298 | (set (match_operand:DI 3 "general_operand" "") | |
5299 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
5300 | (clobber (match_dup 4))] | |
9db1d521 | 5301 | "TARGET_64BIT" |
9db1d521 | 5302 | { |
f1e77d83 | 5303 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
5304 | |
5305 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
5306 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
5307 | |
5308 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 5309 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
5310 | |
5311 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5312 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5313 | |
5314 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5315 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5316 | |
9db1d521 | 5317 | DONE; |
10bbf137 | 5318 | }) |
9db1d521 HP |
5319 | |
5320 | (define_insn "divmodtidi3" | |
4023fb28 UW |
5321 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
5322 | (ior:TI | |
4023fb28 UW |
5323 | (ashift:TI |
5324 | (zero_extend:TI | |
5665e398 | 5325 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5326 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
5327 | (const_int 64)) |
5328 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
5329 | "TARGET_64BIT" |
5330 | "@ | |
d40c829f UW |
5331 | dsgr\t%0,%2 |
5332 | dsg\t%0,%2" | |
d3632d41 | 5333 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5334 | (set_attr "type" "idiv")]) |
9db1d521 | 5335 | |
4023fb28 UW |
5336 | (define_insn "divmodtisi3" |
5337 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5338 | (ior:TI | |
4023fb28 UW |
5339 | (ashift:TI |
5340 | (zero_extend:TI | |
5665e398 | 5341 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 5342 | (sign_extend:DI |
fb492564 | 5343 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
5344 | (const_int 64)) |
5345 | (zero_extend:TI | |
5346 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 5347 | "TARGET_64BIT" |
4023fb28 | 5348 | "@ |
d40c829f UW |
5349 | dsgfr\t%0,%2 |
5350 | dsgf\t%0,%2" | |
d3632d41 | 5351 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5352 | (set_attr "type" "idiv")]) |
9db1d521 | 5353 | |
4023fb28 UW |
5354 | ; |
5355 | ; udivmoddi4 instruction pattern(s). | |
5356 | ; | |
9db1d521 | 5357 | |
4023fb28 UW |
5358 | (define_expand "udivmoddi4" |
5359 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5360 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
5361 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
5362 | (set (match_operand:DI 3 "general_operand" "") | |
5363 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
5364 | (clobber (match_dup 4))] | |
9db1d521 | 5365 | "TARGET_64BIT" |
9db1d521 | 5366 | { |
4023fb28 UW |
5367 | rtx insn, div_equal, mod_equal, equal; |
5368 | ||
5369 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
5370 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
5371 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
5372 | gen_rtx_ASHIFT (TImode, |
5373 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
5374 | GEN_INT (64)), |
5375 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
5376 | |
5377 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 5378 | emit_clobber (operands[4]); |
4023fb28 UW |
5379 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
5380 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 5381 | |
4023fb28 | 5382 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5383 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5384 | |
5385 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5386 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5387 | |
5388 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5389 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5390 | |
9db1d521 | 5391 | DONE; |
10bbf137 | 5392 | }) |
9db1d521 HP |
5393 | |
5394 | (define_insn "udivmodtidi3" | |
4023fb28 | 5395 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 5396 | (ior:TI |
5665e398 UW |
5397 | (ashift:TI |
5398 | (zero_extend:TI | |
5399 | (truncate:DI | |
2f7e5a0d EC |
5400 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
5401 | (zero_extend:TI | |
fb492564 | 5402 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5403 | (const_int 64)) |
5404 | (zero_extend:TI | |
5405 | (truncate:DI | |
5406 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
5407 | "TARGET_64BIT" |
5408 | "@ | |
d40c829f UW |
5409 | dlgr\t%0,%2 |
5410 | dlg\t%0,%2" | |
d3632d41 | 5411 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5412 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5413 | |
5414 | ; | |
4023fb28 | 5415 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
5416 | ; |
5417 | ||
4023fb28 UW |
5418 | (define_expand "divmodsi4" |
5419 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5420 | (div:SI (match_operand:SI 1 "general_operand" "") | |
5421 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5422 | (set (match_operand:SI 3 "general_operand" "") | |
5423 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
5424 | (clobber (match_dup 4))] | |
9db1d521 | 5425 | "!TARGET_64BIT" |
9db1d521 | 5426 | { |
4023fb28 UW |
5427 | rtx insn, div_equal, mod_equal, equal; |
5428 | ||
5429 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
5430 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
5431 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5432 | gen_rtx_ASHIFT (DImode, |
5433 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5434 | GEN_INT (32)), |
5435 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
5436 | |
5437 | operands[4] = gen_reg_rtx(DImode); | |
5438 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 5439 | |
4023fb28 | 5440 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5441 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5442 | |
5443 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5444 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5445 | |
5446 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5447 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5448 | |
9db1d521 | 5449 | DONE; |
10bbf137 | 5450 | }) |
9db1d521 HP |
5451 | |
5452 | (define_insn "divmoddisi3" | |
4023fb28 | 5453 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 5454 | (ior:DI |
5665e398 UW |
5455 | (ashift:DI |
5456 | (zero_extend:DI | |
5457 | (truncate:SI | |
2f7e5a0d EC |
5458 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
5459 | (sign_extend:DI | |
5665e398 UW |
5460 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
5461 | (const_int 32)) | |
5462 | (zero_extend:DI | |
5463 | (truncate:SI | |
5464 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
5465 | "!TARGET_64BIT" |
5466 | "@ | |
d40c829f UW |
5467 | dr\t%0,%2 |
5468 | d\t%0,%2" | |
9db1d521 | 5469 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5470 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5471 | |
5472 | ; | |
5473 | ; udivsi3 and umodsi3 instruction pattern(s). | |
5474 | ; | |
5475 | ||
f1e77d83 UW |
5476 | (define_expand "udivmodsi4" |
5477 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5478 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5479 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5480 | (set (match_operand:SI 3 "general_operand" "") | |
5481 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
5482 | (clobber (match_dup 4))] | |
5483 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
5484 | { | |
5485 | rtx insn, div_equal, mod_equal, equal; | |
5486 | ||
5487 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5488 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5489 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
5490 | gen_rtx_ASHIFT (DImode, |
5491 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5492 | GEN_INT (32)), |
5493 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
5494 | |
5495 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 5496 | emit_clobber (operands[4]); |
f1e77d83 UW |
5497 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
5498 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 5499 | |
f1e77d83 | 5500 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5501 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
5502 | |
5503 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5504 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
5505 | |
5506 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5507 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
5508 | |
5509 | DONE; | |
5510 | }) | |
5511 | ||
5512 | (define_insn "udivmoddisi3" | |
5513 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 5514 | (ior:DI |
5665e398 UW |
5515 | (ashift:DI |
5516 | (zero_extend:DI | |
5517 | (truncate:SI | |
2f7e5a0d EC |
5518 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
5519 | (zero_extend:DI | |
fb492564 | 5520 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5521 | (const_int 32)) |
5522 | (zero_extend:DI | |
5523 | (truncate:SI | |
5524 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
5525 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
5526 | "@ | |
5527 | dlr\t%0,%2 | |
5528 | dl\t%0,%2" | |
5529 | [(set_attr "op_type" "RRE,RXY") | |
5530 | (set_attr "type" "idiv")]) | |
4023fb28 | 5531 | |
9db1d521 HP |
5532 | (define_expand "udivsi3" |
5533 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5534 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
5535 | (match_operand:SI 2 "general_operand" ""))) |
5536 | (clobber (match_dup 3))] | |
f1e77d83 | 5537 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 5538 | { |
4023fb28 UW |
5539 | rtx insn, udiv_equal, umod_equal, equal; |
5540 | ||
5541 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5542 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5543 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5544 | gen_rtx_ASHIFT (DImode, |
5545 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5546 | GEN_INT (32)), |
5547 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5548 | |
4023fb28 | 5549 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5550 | |
5551 | if (CONSTANT_P (operands[2])) | |
5552 | { | |
5553 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
5554 | { | |
5555 | rtx label1 = gen_label_rtx (); | |
5556 | ||
4023fb28 UW |
5557 | operands[1] = make_safe_from (operands[1], operands[0]); |
5558 | emit_move_insn (operands[0], const0_rtx); | |
5559 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 5560 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 5561 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5562 | emit_label (label1); |
5563 | } | |
5564 | else | |
5565 | { | |
c7453384 EC |
5566 | operands[2] = force_reg (SImode, operands[2]); |
5567 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5568 | |
5569 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5570 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5571 | operands[2])); | |
bd94cb6e | 5572 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5573 | |
5574 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5575 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 5576 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
5577 | } |
5578 | } | |
5579 | else | |
c7453384 | 5580 | { |
9db1d521 HP |
5581 | rtx label1 = gen_label_rtx (); |
5582 | rtx label2 = gen_label_rtx (); | |
5583 | rtx label3 = gen_label_rtx (); | |
5584 | ||
c7453384 EC |
5585 | operands[1] = force_reg (SImode, operands[1]); |
5586 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5587 | operands[2] = force_reg (SImode, operands[2]); | |
5588 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5589 | |
5590 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
5591 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
5592 | emit_jump_insn (gen_bgtu (label3)); | |
220a826e | 5593 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
5594 | emit_jump_insn (gen_blt (label2)); |
5595 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5596 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
5597 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5598 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5599 | operands[2])); | |
bd94cb6e | 5600 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5601 | |
5602 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5603 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
5604 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
5605 | ||
f314b9b1 | 5606 | emit_jump (label3); |
9db1d521 | 5607 | emit_label (label1); |
4023fb28 | 5608 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 5609 | emit_jump (label3); |
9db1d521 | 5610 | emit_label (label2); |
4023fb28 | 5611 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5612 | emit_label (label3); |
5613 | } | |
c7453384 | 5614 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 5615 | DONE; |
10bbf137 | 5616 | }) |
9db1d521 HP |
5617 | |
5618 | (define_expand "umodsi3" | |
5619 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5620 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
5621 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
5622 | (clobber (match_dup 3))] | |
f1e77d83 | 5623 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 5624 | { |
4023fb28 UW |
5625 | rtx insn, udiv_equal, umod_equal, equal; |
5626 | ||
5627 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5628 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5629 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5630 | gen_rtx_ASHIFT (DImode, |
5631 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5632 | GEN_INT (32)), |
5633 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5634 | |
4023fb28 | 5635 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5636 | |
5637 | if (CONSTANT_P (operands[2])) | |
5638 | { | |
5639 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
5640 | { | |
5641 | rtx label1 = gen_label_rtx (); | |
5642 | ||
4023fb28 UW |
5643 | operands[1] = make_safe_from (operands[1], operands[0]); |
5644 | emit_move_insn (operands[0], operands[1]); | |
5645 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 5646 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
5647 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
5648 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
5649 | emit_label (label1); |
5650 | } | |
5651 | else | |
5652 | { | |
c7453384 EC |
5653 | operands[2] = force_reg (SImode, operands[2]); |
5654 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5655 | |
5656 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5657 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5658 | operands[2])); | |
bd94cb6e | 5659 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5660 | |
5661 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5662 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 5663 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
5664 | } |
5665 | } | |
5666 | else | |
5667 | { | |
5668 | rtx label1 = gen_label_rtx (); | |
5669 | rtx label2 = gen_label_rtx (); | |
5670 | rtx label3 = gen_label_rtx (); | |
5671 | ||
c7453384 EC |
5672 | operands[1] = force_reg (SImode, operands[1]); |
5673 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5674 | operands[2] = force_reg (SImode, operands[2]); | |
5675 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5676 | |
c7453384 | 5677 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 5678 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 | 5679 | emit_jump_insn (gen_bgtu (label3)); |
220a826e | 5680 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
5681 | emit_jump_insn (gen_blt (label2)); |
5682 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5683 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
5684 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5685 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5686 | operands[2])); | |
bd94cb6e | 5687 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5688 | |
5689 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5690 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
5691 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
5692 | ||
f314b9b1 | 5693 | emit_jump (label3); |
9db1d521 | 5694 | emit_label (label1); |
4023fb28 | 5695 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5696 | emit_jump (label3); |
9db1d521 | 5697 | emit_label (label2); |
4023fb28 | 5698 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5699 | emit_label (label3); |
5700 | } | |
9db1d521 | 5701 | DONE; |
10bbf137 | 5702 | }) |
9db1d521 HP |
5703 | |
5704 | ; | |
f5905b37 | 5705 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
5706 | ; |
5707 | ||
609e7e80 | 5708 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 5709 | (define_insn "div<mode>3" |
609e7e80 AK |
5710 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5711 | (div:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
5712 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5713 | "TARGET_HARD_FLOAT" |
9db1d521 | 5714 | "@ |
609e7e80 | 5715 | d<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5716 | d<xde>b\t%0,%2" |
609e7e80 | 5717 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5718 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 5719 | |
9db1d521 HP |
5720 | |
5721 | ;; | |
5722 | ;;- And instructions. | |
5723 | ;; | |
5724 | ||
047d35ed AS |
5725 | (define_expand "and<mode>3" |
5726 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5727 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5728 | (match_operand:INT 2 "general_operand" ""))) | |
5729 | (clobber (reg:CC CC_REGNUM))] | |
5730 | "" | |
5731 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
5732 | ||
9db1d521 HP |
5733 | ; |
5734 | ; anddi3 instruction pattern(s). | |
5735 | ; | |
5736 | ||
5737 | (define_insn "*anddi3_cc" | |
ae156f85 | 5738 | [(set (reg CC_REGNUM) |
96fd3851 | 5739 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 5740 | (match_operand:DI 2 "general_operand" "d,RT")) |
9db1d521 | 5741 | (const_int 0))) |
4023fb28 | 5742 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
5743 | (and:DI (match_dup 1) (match_dup 2)))] |
5744 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5745 | "@ | |
d40c829f UW |
5746 | ngr\t%0,%2 |
5747 | ng\t%0,%2" | |
9381e3f1 WG |
5748 | [(set_attr "op_type" "RRE,RXY") |
5749 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
5750 | |
5751 | (define_insn "*anddi3_cconly" | |
ae156f85 | 5752 | [(set (reg CC_REGNUM) |
96fd3851 | 5753 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 5754 | (match_operand:DI 2 "general_operand" "d,RT")) |
9db1d521 HP |
5755 | (const_int 0))) |
5756 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
5757 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
5758 | /* Do not steal TM patterns. */ | |
5759 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 5760 | "@ |
d40c829f UW |
5761 | ngr\t%0,%2 |
5762 | ng\t%0,%2" | |
9381e3f1 WG |
5763 | [(set_attr "op_type" "RRE,RXY") |
5764 | (set_attr "z10prop" "z10_super_E1, z10_super_E1")]) | |
9db1d521 | 5765 | |
3af8e996 | 5766 | (define_insn "*anddi3" |
ec24698e UW |
5767 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") |
5768 | (and:DI (match_operand:DI 1 "nonimmediate_operand" | |
5769 | "%d,o,0,0,0,0,0,0,0,0,0,0") | |
5770 | (match_operand:DI 2 "general_operand" | |
fb492564 | 5771 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q"))) |
ec24698e | 5772 | (clobber (reg:CC CC_REGNUM))] |
3af8e996 | 5773 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
5774 | "@ |
5775 | # | |
5776 | # | |
5777 | nihh\t%0,%j2 | |
5778 | nihl\t%0,%j2 | |
5779 | nilh\t%0,%j2 | |
5780 | nill\t%0,%j2 | |
5781 | nihf\t%0,%m2 | |
5782 | nilf\t%0,%m2 | |
5783 | ngr\t%0,%2 | |
5784 | ng\t%0,%2 | |
5785 | # | |
5786 | #" | |
3af8e996 | 5787 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") |
9381e3f1 WG |
5788 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*") |
5789 | (set_attr "z10prop" "*, | |
5790 | *, | |
5791 | z10_super_E1, | |
5792 | z10_super_E1, | |
5793 | z10_super_E1, | |
5794 | z10_super_E1, | |
5795 | z10_super_E1, | |
5796 | z10_super_E1, | |
5797 | z10_super_E1, | |
5798 | z10_super_E1, | |
5799 | *, | |
5800 | *")]) | |
0dfa6c5e UW |
5801 | |
5802 | (define_split | |
5803 | [(set (match_operand:DI 0 "s_operand" "") | |
5804 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5805 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5806 | "reload_completed" |
5807 | [(parallel | |
5808 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5809 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5810 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5811 | |
9db1d521 HP |
5812 | |
5813 | ; | |
5814 | ; andsi3 instruction pattern(s). | |
5815 | ; | |
5816 | ||
5817 | (define_insn "*andsi3_cc" | |
ae156f85 | 5818 | [(set (reg CC_REGNUM) |
ec24698e UW |
5819 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5820 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5821 | (const_int 0))) |
ec24698e | 5822 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
9db1d521 HP |
5823 | (and:SI (match_dup 1) (match_dup 2)))] |
5824 | "s390_match_ccmode(insn, CCTmode)" | |
5825 | "@ | |
ec24698e | 5826 | nilf\t%0,%o2 |
d40c829f UW |
5827 | nr\t%0,%2 |
5828 | n\t%0,%2 | |
5829 | ny\t%0,%2" | |
9381e3f1 WG |
5830 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
5831 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
5832 | |
5833 | (define_insn "*andsi3_cconly" | |
ae156f85 | 5834 | [(set (reg CC_REGNUM) |
ec24698e UW |
5835 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5836 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5837 | (const_int 0))) |
ec24698e | 5838 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
68f9c5e2 UW |
5839 | "s390_match_ccmode(insn, CCTmode) |
5840 | /* Do not steal TM patterns. */ | |
5841 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 5842 | "@ |
ec24698e | 5843 | nilf\t%0,%o2 |
d40c829f UW |
5844 | nr\t%0,%2 |
5845 | n\t%0,%2 | |
5846 | ny\t%0,%2" | |
9381e3f1 WG |
5847 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
5848 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5849 | |
f19a9af7 | 5850 | (define_insn "*andsi3_zarch" |
ec24698e | 5851 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
0dfa6c5e | 5852 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
ec24698e | 5853 | "%d,o,0,0,0,0,0,0,0,0") |
0dfa6c5e | 5854 | (match_operand:SI 2 "general_operand" |
ec24698e | 5855 | "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q"))) |
ae156f85 | 5856 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5857 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5858 | "@ |
f19a9af7 AK |
5859 | # |
5860 | # | |
5861 | nilh\t%0,%j2 | |
2f7e5a0d | 5862 | nill\t%0,%j2 |
ec24698e | 5863 | nilf\t%0,%o2 |
d40c829f UW |
5864 | nr\t%0,%2 |
5865 | n\t%0,%2 | |
8cb66696 | 5866 | ny\t%0,%2 |
0dfa6c5e | 5867 | # |
19b63d8e | 5868 | #" |
9381e3f1 WG |
5869 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS") |
5870 | (set_attr "z10prop" "*, | |
5871 | *, | |
5872 | z10_super_E1, | |
5873 | z10_super_E1, | |
5874 | z10_super_E1, | |
5875 | z10_super_E1, | |
5876 | z10_super_E1, | |
5877 | z10_super_E1, | |
5878 | *, | |
5879 | *")]) | |
f19a9af7 AK |
5880 | |
5881 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
5882 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5883 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5884 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
ae156f85 | 5885 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5886 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5887 | "@ |
5888 | nr\t%0,%2 | |
8cb66696 | 5889 | n\t%0,%2 |
0dfa6c5e | 5890 | # |
19b63d8e | 5891 | #" |
9381e3f1 WG |
5892 | [(set_attr "op_type" "RR,RX,SI,SS") |
5893 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
5894 | ||
0dfa6c5e UW |
5895 | |
5896 | (define_split | |
5897 | [(set (match_operand:SI 0 "s_operand" "") | |
5898 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5899 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5900 | "reload_completed" |
5901 | [(parallel | |
5902 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5903 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5904 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5905 | |
9db1d521 HP |
5906 | ; |
5907 | ; andhi3 instruction pattern(s). | |
5908 | ; | |
5909 | ||
8cb66696 | 5910 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
5911 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5912 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5913 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
ae156f85 | 5914 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5915 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5916 | "@ |
d40c829f | 5917 | nr\t%0,%2 |
8cb66696 | 5918 | nill\t%0,%x2 |
0dfa6c5e | 5919 | # |
19b63d8e | 5920 | #" |
9381e3f1 WG |
5921 | [(set_attr "op_type" "RR,RI,SI,SS") |
5922 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*") | |
5923 | ]) | |
8cb66696 UW |
5924 | |
5925 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
5926 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5927 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5928 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 5929 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5930 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5931 | "@ | |
5932 | nr\t%0,%2 | |
0dfa6c5e | 5933 | # |
19b63d8e | 5934 | #" |
9381e3f1 WG |
5935 | [(set_attr "op_type" "RR,SI,SS") |
5936 | (set_attr "z10prop" "z10_super_E1,*,*") | |
5937 | ]) | |
0dfa6c5e UW |
5938 | |
5939 | (define_split | |
5940 | [(set (match_operand:HI 0 "s_operand" "") | |
5941 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5942 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5943 | "reload_completed" |
5944 | [(parallel | |
5945 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5946 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5947 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 5948 | |
9db1d521 HP |
5949 | ; |
5950 | ; andqi3 instruction pattern(s). | |
5951 | ; | |
5952 | ||
8cb66696 UW |
5953 | (define_insn "*andqi3_zarch" |
5954 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5955 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5956 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5957 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5958 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5959 | "@ |
d40c829f | 5960 | nr\t%0,%2 |
8cb66696 | 5961 | nill\t%0,%b2 |
fc0ea003 UW |
5962 | ni\t%S0,%b2 |
5963 | niy\t%S0,%b2 | |
19b63d8e | 5964 | #" |
9381e3f1 WG |
5965 | [(set_attr "op_type" "RR,RI,SI,SIY,SS") |
5966 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
5967 | |
5968 | (define_insn "*andqi3_esa" | |
5969 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5970 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5971 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5972 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5973 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5974 | "@ |
8cb66696 | 5975 | nr\t%0,%2 |
fc0ea003 | 5976 | ni\t%S0,%b2 |
19b63d8e | 5977 | #" |
9381e3f1 WG |
5978 | [(set_attr "op_type" "RR,SI,SS") |
5979 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 5980 | |
19b63d8e UW |
5981 | ; |
5982 | ; Block and (NC) patterns. | |
5983 | ; | |
5984 | ||
5985 | (define_insn "*nc" | |
5986 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5987 | (and:BLK (match_dup 0) | |
5988 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5989 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5990 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5991 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5992 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 5993 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5994 | |
5995 | (define_split | |
5996 | [(set (match_operand 0 "memory_operand" "") | |
5997 | (and (match_dup 0) | |
5998 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5999 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6000 | "reload_completed |
6001 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6002 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6003 | [(parallel | |
6004 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
6005 | (use (match_dup 2)) | |
ae156f85 | 6006 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6007 | { |
6008 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6009 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6010 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6011 | }) | |
6012 | ||
6013 | (define_peephole2 | |
6014 | [(parallel | |
6015 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6016 | (and:BLK (match_dup 0) | |
6017 | (match_operand:BLK 1 "memory_operand" ""))) | |
6018 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6019 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6020 | (parallel |
6021 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6022 | (and:BLK (match_dup 3) | |
6023 | (match_operand:BLK 4 "memory_operand" ""))) | |
6024 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6025 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6026 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6027 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6028 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6029 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6030 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6031 | [(parallel | |
6032 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
6033 | (use (match_dup 8)) | |
ae156f85 | 6034 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6035 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6036 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6037 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6038 | ||
9db1d521 HP |
6039 | |
6040 | ;; | |
6041 | ;;- Bit set (inclusive or) instructions. | |
6042 | ;; | |
6043 | ||
047d35ed AS |
6044 | (define_expand "ior<mode>3" |
6045 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6046 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6047 | (match_operand:INT 2 "general_operand" ""))) | |
6048 | (clobber (reg:CC CC_REGNUM))] | |
6049 | "" | |
6050 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
6051 | ||
9db1d521 HP |
6052 | ; |
6053 | ; iordi3 instruction pattern(s). | |
6054 | ; | |
6055 | ||
4023fb28 | 6056 | (define_insn "*iordi3_cc" |
ae156f85 | 6057 | [(set (reg CC_REGNUM) |
96fd3851 | 6058 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 6059 | (match_operand:DI 2 "general_operand" "d,RT")) |
4023fb28 UW |
6060 | (const_int 0))) |
6061 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6062 | (ior:DI (match_dup 1) (match_dup 2)))] | |
6063 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6064 | "@ | |
d40c829f UW |
6065 | ogr\t%0,%2 |
6066 | og\t%0,%2" | |
9381e3f1 WG |
6067 | [(set_attr "op_type" "RRE,RXY") |
6068 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6069 | |
6070 | (define_insn "*iordi3_cconly" | |
ae156f85 | 6071 | [(set (reg CC_REGNUM) |
96fd3851 | 6072 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 6073 | (match_operand:DI 2 "general_operand" "d,RT")) |
4023fb28 UW |
6074 | (const_int 0))) |
6075 | (clobber (match_scratch:DI 0 "=d,d"))] | |
6076 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6077 | "@ | |
d40c829f UW |
6078 | ogr\t%0,%2 |
6079 | og\t%0,%2" | |
9381e3f1 WG |
6080 | [(set_attr "op_type" "RRE,RXY") |
6081 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6082 | |
3af8e996 | 6083 | (define_insn "*iordi3" |
ec24698e UW |
6084 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
6085 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") | |
6086 | (match_operand:DI 2 "general_operand" | |
fb492564 | 6087 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q"))) |
ec24698e | 6088 | (clobber (reg:CC CC_REGNUM))] |
3af8e996 | 6089 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6090 | "@ |
6091 | oihh\t%0,%i2 | |
6092 | oihl\t%0,%i2 | |
6093 | oilh\t%0,%i2 | |
6094 | oill\t%0,%i2 | |
6095 | oihf\t%0,%k2 | |
6096 | oilf\t%0,%k2 | |
6097 | ogr\t%0,%2 | |
6098 | og\t%0,%2 | |
6099 | # | |
6100 | #" | |
3af8e996 | 6101 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS") |
9381e3f1 WG |
6102 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*") |
6103 | (set_attr "z10prop" "z10_super_E1, | |
6104 | z10_super_E1, | |
6105 | z10_super_E1, | |
6106 | z10_super_E1, | |
6107 | z10_super_E1, | |
6108 | z10_super_E1, | |
6109 | z10_super_E1, | |
6110 | z10_super_E1, | |
6111 | *, | |
6112 | *")]) | |
0dfa6c5e UW |
6113 | |
6114 | (define_split | |
6115 | [(set (match_operand:DI 0 "s_operand" "") | |
6116 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6117 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6118 | "reload_completed" |
6119 | [(parallel | |
6120 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6121 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6122 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6123 | |
9db1d521 HP |
6124 | ; |
6125 | ; iorsi3 instruction pattern(s). | |
6126 | ; | |
6127 | ||
4023fb28 | 6128 | (define_insn "*iorsi3_cc" |
ae156f85 | 6129 | [(set (reg CC_REGNUM) |
ec24698e UW |
6130 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
6131 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 6132 | (const_int 0))) |
ec24698e | 6133 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
6134 | (ior:SI (match_dup 1) (match_dup 2)))] |
6135 | "s390_match_ccmode(insn, CCTmode)" | |
6136 | "@ | |
ec24698e | 6137 | oilf\t%0,%o2 |
d40c829f UW |
6138 | or\t%0,%2 |
6139 | o\t%0,%2 | |
6140 | oy\t%0,%2" | |
9381e3f1 WG |
6141 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
6142 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6143 | |
6144 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 6145 | [(set (reg CC_REGNUM) |
ec24698e UW |
6146 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
6147 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 6148 | (const_int 0))) |
ec24698e | 6149 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
6150 | "s390_match_ccmode(insn, CCTmode)" |
6151 | "@ | |
ec24698e | 6152 | oilf\t%0,%o2 |
d40c829f UW |
6153 | or\t%0,%2 |
6154 | o\t%0,%2 | |
6155 | oy\t%0,%2" | |
9381e3f1 WG |
6156 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
6157 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6158 | |
8cb66696 | 6159 | (define_insn "*iorsi3_zarch" |
ec24698e UW |
6160 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
6161 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") | |
6162 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6163 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6164 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6165 | "@ |
f19a9af7 AK |
6166 | oilh\t%0,%i2 |
6167 | oill\t%0,%i2 | |
ec24698e | 6168 | oilf\t%0,%o2 |
d40c829f UW |
6169 | or\t%0,%2 |
6170 | o\t%0,%2 | |
8cb66696 | 6171 | oy\t%0,%2 |
0dfa6c5e | 6172 | # |
19b63d8e | 6173 | #" |
9381e3f1 WG |
6174 | [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS") |
6175 | (set_attr "z10prop" "z10_super_E1, | |
6176 | z10_super_E1, | |
6177 | z10_super_E1, | |
6178 | z10_super_E1, | |
6179 | z10_super_E1, | |
6180 | z10_super_E1, | |
6181 | *, | |
6182 | *")]) | |
8cb66696 UW |
6183 | |
6184 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 6185 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 6186 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 6187 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 6188 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6189 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6190 | "@ |
6191 | or\t%0,%2 | |
8cb66696 | 6192 | o\t%0,%2 |
0dfa6c5e | 6193 | # |
19b63d8e | 6194 | #" |
9381e3f1 WG |
6195 | [(set_attr "op_type" "RR,RX,SI,SS") |
6196 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6197 | |
6198 | (define_split | |
6199 | [(set (match_operand:SI 0 "s_operand" "") | |
6200 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6201 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6202 | "reload_completed" |
6203 | [(parallel | |
6204 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6205 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6206 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6207 | |
4023fb28 UW |
6208 | ; |
6209 | ; iorhi3 instruction pattern(s). | |
6210 | ; | |
6211 | ||
8cb66696 | 6212 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
6213 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
6214 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
6215 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
ae156f85 | 6216 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6217 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6218 | "@ |
d40c829f | 6219 | or\t%0,%2 |
8cb66696 | 6220 | oill\t%0,%x2 |
0dfa6c5e | 6221 | # |
19b63d8e | 6222 | #" |
9381e3f1 WG |
6223 | [(set_attr "op_type" "RR,RI,SI,SS") |
6224 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
8cb66696 UW |
6225 | |
6226 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
6227 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6228 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6229 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 6230 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6231 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6232 | "@ | |
6233 | or\t%0,%2 | |
0dfa6c5e | 6234 | # |
19b63d8e | 6235 | #" |
9381e3f1 WG |
6236 | [(set_attr "op_type" "RR,SI,SS") |
6237 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6238 | |
6239 | (define_split | |
6240 | [(set (match_operand:HI 0 "s_operand" "") | |
6241 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6242 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6243 | "reload_completed" |
6244 | [(parallel | |
6245 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6246 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6247 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 6248 | |
9db1d521 | 6249 | ; |
4023fb28 | 6250 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
6251 | ; |
6252 | ||
8cb66696 UW |
6253 | (define_insn "*iorqi3_zarch" |
6254 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
6255 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6256 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 6257 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6258 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6259 | "@ |
d40c829f | 6260 | or\t%0,%2 |
8cb66696 | 6261 | oill\t%0,%b2 |
fc0ea003 UW |
6262 | oi\t%S0,%b2 |
6263 | oiy\t%S0,%b2 | |
19b63d8e | 6264 | #" |
9381e3f1 WG |
6265 | [(set_attr "op_type" "RR,RI,SI,SIY,SS") |
6266 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
6267 | |
6268 | (define_insn "*iorqi3_esa" | |
6269 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6270 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6271 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6272 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6273 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6274 | "@ |
8cb66696 | 6275 | or\t%0,%2 |
fc0ea003 | 6276 | oi\t%S0,%b2 |
19b63d8e | 6277 | #" |
9381e3f1 WG |
6278 | [(set_attr "op_type" "RR,SI,SS") |
6279 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 6280 | |
19b63d8e UW |
6281 | ; |
6282 | ; Block inclusive or (OC) patterns. | |
6283 | ; | |
6284 | ||
6285 | (define_insn "*oc" | |
6286 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6287 | (ior:BLK (match_dup 0) | |
6288 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6289 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6290 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6291 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6292 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 6293 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6294 | |
6295 | (define_split | |
6296 | [(set (match_operand 0 "memory_operand" "") | |
6297 | (ior (match_dup 0) | |
6298 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6299 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6300 | "reload_completed |
6301 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6302 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6303 | [(parallel | |
6304 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
6305 | (use (match_dup 2)) | |
ae156f85 | 6306 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6307 | { |
6308 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6309 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6310 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6311 | }) | |
6312 | ||
6313 | (define_peephole2 | |
6314 | [(parallel | |
6315 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6316 | (ior:BLK (match_dup 0) | |
6317 | (match_operand:BLK 1 "memory_operand" ""))) | |
6318 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6319 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6320 | (parallel |
6321 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6322 | (ior:BLK (match_dup 3) | |
6323 | (match_operand:BLK 4 "memory_operand" ""))) | |
6324 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6325 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6326 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6327 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6328 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6329 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6330 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6331 | [(parallel | |
6332 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
6333 | (use (match_dup 8)) | |
ae156f85 | 6334 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6335 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6336 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6337 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6338 | ||
9db1d521 HP |
6339 | |
6340 | ;; | |
6341 | ;;- Xor instructions. | |
6342 | ;; | |
6343 | ||
047d35ed AS |
6344 | (define_expand "xor<mode>3" |
6345 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6346 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6347 | (match_operand:INT 2 "general_operand" ""))) | |
6348 | (clobber (reg:CC CC_REGNUM))] | |
6349 | "" | |
6350 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
6351 | ||
9db1d521 HP |
6352 | ; |
6353 | ; xordi3 instruction pattern(s). | |
6354 | ; | |
6355 | ||
4023fb28 | 6356 | (define_insn "*xordi3_cc" |
ae156f85 | 6357 | [(set (reg CC_REGNUM) |
96fd3851 | 6358 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 6359 | (match_operand:DI 2 "general_operand" "d,RT")) |
4023fb28 UW |
6360 | (const_int 0))) |
6361 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6362 | (xor:DI (match_dup 1) (match_dup 2)))] | |
6363 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6364 | "@ | |
d40c829f UW |
6365 | xgr\t%0,%2 |
6366 | xg\t%0,%2" | |
9381e3f1 WG |
6367 | [(set_attr "op_type" "RRE,RXY") |
6368 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6369 | |
6370 | (define_insn "*xordi3_cconly" | |
ae156f85 | 6371 | [(set (reg CC_REGNUM) |
96fd3851 | 6372 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
fb492564 | 6373 | (match_operand:DI 2 "general_operand" "d,RT")) |
4023fb28 UW |
6374 | (const_int 0))) |
6375 | (clobber (match_scratch:DI 0 "=d,d"))] | |
6376 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
6377 | "@ | |
d40c829f | 6378 | xgr\t%0,%2 |
c7fd8cd8 | 6379 | xg\t%0,%2" |
9381e3f1 WG |
6380 | [(set_attr "op_type" "RRE,RXY") |
6381 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6382 | |
3af8e996 | 6383 | (define_insn "*xordi3" |
ec24698e UW |
6384 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") |
6385 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
fb492564 | 6386 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q"))) |
ec24698e | 6387 | (clobber (reg:CC CC_REGNUM))] |
3af8e996 | 6388 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6389 | "@ |
6390 | xihf\t%0,%k2 | |
6391 | xilf\t%0,%k2 | |
6392 | xgr\t%0,%2 | |
6393 | xg\t%0,%2 | |
6394 | # | |
6395 | #" | |
3af8e996 | 6396 | [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS") |
9381e3f1 WG |
6397 | (set_attr "cpu_facility" "extimm,extimm,*,*,*,*") |
6398 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6399 | |
6400 | (define_split | |
6401 | [(set (match_operand:DI 0 "s_operand" "") | |
6402 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6403 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6404 | "reload_completed" |
6405 | [(parallel | |
6406 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6407 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6408 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 6409 | |
9db1d521 HP |
6410 | ; |
6411 | ; xorsi3 instruction pattern(s). | |
6412 | ; | |
6413 | ||
4023fb28 | 6414 | (define_insn "*xorsi3_cc" |
ae156f85 | 6415 | [(set (reg CC_REGNUM) |
ec24698e UW |
6416 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
6417 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 6418 | (const_int 0))) |
ec24698e | 6419 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
6420 | (xor:SI (match_dup 1) (match_dup 2)))] |
6421 | "s390_match_ccmode(insn, CCTmode)" | |
6422 | "@ | |
ec24698e | 6423 | xilf\t%0,%o2 |
d40c829f UW |
6424 | xr\t%0,%2 |
6425 | x\t%0,%2 | |
6426 | xy\t%0,%2" | |
9381e3f1 WG |
6427 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
6428 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6429 | |
6430 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 6431 | [(set (reg CC_REGNUM) |
ec24698e UW |
6432 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
6433 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 6434 | (const_int 0))) |
ec24698e | 6435 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
6436 | "s390_match_ccmode(insn, CCTmode)" |
6437 | "@ | |
ec24698e | 6438 | xilf\t%0,%o2 |
d40c829f UW |
6439 | xr\t%0,%2 |
6440 | x\t%0,%2 | |
6441 | xy\t%0,%2" | |
9381e3f1 WG |
6442 | [(set_attr "op_type" "RIL,RR,RX,RXY") |
6443 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6444 | |
8cb66696 | 6445 | (define_insn "*xorsi3" |
ec24698e UW |
6446 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") |
6447 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
6448 | (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6449 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6450 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6451 | "@ |
ec24698e | 6452 | xilf\t%0,%o2 |
d40c829f UW |
6453 | xr\t%0,%2 |
6454 | x\t%0,%2 | |
8cb66696 | 6455 | xy\t%0,%2 |
0dfa6c5e | 6456 | # |
19b63d8e | 6457 | #" |
9381e3f1 WG |
6458 | [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS") |
6459 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6460 | |
6461 | (define_split | |
6462 | [(set (match_operand:SI 0 "s_operand" "") | |
6463 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6464 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6465 | "reload_completed" |
6466 | [(parallel | |
6467 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6468 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6469 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 6470 | |
9db1d521 HP |
6471 | ; |
6472 | ; xorhi3 instruction pattern(s). | |
6473 | ; | |
6474 | ||
8cb66696 | 6475 | (define_insn "*xorhi3" |
ec24698e UW |
6476 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
6477 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
6478 | (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q"))) | |
ae156f85 | 6479 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6480 | "s390_logical_operator_ok_p (operands)" |
6481 | "@ | |
ec24698e | 6482 | xilf\t%0,%x2 |
8cb66696 | 6483 | xr\t%0,%2 |
0dfa6c5e | 6484 | # |
19b63d8e | 6485 | #" |
9381e3f1 WG |
6486 | [(set_attr "op_type" "RIL,RR,SI,SS") |
6487 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6488 | |
6489 | (define_split | |
6490 | [(set (match_operand:HI 0 "s_operand" "") | |
6491 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6492 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6493 | "reload_completed" |
6494 | [(parallel | |
6495 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6496 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6497 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 6498 | |
9db1d521 HP |
6499 | ; |
6500 | ; xorqi3 instruction pattern(s). | |
6501 | ; | |
6502 | ||
8cb66696 | 6503 | (define_insn "*xorqi3" |
ec24698e UW |
6504 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") |
6505 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6506 | (match_operand:QI 2 "general_operand" "Os,d,n,n,Q"))) | |
ae156f85 | 6507 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6508 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6509 | "@ |
ec24698e | 6510 | xilf\t%0,%b2 |
8cb66696 | 6511 | xr\t%0,%2 |
fc0ea003 UW |
6512 | xi\t%S0,%b2 |
6513 | xiy\t%S0,%b2 | |
19b63d8e | 6514 | #" |
9381e3f1 WG |
6515 | [(set_attr "op_type" "RIL,RR,SI,SIY,SS") |
6516 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")]) | |
6517 | ||
4023fb28 | 6518 | |
19b63d8e UW |
6519 | ; |
6520 | ; Block exclusive or (XC) patterns. | |
6521 | ; | |
6522 | ||
6523 | (define_insn "*xc" | |
6524 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6525 | (xor:BLK (match_dup 0) | |
6526 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6527 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6528 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6529 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6530 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 6531 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6532 | |
6533 | (define_split | |
6534 | [(set (match_operand 0 "memory_operand" "") | |
6535 | (xor (match_dup 0) | |
6536 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6537 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6538 | "reload_completed |
6539 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6540 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6541 | [(parallel | |
6542 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
6543 | (use (match_dup 2)) | |
ae156f85 | 6544 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6545 | { |
6546 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6547 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6548 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6549 | }) | |
6550 | ||
6551 | (define_peephole2 | |
6552 | [(parallel | |
6553 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6554 | (xor:BLK (match_dup 0) | |
6555 | (match_operand:BLK 1 "memory_operand" ""))) | |
6556 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6557 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6558 | (parallel |
6559 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6560 | (xor:BLK (match_dup 3) | |
6561 | (match_operand:BLK 4 "memory_operand" ""))) | |
6562 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6563 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6564 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6565 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6566 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6567 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6568 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6569 | [(parallel | |
6570 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
6571 | (use (match_dup 8)) | |
ae156f85 | 6572 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6573 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6574 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6575 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6576 | ||
6577 | ; | |
6578 | ; Block xor (XC) patterns with src == dest. | |
6579 | ; | |
6580 | ||
6581 | (define_insn "*xc_zero" | |
6582 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6583 | (const_int 0)) | |
6584 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 6585 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6586 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 6587 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 6588 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6589 | |
6590 | (define_peephole2 | |
6591 | [(parallel | |
6592 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6593 | (const_int 0)) | |
6594 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 6595 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6596 | (parallel |
6597 | [(set (match_operand:BLK 2 "memory_operand" "") | |
6598 | (const_int 0)) | |
6599 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 6600 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6601 | "s390_offset_p (operands[0], operands[2], operands[1]) |
6602 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
6603 | [(parallel | |
6604 | [(set (match_dup 4) (const_int 0)) | |
6605 | (use (match_dup 5)) | |
ae156f85 | 6606 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6607 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6608 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
6609 | ||
9db1d521 HP |
6610 | |
6611 | ;; | |
6612 | ;;- Negate instructions. | |
6613 | ;; | |
6614 | ||
6615 | ; | |
9a91a21f | 6616 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
6617 | ; |
6618 | ||
9a91a21f | 6619 | (define_expand "neg<mode>2" |
9db1d521 | 6620 | [(parallel |
9a91a21f AS |
6621 | [(set (match_operand:DSI 0 "register_operand" "=d") |
6622 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 6623 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6624 | "" |
6625 | "") | |
6626 | ||
26a89301 | 6627 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 6628 | [(set (reg CC_REGNUM) |
26a89301 UW |
6629 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6630 | (match_operand:SI 1 "register_operand" "d") 0) | |
6631 | (const_int 32)) (const_int 32))) | |
6632 | (const_int 0))) | |
6633 | (set (match_operand:DI 0 "register_operand" "=d") | |
6634 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
6635 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6636 | "lcgfr\t%0,%1" | |
729e750f WG |
6637 | [(set_attr "op_type" "RRE") |
6638 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 6639 | |
26a89301 UW |
6640 | (define_insn "*negdi2_sign" |
6641 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6642 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 6643 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6644 | "TARGET_64BIT" |
6645 | "lcgfr\t%0,%1" | |
729e750f WG |
6646 | [(set_attr "op_type" "RRE") |
6647 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6648 | |
43a09b63 | 6649 | ; lcr, lcgr |
9a91a21f | 6650 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 6651 | [(set (reg CC_REGNUM) |
9a91a21f | 6652 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6653 | (const_int 0))) |
9a91a21f AS |
6654 | (set (match_operand:GPR 0 "register_operand" "=d") |
6655 | (neg:GPR (match_dup 1)))] | |
6656 | "s390_match_ccmode (insn, CCAmode)" | |
6657 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6658 | [(set_attr "op_type" "RR<E>") |
6659 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6660 | |
6661 | ; lcr, lcgr | |
9a91a21f | 6662 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 6663 | [(set (reg CC_REGNUM) |
9a91a21f | 6664 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6665 | (const_int 0))) |
9a91a21f AS |
6666 | (clobber (match_scratch:GPR 0 "=d"))] |
6667 | "s390_match_ccmode (insn, CCAmode)" | |
6668 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6669 | [(set_attr "op_type" "RR<E>") |
6670 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6671 | |
6672 | ; lcr, lcgr | |
9a91a21f AS |
6673 | (define_insn "*neg<mode>2" |
6674 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6675 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 6676 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
6677 | "" |
6678 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6679 | [(set_attr "op_type" "RR<E>") |
6680 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 6681 | |
26a89301 | 6682 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
6683 | [(set (match_operand:DI 0 "register_operand" "=d") |
6684 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 6685 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6686 | "!TARGET_64BIT" |
26a89301 UW |
6687 | "#" |
6688 | "&& reload_completed" | |
6689 | [(parallel | |
6690 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 6691 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 6692 | (parallel |
ae156f85 | 6693 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
6694 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
6695 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
6696 | (set (pc) | |
ae156f85 | 6697 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
6698 | (pc) |
6699 | (label_ref (match_dup 6)))) | |
6700 | (parallel | |
6701 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 6702 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
6703 | (match_dup 6)] |
6704 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
6705 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
6706 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
6707 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
6708 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 6709 | |
9db1d521 | 6710 | ; |
f5905b37 | 6711 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
6712 | ; |
6713 | ||
f5905b37 | 6714 | (define_expand "neg<mode>2" |
9db1d521 | 6715 | [(parallel |
7b6baae1 AK |
6716 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6717 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 6718 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6719 | "TARGET_HARD_FLOAT" |
6720 | "") | |
6721 | ||
43a09b63 | 6722 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 6723 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 6724 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6725 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
6726 | (match_operand:BFP 2 "const0_operand" ""))) | |
6727 | (set (match_operand:BFP 0 "register_operand" "=f") | |
6728 | (neg:BFP (match_dup 1)))] | |
142cd70f | 6729 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6730 | "lc<xde>br\t%0,%1" |
26a89301 | 6731 | [(set_attr "op_type" "RRE") |
f5905b37 | 6732 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6733 | |
6734 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 6735 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 6736 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6737 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
6738 | (match_operand:BFP 2 "const0_operand" ""))) | |
6739 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 6740 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6741 | "lc<xde>br\t%0,%1" |
26a89301 | 6742 | [(set_attr "op_type" "RRE") |
f5905b37 | 6743 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 6744 | |
85dae55a AK |
6745 | ; lcdfr |
6746 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
6747 | [(set (match_operand:FP 0 "register_operand" "=f") |
6748 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 6749 | "TARGET_DFP" |
85dae55a AK |
6750 | "lcdfr\t%0,%1" |
6751 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 6752 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 6753 | |
43a09b63 | 6754 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 6755 | (define_insn "*neg<mode>2" |
7b6baae1 AK |
6756 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6757 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 6758 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6759 | "TARGET_HARD_FLOAT" |
f61a2c7d | 6760 | "lc<xde>br\t%0,%1" |
077dab3b | 6761 | [(set_attr "op_type" "RRE") |
f5905b37 | 6762 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6763 | |
9db1d521 HP |
6764 | |
6765 | ;; | |
6766 | ;;- Absolute value instructions. | |
6767 | ;; | |
6768 | ||
6769 | ; | |
9a91a21f | 6770 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
6771 | ; |
6772 | ||
26a89301 | 6773 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 6774 | [(set (reg CC_REGNUM) |
26a89301 UW |
6775 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6776 | (match_operand:SI 1 "register_operand" "d") 0) | |
6777 | (const_int 32)) (const_int 32))) | |
6778 | (const_int 0))) | |
6779 | (set (match_operand:DI 0 "register_operand" "=d") | |
6780 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
6781 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6782 | "lpgfr\t%0,%1" | |
729e750f WG |
6783 | [(set_attr "op_type" "RRE") |
6784 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
6785 | |
6786 | (define_insn "*absdi2_sign" | |
6787 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6788 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 6789 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6790 | "TARGET_64BIT" |
6791 | "lpgfr\t%0,%1" | |
729e750f WG |
6792 | [(set_attr "op_type" "RRE") |
6793 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6794 | |
43a09b63 | 6795 | ; lpr, lpgr |
9a91a21f | 6796 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 6797 | [(set (reg CC_REGNUM) |
9a91a21f | 6798 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 6799 | (const_int 0))) |
9a91a21f AS |
6800 | (set (match_operand:GPR 0 "register_operand" "=d") |
6801 | (abs:GPR (match_dup 1)))] | |
26a89301 | 6802 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 6803 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
6804 | [(set_attr "op_type" "RR<E>") |
6805 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 6806 | |
9381e3f1 | 6807 | ; lpr, lpgr |
9a91a21f | 6808 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 6809 | [(set (reg CC_REGNUM) |
9a91a21f | 6810 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6811 | (const_int 0))) |
9a91a21f | 6812 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6813 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 6814 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
6815 | [(set_attr "op_type" "RR<E>") |
6816 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
6817 | |
6818 | ; lpr, lpgr | |
9a91a21f AS |
6819 | (define_insn "abs<mode>2" |
6820 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6821 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 6822 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6823 | "" |
9a91a21f | 6824 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
6825 | [(set_attr "op_type" "RR<E>") |
6826 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 6827 | |
9db1d521 | 6828 | ; |
f5905b37 | 6829 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
6830 | ; |
6831 | ||
f5905b37 | 6832 | (define_expand "abs<mode>2" |
9db1d521 | 6833 | [(parallel |
7b6baae1 AK |
6834 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6835 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 6836 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6837 | "TARGET_HARD_FLOAT" |
6838 | "") | |
6839 | ||
43a09b63 | 6840 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 6841 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 6842 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6843 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
6844 | (match_operand:BFP 2 "const0_operand" ""))) | |
6845 | (set (match_operand:BFP 0 "register_operand" "=f") | |
6846 | (abs:BFP (match_dup 1)))] | |
142cd70f | 6847 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6848 | "lp<xde>br\t%0,%1" |
26a89301 | 6849 | [(set_attr "op_type" "RRE") |
f5905b37 | 6850 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6851 | |
6852 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 6853 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 6854 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6855 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
6856 | (match_operand:BFP 2 "const0_operand" ""))) | |
6857 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 6858 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6859 | "lp<xde>br\t%0,%1" |
26a89301 | 6860 | [(set_attr "op_type" "RRE") |
f5905b37 | 6861 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 6862 | |
85dae55a AK |
6863 | ; lpdfr |
6864 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
6865 | [(set (match_operand:FP 0 "register_operand" "=f") |
6866 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 6867 | "TARGET_DFP" |
85dae55a AK |
6868 | "lpdfr\t%0,%1" |
6869 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 6870 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 6871 | |
43a09b63 | 6872 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 6873 | (define_insn "*abs<mode>2" |
7b6baae1 AK |
6874 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6875 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 6876 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6877 | "TARGET_HARD_FLOAT" |
f61a2c7d | 6878 | "lp<xde>br\t%0,%1" |
077dab3b | 6879 | [(set_attr "op_type" "RRE") |
f5905b37 | 6880 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6881 | |
9db1d521 | 6882 | |
3ef093a8 AK |
6883 | ;; |
6884 | ;;- Negated absolute value instructions | |
6885 | ;; | |
6886 | ||
6887 | ; | |
6888 | ; Integer | |
6889 | ; | |
6890 | ||
26a89301 | 6891 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 6892 | [(set (reg CC_REGNUM) |
26a89301 UW |
6893 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6894 | (match_operand:SI 1 "register_operand" "d") 0) | |
6895 | (const_int 32)) (const_int 32)))) | |
6896 | (const_int 0))) | |
6897 | (set (match_operand:DI 0 "register_operand" "=d") | |
6898 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6899 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6900 | "lngfr\t%0,%1" | |
729e750f WG |
6901 | [(set_attr "op_type" "RRE") |
6902 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 6903 | |
26a89301 UW |
6904 | (define_insn "*negabsdi2_sign" |
6905 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6906 | (neg:DI (abs:DI (sign_extend:DI | |
6907 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 6908 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6909 | "TARGET_64BIT" |
6910 | "lngfr\t%0,%1" | |
729e750f WG |
6911 | [(set_attr "op_type" "RRE") |
6912 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 6913 | |
43a09b63 | 6914 | ; lnr, lngr |
9a91a21f | 6915 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6916 | [(set (reg CC_REGNUM) |
9a91a21f | 6917 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6918 | (const_int 0))) |
9a91a21f AS |
6919 | (set (match_operand:GPR 0 "register_operand" "=d") |
6920 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 6921 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 6922 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
6923 | [(set_attr "op_type" "RR<E>") |
6924 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
6925 | |
6926 | ; lnr, lngr | |
9a91a21f | 6927 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6928 | [(set (reg CC_REGNUM) |
9a91a21f | 6929 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6930 | (const_int 0))) |
9a91a21f | 6931 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6932 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 6933 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
6934 | [(set_attr "op_type" "RR<E>") |
6935 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
6936 | |
6937 | ; lnr, lngr | |
9a91a21f AS |
6938 | (define_insn "*negabs<mode>2" |
6939 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6940 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 6941 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 6942 | "" |
9a91a21f | 6943 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
6944 | [(set_attr "op_type" "RR<E>") |
6945 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6946 | |
3ef093a8 AK |
6947 | ; |
6948 | ; Floating point | |
6949 | ; | |
6950 | ||
43a09b63 | 6951 | ; lnxbr, lndbr, lnebr |
f5905b37 | 6952 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6953 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6954 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
6955 | (match_operand:BFP 2 "const0_operand" ""))) | |
6956 | (set (match_operand:BFP 0 "register_operand" "=f") | |
6957 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 6958 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6959 | "ln<xde>br\t%0,%1" |
26a89301 | 6960 | [(set_attr "op_type" "RRE") |
f5905b37 | 6961 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
6962 | |
6963 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 6964 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6965 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
6966 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
6967 | (match_operand:BFP 2 "const0_operand" ""))) | |
6968 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 6969 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 6970 | "ln<xde>br\t%0,%1" |
26a89301 | 6971 | [(set_attr "op_type" "RRE") |
f5905b37 | 6972 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 6973 | |
85dae55a AK |
6974 | ; lndfr |
6975 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
6976 | [(set (match_operand:FP 0 "register_operand" "=f") |
6977 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 6978 | "TARGET_DFP" |
85dae55a AK |
6979 | "lndfr\t%0,%1" |
6980 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 6981 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 6982 | |
43a09b63 | 6983 | ; lnxbr, lndbr, lnebr |
f5905b37 | 6984 | (define_insn "*negabs<mode>2" |
7b6baae1 AK |
6985 | [(set (match_operand:BFP 0 "register_operand" "=f") |
6986 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))) | |
ae156f85 | 6987 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6988 | "TARGET_HARD_FLOAT" |
f61a2c7d | 6989 | "ln<xde>br\t%0,%1" |
26a89301 | 6990 | [(set_attr "op_type" "RRE") |
f5905b37 | 6991 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6992 | |
85dae55a AK |
6993 | ;; |
6994 | ;;- Copy sign instructions | |
6995 | ;; | |
6996 | ||
6997 | ; cpsdr | |
6998 | (define_insn "copysign<mode>3" | |
609e7e80 AK |
6999 | [(set (match_operand:FP 0 "register_operand" "=f") |
7000 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
9381e3f1 | 7001 | (match_operand:FP 2 "register_operand" "f")] |
85dae55a | 7002 | UNSPEC_COPYSIGN))] |
fb068247 | 7003 | "TARGET_DFP" |
85dae55a AK |
7004 | "cpsdr\t%0,%2,%1" |
7005 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 7006 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7007 | |
4023fb28 UW |
7008 | ;; |
7009 | ;;- Square root instructions. | |
7010 | ;; | |
7011 | ||
7012 | ; | |
f5905b37 | 7013 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
7014 | ; |
7015 | ||
9381e3f1 | 7016 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 7017 | (define_insn "sqrt<mode>2" |
7b6baae1 AK |
7018 | [(set (match_operand:BFP 0 "register_operand" "=f,f") |
7019 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 7020 | "TARGET_HARD_FLOAT" |
4023fb28 | 7021 | "@ |
f61a2c7d AK |
7022 | sq<xde>br\t%0,%1 |
7023 | sq<xde>b\t%0,%1" | |
a036c6f7 | 7024 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 7025 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 7026 | |
9db1d521 HP |
7027 | |
7028 | ;; | |
7029 | ;;- One complement instructions. | |
7030 | ;; | |
7031 | ||
7032 | ; | |
342cf42b | 7033 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 7034 | ; |
c7453384 | 7035 | |
342cf42b | 7036 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 7037 | [(parallel |
342cf42b AS |
7038 | [(set (match_operand:INT 0 "register_operand" "") |
7039 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
7040 | (const_int -1))) | |
ae156f85 | 7041 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 7042 | "" |
4023fb28 | 7043 | "") |
9db1d521 HP |
7044 | |
7045 | ||
ec24698e UW |
7046 | ;; |
7047 | ;; Find leftmost bit instructions. | |
7048 | ;; | |
7049 | ||
7050 | (define_expand "clzdi2" | |
7051 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7052 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
7053 | "TARGET_EXTIMM && TARGET_64BIT" | |
7054 | { | |
7055 | rtx insn, clz_equal; | |
7056 | rtx wide_reg = gen_reg_rtx (TImode); | |
7057 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
7058 | ||
7059 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
7060 | ||
7061 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
7062 | ||
9381e3f1 | 7063 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 7064 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
7065 | |
7066 | DONE; | |
7067 | }) | |
7068 | ||
7069 | (define_insn "clztidi2" | |
7070 | [(set (match_operand:TI 0 "register_operand" "=d") | |
7071 | (ior:TI | |
9381e3f1 WG |
7072 | (ashift:TI |
7073 | (zero_extend:TI | |
ec24698e UW |
7074 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
7075 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
7076 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 7077 | |
ec24698e UW |
7078 | (const_int 64)) |
7079 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
7080 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 7081 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e UW |
7082 | == (unsigned HOST_WIDE_INT) 1 << 63 |
7083 | && TARGET_EXTIMM && TARGET_64BIT" | |
7084 | "flogr\t%0,%1" | |
7085 | [(set_attr "op_type" "RRE")]) | |
7086 | ||
7087 | ||
9db1d521 HP |
7088 | ;; |
7089 | ;;- Rotate instructions. | |
7090 | ;; | |
7091 | ||
7092 | ; | |
9a91a21f | 7093 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
7094 | ; |
7095 | ||
43a09b63 | 7096 | ; rll, rllg |
9a91a21f AS |
7097 | (define_insn "rotl<mode>3" |
7098 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7099 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 7100 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 7101 | "TARGET_CPU_ZARCH" |
9a91a21f | 7102 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 7103 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
7104 | (set_attr "atype" "reg") |
7105 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7106 | |
43a09b63 | 7107 | ; rll, rllg |
4989e88a AK |
7108 | (define_insn "*rotl<mode>3_and" |
7109 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7110 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7111 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7112 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7113 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
7114 | "rll<g>\t%0,%1,%Y2" | |
7115 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
7116 | (set_attr "atype" "reg") |
7117 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7118 | |
9db1d521 HP |
7119 | |
7120 | ;; | |
f337b930 | 7121 | ;;- Shift instructions. |
9db1d521 | 7122 | ;; |
9db1d521 HP |
7123 | |
7124 | ; | |
1b48c8cc | 7125 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
9db1d521 HP |
7126 | ; |
7127 | ||
1b48c8cc AS |
7128 | (define_expand "<shift><mode>3" |
7129 | [(set (match_operand:DSI 0 "register_operand" "") | |
7130 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
7131 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
7132 | "" |
7133 | "") | |
7134 | ||
43a09b63 | 7135 | ; sldl, srdl |
f337b930 | 7136 | (define_insn "*<shift>di3_31" |
ac32b25e | 7137 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 7138 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7139 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9db1d521 | 7140 | "!TARGET_64BIT" |
f337b930 | 7141 | "s<lr>dl\t%0,%Y2" |
077dab3b HP |
7142 | [(set_attr "op_type" "RS") |
7143 | (set_attr "atype" "reg")]) | |
9db1d521 | 7144 | |
43a09b63 | 7145 | ; sll, srl, sllg, srlg |
1b48c8cc AS |
7146 | (define_insn "*<shift><mode>3" |
7147 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7148 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7149 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] | |
7150 | "" | |
7151 | "s<lr>l<g>\t%0,<1>%Y2" | |
7152 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7153 | (set_attr "atype" "reg") |
7154 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7155 | |
43a09b63 | 7156 | ; sldl, srdl |
4989e88a AK |
7157 | (define_insn "*<shift>di3_31_and" |
7158 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7159 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7160 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7161 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7162 | "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
7163 | "s<lr>dl\t%0,%Y2" | |
7164 | [(set_attr "op_type" "RS") | |
7165 | (set_attr "atype" "reg")]) | |
7166 | ||
43a09b63 | 7167 | ; sll, srl, sllg, srlg |
1b48c8cc AS |
7168 | (define_insn "*<shift><mode>3_and" |
7169 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7170 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7171 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7172 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7173 | "(INTVAL (operands[3]) & 63) == 63" | |
7174 | "s<lr>l<g>\t%0,<1>%Y2" | |
7175 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7176 | (set_attr "atype" "reg") |
7177 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7178 | |
9db1d521 | 7179 | ; |
1b48c8cc | 7180 | ; ashr(di|si)3 instruction pattern(s). |
9db1d521 HP |
7181 | ; |
7182 | ||
1b48c8cc | 7183 | (define_expand "ashr<mode>3" |
9db1d521 | 7184 | [(parallel |
1b48c8cc AS |
7185 | [(set (match_operand:DSI 0 "register_operand" "") |
7186 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
7187 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 7188 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7189 | "" |
7190 | "") | |
7191 | ||
ecbe845e | 7192 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 7193 | [(set (reg CC_REGNUM) |
ac32b25e | 7194 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7195 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7196 | (const_int 0))) |
ac32b25e | 7197 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
7198 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
7199 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 7200 | "srda\t%0,%Y2" |
077dab3b HP |
7201 | [(set_attr "op_type" "RS") |
7202 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
7203 | |
7204 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 7205 | [(set (reg CC_REGNUM) |
ac32b25e | 7206 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7207 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7208 | (const_int 0))) |
ac32b25e | 7209 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 7210 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7211 | "srda\t%0,%Y2" |
077dab3b HP |
7212 | [(set_attr "op_type" "RS") |
7213 | (set_attr "atype" "reg")]) | |
ecbe845e | 7214 | |
9db1d521 | 7215 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
7216 | [(set (match_operand:DI 0 "register_operand" "=d") |
7217 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 7218 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 7219 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 7220 | "!TARGET_64BIT" |
ac32b25e | 7221 | "srda\t%0,%Y2" |
077dab3b HP |
7222 | [(set_attr "op_type" "RS") |
7223 | (set_attr "atype" "reg")]) | |
c7453384 | 7224 | |
43a09b63 | 7225 | ; sra, srag |
1b48c8cc | 7226 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 7227 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
7228 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
7229 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
ecbe845e | 7230 | (const_int 0))) |
1b48c8cc AS |
7231 | (set (match_operand:GPR 0 "register_operand" "=d") |
7232 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] | |
7233 | "s390_match_ccmode(insn, CCSmode)" | |
7234 | "sra<g>\t%0,<1>%Y2" | |
7235 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7236 | (set_attr "atype" "reg") |
7237 | (set_attr "z10prop" "z10_super_E1")]) | |
ecbe845e | 7238 | |
43a09b63 | 7239 | ; sra, srag |
1b48c8cc | 7240 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 7241 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
7242 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
7243 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
ecbe845e | 7244 | (const_int 0))) |
1b48c8cc AS |
7245 | (clobber (match_scratch:GPR 0 "=d"))] |
7246 | "s390_match_ccmode(insn, CCSmode)" | |
7247 | "sra<g>\t%0,<1>%Y2" | |
7248 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7249 | (set_attr "atype" "reg") |
7250 | (set_attr "z10prop" "z10_super_E1")]) | |
ecbe845e | 7251 | |
43a09b63 | 7252 | ; sra, srag |
1b48c8cc AS |
7253 | (define_insn "*ashr<mode>3" |
7254 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7255 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7256 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) | |
ae156f85 | 7257 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc AS |
7258 | "" |
7259 | "sra<g>\t%0,<1>%Y2" | |
7260 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7261 | (set_attr "atype" "reg") |
7262 | (set_attr "z10prop" "z10_super_E1")]) | |
077dab3b | 7263 | |
9db1d521 | 7264 | |
4989e88a AK |
7265 | ; shift pattern with implicit ANDs |
7266 | ||
7267 | (define_insn "*ashrdi3_cc_31_and" | |
7268 | [(set (reg CC_REGNUM) | |
7269 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7270 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7271 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7272 | (const_int 0))) | |
7273 | (set (match_operand:DI 0 "register_operand" "=d") | |
7274 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
7275 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
7276 | && (INTVAL (operands[3]) & 63) == 63" | |
7277 | "srda\t%0,%Y2" | |
7278 | [(set_attr "op_type" "RS") | |
7279 | (set_attr "atype" "reg")]) | |
7280 | ||
7281 | (define_insn "*ashrdi3_cconly_31_and" | |
7282 | [(set (reg CC_REGNUM) | |
7283 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7284 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7285 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7286 | (const_int 0))) | |
7287 | (clobber (match_scratch:DI 0 "=d"))] | |
7288 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
7289 | && (INTVAL (operands[3]) & 63) == 63" | |
7290 | "srda\t%0,%Y2" | |
7291 | [(set_attr "op_type" "RS") | |
7292 | (set_attr "atype" "reg")]) | |
7293 | ||
7294 | (define_insn "*ashrdi3_31_and" | |
7295 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7296 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7297 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7298 | (match_operand:SI 3 "const_int_operand" "n")))) | |
7299 | (clobber (reg:CC CC_REGNUM))] | |
7300 | "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
7301 | "srda\t%0,%Y2" | |
7302 | [(set_attr "op_type" "RS") | |
7303 | (set_attr "atype" "reg")]) | |
7304 | ||
43a09b63 | 7305 | ; sra, srag |
1b48c8cc | 7306 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 7307 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
7308 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
7309 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7310 | (match_operand:SI 3 "const_int_operand" "n"))) | |
4989e88a | 7311 | (const_int 0))) |
1b48c8cc AS |
7312 | (set (match_operand:GPR 0 "register_operand" "=d") |
7313 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
4989e88a | 7314 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
1b48c8cc AS |
7315 | "sra<g>\t%0,<1>%Y2" |
7316 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7317 | (set_attr "atype" "reg") |
7318 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7319 | |
43a09b63 | 7320 | ; sra, srag |
1b48c8cc | 7321 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 7322 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
7323 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
7324 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7325 | (match_operand:SI 3 "const_int_operand" "n"))) | |
4989e88a | 7326 | (const_int 0))) |
1b48c8cc | 7327 | (clobber (match_scratch:GPR 0 "=d"))] |
4989e88a | 7328 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
1b48c8cc AS |
7329 | "sra<g>\t%0,<1>%Y2" |
7330 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7331 | (set_attr "atype" "reg") |
7332 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7333 | |
43a09b63 | 7334 | ; sra, srag |
1b48c8cc AS |
7335 | (define_insn "*ashr<mode>3_and" |
7336 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7337 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
7338 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7339 | (match_operand:SI 3 "const_int_operand" "n")))) | |
4989e88a AK |
7340 | (clobber (reg:CC CC_REGNUM))] |
7341 | "(INTVAL (operands[3]) & 63) == 63" | |
1b48c8cc AS |
7342 | "sra<g>\t%0,<1>%Y2" |
7343 | [(set_attr "op_type" "RS<E>") | |
9381e3f1 WG |
7344 | (set_attr "atype" "reg") |
7345 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7346 | |
9db1d521 | 7347 | |
9db1d521 HP |
7348 | ;; |
7349 | ;; Branch instruction patterns. | |
7350 | ;; | |
7351 | ||
fa77b251 AS |
7352 | (define_expand "b<code>" |
7353 | [(set (pc) | |
7354 | (if_then_else (COMPARE (match_operand 0 "" "") | |
7355 | (const_int 0)) | |
7356 | (match_dup 0) | |
7357 | (pc)))] | |
ba956982 | 7358 | "" |
6590e19a | 7359 | "s390_emit_jump (operands[0], |
fa77b251 | 7360 | s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;") |
ba956982 | 7361 | |
9db1d521 HP |
7362 | |
7363 | ;; | |
7364 | ;;- Conditional jump instructions. | |
7365 | ;; | |
7366 | ||
6590e19a UW |
7367 | (define_insn "*cjump_64" |
7368 | [(set (pc) | |
7369 | (if_then_else | |
ae156f85 | 7370 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7371 | (label_ref (match_operand 0 "" "")) |
7372 | (pc)))] | |
7373 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7374 | { |
13e58269 | 7375 | if (get_attr_length (insn) == 4) |
d40c829f | 7376 | return "j%C1\t%l0"; |
6590e19a | 7377 | else |
d40c829f | 7378 | return "jg%C1\t%l0"; |
6590e19a UW |
7379 | } |
7380 | [(set_attr "op_type" "RI") | |
7381 | (set_attr "type" "branch") | |
7382 | (set (attr "length") | |
7383 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7384 | (const_int 4) (const_int 6)))]) | |
7385 | ||
7386 | (define_insn "*cjump_31" | |
7387 | [(set (pc) | |
7388 | (if_then_else | |
ae156f85 | 7389 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7390 | (label_ref (match_operand 0 "" "")) |
7391 | (pc)))] | |
7392 | "!TARGET_CPU_ZARCH" | |
7393 | { | |
8d933e31 AS |
7394 | gcc_assert (get_attr_length (insn) == 4); |
7395 | return "j%C1\t%l0"; | |
10bbf137 | 7396 | } |
9db1d521 | 7397 | [(set_attr "op_type" "RI") |
077dab3b | 7398 | (set_attr "type" "branch") |
13e58269 | 7399 | (set (attr "length") |
6590e19a UW |
7400 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7401 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7402 | (const_int 4) (const_int 6)) | |
7403 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7404 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7405 | |
f314b9b1 | 7406 | (define_insn "*cjump_long" |
6590e19a UW |
7407 | [(set (pc) |
7408 | (if_then_else | |
ae156f85 | 7409 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7410 | (match_operand 0 "address_operand" "U") |
7411 | (pc)))] | |
9db1d521 | 7412 | "" |
f314b9b1 UW |
7413 | { |
7414 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7415 | return "b%C1r\t%0"; |
f314b9b1 | 7416 | else |
d40c829f | 7417 | return "b%C1\t%a0"; |
10bbf137 | 7418 | } |
c7453384 | 7419 | [(set (attr "op_type") |
f314b9b1 UW |
7420 | (if_then_else (match_operand 0 "register_operand" "") |
7421 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 7422 | (set_attr "type" "branch") |
077dab3b | 7423 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7424 | |
7425 | ||
7426 | ;; | |
7427 | ;;- Negated conditional jump instructions. | |
7428 | ;; | |
7429 | ||
6590e19a UW |
7430 | (define_insn "*icjump_64" |
7431 | [(set (pc) | |
7432 | (if_then_else | |
ae156f85 | 7433 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7434 | (pc) |
7435 | (label_ref (match_operand 0 "" ""))))] | |
7436 | "TARGET_CPU_ZARCH" | |
c7453384 | 7437 | { |
13e58269 | 7438 | if (get_attr_length (insn) == 4) |
d40c829f | 7439 | return "j%D1\t%l0"; |
6590e19a | 7440 | else |
d40c829f | 7441 | return "jg%D1\t%l0"; |
6590e19a UW |
7442 | } |
7443 | [(set_attr "op_type" "RI") | |
7444 | (set_attr "type" "branch") | |
7445 | (set (attr "length") | |
7446 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7447 | (const_int 4) (const_int 6)))]) | |
7448 | ||
7449 | (define_insn "*icjump_31" | |
7450 | [(set (pc) | |
7451 | (if_then_else | |
ae156f85 | 7452 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7453 | (pc) |
7454 | (label_ref (match_operand 0 "" ""))))] | |
7455 | "!TARGET_CPU_ZARCH" | |
7456 | { | |
8d933e31 AS |
7457 | gcc_assert (get_attr_length (insn) == 4); |
7458 | return "j%D1\t%l0"; | |
10bbf137 | 7459 | } |
9db1d521 | 7460 | [(set_attr "op_type" "RI") |
077dab3b | 7461 | (set_attr "type" "branch") |
13e58269 | 7462 | (set (attr "length") |
6590e19a UW |
7463 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7464 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7465 | (const_int 4) (const_int 6)) | |
7466 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7467 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7468 | |
f314b9b1 | 7469 | (define_insn "*icjump_long" |
6590e19a UW |
7470 | [(set (pc) |
7471 | (if_then_else | |
ae156f85 | 7472 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7473 | (pc) |
7474 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 7475 | "" |
f314b9b1 UW |
7476 | { |
7477 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7478 | return "b%D1r\t%0"; |
f314b9b1 | 7479 | else |
d40c829f | 7480 | return "b%D1\t%a0"; |
10bbf137 | 7481 | } |
c7453384 | 7482 | [(set (attr "op_type") |
f314b9b1 UW |
7483 | (if_then_else (match_operand 0 "register_operand" "") |
7484 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7485 | (set_attr "type" "branch") |
7486 | (set_attr "atype" "agen")]) | |
9db1d521 | 7487 | |
4456530d HP |
7488 | ;; |
7489 | ;;- Trap instructions. | |
7490 | ;; | |
7491 | ||
7492 | (define_insn "trap" | |
7493 | [(trap_if (const_int 1) (const_int 0))] | |
7494 | "" | |
d40c829f | 7495 | "j\t.+2" |
6590e19a | 7496 | [(set_attr "op_type" "RI") |
077dab3b | 7497 | (set_attr "type" "branch")]) |
4456530d HP |
7498 | |
7499 | (define_expand "conditional_trap" | |
6590e19a UW |
7500 | [(trap_if (match_operand 0 "comparison_operator" "") |
7501 | (match_operand 1 "general_operand" ""))] | |
4456530d | 7502 | "" |
4456530d | 7503 | { |
6590e19a | 7504 | if (operands[1] != const0_rtx) FAIL; |
9381e3f1 | 7505 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), |
6590e19a | 7506 | s390_compare_op0, s390_compare_op1); |
10bbf137 | 7507 | }) |
4456530d HP |
7508 | |
7509 | (define_insn "*trap" | |
ae156f85 | 7510 | [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4456530d HP |
7511 | (const_int 0))] |
7512 | "" | |
d40c829f | 7513 | "j%C0\t.+2"; |
077dab3b HP |
7514 | [(set_attr "op_type" "RI") |
7515 | (set_attr "type" "branch")]) | |
9db1d521 | 7516 | |
963fc8d0 AK |
7517 | ; crt, cgrt, cit, cgit |
7518 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
7519 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
7520 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7521 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
7522 | (const_int 0))] | |
7523 | "TARGET_Z10" | |
7524 | "@ | |
7525 | c<g>rt%C0\t%1,%2 | |
7526 | c<g>it%C0\t%1,%h2" | |
7527 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7528 | (set_attr "type" "branch") |
729e750f | 7529 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 AK |
7530 | |
7531 | ; clrt, clgrt, clfit, clgit | |
7532 | (define_insn "*cmp_and_trap_unsigned_int<mode>" | |
7533 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
7534 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7535 | (match_operand:GPR 2 "nonmemory_operand" "d,D")]) | |
7536 | (const_int 0))] | |
7537 | "TARGET_Z10" | |
7538 | "@ | |
7539 | cl<g>rt%C0\t%1,%2 | |
7540 | cl<gf>it%C0\t%1,%x2" | |
7541 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7542 | (set_attr "type" "branch") |
729e750f | 7543 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 7544 | |
9db1d521 | 7545 | ;; |
0a3bdf9d | 7546 | ;;- Loop instructions. |
9db1d521 | 7547 | ;; |
0a3bdf9d UW |
7548 | ;; This is all complicated by the fact that since this is a jump insn |
7549 | ;; we must handle our own output reloads. | |
c7453384 | 7550 | |
0a3bdf9d UW |
7551 | (define_expand "doloop_end" |
7552 | [(use (match_operand 0 "" "")) ; loop pseudo | |
7553 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
7554 | (use (match_operand 2 "" "")) ; max iterations | |
7555 | (use (match_operand 3 "" "")) ; loop level | |
7556 | (use (match_operand 4 "" ""))] ; label | |
7557 | "" | |
0a3bdf9d | 7558 | { |
6590e19a UW |
7559 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
7560 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
7561 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
7562 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
7563 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
7564 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
7565 | else | |
7566 | FAIL; | |
7567 | ||
7568 | DONE; | |
10bbf137 | 7569 | }) |
0a3bdf9d | 7570 | |
6590e19a | 7571 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
7572 | [(set (pc) |
7573 | (if_then_else | |
7e665d18 | 7574 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
7575 | (const_int 1)) |
7576 | (label_ref (match_operand 0 "" "")) | |
7577 | (pc))) | |
7e665d18 | 7578 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 7579 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 7580 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 7581 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 7582 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
7583 | { |
7584 | if (which_alternative != 0) | |
10bbf137 | 7585 | return "#"; |
0a3bdf9d | 7586 | else if (get_attr_length (insn) == 4) |
d40c829f | 7587 | return "brct\t%1,%l0"; |
6590e19a | 7588 | else |
545d16ff | 7589 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
7590 | } |
7591 | "&& reload_completed | |
7592 | && (! REG_P (operands[2]) | |
7593 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
7594 | [(set (match_dup 3) (match_dup 1)) |
7595 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
7596 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
7597 | (const_int 0))) | |
7598 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7599 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 7600 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
7601 | (label_ref (match_dup 0)) |
7602 | (pc)))] | |
7603 | "" | |
7604 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
7605 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
7606 | ; hurt us in the (rare) case of ahi. | |
729e750f | 7607 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
7608 | (set_attr "type" "branch") |
7609 | (set (attr "length") | |
7610 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7611 | (const_int 4) (const_int 10)))]) | |
7612 | ||
7613 | (define_insn_and_split "doloop_si31" | |
7614 | [(set (pc) | |
7615 | (if_then_else | |
7e665d18 | 7616 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
7617 | (const_int 1)) |
7618 | (label_ref (match_operand 0 "" "")) | |
7619 | (pc))) | |
7e665d18 | 7620 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 7621 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 7622 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 7623 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
7624 | "!TARGET_CPU_ZARCH" |
7625 | { | |
7626 | if (which_alternative != 0) | |
7627 | return "#"; | |
7628 | else if (get_attr_length (insn) == 4) | |
7629 | return "brct\t%1,%l0"; | |
0a3bdf9d | 7630 | else |
8d933e31 | 7631 | gcc_unreachable (); |
10bbf137 | 7632 | } |
6590e19a UW |
7633 | "&& reload_completed |
7634 | && (! REG_P (operands[2]) | |
7635 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
7636 | [(set (match_dup 3) (match_dup 1)) |
7637 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
7638 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
7639 | (const_int 0))) | |
7640 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7641 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 7642 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
7643 | (label_ref (match_dup 0)) |
7644 | (pc)))] | |
7645 | "" | |
0a3bdf9d | 7646 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
7647 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
7648 | ; hurt us in the (rare) case of ahi. | |
729e750f | 7649 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 7650 | (set_attr "type" "branch") |
0a3bdf9d | 7651 | (set (attr "length") |
6590e19a UW |
7652 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7653 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7654 | (const_int 4) (const_int 6)) | |
7655 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7656 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7657 | |
0a3bdf9d UW |
7658 | (define_insn "*doloop_si_long" |
7659 | [(set (pc) | |
7660 | (if_then_else | |
7e665d18 | 7661 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 7662 | (const_int 1)) |
7e665d18 | 7663 | (match_operand 0 "address_operand" "U") |
0a3bdf9d | 7664 | (pc))) |
7e665d18 | 7665 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 7666 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 7667 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 7668 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 7669 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
7670 | { |
7671 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7672 | return "bctr\t%1,%0"; |
0a3bdf9d | 7673 | else |
d40c829f | 7674 | return "bct\t%1,%a0"; |
10bbf137 | 7675 | } |
c7453384 | 7676 | [(set (attr "op_type") |
0a3bdf9d UW |
7677 | (if_then_else (match_operand 0 "register_operand" "") |
7678 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 7679 | (set_attr "type" "branch") |
729e750f WG |
7680 | (set_attr "atype" "agen") |
7681 | (set_attr "z10prop" "z10_cobra")]) | |
0a3bdf9d | 7682 | |
6590e19a | 7683 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
7684 | [(set (pc) |
7685 | (if_then_else | |
7e665d18 | 7686 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
7687 | (const_int 1)) |
7688 | (label_ref (match_operand 0 "" "")) | |
7689 | (pc))) | |
7e665d18 | 7690 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 7691 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 7692 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 7693 | (clobber (reg:CC CC_REGNUM))] |
0a3bdf9d | 7694 | "TARGET_64BIT" |
0a3bdf9d UW |
7695 | { |
7696 | if (which_alternative != 0) | |
10bbf137 | 7697 | return "#"; |
0a3bdf9d | 7698 | else if (get_attr_length (insn) == 4) |
d40c829f | 7699 | return "brctg\t%1,%l0"; |
0a3bdf9d | 7700 | else |
545d16ff | 7701 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 7702 | } |
6590e19a | 7703 | "&& reload_completed |
0a3bdf9d UW |
7704 | && (! REG_P (operands[2]) |
7705 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
7706 | [(set (match_dup 3) (match_dup 1)) |
7707 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
7708 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
7709 | (const_int 0))) | |
7710 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
7711 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 7712 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 7713 | (label_ref (match_dup 0)) |
0a3bdf9d | 7714 | (pc)))] |
6590e19a UW |
7715 | "" |
7716 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
7717 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
7718 | ; hurt us in the (rare) case of ahi. | |
729e750f | 7719 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
7720 | (set_attr "type" "branch") |
7721 | (set (attr "length") | |
7722 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7723 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
7724 | |
7725 | ;; | |
7726 | ;;- Unconditional jump instructions. | |
7727 | ;; | |
7728 | ||
7729 | ; | |
7730 | ; jump instruction pattern(s). | |
7731 | ; | |
7732 | ||
6590e19a UW |
7733 | (define_expand "jump" |
7734 | [(match_operand 0 "" "")] | |
9db1d521 | 7735 | "" |
6590e19a UW |
7736 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
7737 | ||
7738 | (define_insn "*jump64" | |
7739 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7740 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7741 | { |
13e58269 | 7742 | if (get_attr_length (insn) == 4) |
d40c829f | 7743 | return "j\t%l0"; |
6590e19a | 7744 | else |
d40c829f | 7745 | return "jg\t%l0"; |
6590e19a UW |
7746 | } |
7747 | [(set_attr "op_type" "RI") | |
7748 | (set_attr "type" "branch") | |
7749 | (set (attr "length") | |
7750 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7751 | (const_int 4) (const_int 6)))]) | |
7752 | ||
7753 | (define_insn "*jump31" | |
7754 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7755 | "!TARGET_CPU_ZARCH" | |
7756 | { | |
8d933e31 AS |
7757 | gcc_assert (get_attr_length (insn) == 4); |
7758 | return "j\t%l0"; | |
10bbf137 | 7759 | } |
9db1d521 | 7760 | [(set_attr "op_type" "RI") |
077dab3b | 7761 | (set_attr "type" "branch") |
13e58269 | 7762 | (set (attr "length") |
6590e19a UW |
7763 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7764 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7765 | (const_int 4) (const_int 6)) | |
7766 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7767 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
7768 | |
7769 | ; | |
7770 | ; indirect-jump instruction pattern(s). | |
7771 | ; | |
7772 | ||
7773 | (define_insn "indirect_jump" | |
d3632d41 | 7774 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 7775 | "" |
f314b9b1 UW |
7776 | { |
7777 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7778 | return "br\t%0"; |
f314b9b1 | 7779 | else |
d40c829f | 7780 | return "b\t%a0"; |
10bbf137 | 7781 | } |
c7453384 | 7782 | [(set (attr "op_type") |
f314b9b1 UW |
7783 | (if_then_else (match_operand 0 "register_operand" "") |
7784 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 7785 | (set_attr "type" "branch") |
729e750f | 7786 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7787 | |
7788 | ; | |
f314b9b1 | 7789 | ; casesi instruction pattern(s). |
9db1d521 HP |
7790 | ; |
7791 | ||
f314b9b1 | 7792 | (define_insn "casesi_jump" |
d3632d41 | 7793 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 7794 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 7795 | "" |
9db1d521 | 7796 | { |
f314b9b1 | 7797 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 7798 | return "br\t%0"; |
f314b9b1 | 7799 | else |
d40c829f | 7800 | return "b\t%a0"; |
10bbf137 | 7801 | } |
c7453384 | 7802 | [(set (attr "op_type") |
f314b9b1 UW |
7803 | (if_then_else (match_operand 0 "register_operand" "") |
7804 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7805 | (set_attr "type" "branch") |
7806 | (set_attr "atype" "agen")]) | |
9db1d521 | 7807 | |
f314b9b1 UW |
7808 | (define_expand "casesi" |
7809 | [(match_operand:SI 0 "general_operand" "") | |
7810 | (match_operand:SI 1 "general_operand" "") | |
7811 | (match_operand:SI 2 "general_operand" "") | |
7812 | (label_ref (match_operand 3 "" "")) | |
7813 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 7814 | "" |
f314b9b1 UW |
7815 | { |
7816 | rtx index = gen_reg_rtx (SImode); | |
7817 | rtx base = gen_reg_rtx (Pmode); | |
7818 | rtx target = gen_reg_rtx (Pmode); | |
7819 | ||
7820 | emit_move_insn (index, operands[0]); | |
7821 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
7822 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 7823 | operands[4]); |
f314b9b1 UW |
7824 | |
7825 | if (Pmode != SImode) | |
7826 | index = convert_to_mode (Pmode, index, 1); | |
7827 | if (GET_CODE (index) != REG) | |
7828 | index = copy_to_mode_reg (Pmode, index); | |
7829 | ||
7830 | if (TARGET_64BIT) | |
7831 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
7832 | else | |
a556fd39 | 7833 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 7834 | |
f314b9b1 UW |
7835 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
7836 | ||
542a8afa | 7837 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
7838 | emit_move_insn (target, index); |
7839 | ||
7840 | if (flag_pic) | |
7841 | target = gen_rtx_PLUS (Pmode, base, target); | |
7842 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
7843 | ||
7844 | DONE; | |
10bbf137 | 7845 | }) |
9db1d521 HP |
7846 | |
7847 | ||
7848 | ;; | |
7849 | ;;- Jump to subroutine. | |
7850 | ;; | |
7851 | ;; | |
7852 | ||
7853 | ; | |
7854 | ; untyped call instruction pattern(s). | |
7855 | ; | |
7856 | ||
7857 | ;; Call subroutine returning any type. | |
7858 | (define_expand "untyped_call" | |
7859 | [(parallel [(call (match_operand 0 "" "") | |
7860 | (const_int 0)) | |
7861 | (match_operand 1 "" "") | |
7862 | (match_operand 2 "" "")])] | |
7863 | "" | |
9db1d521 HP |
7864 | { |
7865 | int i; | |
7866 | ||
7867 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
7868 | ||
7869 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7870 | { | |
7871 | rtx set = XVECEXP (operands[2], 0, i); | |
7872 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7873 | } | |
7874 | ||
7875 | /* The optimizer does not know that the call sets the function value | |
7876 | registers we stored in the result block. We avoid problems by | |
7877 | claiming that all hard registers are used and clobbered at this | |
7878 | point. */ | |
7879 | emit_insn (gen_blockage ()); | |
7880 | ||
7881 | DONE; | |
10bbf137 | 7882 | }) |
9db1d521 HP |
7883 | |
7884 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7885 | ;; all of memory. This blocks insns from being moved across this point. | |
7886 | ||
7887 | (define_insn "blockage" | |
10bbf137 | 7888 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 7889 | "" |
4023fb28 | 7890 | "" |
d5869ca0 UW |
7891 | [(set_attr "type" "none") |
7892 | (set_attr "length" "0")]) | |
4023fb28 | 7893 | |
9db1d521 | 7894 | ; |
ed9676cf | 7895 | ; sibcall patterns |
9db1d521 HP |
7896 | ; |
7897 | ||
ed9676cf | 7898 | (define_expand "sibcall" |
44b8152b | 7899 | [(call (match_operand 0 "" "") |
ed9676cf | 7900 | (match_operand 1 "" ""))] |
9db1d521 | 7901 | "" |
9db1d521 | 7902 | { |
ed9676cf AK |
7903 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
7904 | DONE; | |
7905 | }) | |
9db1d521 | 7906 | |
ed9676cf | 7907 | (define_insn "*sibcall_br" |
ae156f85 | 7908 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 7909 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 7910 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7911 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
7912 | "br\t%%r1" | |
7913 | [(set_attr "op_type" "RR") | |
7914 | (set_attr "type" "branch") | |
7915 | (set_attr "atype" "agen")]) | |
9db1d521 | 7916 | |
ed9676cf AK |
7917 | (define_insn "*sibcall_brc" |
7918 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7919 | (match_operand 1 "const_int_operand" "n"))] | |
7920 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7921 | "j\t%0" | |
7922 | [(set_attr "op_type" "RI") | |
7923 | (set_attr "type" "branch")]) | |
9db1d521 | 7924 | |
ed9676cf AK |
7925 | (define_insn "*sibcall_brcl" |
7926 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7927 | (match_operand 1 "const_int_operand" "n"))] | |
7928 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7929 | "jg\t%0" | |
7930 | [(set_attr "op_type" "RIL") | |
7931 | (set_attr "type" "branch")]) | |
44b8152b | 7932 | |
ed9676cf AK |
7933 | ; |
7934 | ; sibcall_value patterns | |
7935 | ; | |
9e8327e3 | 7936 | |
ed9676cf AK |
7937 | (define_expand "sibcall_value" |
7938 | [(set (match_operand 0 "" "") | |
7939 | (call (match_operand 1 "" "") | |
7940 | (match_operand 2 "" "")))] | |
7941 | "" | |
7942 | { | |
7943 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 7944 | DONE; |
10bbf137 | 7945 | }) |
9db1d521 | 7946 | |
ed9676cf AK |
7947 | (define_insn "*sibcall_value_br" |
7948 | [(set (match_operand 0 "" "") | |
ae156f85 | 7949 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 7950 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 7951 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7952 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
7953 | "br\t%%r1" | |
7954 | [(set_attr "op_type" "RR") | |
7955 | (set_attr "type" "branch") | |
7956 | (set_attr "atype" "agen")]) | |
7957 | ||
7958 | (define_insn "*sibcall_value_brc" | |
7959 | [(set (match_operand 0 "" "") | |
7960 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7961 | (match_operand 2 "const_int_operand" "n")))] | |
7962 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7963 | "j\t%1" | |
7964 | [(set_attr "op_type" "RI") | |
7965 | (set_attr "type" "branch")]) | |
7966 | ||
7967 | (define_insn "*sibcall_value_brcl" | |
7968 | [(set (match_operand 0 "" "") | |
7969 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7970 | (match_operand 2 "const_int_operand" "n")))] | |
7971 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7972 | "jg\t%1" | |
7973 | [(set_attr "op_type" "RIL") | |
7974 | (set_attr "type" "branch")]) | |
7975 | ||
7976 | ||
7977 | ; | |
7978 | ; call instruction pattern(s). | |
7979 | ; | |
7980 | ||
7981 | (define_expand "call" | |
7982 | [(call (match_operand 0 "" "") | |
7983 | (match_operand 1 "" "")) | |
7984 | (use (match_operand 2 "" ""))] | |
44b8152b | 7985 | "" |
ed9676cf | 7986 | { |
2f7e5a0d | 7987 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
7988 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
7989 | DONE; | |
7990 | }) | |
44b8152b | 7991 | |
9e8327e3 UW |
7992 | (define_insn "*bras" |
7993 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7994 | (match_operand 1 "const_int_operand" "n")) | |
7995 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7996 | "!SIBLING_CALL_P (insn) |
7997 | && TARGET_SMALL_EXEC | |
ed9676cf | 7998 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 7999 | "bras\t%2,%0" |
9db1d521 | 8000 | [(set_attr "op_type" "RI") |
4023fb28 | 8001 | (set_attr "type" "jsr")]) |
9db1d521 | 8002 | |
9e8327e3 UW |
8003 | (define_insn "*brasl" |
8004 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8005 | (match_operand 1 "const_int_operand" "n")) | |
8006 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8007 | "!SIBLING_CALL_P (insn) |
8008 | && TARGET_CPU_ZARCH | |
ed9676cf | 8009 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8010 | "brasl\t%2,%0" |
8011 | [(set_attr "op_type" "RIL") | |
077dab3b | 8012 | (set_attr "type" "jsr")]) |
9db1d521 | 8013 | |
9e8327e3 UW |
8014 | (define_insn "*basr" |
8015 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
8016 | (match_operand 1 "const_int_operand" "n")) | |
8017 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 8018 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8019 | { |
8020 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8021 | return "basr\t%2,%0"; | |
8022 | else | |
8023 | return "bas\t%2,%a0"; | |
8024 | } | |
8025 | [(set (attr "op_type") | |
8026 | (if_then_else (match_operand 0 "register_operand" "") | |
8027 | (const_string "RR") (const_string "RX"))) | |
8028 | (set_attr "type" "jsr") | |
8029 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8030 | |
8031 | ; | |
8032 | ; call_value instruction pattern(s). | |
8033 | ; | |
8034 | ||
8035 | (define_expand "call_value" | |
44b8152b UW |
8036 | [(set (match_operand 0 "" "") |
8037 | (call (match_operand 1 "" "") | |
8038 | (match_operand 2 "" ""))) | |
8039 | (use (match_operand 3 "" ""))] | |
9db1d521 | 8040 | "" |
9db1d521 | 8041 | { |
2f7e5a0d | 8042 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 8043 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 8044 | DONE; |
10bbf137 | 8045 | }) |
9db1d521 | 8046 | |
9e8327e3 | 8047 | (define_insn "*bras_r" |
c19ec8f9 | 8048 | [(set (match_operand 0 "" "") |
9e8327e3 | 8049 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 8050 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 8051 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
8052 | "!SIBLING_CALL_P (insn) |
8053 | && TARGET_SMALL_EXEC | |
ed9676cf | 8054 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8055 | "bras\t%3,%1" |
9db1d521 | 8056 | [(set_attr "op_type" "RI") |
f2d3c02a | 8057 | (set_attr "type" "jsr")]) |
9db1d521 | 8058 | |
9e8327e3 | 8059 | (define_insn "*brasl_r" |
c19ec8f9 | 8060 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8061 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8062 | (match_operand 2 "const_int_operand" "n"))) | |
8063 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
8064 | "!SIBLING_CALL_P (insn) |
8065 | && TARGET_CPU_ZARCH | |
ed9676cf | 8066 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8067 | "brasl\t%3,%1" |
8068 | [(set_attr "op_type" "RIL") | |
077dab3b | 8069 | (set_attr "type" "jsr")]) |
9db1d521 | 8070 | |
9e8327e3 | 8071 | (define_insn "*basr_r" |
c19ec8f9 | 8072 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8073 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
8074 | (match_operand 2 "const_int_operand" "n"))) | |
8075 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 8076 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8077 | { |
8078 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8079 | return "basr\t%3,%1"; | |
8080 | else | |
8081 | return "bas\t%3,%a1"; | |
8082 | } | |
8083 | [(set (attr "op_type") | |
8084 | (if_then_else (match_operand 1 "register_operand" "") | |
8085 | (const_string "RR") (const_string "RX"))) | |
8086 | (set_attr "type" "jsr") | |
8087 | (set_attr "atype" "agen")]) | |
9db1d521 | 8088 | |
fd3cd001 UW |
8089 | ;; |
8090 | ;;- Thread-local storage support. | |
8091 | ;; | |
8092 | ||
c5aa1d12 | 8093 | (define_expand "get_tp_64" |
ae156f85 | 8094 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] |
fd3cd001 | 8095 | "TARGET_64BIT" |
c5aa1d12 | 8096 | "") |
fd3cd001 | 8097 | |
c5aa1d12 | 8098 | (define_expand "get_tp_31" |
ae156f85 | 8099 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] |
fd3cd001 | 8100 | "!TARGET_64BIT" |
c5aa1d12 | 8101 | "") |
fd3cd001 | 8102 | |
c5aa1d12 | 8103 | (define_expand "set_tp_64" |
ae156f85 AS |
8104 | [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) |
8105 | (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 8106 | "TARGET_64BIT" |
c5aa1d12 | 8107 | "") |
fd3cd001 | 8108 | |
c5aa1d12 | 8109 | (define_expand "set_tp_31" |
ae156f85 AS |
8110 | [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) |
8111 | (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 8112 | "!TARGET_64BIT" |
c5aa1d12 UW |
8113 | "") |
8114 | ||
8115 | (define_insn "*set_tp" | |
ae156f85 | 8116 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
8117 | "" |
8118 | "" | |
8119 | [(set_attr "type" "none") | |
8120 | (set_attr "length" "0")]) | |
c7453384 | 8121 | |
fd3cd001 UW |
8122 | (define_insn "*tls_load_64" |
8123 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 8124 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
8125 | (match_operand:DI 2 "" "")] |
8126 | UNSPEC_TLS_LOAD))] | |
8127 | "TARGET_64BIT" | |
d40c829f | 8128 | "lg\t%0,%1%J2" |
9381e3f1 WG |
8129 | [(set_attr "op_type" "RXE") |
8130 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
8131 | |
8132 | (define_insn "*tls_load_31" | |
d3632d41 UW |
8133 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
8134 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
8135 | (match_operand:SI 2 "" "")] |
8136 | UNSPEC_TLS_LOAD))] | |
8137 | "!TARGET_64BIT" | |
d3632d41 | 8138 | "@ |
d40c829f UW |
8139 | l\t%0,%1%J2 |
8140 | ly\t%0,%1%J2" | |
9381e3f1 | 8141 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 8142 | (set_attr "type" "load") |
9381e3f1 | 8143 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 8144 | |
9e8327e3 | 8145 | (define_insn "*bras_tls" |
c19ec8f9 | 8146 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8147 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8148 | (match_operand 2 "const_int_operand" "n"))) | |
8149 | (clobber (match_operand 3 "register_operand" "=r")) | |
8150 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8151 | "!SIBLING_CALL_P (insn) |
8152 | && TARGET_SMALL_EXEC | |
ed9676cf | 8153 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8154 | "bras\t%3,%1%J4" |
fd3cd001 UW |
8155 | [(set_attr "op_type" "RI") |
8156 | (set_attr "type" "jsr")]) | |
8157 | ||
9e8327e3 | 8158 | (define_insn "*brasl_tls" |
c19ec8f9 | 8159 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8160 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8161 | (match_operand 2 "const_int_operand" "n"))) | |
8162 | (clobber (match_operand 3 "register_operand" "=r")) | |
8163 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8164 | "!SIBLING_CALL_P (insn) |
8165 | && TARGET_CPU_ZARCH | |
ed9676cf | 8166 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8167 | "brasl\t%3,%1%J4" |
8168 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
8169 | (set_attr "type" "jsr")]) |
8170 | ||
9e8327e3 | 8171 | (define_insn "*basr_tls" |
c19ec8f9 | 8172 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8173 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
8174 | (match_operand 2 "const_int_operand" "n"))) | |
8175 | (clobber (match_operand 3 "register_operand" "=r")) | |
8176 | (use (match_operand 4 "" ""))] | |
ed9676cf | 8177 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8178 | { |
8179 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8180 | return "basr\t%3,%1%J4"; | |
8181 | else | |
8182 | return "bas\t%3,%a1%J4"; | |
8183 | } | |
8184 | [(set (attr "op_type") | |
8185 | (if_then_else (match_operand 1 "register_operand" "") | |
8186 | (const_string "RR") (const_string "RX"))) | |
8187 | (set_attr "type" "jsr") | |
8188 | (set_attr "atype" "agen")]) | |
fd3cd001 | 8189 | |
e0374221 AS |
8190 | ;; |
8191 | ;;- Atomic operations | |
8192 | ;; | |
8193 | ||
8194 | ; | |
8195 | ; memory barrier pattern. | |
8196 | ; | |
8197 | ||
8198 | (define_expand "memory_barrier" | |
1a8c13b3 UB |
8199 | [(set (match_dup 0) |
8200 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] | |
e0374221 AS |
8201 | "" |
8202 | { | |
1a8c13b3 | 8203 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); |
e0374221 AS |
8204 | MEM_VOLATILE_P (operands[0]) = 1; |
8205 | }) | |
8206 | ||
8207 | (define_insn "*memory_barrier" | |
8208 | [(set (match_operand:BLK 0 "" "") | |
1a8c13b3 | 8209 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 AS |
8210 | "" |
8211 | "bcr\t15,0" | |
8212 | [(set_attr "op_type" "RR")]) | |
1a8c13b3 | 8213 | |
9381e3f1 WG |
8214 | ; Although bcr is superscalar on Z10, this variant will never become part of |
8215 | ; an execution group. | |
e0374221 AS |
8216 | |
8217 | ; | |
8218 | ; compare and swap patterns. | |
8219 | ; | |
8220 | ||
8006eaa6 AS |
8221 | (define_expand "sync_compare_and_swap<mode>" |
8222 | [(parallel | |
8223 | [(set (match_operand:TDSI 0 "register_operand" "") | |
8224 | (match_operand:TDSI 1 "memory_operand" "")) | |
8225 | (set (match_dup 1) | |
8226 | (unspec_volatile:TDSI | |
8227 | [(match_dup 1) | |
8228 | (match_operand:TDSI 2 "register_operand" "") | |
8229 | (match_operand:TDSI 3 "register_operand" "")] | |
8230 | UNSPECV_CAS)) | |
8231 | (set (reg:CCZ1 CC_REGNUM) | |
8232 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8233 | "") | |
e0374221 | 8234 | |
3093f076 AS |
8235 | (define_expand "sync_compare_and_swap<mode>" |
8236 | [(parallel | |
8237 | [(set (match_operand:HQI 0 "register_operand" "") | |
8238 | (match_operand:HQI 1 "memory_operand" "")) | |
8239 | (set (match_dup 1) | |
8240 | (unspec_volatile:HQI | |
8241 | [(match_dup 1) | |
8242 | (match_operand:HQI 2 "general_operand" "") | |
8243 | (match_operand:HQI 3 "general_operand" "")] | |
8244 | UNSPECV_CAS)) | |
8245 | (set (reg:CCZ1 CC_REGNUM) | |
8246 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8247 | "" | |
9381e3f1 | 8248 | "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], |
3093f076 AS |
8249 | operands[2], operands[3]); DONE;") |
8250 | ||
e0374221 AS |
8251 | (define_expand "sync_compare_and_swap_cc<mode>" |
8252 | [(parallel | |
8006eaa6 AS |
8253 | [(set (match_operand:TDSI 0 "register_operand" "") |
8254 | (match_operand:TDSI 1 "memory_operand" "")) | |
e0374221 | 8255 | (set (match_dup 1) |
8006eaa6 | 8256 | (unspec_volatile:TDSI |
e0374221 | 8257 | [(match_dup 1) |
8006eaa6 AS |
8258 | (match_operand:TDSI 2 "register_operand" "") |
8259 | (match_operand:TDSI 3 "register_operand" "")] | |
e0374221 AS |
8260 | UNSPECV_CAS)) |
8261 | (set (match_dup 4) | |
69950452 | 8262 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] |
e0374221 AS |
8263 | "" |
8264 | { | |
8006eaa6 | 8265 | /* Emulate compare. */ |
69950452 | 8266 | operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
e0374221 AS |
8267 | s390_compare_op0 = operands[1]; |
8268 | s390_compare_op1 = operands[2]; | |
8269 | s390_compare_emitted = operands[4]; | |
8270 | }) | |
8271 | ||
43a09b63 | 8272 | ; cds, cdsg |
8006eaa6 AS |
8273 | (define_insn "*sync_compare_and_swap<mode>" |
8274 | [(set (match_operand:DP 0 "register_operand" "=r") | |
8275 | (match_operand:DP 1 "memory_operand" "+Q")) | |
8276 | (set (match_dup 1) | |
8277 | (unspec_volatile:DP | |
8278 | [(match_dup 1) | |
8279 | (match_operand:DP 2 "register_operand" "0") | |
8280 | (match_operand:DP 3 "register_operand" "r")] | |
8281 | UNSPECV_CAS)) | |
8282 | (set (reg:CCZ1 CC_REGNUM) | |
8283 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
8284 | "" | |
8285 | "cds<tg>\t%0,%3,%S1" | |
8286 | [(set_attr "op_type" "RS<TE>") | |
8287 | (set_attr "type" "sem")]) | |
8288 | ||
43a09b63 | 8289 | ; cs, csg |
8006eaa6 | 8290 | (define_insn "*sync_compare_and_swap<mode>" |
e0374221 AS |
8291 | [(set (match_operand:GPR 0 "register_operand" "=r") |
8292 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
8293 | (set (match_dup 1) | |
8294 | (unspec_volatile:GPR | |
8295 | [(match_dup 1) | |
8296 | (match_operand:GPR 2 "register_operand" "0") | |
8297 | (match_operand:GPR 3 "register_operand" "r")] | |
8298 | UNSPECV_CAS)) | |
69950452 AS |
8299 | (set (reg:CCZ1 CC_REGNUM) |
8300 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 8301 | "" |
e0374221 AS |
8302 | "cs<g>\t%0,%3,%S1" |
8303 | [(set_attr "op_type" "RS<E>") | |
8304 | (set_attr "type" "sem")]) | |
8305 | ||
8306 | ||
45d18331 AS |
8307 | ; |
8308 | ; Other atomic instruction patterns. | |
8309 | ; | |
8310 | ||
8311 | (define_expand "sync_lock_test_and_set<mode>" | |
8312 | [(match_operand:HQI 0 "register_operand") | |
8313 | (match_operand:HQI 1 "memory_operand") | |
8314 | (match_operand:HQI 2 "general_operand")] | |
8315 | "" | |
9381e3f1 | 8316 | "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], |
45d18331 AS |
8317 | operands[2], false); DONE;") |
8318 | ||
8319 | (define_expand "sync_<atomic><mode>" | |
8320 | [(set (match_operand:HQI 0 "memory_operand") | |
8321 | (ATOMIC:HQI (match_dup 0) | |
8322 | (match_operand:HQI 1 "general_operand")))] | |
8323 | "" | |
9381e3f1 | 8324 | "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], |
45d18331 AS |
8325 | operands[1], false); DONE;") |
8326 | ||
8327 | (define_expand "sync_old_<atomic><mode>" | |
8328 | [(set (match_operand:HQI 0 "register_operand") | |
8329 | (match_operand:HQI 1 "memory_operand")) | |
8330 | (set (match_dup 1) | |
8331 | (ATOMIC:HQI (match_dup 1) | |
8332 | (match_operand:HQI 2 "general_operand")))] | |
8333 | "" | |
9381e3f1 | 8334 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], |
45d18331 AS |
8335 | operands[2], false); DONE;") |
8336 | ||
8337 | (define_expand "sync_new_<atomic><mode>" | |
8338 | [(set (match_operand:HQI 0 "register_operand") | |
8339 | (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") | |
9381e3f1 | 8340 | (match_operand:HQI 2 "general_operand"))) |
45d18331 AS |
8341 | (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] |
8342 | "" | |
9381e3f1 | 8343 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], |
45d18331 AS |
8344 | operands[2], true); DONE;") |
8345 | ||
9db1d521 HP |
8346 | ;; |
8347 | ;;- Miscellaneous instructions. | |
8348 | ;; | |
8349 | ||
8350 | ; | |
8351 | ; allocate stack instruction pattern(s). | |
8352 | ; | |
8353 | ||
8354 | (define_expand "allocate_stack" | |
ef44a6ff UW |
8355 | [(match_operand 0 "general_operand" "") |
8356 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 8357 | "TARGET_BACKCHAIN" |
9db1d521 | 8358 | { |
ef44a6ff | 8359 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 8360 | |
ef44a6ff UW |
8361 | emit_move_insn (temp, s390_back_chain_rtx ()); |
8362 | anti_adjust_stack (operands[1]); | |
8363 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 8364 | |
ef44a6ff UW |
8365 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
8366 | DONE; | |
10bbf137 | 8367 | }) |
9db1d521 HP |
8368 | |
8369 | ||
8370 | ; | |
43ab026f | 8371 | ; setjmp instruction pattern. |
9db1d521 HP |
8372 | ; |
8373 | ||
9db1d521 | 8374 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 8375 | [(match_operand 0 "" "")] |
f314b9b1 | 8376 | "flag_pic" |
9db1d521 | 8377 | { |
585539a1 | 8378 | emit_insn (s390_load_got ()); |
c41c1387 | 8379 | emit_use (pic_offset_table_rtx); |
9db1d521 | 8380 | DONE; |
fd7643fb | 8381 | }) |
9db1d521 | 8382 | |
9db1d521 HP |
8383 | ;; These patterns say how to save and restore the stack pointer. We need not |
8384 | ;; save the stack pointer at function level since we are careful to | |
8385 | ;; preserve the backchain. At block level, we have to restore the backchain | |
8386 | ;; when we restore the stack pointer. | |
8387 | ;; | |
8388 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
8389 | ;; backchain and restore both. Note that in the nonlocal case, the | |
8390 | ;; save area is a memory location. | |
8391 | ||
8392 | (define_expand "save_stack_function" | |
8393 | [(match_operand 0 "general_operand" "") | |
8394 | (match_operand 1 "general_operand" "")] | |
8395 | "" | |
8396 | "DONE;") | |
8397 | ||
8398 | (define_expand "restore_stack_function" | |
8399 | [(match_operand 0 "general_operand" "") | |
8400 | (match_operand 1 "general_operand" "")] | |
8401 | "" | |
8402 | "DONE;") | |
8403 | ||
8404 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
8405 | [(match_operand 0 "register_operand" "") |
8406 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 8407 | "TARGET_BACKCHAIN" |
9db1d521 | 8408 | { |
ef44a6ff UW |
8409 | rtx temp = gen_reg_rtx (Pmode); |
8410 | ||
8411 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
8412 | emit_move_insn (operands[0], operands[1]); | |
8413 | emit_move_insn (s390_back_chain_rtx (), temp); | |
8414 | ||
8415 | DONE; | |
10bbf137 | 8416 | }) |
9db1d521 HP |
8417 | |
8418 | (define_expand "save_stack_nonlocal" | |
8419 | [(match_operand 0 "memory_operand" "") | |
8420 | (match_operand 1 "register_operand" "")] | |
8421 | "" | |
9db1d521 | 8422 | { |
ef44a6ff UW |
8423 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
8424 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
8425 | ||
8426 | /* Copy the backchain to the first word, sp to the second and the | |
8427 | literal pool base to the third. */ | |
8428 | ||
b3d31392 | 8429 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
8430 | { |
8431 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
8432 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
8433 | } | |
8434 | ||
8435 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
8436 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 8437 | |
9db1d521 | 8438 | DONE; |
10bbf137 | 8439 | }) |
9db1d521 HP |
8440 | |
8441 | (define_expand "restore_stack_nonlocal" | |
8442 | [(match_operand 0 "register_operand" "") | |
8443 | (match_operand 1 "memory_operand" "")] | |
8444 | "" | |
9db1d521 | 8445 | { |
ef44a6ff | 8446 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 8447 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 8448 | rtx temp = NULL_RTX; |
9db1d521 | 8449 | |
43ab026f | 8450 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 8451 | literal pool base from the third. */ |
43ab026f | 8452 | |
b3d31392 | 8453 | if (TARGET_BACKCHAIN) |
ef44a6ff | 8454 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
9381e3f1 | 8455 | |
ef44a6ff UW |
8456 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); |
8457 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
8458 | ||
8459 | if (temp) | |
8460 | emit_move_insn (s390_back_chain_rtx (), temp); | |
8461 | ||
c41c1387 | 8462 | emit_use (base); |
9db1d521 | 8463 | DONE; |
10bbf137 | 8464 | }) |
9db1d521 | 8465 | |
7bcebb25 AK |
8466 | (define_expand "exception_receiver" |
8467 | [(const_int 0)] | |
8468 | "" | |
8469 | { | |
8470 | s390_set_has_landing_pad_p (true); | |
8471 | DONE; | |
8472 | }) | |
9db1d521 HP |
8473 | |
8474 | ; | |
8475 | ; nop instruction pattern(s). | |
8476 | ; | |
8477 | ||
8478 | (define_insn "nop" | |
8479 | [(const_int 0)] | |
8480 | "" | |
d40c829f | 8481 | "lr\t0,0" |
729e750f WG |
8482 | [(set_attr "op_type" "RR") |
8483 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 8484 | |
d277db6b WG |
8485 | (define_insn "nop1" |
8486 | [(const_int 1)] | |
8487 | "" | |
8488 | "lr\t1,1" | |
8489 | [(set_attr "op_type" "RR")]) | |
8490 | ||
9db1d521 HP |
8491 | |
8492 | ; | |
8493 | ; Special literal pool access instruction pattern(s). | |
8494 | ; | |
8495 | ||
416cf582 UW |
8496 | (define_insn "*pool_entry" |
8497 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
8498 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 8499 | "" |
9db1d521 | 8500 | { |
416cf582 UW |
8501 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
8502 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 8503 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
8504 | return ""; |
8505 | } | |
b628bd8e | 8506 | [(set (attr "length") |
416cf582 | 8507 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 8508 | |
9bb86f41 UW |
8509 | (define_insn "pool_align" |
8510 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
8511 | UNSPECV_POOL_ALIGN)] | |
8512 | "" | |
8513 | ".align\t%0" | |
b628bd8e | 8514 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 8515 | |
9bb86f41 UW |
8516 | (define_insn "pool_section_start" |
8517 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
8518 | "" | |
8519 | ".section\t.rodata" | |
b628bd8e | 8520 | [(set_attr "length" "0")]) |
b2ccb744 | 8521 | |
9bb86f41 UW |
8522 | (define_insn "pool_section_end" |
8523 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
8524 | "" | |
b2ccb744 | 8525 | ".previous" |
b628bd8e | 8526 | [(set_attr "length" "0")]) |
b2ccb744 | 8527 | |
5af2f3d3 | 8528 | (define_insn "main_base_31_small" |
9e8327e3 UW |
8529 | [(set (match_operand 0 "register_operand" "=a") |
8530 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8531 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
8532 | "basr\t%0,0" |
8533 | [(set_attr "op_type" "RR") | |
8534 | (set_attr "type" "la")]) | |
8535 | ||
8536 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
8537 | [(set (match_operand 0 "register_operand" "=a") |
8538 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 8539 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 8540 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
8541 | "bras\t%0,%2" |
8542 | [(set_attr "op_type" "RI")]) | |
8543 | ||
8544 | (define_insn "main_base_64" | |
9e8327e3 UW |
8545 | [(set (match_operand 0 "register_operand" "=a") |
8546 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8547 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
8548 | "larl\t%0,%1" |
8549 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 8550 | (set_attr "type" "larl") |
729e750f | 8551 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
8552 | |
8553 | (define_insn "main_pool" | |
585539a1 UW |
8554 | [(set (match_operand 0 "register_operand" "=a") |
8555 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
8556 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
8557 | { |
8558 | gcc_unreachable (); | |
8559 | } | |
9381e3f1 | 8560 | [(set (attr "type") |
ea77e738 UW |
8561 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
8562 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 8563 | |
aee4e0db | 8564 | (define_insn "reload_base_31" |
9e8327e3 UW |
8565 | [(set (match_operand 0 "register_operand" "=a") |
8566 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8567 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8568 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
8569 | [(set_attr "length" "6") |
8570 | (set_attr "type" "la")]) | |
b2ccb744 | 8571 | |
aee4e0db | 8572 | (define_insn "reload_base_64" |
9e8327e3 UW |
8573 | [(set (match_operand 0 "register_operand" "=a") |
8574 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8575 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8576 | "larl\t%0,%1" |
aee4e0db | 8577 | [(set_attr "op_type" "RIL") |
9381e3f1 | 8578 | (set_attr "type" "larl") |
729e750f | 8579 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 8580 | |
aee4e0db | 8581 | (define_insn "pool" |
fd7643fb | 8582 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 8583 | "" |
8d933e31 AS |
8584 | { |
8585 | gcc_unreachable (); | |
8586 | } | |
b628bd8e | 8587 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 8588 | |
4023fb28 UW |
8589 | ;; |
8590 | ;; Insns related to generating the function prologue and epilogue. | |
8591 | ;; | |
8592 | ||
8593 | ||
8594 | (define_expand "prologue" | |
8595 | [(use (const_int 0))] | |
8596 | "" | |
10bbf137 | 8597 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
8598 | |
8599 | (define_expand "epilogue" | |
8600 | [(use (const_int 1))] | |
8601 | "" | |
ed9676cf AK |
8602 | "s390_emit_epilogue (false); DONE;") |
8603 | ||
8604 | (define_expand "sibcall_epilogue" | |
8605 | [(use (const_int 0))] | |
8606 | "" | |
8607 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 8608 | |
9e8327e3 | 8609 | (define_insn "*return" |
4023fb28 | 8610 | [(return) |
9e8327e3 UW |
8611 | (use (match_operand 0 "register_operand" "a"))] |
8612 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8613 | "br\t%0" |
4023fb28 | 8614 | [(set_attr "op_type" "RR") |
c7453384 | 8615 | (set_attr "type" "jsr") |
077dab3b | 8616 | (set_attr "atype" "agen")]) |
4023fb28 | 8617 | |
4023fb28 | 8618 | |
c7453384 | 8619 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 8620 | ;; pointer. This is used for compatibility. |
c7453384 EC |
8621 | |
8622 | (define_expand "ptr_extend" | |
8623 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8624 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 8625 | "TARGET_64BIT" |
c7453384 | 8626 | { |
c7453384 EC |
8627 | emit_insn (gen_anddi3 (operands[0], |
8628 | gen_lowpart (DImode, operands[1]), | |
8629 | GEN_INT (0x7fffffff))); | |
c7453384 | 8630 | DONE; |
10bbf137 | 8631 | }) |
4798630c D |
8632 | |
8633 | ;; Instruction definition to expand eh_return macro to support | |
8634 | ;; swapping in special linkage return addresses. | |
8635 | ||
8636 | (define_expand "eh_return" | |
8637 | [(use (match_operand 0 "register_operand" ""))] | |
8638 | "TARGET_TPF" | |
8639 | { | |
8640 | s390_emit_tpf_eh_return (operands[0]); | |
8641 | DONE; | |
8642 | }) | |
8643 | ||
7b8acc34 AK |
8644 | ; |
8645 | ; Stack Protector Patterns | |
8646 | ; | |
8647 | ||
8648 | (define_expand "stack_protect_set" | |
8649 | [(set (match_operand 0 "memory_operand" "") | |
8650 | (match_operand 1 "memory_operand" ""))] | |
8651 | "" | |
8652 | { | |
8653 | #ifdef TARGET_THREAD_SSP_OFFSET | |
8654 | operands[1] | |
8655 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
8656 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
8657 | #endif | |
8658 | if (TARGET_64BIT) | |
8659 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
8660 | else | |
8661 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
8662 | ||
8663 | DONE; | |
8664 | }) | |
8665 | ||
8666 | (define_insn "stack_protect_set<mode>" | |
8667 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
8668 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
8669 | "" | |
8670 | "mvc\t%O0(%G0,%R0),%S1" | |
8671 | [(set_attr "op_type" "SS")]) | |
8672 | ||
8673 | (define_expand "stack_protect_test" | |
8674 | [(set (reg:CC CC_REGNUM) | |
8675 | (compare (match_operand 0 "memory_operand" "") | |
8676 | (match_operand 1 "memory_operand" ""))) | |
8677 | (match_operand 2 "" "")] | |
8678 | "" | |
8679 | { | |
8680 | #ifdef TARGET_THREAD_SSP_OFFSET | |
8681 | operands[1] | |
8682 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
8683 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
8684 | #endif | |
8685 | s390_compare_op0 = operands[0]; | |
8686 | s390_compare_op1 = operands[1]; | |
8687 | s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM); | |
8688 | ||
8689 | if (TARGET_64BIT) | |
8690 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
8691 | else | |
8692 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
8693 | ||
8694 | emit_jump_insn (gen_beq (operands[2])); | |
8695 | ||
8696 | DONE; | |
8697 | }) | |
8698 | ||
8699 | (define_insn "stack_protect_test<mode>" | |
8700 | [(set (reg:CCZ CC_REGNUM) | |
8701 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
8702 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
8703 | "" | |
8704 | "clc\t%O0(%G0,%R0),%S1" | |
8705 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
8706 | |
8707 | ; This is used in s390_emit_prologue in order to prevent insns | |
8708 | ; adjusting the stack pointer to be moved over insns writing stack | |
8709 | ; slots using a copy of the stack pointer in a different register. | |
8710 | (define_insn "stack_tie" | |
8711 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
8712 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
8713 | "" | |
8714 | "" | |
8715 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
8716 | |
8717 | ||
8718 | ; | |
8719 | ; Data prefetch patterns | |
8720 | ; | |
8721 | ||
8722 | (define_insn "prefetch" | |
8723 | [(prefetch (match_operand 0 "address_operand" "UW,X") | |
8724 | (match_operand:SI 1 "const_int_operand" "n,n") | |
8725 | (match_operand:SI 2 "const_int_operand" "n,n"))] | |
8726 | "TARGET_Z10" | |
8727 | { | |
8728 | if (larl_operand (operands[0], Pmode)) | |
8729 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
8730 | ||
8731 | if (s390_mem_constraint ("W", operands[0]) | |
8732 | || s390_mem_constraint ("U", operands[0])) | |
8733 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; | |
8734 | ||
8735 | /* This point might be reached if op0 is a larl operand with an | |
8736 | uneven addend. In this case we simply omit issuing a prefetch | |
8737 | instruction. */ | |
8738 | ||
8739 | return ""; | |
9381e3f1 WG |
8740 | } |
8741 | [(set_attr "type" "load,larl") | |
8742 | (set_attr "op_type" "RXY,RIL") | |
8743 | (set_attr "z10prop" "z10_super")]) |