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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
66647d44 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
c75c517d | 3 | ;; 2009, 2010 Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
5 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
6 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 7 | |
58add37a UW |
8 | ;; This file is part of GCC. |
9 | ||
10 | ;; GCC is free software; you can redistribute it and/or modify it under | |
11 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
13 | ;; version. |
14 | ||
15 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | ;; for more details. | |
9db1d521 HP |
19 | |
20 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | ;; along with GCC; see the file COPYING3. If not see |
22 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
23 | |
24 | ;; | |
cd8dc1f9 | 25 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 26 | ;; |
cd8dc1f9 | 27 | |
9db1d521 HP |
28 | ;; Special formats used for outputting 390 instructions. |
29 | ;; | |
f19a9af7 AK |
30 | ;; %C: print opcode suffix for branch condition. |
31 | ;; %D: print opcode suffix for inverse branch condition. | |
32 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 33 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
34 | ;; %O: print only the displacement of a memory reference. |
35 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 36 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
37 | ;; %N: print the second word of a DImode operand. |
38 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 39 | ;; %Y: print shift count operand. |
f4aa3848 | 40 | ;; |
f19a9af7 | 41 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 42 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
43 | ;; %x: print integer X as if it's an unsigned halfword. |
44 | ;; %h: print integer X as if it's a signed halfword. | |
45 | ;; %i: print the first nonzero HImode part of X. | |
46 | ;; %j: print the first HImode part unequal to -1 of X. | |
47 | ;; %k: print the first nonzero SImode part of X. | |
48 | ;; %m: print the first SImode part unequal to -1 of X. | |
49 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
50 | ;; |
51 | ;; We have a special constraint for pattern matching. | |
52 | ;; | |
53 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
54 | ;; | |
9db1d521 | 55 | |
fd3cd001 UW |
56 | ;; |
57 | ;; UNSPEC usage | |
58 | ;; | |
59 | ||
30a49b23 AK |
60 | (define_c_enum "unspec" [ |
61 | ; Miscellaneous | |
62 | UNSPEC_ROUND | |
63 | UNSPEC_CCU_TO_INT | |
64 | UNSPEC_CCZ_TO_INT | |
65 | UNSPEC_ICM | |
66 | UNSPEC_TIE | |
10bbf137 UW |
67 | |
68 | ; GOT/PLT and lt-relative accesses | |
30a49b23 AK |
69 | UNSPEC_LTREL_OFFSET |
70 | UNSPEC_LTREL_BASE | |
71 | UNSPEC_POOL_OFFSET | |
72 | UNSPEC_GOTENT | |
73 | UNSPEC_GOT | |
74 | UNSPEC_GOTOFF | |
75 | UNSPEC_PLT | |
76 | UNSPEC_PLTOFF | |
fd7643fb UW |
77 | |
78 | ; Literal pool | |
30a49b23 AK |
79 | UNSPEC_RELOAD_BASE |
80 | UNSPEC_MAIN_BASE | |
81 | UNSPEC_LTREF | |
82 | UNSPEC_INSN | |
83 | UNSPEC_EXECUTE | |
fd7643fb | 84 | |
1a8c13b3 | 85 | ; Atomic Support |
30a49b23 | 86 | UNSPEC_MB |
78ce265b | 87 | UNSPEC_MOVA |
1a8c13b3 | 88 | |
fd7643fb | 89 | ; TLS relocation specifiers |
30a49b23 AK |
90 | UNSPEC_TLSGD |
91 | UNSPEC_TLSLDM | |
92 | UNSPEC_NTPOFF | |
93 | UNSPEC_DTPOFF | |
94 | UNSPEC_GOTNTPOFF | |
95 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
96 | |
97 | ; TLS support | |
30a49b23 AK |
98 | UNSPEC_TLSLDM_NTPOFF |
99 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
100 | |
101 | ; String Functions | |
30a49b23 AK |
102 | UNSPEC_SRST |
103 | UNSPEC_MVST | |
638e37c2 | 104 | |
7b8acc34 | 105 | ; Stack Smashing Protector |
30a49b23 AK |
106 | UNSPEC_SP_SET |
107 | UNSPEC_SP_TEST | |
85dae55a | 108 | |
638e37c2 | 109 | ; Test Data Class (TDC) |
30a49b23 | 110 | UNSPEC_TDC_INSN |
65b1d8ea AK |
111 | |
112 | ; Population Count | |
30a49b23 AK |
113 | UNSPEC_POPCNT |
114 | UNSPEC_COPYSIGN | |
fd3cd001 UW |
115 | ]) |
116 | ||
117 | ;; | |
118 | ;; UNSPEC_VOLATILE usage | |
119 | ;; | |
120 | ||
30a49b23 AK |
121 | (define_c_enum "unspecv" [ |
122 | ; Blockage | |
123 | UNSPECV_BLOCKAGE | |
10bbf137 | 124 | |
2f7e5a0d | 125 | ; TPF Support |
30a49b23 AK |
126 | UNSPECV_TPF_PROLOGUE |
127 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 128 | |
10bbf137 | 129 | ; Literal pool |
30a49b23 AK |
130 | UNSPECV_POOL |
131 | UNSPECV_POOL_SECTION | |
132 | UNSPECV_POOL_ALIGN | |
133 | UNSPECV_POOL_ENTRY | |
134 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
135 | |
136 | ; TLS support | |
30a49b23 | 137 | UNSPECV_SET_TP |
e0374221 AS |
138 | |
139 | ; Atomic Support | |
30a49b23 AK |
140 | UNSPECV_CAS |
141 | UNSPECV_ATOMIC_OP | |
fd3cd001 UW |
142 | ]) |
143 | ||
ae156f85 AS |
144 | ;; |
145 | ;; Registers | |
146 | ;; | |
147 | ||
35dd9a0e AK |
148 | ; Registers with special meaning |
149 | ||
ae156f85 AS |
150 | (define_constants |
151 | [ | |
152 | ; Sibling call register. | |
153 | (SIBCALL_REGNUM 1) | |
154 | ; Literal pool base register. | |
155 | (BASE_REGNUM 13) | |
156 | ; Return address register. | |
157 | (RETURN_REGNUM 14) | |
158 | ; Condition code register. | |
159 | (CC_REGNUM 33) | |
f4aa3848 | 160 | ; Thread local storage pointer register. |
ae156f85 AS |
161 | (TP_REGNUM 36) |
162 | ]) | |
163 | ||
35dd9a0e AK |
164 | ; Hardware register names |
165 | ||
166 | (define_constants | |
167 | [ | |
168 | ; General purpose registers | |
169 | (GPR0_REGNUM 0) | |
170 | ; Floating point registers. | |
171 | (FPR0_REGNUM 16) | |
172 | (FPR2_REGNUM 18) | |
173 | ]) | |
174 | ||
175 | ;; | |
176 | ;; PFPO GPR0 argument format | |
177 | ;; | |
178 | ||
179 | (define_constants | |
180 | [ | |
181 | ; PFPO operation type | |
182 | (PFPO_CONVERT 0x1000000) | |
183 | ; PFPO operand types | |
184 | (PFPO_OP_TYPE_SF 0x5) | |
185 | (PFPO_OP_TYPE_DF 0x6) | |
186 | (PFPO_OP_TYPE_TF 0x7) | |
187 | (PFPO_OP_TYPE_SD 0x8) | |
188 | (PFPO_OP_TYPE_DD 0x9) | |
189 | (PFPO_OP_TYPE_TD 0xa) | |
190 | ; Bitposition of operand types | |
191 | (PFPO_OP0_TYPE_SHIFT 16) | |
192 | (PFPO_OP1_TYPE_SHIFT 8) | |
193 | ]) | |
194 | ||
fd3cd001 | 195 | |
29a74354 UW |
196 | ;; Instruction operand type as used in the Principles of Operation. |
197 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 198 | |
29a74354 | 199 | (define_attr "op_type" |
963fc8d0 | 200 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" |
b628bd8e | 201 | (const_string "NN")) |
9db1d521 | 202 | |
29a74354 | 203 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 204 | |
077dab3b | 205 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 206 | cs,vs,store,sem,idiv, |
ed0e512a | 207 | imulhi,imulsi,imuldi, |
2cdece44 | 208 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
209 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
210 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 211 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 212 | fmadddf,fmaddsf, |
9381e3f1 WG |
213 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
214 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
215 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
216 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
217 | ftoidfp, other" | |
29a74354 UW |
218 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
219 | (eq_attr "op_type" "SS") (const_string "cs")] | |
220 | (const_string "integer"))) | |
9db1d521 | 221 | |
29a74354 UW |
222 | ;; Another attribute used for scheduling purposes: |
223 | ;; agen: Instruction uses the address generation unit | |
224 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
225 | |
226 | (define_attr "atype" "agen,reg" | |
c68e7b86 | 227 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") |
0101708c AS |
228 | (const_string "reg") |
229 | (const_string "agen"))) | |
9db1d521 | 230 | |
9381e3f1 WG |
231 | ;; Properties concerning Z10 execution grouping and value forwarding. |
232 | ;; z10_super: instruction is superscalar. | |
233 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
234 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
235 | ;; target register. It can forward this value to a second instruction that reads | |
236 | ;; the same register if that second instruction is issued in the same group. | |
237 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
238 | ;; instruction in the S pipe writes to the register, then the T instruction | |
239 | ;; can immediately read the new value. | |
240 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
241 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
242 | ;; |
243 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
244 | ||
245 | ||
246 | (define_attr "z10prop" "none, | |
247 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
248 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
249 | z10_rec, | |
250 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 251 | z10_c" |
9381e3f1 WG |
252 | (const_string "none")) |
253 | ||
65b1d8ea AK |
254 | ;; Properties concerning Z196 decoding |
255 | ;; z196_alone: must group alone | |
256 | ;; z196_end: ends a group | |
257 | ;; z196_cracked: instruction is cracked or expanded | |
258 | (define_attr "z196prop" "none, | |
259 | z196_alone, z196_ends, | |
260 | z196_cracked" | |
261 | (const_string "none")) | |
9381e3f1 | 262 | |
22ac2c2f AK |
263 | (define_attr "mnemonic" "unknown" (const_string "unknown")) |
264 | ||
9db1d521 HP |
265 | ;; Length in bytes. |
266 | ||
267 | (define_attr "length" "" | |
963fc8d0 AK |
268 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
269 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 270 | (const_int 6))) |
9db1d521 | 271 | |
29a74354 UW |
272 | |
273 | ;; Processor type. This attribute must exactly match the processor_type | |
274 | ;; enumeration in s390.h. The current machine description does not | |
275 | ;; distinguish between g5 and g6, but there are differences between the two | |
276 | ;; CPUs could in theory be modeled. | |
277 | ||
22ac2c2f | 278 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12" |
90c6fd8a | 279 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 280 | |
22ac2c2f | 281 | (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196,zEC12" |
3af8e996 AK |
282 | (const_string "standard")) |
283 | ||
284 | (define_attr "enabled" "" | |
285 | (cond [(eq_attr "cpu_facility" "standard") | |
286 | (const_int 1) | |
287 | ||
288 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 289 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
290 | (const_int 1) |
291 | ||
292 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 293 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
294 | (const_int 1) |
295 | ||
296 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 297 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
298 | (const_int 1) |
299 | ||
300 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 301 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
302 | (const_int 1) |
303 | ||
304 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 305 | (match_test "TARGET_DFP")) |
93538e8e AK |
306 | (const_int 1) |
307 | ||
308 | (and (eq_attr "cpu_facility" "z10") | |
d7f99b2c | 309 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
310 | (const_int 1) |
311 | ||
312 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 313 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
314 | (const_int 1) |
315 | ||
316 | (and (eq_attr "cpu_facility" "zEC12") | |
317 | (match_test "TARGET_ZEC12")) | |
3af8e996 AK |
318 | (const_int 1)] |
319 | (const_int 0))) | |
320 | ||
29a74354 UW |
321 | ;; Pipeline description for z900. For lack of anything better, |
322 | ;; this description is also used for the g5 and g6. | |
323 | (include "2064.md") | |
324 | ||
3443392a | 325 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
326 | (include "2084.md") |
327 | ||
9381e3f1 WG |
328 | ;; Pipeline description for z10 |
329 | (include "2097.md") | |
330 | ||
65b1d8ea AK |
331 | ;; Pipeline description for z196 |
332 | (include "2817.md") | |
333 | ||
22ac2c2f AK |
334 | ;; Pipeline description for zEC12 |
335 | (include "2827.md") | |
336 | ||
0bfc3f69 AS |
337 | ;; Predicates |
338 | (include "predicates.md") | |
339 | ||
cd8dc1f9 WG |
340 | ;; Constraint definitions |
341 | (include "constraints.md") | |
342 | ||
a8ba31f2 EC |
343 | ;; Other includes |
344 | (include "tpf.md") | |
f52c81dd | 345 | |
3abcb3a7 | 346 | ;; Iterators |
f52c81dd | 347 | |
3abcb3a7 | 348 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 349 | ;; same template. |
f4aa3848 | 350 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 351 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 | 352 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
963fc8d0 | 353 | (define_mode_iterator FPALL [TF DF SF TD DD SD]) |
3abcb3a7 HPN |
354 | (define_mode_iterator BFP [TF DF SF]) |
355 | (define_mode_iterator DFP [TD DD]) | |
356 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
357 | (define_mode_iterator DSF [DF SF]) | |
358 | (define_mode_iterator SD_SF [SF SD]) | |
359 | (define_mode_iterator DD_DF [DF DD]) | |
360 | (define_mode_iterator TD_TF [TF TD]) | |
361 | ||
3abcb3a7 | 362 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 363 | ;; from the same template. |
9602b6a1 | 364 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 365 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 366 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 367 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 368 | |
3abcb3a7 | 369 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 370 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 371 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 372 | |
78ce265b RH |
373 | ;; These macros refer to the actual word_mode of the configuration. |
374 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
375 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
376 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
377 | ||
6e0d70c9 AK |
378 | ;; Used by the umul pattern to express modes having half the size. |
379 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
380 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
381 | ||
3abcb3a7 | 382 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 383 | ;; the same template. |
3abcb3a7 | 384 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 385 | |
3abcb3a7 | 386 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 387 | ;; same template. |
9602b6a1 | 388 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
963fc8d0 | 389 | (define_mode_iterator INTALL [TI DI SI HI QI]) |
78ce265b | 390 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
342cf42b | 391 | |
3abcb3a7 | 392 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 393 | ;; the same template. |
3abcb3a7 | 394 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 395 | |
3abcb3a7 HPN |
396 | ;; This iterator and attribute allow to combine most atomic operations. |
397 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 398 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
f4aa3848 | 399 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") |
45d18331 | 400 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 401 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 402 | |
f4aa3848 | 403 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
404 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
405 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 406 | |
f4aa3848 AK |
407 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
408 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
409 | ;; SDmode. |
410 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 411 | |
609e7e80 | 412 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
413 | ;; Likewise for "<RXe>". |
414 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
415 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
416 | ||
609e7e80 | 417 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 418 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
419 | ;; dfp variants in a single insn definition. |
420 | ||
3abcb3a7 | 421 | ;; This attribute is used to set op_type accordingly. |
f4aa3848 | 422 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
609e7e80 AK |
423 | (DD "RRR") (SD "RRR")]) |
424 | ||
f4aa3848 | 425 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
426 | ;; first and the second operand match for bfp modes. |
427 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
428 | ||
f4aa3848 | 429 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
430 | ;; additional operand for the dfp instructions. |
431 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
432 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
433 | ||
f5905b37 | 434 | |
85dae55a AK |
435 | ;; This attribute is used in the operand constraint list |
436 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
437 | ;; TFmode values are represented by a fp register pair. Since the | |
438 | ;; sign bit instructions only handle single source and target fp registers | |
439 | ;; these instructions can only be used for TFmode values if the source and | |
440 | ;; target operand uses the same fp register. | |
441 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
442 | ||
609e7e80 AK |
443 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
444 | ;; This is used to disable the memory alternative in TFmode patterns. | |
445 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
446 | ||
3abcb3a7 | 447 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
448 | ;; within instruction mnemonics. |
449 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
450 | ||
0387c142 WG |
451 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
452 | ;; modes and to an empty string for bfp modes. | |
453 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
454 | ||
1b48c8cc AS |
455 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
456 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
457 | ;; version only operates on one register. | |
458 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
459 | ||
460 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
461 | ;; version only operates on one register. The DImode version needs an additional | |
462 | ;; register for the assembler output. | |
463 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
464 | |
465 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
466 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
467 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
468 | ||
469 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 470 | ;; pattern itself and the corresponding function calls. |
f337b930 | 471 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
472 | |
473 | ;; This attribute handles differences in the instruction 'type' and will result | |
474 | ;; in "RRE" for DImode and "RR" for SImode. | |
475 | (define_mode_attr E [(DI "E") (SI "")]) | |
476 | ||
3298c037 AK |
477 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
478 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
479 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
480 | ||
8006eaa6 AS |
481 | ;; This attribute handles differences in the instruction 'type' and will result |
482 | ;; in "RSE" for TImode and "RS" for DImode. | |
483 | (define_mode_attr TE [(TI "E") (DI "")]) | |
484 | ||
9a91a21f AS |
485 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
486 | ;; and "lcr" in SImode. | |
487 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 488 | |
3298c037 AK |
489 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
490 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
491 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
492 | ;; variant for long displacements. | |
493 | (define_mode_attr y [(DI "g") (SI "y")]) | |
494 | ||
9602b6a1 | 495 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
496 | ;; and "cds" in DImode. |
497 | (define_mode_attr tg [(TI "g") (DI "")]) | |
498 | ||
78ce265b RH |
499 | ;; In TDI templates, a string like "c<d>sg". |
500 | (define_mode_attr td [(TI "d") (DI "")]) | |
501 | ||
2f8f8434 AS |
502 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
503 | ;; and "cfdbr" in SImode. | |
504 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
505 | ||
65b1d8ea AK |
506 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
507 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
508 | ;; 3 operands shift instructions into the existing patterns. | |
509 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
510 | ||
f52c81dd AS |
511 | ;; ICM mask required to load MODE value into the lowest subreg |
512 | ;; of a SImode register. | |
513 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
514 | ||
f6ee577c AS |
515 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
516 | ;; HImode and "llgc" in QImode. | |
517 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
518 | ||
a1aed706 AS |
519 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
520 | ;; in SImode. | |
521 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
522 | ||
609e7e80 AK |
523 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
524 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
525 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
526 | ||
f52c81dd AS |
527 | ;; Maximum unsigned integer that fits in MODE. |
528 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
529 | ||
75ca1b39 RH |
530 | ;; Start and end field computations for RISBG et al. |
531 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
532 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
533 | ||
9db1d521 HP |
534 | ;; |
535 | ;;- Compare instructions. | |
536 | ;; | |
537 | ||
07893d4f | 538 | ; Test-under-Mask instructions |
9db1d521 | 539 | |
07893d4f | 540 | (define_insn "*tmqi_mem" |
ae156f85 | 541 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
542 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
543 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
544 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 545 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 546 | "@ |
fc0ea003 UW |
547 | tm\t%S0,%b1 |
548 | tmy\t%S0,%b1" | |
9381e3f1 WG |
549 | [(set_attr "op_type" "SI,SIY") |
550 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 551 | |
05b9aaaa | 552 | (define_insn "*tmdi_reg" |
ae156f85 | 553 | [(set (reg CC_REGNUM) |
f19a9af7 | 554 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 555 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
556 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
557 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 558 | "TARGET_ZARCH |
3ed99cc9 | 559 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
560 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
561 | "@ | |
562 | tmhh\t%0,%i1 | |
563 | tmhl\t%0,%i1 | |
564 | tmlh\t%0,%i1 | |
565 | tmll\t%0,%i1" | |
9381e3f1 WG |
566 | [(set_attr "op_type" "RI") |
567 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
568 | |
569 | (define_insn "*tmsi_reg" | |
ae156f85 | 570 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
571 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
572 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
573 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 574 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
575 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
576 | "@ | |
577 | tmh\t%0,%i1 | |
578 | tml\t%0,%i1" | |
729e750f WG |
579 | [(set_attr "op_type" "RI") |
580 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 581 | |
f52c81dd | 582 | (define_insn "*tm<mode>_full" |
ae156f85 | 583 | [(set (reg CC_REGNUM) |
f52c81dd AS |
584 | (compare (match_operand:HQI 0 "register_operand" "d") |
585 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 586 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 587 | "tml\t%0,<max_uint>" |
729e750f WG |
588 | [(set_attr "op_type" "RI") |
589 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 590 | |
07893d4f | 591 | |
08a5aaa2 | 592 | ; |
07893d4f | 593 | ; Load-and-Test instructions |
08a5aaa2 AS |
594 | ; |
595 | ||
c0220ea4 | 596 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
597 | |
598 | (define_insn "*tstdi_sign" | |
ae156f85 | 599 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
600 | (compare |
601 | (ashiftrt:DI | |
602 | (ashift:DI | |
603 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
604 | (const_int 32)) (const_int 32)) | |
605 | (match_operand:DI 1 "const0_operand" ""))) | |
606 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 607 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 608 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
609 | "ltgfr\t%2,%0 |
610 | ltgf\t%2,%0" | |
611 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
612 | (set_attr "cpu_facility" "*,z10") |
613 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 614 | |
43a09b63 | 615 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 616 | (define_insn "*tst<mode>_extimm" |
ec24698e | 617 | [(set (reg CC_REGNUM) |
fb492564 | 618 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
619 | (match_operand:GPR 1 "const0_operand" ""))) |
620 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 621 | (match_dup 0))] |
08a5aaa2 | 622 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 623 | "@ |
08a5aaa2 AS |
624 | lt<g>r\t%2,%0 |
625 | lt<g>\t%2,%0" | |
9381e3f1 | 626 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 627 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 628 | |
43a09b63 | 629 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 630 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 631 | [(set (reg CC_REGNUM) |
fb492564 | 632 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
633 | (match_operand:GPR 1 "const0_operand" ""))) |
634 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
635 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 636 | "@ |
08a5aaa2 AS |
637 | lt<g>r\t%0,%0 |
638 | lt<g>\t%2,%0" | |
9381e3f1 | 639 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 640 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 641 | |
07893d4f | 642 | (define_insn "*tstdi" |
ae156f85 | 643 | [(set (reg CC_REGNUM) |
07893d4f UW |
644 | (compare (match_operand:DI 0 "register_operand" "d") |
645 | (match_operand:DI 1 "const0_operand" ""))) | |
646 | (set (match_operand:DI 2 "register_operand" "=d") | |
647 | (match_dup 0))] | |
9602b6a1 | 648 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 649 | "ltgr\t%2,%0" |
9381e3f1 WG |
650 | [(set_attr "op_type" "RRE") |
651 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 652 | |
07893d4f | 653 | (define_insn "*tstsi" |
ae156f85 | 654 | [(set (reg CC_REGNUM) |
d3632d41 | 655 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 656 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 657 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 658 | (match_dup 0))] |
ec24698e | 659 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 660 | "@ |
d40c829f | 661 | ltr\t%2,%0 |
fc0ea003 UW |
662 | icm\t%2,15,%S0 |
663 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
664 | [(set_attr "op_type" "RR,RS,RSY") |
665 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 666 | |
07893d4f | 667 | (define_insn "*tstsi_cconly" |
ae156f85 | 668 | [(set (reg CC_REGNUM) |
d3632d41 | 669 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 670 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 671 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
672 | "s390_match_ccmode(insn, CCSmode)" |
673 | "@ | |
d40c829f | 674 | ltr\t%0,%0 |
fc0ea003 UW |
675 | icm\t%2,15,%S0 |
676 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
677 | [(set_attr "op_type" "RR,RS,RSY") |
678 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 679 | |
08a5aaa2 AS |
680 | (define_insn "*tstdi_cconly_31" |
681 | [(set (reg CC_REGNUM) | |
682 | (compare (match_operand:DI 0 "register_operand" "d") | |
683 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 684 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
685 | "srda\t%0,0" |
686 | [(set_attr "op_type" "RS") | |
687 | (set_attr "atype" "reg")]) | |
688 | ||
43a09b63 | 689 | ; ltr, ltgr |
08a5aaa2 | 690 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 691 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
692 | (compare (match_operand:GPR 0 "register_operand" "d") |
693 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 694 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 695 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
696 | [(set_attr "op_type" "RR<E>") |
697 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 698 | |
c0220ea4 | 699 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 700 | |
f52c81dd | 701 | (define_insn "*tst<mode>CCT" |
ae156f85 | 702 | [(set (reg CC_REGNUM) |
f52c81dd AS |
703 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
704 | (match_operand:HQI 1 "const0_operand" ""))) | |
705 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
706 | (match_dup 0))] |
707 | "s390_match_ccmode(insn, CCTmode)" | |
708 | "@ | |
f52c81dd AS |
709 | icm\t%2,<icm_lo>,%S0 |
710 | icmy\t%2,<icm_lo>,%S0 | |
711 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
712 | [(set_attr "op_type" "RS,RSY,RI") |
713 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
714 | |
715 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 716 | [(set (reg CC_REGNUM) |
d3632d41 | 717 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 718 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 719 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
720 | "s390_match_ccmode(insn, CCTmode)" |
721 | "@ | |
fc0ea003 UW |
722 | icm\t%2,3,%S0 |
723 | icmy\t%2,3,%S0 | |
d40c829f | 724 | tml\t%0,65535" |
9381e3f1 WG |
725 | [(set_attr "op_type" "RS,RSY,RI") |
726 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 727 | |
3af97654 | 728 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 729 | [(set (reg CC_REGNUM) |
d3632d41 | 730 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
731 | (match_operand:QI 1 "const0_operand" "")))] |
732 | "s390_match_ccmode(insn, CCTmode)" | |
733 | "@ | |
fc0ea003 UW |
734 | cli\t%S0,0 |
735 | cliy\t%S0,0 | |
d40c829f | 736 | tml\t%0,255" |
9381e3f1 | 737 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 738 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 739 | |
f52c81dd | 740 | (define_insn "*tst<mode>" |
ae156f85 | 741 | [(set (reg CC_REGNUM) |
f52c81dd AS |
742 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
743 | (match_operand:HQI 1 "const0_operand" ""))) | |
744 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
745 | (match_dup 0))] |
746 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 747 | "@ |
f52c81dd AS |
748 | icm\t%2,<icm_lo>,%S0 |
749 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
750 | [(set_attr "op_type" "RS,RSY") |
751 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 752 | |
f52c81dd | 753 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 754 | [(set (reg CC_REGNUM) |
f52c81dd AS |
755 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
756 | (match_operand:HQI 1 "const0_operand" ""))) | |
757 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 758 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 759 | "@ |
f52c81dd AS |
760 | icm\t%2,<icm_lo>,%S0 |
761 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
762 | [(set_attr "op_type" "RS,RSY") |
763 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 764 | |
9db1d521 | 765 | |
575f7c2b UW |
766 | ; Compare (equality) instructions |
767 | ||
768 | (define_insn "*cmpdi_cct" | |
ae156f85 | 769 | [(set (reg CC_REGNUM) |
ec24698e | 770 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 771 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 772 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
773 | "@ |
774 | cgr\t%0,%1 | |
f4f41b4e | 775 | cghi\t%0,%h1 |
ec24698e | 776 | cgfi\t%0,%1 |
575f7c2b | 777 | cg\t%0,%1 |
19b63d8e | 778 | #" |
9381e3f1 WG |
779 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
780 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
781 | |
782 | (define_insn "*cmpsi_cct" | |
ae156f85 | 783 | [(set (reg CC_REGNUM) |
ec24698e UW |
784 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
785 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 786 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
787 | "@ |
788 | cr\t%0,%1 | |
f4f41b4e | 789 | chi\t%0,%h1 |
ec24698e | 790 | cfi\t%0,%1 |
575f7c2b UW |
791 | c\t%0,%1 |
792 | cy\t%0,%1 | |
19b63d8e | 793 | #" |
9381e3f1 | 794 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 795 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 796 | |
07893d4f | 797 | ; Compare (signed) instructions |
4023fb28 | 798 | |
07893d4f | 799 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 800 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
801 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
802 | "d,RT,b")) | |
803 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 804 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 805 | "@ |
d40c829f | 806 | cgfr\t%0,%1 |
963fc8d0 AK |
807 | cgf\t%0,%1 |
808 | cgfrl\t%0,%1" | |
809 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 810 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 811 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 812 | |
9381e3f1 WG |
813 | |
814 | ||
07893d4f | 815 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 816 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
817 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
818 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 819 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 820 | "@ |
d40c829f | 821 | ch\t%0,%1 |
963fc8d0 AK |
822 | chy\t%0,%1 |
823 | chrl\t%0,%1" | |
824 | [(set_attr "op_type" "RX,RXY,RIL") | |
825 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
826 | (set_attr "type" "*,*,larl") |
827 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
828 | |
829 | (define_insn "*cmphi_ccs_z10" | |
830 | [(set (reg CC_REGNUM) | |
831 | (compare (match_operand:HI 0 "s_operand" "Q") | |
832 | (match_operand:HI 1 "immediate_operand" "K")))] | |
833 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
834 | "chhsi\t%0,%1" | |
65b1d8ea AK |
835 | [(set_attr "op_type" "SIL") |
836 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
837 | |
838 | (define_insn "*cmpdi_ccs_signhi_rl" | |
839 | [(set (reg CC_REGNUM) | |
840 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
841 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
842 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
843 | "@ | |
844 | cgh\t%0,%1 | |
845 | cghrl\t%0,%1" | |
846 | [(set_attr "op_type" "RXY,RIL") | |
847 | (set_attr "type" "*,larl")]) | |
4023fb28 | 848 | |
963fc8d0 | 849 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 850 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 851 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
852 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
853 | "d,d,Q, d,d,d,d") | |
854 | (match_operand:GPR 1 "general_operand" | |
855 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 856 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 857 | "@ |
3298c037 AK |
858 | c<g>r\t%0,%1 |
859 | c<g>hi\t%0,%h1 | |
963fc8d0 | 860 | c<g>hsi\t%0,%h1 |
3298c037 AK |
861 | c<g>fi\t%0,%1 |
862 | c<g>\t%0,%1 | |
963fc8d0 AK |
863 | c<y>\t%0,%1 |
864 | c<g>rl\t%0,%1" | |
865 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
866 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
867 | (set_attr "type" "*,*,*,*,*,*,larl") |
868 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 869 | |
07893d4f UW |
870 | |
871 | ; Compare (unsigned) instructions | |
9db1d521 | 872 | |
963fc8d0 AK |
873 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
874 | [(set (reg CC_REGNUM) | |
875 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
876 | "larl_operand" "X"))) | |
877 | (match_operand:SI 0 "register_operand" "d")))] | |
878 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
879 | "clhrl\t%0,%1" | |
880 | [(set_attr "op_type" "RIL") | |
729e750f WG |
881 | (set_attr "type" "larl") |
882 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
883 | |
884 | ; clhrl, clghrl | |
885 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
886 | [(set (reg CC_REGNUM) | |
887 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
888 | "larl_operand" "X"))) | |
889 | (match_operand:GPR 0 "register_operand" "d")))] | |
890 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
891 | "cl<g>hrl\t%0,%1" | |
892 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
893 | (set_attr "type" "larl") |
894 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 895 | |
07893d4f | 896 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 897 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
898 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
899 | "d,RT,b")) | |
900 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 901 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 902 | "@ |
d40c829f | 903 | clgfr\t%0,%1 |
963fc8d0 AK |
904 | clgf\t%0,%1 |
905 | clgfrl\t%0,%1" | |
906 | [(set_attr "op_type" "RRE,RXY,RIL") | |
907 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
908 | (set_attr "type" "*,*,larl") |
909 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 910 | |
07893d4f | 911 | (define_insn "*cmpdi_ccu" |
ae156f85 | 912 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
913 | (compare (match_operand:DI 0 "nonimmediate_operand" |
914 | "d, d,d,Q, d, Q,BQ") | |
915 | (match_operand:DI 1 "general_operand" | |
916 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 917 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 918 | "@ |
d40c829f | 919 | clgr\t%0,%1 |
ec24698e | 920 | clgfi\t%0,%1 |
963fc8d0 AK |
921 | clgrl\t%0,%1 |
922 | clghsi\t%0,%x1 | |
575f7c2b | 923 | clg\t%0,%1 |
e221ef54 | 924 | # |
19b63d8e | 925 | #" |
963fc8d0 AK |
926 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
927 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
928 | (set_attr "type" "*,*,larl,*,*,*,*") |
929 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 930 | |
07893d4f | 931 | (define_insn "*cmpsi_ccu" |
ae156f85 | 932 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
933 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
934 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 935 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 936 | "@ |
d40c829f | 937 | clr\t%0,%1 |
ec24698e | 938 | clfi\t%0,%o1 |
963fc8d0 AK |
939 | clrl\t%0,%1 |
940 | clfhsi\t%0,%x1 | |
d40c829f | 941 | cl\t%0,%1 |
575f7c2b | 942 | cly\t%0,%1 |
e221ef54 | 943 | # |
19b63d8e | 944 | #" |
963fc8d0 AK |
945 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
946 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
947 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
948 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 949 | |
07893d4f | 950 | (define_insn "*cmphi_ccu" |
ae156f85 | 951 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
952 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
953 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 954 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 955 | && !register_operand (operands[1], HImode)" |
d3632d41 | 956 | "@ |
fc0ea003 UW |
957 | clm\t%0,3,%S1 |
958 | clmy\t%0,3,%S1 | |
963fc8d0 | 959 | clhhsi\t%0,%1 |
e221ef54 | 960 | # |
19b63d8e | 961 | #" |
963fc8d0 | 962 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
963 | (set_attr "cpu_facility" "*,*,z10,*,*") |
964 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
965 | |
966 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 967 | [(set (reg CC_REGNUM) |
e221ef54 UW |
968 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
969 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 970 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 971 | && !register_operand (operands[1], QImode)" |
d3632d41 | 972 | "@ |
fc0ea003 UW |
973 | clm\t%0,1,%S1 |
974 | clmy\t%0,1,%S1 | |
975 | cli\t%S0,%b1 | |
976 | cliy\t%S0,%b1 | |
e221ef54 | 977 | # |
19b63d8e | 978 | #" |
9381e3f1 WG |
979 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
980 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
981 | |
982 | ||
19b63d8e UW |
983 | ; Block compare (CLC) instruction patterns. |
984 | ||
985 | (define_insn "*clc" | |
ae156f85 | 986 | [(set (reg CC_REGNUM) |
d4f52f0e | 987 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
988 | (match_operand:BLK 1 "memory_operand" "Q"))) |
989 | (use (match_operand 2 "const_int_operand" "n"))] | |
990 | "s390_match_ccmode (insn, CCUmode) | |
991 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 992 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 993 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
994 | |
995 | (define_split | |
ae156f85 | 996 | [(set (reg CC_REGNUM) |
19b63d8e UW |
997 | (compare (match_operand 0 "memory_operand" "") |
998 | (match_operand 1 "memory_operand" "")))] | |
999 | "reload_completed | |
1000 | && s390_match_ccmode (insn, CCUmode) | |
1001 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1002 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1003 | [(parallel | |
1004 | [(set (match_dup 0) (match_dup 1)) | |
1005 | (use (match_dup 2))])] | |
1006 | { | |
1007 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1008 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1009 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1010 | ||
1011 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1012 | operands[0], operands[1]); | |
1013 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1014 | }) | |
1015 | ||
1016 | ||
609e7e80 | 1017 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1018 | |
609e7e80 | 1019 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1020 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1021 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1022 | (compare (match_operand:FP 0 "register_operand" "f") |
1023 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1024 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1025 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1026 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1027 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1028 | |
be5de7a1 | 1029 | ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb |
f5905b37 | 1030 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1031 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1032 | (compare (match_operand:FP 0 "register_operand" "f,f") |
1033 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 1034 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1035 | "@ |
609e7e80 | 1036 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1037 | c<xde>b\t%0,%1" |
077dab3b | 1038 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 1039 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1040 | |
963fc8d0 AK |
1041 | |
1042 | ; Compare and Branch instructions | |
1043 | ||
1044 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1045 | ; The following instructions do a complementary access of their second |
1046 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1047 | (define_insn "*cmp_and_br_signed_<mode>" |
1048 | [(set (pc) | |
1049 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1050 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1051 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1052 | (label_ref (match_operand 3 "" "")) | |
1053 | (pc))) | |
1054 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1055 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1056 | { |
1057 | if (get_attr_length (insn) == 6) | |
1058 | return which_alternative ? | |
1059 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1060 | else | |
1061 | return which_alternative ? | |
1062 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1063 | } | |
1064 | [(set_attr "op_type" "RIE") | |
1065 | (set_attr "type" "branch") | |
e3cba5e5 | 1066 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1067 | (set (attr "length") |
1068 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1069 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1070 | ; 10 byte for cgr/jg | |
1071 | ||
1072 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1073 | ; The following instructions do a complementary access of their second |
1074 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1075 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1076 | [(set (pc) | |
1077 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1078 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1079 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1080 | (label_ref (match_operand 3 "" "")) | |
1081 | (pc))) | |
1082 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1083 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1084 | { |
1085 | if (get_attr_length (insn) == 6) | |
1086 | return which_alternative ? | |
1087 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1088 | else | |
1089 | return which_alternative ? | |
1090 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1091 | } | |
1092 | [(set_attr "op_type" "RIE") | |
1093 | (set_attr "type" "branch") | |
e3cba5e5 | 1094 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1095 | (set (attr "length") |
1096 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1097 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1098 | ; 10 byte for clgr/jg | |
1099 | ||
b0f86a7e AK |
1100 | ; And now the same two patterns as above but with a negated CC mask. |
1101 | ||
1102 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1103 | ; The following instructions do a complementary access of their second | |
1104 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1105 | (define_insn "*icmp_and_br_signed_<mode>" | |
1106 | [(set (pc) | |
1107 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1108 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1109 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1110 | (pc) | |
1111 | (label_ref (match_operand 3 "" "")))) | |
1112 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1113 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1114 | { |
1115 | if (get_attr_length (insn) == 6) | |
1116 | return which_alternative ? | |
1117 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1118 | else | |
1119 | return which_alternative ? | |
1120 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1121 | } | |
1122 | [(set_attr "op_type" "RIE") | |
1123 | (set_attr "type" "branch") | |
1124 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1125 | (set (attr "length") | |
1126 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1127 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1128 | ; 10 byte for cgr/jg | |
1129 | ||
1130 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1131 | ; The following instructions do a complementary access of their second | |
1132 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1133 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1134 | [(set (pc) | |
1135 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1136 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1137 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1138 | (pc) | |
1139 | (label_ref (match_operand 3 "" "")))) | |
1140 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1141 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1142 | { |
1143 | if (get_attr_length (insn) == 6) | |
1144 | return which_alternative ? | |
1145 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1146 | else | |
1147 | return which_alternative ? | |
1148 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1149 | } | |
1150 | [(set_attr "op_type" "RIE") | |
1151 | (set_attr "type" "branch") | |
1152 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1153 | (set (attr "length") | |
1154 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1155 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1156 | ; 10 byte for clgr/jg | |
1157 | ||
9db1d521 HP |
1158 | ;; |
1159 | ;;- Move instructions. | |
1160 | ;; | |
1161 | ||
1162 | ; | |
1163 | ; movti instruction pattern(s). | |
1164 | ; | |
1165 | ||
1166 | (define_insn "movti" | |
f2dc2f86 AK |
1167 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") |
1168 | (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] | |
9602b6a1 | 1169 | "TARGET_ZARCH" |
4023fb28 | 1170 | "@ |
fc0ea003 UW |
1171 | lmg\t%0,%N0,%S1 |
1172 | stmg\t%1,%N1,%S0 | |
4023fb28 | 1173 | # |
19b63d8e | 1174 | #" |
f2dc2f86 AK |
1175 | [(set_attr "op_type" "RSY,RSY,*,*") |
1176 | (set_attr "type" "lm,stm,*,*")]) | |
4023fb28 UW |
1177 | |
1178 | (define_split | |
1179 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1180 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1181 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1182 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1183 | [(set (match_dup 2) (match_dup 4)) |
1184 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1185 | { |
dc65c307 UW |
1186 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1187 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1188 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1189 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1190 | }) | |
1191 | ||
1192 | (define_split | |
1193 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1194 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1195 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1196 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1197 | [(set (match_dup 2) (match_dup 4)) | |
1198 | (set (match_dup 3) (match_dup 5))] | |
1199 | { | |
1200 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1201 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1202 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1203 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1204 | }) | |
4023fb28 UW |
1205 | |
1206 | (define_split | |
1207 | [(set (match_operand:TI 0 "register_operand" "") | |
1208 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1209 | "TARGET_ZARCH && reload_completed |
4023fb28 | 1210 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1211 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1212 | { |
1213 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1214 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1215 | s390_load_address (addr, XEXP (operands[1], 0)); |
1216 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1217 | }) |
1218 | ||
833cd70a AK |
1219 | |
1220 | ; | |
1221 | ; Patterns used for secondary reloads | |
1222 | ; | |
1223 | ||
963fc8d0 AK |
1224 | ; z10 provides move instructions accepting larl memory operands. |
1225 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1226 | ; These patterns are also used for unaligned SI and DI accesses. | |
1227 | ||
1228 | (define_expand "reload<INTALL:mode><P:mode>_tomem_z10" | |
1229 | [(parallel [(match_operand:INTALL 0 "memory_operand" "") | |
1230 | (match_operand:INTALL 1 "register_operand" "=d") | |
1231 | (match_operand:P 2 "register_operand" "=&a")])] | |
1232 | "TARGET_Z10" | |
1233 | { | |
1234 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1235 | DONE; | |
1236 | }) | |
1237 | ||
1238 | (define_expand "reload<INTALL:mode><P:mode>_toreg_z10" | |
1239 | [(parallel [(match_operand:INTALL 0 "register_operand" "=d") | |
1240 | (match_operand:INTALL 1 "memory_operand" "") | |
1241 | (match_operand:P 2 "register_operand" "=a")])] | |
1242 | "TARGET_Z10" | |
1243 | { | |
1244 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1245 | DONE; | |
1246 | }) | |
1247 | ||
1248 | (define_expand "reload<FPALL:mode><P:mode>_tomem_z10" | |
1249 | [(parallel [(match_operand:FPALL 0 "memory_operand" "") | |
1250 | (match_operand:FPALL 1 "register_operand" "=d") | |
1251 | (match_operand:P 2 "register_operand" "=&a")])] | |
1252 | "TARGET_Z10" | |
1253 | { | |
1254 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1255 | DONE; | |
1256 | }) | |
1257 | ||
1258 | (define_expand "reload<FPALL:mode><P:mode>_toreg_z10" | |
1259 | [(parallel [(match_operand:FPALL 0 "register_operand" "=d") | |
1260 | (match_operand:FPALL 1 "memory_operand" "") | |
1261 | (match_operand:P 2 "register_operand" "=a")])] | |
1262 | "TARGET_Z10" | |
1263 | { | |
1264 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1265 | DONE; | |
1266 | }) | |
1267 | ||
1268 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1269 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1270 | (match_operand:P 1 "larl_operand" "") | |
1271 | (match_operand:P 2 "register_operand" "=a")])] | |
1272 | "TARGET_Z10" | |
1273 | { | |
1274 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1275 | DONE; | |
1276 | }) | |
1277 | ||
833cd70a AK |
1278 | ; Handles loading a PLUS (load address) expression |
1279 | ||
1280 | (define_expand "reload<mode>_plus" | |
1281 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1282 | (match_operand:P 1 "s390_plus_operand" "") | |
1283 | (match_operand:P 2 "register_operand" "=&a")])] | |
1284 | "" | |
1285 | { | |
1286 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1287 | DONE; | |
1288 | }) | |
1289 | ||
1290 | ; Handles assessing a non-offsetable memory address | |
1291 | ||
1292 | (define_expand "reload<mode>_nonoffmem_in" | |
1293 | [(parallel [(match_operand 0 "register_operand" "") | |
1294 | (match_operand 1 "" "") | |
1295 | (match_operand:P 2 "register_operand" "=&a")])] | |
1296 | "" | |
1297 | { | |
1298 | gcc_assert (MEM_P (operands[1])); | |
1299 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1300 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1301 | emit_move_insn (operands[0], operands[1]); | |
1302 | DONE; | |
1303 | }) | |
1304 | ||
1305 | (define_expand "reload<mode>_nonoffmem_out" | |
1306 | [(parallel [(match_operand 0 "" "") | |
1307 | (match_operand 1 "register_operand" "") | |
1308 | (match_operand:P 2 "register_operand" "=&a")])] | |
1309 | "" | |
dc65c307 | 1310 | { |
9c3c3dcc | 1311 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1312 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1313 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1314 | emit_move_insn (operands[0], operands[1]); | |
1315 | DONE; | |
1316 | }) | |
9db1d521 | 1317 | |
1f9e1fc6 AK |
1318 | (define_expand "reload<mode>_PIC_addr" |
1319 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1320 | (match_operand 1 "larl_operand" "") | |
1321 | (match_operand:P 2 "register_operand" "=a")])] | |
1322 | "" | |
1323 | { | |
0a2aaacc KG |
1324 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1325 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1326 | }) |
1327 | ||
9db1d521 HP |
1328 | ; |
1329 | ; movdi instruction pattern(s). | |
1330 | ; | |
1331 | ||
9db1d521 HP |
1332 | (define_expand "movdi" |
1333 | [(set (match_operand:DI 0 "general_operand" "") | |
1334 | (match_operand:DI 1 "general_operand" ""))] | |
1335 | "" | |
9db1d521 | 1336 | { |
fd3cd001 | 1337 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1338 | if (TARGET_64BIT |
1339 | && (SYMBOLIC_CONST (operands[1]) | |
1340 | || (GET_CODE (operands[1]) == PLUS | |
1341 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1342 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1343 | emit_symbolic_move (operands); |
10bbf137 | 1344 | }) |
9db1d521 | 1345 | |
4023fb28 UW |
1346 | (define_insn "*movdi_larl" |
1347 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1348 | (match_operand:DI 1 "larl_operand" "X"))] | |
1349 | "TARGET_64BIT | |
8e509cf9 | 1350 | && !FP_REG_P (operands[0])" |
d40c829f | 1351 | "larl\t%0,%1" |
4023fb28 | 1352 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1353 | (set_attr "type" "larl") |
1354 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1355 | |
3af8e996 | 1356 | (define_insn "*movdi_64" |
85dae55a | 1357 | [(set (match_operand:DI 0 "nonimmediate_operand" |
963fc8d0 | 1358 | "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, |
f2dc2f86 | 1359 | RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") |
85dae55a | 1360 | (match_operand:DI 1 "general_operand" |
963fc8d0 | 1361 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, |
f2dc2f86 | 1362 | d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] |
9602b6a1 | 1363 | "TARGET_ZARCH" |
85dae55a AK |
1364 | "@ |
1365 | lghi\t%0,%h1 | |
1366 | llihh\t%0,%i1 | |
1367 | llihl\t%0,%i1 | |
1368 | llilh\t%0,%i1 | |
1369 | llill\t%0,%i1 | |
1370 | lgfi\t%0,%1 | |
1371 | llihf\t%0,%k1 | |
1372 | llilf\t%0,%k1 | |
1373 | ldgr\t%0,%1 | |
1374 | lgdr\t%0,%1 | |
1375 | lay\t%0,%a1 | |
963fc8d0 | 1376 | lgrl\t%0,%1 |
85dae55a AK |
1377 | lgr\t%0,%1 |
1378 | lg\t%0,%1 | |
1379 | stg\t%1,%0 | |
1380 | ldr\t%0,%1 | |
1381 | ld\t%0,%1 | |
1382 | ldy\t%0,%1 | |
1383 | std\t%1,%0 | |
1384 | stdy\t%1,%0 | |
963fc8d0 AK |
1385 | stgrl\t%1,%0 |
1386 | mvghi\t%0,%1 | |
85dae55a AK |
1387 | # |
1388 | # | |
1389 | stam\t%1,%N1,%S0 | |
f2dc2f86 | 1390 | lam\t%0,%N0,%S1" |
963fc8d0 | 1391 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
f2dc2f86 | 1392 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS") |
963fc8d0 AK |
1393 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
1394 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, | |
f2dc2f86 | 1395 | *,*") |
3af8e996 | 1396 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1397 | z10,*,*,*,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1398 | z10,z10,*,*,*,*") |
9381e3f1 WG |
1399 | (set_attr "z10prop" "z10_fwd_A1, |
1400 | z10_fwd_E1, | |
1401 | z10_fwd_E1, | |
1402 | z10_fwd_E1, | |
1403 | z10_fwd_E1, | |
1404 | z10_fwd_A1, | |
1405 | z10_fwd_E1, | |
1406 | z10_fwd_E1, | |
1407 | *, | |
1408 | *, | |
1409 | z10_fwd_A1, | |
1410 | z10_fwd_A3, | |
1411 | z10_fr_E1, | |
1412 | z10_fwd_A3, | |
1413 | z10_rec, | |
1414 | *, | |
1415 | *, | |
1416 | *, | |
1417 | *, | |
1418 | *, | |
1419 | z10_rec, | |
1420 | z10_super, | |
1421 | *, | |
1422 | *, | |
1423 | *, | |
9381e3f1 WG |
1424 | *") |
1425 | ]) | |
c5aa1d12 UW |
1426 | |
1427 | (define_split | |
1428 | [(set (match_operand:DI 0 "register_operand" "") | |
1429 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1430 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1431 | [(set (match_dup 2) (match_dup 3)) |
1432 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1433 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1434 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1435 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1436 | ||
1437 | (define_split | |
1438 | [(set (match_operand:DI 0 "register_operand" "") | |
1439 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1440 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1441 | && dead_or_set_p (insn, operands[1])" |
1442 | [(set (match_dup 3) (match_dup 2)) | |
1443 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1444 | (set (match_dup 4) (match_dup 2))] | |
1445 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1446 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1447 | ||
1448 | (define_split | |
1449 | [(set (match_operand:DI 0 "register_operand" "") | |
1450 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1451 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1452 | && !dead_or_set_p (insn, operands[1])" |
1453 | [(set (match_dup 3) (match_dup 2)) | |
1454 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1455 | (set (match_dup 4) (match_dup 2)) | |
1456 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1457 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1458 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1459 | |
1460 | (define_insn "*movdi_31" | |
963fc8d0 | 1461 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1462 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1463 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1464 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1465 | "!TARGET_ZARCH" |
4023fb28 | 1466 | "@ |
fc0ea003 | 1467 | lm\t%0,%N0,%S1 |
c4d50129 | 1468 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1469 | stm\t%1,%N1,%S0 |
c4d50129 | 1470 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1471 | # |
1472 | # | |
d40c829f UW |
1473 | ldr\t%0,%1 |
1474 | ld\t%0,%1 | |
1475 | ldy\t%0,%1 | |
1476 | std\t%1,%0 | |
1477 | stdy\t%1,%0 | |
19b63d8e | 1478 | #" |
f2dc2f86 AK |
1479 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1480 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1481 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1482 | |
1483 | ; For a load from a symbol ref we can use one of the target registers | |
1484 | ; together with larl to load the address. | |
1485 | (define_split | |
1486 | [(set (match_operand:DI 0 "register_operand" "") | |
1487 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1488 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1489 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1490 | [(set (match_dup 2) (match_dup 3)) | |
1491 | (set (match_dup 0) (match_dup 1))] | |
1492 | { | |
1493 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1494 | operands[3] = XEXP (operands[1], 0); | |
1495 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1496 | }) | |
4023fb28 UW |
1497 | |
1498 | (define_split | |
1499 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1500 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1501 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1502 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1503 | [(set (match_dup 2) (match_dup 4)) |
1504 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1505 | { |
dc65c307 UW |
1506 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1507 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1508 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1509 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1510 | }) | |
1511 | ||
1512 | (define_split | |
1513 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1514 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1515 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1516 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1517 | [(set (match_dup 2) (match_dup 4)) | |
1518 | (set (match_dup 3) (match_dup 5))] | |
1519 | { | |
1520 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1521 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1522 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1523 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1524 | }) | |
9db1d521 | 1525 | |
4023fb28 UW |
1526 | (define_split |
1527 | [(set (match_operand:DI 0 "register_operand" "") | |
1528 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1529 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1530 | && !FP_REG_P (operands[0]) |
4023fb28 | 1531 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1532 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1533 | { |
1534 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1535 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1536 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1537 | }) |
1538 | ||
84817c5d UW |
1539 | (define_peephole2 |
1540 | [(set (match_operand:DI 0 "register_operand" "") | |
1541 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1542 | "TARGET_ZARCH |
84817c5d UW |
1543 | && !FP_REG_P (operands[0]) |
1544 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1545 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1546 | && get_pool_mode (operands[1]) == DImode | |
1547 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1548 | [(set (match_dup 0) (match_dup 2))] | |
1549 | "operands[2] = get_pool_constant (operands[1]);") | |
1550 | ||
7bdff56f UW |
1551 | (define_insn "*la_64" |
1552 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1553 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1554 | "TARGET_64BIT" |
1555 | "@ | |
1556 | la\t%0,%a1 | |
1557 | lay\t%0,%a1" | |
1558 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1559 | (set_attr "type" "la") |
1560 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1561 | |
1562 | (define_peephole2 | |
1563 | [(parallel | |
1564 | [(set (match_operand:DI 0 "register_operand" "") | |
1565 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1566 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1567 | "TARGET_64BIT |
e1d5ee28 | 1568 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1569 | [(set (match_dup 0) (match_dup 1))] |
1570 | "") | |
1571 | ||
1572 | (define_peephole2 | |
1573 | [(set (match_operand:DI 0 "register_operand" "") | |
1574 | (match_operand:DI 1 "register_operand" "")) | |
1575 | (parallel | |
1576 | [(set (match_dup 0) | |
1577 | (plus:DI (match_dup 0) | |
1578 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1579 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1580 | "TARGET_64BIT |
1581 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1582 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1583 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1584 | "") | |
1585 | ||
9db1d521 HP |
1586 | ; |
1587 | ; movsi instruction pattern(s). | |
1588 | ; | |
1589 | ||
9db1d521 HP |
1590 | (define_expand "movsi" |
1591 | [(set (match_operand:SI 0 "general_operand" "") | |
1592 | (match_operand:SI 1 "general_operand" ""))] | |
1593 | "" | |
9db1d521 | 1594 | { |
fd3cd001 | 1595 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1596 | if (!TARGET_64BIT |
1597 | && (SYMBOLIC_CONST (operands[1]) | |
1598 | || (GET_CODE (operands[1]) == PLUS | |
1599 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1600 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1601 | emit_symbolic_move (operands); |
10bbf137 | 1602 | }) |
9db1d521 | 1603 | |
9e8327e3 UW |
1604 | (define_insn "*movsi_larl" |
1605 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1606 | (match_operand:SI 1 "larl_operand" "X"))] | |
1607 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1608 | && !FP_REG_P (operands[0])" | |
1609 | "larl\t%0,%1" | |
1610 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1611 | (set_attr "type" "larl") |
729e750f | 1612 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1613 | |
f19a9af7 | 1614 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1615 | [(set (match_operand:SI 0 "nonimmediate_operand" |
f2dc2f86 | 1616 | "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t") |
2f7e5a0d | 1617 | (match_operand:SI 1 "general_operand" |
f2dc2f86 | 1618 | "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))] |
f19a9af7 | 1619 | "TARGET_ZARCH" |
9db1d521 | 1620 | "@ |
f19a9af7 AK |
1621 | lhi\t%0,%h1 |
1622 | llilh\t%0,%i1 | |
1623 | llill\t%0,%i1 | |
ec24698e | 1624 | iilf\t%0,%o1 |
f19a9af7 | 1625 | lay\t%0,%a1 |
963fc8d0 | 1626 | lrl\t%0,%1 |
d40c829f UW |
1627 | lr\t%0,%1 |
1628 | l\t%0,%1 | |
1629 | ly\t%0,%1 | |
1630 | st\t%1,%0 | |
1631 | sty\t%1,%0 | |
1632 | ler\t%0,%1 | |
1633 | le\t%0,%1 | |
1634 | ley\t%0,%1 | |
1635 | ste\t%1,%0 | |
1636 | stey\t%1,%0 | |
c5aa1d12 UW |
1637 | ear\t%0,%1 |
1638 | sar\t%0,%1 | |
1639 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1640 | strl\t%1,%0 |
1641 | mvhi\t%0,%1 | |
f2dc2f86 | 1642 | lam\t%0,%0,%S1" |
963fc8d0 | 1643 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
f2dc2f86 | 1644 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS") |
9381e3f1 WG |
1645 | (set_attr "type" "*, |
1646 | *, | |
1647 | *, | |
1648 | *, | |
1649 | la, | |
1650 | larl, | |
1651 | lr, | |
1652 | load, | |
1653 | load, | |
1654 | store, | |
1655 | store, | |
1656 | floadsf, | |
1657 | floadsf, | |
1658 | floadsf, | |
1659 | fstoresf, | |
1660 | fstoresf, | |
1661 | *, | |
1662 | *, | |
1663 | *, | |
1664 | larl, | |
1665 | *, | |
9381e3f1 | 1666 | *") |
963fc8d0 | 1667 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1668 | *,*,longdisp,*,longdisp,*,*,*,z10,z10,*") |
9381e3f1 WG |
1669 | (set_attr "z10prop" "z10_fwd_A1, |
1670 | z10_fwd_E1, | |
1671 | z10_fwd_E1, | |
1672 | z10_fwd_A1, | |
1673 | z10_fwd_A1, | |
1674 | z10_fwd_A3, | |
1675 | z10_fr_E1, | |
1676 | z10_fwd_A3, | |
1677 | z10_fwd_A3, | |
729e750f | 1678 | z10_rec, |
9381e3f1 WG |
1679 | z10_rec, |
1680 | *, | |
1681 | *, | |
1682 | *, | |
1683 | *, | |
1684 | *, | |
1685 | z10_super_E1, | |
1686 | z10_super, | |
1687 | *, | |
1688 | z10_rec, | |
1689 | z10_super, | |
9381e3f1 | 1690 | *")]) |
f19a9af7 AK |
1691 | |
1692 | (define_insn "*movsi_esa" | |
f2dc2f86 AK |
1693 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t") |
1694 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1695 | "!TARGET_ZARCH" |
1696 | "@ | |
1697 | lhi\t%0,%h1 | |
1698 | lr\t%0,%1 | |
1699 | l\t%0,%1 | |
1700 | st\t%1,%0 | |
1701 | ler\t%0,%1 | |
1702 | le\t%0,%1 | |
1703 | ste\t%1,%0 | |
c5aa1d12 UW |
1704 | ear\t%0,%1 |
1705 | sar\t%0,%1 | |
1706 | stam\t%1,%1,%S0 | |
f2dc2f86 AK |
1707 | lam\t%0,%0,%S1" |
1708 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS") | |
1709 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*") | |
9381e3f1 WG |
1710 | (set_attr "z10prop" "z10_fwd_A1, |
1711 | z10_fr_E1, | |
1712 | z10_fwd_A3, | |
729e750f | 1713 | z10_rec, |
9381e3f1 WG |
1714 | *, |
1715 | *, | |
1716 | *, | |
1717 | z10_super_E1, | |
1718 | z10_super, | |
1719 | *, | |
9381e3f1 WG |
1720 | *") |
1721 | ]) | |
9db1d521 | 1722 | |
84817c5d UW |
1723 | (define_peephole2 |
1724 | [(set (match_operand:SI 0 "register_operand" "") | |
1725 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1726 | "!FP_REG_P (operands[0]) | |
1727 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1728 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1729 | && get_pool_mode (operands[1]) == SImode | |
1730 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1731 | [(set (match_dup 0) (match_dup 2))] | |
1732 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1733 | |
7bdff56f UW |
1734 | (define_insn "*la_31" |
1735 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1736 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1737 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1738 | "@ | |
1739 | la\t%0,%a1 | |
1740 | lay\t%0,%a1" | |
1741 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1742 | (set_attr "type" "la") |
1743 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1744 | |
1745 | (define_peephole2 | |
1746 | [(parallel | |
1747 | [(set (match_operand:SI 0 "register_operand" "") | |
1748 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1749 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1750 | "!TARGET_64BIT |
e1d5ee28 | 1751 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1752 | [(set (match_dup 0) (match_dup 1))] |
1753 | "") | |
1754 | ||
1755 | (define_peephole2 | |
1756 | [(set (match_operand:SI 0 "register_operand" "") | |
1757 | (match_operand:SI 1 "register_operand" "")) | |
1758 | (parallel | |
1759 | [(set (match_dup 0) | |
1760 | (plus:SI (match_dup 0) | |
1761 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1762 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1763 | "!TARGET_64BIT |
1764 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1765 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1766 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1767 | "") | |
1768 | ||
1769 | (define_insn "*la_31_and" | |
1770 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1771 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
1772 | (const_int 2147483647)))] |
1773 | "!TARGET_64BIT" | |
1774 | "@ | |
1775 | la\t%0,%a1 | |
1776 | lay\t%0,%a1" | |
1777 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1778 | (set_attr "type" "la") |
1779 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1780 | |
1781 | (define_insn_and_split "*la_31_and_cc" | |
1782 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1783 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1784 | (const_int 2147483647))) | |
ae156f85 | 1785 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1786 | "!TARGET_64BIT" |
1787 | "#" | |
1788 | "&& reload_completed" | |
1789 | [(set (match_dup 0) | |
1790 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1791 | "" | |
1792 | [(set_attr "op_type" "RX") | |
1793 | (set_attr "type" "la")]) | |
1794 | ||
1795 | (define_insn "force_la_31" | |
1796 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1797 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
1798 | (use (const_int 0))] |
1799 | "!TARGET_64BIT" | |
1800 | "@ | |
1801 | la\t%0,%a1 | |
1802 | lay\t%0,%a1" | |
1803 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
1804 | (set_attr "type" "la") |
1805 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 1806 | |
9db1d521 HP |
1807 | ; |
1808 | ; movhi instruction pattern(s). | |
1809 | ; | |
1810 | ||
02ed3c5e UW |
1811 | (define_expand "movhi" |
1812 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1813 | (match_operand:HI 1 "general_operand" ""))] | |
1814 | "" | |
1815 | { | |
2f7e5a0d | 1816 | /* Make it explicit that loading a register from memory |
02ed3c5e | 1817 | always sign-extends (at least) to SImode. */ |
b3a13419 | 1818 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 1819 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1820 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1821 | { |
1822 | rtx tmp = gen_reg_rtx (SImode); | |
1823 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1824 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1825 | operands[1] = gen_lowpart (HImode, tmp); | |
1826 | } | |
1827 | }) | |
1828 | ||
1829 | (define_insn "*movhi" | |
f2dc2f86 AK |
1830 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q") |
1831 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))] | |
9db1d521 HP |
1832 | "" |
1833 | "@ | |
d40c829f UW |
1834 | lr\t%0,%1 |
1835 | lhi\t%0,%h1 | |
1836 | lh\t%0,%1 | |
1837 | lhy\t%0,%1 | |
963fc8d0 | 1838 | lhrl\t%0,%1 |
d40c829f UW |
1839 | sth\t%1,%0 |
1840 | sthy\t%1,%0 | |
963fc8d0 | 1841 | sthrl\t%1,%0 |
f2dc2f86 AK |
1842 | mvhhi\t%0,%1" |
1843 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL") | |
1844 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*") | |
1845 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10") | |
9381e3f1 WG |
1846 | (set_attr "z10prop" "z10_fr_E1, |
1847 | z10_fwd_A1, | |
1848 | z10_super_E1, | |
1849 | z10_super_E1, | |
1850 | z10_super_E1, | |
729e750f | 1851 | z10_rec, |
9381e3f1 WG |
1852 | z10_rec, |
1853 | z10_rec, | |
f2dc2f86 | 1854 | z10_super")]) |
9db1d521 | 1855 | |
84817c5d UW |
1856 | (define_peephole2 |
1857 | [(set (match_operand:HI 0 "register_operand" "") | |
1858 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1859 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1860 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1861 | && get_pool_mode (operands[1]) == HImode | |
1862 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1863 | [(set (match_dup 0) (match_dup 2))] | |
1864 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1865 | |
9db1d521 HP |
1866 | ; |
1867 | ; movqi instruction pattern(s). | |
1868 | ; | |
1869 | ||
02ed3c5e UW |
1870 | (define_expand "movqi" |
1871 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1872 | (match_operand:QI 1 "general_operand" ""))] | |
1873 | "" | |
1874 | { | |
c19ec8f9 | 1875 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1876 | is just as fast as a QImode load. */ |
b3a13419 | 1877 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 1878 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1879 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1880 | { |
9602b6a1 AK |
1881 | rtx tmp = gen_reg_rtx (DImode); |
1882 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
02ed3c5e UW |
1883 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1884 | operands[1] = gen_lowpart (QImode, tmp); | |
1885 | } | |
1886 | }) | |
4023fb28 | 1887 | |
02ed3c5e | 1888 | (define_insn "*movqi" |
0a88561f AK |
1889 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1890 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1891 | "" |
1892 | "@ | |
d40c829f UW |
1893 | lr\t%0,%1 |
1894 | lhi\t%0,%b1 | |
1895 | ic\t%0,%1 | |
1896 | icy\t%0,%1 | |
1897 | stc\t%1,%0 | |
1898 | stcy\t%1,%0 | |
fc0ea003 | 1899 | mvi\t%S0,%b1 |
0a88561f | 1900 | mviy\t%S0,%b1 |
b247e88a | 1901 | #" |
0a88561f AK |
1902 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1903 | (set_attr "type" "lr,*,*,*,store,store,store,store,*") | |
9381e3f1 WG |
1904 | (set_attr "z10prop" "z10_fr_E1, |
1905 | z10_fwd_A1, | |
1906 | z10_super_E1, | |
1907 | z10_super_E1, | |
729e750f | 1908 | z10_rec, |
9381e3f1 WG |
1909 | z10_rec, |
1910 | z10_super, | |
0a88561f AK |
1911 | z10_super, |
1912 | *")]) | |
9db1d521 | 1913 | |
84817c5d UW |
1914 | (define_peephole2 |
1915 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1916 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1917 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1918 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1919 | && get_pool_mode (operands[1]) == QImode | |
1920 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1921 | [(set (match_dup 0) (match_dup 2))] | |
1922 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1923 | |
9db1d521 | 1924 | ; |
05b9aaaa | 1925 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1926 | ; |
1927 | ||
1928 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1929 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1930 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1931 | "" |
d3632d41 | 1932 | "@ |
d40c829f UW |
1933 | ic\t%0,%1 |
1934 | icy\t%0,%1" | |
9381e3f1 | 1935 | [(set_attr "op_type" "RX,RXY") |
729e750f | 1936 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
1937 | |
1938 | ; | |
1939 | ; movstricthi instruction pattern(s). | |
1940 | ; | |
1941 | ||
1942 | (define_insn "*movstricthi" | |
d3632d41 | 1943 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1944 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1945 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1946 | "" |
d3632d41 | 1947 | "@ |
fc0ea003 UW |
1948 | icm\t%0,3,%S1 |
1949 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
1950 | [(set_attr "op_type" "RS,RSY") |
1951 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
1952 | |
1953 | ; | |
1954 | ; movstrictsi instruction pattern(s). | |
1955 | ; | |
1956 | ||
05b9aaaa | 1957 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1958 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1959 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 1960 | "TARGET_ZARCH" |
9db1d521 | 1961 | "@ |
d40c829f UW |
1962 | lr\t%0,%1 |
1963 | l\t%0,%1 | |
c5aa1d12 UW |
1964 | ly\t%0,%1 |
1965 | ear\t%0,%1" | |
1966 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
1967 | (set_attr "type" "lr,load,load,*") |
1968 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 1969 | |
f61a2c7d | 1970 | ; |
609e7e80 | 1971 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
1972 | ; |
1973 | ||
609e7e80 AK |
1974 | (define_expand "mov<mode>" |
1975 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
1976 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
1977 | "" |
1978 | "") | |
1979 | ||
609e7e80 | 1980 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
1981 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
1982 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 1983 | "TARGET_ZARCH" |
f61a2c7d | 1984 | "@ |
65b1d8ea | 1985 | lzxr\t%0 |
f61a2c7d AK |
1986 | lxr\t%0,%1 |
1987 | # | |
1988 | # | |
1989 | lmg\t%0,%N0,%S1 | |
1990 | stmg\t%1,%N1,%S0 | |
1991 | # | |
f61a2c7d | 1992 | #" |
65b1d8ea AK |
1993 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
1994 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
1995 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 1996 | |
609e7e80 | 1997 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
1998 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
1999 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2000 | "!TARGET_ZARCH" |
f61a2c7d | 2001 | "@ |
65b1d8ea | 2002 | lzxr\t%0 |
f61a2c7d AK |
2003 | lxr\t%0,%1 |
2004 | # | |
f61a2c7d | 2005 | #" |
65b1d8ea AK |
2006 | [(set_attr "op_type" "RRE,RRE,*,*") |
2007 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2008 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2009 | |
2010 | ; TFmode in GPRs splitters | |
2011 | ||
2012 | (define_split | |
609e7e80 AK |
2013 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2014 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2015 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2016 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2017 | [(set (match_dup 2) (match_dup 4)) |
2018 | (set (match_dup 3) (match_dup 5))] | |
2019 | { | |
609e7e80 AK |
2020 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2021 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2022 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2023 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2024 | }) |
2025 | ||
2026 | (define_split | |
609e7e80 AK |
2027 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2028 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2029 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2030 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2031 | [(set (match_dup 2) (match_dup 4)) |
2032 | (set (match_dup 3) (match_dup 5))] | |
2033 | { | |
609e7e80 AK |
2034 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2035 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2036 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2037 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2038 | }) |
2039 | ||
2040 | (define_split | |
609e7e80 AK |
2041 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2042 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2043 | "TARGET_ZARCH && reload_completed |
f61a2c7d AK |
2044 | && !FP_REG_P (operands[0]) |
2045 | && !s_operand (operands[1], VOIDmode)" | |
2046 | [(set (match_dup 0) (match_dup 1))] | |
2047 | { | |
609e7e80 | 2048 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2049 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2050 | s390_load_address (addr, XEXP (operands[1], 0)); |
2051 | operands[1] = replace_equiv_address (operands[1], addr); | |
2052 | }) | |
2053 | ||
7b6baae1 | 2054 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2055 | |
2056 | (define_split | |
609e7e80 AK |
2057 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2058 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2059 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2060 | && FP_REG_P (operands[0])" |
2061 | [(set (match_dup 2) (match_dup 4)) | |
2062 | (set (match_dup 3) (match_dup 5))] | |
2063 | { | |
609e7e80 AK |
2064 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2065 | <MODE>mode, 0); | |
2066 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2067 | <MODE>mode, 8); | |
2068 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2069 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2070 | }) |
2071 | ||
2072 | (define_split | |
609e7e80 AK |
2073 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2074 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2075 | "reload_completed && offsettable_memref_p (operands[0]) |
2076 | && FP_REG_P (operands[1])" | |
2077 | [(set (match_dup 2) (match_dup 4)) | |
2078 | (set (match_dup 3) (match_dup 5))] | |
2079 | { | |
609e7e80 AK |
2080 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2081 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2082 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2083 | <MODE>mode, 0); | |
2084 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2085 | <MODE>mode, 8); | |
f61a2c7d AK |
2086 | }) |
2087 | ||
9db1d521 | 2088 | ; |
609e7e80 | 2089 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2090 | ; |
2091 | ||
609e7e80 AK |
2092 | (define_expand "mov<mode>" |
2093 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2094 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2095 | "" |
13c025c1 | 2096 | "") |
9db1d521 | 2097 | |
609e7e80 AK |
2098 | (define_insn "*mov<mode>_64dfp" |
2099 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2100 | "=f,f,f,d,f,f,R,T,d,d, d,RT") |
609e7e80 | 2101 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2102 | " G,f,d,f,R,T,f,f,G,d,RT, d"))] |
9602b6a1 | 2103 | "TARGET_DFP" |
85dae55a | 2104 | "@ |
65b1d8ea | 2105 | lzdr\t%0 |
85dae55a AK |
2106 | ldr\t%0,%1 |
2107 | ldgr\t%0,%1 | |
2108 | lgdr\t%0,%1 | |
2109 | ld\t%0,%1 | |
2110 | ldy\t%0,%1 | |
2111 | std\t%1,%0 | |
2112 | stdy\t%1,%0 | |
45e5214c | 2113 | lghi\t%0,0 |
85dae55a AK |
2114 | lgr\t%0,%1 |
2115 | lg\t%0,%1 | |
f2dc2f86 | 2116 | stg\t%1,%0" |
65b1d8ea AK |
2117 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2118 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, | |
45e5214c | 2119 | fstoredf,fstoredf,*,lr,load,store") |
65b1d8ea AK |
2120 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") |
2121 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
85dae55a | 2122 | |
609e7e80 | 2123 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2124 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT") |
2125 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))] | |
9602b6a1 | 2126 | "TARGET_ZARCH" |
9db1d521 | 2127 | "@ |
65b1d8ea | 2128 | lzdr\t%0 |
d40c829f UW |
2129 | ldr\t%0,%1 |
2130 | ld\t%0,%1 | |
2131 | ldy\t%0,%1 | |
2132 | std\t%1,%0 | |
2133 | stdy\t%1,%0 | |
45e5214c | 2134 | lghi\t%0,0 |
d40c829f UW |
2135 | lgr\t%0,%1 |
2136 | lg\t%0,%1 | |
f2dc2f86 | 2137 | stg\t%1,%0" |
65b1d8ea AK |
2138 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2139 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2140 | fstore<mode>,fstore<mode>,*,lr,load,store") | |
2141 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") | |
2142 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")]) | |
609e7e80 AK |
2143 | |
2144 | (define_insn "*mov<mode>_31" | |
2145 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2146 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2147 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2148 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2149 | "!TARGET_ZARCH" |
9db1d521 | 2150 | "@ |
65b1d8ea | 2151 | lzdr\t%0 |
d40c829f UW |
2152 | ldr\t%0,%1 |
2153 | ld\t%0,%1 | |
2154 | ldy\t%0,%1 | |
2155 | std\t%1,%0 | |
2156 | stdy\t%1,%0 | |
fc0ea003 | 2157 | lm\t%0,%N0,%S1 |
c4d50129 | 2158 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2159 | stm\t%1,%N1,%S0 |
c4d50129 | 2160 | stmy\t%1,%N1,%S0 |
4023fb28 | 2161 | # |
19b63d8e | 2162 | #" |
65b1d8ea AK |
2163 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2164 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2165 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2166 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2167 | |
2168 | (define_split | |
609e7e80 AK |
2169 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2170 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2171 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2172 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2173 | [(set (match_dup 2) (match_dup 4)) |
2174 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2175 | { |
609e7e80 AK |
2176 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2177 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2178 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2179 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2180 | }) |
2181 | ||
2182 | (define_split | |
609e7e80 AK |
2183 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2184 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2185 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2186 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2187 | [(set (match_dup 2) (match_dup 4)) |
2188 | (set (match_dup 3) (match_dup 5))] | |
2189 | { | |
609e7e80 AK |
2190 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2191 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2192 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2193 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2194 | }) |
9db1d521 | 2195 | |
4023fb28 | 2196 | (define_split |
609e7e80 AK |
2197 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2198 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2199 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2200 | && !FP_REG_P (operands[0]) |
4023fb28 | 2201 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2202 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2203 | { |
609e7e80 | 2204 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2205 | s390_load_address (addr, XEXP (operands[1], 0)); |
2206 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2207 | }) |
2208 | ||
9db1d521 | 2209 | ; |
609e7e80 | 2210 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2211 | ; |
2212 | ||
609e7e80 AK |
2213 | (define_insn "mov<mode>" |
2214 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
65b1d8ea | 2215 | "=f,f,f,f,R,T,d,d,d,d,R,T") |
609e7e80 | 2216 | (match_operand:SD_SF 1 "general_operand" |
65b1d8ea | 2217 | " G,f,R,T,f,f,G,d,R,T,d,d"))] |
4023fb28 | 2218 | "" |
9db1d521 | 2219 | "@ |
65b1d8ea | 2220 | lzer\t%0 |
d40c829f UW |
2221 | ler\t%0,%1 |
2222 | le\t%0,%1 | |
2223 | ley\t%0,%1 | |
2224 | ste\t%1,%0 | |
2225 | stey\t%1,%0 | |
45e5214c | 2226 | lhi\t%0,0 |
d40c829f UW |
2227 | lr\t%0,%1 |
2228 | l\t%0,%1 | |
2229 | ly\t%0,%1 | |
2230 | st\t%1,%0 | |
f2dc2f86 | 2231 | sty\t%1,%0" |
65b1d8ea AK |
2232 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY") |
2233 | (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>, | |
2234 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") | |
2235 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2236 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2237 | |
9dc62c00 AK |
2238 | ; |
2239 | ; movcc instruction pattern | |
2240 | ; | |
2241 | ||
2242 | (define_insn "movcc" | |
2243 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
2244 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
2245 | "" | |
2246 | "@ | |
2247 | lr\t%0,%1 | |
2248 | tmh\t%1,12288 | |
2249 | ipm\t%0 | |
2250 | st\t%0,%1 | |
2251 | sty\t%0,%1 | |
2252 | l\t%1,%0 | |
2253 | ly\t%1,%0" | |
8dd3b235 | 2254 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
9381e3f1 | 2255 | (set_attr "type" "lr,*,*,store,store,load,load") |
65b1d8ea AK |
2256 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3") |
2257 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) | |
9dc62c00 | 2258 | |
19b63d8e UW |
2259 | ; |
2260 | ; Block move (MVC) patterns. | |
2261 | ; | |
2262 | ||
2263 | (define_insn "*mvc" | |
2264 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2265 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2266 | (use (match_operand 2 "const_int_operand" "n"))] | |
2267 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2268 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2269 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2270 | |
0a88561f AK |
2271 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2272 | ; order to have it implemented with mvc. | |
2273 | ||
2274 | (define_split | |
2275 | [(set (match_operand:QI 0 "memory_operand" "") | |
2276 | (match_operand:QI 1 "memory_operand" ""))] | |
2277 | "reload_completed" | |
2278 | [(parallel | |
2279 | [(set (match_dup 0) (match_dup 1)) | |
2280 | (use (const_int 1))])] | |
2281 | { | |
2282 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2283 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2284 | }) | |
2285 | ||
2286 | ||
19b63d8e UW |
2287 | (define_peephole2 |
2288 | [(parallel | |
2289 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2290 | (match_operand:BLK 1 "memory_operand" "")) | |
2291 | (use (match_operand 2 "const_int_operand" ""))]) | |
2292 | (parallel | |
2293 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2294 | (match_operand:BLK 4 "memory_operand" "")) | |
2295 | (use (match_operand 5 "const_int_operand" ""))])] | |
2296 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2297 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2298 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2299 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2300 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2301 | [(parallel | |
2302 | [(set (match_dup 6) (match_dup 7)) | |
2303 | (use (match_dup 8))])] | |
2304 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2305 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2306 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2307 | ||
2308 | ||
9db1d521 HP |
2309 | ; |
2310 | ; load_multiple pattern(s). | |
2311 | ; | |
22ea6b4f UW |
2312 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2313 | ; we currently support load_multiple/store_multiple only after reload. | |
2314 | ; | |
9db1d521 HP |
2315 | |
2316 | (define_expand "load_multiple" | |
2317 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2318 | (match_operand 1 "" "")) | |
2319 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2320 | "reload_completed" |
9db1d521 | 2321 | { |
c19ec8f9 | 2322 | enum machine_mode mode; |
9db1d521 HP |
2323 | int regno; |
2324 | int count; | |
2325 | rtx from; | |
4023fb28 | 2326 | int i, off; |
9db1d521 HP |
2327 | |
2328 | /* Support only loading a constant number of fixed-point registers from | |
2329 | memory and only bother with this if more than two */ | |
2330 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2331 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2332 | || INTVAL (operands[2]) > 16 |
2333 | || GET_CODE (operands[1]) != MEM | |
2334 | || GET_CODE (operands[0]) != REG | |
2335 | || REGNO (operands[0]) >= 16) | |
2336 | FAIL; | |
2337 | ||
2338 | count = INTVAL (operands[2]); | |
2339 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2340 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2341 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2342 | FAIL; |
9db1d521 HP |
2343 | |
2344 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2345 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2346 | { |
2347 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2348 | { | |
2349 | from = XEXP (operands[1], 0); | |
2350 | off = 0; | |
2351 | } | |
2352 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2353 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2354 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2355 | { | |
2356 | from = XEXP (XEXP (operands[1], 0), 0); | |
2357 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2358 | } | |
2359 | else | |
2360 | FAIL; | |
4023fb28 UW |
2361 | } |
2362 | else | |
2363 | { | |
2364 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2365 | off = 0; | |
2366 | } | |
9db1d521 HP |
2367 | |
2368 | for (i = 0; i < count; i++) | |
2369 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
2370 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
2371 | change_address (operands[1], mode, | |
0a81f074 RS |
2372 | plus_constant (Pmode, from, |
2373 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2374 | }) |
9db1d521 HP |
2375 | |
2376 | (define_insn "*load_multiple_di" | |
2377 | [(match_parallel 0 "load_multiple_operation" | |
2378 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2379 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2380 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2381 | { |
2382 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2383 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2384 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2385 | } |
d3632d41 | 2386 | [(set_attr "op_type" "RSY") |
4023fb28 | 2387 | (set_attr "type" "lm")]) |
9db1d521 HP |
2388 | |
2389 | (define_insn "*load_multiple_si" | |
2390 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2391 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2392 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2393 | "reload_completed" |
9db1d521 HP |
2394 | { |
2395 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2396 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2397 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2398 | } |
d3632d41 | 2399 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2400 | (set_attr "type" "lm")]) |
9db1d521 HP |
2401 | |
2402 | ; | |
c7453384 | 2403 | ; store multiple pattern(s). |
9db1d521 HP |
2404 | ; |
2405 | ||
2406 | (define_expand "store_multiple" | |
2407 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2408 | (match_operand 1 "" "")) | |
2409 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2410 | "reload_completed" |
9db1d521 | 2411 | { |
c19ec8f9 | 2412 | enum machine_mode mode; |
9db1d521 HP |
2413 | int regno; |
2414 | int count; | |
2415 | rtx to; | |
4023fb28 | 2416 | int i, off; |
9db1d521 HP |
2417 | |
2418 | /* Support only storing a constant number of fixed-point registers to | |
2419 | memory and only bother with this if more than two. */ | |
2420 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2421 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2422 | || INTVAL (operands[2]) > 16 |
2423 | || GET_CODE (operands[0]) != MEM | |
2424 | || GET_CODE (operands[1]) != REG | |
2425 | || REGNO (operands[1]) >= 16) | |
2426 | FAIL; | |
2427 | ||
2428 | count = INTVAL (operands[2]); | |
2429 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2430 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2431 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2432 | FAIL; |
9db1d521 HP |
2433 | |
2434 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2435 | |
b3a13419 | 2436 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2437 | { |
2438 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2439 | { | |
2440 | to = XEXP (operands[0], 0); | |
2441 | off = 0; | |
2442 | } | |
2443 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2444 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2445 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2446 | { | |
2447 | to = XEXP (XEXP (operands[0], 0), 0); | |
2448 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2449 | } | |
2450 | else | |
2451 | FAIL; | |
4023fb28 | 2452 | } |
c7453384 | 2453 | else |
4023fb28 UW |
2454 | { |
2455 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2456 | off = 0; | |
2457 | } | |
9db1d521 HP |
2458 | |
2459 | for (i = 0; i < count; i++) | |
2460 | XVECEXP (operands[3], 0, i) | |
2461 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 | 2462 | change_address (operands[0], mode, |
0a81f074 RS |
2463 | plus_constant (Pmode, to, |
2464 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2465 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2466 | }) |
9db1d521 HP |
2467 | |
2468 | (define_insn "*store_multiple_di" | |
2469 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2470 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2471 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2472 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2473 | { |
2474 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2475 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2476 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2477 | } |
d3632d41 | 2478 | [(set_attr "op_type" "RSY") |
4023fb28 | 2479 | (set_attr "type" "stm")]) |
9db1d521 HP |
2480 | |
2481 | ||
2482 | (define_insn "*store_multiple_si" | |
2483 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2484 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2485 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2486 | "reload_completed" |
9db1d521 HP |
2487 | { |
2488 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2489 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2490 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2491 | } |
d3632d41 | 2492 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2493 | (set_attr "type" "stm")]) |
9db1d521 HP |
2494 | |
2495 | ;; | |
2496 | ;; String instructions. | |
2497 | ;; | |
2498 | ||
963fc8d0 | 2499 | (define_insn "*execute_rl" |
2771c2f9 | 2500 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2501 | [(unspec [(match_operand 1 "register_operand" "a") |
2502 | (match_operand 2 "" "") | |
2503 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2504 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2505 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2506 | "exrl\t%1,%3" | |
2507 | [(set_attr "op_type" "RIL") | |
2508 | (set_attr "type" "cs")]) | |
2509 | ||
9bb86f41 | 2510 | (define_insn "*execute" |
2771c2f9 | 2511 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2512 | [(unspec [(match_operand 1 "register_operand" "a") |
2513 | (match_operand:BLK 2 "memory_operand" "R") | |
2514 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2515 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2516 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2517 | "ex\t%1,%2" | |
29a74354 UW |
2518 | [(set_attr "op_type" "RX") |
2519 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2520 | |
2521 | ||
91d39d71 UW |
2522 | ; |
2523 | ; strlenM instruction pattern(s). | |
2524 | ; | |
2525 | ||
9db2f16d | 2526 | (define_expand "strlen<mode>" |
ccbdc0d4 | 2527 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2528 | (parallel |
91d39d71 | 2529 | [(set (match_dup 4) |
9db2f16d | 2530 | (unspec:P [(const_int 0) |
91d39d71 | 2531 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2532 | (reg:SI 0) |
91d39d71 | 2533 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2534 | (clobber (scratch:P)) |
ae156f85 | 2535 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2536 | (parallel |
9db2f16d AS |
2537 | [(set (match_operand:P 0 "register_operand" "") |
2538 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2539 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2540 | "" |
91d39d71 | 2541 | { |
9db2f16d AS |
2542 | operands[4] = gen_reg_rtx (Pmode); |
2543 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2544 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2545 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2546 | }) | |
2547 | ||
9db2f16d AS |
2548 | (define_insn "*strlen<mode>" |
2549 | [(set (match_operand:P 0 "register_operand" "=a") | |
2550 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2551 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2552 | (reg:SI 0) |
91d39d71 | 2553 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2554 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2555 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2556 | "" |
91d39d71 | 2557 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2558 | [(set_attr "length" "8") |
2559 | (set_attr "type" "vs")]) | |
91d39d71 | 2560 | |
ccbdc0d4 AS |
2561 | ; |
2562 | ; cmpstrM instruction pattern(s). | |
2563 | ; | |
2564 | ||
2565 | (define_expand "cmpstrsi" | |
2566 | [(set (reg:SI 0) (const_int 0)) | |
2567 | (parallel | |
2568 | [(clobber (match_operand 3 "" "")) | |
2569 | (clobber (match_dup 4)) | |
2570 | (set (reg:CCU CC_REGNUM) | |
2571 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2572 | (match_operand:BLK 2 "memory_operand" ""))) | |
2573 | (use (reg:SI 0))]) | |
2574 | (parallel | |
2575 | [(set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 2576 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT)) |
ccbdc0d4 AS |
2577 | (clobber (reg:CC CC_REGNUM))])] |
2578 | "" | |
2579 | { | |
2580 | /* As the result of CMPINT is inverted compared to what we need, | |
2581 | we have to swap the operands. */ | |
2582 | rtx op1 = operands[2]; | |
2583 | rtx op2 = operands[1]; | |
2584 | rtx addr1 = gen_reg_rtx (Pmode); | |
2585 | rtx addr2 = gen_reg_rtx (Pmode); | |
2586 | ||
2587 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2588 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2589 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2590 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2591 | operands[3] = addr1; | |
2592 | operands[4] = addr2; | |
2593 | }) | |
2594 | ||
2595 | (define_insn "*cmpstr<mode>" | |
2596 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2597 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2598 | (set (reg:CCU CC_REGNUM) | |
2599 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2600 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2601 | (use (reg:SI 0))] | |
2602 | "" | |
2603 | "clst\t%0,%1\;jo\t.-4" | |
2604 | [(set_attr "length" "8") | |
2605 | (set_attr "type" "vs")]) | |
9381e3f1 | 2606 | |
742090fc AS |
2607 | ; |
2608 | ; movstr instruction pattern. | |
2609 | ; | |
2610 | ||
2611 | (define_expand "movstr" | |
2612 | [(set (reg:SI 0) (const_int 0)) | |
9381e3f1 | 2613 | (parallel |
742090fc AS |
2614 | [(clobber (match_dup 3)) |
2615 | (set (match_operand:BLK 1 "memory_operand" "") | |
2616 | (match_operand:BLK 2 "memory_operand" "")) | |
2617 | (set (match_operand 0 "register_operand" "") | |
9381e3f1 | 2618 | (unspec [(match_dup 1) |
742090fc AS |
2619 | (match_dup 2) |
2620 | (reg:SI 0)] UNSPEC_MVST)) | |
2621 | (clobber (reg:CC CC_REGNUM))])] | |
2622 | "" | |
2623 | { | |
2624 | rtx addr1 = gen_reg_rtx (Pmode); | |
2625 | rtx addr2 = gen_reg_rtx (Pmode); | |
2626 | ||
2627 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2628 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2629 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2630 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2631 | operands[3] = addr2; | |
2632 | }) | |
2633 | ||
2634 | (define_insn "*movstr" | |
2635 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2636 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2637 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2638 | (set (match_operand:P 0 "register_operand" "=d") | |
9381e3f1 | 2639 | (unspec [(mem:BLK (match_dup 1)) |
742090fc AS |
2640 | (mem:BLK (match_dup 3)) |
2641 | (reg:SI 0)] UNSPEC_MVST)) | |
2642 | (clobber (reg:CC CC_REGNUM))] | |
2643 | "" | |
2644 | "mvst\t%1,%2\;jo\t.-4" | |
2645 | [(set_attr "length" "8") | |
2646 | (set_attr "type" "vs")]) | |
9381e3f1 | 2647 | |
742090fc | 2648 | |
9db1d521 | 2649 | ; |
70128ad9 | 2650 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2651 | ; |
2652 | ||
9db2f16d | 2653 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2654 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2655 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2656 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2657 | (match_operand 3 "" "")] |
2658 | "" | |
367d32f3 AK |
2659 | { |
2660 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
2661 | DONE; | |
2662 | else | |
2663 | FAIL; | |
2664 | }) | |
9db1d521 | 2665 | |
ecbe845e UW |
2666 | ; Move a block that is up to 256 bytes in length. |
2667 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2668 | |
70128ad9 | 2669 | (define_expand "movmem_short" |
b9404c99 UW |
2670 | [(parallel |
2671 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2672 | (match_operand:BLK 1 "memory_operand" "")) | |
2673 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2674 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2675 | (clobber (match_dup 3))])] |
2676 | "" | |
2677 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2678 | |
70128ad9 | 2679 | (define_insn "*movmem_short" |
963fc8d0 AK |
2680 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
2681 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2682 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2683 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
2684 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
2685 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 2686 | "#" |
963fc8d0 AK |
2687 | [(set_attr "type" "cs") |
2688 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
ecbe845e | 2689 | |
9bb86f41 UW |
2690 | (define_split |
2691 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2692 | (match_operand:BLK 1 "memory_operand" "")) | |
2693 | (use (match_operand 2 "const_int_operand" "")) | |
2694 | (use (match_operand 3 "immediate_operand" "")) | |
2695 | (clobber (scratch))] | |
2696 | "reload_completed" | |
2697 | [(parallel | |
2698 | [(set (match_dup 0) (match_dup 1)) | |
2699 | (use (match_dup 2))])] | |
2700 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2701 | |
9bb86f41 UW |
2702 | (define_split |
2703 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2704 | (match_operand:BLK 1 "memory_operand" "")) | |
2705 | (use (match_operand 2 "register_operand" "")) | |
2706 | (use (match_operand 3 "memory_operand" "")) | |
2707 | (clobber (scratch))] | |
2708 | "reload_completed" | |
2709 | [(parallel | |
2710 | [(unspec [(match_dup 2) (match_dup 3) | |
2711 | (const_int 0)] UNSPEC_EXECUTE) | |
2712 | (set (match_dup 0) (match_dup 1)) | |
2713 | (use (const_int 1))])] | |
2714 | "") | |
2715 | ||
963fc8d0 AK |
2716 | (define_split |
2717 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2718 | (match_operand:BLK 1 "memory_operand" "")) | |
2719 | (use (match_operand 2 "register_operand" "")) | |
2720 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2721 | (clobber (scratch))] | |
2722 | "TARGET_Z10 && reload_completed" | |
2723 | [(parallel | |
2724 | [(unspec [(match_dup 2) (const_int 0) | |
2725 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2726 | (set (match_dup 0) (match_dup 1)) | |
2727 | (use (const_int 1))])] | |
2728 | "operands[3] = gen_label_rtx ();") | |
2729 | ||
9bb86f41 UW |
2730 | (define_split |
2731 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2732 | (match_operand:BLK 1 "memory_operand" "")) | |
2733 | (use (match_operand 2 "register_operand" "")) | |
2734 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2735 | (clobber (match_operand 3 "register_operand" ""))] | |
2736 | "reload_completed && TARGET_CPU_ZARCH" | |
2737 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2738 | (parallel | |
9381e3f1 | 2739 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
2740 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
2741 | (set (match_dup 0) (match_dup 1)) | |
2742 | (use (const_int 1))])] | |
2743 | "operands[4] = gen_label_rtx ();") | |
2744 | ||
a41c6c53 | 2745 | ; Move a block of arbitrary length. |
9db1d521 | 2746 | |
70128ad9 | 2747 | (define_expand "movmem_long" |
b9404c99 UW |
2748 | [(parallel |
2749 | [(clobber (match_dup 2)) | |
2750 | (clobber (match_dup 3)) | |
2751 | (set (match_operand:BLK 0 "memory_operand" "") | |
2752 | (match_operand:BLK 1 "memory_operand" "")) | |
2753 | (use (match_operand 2 "general_operand" "")) | |
2754 | (use (match_dup 3)) | |
ae156f85 | 2755 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2756 | "" |
2757 | { | |
9602b6a1 AK |
2758 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
2759 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
2760 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
2761 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
2762 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
2763 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
2764 | rtx len0 = gen_lowpart (Pmode, reg0); |
2765 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2766 | ||
c41c1387 | 2767 | emit_clobber (reg0); |
b9404c99 UW |
2768 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2769 | emit_move_insn (len0, operands[2]); | |
2770 | ||
c41c1387 | 2771 | emit_clobber (reg1); |
b9404c99 UW |
2772 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2773 | emit_move_insn (len1, operands[2]); | |
2774 | ||
2775 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2776 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2777 | operands[2] = reg0; | |
2778 | operands[3] = reg1; | |
2779 | }) | |
2780 | ||
a1aed706 AS |
2781 | (define_insn "*movmem_long" |
2782 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2783 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2784 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2785 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2786 | (use (match_dup 2)) |
2787 | (use (match_dup 3)) | |
ae156f85 | 2788 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
2789 | "TARGET_64BIT || !TARGET_ZARCH" |
2790 | "mvcle\t%0,%1,0\;jo\t.-4" | |
2791 | [(set_attr "length" "8") | |
2792 | (set_attr "type" "vs")]) | |
2793 | ||
2794 | (define_insn "*movmem_long_31z" | |
2795 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2796 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2797 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
2798 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
2799 | (use (match_dup 2)) | |
2800 | (use (match_dup 3)) | |
2801 | (clobber (reg:CC CC_REGNUM))] | |
2802 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 2803 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2804 | [(set_attr "length" "8") |
2805 | (set_attr "type" "vs")]) | |
9db1d521 | 2806 | |
638e37c2 WG |
2807 | |
2808 | ; | |
2809 | ; Test data class. | |
2810 | ; | |
2811 | ||
0f67fa83 WG |
2812 | (define_expand "signbit<mode>2" |
2813 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2814 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2815 | (match_dup 2)] | |
0f67fa83 WG |
2816 | UNSPEC_TDC_INSN)) |
2817 | (set (match_operand:SI 0 "register_operand" "=d") | |
2818 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
2819 | "TARGET_HARD_FLOAT" | |
2820 | { | |
2821 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
2822 | }) | |
2823 | ||
638e37c2 WG |
2824 | (define_expand "isinf<mode>2" |
2825 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2826 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2827 | (match_dup 2)] | |
638e37c2 WG |
2828 | UNSPEC_TDC_INSN)) |
2829 | (set (match_operand:SI 0 "register_operand" "=d") | |
2830 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
142cd70f | 2831 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
2832 | { |
2833 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
2834 | }) | |
2835 | ||
2836 | ; This insn is used to generate all variants of the Test Data Class | |
2837 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
2838 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 2839 | ; specifying the required test(s). |
638e37c2 | 2840 | ; |
be5de7a1 | 2841 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
2842 | (define_insn "*TDC_insn_<mode>" |
2843 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 2844 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 2845 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 2846 | "TARGET_HARD_FLOAT" |
0387c142 | 2847 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 2848 | [(set_attr "op_type" "RXE") |
9381e3f1 | 2849 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 WG |
2850 | |
2851 | (define_insn_and_split "*ccz_to_int" | |
2852 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2853 | (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")] | |
2854 | UNSPEC_CCZ_TO_INT))] | |
2855 | "" | |
2856 | "#" | |
2857 | "reload_completed" | |
2858 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
2859 | ||
2860 | ||
9db1d521 | 2861 | ; |
57e84f18 | 2862 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2863 | ; |
2864 | ||
57e84f18 | 2865 | (define_expand "setmem<mode>" |
a41c6c53 | 2866 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2867 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2868 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2869 | (match_operand 3 "" "")] |
a41c6c53 | 2870 | "" |
6d057022 | 2871 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2872 | |
a41c6c53 | 2873 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2874 | ; The block length is taken as (operands[1] % 256) + 1. |
2875 | ||
70128ad9 | 2876 | (define_expand "clrmem_short" |
b9404c99 UW |
2877 | [(parallel |
2878 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2879 | (const_int 0)) | |
2880 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2881 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2882 | (clobber (match_dup 2)) |
ae156f85 | 2883 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2884 | "" |
2885 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2886 | |
70128ad9 | 2887 | (define_insn "*clrmem_short" |
963fc8d0 | 2888 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 2889 | (const_int 0)) |
963fc8d0 AK |
2890 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
2891 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 2892 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 2893 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 2894 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 2895 | "#" |
963fc8d0 AK |
2896 | [(set_attr "type" "cs") |
2897 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9bb86f41 UW |
2898 | |
2899 | (define_split | |
2900 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2901 | (const_int 0)) | |
2902 | (use (match_operand 1 "const_int_operand" "")) | |
2903 | (use (match_operand 2 "immediate_operand" "")) | |
2904 | (clobber (scratch)) | |
ae156f85 | 2905 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2906 | "reload_completed" |
2907 | [(parallel | |
2908 | [(set (match_dup 0) (const_int 0)) | |
2909 | (use (match_dup 1)) | |
ae156f85 | 2910 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2911 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2912 | |
9bb86f41 UW |
2913 | (define_split |
2914 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2915 | (const_int 0)) | |
2916 | (use (match_operand 1 "register_operand" "")) | |
2917 | (use (match_operand 2 "memory_operand" "")) | |
2918 | (clobber (scratch)) | |
ae156f85 | 2919 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2920 | "reload_completed" |
2921 | [(parallel | |
2922 | [(unspec [(match_dup 1) (match_dup 2) | |
2923 | (const_int 0)] UNSPEC_EXECUTE) | |
2924 | (set (match_dup 0) (const_int 0)) | |
2925 | (use (const_int 1)) | |
ae156f85 | 2926 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2927 | "") |
9db1d521 | 2928 | |
963fc8d0 AK |
2929 | (define_split |
2930 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2931 | (const_int 0)) | |
2932 | (use (match_operand 1 "register_operand" "")) | |
2933 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2934 | (clobber (scratch)) | |
2935 | (clobber (reg:CC CC_REGNUM))] | |
2936 | "TARGET_Z10 && reload_completed" | |
2937 | [(parallel | |
2938 | [(unspec [(match_dup 1) (const_int 0) | |
2939 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2940 | (set (match_dup 0) (const_int 0)) | |
2941 | (use (const_int 1)) | |
2942 | (clobber (reg:CC CC_REGNUM))])] | |
2943 | "operands[3] = gen_label_rtx ();") | |
2944 | ||
9bb86f41 UW |
2945 | (define_split |
2946 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2947 | (const_int 0)) | |
2948 | (use (match_operand 1 "register_operand" "")) | |
2949 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2950 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2951 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2952 | "reload_completed && TARGET_CPU_ZARCH" |
2953 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2954 | (parallel | |
9381e3f1 | 2955 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
2956 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
2957 | (set (match_dup 0) (const_int 0)) | |
2958 | (use (const_int 1)) | |
ae156f85 | 2959 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2960 | "operands[3] = gen_label_rtx ();") |
2961 | ||
9381e3f1 | 2962 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2963 | |
6d057022 | 2964 | (define_expand "setmem_long" |
b9404c99 UW |
2965 | [(parallel |
2966 | [(clobber (match_dup 1)) | |
2967 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 2968 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 2969 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2970 | (use (match_dup 3)) |
ae156f85 | 2971 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2972 | "" |
a41c6c53 | 2973 | { |
9602b6a1 AK |
2974 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
2975 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
2976 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
2977 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
2978 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 2979 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 2980 | |
c41c1387 | 2981 | emit_clobber (reg0); |
b9404c99 UW |
2982 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2983 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2984 | |
b9404c99 | 2985 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2986 | |
b9404c99 UW |
2987 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2988 | operands[1] = reg0; | |
6d057022 | 2989 | operands[3] = reg1; |
b9404c99 | 2990 | }) |
a41c6c53 | 2991 | |
6d057022 | 2992 | (define_insn "*setmem_long" |
a1aed706 | 2993 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 2994 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 2995 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 2996 | (use (match_dup 3)) |
a1aed706 | 2997 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2998 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 2999 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3000 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3001 | [(set_attr "length" "8") |
3002 | (set_attr "type" "vs")]) | |
9db1d521 | 3003 | |
4989e88a AK |
3004 | (define_insn "*setmem_long_and" |
3005 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3006 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
3007 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
3008 | (match_operand 4 "const_int_operand" "n"))) | |
3009 | (use (match_dup 3)) | |
3010 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3011 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 AK |
3012 | "(TARGET_64BIT || !TARGET_ZARCH) && |
3013 | (INTVAL (operands[4]) & 255) == 255" | |
3014 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3015 | [(set_attr "length" "8") | |
3016 | (set_attr "type" "vs")]) | |
3017 | ||
3018 | (define_insn "*setmem_long_31z" | |
3019 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3020 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
3021 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) | |
3022 | (use (match_dup 3)) | |
3023 | (use (match_operand:TI 1 "register_operand" "d")) | |
3024 | (clobber (reg:CC CC_REGNUM))] | |
3025 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3026 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3027 | [(set_attr "length" "8") | |
3028 | (set_attr "type" "vs")]) | |
9602b6a1 | 3029 | |
9db1d521 | 3030 | ; |
358b8f01 | 3031 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3032 | ; |
3033 | ||
358b8f01 | 3034 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3035 | [(set (match_operand:SI 0 "register_operand" "") |
3036 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3037 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3038 | (use (match_operand:SI 3 "general_operand" "")) | |
3039 | (use (match_operand:SI 4 "" ""))] | |
3040 | "" | |
367d32f3 AK |
3041 | { |
3042 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3043 | operands[2], operands[3])) | |
3044 | DONE; | |
3045 | else | |
3046 | FAIL; | |
3047 | }) | |
9db1d521 | 3048 | |
a41c6c53 UW |
3049 | ; Compare a block that is up to 256 bytes in length. |
3050 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3051 | |
b9404c99 UW |
3052 | (define_expand "cmpmem_short" |
3053 | [(parallel | |
ae156f85 | 3054 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3055 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3056 | (match_operand:BLK 1 "memory_operand" ""))) |
3057 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3058 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3059 | (clobber (match_dup 3))])] |
3060 | "" | |
3061 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3062 | |
b9404c99 | 3063 | (define_insn "*cmpmem_short" |
ae156f85 | 3064 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3065 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3066 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3067 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3068 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3069 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3070 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3071 | "#" |
963fc8d0 AK |
3072 | [(set_attr "type" "cs") |
3073 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9db1d521 | 3074 | |
9bb86f41 | 3075 | (define_split |
ae156f85 | 3076 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3077 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3078 | (match_operand:BLK 1 "memory_operand" ""))) | |
3079 | (use (match_operand 2 "const_int_operand" "")) | |
3080 | (use (match_operand 3 "immediate_operand" "")) | |
3081 | (clobber (scratch))] | |
3082 | "reload_completed" | |
3083 | [(parallel | |
ae156f85 | 3084 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3085 | (use (match_dup 2))])] |
3086 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3087 | |
9bb86f41 | 3088 | (define_split |
ae156f85 | 3089 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3090 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3091 | (match_operand:BLK 1 "memory_operand" ""))) | |
3092 | (use (match_operand 2 "register_operand" "")) | |
3093 | (use (match_operand 3 "memory_operand" "")) | |
3094 | (clobber (scratch))] | |
3095 | "reload_completed" | |
3096 | [(parallel | |
3097 | [(unspec [(match_dup 2) (match_dup 3) | |
3098 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3099 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3100 | (use (const_int 1))])] |
3101 | "") | |
3102 | ||
963fc8d0 AK |
3103 | (define_split |
3104 | [(set (reg:CCU CC_REGNUM) | |
3105 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3106 | (match_operand:BLK 1 "memory_operand" ""))) | |
3107 | (use (match_operand 2 "register_operand" "")) | |
3108 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3109 | (clobber (scratch))] | |
3110 | "TARGET_Z10 && reload_completed" | |
3111 | [(parallel | |
3112 | [(unspec [(match_dup 2) (const_int 0) | |
3113 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3114 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3115 | (use (const_int 1))])] | |
3116 | "operands[4] = gen_label_rtx ();") | |
3117 | ||
9bb86f41 | 3118 | (define_split |
ae156f85 | 3119 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3120 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3121 | (match_operand:BLK 1 "memory_operand" ""))) | |
3122 | (use (match_operand 2 "register_operand" "")) | |
3123 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3124 | (clobber (match_operand 3 "register_operand" ""))] | |
3125 | "reload_completed && TARGET_CPU_ZARCH" | |
3126 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3127 | (parallel | |
9381e3f1 | 3128 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3129 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3130 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3131 | (use (const_int 1))])] |
3132 | "operands[4] = gen_label_rtx ();") | |
3133 | ||
a41c6c53 | 3134 | ; Compare a block of arbitrary length. |
9db1d521 | 3135 | |
b9404c99 UW |
3136 | (define_expand "cmpmem_long" |
3137 | [(parallel | |
3138 | [(clobber (match_dup 2)) | |
3139 | (clobber (match_dup 3)) | |
ae156f85 | 3140 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3141 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3142 | (match_operand:BLK 1 "memory_operand" ""))) |
3143 | (use (match_operand 2 "general_operand" "")) | |
3144 | (use (match_dup 3))])] | |
3145 | "" | |
3146 | { | |
9602b6a1 AK |
3147 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3148 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
3149 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
3150 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3151 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3152 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3153 | rtx len0 = gen_lowpart (Pmode, reg0); |
3154 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3155 | ||
c41c1387 | 3156 | emit_clobber (reg0); |
b9404c99 UW |
3157 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3158 | emit_move_insn (len0, operands[2]); | |
3159 | ||
c41c1387 | 3160 | emit_clobber (reg1); |
b9404c99 UW |
3161 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3162 | emit_move_insn (len1, operands[2]); | |
3163 | ||
3164 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3165 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3166 | operands[2] = reg0; | |
3167 | operands[3] = reg1; | |
3168 | }) | |
3169 | ||
a1aed706 AS |
3170 | (define_insn "*cmpmem_long" |
3171 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3172 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3173 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3174 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3175 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3176 | (use (match_dup 2)) |
3177 | (use (match_dup 3))] | |
9602b6a1 | 3178 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3179 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3180 | [(set_attr "length" "8") |
3181 | (set_attr "type" "vs")]) | |
9db1d521 | 3182 | |
9602b6a1 AK |
3183 | (define_insn "*cmpmem_long_31z" |
3184 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3185 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3186 | (set (reg:CCU CC_REGNUM) | |
3187 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3188 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3189 | (use (match_dup 2)) | |
3190 | (use (match_dup 3))] | |
3191 | "!TARGET_64BIT && TARGET_ZARCH" | |
3192 | "clcle\t%0,%1,0\;jo\t.-4" | |
3193 | [(set_attr "op_type" "NN") | |
3194 | (set_attr "type" "vs") | |
3195 | (set_attr "length" "8")]) | |
3196 | ||
02887425 UW |
3197 | ; Convert CCUmode condition code to integer. |
3198 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3199 | |
02887425 | 3200 | (define_insn_and_split "cmpint" |
9db1d521 | 3201 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3202 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3203 | UNSPEC_CCU_TO_INT)) |
ae156f85 | 3204 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3205 | "" |
02887425 UW |
3206 | "#" |
3207 | "reload_completed" | |
3208 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3209 | (parallel | |
3210 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3211 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3212 | |
3213 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3214 | [(set (reg CC_REGNUM) |
02887425 | 3215 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3216 | UNSPEC_CCU_TO_INT) |
02887425 UW |
3217 | (const_int 0))) |
3218 | (set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 3219 | (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))] |
02887425 UW |
3220 | "s390_match_ccmode (insn, CCSmode)" |
3221 | "#" | |
3222 | "&& reload_completed" | |
3223 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3224 | (parallel | |
3225 | [(set (match_dup 2) (match_dup 3)) | |
3226 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3227 | { |
02887425 UW |
3228 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3229 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3230 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3231 | }) | |
9db1d521 | 3232 | |
02887425 | 3233 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3234 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3235 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3236 | UNSPEC_CCU_TO_INT))) |
ae156f85 | 3237 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3238 | "TARGET_ZARCH" |
02887425 UW |
3239 | "#" |
3240 | "&& reload_completed" | |
3241 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3242 | (parallel | |
3243 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3244 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3245 | |
3246 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3247 | [(set (reg CC_REGNUM) |
9381e3f1 | 3248 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3249 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3250 | UNSPEC_CCU_TO_INT) 0) |
02887425 UW |
3251 | (const_int 32)) (const_int 32)) |
3252 | (const_int 0))) | |
3253 | (set (match_operand:DI 0 "register_operand" "=d") | |
638e37c2 | 3254 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] |
9602b6a1 | 3255 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3256 | "#" |
3257 | "&& reload_completed" | |
3258 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3259 | (parallel | |
3260 | [(set (match_dup 2) (match_dup 3)) | |
3261 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3262 | { |
02887425 UW |
3263 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3264 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3265 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3266 | }) | |
9db1d521 | 3267 | |
4023fb28 | 3268 | |
9db1d521 HP |
3269 | ;; |
3270 | ;;- Conversion instructions. | |
3271 | ;; | |
3272 | ||
6fa05db6 | 3273 | (define_insn "*sethighpartsi" |
d3632d41 | 3274 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3275 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3276 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3277 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3278 | "" |
d3632d41 | 3279 | "@ |
6fa05db6 AS |
3280 | icm\t%0,%2,%S1 |
3281 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3282 | [(set_attr "op_type" "RS,RSY") |
3283 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3284 | |
6fa05db6 | 3285 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3286 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3287 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3288 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3289 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3290 | "TARGET_ZARCH" |
6fa05db6 | 3291 | "icmh\t%0,%2,%S1" |
729e750f WG |
3292 | [(set_attr "op_type" "RSY") |
3293 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3294 | |
6fa05db6 | 3295 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3296 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3297 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3298 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3299 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3300 | "!TARGET_ZARCH" |
d3632d41 | 3301 | "@ |
6fa05db6 AS |
3302 | icm\t%0,%2,%S1 |
3303 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3304 | [(set_attr "op_type" "RS,RSY") |
3305 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3306 | ||
4023fb28 | 3307 | |
6fa05db6 AS |
3308 | (define_insn_and_split "*extzv<mode>" |
3309 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3310 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3311 | (match_operand 2 "const_int_operand" "n") | |
3312 | (const_int 0))) | |
ae156f85 | 3313 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3314 | "INTVAL (operands[2]) > 0 |
3315 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3316 | "#" |
3317 | "&& reload_completed" | |
4023fb28 | 3318 | [(parallel |
6fa05db6 | 3319 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3320 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3321 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3322 | { |
6fa05db6 AS |
3323 | int bitsize = INTVAL (operands[2]); |
3324 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3325 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3326 | ||
3327 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3328 | set_mem_size (operands[1], size); |
6fa05db6 AS |
3329 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); |
3330 | operands[3] = GEN_INT (mask); | |
b628bd8e | 3331 | }) |
4023fb28 | 3332 | |
6fa05db6 AS |
3333 | (define_insn_and_split "*extv<mode>" |
3334 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3335 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3336 | (match_operand 2 "const_int_operand" "n") | |
3337 | (const_int 0))) | |
ae156f85 | 3338 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3339 | "INTVAL (operands[2]) > 0 |
3340 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3341 | "#" |
3342 | "&& reload_completed" | |
4023fb28 | 3343 | [(parallel |
6fa05db6 | 3344 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3345 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3346 | (parallel |
3347 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3348 | (clobber (reg:CC CC_REGNUM))])] | |
3349 | { | |
3350 | int bitsize = INTVAL (operands[2]); | |
3351 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3352 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3353 | ||
3354 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3355 | set_mem_size (operands[1], size); |
6fa05db6 AS |
3356 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); |
3357 | operands[3] = GEN_INT (mask); | |
3358 | }) | |
3359 | ||
3360 | ; | |
3361 | ; insv instruction patterns | |
3362 | ; | |
3363 | ||
3364 | (define_expand "insv" | |
3365 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3366 | (match_operand 1 "const_int_operand" "") | |
3367 | (match_operand 2 "const_int_operand" "")) | |
3368 | (match_operand 3 "general_operand" ""))] | |
3369 | "" | |
4023fb28 | 3370 | { |
6fa05db6 AS |
3371 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3372 | DONE; | |
3373 | FAIL; | |
b628bd8e | 3374 | }) |
4023fb28 | 3375 | |
22ac2c2f AK |
3376 | (define_insn "*insv<mode>_zEC12" |
3377 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
3378 | (match_operand 1 "const_int_operand" "I") | |
3379 | (match_operand 2 "const_int_operand" "I")) | |
3380 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] | |
3381 | "TARGET_ZEC12 | |
3382 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= | |
3383 | GET_MODE_BITSIZE (<MODE>mode)" | |
3384 | { | |
3385 | int start = INTVAL (operands[2]); | |
3386 | int size = INTVAL (operands[1]); | |
3387 | int offset = 64 - GET_MODE_BITSIZE (<MODE>mode); | |
3388 | ||
3389 | operands[2] = GEN_INT (offset + start); /* start bit position */ | |
3390 | operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ | |
3391 | operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - | |
3392 | start - size); /* left shift count */ | |
3393 | ||
3394 | return "risbgn\t%0,%3,%b2,%b1,%b4"; | |
3395 | } | |
3396 | [(set_attr "op_type" "RIE")]) | |
3397 | ||
963fc8d0 AK |
3398 | (define_insn "*insv<mode>_z10" |
3399 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
3400 | (match_operand 1 "const_int_operand" "I") | |
3401 | (match_operand 2 "const_int_operand" "I")) | |
3402 | (match_operand:GPR 3 "nonimmediate_operand" "d")) | |
3403 | (clobber (reg:CC CC_REGNUM))] | |
3404 | "TARGET_Z10 | |
3405 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= | |
3406 | GET_MODE_BITSIZE (<MODE>mode)" | |
3407 | { | |
3408 | int start = INTVAL (operands[2]); | |
3409 | int size = INTVAL (operands[1]); | |
3410 | int offset = 64 - GET_MODE_BITSIZE (<MODE>mode); | |
3411 | ||
3412 | operands[2] = GEN_INT (offset + start); /* start bit position */ | |
3413 | operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ | |
3414 | operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - | |
3415 | start - size); /* left shift count */ | |
3416 | ||
3417 | return "risbg\t%0,%3,%b2,%b1,%b4"; | |
3418 | } | |
9381e3f1 WG |
3419 | [(set_attr "op_type" "RIE") |
3420 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3421 | |
22ac2c2f AK |
3422 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3423 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3424 | (define_insn "*insv<mode>_zEC12_noshift" | |
3425 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3426 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3427 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
22ac2c2f | 3428 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 RH |
3429 | (match_operand:GPR 4 "const_int_operand" ""))))] |
3430 | "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3431 | "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
22ac2c2f AK |
3432 | [(set_attr "op_type" "RIE")]) |
3433 | ||
963fc8d0 AK |
3434 | (define_insn "*insv<mode>_z10_noshift" |
3435 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3436 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3437 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
963fc8d0 | 3438 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 | 3439 | (match_operand:GPR 4 "const_int_operand" "")))) |
963fc8d0 | 3440 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 RH |
3441 | "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3442 | "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
9381e3f1 WG |
3443 | [(set_attr "op_type" "RIE") |
3444 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3445 | |
3446 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3447 | (define_insn "*insv<mode>_or_z10_noshift" | |
3448 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3449 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3450 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
963fc8d0 AK |
3451 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) |
3452 | (clobber (reg:CC CC_REGNUM))] | |
75ca1b39 RH |
3453 | "TARGET_Z10" |
3454 | "rosbg\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
963fc8d0 AK |
3455 | [(set_attr "op_type" "RIE")]) |
3456 | ||
6fa05db6 | 3457 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 3458 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
3459 | (match_operand 1 "const_int_operand" "n,n") |
3460 | (const_int 0)) | |
9602b6a1 | 3461 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
3462 | "INTVAL (operands[1]) > 0 |
3463 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3464 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3465 | { | |
3466 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3467 | ||
3468 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 3469 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
3470 | : "stcmy\t%2,%1,%S0"; |
3471 | } | |
9381e3f1 WG |
3472 | [(set_attr "op_type" "RS,RSY") |
3473 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
3474 | |
3475 | (define_insn "*insvdi_mem_reghigh" | |
3476 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3477 | (match_operand 1 "const_int_operand" "n") | |
3478 | (const_int 0)) | |
3479 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3480 | (const_int 32)))] | |
9602b6a1 | 3481 | "TARGET_ZARCH |
6fa05db6 AS |
3482 | && INTVAL (operands[1]) > 0 |
3483 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3484 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3485 | { | |
3486 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3487 | ||
3488 | operands[1] = GEN_INT ((1ul << size) - 1); | |
3489 | return "stcmh\t%2,%1,%S0"; | |
3490 | } | |
9381e3f1 WG |
3491 | [(set_attr "op_type" "RSY") |
3492 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 3493 | |
9602b6a1 AK |
3494 | (define_insn "*insvdi_reg_imm" |
3495 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3496 | (const_int 16) | |
3497 | (match_operand 1 "const_int_operand" "n")) | |
3498 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
3499 | "TARGET_ZARCH |
3500 | && INTVAL (operands[1]) >= 0 | |
3501 | && INTVAL (operands[1]) < BITS_PER_WORD | |
3502 | && INTVAL (operands[1]) % 16 == 0" | |
3503 | { | |
3504 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3505 | { | |
3506 | case 64: return "iihh\t%0,%x2"; break; | |
3507 | case 48: return "iihl\t%0,%x2"; break; | |
3508 | case 32: return "iilh\t%0,%x2"; break; | |
3509 | case 16: return "iill\t%0,%x2"; break; | |
3510 | default: gcc_unreachable(); | |
3511 | } | |
3512 | } | |
9381e3f1 WG |
3513 | [(set_attr "op_type" "RI") |
3514 | (set_attr "z10prop" "z10_super_E1")]) | |
3515 | ||
9fec758d WG |
3516 | ; Update the left-most 32 bit of a DI. |
3517 | (define_insn "*insv_h_di_reg_extimm" | |
3518 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3519 | (const_int 32) | |
3520 | (const_int 0)) | |
3521 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3522 | "TARGET_EXTIMM" | |
3523 | "iihf\t%0,%o1" | |
3524 | [(set_attr "op_type" "RIL") | |
3525 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 3526 | |
d378b983 RH |
3527 | ; Update the right-most 32 bit of a DI. |
3528 | (define_insn "*insv_l_di_reg_extimm" | |
3529 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3530 | (const_int 32) | |
3531 | (const_int 32)) | |
3532 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3533 | "TARGET_EXTIMM" | |
3534 | "iilf\t%0,%o1" | |
9381e3f1 | 3535 | [(set_attr "op_type" "RIL") |
9fec758d | 3536 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 3537 | |
9db1d521 HP |
3538 | ; |
3539 | ; extendsidi2 instruction pattern(s). | |
3540 | ; | |
3541 | ||
4023fb28 UW |
3542 | (define_expand "extendsidi2" |
3543 | [(set (match_operand:DI 0 "register_operand" "") | |
3544 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3545 | "" | |
4023fb28 | 3546 | { |
9602b6a1 | 3547 | if (!TARGET_ZARCH) |
4023fb28 | 3548 | { |
c41c1387 | 3549 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3550 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
3551 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
3552 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
3553 | DONE; |
3554 | } | |
ec24698e | 3555 | }) |
4023fb28 UW |
3556 | |
3557 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
3558 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3559 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3560 | "TARGET_ZARCH" |
9db1d521 | 3561 | "@ |
d40c829f | 3562 | lgfr\t%0,%1 |
963fc8d0 AK |
3563 | lgf\t%0,%1 |
3564 | lgfrl\t%0,%1" | |
3565 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3566 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3567 | (set_attr "cpu_facility" "*,*,z10") |
3568 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3569 | |
9db1d521 | 3570 | ; |
56477c21 | 3571 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3572 | ; |
3573 | ||
56477c21 AS |
3574 | (define_expand "extend<HQI:mode><DSI:mode>2" |
3575 | [(set (match_operand:DSI 0 "register_operand" "") | |
3576 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 3577 | "" |
4023fb28 | 3578 | { |
9602b6a1 | 3579 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
3580 | { |
3581 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 3582 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
3583 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
3584 | DONE; | |
3585 | } | |
ec24698e | 3586 | else if (!TARGET_EXTIMM) |
4023fb28 | 3587 | { |
56477c21 AS |
3588 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - |
3589 | GET_MODE_BITSIZE (<HQI:MODE>mode)); | |
3590 | ||
3591 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
3592 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
3593 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
3594 | DONE; |
3595 | } | |
ec24698e UW |
3596 | }) |
3597 | ||
56477c21 AS |
3598 | ; |
3599 | ; extendhidi2 instruction pattern(s). | |
3600 | ; | |
3601 | ||
ec24698e | 3602 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
3603 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3604 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 3605 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
3606 | "@ |
3607 | lghr\t%0,%1 | |
963fc8d0 AK |
3608 | lgh\t%0,%1 |
3609 | lghrl\t%0,%1" | |
3610 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3611 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3612 | (set_attr "cpu_facility" "extimm,extimm,z10") |
3613 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
3614 | |
3615 | (define_insn "*extendhidi2" | |
9db1d521 | 3616 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 3617 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 3618 | "TARGET_ZARCH" |
d40c829f | 3619 | "lgh\t%0,%1" |
9381e3f1 WG |
3620 | [(set_attr "op_type" "RXY") |
3621 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 3622 | |
9db1d521 | 3623 | ; |
56477c21 | 3624 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
3625 | ; |
3626 | ||
ec24698e | 3627 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
3628 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3629 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
3630 | "TARGET_EXTIMM" |
3631 | "@ | |
3632 | lhr\t%0,%1 | |
3633 | lh\t%0,%1 | |
963fc8d0 AK |
3634 | lhy\t%0,%1 |
3635 | lhrl\t%0,%1" | |
3636 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
3637 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
3638 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
3639 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3640 | |
4023fb28 | 3641 | (define_insn "*extendhisi2" |
d3632d41 UW |
3642 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3643 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 3644 | "!TARGET_EXTIMM" |
d3632d41 | 3645 | "@ |
d40c829f UW |
3646 | lh\t%0,%1 |
3647 | lhy\t%0,%1" | |
9381e3f1 WG |
3648 | [(set_attr "op_type" "RX,RXY") |
3649 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3650 | |
56477c21 AS |
3651 | ; |
3652 | ; extendqi(si|di)2 instruction pattern(s). | |
3653 | ; | |
3654 | ||
43a09b63 | 3655 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
3656 | (define_insn "*extendqi<mode>2_extimm" |
3657 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3658 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3659 | "TARGET_EXTIMM" |
3660 | "@ | |
56477c21 AS |
3661 | l<g>br\t%0,%1 |
3662 | l<g>b\t%0,%1" | |
9381e3f1 WG |
3663 | [(set_attr "op_type" "RRE,RXY") |
3664 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 3665 | |
43a09b63 | 3666 | ; lb, lgb |
56477c21 AS |
3667 | (define_insn "*extendqi<mode>2" |
3668 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3669 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
3670 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
3671 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
3672 | [(set_attr "op_type" "RXY") |
3673 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 3674 | |
56477c21 AS |
3675 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
3676 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3677 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 3678 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 3679 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
3680 | "#" |
3681 | "&& reload_completed" | |
4023fb28 | 3682 | [(parallel |
56477c21 | 3683 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 3684 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 3685 | (parallel |
56477c21 | 3686 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 3687 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
3688 | { |
3689 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3690 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
56477c21 AS |
3691 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) |
3692 | - GET_MODE_BITSIZE (QImode)); | |
6fa05db6 | 3693 | }) |
9db1d521 | 3694 | |
9db1d521 HP |
3695 | ; |
3696 | ; zero_extendsidi2 instruction pattern(s). | |
3697 | ; | |
3698 | ||
4023fb28 UW |
3699 | (define_expand "zero_extendsidi2" |
3700 | [(set (match_operand:DI 0 "register_operand" "") | |
3701 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3702 | "" | |
4023fb28 | 3703 | { |
9602b6a1 | 3704 | if (!TARGET_ZARCH) |
4023fb28 | 3705 | { |
c41c1387 | 3706 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3707 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
3708 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
3709 | DONE; |
3710 | } | |
ec24698e | 3711 | }) |
4023fb28 UW |
3712 | |
3713 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
3714 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3715 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3716 | "TARGET_ZARCH" |
9db1d521 | 3717 | "@ |
d40c829f | 3718 | llgfr\t%0,%1 |
963fc8d0 AK |
3719 | llgf\t%0,%1 |
3720 | llgfrl\t%0,%1" | |
3721 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3722 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3723 | (set_attr "cpu_facility" "*,*,z10") |
3724 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 3725 | |
288e517f AK |
3726 | ; |
3727 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
3728 | ; | |
3729 | ||
d6083c7d UW |
3730 | (define_insn "*llgt_sidi" |
3731 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3732 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3733 | (const_int 2147483647)))] |
9602b6a1 | 3734 | "TARGET_ZARCH" |
d6083c7d | 3735 | "llgt\t%0,%1" |
9381e3f1 WG |
3736 | [(set_attr "op_type" "RXE") |
3737 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
3738 | |
3739 | (define_insn_and_split "*llgt_sidi_split" | |
3740 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3741 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3742 | (const_int 2147483647))) |
ae156f85 | 3743 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3744 | "TARGET_ZARCH" |
d6083c7d UW |
3745 | "#" |
3746 | "&& reload_completed" | |
3747 | [(set (match_dup 0) | |
3748 | (and:DI (subreg:DI (match_dup 1) 0) | |
3749 | (const_int 2147483647)))] | |
3750 | "") | |
3751 | ||
288e517f AK |
3752 | (define_insn "*llgt_sisi" |
3753 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 3754 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 3755 | (const_int 2147483647)))] |
c4d50129 | 3756 | "TARGET_ZARCH" |
288e517f AK |
3757 | "@ |
3758 | llgtr\t%0,%1 | |
3759 | llgt\t%0,%1" | |
9381e3f1 WG |
3760 | [(set_attr "op_type" "RRE,RXE") |
3761 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3762 | |
288e517f AK |
3763 | (define_insn "*llgt_didi" |
3764 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3765 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
3766 | (const_int 2147483647)))] | |
9602b6a1 | 3767 | "TARGET_ZARCH" |
288e517f AK |
3768 | "@ |
3769 | llgtr\t%0,%1 | |
3770 | llgt\t%0,%N1" | |
9381e3f1 WG |
3771 | [(set_attr "op_type" "RRE,RXE") |
3772 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3773 | |
f19a9af7 | 3774 | (define_split |
9602b6a1 AK |
3775 | [(set (match_operand:DSI 0 "register_operand" "") |
3776 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 3777 | (const_int 2147483647))) |
ae156f85 | 3778 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 3779 | "TARGET_ZARCH && reload_completed" |
288e517f | 3780 | [(set (match_dup 0) |
9602b6a1 | 3781 | (and:DSI (match_dup 1) |
f6ee577c | 3782 | (const_int 2147483647)))] |
288e517f AK |
3783 | "") |
3784 | ||
9db1d521 | 3785 | ; |
56477c21 | 3786 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3787 | ; |
3788 | ||
56477c21 AS |
3789 | (define_expand "zero_extend<mode>di2" |
3790 | [(set (match_operand:DI 0 "register_operand" "") | |
3791 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3792 | "" | |
3793 | { | |
9602b6a1 | 3794 | if (!TARGET_ZARCH) |
56477c21 AS |
3795 | { |
3796 | rtx tmp = gen_reg_rtx (SImode); | |
3797 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3798 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3799 | DONE; | |
3800 | } | |
3801 | else if (!TARGET_EXTIMM) | |
3802 | { | |
9381e3f1 | 3803 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - |
56477c21 AS |
3804 | GET_MODE_BITSIZE(<MODE>mode)); |
3805 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3806 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
3807 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
3808 | DONE; | |
3809 | } | |
3810 | }) | |
3811 | ||
f6ee577c | 3812 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 3813 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 3814 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 3815 | "" |
4023fb28 | 3816 | { |
ec24698e UW |
3817 | if (!TARGET_EXTIMM) |
3818 | { | |
3819 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 3820 | emit_insn (gen_andsi3 (operands[0], operands[1], |
ec24698e UW |
3821 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); |
3822 | DONE; | |
56477c21 | 3823 | } |
ec24698e UW |
3824 | }) |
3825 | ||
963fc8d0 AK |
3826 | ; llhrl, llghrl |
3827 | (define_insn "*zero_extendhi<mode>2_z10" | |
3828 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3829 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
3830 | "TARGET_Z10" | |
3831 | "@ | |
3832 | ll<g>hr\t%0,%1 | |
3833 | ll<g>h\t%0,%1 | |
3834 | ll<g>hrl\t%0,%1" | |
3835 | [(set_attr "op_type" "RXY,RRE,RIL") | |
3836 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 3837 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 3838 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 3839 | |
43a09b63 | 3840 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
3841 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
3842 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3843 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3844 | "TARGET_EXTIMM" |
3845 | "@ | |
56477c21 AS |
3846 | ll<g><hc>r\t%0,%1 |
3847 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
3848 | [(set_attr "op_type" "RRE,RXY") |
3849 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 3850 | |
43a09b63 | 3851 | ; llgh, llgc |
56477c21 AS |
3852 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
3853 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3854 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 3855 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 3856 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
3857 | [(set_attr "op_type" "RXY") |
3858 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
3859 | |
3860 | (define_insn_and_split "*zero_extendhisi2_31" | |
3861 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 3862 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 3863 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 3864 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3865 | "#" |
3866 | "&& reload_completed" | |
3867 | [(set (match_dup 0) (const_int 0)) | |
3868 | (parallel | |
3869 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 3870 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 3871 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 3872 | |
cc7ab9b7 UW |
3873 | (define_insn_and_split "*zero_extendqisi2_31" |
3874 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 3875 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3876 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3877 | "#" |
3878 | "&& reload_completed" | |
3879 | [(set (match_dup 0) (const_int 0)) | |
3880 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3881 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 3882 | |
9db1d521 HP |
3883 | ; |
3884 | ; zero_extendqihi2 instruction pattern(s). | |
3885 | ; | |
3886 | ||
9db1d521 HP |
3887 | (define_expand "zero_extendqihi2" |
3888 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 3889 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 3890 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 3891 | { |
4023fb28 UW |
3892 | operands[1] = gen_lowpart (HImode, operands[1]); |
3893 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
3894 | DONE; | |
ec24698e | 3895 | }) |
9db1d521 | 3896 | |
4023fb28 | 3897 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 3898 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 3899 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 3900 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 3901 | "llgc\t%0,%1" |
9381e3f1 WG |
3902 | [(set_attr "op_type" "RXY") |
3903 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 3904 | |
cc7ab9b7 UW |
3905 | (define_insn_and_split "*zero_extendqihi2_31" |
3906 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 3907 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3908 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3909 | "#" |
3910 | "&& reload_completed" | |
3911 | [(set (match_dup 0) (const_int 0)) | |
3912 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3913 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 3914 | |
609e7e80 AK |
3915 | ; |
3916 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
3917 | ; | |
3918 | ||
3919 | (define_expand "fixuns_truncdddi2" | |
3920 | [(parallel | |
3921 | [(set (match_operand:DI 0 "register_operand" "") | |
3922 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
65b1d8ea AK |
3923 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) |
3924 | (clobber (reg:CC CC_REGNUM))])] | |
9381e3f1 | 3925 | |
fb068247 | 3926 | "TARGET_HARD_DFP" |
609e7e80 | 3927 | { |
65b1d8ea AK |
3928 | if (!TARGET_Z196) |
3929 | { | |
3930 | rtx label1 = gen_label_rtx (); | |
3931 | rtx label2 = gen_label_rtx (); | |
3932 | rtx temp = gen_reg_rtx (TDmode); | |
3933 | REAL_VALUE_TYPE cmp, sub; | |
3934 | ||
3935 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3936 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3937 | ||
3938 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
3939 | solution is doing the check and the subtraction in TD mode and using a | |
3940 | TD -> DI convert afterwards. */ | |
3941 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
3942 | temp = force_reg (TDmode, temp); | |
3943 | emit_cmp_and_jump_insns (temp, | |
3944 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
3945 | LT, NULL_RTX, VOIDmode, 0, label1); | |
3946 | emit_insn (gen_subtd3 (temp, temp, | |
3947 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
3948 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
3949 | emit_jump (label2); | |
3950 | ||
3951 | emit_label (label1); | |
3952 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
3953 | emit_label (label2); | |
3954 | DONE; | |
3955 | } | |
609e7e80 AK |
3956 | }) |
3957 | ||
3958 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
3959 | [(parallel |
3960 | [(set (match_operand:DI 0 "register_operand" "") | |
3961 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
3962 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) | |
3963 | (clobber (reg:CC CC_REGNUM))])] | |
3964 | ||
fb068247 | 3965 | "TARGET_HARD_DFP" |
609e7e80 | 3966 | { |
65b1d8ea AK |
3967 | if (!TARGET_Z196) |
3968 | { | |
3969 | rtx label1 = gen_label_rtx (); | |
3970 | rtx label2 = gen_label_rtx (); | |
3971 | rtx temp = gen_reg_rtx (TDmode); | |
3972 | REAL_VALUE_TYPE cmp, sub; | |
3973 | ||
3974 | operands[1] = force_reg (TDmode, operands[1]); | |
3975 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3976 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3977 | ||
3978 | emit_cmp_and_jump_insns (operands[1], | |
3979 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
3980 | LT, NULL_RTX, VOIDmode, 0, label1); | |
3981 | emit_insn (gen_subtd3 (temp, operands[1], | |
3982 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
3983 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
3984 | emit_jump (label2); | |
3985 | ||
3986 | emit_label (label1); | |
3987 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
3988 | emit_label (label2); | |
3989 | DONE; | |
3990 | } | |
609e7e80 | 3991 | }) |
cc7ab9b7 | 3992 | |
9db1d521 | 3993 | ; |
65b1d8ea | 3994 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 3995 | ; instruction pattern(s). |
9db1d521 HP |
3996 | ; |
3997 | ||
7b6baae1 | 3998 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
3999 | [(parallel |
4000 | [(set (match_operand:GPR 0 "register_operand" "") | |
4001 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4002 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4003 | (clobber (reg:CC CC_REGNUM))])] | |
142cd70f | 4004 | "TARGET_HARD_FLOAT" |
9db1d521 | 4005 | { |
65b1d8ea AK |
4006 | if (!TARGET_Z196) |
4007 | { | |
4008 | rtx label1 = gen_label_rtx (); | |
4009 | rtx label2 = gen_label_rtx (); | |
4010 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4011 | REAL_VALUE_TYPE cmp, sub; | |
4012 | ||
4013 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4014 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); | |
4015 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); | |
4016 | ||
4017 | emit_cmp_and_jump_insns (operands[1], | |
4018 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), | |
4019 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4020 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4021 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); | |
4022 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4023 | GEN_INT (7))); | |
4024 | emit_jump (label2); | |
4025 | ||
4026 | emit_label (label1); | |
4027 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4028 | operands[1], GEN_INT (5))); | |
4029 | emit_label (label2); | |
4030 | DONE; | |
4031 | } | |
10bbf137 | 4032 | }) |
9db1d521 | 4033 | |
65b1d8ea AK |
4034 | ; fixuns_trunc(td|dd)si2 expander |
4035 | (define_expand "fixuns_trunc<mode>si2" | |
4036 | [(parallel | |
4037 | [(set (match_operand:SI 0 "register_operand" "") | |
4038 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
4039 | (unspec:SI [(const_int 5)] UNSPEC_ROUND) | |
4040 | (clobber (reg:CC CC_REGNUM))])] | |
8540e6e8 | 4041 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4042 | "") |
4043 | ||
4044 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4045 | ||
4046 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr | |
4047 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4048 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
4049 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
4050 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4051 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4052 | (clobber (reg:CC CC_REGNUM))] | |
4053 | "TARGET_Z196" | |
4054 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" | |
4055 | [(set_attr "op_type" "RRF") | |
4056 | (set_attr "type" "ftoi")]) | |
4057 | ||
b60cb710 AK |
4058 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4059 | [(set (match_operand:GPR 0 "register_operand" "") | |
4060 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4061 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4062 | { |
b60cb710 AK |
4063 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
4064 | GEN_INT (5))); | |
9db1d521 | 4065 | DONE; |
10bbf137 | 4066 | }) |
9db1d521 | 4067 | |
43a09b63 | 4068 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
142cd70f | 4069 | (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
2f8f8434 | 4070 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7b6baae1 | 4071 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) |
2f8f8434 | 4072 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) |
ae156f85 | 4073 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4074 | "TARGET_HARD_FLOAT" |
7b6baae1 | 4075 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4076 | [(set_attr "op_type" "RRE") |
077dab3b | 4077 | (set_attr "type" "ftoi")]) |
9db1d521 | 4078 | |
609e7e80 AK |
4079 | |
4080 | ; | |
4081 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4082 | ; | |
4083 | ||
99cd7dd0 AK |
4084 | (define_expand "fix_trunc<mode>di2" |
4085 | [(set (match_operand:DI 0 "register_operand" "") | |
4086 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4087 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4088 | { |
4089 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4090 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
4091 | GEN_INT (9))); | |
4092 | DONE; | |
4093 | }) | |
4094 | ||
609e7e80 | 4095 | ; cgxtr, cgdtr |
99cd7dd0 | 4096 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4097 | [(set (match_operand:DI 0 "register_operand" "=d") |
4098 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4099 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4100 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4101 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4102 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4103 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4104 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4105 | |
4106 | ||
f61a2c7d AK |
4107 | ; |
4108 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4109 | ; | |
4110 | ||
4111 | (define_expand "fix_trunctf<mode>2" | |
4112 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4113 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
4114 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4115 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 4116 | "TARGET_HARD_FLOAT" |
142cd70f | 4117 | "") |
9db1d521 | 4118 | |
9db1d521 | 4119 | |
9db1d521 | 4120 | ; |
142cd70f | 4121 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4122 | ; |
4123 | ||
609e7e80 | 4124 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4125 | (define_insn "floatdi<mode>2" |
609e7e80 AK |
4126 | [(set (match_operand:FP 0 "register_operand" "=f") |
4127 | (float:FP (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 4128 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
609e7e80 | 4129 | "c<xde>g<bt>r\t%0,%1" |
9db1d521 | 4130 | [(set_attr "op_type" "RRE") |
9381e3f1 | 4131 | (set_attr "type" "itof<mode>" )]) |
9db1d521 | 4132 | |
43a09b63 | 4133 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4134 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4135 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4136 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4137 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4138 | "c<xde>fbr\t%0,%1" |
4139 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4140 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4141 | |
65b1d8ea AK |
4142 | ; cxftr, cdftr |
4143 | (define_insn "floatsi<mode>2" | |
4144 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4145 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4146 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4147 | "c<xde>ftr\t%0,0,%1,0" | |
4148 | [(set_attr "op_type" "RRE") | |
4149 | (set_attr "type" "itof<mode>" )]) | |
4150 | ||
4151 | ; | |
4152 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4153 | ; | |
4154 | ||
4155 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr | |
4156 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
4157 | (define_insn "floatuns<GPR:mode><FP:mode>2" | |
4158 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4159 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4160 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4161 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" | |
4162 | [(set_attr "op_type" "RRE") | |
4163 | (set_attr "type" "itof<FP:mode>" )]) | |
f61a2c7d | 4164 | |
9db1d521 HP |
4165 | ; |
4166 | ; truncdfsf2 instruction pattern(s). | |
4167 | ; | |
4168 | ||
142cd70f | 4169 | (define_insn "truncdfsf2" |
9db1d521 | 4170 | [(set (match_operand:SF 0 "register_operand" "=f") |
a036c6f7 | 4171 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
142cd70f | 4172 | "TARGET_HARD_FLOAT" |
d40c829f | 4173 | "ledbr\t%0,%1" |
f61a2c7d AK |
4174 | [(set_attr "op_type" "RRE") |
4175 | (set_attr "type" "ftruncdf")]) | |
9db1d521 | 4176 | |
f61a2c7d | 4177 | ; |
142cd70f | 4178 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4179 | ; |
4180 | ||
142cd70f AK |
4181 | ; ldxbr, lexbr |
4182 | (define_insn "trunctf<mode>2" | |
4183 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4184 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4185 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4186 | "TARGET_HARD_FLOAT" |
4187 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4188 | [(set_attr "length" "6") |
9381e3f1 | 4189 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4190 | |
609e7e80 AK |
4191 | ; |
4192 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4193 | ; | |
4194 | ||
4195 | (define_insn "trunctddd2" | |
4196 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
4197 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4198 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4199 | "TARGET_HARD_DFP" |
bf259a77 AK |
4200 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4201 | [(set_attr "length" "6") | |
9381e3f1 | 4202 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4203 | |
4204 | (define_insn "truncddsd2" | |
4205 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4206 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4207 | "TARGET_HARD_DFP" |
609e7e80 AK |
4208 | "ledtr\t%0,0,%1,0" |
4209 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4210 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4211 | |
9db1d521 | 4212 | ; |
142cd70f | 4213 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4214 | ; |
4215 | ||
142cd70f AK |
4216 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
4217 | (define_insn "extend<DSF:mode><BFP:mode>2" | |
4218 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
4219 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] | |
4220 | "TARGET_HARD_FLOAT | |
4221 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)" | |
f61a2c7d | 4222 | "@ |
142cd70f AK |
4223 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4224 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
f61a2c7d | 4225 | [(set_attr "op_type" "RRE,RXE") |
142cd70f | 4226 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) |
f61a2c7d | 4227 | |
609e7e80 AK |
4228 | ; |
4229 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4230 | ; | |
4231 | ||
4232 | (define_insn "extendddtd2" | |
4233 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4234 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4235 | "TARGET_HARD_DFP" |
609e7e80 AK |
4236 | "lxdtr\t%0,%1,0" |
4237 | [(set_attr "op_type" "RRF") | |
4238 | (set_attr "type" "fsimptf")]) | |
4239 | ||
4240 | (define_insn "extendsddd2" | |
4241 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4242 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4243 | "TARGET_HARD_DFP" |
609e7e80 AK |
4244 | "ldetr\t%0,%1,0" |
4245 | [(set_attr "op_type" "RRF") | |
4246 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4247 | |
35dd9a0e AK |
4248 | ; Binary <-> Decimal floating point trunc patterns |
4249 | ; | |
4250 | ||
4251 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4252 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4253 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4254 | (use (reg:SI GPR0_REGNUM)) | |
4255 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4256 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4257 | "pfpo") |
4258 | ||
4259 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4260 | [(set (reg:BFP FPR0_REGNUM) | |
4261 | (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4262 | (use (reg:SI GPR0_REGNUM)) | |
4263 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4264 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4265 | "pfpo") |
4266 | ||
4267 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
4268 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4269 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4270 | (parallel | |
4271 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4272 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4273 | (use (reg:SI GPR0_REGNUM)) | |
4274 | (clobber (reg:CC CC_REGNUM))]) | |
4275 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4276 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4277 | "TARGET_HARD_DFP |
35dd9a0e AK |
4278 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4279 | { | |
4280 | HOST_WIDE_INT flags; | |
4281 | ||
4282 | flags = (PFPO_CONVERT | | |
4283 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4284 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4285 | ||
4286 | operands[2] = GEN_INT (flags); | |
4287 | }) | |
4288 | ||
4289 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
4290 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4291 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4292 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4293 | (parallel | |
4294 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4295 | (use (reg:SI GPR0_REGNUM)) | |
4296 | (clobber (reg:CC CC_REGNUM))]) | |
4297 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4298 | "TARGET_HARD_DFP |
35dd9a0e AK |
4299 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
4300 | { | |
4301 | HOST_WIDE_INT flags; | |
4302 | ||
4303 | flags = (PFPO_CONVERT | | |
4304 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4305 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4306 | ||
4307 | operands[2] = GEN_INT (flags); | |
4308 | }) | |
4309 | ||
4310 | ; | |
4311 | ; Binary <-> Decimal floating point extend patterns | |
4312 | ; | |
4313 | ||
4314 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
4315 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4316 | (use (reg:SI GPR0_REGNUM)) | |
4317 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4318 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4319 | "pfpo") |
4320 | ||
4321 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
4322 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4323 | (use (reg:SI GPR0_REGNUM)) | |
4324 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4325 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4326 | "pfpo") |
4327 | ||
4328 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
4329 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4330 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4331 | (parallel | |
4332 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4333 | (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4334 | (use (reg:SI GPR0_REGNUM)) | |
4335 | (clobber (reg:CC CC_REGNUM))]) | |
4336 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4337 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4338 | "TARGET_HARD_DFP |
35dd9a0e AK |
4339 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4340 | { | |
4341 | HOST_WIDE_INT flags; | |
4342 | ||
4343 | flags = (PFPO_CONVERT | | |
4344 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4345 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4346 | ||
4347 | operands[2] = GEN_INT (flags); | |
4348 | }) | |
4349 | ||
4350 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
4351 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4352 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4353 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4354 | (parallel | |
4355 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4356 | (use (reg:SI GPR0_REGNUM)) | |
4357 | (clobber (reg:CC CC_REGNUM))]) | |
4358 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4359 | "TARGET_HARD_DFP |
35dd9a0e AK |
4360 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
4361 | { | |
4362 | HOST_WIDE_INT flags; | |
4363 | ||
4364 | flags = (PFPO_CONVERT | | |
4365 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4366 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4367 | ||
4368 | operands[2] = GEN_INT (flags); | |
4369 | }) | |
4370 | ||
4371 | ||
9db1d521 | 4372 | ;; |
fae778eb | 4373 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 4374 | ;; |
fae778eb | 4375 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
4376 | ; because of unpredictable Bits in Register for Halfword and Byte |
4377 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
4378 | ||
07893d4f UW |
4379 | ;; |
4380 | ;;- Add instructions. | |
4381 | ;; | |
4382 | ||
1c7b1b7e UW |
4383 | ; |
4384 | ; addti3 instruction pattern(s). | |
4385 | ; | |
4386 | ||
4387 | (define_insn_and_split "addti3" | |
4388 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4389 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
4390 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4391 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4392 | "TARGET_ZARCH" |
1c7b1b7e UW |
4393 | "#" |
4394 | "&& reload_completed" | |
4395 | [(parallel | |
ae156f85 | 4396 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
4397 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
4398 | (match_dup 7))) | |
4399 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
4400 | (parallel | |
a94a76a7 UW |
4401 | [(set (match_dup 3) (plus:DI |
4402 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4403 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4404 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
4405 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4406 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4407 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4408 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4409 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4410 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4411 | |
07893d4f UW |
4412 | ; |
4413 | ; adddi3 instruction pattern(s). | |
4414 | ; | |
4415 | ||
3298c037 AK |
4416 | (define_expand "adddi3" |
4417 | [(parallel | |
963fc8d0 | 4418 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
4419 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
4420 | (match_operand:DI 2 "general_operand" ""))) | |
4421 | (clobber (reg:CC CC_REGNUM))])] | |
4422 | "" | |
4423 | "") | |
4424 | ||
07893d4f UW |
4425 | (define_insn "*adddi3_sign" |
4426 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4427 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4428 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4429 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4430 | "TARGET_ZARCH" |
07893d4f | 4431 | "@ |
d40c829f UW |
4432 | agfr\t%0,%2 |
4433 | agf\t%0,%2" | |
65b1d8ea AK |
4434 | [(set_attr "op_type" "RRE,RXY") |
4435 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
4436 | |
4437 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 4438 | [(set (reg CC_REGNUM) |
fb492564 | 4439 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4440 | (match_operand:DI 1 "register_operand" "0,0")) |
4441 | (const_int 0))) | |
4442 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4443 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 4444 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4445 | "@ |
d40c829f UW |
4446 | algfr\t%0,%2 |
4447 | algf\t%0,%2" | |
9381e3f1 WG |
4448 | [(set_attr "op_type" "RRE,RXY") |
4449 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4450 | |
4451 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 4452 | [(set (reg CC_REGNUM) |
fb492564 | 4453 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4454 | (match_operand:DI 1 "register_operand" "0,0")) |
4455 | (const_int 0))) | |
4456 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 4457 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4458 | "@ |
d40c829f UW |
4459 | algfr\t%0,%2 |
4460 | algf\t%0,%2" | |
9381e3f1 WG |
4461 | [(set_attr "op_type" "RRE,RXY") |
4462 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4463 | |
4464 | (define_insn "*adddi3_zero" | |
4465 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4466 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4467 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4468 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4469 | "TARGET_ZARCH" |
07893d4f | 4470 | "@ |
d40c829f UW |
4471 | algfr\t%0,%2 |
4472 | algf\t%0,%2" | |
9381e3f1 WG |
4473 | [(set_attr "op_type" "RRE,RXY") |
4474 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 4475 | |
e69166de | 4476 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 4477 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
4478 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
4479 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4480 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4481 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
4482 | "#" |
4483 | "&& reload_completed" | |
4484 | [(parallel | |
ae156f85 | 4485 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
4486 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4487 | (match_dup 7))) | |
4488 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4489 | (parallel | |
a94a76a7 UW |
4490 | [(set (match_dup 3) (plus:SI |
4491 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4492 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4493 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
4494 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4495 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4496 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4497 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4498 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4499 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4500 | |
07893d4f | 4501 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 4502 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 4503 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 4504 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4505 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4506 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4507 | "#" |
4508 | "&& reload_completed" | |
4509 | [(parallel | |
4510 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4511 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4512 | (parallel |
ae156f85 | 4513 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
4514 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4515 | (match_dup 7))) | |
4516 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4517 | (set (pc) | |
ae156f85 | 4518 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4519 | (pc) |
4520 | (label_ref (match_dup 9)))) | |
4521 | (parallel | |
4522 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 4523 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4524 | (match_dup 9)] |
97c6f7ad UW |
4525 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4526 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4527 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4528 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4529 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4530 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4531 | operands[9] = gen_label_rtx ();") |
9db1d521 | 4532 | |
3298c037 AK |
4533 | ; |
4534 | ; addsi3 instruction pattern(s). | |
4535 | ; | |
4536 | ||
4537 | (define_expand "addsi3" | |
07893d4f | 4538 | [(parallel |
963fc8d0 | 4539 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
4540 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
4541 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4542 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4543 | "" |
07893d4f | 4544 | "") |
9db1d521 | 4545 | |
3298c037 AK |
4546 | (define_insn "*addsi3_sign" |
4547 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4548 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
4549 | (match_operand:SI 1 "register_operand" "0,0"))) | |
4550 | (clobber (reg:CC CC_REGNUM))] | |
4551 | "" | |
4552 | "@ | |
4553 | ah\t%0,%2 | |
4554 | ahy\t%0,%2" | |
65b1d8ea AK |
4555 | [(set_attr "op_type" "RX,RXY") |
4556 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 4557 | |
9db1d521 | 4558 | ; |
3298c037 | 4559 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 4560 | ; |
9db1d521 | 4561 | |
65b1d8ea | 4562 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 4563 | (define_insn "*add<mode>3" |
65b1d8ea AK |
4564 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
4565 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
4566 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
4567 | (clobber (reg:CC CC_REGNUM))] |
4568 | "" | |
ec24698e | 4569 | "@ |
3298c037 | 4570 | a<g>r\t%0,%2 |
65b1d8ea | 4571 | a<g>rk\t%0,%1,%2 |
3298c037 | 4572 | a<g>hi\t%0,%h2 |
65b1d8ea | 4573 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
4574 | al<g>fi\t%0,%2 |
4575 | sl<g>fi\t%0,%n2 | |
4576 | a<g>\t%0,%2 | |
963fc8d0 AK |
4577 | a<y>\t%0,%2 |
4578 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4579 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
4580 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
4581 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4582 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 4583 | |
65b1d8ea | 4584 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 4585 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 4586 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4587 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
4588 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 4589 | (match_dup 1))) |
65b1d8ea | 4590 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 4591 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4592 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4593 | "@ |
3298c037 | 4594 | al<g>r\t%0,%2 |
65b1d8ea | 4595 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4596 | al<g>fi\t%0,%2 |
4597 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4598 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4599 | al<g>\t%0,%2 |
963fc8d0 AK |
4600 | al<y>\t%0,%2 |
4601 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4602 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4603 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4604 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4605 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4606 | |
65b1d8ea | 4607 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4608 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 4609 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4610 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4611 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4612 | (match_dup 1))) |
65b1d8ea | 4613 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4614 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4615 | "@ |
3298c037 | 4616 | al<g>r\t%0,%2 |
65b1d8ea | 4617 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4618 | al<g>\t%0,%2 |
4619 | al<y>\t%0,%2" | |
65b1d8ea AK |
4620 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4621 | (set_attr "cpu_facility" "*,z196,*,*") | |
4622 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4623 | |
65b1d8ea | 4624 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4625 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 4626 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4627 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4628 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 4629 | (match_dup 2))) |
65b1d8ea | 4630 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4631 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4632 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4633 | "@ |
3298c037 | 4634 | al<g>r\t%0,%2 |
65b1d8ea | 4635 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4636 | al<g>fi\t%0,%2 |
4637 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4638 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4639 | al<g>\t%0,%2 |
963fc8d0 AK |
4640 | al<y>\t%0,%2 |
4641 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4642 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4643 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4644 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4645 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4646 | |
65b1d8ea | 4647 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4648 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 4649 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4650 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4651 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4652 | (match_dup 2))) |
65b1d8ea | 4653 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4654 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4655 | "@ |
3298c037 | 4656 | al<g>r\t%0,%2 |
65b1d8ea | 4657 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4658 | al<g>\t%0,%2 |
4659 | al<y>\t%0,%2" | |
65b1d8ea AK |
4660 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4661 | (set_attr "cpu_facility" "*,z196,*,*") | |
4662 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4663 | |
65b1d8ea | 4664 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4665 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4666 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4667 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4668 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 4669 | (const_int 0))) |
65b1d8ea | 4670 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4671 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4672 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4673 | "@ |
3298c037 | 4674 | al<g>r\t%0,%2 |
65b1d8ea | 4675 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4676 | al<g>fi\t%0,%2 |
4677 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4678 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4679 | al<g>\t%0,%2 |
963fc8d0 AK |
4680 | al<y>\t%0,%2 |
4681 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4682 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4683 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4684 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4685 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4686 | |
65b1d8ea | 4687 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4688 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4689 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4690 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4691 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 4692 | (const_int 0))) |
65b1d8ea | 4693 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4694 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4695 | "@ |
3298c037 | 4696 | al<g>r\t%0,%2 |
65b1d8ea | 4697 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4698 | al<g>\t%0,%2 |
4699 | al<y>\t%0,%2" | |
65b1d8ea AK |
4700 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4701 | (set_attr "cpu_facility" "*,z196,*,*") | |
4702 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4703 | |
65b1d8ea | 4704 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4705 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 4706 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4707 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4708 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
4709 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 4710 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 4711 | "@ |
3298c037 | 4712 | al<g>r\t%0,%2 |
65b1d8ea | 4713 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4714 | al<g>\t%0,%2 |
4715 | al<y>\t%0,%2" | |
65b1d8ea AK |
4716 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4717 | (set_attr "cpu_facility" "*,z196,*,*") | |
4718 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4719 | |
963fc8d0 | 4720 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
4721 | (define_insn "*add<mode>3_imm_cc" |
4722 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
4723 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
4724 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 4725 | (const_int 0))) |
65b1d8ea | 4726 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
4727 | (plus:GPR (match_dup 1) (match_dup 2)))] |
4728 | "s390_match_ccmode (insn, CCAmode) | |
4729 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
963fc8d0 AK |
4730 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
4731 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) | |
3298c037 | 4732 | && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" |
9db1d521 | 4733 | "@ |
3298c037 | 4734 | a<g>hi\t%0,%h2 |
65b1d8ea | 4735 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
4736 | a<g>fi\t%0,%2 |
4737 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4738 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
4739 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
4740 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4741 | |
9db1d521 | 4742 | ; |
609e7e80 | 4743 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4744 | ; |
4745 | ||
609e7e80 | 4746 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
142cd70f | 4747 | (define_insn "add<mode>3" |
609e7e80 AK |
4748 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4749 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4750 | (match_operand:FP 2 "general_operand" " f,<Rf>"))) | |
ae156f85 | 4751 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4752 | "TARGET_HARD_FLOAT" |
9db1d521 | 4753 | "@ |
609e7e80 | 4754 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4755 | a<xde>b\t%0,%2" |
609e7e80 | 4756 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4757 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4758 | |
609e7e80 | 4759 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4760 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4761 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4762 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4763 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4764 | (match_operand:FP 3 "const0_operand" ""))) | |
4765 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
4766 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 4767 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4768 | "@ |
609e7e80 | 4769 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4770 | a<xde>b\t%0,%2" |
609e7e80 | 4771 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4772 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4773 | |
609e7e80 | 4774 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4775 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4776 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4777 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4778 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4779 | (match_operand:FP 3 "const0_operand" ""))) | |
4780 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 4781 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4782 | "@ |
609e7e80 | 4783 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4784 | a<xde>b\t%0,%2" |
609e7e80 | 4785 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4786 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4787 | |
9db1d521 HP |
4788 | |
4789 | ;; | |
4790 | ;;- Subtract instructions. | |
4791 | ;; | |
4792 | ||
1c7b1b7e UW |
4793 | ; |
4794 | ; subti3 instruction pattern(s). | |
4795 | ; | |
4796 | ||
4797 | (define_insn_and_split "subti3" | |
4798 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4799 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
4800 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4801 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4802 | "TARGET_ZARCH" |
1c7b1b7e UW |
4803 | "#" |
4804 | "&& reload_completed" | |
4805 | [(parallel | |
ae156f85 | 4806 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
4807 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
4808 | (match_dup 7))) | |
4809 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
4810 | (parallel | |
4811 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4812 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4813 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
4814 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4815 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4816 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4817 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4818 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4819 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4820 | |
9db1d521 HP |
4821 | ; |
4822 | ; subdi3 instruction pattern(s). | |
4823 | ; | |
4824 | ||
3298c037 AK |
4825 | (define_expand "subdi3" |
4826 | [(parallel | |
4827 | [(set (match_operand:DI 0 "register_operand" "") | |
4828 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4829 | (match_operand:DI 2 "general_operand" ""))) | |
4830 | (clobber (reg:CC CC_REGNUM))])] | |
4831 | "" | |
4832 | "") | |
4833 | ||
07893d4f UW |
4834 | (define_insn "*subdi3_sign" |
4835 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4836 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4837 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4838 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4839 | "TARGET_ZARCH" |
07893d4f | 4840 | "@ |
d40c829f UW |
4841 | sgfr\t%0,%2 |
4842 | sgf\t%0,%2" | |
9381e3f1 | 4843 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
4844 | (set_attr "z10prop" "z10_c,*") |
4845 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
4846 | |
4847 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 4848 | [(set (reg CC_REGNUM) |
07893d4f | 4849 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4850 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4851 | (const_int 0))) |
4852 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4853 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 4854 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4855 | "@ |
d40c829f UW |
4856 | slgfr\t%0,%2 |
4857 | slgf\t%0,%2" | |
9381e3f1 WG |
4858 | [(set_attr "op_type" "RRE,RXY") |
4859 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4860 | |
4861 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 4862 | [(set (reg CC_REGNUM) |
07893d4f | 4863 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4864 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4865 | (const_int 0))) |
4866 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 4867 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4868 | "@ |
d40c829f UW |
4869 | slgfr\t%0,%2 |
4870 | slgf\t%0,%2" | |
9381e3f1 WG |
4871 | [(set_attr "op_type" "RRE,RXY") |
4872 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4873 | |
4874 | (define_insn "*subdi3_zero" | |
4875 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4876 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4877 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4878 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4879 | "TARGET_ZARCH" |
07893d4f | 4880 | "@ |
d40c829f UW |
4881 | slgfr\t%0,%2 |
4882 | slgf\t%0,%2" | |
9381e3f1 WG |
4883 | [(set_attr "op_type" "RRE,RXY") |
4884 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 4885 | |
e69166de UW |
4886 | (define_insn_and_split "*subdi3_31z" |
4887 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4888 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4889 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4890 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4891 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
4892 | "#" |
4893 | "&& reload_completed" | |
4894 | [(parallel | |
ae156f85 | 4895 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
4896 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4897 | (match_dup 7))) | |
4898 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4899 | (parallel | |
4900 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4901 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4902 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
4903 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4904 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4905 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4906 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4907 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4908 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4909 | |
07893d4f UW |
4910 | (define_insn_and_split "*subdi3_31" |
4911 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4912 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 4913 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4914 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4915 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4916 | "#" |
4917 | "&& reload_completed" | |
4918 | [(parallel | |
4919 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4920 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4921 | (parallel |
ae156f85 | 4922 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
4923 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4924 | (match_dup 7))) | |
4925 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4926 | (set (pc) | |
ae156f85 | 4927 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4928 | (pc) |
4929 | (label_ref (match_dup 9)))) | |
4930 | (parallel | |
4931 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 4932 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4933 | (match_dup 9)] |
97c6f7ad UW |
4934 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4935 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4936 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4937 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4938 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4939 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4940 | operands[9] = gen_label_rtx ();") |
07893d4f | 4941 | |
3298c037 AK |
4942 | ; |
4943 | ; subsi3 instruction pattern(s). | |
4944 | ; | |
4945 | ||
4946 | (define_expand "subsi3" | |
07893d4f | 4947 | [(parallel |
3298c037 AK |
4948 | [(set (match_operand:SI 0 "register_operand" "") |
4949 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
4950 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4951 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4952 | "" |
07893d4f | 4953 | "") |
9db1d521 | 4954 | |
3298c037 AK |
4955 | (define_insn "*subsi3_sign" |
4956 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4957 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4958 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
4959 | (clobber (reg:CC CC_REGNUM))] | |
4960 | "" | |
4961 | "@ | |
4962 | sh\t%0,%2 | |
4963 | shy\t%0,%2" | |
65b1d8ea AK |
4964 | [(set_attr "op_type" "RX,RXY") |
4965 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 4966 | |
9db1d521 | 4967 | ; |
3298c037 | 4968 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
4969 | ; |
4970 | ||
65b1d8ea | 4971 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 4972 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
4973 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
4974 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
4975 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
4976 | (clobber (reg:CC CC_REGNUM))] |
4977 | "" | |
4978 | "@ | |
4979 | s<g>r\t%0,%2 | |
65b1d8ea | 4980 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
4981 | s<g>\t%0,%2 |
4982 | s<y>\t%0,%2" | |
65b1d8ea AK |
4983 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4984 | (set_attr "cpu_facility" "*,z196,*,*") | |
4985 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 4986 | |
65b1d8ea | 4987 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 4988 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 4989 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4990 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
4991 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4992 | (match_dup 1))) |
65b1d8ea | 4993 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 4994 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4995 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4996 | "@ |
3298c037 | 4997 | sl<g>r\t%0,%2 |
65b1d8ea | 4998 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
4999 | sl<g>\t%0,%2 |
5000 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5001 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5002 | (set_attr "cpu_facility" "*,z196,*,*") | |
5003 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5004 | |
65b1d8ea | 5005 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5006 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 5007 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5008 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5009 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5010 | (match_dup 1))) |
65b1d8ea | 5011 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5012 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5013 | "@ |
3298c037 | 5014 | sl<g>r\t%0,%2 |
65b1d8ea | 5015 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5016 | sl<g>\t%0,%2 |
5017 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5018 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5019 | (set_attr "cpu_facility" "*,z196,*,*") | |
5020 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5021 | |
65b1d8ea | 5022 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5023 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5024 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5025 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5026 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5027 | (const_int 0))) |
65b1d8ea | 5028 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5029 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5030 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5031 | "@ |
3298c037 | 5032 | sl<g>r\t%0,%2 |
65b1d8ea | 5033 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5034 | sl<g>\t%0,%2 |
5035 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5036 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5037 | (set_attr "cpu_facility" "*,z196,*,*") | |
5038 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5039 | |
65b1d8ea | 5040 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5041 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5042 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5043 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5044 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5045 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5046 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5047 | "s390_match_ccmode (insn, CCL3mode)" |
5048 | "@ | |
3298c037 | 5049 | sl<g>r\t%0,%2 |
65b1d8ea | 5050 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5051 | sl<g>\t%0,%2 |
5052 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5053 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5054 | (set_attr "cpu_facility" "*,z196,*,*") | |
5055 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5056 | |
65b1d8ea | 5057 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5058 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5059 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5060 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5061 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5062 | (const_int 0))) |
65b1d8ea | 5063 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5064 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5065 | "@ |
3298c037 | 5066 | sl<g>r\t%0,%2 |
65b1d8ea | 5067 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5068 | sl<g>\t%0,%2 |
5069 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5070 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5071 | (set_attr "cpu_facility" "*,z196,*,*") | |
5072 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5073 | |
9db1d521 | 5074 | |
65b1d8ea | 5075 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5076 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5077 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5078 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5079 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5080 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5081 | "s390_match_ccmode (insn, CCL3mode)" |
5082 | "@ | |
3298c037 | 5083 | sl<g>r\t%0,%2 |
65b1d8ea | 5084 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5085 | sl<g>\t%0,%2 |
5086 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5087 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5088 | (set_attr "cpu_facility" "*,z196,*,*") | |
5089 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5090 | |
9db1d521 HP |
5091 | |
5092 | ; | |
609e7e80 | 5093 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5094 | ; |
5095 | ||
d46f24b6 | 5096 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5097 | (define_insn "sub<mode>3" |
609e7e80 AK |
5098 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
5099 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
142cd70f | 5100 | (match_operand:FP 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 5101 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5102 | "TARGET_HARD_FLOAT" |
9db1d521 | 5103 | "@ |
609e7e80 | 5104 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5105 | s<xde>b\t%0,%2" |
609e7e80 | 5106 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5107 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5108 | |
d46f24b6 | 5109 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5110 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5111 | [(set (reg CC_REGNUM) |
609e7e80 | 5112 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 5113 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
5114 | (match_operand:FP 3 "const0_operand" ""))) |
5115 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5116 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5117 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5118 | "@ |
609e7e80 | 5119 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5120 | s<xde>b\t%0,%2" |
609e7e80 | 5121 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5122 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5123 | |
d46f24b6 | 5124 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5125 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5126 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5127 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
5128 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
5129 | (match_operand:FP 3 "const0_operand" ""))) | |
5130 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5131 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5132 | "@ |
609e7e80 | 5133 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5134 | s<xde>b\t%0,%2" |
609e7e80 | 5135 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5136 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5137 | |
9db1d521 | 5138 | |
e69166de UW |
5139 | ;; |
5140 | ;;- Conditional add/subtract instructions. | |
5141 | ;; | |
5142 | ||
5143 | ; | |
9a91a21f | 5144 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
5145 | ; |
5146 | ||
a996720c UW |
5147 | ; the following 4 patterns are used when the result of an add with |
5148 | ; carry is checked for an overflow condition | |
5149 | ||
5150 | ; op1 + op2 + c < op1 | |
5151 | ||
5152 | ; alcr, alc, alcgr, alcg | |
5153 | (define_insn "*add<mode>3_alc_carry1_cc" | |
5154 | [(set (reg CC_REGNUM) | |
5155 | (compare | |
5156 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5157 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5158 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5159 | (match_dup 1))) |
5160 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5161 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5162 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5163 | "@ | |
5164 | alc<g>r\t%0,%2 | |
5165 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5166 | [(set_attr "op_type" "RRE,RXY") |
5167 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5168 | |
5169 | ; alcr, alc, alcgr, alcg | |
5170 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
5171 | [(set (reg CC_REGNUM) | |
5172 | (compare | |
5173 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5174 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5175 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5176 | (match_dup 1))) |
5177 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5178 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5179 | "@ | |
5180 | alc<g>r\t%0,%2 | |
5181 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5182 | [(set_attr "op_type" "RRE,RXY") |
5183 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5184 | |
5185 | ; op1 + op2 + c < op2 | |
5186 | ||
5187 | ; alcr, alc, alcgr, alcg | |
5188 | (define_insn "*add<mode>3_alc_carry2_cc" | |
5189 | [(set (reg CC_REGNUM) | |
5190 | (compare | |
5191 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5192 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5193 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5194 | (match_dup 2))) |
5195 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5196 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5197 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5198 | "@ | |
5199 | alc<g>r\t%0,%2 | |
5200 | alc<g>\t%0,%2" | |
5201 | [(set_attr "op_type" "RRE,RXY")]) | |
5202 | ||
5203 | ; alcr, alc, alcgr, alcg | |
5204 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
5205 | [(set (reg CC_REGNUM) | |
5206 | (compare | |
5207 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5208 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5209 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5210 | (match_dup 2))) |
5211 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5212 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5213 | "@ | |
5214 | alc<g>r\t%0,%2 | |
5215 | alc<g>\t%0,%2" | |
5216 | [(set_attr "op_type" "RRE,RXY")]) | |
5217 | ||
43a09b63 | 5218 | ; alcr, alc, alcgr, alcg |
9a91a21f | 5219 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 5220 | [(set (reg CC_REGNUM) |
e69166de | 5221 | (compare |
a94a76a7 UW |
5222 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5223 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5224 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 5225 | (const_int 0))) |
9a91a21f | 5226 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 5227 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 5228 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5229 | "@ |
9a91a21f AS |
5230 | alc<g>r\t%0,%2 |
5231 | alc<g>\t%0,%2" | |
e69166de UW |
5232 | [(set_attr "op_type" "RRE,RXY")]) |
5233 | ||
43a09b63 | 5234 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
5235 | (define_insn "*add<mode>3_alc" |
5236 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
5237 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5238 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5239 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 5240 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5241 | "TARGET_CPU_ZARCH" |
e69166de | 5242 | "@ |
9a91a21f AS |
5243 | alc<g>r\t%0,%2 |
5244 | alc<g>\t%0,%2" | |
e69166de UW |
5245 | [(set_attr "op_type" "RRE,RXY")]) |
5246 | ||
43a09b63 | 5247 | ; slbr, slb, slbgr, slbg |
9a91a21f | 5248 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 5249 | [(set (reg CC_REGNUM) |
e69166de | 5250 | (compare |
9a91a21f | 5251 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 5252 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5253 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 5254 | (const_int 0))) |
9a91a21f AS |
5255 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
5256 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 5257 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5258 | "@ |
9a91a21f AS |
5259 | slb<g>r\t%0,%2 |
5260 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5261 | [(set_attr "op_type" "RRE,RXY") |
5262 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5263 | |
43a09b63 | 5264 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
5265 | (define_insn "*sub<mode>3_slb" |
5266 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5267 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 5268 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5269 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 5270 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5271 | "TARGET_CPU_ZARCH" |
e69166de | 5272 | "@ |
9a91a21f AS |
5273 | slb<g>r\t%0,%2 |
5274 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5275 | [(set_attr "op_type" "RRE,RXY") |
5276 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5277 | |
9a91a21f AS |
5278 | (define_expand "add<mode>cc" |
5279 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 5280 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
5281 | (match_operand:GPR 2 "register_operand" "") |
5282 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 5283 | "TARGET_CPU_ZARCH" |
9381e3f1 | 5284 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 5285 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 5286 | operands[0], operands[2], |
5d880bd2 UW |
5287 | operands[3])) FAIL; DONE;") |
5288 | ||
5289 | ; | |
5290 | ; scond instruction pattern(s). | |
5291 | ; | |
5292 | ||
9a91a21f AS |
5293 | (define_insn_and_split "*scond<mode>" |
5294 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5295 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 5296 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5297 | "TARGET_CPU_ZARCH" |
5298 | "#" | |
5299 | "&& reload_completed" | |
5300 | [(set (match_dup 0) (const_int 0)) | |
5301 | (parallel | |
a94a76a7 UW |
5302 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
5303 | (match_dup 0))) | |
ae156f85 | 5304 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5305 | "") |
5d880bd2 | 5306 | |
9a91a21f AS |
5307 | (define_insn_and_split "*scond<mode>_neg" |
5308 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5309 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 5310 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5311 | "TARGET_CPU_ZARCH" |
5312 | "#" | |
5313 | "&& reload_completed" | |
5314 | [(set (match_dup 0) (const_int 0)) | |
5315 | (parallel | |
9a91a21f AS |
5316 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
5317 | (match_dup 1))) | |
ae156f85 | 5318 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 5319 | (parallel |
9a91a21f | 5320 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 5321 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5322 | "") |
5d880bd2 | 5323 | |
5d880bd2 | 5324 | |
f90b7a5a | 5325 | (define_expand "cstore<mode>4" |
9a91a21f | 5326 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
5327 | (match_operator:SI 1 "s390_scond_operator" |
5328 | [(match_operand:GPR 2 "register_operand" "") | |
5329 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 5330 | "TARGET_CPU_ZARCH" |
f90b7a5a | 5331 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
5332 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
5333 | ||
f90b7a5a | 5334 | (define_expand "cstorecc4" |
69950452 | 5335 | [(parallel |
f90b7a5a PB |
5336 | [(set (match_operand:SI 0 "register_operand" "") |
5337 | (match_operator:SI 1 "s390_eqne_operator" | |
5338 | [(match_operand:CCZ1 2 "register_operand") | |
5339 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
5340 | (clobber (reg:CC CC_REGNUM))])] |
5341 | "" | |
f90b7a5a PB |
5342 | "emit_insn (gen_sne (operands[0], operands[2])); |
5343 | if (GET_CODE (operands[1]) == EQ) | |
5344 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
5345 | DONE;") | |
69950452 | 5346 | |
f90b7a5a | 5347 | (define_insn_and_split "sne" |
69950452 | 5348 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 5349 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
5350 | (const_int 0))) |
5351 | (clobber (reg:CC CC_REGNUM))] | |
5352 | "" | |
5353 | "#" | |
5354 | "reload_completed" | |
5355 | [(parallel | |
5356 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
5357 | (clobber (reg:CC CC_REGNUM))])]) | |
5358 | ||
e69166de | 5359 | |
65b1d8ea AK |
5360 | ;; |
5361 | ;; - Conditional move instructions (introduced with z196) | |
5362 | ;; | |
5363 | ||
5364 | (define_expand "mov<mode>cc" | |
5365 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
5366 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
5367 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
5368 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
5369 | "TARGET_Z196" | |
5370 | "operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
5371 | XEXP (operands[1], 0), XEXP (operands[1], 1));") | |
5372 | ||
27037b5f | 5373 | ; locr, loc, stoc, locgr, locg, stocg |
65b1d8ea AK |
5374 | (define_insn_and_split "*mov<mode>cc" |
5375 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
5376 | (if_then_else:GPR | |
5377 | (match_operator 1 "s390_comparison" | |
5378 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5379 | (const_int 0)]) | |
5380 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") | |
5381 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
5382 | "TARGET_Z196" | |
5383 | "@ | |
5384 | loc<g>r%C1\t%0,%3 | |
5385 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
5386 | loc<g>%C1\t%0,%3 |
5387 | loc<g>%D1\t%0,%4 | |
5388 | stoc<g>%C1\t%3,%0 | |
5389 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
5390 | #" |
5391 | "&& reload_completed | |
5392 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
5393 | [(set (match_dup 0) | |
5394 | (if_then_else:GPR | |
5395 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5396 | (match_dup 3) | |
5397 | (match_dup 0))) | |
5398 | (set (match_dup 0) | |
5399 | (if_then_else:GPR | |
5400 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5401 | (match_dup 0) | |
5402 | (match_dup 4)))] | |
5403 | "" | |
5404 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
5405 | ||
9db1d521 HP |
5406 | ;; |
5407 | ;;- Multiply instructions. | |
5408 | ;; | |
5409 | ||
4023fb28 UW |
5410 | ; |
5411 | ; muldi3 instruction pattern(s). | |
5412 | ; | |
9db1d521 | 5413 | |
07893d4f UW |
5414 | (define_insn "*muldi3_sign" |
5415 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 5416 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5417 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 5418 | "TARGET_ZARCH" |
07893d4f | 5419 | "@ |
d40c829f UW |
5420 | msgfr\t%0,%2 |
5421 | msgf\t%0,%2" | |
963fc8d0 AK |
5422 | [(set_attr "op_type" "RRE,RXY") |
5423 | (set_attr "type" "imuldi")]) | |
07893d4f | 5424 | |
4023fb28 | 5425 | (define_insn "muldi3" |
963fc8d0 AK |
5426 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
5427 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5428 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 5429 | "TARGET_ZARCH" |
9db1d521 | 5430 | "@ |
d40c829f UW |
5431 | msgr\t%0,%2 |
5432 | mghi\t%0,%h2 | |
963fc8d0 AK |
5433 | msg\t%0,%2 |
5434 | msgfi\t%0,%2" | |
5435 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
5436 | (set_attr "type" "imuldi") | |
5437 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 5438 | |
9db1d521 HP |
5439 | ; |
5440 | ; mulsi3 instruction pattern(s). | |
5441 | ; | |
5442 | ||
f1e77d83 | 5443 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
5444 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
5445 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5446 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 5447 | "" |
963fc8d0 AK |
5448 | "@ |
5449 | mh\t%0,%2 | |
5450 | mhy\t%0,%2" | |
5451 | [(set_attr "op_type" "RX,RXY") | |
5452 | (set_attr "type" "imulhi") | |
5453 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 5454 | |
9db1d521 | 5455 | (define_insn "mulsi3" |
963fc8d0 AK |
5456 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
5457 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5458 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
5459 | "" |
5460 | "@ | |
d40c829f UW |
5461 | msr\t%0,%2 |
5462 | mhi\t%0,%h2 | |
5463 | ms\t%0,%2 | |
963fc8d0 AK |
5464 | msy\t%0,%2 |
5465 | msfi\t%0,%2" | |
5466 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
5467 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
5468 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 5469 | |
4023fb28 UW |
5470 | ; |
5471 | ; mulsidi3 instruction pattern(s). | |
5472 | ; | |
5473 | ||
f1e77d83 | 5474 | (define_insn "mulsidi3" |
963fc8d0 | 5475 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 5476 | (mult:DI (sign_extend:DI |
963fc8d0 | 5477 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 5478 | (sign_extend:DI |
963fc8d0 | 5479 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 5480 | "!TARGET_ZARCH" |
f1e77d83 UW |
5481 | "@ |
5482 | mr\t%0,%2 | |
963fc8d0 AK |
5483 | m\t%0,%2 |
5484 | mfy\t%0,%2" | |
5485 | [(set_attr "op_type" "RR,RX,RXY") | |
5486 | (set_attr "type" "imulsi") | |
5487 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 5488 | |
f1e77d83 | 5489 | ; |
6e0d70c9 | 5490 | ; umul instruction pattern(s). |
f1e77d83 | 5491 | ; |
c7453384 | 5492 | |
6e0d70c9 AK |
5493 | ; mlr, ml, mlgr, mlg |
5494 | (define_insn "umul<dwh><mode>3" | |
5495 | [(set (match_operand:DW 0 "register_operand" "=d, d") | |
5496 | (mult:DW (zero_extend:DW | |
5497 | (match_operand:<DWH> 1 "register_operand" "%0, 0")) | |
5498 | (zero_extend:DW | |
5499 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] | |
5500 | "TARGET_CPU_ZARCH" | |
f1e77d83 | 5501 | "@ |
6e0d70c9 AK |
5502 | ml<tg>r\t%0,%2 |
5503 | ml<tg>\t%0,%2" | |
f1e77d83 | 5504 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 5505 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 5506 | |
9db1d521 | 5507 | ; |
609e7e80 | 5508 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5509 | ; |
5510 | ||
9381e3f1 | 5511 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 5512 | (define_insn "mul<mode>3" |
609e7e80 AK |
5513 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5514 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
5515 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5516 | "TARGET_HARD_FLOAT" |
9db1d521 | 5517 | "@ |
609e7e80 | 5518 | m<xdee><bt>r\t%0,<op1>%2 |
f61a2c7d | 5519 | m<xdee>b\t%0,%2" |
609e7e80 | 5520 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5521 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 5522 | |
9381e3f1 | 5523 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 5524 | (define_insn "fma<mode>4" |
f61a2c7d | 5525 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
d7ecb504 RH |
5526 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5527 | (match_operand:DSF 2 "nonimmediate_operand" "f,R") | |
f61a2c7d | 5528 | (match_operand:DSF 3 "register_operand" "0,0")))] |
d7ecb504 | 5529 | "TARGET_HARD_FLOAT" |
a1b892b5 | 5530 | "@ |
f61a2c7d AK |
5531 | ma<xde>br\t%0,%1,%2 |
5532 | ma<xde>b\t%0,%1,%2" | |
a1b892b5 | 5533 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5534 | (set_attr "type" "fmadd<mode>")]) |
a1b892b5 | 5535 | |
43a09b63 | 5536 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 5537 | (define_insn "fms<mode>4" |
f61a2c7d | 5538 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
d7ecb504 RH |
5539 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5540 | (match_operand:DSF 2 "nonimmediate_operand" "f,R") | |
5541 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))] | |
5542 | "TARGET_HARD_FLOAT" | |
a1b892b5 | 5543 | "@ |
f61a2c7d AK |
5544 | ms<xde>br\t%0,%1,%2 |
5545 | ms<xde>b\t%0,%1,%2" | |
ce50cae8 | 5546 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5547 | (set_attr "type" "fmadd<mode>")]) |
9db1d521 HP |
5548 | |
5549 | ;; | |
5550 | ;;- Divide and modulo instructions. | |
5551 | ;; | |
5552 | ||
5553 | ; | |
4023fb28 | 5554 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
5555 | ; |
5556 | ||
4023fb28 UW |
5557 | (define_expand "divmoddi4" |
5558 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 5559 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
5560 | (match_operand:DI 2 "general_operand" ""))) |
5561 | (set (match_operand:DI 3 "general_operand" "") | |
5562 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
5563 | (clobber (match_dup 4))] | |
9602b6a1 | 5564 | "TARGET_ZARCH" |
9db1d521 | 5565 | { |
f1e77d83 | 5566 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
5567 | |
5568 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
5569 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
5570 | |
5571 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 5572 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
5573 | |
5574 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5575 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5576 | |
5577 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5578 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5579 | |
9db1d521 | 5580 | DONE; |
10bbf137 | 5581 | }) |
9db1d521 HP |
5582 | |
5583 | (define_insn "divmodtidi3" | |
4023fb28 UW |
5584 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
5585 | (ior:TI | |
4023fb28 UW |
5586 | (ashift:TI |
5587 | (zero_extend:TI | |
5665e398 | 5588 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5589 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
5590 | (const_int 64)) |
5591 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 5592 | "TARGET_ZARCH" |
9db1d521 | 5593 | "@ |
d40c829f UW |
5594 | dsgr\t%0,%2 |
5595 | dsg\t%0,%2" | |
d3632d41 | 5596 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5597 | (set_attr "type" "idiv")]) |
9db1d521 | 5598 | |
4023fb28 UW |
5599 | (define_insn "divmodtisi3" |
5600 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5601 | (ior:TI | |
4023fb28 UW |
5602 | (ashift:TI |
5603 | (zero_extend:TI | |
5665e398 | 5604 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 5605 | (sign_extend:DI |
fb492564 | 5606 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
5607 | (const_int 64)) |
5608 | (zero_extend:TI | |
5609 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 5610 | "TARGET_ZARCH" |
4023fb28 | 5611 | "@ |
d40c829f UW |
5612 | dsgfr\t%0,%2 |
5613 | dsgf\t%0,%2" | |
d3632d41 | 5614 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5615 | (set_attr "type" "idiv")]) |
9db1d521 | 5616 | |
4023fb28 UW |
5617 | ; |
5618 | ; udivmoddi4 instruction pattern(s). | |
5619 | ; | |
9db1d521 | 5620 | |
4023fb28 UW |
5621 | (define_expand "udivmoddi4" |
5622 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5623 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
5624 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
5625 | (set (match_operand:DI 3 "general_operand" "") | |
5626 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
5627 | (clobber (match_dup 4))] | |
9602b6a1 | 5628 | "TARGET_ZARCH" |
9db1d521 | 5629 | { |
4023fb28 UW |
5630 | rtx insn, div_equal, mod_equal, equal; |
5631 | ||
5632 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
5633 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
5634 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
5635 | gen_rtx_ASHIFT (TImode, |
5636 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
5637 | GEN_INT (64)), |
5638 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
5639 | |
5640 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 5641 | emit_clobber (operands[4]); |
4023fb28 UW |
5642 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
5643 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 5644 | |
4023fb28 | 5645 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5646 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5647 | |
5648 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5649 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5650 | |
5651 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5652 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5653 | |
9db1d521 | 5654 | DONE; |
10bbf137 | 5655 | }) |
9db1d521 HP |
5656 | |
5657 | (define_insn "udivmodtidi3" | |
4023fb28 | 5658 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 5659 | (ior:TI |
5665e398 UW |
5660 | (ashift:TI |
5661 | (zero_extend:TI | |
5662 | (truncate:DI | |
2f7e5a0d EC |
5663 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
5664 | (zero_extend:TI | |
fb492564 | 5665 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5666 | (const_int 64)) |
5667 | (zero_extend:TI | |
5668 | (truncate:DI | |
5669 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 5670 | "TARGET_ZARCH" |
9db1d521 | 5671 | "@ |
d40c829f UW |
5672 | dlgr\t%0,%2 |
5673 | dlg\t%0,%2" | |
d3632d41 | 5674 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5675 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5676 | |
5677 | ; | |
4023fb28 | 5678 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
5679 | ; |
5680 | ||
4023fb28 UW |
5681 | (define_expand "divmodsi4" |
5682 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5683 | (div:SI (match_operand:SI 1 "general_operand" "") | |
5684 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5685 | (set (match_operand:SI 3 "general_operand" "") | |
5686 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
5687 | (clobber (match_dup 4))] | |
9602b6a1 | 5688 | "!TARGET_ZARCH" |
9db1d521 | 5689 | { |
4023fb28 UW |
5690 | rtx insn, div_equal, mod_equal, equal; |
5691 | ||
5692 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
5693 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
5694 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5695 | gen_rtx_ASHIFT (DImode, |
5696 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5697 | GEN_INT (32)), |
5698 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
5699 | |
5700 | operands[4] = gen_reg_rtx(DImode); | |
5701 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 5702 | |
4023fb28 | 5703 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5704 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5705 | |
5706 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5707 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5708 | |
5709 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5710 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5711 | |
9db1d521 | 5712 | DONE; |
10bbf137 | 5713 | }) |
9db1d521 HP |
5714 | |
5715 | (define_insn "divmoddisi3" | |
4023fb28 | 5716 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 5717 | (ior:DI |
5665e398 UW |
5718 | (ashift:DI |
5719 | (zero_extend:DI | |
5720 | (truncate:SI | |
2f7e5a0d EC |
5721 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
5722 | (sign_extend:DI | |
5665e398 UW |
5723 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
5724 | (const_int 32)) | |
5725 | (zero_extend:DI | |
5726 | (truncate:SI | |
5727 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5728 | "!TARGET_ZARCH" |
9db1d521 | 5729 | "@ |
d40c829f UW |
5730 | dr\t%0,%2 |
5731 | d\t%0,%2" | |
9db1d521 | 5732 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5733 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5734 | |
5735 | ; | |
5736 | ; udivsi3 and umodsi3 instruction pattern(s). | |
5737 | ; | |
5738 | ||
f1e77d83 UW |
5739 | (define_expand "udivmodsi4" |
5740 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5741 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5742 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5743 | (set (match_operand:SI 3 "general_operand" "") | |
5744 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
5745 | (clobber (match_dup 4))] | |
9602b6a1 | 5746 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5747 | { |
5748 | rtx insn, div_equal, mod_equal, equal; | |
5749 | ||
5750 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5751 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5752 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
5753 | gen_rtx_ASHIFT (DImode, |
5754 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5755 | GEN_INT (32)), |
5756 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
5757 | |
5758 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 5759 | emit_clobber (operands[4]); |
f1e77d83 UW |
5760 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
5761 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 5762 | |
f1e77d83 | 5763 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5764 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
5765 | |
5766 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5767 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
5768 | |
5769 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5770 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
5771 | |
5772 | DONE; | |
5773 | }) | |
5774 | ||
5775 | (define_insn "udivmoddisi3" | |
5776 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 5777 | (ior:DI |
5665e398 UW |
5778 | (ashift:DI |
5779 | (zero_extend:DI | |
5780 | (truncate:SI | |
2f7e5a0d EC |
5781 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
5782 | (zero_extend:DI | |
fb492564 | 5783 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5784 | (const_int 32)) |
5785 | (zero_extend:DI | |
5786 | (truncate:SI | |
5787 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5788 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5789 | "@ |
5790 | dlr\t%0,%2 | |
5791 | dl\t%0,%2" | |
5792 | [(set_attr "op_type" "RRE,RXY") | |
5793 | (set_attr "type" "idiv")]) | |
4023fb28 | 5794 | |
9db1d521 HP |
5795 | (define_expand "udivsi3" |
5796 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5797 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
5798 | (match_operand:SI 2 "general_operand" ""))) |
5799 | (clobber (match_dup 3))] | |
9602b6a1 | 5800 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 5801 | { |
4023fb28 UW |
5802 | rtx insn, udiv_equal, umod_equal, equal; |
5803 | ||
5804 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5805 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5806 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5807 | gen_rtx_ASHIFT (DImode, |
5808 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5809 | GEN_INT (32)), |
5810 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5811 | |
4023fb28 | 5812 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5813 | |
5814 | if (CONSTANT_P (operands[2])) | |
5815 | { | |
5816 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
5817 | { | |
5818 | rtx label1 = gen_label_rtx (); | |
5819 | ||
4023fb28 UW |
5820 | operands[1] = make_safe_from (operands[1], operands[0]); |
5821 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5822 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
5823 | SImode, 1, label1); | |
4023fb28 | 5824 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5825 | emit_label (label1); |
5826 | } | |
5827 | else | |
5828 | { | |
c7453384 EC |
5829 | operands[2] = force_reg (SImode, operands[2]); |
5830 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5831 | |
5832 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5833 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5834 | operands[2])); | |
bd94cb6e | 5835 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5836 | |
5837 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5838 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 5839 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
5840 | } |
5841 | } | |
5842 | else | |
c7453384 | 5843 | { |
9db1d521 HP |
5844 | rtx label1 = gen_label_rtx (); |
5845 | rtx label2 = gen_label_rtx (); | |
5846 | rtx label3 = gen_label_rtx (); | |
5847 | ||
c7453384 EC |
5848 | operands[1] = force_reg (SImode, operands[1]); |
5849 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5850 | operands[2] = force_reg (SImode, operands[2]); | |
5851 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5852 | |
5853 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5854 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
5855 | SImode, 1, label3); | |
5856 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
5857 | SImode, 0, label2); | |
5858 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
5859 | SImode, 0, label1); | |
4023fb28 UW |
5860 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5861 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5862 | operands[2])); | |
bd94cb6e | 5863 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5864 | |
5865 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5866 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
5867 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
5868 | ||
f314b9b1 | 5869 | emit_jump (label3); |
9db1d521 | 5870 | emit_label (label1); |
4023fb28 | 5871 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 5872 | emit_jump (label3); |
9db1d521 | 5873 | emit_label (label2); |
4023fb28 | 5874 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5875 | emit_label (label3); |
5876 | } | |
c7453384 | 5877 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 5878 | DONE; |
10bbf137 | 5879 | }) |
9db1d521 HP |
5880 | |
5881 | (define_expand "umodsi3" | |
5882 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5883 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
5884 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
5885 | (clobber (match_dup 3))] | |
9602b6a1 | 5886 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 5887 | { |
4023fb28 UW |
5888 | rtx insn, udiv_equal, umod_equal, equal; |
5889 | ||
5890 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5891 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5892 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5893 | gen_rtx_ASHIFT (DImode, |
5894 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5895 | GEN_INT (32)), |
5896 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5897 | |
4023fb28 | 5898 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5899 | |
5900 | if (CONSTANT_P (operands[2])) | |
5901 | { | |
5902 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
5903 | { | |
5904 | rtx label1 = gen_label_rtx (); | |
5905 | ||
4023fb28 UW |
5906 | operands[1] = make_safe_from (operands[1], operands[0]); |
5907 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
5908 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
5909 | SImode, 1, label1); | |
4023fb28 UW |
5910 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
5911 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
5912 | emit_label (label1); |
5913 | } | |
5914 | else | |
5915 | { | |
c7453384 EC |
5916 | operands[2] = force_reg (SImode, operands[2]); |
5917 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5918 | |
5919 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5920 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5921 | operands[2])); | |
bd94cb6e | 5922 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5923 | |
5924 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5925 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 5926 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
5927 | } |
5928 | } | |
5929 | else | |
5930 | { | |
5931 | rtx label1 = gen_label_rtx (); | |
5932 | rtx label2 = gen_label_rtx (); | |
5933 | rtx label3 = gen_label_rtx (); | |
5934 | ||
c7453384 EC |
5935 | operands[1] = force_reg (SImode, operands[1]); |
5936 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5937 | operands[2] = force_reg (SImode, operands[2]); | |
5938 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5939 | |
c7453384 | 5940 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
5941 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
5942 | SImode, 1, label3); | |
5943 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
5944 | SImode, 0, label2); | |
5945 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
5946 | SImode, 0, label1); | |
4023fb28 UW |
5947 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5948 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5949 | operands[2])); | |
bd94cb6e | 5950 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5951 | |
5952 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5953 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
5954 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
5955 | ||
f314b9b1 | 5956 | emit_jump (label3); |
9db1d521 | 5957 | emit_label (label1); |
4023fb28 | 5958 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5959 | emit_jump (label3); |
9db1d521 | 5960 | emit_label (label2); |
4023fb28 | 5961 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5962 | emit_label (label3); |
5963 | } | |
9db1d521 | 5964 | DONE; |
10bbf137 | 5965 | }) |
9db1d521 HP |
5966 | |
5967 | ; | |
f5905b37 | 5968 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
5969 | ; |
5970 | ||
609e7e80 | 5971 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 5972 | (define_insn "div<mode>3" |
609e7e80 AK |
5973 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5974 | (div:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
5975 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5976 | "TARGET_HARD_FLOAT" |
9db1d521 | 5977 | "@ |
609e7e80 | 5978 | d<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5979 | d<xde>b\t%0,%2" |
609e7e80 | 5980 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5981 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 5982 | |
9db1d521 HP |
5983 | |
5984 | ;; | |
5985 | ;;- And instructions. | |
5986 | ;; | |
5987 | ||
047d35ed AS |
5988 | (define_expand "and<mode>3" |
5989 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5990 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5991 | (match_operand:INT 2 "general_operand" ""))) | |
5992 | (clobber (reg:CC CC_REGNUM))] | |
5993 | "" | |
5994 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
5995 | ||
9db1d521 HP |
5996 | ; |
5997 | ; anddi3 instruction pattern(s). | |
5998 | ; | |
5999 | ||
6000 | (define_insn "*anddi3_cc" | |
ae156f85 | 6001 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6002 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6003 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
9db1d521 | 6004 | (const_int 0))) |
65b1d8ea | 6005 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
9db1d521 | 6006 | (and:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6007 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
9db1d521 | 6008 | "@ |
d40c829f | 6009 | ngr\t%0,%2 |
65b1d8ea | 6010 | ngrk\t%0,%1,%2 |
d40c829f | 6011 | ng\t%0,%2" |
65b1d8ea AK |
6012 | [(set_attr "op_type" "RRE,RRF,RXY") |
6013 | (set_attr "cpu_facility" "*,z196,*") | |
6014 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
9db1d521 HP |
6015 | |
6016 | (define_insn "*anddi3_cconly" | |
ae156f85 | 6017 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6018 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6019 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
9db1d521 | 6020 | (const_int 0))) |
65b1d8ea | 6021 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 6022 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH |
68f9c5e2 UW |
6023 | /* Do not steal TM patterns. */ |
6024 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 6025 | "@ |
d40c829f | 6026 | ngr\t%0,%2 |
65b1d8ea | 6027 | ngrk\t%0,%1,%2 |
d40c829f | 6028 | ng\t%0,%2" |
65b1d8ea AK |
6029 | [(set_attr "op_type" "RRE,RRF,RXY") |
6030 | (set_attr "cpu_facility" "*,z196,*") | |
6031 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
9db1d521 | 6032 | |
3af8e996 | 6033 | (define_insn "*anddi3" |
65b1d8ea AK |
6034 | [(set (match_operand:DI 0 "nonimmediate_operand" |
6035 | "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q") | |
ec24698e | 6036 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
65b1d8ea | 6037 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0") |
ec24698e | 6038 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 6039 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q"))) |
ec24698e | 6040 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6041 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6042 | "@ |
6043 | # | |
6044 | # | |
6045 | nihh\t%0,%j2 | |
6046 | nihl\t%0,%j2 | |
6047 | nilh\t%0,%j2 | |
6048 | nill\t%0,%j2 | |
6049 | nihf\t%0,%m2 | |
6050 | nilf\t%0,%m2 | |
6051 | ngr\t%0,%2 | |
65b1d8ea | 6052 | ngrk\t%0,%1,%2 |
ec24698e UW |
6053 | ng\t%0,%2 |
6054 | # | |
6055 | #" | |
65b1d8ea AK |
6056 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
6057 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
6058 | (set_attr "z10prop" "*, |
6059 | *, | |
6060 | z10_super_E1, | |
6061 | z10_super_E1, | |
6062 | z10_super_E1, | |
6063 | z10_super_E1, | |
6064 | z10_super_E1, | |
6065 | z10_super_E1, | |
6066 | z10_super_E1, | |
65b1d8ea | 6067 | *, |
9381e3f1 WG |
6068 | z10_super_E1, |
6069 | *, | |
6070 | *")]) | |
0dfa6c5e UW |
6071 | |
6072 | (define_split | |
6073 | [(set (match_operand:DI 0 "s_operand" "") | |
6074 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6075 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6076 | "reload_completed" |
6077 | [(parallel | |
6078 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6079 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6080 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6081 | |
9db1d521 HP |
6082 | |
6083 | ; | |
6084 | ; andsi3 instruction pattern(s). | |
6085 | ; | |
6086 | ||
6087 | (define_insn "*andsi3_cc" | |
ae156f85 | 6088 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6089 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6090 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
9db1d521 | 6091 | (const_int 0))) |
65b1d8ea | 6092 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
9db1d521 HP |
6093 | (and:SI (match_dup 1) (match_dup 2)))] |
6094 | "s390_match_ccmode(insn, CCTmode)" | |
6095 | "@ | |
ec24698e | 6096 | nilf\t%0,%o2 |
d40c829f | 6097 | nr\t%0,%2 |
65b1d8ea | 6098 | nrk\t%0,%1,%2 |
d40c829f UW |
6099 | n\t%0,%2 |
6100 | ny\t%0,%2" | |
65b1d8ea AK |
6101 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6102 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6103 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6104 | |
6105 | (define_insn "*andsi3_cconly" | |
ae156f85 | 6106 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6107 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6108 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
9db1d521 | 6109 | (const_int 0))) |
65b1d8ea | 6110 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
68f9c5e2 UW |
6111 | "s390_match_ccmode(insn, CCTmode) |
6112 | /* Do not steal TM patterns. */ | |
6113 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 6114 | "@ |
ec24698e | 6115 | nilf\t%0,%o2 |
d40c829f | 6116 | nr\t%0,%2 |
65b1d8ea | 6117 | nrk\t%0,%1,%2 |
d40c829f UW |
6118 | n\t%0,%2 |
6119 | ny\t%0,%2" | |
65b1d8ea AK |
6120 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6121 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6122 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6123 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6124 | |
f19a9af7 | 6125 | (define_insn "*andsi3_zarch" |
65b1d8ea AK |
6126 | [(set (match_operand:SI 0 "nonimmediate_operand" |
6127 | "=d,d, d, d, d,d,d,d,d, AQ,Q") | |
0dfa6c5e | 6128 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
65b1d8ea | 6129 | "%d,o, 0, 0, 0,0,d,0,0, 0,0") |
0dfa6c5e | 6130 | (match_operand:SI 2 "general_operand" |
65b1d8ea | 6131 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q"))) |
ae156f85 | 6132 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6133 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6134 | "@ |
f19a9af7 AK |
6135 | # |
6136 | # | |
6137 | nilh\t%0,%j2 | |
2f7e5a0d | 6138 | nill\t%0,%j2 |
ec24698e | 6139 | nilf\t%0,%o2 |
d40c829f | 6140 | nr\t%0,%2 |
65b1d8ea | 6141 | nrk\t%0,%1,%2 |
d40c829f | 6142 | n\t%0,%2 |
8cb66696 | 6143 | ny\t%0,%2 |
0dfa6c5e | 6144 | # |
19b63d8e | 6145 | #" |
65b1d8ea AK |
6146 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
6147 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
6148 | (set_attr "z10prop" "*, |
6149 | *, | |
6150 | z10_super_E1, | |
6151 | z10_super_E1, | |
6152 | z10_super_E1, | |
6153 | z10_super_E1, | |
65b1d8ea | 6154 | *, |
9381e3f1 WG |
6155 | z10_super_E1, |
6156 | z10_super_E1, | |
6157 | *, | |
6158 | *")]) | |
f19a9af7 AK |
6159 | |
6160 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
6161 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
6162 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
6163 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 6164 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6165 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6166 | "@ |
6167 | nr\t%0,%2 | |
8cb66696 | 6168 | n\t%0,%2 |
0dfa6c5e | 6169 | # |
19b63d8e | 6170 | #" |
9381e3f1 WG |
6171 | [(set_attr "op_type" "RR,RX,SI,SS") |
6172 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6173 | ||
0dfa6c5e UW |
6174 | |
6175 | (define_split | |
6176 | [(set (match_operand:SI 0 "s_operand" "") | |
6177 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6178 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6179 | "reload_completed" |
6180 | [(parallel | |
6181 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6182 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6183 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6184 | |
9db1d521 HP |
6185 | ; |
6186 | ; andhi3 instruction pattern(s). | |
6187 | ; | |
6188 | ||
8cb66696 | 6189 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
6190 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6191 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6192 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 6193 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6194 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6195 | "@ |
d40c829f | 6196 | nr\t%0,%2 |
65b1d8ea | 6197 | nrk\t%0,%1,%2 |
8cb66696 | 6198 | nill\t%0,%x2 |
0dfa6c5e | 6199 | # |
19b63d8e | 6200 | #" |
65b1d8ea AK |
6201 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6202 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6203 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 6204 | ]) |
8cb66696 UW |
6205 | |
6206 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
6207 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6208 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6209 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 6210 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6211 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6212 | "@ | |
6213 | nr\t%0,%2 | |
0dfa6c5e | 6214 | # |
19b63d8e | 6215 | #" |
9381e3f1 WG |
6216 | [(set_attr "op_type" "RR,SI,SS") |
6217 | (set_attr "z10prop" "z10_super_E1,*,*") | |
6218 | ]) | |
0dfa6c5e UW |
6219 | |
6220 | (define_split | |
6221 | [(set (match_operand:HI 0 "s_operand" "") | |
6222 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6223 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6224 | "reload_completed" |
6225 | [(parallel | |
6226 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6227 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6228 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 6229 | |
9db1d521 HP |
6230 | ; |
6231 | ; andqi3 instruction pattern(s). | |
6232 | ; | |
6233 | ||
8cb66696 | 6234 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
6235 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6236 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6237 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6238 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6239 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6240 | "@ |
d40c829f | 6241 | nr\t%0,%2 |
65b1d8ea | 6242 | nrk\t%0,%1,%2 |
8cb66696 | 6243 | nill\t%0,%b2 |
fc0ea003 UW |
6244 | ni\t%S0,%b2 |
6245 | niy\t%S0,%b2 | |
19b63d8e | 6246 | #" |
65b1d8ea AK |
6247 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6248 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6249 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
6250 | |
6251 | (define_insn "*andqi3_esa" | |
6252 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6253 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6254 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6255 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6256 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6257 | "@ |
8cb66696 | 6258 | nr\t%0,%2 |
fc0ea003 | 6259 | ni\t%S0,%b2 |
19b63d8e | 6260 | #" |
9381e3f1 WG |
6261 | [(set_attr "op_type" "RR,SI,SS") |
6262 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 6263 | |
19b63d8e UW |
6264 | ; |
6265 | ; Block and (NC) patterns. | |
6266 | ; | |
6267 | ||
6268 | (define_insn "*nc" | |
6269 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6270 | (and:BLK (match_dup 0) | |
6271 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6272 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6273 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6274 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6275 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6276 | [(set_attr "op_type" "SS") |
6277 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6278 | |
6279 | (define_split | |
6280 | [(set (match_operand 0 "memory_operand" "") | |
6281 | (and (match_dup 0) | |
6282 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6283 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6284 | "reload_completed |
6285 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6286 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6287 | [(parallel | |
6288 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
6289 | (use (match_dup 2)) | |
ae156f85 | 6290 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6291 | { |
6292 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6293 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6294 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6295 | }) | |
6296 | ||
6297 | (define_peephole2 | |
6298 | [(parallel | |
6299 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6300 | (and:BLK (match_dup 0) | |
6301 | (match_operand:BLK 1 "memory_operand" ""))) | |
6302 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6303 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6304 | (parallel |
6305 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6306 | (and:BLK (match_dup 3) | |
6307 | (match_operand:BLK 4 "memory_operand" ""))) | |
6308 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6309 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6310 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6311 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6312 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6313 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6314 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6315 | [(parallel | |
6316 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
6317 | (use (match_dup 8)) | |
ae156f85 | 6318 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6319 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6320 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6321 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6322 | ||
9db1d521 HP |
6323 | |
6324 | ;; | |
6325 | ;;- Bit set (inclusive or) instructions. | |
6326 | ;; | |
6327 | ||
047d35ed AS |
6328 | (define_expand "ior<mode>3" |
6329 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6330 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6331 | (match_operand:INT 2 "general_operand" ""))) | |
6332 | (clobber (reg:CC CC_REGNUM))] | |
6333 | "" | |
6334 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
6335 | ||
9db1d521 HP |
6336 | ; |
6337 | ; iordi3 instruction pattern(s). | |
6338 | ; | |
6339 | ||
4023fb28 | 6340 | (define_insn "*iordi3_cc" |
ae156f85 | 6341 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6342 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6343 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6344 | (const_int 0))) |
65b1d8ea | 6345 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6346 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6347 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6348 | "@ |
d40c829f | 6349 | ogr\t%0,%2 |
65b1d8ea | 6350 | ogrk\t%0,%1,%2 |
d40c829f | 6351 | og\t%0,%2" |
65b1d8ea AK |
6352 | [(set_attr "op_type" "RRE,RRF,RXY") |
6353 | (set_attr "cpu_facility" "*,z196,*") | |
6354 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
6355 | |
6356 | (define_insn "*iordi3_cconly" | |
ae156f85 | 6357 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6358 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
6359 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6360 | (const_int 0))) |
65b1d8ea | 6361 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 6362 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6363 | "@ |
d40c829f | 6364 | ogr\t%0,%2 |
65b1d8ea | 6365 | ogrk\t%0,%1,%2 |
d40c829f | 6366 | og\t%0,%2" |
65b1d8ea AK |
6367 | [(set_attr "op_type" "RRE,RRF,RXY") |
6368 | (set_attr "cpu_facility" "*,z196,*") | |
6369 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6370 | |
3af8e996 | 6371 | (define_insn "*iordi3" |
65b1d8ea AK |
6372 | [(set (match_operand:DI 0 "nonimmediate_operand" |
6373 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
6374 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
6375 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 6376 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 6377 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 6378 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6379 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6380 | "@ |
6381 | oihh\t%0,%i2 | |
6382 | oihl\t%0,%i2 | |
6383 | oilh\t%0,%i2 | |
6384 | oill\t%0,%i2 | |
6385 | oihf\t%0,%k2 | |
6386 | oilf\t%0,%k2 | |
6387 | ogr\t%0,%2 | |
65b1d8ea | 6388 | ogrk\t%0,%1,%2 |
ec24698e UW |
6389 | og\t%0,%2 |
6390 | # | |
6391 | #" | |
65b1d8ea AK |
6392 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
6393 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
6394 | (set_attr "z10prop" "z10_super_E1, |
6395 | z10_super_E1, | |
6396 | z10_super_E1, | |
6397 | z10_super_E1, | |
6398 | z10_super_E1, | |
6399 | z10_super_E1, | |
6400 | z10_super_E1, | |
65b1d8ea | 6401 | *, |
9381e3f1 WG |
6402 | z10_super_E1, |
6403 | *, | |
6404 | *")]) | |
0dfa6c5e UW |
6405 | |
6406 | (define_split | |
6407 | [(set (match_operand:DI 0 "s_operand" "") | |
6408 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6409 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6410 | "reload_completed" |
6411 | [(parallel | |
6412 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6413 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6414 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6415 | |
9db1d521 HP |
6416 | ; |
6417 | ; iorsi3 instruction pattern(s). | |
6418 | ; | |
6419 | ||
4023fb28 | 6420 | (define_insn "*iorsi3_cc" |
ae156f85 | 6421 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6422 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6423 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6424 | (const_int 0))) |
65b1d8ea | 6425 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6426 | (ior:SI (match_dup 1) (match_dup 2)))] |
6427 | "s390_match_ccmode(insn, CCTmode)" | |
6428 | "@ | |
ec24698e | 6429 | oilf\t%0,%o2 |
d40c829f | 6430 | or\t%0,%2 |
65b1d8ea | 6431 | ork\t%0,%1,%2 |
d40c829f UW |
6432 | o\t%0,%2 |
6433 | oy\t%0,%2" | |
65b1d8ea AK |
6434 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6435 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6436 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6437 | |
6438 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 6439 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6440 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6441 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6442 | (const_int 0))) |
65b1d8ea | 6443 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6444 | "s390_match_ccmode(insn, CCTmode)" |
6445 | "@ | |
ec24698e | 6446 | oilf\t%0,%o2 |
d40c829f | 6447 | or\t%0,%2 |
65b1d8ea | 6448 | ork\t%0,%1,%2 |
d40c829f UW |
6449 | o\t%0,%2 |
6450 | oy\t%0,%2" | |
65b1d8ea AK |
6451 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6452 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6453 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6454 | |
8cb66696 | 6455 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
6456 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
6457 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
6458 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6459 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6460 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6461 | "@ |
f19a9af7 AK |
6462 | oilh\t%0,%i2 |
6463 | oill\t%0,%i2 | |
ec24698e | 6464 | oilf\t%0,%o2 |
d40c829f | 6465 | or\t%0,%2 |
65b1d8ea | 6466 | ork\t%0,%1,%2 |
d40c829f | 6467 | o\t%0,%2 |
8cb66696 | 6468 | oy\t%0,%2 |
0dfa6c5e | 6469 | # |
19b63d8e | 6470 | #" |
65b1d8ea AK |
6471 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
6472 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
6473 | (set_attr "z10prop" "z10_super_E1, |
6474 | z10_super_E1, | |
6475 | z10_super_E1, | |
6476 | z10_super_E1, | |
65b1d8ea | 6477 | *, |
9381e3f1 WG |
6478 | z10_super_E1, |
6479 | z10_super_E1, | |
6480 | *, | |
6481 | *")]) | |
8cb66696 UW |
6482 | |
6483 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 6484 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 6485 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 6486 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 6487 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6488 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6489 | "@ |
6490 | or\t%0,%2 | |
8cb66696 | 6491 | o\t%0,%2 |
0dfa6c5e | 6492 | # |
19b63d8e | 6493 | #" |
9381e3f1 WG |
6494 | [(set_attr "op_type" "RR,RX,SI,SS") |
6495 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6496 | |
6497 | (define_split | |
6498 | [(set (match_operand:SI 0 "s_operand" "") | |
6499 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6500 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6501 | "reload_completed" |
6502 | [(parallel | |
6503 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6504 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6505 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6506 | |
4023fb28 UW |
6507 | ; |
6508 | ; iorhi3 instruction pattern(s). | |
6509 | ; | |
6510 | ||
8cb66696 | 6511 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
6512 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6513 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6514 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 6515 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6516 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6517 | "@ |
d40c829f | 6518 | or\t%0,%2 |
65b1d8ea | 6519 | ork\t%0,%1,%2 |
8cb66696 | 6520 | oill\t%0,%x2 |
0dfa6c5e | 6521 | # |
19b63d8e | 6522 | #" |
65b1d8ea AK |
6523 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6524 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6525 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
6526 | |
6527 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
6528 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6529 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6530 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 6531 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6532 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6533 | "@ | |
6534 | or\t%0,%2 | |
0dfa6c5e | 6535 | # |
19b63d8e | 6536 | #" |
9381e3f1 WG |
6537 | [(set_attr "op_type" "RR,SI,SS") |
6538 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6539 | |
6540 | (define_split | |
6541 | [(set (match_operand:HI 0 "s_operand" "") | |
6542 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6543 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6544 | "reload_completed" |
6545 | [(parallel | |
6546 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6547 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6548 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 6549 | |
9db1d521 | 6550 | ; |
4023fb28 | 6551 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
6552 | ; |
6553 | ||
8cb66696 | 6554 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
6555 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6556 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6557 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6558 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6559 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6560 | "@ |
d40c829f | 6561 | or\t%0,%2 |
65b1d8ea | 6562 | ork\t%0,%1,%2 |
8cb66696 | 6563 | oill\t%0,%b2 |
fc0ea003 UW |
6564 | oi\t%S0,%b2 |
6565 | oiy\t%S0,%b2 | |
19b63d8e | 6566 | #" |
65b1d8ea AK |
6567 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6568 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6569 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
6570 | z10_super,z10_super,*")]) | |
8cb66696 UW |
6571 | |
6572 | (define_insn "*iorqi3_esa" | |
6573 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6574 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6575 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6576 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6577 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6578 | "@ |
8cb66696 | 6579 | or\t%0,%2 |
fc0ea003 | 6580 | oi\t%S0,%b2 |
19b63d8e | 6581 | #" |
9381e3f1 WG |
6582 | [(set_attr "op_type" "RR,SI,SS") |
6583 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 6584 | |
19b63d8e UW |
6585 | ; |
6586 | ; Block inclusive or (OC) patterns. | |
6587 | ; | |
6588 | ||
6589 | (define_insn "*oc" | |
6590 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6591 | (ior:BLK (match_dup 0) | |
6592 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6593 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6594 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6595 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6596 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6597 | [(set_attr "op_type" "SS") |
6598 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6599 | |
6600 | (define_split | |
6601 | [(set (match_operand 0 "memory_operand" "") | |
6602 | (ior (match_dup 0) | |
6603 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6604 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6605 | "reload_completed |
6606 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6607 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6608 | [(parallel | |
6609 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
6610 | (use (match_dup 2)) | |
ae156f85 | 6611 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6612 | { |
6613 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6614 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6615 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6616 | }) | |
6617 | ||
6618 | (define_peephole2 | |
6619 | [(parallel | |
6620 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6621 | (ior:BLK (match_dup 0) | |
6622 | (match_operand:BLK 1 "memory_operand" ""))) | |
6623 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6624 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6625 | (parallel |
6626 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6627 | (ior:BLK (match_dup 3) | |
6628 | (match_operand:BLK 4 "memory_operand" ""))) | |
6629 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6630 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6631 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6632 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6633 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6634 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6635 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6636 | [(parallel | |
6637 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
6638 | (use (match_dup 8)) | |
ae156f85 | 6639 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6640 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6641 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6642 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6643 | ||
9db1d521 HP |
6644 | |
6645 | ;; | |
6646 | ;;- Xor instructions. | |
6647 | ;; | |
6648 | ||
047d35ed AS |
6649 | (define_expand "xor<mode>3" |
6650 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6651 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6652 | (match_operand:INT 2 "general_operand" ""))) | |
6653 | (clobber (reg:CC CC_REGNUM))] | |
6654 | "" | |
6655 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
6656 | ||
9db1d521 HP |
6657 | ; |
6658 | ; xordi3 instruction pattern(s). | |
6659 | ; | |
6660 | ||
4023fb28 | 6661 | (define_insn "*xordi3_cc" |
ae156f85 | 6662 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6663 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6664 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6665 | (const_int 0))) |
65b1d8ea | 6666 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6667 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6668 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6669 | "@ |
d40c829f | 6670 | xgr\t%0,%2 |
65b1d8ea | 6671 | xgrk\t%0,%1,%2 |
d40c829f | 6672 | xg\t%0,%2" |
65b1d8ea | 6673 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 6674 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 6675 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
6676 | |
6677 | (define_insn "*xordi3_cconly" | |
ae156f85 | 6678 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6679 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6680 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6681 | (const_int 0))) |
65b1d8ea | 6682 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 6683 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6684 | "@ |
d40c829f | 6685 | xgr\t%0,%2 |
65b1d8ea | 6686 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 6687 | xg\t%0,%2" |
65b1d8ea AK |
6688 | [(set_attr "op_type" "RRE,RRF,RXY") |
6689 | (set_attr "cpu_facility" "*,z196,*") | |
6690 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6691 | |
3af8e996 | 6692 | (define_insn "*xordi3" |
65b1d8ea AK |
6693 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
6694 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
6695 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 6696 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6697 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6698 | "@ |
6699 | xihf\t%0,%k2 | |
6700 | xilf\t%0,%k2 | |
6701 | xgr\t%0,%2 | |
65b1d8ea | 6702 | xgrk\t%0,%1,%2 |
ec24698e UW |
6703 | xg\t%0,%2 |
6704 | # | |
6705 | #" | |
65b1d8ea AK |
6706 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
6707 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
6708 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
6709 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6710 | |
6711 | (define_split | |
6712 | [(set (match_operand:DI 0 "s_operand" "") | |
6713 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6714 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6715 | "reload_completed" |
6716 | [(parallel | |
6717 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6718 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6719 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 6720 | |
9db1d521 HP |
6721 | ; |
6722 | ; xorsi3 instruction pattern(s). | |
6723 | ; | |
6724 | ||
4023fb28 | 6725 | (define_insn "*xorsi3_cc" |
ae156f85 | 6726 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6727 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6728 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6729 | (const_int 0))) |
65b1d8ea | 6730 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6731 | (xor:SI (match_dup 1) (match_dup 2)))] |
6732 | "s390_match_ccmode(insn, CCTmode)" | |
6733 | "@ | |
ec24698e | 6734 | xilf\t%0,%o2 |
d40c829f | 6735 | xr\t%0,%2 |
65b1d8ea | 6736 | xrk\t%0,%1,%2 |
d40c829f UW |
6737 | x\t%0,%2 |
6738 | xy\t%0,%2" | |
65b1d8ea AK |
6739 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6740 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6741 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6742 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6743 | |
6744 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 6745 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6746 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6747 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6748 | (const_int 0))) |
65b1d8ea | 6749 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6750 | "s390_match_ccmode(insn, CCTmode)" |
6751 | "@ | |
ec24698e | 6752 | xilf\t%0,%o2 |
d40c829f | 6753 | xr\t%0,%2 |
65b1d8ea | 6754 | xrk\t%0,%1,%2 |
d40c829f UW |
6755 | x\t%0,%2 |
6756 | xy\t%0,%2" | |
65b1d8ea AK |
6757 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6758 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6759 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6760 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6761 | |
8cb66696 | 6762 | (define_insn "*xorsi3" |
65b1d8ea AK |
6763 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
6764 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
6765 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6766 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6767 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6768 | "@ |
ec24698e | 6769 | xilf\t%0,%o2 |
d40c829f | 6770 | xr\t%0,%2 |
65b1d8ea | 6771 | xrk\t%0,%1,%2 |
d40c829f | 6772 | x\t%0,%2 |
8cb66696 | 6773 | xy\t%0,%2 |
0dfa6c5e | 6774 | # |
19b63d8e | 6775 | #" |
65b1d8ea AK |
6776 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
6777 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
6778 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6779 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6780 | |
6781 | (define_split | |
6782 | [(set (match_operand:SI 0 "s_operand" "") | |
6783 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6784 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6785 | "reload_completed" |
6786 | [(parallel | |
6787 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6788 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6789 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 6790 | |
9db1d521 HP |
6791 | ; |
6792 | ; xorhi3 instruction pattern(s). | |
6793 | ; | |
6794 | ||
8cb66696 | 6795 | (define_insn "*xorhi3" |
65b1d8ea AK |
6796 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6797 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
6798 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 6799 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6800 | "s390_logical_operator_ok_p (operands)" |
6801 | "@ | |
ec24698e | 6802 | xilf\t%0,%x2 |
8cb66696 | 6803 | xr\t%0,%2 |
65b1d8ea | 6804 | xrk\t%0,%1,%2 |
0dfa6c5e | 6805 | # |
19b63d8e | 6806 | #" |
65b1d8ea AK |
6807 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
6808 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6809 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
6810 | |
6811 | (define_split | |
6812 | [(set (match_operand:HI 0 "s_operand" "") | |
6813 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6814 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6815 | "reload_completed" |
6816 | [(parallel | |
6817 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6818 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6819 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 6820 | |
9db1d521 HP |
6821 | ; |
6822 | ; xorqi3 instruction pattern(s). | |
6823 | ; | |
6824 | ||
8cb66696 | 6825 | (define_insn "*xorqi3" |
65b1d8ea AK |
6826 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6827 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
6828 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 6829 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6830 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6831 | "@ |
ec24698e | 6832 | xilf\t%0,%b2 |
8cb66696 | 6833 | xr\t%0,%2 |
65b1d8ea | 6834 | xrk\t%0,%1,%2 |
fc0ea003 UW |
6835 | xi\t%S0,%b2 |
6836 | xiy\t%S0,%b2 | |
19b63d8e | 6837 | #" |
65b1d8ea AK |
6838 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
6839 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
6840 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 6841 | |
4023fb28 | 6842 | |
19b63d8e UW |
6843 | ; |
6844 | ; Block exclusive or (XC) patterns. | |
6845 | ; | |
6846 | ||
6847 | (define_insn "*xc" | |
6848 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6849 | (xor:BLK (match_dup 0) | |
6850 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6851 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6852 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6853 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6854 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 6855 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6856 | |
6857 | (define_split | |
6858 | [(set (match_operand 0 "memory_operand" "") | |
6859 | (xor (match_dup 0) | |
6860 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6861 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6862 | "reload_completed |
6863 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6864 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6865 | [(parallel | |
6866 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
6867 | (use (match_dup 2)) | |
ae156f85 | 6868 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6869 | { |
6870 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6871 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6872 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6873 | }) | |
6874 | ||
6875 | (define_peephole2 | |
6876 | [(parallel | |
6877 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6878 | (xor:BLK (match_dup 0) | |
6879 | (match_operand:BLK 1 "memory_operand" ""))) | |
6880 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6881 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6882 | (parallel |
6883 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6884 | (xor:BLK (match_dup 3) | |
6885 | (match_operand:BLK 4 "memory_operand" ""))) | |
6886 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6887 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6888 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6889 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6890 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6891 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6892 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6893 | [(parallel | |
6894 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
6895 | (use (match_dup 8)) | |
ae156f85 | 6896 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6897 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6898 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6899 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6900 | ||
6901 | ; | |
6902 | ; Block xor (XC) patterns with src == dest. | |
6903 | ; | |
6904 | ||
6905 | (define_insn "*xc_zero" | |
6906 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6907 | (const_int 0)) | |
6908 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 6909 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6910 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 6911 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
6912 | [(set_attr "op_type" "SS") |
6913 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6914 | |
6915 | (define_peephole2 | |
6916 | [(parallel | |
6917 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6918 | (const_int 0)) | |
6919 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 6920 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6921 | (parallel |
6922 | [(set (match_operand:BLK 2 "memory_operand" "") | |
6923 | (const_int 0)) | |
6924 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 6925 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6926 | "s390_offset_p (operands[0], operands[2], operands[1]) |
6927 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
6928 | [(parallel | |
6929 | [(set (match_dup 4) (const_int 0)) | |
6930 | (use (match_dup 5)) | |
ae156f85 | 6931 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6932 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6933 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
6934 | ||
9db1d521 HP |
6935 | |
6936 | ;; | |
6937 | ;;- Negate instructions. | |
6938 | ;; | |
6939 | ||
6940 | ; | |
9a91a21f | 6941 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
6942 | ; |
6943 | ||
9a91a21f | 6944 | (define_expand "neg<mode>2" |
9db1d521 | 6945 | [(parallel |
9a91a21f AS |
6946 | [(set (match_operand:DSI 0 "register_operand" "=d") |
6947 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 6948 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6949 | "" |
6950 | "") | |
6951 | ||
26a89301 | 6952 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 6953 | [(set (reg CC_REGNUM) |
26a89301 UW |
6954 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6955 | (match_operand:SI 1 "register_operand" "d") 0) | |
6956 | (const_int 32)) (const_int 32))) | |
6957 | (const_int 0))) | |
6958 | (set (match_operand:DI 0 "register_operand" "=d") | |
6959 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 6960 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 6961 | "lcgfr\t%0,%1" |
729e750f WG |
6962 | [(set_attr "op_type" "RRE") |
6963 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 6964 | |
26a89301 UW |
6965 | (define_insn "*negdi2_sign" |
6966 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6967 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 6968 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6969 | "TARGET_ZARCH" |
26a89301 | 6970 | "lcgfr\t%0,%1" |
729e750f WG |
6971 | [(set_attr "op_type" "RRE") |
6972 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6973 | |
43a09b63 | 6974 | ; lcr, lcgr |
9a91a21f | 6975 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 6976 | [(set (reg CC_REGNUM) |
9a91a21f | 6977 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6978 | (const_int 0))) |
9a91a21f AS |
6979 | (set (match_operand:GPR 0 "register_operand" "=d") |
6980 | (neg:GPR (match_dup 1)))] | |
6981 | "s390_match_ccmode (insn, CCAmode)" | |
6982 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6983 | [(set_attr "op_type" "RR<E>") |
6984 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6985 | |
6986 | ; lcr, lcgr | |
9a91a21f | 6987 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 6988 | [(set (reg CC_REGNUM) |
9a91a21f | 6989 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6990 | (const_int 0))) |
9a91a21f AS |
6991 | (clobber (match_scratch:GPR 0 "=d"))] |
6992 | "s390_match_ccmode (insn, CCAmode)" | |
6993 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6994 | [(set_attr "op_type" "RR<E>") |
6995 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6996 | |
6997 | ; lcr, lcgr | |
9a91a21f AS |
6998 | (define_insn "*neg<mode>2" |
6999 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7000 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7001 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
7002 | "" |
7003 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7004 | [(set_attr "op_type" "RR<E>") |
7005 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 7006 | |
26a89301 | 7007 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
7008 | [(set (match_operand:DI 0 "register_operand" "=d") |
7009 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 7010 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7011 | "!TARGET_ZARCH" |
26a89301 UW |
7012 | "#" |
7013 | "&& reload_completed" | |
7014 | [(parallel | |
7015 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 7016 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 7017 | (parallel |
ae156f85 | 7018 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
7019 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
7020 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
7021 | (set (pc) | |
ae156f85 | 7022 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
7023 | (pc) |
7024 | (label_ref (match_dup 6)))) | |
7025 | (parallel | |
7026 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 7027 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
7028 | (match_dup 6)] |
7029 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7030 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7031 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7032 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7033 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 7034 | |
9db1d521 | 7035 | ; |
f5905b37 | 7036 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7037 | ; |
7038 | ||
f5905b37 | 7039 | (define_expand "neg<mode>2" |
9db1d521 | 7040 | [(parallel |
7b6baae1 AK |
7041 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7042 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7043 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7044 | "TARGET_HARD_FLOAT" |
7045 | "") | |
7046 | ||
43a09b63 | 7047 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7048 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7049 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7050 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7051 | (match_operand:BFP 2 "const0_operand" ""))) | |
7052 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7053 | (neg:BFP (match_dup 1)))] | |
142cd70f | 7054 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7055 | "lc<xde>br\t%0,%1" |
26a89301 | 7056 | [(set_attr "op_type" "RRE") |
f5905b37 | 7057 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7058 | |
7059 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 7060 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7061 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7062 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7063 | (match_operand:BFP 2 "const0_operand" ""))) | |
7064 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7065 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7066 | "lc<xde>br\t%0,%1" |
26a89301 | 7067 | [(set_attr "op_type" "RRE") |
f5905b37 | 7068 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7069 | |
85dae55a AK |
7070 | ; lcdfr |
7071 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
7072 | [(set (match_operand:FP 0 "register_operand" "=f") |
7073 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7074 | "TARGET_DFP" |
85dae55a AK |
7075 | "lcdfr\t%0,%1" |
7076 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7077 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7078 | |
43a09b63 | 7079 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7080 | (define_insn "*neg<mode>2" |
7b6baae1 AK |
7081 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7082 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7083 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7084 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7085 | "lc<xde>br\t%0,%1" |
077dab3b | 7086 | [(set_attr "op_type" "RRE") |
f5905b37 | 7087 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7088 | |
9db1d521 HP |
7089 | |
7090 | ;; | |
7091 | ;;- Absolute value instructions. | |
7092 | ;; | |
7093 | ||
7094 | ; | |
9a91a21f | 7095 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
7096 | ; |
7097 | ||
26a89301 | 7098 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 7099 | [(set (reg CC_REGNUM) |
26a89301 UW |
7100 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7101 | (match_operand:SI 1 "register_operand" "d") 0) | |
7102 | (const_int 32)) (const_int 32))) | |
7103 | (const_int 0))) | |
7104 | (set (match_operand:DI 0 "register_operand" "=d") | |
7105 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7106 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7107 | "lpgfr\t%0,%1" |
729e750f WG |
7108 | [(set_attr "op_type" "RRE") |
7109 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
7110 | |
7111 | (define_insn "*absdi2_sign" | |
7112 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7113 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7114 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7115 | "TARGET_ZARCH" |
26a89301 | 7116 | "lpgfr\t%0,%1" |
729e750f WG |
7117 | [(set_attr "op_type" "RRE") |
7118 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7119 | |
43a09b63 | 7120 | ; lpr, lpgr |
9a91a21f | 7121 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7122 | [(set (reg CC_REGNUM) |
9a91a21f | 7123 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 7124 | (const_int 0))) |
9a91a21f AS |
7125 | (set (match_operand:GPR 0 "register_operand" "=d") |
7126 | (abs:GPR (match_dup 1)))] | |
26a89301 | 7127 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7128 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7129 | [(set_attr "op_type" "RR<E>") |
7130 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 7131 | |
9381e3f1 | 7132 | ; lpr, lpgr |
9a91a21f | 7133 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7134 | [(set (reg CC_REGNUM) |
9a91a21f | 7135 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7136 | (const_int 0))) |
9a91a21f | 7137 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7138 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7139 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7140 | [(set_attr "op_type" "RR<E>") |
7141 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7142 | |
7143 | ; lpr, lpgr | |
9a91a21f AS |
7144 | (define_insn "abs<mode>2" |
7145 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7146 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7147 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 7148 | "" |
9a91a21f | 7149 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7150 | [(set_attr "op_type" "RR<E>") |
7151 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 7152 | |
9db1d521 | 7153 | ; |
f5905b37 | 7154 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7155 | ; |
7156 | ||
f5905b37 | 7157 | (define_expand "abs<mode>2" |
9db1d521 | 7158 | [(parallel |
7b6baae1 AK |
7159 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7160 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7161 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7162 | "TARGET_HARD_FLOAT" |
7163 | "") | |
7164 | ||
43a09b63 | 7165 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7166 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7167 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7168 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7169 | (match_operand:BFP 2 "const0_operand" ""))) | |
7170 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7171 | (abs:BFP (match_dup 1)))] | |
142cd70f | 7172 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7173 | "lp<xde>br\t%0,%1" |
26a89301 | 7174 | [(set_attr "op_type" "RRE") |
f5905b37 | 7175 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7176 | |
7177 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 7178 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7179 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7180 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7181 | (match_operand:BFP 2 "const0_operand" ""))) | |
7182 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7183 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7184 | "lp<xde>br\t%0,%1" |
26a89301 | 7185 | [(set_attr "op_type" "RRE") |
f5905b37 | 7186 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7187 | |
85dae55a AK |
7188 | ; lpdfr |
7189 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
7190 | [(set (match_operand:FP 0 "register_operand" "=f") |
7191 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7192 | "TARGET_DFP" |
85dae55a AK |
7193 | "lpdfr\t%0,%1" |
7194 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7195 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7196 | |
43a09b63 | 7197 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7198 | (define_insn "*abs<mode>2" |
7b6baae1 AK |
7199 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7200 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7201 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7202 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7203 | "lp<xde>br\t%0,%1" |
077dab3b | 7204 | [(set_attr "op_type" "RRE") |
f5905b37 | 7205 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7206 | |
9db1d521 | 7207 | |
3ef093a8 AK |
7208 | ;; |
7209 | ;;- Negated absolute value instructions | |
7210 | ;; | |
7211 | ||
7212 | ; | |
7213 | ; Integer | |
7214 | ; | |
7215 | ||
26a89301 | 7216 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 7217 | [(set (reg CC_REGNUM) |
26a89301 UW |
7218 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7219 | (match_operand:SI 1 "register_operand" "d") 0) | |
7220 | (const_int 32)) (const_int 32)))) | |
7221 | (const_int 0))) | |
7222 | (set (match_operand:DI 0 "register_operand" "=d") | |
7223 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 7224 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7225 | "lngfr\t%0,%1" |
729e750f WG |
7226 | [(set_attr "op_type" "RRE") |
7227 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7228 | |
26a89301 UW |
7229 | (define_insn "*negabsdi2_sign" |
7230 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7231 | (neg:DI (abs:DI (sign_extend:DI | |
7232 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 7233 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7234 | "TARGET_ZARCH" |
26a89301 | 7235 | "lngfr\t%0,%1" |
729e750f WG |
7236 | [(set_attr "op_type" "RRE") |
7237 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 7238 | |
43a09b63 | 7239 | ; lnr, lngr |
9a91a21f | 7240 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7241 | [(set (reg CC_REGNUM) |
9a91a21f | 7242 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7243 | (const_int 0))) |
9a91a21f AS |
7244 | (set (match_operand:GPR 0 "register_operand" "=d") |
7245 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 7246 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7247 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7248 | [(set_attr "op_type" "RR<E>") |
7249 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7250 | |
7251 | ; lnr, lngr | |
9a91a21f | 7252 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7253 | [(set (reg CC_REGNUM) |
9a91a21f | 7254 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7255 | (const_int 0))) |
9a91a21f | 7256 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7257 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7258 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7259 | [(set_attr "op_type" "RR<E>") |
7260 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7261 | |
7262 | ; lnr, lngr | |
9a91a21f AS |
7263 | (define_insn "*negabs<mode>2" |
7264 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7265 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 7266 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 7267 | "" |
9a91a21f | 7268 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7269 | [(set_attr "op_type" "RR<E>") |
7270 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7271 | |
3ef093a8 AK |
7272 | ; |
7273 | ; Floating point | |
7274 | ; | |
7275 | ||
43a09b63 | 7276 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7277 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7278 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7279 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7280 | (match_operand:BFP 2 "const0_operand" ""))) | |
7281 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7282 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 7283 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7284 | "ln<xde>br\t%0,%1" |
26a89301 | 7285 | [(set_attr "op_type" "RRE") |
f5905b37 | 7286 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7287 | |
7288 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 7289 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7290 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7291 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7292 | (match_operand:BFP 2 "const0_operand" ""))) | |
7293 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7294 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7295 | "ln<xde>br\t%0,%1" |
26a89301 | 7296 | [(set_attr "op_type" "RRE") |
f5905b37 | 7297 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7298 | |
85dae55a AK |
7299 | ; lndfr |
7300 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
7301 | [(set (match_operand:FP 0 "register_operand" "=f") |
7302 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 7303 | "TARGET_DFP" |
85dae55a AK |
7304 | "lndfr\t%0,%1" |
7305 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7306 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7307 | |
43a09b63 | 7308 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7309 | (define_insn "*negabs<mode>2" |
7b6baae1 AK |
7310 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7311 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))) | |
ae156f85 | 7312 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7313 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7314 | "ln<xde>br\t%0,%1" |
26a89301 | 7315 | [(set_attr "op_type" "RRE") |
f5905b37 | 7316 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 7317 | |
4023fb28 UW |
7318 | ;; |
7319 | ;;- Square root instructions. | |
7320 | ;; | |
7321 | ||
7322 | ; | |
f5905b37 | 7323 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
7324 | ; |
7325 | ||
9381e3f1 | 7326 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 7327 | (define_insn "sqrt<mode>2" |
7b6baae1 AK |
7328 | [(set (match_operand:BFP 0 "register_operand" "=f,f") |
7329 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 7330 | "TARGET_HARD_FLOAT" |
4023fb28 | 7331 | "@ |
f61a2c7d AK |
7332 | sq<xde>br\t%0,%1 |
7333 | sq<xde>b\t%0,%1" | |
a036c6f7 | 7334 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 7335 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 7336 | |
9db1d521 HP |
7337 | |
7338 | ;; | |
7339 | ;;- One complement instructions. | |
7340 | ;; | |
7341 | ||
7342 | ; | |
342cf42b | 7343 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 7344 | ; |
c7453384 | 7345 | |
342cf42b | 7346 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 7347 | [(parallel |
342cf42b AS |
7348 | [(set (match_operand:INT 0 "register_operand" "") |
7349 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
7350 | (const_int -1))) | |
ae156f85 | 7351 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 7352 | "" |
4023fb28 | 7353 | "") |
9db1d521 HP |
7354 | |
7355 | ||
ec24698e UW |
7356 | ;; |
7357 | ;; Find leftmost bit instructions. | |
7358 | ;; | |
7359 | ||
7360 | (define_expand "clzdi2" | |
7361 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7362 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 7363 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7364 | { |
7365 | rtx insn, clz_equal; | |
7366 | rtx wide_reg = gen_reg_rtx (TImode); | |
7367 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
7368 | ||
7369 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
7370 | ||
7371 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
7372 | ||
9381e3f1 | 7373 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 7374 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
7375 | |
7376 | DONE; | |
7377 | }) | |
7378 | ||
7379 | (define_insn "clztidi2" | |
7380 | [(set (match_operand:TI 0 "register_operand" "=d") | |
7381 | (ior:TI | |
9381e3f1 WG |
7382 | (ashift:TI |
7383 | (zero_extend:TI | |
ec24698e UW |
7384 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
7385 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
7386 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 7387 | |
ec24698e UW |
7388 | (const_int 64)) |
7389 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
7390 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 7391 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 7392 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 7393 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7394 | "flogr\t%0,%1" |
7395 | [(set_attr "op_type" "RRE")]) | |
7396 | ||
7397 | ||
9db1d521 HP |
7398 | ;; |
7399 | ;;- Rotate instructions. | |
7400 | ;; | |
7401 | ||
7402 | ; | |
9a91a21f | 7403 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
7404 | ; |
7405 | ||
43a09b63 | 7406 | ; rll, rllg |
9a91a21f AS |
7407 | (define_insn "rotl<mode>3" |
7408 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7409 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 7410 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 7411 | "TARGET_CPU_ZARCH" |
9a91a21f | 7412 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 7413 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
7414 | (set_attr "atype" "reg") |
7415 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7416 | |
43a09b63 | 7417 | ; rll, rllg |
4989e88a AK |
7418 | (define_insn "*rotl<mode>3_and" |
7419 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7420 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7421 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7422 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7423 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
7424 | "rll<g>\t%0,%1,%Y2" | |
7425 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
7426 | (set_attr "atype" "reg") |
7427 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7428 | |
9db1d521 HP |
7429 | |
7430 | ;; | |
f337b930 | 7431 | ;;- Shift instructions. |
9db1d521 | 7432 | ;; |
9db1d521 HP |
7433 | |
7434 | ; | |
1b48c8cc | 7435 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 7436 | ; Left shifts and logical right shifts |
9db1d521 | 7437 | |
1b48c8cc AS |
7438 | (define_expand "<shift><mode>3" |
7439 | [(set (match_operand:DSI 0 "register_operand" "") | |
7440 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
7441 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
7442 | "" |
7443 | "") | |
7444 | ||
43a09b63 | 7445 | ; sldl, srdl |
f337b930 | 7446 | (define_insn "*<shift>di3_31" |
ac32b25e | 7447 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 7448 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7449 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9602b6a1 | 7450 | "!TARGET_ZARCH" |
f337b930 | 7451 | "s<lr>dl\t%0,%Y2" |
077dab3b | 7452 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
7453 | (set_attr "atype" "reg") |
7454 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 7455 | |
65b1d8ea | 7456 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7457 | (define_insn "*<shift><mode>3" |
65b1d8ea AK |
7458 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7459 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7460 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] | |
1b48c8cc | 7461 | "" |
65b1d8ea AK |
7462 | "@ |
7463 | s<lr>l<g>\t%0,<1>%Y2 | |
7464 | s<lr>l<gk>\t%0,%1,%Y2" | |
7465 | [(set_attr "op_type" "RS<E>,RSY") | |
7466 | (set_attr "atype" "reg,reg") | |
7467 | (set_attr "cpu_facility" "*,z196") | |
7468 | (set_attr "z10prop" "z10_super_E1,*")]) | |
9db1d521 | 7469 | |
43a09b63 | 7470 | ; sldl, srdl |
4989e88a AK |
7471 | (define_insn "*<shift>di3_31_and" |
7472 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7473 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7474 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7475 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
9602b6a1 | 7476 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7477 | "s<lr>dl\t%0,%Y2" |
7478 | [(set_attr "op_type" "RS") | |
7479 | (set_attr "atype" "reg")]) | |
7480 | ||
65b1d8ea | 7481 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7482 | (define_insn "*<shift><mode>3_and" |
65b1d8ea AK |
7483 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7484 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7485 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7486 | (match_operand:SI 3 "const_int_operand" "n,n"))))] | |
1b48c8cc | 7487 | "(INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7488 | "@ |
7489 | s<lr>l<g>\t%0,<1>%Y2 | |
7490 | s<lr>l<gk>\t%0,%1,%Y2" | |
7491 | [(set_attr "op_type" "RS<E>,RSY") | |
7492 | (set_attr "atype" "reg,reg") | |
7493 | (set_attr "cpu_facility" "*,z196") | |
7494 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7495 | |
9db1d521 | 7496 | ; |
1b48c8cc | 7497 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 7498 | ; Arithmetic right shifts |
9db1d521 | 7499 | |
1b48c8cc | 7500 | (define_expand "ashr<mode>3" |
9db1d521 | 7501 | [(parallel |
1b48c8cc AS |
7502 | [(set (match_operand:DSI 0 "register_operand" "") |
7503 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
7504 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 7505 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7506 | "" |
7507 | "") | |
7508 | ||
ecbe845e | 7509 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 7510 | [(set (reg CC_REGNUM) |
ac32b25e | 7511 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7512 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7513 | (const_int 0))) |
ac32b25e | 7514 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e | 7515 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7516 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7517 | "srda\t%0,%Y2" |
077dab3b HP |
7518 | [(set_attr "op_type" "RS") |
7519 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
7520 | |
7521 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 7522 | [(set (reg CC_REGNUM) |
ac32b25e | 7523 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7524 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7525 | (const_int 0))) |
ac32b25e | 7526 | (clobber (match_scratch:DI 0 "=d"))] |
9602b6a1 | 7527 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7528 | "srda\t%0,%Y2" |
077dab3b HP |
7529 | [(set_attr "op_type" "RS") |
7530 | (set_attr "atype" "reg")]) | |
ecbe845e | 7531 | |
9db1d521 | 7532 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
7533 | [(set (match_operand:DI 0 "register_operand" "=d") |
7534 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 7535 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 7536 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7537 | "!TARGET_ZARCH" |
ac32b25e | 7538 | "srda\t%0,%Y2" |
077dab3b HP |
7539 | [(set_attr "op_type" "RS") |
7540 | (set_attr "atype" "reg")]) | |
c7453384 | 7541 | |
65b1d8ea | 7542 | ; sra, srag, srak |
1b48c8cc | 7543 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 7544 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7545 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7546 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7547 | (const_int 0))) |
65b1d8ea | 7548 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc AS |
7549 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] |
7550 | "s390_match_ccmode(insn, CCSmode)" | |
65b1d8ea AK |
7551 | "@ |
7552 | sra<g>\t%0,<1>%Y2 | |
7553 | sra<gk>\t%0,%1,%Y2" | |
7554 | [(set_attr "op_type" "RS<E>,RSY") | |
7555 | (set_attr "atype" "reg,reg") | |
7556 | (set_attr "cpu_facility" "*,z196") | |
7557 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7558 | |
65b1d8ea | 7559 | ; sra, srag, srak |
1b48c8cc | 7560 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 7561 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7562 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7563 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7564 | (const_int 0))) |
65b1d8ea | 7565 | (clobber (match_scratch:GPR 0 "=d,d"))] |
1b48c8cc | 7566 | "s390_match_ccmode(insn, CCSmode)" |
65b1d8ea AK |
7567 | "@ |
7568 | sra<g>\t%0,<1>%Y2 | |
7569 | sra<gk>\t%0,%1,%Y2" | |
7570 | [(set_attr "op_type" "RS<E>,RSY") | |
7571 | (set_attr "atype" "reg,reg") | |
7572 | (set_attr "cpu_facility" "*,z196") | |
7573 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7574 | |
43a09b63 | 7575 | ; sra, srag |
1b48c8cc | 7576 | (define_insn "*ashr<mode>3" |
65b1d8ea AK |
7577 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7578 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7579 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) | |
ae156f85 | 7580 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 7581 | "" |
65b1d8ea AK |
7582 | "@ |
7583 | sra<g>\t%0,<1>%Y2 | |
7584 | sra<gk>\t%0,%1,%Y2" | |
7585 | [(set_attr "op_type" "RS<E>,RSY") | |
7586 | (set_attr "atype" "reg,reg") | |
7587 | (set_attr "cpu_facility" "*,z196") | |
7588 | (set_attr "z10prop" "z10_super_E1,*")]) | |
077dab3b | 7589 | |
9db1d521 | 7590 | |
4989e88a AK |
7591 | ; shift pattern with implicit ANDs |
7592 | ||
7593 | (define_insn "*ashrdi3_cc_31_and" | |
7594 | [(set (reg CC_REGNUM) | |
7595 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7596 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7597 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7598 | (const_int 0))) | |
7599 | (set (match_operand:DI 0 "register_operand" "=d") | |
7600 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
9602b6a1 | 7601 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7602 | && (INTVAL (operands[3]) & 63) == 63" |
7603 | "srda\t%0,%Y2" | |
7604 | [(set_attr "op_type" "RS") | |
7605 | (set_attr "atype" "reg")]) | |
7606 | ||
7607 | (define_insn "*ashrdi3_cconly_31_and" | |
7608 | [(set (reg CC_REGNUM) | |
7609 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7610 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7611 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7612 | (const_int 0))) | |
7613 | (clobber (match_scratch:DI 0 "=d"))] | |
9602b6a1 | 7614 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7615 | && (INTVAL (operands[3]) & 63) == 63" |
7616 | "srda\t%0,%Y2" | |
7617 | [(set_attr "op_type" "RS") | |
7618 | (set_attr "atype" "reg")]) | |
7619 | ||
7620 | (define_insn "*ashrdi3_31_and" | |
7621 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7622 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7623 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7624 | (match_operand:SI 3 "const_int_operand" "n")))) | |
7625 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 7626 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7627 | "srda\t%0,%Y2" |
7628 | [(set_attr "op_type" "RS") | |
7629 | (set_attr "atype" "reg")]) | |
7630 | ||
65b1d8ea | 7631 | ; sra, srag, srak |
1b48c8cc | 7632 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 7633 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7634 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7635 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7636 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7637 | (const_int 0))) |
65b1d8ea | 7638 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc | 7639 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] |
4989e88a | 7640 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7641 | "@ |
7642 | sra<g>\t%0,<1>%Y2 | |
7643 | sra<gk>\t%0,%1,%Y2" | |
7644 | [(set_attr "op_type" "RS<E>,RSY") | |
7645 | (set_attr "atype" "reg,reg") | |
7646 | (set_attr "cpu_facility" "*,z196") | |
7647 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7648 | |
65b1d8ea | 7649 | ; sra, srag, srak |
1b48c8cc | 7650 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 7651 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7652 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7653 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7654 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7655 | (const_int 0))) |
65b1d8ea | 7656 | (clobber (match_scratch:GPR 0 "=d,d"))] |
4989e88a | 7657 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7658 | "@ |
7659 | sra<g>\t%0,<1>%Y2 | |
7660 | sra<gk>\t%0,%1,%Y2" | |
7661 | [(set_attr "op_type" "RS<E>,RSY") | |
7662 | (set_attr "atype" "reg,reg") | |
7663 | (set_attr "cpu_facility" "*,z196") | |
7664 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7665 | |
65b1d8ea | 7666 | ; sra, srag, srak |
1b48c8cc | 7667 | (define_insn "*ashr<mode>3_and" |
65b1d8ea AK |
7668 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7669 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7670 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7671 | (match_operand:SI 3 "const_int_operand" "n,n")))) | |
4989e88a AK |
7672 | (clobber (reg:CC CC_REGNUM))] |
7673 | "(INTVAL (operands[3]) & 63) == 63" | |
65b1d8ea AK |
7674 | "@ |
7675 | sra<g>\t%0,<1>%Y2 | |
7676 | sra<gk>\t%0,%1,%Y2" | |
7677 | [(set_attr "op_type" "RS<E>,RSY") | |
7678 | (set_attr "atype" "reg,reg") | |
01496eca | 7679 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 7680 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 7681 | |
9db1d521 | 7682 | |
9db1d521 HP |
7683 | ;; |
7684 | ;; Branch instruction patterns. | |
7685 | ;; | |
7686 | ||
f90b7a5a | 7687 | (define_expand "cbranch<mode>4" |
fa77b251 | 7688 | [(set (pc) |
f90b7a5a PB |
7689 | (if_then_else (match_operator 0 "comparison_operator" |
7690 | [(match_operand:GPR 1 "register_operand" "") | |
7691 | (match_operand:GPR 2 "general_operand" "")]) | |
7692 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 7693 | (pc)))] |
ba956982 | 7694 | "" |
f90b7a5a PB |
7695 | "s390_emit_jump (operands[3], |
7696 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7697 | DONE;") | |
7698 | ||
7699 | (define_expand "cbranch<mode>4" | |
7700 | [(set (pc) | |
7701 | (if_then_else (match_operator 0 "comparison_operator" | |
7702 | [(match_operand:FP 1 "register_operand" "") | |
7703 | (match_operand:FP 2 "general_operand" "")]) | |
7704 | (label_ref (match_operand 3 "" "")) | |
7705 | (pc)))] | |
7706 | "TARGET_HARD_FLOAT" | |
7707 | "s390_emit_jump (operands[3], | |
7708 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7709 | DONE;") | |
7710 | ||
7711 | (define_expand "cbranchcc4" | |
7712 | [(set (pc) | |
7713 | (if_then_else (match_operator 0 "s390_eqne_operator" | |
7714 | [(match_operand 1 "cc_reg_operand" "") | |
7715 | (match_operand 2 "const0_operand" "")]) | |
7716 | (label_ref (match_operand 3 "" "")) | |
7717 | (pc)))] | |
7718 | "TARGET_HARD_FLOAT" | |
7719 | "s390_emit_jump (operands[3], | |
7720 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7721 | DONE;") | |
7722 | ||
ba956982 | 7723 | |
9db1d521 HP |
7724 | |
7725 | ;; | |
7726 | ;;- Conditional jump instructions. | |
7727 | ;; | |
7728 | ||
6590e19a UW |
7729 | (define_insn "*cjump_64" |
7730 | [(set (pc) | |
7731 | (if_then_else | |
ae156f85 | 7732 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7733 | (label_ref (match_operand 0 "" "")) |
7734 | (pc)))] | |
7735 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7736 | { |
13e58269 | 7737 | if (get_attr_length (insn) == 4) |
d40c829f | 7738 | return "j%C1\t%l0"; |
6590e19a | 7739 | else |
d40c829f | 7740 | return "jg%C1\t%l0"; |
6590e19a UW |
7741 | } |
7742 | [(set_attr "op_type" "RI") | |
7743 | (set_attr "type" "branch") | |
7744 | (set (attr "length") | |
7745 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7746 | (const_int 4) (const_int 6)))]) | |
7747 | ||
7748 | (define_insn "*cjump_31" | |
7749 | [(set (pc) | |
7750 | (if_then_else | |
ae156f85 | 7751 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7752 | (label_ref (match_operand 0 "" "")) |
7753 | (pc)))] | |
7754 | "!TARGET_CPU_ZARCH" | |
7755 | { | |
8d933e31 AS |
7756 | gcc_assert (get_attr_length (insn) == 4); |
7757 | return "j%C1\t%l0"; | |
10bbf137 | 7758 | } |
9db1d521 | 7759 | [(set_attr "op_type" "RI") |
077dab3b | 7760 | (set_attr "type" "branch") |
13e58269 | 7761 | (set (attr "length") |
d7f99b2c | 7762 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
7763 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
7764 | (const_int 4) (const_int 6)) | |
7765 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7766 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7767 | |
f314b9b1 | 7768 | (define_insn "*cjump_long" |
6590e19a UW |
7769 | [(set (pc) |
7770 | (if_then_else | |
ae156f85 | 7771 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 7772 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 7773 | (pc)))] |
9db1d521 | 7774 | "" |
f314b9b1 UW |
7775 | { |
7776 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7777 | return "b%C1r\t%0"; |
f314b9b1 | 7778 | else |
d40c829f | 7779 | return "b%C1\t%a0"; |
10bbf137 | 7780 | } |
c7453384 | 7781 | [(set (attr "op_type") |
f314b9b1 UW |
7782 | (if_then_else (match_operand 0 "register_operand" "") |
7783 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 7784 | (set_attr "type" "branch") |
077dab3b | 7785 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7786 | |
7787 | ||
7788 | ;; | |
7789 | ;;- Negated conditional jump instructions. | |
7790 | ;; | |
7791 | ||
6590e19a UW |
7792 | (define_insn "*icjump_64" |
7793 | [(set (pc) | |
7794 | (if_then_else | |
ae156f85 | 7795 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7796 | (pc) |
7797 | (label_ref (match_operand 0 "" ""))))] | |
7798 | "TARGET_CPU_ZARCH" | |
c7453384 | 7799 | { |
13e58269 | 7800 | if (get_attr_length (insn) == 4) |
d40c829f | 7801 | return "j%D1\t%l0"; |
6590e19a | 7802 | else |
d40c829f | 7803 | return "jg%D1\t%l0"; |
6590e19a UW |
7804 | } |
7805 | [(set_attr "op_type" "RI") | |
7806 | (set_attr "type" "branch") | |
7807 | (set (attr "length") | |
7808 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7809 | (const_int 4) (const_int 6)))]) | |
7810 | ||
7811 | (define_insn "*icjump_31" | |
7812 | [(set (pc) | |
7813 | (if_then_else | |
ae156f85 | 7814 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7815 | (pc) |
7816 | (label_ref (match_operand 0 "" ""))))] | |
7817 | "!TARGET_CPU_ZARCH" | |
7818 | { | |
8d933e31 AS |
7819 | gcc_assert (get_attr_length (insn) == 4); |
7820 | return "j%D1\t%l0"; | |
10bbf137 | 7821 | } |
9db1d521 | 7822 | [(set_attr "op_type" "RI") |
077dab3b | 7823 | (set_attr "type" "branch") |
13e58269 | 7824 | (set (attr "length") |
d7f99b2c | 7825 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
7826 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
7827 | (const_int 4) (const_int 6)) | |
7828 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7829 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7830 | |
f314b9b1 | 7831 | (define_insn "*icjump_long" |
6590e19a UW |
7832 | [(set (pc) |
7833 | (if_then_else | |
ae156f85 | 7834 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 7835 | (pc) |
4fe6dea8 | 7836 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 7837 | "" |
f314b9b1 UW |
7838 | { |
7839 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7840 | return "b%D1r\t%0"; |
f314b9b1 | 7841 | else |
d40c829f | 7842 | return "b%D1\t%a0"; |
10bbf137 | 7843 | } |
c7453384 | 7844 | [(set (attr "op_type") |
f314b9b1 UW |
7845 | (if_then_else (match_operand 0 "register_operand" "") |
7846 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7847 | (set_attr "type" "branch") |
7848 | (set_attr "atype" "agen")]) | |
9db1d521 | 7849 | |
4456530d HP |
7850 | ;; |
7851 | ;;- Trap instructions. | |
7852 | ;; | |
7853 | ||
7854 | (define_insn "trap" | |
7855 | [(trap_if (const_int 1) (const_int 0))] | |
7856 | "" | |
d40c829f | 7857 | "j\t.+2" |
6590e19a | 7858 | [(set_attr "op_type" "RI") |
077dab3b | 7859 | (set_attr "type" "branch")]) |
4456530d | 7860 | |
f90b7a5a PB |
7861 | (define_expand "ctrap<mode>4" |
7862 | [(trap_if (match_operator 0 "comparison_operator" | |
7863 | [(match_operand:GPR 1 "register_operand" "") | |
7864 | (match_operand:GPR 2 "general_operand" "")]) | |
7865 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 7866 | "" |
f90b7a5a PB |
7867 | { |
7868 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
7869 | operands[1], operands[2]); | |
7870 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
7871 | DONE; | |
7872 | }) | |
7873 | ||
7874 | (define_expand "ctrap<mode>4" | |
7875 | [(trap_if (match_operator 0 "comparison_operator" | |
7876 | [(match_operand:FP 1 "register_operand" "") | |
7877 | (match_operand:FP 2 "general_operand" "")]) | |
7878 | (match_operand 3 "const0_operand" ""))] | |
7879 | "" | |
7880 | { | |
7881 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
7882 | operands[1], operands[2]); | |
7883 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
7884 | DONE; | |
7885 | }) | |
4456530d | 7886 | |
f90b7a5a PB |
7887 | (define_insn "condtrap" |
7888 | [(trap_if (match_operator 0 "s390_comparison" | |
7889 | [(match_operand 1 "cc_reg_operand" "c") | |
7890 | (const_int 0)]) | |
4456530d HP |
7891 | (const_int 0))] |
7892 | "" | |
d40c829f | 7893 | "j%C0\t.+2"; |
077dab3b HP |
7894 | [(set_attr "op_type" "RI") |
7895 | (set_attr "type" "branch")]) | |
9db1d521 | 7896 | |
963fc8d0 AK |
7897 | ; crt, cgrt, cit, cgit |
7898 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
7899 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
7900 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7901 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
7902 | (const_int 0))] | |
7903 | "TARGET_Z10" | |
7904 | "@ | |
7905 | c<g>rt%C0\t%1,%2 | |
7906 | c<g>it%C0\t%1,%h2" | |
7907 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7908 | (set_attr "type" "branch") |
729e750f | 7909 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 7910 | |
22ac2c2f | 7911 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
7912 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
7913 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
22ac2c2f AK |
7914 | [(match_operand:GPR 1 "register_operand" "d,d, d") |
7915 | (match_operand:GPR 2 "general_operand" "d,D,RT")]) | |
963fc8d0 AK |
7916 | (const_int 0))] |
7917 | "TARGET_Z10" | |
7918 | "@ | |
7919 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
7920 | cl<gf>it%C0\t%1,%x2 |
7921 | cl<g>t%C0\t%1,%2" | |
7922 | [(set_attr "op_type" "RRF,RIE,RSY") | |
7923 | (set_attr "type" "branch") | |
7924 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
7925 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
7926 | ||
7927 | ; lat, lgat | |
7928 | (define_insn "*load_and_trap<mode>" | |
7929 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") | |
7930 | (const_int 0)) | |
7931 | (const_int 0)) | |
7932 | (set (match_operand:GPR 1 "register_operand" "=d") | |
7933 | (match_dup 0))] | |
7934 | "TARGET_ZEC12" | |
7935 | "l<g>at\t%1,%0" | |
7936 | [(set_attr "op_type" "RXY")]) | |
7937 | ||
963fc8d0 | 7938 | |
9db1d521 | 7939 | ;; |
0a3bdf9d | 7940 | ;;- Loop instructions. |
9db1d521 | 7941 | ;; |
0a3bdf9d UW |
7942 | ;; This is all complicated by the fact that since this is a jump insn |
7943 | ;; we must handle our own output reloads. | |
c7453384 | 7944 | |
f1149235 AK |
7945 | ;; branch on index |
7946 | ||
7947 | ; This splitter will be matched by combine and has to add the 2 moves | |
7948 | ; necessary to load the compare and the increment values into a | |
7949 | ; register pair as needed by brxle. | |
7950 | ||
7951 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
7952 | [(set (pc) | |
7953 | (if_then_else | |
7954 | (match_operator 6 "s390_brx_operator" | |
7955 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
7956 | (match_operand:GPR 2 "general_operand" "")) | |
7957 | (match_operand:GPR 3 "register_operand" "")]) | |
7958 | (label_ref (match_operand 0 "" "")) | |
7959 | (pc))) | |
7960 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
7961 | (plus:GPR (match_dup 1) (match_dup 2))) | |
7962 | (clobber (match_scratch:GPR 5 ""))] | |
7963 | "TARGET_CPU_ZARCH" | |
7964 | "#" | |
7965 | "!reload_completed && !reload_in_progress" | |
7966 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
7967 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
7968 | (parallel [(set (pc) | |
7969 | (if_then_else | |
7970 | (match_op_dup 6 | |
7971 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
7972 | (match_dup 8)]) | |
7973 | (label_ref (match_dup 0)) | |
7974 | (pc))) | |
7975 | (set (match_dup 4) | |
7976 | (plus:GPR (match_dup 1) (match_dup 7))) | |
7977 | (clobber (match_dup 5)) | |
7978 | (clobber (reg:CC CC_REGNUM))])] | |
7979 | { | |
7980 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
7981 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
7982 | gen_highpart (word_mode, dreg)); | |
7983 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
7984 | gen_lowpart (word_mode, dreg)); | |
7985 | }) | |
7986 | ||
7987 | ; brxlg, brxhg | |
7988 | ||
7989 | (define_insn_and_split "*brxg_64bit" | |
7990 | [(set (pc) | |
7991 | (if_then_else | |
7992 | (match_operator 5 "s390_brx_operator" | |
7993 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
7994 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
7995 | (subreg:DI (match_dup 2) 8)]) | |
7996 | (label_ref (match_operand 0 "" "")) | |
7997 | (pc))) | |
7998 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
7999 | (plus:DI (match_dup 1) | |
8000 | (subreg:DI (match_dup 2) 0))) | |
8001 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
8002 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8003 | "TARGET_ZARCH" |
f1149235 AK |
8004 | { |
8005 | if (which_alternative != 0) | |
8006 | return "#"; | |
8007 | else if (get_attr_length (insn) == 6) | |
8008 | return "brx%E5g\t%1,%2,%l0"; | |
8009 | else | |
8010 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
8011 | } | |
8012 | "&& reload_completed | |
8013 | && (!REG_P (operands[3]) | |
8014 | || !rtx_equal_p (operands[1], operands[3]))" | |
8015 | [(set (match_dup 4) (match_dup 1)) | |
8016 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
8017 | (clobber (reg:CC CC_REGNUM))]) | |
8018 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
8019 | (set (match_dup 3) (match_dup 4)) | |
8020 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8021 | (label_ref (match_dup 0)) | |
8022 | (pc)))] | |
8023 | "" | |
8024 | [(set_attr "op_type" "RIE") | |
8025 | (set_attr "type" "branch") | |
8026 | (set (attr "length") | |
8027 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8028 | (const_int 6) (const_int 16)))]) | |
8029 | ||
8030 | ; brxle, brxh | |
8031 | ||
8032 | (define_insn_and_split "*brx_64bit" | |
8033 | [(set (pc) | |
8034 | (if_then_else | |
8035 | (match_operator 5 "s390_brx_operator" | |
8036 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8037 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
8038 | (subreg:SI (match_dup 2) 12)]) | |
8039 | (label_ref (match_operand 0 "" "")) | |
8040 | (pc))) | |
8041 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8042 | (plus:SI (match_dup 1) | |
8043 | (subreg:SI (match_dup 2) 4))) | |
8044 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8045 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8046 | "TARGET_ZARCH" |
f1149235 AK |
8047 | { |
8048 | if (which_alternative != 0) | |
8049 | return "#"; | |
8050 | else if (get_attr_length (insn) == 6) | |
8051 | return "brx%C5\t%1,%2,%l0"; | |
8052 | else | |
8053 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8054 | } | |
8055 | "&& reload_completed | |
8056 | && (!REG_P (operands[3]) | |
8057 | || !rtx_equal_p (operands[1], operands[3]))" | |
8058 | [(set (match_dup 4) (match_dup 1)) | |
8059 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8060 | (clobber (reg:CC CC_REGNUM))]) | |
8061 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
8062 | (set (match_dup 3) (match_dup 4)) | |
8063 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8064 | (label_ref (match_dup 0)) | |
8065 | (pc)))] | |
8066 | "" | |
8067 | [(set_attr "op_type" "RSI") | |
8068 | (set_attr "type" "branch") | |
8069 | (set (attr "length") | |
8070 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8071 | (const_int 6) (const_int 14)))]) | |
8072 | ||
8073 | ; brxle, brxh | |
8074 | ||
8075 | (define_insn_and_split "*brx_31bit" | |
8076 | [(set (pc) | |
8077 | (if_then_else | |
8078 | (match_operator 5 "s390_brx_operator" | |
8079 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8080 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
8081 | (subreg:SI (match_dup 2) 4)]) | |
8082 | (label_ref (match_operand 0 "" "")) | |
8083 | (pc))) | |
8084 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8085 | (plus:SI (match_dup 1) | |
8086 | (subreg:SI (match_dup 2) 0))) | |
8087 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8088 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8089 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
8090 | { |
8091 | if (which_alternative != 0) | |
8092 | return "#"; | |
8093 | else if (get_attr_length (insn) == 6) | |
8094 | return "brx%C5\t%1,%2,%l0"; | |
8095 | else | |
8096 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8097 | } | |
8098 | "&& reload_completed | |
8099 | && (!REG_P (operands[3]) | |
8100 | || !rtx_equal_p (operands[1], operands[3]))" | |
8101 | [(set (match_dup 4) (match_dup 1)) | |
8102 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
8103 | (clobber (reg:CC CC_REGNUM))]) | |
8104 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8105 | (set (match_dup 3) (match_dup 4)) | |
8106 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8107 | (label_ref (match_dup 0)) | |
8108 | (pc)))] | |
8109 | "" | |
8110 | [(set_attr "op_type" "RSI") | |
8111 | (set_attr "type" "branch") | |
8112 | (set (attr "length") | |
8113 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8114 | (const_int 6) (const_int 14)))]) | |
8115 | ||
8116 | ||
8117 | ;; branch on count | |
8118 | ||
0a3bdf9d UW |
8119 | (define_expand "doloop_end" |
8120 | [(use (match_operand 0 "" "")) ; loop pseudo | |
8121 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
8122 | (use (match_operand 2 "" "")) ; max iterations | |
8123 | (use (match_operand 3 "" "")) ; loop level | |
2407343c JR |
8124 | (use (match_operand 4 "" "")) ; label |
8125 | (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0 | |
0a3bdf9d | 8126 | "" |
0a3bdf9d | 8127 | { |
6590e19a UW |
8128 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
8129 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
8130 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
8131 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
9602b6a1 | 8132 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
0a3bdf9d UW |
8133 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); |
8134 | else | |
8135 | FAIL; | |
8136 | ||
8137 | DONE; | |
10bbf137 | 8138 | }) |
0a3bdf9d | 8139 | |
6590e19a | 8140 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
8141 | [(set (pc) |
8142 | (if_then_else | |
7e665d18 | 8143 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8144 | (const_int 1)) |
8145 | (label_ref (match_operand 0 "" "")) | |
8146 | (pc))) | |
7e665d18 | 8147 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8148 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8149 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8150 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8151 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8152 | { |
8153 | if (which_alternative != 0) | |
10bbf137 | 8154 | return "#"; |
0a3bdf9d | 8155 | else if (get_attr_length (insn) == 4) |
d40c829f | 8156 | return "brct\t%1,%l0"; |
6590e19a | 8157 | else |
545d16ff | 8158 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
8159 | } |
8160 | "&& reload_completed | |
8161 | && (! REG_P (operands[2]) | |
8162 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8163 | [(set (match_dup 3) (match_dup 1)) |
8164 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8165 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8166 | (const_int 0))) | |
8167 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8168 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8169 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8170 | (label_ref (match_dup 0)) |
8171 | (pc)))] | |
8172 | "" | |
8173 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8174 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8175 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8176 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8177 | (set_attr "type" "branch") |
8178 | (set (attr "length") | |
8179 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8180 | (const_int 4) (const_int 10)))]) | |
8181 | ||
8182 | (define_insn_and_split "doloop_si31" | |
8183 | [(set (pc) | |
8184 | (if_then_else | |
7e665d18 | 8185 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
8186 | (const_int 1)) |
8187 | (label_ref (match_operand 0 "" "")) | |
8188 | (pc))) | |
7e665d18 | 8189 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 8190 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8191 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8192 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
8193 | "!TARGET_CPU_ZARCH" |
8194 | { | |
8195 | if (which_alternative != 0) | |
8196 | return "#"; | |
8197 | else if (get_attr_length (insn) == 4) | |
8198 | return "brct\t%1,%l0"; | |
0a3bdf9d | 8199 | else |
8d933e31 | 8200 | gcc_unreachable (); |
10bbf137 | 8201 | } |
6590e19a UW |
8202 | "&& reload_completed |
8203 | && (! REG_P (operands[2]) | |
8204 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8205 | [(set (match_dup 3) (match_dup 1)) |
8206 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8207 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8208 | (const_int 0))) | |
8209 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8210 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8211 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8212 | (label_ref (match_dup 0)) |
8213 | (pc)))] | |
8214 | "" | |
0a3bdf9d | 8215 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
8216 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8217 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8218 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 8219 | (set_attr "type" "branch") |
0a3bdf9d | 8220 | (set (attr "length") |
d7f99b2c | 8221 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8222 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8223 | (const_int 4) (const_int 6)) | |
8224 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8225 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8226 | |
0a3bdf9d UW |
8227 | (define_insn "*doloop_si_long" |
8228 | [(set (pc) | |
8229 | (if_then_else | |
7e665d18 | 8230 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 8231 | (const_int 1)) |
4fe6dea8 | 8232 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 8233 | (pc))) |
7e665d18 | 8234 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 8235 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8236 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 8237 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8238 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8239 | { |
8240 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8241 | return "bctr\t%1,%0"; |
0a3bdf9d | 8242 | else |
d40c829f | 8243 | return "bct\t%1,%a0"; |
10bbf137 | 8244 | } |
c7453384 | 8245 | [(set (attr "op_type") |
0a3bdf9d UW |
8246 | (if_then_else (match_operand 0 "register_operand" "") |
8247 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8248 | (set_attr "type" "branch") |
729e750f | 8249 | (set_attr "atype" "agen") |
65b1d8ea AK |
8250 | (set_attr "z10prop" "z10_c") |
8251 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 8252 | |
6590e19a | 8253 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
8254 | [(set (pc) |
8255 | (if_then_else | |
7e665d18 | 8256 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8257 | (const_int 1)) |
8258 | (label_ref (match_operand 0 "" "")) | |
8259 | (pc))) | |
7e665d18 | 8260 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8261 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 8262 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 8263 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8264 | "TARGET_ZARCH" |
0a3bdf9d UW |
8265 | { |
8266 | if (which_alternative != 0) | |
10bbf137 | 8267 | return "#"; |
0a3bdf9d | 8268 | else if (get_attr_length (insn) == 4) |
d40c829f | 8269 | return "brctg\t%1,%l0"; |
0a3bdf9d | 8270 | else |
545d16ff | 8271 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 8272 | } |
6590e19a | 8273 | "&& reload_completed |
0a3bdf9d UW |
8274 | && (! REG_P (operands[2]) |
8275 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8276 | [(set (match_dup 3) (match_dup 1)) |
8277 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
8278 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
8279 | (const_int 0))) | |
8280 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
8281 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8282 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 8283 | (label_ref (match_dup 0)) |
0a3bdf9d | 8284 | (pc)))] |
6590e19a UW |
8285 | "" |
8286 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8287 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8288 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8289 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8290 | (set_attr "type" "branch") |
8291 | (set (attr "length") | |
8292 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8293 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
8294 | |
8295 | ;; | |
8296 | ;;- Unconditional jump instructions. | |
8297 | ;; | |
8298 | ||
8299 | ; | |
8300 | ; jump instruction pattern(s). | |
8301 | ; | |
8302 | ||
6590e19a UW |
8303 | (define_expand "jump" |
8304 | [(match_operand 0 "" "")] | |
9db1d521 | 8305 | "" |
6590e19a UW |
8306 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
8307 | ||
8308 | (define_insn "*jump64" | |
8309 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8310 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8311 | { |
13e58269 | 8312 | if (get_attr_length (insn) == 4) |
d40c829f | 8313 | return "j\t%l0"; |
6590e19a | 8314 | else |
d40c829f | 8315 | return "jg\t%l0"; |
6590e19a UW |
8316 | } |
8317 | [(set_attr "op_type" "RI") | |
8318 | (set_attr "type" "branch") | |
8319 | (set (attr "length") | |
8320 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8321 | (const_int 4) (const_int 6)))]) | |
8322 | ||
8323 | (define_insn "*jump31" | |
8324 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8325 | "!TARGET_CPU_ZARCH" | |
8326 | { | |
8d933e31 AS |
8327 | gcc_assert (get_attr_length (insn) == 4); |
8328 | return "j\t%l0"; | |
10bbf137 | 8329 | } |
9db1d521 | 8330 | [(set_attr "op_type" "RI") |
077dab3b | 8331 | (set_attr "type" "branch") |
13e58269 | 8332 | (set (attr "length") |
d7f99b2c | 8333 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8334 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8335 | (const_int 4) (const_int 6)) | |
8336 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8337 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
8338 | |
8339 | ; | |
8340 | ; indirect-jump instruction pattern(s). | |
8341 | ; | |
8342 | ||
8343 | (define_insn "indirect_jump" | |
4fe6dea8 | 8344 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 8345 | "" |
f314b9b1 UW |
8346 | { |
8347 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8348 | return "br\t%0"; |
f314b9b1 | 8349 | else |
d40c829f | 8350 | return "b\t%a0"; |
10bbf137 | 8351 | } |
c7453384 | 8352 | [(set (attr "op_type") |
f314b9b1 UW |
8353 | (if_then_else (match_operand 0 "register_operand" "") |
8354 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8355 | (set_attr "type" "branch") |
729e750f | 8356 | (set_attr "atype" "agen")]) |
9db1d521 HP |
8357 | |
8358 | ; | |
f314b9b1 | 8359 | ; casesi instruction pattern(s). |
9db1d521 HP |
8360 | ; |
8361 | ||
f314b9b1 | 8362 | (define_insn "casesi_jump" |
4fe6dea8 | 8363 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 8364 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 8365 | "" |
9db1d521 | 8366 | { |
f314b9b1 | 8367 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 8368 | return "br\t%0"; |
f314b9b1 | 8369 | else |
d40c829f | 8370 | return "b\t%a0"; |
10bbf137 | 8371 | } |
c7453384 | 8372 | [(set (attr "op_type") |
f314b9b1 UW |
8373 | (if_then_else (match_operand 0 "register_operand" "") |
8374 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8375 | (set_attr "type" "branch") |
8376 | (set_attr "atype" "agen")]) | |
9db1d521 | 8377 | |
f314b9b1 UW |
8378 | (define_expand "casesi" |
8379 | [(match_operand:SI 0 "general_operand" "") | |
8380 | (match_operand:SI 1 "general_operand" "") | |
8381 | (match_operand:SI 2 "general_operand" "") | |
8382 | (label_ref (match_operand 3 "" "")) | |
8383 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 8384 | "" |
f314b9b1 UW |
8385 | { |
8386 | rtx index = gen_reg_rtx (SImode); | |
8387 | rtx base = gen_reg_rtx (Pmode); | |
8388 | rtx target = gen_reg_rtx (Pmode); | |
8389 | ||
8390 | emit_move_insn (index, operands[0]); | |
8391 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
8392 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 8393 | operands[4]); |
f314b9b1 UW |
8394 | |
8395 | if (Pmode != SImode) | |
8396 | index = convert_to_mode (Pmode, index, 1); | |
8397 | if (GET_CODE (index) != REG) | |
8398 | index = copy_to_mode_reg (Pmode, index); | |
8399 | ||
8400 | if (TARGET_64BIT) | |
8401 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
8402 | else | |
a556fd39 | 8403 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 8404 | |
f314b9b1 UW |
8405 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
8406 | ||
542a8afa | 8407 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
8408 | emit_move_insn (target, index); |
8409 | ||
8410 | if (flag_pic) | |
8411 | target = gen_rtx_PLUS (Pmode, base, target); | |
8412 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
8413 | ||
8414 | DONE; | |
10bbf137 | 8415 | }) |
9db1d521 HP |
8416 | |
8417 | ||
8418 | ;; | |
8419 | ;;- Jump to subroutine. | |
8420 | ;; | |
8421 | ;; | |
8422 | ||
8423 | ; | |
8424 | ; untyped call instruction pattern(s). | |
8425 | ; | |
8426 | ||
8427 | ;; Call subroutine returning any type. | |
8428 | (define_expand "untyped_call" | |
8429 | [(parallel [(call (match_operand 0 "" "") | |
8430 | (const_int 0)) | |
8431 | (match_operand 1 "" "") | |
8432 | (match_operand 2 "" "")])] | |
8433 | "" | |
9db1d521 HP |
8434 | { |
8435 | int i; | |
8436 | ||
8437 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
8438 | ||
8439 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
8440 | { | |
8441 | rtx set = XVECEXP (operands[2], 0, i); | |
8442 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
8443 | } | |
8444 | ||
8445 | /* The optimizer does not know that the call sets the function value | |
8446 | registers we stored in the result block. We avoid problems by | |
8447 | claiming that all hard registers are used and clobbered at this | |
8448 | point. */ | |
8449 | emit_insn (gen_blockage ()); | |
8450 | ||
8451 | DONE; | |
10bbf137 | 8452 | }) |
9db1d521 HP |
8453 | |
8454 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
8455 | ;; all of memory. This blocks insns from being moved across this point. | |
8456 | ||
8457 | (define_insn "blockage" | |
10bbf137 | 8458 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 8459 | "" |
4023fb28 | 8460 | "" |
d5869ca0 UW |
8461 | [(set_attr "type" "none") |
8462 | (set_attr "length" "0")]) | |
4023fb28 | 8463 | |
9db1d521 | 8464 | ; |
ed9676cf | 8465 | ; sibcall patterns |
9db1d521 HP |
8466 | ; |
8467 | ||
ed9676cf | 8468 | (define_expand "sibcall" |
44b8152b | 8469 | [(call (match_operand 0 "" "") |
ed9676cf | 8470 | (match_operand 1 "" ""))] |
9db1d521 | 8471 | "" |
9db1d521 | 8472 | { |
ed9676cf AK |
8473 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
8474 | DONE; | |
8475 | }) | |
9db1d521 | 8476 | |
ed9676cf | 8477 | (define_insn "*sibcall_br" |
ae156f85 | 8478 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8479 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 8480 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8481 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
8482 | "br\t%%r1" | |
8483 | [(set_attr "op_type" "RR") | |
8484 | (set_attr "type" "branch") | |
8485 | (set_attr "atype" "agen")]) | |
9db1d521 | 8486 | |
ed9676cf AK |
8487 | (define_insn "*sibcall_brc" |
8488 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8489 | (match_operand 1 "const_int_operand" "n"))] | |
8490 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8491 | "j\t%0" | |
8492 | [(set_attr "op_type" "RI") | |
8493 | (set_attr "type" "branch")]) | |
9db1d521 | 8494 | |
ed9676cf AK |
8495 | (define_insn "*sibcall_brcl" |
8496 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8497 | (match_operand 1 "const_int_operand" "n"))] | |
8498 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8499 | "jg\t%0" | |
8500 | [(set_attr "op_type" "RIL") | |
8501 | (set_attr "type" "branch")]) | |
44b8152b | 8502 | |
ed9676cf AK |
8503 | ; |
8504 | ; sibcall_value patterns | |
8505 | ; | |
9e8327e3 | 8506 | |
ed9676cf AK |
8507 | (define_expand "sibcall_value" |
8508 | [(set (match_operand 0 "" "") | |
8509 | (call (match_operand 1 "" "") | |
8510 | (match_operand 2 "" "")))] | |
8511 | "" | |
8512 | { | |
8513 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 8514 | DONE; |
10bbf137 | 8515 | }) |
9db1d521 | 8516 | |
ed9676cf AK |
8517 | (define_insn "*sibcall_value_br" |
8518 | [(set (match_operand 0 "" "") | |
ae156f85 | 8519 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8520 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 8521 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8522 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
8523 | "br\t%%r1" | |
8524 | [(set_attr "op_type" "RR") | |
8525 | (set_attr "type" "branch") | |
8526 | (set_attr "atype" "agen")]) | |
8527 | ||
8528 | (define_insn "*sibcall_value_brc" | |
8529 | [(set (match_operand 0 "" "") | |
8530 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8531 | (match_operand 2 "const_int_operand" "n")))] | |
8532 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8533 | "j\t%1" | |
8534 | [(set_attr "op_type" "RI") | |
8535 | (set_attr "type" "branch")]) | |
8536 | ||
8537 | (define_insn "*sibcall_value_brcl" | |
8538 | [(set (match_operand 0 "" "") | |
8539 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8540 | (match_operand 2 "const_int_operand" "n")))] | |
8541 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8542 | "jg\t%1" | |
8543 | [(set_attr "op_type" "RIL") | |
8544 | (set_attr "type" "branch")]) | |
8545 | ||
8546 | ||
8547 | ; | |
8548 | ; call instruction pattern(s). | |
8549 | ; | |
8550 | ||
8551 | (define_expand "call" | |
8552 | [(call (match_operand 0 "" "") | |
8553 | (match_operand 1 "" "")) | |
8554 | (use (match_operand 2 "" ""))] | |
44b8152b | 8555 | "" |
ed9676cf | 8556 | { |
2f7e5a0d | 8557 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
8558 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
8559 | DONE; | |
8560 | }) | |
44b8152b | 8561 | |
9e8327e3 UW |
8562 | (define_insn "*bras" |
8563 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8564 | (match_operand 1 "const_int_operand" "n")) | |
8565 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8566 | "!SIBLING_CALL_P (insn) |
8567 | && TARGET_SMALL_EXEC | |
ed9676cf | 8568 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 8569 | "bras\t%2,%0" |
9db1d521 | 8570 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8571 | (set_attr "type" "jsr") |
8572 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8573 | |
9e8327e3 UW |
8574 | (define_insn "*brasl" |
8575 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8576 | (match_operand 1 "const_int_operand" "n")) | |
8577 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8578 | "!SIBLING_CALL_P (insn) |
8579 | && TARGET_CPU_ZARCH | |
ed9676cf | 8580 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8581 | "brasl\t%2,%0" |
8582 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8583 | (set_attr "type" "jsr") |
8584 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8585 | |
9e8327e3 | 8586 | (define_insn "*basr" |
4fe6dea8 | 8587 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
8588 | (match_operand 1 "const_int_operand" "n")) |
8589 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 8590 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8591 | { |
8592 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8593 | return "basr\t%2,%0"; | |
8594 | else | |
8595 | return "bas\t%2,%a0"; | |
8596 | } | |
8597 | [(set (attr "op_type") | |
8598 | (if_then_else (match_operand 0 "register_operand" "") | |
8599 | (const_string "RR") (const_string "RX"))) | |
8600 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8601 | (set_attr "atype" "agen") |
8602 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
8603 | |
8604 | ; | |
8605 | ; call_value instruction pattern(s). | |
8606 | ; | |
8607 | ||
8608 | (define_expand "call_value" | |
44b8152b UW |
8609 | [(set (match_operand 0 "" "") |
8610 | (call (match_operand 1 "" "") | |
8611 | (match_operand 2 "" ""))) | |
8612 | (use (match_operand 3 "" ""))] | |
9db1d521 | 8613 | "" |
9db1d521 | 8614 | { |
2f7e5a0d | 8615 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 8616 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 8617 | DONE; |
10bbf137 | 8618 | }) |
9db1d521 | 8619 | |
9e8327e3 | 8620 | (define_insn "*bras_r" |
c19ec8f9 | 8621 | [(set (match_operand 0 "" "") |
9e8327e3 | 8622 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 8623 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 8624 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
8625 | "!SIBLING_CALL_P (insn) |
8626 | && TARGET_SMALL_EXEC | |
ed9676cf | 8627 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8628 | "bras\t%3,%1" |
9db1d521 | 8629 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8630 | (set_attr "type" "jsr") |
8631 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8632 | |
9e8327e3 | 8633 | (define_insn "*brasl_r" |
c19ec8f9 | 8634 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8635 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8636 | (match_operand 2 "const_int_operand" "n"))) | |
8637 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
8638 | "!SIBLING_CALL_P (insn) |
8639 | && TARGET_CPU_ZARCH | |
ed9676cf | 8640 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8641 | "brasl\t%3,%1" |
8642 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8643 | (set_attr "type" "jsr") |
8644 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8645 | |
9e8327e3 | 8646 | (define_insn "*basr_r" |
c19ec8f9 | 8647 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8648 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8649 | (match_operand 2 "const_int_operand" "n"))) |
8650 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 8651 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8652 | { |
8653 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8654 | return "basr\t%3,%1"; | |
8655 | else | |
8656 | return "bas\t%3,%a1"; | |
8657 | } | |
8658 | [(set (attr "op_type") | |
8659 | (if_then_else (match_operand 1 "register_operand" "") | |
8660 | (const_string "RR") (const_string "RX"))) | |
8661 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8662 | (set_attr "atype" "agen") |
8663 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8664 | |
fd3cd001 UW |
8665 | ;; |
8666 | ;;- Thread-local storage support. | |
8667 | ;; | |
8668 | ||
f959607b CLT |
8669 | (define_expand "get_thread_pointer<mode>" |
8670 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
8671 | "" | |
c5aa1d12 | 8672 | "") |
fd3cd001 | 8673 | |
f959607b CLT |
8674 | (define_expand "set_thread_pointer<mode>" |
8675 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
8676 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
8677 | "" | |
c5aa1d12 UW |
8678 | "") |
8679 | ||
8680 | (define_insn "*set_tp" | |
ae156f85 | 8681 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
8682 | "" |
8683 | "" | |
8684 | [(set_attr "type" "none") | |
8685 | (set_attr "length" "0")]) | |
c7453384 | 8686 | |
fd3cd001 UW |
8687 | (define_insn "*tls_load_64" |
8688 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 8689 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
8690 | (match_operand:DI 2 "" "")] |
8691 | UNSPEC_TLS_LOAD))] | |
8692 | "TARGET_64BIT" | |
d40c829f | 8693 | "lg\t%0,%1%J2" |
9381e3f1 WG |
8694 | [(set_attr "op_type" "RXE") |
8695 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
8696 | |
8697 | (define_insn "*tls_load_31" | |
d3632d41 UW |
8698 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
8699 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
8700 | (match_operand:SI 2 "" "")] |
8701 | UNSPEC_TLS_LOAD))] | |
8702 | "!TARGET_64BIT" | |
d3632d41 | 8703 | "@ |
d40c829f UW |
8704 | l\t%0,%1%J2 |
8705 | ly\t%0,%1%J2" | |
9381e3f1 | 8706 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 8707 | (set_attr "type" "load") |
9381e3f1 | 8708 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 8709 | |
9e8327e3 | 8710 | (define_insn "*bras_tls" |
c19ec8f9 | 8711 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8712 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8713 | (match_operand 2 "const_int_operand" "n"))) | |
8714 | (clobber (match_operand 3 "register_operand" "=r")) | |
8715 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8716 | "!SIBLING_CALL_P (insn) |
8717 | && TARGET_SMALL_EXEC | |
ed9676cf | 8718 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8719 | "bras\t%3,%1%J4" |
fd3cd001 | 8720 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8721 | (set_attr "type" "jsr") |
8722 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8723 | |
9e8327e3 | 8724 | (define_insn "*brasl_tls" |
c19ec8f9 | 8725 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8726 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8727 | (match_operand 2 "const_int_operand" "n"))) | |
8728 | (clobber (match_operand 3 "register_operand" "=r")) | |
8729 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8730 | "!SIBLING_CALL_P (insn) |
8731 | && TARGET_CPU_ZARCH | |
ed9676cf | 8732 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8733 | "brasl\t%3,%1%J4" |
8734 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8735 | (set_attr "type" "jsr") |
8736 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8737 | |
9e8327e3 | 8738 | (define_insn "*basr_tls" |
c19ec8f9 | 8739 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8740 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8741 | (match_operand 2 "const_int_operand" "n"))) |
8742 | (clobber (match_operand 3 "register_operand" "=r")) | |
8743 | (use (match_operand 4 "" ""))] | |
ed9676cf | 8744 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8745 | { |
8746 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8747 | return "basr\t%3,%1%J4"; | |
8748 | else | |
8749 | return "bas\t%3,%a1%J4"; | |
8750 | } | |
8751 | [(set (attr "op_type") | |
8752 | (if_then_else (match_operand 1 "register_operand" "") | |
8753 | (const_string "RR") (const_string "RX"))) | |
8754 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8755 | (set_attr "atype" "agen") |
8756 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8757 | |
e0374221 AS |
8758 | ;; |
8759 | ;;- Atomic operations | |
8760 | ;; | |
8761 | ||
8762 | ; | |
78ce265b | 8763 | ; memory barrier patterns. |
e0374221 AS |
8764 | ; |
8765 | ||
78ce265b RH |
8766 | (define_expand "mem_signal_fence" |
8767 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
8768 | "" |
8769 | { | |
78ce265b RH |
8770 | /* The s390 memory model is strong enough not to require any |
8771 | barrier in order to synchronize a thread with itself. */ | |
8772 | DONE; | |
8773 | }) | |
8774 | ||
8775 | (define_expand "mem_thread_fence" | |
8776 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
8777 | "" | |
8778 | { | |
8779 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
8780 | enough not to require barriers of any kind. */ | |
8781 | if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST) | |
8782 | { | |
8783 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
8784 | MEM_VOLATILE_P (mem) = 1; | |
8785 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
8786 | } | |
8787 | DONE; | |
e0374221 AS |
8788 | }) |
8789 | ||
78ce265b RH |
8790 | ; Although bcr is superscalar on Z10, this variant will never |
8791 | ; become part of an execution group. | |
8792 | (define_insn "mem_thread_fence_1" | |
e0374221 | 8793 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 8794 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 AS |
8795 | "" |
8796 | "bcr\t15,0" | |
8797 | [(set_attr "op_type" "RR")]) | |
1a8c13b3 | 8798 | |
78ce265b RH |
8799 | ; |
8800 | ; atomic load/store operations | |
8801 | ; | |
8802 | ||
8803 | ; Atomic loads need not examine the memory model at all. | |
8804 | (define_expand "atomic_load<mode>" | |
8805 | [(match_operand:DINT 0 "register_operand") ;; output | |
8806 | (match_operand:DINT 1 "memory_operand") ;; memory | |
8807 | (match_operand:SI 2 "const_int_operand")] ;; model | |
8808 | "" | |
8809 | { | |
8810 | if (<MODE>mode == TImode) | |
8811 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
8812 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
8813 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
8814 | else | |
8815 | emit_move_insn (operands[0], operands[1]); | |
8816 | DONE; | |
8817 | }) | |
8818 | ||
8819 | ; Different from movdi_31 in that we want no splitters. | |
8820 | (define_insn "atomic_loaddi_1" | |
8821 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
8822 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
8823 | UNSPEC_MOVA))] | |
8824 | "!TARGET_ZARCH" | |
8825 | "@ | |
8826 | lm\t%0,%M0,%S1 | |
8827 | lmy\t%0,%M0,%S1 | |
8828 | ld\t%0,%1 | |
8829 | ldy\t%0,%1" | |
8830 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
8831 | (set_attr "type" "lm,lm,floaddf,floaddf")]) | |
8832 | ||
8833 | (define_insn "atomic_loadti_1" | |
8834 | [(set (match_operand:TI 0 "register_operand" "=r") | |
8835 | (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] | |
8836 | UNSPEC_MOVA))] | |
8837 | "TARGET_ZARCH" | |
8838 | "lpq\t%0,%1" | |
8839 | [(set_attr "op_type" "RXY") | |
8840 | (set_attr "type" "other")]) | |
8841 | ||
8842 | ; Atomic stores must(?) enforce sequential consistency. | |
8843 | (define_expand "atomic_store<mode>" | |
8844 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
8845 | (match_operand:DINT 1 "register_operand") ;; input | |
8846 | (match_operand:SI 2 "const_int_operand")] ;; model | |
8847 | "" | |
8848 | { | |
8849 | enum memmodel model = (enum memmodel) INTVAL (operands[2]); | |
8850 | ||
8851 | if (<MODE>mode == TImode) | |
8852 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
8853 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
8854 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
8855 | else | |
8856 | emit_move_insn (operands[0], operands[1]); | |
8857 | if (model == MEMMODEL_SEQ_CST) | |
8858 | emit_insn (gen_mem_thread_fence (operands[2])); | |
8859 | DONE; | |
8860 | }) | |
8861 | ||
8862 | ; Different from movdi_31 in that we want no splitters. | |
8863 | (define_insn "atomic_storedi_1" | |
8864 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
8865 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
8866 | UNSPEC_MOVA))] | |
8867 | "!TARGET_ZARCH" | |
8868 | "@ | |
8869 | stm\t%1,%N1,%S0 | |
8870 | stmy\t%1,%N1,%S0 | |
8871 | std %1,%0 | |
8872 | stdy %1,%0" | |
8873 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
8874 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) | |
8875 | ||
8876 | (define_insn "atomic_storeti_1" | |
8877 | [(set (match_operand:TI 0 "memory_operand" "=RT") | |
8878 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] | |
8879 | UNSPEC_MOVA))] | |
8880 | "TARGET_ZARCH" | |
8881 | "stpq\t%1,%0" | |
8882 | [(set_attr "op_type" "RXY") | |
8883 | (set_attr "type" "other")]) | |
e0374221 AS |
8884 | |
8885 | ; | |
8886 | ; compare and swap patterns. | |
8887 | ; | |
8888 | ||
78ce265b RH |
8889 | (define_expand "atomic_compare_and_swap<mode>" |
8890 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 8891 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
8892 | (match_operand:DGPR 2 "memory_operand") ;; memory |
8893 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
8894 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
8895 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
8896 | (match_operand:SI 6 "const_int_operand") ;; success model | |
8897 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
8898 | "" | |
8899 | { | |
215770ad UW |
8900 | rtx cc, cmp, output = operands[1]; |
8901 | ||
8902 | if (!register_operand (output, <MODE>mode)) | |
8903 | output = gen_reg_rtx (<MODE>mode); | |
8904 | ||
78ce265b | 8905 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
8906 | (output, operands[2], operands[3], operands[4])); |
8907 | ||
8908 | /* We deliberately accept non-register operands in the predicate | |
8909 | to ensure the write back to the output operand happens *before* | |
8910 | the store-flags code below. This makes it easier for combine | |
8911 | to merge the store-flags code with a potential test-and-branch | |
8912 | pattern following (immediately!) afterwards. */ | |
8913 | if (output != operands[1]) | |
8914 | emit_move_insn (operands[1], output); | |
8915 | ||
78ce265b RH |
8916 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
8917 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
8918 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
8919 | DONE; | |
8920 | }) | |
e0374221 | 8921 | |
78ce265b RH |
8922 | (define_expand "atomic_compare_and_swap<mode>" |
8923 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 8924 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
8925 | (match_operand:HQI 2 "memory_operand") ;; memory |
8926 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
8927 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
8928 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
8929 | (match_operand:SI 6 "const_int_operand") ;; success model | |
8930 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 8931 | "" |
78ce265b RH |
8932 | { |
8933 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
8934 | operands[3], operands[4], INTVAL (operands[5])); | |
8935 | DONE; | |
8936 | }) | |
3093f076 | 8937 | |
78ce265b RH |
8938 | (define_expand "atomic_compare_and_swap<mode>_internal" |
8939 | [(parallel | |
8940 | [(set (match_operand:DGPR 0 "register_operand") | |
8941 | (match_operand:DGPR 1 "memory_operand")) | |
8942 | (set (match_dup 1) | |
8943 | (unspec_volatile:DGPR | |
8944 | [(match_dup 1) | |
8945 | (match_operand:DGPR 2 "register_operand") | |
8946 | (match_operand:DGPR 3 "register_operand")] | |
8947 | UNSPECV_CAS)) | |
8948 | (set (reg:CCZ1 CC_REGNUM) | |
8949 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8950 | "") | |
8951 | ||
8952 | ; cdsg, csg | |
8953 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
8954 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
8955 | (match_operand:TDI 1 "memory_operand" "+QS")) | |
8006eaa6 | 8956 | (set (match_dup 1) |
78ce265b | 8957 | (unspec_volatile:TDI |
8006eaa6 | 8958 | [(match_dup 1) |
78ce265b RH |
8959 | (match_operand:TDI 2 "register_operand" "0") |
8960 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
8961 | UNSPECV_CAS)) |
8962 | (set (reg:CCZ1 CC_REGNUM) | |
8963 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
8964 | "TARGET_ZARCH" |
8965 | "c<td>sg\t%0,%3,%S1" | |
8966 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
8967 | (set_attr "type" "sem")]) |
8968 | ||
78ce265b RH |
8969 | ; cds, cdsy |
8970 | (define_insn "*atomic_compare_and_swapdi_2" | |
8971 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
8972 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 8973 | (set (match_dup 1) |
78ce265b RH |
8974 | (unspec_volatile:DI |
8975 | [(match_dup 1) | |
8976 | (match_operand:DI 2 "register_operand" "0,0") | |
8977 | (match_operand:DI 3 "register_operand" "r,r")] | |
8978 | UNSPECV_CAS)) | |
8979 | (set (reg:CCZ1 CC_REGNUM) | |
8980 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
8981 | "!TARGET_ZARCH" | |
8982 | "@ | |
8983 | cds\t%0,%3,%S1 | |
8984 | cdsy\t%0,%3,%S1" | |
8985 | [(set_attr "op_type" "RS,RSY") | |
8986 | (set_attr "type" "sem")]) | |
8987 | ||
8988 | ; cs, csy | |
8989 | (define_insn "*atomic_compare_and_swapsi_3" | |
8990 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
8991 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
8992 | (set (match_dup 1) | |
8993 | (unspec_volatile:SI | |
e0374221 | 8994 | [(match_dup 1) |
78ce265b RH |
8995 | (match_operand:SI 2 "register_operand" "0,0") |
8996 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 8997 | UNSPECV_CAS)) |
69950452 AS |
8998 | (set (reg:CCZ1 CC_REGNUM) |
8999 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 9000 | "" |
78ce265b RH |
9001 | "@ |
9002 | cs\t%0,%3,%S1 | |
9003 | csy\t%0,%3,%S1" | |
9004 | [(set_attr "op_type" "RS,RSY") | |
e0374221 AS |
9005 | (set_attr "type" "sem")]) |
9006 | ||
45d18331 AS |
9007 | ; |
9008 | ; Other atomic instruction patterns. | |
9009 | ; | |
9010 | ||
65b1d8ea AK |
9011 | ; z196 load and add, xor, or and and instructions |
9012 | ||
78ce265b RH |
9013 | (define_expand "atomic_fetch_<atomic><mode>" |
9014 | [(match_operand:GPR 0 "register_operand") ;; val out | |
9015 | (ATOMIC_Z196:GPR | |
9016 | (match_operand:GPR 1 "memory_operand") ;; memory | |
9017 | (match_operand:GPR 2 "register_operand")) ;; val in | |
9018 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 9019 | "TARGET_Z196" |
78ce265b RH |
9020 | { |
9021 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf | |
9022 | (operands[0], operands[1], operands[2])); | |
9023 | DONE; | |
9024 | }) | |
65b1d8ea AK |
9025 | |
9026 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
9027 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
9028 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
9029 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
9030 | (set (match_dup 1) | |
9031 | (unspec_volatile:GPR | |
9032 | [(ATOMIC_Z196:GPR (match_dup 1) | |
9033 | (match_operand:GPR 2 "general_operand" "d"))] | |
9034 | UNSPECV_ATOMIC_OP)) | |
9035 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 9036 | "TARGET_Z196" |
78ce265b RH |
9037 | "la<noxa><g>\t%0,%2,%1" |
9038 | [(set_attr "op_type" "RSY") | |
9039 | (set_attr "type" "sem")]) | |
65b1d8ea | 9040 | |
78ce265b RH |
9041 | ;; For SImode and larger, the optabs.c code will do just fine in |
9042 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
9043 | ;; better by expanding our own loop. | |
65b1d8ea | 9044 | |
78ce265b RH |
9045 | (define_expand "atomic_<atomic><mode>" |
9046 | [(ATOMIC:HQI | |
9047 | (match_operand:HQI 0 "memory_operand") ;; memory | |
9048 | (match_operand:HQI 1 "general_operand")) ;; val in | |
9049 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 9050 | "" |
78ce265b RH |
9051 | { |
9052 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
9053 | operands[1], false); | |
9054 | DONE; | |
9055 | }) | |
45d18331 | 9056 | |
78ce265b RH |
9057 | (define_expand "atomic_fetch_<atomic><mode>" |
9058 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9059 | (ATOMIC:HQI | |
9060 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9061 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9062 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9063 | "" |
78ce265b RH |
9064 | { |
9065 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9066 | operands[2], false); | |
9067 | DONE; | |
9068 | }) | |
9069 | ||
9070 | (define_expand "atomic_<atomic>_fetch<mode>" | |
9071 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9072 | (ATOMIC:HQI | |
9073 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9074 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9075 | (match_operand:SI 3 "const_int_operand")] ;; model | |
9076 | "" | |
9077 | { | |
9078 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9079 | operands[2], true); | |
9080 | DONE; | |
9081 | }) | |
9082 | ||
9083 | (define_expand "atomic_exchange<mode>" | |
9084 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9085 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9086 | (match_operand:HQI 2 "general_operand") ;; val in | |
9087 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9088 | "" |
78ce265b RH |
9089 | { |
9090 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
9091 | operands[2], false); | |
9092 | DONE; | |
9093 | }) | |
45d18331 | 9094 | |
9db1d521 HP |
9095 | ;; |
9096 | ;;- Miscellaneous instructions. | |
9097 | ;; | |
9098 | ||
9099 | ; | |
9100 | ; allocate stack instruction pattern(s). | |
9101 | ; | |
9102 | ||
9103 | (define_expand "allocate_stack" | |
ef44a6ff UW |
9104 | [(match_operand 0 "general_operand" "") |
9105 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 9106 | "TARGET_BACKCHAIN" |
9db1d521 | 9107 | { |
ef44a6ff | 9108 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 9109 | |
ef44a6ff UW |
9110 | emit_move_insn (temp, s390_back_chain_rtx ()); |
9111 | anti_adjust_stack (operands[1]); | |
9112 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 9113 | |
ef44a6ff UW |
9114 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
9115 | DONE; | |
10bbf137 | 9116 | }) |
9db1d521 HP |
9117 | |
9118 | ||
9119 | ; | |
43ab026f | 9120 | ; setjmp instruction pattern. |
9db1d521 HP |
9121 | ; |
9122 | ||
9db1d521 | 9123 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 9124 | [(match_operand 0 "" "")] |
f314b9b1 | 9125 | "flag_pic" |
9db1d521 | 9126 | { |
585539a1 | 9127 | emit_insn (s390_load_got ()); |
c41c1387 | 9128 | emit_use (pic_offset_table_rtx); |
9db1d521 | 9129 | DONE; |
fd7643fb | 9130 | }) |
9db1d521 | 9131 | |
9db1d521 HP |
9132 | ;; These patterns say how to save and restore the stack pointer. We need not |
9133 | ;; save the stack pointer at function level since we are careful to | |
9134 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9135 | ;; when we restore the stack pointer. | |
9136 | ;; | |
9137 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9138 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9139 | ;; save area is a memory location. | |
9140 | ||
9141 | (define_expand "save_stack_function" | |
9142 | [(match_operand 0 "general_operand" "") | |
9143 | (match_operand 1 "general_operand" "")] | |
9144 | "" | |
9145 | "DONE;") | |
9146 | ||
9147 | (define_expand "restore_stack_function" | |
9148 | [(match_operand 0 "general_operand" "") | |
9149 | (match_operand 1 "general_operand" "")] | |
9150 | "" | |
9151 | "DONE;") | |
9152 | ||
9153 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
9154 | [(match_operand 0 "register_operand" "") |
9155 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 9156 | "TARGET_BACKCHAIN" |
9db1d521 | 9157 | { |
ef44a6ff UW |
9158 | rtx temp = gen_reg_rtx (Pmode); |
9159 | ||
9160 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
9161 | emit_move_insn (operands[0], operands[1]); | |
9162 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9163 | ||
9164 | DONE; | |
10bbf137 | 9165 | }) |
9db1d521 HP |
9166 | |
9167 | (define_expand "save_stack_nonlocal" | |
9168 | [(match_operand 0 "memory_operand" "") | |
9169 | (match_operand 1 "register_operand" "")] | |
9170 | "" | |
9db1d521 | 9171 | { |
ef44a6ff UW |
9172 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
9173 | ||
9174 | /* Copy the backchain to the first word, sp to the second and the | |
9175 | literal pool base to the third. */ | |
9176 | ||
9602b6a1 AK |
9177 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
9178 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
9179 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
9180 | ||
b3d31392 | 9181 | if (TARGET_BACKCHAIN) |
9602b6a1 | 9182 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 9183 | |
9602b6a1 AK |
9184 | emit_move_insn (save_sp, operands[1]); |
9185 | emit_move_insn (save_bp, base); | |
9db1d521 | 9186 | |
9db1d521 | 9187 | DONE; |
10bbf137 | 9188 | }) |
9db1d521 HP |
9189 | |
9190 | (define_expand "restore_stack_nonlocal" | |
9191 | [(match_operand 0 "register_operand" "") | |
9192 | (match_operand 1 "memory_operand" "")] | |
9193 | "" | |
9db1d521 | 9194 | { |
490ceeb4 | 9195 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 9196 | rtx temp = NULL_RTX; |
9db1d521 | 9197 | |
43ab026f | 9198 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 9199 | literal pool base from the third. */ |
43ab026f | 9200 | |
9602b6a1 AK |
9201 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
9202 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
9203 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
9204 | ||
b3d31392 | 9205 | if (TARGET_BACKCHAIN) |
9602b6a1 | 9206 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 9207 | |
9602b6a1 AK |
9208 | emit_move_insn (base, save_bp); |
9209 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
9210 | |
9211 | if (temp) | |
9212 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9213 | ||
c41c1387 | 9214 | emit_use (base); |
9db1d521 | 9215 | DONE; |
10bbf137 | 9216 | }) |
9db1d521 | 9217 | |
7bcebb25 AK |
9218 | (define_expand "exception_receiver" |
9219 | [(const_int 0)] | |
9220 | "" | |
9221 | { | |
9222 | s390_set_has_landing_pad_p (true); | |
9223 | DONE; | |
9224 | }) | |
9db1d521 HP |
9225 | |
9226 | ; | |
9227 | ; nop instruction pattern(s). | |
9228 | ; | |
9229 | ||
9230 | (define_insn "nop" | |
9231 | [(const_int 0)] | |
9232 | "" | |
d40c829f | 9233 | "lr\t0,0" |
729e750f WG |
9234 | [(set_attr "op_type" "RR") |
9235 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 9236 | |
d277db6b WG |
9237 | (define_insn "nop1" |
9238 | [(const_int 1)] | |
9239 | "" | |
9240 | "lr\t1,1" | |
9241 | [(set_attr "op_type" "RR")]) | |
9242 | ||
9db1d521 HP |
9243 | |
9244 | ; | |
9245 | ; Special literal pool access instruction pattern(s). | |
9246 | ; | |
9247 | ||
416cf582 UW |
9248 | (define_insn "*pool_entry" |
9249 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
9250 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 9251 | "" |
9db1d521 | 9252 | { |
416cf582 UW |
9253 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
9254 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 9255 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
9256 | return ""; |
9257 | } | |
b628bd8e | 9258 | [(set (attr "length") |
416cf582 | 9259 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 9260 | |
9bb86f41 UW |
9261 | (define_insn "pool_align" |
9262 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
9263 | UNSPECV_POOL_ALIGN)] | |
9264 | "" | |
9265 | ".align\t%0" | |
b628bd8e | 9266 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 9267 | |
9bb86f41 UW |
9268 | (define_insn "pool_section_start" |
9269 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
9270 | "" | |
9271 | ".section\t.rodata" | |
b628bd8e | 9272 | [(set_attr "length" "0")]) |
b2ccb744 | 9273 | |
9bb86f41 UW |
9274 | (define_insn "pool_section_end" |
9275 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
9276 | "" | |
b2ccb744 | 9277 | ".previous" |
b628bd8e | 9278 | [(set_attr "length" "0")]) |
b2ccb744 | 9279 | |
5af2f3d3 | 9280 | (define_insn "main_base_31_small" |
9e8327e3 UW |
9281 | [(set (match_operand 0 "register_operand" "=a") |
9282 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9283 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9284 | "basr\t%0,0" |
9285 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
9286 | (set_attr "type" "la") |
9287 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9288 | |
9289 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
9290 | [(set (match_operand 0 "register_operand" "=a") |
9291 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 9292 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 9293 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 9294 | "bras\t%0,%2" |
65b1d8ea AK |
9295 | [(set_attr "op_type" "RI") |
9296 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9297 | |
9298 | (define_insn "main_base_64" | |
9e8327e3 UW |
9299 | [(set (match_operand 0 "register_operand" "=a") |
9300 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9301 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9302 | "larl\t%0,%1" |
9303 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 9304 | (set_attr "type" "larl") |
729e750f | 9305 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
9306 | |
9307 | (define_insn "main_pool" | |
585539a1 UW |
9308 | [(set (match_operand 0 "register_operand" "=a") |
9309 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
9310 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
9311 | { |
9312 | gcc_unreachable (); | |
9313 | } | |
9381e3f1 | 9314 | [(set (attr "type") |
d7f99b2c | 9315 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 9316 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 9317 | |
aee4e0db | 9318 | (define_insn "reload_base_31" |
9e8327e3 UW |
9319 | [(set (match_operand 0 "register_operand" "=a") |
9320 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9321 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9322 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 9323 | [(set_attr "length" "6") |
65b1d8ea AK |
9324 | (set_attr "type" "la") |
9325 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 9326 | |
aee4e0db | 9327 | (define_insn "reload_base_64" |
9e8327e3 UW |
9328 | [(set (match_operand 0 "register_operand" "=a") |
9329 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9330 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9331 | "larl\t%0,%1" |
aee4e0db | 9332 | [(set_attr "op_type" "RIL") |
9381e3f1 | 9333 | (set_attr "type" "larl") |
729e750f | 9334 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 9335 | |
aee4e0db | 9336 | (define_insn "pool" |
fd7643fb | 9337 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 9338 | "" |
8d933e31 AS |
9339 | { |
9340 | gcc_unreachable (); | |
9341 | } | |
b628bd8e | 9342 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 9343 | |
4023fb28 UW |
9344 | ;; |
9345 | ;; Insns related to generating the function prologue and epilogue. | |
9346 | ;; | |
9347 | ||
9348 | ||
9349 | (define_expand "prologue" | |
9350 | [(use (const_int 0))] | |
9351 | "" | |
10bbf137 | 9352 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
9353 | |
9354 | (define_expand "epilogue" | |
9355 | [(use (const_int 1))] | |
9356 | "" | |
ed9676cf AK |
9357 | "s390_emit_epilogue (false); DONE;") |
9358 | ||
9359 | (define_expand "sibcall_epilogue" | |
9360 | [(use (const_int 0))] | |
9361 | "" | |
9362 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 9363 | |
9e8327e3 | 9364 | (define_insn "*return" |
4023fb28 | 9365 | [(return) |
9e8327e3 UW |
9366 | (use (match_operand 0 "register_operand" "a"))] |
9367 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9368 | "br\t%0" |
4023fb28 | 9369 | [(set_attr "op_type" "RR") |
c7453384 | 9370 | (set_attr "type" "jsr") |
077dab3b | 9371 | (set_attr "atype" "agen")]) |
4023fb28 | 9372 | |
4023fb28 | 9373 | |
c7453384 | 9374 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 9375 | ;; pointer. This is used for compatibility. |
c7453384 EC |
9376 | |
9377 | (define_expand "ptr_extend" | |
9378 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9379 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 9380 | "TARGET_64BIT" |
c7453384 | 9381 | { |
c7453384 EC |
9382 | emit_insn (gen_anddi3 (operands[0], |
9383 | gen_lowpart (DImode, operands[1]), | |
9384 | GEN_INT (0x7fffffff))); | |
c7453384 | 9385 | DONE; |
10bbf137 | 9386 | }) |
4798630c D |
9387 | |
9388 | ;; Instruction definition to expand eh_return macro to support | |
9389 | ;; swapping in special linkage return addresses. | |
9390 | ||
9391 | (define_expand "eh_return" | |
9392 | [(use (match_operand 0 "register_operand" ""))] | |
9393 | "TARGET_TPF" | |
9394 | { | |
9395 | s390_emit_tpf_eh_return (operands[0]); | |
9396 | DONE; | |
9397 | }) | |
9398 | ||
7b8acc34 AK |
9399 | ; |
9400 | ; Stack Protector Patterns | |
9401 | ; | |
9402 | ||
9403 | (define_expand "stack_protect_set" | |
9404 | [(set (match_operand 0 "memory_operand" "") | |
9405 | (match_operand 1 "memory_operand" ""))] | |
9406 | "" | |
9407 | { | |
9408 | #ifdef TARGET_THREAD_SSP_OFFSET | |
9409 | operands[1] | |
9410 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9411 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9412 | #endif | |
9413 | if (TARGET_64BIT) | |
9414 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
9415 | else | |
9416 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
9417 | ||
9418 | DONE; | |
9419 | }) | |
9420 | ||
9421 | (define_insn "stack_protect_set<mode>" | |
9422 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
9423 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
9424 | "" | |
9425 | "mvc\t%O0(%G0,%R0),%S1" | |
9426 | [(set_attr "op_type" "SS")]) | |
9427 | ||
9428 | (define_expand "stack_protect_test" | |
9429 | [(set (reg:CC CC_REGNUM) | |
9430 | (compare (match_operand 0 "memory_operand" "") | |
9431 | (match_operand 1 "memory_operand" ""))) | |
9432 | (match_operand 2 "" "")] | |
9433 | "" | |
9434 | { | |
f90b7a5a | 9435 | rtx cc_reg, test; |
7b8acc34 AK |
9436 | #ifdef TARGET_THREAD_SSP_OFFSET |
9437 | operands[1] | |
9438 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9439 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9440 | #endif | |
7b8acc34 AK |
9441 | if (TARGET_64BIT) |
9442 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
9443 | else | |
9444 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
9445 | ||
f90b7a5a PB |
9446 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
9447 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
9448 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
9449 | DONE; |
9450 | }) | |
9451 | ||
9452 | (define_insn "stack_protect_test<mode>" | |
9453 | [(set (reg:CCZ CC_REGNUM) | |
9454 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
9455 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
9456 | "" | |
9457 | "clc\t%O0(%G0,%R0),%S1" | |
9458 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
9459 | |
9460 | ; This is used in s390_emit_prologue in order to prevent insns | |
9461 | ; adjusting the stack pointer to be moved over insns writing stack | |
9462 | ; slots using a copy of the stack pointer in a different register. | |
9463 | (define_insn "stack_tie" | |
9464 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
9465 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
9466 | "" | |
9467 | "" | |
9468 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
9469 | |
9470 | ||
9471 | ; | |
9472 | ; Data prefetch patterns | |
9473 | ; | |
9474 | ||
9475 | (define_insn "prefetch" | |
22d72dbc AK |
9476 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
9477 | (match_operand:SI 1 "const_int_operand" " n,n") | |
9478 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
9479 | "TARGET_Z10" | |
963fc8d0 | 9480 | { |
4fe6dea8 AK |
9481 | switch (which_alternative) |
9482 | { | |
9483 | case 0: | |
4fe6dea8 | 9484 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 9485 | case 1: |
4fe6dea8 AK |
9486 | if (larl_operand (operands[0], Pmode)) |
9487 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
9488 | default: | |
9489 | ||
9490 | /* This might be reached for symbolic operands with an odd | |
9491 | addend. We simply omit the prefetch for such rare cases. */ | |
9492 | ||
9493 | return ""; | |
9494 | } | |
9381e3f1 | 9495 | } |
22d72dbc AK |
9496 | [(set_attr "type" "load,larl") |
9497 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
9498 | (set_attr "z10prop" "z10_super") |
9499 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
9500 | |
9501 | ||
9502 | ; | |
9503 | ; Byte swap instructions | |
9504 | ; | |
9505 | ||
9506 | (define_insn "bswap<mode>2" | |
9507 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
9508 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] | |
677fbff4 | 9509 | "TARGET_CPU_ZARCH" |
07da44ab AK |
9510 | "@ |
9511 | lrv<g>r\t%0,%1 | |
9512 | lrv<g>\t%0,%1" | |
9513 | [(set_attr "type" "*,load") | |
9514 | (set_attr "op_type" "RRE,RXY") | |
9515 | (set_attr "z10prop" "z10_super")]) | |
65b1d8ea AK |
9516 | |
9517 | ||
9518 | ; | |
9519 | ; Population count instruction | |
9520 | ; | |
9521 | ||
9522 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
9523 | ; portions and stores the result in the corresponding bytes in op0. | |
9524 | (define_insn "*popcount<mode>" | |
9525 | [(set (match_operand:INT 0 "register_operand" "=d") | |
9526 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
9527 | (clobber (reg:CC CC_REGNUM))] | |
9528 | "TARGET_Z196" | |
9529 | "popcnt\t%0,%1" | |
9530 | [(set_attr "op_type" "RRE")]) | |
9531 | ||
9532 | (define_expand "popcountdi2" | |
9533 | [; popcnt op0, op1 | |
9534 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
9535 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
9536 | UNSPEC_POPCNT)) | |
9537 | (clobber (reg:CC CC_REGNUM))]) | |
9538 | ; sllg op2, op0, 32 | |
9539 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
9540 | ; agr op0, op2 | |
9541 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9542 | (clobber (reg:CC CC_REGNUM))]) | |
9543 | ; sllg op2, op0, 16 | |
17465c6e | 9544 | (set (match_dup 2) |
65b1d8ea AK |
9545 | (ashift:DI (match_dup 0) (const_int 16))) |
9546 | ; agr op0, op2 | |
9547 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9548 | (clobber (reg:CC CC_REGNUM))]) | |
9549 | ; sllg op2, op0, 8 | |
9550 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
9551 | ; agr op0, op2 | |
9552 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9553 | (clobber (reg:CC CC_REGNUM))]) | |
9554 | ; srlg op0, op0, 56 | |
9555 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
9556 | "TARGET_Z196 && TARGET_64BIT" | |
9557 | "operands[2] = gen_reg_rtx (DImode);") | |
9558 | ||
9559 | (define_expand "popcountsi2" | |
9560 | [; popcnt op0, op1 | |
9561 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
9562 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
9563 | UNSPEC_POPCNT)) | |
9564 | (clobber (reg:CC CC_REGNUM))]) | |
9565 | ; sllk op2, op0, 16 | |
17465c6e | 9566 | (set (match_dup 2) |
65b1d8ea AK |
9567 | (ashift:SI (match_dup 0) (const_int 16))) |
9568 | ; ar op0, op2 | |
9569 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9570 | (clobber (reg:CC CC_REGNUM))]) | |
9571 | ; sllk op2, op0, 8 | |
9572 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
9573 | ; ar op0, op2 | |
9574 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9575 | (clobber (reg:CC CC_REGNUM))]) | |
9576 | ; srl op0, op0, 24 | |
9577 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
9578 | "TARGET_Z196" | |
9579 | "operands[2] = gen_reg_rtx (SImode);") | |
9580 | ||
9581 | (define_expand "popcounthi2" | |
9582 | [; popcnt op0, op1 | |
9583 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
9584 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
9585 | UNSPEC_POPCNT)) | |
9586 | (clobber (reg:CC CC_REGNUM))]) | |
9587 | ; sllk op2, op0, 8 | |
17465c6e | 9588 | (set (match_dup 2) |
65b1d8ea AK |
9589 | (ashift:SI (match_dup 0) (const_int 8))) |
9590 | ; ar op0, op2 | |
9591 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9592 | (clobber (reg:CC CC_REGNUM))]) | |
9593 | ; srl op0, op0, 8 | |
9594 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
9595 | "TARGET_Z196" | |
9596 | "operands[2] = gen_reg_rtx (SImode);") | |
9597 | ||
9598 | (define_expand "popcountqi2" | |
9599 | [; popcnt op0, op1 | |
9600 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
9601 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
9602 | UNSPEC_POPCNT)) | |
9603 | (clobber (reg:CC CC_REGNUM))])] | |
9604 | "TARGET_Z196" | |
9605 | "") | |
9606 | ||
9607 | ;; | |
9608 | ;;- Copy sign instructions | |
9609 | ;; | |
9610 | ||
9611 | (define_insn "copysign<mode>3" | |
9612 | [(set (match_operand:FP 0 "register_operand" "=f") | |
9613 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
9614 | (match_operand:FP 2 "register_operand" "f")] | |
9615 | UNSPEC_COPYSIGN))] | |
9616 | "TARGET_Z196" | |
9617 | "cpsdr\t%0,%2,%1" | |
9618 | [(set_attr "op_type" "RRF") | |
9619 | (set_attr "type" "fsimp<mode>")]) |