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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
66647d44 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, |
c75c517d | 3 | ;; 2009, 2010 Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
5 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
6 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 7 | |
58add37a UW |
8 | ;; This file is part of GCC. |
9 | ||
10 | ;; GCC is free software; you can redistribute it and/or modify it under | |
11 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
13 | ;; version. |
14 | ||
15 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | ;; for more details. | |
9db1d521 HP |
19 | |
20 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | ;; along with GCC; see the file COPYING3. If not see |
22 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
23 | |
24 | ;; | |
cd8dc1f9 | 25 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 26 | ;; |
cd8dc1f9 | 27 | |
9db1d521 HP |
28 | ;; Special formats used for outputting 390 instructions. |
29 | ;; | |
f19a9af7 AK |
30 | ;; %C: print opcode suffix for branch condition. |
31 | ;; %D: print opcode suffix for inverse branch condition. | |
32 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 33 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
34 | ;; %O: print only the displacement of a memory reference. |
35 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 36 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
37 | ;; %N: print the second word of a DImode operand. |
38 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 39 | ;; %Y: print shift count operand. |
f4aa3848 | 40 | ;; |
f19a9af7 | 41 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 42 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
43 | ;; %x: print integer X as if it's an unsigned halfword. |
44 | ;; %h: print integer X as if it's a signed halfword. | |
45 | ;; %i: print the first nonzero HImode part of X. | |
46 | ;; %j: print the first HImode part unequal to -1 of X. | |
47 | ;; %k: print the first nonzero SImode part of X. | |
48 | ;; %m: print the first SImode part unequal to -1 of X. | |
49 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
50 | ;; |
51 | ;; We have a special constraint for pattern matching. | |
52 | ;; | |
53 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
54 | ;; | |
9db1d521 | 55 | |
fd3cd001 UW |
56 | ;; |
57 | ;; UNSPEC usage | |
58 | ;; | |
59 | ||
60 | (define_constants | |
10bbf137 UW |
61 | [; Miscellaneous |
62 | (UNSPEC_ROUND 1) | |
638e37c2 WG |
63 | (UNSPEC_CCU_TO_INT 2) |
64 | (UNSPEC_CCZ_TO_INT 3) | |
6fa05db6 | 65 | (UNSPEC_ICM 10) |
12959abe | 66 | (UNSPEC_TIE 11) |
10bbf137 UW |
67 | |
68 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
69 | (UNSPEC_LTREL_OFFSET 100) |
70 | (UNSPEC_LTREL_BASE 101) | |
dc66391d | 71 | (UNSPEC_POOL_OFFSET 102) |
fd7643fb UW |
72 | (UNSPEC_GOTENT 110) |
73 | (UNSPEC_GOT 111) | |
74 | (UNSPEC_GOTOFF 112) | |
75 | (UNSPEC_PLT 113) | |
76 | (UNSPEC_PLTOFF 114) | |
77 | ||
78 | ; Literal pool | |
79 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 80 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 81 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
82 | (UNSPEC_INSN 213) |
83 | (UNSPEC_EXECUTE 214) | |
fd7643fb | 84 | |
1a8c13b3 UB |
85 | ; Atomic Support |
86 | (UNSPEC_MB 400) | |
87 | ||
fd7643fb | 88 | ; TLS relocation specifiers |
fd3cd001 UW |
89 | (UNSPEC_TLSGD 500) |
90 | (UNSPEC_TLSLDM 501) | |
91 | (UNSPEC_NTPOFF 502) | |
92 | (UNSPEC_DTPOFF 503) | |
93 | (UNSPEC_GOTNTPOFF 504) | |
94 | (UNSPEC_INDNTPOFF 505) | |
95 | ||
96 | ; TLS support | |
fd3cd001 UW |
97 | (UNSPEC_TLSLDM_NTPOFF 511) |
98 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
99 | |
100 | ; String Functions | |
7b8acc34 | 101 | (UNSPEC_SRST 600) |
742090fc | 102 | (UNSPEC_MVST 601) |
638e37c2 | 103 | |
7b8acc34 AK |
104 | ; Stack Smashing Protector |
105 | (UNSPEC_SP_SET 700) | |
106 | (UNSPEC_SP_TEST 701) | |
85dae55a | 107 | |
638e37c2 | 108 | ; Test Data Class (TDC) |
30972225 | 109 | (UNSPEC_TDC_INSN 800) |
65b1d8ea AK |
110 | |
111 | ; Population Count | |
112 | (UNSPEC_POPCNT 900) | |
113 | (UNSPEC_COPYSIGN 901) | |
fd3cd001 UW |
114 | ]) |
115 | ||
116 | ;; | |
117 | ;; UNSPEC_VOLATILE usage | |
118 | ;; | |
119 | ||
120 | (define_constants | |
10bbf137 UW |
121 | [; Blockage |
122 | (UNSPECV_BLOCKAGE 0) | |
123 | ||
2f7e5a0d EC |
124 | ; TPF Support |
125 | (UNSPECV_TPF_PROLOGUE 20) | |
126 | (UNSPECV_TPF_EPILOGUE 21) | |
127 | ||
10bbf137 | 128 | ; Literal pool |
fd7643fb | 129 | (UNSPECV_POOL 200) |
9bb86f41 UW |
130 | (UNSPECV_POOL_SECTION 201) |
131 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 132 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
133 | (UNSPECV_MAIN_POOL 300) |
134 | ||
135 | ; TLS support | |
fd3cd001 | 136 | (UNSPECV_SET_TP 500) |
e0374221 AS |
137 | |
138 | ; Atomic Support | |
1a8c13b3 | 139 | (UNSPECV_CAS 700) |
65b1d8ea | 140 | (UNSPECV_ATOMIC_OP 701) |
fd3cd001 UW |
141 | ]) |
142 | ||
ae156f85 AS |
143 | ;; |
144 | ;; Registers | |
145 | ;; | |
146 | ||
35dd9a0e AK |
147 | ; Registers with special meaning |
148 | ||
ae156f85 AS |
149 | (define_constants |
150 | [ | |
151 | ; Sibling call register. | |
152 | (SIBCALL_REGNUM 1) | |
153 | ; Literal pool base register. | |
154 | (BASE_REGNUM 13) | |
155 | ; Return address register. | |
156 | (RETURN_REGNUM 14) | |
157 | ; Condition code register. | |
158 | (CC_REGNUM 33) | |
f4aa3848 | 159 | ; Thread local storage pointer register. |
ae156f85 AS |
160 | (TP_REGNUM 36) |
161 | ]) | |
162 | ||
35dd9a0e AK |
163 | ; Hardware register names |
164 | ||
165 | (define_constants | |
166 | [ | |
167 | ; General purpose registers | |
168 | (GPR0_REGNUM 0) | |
169 | ; Floating point registers. | |
170 | (FPR0_REGNUM 16) | |
171 | (FPR2_REGNUM 18) | |
172 | ]) | |
173 | ||
174 | ;; | |
175 | ;; PFPO GPR0 argument format | |
176 | ;; | |
177 | ||
178 | (define_constants | |
179 | [ | |
180 | ; PFPO operation type | |
181 | (PFPO_CONVERT 0x1000000) | |
182 | ; PFPO operand types | |
183 | (PFPO_OP_TYPE_SF 0x5) | |
184 | (PFPO_OP_TYPE_DF 0x6) | |
185 | (PFPO_OP_TYPE_TF 0x7) | |
186 | (PFPO_OP_TYPE_SD 0x8) | |
187 | (PFPO_OP_TYPE_DD 0x9) | |
188 | (PFPO_OP_TYPE_TD 0xa) | |
189 | ; Bitposition of operand types | |
190 | (PFPO_OP0_TYPE_SHIFT 16) | |
191 | (PFPO_OP1_TYPE_SHIFT 8) | |
192 | ]) | |
193 | ||
fd3cd001 | 194 | |
29a74354 UW |
195 | ;; Instruction operand type as used in the Principles of Operation. |
196 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 197 | |
29a74354 | 198 | (define_attr "op_type" |
963fc8d0 | 199 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" |
b628bd8e | 200 | (const_string "NN")) |
9db1d521 | 201 | |
29a74354 | 202 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 203 | |
077dab3b | 204 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 205 | cs,vs,store,sem,idiv, |
ed0e512a | 206 | imulhi,imulsi,imuldi, |
2cdece44 | 207 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
208 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
209 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 210 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 211 | fmadddf,fmaddsf, |
9381e3f1 WG |
212 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
213 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
214 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
215 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
216 | ftoidfp, other" | |
29a74354 UW |
217 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
218 | (eq_attr "op_type" "SS") (const_string "cs")] | |
219 | (const_string "integer"))) | |
9db1d521 | 220 | |
29a74354 UW |
221 | ;; Another attribute used for scheduling purposes: |
222 | ;; agen: Instruction uses the address generation unit | |
223 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
224 | |
225 | (define_attr "atype" "agen,reg" | |
c68e7b86 | 226 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") |
0101708c AS |
227 | (const_string "reg") |
228 | (const_string "agen"))) | |
9db1d521 | 229 | |
9381e3f1 WG |
230 | ;; Properties concerning Z10 execution grouping and value forwarding. |
231 | ;; z10_super: instruction is superscalar. | |
232 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
233 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
234 | ;; target register. It can forward this value to a second instruction that reads | |
235 | ;; the same register if that second instruction is issued in the same group. | |
236 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
237 | ;; instruction in the S pipe writes to the register, then the T instruction | |
238 | ;; can immediately read the new value. | |
239 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
240 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
241 | ;; |
242 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
243 | ||
244 | ||
245 | (define_attr "z10prop" "none, | |
246 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
247 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
248 | z10_rec, | |
249 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 250 | z10_c" |
9381e3f1 WG |
251 | (const_string "none")) |
252 | ||
65b1d8ea AK |
253 | ;; Properties concerning Z196 decoding |
254 | ;; z196_alone: must group alone | |
255 | ;; z196_end: ends a group | |
256 | ;; z196_cracked: instruction is cracked or expanded | |
257 | (define_attr "z196prop" "none, | |
258 | z196_alone, z196_ends, | |
259 | z196_cracked" | |
260 | (const_string "none")) | |
9381e3f1 | 261 | |
9db1d521 HP |
262 | ;; Length in bytes. |
263 | ||
264 | (define_attr "length" "" | |
963fc8d0 AK |
265 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
266 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 267 | (const_int 6))) |
9db1d521 | 268 | |
29a74354 UW |
269 | |
270 | ;; Processor type. This attribute must exactly match the processor_type | |
271 | ;; enumeration in s390.h. The current machine description does not | |
272 | ;; distinguish between g5 and g6, but there are differences between the two | |
273 | ;; CPUs could in theory be modeled. | |
274 | ||
65b1d8ea | 275 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z10,z196" |
90c6fd8a | 276 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 277 | |
65b1d8ea | 278 | (define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196" |
3af8e996 AK |
279 | (const_string "standard")) |
280 | ||
281 | (define_attr "enabled" "" | |
282 | (cond [(eq_attr "cpu_facility" "standard") | |
283 | (const_int 1) | |
284 | ||
285 | (and (eq_attr "cpu_facility" "ieee") | |
286 | (ne (symbol_ref "TARGET_CPU_IEEE_FLOAT") (const_int 0))) | |
287 | (const_int 1) | |
288 | ||
289 | (and (eq_attr "cpu_facility" "zarch") | |
290 | (ne (symbol_ref "TARGET_ZARCH") (const_int 0))) | |
291 | (const_int 1) | |
292 | ||
293 | (and (eq_attr "cpu_facility" "longdisp") | |
294 | (ne (symbol_ref "TARGET_LONG_DISPLACEMENT") (const_int 0))) | |
295 | (const_int 1) | |
296 | ||
297 | (and (eq_attr "cpu_facility" "extimm") | |
298 | (ne (symbol_ref "TARGET_EXTIMM") (const_int 0))) | |
299 | (const_int 1) | |
300 | ||
301 | (and (eq_attr "cpu_facility" "dfp") | |
302 | (ne (symbol_ref "TARGET_DFP") (const_int 0))) | |
93538e8e AK |
303 | (const_int 1) |
304 | ||
305 | (and (eq_attr "cpu_facility" "z10") | |
306 | (ne (symbol_ref "TARGET_Z10") (const_int 0))) | |
65b1d8ea AK |
307 | (const_int 1) |
308 | ||
309 | (and (eq_attr "cpu_facility" "z196") | |
310 | (ne (symbol_ref "TARGET_Z196") (const_int 0))) | |
3af8e996 AK |
311 | (const_int 1)] |
312 | (const_int 0))) | |
313 | ||
29a74354 UW |
314 | ;; Pipeline description for z900. For lack of anything better, |
315 | ;; this description is also used for the g5 and g6. | |
316 | (include "2064.md") | |
317 | ||
3443392a | 318 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
319 | (include "2084.md") |
320 | ||
9381e3f1 WG |
321 | ;; Pipeline description for z10 |
322 | (include "2097.md") | |
323 | ||
65b1d8ea AK |
324 | ;; Pipeline description for z196 |
325 | (include "2817.md") | |
326 | ||
0bfc3f69 AS |
327 | ;; Predicates |
328 | (include "predicates.md") | |
329 | ||
cd8dc1f9 WG |
330 | ;; Constraint definitions |
331 | (include "constraints.md") | |
332 | ||
a8ba31f2 EC |
333 | ;; Other includes |
334 | (include "tpf.md") | |
f52c81dd | 335 | |
3abcb3a7 | 336 | ;; Iterators |
f52c81dd | 337 | |
3abcb3a7 | 338 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 339 | ;; same template. |
f4aa3848 | 340 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 341 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 | 342 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
963fc8d0 | 343 | (define_mode_iterator FPALL [TF DF SF TD DD SD]) |
3abcb3a7 HPN |
344 | (define_mode_iterator BFP [TF DF SF]) |
345 | (define_mode_iterator DFP [TD DD]) | |
346 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
347 | (define_mode_iterator DSF [DF SF]) | |
348 | (define_mode_iterator SD_SF [SF SD]) | |
349 | (define_mode_iterator DD_DF [DF DD]) | |
350 | (define_mode_iterator TD_TF [TF TD]) | |
351 | ||
352 | ;; This mode iterator allows 31-bit and 64-bit TDSI patterns to be generated | |
8006eaa6 | 353 | ;; from the same template. |
3abcb3a7 | 354 | (define_mode_iterator TDSI [(TI "TARGET_64BIT") DI SI]) |
8006eaa6 | 355 | |
3abcb3a7 | 356 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 357 | ;; from the same template. |
9602b6a1 | 358 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
3abcb3a7 | 359 | (define_mode_iterator DSI [DI SI]) |
9db2f16d | 360 | |
3abcb3a7 | 361 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 362 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 363 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 364 | |
9602b6a1 AK |
365 | ;; These macros refer to the actual word_mode of the configuration. This is equal |
366 | ;; to Pmode except on 31-bit machines in zarch mode. | |
367 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) | |
368 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
369 | ||
3abcb3a7 | 370 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 371 | ;; the same template. |
3abcb3a7 | 372 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 373 | |
3abcb3a7 | 374 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 375 | ;; same template. |
9602b6a1 | 376 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
963fc8d0 | 377 | (define_mode_iterator INTALL [TI DI SI HI QI]) |
342cf42b | 378 | |
3abcb3a7 | 379 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 380 | ;; the same template. |
3abcb3a7 | 381 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 382 | |
3abcb3a7 HPN |
383 | ;; This iterator and attribute allow to combine most atomic operations. |
384 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 385 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
f4aa3848 | 386 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") |
45d18331 | 387 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 388 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 389 | |
f4aa3848 | 390 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
391 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
392 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 393 | |
f4aa3848 AK |
394 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
395 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
396 | ;; SDmode. |
397 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 398 | |
609e7e80 | 399 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
400 | ;; Likewise for "<RXe>". |
401 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
402 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
403 | ||
609e7e80 | 404 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 405 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
406 | ;; dfp variants in a single insn definition. |
407 | ||
3abcb3a7 | 408 | ;; This attribute is used to set op_type accordingly. |
f4aa3848 | 409 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
609e7e80 AK |
410 | (DD "RRR") (SD "RRR")]) |
411 | ||
f4aa3848 | 412 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
413 | ;; first and the second operand match for bfp modes. |
414 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
415 | ||
f4aa3848 | 416 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
417 | ;; additional operand for the dfp instructions. |
418 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
419 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
420 | ||
f5905b37 | 421 | |
85dae55a AK |
422 | ;; This attribute is used in the operand constraint list |
423 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
424 | ;; TFmode values are represented by a fp register pair. Since the | |
425 | ;; sign bit instructions only handle single source and target fp registers | |
426 | ;; these instructions can only be used for TFmode values if the source and | |
427 | ;; target operand uses the same fp register. | |
428 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
429 | ||
609e7e80 AK |
430 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
431 | ;; This is used to disable the memory alternative in TFmode patterns. | |
432 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
433 | ||
3abcb3a7 | 434 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
435 | ;; within instruction mnemonics. |
436 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
437 | ||
0387c142 WG |
438 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
439 | ;; modes and to an empty string for bfp modes. | |
440 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
441 | ||
1b48c8cc AS |
442 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
443 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
444 | ;; version only operates on one register. | |
445 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
446 | ||
447 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
448 | ;; version only operates on one register. The DImode version needs an additional | |
449 | ;; register for the assembler output. | |
450 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
451 | |
452 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
453 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
454 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
455 | ||
456 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 457 | ;; pattern itself and the corresponding function calls. |
f337b930 | 458 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
459 | |
460 | ;; This attribute handles differences in the instruction 'type' and will result | |
461 | ;; in "RRE" for DImode and "RR" for SImode. | |
462 | (define_mode_attr E [(DI "E") (SI "")]) | |
463 | ||
3298c037 AK |
464 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
465 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
466 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
467 | ||
8006eaa6 AS |
468 | ;; This attribute handles differences in the instruction 'type' and will result |
469 | ;; in "RSE" for TImode and "RS" for DImode. | |
470 | (define_mode_attr TE [(TI "E") (DI "")]) | |
471 | ||
9a91a21f AS |
472 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
473 | ;; and "lcr" in SImode. | |
474 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 475 | |
3298c037 AK |
476 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
477 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
478 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
479 | ;; variant for long displacements. | |
480 | (define_mode_attr y [(DI "g") (SI "y")]) | |
481 | ||
9602b6a1 | 482 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
483 | ;; and "cds" in DImode. |
484 | (define_mode_attr tg [(TI "g") (DI "")]) | |
485 | ||
2f8f8434 AS |
486 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
487 | ;; and "cfdbr" in SImode. | |
488 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
489 | ||
65b1d8ea AK |
490 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
491 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
492 | ;; 3 operands shift instructions into the existing patterns. | |
493 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
494 | ||
f52c81dd AS |
495 | ;; ICM mask required to load MODE value into the lowest subreg |
496 | ;; of a SImode register. | |
497 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
498 | ||
f6ee577c AS |
499 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
500 | ;; HImode and "llgc" in QImode. | |
501 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
502 | ||
a1aed706 AS |
503 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
504 | ;; in SImode. | |
505 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
506 | ||
609e7e80 AK |
507 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
508 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
509 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
510 | ||
f52c81dd AS |
511 | ;; Maximum unsigned integer that fits in MODE. |
512 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
513 | ||
9db1d521 HP |
514 | ;; |
515 | ;;- Compare instructions. | |
516 | ;; | |
517 | ||
07893d4f | 518 | ; Test-under-Mask instructions |
9db1d521 | 519 | |
07893d4f | 520 | (define_insn "*tmqi_mem" |
ae156f85 | 521 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
522 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
523 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
524 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 525 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 526 | "@ |
fc0ea003 UW |
527 | tm\t%S0,%b1 |
528 | tmy\t%S0,%b1" | |
9381e3f1 WG |
529 | [(set_attr "op_type" "SI,SIY") |
530 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 531 | |
05b9aaaa | 532 | (define_insn "*tmdi_reg" |
ae156f85 | 533 | [(set (reg CC_REGNUM) |
f19a9af7 | 534 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 535 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
536 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
537 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 538 | "TARGET_ZARCH |
3ed99cc9 | 539 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
540 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
541 | "@ | |
542 | tmhh\t%0,%i1 | |
543 | tmhl\t%0,%i1 | |
544 | tmlh\t%0,%i1 | |
545 | tmll\t%0,%i1" | |
9381e3f1 WG |
546 | [(set_attr "op_type" "RI") |
547 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
548 | |
549 | (define_insn "*tmsi_reg" | |
ae156f85 | 550 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
551 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
552 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
553 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 554 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
555 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
556 | "@ | |
557 | tmh\t%0,%i1 | |
558 | tml\t%0,%i1" | |
729e750f WG |
559 | [(set_attr "op_type" "RI") |
560 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 561 | |
f52c81dd | 562 | (define_insn "*tm<mode>_full" |
ae156f85 | 563 | [(set (reg CC_REGNUM) |
f52c81dd AS |
564 | (compare (match_operand:HQI 0 "register_operand" "d") |
565 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 566 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 567 | "tml\t%0,<max_uint>" |
729e750f WG |
568 | [(set_attr "op_type" "RI") |
569 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 570 | |
07893d4f | 571 | |
08a5aaa2 | 572 | ; |
07893d4f | 573 | ; Load-and-Test instructions |
08a5aaa2 AS |
574 | ; |
575 | ||
c0220ea4 | 576 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
577 | |
578 | (define_insn "*tstdi_sign" | |
ae156f85 | 579 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
580 | (compare |
581 | (ashiftrt:DI | |
582 | (ashift:DI | |
583 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
584 | (const_int 32)) (const_int 32)) | |
585 | (match_operand:DI 1 "const0_operand" ""))) | |
586 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 587 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 588 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
589 | "ltgfr\t%2,%0 |
590 | ltgf\t%2,%0" | |
591 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
592 | (set_attr "cpu_facility" "*,z10") |
593 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 594 | |
43a09b63 | 595 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 596 | (define_insn "*tst<mode>_extimm" |
ec24698e | 597 | [(set (reg CC_REGNUM) |
fb492564 | 598 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
599 | (match_operand:GPR 1 "const0_operand" ""))) |
600 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 601 | (match_dup 0))] |
08a5aaa2 | 602 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 603 | "@ |
08a5aaa2 AS |
604 | lt<g>r\t%2,%0 |
605 | lt<g>\t%2,%0" | |
9381e3f1 | 606 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 607 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 608 | |
43a09b63 | 609 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 610 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 611 | [(set (reg CC_REGNUM) |
fb492564 | 612 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
613 | (match_operand:GPR 1 "const0_operand" ""))) |
614 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
615 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 616 | "@ |
08a5aaa2 AS |
617 | lt<g>r\t%0,%0 |
618 | lt<g>\t%2,%0" | |
9381e3f1 | 619 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 620 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 621 | |
07893d4f | 622 | (define_insn "*tstdi" |
ae156f85 | 623 | [(set (reg CC_REGNUM) |
07893d4f UW |
624 | (compare (match_operand:DI 0 "register_operand" "d") |
625 | (match_operand:DI 1 "const0_operand" ""))) | |
626 | (set (match_operand:DI 2 "register_operand" "=d") | |
627 | (match_dup 0))] | |
9602b6a1 | 628 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 629 | "ltgr\t%2,%0" |
9381e3f1 WG |
630 | [(set_attr "op_type" "RRE") |
631 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 632 | |
07893d4f | 633 | (define_insn "*tstsi" |
ae156f85 | 634 | [(set (reg CC_REGNUM) |
d3632d41 | 635 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 636 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 637 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 638 | (match_dup 0))] |
ec24698e | 639 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 640 | "@ |
d40c829f | 641 | ltr\t%2,%0 |
fc0ea003 UW |
642 | icm\t%2,15,%S0 |
643 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
644 | [(set_attr "op_type" "RR,RS,RSY") |
645 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 646 | |
07893d4f | 647 | (define_insn "*tstsi_cconly" |
ae156f85 | 648 | [(set (reg CC_REGNUM) |
d3632d41 | 649 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 650 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 651 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
652 | "s390_match_ccmode(insn, CCSmode)" |
653 | "@ | |
d40c829f | 654 | ltr\t%0,%0 |
fc0ea003 UW |
655 | icm\t%2,15,%S0 |
656 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
657 | [(set_attr "op_type" "RR,RS,RSY") |
658 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 659 | |
08a5aaa2 AS |
660 | (define_insn "*tstdi_cconly_31" |
661 | [(set (reg CC_REGNUM) | |
662 | (compare (match_operand:DI 0 "register_operand" "d") | |
663 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 664 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
665 | "srda\t%0,0" |
666 | [(set_attr "op_type" "RS") | |
667 | (set_attr "atype" "reg")]) | |
668 | ||
43a09b63 | 669 | ; ltr, ltgr |
08a5aaa2 | 670 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 671 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
672 | (compare (match_operand:GPR 0 "register_operand" "d") |
673 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 674 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 675 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
676 | [(set_attr "op_type" "RR<E>") |
677 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 678 | |
c0220ea4 | 679 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 680 | |
f52c81dd | 681 | (define_insn "*tst<mode>CCT" |
ae156f85 | 682 | [(set (reg CC_REGNUM) |
f52c81dd AS |
683 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
684 | (match_operand:HQI 1 "const0_operand" ""))) | |
685 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
686 | (match_dup 0))] |
687 | "s390_match_ccmode(insn, CCTmode)" | |
688 | "@ | |
f52c81dd AS |
689 | icm\t%2,<icm_lo>,%S0 |
690 | icmy\t%2,<icm_lo>,%S0 | |
691 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
692 | [(set_attr "op_type" "RS,RSY,RI") |
693 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
694 | |
695 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 696 | [(set (reg CC_REGNUM) |
d3632d41 | 697 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 698 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 699 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
700 | "s390_match_ccmode(insn, CCTmode)" |
701 | "@ | |
fc0ea003 UW |
702 | icm\t%2,3,%S0 |
703 | icmy\t%2,3,%S0 | |
d40c829f | 704 | tml\t%0,65535" |
9381e3f1 WG |
705 | [(set_attr "op_type" "RS,RSY,RI") |
706 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 707 | |
3af97654 | 708 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 709 | [(set (reg CC_REGNUM) |
d3632d41 | 710 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
711 | (match_operand:QI 1 "const0_operand" "")))] |
712 | "s390_match_ccmode(insn, CCTmode)" | |
713 | "@ | |
fc0ea003 UW |
714 | cli\t%S0,0 |
715 | cliy\t%S0,0 | |
d40c829f | 716 | tml\t%0,255" |
9381e3f1 | 717 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 718 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 719 | |
f52c81dd | 720 | (define_insn "*tst<mode>" |
ae156f85 | 721 | [(set (reg CC_REGNUM) |
f52c81dd AS |
722 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
723 | (match_operand:HQI 1 "const0_operand" ""))) | |
724 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
725 | (match_dup 0))] |
726 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 727 | "@ |
f52c81dd AS |
728 | icm\t%2,<icm_lo>,%S0 |
729 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
730 | [(set_attr "op_type" "RS,RSY") |
731 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 732 | |
f52c81dd | 733 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 734 | [(set (reg CC_REGNUM) |
f52c81dd AS |
735 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
736 | (match_operand:HQI 1 "const0_operand" ""))) | |
737 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 738 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 739 | "@ |
f52c81dd AS |
740 | icm\t%2,<icm_lo>,%S0 |
741 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
742 | [(set_attr "op_type" "RS,RSY") |
743 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 744 | |
9db1d521 | 745 | |
575f7c2b UW |
746 | ; Compare (equality) instructions |
747 | ||
748 | (define_insn "*cmpdi_cct" | |
ae156f85 | 749 | [(set (reg CC_REGNUM) |
ec24698e | 750 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 751 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 752 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
753 | "@ |
754 | cgr\t%0,%1 | |
f4f41b4e | 755 | cghi\t%0,%h1 |
ec24698e | 756 | cgfi\t%0,%1 |
575f7c2b | 757 | cg\t%0,%1 |
19b63d8e | 758 | #" |
9381e3f1 WG |
759 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
760 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
761 | |
762 | (define_insn "*cmpsi_cct" | |
ae156f85 | 763 | [(set (reg CC_REGNUM) |
ec24698e UW |
764 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
765 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 766 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
767 | "@ |
768 | cr\t%0,%1 | |
f4f41b4e | 769 | chi\t%0,%h1 |
ec24698e | 770 | cfi\t%0,%1 |
575f7c2b UW |
771 | c\t%0,%1 |
772 | cy\t%0,%1 | |
19b63d8e | 773 | #" |
9381e3f1 | 774 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 775 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 776 | |
07893d4f | 777 | ; Compare (signed) instructions |
4023fb28 | 778 | |
07893d4f | 779 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 780 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
781 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
782 | "d,RT,b")) | |
783 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 784 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 785 | "@ |
d40c829f | 786 | cgfr\t%0,%1 |
963fc8d0 AK |
787 | cgf\t%0,%1 |
788 | cgfrl\t%0,%1" | |
789 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 790 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 791 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 792 | |
9381e3f1 WG |
793 | |
794 | ||
07893d4f | 795 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 796 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
797 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
798 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 799 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 800 | "@ |
d40c829f | 801 | ch\t%0,%1 |
963fc8d0 AK |
802 | chy\t%0,%1 |
803 | chrl\t%0,%1" | |
804 | [(set_attr "op_type" "RX,RXY,RIL") | |
805 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
806 | (set_attr "type" "*,*,larl") |
807 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
808 | |
809 | (define_insn "*cmphi_ccs_z10" | |
810 | [(set (reg CC_REGNUM) | |
811 | (compare (match_operand:HI 0 "s_operand" "Q") | |
812 | (match_operand:HI 1 "immediate_operand" "K")))] | |
813 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
814 | "chhsi\t%0,%1" | |
65b1d8ea AK |
815 | [(set_attr "op_type" "SIL") |
816 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
817 | |
818 | (define_insn "*cmpdi_ccs_signhi_rl" | |
819 | [(set (reg CC_REGNUM) | |
820 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
821 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
822 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
823 | "@ | |
824 | cgh\t%0,%1 | |
825 | cghrl\t%0,%1" | |
826 | [(set_attr "op_type" "RXY,RIL") | |
827 | (set_attr "type" "*,larl")]) | |
4023fb28 | 828 | |
963fc8d0 | 829 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 830 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 831 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
832 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
833 | "d,d,Q, d,d,d,d") | |
834 | (match_operand:GPR 1 "general_operand" | |
835 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 836 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 837 | "@ |
3298c037 AK |
838 | c<g>r\t%0,%1 |
839 | c<g>hi\t%0,%h1 | |
963fc8d0 | 840 | c<g>hsi\t%0,%h1 |
3298c037 AK |
841 | c<g>fi\t%0,%1 |
842 | c<g>\t%0,%1 | |
963fc8d0 AK |
843 | c<y>\t%0,%1 |
844 | c<g>rl\t%0,%1" | |
845 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
846 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
847 | (set_attr "type" "*,*,*,*,*,*,larl") |
848 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 849 | |
07893d4f UW |
850 | |
851 | ; Compare (unsigned) instructions | |
9db1d521 | 852 | |
963fc8d0 AK |
853 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
854 | [(set (reg CC_REGNUM) | |
855 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
856 | "larl_operand" "X"))) | |
857 | (match_operand:SI 0 "register_operand" "d")))] | |
858 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
859 | "clhrl\t%0,%1" | |
860 | [(set_attr "op_type" "RIL") | |
729e750f WG |
861 | (set_attr "type" "larl") |
862 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
863 | |
864 | ; clhrl, clghrl | |
865 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
866 | [(set (reg CC_REGNUM) | |
867 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
868 | "larl_operand" "X"))) | |
869 | (match_operand:GPR 0 "register_operand" "d")))] | |
870 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
871 | "cl<g>hrl\t%0,%1" | |
872 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
873 | (set_attr "type" "larl") |
874 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 875 | |
07893d4f | 876 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 877 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
878 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
879 | "d,RT,b")) | |
880 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 881 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 882 | "@ |
d40c829f | 883 | clgfr\t%0,%1 |
963fc8d0 AK |
884 | clgf\t%0,%1 |
885 | clgfrl\t%0,%1" | |
886 | [(set_attr "op_type" "RRE,RXY,RIL") | |
887 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
888 | (set_attr "type" "*,*,larl") |
889 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 890 | |
07893d4f | 891 | (define_insn "*cmpdi_ccu" |
ae156f85 | 892 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
893 | (compare (match_operand:DI 0 "nonimmediate_operand" |
894 | "d, d,d,Q, d, Q,BQ") | |
895 | (match_operand:DI 1 "general_operand" | |
896 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 897 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 898 | "@ |
d40c829f | 899 | clgr\t%0,%1 |
ec24698e | 900 | clgfi\t%0,%1 |
963fc8d0 AK |
901 | clgrl\t%0,%1 |
902 | clghsi\t%0,%x1 | |
575f7c2b | 903 | clg\t%0,%1 |
e221ef54 | 904 | # |
19b63d8e | 905 | #" |
963fc8d0 AK |
906 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
907 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
908 | (set_attr "type" "*,*,larl,*,*,*,*") |
909 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 910 | |
07893d4f | 911 | (define_insn "*cmpsi_ccu" |
ae156f85 | 912 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
913 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
914 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 915 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 916 | "@ |
d40c829f | 917 | clr\t%0,%1 |
ec24698e | 918 | clfi\t%0,%o1 |
963fc8d0 AK |
919 | clrl\t%0,%1 |
920 | clfhsi\t%0,%x1 | |
d40c829f | 921 | cl\t%0,%1 |
575f7c2b | 922 | cly\t%0,%1 |
e221ef54 | 923 | # |
19b63d8e | 924 | #" |
963fc8d0 AK |
925 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
926 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
927 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
928 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 929 | |
07893d4f | 930 | (define_insn "*cmphi_ccu" |
ae156f85 | 931 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
932 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
933 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 934 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 935 | && !register_operand (operands[1], HImode)" |
d3632d41 | 936 | "@ |
fc0ea003 UW |
937 | clm\t%0,3,%S1 |
938 | clmy\t%0,3,%S1 | |
963fc8d0 | 939 | clhhsi\t%0,%1 |
e221ef54 | 940 | # |
19b63d8e | 941 | #" |
963fc8d0 | 942 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
943 | (set_attr "cpu_facility" "*,*,z10,*,*") |
944 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
945 | |
946 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 947 | [(set (reg CC_REGNUM) |
e221ef54 UW |
948 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
949 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 950 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 951 | && !register_operand (operands[1], QImode)" |
d3632d41 | 952 | "@ |
fc0ea003 UW |
953 | clm\t%0,1,%S1 |
954 | clmy\t%0,1,%S1 | |
955 | cli\t%S0,%b1 | |
956 | cliy\t%S0,%b1 | |
e221ef54 | 957 | # |
19b63d8e | 958 | #" |
9381e3f1 WG |
959 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
960 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
961 | |
962 | ||
19b63d8e UW |
963 | ; Block compare (CLC) instruction patterns. |
964 | ||
965 | (define_insn "*clc" | |
ae156f85 | 966 | [(set (reg CC_REGNUM) |
d4f52f0e | 967 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
968 | (match_operand:BLK 1 "memory_operand" "Q"))) |
969 | (use (match_operand 2 "const_int_operand" "n"))] | |
970 | "s390_match_ccmode (insn, CCUmode) | |
971 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 972 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 973 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
974 | |
975 | (define_split | |
ae156f85 | 976 | [(set (reg CC_REGNUM) |
19b63d8e UW |
977 | (compare (match_operand 0 "memory_operand" "") |
978 | (match_operand 1 "memory_operand" "")))] | |
979 | "reload_completed | |
980 | && s390_match_ccmode (insn, CCUmode) | |
981 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
982 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
983 | [(parallel | |
984 | [(set (match_dup 0) (match_dup 1)) | |
985 | (use (match_dup 2))])] | |
986 | { | |
987 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
988 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
989 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
990 | ||
991 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
992 | operands[0], operands[1]); | |
993 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
994 | }) | |
995 | ||
996 | ||
609e7e80 | 997 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 998 | |
609e7e80 | 999 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1000 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1001 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1002 | (compare (match_operand:FP 0 "register_operand" "f") |
1003 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1004 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1005 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1006 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1007 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1008 | |
d46f24b6 | 1009 | ; cxtr, cxbr, cdbr, cebr, cdb, ceb, cxbtr, cdbtr |
f5905b37 | 1010 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1011 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1012 | (compare (match_operand:FP 0 "register_operand" "f,f") |
1013 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 1014 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1015 | "@ |
609e7e80 | 1016 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1017 | c<xde>b\t%0,%1" |
077dab3b | 1018 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 1019 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1020 | |
963fc8d0 AK |
1021 | |
1022 | ; Compare and Branch instructions | |
1023 | ||
1024 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1025 | ; The following instructions do a complementary access of their second |
1026 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1027 | (define_insn "*cmp_and_br_signed_<mode>" |
1028 | [(set (pc) | |
1029 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1030 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1031 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1032 | (label_ref (match_operand 3 "" "")) | |
1033 | (pc))) | |
1034 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1035 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1036 | { |
1037 | if (get_attr_length (insn) == 6) | |
1038 | return which_alternative ? | |
1039 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1040 | else | |
1041 | return which_alternative ? | |
1042 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1043 | } | |
1044 | [(set_attr "op_type" "RIE") | |
1045 | (set_attr "type" "branch") | |
e3cba5e5 | 1046 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1047 | (set (attr "length") |
1048 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1049 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1050 | ; 10 byte for cgr/jg | |
1051 | ||
1052 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1053 | ; The following instructions do a complementary access of their second |
1054 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1055 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1056 | [(set (pc) | |
1057 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1058 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1059 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1060 | (label_ref (match_operand 3 "" "")) | |
1061 | (pc))) | |
1062 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1063 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1064 | { |
1065 | if (get_attr_length (insn) == 6) | |
1066 | return which_alternative ? | |
1067 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1068 | else | |
1069 | return which_alternative ? | |
1070 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1071 | } | |
1072 | [(set_attr "op_type" "RIE") | |
1073 | (set_attr "type" "branch") | |
e3cba5e5 | 1074 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1075 | (set (attr "length") |
1076 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1077 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1078 | ; 10 byte for clgr/jg | |
1079 | ||
b0f86a7e AK |
1080 | ; And now the same two patterns as above but with a negated CC mask. |
1081 | ||
1082 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1083 | ; The following instructions do a complementary access of their second | |
1084 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1085 | (define_insn "*icmp_and_br_signed_<mode>" | |
1086 | [(set (pc) | |
1087 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1088 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1089 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1090 | (pc) | |
1091 | (label_ref (match_operand 3 "" "")))) | |
1092 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1093 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1094 | { |
1095 | if (get_attr_length (insn) == 6) | |
1096 | return which_alternative ? | |
1097 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1098 | else | |
1099 | return which_alternative ? | |
1100 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1101 | } | |
1102 | [(set_attr "op_type" "RIE") | |
1103 | (set_attr "type" "branch") | |
1104 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1105 | (set (attr "length") | |
1106 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1107 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1108 | ; 10 byte for cgr/jg | |
1109 | ||
1110 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1111 | ; The following instructions do a complementary access of their second | |
1112 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1113 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1114 | [(set (pc) | |
1115 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1116 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1117 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1118 | (pc) | |
1119 | (label_ref (match_operand 3 "" "")))) | |
1120 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1121 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1122 | { |
1123 | if (get_attr_length (insn) == 6) | |
1124 | return which_alternative ? | |
1125 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1126 | else | |
1127 | return which_alternative ? | |
1128 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1129 | } | |
1130 | [(set_attr "op_type" "RIE") | |
1131 | (set_attr "type" "branch") | |
1132 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1133 | (set (attr "length") | |
1134 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1135 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1136 | ; 10 byte for clgr/jg | |
1137 | ||
9db1d521 HP |
1138 | ;; |
1139 | ;;- Move instructions. | |
1140 | ;; | |
1141 | ||
1142 | ; | |
1143 | ; movti instruction pattern(s). | |
1144 | ; | |
1145 | ||
1146 | (define_insn "movti" | |
f2dc2f86 AK |
1147 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") |
1148 | (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] | |
9602b6a1 | 1149 | "TARGET_ZARCH" |
4023fb28 | 1150 | "@ |
fc0ea003 UW |
1151 | lmg\t%0,%N0,%S1 |
1152 | stmg\t%1,%N1,%S0 | |
4023fb28 | 1153 | # |
19b63d8e | 1154 | #" |
f2dc2f86 AK |
1155 | [(set_attr "op_type" "RSY,RSY,*,*") |
1156 | (set_attr "type" "lm,stm,*,*")]) | |
4023fb28 UW |
1157 | |
1158 | (define_split | |
1159 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1160 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1161 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1162 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1163 | [(set (match_dup 2) (match_dup 4)) |
1164 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1165 | { |
dc65c307 UW |
1166 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1167 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1168 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1169 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1170 | }) | |
1171 | ||
1172 | (define_split | |
1173 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1174 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1175 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1176 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1177 | [(set (match_dup 2) (match_dup 4)) | |
1178 | (set (match_dup 3) (match_dup 5))] | |
1179 | { | |
1180 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1181 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1182 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1183 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1184 | }) | |
4023fb28 UW |
1185 | |
1186 | (define_split | |
1187 | [(set (match_operand:TI 0 "register_operand" "") | |
1188 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1189 | "TARGET_ZARCH && reload_completed |
4023fb28 | 1190 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1191 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1192 | { |
1193 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1194 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1195 | s390_load_address (addr, XEXP (operands[1], 0)); |
1196 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1197 | }) |
1198 | ||
833cd70a AK |
1199 | |
1200 | ; | |
1201 | ; Patterns used for secondary reloads | |
1202 | ; | |
1203 | ||
963fc8d0 AK |
1204 | ; z10 provides move instructions accepting larl memory operands. |
1205 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1206 | ; These patterns are also used for unaligned SI and DI accesses. | |
1207 | ||
1208 | (define_expand "reload<INTALL:mode><P:mode>_tomem_z10" | |
1209 | [(parallel [(match_operand:INTALL 0 "memory_operand" "") | |
1210 | (match_operand:INTALL 1 "register_operand" "=d") | |
1211 | (match_operand:P 2 "register_operand" "=&a")])] | |
1212 | "TARGET_Z10" | |
1213 | { | |
1214 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1215 | DONE; | |
1216 | }) | |
1217 | ||
1218 | (define_expand "reload<INTALL:mode><P:mode>_toreg_z10" | |
1219 | [(parallel [(match_operand:INTALL 0 "register_operand" "=d") | |
1220 | (match_operand:INTALL 1 "memory_operand" "") | |
1221 | (match_operand:P 2 "register_operand" "=a")])] | |
1222 | "TARGET_Z10" | |
1223 | { | |
1224 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1225 | DONE; | |
1226 | }) | |
1227 | ||
1228 | (define_expand "reload<FPALL:mode><P:mode>_tomem_z10" | |
1229 | [(parallel [(match_operand:FPALL 0 "memory_operand" "") | |
1230 | (match_operand:FPALL 1 "register_operand" "=d") | |
1231 | (match_operand:P 2 "register_operand" "=&a")])] | |
1232 | "TARGET_Z10" | |
1233 | { | |
1234 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1235 | DONE; | |
1236 | }) | |
1237 | ||
1238 | (define_expand "reload<FPALL:mode><P:mode>_toreg_z10" | |
1239 | [(parallel [(match_operand:FPALL 0 "register_operand" "=d") | |
1240 | (match_operand:FPALL 1 "memory_operand" "") | |
1241 | (match_operand:P 2 "register_operand" "=a")])] | |
1242 | "TARGET_Z10" | |
1243 | { | |
1244 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1245 | DONE; | |
1246 | }) | |
1247 | ||
1248 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1249 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1250 | (match_operand:P 1 "larl_operand" "") | |
1251 | (match_operand:P 2 "register_operand" "=a")])] | |
1252 | "TARGET_Z10" | |
1253 | { | |
1254 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1255 | DONE; | |
1256 | }) | |
1257 | ||
833cd70a AK |
1258 | ; Handles loading a PLUS (load address) expression |
1259 | ||
1260 | (define_expand "reload<mode>_plus" | |
1261 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1262 | (match_operand:P 1 "s390_plus_operand" "") | |
1263 | (match_operand:P 2 "register_operand" "=&a")])] | |
1264 | "" | |
1265 | { | |
1266 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1267 | DONE; | |
1268 | }) | |
1269 | ||
1270 | ; Handles assessing a non-offsetable memory address | |
1271 | ||
1272 | (define_expand "reload<mode>_nonoffmem_in" | |
1273 | [(parallel [(match_operand 0 "register_operand" "") | |
1274 | (match_operand 1 "" "") | |
1275 | (match_operand:P 2 "register_operand" "=&a")])] | |
1276 | "" | |
1277 | { | |
1278 | gcc_assert (MEM_P (operands[1])); | |
1279 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1280 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1281 | emit_move_insn (operands[0], operands[1]); | |
1282 | DONE; | |
1283 | }) | |
1284 | ||
1285 | (define_expand "reload<mode>_nonoffmem_out" | |
1286 | [(parallel [(match_operand 0 "" "") | |
1287 | (match_operand 1 "register_operand" "") | |
1288 | (match_operand:P 2 "register_operand" "=&a")])] | |
1289 | "" | |
dc65c307 | 1290 | { |
9c3c3dcc | 1291 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1292 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1293 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1294 | emit_move_insn (operands[0], operands[1]); | |
1295 | DONE; | |
1296 | }) | |
9db1d521 | 1297 | |
1f9e1fc6 AK |
1298 | (define_expand "reload<mode>_PIC_addr" |
1299 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1300 | (match_operand 1 "larl_operand" "") | |
1301 | (match_operand:P 2 "register_operand" "=a")])] | |
1302 | "" | |
1303 | { | |
0a2aaacc KG |
1304 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1305 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1306 | }) |
1307 | ||
9db1d521 HP |
1308 | ; |
1309 | ; movdi instruction pattern(s). | |
1310 | ; | |
1311 | ||
9db1d521 HP |
1312 | (define_expand "movdi" |
1313 | [(set (match_operand:DI 0 "general_operand" "") | |
1314 | (match_operand:DI 1 "general_operand" ""))] | |
1315 | "" | |
9db1d521 | 1316 | { |
fd3cd001 | 1317 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1318 | if (TARGET_64BIT |
1319 | && (SYMBOLIC_CONST (operands[1]) | |
1320 | || (GET_CODE (operands[1]) == PLUS | |
1321 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1322 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1323 | emit_symbolic_move (operands); |
10bbf137 | 1324 | }) |
9db1d521 | 1325 | |
4023fb28 UW |
1326 | (define_insn "*movdi_larl" |
1327 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1328 | (match_operand:DI 1 "larl_operand" "X"))] | |
1329 | "TARGET_64BIT | |
8e509cf9 | 1330 | && !FP_REG_P (operands[0])" |
d40c829f | 1331 | "larl\t%0,%1" |
4023fb28 | 1332 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1333 | (set_attr "type" "larl") |
1334 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1335 | |
3af8e996 | 1336 | (define_insn "*movdi_64" |
85dae55a | 1337 | [(set (match_operand:DI 0 "nonimmediate_operand" |
963fc8d0 | 1338 | "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, |
f2dc2f86 | 1339 | RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") |
85dae55a | 1340 | (match_operand:DI 1 "general_operand" |
963fc8d0 | 1341 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, |
f2dc2f86 | 1342 | d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] |
9602b6a1 | 1343 | "TARGET_ZARCH" |
85dae55a AK |
1344 | "@ |
1345 | lghi\t%0,%h1 | |
1346 | llihh\t%0,%i1 | |
1347 | llihl\t%0,%i1 | |
1348 | llilh\t%0,%i1 | |
1349 | llill\t%0,%i1 | |
1350 | lgfi\t%0,%1 | |
1351 | llihf\t%0,%k1 | |
1352 | llilf\t%0,%k1 | |
1353 | ldgr\t%0,%1 | |
1354 | lgdr\t%0,%1 | |
1355 | lay\t%0,%a1 | |
963fc8d0 | 1356 | lgrl\t%0,%1 |
85dae55a AK |
1357 | lgr\t%0,%1 |
1358 | lg\t%0,%1 | |
1359 | stg\t%1,%0 | |
1360 | ldr\t%0,%1 | |
1361 | ld\t%0,%1 | |
1362 | ldy\t%0,%1 | |
1363 | std\t%1,%0 | |
1364 | stdy\t%1,%0 | |
963fc8d0 AK |
1365 | stgrl\t%1,%0 |
1366 | mvghi\t%0,%1 | |
85dae55a AK |
1367 | # |
1368 | # | |
1369 | stam\t%1,%N1,%S0 | |
f2dc2f86 | 1370 | lam\t%0,%N0,%S1" |
963fc8d0 | 1371 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
f2dc2f86 | 1372 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS") |
963fc8d0 AK |
1373 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
1374 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, | |
f2dc2f86 | 1375 | *,*") |
3af8e996 | 1376 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1377 | z10,*,*,*,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1378 | z10,z10,*,*,*,*") |
9381e3f1 WG |
1379 | (set_attr "z10prop" "z10_fwd_A1, |
1380 | z10_fwd_E1, | |
1381 | z10_fwd_E1, | |
1382 | z10_fwd_E1, | |
1383 | z10_fwd_E1, | |
1384 | z10_fwd_A1, | |
1385 | z10_fwd_E1, | |
1386 | z10_fwd_E1, | |
1387 | *, | |
1388 | *, | |
1389 | z10_fwd_A1, | |
1390 | z10_fwd_A3, | |
1391 | z10_fr_E1, | |
1392 | z10_fwd_A3, | |
1393 | z10_rec, | |
1394 | *, | |
1395 | *, | |
1396 | *, | |
1397 | *, | |
1398 | *, | |
1399 | z10_rec, | |
1400 | z10_super, | |
1401 | *, | |
1402 | *, | |
1403 | *, | |
9381e3f1 WG |
1404 | *") |
1405 | ]) | |
c5aa1d12 UW |
1406 | |
1407 | (define_split | |
1408 | [(set (match_operand:DI 0 "register_operand" "") | |
1409 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1410 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1411 | [(set (match_dup 2) (match_dup 3)) |
1412 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1413 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1414 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1415 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1416 | ||
1417 | (define_split | |
1418 | [(set (match_operand:DI 0 "register_operand" "") | |
1419 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1420 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1421 | && dead_or_set_p (insn, operands[1])" |
1422 | [(set (match_dup 3) (match_dup 2)) | |
1423 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1424 | (set (match_dup 4) (match_dup 2))] | |
1425 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1426 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1427 | ||
1428 | (define_split | |
1429 | [(set (match_operand:DI 0 "register_operand" "") | |
1430 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1431 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1432 | && !dead_or_set_p (insn, operands[1])" |
1433 | [(set (match_dup 3) (match_dup 2)) | |
1434 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1435 | (set (match_dup 4) (match_dup 2)) | |
1436 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1437 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1438 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1439 | |
1440 | (define_insn "*movdi_31" | |
963fc8d0 | 1441 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1442 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1443 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1444 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1445 | "!TARGET_ZARCH" |
4023fb28 | 1446 | "@ |
fc0ea003 | 1447 | lm\t%0,%N0,%S1 |
c4d50129 | 1448 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1449 | stm\t%1,%N1,%S0 |
c4d50129 | 1450 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1451 | # |
1452 | # | |
d40c829f UW |
1453 | ldr\t%0,%1 |
1454 | ld\t%0,%1 | |
1455 | ldy\t%0,%1 | |
1456 | std\t%1,%0 | |
1457 | stdy\t%1,%0 | |
19b63d8e | 1458 | #" |
f2dc2f86 AK |
1459 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1460 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1461 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1462 | |
1463 | ; For a load from a symbol ref we can use one of the target registers | |
1464 | ; together with larl to load the address. | |
1465 | (define_split | |
1466 | [(set (match_operand:DI 0 "register_operand" "") | |
1467 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1468 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1469 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1470 | [(set (match_dup 2) (match_dup 3)) | |
1471 | (set (match_dup 0) (match_dup 1))] | |
1472 | { | |
1473 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1474 | operands[3] = XEXP (operands[1], 0); | |
1475 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1476 | }) | |
4023fb28 UW |
1477 | |
1478 | (define_split | |
1479 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1480 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1481 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1482 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1483 | [(set (match_dup 2) (match_dup 4)) |
1484 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1485 | { |
dc65c307 UW |
1486 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1487 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1488 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1489 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1490 | }) | |
1491 | ||
1492 | (define_split | |
1493 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1494 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1495 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1496 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1497 | [(set (match_dup 2) (match_dup 4)) | |
1498 | (set (match_dup 3) (match_dup 5))] | |
1499 | { | |
1500 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1501 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1502 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1503 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1504 | }) | |
9db1d521 | 1505 | |
4023fb28 UW |
1506 | (define_split |
1507 | [(set (match_operand:DI 0 "register_operand" "") | |
1508 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1509 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1510 | && !FP_REG_P (operands[0]) |
4023fb28 | 1511 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1512 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1513 | { |
1514 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1515 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1516 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1517 | }) |
1518 | ||
84817c5d UW |
1519 | (define_peephole2 |
1520 | [(set (match_operand:DI 0 "register_operand" "") | |
1521 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1522 | "TARGET_ZARCH |
84817c5d UW |
1523 | && !FP_REG_P (operands[0]) |
1524 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1525 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1526 | && get_pool_mode (operands[1]) == DImode | |
1527 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1528 | [(set (match_dup 0) (match_dup 2))] | |
1529 | "operands[2] = get_pool_constant (operands[1]);") | |
1530 | ||
7bdff56f UW |
1531 | (define_insn "*la_64" |
1532 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1533 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1534 | "TARGET_64BIT" |
1535 | "@ | |
1536 | la\t%0,%a1 | |
1537 | lay\t%0,%a1" | |
1538 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1539 | (set_attr "type" "la") |
1540 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1541 | |
1542 | (define_peephole2 | |
1543 | [(parallel | |
1544 | [(set (match_operand:DI 0 "register_operand" "") | |
1545 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1546 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1547 | "TARGET_64BIT |
e1d5ee28 | 1548 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1549 | [(set (match_dup 0) (match_dup 1))] |
1550 | "") | |
1551 | ||
1552 | (define_peephole2 | |
1553 | [(set (match_operand:DI 0 "register_operand" "") | |
1554 | (match_operand:DI 1 "register_operand" "")) | |
1555 | (parallel | |
1556 | [(set (match_dup 0) | |
1557 | (plus:DI (match_dup 0) | |
1558 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1559 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1560 | "TARGET_64BIT |
1561 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1562 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1563 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1564 | "") | |
1565 | ||
9db1d521 HP |
1566 | ; |
1567 | ; movsi instruction pattern(s). | |
1568 | ; | |
1569 | ||
9db1d521 HP |
1570 | (define_expand "movsi" |
1571 | [(set (match_operand:SI 0 "general_operand" "") | |
1572 | (match_operand:SI 1 "general_operand" ""))] | |
1573 | "" | |
9db1d521 | 1574 | { |
fd3cd001 | 1575 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1576 | if (!TARGET_64BIT |
1577 | && (SYMBOLIC_CONST (operands[1]) | |
1578 | || (GET_CODE (operands[1]) == PLUS | |
1579 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1580 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1581 | emit_symbolic_move (operands); |
10bbf137 | 1582 | }) |
9db1d521 | 1583 | |
9e8327e3 UW |
1584 | (define_insn "*movsi_larl" |
1585 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1586 | (match_operand:SI 1 "larl_operand" "X"))] | |
1587 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1588 | && !FP_REG_P (operands[0])" | |
1589 | "larl\t%0,%1" | |
1590 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1591 | (set_attr "type" "larl") |
729e750f | 1592 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1593 | |
f19a9af7 | 1594 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1595 | [(set (match_operand:SI 0 "nonimmediate_operand" |
f2dc2f86 | 1596 | "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t") |
2f7e5a0d | 1597 | (match_operand:SI 1 "general_operand" |
f2dc2f86 | 1598 | "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))] |
f19a9af7 | 1599 | "TARGET_ZARCH" |
9db1d521 | 1600 | "@ |
f19a9af7 AK |
1601 | lhi\t%0,%h1 |
1602 | llilh\t%0,%i1 | |
1603 | llill\t%0,%i1 | |
ec24698e | 1604 | iilf\t%0,%o1 |
f19a9af7 | 1605 | lay\t%0,%a1 |
963fc8d0 | 1606 | lrl\t%0,%1 |
d40c829f UW |
1607 | lr\t%0,%1 |
1608 | l\t%0,%1 | |
1609 | ly\t%0,%1 | |
1610 | st\t%1,%0 | |
1611 | sty\t%1,%0 | |
1612 | ler\t%0,%1 | |
1613 | le\t%0,%1 | |
1614 | ley\t%0,%1 | |
1615 | ste\t%1,%0 | |
1616 | stey\t%1,%0 | |
c5aa1d12 UW |
1617 | ear\t%0,%1 |
1618 | sar\t%0,%1 | |
1619 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1620 | strl\t%1,%0 |
1621 | mvhi\t%0,%1 | |
f2dc2f86 | 1622 | lam\t%0,%0,%S1" |
963fc8d0 | 1623 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
f2dc2f86 | 1624 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS") |
9381e3f1 WG |
1625 | (set_attr "type" "*, |
1626 | *, | |
1627 | *, | |
1628 | *, | |
1629 | la, | |
1630 | larl, | |
1631 | lr, | |
1632 | load, | |
1633 | load, | |
1634 | store, | |
1635 | store, | |
1636 | floadsf, | |
1637 | floadsf, | |
1638 | floadsf, | |
1639 | fstoresf, | |
1640 | fstoresf, | |
1641 | *, | |
1642 | *, | |
1643 | *, | |
1644 | larl, | |
1645 | *, | |
9381e3f1 | 1646 | *") |
963fc8d0 | 1647 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1648 | *,*,longdisp,*,longdisp,*,*,*,z10,z10,*") |
9381e3f1 WG |
1649 | (set_attr "z10prop" "z10_fwd_A1, |
1650 | z10_fwd_E1, | |
1651 | z10_fwd_E1, | |
1652 | z10_fwd_A1, | |
1653 | z10_fwd_A1, | |
1654 | z10_fwd_A3, | |
1655 | z10_fr_E1, | |
1656 | z10_fwd_A3, | |
1657 | z10_fwd_A3, | |
729e750f | 1658 | z10_rec, |
9381e3f1 WG |
1659 | z10_rec, |
1660 | *, | |
1661 | *, | |
1662 | *, | |
1663 | *, | |
1664 | *, | |
1665 | z10_super_E1, | |
1666 | z10_super, | |
1667 | *, | |
1668 | z10_rec, | |
1669 | z10_super, | |
9381e3f1 | 1670 | *")]) |
f19a9af7 AK |
1671 | |
1672 | (define_insn "*movsi_esa" | |
f2dc2f86 AK |
1673 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t") |
1674 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1675 | "!TARGET_ZARCH" |
1676 | "@ | |
1677 | lhi\t%0,%h1 | |
1678 | lr\t%0,%1 | |
1679 | l\t%0,%1 | |
1680 | st\t%1,%0 | |
1681 | ler\t%0,%1 | |
1682 | le\t%0,%1 | |
1683 | ste\t%1,%0 | |
c5aa1d12 UW |
1684 | ear\t%0,%1 |
1685 | sar\t%0,%1 | |
1686 | stam\t%1,%1,%S0 | |
f2dc2f86 AK |
1687 | lam\t%0,%0,%S1" |
1688 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS") | |
1689 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*") | |
9381e3f1 WG |
1690 | (set_attr "z10prop" "z10_fwd_A1, |
1691 | z10_fr_E1, | |
1692 | z10_fwd_A3, | |
729e750f | 1693 | z10_rec, |
9381e3f1 WG |
1694 | *, |
1695 | *, | |
1696 | *, | |
1697 | z10_super_E1, | |
1698 | z10_super, | |
1699 | *, | |
9381e3f1 WG |
1700 | *") |
1701 | ]) | |
9db1d521 | 1702 | |
84817c5d UW |
1703 | (define_peephole2 |
1704 | [(set (match_operand:SI 0 "register_operand" "") | |
1705 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1706 | "!FP_REG_P (operands[0]) | |
1707 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1708 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1709 | && get_pool_mode (operands[1]) == SImode | |
1710 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1711 | [(set (match_dup 0) (match_dup 2))] | |
1712 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1713 | |
7bdff56f UW |
1714 | (define_insn "*la_31" |
1715 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1716 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1717 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1718 | "@ | |
1719 | la\t%0,%a1 | |
1720 | lay\t%0,%a1" | |
1721 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1722 | (set_attr "type" "la") |
1723 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1724 | |
1725 | (define_peephole2 | |
1726 | [(parallel | |
1727 | [(set (match_operand:SI 0 "register_operand" "") | |
1728 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1729 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1730 | "!TARGET_64BIT |
e1d5ee28 | 1731 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1732 | [(set (match_dup 0) (match_dup 1))] |
1733 | "") | |
1734 | ||
1735 | (define_peephole2 | |
1736 | [(set (match_operand:SI 0 "register_operand" "") | |
1737 | (match_operand:SI 1 "register_operand" "")) | |
1738 | (parallel | |
1739 | [(set (match_dup 0) | |
1740 | (plus:SI (match_dup 0) | |
1741 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1742 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1743 | "!TARGET_64BIT |
1744 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1745 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1746 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1747 | "") | |
1748 | ||
1749 | (define_insn "*la_31_and" | |
1750 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1751 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
1752 | (const_int 2147483647)))] |
1753 | "!TARGET_64BIT" | |
1754 | "@ | |
1755 | la\t%0,%a1 | |
1756 | lay\t%0,%a1" | |
1757 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1758 | (set_attr "type" "la") |
1759 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1760 | |
1761 | (define_insn_and_split "*la_31_and_cc" | |
1762 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1763 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1764 | (const_int 2147483647))) | |
ae156f85 | 1765 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1766 | "!TARGET_64BIT" |
1767 | "#" | |
1768 | "&& reload_completed" | |
1769 | [(set (match_dup 0) | |
1770 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1771 | "" | |
1772 | [(set_attr "op_type" "RX") | |
1773 | (set_attr "type" "la")]) | |
1774 | ||
1775 | (define_insn "force_la_31" | |
1776 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1777 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
1778 | (use (const_int 0))] |
1779 | "!TARGET_64BIT" | |
1780 | "@ | |
1781 | la\t%0,%a1 | |
1782 | lay\t%0,%a1" | |
1783 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
1784 | (set_attr "type" "la") |
1785 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 1786 | |
9db1d521 HP |
1787 | ; |
1788 | ; movhi instruction pattern(s). | |
1789 | ; | |
1790 | ||
02ed3c5e UW |
1791 | (define_expand "movhi" |
1792 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1793 | (match_operand:HI 1 "general_operand" ""))] | |
1794 | "" | |
1795 | { | |
2f7e5a0d | 1796 | /* Make it explicit that loading a register from memory |
02ed3c5e | 1797 | always sign-extends (at least) to SImode. */ |
b3a13419 | 1798 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 1799 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1800 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1801 | { |
1802 | rtx tmp = gen_reg_rtx (SImode); | |
1803 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1804 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1805 | operands[1] = gen_lowpart (HImode, tmp); | |
1806 | } | |
1807 | }) | |
1808 | ||
1809 | (define_insn "*movhi" | |
f2dc2f86 AK |
1810 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q") |
1811 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))] | |
9db1d521 HP |
1812 | "" |
1813 | "@ | |
d40c829f UW |
1814 | lr\t%0,%1 |
1815 | lhi\t%0,%h1 | |
1816 | lh\t%0,%1 | |
1817 | lhy\t%0,%1 | |
963fc8d0 | 1818 | lhrl\t%0,%1 |
d40c829f UW |
1819 | sth\t%1,%0 |
1820 | sthy\t%1,%0 | |
963fc8d0 | 1821 | sthrl\t%1,%0 |
f2dc2f86 AK |
1822 | mvhhi\t%0,%1" |
1823 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL") | |
1824 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*") | |
1825 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10") | |
9381e3f1 WG |
1826 | (set_attr "z10prop" "z10_fr_E1, |
1827 | z10_fwd_A1, | |
1828 | z10_super_E1, | |
1829 | z10_super_E1, | |
1830 | z10_super_E1, | |
729e750f | 1831 | z10_rec, |
9381e3f1 WG |
1832 | z10_rec, |
1833 | z10_rec, | |
f2dc2f86 | 1834 | z10_super")]) |
9db1d521 | 1835 | |
84817c5d UW |
1836 | (define_peephole2 |
1837 | [(set (match_operand:HI 0 "register_operand" "") | |
1838 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1839 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1840 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1841 | && get_pool_mode (operands[1]) == HImode | |
1842 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1843 | [(set (match_dup 0) (match_dup 2))] | |
1844 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1845 | |
9db1d521 HP |
1846 | ; |
1847 | ; movqi instruction pattern(s). | |
1848 | ; | |
1849 | ||
02ed3c5e UW |
1850 | (define_expand "movqi" |
1851 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1852 | (match_operand:QI 1 "general_operand" ""))] | |
1853 | "" | |
1854 | { | |
c19ec8f9 | 1855 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1856 | is just as fast as a QImode load. */ |
b3a13419 | 1857 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 1858 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1859 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1860 | { |
9602b6a1 AK |
1861 | rtx tmp = gen_reg_rtx (DImode); |
1862 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
02ed3c5e UW |
1863 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1864 | operands[1] = gen_lowpart (QImode, tmp); | |
1865 | } | |
1866 | }) | |
4023fb28 | 1867 | |
02ed3c5e | 1868 | (define_insn "*movqi" |
0a88561f AK |
1869 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1870 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1871 | "" |
1872 | "@ | |
d40c829f UW |
1873 | lr\t%0,%1 |
1874 | lhi\t%0,%b1 | |
1875 | ic\t%0,%1 | |
1876 | icy\t%0,%1 | |
1877 | stc\t%1,%0 | |
1878 | stcy\t%1,%0 | |
fc0ea003 | 1879 | mvi\t%S0,%b1 |
0a88561f | 1880 | mviy\t%S0,%b1 |
b247e88a | 1881 | #" |
0a88561f AK |
1882 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1883 | (set_attr "type" "lr,*,*,*,store,store,store,store,*") | |
9381e3f1 WG |
1884 | (set_attr "z10prop" "z10_fr_E1, |
1885 | z10_fwd_A1, | |
1886 | z10_super_E1, | |
1887 | z10_super_E1, | |
729e750f | 1888 | z10_rec, |
9381e3f1 WG |
1889 | z10_rec, |
1890 | z10_super, | |
0a88561f AK |
1891 | z10_super, |
1892 | *")]) | |
9db1d521 | 1893 | |
84817c5d UW |
1894 | (define_peephole2 |
1895 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1896 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1897 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1898 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1899 | && get_pool_mode (operands[1]) == QImode | |
1900 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1901 | [(set (match_dup 0) (match_dup 2))] | |
1902 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1903 | |
9db1d521 | 1904 | ; |
05b9aaaa | 1905 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1906 | ; |
1907 | ||
1908 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1909 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1910 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1911 | "" |
d3632d41 | 1912 | "@ |
d40c829f UW |
1913 | ic\t%0,%1 |
1914 | icy\t%0,%1" | |
9381e3f1 | 1915 | [(set_attr "op_type" "RX,RXY") |
729e750f | 1916 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
1917 | |
1918 | ; | |
1919 | ; movstricthi instruction pattern(s). | |
1920 | ; | |
1921 | ||
1922 | (define_insn "*movstricthi" | |
d3632d41 | 1923 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1924 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1925 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1926 | "" |
d3632d41 | 1927 | "@ |
fc0ea003 UW |
1928 | icm\t%0,3,%S1 |
1929 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
1930 | [(set_attr "op_type" "RS,RSY") |
1931 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
1932 | |
1933 | ; | |
1934 | ; movstrictsi instruction pattern(s). | |
1935 | ; | |
1936 | ||
05b9aaaa | 1937 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1938 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1939 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 1940 | "TARGET_ZARCH" |
9db1d521 | 1941 | "@ |
d40c829f UW |
1942 | lr\t%0,%1 |
1943 | l\t%0,%1 | |
c5aa1d12 UW |
1944 | ly\t%0,%1 |
1945 | ear\t%0,%1" | |
1946 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
1947 | (set_attr "type" "lr,load,load,*") |
1948 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 1949 | |
f61a2c7d | 1950 | ; |
609e7e80 | 1951 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
1952 | ; |
1953 | ||
609e7e80 AK |
1954 | (define_expand "mov<mode>" |
1955 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
1956 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
1957 | "" |
1958 | "") | |
1959 | ||
609e7e80 | 1960 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
1961 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
1962 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 1963 | "TARGET_ZARCH" |
f61a2c7d | 1964 | "@ |
65b1d8ea | 1965 | lzxr\t%0 |
f61a2c7d AK |
1966 | lxr\t%0,%1 |
1967 | # | |
1968 | # | |
1969 | lmg\t%0,%N0,%S1 | |
1970 | stmg\t%1,%N1,%S0 | |
1971 | # | |
f61a2c7d | 1972 | #" |
65b1d8ea AK |
1973 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
1974 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
1975 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 1976 | |
609e7e80 | 1977 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
1978 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
1979 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 1980 | "!TARGET_ZARCH" |
f61a2c7d | 1981 | "@ |
65b1d8ea | 1982 | lzxr\t%0 |
f61a2c7d AK |
1983 | lxr\t%0,%1 |
1984 | # | |
f61a2c7d | 1985 | #" |
65b1d8ea AK |
1986 | [(set_attr "op_type" "RRE,RRE,*,*") |
1987 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
1988 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
1989 | |
1990 | ; TFmode in GPRs splitters | |
1991 | ||
1992 | (define_split | |
609e7e80 AK |
1993 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
1994 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 1995 | "TARGET_ZARCH && reload_completed |
609e7e80 | 1996 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
1997 | [(set (match_dup 2) (match_dup 4)) |
1998 | (set (match_dup 3) (match_dup 5))] | |
1999 | { | |
609e7e80 AK |
2000 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2001 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2002 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2003 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2004 | }) |
2005 | ||
2006 | (define_split | |
609e7e80 AK |
2007 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2008 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2009 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2010 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2011 | [(set (match_dup 2) (match_dup 4)) |
2012 | (set (match_dup 3) (match_dup 5))] | |
2013 | { | |
609e7e80 AK |
2014 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2015 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2016 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2017 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2018 | }) |
2019 | ||
2020 | (define_split | |
609e7e80 AK |
2021 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2022 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2023 | "TARGET_ZARCH && reload_completed |
f61a2c7d AK |
2024 | && !FP_REG_P (operands[0]) |
2025 | && !s_operand (operands[1], VOIDmode)" | |
2026 | [(set (match_dup 0) (match_dup 1))] | |
2027 | { | |
609e7e80 | 2028 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
f61a2c7d AK |
2029 | s390_load_address (addr, XEXP (operands[1], 0)); |
2030 | operands[1] = replace_equiv_address (operands[1], addr); | |
2031 | }) | |
2032 | ||
7b6baae1 | 2033 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2034 | |
2035 | (define_split | |
609e7e80 AK |
2036 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2037 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2038 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2039 | && FP_REG_P (operands[0])" |
2040 | [(set (match_dup 2) (match_dup 4)) | |
2041 | (set (match_dup 3) (match_dup 5))] | |
2042 | { | |
609e7e80 AK |
2043 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2044 | <MODE>mode, 0); | |
2045 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2046 | <MODE>mode, 8); | |
2047 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2048 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2049 | }) |
2050 | ||
2051 | (define_split | |
609e7e80 AK |
2052 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2053 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2054 | "reload_completed && offsettable_memref_p (operands[0]) |
2055 | && FP_REG_P (operands[1])" | |
2056 | [(set (match_dup 2) (match_dup 4)) | |
2057 | (set (match_dup 3) (match_dup 5))] | |
2058 | { | |
609e7e80 AK |
2059 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2060 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2061 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2062 | <MODE>mode, 0); | |
2063 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2064 | <MODE>mode, 8); | |
f61a2c7d AK |
2065 | }) |
2066 | ||
9db1d521 | 2067 | ; |
609e7e80 | 2068 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2069 | ; |
2070 | ||
609e7e80 AK |
2071 | (define_expand "mov<mode>" |
2072 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2073 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2074 | "" |
13c025c1 | 2075 | "") |
9db1d521 | 2076 | |
609e7e80 AK |
2077 | (define_insn "*mov<mode>_64dfp" |
2078 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2079 | "=f,f,f,d,f,f,R,T,d,d, d,RT") |
609e7e80 | 2080 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2081 | " G,f,d,f,R,T,f,f,G,d,RT, d"))] |
9602b6a1 | 2082 | "TARGET_DFP" |
85dae55a | 2083 | "@ |
65b1d8ea | 2084 | lzdr\t%0 |
85dae55a AK |
2085 | ldr\t%0,%1 |
2086 | ldgr\t%0,%1 | |
2087 | lgdr\t%0,%1 | |
2088 | ld\t%0,%1 | |
2089 | ldy\t%0,%1 | |
2090 | std\t%1,%0 | |
2091 | stdy\t%1,%0 | |
45e5214c | 2092 | lghi\t%0,0 |
85dae55a AK |
2093 | lgr\t%0,%1 |
2094 | lg\t%0,%1 | |
f2dc2f86 | 2095 | stg\t%1,%0" |
65b1d8ea AK |
2096 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2097 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, | |
45e5214c | 2098 | fstoredf,fstoredf,*,lr,load,store") |
65b1d8ea AK |
2099 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") |
2100 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
85dae55a | 2101 | |
609e7e80 | 2102 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2103 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT") |
2104 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))] | |
9602b6a1 | 2105 | "TARGET_ZARCH" |
9db1d521 | 2106 | "@ |
65b1d8ea | 2107 | lzdr\t%0 |
d40c829f UW |
2108 | ldr\t%0,%1 |
2109 | ld\t%0,%1 | |
2110 | ldy\t%0,%1 | |
2111 | std\t%1,%0 | |
2112 | stdy\t%1,%0 | |
45e5214c | 2113 | lghi\t%0,0 |
d40c829f UW |
2114 | lgr\t%0,%1 |
2115 | lg\t%0,%1 | |
f2dc2f86 | 2116 | stg\t%1,%0" |
65b1d8ea AK |
2117 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2118 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2119 | fstore<mode>,fstore<mode>,*,lr,load,store") | |
2120 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") | |
2121 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")]) | |
609e7e80 AK |
2122 | |
2123 | (define_insn "*mov<mode>_31" | |
2124 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2125 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2126 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2127 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2128 | "!TARGET_ZARCH" |
9db1d521 | 2129 | "@ |
65b1d8ea | 2130 | lzdr\t%0 |
d40c829f UW |
2131 | ldr\t%0,%1 |
2132 | ld\t%0,%1 | |
2133 | ldy\t%0,%1 | |
2134 | std\t%1,%0 | |
2135 | stdy\t%1,%0 | |
fc0ea003 | 2136 | lm\t%0,%N0,%S1 |
c4d50129 | 2137 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2138 | stm\t%1,%N1,%S0 |
c4d50129 | 2139 | stmy\t%1,%N1,%S0 |
4023fb28 | 2140 | # |
19b63d8e | 2141 | #" |
65b1d8ea AK |
2142 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2143 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2144 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2145 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2146 | |
2147 | (define_split | |
609e7e80 AK |
2148 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2149 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2150 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2151 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2152 | [(set (match_dup 2) (match_dup 4)) |
2153 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2154 | { |
609e7e80 AK |
2155 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2156 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2157 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2158 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2159 | }) |
2160 | ||
2161 | (define_split | |
609e7e80 AK |
2162 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2163 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2164 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2165 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2166 | [(set (match_dup 2) (match_dup 4)) |
2167 | (set (match_dup 3) (match_dup 5))] | |
2168 | { | |
609e7e80 AK |
2169 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2170 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2171 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2172 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2173 | }) |
9db1d521 | 2174 | |
4023fb28 | 2175 | (define_split |
609e7e80 AK |
2176 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2177 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2178 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2179 | && !FP_REG_P (operands[0]) |
4023fb28 | 2180 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2181 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2182 | { |
609e7e80 | 2183 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2184 | s390_load_address (addr, XEXP (operands[1], 0)); |
2185 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2186 | }) |
2187 | ||
9db1d521 | 2188 | ; |
609e7e80 | 2189 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2190 | ; |
2191 | ||
609e7e80 AK |
2192 | (define_insn "mov<mode>" |
2193 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
65b1d8ea | 2194 | "=f,f,f,f,R,T,d,d,d,d,R,T") |
609e7e80 | 2195 | (match_operand:SD_SF 1 "general_operand" |
65b1d8ea | 2196 | " G,f,R,T,f,f,G,d,R,T,d,d"))] |
4023fb28 | 2197 | "" |
9db1d521 | 2198 | "@ |
65b1d8ea | 2199 | lzer\t%0 |
d40c829f UW |
2200 | ler\t%0,%1 |
2201 | le\t%0,%1 | |
2202 | ley\t%0,%1 | |
2203 | ste\t%1,%0 | |
2204 | stey\t%1,%0 | |
45e5214c | 2205 | lhi\t%0,0 |
d40c829f UW |
2206 | lr\t%0,%1 |
2207 | l\t%0,%1 | |
2208 | ly\t%0,%1 | |
2209 | st\t%1,%0 | |
f2dc2f86 | 2210 | sty\t%1,%0" |
65b1d8ea AK |
2211 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY") |
2212 | (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>, | |
2213 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") | |
2214 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2215 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2216 | |
9dc62c00 AK |
2217 | ; |
2218 | ; movcc instruction pattern | |
2219 | ; | |
2220 | ||
2221 | (define_insn "movcc" | |
2222 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
2223 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
2224 | "" | |
2225 | "@ | |
2226 | lr\t%0,%1 | |
2227 | tmh\t%1,12288 | |
2228 | ipm\t%0 | |
2229 | st\t%0,%1 | |
2230 | sty\t%0,%1 | |
2231 | l\t%1,%0 | |
2232 | ly\t%1,%0" | |
8dd3b235 | 2233 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
9381e3f1 | 2234 | (set_attr "type" "lr,*,*,store,store,load,load") |
65b1d8ea AK |
2235 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3") |
2236 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) | |
9dc62c00 | 2237 | |
19b63d8e UW |
2238 | ; |
2239 | ; Block move (MVC) patterns. | |
2240 | ; | |
2241 | ||
2242 | (define_insn "*mvc" | |
2243 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2244 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2245 | (use (match_operand 2 "const_int_operand" "n"))] | |
2246 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2247 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2248 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2249 | |
0a88561f AK |
2250 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2251 | ; order to have it implemented with mvc. | |
2252 | ||
2253 | (define_split | |
2254 | [(set (match_operand:QI 0 "memory_operand" "") | |
2255 | (match_operand:QI 1 "memory_operand" ""))] | |
2256 | "reload_completed" | |
2257 | [(parallel | |
2258 | [(set (match_dup 0) (match_dup 1)) | |
2259 | (use (const_int 1))])] | |
2260 | { | |
2261 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2262 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2263 | }) | |
2264 | ||
2265 | ||
19b63d8e UW |
2266 | (define_peephole2 |
2267 | [(parallel | |
2268 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2269 | (match_operand:BLK 1 "memory_operand" "")) | |
2270 | (use (match_operand 2 "const_int_operand" ""))]) | |
2271 | (parallel | |
2272 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2273 | (match_operand:BLK 4 "memory_operand" "")) | |
2274 | (use (match_operand 5 "const_int_operand" ""))])] | |
2275 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2276 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2277 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2278 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2279 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2280 | [(parallel | |
2281 | [(set (match_dup 6) (match_dup 7)) | |
2282 | (use (match_dup 8))])] | |
2283 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2284 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2285 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2286 | ||
2287 | ||
9db1d521 HP |
2288 | ; |
2289 | ; load_multiple pattern(s). | |
2290 | ; | |
22ea6b4f UW |
2291 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2292 | ; we currently support load_multiple/store_multiple only after reload. | |
2293 | ; | |
9db1d521 HP |
2294 | |
2295 | (define_expand "load_multiple" | |
2296 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2297 | (match_operand 1 "" "")) | |
2298 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2299 | "reload_completed" |
9db1d521 | 2300 | { |
c19ec8f9 | 2301 | enum machine_mode mode; |
9db1d521 HP |
2302 | int regno; |
2303 | int count; | |
2304 | rtx from; | |
4023fb28 | 2305 | int i, off; |
9db1d521 HP |
2306 | |
2307 | /* Support only loading a constant number of fixed-point registers from | |
2308 | memory and only bother with this if more than two */ | |
2309 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2310 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2311 | || INTVAL (operands[2]) > 16 |
2312 | || GET_CODE (operands[1]) != MEM | |
2313 | || GET_CODE (operands[0]) != REG | |
2314 | || REGNO (operands[0]) >= 16) | |
2315 | FAIL; | |
2316 | ||
2317 | count = INTVAL (operands[2]); | |
2318 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2319 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2320 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2321 | FAIL; |
9db1d521 HP |
2322 | |
2323 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2324 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2325 | { |
2326 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2327 | { | |
2328 | from = XEXP (operands[1], 0); | |
2329 | off = 0; | |
2330 | } | |
2331 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2332 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2333 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2334 | { | |
2335 | from = XEXP (XEXP (operands[1], 0), 0); | |
2336 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2337 | } | |
2338 | else | |
2339 | FAIL; | |
4023fb28 UW |
2340 | } |
2341 | else | |
2342 | { | |
2343 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2344 | off = 0; | |
2345 | } | |
9db1d521 HP |
2346 | |
2347 | for (i = 0; i < count; i++) | |
2348 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
2349 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
2350 | change_address (operands[1], mode, | |
2351 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2352 | }) |
9db1d521 HP |
2353 | |
2354 | (define_insn "*load_multiple_di" | |
2355 | [(match_parallel 0 "load_multiple_operation" | |
2356 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2357 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2358 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2359 | { |
2360 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2361 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2362 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2363 | } |
d3632d41 | 2364 | [(set_attr "op_type" "RSY") |
4023fb28 | 2365 | (set_attr "type" "lm")]) |
9db1d521 HP |
2366 | |
2367 | (define_insn "*load_multiple_si" | |
2368 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2369 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2370 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2371 | "reload_completed" |
9db1d521 HP |
2372 | { |
2373 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2374 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2375 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2376 | } |
d3632d41 | 2377 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2378 | (set_attr "type" "lm")]) |
9db1d521 HP |
2379 | |
2380 | ; | |
c7453384 | 2381 | ; store multiple pattern(s). |
9db1d521 HP |
2382 | ; |
2383 | ||
2384 | (define_expand "store_multiple" | |
2385 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2386 | (match_operand 1 "" "")) | |
2387 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2388 | "reload_completed" |
9db1d521 | 2389 | { |
c19ec8f9 | 2390 | enum machine_mode mode; |
9db1d521 HP |
2391 | int regno; |
2392 | int count; | |
2393 | rtx to; | |
4023fb28 | 2394 | int i, off; |
9db1d521 HP |
2395 | |
2396 | /* Support only storing a constant number of fixed-point registers to | |
2397 | memory and only bother with this if more than two. */ | |
2398 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2399 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2400 | || INTVAL (operands[2]) > 16 |
2401 | || GET_CODE (operands[0]) != MEM | |
2402 | || GET_CODE (operands[1]) != REG | |
2403 | || REGNO (operands[1]) >= 16) | |
2404 | FAIL; | |
2405 | ||
2406 | count = INTVAL (operands[2]); | |
2407 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2408 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2409 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2410 | FAIL; |
9db1d521 HP |
2411 | |
2412 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2413 | |
b3a13419 | 2414 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2415 | { |
2416 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2417 | { | |
2418 | to = XEXP (operands[0], 0); | |
2419 | off = 0; | |
2420 | } | |
2421 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2422 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2423 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2424 | { | |
2425 | to = XEXP (XEXP (operands[0], 0), 0); | |
2426 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2427 | } | |
2428 | else | |
2429 | FAIL; | |
4023fb28 | 2430 | } |
c7453384 | 2431 | else |
4023fb28 UW |
2432 | { |
2433 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2434 | off = 0; | |
2435 | } | |
9db1d521 HP |
2436 | |
2437 | for (i = 0; i < count; i++) | |
2438 | XVECEXP (operands[3], 0, i) | |
2439 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
2440 | change_address (operands[0], mode, |
2441 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
2442 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 2443 | }) |
9db1d521 HP |
2444 | |
2445 | (define_insn "*store_multiple_di" | |
2446 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2447 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2448 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2449 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2450 | { |
2451 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2452 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2453 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2454 | } |
d3632d41 | 2455 | [(set_attr "op_type" "RSY") |
4023fb28 | 2456 | (set_attr "type" "stm")]) |
9db1d521 HP |
2457 | |
2458 | ||
2459 | (define_insn "*store_multiple_si" | |
2460 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2461 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2462 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2463 | "reload_completed" |
9db1d521 HP |
2464 | { |
2465 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2466 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2467 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2468 | } |
d3632d41 | 2469 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2470 | (set_attr "type" "stm")]) |
9db1d521 HP |
2471 | |
2472 | ;; | |
2473 | ;; String instructions. | |
2474 | ;; | |
2475 | ||
963fc8d0 AK |
2476 | (define_insn "*execute_rl" |
2477 | [(match_parallel 0 "" | |
2478 | [(unspec [(match_operand 1 "register_operand" "a") | |
2479 | (match_operand 2 "" "") | |
2480 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2481 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2482 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2483 | "exrl\t%1,%3" | |
2484 | [(set_attr "op_type" "RIL") | |
2485 | (set_attr "type" "cs")]) | |
2486 | ||
9bb86f41 UW |
2487 | (define_insn "*execute" |
2488 | [(match_parallel 0 "" | |
2489 | [(unspec [(match_operand 1 "register_operand" "a") | |
2490 | (match_operand:BLK 2 "memory_operand" "R") | |
2491 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2492 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2493 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2494 | "ex\t%1,%2" | |
29a74354 UW |
2495 | [(set_attr "op_type" "RX") |
2496 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2497 | |
2498 | ||
91d39d71 UW |
2499 | ; |
2500 | ; strlenM instruction pattern(s). | |
2501 | ; | |
2502 | ||
9db2f16d | 2503 | (define_expand "strlen<mode>" |
ccbdc0d4 | 2504 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2505 | (parallel |
91d39d71 | 2506 | [(set (match_dup 4) |
9db2f16d | 2507 | (unspec:P [(const_int 0) |
91d39d71 | 2508 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2509 | (reg:SI 0) |
91d39d71 | 2510 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2511 | (clobber (scratch:P)) |
ae156f85 | 2512 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2513 | (parallel |
9db2f16d AS |
2514 | [(set (match_operand:P 0 "register_operand" "") |
2515 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2516 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2517 | "" |
91d39d71 | 2518 | { |
9db2f16d AS |
2519 | operands[4] = gen_reg_rtx (Pmode); |
2520 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2521 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2522 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2523 | }) | |
2524 | ||
9db2f16d AS |
2525 | (define_insn "*strlen<mode>" |
2526 | [(set (match_operand:P 0 "register_operand" "=a") | |
2527 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2528 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2529 | (reg:SI 0) |
91d39d71 | 2530 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2531 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2532 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2533 | "" |
91d39d71 | 2534 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2535 | [(set_attr "length" "8") |
2536 | (set_attr "type" "vs")]) | |
91d39d71 | 2537 | |
ccbdc0d4 AS |
2538 | ; |
2539 | ; cmpstrM instruction pattern(s). | |
2540 | ; | |
2541 | ||
2542 | (define_expand "cmpstrsi" | |
2543 | [(set (reg:SI 0) (const_int 0)) | |
2544 | (parallel | |
2545 | [(clobber (match_operand 3 "" "")) | |
2546 | (clobber (match_dup 4)) | |
2547 | (set (reg:CCU CC_REGNUM) | |
2548 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2549 | (match_operand:BLK 2 "memory_operand" ""))) | |
2550 | (use (reg:SI 0))]) | |
2551 | (parallel | |
2552 | [(set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 2553 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CCU_TO_INT)) |
ccbdc0d4 AS |
2554 | (clobber (reg:CC CC_REGNUM))])] |
2555 | "" | |
2556 | { | |
2557 | /* As the result of CMPINT is inverted compared to what we need, | |
2558 | we have to swap the operands. */ | |
2559 | rtx op1 = operands[2]; | |
2560 | rtx op2 = operands[1]; | |
2561 | rtx addr1 = gen_reg_rtx (Pmode); | |
2562 | rtx addr2 = gen_reg_rtx (Pmode); | |
2563 | ||
2564 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2565 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2566 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2567 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2568 | operands[3] = addr1; | |
2569 | operands[4] = addr2; | |
2570 | }) | |
2571 | ||
2572 | (define_insn "*cmpstr<mode>" | |
2573 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2574 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2575 | (set (reg:CCU CC_REGNUM) | |
2576 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2577 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2578 | (use (reg:SI 0))] | |
2579 | "" | |
2580 | "clst\t%0,%1\;jo\t.-4" | |
2581 | [(set_attr "length" "8") | |
2582 | (set_attr "type" "vs")]) | |
9381e3f1 | 2583 | |
742090fc AS |
2584 | ; |
2585 | ; movstr instruction pattern. | |
2586 | ; | |
2587 | ||
2588 | (define_expand "movstr" | |
2589 | [(set (reg:SI 0) (const_int 0)) | |
9381e3f1 | 2590 | (parallel |
742090fc AS |
2591 | [(clobber (match_dup 3)) |
2592 | (set (match_operand:BLK 1 "memory_operand" "") | |
2593 | (match_operand:BLK 2 "memory_operand" "")) | |
2594 | (set (match_operand 0 "register_operand" "") | |
9381e3f1 | 2595 | (unspec [(match_dup 1) |
742090fc AS |
2596 | (match_dup 2) |
2597 | (reg:SI 0)] UNSPEC_MVST)) | |
2598 | (clobber (reg:CC CC_REGNUM))])] | |
2599 | "" | |
2600 | { | |
2601 | rtx addr1 = gen_reg_rtx (Pmode); | |
2602 | rtx addr2 = gen_reg_rtx (Pmode); | |
2603 | ||
2604 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2605 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2606 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2607 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2608 | operands[3] = addr2; | |
2609 | }) | |
2610 | ||
2611 | (define_insn "*movstr" | |
2612 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2613 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2614 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2615 | (set (match_operand:P 0 "register_operand" "=d") | |
9381e3f1 | 2616 | (unspec [(mem:BLK (match_dup 1)) |
742090fc AS |
2617 | (mem:BLK (match_dup 3)) |
2618 | (reg:SI 0)] UNSPEC_MVST)) | |
2619 | (clobber (reg:CC CC_REGNUM))] | |
2620 | "" | |
2621 | "mvst\t%1,%2\;jo\t.-4" | |
2622 | [(set_attr "length" "8") | |
2623 | (set_attr "type" "vs")]) | |
9381e3f1 | 2624 | |
742090fc | 2625 | |
9db1d521 | 2626 | ; |
70128ad9 | 2627 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2628 | ; |
2629 | ||
9db2f16d | 2630 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2631 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2632 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2633 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2634 | (match_operand 3 "" "")] |
2635 | "" | |
70128ad9 | 2636 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2637 | |
ecbe845e UW |
2638 | ; Move a block that is up to 256 bytes in length. |
2639 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2640 | |
70128ad9 | 2641 | (define_expand "movmem_short" |
b9404c99 UW |
2642 | [(parallel |
2643 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2644 | (match_operand:BLK 1 "memory_operand" "")) | |
2645 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2646 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2647 | (clobber (match_dup 3))])] |
2648 | "" | |
2649 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2650 | |
70128ad9 | 2651 | (define_insn "*movmem_short" |
963fc8d0 AK |
2652 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
2653 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2654 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2655 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
2656 | (clobber (match_scratch 4 "=X,X,X,&a"))] | |
b9404c99 | 2657 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2658 | && GET_MODE (operands[4]) == Pmode" |
2659 | "#" | |
963fc8d0 AK |
2660 | [(set_attr "type" "cs") |
2661 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
ecbe845e | 2662 | |
9bb86f41 UW |
2663 | (define_split |
2664 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2665 | (match_operand:BLK 1 "memory_operand" "")) | |
2666 | (use (match_operand 2 "const_int_operand" "")) | |
2667 | (use (match_operand 3 "immediate_operand" "")) | |
2668 | (clobber (scratch))] | |
2669 | "reload_completed" | |
2670 | [(parallel | |
2671 | [(set (match_dup 0) (match_dup 1)) | |
2672 | (use (match_dup 2))])] | |
2673 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2674 | |
9bb86f41 UW |
2675 | (define_split |
2676 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2677 | (match_operand:BLK 1 "memory_operand" "")) | |
2678 | (use (match_operand 2 "register_operand" "")) | |
2679 | (use (match_operand 3 "memory_operand" "")) | |
2680 | (clobber (scratch))] | |
2681 | "reload_completed" | |
2682 | [(parallel | |
2683 | [(unspec [(match_dup 2) (match_dup 3) | |
2684 | (const_int 0)] UNSPEC_EXECUTE) | |
2685 | (set (match_dup 0) (match_dup 1)) | |
2686 | (use (const_int 1))])] | |
2687 | "") | |
2688 | ||
963fc8d0 AK |
2689 | (define_split |
2690 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2691 | (match_operand:BLK 1 "memory_operand" "")) | |
2692 | (use (match_operand 2 "register_operand" "")) | |
2693 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2694 | (clobber (scratch))] | |
2695 | "TARGET_Z10 && reload_completed" | |
2696 | [(parallel | |
2697 | [(unspec [(match_dup 2) (const_int 0) | |
2698 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2699 | (set (match_dup 0) (match_dup 1)) | |
2700 | (use (const_int 1))])] | |
2701 | "operands[3] = gen_label_rtx ();") | |
2702 | ||
9bb86f41 UW |
2703 | (define_split |
2704 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2705 | (match_operand:BLK 1 "memory_operand" "")) | |
2706 | (use (match_operand 2 "register_operand" "")) | |
2707 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2708 | (clobber (match_operand 3 "register_operand" ""))] | |
2709 | "reload_completed && TARGET_CPU_ZARCH" | |
2710 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2711 | (parallel | |
9381e3f1 | 2712 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
2713 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
2714 | (set (match_dup 0) (match_dup 1)) | |
2715 | (use (const_int 1))])] | |
2716 | "operands[4] = gen_label_rtx ();") | |
2717 | ||
a41c6c53 | 2718 | ; Move a block of arbitrary length. |
9db1d521 | 2719 | |
70128ad9 | 2720 | (define_expand "movmem_long" |
b9404c99 UW |
2721 | [(parallel |
2722 | [(clobber (match_dup 2)) | |
2723 | (clobber (match_dup 3)) | |
2724 | (set (match_operand:BLK 0 "memory_operand" "") | |
2725 | (match_operand:BLK 1 "memory_operand" "")) | |
2726 | (use (match_operand 2 "general_operand" "")) | |
2727 | (use (match_dup 3)) | |
ae156f85 | 2728 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2729 | "" |
2730 | { | |
9602b6a1 AK |
2731 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
2732 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
2733 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
2734 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
2735 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
2736 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
2737 | rtx len0 = gen_lowpart (Pmode, reg0); |
2738 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2739 | ||
c41c1387 | 2740 | emit_clobber (reg0); |
b9404c99 UW |
2741 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2742 | emit_move_insn (len0, operands[2]); | |
2743 | ||
c41c1387 | 2744 | emit_clobber (reg1); |
b9404c99 UW |
2745 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2746 | emit_move_insn (len1, operands[2]); | |
2747 | ||
2748 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2749 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2750 | operands[2] = reg0; | |
2751 | operands[3] = reg1; | |
2752 | }) | |
2753 | ||
a1aed706 AS |
2754 | (define_insn "*movmem_long" |
2755 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2756 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2757 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2758 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2759 | (use (match_dup 2)) |
2760 | (use (match_dup 3)) | |
ae156f85 | 2761 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
2762 | "TARGET_64BIT || !TARGET_ZARCH" |
2763 | "mvcle\t%0,%1,0\;jo\t.-4" | |
2764 | [(set_attr "length" "8") | |
2765 | (set_attr "type" "vs")]) | |
2766 | ||
2767 | (define_insn "*movmem_long_31z" | |
2768 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2769 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2770 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
2771 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
2772 | (use (match_dup 2)) | |
2773 | (use (match_dup 3)) | |
2774 | (clobber (reg:CC CC_REGNUM))] | |
2775 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 2776 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2777 | [(set_attr "length" "8") |
2778 | (set_attr "type" "vs")]) | |
9db1d521 | 2779 | |
638e37c2 WG |
2780 | |
2781 | ; | |
2782 | ; Test data class. | |
2783 | ; | |
2784 | ||
0f67fa83 WG |
2785 | (define_expand "signbit<mode>2" |
2786 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2787 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2788 | (match_dup 2)] | |
0f67fa83 WG |
2789 | UNSPEC_TDC_INSN)) |
2790 | (set (match_operand:SI 0 "register_operand" "=d") | |
2791 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
2792 | "TARGET_HARD_FLOAT" | |
2793 | { | |
2794 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
2795 | }) | |
2796 | ||
638e37c2 WG |
2797 | (define_expand "isinf<mode>2" |
2798 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2799 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2800 | (match_dup 2)] | |
638e37c2 WG |
2801 | UNSPEC_TDC_INSN)) |
2802 | (set (match_operand:SI 0 "register_operand" "=d") | |
2803 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CCZ_TO_INT))] | |
142cd70f | 2804 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
2805 | { |
2806 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
2807 | }) | |
2808 | ||
2809 | ; This insn is used to generate all variants of the Test Data Class | |
2810 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
2811 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 2812 | ; specifying the required test(s). |
638e37c2 WG |
2813 | ; |
2814 | (define_insn "*TDC_insn_<mode>" | |
2815 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 2816 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 2817 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 2818 | "TARGET_HARD_FLOAT" |
0387c142 | 2819 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 2820 | [(set_attr "op_type" "RXE") |
9381e3f1 | 2821 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 WG |
2822 | |
2823 | (define_insn_and_split "*ccz_to_int" | |
2824 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2825 | (unspec:SI [(match_operand:CCZ 1 "register_operand" "0")] | |
2826 | UNSPEC_CCZ_TO_INT))] | |
2827 | "" | |
2828 | "#" | |
2829 | "reload_completed" | |
2830 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
2831 | ||
2832 | ||
9db1d521 | 2833 | ; |
57e84f18 | 2834 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2835 | ; |
2836 | ||
57e84f18 | 2837 | (define_expand "setmem<mode>" |
a41c6c53 | 2838 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2839 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2840 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2841 | (match_operand 3 "" "")] |
a41c6c53 | 2842 | "" |
6d057022 | 2843 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2844 | |
a41c6c53 | 2845 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2846 | ; The block length is taken as (operands[1] % 256) + 1. |
2847 | ||
70128ad9 | 2848 | (define_expand "clrmem_short" |
b9404c99 UW |
2849 | [(parallel |
2850 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2851 | (const_int 0)) | |
2852 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2853 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2854 | (clobber (match_dup 2)) |
ae156f85 | 2855 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2856 | "" |
2857 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2858 | |
70128ad9 | 2859 | (define_insn "*clrmem_short" |
963fc8d0 | 2860 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 2861 | (const_int 0)) |
963fc8d0 AK |
2862 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
2863 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
2864 | (clobber (match_scratch 3 "=X,X,X,&a")) | |
ae156f85 | 2865 | (clobber (reg:CC CC_REGNUM))] |
b9404c99 | 2866 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
2867 | && GET_MODE (operands[3]) == Pmode" |
2868 | "#" | |
963fc8d0 AK |
2869 | [(set_attr "type" "cs") |
2870 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9bb86f41 UW |
2871 | |
2872 | (define_split | |
2873 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2874 | (const_int 0)) | |
2875 | (use (match_operand 1 "const_int_operand" "")) | |
2876 | (use (match_operand 2 "immediate_operand" "")) | |
2877 | (clobber (scratch)) | |
ae156f85 | 2878 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2879 | "reload_completed" |
2880 | [(parallel | |
2881 | [(set (match_dup 0) (const_int 0)) | |
2882 | (use (match_dup 1)) | |
ae156f85 | 2883 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2884 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2885 | |
9bb86f41 UW |
2886 | (define_split |
2887 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2888 | (const_int 0)) | |
2889 | (use (match_operand 1 "register_operand" "")) | |
2890 | (use (match_operand 2 "memory_operand" "")) | |
2891 | (clobber (scratch)) | |
ae156f85 | 2892 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2893 | "reload_completed" |
2894 | [(parallel | |
2895 | [(unspec [(match_dup 1) (match_dup 2) | |
2896 | (const_int 0)] UNSPEC_EXECUTE) | |
2897 | (set (match_dup 0) (const_int 0)) | |
2898 | (use (const_int 1)) | |
ae156f85 | 2899 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2900 | "") |
9db1d521 | 2901 | |
963fc8d0 AK |
2902 | (define_split |
2903 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2904 | (const_int 0)) | |
2905 | (use (match_operand 1 "register_operand" "")) | |
2906 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2907 | (clobber (scratch)) | |
2908 | (clobber (reg:CC CC_REGNUM))] | |
2909 | "TARGET_Z10 && reload_completed" | |
2910 | [(parallel | |
2911 | [(unspec [(match_dup 1) (const_int 0) | |
2912 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2913 | (set (match_dup 0) (const_int 0)) | |
2914 | (use (const_int 1)) | |
2915 | (clobber (reg:CC CC_REGNUM))])] | |
2916 | "operands[3] = gen_label_rtx ();") | |
2917 | ||
9bb86f41 UW |
2918 | (define_split |
2919 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2920 | (const_int 0)) | |
2921 | (use (match_operand 1 "register_operand" "")) | |
2922 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2923 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2924 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2925 | "reload_completed && TARGET_CPU_ZARCH" |
2926 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2927 | (parallel | |
9381e3f1 | 2928 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
2929 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
2930 | (set (match_dup 0) (const_int 0)) | |
2931 | (use (const_int 1)) | |
ae156f85 | 2932 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2933 | "operands[3] = gen_label_rtx ();") |
2934 | ||
9381e3f1 | 2935 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2936 | |
6d057022 | 2937 | (define_expand "setmem_long" |
b9404c99 UW |
2938 | [(parallel |
2939 | [(clobber (match_dup 1)) | |
2940 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 2941 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 2942 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2943 | (use (match_dup 3)) |
ae156f85 | 2944 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2945 | "" |
a41c6c53 | 2946 | { |
9602b6a1 AK |
2947 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
2948 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
2949 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
2950 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
2951 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 2952 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 2953 | |
c41c1387 | 2954 | emit_clobber (reg0); |
b9404c99 UW |
2955 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2956 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2957 | |
b9404c99 | 2958 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2959 | |
b9404c99 UW |
2960 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2961 | operands[1] = reg0; | |
6d057022 | 2962 | operands[3] = reg1; |
b9404c99 | 2963 | }) |
a41c6c53 | 2964 | |
6d057022 | 2965 | (define_insn "*setmem_long" |
a1aed706 | 2966 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 2967 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 2968 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 2969 | (use (match_dup 3)) |
a1aed706 | 2970 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2971 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 2972 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 2973 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
2974 | [(set_attr "length" "8") |
2975 | (set_attr "type" "vs")]) | |
9db1d521 | 2976 | |
4989e88a AK |
2977 | (define_insn "*setmem_long_and" |
2978 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2979 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
2980 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
2981 | (match_operand 4 "const_int_operand" "n"))) | |
2982 | (use (match_dup 3)) | |
2983 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
2984 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 AK |
2985 | "(TARGET_64BIT || !TARGET_ZARCH) && |
2986 | (INTVAL (operands[4]) & 255) == 255" | |
2987 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
2988 | [(set_attr "length" "8") | |
2989 | (set_attr "type" "vs")]) | |
2990 | ||
2991 | (define_insn "*setmem_long_31z" | |
2992 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2993 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
2994 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) | |
2995 | (use (match_dup 3)) | |
2996 | (use (match_operand:TI 1 "register_operand" "d")) | |
2997 | (clobber (reg:CC CC_REGNUM))] | |
2998 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
2999 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3000 | [(set_attr "length" "8") | |
3001 | (set_attr "type" "vs")]) | |
9602b6a1 | 3002 | |
9db1d521 | 3003 | ; |
358b8f01 | 3004 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3005 | ; |
3006 | ||
358b8f01 | 3007 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3008 | [(set (match_operand:SI 0 "register_operand" "") |
3009 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3010 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3011 | (use (match_operand:SI 3 "general_operand" "")) | |
3012 | (use (match_operand:SI 4 "" ""))] | |
3013 | "" | |
c7453384 | 3014 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 3015 | operands[2], operands[3]); DONE;") |
9db1d521 | 3016 | |
a41c6c53 UW |
3017 | ; Compare a block that is up to 256 bytes in length. |
3018 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3019 | |
b9404c99 UW |
3020 | (define_expand "cmpmem_short" |
3021 | [(parallel | |
ae156f85 | 3022 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3023 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3024 | (match_operand:BLK 1 "memory_operand" ""))) |
3025 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3026 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3027 | (clobber (match_dup 3))])] |
3028 | "" | |
3029 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3030 | |
b9404c99 | 3031 | (define_insn "*cmpmem_short" |
ae156f85 | 3032 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3033 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3034 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3035 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3036 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
3037 | (clobber (match_scratch 4 "=X,X,X,&a"))] | |
b9404c99 | 3038 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
3039 | && GET_MODE (operands[4]) == Pmode" |
3040 | "#" | |
963fc8d0 AK |
3041 | [(set_attr "type" "cs") |
3042 | (set_attr "cpu_facility" "*,*,z10,*")]) | |
9db1d521 | 3043 | |
9bb86f41 | 3044 | (define_split |
ae156f85 | 3045 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3046 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3047 | (match_operand:BLK 1 "memory_operand" ""))) | |
3048 | (use (match_operand 2 "const_int_operand" "")) | |
3049 | (use (match_operand 3 "immediate_operand" "")) | |
3050 | (clobber (scratch))] | |
3051 | "reload_completed" | |
3052 | [(parallel | |
ae156f85 | 3053 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3054 | (use (match_dup 2))])] |
3055 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3056 | |
9bb86f41 | 3057 | (define_split |
ae156f85 | 3058 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3059 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3060 | (match_operand:BLK 1 "memory_operand" ""))) | |
3061 | (use (match_operand 2 "register_operand" "")) | |
3062 | (use (match_operand 3 "memory_operand" "")) | |
3063 | (clobber (scratch))] | |
3064 | "reload_completed" | |
3065 | [(parallel | |
3066 | [(unspec [(match_dup 2) (match_dup 3) | |
3067 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3068 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3069 | (use (const_int 1))])] |
3070 | "") | |
3071 | ||
963fc8d0 AK |
3072 | (define_split |
3073 | [(set (reg:CCU CC_REGNUM) | |
3074 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3075 | (match_operand:BLK 1 "memory_operand" ""))) | |
3076 | (use (match_operand 2 "register_operand" "")) | |
3077 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3078 | (clobber (scratch))] | |
3079 | "TARGET_Z10 && reload_completed" | |
3080 | [(parallel | |
3081 | [(unspec [(match_dup 2) (const_int 0) | |
3082 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3083 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3084 | (use (const_int 1))])] | |
3085 | "operands[4] = gen_label_rtx ();") | |
3086 | ||
9bb86f41 | 3087 | (define_split |
ae156f85 | 3088 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3089 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3090 | (match_operand:BLK 1 "memory_operand" ""))) | |
3091 | (use (match_operand 2 "register_operand" "")) | |
3092 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3093 | (clobber (match_operand 3 "register_operand" ""))] | |
3094 | "reload_completed && TARGET_CPU_ZARCH" | |
3095 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3096 | (parallel | |
9381e3f1 | 3097 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3098 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3099 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3100 | (use (const_int 1))])] |
3101 | "operands[4] = gen_label_rtx ();") | |
3102 | ||
a41c6c53 | 3103 | ; Compare a block of arbitrary length. |
9db1d521 | 3104 | |
b9404c99 UW |
3105 | (define_expand "cmpmem_long" |
3106 | [(parallel | |
3107 | [(clobber (match_dup 2)) | |
3108 | (clobber (match_dup 3)) | |
ae156f85 | 3109 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3110 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3111 | (match_operand:BLK 1 "memory_operand" ""))) |
3112 | (use (match_operand 2 "general_operand" "")) | |
3113 | (use (match_dup 3))])] | |
3114 | "" | |
3115 | { | |
9602b6a1 AK |
3116 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3117 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
3118 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
3119 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3120 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3121 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3122 | rtx len0 = gen_lowpart (Pmode, reg0); |
3123 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3124 | ||
c41c1387 | 3125 | emit_clobber (reg0); |
b9404c99 UW |
3126 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3127 | emit_move_insn (len0, operands[2]); | |
3128 | ||
c41c1387 | 3129 | emit_clobber (reg1); |
b9404c99 UW |
3130 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3131 | emit_move_insn (len1, operands[2]); | |
3132 | ||
3133 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3134 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3135 | operands[2] = reg0; | |
3136 | operands[3] = reg1; | |
3137 | }) | |
3138 | ||
a1aed706 AS |
3139 | (define_insn "*cmpmem_long" |
3140 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3141 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3142 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3143 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3144 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3145 | (use (match_dup 2)) |
3146 | (use (match_dup 3))] | |
9602b6a1 | 3147 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3148 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3149 | [(set_attr "length" "8") |
3150 | (set_attr "type" "vs")]) | |
9db1d521 | 3151 | |
9602b6a1 AK |
3152 | (define_insn "*cmpmem_long_31z" |
3153 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3154 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3155 | (set (reg:CCU CC_REGNUM) | |
3156 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3157 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3158 | (use (match_dup 2)) | |
3159 | (use (match_dup 3))] | |
3160 | "!TARGET_64BIT && TARGET_ZARCH" | |
3161 | "clcle\t%0,%1,0\;jo\t.-4" | |
3162 | [(set_attr "op_type" "NN") | |
3163 | (set_attr "type" "vs") | |
3164 | (set_attr "length" "8")]) | |
3165 | ||
02887425 UW |
3166 | ; Convert CCUmode condition code to integer. |
3167 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3168 | |
02887425 | 3169 | (define_insn_and_split "cmpint" |
9db1d521 | 3170 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3171 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3172 | UNSPEC_CCU_TO_INT)) |
ae156f85 | 3173 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3174 | "" |
02887425 UW |
3175 | "#" |
3176 | "reload_completed" | |
3177 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3178 | (parallel | |
3179 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3180 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3181 | |
3182 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3183 | [(set (reg CC_REGNUM) |
02887425 | 3184 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3185 | UNSPEC_CCU_TO_INT) |
02887425 UW |
3186 | (const_int 0))) |
3187 | (set (match_operand:SI 0 "register_operand" "=d") | |
638e37c2 | 3188 | (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT))] |
02887425 UW |
3189 | "s390_match_ccmode (insn, CCSmode)" |
3190 | "#" | |
3191 | "&& reload_completed" | |
3192 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3193 | (parallel | |
3194 | [(set (match_dup 2) (match_dup 3)) | |
3195 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3196 | { |
02887425 UW |
3197 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3198 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3199 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3200 | }) | |
9db1d521 | 3201 | |
02887425 | 3202 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3203 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3204 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3205 | UNSPEC_CCU_TO_INT))) |
ae156f85 | 3206 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3207 | "TARGET_ZARCH" |
02887425 UW |
3208 | "#" |
3209 | "&& reload_completed" | |
3210 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3211 | (parallel | |
3212 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3213 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3214 | |
3215 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3216 | [(set (reg CC_REGNUM) |
9381e3f1 | 3217 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3218 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
638e37c2 | 3219 | UNSPEC_CCU_TO_INT) 0) |
02887425 UW |
3220 | (const_int 32)) (const_int 32)) |
3221 | (const_int 0))) | |
3222 | (set (match_operand:DI 0 "register_operand" "=d") | |
638e37c2 | 3223 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))] |
9602b6a1 | 3224 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3225 | "#" |
3226 | "&& reload_completed" | |
3227 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3228 | (parallel | |
3229 | [(set (match_dup 2) (match_dup 3)) | |
3230 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3231 | { |
02887425 UW |
3232 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3233 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3234 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3235 | }) | |
9db1d521 | 3236 | |
4023fb28 | 3237 | |
9db1d521 HP |
3238 | ;; |
3239 | ;;- Conversion instructions. | |
3240 | ;; | |
3241 | ||
6fa05db6 | 3242 | (define_insn "*sethighpartsi" |
d3632d41 | 3243 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3244 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3245 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3246 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3247 | "" |
d3632d41 | 3248 | "@ |
6fa05db6 AS |
3249 | icm\t%0,%2,%S1 |
3250 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3251 | [(set_attr "op_type" "RS,RSY") |
3252 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3253 | |
6fa05db6 | 3254 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3255 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3256 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3257 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3258 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3259 | "TARGET_ZARCH" |
6fa05db6 | 3260 | "icmh\t%0,%2,%S1" |
729e750f WG |
3261 | [(set_attr "op_type" "RSY") |
3262 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3263 | |
6fa05db6 | 3264 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3265 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3266 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3267 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3268 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3269 | "!TARGET_ZARCH" |
d3632d41 | 3270 | "@ |
6fa05db6 AS |
3271 | icm\t%0,%2,%S1 |
3272 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3273 | [(set_attr "op_type" "RS,RSY") |
3274 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3275 | ||
4023fb28 | 3276 | |
6fa05db6 AS |
3277 | (define_insn_and_split "*extzv<mode>" |
3278 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3279 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3280 | (match_operand 2 "const_int_operand" "n") | |
3281 | (const_int 0))) | |
ae156f85 | 3282 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3283 | "INTVAL (operands[2]) > 0 |
3284 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3285 | "#" |
3286 | "&& reload_completed" | |
4023fb28 | 3287 | [(parallel |
6fa05db6 | 3288 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3289 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3290 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3291 | { |
6fa05db6 AS |
3292 | int bitsize = INTVAL (operands[2]); |
3293 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3294 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3295 | ||
3296 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3297 | set_mem_size (operands[1], GEN_INT (size)); | |
3298 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
3299 | operands[3] = GEN_INT (mask); | |
b628bd8e | 3300 | }) |
4023fb28 | 3301 | |
6fa05db6 AS |
3302 | (define_insn_and_split "*extv<mode>" |
3303 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3304 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
3305 | (match_operand 2 "const_int_operand" "n") | |
3306 | (const_int 0))) | |
ae156f85 | 3307 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
3308 | "INTVAL (operands[2]) > 0 |
3309 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
3310 | "#" |
3311 | "&& reload_completed" | |
4023fb28 | 3312 | [(parallel |
6fa05db6 | 3313 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3314 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3315 | (parallel |
3316 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3317 | (clobber (reg:CC CC_REGNUM))])] | |
3318 | { | |
3319 | int bitsize = INTVAL (operands[2]); | |
3320 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3321 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3322 | ||
3323 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3324 | set_mem_size (operands[1], GEN_INT (size)); | |
3325 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
3326 | operands[3] = GEN_INT (mask); | |
3327 | }) | |
3328 | ||
3329 | ; | |
3330 | ; insv instruction patterns | |
3331 | ; | |
3332 | ||
3333 | (define_expand "insv" | |
3334 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3335 | (match_operand 1 "const_int_operand" "") | |
3336 | (match_operand 2 "const_int_operand" "")) | |
3337 | (match_operand 3 "general_operand" ""))] | |
3338 | "" | |
4023fb28 | 3339 | { |
6fa05db6 AS |
3340 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3341 | DONE; | |
3342 | FAIL; | |
b628bd8e | 3343 | }) |
4023fb28 | 3344 | |
963fc8d0 AK |
3345 | (define_insn "*insv<mode>_z10" |
3346 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
3347 | (match_operand 1 "const_int_operand" "I") | |
3348 | (match_operand 2 "const_int_operand" "I")) | |
3349 | (match_operand:GPR 3 "nonimmediate_operand" "d")) | |
3350 | (clobber (reg:CC CC_REGNUM))] | |
3351 | "TARGET_Z10 | |
3352 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= | |
3353 | GET_MODE_BITSIZE (<MODE>mode)" | |
3354 | { | |
3355 | int start = INTVAL (operands[2]); | |
3356 | int size = INTVAL (operands[1]); | |
3357 | int offset = 64 - GET_MODE_BITSIZE (<MODE>mode); | |
3358 | ||
3359 | operands[2] = GEN_INT (offset + start); /* start bit position */ | |
3360 | operands[1] = GEN_INT (offset + start + size - 1); /* end bit position */ | |
3361 | operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - | |
3362 | start - size); /* left shift count */ | |
3363 | ||
3364 | return "risbg\t%0,%3,%b2,%b1,%b4"; | |
3365 | } | |
9381e3f1 WG |
3366 | [(set_attr "op_type" "RIE") |
3367 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3368 | |
3369 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3370 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3371 | (define_insn "*insv<mode>_z10_noshift" | |
3372 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3373 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3374 | (match_operand 2 "const_int_operand" "n")) | |
3375 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") | |
3376 | (match_operand 4 "const_int_operand" "n")))) | |
3377 | (clobber (reg:CC CC_REGNUM))] | |
3378 | "TARGET_Z10 | |
3379 | && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3380 | GET_MODE_BITSIZE (<MODE>mode), NULL, NULL) | |
3381 | && INTVAL (operands[2]) == ~(INTVAL (operands[4]))" | |
3382 | ||
3383 | { | |
3384 | int start; | |
3385 | int size; | |
3386 | ||
3387 | s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3388 | GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3389 | ||
3390 | operands[5] = GEN_INT (64 - start - size); /* start bit position */ | |
3391 | operands[6] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3392 | operands[7] = const0_rtx; /* left shift count */ | |
3393 | ||
3394 | return "risbg\t%0,%1,%b5,%b6,%b7"; | |
3395 | } | |
9381e3f1 WG |
3396 | [(set_attr "op_type" "RIE") |
3397 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 AK |
3398 | |
3399 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest | |
3400 | (define_insn "*insv<mode>_or_z10_noshift" | |
3401 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3402 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3403 | (match_operand 2 "const_int_operand" "n")) | |
3404 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
3405 | (clobber (reg:CC CC_REGNUM))] | |
3406 | "TARGET_Z10 | |
3407 | && s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3408 | GET_MODE_BITSIZE (<MODE>mode), NULL, NULL)" | |
3409 | { | |
3410 | int start; | |
3411 | int size; | |
3412 | ||
3413 | s390_contiguous_bitmask_p (INTVAL (operands[2]), | |
3414 | GET_MODE_BITSIZE (<MODE>mode), &start, &size); | |
3415 | ||
3416 | operands[4] = GEN_INT (64 - start - size); /* start bit position */ | |
3417 | operands[5] = GEN_INT (64 - 1 - start); /* end bit position */ | |
3418 | operands[6] = const0_rtx; /* left shift count */ | |
3419 | ||
3420 | return "rosbg\t%0,%1,%b4,%b5,%b6"; | |
3421 | } | |
3422 | [(set_attr "op_type" "RIE")]) | |
3423 | ||
6fa05db6 | 3424 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 3425 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
3426 | (match_operand 1 "const_int_operand" "n,n") |
3427 | (const_int 0)) | |
9602b6a1 | 3428 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
3429 | "INTVAL (operands[1]) > 0 |
3430 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3431 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3432 | { | |
3433 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3434 | ||
3435 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 3436 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
3437 | : "stcmy\t%2,%1,%S0"; |
3438 | } | |
9381e3f1 WG |
3439 | [(set_attr "op_type" "RS,RSY") |
3440 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
3441 | |
3442 | (define_insn "*insvdi_mem_reghigh" | |
3443 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3444 | (match_operand 1 "const_int_operand" "n") | |
3445 | (const_int 0)) | |
3446 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3447 | (const_int 32)))] | |
9602b6a1 | 3448 | "TARGET_ZARCH |
6fa05db6 AS |
3449 | && INTVAL (operands[1]) > 0 |
3450 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3451 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3452 | { | |
3453 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3454 | ||
3455 | operands[1] = GEN_INT ((1ul << size) - 1); | |
3456 | return "stcmh\t%2,%1,%S0"; | |
3457 | } | |
9381e3f1 WG |
3458 | [(set_attr "op_type" "RSY") |
3459 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 3460 | |
9602b6a1 AK |
3461 | (define_insn "*insvdi_reg_imm" |
3462 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3463 | (const_int 16) | |
3464 | (match_operand 1 "const_int_operand" "n")) | |
3465 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
3466 | "TARGET_ZARCH |
3467 | && INTVAL (operands[1]) >= 0 | |
3468 | && INTVAL (operands[1]) < BITS_PER_WORD | |
3469 | && INTVAL (operands[1]) % 16 == 0" | |
3470 | { | |
3471 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3472 | { | |
3473 | case 64: return "iihh\t%0,%x2"; break; | |
3474 | case 48: return "iihl\t%0,%x2"; break; | |
3475 | case 32: return "iilh\t%0,%x2"; break; | |
3476 | case 16: return "iill\t%0,%x2"; break; | |
3477 | default: gcc_unreachable(); | |
3478 | } | |
3479 | } | |
9381e3f1 WG |
3480 | [(set_attr "op_type" "RI") |
3481 | (set_attr "z10prop" "z10_super_E1")]) | |
3482 | ||
9fec758d WG |
3483 | ; Update the left-most 32 bit of a DI. |
3484 | (define_insn "*insv_h_di_reg_extimm" | |
3485 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3486 | (const_int 32) | |
3487 | (const_int 0)) | |
3488 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3489 | "TARGET_EXTIMM" | |
3490 | "iihf\t%0,%o1" | |
3491 | [(set_attr "op_type" "RIL") | |
3492 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 3493 | |
9fec758d WG |
3494 | ; Update the right-most 32 bit of a DI, or the whole of a SI. |
3495 | (define_insn "*insv_l<mode>_reg_extimm" | |
6fa05db6 AS |
3496 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") |
3497 | (const_int 32) | |
3498 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 3499 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 | 3500 | "TARGET_EXTIMM |
9fec758d WG |
3501 | && BITS_PER_WORD - INTVAL (operands[1]) == 32" |
3502 | "iilf\t%0,%o2" | |
9381e3f1 | 3503 | [(set_attr "op_type" "RIL") |
9fec758d | 3504 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 3505 | |
9db1d521 HP |
3506 | ; |
3507 | ; extendsidi2 instruction pattern(s). | |
3508 | ; | |
3509 | ||
4023fb28 UW |
3510 | (define_expand "extendsidi2" |
3511 | [(set (match_operand:DI 0 "register_operand" "") | |
3512 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3513 | "" | |
4023fb28 | 3514 | { |
9602b6a1 | 3515 | if (!TARGET_ZARCH) |
4023fb28 | 3516 | { |
c41c1387 | 3517 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3518 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
3519 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
3520 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
3521 | DONE; |
3522 | } | |
ec24698e | 3523 | }) |
4023fb28 UW |
3524 | |
3525 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
3526 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3527 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3528 | "TARGET_ZARCH" |
9db1d521 | 3529 | "@ |
d40c829f | 3530 | lgfr\t%0,%1 |
963fc8d0 AK |
3531 | lgf\t%0,%1 |
3532 | lgfrl\t%0,%1" | |
3533 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3534 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3535 | (set_attr "cpu_facility" "*,*,z10") |
3536 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3537 | |
9db1d521 | 3538 | ; |
56477c21 | 3539 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3540 | ; |
3541 | ||
56477c21 AS |
3542 | (define_expand "extend<HQI:mode><DSI:mode>2" |
3543 | [(set (match_operand:DSI 0 "register_operand" "") | |
3544 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 3545 | "" |
4023fb28 | 3546 | { |
9602b6a1 | 3547 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
3548 | { |
3549 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 3550 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
3551 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
3552 | DONE; | |
3553 | } | |
ec24698e | 3554 | else if (!TARGET_EXTIMM) |
4023fb28 | 3555 | { |
56477c21 AS |
3556 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - |
3557 | GET_MODE_BITSIZE (<HQI:MODE>mode)); | |
3558 | ||
3559 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
3560 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
3561 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
3562 | DONE; |
3563 | } | |
ec24698e UW |
3564 | }) |
3565 | ||
56477c21 AS |
3566 | ; |
3567 | ; extendhidi2 instruction pattern(s). | |
3568 | ; | |
3569 | ||
ec24698e | 3570 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
3571 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3572 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 3573 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
3574 | "@ |
3575 | lghr\t%0,%1 | |
963fc8d0 AK |
3576 | lgh\t%0,%1 |
3577 | lghrl\t%0,%1" | |
3578 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3579 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3580 | (set_attr "cpu_facility" "extimm,extimm,z10") |
3581 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
3582 | |
3583 | (define_insn "*extendhidi2" | |
9db1d521 | 3584 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 3585 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 3586 | "TARGET_ZARCH" |
d40c829f | 3587 | "lgh\t%0,%1" |
9381e3f1 WG |
3588 | [(set_attr "op_type" "RXY") |
3589 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 3590 | |
9db1d521 | 3591 | ; |
56477c21 | 3592 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
3593 | ; |
3594 | ||
ec24698e | 3595 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
3596 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3597 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
3598 | "TARGET_EXTIMM" |
3599 | "@ | |
3600 | lhr\t%0,%1 | |
3601 | lh\t%0,%1 | |
963fc8d0 AK |
3602 | lhy\t%0,%1 |
3603 | lhrl\t%0,%1" | |
3604 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
3605 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
3606 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
3607 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3608 | |
4023fb28 | 3609 | (define_insn "*extendhisi2" |
d3632d41 UW |
3610 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3611 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 3612 | "!TARGET_EXTIMM" |
d3632d41 | 3613 | "@ |
d40c829f UW |
3614 | lh\t%0,%1 |
3615 | lhy\t%0,%1" | |
9381e3f1 WG |
3616 | [(set_attr "op_type" "RX,RXY") |
3617 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3618 | |
56477c21 AS |
3619 | ; |
3620 | ; extendqi(si|di)2 instruction pattern(s). | |
3621 | ; | |
3622 | ||
43a09b63 | 3623 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
3624 | (define_insn "*extendqi<mode>2_extimm" |
3625 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3626 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3627 | "TARGET_EXTIMM" |
3628 | "@ | |
56477c21 AS |
3629 | l<g>br\t%0,%1 |
3630 | l<g>b\t%0,%1" | |
9381e3f1 WG |
3631 | [(set_attr "op_type" "RRE,RXY") |
3632 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 3633 | |
43a09b63 | 3634 | ; lb, lgb |
56477c21 AS |
3635 | (define_insn "*extendqi<mode>2" |
3636 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3637 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
3638 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
3639 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
3640 | [(set_attr "op_type" "RXY") |
3641 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 3642 | |
56477c21 AS |
3643 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
3644 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3645 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 3646 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 3647 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
3648 | "#" |
3649 | "&& reload_completed" | |
4023fb28 | 3650 | [(parallel |
56477c21 | 3651 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 3652 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 3653 | (parallel |
56477c21 | 3654 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 3655 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
3656 | { |
3657 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
3658 | set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); | |
56477c21 AS |
3659 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) |
3660 | - GET_MODE_BITSIZE (QImode)); | |
6fa05db6 | 3661 | }) |
9db1d521 | 3662 | |
9db1d521 HP |
3663 | ; |
3664 | ; zero_extendsidi2 instruction pattern(s). | |
3665 | ; | |
3666 | ||
4023fb28 UW |
3667 | (define_expand "zero_extendsidi2" |
3668 | [(set (match_operand:DI 0 "register_operand" "") | |
3669 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3670 | "" | |
4023fb28 | 3671 | { |
9602b6a1 | 3672 | if (!TARGET_ZARCH) |
4023fb28 | 3673 | { |
c41c1387 | 3674 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3675 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
3676 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
3677 | DONE; |
3678 | } | |
ec24698e | 3679 | }) |
4023fb28 UW |
3680 | |
3681 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
3682 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3683 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3684 | "TARGET_ZARCH" |
9db1d521 | 3685 | "@ |
d40c829f | 3686 | llgfr\t%0,%1 |
963fc8d0 AK |
3687 | llgf\t%0,%1 |
3688 | llgfrl\t%0,%1" | |
3689 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3690 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3691 | (set_attr "cpu_facility" "*,*,z10") |
3692 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 3693 | |
288e517f AK |
3694 | ; |
3695 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
3696 | ; | |
3697 | ||
d6083c7d UW |
3698 | (define_insn "*llgt_sidi" |
3699 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3700 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3701 | (const_int 2147483647)))] |
9602b6a1 | 3702 | "TARGET_ZARCH" |
d6083c7d | 3703 | "llgt\t%0,%1" |
9381e3f1 WG |
3704 | [(set_attr "op_type" "RXE") |
3705 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
3706 | |
3707 | (define_insn_and_split "*llgt_sidi_split" | |
3708 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3709 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3710 | (const_int 2147483647))) |
ae156f85 | 3711 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3712 | "TARGET_ZARCH" |
d6083c7d UW |
3713 | "#" |
3714 | "&& reload_completed" | |
3715 | [(set (match_dup 0) | |
3716 | (and:DI (subreg:DI (match_dup 1) 0) | |
3717 | (const_int 2147483647)))] | |
3718 | "") | |
3719 | ||
288e517f AK |
3720 | (define_insn "*llgt_sisi" |
3721 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 3722 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 3723 | (const_int 2147483647)))] |
c4d50129 | 3724 | "TARGET_ZARCH" |
288e517f AK |
3725 | "@ |
3726 | llgtr\t%0,%1 | |
3727 | llgt\t%0,%1" | |
9381e3f1 WG |
3728 | [(set_attr "op_type" "RRE,RXE") |
3729 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3730 | |
288e517f AK |
3731 | (define_insn "*llgt_didi" |
3732 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3733 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
3734 | (const_int 2147483647)))] | |
9602b6a1 | 3735 | "TARGET_ZARCH" |
288e517f AK |
3736 | "@ |
3737 | llgtr\t%0,%1 | |
3738 | llgt\t%0,%N1" | |
9381e3f1 WG |
3739 | [(set_attr "op_type" "RRE,RXE") |
3740 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3741 | |
f19a9af7 | 3742 | (define_split |
9602b6a1 AK |
3743 | [(set (match_operand:DSI 0 "register_operand" "") |
3744 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 3745 | (const_int 2147483647))) |
ae156f85 | 3746 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 3747 | "TARGET_ZARCH && reload_completed" |
288e517f | 3748 | [(set (match_dup 0) |
9602b6a1 | 3749 | (and:DSI (match_dup 1) |
f6ee577c | 3750 | (const_int 2147483647)))] |
288e517f AK |
3751 | "") |
3752 | ||
9db1d521 | 3753 | ; |
56477c21 | 3754 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3755 | ; |
3756 | ||
56477c21 AS |
3757 | (define_expand "zero_extend<mode>di2" |
3758 | [(set (match_operand:DI 0 "register_operand" "") | |
3759 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3760 | "" | |
3761 | { | |
9602b6a1 | 3762 | if (!TARGET_ZARCH) |
56477c21 AS |
3763 | { |
3764 | rtx tmp = gen_reg_rtx (SImode); | |
3765 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3766 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3767 | DONE; | |
3768 | } | |
3769 | else if (!TARGET_EXTIMM) | |
3770 | { | |
9381e3f1 | 3771 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - |
56477c21 AS |
3772 | GET_MODE_BITSIZE(<MODE>mode)); |
3773 | operands[1] = gen_lowpart (DImode, operands[1]); | |
3774 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
3775 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
3776 | DONE; | |
3777 | } | |
3778 | }) | |
3779 | ||
f6ee577c | 3780 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 3781 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 3782 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 3783 | "" |
4023fb28 | 3784 | { |
ec24698e UW |
3785 | if (!TARGET_EXTIMM) |
3786 | { | |
3787 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 3788 | emit_insn (gen_andsi3 (operands[0], operands[1], |
ec24698e UW |
3789 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); |
3790 | DONE; | |
56477c21 | 3791 | } |
ec24698e UW |
3792 | }) |
3793 | ||
963fc8d0 AK |
3794 | ; llhrl, llghrl |
3795 | (define_insn "*zero_extendhi<mode>2_z10" | |
3796 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3797 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
3798 | "TARGET_Z10" | |
3799 | "@ | |
3800 | ll<g>hr\t%0,%1 | |
3801 | ll<g>h\t%0,%1 | |
3802 | ll<g>hrl\t%0,%1" | |
3803 | [(set_attr "op_type" "RXY,RRE,RIL") | |
3804 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 3805 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 3806 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 3807 | |
43a09b63 | 3808 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
3809 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
3810 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3811 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3812 | "TARGET_EXTIMM" |
3813 | "@ | |
56477c21 AS |
3814 | ll<g><hc>r\t%0,%1 |
3815 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
3816 | [(set_attr "op_type" "RRE,RXY") |
3817 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 3818 | |
43a09b63 | 3819 | ; llgh, llgc |
56477c21 AS |
3820 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
3821 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3822 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 3823 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 3824 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
3825 | [(set_attr "op_type" "RXY") |
3826 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
3827 | |
3828 | (define_insn_and_split "*zero_extendhisi2_31" | |
3829 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 3830 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 3831 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 3832 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3833 | "#" |
3834 | "&& reload_completed" | |
3835 | [(set (match_dup 0) (const_int 0)) | |
3836 | (parallel | |
3837 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 3838 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 3839 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 3840 | |
cc7ab9b7 UW |
3841 | (define_insn_and_split "*zero_extendqisi2_31" |
3842 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 3843 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3844 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3845 | "#" |
3846 | "&& reload_completed" | |
3847 | [(set (match_dup 0) (const_int 0)) | |
3848 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3849 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 3850 | |
9db1d521 HP |
3851 | ; |
3852 | ; zero_extendqihi2 instruction pattern(s). | |
3853 | ; | |
3854 | ||
9db1d521 HP |
3855 | (define_expand "zero_extendqihi2" |
3856 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 3857 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 3858 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 3859 | { |
4023fb28 UW |
3860 | operands[1] = gen_lowpart (HImode, operands[1]); |
3861 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
3862 | DONE; | |
ec24698e | 3863 | }) |
9db1d521 | 3864 | |
4023fb28 | 3865 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 3866 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 3867 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 3868 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 3869 | "llgc\t%0,%1" |
9381e3f1 WG |
3870 | [(set_attr "op_type" "RXY") |
3871 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 3872 | |
cc7ab9b7 UW |
3873 | (define_insn_and_split "*zero_extendqihi2_31" |
3874 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 3875 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 3876 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
3877 | "#" |
3878 | "&& reload_completed" | |
3879 | [(set (match_dup 0) (const_int 0)) | |
3880 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 3881 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 3882 | |
609e7e80 AK |
3883 | ; |
3884 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
3885 | ; | |
3886 | ||
3887 | (define_expand "fixuns_truncdddi2" | |
3888 | [(parallel | |
3889 | [(set (match_operand:DI 0 "register_operand" "") | |
3890 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
65b1d8ea AK |
3891 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) |
3892 | (clobber (reg:CC CC_REGNUM))])] | |
9381e3f1 | 3893 | |
fb068247 | 3894 | "TARGET_HARD_DFP" |
609e7e80 | 3895 | { |
65b1d8ea AK |
3896 | if (!TARGET_Z196) |
3897 | { | |
3898 | rtx label1 = gen_label_rtx (); | |
3899 | rtx label2 = gen_label_rtx (); | |
3900 | rtx temp = gen_reg_rtx (TDmode); | |
3901 | REAL_VALUE_TYPE cmp, sub; | |
3902 | ||
3903 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3904 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3905 | ||
3906 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
3907 | solution is doing the check and the subtraction in TD mode and using a | |
3908 | TD -> DI convert afterwards. */ | |
3909 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
3910 | temp = force_reg (TDmode, temp); | |
3911 | emit_cmp_and_jump_insns (temp, | |
3912 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
3913 | LT, NULL_RTX, VOIDmode, 0, label1); | |
3914 | emit_insn (gen_subtd3 (temp, temp, | |
3915 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
3916 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
3917 | emit_jump (label2); | |
3918 | ||
3919 | emit_label (label1); | |
3920 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
3921 | emit_label (label2); | |
3922 | DONE; | |
3923 | } | |
609e7e80 AK |
3924 | }) |
3925 | ||
3926 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
3927 | [(parallel |
3928 | [(set (match_operand:DI 0 "register_operand" "") | |
3929 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
3930 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) | |
3931 | (clobber (reg:CC CC_REGNUM))])] | |
3932 | ||
fb068247 | 3933 | "TARGET_HARD_DFP" |
609e7e80 | 3934 | { |
65b1d8ea AK |
3935 | if (!TARGET_Z196) |
3936 | { | |
3937 | rtx label1 = gen_label_rtx (); | |
3938 | rtx label2 = gen_label_rtx (); | |
3939 | rtx temp = gen_reg_rtx (TDmode); | |
3940 | REAL_VALUE_TYPE cmp, sub; | |
3941 | ||
3942 | operands[1] = force_reg (TDmode, operands[1]); | |
3943 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
3944 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
3945 | ||
3946 | emit_cmp_and_jump_insns (operands[1], | |
3947 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
3948 | LT, NULL_RTX, VOIDmode, 0, label1); | |
3949 | emit_insn (gen_subtd3 (temp, operands[1], | |
3950 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
3951 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
3952 | emit_jump (label2); | |
3953 | ||
3954 | emit_label (label1); | |
3955 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
3956 | emit_label (label2); | |
3957 | DONE; | |
3958 | } | |
609e7e80 | 3959 | }) |
cc7ab9b7 | 3960 | |
9db1d521 | 3961 | ; |
65b1d8ea | 3962 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 3963 | ; instruction pattern(s). |
9db1d521 HP |
3964 | ; |
3965 | ||
7b6baae1 | 3966 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
3967 | [(parallel |
3968 | [(set (match_operand:GPR 0 "register_operand" "") | |
3969 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
3970 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
3971 | (clobber (reg:CC CC_REGNUM))])] | |
142cd70f | 3972 | "TARGET_HARD_FLOAT" |
9db1d521 | 3973 | { |
65b1d8ea AK |
3974 | if (!TARGET_Z196) |
3975 | { | |
3976 | rtx label1 = gen_label_rtx (); | |
3977 | rtx label2 = gen_label_rtx (); | |
3978 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
3979 | REAL_VALUE_TYPE cmp, sub; | |
3980 | ||
3981 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
3982 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode); | |
3983 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode); | |
3984 | ||
3985 | emit_cmp_and_jump_insns (operands[1], | |
3986 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), | |
3987 | LT, NULL_RTX, VOIDmode, 0, label1); | |
3988 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
3989 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); | |
3990 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
3991 | GEN_INT (7))); | |
3992 | emit_jump (label2); | |
3993 | ||
3994 | emit_label (label1); | |
3995 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
3996 | operands[1], GEN_INT (5))); | |
3997 | emit_label (label2); | |
3998 | DONE; | |
3999 | } | |
10bbf137 | 4000 | }) |
9db1d521 | 4001 | |
65b1d8ea AK |
4002 | ; fixuns_trunc(td|dd)si2 expander |
4003 | (define_expand "fixuns_trunc<mode>si2" | |
4004 | [(parallel | |
4005 | [(set (match_operand:SI 0 "register_operand" "") | |
4006 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
4007 | (unspec:SI [(const_int 5)] UNSPEC_ROUND) | |
4008 | (clobber (reg:CC CC_REGNUM))])] | |
4009 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4010 | "") | |
4011 | ||
4012 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4013 | ||
4014 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr | |
4015 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4016 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
4017 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
4018 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4019 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4020 | (clobber (reg:CC CC_REGNUM))] | |
4021 | "TARGET_Z196" | |
4022 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" | |
4023 | [(set_attr "op_type" "RRF") | |
4024 | (set_attr "type" "ftoi")]) | |
4025 | ||
b60cb710 AK |
4026 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4027 | [(set (match_operand:GPR 0 "register_operand" "") | |
4028 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4029 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4030 | { |
b60cb710 AK |
4031 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
4032 | GEN_INT (5))); | |
9db1d521 | 4033 | DONE; |
10bbf137 | 4034 | }) |
9db1d521 | 4035 | |
43a09b63 | 4036 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
142cd70f | 4037 | (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
2f8f8434 | 4038 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7b6baae1 | 4039 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) |
2f8f8434 | 4040 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) |
ae156f85 | 4041 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4042 | "TARGET_HARD_FLOAT" |
7b6baae1 | 4043 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4044 | [(set_attr "op_type" "RRE") |
077dab3b | 4045 | (set_attr "type" "ftoi")]) |
9db1d521 | 4046 | |
609e7e80 AK |
4047 | |
4048 | ; | |
4049 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4050 | ; | |
4051 | ||
99cd7dd0 AK |
4052 | (define_expand "fix_trunc<mode>di2" |
4053 | [(set (match_operand:DI 0 "register_operand" "") | |
4054 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4055 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4056 | { |
4057 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4058 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
4059 | GEN_INT (9))); | |
4060 | DONE; | |
4061 | }) | |
4062 | ||
609e7e80 | 4063 | ; cgxtr, cgdtr |
99cd7dd0 | 4064 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4065 | [(set (match_operand:DI 0 "register_operand" "=d") |
4066 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4067 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4068 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4069 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4070 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4071 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4072 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4073 | |
4074 | ||
f61a2c7d AK |
4075 | ; |
4076 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4077 | ; | |
4078 | ||
4079 | (define_expand "fix_trunctf<mode>2" | |
4080 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4081 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
4082 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4083 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 4084 | "TARGET_HARD_FLOAT" |
142cd70f | 4085 | "") |
9db1d521 | 4086 | |
9db1d521 | 4087 | |
9db1d521 | 4088 | ; |
142cd70f | 4089 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4090 | ; |
4091 | ||
609e7e80 | 4092 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4093 | (define_insn "floatdi<mode>2" |
609e7e80 AK |
4094 | [(set (match_operand:FP 0 "register_operand" "=f") |
4095 | (float:FP (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 4096 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
609e7e80 | 4097 | "c<xde>g<bt>r\t%0,%1" |
9db1d521 | 4098 | [(set_attr "op_type" "RRE") |
9381e3f1 | 4099 | (set_attr "type" "itof<mode>" )]) |
9db1d521 | 4100 | |
43a09b63 | 4101 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4102 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4103 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4104 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4105 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4106 | "c<xde>fbr\t%0,%1" |
4107 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4108 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4109 | |
65b1d8ea AK |
4110 | ; cxftr, cdftr |
4111 | (define_insn "floatsi<mode>2" | |
4112 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4113 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4114 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4115 | "c<xde>ftr\t%0,0,%1,0" | |
4116 | [(set_attr "op_type" "RRE") | |
4117 | (set_attr "type" "itof<mode>" )]) | |
4118 | ||
4119 | ; | |
4120 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4121 | ; | |
4122 | ||
4123 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr | |
4124 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
4125 | (define_insn "floatuns<GPR:mode><FP:mode>2" | |
4126 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4127 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4128 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4129 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" | |
4130 | [(set_attr "op_type" "RRE") | |
4131 | (set_attr "type" "itof<FP:mode>" )]) | |
f61a2c7d | 4132 | |
9db1d521 HP |
4133 | ; |
4134 | ; truncdfsf2 instruction pattern(s). | |
4135 | ; | |
4136 | ||
142cd70f | 4137 | (define_insn "truncdfsf2" |
9db1d521 | 4138 | [(set (match_operand:SF 0 "register_operand" "=f") |
a036c6f7 | 4139 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
142cd70f | 4140 | "TARGET_HARD_FLOAT" |
d40c829f | 4141 | "ledbr\t%0,%1" |
f61a2c7d AK |
4142 | [(set_attr "op_type" "RRE") |
4143 | (set_attr "type" "ftruncdf")]) | |
9db1d521 | 4144 | |
f61a2c7d | 4145 | ; |
142cd70f | 4146 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4147 | ; |
4148 | ||
142cd70f AK |
4149 | ; ldxbr, lexbr |
4150 | (define_insn "trunctf<mode>2" | |
4151 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4152 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4153 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4154 | "TARGET_HARD_FLOAT" |
4155 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4156 | [(set_attr "length" "6") |
9381e3f1 | 4157 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4158 | |
609e7e80 AK |
4159 | ; |
4160 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4161 | ; | |
4162 | ||
4163 | (define_insn "trunctddd2" | |
4164 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
4165 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4166 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4167 | "TARGET_HARD_DFP" |
bf259a77 AK |
4168 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4169 | [(set_attr "length" "6") | |
9381e3f1 | 4170 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4171 | |
4172 | (define_insn "truncddsd2" | |
4173 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4174 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4175 | "TARGET_HARD_DFP" |
609e7e80 AK |
4176 | "ledtr\t%0,0,%1,0" |
4177 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4178 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4179 | |
9db1d521 | 4180 | ; |
142cd70f | 4181 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4182 | ; |
4183 | ||
142cd70f AK |
4184 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
4185 | (define_insn "extend<DSF:mode><BFP:mode>2" | |
4186 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
4187 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] | |
4188 | "TARGET_HARD_FLOAT | |
4189 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)" | |
f61a2c7d | 4190 | "@ |
142cd70f AK |
4191 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4192 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
f61a2c7d | 4193 | [(set_attr "op_type" "RRE,RXE") |
142cd70f | 4194 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) |
f61a2c7d | 4195 | |
609e7e80 AK |
4196 | ; |
4197 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4198 | ; | |
4199 | ||
4200 | (define_insn "extendddtd2" | |
4201 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4202 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4203 | "TARGET_HARD_DFP" |
609e7e80 AK |
4204 | "lxdtr\t%0,%1,0" |
4205 | [(set_attr "op_type" "RRF") | |
4206 | (set_attr "type" "fsimptf")]) | |
4207 | ||
4208 | (define_insn "extendsddd2" | |
4209 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4210 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4211 | "TARGET_HARD_DFP" |
609e7e80 AK |
4212 | "ldetr\t%0,%1,0" |
4213 | [(set_attr "op_type" "RRF") | |
4214 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4215 | |
35dd9a0e AK |
4216 | ; Binary <-> Decimal floating point trunc patterns |
4217 | ; | |
4218 | ||
4219 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4220 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4221 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4222 | (use (reg:SI GPR0_REGNUM)) | |
4223 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4224 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4225 | "pfpo") |
4226 | ||
4227 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4228 | [(set (reg:BFP FPR0_REGNUM) | |
4229 | (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4230 | (use (reg:SI GPR0_REGNUM)) | |
4231 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4232 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4233 | "pfpo") |
4234 | ||
4235 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
4236 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4237 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4238 | (parallel | |
4239 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4240 | (float_truncate:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4241 | (use (reg:SI GPR0_REGNUM)) | |
4242 | (clobber (reg:CC CC_REGNUM))]) | |
4243 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4244 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4245 | "TARGET_HARD_DFP |
35dd9a0e AK |
4246 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4247 | { | |
4248 | HOST_WIDE_INT flags; | |
4249 | ||
4250 | flags = (PFPO_CONVERT | | |
4251 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4252 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4253 | ||
4254 | operands[2] = GEN_INT (flags); | |
4255 | }) | |
4256 | ||
4257 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
4258 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4259 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4260 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4261 | (parallel | |
4262 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4263 | (use (reg:SI GPR0_REGNUM)) | |
4264 | (clobber (reg:CC CC_REGNUM))]) | |
4265 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4266 | "TARGET_HARD_DFP |
35dd9a0e AK |
4267 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
4268 | { | |
4269 | HOST_WIDE_INT flags; | |
4270 | ||
4271 | flags = (PFPO_CONVERT | | |
4272 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4273 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4274 | ||
4275 | operands[2] = GEN_INT (flags); | |
4276 | }) | |
4277 | ||
4278 | ; | |
4279 | ; Binary <-> Decimal floating point extend patterns | |
4280 | ; | |
4281 | ||
4282 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
4283 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4284 | (use (reg:SI GPR0_REGNUM)) | |
4285 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4286 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4287 | "pfpo") |
4288 | ||
4289 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
4290 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4291 | (use (reg:SI GPR0_REGNUM)) | |
4292 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4293 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4294 | "pfpo") |
4295 | ||
4296 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
4297 | [(set (reg:BFP FPR2_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) | |
4298 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4299 | (parallel | |
4300 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
4301 | (float_extend:DFP_ALL (reg:BFP FPR2_REGNUM))) | |
4302 | (use (reg:SI GPR0_REGNUM)) | |
4303 | (clobber (reg:CC CC_REGNUM))]) | |
4304 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4305 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4306 | "TARGET_HARD_DFP |
35dd9a0e AK |
4307 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4308 | { | |
4309 | HOST_WIDE_INT flags; | |
4310 | ||
4311 | flags = (PFPO_CONVERT | | |
4312 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4313 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4314 | ||
4315 | operands[2] = GEN_INT (flags); | |
4316 | }) | |
4317 | ||
4318 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
4319 | [(set (reg:DFP_ALL FPR2_REGNUM) | |
4320 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) | |
4321 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4322 | (parallel | |
4323 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR2_REGNUM))) | |
4324 | (use (reg:SI GPR0_REGNUM)) | |
4325 | (clobber (reg:CC CC_REGNUM))]) | |
4326 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4327 | "TARGET_HARD_DFP |
35dd9a0e AK |
4328 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
4329 | { | |
4330 | HOST_WIDE_INT flags; | |
4331 | ||
4332 | flags = (PFPO_CONVERT | | |
4333 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4334 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4335 | ||
4336 | operands[2] = GEN_INT (flags); | |
4337 | }) | |
4338 | ||
4339 | ||
9db1d521 | 4340 | ;; |
fae778eb | 4341 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 4342 | ;; |
fae778eb | 4343 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
4344 | ; because of unpredictable Bits in Register for Halfword and Byte |
4345 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
4346 | ||
07893d4f UW |
4347 | ;; |
4348 | ;;- Add instructions. | |
4349 | ;; | |
4350 | ||
1c7b1b7e UW |
4351 | ; |
4352 | ; addti3 instruction pattern(s). | |
4353 | ; | |
4354 | ||
4355 | (define_insn_and_split "addti3" | |
4356 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4357 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
4358 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4359 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4360 | "TARGET_ZARCH" |
1c7b1b7e UW |
4361 | "#" |
4362 | "&& reload_completed" | |
4363 | [(parallel | |
ae156f85 | 4364 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
4365 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
4366 | (match_dup 7))) | |
4367 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
4368 | (parallel | |
a94a76a7 UW |
4369 | [(set (match_dup 3) (plus:DI |
4370 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4371 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4372 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
4373 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4374 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4375 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4376 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4377 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4378 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4379 | |
07893d4f UW |
4380 | ; |
4381 | ; adddi3 instruction pattern(s). | |
4382 | ; | |
4383 | ||
3298c037 AK |
4384 | (define_expand "adddi3" |
4385 | [(parallel | |
963fc8d0 | 4386 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
4387 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
4388 | (match_operand:DI 2 "general_operand" ""))) | |
4389 | (clobber (reg:CC CC_REGNUM))])] | |
4390 | "" | |
4391 | "") | |
4392 | ||
07893d4f UW |
4393 | (define_insn "*adddi3_sign" |
4394 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4395 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4396 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4397 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4398 | "TARGET_ZARCH" |
07893d4f | 4399 | "@ |
d40c829f UW |
4400 | agfr\t%0,%2 |
4401 | agf\t%0,%2" | |
65b1d8ea AK |
4402 | [(set_attr "op_type" "RRE,RXY") |
4403 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
4404 | |
4405 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 4406 | [(set (reg CC_REGNUM) |
fb492564 | 4407 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4408 | (match_operand:DI 1 "register_operand" "0,0")) |
4409 | (const_int 0))) | |
4410 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4411 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 4412 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4413 | "@ |
d40c829f UW |
4414 | algfr\t%0,%2 |
4415 | algf\t%0,%2" | |
9381e3f1 WG |
4416 | [(set_attr "op_type" "RRE,RXY") |
4417 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4418 | |
4419 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 4420 | [(set (reg CC_REGNUM) |
fb492564 | 4421 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4422 | (match_operand:DI 1 "register_operand" "0,0")) |
4423 | (const_int 0))) | |
4424 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 4425 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4426 | "@ |
d40c829f UW |
4427 | algfr\t%0,%2 |
4428 | algf\t%0,%2" | |
9381e3f1 WG |
4429 | [(set_attr "op_type" "RRE,RXY") |
4430 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4431 | |
4432 | (define_insn "*adddi3_zero" | |
4433 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4434 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4435 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4436 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4437 | "TARGET_ZARCH" |
07893d4f | 4438 | "@ |
d40c829f UW |
4439 | algfr\t%0,%2 |
4440 | algf\t%0,%2" | |
9381e3f1 WG |
4441 | [(set_attr "op_type" "RRE,RXY") |
4442 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 4443 | |
e69166de | 4444 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 4445 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
4446 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
4447 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4448 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4449 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
4450 | "#" |
4451 | "&& reload_completed" | |
4452 | [(parallel | |
ae156f85 | 4453 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
4454 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4455 | (match_dup 7))) | |
4456 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4457 | (parallel | |
a94a76a7 UW |
4458 | [(set (match_dup 3) (plus:SI |
4459 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4460 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4461 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
4462 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4463 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4464 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4465 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4466 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4467 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4468 | |
07893d4f | 4469 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 4470 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 4471 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 4472 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4473 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4474 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4475 | "#" |
4476 | "&& reload_completed" | |
4477 | [(parallel | |
4478 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4479 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4480 | (parallel |
ae156f85 | 4481 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
4482 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4483 | (match_dup 7))) | |
4484 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4485 | (set (pc) | |
ae156f85 | 4486 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4487 | (pc) |
4488 | (label_ref (match_dup 9)))) | |
4489 | (parallel | |
4490 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 4491 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4492 | (match_dup 9)] |
97c6f7ad UW |
4493 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4494 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4495 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4496 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4497 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4498 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4499 | operands[9] = gen_label_rtx ();") |
9db1d521 | 4500 | |
3298c037 AK |
4501 | ; |
4502 | ; addsi3 instruction pattern(s). | |
4503 | ; | |
4504 | ||
4505 | (define_expand "addsi3" | |
07893d4f | 4506 | [(parallel |
963fc8d0 | 4507 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
4508 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
4509 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4510 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4511 | "" |
07893d4f | 4512 | "") |
9db1d521 | 4513 | |
3298c037 AK |
4514 | (define_insn "*addsi3_sign" |
4515 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4516 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
4517 | (match_operand:SI 1 "register_operand" "0,0"))) | |
4518 | (clobber (reg:CC CC_REGNUM))] | |
4519 | "" | |
4520 | "@ | |
4521 | ah\t%0,%2 | |
4522 | ahy\t%0,%2" | |
65b1d8ea AK |
4523 | [(set_attr "op_type" "RX,RXY") |
4524 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 4525 | |
9db1d521 | 4526 | ; |
3298c037 | 4527 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 4528 | ; |
9db1d521 | 4529 | |
65b1d8ea | 4530 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 4531 | (define_insn "*add<mode>3" |
65b1d8ea AK |
4532 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
4533 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
4534 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
4535 | (clobber (reg:CC CC_REGNUM))] |
4536 | "" | |
ec24698e | 4537 | "@ |
3298c037 | 4538 | a<g>r\t%0,%2 |
65b1d8ea | 4539 | a<g>rk\t%0,%1,%2 |
3298c037 | 4540 | a<g>hi\t%0,%h2 |
65b1d8ea | 4541 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
4542 | al<g>fi\t%0,%2 |
4543 | sl<g>fi\t%0,%n2 | |
4544 | a<g>\t%0,%2 | |
963fc8d0 AK |
4545 | a<y>\t%0,%2 |
4546 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4547 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
4548 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
4549 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4550 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 4551 | |
65b1d8ea | 4552 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 4553 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 4554 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4555 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
4556 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 4557 | (match_dup 1))) |
65b1d8ea | 4558 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 4559 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4560 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4561 | "@ |
3298c037 | 4562 | al<g>r\t%0,%2 |
65b1d8ea | 4563 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4564 | al<g>fi\t%0,%2 |
4565 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4566 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4567 | al<g>\t%0,%2 |
963fc8d0 AK |
4568 | al<y>\t%0,%2 |
4569 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4570 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4571 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4572 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4573 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4574 | |
65b1d8ea | 4575 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4576 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 4577 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4578 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4579 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4580 | (match_dup 1))) |
65b1d8ea | 4581 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4582 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4583 | "@ |
3298c037 | 4584 | al<g>r\t%0,%2 |
65b1d8ea | 4585 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4586 | al<g>\t%0,%2 |
4587 | al<y>\t%0,%2" | |
65b1d8ea AK |
4588 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4589 | (set_attr "cpu_facility" "*,z196,*,*") | |
4590 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4591 | |
65b1d8ea | 4592 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4593 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 4594 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4595 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4596 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 4597 | (match_dup 2))) |
65b1d8ea | 4598 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4599 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4600 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4601 | "@ |
3298c037 | 4602 | al<g>r\t%0,%2 |
65b1d8ea | 4603 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4604 | al<g>fi\t%0,%2 |
4605 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4606 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4607 | al<g>\t%0,%2 |
963fc8d0 AK |
4608 | al<y>\t%0,%2 |
4609 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4610 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4611 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4612 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4613 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4614 | |
65b1d8ea | 4615 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4616 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 4617 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4618 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4619 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4620 | (match_dup 2))) |
65b1d8ea | 4621 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4622 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4623 | "@ |
3298c037 | 4624 | al<g>r\t%0,%2 |
65b1d8ea | 4625 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4626 | al<g>\t%0,%2 |
4627 | al<y>\t%0,%2" | |
65b1d8ea AK |
4628 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4629 | (set_attr "cpu_facility" "*,z196,*,*") | |
4630 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4631 | |
65b1d8ea | 4632 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4633 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4634 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4635 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4636 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 4637 | (const_int 0))) |
65b1d8ea | 4638 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4639 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4640 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4641 | "@ |
3298c037 | 4642 | al<g>r\t%0,%2 |
65b1d8ea | 4643 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4644 | al<g>fi\t%0,%2 |
4645 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4646 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4647 | al<g>\t%0,%2 |
963fc8d0 AK |
4648 | al<y>\t%0,%2 |
4649 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4650 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4651 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4652 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4653 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4654 | |
65b1d8ea | 4655 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4656 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4657 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4658 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4659 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 4660 | (const_int 0))) |
65b1d8ea | 4661 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4662 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4663 | "@ |
3298c037 | 4664 | al<g>r\t%0,%2 |
65b1d8ea | 4665 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4666 | al<g>\t%0,%2 |
4667 | al<y>\t%0,%2" | |
65b1d8ea AK |
4668 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4669 | (set_attr "cpu_facility" "*,z196,*,*") | |
4670 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4671 | |
65b1d8ea | 4672 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4673 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 4674 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4675 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4676 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
4677 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 4678 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 4679 | "@ |
3298c037 | 4680 | al<g>r\t%0,%2 |
65b1d8ea | 4681 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4682 | al<g>\t%0,%2 |
4683 | al<y>\t%0,%2" | |
65b1d8ea AK |
4684 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4685 | (set_attr "cpu_facility" "*,z196,*,*") | |
4686 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4687 | |
963fc8d0 | 4688 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
4689 | (define_insn "*add<mode>3_imm_cc" |
4690 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
4691 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
4692 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 4693 | (const_int 0))) |
65b1d8ea | 4694 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
4695 | (plus:GPR (match_dup 1) (match_dup 2)))] |
4696 | "s390_match_ccmode (insn, CCAmode) | |
4697 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
963fc8d0 AK |
4698 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
4699 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'C', \"C\")) | |
3298c037 | 4700 | && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))" |
9db1d521 | 4701 | "@ |
3298c037 | 4702 | a<g>hi\t%0,%h2 |
65b1d8ea | 4703 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
4704 | a<g>fi\t%0,%2 |
4705 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4706 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
4707 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
4708 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4709 | |
9db1d521 | 4710 | ; |
609e7e80 | 4711 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4712 | ; |
4713 | ||
609e7e80 | 4714 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
142cd70f | 4715 | (define_insn "add<mode>3" |
609e7e80 AK |
4716 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4717 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4718 | (match_operand:FP 2 "general_operand" " f,<Rf>"))) | |
ae156f85 | 4719 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4720 | "TARGET_HARD_FLOAT" |
9db1d521 | 4721 | "@ |
609e7e80 | 4722 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4723 | a<xde>b\t%0,%2" |
609e7e80 | 4724 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4725 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4726 | |
609e7e80 | 4727 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4728 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4729 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4730 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4731 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4732 | (match_operand:FP 3 "const0_operand" ""))) | |
4733 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
4734 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 4735 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4736 | "@ |
609e7e80 | 4737 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4738 | a<xde>b\t%0,%2" |
609e7e80 | 4739 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4740 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4741 | |
609e7e80 | 4742 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 4743 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4744 | [(set (reg CC_REGNUM) |
609e7e80 AK |
4745 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
4746 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
4747 | (match_operand:FP 3 "const0_operand" ""))) | |
4748 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 4749 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 4750 | "@ |
609e7e80 | 4751 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 4752 | a<xde>b\t%0,%2" |
609e7e80 | 4753 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 4754 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4755 | |
9db1d521 HP |
4756 | |
4757 | ;; | |
4758 | ;;- Subtract instructions. | |
4759 | ;; | |
4760 | ||
1c7b1b7e UW |
4761 | ; |
4762 | ; subti3 instruction pattern(s). | |
4763 | ; | |
4764 | ||
4765 | (define_insn_and_split "subti3" | |
4766 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4767 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
4768 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4769 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4770 | "TARGET_ZARCH" |
1c7b1b7e UW |
4771 | "#" |
4772 | "&& reload_completed" | |
4773 | [(parallel | |
ae156f85 | 4774 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
4775 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
4776 | (match_dup 7))) | |
4777 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
4778 | (parallel | |
4779 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4780 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4781 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
4782 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4783 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4784 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4785 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4786 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4787 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4788 | |
9db1d521 HP |
4789 | ; |
4790 | ; subdi3 instruction pattern(s). | |
4791 | ; | |
4792 | ||
3298c037 AK |
4793 | (define_expand "subdi3" |
4794 | [(parallel | |
4795 | [(set (match_operand:DI 0 "register_operand" "") | |
4796 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4797 | (match_operand:DI 2 "general_operand" ""))) | |
4798 | (clobber (reg:CC CC_REGNUM))])] | |
4799 | "" | |
4800 | "") | |
4801 | ||
07893d4f UW |
4802 | (define_insn "*subdi3_sign" |
4803 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4804 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4805 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4806 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4807 | "TARGET_ZARCH" |
07893d4f | 4808 | "@ |
d40c829f UW |
4809 | sgfr\t%0,%2 |
4810 | sgf\t%0,%2" | |
9381e3f1 | 4811 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
4812 | (set_attr "z10prop" "z10_c,*") |
4813 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
4814 | |
4815 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 4816 | [(set (reg CC_REGNUM) |
07893d4f | 4817 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4818 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4819 | (const_int 0))) |
4820 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4821 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 4822 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4823 | "@ |
d40c829f UW |
4824 | slgfr\t%0,%2 |
4825 | slgf\t%0,%2" | |
9381e3f1 WG |
4826 | [(set_attr "op_type" "RRE,RXY") |
4827 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4828 | |
4829 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 4830 | [(set (reg CC_REGNUM) |
07893d4f | 4831 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 4832 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
4833 | (const_int 0))) |
4834 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 4835 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4836 | "@ |
d40c829f UW |
4837 | slgfr\t%0,%2 |
4838 | slgf\t%0,%2" | |
9381e3f1 WG |
4839 | [(set_attr "op_type" "RRE,RXY") |
4840 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
4841 | |
4842 | (define_insn "*subdi3_zero" | |
4843 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4844 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 4845 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 4846 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4847 | "TARGET_ZARCH" |
07893d4f | 4848 | "@ |
d40c829f UW |
4849 | slgfr\t%0,%2 |
4850 | slgf\t%0,%2" | |
9381e3f1 WG |
4851 | [(set_attr "op_type" "RRE,RXY") |
4852 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 4853 | |
e69166de UW |
4854 | (define_insn_and_split "*subdi3_31z" |
4855 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4856 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4857 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4858 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4859 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
4860 | "#" |
4861 | "&& reload_completed" | |
4862 | [(parallel | |
ae156f85 | 4863 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
4864 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4865 | (match_dup 7))) | |
4866 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4867 | (parallel | |
4868 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
4869 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
4870 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
4871 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4872 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4873 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4874 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4875 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4876 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4877 | |
07893d4f UW |
4878 | (define_insn_and_split "*subdi3_31" |
4879 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4880 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 4881 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4882 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4883 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4884 | "#" |
4885 | "&& reload_completed" | |
4886 | [(parallel | |
4887 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4888 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4889 | (parallel |
ae156f85 | 4890 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
4891 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
4892 | (match_dup 7))) | |
4893 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4894 | (set (pc) | |
ae156f85 | 4895 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4896 | (pc) |
4897 | (label_ref (match_dup 9)))) | |
4898 | (parallel | |
4899 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 4900 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4901 | (match_dup 9)] |
97c6f7ad UW |
4902 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4903 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4904 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4905 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4906 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4907 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4908 | operands[9] = gen_label_rtx ();") |
07893d4f | 4909 | |
3298c037 AK |
4910 | ; |
4911 | ; subsi3 instruction pattern(s). | |
4912 | ; | |
4913 | ||
4914 | (define_expand "subsi3" | |
07893d4f | 4915 | [(parallel |
3298c037 AK |
4916 | [(set (match_operand:SI 0 "register_operand" "") |
4917 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
4918 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4919 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4920 | "" |
07893d4f | 4921 | "") |
9db1d521 | 4922 | |
3298c037 AK |
4923 | (define_insn "*subsi3_sign" |
4924 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4925 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4926 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
4927 | (clobber (reg:CC CC_REGNUM))] | |
4928 | "" | |
4929 | "@ | |
4930 | sh\t%0,%2 | |
4931 | shy\t%0,%2" | |
65b1d8ea AK |
4932 | [(set_attr "op_type" "RX,RXY") |
4933 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 4934 | |
9db1d521 | 4935 | ; |
3298c037 | 4936 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
4937 | ; |
4938 | ||
65b1d8ea | 4939 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 4940 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
4941 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
4942 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
4943 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
4944 | (clobber (reg:CC CC_REGNUM))] |
4945 | "" | |
4946 | "@ | |
4947 | s<g>r\t%0,%2 | |
65b1d8ea | 4948 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
4949 | s<g>\t%0,%2 |
4950 | s<y>\t%0,%2" | |
65b1d8ea AK |
4951 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4952 | (set_attr "cpu_facility" "*,z196,*,*") | |
4953 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 4954 | |
65b1d8ea | 4955 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 4956 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 4957 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4958 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
4959 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4960 | (match_dup 1))) |
65b1d8ea | 4961 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 4962 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4963 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4964 | "@ |
3298c037 | 4965 | sl<g>r\t%0,%2 |
65b1d8ea | 4966 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
4967 | sl<g>\t%0,%2 |
4968 | sl<y>\t%0,%2" | |
65b1d8ea AK |
4969 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4970 | (set_attr "cpu_facility" "*,z196,*,*") | |
4971 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4972 | |
65b1d8ea | 4973 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 4974 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 4975 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4976 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
4977 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4978 | (match_dup 1))) |
65b1d8ea | 4979 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 4980 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4981 | "@ |
3298c037 | 4982 | sl<g>r\t%0,%2 |
65b1d8ea | 4983 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
4984 | sl<g>\t%0,%2 |
4985 | sl<y>\t%0,%2" | |
65b1d8ea AK |
4986 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4987 | (set_attr "cpu_facility" "*,z196,*,*") | |
4988 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4989 | |
65b1d8ea | 4990 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 4991 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4992 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4993 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
4994 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 4995 | (const_int 0))) |
65b1d8ea | 4996 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 4997 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4998 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4999 | "@ |
3298c037 | 5000 | sl<g>r\t%0,%2 |
65b1d8ea | 5001 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5002 | sl<g>\t%0,%2 |
5003 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5004 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5005 | (set_attr "cpu_facility" "*,z196,*,*") | |
5006 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5007 | |
65b1d8ea | 5008 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5009 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5010 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5011 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5012 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5013 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5014 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5015 | "s390_match_ccmode (insn, CCL3mode)" |
5016 | "@ | |
3298c037 | 5017 | sl<g>r\t%0,%2 |
65b1d8ea | 5018 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5019 | sl<g>\t%0,%2 |
5020 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5021 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5022 | (set_attr "cpu_facility" "*,z196,*,*") | |
5023 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5024 | |
65b1d8ea | 5025 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5026 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5027 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5028 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5029 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5030 | (const_int 0))) |
65b1d8ea | 5031 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5032 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5033 | "@ |
3298c037 | 5034 | sl<g>r\t%0,%2 |
65b1d8ea | 5035 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5036 | sl<g>\t%0,%2 |
5037 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5038 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5039 | (set_attr "cpu_facility" "*,z196,*,*") | |
5040 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5041 | |
9db1d521 | 5042 | |
65b1d8ea | 5043 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5044 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5045 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5046 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5047 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5048 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5049 | "s390_match_ccmode (insn, CCL3mode)" |
5050 | "@ | |
3298c037 | 5051 | sl<g>r\t%0,%2 |
65b1d8ea | 5052 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5053 | sl<g>\t%0,%2 |
5054 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5055 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5056 | (set_attr "cpu_facility" "*,z196,*,*") | |
5057 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5058 | |
9db1d521 HP |
5059 | |
5060 | ; | |
609e7e80 | 5061 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5062 | ; |
5063 | ||
d46f24b6 | 5064 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5065 | (define_insn "sub<mode>3" |
609e7e80 AK |
5066 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
5067 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
142cd70f | 5068 | (match_operand:FP 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 5069 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5070 | "TARGET_HARD_FLOAT" |
9db1d521 | 5071 | "@ |
609e7e80 | 5072 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5073 | s<xde>b\t%0,%2" |
609e7e80 | 5074 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5075 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5076 | |
d46f24b6 | 5077 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5078 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5079 | [(set (reg CC_REGNUM) |
609e7e80 | 5080 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 5081 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
5082 | (match_operand:FP 3 "const0_operand" ""))) |
5083 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5084 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5085 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5086 | "@ |
609e7e80 | 5087 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5088 | s<xde>b\t%0,%2" |
609e7e80 | 5089 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5090 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5091 | |
d46f24b6 | 5092 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5093 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5094 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5095 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
5096 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
5097 | (match_operand:FP 3 "const0_operand" ""))) | |
5098 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5099 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5100 | "@ |
609e7e80 | 5101 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5102 | s<xde>b\t%0,%2" |
609e7e80 | 5103 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5104 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5105 | |
9db1d521 | 5106 | |
e69166de UW |
5107 | ;; |
5108 | ;;- Conditional add/subtract instructions. | |
5109 | ;; | |
5110 | ||
5111 | ; | |
9a91a21f | 5112 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
5113 | ; |
5114 | ||
a996720c UW |
5115 | ; the following 4 patterns are used when the result of an add with |
5116 | ; carry is checked for an overflow condition | |
5117 | ||
5118 | ; op1 + op2 + c < op1 | |
5119 | ||
5120 | ; alcr, alc, alcgr, alcg | |
5121 | (define_insn "*add<mode>3_alc_carry1_cc" | |
5122 | [(set (reg CC_REGNUM) | |
5123 | (compare | |
5124 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5125 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5126 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5127 | (match_dup 1))) |
5128 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5129 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5130 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5131 | "@ | |
5132 | alc<g>r\t%0,%2 | |
5133 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5134 | [(set_attr "op_type" "RRE,RXY") |
5135 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5136 | |
5137 | ; alcr, alc, alcgr, alcg | |
5138 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
5139 | [(set (reg CC_REGNUM) | |
5140 | (compare | |
5141 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5142 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5143 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5144 | (match_dup 1))) |
5145 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5146 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5147 | "@ | |
5148 | alc<g>r\t%0,%2 | |
5149 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5150 | [(set_attr "op_type" "RRE,RXY") |
5151 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5152 | |
5153 | ; op1 + op2 + c < op2 | |
5154 | ||
5155 | ; alcr, alc, alcgr, alcg | |
5156 | (define_insn "*add<mode>3_alc_carry2_cc" | |
5157 | [(set (reg CC_REGNUM) | |
5158 | (compare | |
5159 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5160 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5161 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5162 | (match_dup 2))) |
5163 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5164 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5165 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5166 | "@ | |
5167 | alc<g>r\t%0,%2 | |
5168 | alc<g>\t%0,%2" | |
5169 | [(set_attr "op_type" "RRE,RXY")]) | |
5170 | ||
5171 | ; alcr, alc, alcgr, alcg | |
5172 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
5173 | [(set (reg CC_REGNUM) | |
5174 | (compare | |
5175 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5176 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5177 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5178 | (match_dup 2))) |
5179 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5180 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5181 | "@ | |
5182 | alc<g>r\t%0,%2 | |
5183 | alc<g>\t%0,%2" | |
5184 | [(set_attr "op_type" "RRE,RXY")]) | |
5185 | ||
43a09b63 | 5186 | ; alcr, alc, alcgr, alcg |
9a91a21f | 5187 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 5188 | [(set (reg CC_REGNUM) |
e69166de | 5189 | (compare |
a94a76a7 UW |
5190 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5191 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5192 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 5193 | (const_int 0))) |
9a91a21f | 5194 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 5195 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 5196 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5197 | "@ |
9a91a21f AS |
5198 | alc<g>r\t%0,%2 |
5199 | alc<g>\t%0,%2" | |
e69166de UW |
5200 | [(set_attr "op_type" "RRE,RXY")]) |
5201 | ||
43a09b63 | 5202 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
5203 | (define_insn "*add<mode>3_alc" |
5204 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
5205 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5206 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5207 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 5208 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5209 | "TARGET_CPU_ZARCH" |
e69166de | 5210 | "@ |
9a91a21f AS |
5211 | alc<g>r\t%0,%2 |
5212 | alc<g>\t%0,%2" | |
e69166de UW |
5213 | [(set_attr "op_type" "RRE,RXY")]) |
5214 | ||
43a09b63 | 5215 | ; slbr, slb, slbgr, slbg |
9a91a21f | 5216 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 5217 | [(set (reg CC_REGNUM) |
e69166de | 5218 | (compare |
9a91a21f | 5219 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 5220 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5221 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 5222 | (const_int 0))) |
9a91a21f AS |
5223 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
5224 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 5225 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5226 | "@ |
9a91a21f AS |
5227 | slb<g>r\t%0,%2 |
5228 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5229 | [(set_attr "op_type" "RRE,RXY") |
5230 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5231 | |
43a09b63 | 5232 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
5233 | (define_insn "*sub<mode>3_slb" |
5234 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5235 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 5236 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5237 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 5238 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5239 | "TARGET_CPU_ZARCH" |
e69166de | 5240 | "@ |
9a91a21f AS |
5241 | slb<g>r\t%0,%2 |
5242 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5243 | [(set_attr "op_type" "RRE,RXY") |
5244 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5245 | |
9a91a21f AS |
5246 | (define_expand "add<mode>cc" |
5247 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 5248 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
5249 | (match_operand:GPR 2 "register_operand" "") |
5250 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 5251 | "TARGET_CPU_ZARCH" |
9381e3f1 | 5252 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 5253 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 5254 | operands[0], operands[2], |
5d880bd2 UW |
5255 | operands[3])) FAIL; DONE;") |
5256 | ||
5257 | ; | |
5258 | ; scond instruction pattern(s). | |
5259 | ; | |
5260 | ||
9a91a21f AS |
5261 | (define_insn_and_split "*scond<mode>" |
5262 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5263 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 5264 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5265 | "TARGET_CPU_ZARCH" |
5266 | "#" | |
5267 | "&& reload_completed" | |
5268 | [(set (match_dup 0) (const_int 0)) | |
5269 | (parallel | |
a94a76a7 UW |
5270 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
5271 | (match_dup 0))) | |
ae156f85 | 5272 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5273 | "") |
5d880bd2 | 5274 | |
9a91a21f AS |
5275 | (define_insn_and_split "*scond<mode>_neg" |
5276 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5277 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 5278 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5279 | "TARGET_CPU_ZARCH" |
5280 | "#" | |
5281 | "&& reload_completed" | |
5282 | [(set (match_dup 0) (const_int 0)) | |
5283 | (parallel | |
9a91a21f AS |
5284 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
5285 | (match_dup 1))) | |
ae156f85 | 5286 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 5287 | (parallel |
9a91a21f | 5288 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 5289 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5290 | "") |
5d880bd2 | 5291 | |
5d880bd2 | 5292 | |
f90b7a5a | 5293 | (define_expand "cstore<mode>4" |
9a91a21f | 5294 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
5295 | (match_operator:SI 1 "s390_scond_operator" |
5296 | [(match_operand:GPR 2 "register_operand" "") | |
5297 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 5298 | "TARGET_CPU_ZARCH" |
f90b7a5a | 5299 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
5300 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
5301 | ||
f90b7a5a | 5302 | (define_expand "cstorecc4" |
69950452 | 5303 | [(parallel |
f90b7a5a PB |
5304 | [(set (match_operand:SI 0 "register_operand" "") |
5305 | (match_operator:SI 1 "s390_eqne_operator" | |
5306 | [(match_operand:CCZ1 2 "register_operand") | |
5307 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
5308 | (clobber (reg:CC CC_REGNUM))])] |
5309 | "" | |
f90b7a5a PB |
5310 | "emit_insn (gen_sne (operands[0], operands[2])); |
5311 | if (GET_CODE (operands[1]) == EQ) | |
5312 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
5313 | DONE;") | |
69950452 | 5314 | |
f90b7a5a | 5315 | (define_insn_and_split "sne" |
69950452 | 5316 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 5317 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
5318 | (const_int 0))) |
5319 | (clobber (reg:CC CC_REGNUM))] | |
5320 | "" | |
5321 | "#" | |
5322 | "reload_completed" | |
5323 | [(parallel | |
5324 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
5325 | (clobber (reg:CC CC_REGNUM))])]) | |
5326 | ||
e69166de | 5327 | |
65b1d8ea AK |
5328 | ;; |
5329 | ;; - Conditional move instructions (introduced with z196) | |
5330 | ;; | |
5331 | ||
5332 | (define_expand "mov<mode>cc" | |
5333 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
5334 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
5335 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
5336 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
5337 | "TARGET_Z196" | |
5338 | "operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
5339 | XEXP (operands[1], 0), XEXP (operands[1], 1));") | |
5340 | ||
5341 | ; locr, loc, stoc, locgr, lgoc, stgoc | |
5342 | (define_insn_and_split "*mov<mode>cc" | |
5343 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
5344 | (if_then_else:GPR | |
5345 | (match_operator 1 "s390_comparison" | |
5346 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5347 | (const_int 0)]) | |
5348 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") | |
5349 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
5350 | "TARGET_Z196" | |
5351 | "@ | |
5352 | loc<g>r%C1\t%0,%3 | |
5353 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
5354 | loc<g>%C1\t%0,%3 |
5355 | loc<g>%D1\t%0,%4 | |
5356 | stoc<g>%C1\t%3,%0 | |
5357 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
5358 | #" |
5359 | "&& reload_completed | |
5360 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
5361 | [(set (match_dup 0) | |
5362 | (if_then_else:GPR | |
5363 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5364 | (match_dup 3) | |
5365 | (match_dup 0))) | |
5366 | (set (match_dup 0) | |
5367 | (if_then_else:GPR | |
5368 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5369 | (match_dup 0) | |
5370 | (match_dup 4)))] | |
5371 | "" | |
5372 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
5373 | ||
9db1d521 HP |
5374 | ;; |
5375 | ;;- Multiply instructions. | |
5376 | ;; | |
5377 | ||
4023fb28 UW |
5378 | ; |
5379 | ; muldi3 instruction pattern(s). | |
5380 | ; | |
9db1d521 | 5381 | |
07893d4f UW |
5382 | (define_insn "*muldi3_sign" |
5383 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 5384 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5385 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 5386 | "TARGET_ZARCH" |
07893d4f | 5387 | "@ |
d40c829f UW |
5388 | msgfr\t%0,%2 |
5389 | msgf\t%0,%2" | |
963fc8d0 AK |
5390 | [(set_attr "op_type" "RRE,RXY") |
5391 | (set_attr "type" "imuldi")]) | |
07893d4f | 5392 | |
4023fb28 | 5393 | (define_insn "muldi3" |
963fc8d0 AK |
5394 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
5395 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5396 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 5397 | "TARGET_ZARCH" |
9db1d521 | 5398 | "@ |
d40c829f UW |
5399 | msgr\t%0,%2 |
5400 | mghi\t%0,%h2 | |
963fc8d0 AK |
5401 | msg\t%0,%2 |
5402 | msgfi\t%0,%2" | |
5403 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
5404 | (set_attr "type" "imuldi") | |
5405 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 5406 | |
9db1d521 HP |
5407 | ; |
5408 | ; mulsi3 instruction pattern(s). | |
5409 | ; | |
5410 | ||
f1e77d83 | 5411 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
5412 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
5413 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5414 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 5415 | "" |
963fc8d0 AK |
5416 | "@ |
5417 | mh\t%0,%2 | |
5418 | mhy\t%0,%2" | |
5419 | [(set_attr "op_type" "RX,RXY") | |
5420 | (set_attr "type" "imulhi") | |
5421 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 5422 | |
9db1d521 | 5423 | (define_insn "mulsi3" |
963fc8d0 AK |
5424 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
5425 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5426 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
5427 | "" |
5428 | "@ | |
d40c829f UW |
5429 | msr\t%0,%2 |
5430 | mhi\t%0,%h2 | |
5431 | ms\t%0,%2 | |
963fc8d0 AK |
5432 | msy\t%0,%2 |
5433 | msfi\t%0,%2" | |
5434 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
5435 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
5436 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 5437 | |
4023fb28 UW |
5438 | ; |
5439 | ; mulsidi3 instruction pattern(s). | |
5440 | ; | |
5441 | ||
f1e77d83 | 5442 | (define_insn "mulsidi3" |
963fc8d0 | 5443 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 5444 | (mult:DI (sign_extend:DI |
963fc8d0 | 5445 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 5446 | (sign_extend:DI |
963fc8d0 | 5447 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 5448 | "!TARGET_ZARCH" |
f1e77d83 UW |
5449 | "@ |
5450 | mr\t%0,%2 | |
963fc8d0 AK |
5451 | m\t%0,%2 |
5452 | mfy\t%0,%2" | |
5453 | [(set_attr "op_type" "RR,RX,RXY") | |
5454 | (set_attr "type" "imulsi") | |
5455 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 5456 | |
f1e77d83 UW |
5457 | ; |
5458 | ; umulsidi3 instruction pattern(s). | |
5459 | ; | |
c7453384 | 5460 | |
f1e77d83 UW |
5461 | (define_insn "umulsidi3" |
5462 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5463 | (mult:DI (zero_extend:DI | |
5464 | (match_operand:SI 1 "register_operand" "%0,0")) | |
5465 | (zero_extend:DI | |
fb492564 | 5466 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))] |
9602b6a1 | 5467 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5468 | "@ |
5469 | mlr\t%0,%2 | |
5470 | ml\t%0,%2" | |
5471 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 5472 | (set_attr "type" "imulsi")]) |
c7453384 | 5473 | |
9db1d521 | 5474 | ; |
609e7e80 | 5475 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5476 | ; |
5477 | ||
9381e3f1 | 5478 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 5479 | (define_insn "mul<mode>3" |
609e7e80 AK |
5480 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5481 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
5482 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5483 | "TARGET_HARD_FLOAT" |
9db1d521 | 5484 | "@ |
609e7e80 | 5485 | m<xdee><bt>r\t%0,<op1>%2 |
f61a2c7d | 5486 | m<xdee>b\t%0,%2" |
609e7e80 | 5487 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5488 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 5489 | |
9381e3f1 | 5490 | ; madbr, maebr, maxb, madb, maeb |
f5905b37 | 5491 | (define_insn "*fmadd<mode>" |
f61a2c7d | 5492 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
b09062ee AK |
5493 | (plus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5494 | (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
f61a2c7d | 5495 | (match_operand:DSF 3 "register_operand" "0,0")))] |
142cd70f | 5496 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 5497 | "@ |
f61a2c7d AK |
5498 | ma<xde>br\t%0,%1,%2 |
5499 | ma<xde>b\t%0,%1,%2" | |
a1b892b5 | 5500 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5501 | (set_attr "type" "fmadd<mode>")]) |
a1b892b5 | 5502 | |
43a09b63 | 5503 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
f5905b37 | 5504 | (define_insn "*fmsub<mode>" |
f61a2c7d | 5505 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
b09062ee AK |
5506 | (minus:DSF (mult:DSF (match_operand:DSF 1 "nonimmediate_operand" "f,f") |
5507 | (match_operand:DSF 2 "nonimmediate_operand" "f,R")) | |
f61a2c7d | 5508 | (match_operand:DSF 3 "register_operand" "0,0")))] |
142cd70f | 5509 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 5510 | "@ |
f61a2c7d AK |
5511 | ms<xde>br\t%0,%1,%2 |
5512 | ms<xde>b\t%0,%1,%2" | |
ce50cae8 | 5513 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5514 | (set_attr "type" "fmadd<mode>")]) |
9db1d521 HP |
5515 | |
5516 | ;; | |
5517 | ;;- Divide and modulo instructions. | |
5518 | ;; | |
5519 | ||
5520 | ; | |
4023fb28 | 5521 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
5522 | ; |
5523 | ||
4023fb28 UW |
5524 | (define_expand "divmoddi4" |
5525 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 5526 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
5527 | (match_operand:DI 2 "general_operand" ""))) |
5528 | (set (match_operand:DI 3 "general_operand" "") | |
5529 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
5530 | (clobber (match_dup 4))] | |
9602b6a1 | 5531 | "TARGET_ZARCH" |
9db1d521 | 5532 | { |
f1e77d83 | 5533 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
5534 | |
5535 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
5536 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
5537 | |
5538 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 5539 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
5540 | |
5541 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5542 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5543 | |
5544 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5545 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5546 | |
9db1d521 | 5547 | DONE; |
10bbf137 | 5548 | }) |
9db1d521 HP |
5549 | |
5550 | (define_insn "divmodtidi3" | |
4023fb28 UW |
5551 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
5552 | (ior:TI | |
4023fb28 UW |
5553 | (ashift:TI |
5554 | (zero_extend:TI | |
5665e398 | 5555 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5556 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
5557 | (const_int 64)) |
5558 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 5559 | "TARGET_ZARCH" |
9db1d521 | 5560 | "@ |
d40c829f UW |
5561 | dsgr\t%0,%2 |
5562 | dsg\t%0,%2" | |
d3632d41 | 5563 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5564 | (set_attr "type" "idiv")]) |
9db1d521 | 5565 | |
4023fb28 UW |
5566 | (define_insn "divmodtisi3" |
5567 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5568 | (ior:TI | |
4023fb28 UW |
5569 | (ashift:TI |
5570 | (zero_extend:TI | |
5665e398 | 5571 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 5572 | (sign_extend:DI |
fb492564 | 5573 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
5574 | (const_int 64)) |
5575 | (zero_extend:TI | |
5576 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 5577 | "TARGET_ZARCH" |
4023fb28 | 5578 | "@ |
d40c829f UW |
5579 | dsgfr\t%0,%2 |
5580 | dsgf\t%0,%2" | |
d3632d41 | 5581 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5582 | (set_attr "type" "idiv")]) |
9db1d521 | 5583 | |
4023fb28 UW |
5584 | ; |
5585 | ; udivmoddi4 instruction pattern(s). | |
5586 | ; | |
9db1d521 | 5587 | |
4023fb28 UW |
5588 | (define_expand "udivmoddi4" |
5589 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5590 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
5591 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
5592 | (set (match_operand:DI 3 "general_operand" "") | |
5593 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
5594 | (clobber (match_dup 4))] | |
9602b6a1 | 5595 | "TARGET_ZARCH" |
9db1d521 | 5596 | { |
4023fb28 UW |
5597 | rtx insn, div_equal, mod_equal, equal; |
5598 | ||
5599 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
5600 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
5601 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
5602 | gen_rtx_ASHIFT (TImode, |
5603 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
5604 | GEN_INT (64)), |
5605 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
5606 | |
5607 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 5608 | emit_clobber (operands[4]); |
4023fb28 UW |
5609 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
5610 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 5611 | |
4023fb28 | 5612 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5613 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5614 | |
5615 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5616 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5617 | |
5618 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5619 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5620 | |
9db1d521 | 5621 | DONE; |
10bbf137 | 5622 | }) |
9db1d521 HP |
5623 | |
5624 | (define_insn "udivmodtidi3" | |
4023fb28 | 5625 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 5626 | (ior:TI |
5665e398 UW |
5627 | (ashift:TI |
5628 | (zero_extend:TI | |
5629 | (truncate:DI | |
2f7e5a0d EC |
5630 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
5631 | (zero_extend:TI | |
fb492564 | 5632 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5633 | (const_int 64)) |
5634 | (zero_extend:TI | |
5635 | (truncate:DI | |
5636 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 5637 | "TARGET_ZARCH" |
9db1d521 | 5638 | "@ |
d40c829f UW |
5639 | dlgr\t%0,%2 |
5640 | dlg\t%0,%2" | |
d3632d41 | 5641 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5642 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5643 | |
5644 | ; | |
4023fb28 | 5645 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
5646 | ; |
5647 | ||
4023fb28 UW |
5648 | (define_expand "divmodsi4" |
5649 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5650 | (div:SI (match_operand:SI 1 "general_operand" "") | |
5651 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5652 | (set (match_operand:SI 3 "general_operand" "") | |
5653 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
5654 | (clobber (match_dup 4))] | |
9602b6a1 | 5655 | "!TARGET_ZARCH" |
9db1d521 | 5656 | { |
4023fb28 UW |
5657 | rtx insn, div_equal, mod_equal, equal; |
5658 | ||
5659 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
5660 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
5661 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5662 | gen_rtx_ASHIFT (DImode, |
5663 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5664 | GEN_INT (32)), |
5665 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
5666 | |
5667 | operands[4] = gen_reg_rtx(DImode); | |
5668 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 5669 | |
4023fb28 | 5670 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5671 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5672 | |
5673 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5674 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5675 | |
5676 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5677 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5678 | |
9db1d521 | 5679 | DONE; |
10bbf137 | 5680 | }) |
9db1d521 HP |
5681 | |
5682 | (define_insn "divmoddisi3" | |
4023fb28 | 5683 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 5684 | (ior:DI |
5665e398 UW |
5685 | (ashift:DI |
5686 | (zero_extend:DI | |
5687 | (truncate:SI | |
2f7e5a0d EC |
5688 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
5689 | (sign_extend:DI | |
5665e398 UW |
5690 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
5691 | (const_int 32)) | |
5692 | (zero_extend:DI | |
5693 | (truncate:SI | |
5694 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5695 | "!TARGET_ZARCH" |
9db1d521 | 5696 | "@ |
d40c829f UW |
5697 | dr\t%0,%2 |
5698 | d\t%0,%2" | |
9db1d521 | 5699 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5700 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5701 | |
5702 | ; | |
5703 | ; udivsi3 and umodsi3 instruction pattern(s). | |
5704 | ; | |
5705 | ||
f1e77d83 UW |
5706 | (define_expand "udivmodsi4" |
5707 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5708 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5709 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5710 | (set (match_operand:SI 3 "general_operand" "") | |
5711 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
5712 | (clobber (match_dup 4))] | |
9602b6a1 | 5713 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5714 | { |
5715 | rtx insn, div_equal, mod_equal, equal; | |
5716 | ||
5717 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5718 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5719 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
5720 | gen_rtx_ASHIFT (DImode, |
5721 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5722 | GEN_INT (32)), |
5723 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
5724 | |
5725 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 5726 | emit_clobber (operands[4]); |
f1e77d83 UW |
5727 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
5728 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 5729 | |
f1e77d83 | 5730 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5731 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
5732 | |
5733 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5734 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
5735 | |
5736 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5737 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
5738 | |
5739 | DONE; | |
5740 | }) | |
5741 | ||
5742 | (define_insn "udivmoddisi3" | |
5743 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 5744 | (ior:DI |
5665e398 UW |
5745 | (ashift:DI |
5746 | (zero_extend:DI | |
5747 | (truncate:SI | |
2f7e5a0d EC |
5748 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
5749 | (zero_extend:DI | |
fb492564 | 5750 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5751 | (const_int 32)) |
5752 | (zero_extend:DI | |
5753 | (truncate:SI | |
5754 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5755 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5756 | "@ |
5757 | dlr\t%0,%2 | |
5758 | dl\t%0,%2" | |
5759 | [(set_attr "op_type" "RRE,RXY") | |
5760 | (set_attr "type" "idiv")]) | |
4023fb28 | 5761 | |
9db1d521 HP |
5762 | (define_expand "udivsi3" |
5763 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5764 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
5765 | (match_operand:SI 2 "general_operand" ""))) |
5766 | (clobber (match_dup 3))] | |
9602b6a1 | 5767 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 5768 | { |
4023fb28 UW |
5769 | rtx insn, udiv_equal, umod_equal, equal; |
5770 | ||
5771 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5772 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5773 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5774 | gen_rtx_ASHIFT (DImode, |
5775 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5776 | GEN_INT (32)), |
5777 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5778 | |
4023fb28 | 5779 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5780 | |
5781 | if (CONSTANT_P (operands[2])) | |
5782 | { | |
5783 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
5784 | { | |
5785 | rtx label1 = gen_label_rtx (); | |
5786 | ||
4023fb28 UW |
5787 | operands[1] = make_safe_from (operands[1], operands[0]); |
5788 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5789 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
5790 | SImode, 1, label1); | |
4023fb28 | 5791 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5792 | emit_label (label1); |
5793 | } | |
5794 | else | |
5795 | { | |
c7453384 EC |
5796 | operands[2] = force_reg (SImode, operands[2]); |
5797 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5798 | |
5799 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5800 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5801 | operands[2])); | |
bd94cb6e | 5802 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5803 | |
5804 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5805 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 5806 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
5807 | } |
5808 | } | |
5809 | else | |
c7453384 | 5810 | { |
9db1d521 HP |
5811 | rtx label1 = gen_label_rtx (); |
5812 | rtx label2 = gen_label_rtx (); | |
5813 | rtx label3 = gen_label_rtx (); | |
5814 | ||
c7453384 EC |
5815 | operands[1] = force_reg (SImode, operands[1]); |
5816 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5817 | operands[2] = force_reg (SImode, operands[2]); | |
5818 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5819 | |
5820 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
5821 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
5822 | SImode, 1, label3); | |
5823 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
5824 | SImode, 0, label2); | |
5825 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
5826 | SImode, 0, label1); | |
4023fb28 UW |
5827 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5828 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5829 | operands[2])); | |
bd94cb6e | 5830 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5831 | |
5832 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5833 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
5834 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
5835 | ||
f314b9b1 | 5836 | emit_jump (label3); |
9db1d521 | 5837 | emit_label (label1); |
4023fb28 | 5838 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 5839 | emit_jump (label3); |
9db1d521 | 5840 | emit_label (label2); |
4023fb28 | 5841 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5842 | emit_label (label3); |
5843 | } | |
c7453384 | 5844 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 5845 | DONE; |
10bbf137 | 5846 | }) |
9db1d521 HP |
5847 | |
5848 | (define_expand "umodsi3" | |
5849 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5850 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
5851 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
5852 | (clobber (match_dup 3))] | |
9602b6a1 | 5853 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 5854 | { |
4023fb28 UW |
5855 | rtx insn, udiv_equal, umod_equal, equal; |
5856 | ||
5857 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5858 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5859 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5860 | gen_rtx_ASHIFT (DImode, |
5861 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5862 | GEN_INT (32)), |
5863 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5864 | |
4023fb28 | 5865 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5866 | |
5867 | if (CONSTANT_P (operands[2])) | |
5868 | { | |
5869 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
5870 | { | |
5871 | rtx label1 = gen_label_rtx (); | |
5872 | ||
4023fb28 UW |
5873 | operands[1] = make_safe_from (operands[1], operands[0]); |
5874 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
5875 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
5876 | SImode, 1, label1); | |
4023fb28 UW |
5877 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
5878 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
5879 | emit_label (label1); |
5880 | } | |
5881 | else | |
5882 | { | |
c7453384 EC |
5883 | operands[2] = force_reg (SImode, operands[2]); |
5884 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5885 | |
5886 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5887 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5888 | operands[2])); | |
bd94cb6e | 5889 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5890 | |
5891 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5892 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 5893 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
5894 | } |
5895 | } | |
5896 | else | |
5897 | { | |
5898 | rtx label1 = gen_label_rtx (); | |
5899 | rtx label2 = gen_label_rtx (); | |
5900 | rtx label3 = gen_label_rtx (); | |
5901 | ||
c7453384 EC |
5902 | operands[1] = force_reg (SImode, operands[1]); |
5903 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5904 | operands[2] = force_reg (SImode, operands[2]); | |
5905 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5906 | |
c7453384 | 5907 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
5908 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
5909 | SImode, 1, label3); | |
5910 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
5911 | SImode, 0, label2); | |
5912 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
5913 | SImode, 0, label1); | |
4023fb28 UW |
5914 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5915 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5916 | operands[2])); | |
bd94cb6e | 5917 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
5918 | |
5919 | insn = emit_move_insn (operands[0], | |
4023fb28 | 5920 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
5921 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
5922 | ||
f314b9b1 | 5923 | emit_jump (label3); |
9db1d521 | 5924 | emit_label (label1); |
4023fb28 | 5925 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5926 | emit_jump (label3); |
9db1d521 | 5927 | emit_label (label2); |
4023fb28 | 5928 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5929 | emit_label (label3); |
5930 | } | |
9db1d521 | 5931 | DONE; |
10bbf137 | 5932 | }) |
9db1d521 HP |
5933 | |
5934 | ; | |
f5905b37 | 5935 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
5936 | ; |
5937 | ||
609e7e80 | 5938 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 5939 | (define_insn "div<mode>3" |
609e7e80 AK |
5940 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5941 | (div:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
5942 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5943 | "TARGET_HARD_FLOAT" |
9db1d521 | 5944 | "@ |
609e7e80 | 5945 | d<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5946 | d<xde>b\t%0,%2" |
609e7e80 | 5947 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5948 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 5949 | |
9db1d521 HP |
5950 | |
5951 | ;; | |
5952 | ;;- And instructions. | |
5953 | ;; | |
5954 | ||
047d35ed AS |
5955 | (define_expand "and<mode>3" |
5956 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5957 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5958 | (match_operand:INT 2 "general_operand" ""))) | |
5959 | (clobber (reg:CC CC_REGNUM))] | |
5960 | "" | |
5961 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
5962 | ||
9db1d521 HP |
5963 | ; |
5964 | ; anddi3 instruction pattern(s). | |
5965 | ; | |
5966 | ||
5967 | (define_insn "*anddi3_cc" | |
ae156f85 | 5968 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5969 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
5970 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
9db1d521 | 5971 | (const_int 0))) |
65b1d8ea | 5972 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
9db1d521 | 5973 | (and:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 5974 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
9db1d521 | 5975 | "@ |
d40c829f | 5976 | ngr\t%0,%2 |
65b1d8ea | 5977 | ngrk\t%0,%1,%2 |
d40c829f | 5978 | ng\t%0,%2" |
65b1d8ea AK |
5979 | [(set_attr "op_type" "RRE,RRF,RXY") |
5980 | (set_attr "cpu_facility" "*,z196,*") | |
5981 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
9db1d521 HP |
5982 | |
5983 | (define_insn "*anddi3_cconly" | |
ae156f85 | 5984 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5985 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
5986 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
9db1d521 | 5987 | (const_int 0))) |
65b1d8ea | 5988 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 5989 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH |
68f9c5e2 UW |
5990 | /* Do not steal TM patterns. */ |
5991 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 5992 | "@ |
d40c829f | 5993 | ngr\t%0,%2 |
65b1d8ea | 5994 | ngrk\t%0,%1,%2 |
d40c829f | 5995 | ng\t%0,%2" |
65b1d8ea AK |
5996 | [(set_attr "op_type" "RRE,RRF,RXY") |
5997 | (set_attr "cpu_facility" "*,z196,*") | |
5998 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
9db1d521 | 5999 | |
3af8e996 | 6000 | (define_insn "*anddi3" |
65b1d8ea AK |
6001 | [(set (match_operand:DI 0 "nonimmediate_operand" |
6002 | "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q") | |
ec24698e | 6003 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
65b1d8ea | 6004 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0") |
ec24698e | 6005 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 6006 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q"))) |
ec24698e | 6007 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6008 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6009 | "@ |
6010 | # | |
6011 | # | |
6012 | nihh\t%0,%j2 | |
6013 | nihl\t%0,%j2 | |
6014 | nilh\t%0,%j2 | |
6015 | nill\t%0,%j2 | |
6016 | nihf\t%0,%m2 | |
6017 | nilf\t%0,%m2 | |
6018 | ngr\t%0,%2 | |
65b1d8ea | 6019 | ngrk\t%0,%1,%2 |
ec24698e UW |
6020 | ng\t%0,%2 |
6021 | # | |
6022 | #" | |
65b1d8ea AK |
6023 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
6024 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
6025 | (set_attr "z10prop" "*, |
6026 | *, | |
6027 | z10_super_E1, | |
6028 | z10_super_E1, | |
6029 | z10_super_E1, | |
6030 | z10_super_E1, | |
6031 | z10_super_E1, | |
6032 | z10_super_E1, | |
6033 | z10_super_E1, | |
65b1d8ea | 6034 | *, |
9381e3f1 WG |
6035 | z10_super_E1, |
6036 | *, | |
6037 | *")]) | |
0dfa6c5e UW |
6038 | |
6039 | (define_split | |
6040 | [(set (match_operand:DI 0 "s_operand" "") | |
6041 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6042 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6043 | "reload_completed" |
6044 | [(parallel | |
6045 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6046 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6047 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6048 | |
9db1d521 HP |
6049 | |
6050 | ; | |
6051 | ; andsi3 instruction pattern(s). | |
6052 | ; | |
6053 | ||
6054 | (define_insn "*andsi3_cc" | |
ae156f85 | 6055 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6056 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6057 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
9db1d521 | 6058 | (const_int 0))) |
65b1d8ea | 6059 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
9db1d521 HP |
6060 | (and:SI (match_dup 1) (match_dup 2)))] |
6061 | "s390_match_ccmode(insn, CCTmode)" | |
6062 | "@ | |
ec24698e | 6063 | nilf\t%0,%o2 |
d40c829f | 6064 | nr\t%0,%2 |
65b1d8ea | 6065 | nrk\t%0,%1,%2 |
d40c829f UW |
6066 | n\t%0,%2 |
6067 | ny\t%0,%2" | |
65b1d8ea AK |
6068 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6069 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6070 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6071 | |
6072 | (define_insn "*andsi3_cconly" | |
ae156f85 | 6073 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6074 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6075 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
9db1d521 | 6076 | (const_int 0))) |
65b1d8ea | 6077 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
68f9c5e2 UW |
6078 | "s390_match_ccmode(insn, CCTmode) |
6079 | /* Do not steal TM patterns. */ | |
6080 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 6081 | "@ |
ec24698e | 6082 | nilf\t%0,%o2 |
d40c829f | 6083 | nr\t%0,%2 |
65b1d8ea | 6084 | nrk\t%0,%1,%2 |
d40c829f UW |
6085 | n\t%0,%2 |
6086 | ny\t%0,%2" | |
65b1d8ea AK |
6087 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6088 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6089 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6090 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6091 | |
f19a9af7 | 6092 | (define_insn "*andsi3_zarch" |
65b1d8ea AK |
6093 | [(set (match_operand:SI 0 "nonimmediate_operand" |
6094 | "=d,d, d, d, d,d,d,d,d, AQ,Q") | |
0dfa6c5e | 6095 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
65b1d8ea | 6096 | "%d,o, 0, 0, 0,0,d,0,0, 0,0") |
0dfa6c5e | 6097 | (match_operand:SI 2 "general_operand" |
65b1d8ea | 6098 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q"))) |
ae156f85 | 6099 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6100 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6101 | "@ |
f19a9af7 AK |
6102 | # |
6103 | # | |
6104 | nilh\t%0,%j2 | |
2f7e5a0d | 6105 | nill\t%0,%j2 |
ec24698e | 6106 | nilf\t%0,%o2 |
d40c829f | 6107 | nr\t%0,%2 |
65b1d8ea | 6108 | nrk\t%0,%1,%2 |
d40c829f | 6109 | n\t%0,%2 |
8cb66696 | 6110 | ny\t%0,%2 |
0dfa6c5e | 6111 | # |
19b63d8e | 6112 | #" |
65b1d8ea AK |
6113 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
6114 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
6115 | (set_attr "z10prop" "*, |
6116 | *, | |
6117 | z10_super_E1, | |
6118 | z10_super_E1, | |
6119 | z10_super_E1, | |
6120 | z10_super_E1, | |
65b1d8ea | 6121 | *, |
9381e3f1 WG |
6122 | z10_super_E1, |
6123 | z10_super_E1, | |
6124 | *, | |
6125 | *")]) | |
f19a9af7 AK |
6126 | |
6127 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
6128 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
6129 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
6130 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 6131 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6132 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6133 | "@ |
6134 | nr\t%0,%2 | |
8cb66696 | 6135 | n\t%0,%2 |
0dfa6c5e | 6136 | # |
19b63d8e | 6137 | #" |
9381e3f1 WG |
6138 | [(set_attr "op_type" "RR,RX,SI,SS") |
6139 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6140 | ||
0dfa6c5e UW |
6141 | |
6142 | (define_split | |
6143 | [(set (match_operand:SI 0 "s_operand" "") | |
6144 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6145 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6146 | "reload_completed" |
6147 | [(parallel | |
6148 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6149 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6150 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6151 | |
9db1d521 HP |
6152 | ; |
6153 | ; andhi3 instruction pattern(s). | |
6154 | ; | |
6155 | ||
8cb66696 | 6156 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
6157 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6158 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6159 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 6160 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6161 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6162 | "@ |
d40c829f | 6163 | nr\t%0,%2 |
65b1d8ea | 6164 | nrk\t%0,%1,%2 |
8cb66696 | 6165 | nill\t%0,%x2 |
0dfa6c5e | 6166 | # |
19b63d8e | 6167 | #" |
65b1d8ea AK |
6168 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6169 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6170 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 6171 | ]) |
8cb66696 UW |
6172 | |
6173 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
6174 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6175 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6176 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 6177 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6178 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6179 | "@ | |
6180 | nr\t%0,%2 | |
0dfa6c5e | 6181 | # |
19b63d8e | 6182 | #" |
9381e3f1 WG |
6183 | [(set_attr "op_type" "RR,SI,SS") |
6184 | (set_attr "z10prop" "z10_super_E1,*,*") | |
6185 | ]) | |
0dfa6c5e UW |
6186 | |
6187 | (define_split | |
6188 | [(set (match_operand:HI 0 "s_operand" "") | |
6189 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6190 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6191 | "reload_completed" |
6192 | [(parallel | |
6193 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6194 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6195 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 6196 | |
9db1d521 HP |
6197 | ; |
6198 | ; andqi3 instruction pattern(s). | |
6199 | ; | |
6200 | ||
8cb66696 | 6201 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
6202 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6203 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6204 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6205 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6206 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6207 | "@ |
d40c829f | 6208 | nr\t%0,%2 |
65b1d8ea | 6209 | nrk\t%0,%1,%2 |
8cb66696 | 6210 | nill\t%0,%b2 |
fc0ea003 UW |
6211 | ni\t%S0,%b2 |
6212 | niy\t%S0,%b2 | |
19b63d8e | 6213 | #" |
65b1d8ea AK |
6214 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6215 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6216 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
6217 | |
6218 | (define_insn "*andqi3_esa" | |
6219 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6220 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6221 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6222 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6223 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6224 | "@ |
8cb66696 | 6225 | nr\t%0,%2 |
fc0ea003 | 6226 | ni\t%S0,%b2 |
19b63d8e | 6227 | #" |
9381e3f1 WG |
6228 | [(set_attr "op_type" "RR,SI,SS") |
6229 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 6230 | |
19b63d8e UW |
6231 | ; |
6232 | ; Block and (NC) patterns. | |
6233 | ; | |
6234 | ||
6235 | (define_insn "*nc" | |
6236 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6237 | (and:BLK (match_dup 0) | |
6238 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6239 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6240 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6241 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6242 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6243 | [(set_attr "op_type" "SS") |
6244 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6245 | |
6246 | (define_split | |
6247 | [(set (match_operand 0 "memory_operand" "") | |
6248 | (and (match_dup 0) | |
6249 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6250 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6251 | "reload_completed |
6252 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6253 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6254 | [(parallel | |
6255 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
6256 | (use (match_dup 2)) | |
ae156f85 | 6257 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6258 | { |
6259 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6260 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6261 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6262 | }) | |
6263 | ||
6264 | (define_peephole2 | |
6265 | [(parallel | |
6266 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6267 | (and:BLK (match_dup 0) | |
6268 | (match_operand:BLK 1 "memory_operand" ""))) | |
6269 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6270 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6271 | (parallel |
6272 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6273 | (and:BLK (match_dup 3) | |
6274 | (match_operand:BLK 4 "memory_operand" ""))) | |
6275 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6276 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6277 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6278 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6279 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6280 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6281 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6282 | [(parallel | |
6283 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
6284 | (use (match_dup 8)) | |
ae156f85 | 6285 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6286 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6287 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6288 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6289 | ||
9db1d521 HP |
6290 | |
6291 | ;; | |
6292 | ;;- Bit set (inclusive or) instructions. | |
6293 | ;; | |
6294 | ||
047d35ed AS |
6295 | (define_expand "ior<mode>3" |
6296 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6297 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6298 | (match_operand:INT 2 "general_operand" ""))) | |
6299 | (clobber (reg:CC CC_REGNUM))] | |
6300 | "" | |
6301 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
6302 | ||
9db1d521 HP |
6303 | ; |
6304 | ; iordi3 instruction pattern(s). | |
6305 | ; | |
6306 | ||
4023fb28 | 6307 | (define_insn "*iordi3_cc" |
ae156f85 | 6308 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6309 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6310 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6311 | (const_int 0))) |
65b1d8ea | 6312 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6313 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6314 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6315 | "@ |
d40c829f | 6316 | ogr\t%0,%2 |
65b1d8ea | 6317 | ogrk\t%0,%1,%2 |
d40c829f | 6318 | og\t%0,%2" |
65b1d8ea AK |
6319 | [(set_attr "op_type" "RRE,RRF,RXY") |
6320 | (set_attr "cpu_facility" "*,z196,*") | |
6321 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
6322 | |
6323 | (define_insn "*iordi3_cconly" | |
ae156f85 | 6324 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6325 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
6326 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6327 | (const_int 0))) |
65b1d8ea | 6328 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 6329 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6330 | "@ |
d40c829f | 6331 | ogr\t%0,%2 |
65b1d8ea | 6332 | ogrk\t%0,%1,%2 |
d40c829f | 6333 | og\t%0,%2" |
65b1d8ea AK |
6334 | [(set_attr "op_type" "RRE,RRF,RXY") |
6335 | (set_attr "cpu_facility" "*,z196,*") | |
6336 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6337 | |
3af8e996 | 6338 | (define_insn "*iordi3" |
65b1d8ea AK |
6339 | [(set (match_operand:DI 0 "nonimmediate_operand" |
6340 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
6341 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
6342 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 6343 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 6344 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 6345 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6346 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6347 | "@ |
6348 | oihh\t%0,%i2 | |
6349 | oihl\t%0,%i2 | |
6350 | oilh\t%0,%i2 | |
6351 | oill\t%0,%i2 | |
6352 | oihf\t%0,%k2 | |
6353 | oilf\t%0,%k2 | |
6354 | ogr\t%0,%2 | |
65b1d8ea | 6355 | ogrk\t%0,%1,%2 |
ec24698e UW |
6356 | og\t%0,%2 |
6357 | # | |
6358 | #" | |
65b1d8ea AK |
6359 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
6360 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
6361 | (set_attr "z10prop" "z10_super_E1, |
6362 | z10_super_E1, | |
6363 | z10_super_E1, | |
6364 | z10_super_E1, | |
6365 | z10_super_E1, | |
6366 | z10_super_E1, | |
6367 | z10_super_E1, | |
65b1d8ea | 6368 | *, |
9381e3f1 WG |
6369 | z10_super_E1, |
6370 | *, | |
6371 | *")]) | |
0dfa6c5e UW |
6372 | |
6373 | (define_split | |
6374 | [(set (match_operand:DI 0 "s_operand" "") | |
6375 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6376 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6377 | "reload_completed" |
6378 | [(parallel | |
6379 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6380 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6381 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6382 | |
9db1d521 HP |
6383 | ; |
6384 | ; iorsi3 instruction pattern(s). | |
6385 | ; | |
6386 | ||
4023fb28 | 6387 | (define_insn "*iorsi3_cc" |
ae156f85 | 6388 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6389 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6390 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6391 | (const_int 0))) |
65b1d8ea | 6392 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6393 | (ior:SI (match_dup 1) (match_dup 2)))] |
6394 | "s390_match_ccmode(insn, CCTmode)" | |
6395 | "@ | |
ec24698e | 6396 | oilf\t%0,%o2 |
d40c829f | 6397 | or\t%0,%2 |
65b1d8ea | 6398 | ork\t%0,%1,%2 |
d40c829f UW |
6399 | o\t%0,%2 |
6400 | oy\t%0,%2" | |
65b1d8ea AK |
6401 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6402 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6403 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6404 | |
6405 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 6406 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6407 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6408 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6409 | (const_int 0))) |
65b1d8ea | 6410 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6411 | "s390_match_ccmode(insn, CCTmode)" |
6412 | "@ | |
ec24698e | 6413 | oilf\t%0,%o2 |
d40c829f | 6414 | or\t%0,%2 |
65b1d8ea | 6415 | ork\t%0,%1,%2 |
d40c829f UW |
6416 | o\t%0,%2 |
6417 | oy\t%0,%2" | |
65b1d8ea AK |
6418 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6419 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6420 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6421 | |
8cb66696 | 6422 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
6423 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
6424 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
6425 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6426 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6427 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6428 | "@ |
f19a9af7 AK |
6429 | oilh\t%0,%i2 |
6430 | oill\t%0,%i2 | |
ec24698e | 6431 | oilf\t%0,%o2 |
d40c829f | 6432 | or\t%0,%2 |
65b1d8ea | 6433 | ork\t%0,%1,%2 |
d40c829f | 6434 | o\t%0,%2 |
8cb66696 | 6435 | oy\t%0,%2 |
0dfa6c5e | 6436 | # |
19b63d8e | 6437 | #" |
65b1d8ea AK |
6438 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
6439 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
6440 | (set_attr "z10prop" "z10_super_E1, |
6441 | z10_super_E1, | |
6442 | z10_super_E1, | |
6443 | z10_super_E1, | |
65b1d8ea | 6444 | *, |
9381e3f1 WG |
6445 | z10_super_E1, |
6446 | z10_super_E1, | |
6447 | *, | |
6448 | *")]) | |
8cb66696 UW |
6449 | |
6450 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 6451 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 6452 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 6453 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 6454 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6455 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6456 | "@ |
6457 | or\t%0,%2 | |
8cb66696 | 6458 | o\t%0,%2 |
0dfa6c5e | 6459 | # |
19b63d8e | 6460 | #" |
9381e3f1 WG |
6461 | [(set_attr "op_type" "RR,RX,SI,SS") |
6462 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6463 | |
6464 | (define_split | |
6465 | [(set (match_operand:SI 0 "s_operand" "") | |
6466 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6467 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6468 | "reload_completed" |
6469 | [(parallel | |
6470 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6471 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6472 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6473 | |
4023fb28 UW |
6474 | ; |
6475 | ; iorhi3 instruction pattern(s). | |
6476 | ; | |
6477 | ||
8cb66696 | 6478 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
6479 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6480 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6481 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 6482 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6483 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6484 | "@ |
d40c829f | 6485 | or\t%0,%2 |
65b1d8ea | 6486 | ork\t%0,%1,%2 |
8cb66696 | 6487 | oill\t%0,%x2 |
0dfa6c5e | 6488 | # |
19b63d8e | 6489 | #" |
65b1d8ea AK |
6490 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6491 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6492 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
6493 | |
6494 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
6495 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6496 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6497 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 6498 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6499 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6500 | "@ | |
6501 | or\t%0,%2 | |
0dfa6c5e | 6502 | # |
19b63d8e | 6503 | #" |
9381e3f1 WG |
6504 | [(set_attr "op_type" "RR,SI,SS") |
6505 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6506 | |
6507 | (define_split | |
6508 | [(set (match_operand:HI 0 "s_operand" "") | |
6509 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6510 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6511 | "reload_completed" |
6512 | [(parallel | |
6513 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6514 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6515 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 6516 | |
9db1d521 | 6517 | ; |
4023fb28 | 6518 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
6519 | ; |
6520 | ||
8cb66696 | 6521 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
6522 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6523 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6524 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6525 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6526 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6527 | "@ |
d40c829f | 6528 | or\t%0,%2 |
65b1d8ea | 6529 | ork\t%0,%1,%2 |
8cb66696 | 6530 | oill\t%0,%b2 |
fc0ea003 UW |
6531 | oi\t%S0,%b2 |
6532 | oiy\t%S0,%b2 | |
19b63d8e | 6533 | #" |
65b1d8ea AK |
6534 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6535 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6536 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
6537 | z10_super,z10_super,*")]) | |
8cb66696 UW |
6538 | |
6539 | (define_insn "*iorqi3_esa" | |
6540 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6541 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6542 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6543 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6544 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6545 | "@ |
8cb66696 | 6546 | or\t%0,%2 |
fc0ea003 | 6547 | oi\t%S0,%b2 |
19b63d8e | 6548 | #" |
9381e3f1 WG |
6549 | [(set_attr "op_type" "RR,SI,SS") |
6550 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 6551 | |
19b63d8e UW |
6552 | ; |
6553 | ; Block inclusive or (OC) patterns. | |
6554 | ; | |
6555 | ||
6556 | (define_insn "*oc" | |
6557 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6558 | (ior:BLK (match_dup 0) | |
6559 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6560 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6561 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6562 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6563 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6564 | [(set_attr "op_type" "SS") |
6565 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6566 | |
6567 | (define_split | |
6568 | [(set (match_operand 0 "memory_operand" "") | |
6569 | (ior (match_dup 0) | |
6570 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6571 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6572 | "reload_completed |
6573 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6574 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6575 | [(parallel | |
6576 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
6577 | (use (match_dup 2)) | |
ae156f85 | 6578 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6579 | { |
6580 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6581 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6582 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6583 | }) | |
6584 | ||
6585 | (define_peephole2 | |
6586 | [(parallel | |
6587 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6588 | (ior:BLK (match_dup 0) | |
6589 | (match_operand:BLK 1 "memory_operand" ""))) | |
6590 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6591 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6592 | (parallel |
6593 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6594 | (ior:BLK (match_dup 3) | |
6595 | (match_operand:BLK 4 "memory_operand" ""))) | |
6596 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6597 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6598 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6599 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6600 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6601 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6602 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6603 | [(parallel | |
6604 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
6605 | (use (match_dup 8)) | |
ae156f85 | 6606 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6607 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6608 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6609 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6610 | ||
9db1d521 HP |
6611 | |
6612 | ;; | |
6613 | ;;- Xor instructions. | |
6614 | ;; | |
6615 | ||
047d35ed AS |
6616 | (define_expand "xor<mode>3" |
6617 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6618 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6619 | (match_operand:INT 2 "general_operand" ""))) | |
6620 | (clobber (reg:CC CC_REGNUM))] | |
6621 | "" | |
6622 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
6623 | ||
9db1d521 HP |
6624 | ; |
6625 | ; xordi3 instruction pattern(s). | |
6626 | ; | |
6627 | ||
4023fb28 | 6628 | (define_insn "*xordi3_cc" |
ae156f85 | 6629 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6630 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6631 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6632 | (const_int 0))) |
65b1d8ea | 6633 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6634 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6635 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6636 | "@ |
d40c829f | 6637 | xgr\t%0,%2 |
65b1d8ea | 6638 | xgrk\t%0,%1,%2 |
d40c829f | 6639 | xg\t%0,%2" |
65b1d8ea | 6640 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 6641 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 6642 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
6643 | |
6644 | (define_insn "*xordi3_cconly" | |
ae156f85 | 6645 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6646 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6647 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6648 | (const_int 0))) |
65b1d8ea | 6649 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 6650 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6651 | "@ |
d40c829f | 6652 | xgr\t%0,%2 |
65b1d8ea | 6653 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 6654 | xg\t%0,%2" |
65b1d8ea AK |
6655 | [(set_attr "op_type" "RRE,RRF,RXY") |
6656 | (set_attr "cpu_facility" "*,z196,*") | |
6657 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6658 | |
3af8e996 | 6659 | (define_insn "*xordi3" |
65b1d8ea AK |
6660 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
6661 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
6662 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 6663 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6664 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6665 | "@ |
6666 | xihf\t%0,%k2 | |
6667 | xilf\t%0,%k2 | |
6668 | xgr\t%0,%2 | |
65b1d8ea | 6669 | xgrk\t%0,%1,%2 |
ec24698e UW |
6670 | xg\t%0,%2 |
6671 | # | |
6672 | #" | |
65b1d8ea AK |
6673 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
6674 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
6675 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
6676 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6677 | |
6678 | (define_split | |
6679 | [(set (match_operand:DI 0 "s_operand" "") | |
6680 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6681 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6682 | "reload_completed" |
6683 | [(parallel | |
6684 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6685 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6686 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 6687 | |
9db1d521 HP |
6688 | ; |
6689 | ; xorsi3 instruction pattern(s). | |
6690 | ; | |
6691 | ||
4023fb28 | 6692 | (define_insn "*xorsi3_cc" |
ae156f85 | 6693 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6694 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6695 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6696 | (const_int 0))) |
65b1d8ea | 6697 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6698 | (xor:SI (match_dup 1) (match_dup 2)))] |
6699 | "s390_match_ccmode(insn, CCTmode)" | |
6700 | "@ | |
ec24698e | 6701 | xilf\t%0,%o2 |
d40c829f | 6702 | xr\t%0,%2 |
65b1d8ea | 6703 | xrk\t%0,%1,%2 |
d40c829f UW |
6704 | x\t%0,%2 |
6705 | xy\t%0,%2" | |
65b1d8ea AK |
6706 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6707 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6708 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6709 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6710 | |
6711 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 6712 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6713 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6714 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6715 | (const_int 0))) |
65b1d8ea | 6716 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6717 | "s390_match_ccmode(insn, CCTmode)" |
6718 | "@ | |
ec24698e | 6719 | xilf\t%0,%o2 |
d40c829f | 6720 | xr\t%0,%2 |
65b1d8ea | 6721 | xrk\t%0,%1,%2 |
d40c829f UW |
6722 | x\t%0,%2 |
6723 | xy\t%0,%2" | |
65b1d8ea AK |
6724 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6725 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6726 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6727 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6728 | |
8cb66696 | 6729 | (define_insn "*xorsi3" |
65b1d8ea AK |
6730 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
6731 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
6732 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6733 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6734 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6735 | "@ |
ec24698e | 6736 | xilf\t%0,%o2 |
d40c829f | 6737 | xr\t%0,%2 |
65b1d8ea | 6738 | xrk\t%0,%1,%2 |
d40c829f | 6739 | x\t%0,%2 |
8cb66696 | 6740 | xy\t%0,%2 |
0dfa6c5e | 6741 | # |
19b63d8e | 6742 | #" |
65b1d8ea AK |
6743 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
6744 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
6745 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6746 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6747 | |
6748 | (define_split | |
6749 | [(set (match_operand:SI 0 "s_operand" "") | |
6750 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6751 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6752 | "reload_completed" |
6753 | [(parallel | |
6754 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6755 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6756 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 6757 | |
9db1d521 HP |
6758 | ; |
6759 | ; xorhi3 instruction pattern(s). | |
6760 | ; | |
6761 | ||
8cb66696 | 6762 | (define_insn "*xorhi3" |
65b1d8ea AK |
6763 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6764 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
6765 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 6766 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6767 | "s390_logical_operator_ok_p (operands)" |
6768 | "@ | |
ec24698e | 6769 | xilf\t%0,%x2 |
8cb66696 | 6770 | xr\t%0,%2 |
65b1d8ea | 6771 | xrk\t%0,%1,%2 |
0dfa6c5e | 6772 | # |
19b63d8e | 6773 | #" |
65b1d8ea AK |
6774 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
6775 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6776 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
6777 | |
6778 | (define_split | |
6779 | [(set (match_operand:HI 0 "s_operand" "") | |
6780 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6781 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6782 | "reload_completed" |
6783 | [(parallel | |
6784 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6785 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6786 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 6787 | |
9db1d521 HP |
6788 | ; |
6789 | ; xorqi3 instruction pattern(s). | |
6790 | ; | |
6791 | ||
8cb66696 | 6792 | (define_insn "*xorqi3" |
65b1d8ea AK |
6793 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6794 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
6795 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 6796 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6797 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 6798 | "@ |
ec24698e | 6799 | xilf\t%0,%b2 |
8cb66696 | 6800 | xr\t%0,%2 |
65b1d8ea | 6801 | xrk\t%0,%1,%2 |
fc0ea003 UW |
6802 | xi\t%S0,%b2 |
6803 | xiy\t%S0,%b2 | |
19b63d8e | 6804 | #" |
65b1d8ea AK |
6805 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
6806 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
6807 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 6808 | |
4023fb28 | 6809 | |
19b63d8e UW |
6810 | ; |
6811 | ; Block exclusive or (XC) patterns. | |
6812 | ; | |
6813 | ||
6814 | (define_insn "*xc" | |
6815 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6816 | (xor:BLK (match_dup 0) | |
6817 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6818 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6819 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6820 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6821 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 6822 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6823 | |
6824 | (define_split | |
6825 | [(set (match_operand 0 "memory_operand" "") | |
6826 | (xor (match_dup 0) | |
6827 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6828 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6829 | "reload_completed |
6830 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6831 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6832 | [(parallel | |
6833 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
6834 | (use (match_dup 2)) | |
ae156f85 | 6835 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6836 | { |
6837 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6838 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6839 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6840 | }) | |
6841 | ||
6842 | (define_peephole2 | |
6843 | [(parallel | |
6844 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6845 | (xor:BLK (match_dup 0) | |
6846 | (match_operand:BLK 1 "memory_operand" ""))) | |
6847 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6848 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6849 | (parallel |
6850 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6851 | (xor:BLK (match_dup 3) | |
6852 | (match_operand:BLK 4 "memory_operand" ""))) | |
6853 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6854 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6855 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6856 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6857 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6858 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6859 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6860 | [(parallel | |
6861 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
6862 | (use (match_dup 8)) | |
ae156f85 | 6863 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6864 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6865 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6866 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6867 | ||
6868 | ; | |
6869 | ; Block xor (XC) patterns with src == dest. | |
6870 | ; | |
6871 | ||
6872 | (define_insn "*xc_zero" | |
6873 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6874 | (const_int 0)) | |
6875 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 6876 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6877 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 6878 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
6879 | [(set_attr "op_type" "SS") |
6880 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6881 | |
6882 | (define_peephole2 | |
6883 | [(parallel | |
6884 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6885 | (const_int 0)) | |
6886 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 6887 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6888 | (parallel |
6889 | [(set (match_operand:BLK 2 "memory_operand" "") | |
6890 | (const_int 0)) | |
6891 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 6892 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6893 | "s390_offset_p (operands[0], operands[2], operands[1]) |
6894 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
6895 | [(parallel | |
6896 | [(set (match_dup 4) (const_int 0)) | |
6897 | (use (match_dup 5)) | |
ae156f85 | 6898 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6899 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6900 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
6901 | ||
9db1d521 HP |
6902 | |
6903 | ;; | |
6904 | ;;- Negate instructions. | |
6905 | ;; | |
6906 | ||
6907 | ; | |
9a91a21f | 6908 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
6909 | ; |
6910 | ||
9a91a21f | 6911 | (define_expand "neg<mode>2" |
9db1d521 | 6912 | [(parallel |
9a91a21f AS |
6913 | [(set (match_operand:DSI 0 "register_operand" "=d") |
6914 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 6915 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6916 | "" |
6917 | "") | |
6918 | ||
26a89301 | 6919 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 6920 | [(set (reg CC_REGNUM) |
26a89301 UW |
6921 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6922 | (match_operand:SI 1 "register_operand" "d") 0) | |
6923 | (const_int 32)) (const_int 32))) | |
6924 | (const_int 0))) | |
6925 | (set (match_operand:DI 0 "register_operand" "=d") | |
6926 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 6927 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 6928 | "lcgfr\t%0,%1" |
729e750f WG |
6929 | [(set_attr "op_type" "RRE") |
6930 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 6931 | |
26a89301 UW |
6932 | (define_insn "*negdi2_sign" |
6933 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6934 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 6935 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6936 | "TARGET_ZARCH" |
26a89301 | 6937 | "lcgfr\t%0,%1" |
729e750f WG |
6938 | [(set_attr "op_type" "RRE") |
6939 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 6940 | |
43a09b63 | 6941 | ; lcr, lcgr |
9a91a21f | 6942 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 6943 | [(set (reg CC_REGNUM) |
9a91a21f | 6944 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6945 | (const_int 0))) |
9a91a21f AS |
6946 | (set (match_operand:GPR 0 "register_operand" "=d") |
6947 | (neg:GPR (match_dup 1)))] | |
6948 | "s390_match_ccmode (insn, CCAmode)" | |
6949 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6950 | [(set_attr "op_type" "RR<E>") |
6951 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6952 | |
6953 | ; lcr, lcgr | |
9a91a21f | 6954 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 6955 | [(set (reg CC_REGNUM) |
9a91a21f | 6956 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 6957 | (const_int 0))) |
9a91a21f AS |
6958 | (clobber (match_scratch:GPR 0 "=d"))] |
6959 | "s390_match_ccmode (insn, CCAmode)" | |
6960 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6961 | [(set_attr "op_type" "RR<E>") |
6962 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
6963 | |
6964 | ; lcr, lcgr | |
9a91a21f AS |
6965 | (define_insn "*neg<mode>2" |
6966 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6967 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 6968 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
6969 | "" |
6970 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
6971 | [(set_attr "op_type" "RR<E>") |
6972 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 6973 | |
26a89301 | 6974 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
6975 | [(set (match_operand:DI 0 "register_operand" "=d") |
6976 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 6977 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6978 | "!TARGET_ZARCH" |
26a89301 UW |
6979 | "#" |
6980 | "&& reload_completed" | |
6981 | [(parallel | |
6982 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 6983 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 6984 | (parallel |
ae156f85 | 6985 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
6986 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
6987 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
6988 | (set (pc) | |
ae156f85 | 6989 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
6990 | (pc) |
6991 | (label_ref (match_dup 6)))) | |
6992 | (parallel | |
6993 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 6994 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
6995 | (match_dup 6)] |
6996 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
6997 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
6998 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
6999 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7000 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 7001 | |
9db1d521 | 7002 | ; |
f5905b37 | 7003 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7004 | ; |
7005 | ||
f5905b37 | 7006 | (define_expand "neg<mode>2" |
9db1d521 | 7007 | [(parallel |
7b6baae1 AK |
7008 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7009 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7010 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7011 | "TARGET_HARD_FLOAT" |
7012 | "") | |
7013 | ||
43a09b63 | 7014 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7015 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7016 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7017 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7018 | (match_operand:BFP 2 "const0_operand" ""))) | |
7019 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7020 | (neg:BFP (match_dup 1)))] | |
142cd70f | 7021 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7022 | "lc<xde>br\t%0,%1" |
26a89301 | 7023 | [(set_attr "op_type" "RRE") |
f5905b37 | 7024 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7025 | |
7026 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 7027 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7028 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7029 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7030 | (match_operand:BFP 2 "const0_operand" ""))) | |
7031 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7032 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7033 | "lc<xde>br\t%0,%1" |
26a89301 | 7034 | [(set_attr "op_type" "RRE") |
f5905b37 | 7035 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7036 | |
85dae55a AK |
7037 | ; lcdfr |
7038 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
7039 | [(set (match_operand:FP 0 "register_operand" "=f") |
7040 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7041 | "TARGET_DFP" |
85dae55a AK |
7042 | "lcdfr\t%0,%1" |
7043 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7044 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7045 | |
43a09b63 | 7046 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7047 | (define_insn "*neg<mode>2" |
7b6baae1 AK |
7048 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7049 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7050 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7051 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7052 | "lc<xde>br\t%0,%1" |
077dab3b | 7053 | [(set_attr "op_type" "RRE") |
f5905b37 | 7054 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7055 | |
9db1d521 HP |
7056 | |
7057 | ;; | |
7058 | ;;- Absolute value instructions. | |
7059 | ;; | |
7060 | ||
7061 | ; | |
9a91a21f | 7062 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
7063 | ; |
7064 | ||
26a89301 | 7065 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 7066 | [(set (reg CC_REGNUM) |
26a89301 UW |
7067 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7068 | (match_operand:SI 1 "register_operand" "d") 0) | |
7069 | (const_int 32)) (const_int 32))) | |
7070 | (const_int 0))) | |
7071 | (set (match_operand:DI 0 "register_operand" "=d") | |
7072 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7073 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7074 | "lpgfr\t%0,%1" |
729e750f WG |
7075 | [(set_attr "op_type" "RRE") |
7076 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
7077 | |
7078 | (define_insn "*absdi2_sign" | |
7079 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7080 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7081 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7082 | "TARGET_ZARCH" |
26a89301 | 7083 | "lpgfr\t%0,%1" |
729e750f WG |
7084 | [(set_attr "op_type" "RRE") |
7085 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7086 | |
43a09b63 | 7087 | ; lpr, lpgr |
9a91a21f | 7088 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7089 | [(set (reg CC_REGNUM) |
9a91a21f | 7090 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 7091 | (const_int 0))) |
9a91a21f AS |
7092 | (set (match_operand:GPR 0 "register_operand" "=d") |
7093 | (abs:GPR (match_dup 1)))] | |
26a89301 | 7094 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7095 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7096 | [(set_attr "op_type" "RR<E>") |
7097 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 7098 | |
9381e3f1 | 7099 | ; lpr, lpgr |
9a91a21f | 7100 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7101 | [(set (reg CC_REGNUM) |
9a91a21f | 7102 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7103 | (const_int 0))) |
9a91a21f | 7104 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7105 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7106 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7107 | [(set_attr "op_type" "RR<E>") |
7108 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7109 | |
7110 | ; lpr, lpgr | |
9a91a21f AS |
7111 | (define_insn "abs<mode>2" |
7112 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7113 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7114 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 7115 | "" |
9a91a21f | 7116 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7117 | [(set_attr "op_type" "RR<E>") |
7118 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 7119 | |
9db1d521 | 7120 | ; |
f5905b37 | 7121 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7122 | ; |
7123 | ||
f5905b37 | 7124 | (define_expand "abs<mode>2" |
9db1d521 | 7125 | [(parallel |
7b6baae1 AK |
7126 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7127 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7128 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7129 | "TARGET_HARD_FLOAT" |
7130 | "") | |
7131 | ||
43a09b63 | 7132 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7133 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7134 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7135 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7136 | (match_operand:BFP 2 "const0_operand" ""))) | |
7137 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7138 | (abs:BFP (match_dup 1)))] | |
142cd70f | 7139 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7140 | "lp<xde>br\t%0,%1" |
26a89301 | 7141 | [(set_attr "op_type" "RRE") |
f5905b37 | 7142 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7143 | |
7144 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 7145 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7146 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7147 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7148 | (match_operand:BFP 2 "const0_operand" ""))) | |
7149 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7150 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7151 | "lp<xde>br\t%0,%1" |
26a89301 | 7152 | [(set_attr "op_type" "RRE") |
f5905b37 | 7153 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7154 | |
85dae55a AK |
7155 | ; lpdfr |
7156 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
7157 | [(set (match_operand:FP 0 "register_operand" "=f") |
7158 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7159 | "TARGET_DFP" |
85dae55a AK |
7160 | "lpdfr\t%0,%1" |
7161 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7162 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7163 | |
43a09b63 | 7164 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7165 | (define_insn "*abs<mode>2" |
7b6baae1 AK |
7166 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7167 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7168 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7169 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7170 | "lp<xde>br\t%0,%1" |
077dab3b | 7171 | [(set_attr "op_type" "RRE") |
f5905b37 | 7172 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7173 | |
9db1d521 | 7174 | |
3ef093a8 AK |
7175 | ;; |
7176 | ;;- Negated absolute value instructions | |
7177 | ;; | |
7178 | ||
7179 | ; | |
7180 | ; Integer | |
7181 | ; | |
7182 | ||
26a89301 | 7183 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 7184 | [(set (reg CC_REGNUM) |
26a89301 UW |
7185 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7186 | (match_operand:SI 1 "register_operand" "d") 0) | |
7187 | (const_int 32)) (const_int 32)))) | |
7188 | (const_int 0))) | |
7189 | (set (match_operand:DI 0 "register_operand" "=d") | |
7190 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 7191 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7192 | "lngfr\t%0,%1" |
729e750f WG |
7193 | [(set_attr "op_type" "RRE") |
7194 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7195 | |
26a89301 UW |
7196 | (define_insn "*negabsdi2_sign" |
7197 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7198 | (neg:DI (abs:DI (sign_extend:DI | |
7199 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 7200 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7201 | "TARGET_ZARCH" |
26a89301 | 7202 | "lngfr\t%0,%1" |
729e750f WG |
7203 | [(set_attr "op_type" "RRE") |
7204 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 7205 | |
43a09b63 | 7206 | ; lnr, lngr |
9a91a21f | 7207 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7208 | [(set (reg CC_REGNUM) |
9a91a21f | 7209 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7210 | (const_int 0))) |
9a91a21f AS |
7211 | (set (match_operand:GPR 0 "register_operand" "=d") |
7212 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 7213 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7214 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7215 | [(set_attr "op_type" "RR<E>") |
7216 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7217 | |
7218 | ; lnr, lngr | |
9a91a21f | 7219 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7220 | [(set (reg CC_REGNUM) |
9a91a21f | 7221 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7222 | (const_int 0))) |
9a91a21f | 7223 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7224 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7225 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7226 | [(set_attr "op_type" "RR<E>") |
7227 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7228 | |
7229 | ; lnr, lngr | |
9a91a21f AS |
7230 | (define_insn "*negabs<mode>2" |
7231 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7232 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 7233 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 7234 | "" |
9a91a21f | 7235 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7236 | [(set_attr "op_type" "RR<E>") |
7237 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7238 | |
3ef093a8 AK |
7239 | ; |
7240 | ; Floating point | |
7241 | ; | |
7242 | ||
43a09b63 | 7243 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7244 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7245 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7246 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7247 | (match_operand:BFP 2 "const0_operand" ""))) | |
7248 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7249 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 7250 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7251 | "ln<xde>br\t%0,%1" |
26a89301 | 7252 | [(set_attr "op_type" "RRE") |
f5905b37 | 7253 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7254 | |
7255 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 7256 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7257 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7258 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7259 | (match_operand:BFP 2 "const0_operand" ""))) | |
7260 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7261 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7262 | "ln<xde>br\t%0,%1" |
26a89301 | 7263 | [(set_attr "op_type" "RRE") |
f5905b37 | 7264 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7265 | |
85dae55a AK |
7266 | ; lndfr |
7267 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
7268 | [(set (match_operand:FP 0 "register_operand" "=f") |
7269 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 7270 | "TARGET_DFP" |
85dae55a AK |
7271 | "lndfr\t%0,%1" |
7272 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7273 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7274 | |
43a09b63 | 7275 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7276 | (define_insn "*negabs<mode>2" |
7b6baae1 AK |
7277 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7278 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))) | |
ae156f85 | 7279 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7280 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7281 | "ln<xde>br\t%0,%1" |
26a89301 | 7282 | [(set_attr "op_type" "RRE") |
f5905b37 | 7283 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 7284 | |
4023fb28 UW |
7285 | ;; |
7286 | ;;- Square root instructions. | |
7287 | ;; | |
7288 | ||
7289 | ; | |
f5905b37 | 7290 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
7291 | ; |
7292 | ||
9381e3f1 | 7293 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 7294 | (define_insn "sqrt<mode>2" |
7b6baae1 AK |
7295 | [(set (match_operand:BFP 0 "register_operand" "=f,f") |
7296 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 7297 | "TARGET_HARD_FLOAT" |
4023fb28 | 7298 | "@ |
f61a2c7d AK |
7299 | sq<xde>br\t%0,%1 |
7300 | sq<xde>b\t%0,%1" | |
a036c6f7 | 7301 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 7302 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 7303 | |
9db1d521 HP |
7304 | |
7305 | ;; | |
7306 | ;;- One complement instructions. | |
7307 | ;; | |
7308 | ||
7309 | ; | |
342cf42b | 7310 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 7311 | ; |
c7453384 | 7312 | |
342cf42b | 7313 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 7314 | [(parallel |
342cf42b AS |
7315 | [(set (match_operand:INT 0 "register_operand" "") |
7316 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
7317 | (const_int -1))) | |
ae156f85 | 7318 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 7319 | "" |
4023fb28 | 7320 | "") |
9db1d521 HP |
7321 | |
7322 | ||
ec24698e UW |
7323 | ;; |
7324 | ;; Find leftmost bit instructions. | |
7325 | ;; | |
7326 | ||
7327 | (define_expand "clzdi2" | |
7328 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7329 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 7330 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7331 | { |
7332 | rtx insn, clz_equal; | |
7333 | rtx wide_reg = gen_reg_rtx (TImode); | |
7334 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
7335 | ||
7336 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
7337 | ||
7338 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
7339 | ||
9381e3f1 | 7340 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 7341 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
7342 | |
7343 | DONE; | |
7344 | }) | |
7345 | ||
7346 | (define_insn "clztidi2" | |
7347 | [(set (match_operand:TI 0 "register_operand" "=d") | |
7348 | (ior:TI | |
9381e3f1 WG |
7349 | (ashift:TI |
7350 | (zero_extend:TI | |
ec24698e UW |
7351 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
7352 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
7353 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 7354 | |
ec24698e UW |
7355 | (const_int 64)) |
7356 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
7357 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 7358 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 7359 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 7360 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7361 | "flogr\t%0,%1" |
7362 | [(set_attr "op_type" "RRE")]) | |
7363 | ||
7364 | ||
9db1d521 HP |
7365 | ;; |
7366 | ;;- Rotate instructions. | |
7367 | ;; | |
7368 | ||
7369 | ; | |
9a91a21f | 7370 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
7371 | ; |
7372 | ||
43a09b63 | 7373 | ; rll, rllg |
9a91a21f AS |
7374 | (define_insn "rotl<mode>3" |
7375 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7376 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 7377 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 7378 | "TARGET_CPU_ZARCH" |
9a91a21f | 7379 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 7380 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
7381 | (set_attr "atype" "reg") |
7382 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7383 | |
43a09b63 | 7384 | ; rll, rllg |
4989e88a AK |
7385 | (define_insn "*rotl<mode>3_and" |
7386 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7387 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7388 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7389 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7390 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
7391 | "rll<g>\t%0,%1,%Y2" | |
7392 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
7393 | (set_attr "atype" "reg") |
7394 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7395 | |
9db1d521 HP |
7396 | |
7397 | ;; | |
f337b930 | 7398 | ;;- Shift instructions. |
9db1d521 | 7399 | ;; |
9db1d521 HP |
7400 | |
7401 | ; | |
1b48c8cc | 7402 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 7403 | ; Left shifts and logical right shifts |
9db1d521 | 7404 | |
1b48c8cc AS |
7405 | (define_expand "<shift><mode>3" |
7406 | [(set (match_operand:DSI 0 "register_operand" "") | |
7407 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
7408 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
7409 | "" |
7410 | "") | |
7411 | ||
43a09b63 | 7412 | ; sldl, srdl |
f337b930 | 7413 | (define_insn "*<shift>di3_31" |
ac32b25e | 7414 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 7415 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7416 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9602b6a1 | 7417 | "!TARGET_ZARCH" |
f337b930 | 7418 | "s<lr>dl\t%0,%Y2" |
077dab3b | 7419 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
7420 | (set_attr "atype" "reg") |
7421 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 7422 | |
65b1d8ea | 7423 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7424 | (define_insn "*<shift><mode>3" |
65b1d8ea AK |
7425 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7426 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7427 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] | |
1b48c8cc | 7428 | "" |
65b1d8ea AK |
7429 | "@ |
7430 | s<lr>l<g>\t%0,<1>%Y2 | |
7431 | s<lr>l<gk>\t%0,%1,%Y2" | |
7432 | [(set_attr "op_type" "RS<E>,RSY") | |
7433 | (set_attr "atype" "reg,reg") | |
7434 | (set_attr "cpu_facility" "*,z196") | |
7435 | (set_attr "z10prop" "z10_super_E1,*")]) | |
9db1d521 | 7436 | |
43a09b63 | 7437 | ; sldl, srdl |
4989e88a AK |
7438 | (define_insn "*<shift>di3_31_and" |
7439 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7440 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7441 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7442 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
9602b6a1 | 7443 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7444 | "s<lr>dl\t%0,%Y2" |
7445 | [(set_attr "op_type" "RS") | |
7446 | (set_attr "atype" "reg")]) | |
7447 | ||
65b1d8ea | 7448 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7449 | (define_insn "*<shift><mode>3_and" |
65b1d8ea AK |
7450 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7451 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7452 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7453 | (match_operand:SI 3 "const_int_operand" "n,n"))))] | |
1b48c8cc | 7454 | "(INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7455 | "@ |
7456 | s<lr>l<g>\t%0,<1>%Y2 | |
7457 | s<lr>l<gk>\t%0,%1,%Y2" | |
7458 | [(set_attr "op_type" "RS<E>,RSY") | |
7459 | (set_attr "atype" "reg,reg") | |
7460 | (set_attr "cpu_facility" "*,z196") | |
7461 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7462 | |
9db1d521 | 7463 | ; |
1b48c8cc | 7464 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 7465 | ; Arithmetic right shifts |
9db1d521 | 7466 | |
1b48c8cc | 7467 | (define_expand "ashr<mode>3" |
9db1d521 | 7468 | [(parallel |
1b48c8cc AS |
7469 | [(set (match_operand:DSI 0 "register_operand" "") |
7470 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
7471 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 7472 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7473 | "" |
7474 | "") | |
7475 | ||
ecbe845e | 7476 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 7477 | [(set (reg CC_REGNUM) |
ac32b25e | 7478 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7479 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7480 | (const_int 0))) |
ac32b25e | 7481 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e | 7482 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7483 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7484 | "srda\t%0,%Y2" |
077dab3b HP |
7485 | [(set_attr "op_type" "RS") |
7486 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
7487 | |
7488 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 7489 | [(set (reg CC_REGNUM) |
ac32b25e | 7490 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7491 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7492 | (const_int 0))) |
ac32b25e | 7493 | (clobber (match_scratch:DI 0 "=d"))] |
9602b6a1 | 7494 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7495 | "srda\t%0,%Y2" |
077dab3b HP |
7496 | [(set_attr "op_type" "RS") |
7497 | (set_attr "atype" "reg")]) | |
ecbe845e | 7498 | |
9db1d521 | 7499 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
7500 | [(set (match_operand:DI 0 "register_operand" "=d") |
7501 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 7502 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 7503 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7504 | "!TARGET_ZARCH" |
ac32b25e | 7505 | "srda\t%0,%Y2" |
077dab3b HP |
7506 | [(set_attr "op_type" "RS") |
7507 | (set_attr "atype" "reg")]) | |
c7453384 | 7508 | |
65b1d8ea | 7509 | ; sra, srag, srak |
1b48c8cc | 7510 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 7511 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7512 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7513 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7514 | (const_int 0))) |
65b1d8ea | 7515 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc AS |
7516 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] |
7517 | "s390_match_ccmode(insn, CCSmode)" | |
65b1d8ea AK |
7518 | "@ |
7519 | sra<g>\t%0,<1>%Y2 | |
7520 | sra<gk>\t%0,%1,%Y2" | |
7521 | [(set_attr "op_type" "RS<E>,RSY") | |
7522 | (set_attr "atype" "reg,reg") | |
7523 | (set_attr "cpu_facility" "*,z196") | |
7524 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7525 | |
65b1d8ea | 7526 | ; sra, srag, srak |
1b48c8cc | 7527 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 7528 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7529 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7530 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7531 | (const_int 0))) |
65b1d8ea | 7532 | (clobber (match_scratch:GPR 0 "=d,d"))] |
1b48c8cc | 7533 | "s390_match_ccmode(insn, CCSmode)" |
65b1d8ea AK |
7534 | "@ |
7535 | sra<g>\t%0,<1>%Y2 | |
7536 | sra<gk>\t%0,%1,%Y2" | |
7537 | [(set_attr "op_type" "RS<E>,RSY") | |
7538 | (set_attr "atype" "reg,reg") | |
7539 | (set_attr "cpu_facility" "*,z196") | |
7540 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7541 | |
43a09b63 | 7542 | ; sra, srag |
1b48c8cc | 7543 | (define_insn "*ashr<mode>3" |
65b1d8ea AK |
7544 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7545 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7546 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) | |
ae156f85 | 7547 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 7548 | "" |
65b1d8ea AK |
7549 | "@ |
7550 | sra<g>\t%0,<1>%Y2 | |
7551 | sra<gk>\t%0,%1,%Y2" | |
7552 | [(set_attr "op_type" "RS<E>,RSY") | |
7553 | (set_attr "atype" "reg,reg") | |
7554 | (set_attr "cpu_facility" "*,z196") | |
7555 | (set_attr "z10prop" "z10_super_E1,*")]) | |
077dab3b | 7556 | |
9db1d521 | 7557 | |
4989e88a AK |
7558 | ; shift pattern with implicit ANDs |
7559 | ||
7560 | (define_insn "*ashrdi3_cc_31_and" | |
7561 | [(set (reg CC_REGNUM) | |
7562 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7563 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7564 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7565 | (const_int 0))) | |
7566 | (set (match_operand:DI 0 "register_operand" "=d") | |
7567 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
9602b6a1 | 7568 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7569 | && (INTVAL (operands[3]) & 63) == 63" |
7570 | "srda\t%0,%Y2" | |
7571 | [(set_attr "op_type" "RS") | |
7572 | (set_attr "atype" "reg")]) | |
7573 | ||
7574 | (define_insn "*ashrdi3_cconly_31_and" | |
7575 | [(set (reg CC_REGNUM) | |
7576 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7577 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7578 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7579 | (const_int 0))) | |
7580 | (clobber (match_scratch:DI 0 "=d"))] | |
9602b6a1 | 7581 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7582 | && (INTVAL (operands[3]) & 63) == 63" |
7583 | "srda\t%0,%Y2" | |
7584 | [(set_attr "op_type" "RS") | |
7585 | (set_attr "atype" "reg")]) | |
7586 | ||
7587 | (define_insn "*ashrdi3_31_and" | |
7588 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7589 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7590 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7591 | (match_operand:SI 3 "const_int_operand" "n")))) | |
7592 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 7593 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7594 | "srda\t%0,%Y2" |
7595 | [(set_attr "op_type" "RS") | |
7596 | (set_attr "atype" "reg")]) | |
7597 | ||
65b1d8ea | 7598 | ; sra, srag, srak |
1b48c8cc | 7599 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 7600 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7601 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7602 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7603 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7604 | (const_int 0))) |
65b1d8ea | 7605 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc | 7606 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] |
4989e88a | 7607 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7608 | "@ |
7609 | sra<g>\t%0,<1>%Y2 | |
7610 | sra<gk>\t%0,%1,%Y2" | |
7611 | [(set_attr "op_type" "RS<E>,RSY") | |
7612 | (set_attr "atype" "reg,reg") | |
7613 | (set_attr "cpu_facility" "*,z196") | |
7614 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7615 | |
65b1d8ea | 7616 | ; sra, srag, srak |
1b48c8cc | 7617 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 7618 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7619 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7620 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7621 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7622 | (const_int 0))) |
65b1d8ea | 7623 | (clobber (match_scratch:GPR 0 "=d,d"))] |
4989e88a | 7624 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7625 | "@ |
7626 | sra<g>\t%0,<1>%Y2 | |
7627 | sra<gk>\t%0,%1,%Y2" | |
7628 | [(set_attr "op_type" "RS<E>,RSY") | |
7629 | (set_attr "atype" "reg,reg") | |
7630 | (set_attr "cpu_facility" "*,z196") | |
7631 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7632 | |
65b1d8ea | 7633 | ; sra, srag, srak |
1b48c8cc | 7634 | (define_insn "*ashr<mode>3_and" |
65b1d8ea AK |
7635 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7636 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7637 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7638 | (match_operand:SI 3 "const_int_operand" "n,n")))) | |
4989e88a AK |
7639 | (clobber (reg:CC CC_REGNUM))] |
7640 | "(INTVAL (operands[3]) & 63) == 63" | |
65b1d8ea AK |
7641 | "@ |
7642 | sra<g>\t%0,<1>%Y2 | |
7643 | sra<gk>\t%0,%1,%Y2" | |
7644 | [(set_attr "op_type" "RS<E>,RSY") | |
7645 | (set_attr "atype" "reg,reg") | |
7646 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7647 | |
9db1d521 | 7648 | |
9db1d521 HP |
7649 | ;; |
7650 | ;; Branch instruction patterns. | |
7651 | ;; | |
7652 | ||
f90b7a5a | 7653 | (define_expand "cbranch<mode>4" |
fa77b251 | 7654 | [(set (pc) |
f90b7a5a PB |
7655 | (if_then_else (match_operator 0 "comparison_operator" |
7656 | [(match_operand:GPR 1 "register_operand" "") | |
7657 | (match_operand:GPR 2 "general_operand" "")]) | |
7658 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 7659 | (pc)))] |
ba956982 | 7660 | "" |
f90b7a5a PB |
7661 | "s390_emit_jump (operands[3], |
7662 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7663 | DONE;") | |
7664 | ||
7665 | (define_expand "cbranch<mode>4" | |
7666 | [(set (pc) | |
7667 | (if_then_else (match_operator 0 "comparison_operator" | |
7668 | [(match_operand:FP 1 "register_operand" "") | |
7669 | (match_operand:FP 2 "general_operand" "")]) | |
7670 | (label_ref (match_operand 3 "" "")) | |
7671 | (pc)))] | |
7672 | "TARGET_HARD_FLOAT" | |
7673 | "s390_emit_jump (operands[3], | |
7674 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7675 | DONE;") | |
7676 | ||
7677 | (define_expand "cbranchcc4" | |
7678 | [(set (pc) | |
7679 | (if_then_else (match_operator 0 "s390_eqne_operator" | |
7680 | [(match_operand 1 "cc_reg_operand" "") | |
7681 | (match_operand 2 "const0_operand" "")]) | |
7682 | (label_ref (match_operand 3 "" "")) | |
7683 | (pc)))] | |
7684 | "TARGET_HARD_FLOAT" | |
7685 | "s390_emit_jump (operands[3], | |
7686 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7687 | DONE;") | |
7688 | ||
ba956982 | 7689 | |
9db1d521 HP |
7690 | |
7691 | ;; | |
7692 | ;;- Conditional jump instructions. | |
7693 | ;; | |
7694 | ||
6590e19a UW |
7695 | (define_insn "*cjump_64" |
7696 | [(set (pc) | |
7697 | (if_then_else | |
ae156f85 | 7698 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7699 | (label_ref (match_operand 0 "" "")) |
7700 | (pc)))] | |
7701 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7702 | { |
13e58269 | 7703 | if (get_attr_length (insn) == 4) |
d40c829f | 7704 | return "j%C1\t%l0"; |
6590e19a | 7705 | else |
d40c829f | 7706 | return "jg%C1\t%l0"; |
6590e19a UW |
7707 | } |
7708 | [(set_attr "op_type" "RI") | |
7709 | (set_attr "type" "branch") | |
7710 | (set (attr "length") | |
7711 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7712 | (const_int 4) (const_int 6)))]) | |
7713 | ||
7714 | (define_insn "*cjump_31" | |
7715 | [(set (pc) | |
7716 | (if_then_else | |
ae156f85 | 7717 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7718 | (label_ref (match_operand 0 "" "")) |
7719 | (pc)))] | |
7720 | "!TARGET_CPU_ZARCH" | |
7721 | { | |
8d933e31 AS |
7722 | gcc_assert (get_attr_length (insn) == 4); |
7723 | return "j%C1\t%l0"; | |
10bbf137 | 7724 | } |
9db1d521 | 7725 | [(set_attr "op_type" "RI") |
077dab3b | 7726 | (set_attr "type" "branch") |
13e58269 | 7727 | (set (attr "length") |
6590e19a UW |
7728 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7729 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7730 | (const_int 4) (const_int 6)) | |
7731 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7732 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7733 | |
f314b9b1 | 7734 | (define_insn "*cjump_long" |
6590e19a UW |
7735 | [(set (pc) |
7736 | (if_then_else | |
ae156f85 | 7737 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 7738 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 7739 | (pc)))] |
9db1d521 | 7740 | "" |
f314b9b1 UW |
7741 | { |
7742 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7743 | return "b%C1r\t%0"; |
f314b9b1 | 7744 | else |
d40c829f | 7745 | return "b%C1\t%a0"; |
10bbf137 | 7746 | } |
c7453384 | 7747 | [(set (attr "op_type") |
f314b9b1 UW |
7748 | (if_then_else (match_operand 0 "register_operand" "") |
7749 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 7750 | (set_attr "type" "branch") |
077dab3b | 7751 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7752 | |
7753 | ||
7754 | ;; | |
7755 | ;;- Negated conditional jump instructions. | |
7756 | ;; | |
7757 | ||
6590e19a UW |
7758 | (define_insn "*icjump_64" |
7759 | [(set (pc) | |
7760 | (if_then_else | |
ae156f85 | 7761 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7762 | (pc) |
7763 | (label_ref (match_operand 0 "" ""))))] | |
7764 | "TARGET_CPU_ZARCH" | |
c7453384 | 7765 | { |
13e58269 | 7766 | if (get_attr_length (insn) == 4) |
d40c829f | 7767 | return "j%D1\t%l0"; |
6590e19a | 7768 | else |
d40c829f | 7769 | return "jg%D1\t%l0"; |
6590e19a UW |
7770 | } |
7771 | [(set_attr "op_type" "RI") | |
7772 | (set_attr "type" "branch") | |
7773 | (set (attr "length") | |
7774 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7775 | (const_int 4) (const_int 6)))]) | |
7776 | ||
7777 | (define_insn "*icjump_31" | |
7778 | [(set (pc) | |
7779 | (if_then_else | |
ae156f85 | 7780 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
7781 | (pc) |
7782 | (label_ref (match_operand 0 "" ""))))] | |
7783 | "!TARGET_CPU_ZARCH" | |
7784 | { | |
8d933e31 AS |
7785 | gcc_assert (get_attr_length (insn) == 4); |
7786 | return "j%D1\t%l0"; | |
10bbf137 | 7787 | } |
9db1d521 | 7788 | [(set_attr "op_type" "RI") |
077dab3b | 7789 | (set_attr "type" "branch") |
13e58269 | 7790 | (set (attr "length") |
6590e19a UW |
7791 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7792 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7793 | (const_int 4) (const_int 6)) | |
7794 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7795 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7796 | |
f314b9b1 | 7797 | (define_insn "*icjump_long" |
6590e19a UW |
7798 | [(set (pc) |
7799 | (if_then_else | |
ae156f85 | 7800 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 7801 | (pc) |
4fe6dea8 | 7802 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 7803 | "" |
f314b9b1 UW |
7804 | { |
7805 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7806 | return "b%D1r\t%0"; |
f314b9b1 | 7807 | else |
d40c829f | 7808 | return "b%D1\t%a0"; |
10bbf137 | 7809 | } |
c7453384 | 7810 | [(set (attr "op_type") |
f314b9b1 UW |
7811 | (if_then_else (match_operand 0 "register_operand" "") |
7812 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7813 | (set_attr "type" "branch") |
7814 | (set_attr "atype" "agen")]) | |
9db1d521 | 7815 | |
4456530d HP |
7816 | ;; |
7817 | ;;- Trap instructions. | |
7818 | ;; | |
7819 | ||
7820 | (define_insn "trap" | |
7821 | [(trap_if (const_int 1) (const_int 0))] | |
7822 | "" | |
d40c829f | 7823 | "j\t.+2" |
6590e19a | 7824 | [(set_attr "op_type" "RI") |
077dab3b | 7825 | (set_attr "type" "branch")]) |
4456530d | 7826 | |
f90b7a5a PB |
7827 | (define_expand "ctrap<mode>4" |
7828 | [(trap_if (match_operator 0 "comparison_operator" | |
7829 | [(match_operand:GPR 1 "register_operand" "") | |
7830 | (match_operand:GPR 2 "general_operand" "")]) | |
7831 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 7832 | "" |
f90b7a5a PB |
7833 | { |
7834 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
7835 | operands[1], operands[2]); | |
7836 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
7837 | DONE; | |
7838 | }) | |
7839 | ||
7840 | (define_expand "ctrap<mode>4" | |
7841 | [(trap_if (match_operator 0 "comparison_operator" | |
7842 | [(match_operand:FP 1 "register_operand" "") | |
7843 | (match_operand:FP 2 "general_operand" "")]) | |
7844 | (match_operand 3 "const0_operand" ""))] | |
7845 | "" | |
7846 | { | |
7847 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
7848 | operands[1], operands[2]); | |
7849 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
7850 | DONE; | |
7851 | }) | |
4456530d | 7852 | |
f90b7a5a PB |
7853 | (define_insn "condtrap" |
7854 | [(trap_if (match_operator 0 "s390_comparison" | |
7855 | [(match_operand 1 "cc_reg_operand" "c") | |
7856 | (const_int 0)]) | |
4456530d HP |
7857 | (const_int 0))] |
7858 | "" | |
d40c829f | 7859 | "j%C0\t.+2"; |
077dab3b HP |
7860 | [(set_attr "op_type" "RI") |
7861 | (set_attr "type" "branch")]) | |
9db1d521 | 7862 | |
963fc8d0 AK |
7863 | ; crt, cgrt, cit, cgit |
7864 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
7865 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
7866 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7867 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
7868 | (const_int 0))] | |
7869 | "TARGET_Z10" | |
7870 | "@ | |
7871 | c<g>rt%C0\t%1,%2 | |
7872 | c<g>it%C0\t%1,%h2" | |
7873 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7874 | (set_attr "type" "branch") |
729e750f | 7875 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 AK |
7876 | |
7877 | ; clrt, clgrt, clfit, clgit | |
7878 | (define_insn "*cmp_and_trap_unsigned_int<mode>" | |
7879 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
7880 | [(match_operand:GPR 1 "register_operand" "d,d") | |
7881 | (match_operand:GPR 2 "nonmemory_operand" "d,D")]) | |
7882 | (const_int 0))] | |
7883 | "TARGET_Z10" | |
7884 | "@ | |
7885 | cl<g>rt%C0\t%1,%2 | |
7886 | cl<gf>it%C0\t%1,%x2" | |
7887 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 7888 | (set_attr "type" "branch") |
729e750f | 7889 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 7890 | |
9db1d521 | 7891 | ;; |
0a3bdf9d | 7892 | ;;- Loop instructions. |
9db1d521 | 7893 | ;; |
0a3bdf9d UW |
7894 | ;; This is all complicated by the fact that since this is a jump insn |
7895 | ;; we must handle our own output reloads. | |
c7453384 | 7896 | |
f1149235 AK |
7897 | ;; branch on index |
7898 | ||
7899 | ; This splitter will be matched by combine and has to add the 2 moves | |
7900 | ; necessary to load the compare and the increment values into a | |
7901 | ; register pair as needed by brxle. | |
7902 | ||
7903 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
7904 | [(set (pc) | |
7905 | (if_then_else | |
7906 | (match_operator 6 "s390_brx_operator" | |
7907 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
7908 | (match_operand:GPR 2 "general_operand" "")) | |
7909 | (match_operand:GPR 3 "register_operand" "")]) | |
7910 | (label_ref (match_operand 0 "" "")) | |
7911 | (pc))) | |
7912 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
7913 | (plus:GPR (match_dup 1) (match_dup 2))) | |
7914 | (clobber (match_scratch:GPR 5 ""))] | |
7915 | "TARGET_CPU_ZARCH" | |
7916 | "#" | |
7917 | "!reload_completed && !reload_in_progress" | |
7918 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
7919 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
7920 | (parallel [(set (pc) | |
7921 | (if_then_else | |
7922 | (match_op_dup 6 | |
7923 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
7924 | (match_dup 8)]) | |
7925 | (label_ref (match_dup 0)) | |
7926 | (pc))) | |
7927 | (set (match_dup 4) | |
7928 | (plus:GPR (match_dup 1) (match_dup 7))) | |
7929 | (clobber (match_dup 5)) | |
7930 | (clobber (reg:CC CC_REGNUM))])] | |
7931 | { | |
7932 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
7933 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
7934 | gen_highpart (word_mode, dreg)); | |
7935 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
7936 | gen_lowpart (word_mode, dreg)); | |
7937 | }) | |
7938 | ||
7939 | ; brxlg, brxhg | |
7940 | ||
7941 | (define_insn_and_split "*brxg_64bit" | |
7942 | [(set (pc) | |
7943 | (if_then_else | |
7944 | (match_operator 5 "s390_brx_operator" | |
7945 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
7946 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
7947 | (subreg:DI (match_dup 2) 8)]) | |
7948 | (label_ref (match_operand 0 "" "")) | |
7949 | (pc))) | |
7950 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
7951 | (plus:DI (match_dup 1) | |
7952 | (subreg:DI (match_dup 2) 0))) | |
7953 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
7954 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 7955 | "TARGET_ZARCH" |
f1149235 AK |
7956 | { |
7957 | if (which_alternative != 0) | |
7958 | return "#"; | |
7959 | else if (get_attr_length (insn) == 6) | |
7960 | return "brx%E5g\t%1,%2,%l0"; | |
7961 | else | |
7962 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
7963 | } | |
7964 | "&& reload_completed | |
7965 | && (!REG_P (operands[3]) | |
7966 | || !rtx_equal_p (operands[1], operands[3]))" | |
7967 | [(set (match_dup 4) (match_dup 1)) | |
7968 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
7969 | (clobber (reg:CC CC_REGNUM))]) | |
7970 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
7971 | (set (match_dup 3) (match_dup 4)) | |
7972 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
7973 | (label_ref (match_dup 0)) | |
7974 | (pc)))] | |
7975 | "" | |
7976 | [(set_attr "op_type" "RIE") | |
7977 | (set_attr "type" "branch") | |
7978 | (set (attr "length") | |
7979 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7980 | (const_int 6) (const_int 16)))]) | |
7981 | ||
7982 | ; brxle, brxh | |
7983 | ||
7984 | (define_insn_and_split "*brx_64bit" | |
7985 | [(set (pc) | |
7986 | (if_then_else | |
7987 | (match_operator 5 "s390_brx_operator" | |
7988 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
7989 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
7990 | (subreg:SI (match_dup 2) 12)]) | |
7991 | (label_ref (match_operand 0 "" "")) | |
7992 | (pc))) | |
7993 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
7994 | (plus:SI (match_dup 1) | |
7995 | (subreg:SI (match_dup 2) 4))) | |
7996 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
7997 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 7998 | "TARGET_ZARCH" |
f1149235 AK |
7999 | { |
8000 | if (which_alternative != 0) | |
8001 | return "#"; | |
8002 | else if (get_attr_length (insn) == 6) | |
8003 | return "brx%C5\t%1,%2,%l0"; | |
8004 | else | |
8005 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8006 | } | |
8007 | "&& reload_completed | |
8008 | && (!REG_P (operands[3]) | |
8009 | || !rtx_equal_p (operands[1], operands[3]))" | |
8010 | [(set (match_dup 4) (match_dup 1)) | |
8011 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8012 | (clobber (reg:CC CC_REGNUM))]) | |
8013 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
8014 | (set (match_dup 3) (match_dup 4)) | |
8015 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8016 | (label_ref (match_dup 0)) | |
8017 | (pc)))] | |
8018 | "" | |
8019 | [(set_attr "op_type" "RSI") | |
8020 | (set_attr "type" "branch") | |
8021 | (set (attr "length") | |
8022 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8023 | (const_int 6) (const_int 14)))]) | |
8024 | ||
8025 | ; brxle, brxh | |
8026 | ||
8027 | (define_insn_and_split "*brx_31bit" | |
8028 | [(set (pc) | |
8029 | (if_then_else | |
8030 | (match_operator 5 "s390_brx_operator" | |
8031 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8032 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
8033 | (subreg:SI (match_dup 2) 4)]) | |
8034 | (label_ref (match_operand 0 "" "")) | |
8035 | (pc))) | |
8036 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8037 | (plus:SI (match_dup 1) | |
8038 | (subreg:SI (match_dup 2) 0))) | |
8039 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8040 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8041 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
8042 | { |
8043 | if (which_alternative != 0) | |
8044 | return "#"; | |
8045 | else if (get_attr_length (insn) == 6) | |
8046 | return "brx%C5\t%1,%2,%l0"; | |
8047 | else | |
8048 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8049 | } | |
8050 | "&& reload_completed | |
8051 | && (!REG_P (operands[3]) | |
8052 | || !rtx_equal_p (operands[1], operands[3]))" | |
8053 | [(set (match_dup 4) (match_dup 1)) | |
8054 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
8055 | (clobber (reg:CC CC_REGNUM))]) | |
8056 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8057 | (set (match_dup 3) (match_dup 4)) | |
8058 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8059 | (label_ref (match_dup 0)) | |
8060 | (pc)))] | |
8061 | "" | |
8062 | [(set_attr "op_type" "RSI") | |
8063 | (set_attr "type" "branch") | |
8064 | (set (attr "length") | |
8065 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8066 | (const_int 6) (const_int 14)))]) | |
8067 | ||
8068 | ||
8069 | ;; branch on count | |
8070 | ||
0a3bdf9d UW |
8071 | (define_expand "doloop_end" |
8072 | [(use (match_operand 0 "" "")) ; loop pseudo | |
8073 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
8074 | (use (match_operand 2 "" "")) ; max iterations | |
8075 | (use (match_operand 3 "" "")) ; loop level | |
8076 | (use (match_operand 4 "" ""))] ; label | |
8077 | "" | |
0a3bdf9d | 8078 | { |
6590e19a UW |
8079 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
8080 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
8081 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
8082 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
9602b6a1 | 8083 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
0a3bdf9d UW |
8084 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); |
8085 | else | |
8086 | FAIL; | |
8087 | ||
8088 | DONE; | |
10bbf137 | 8089 | }) |
0a3bdf9d | 8090 | |
6590e19a | 8091 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
8092 | [(set (pc) |
8093 | (if_then_else | |
7e665d18 | 8094 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8095 | (const_int 1)) |
8096 | (label_ref (match_operand 0 "" "")) | |
8097 | (pc))) | |
7e665d18 | 8098 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8099 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8100 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8101 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8102 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8103 | { |
8104 | if (which_alternative != 0) | |
10bbf137 | 8105 | return "#"; |
0a3bdf9d | 8106 | else if (get_attr_length (insn) == 4) |
d40c829f | 8107 | return "brct\t%1,%l0"; |
6590e19a | 8108 | else |
545d16ff | 8109 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
8110 | } |
8111 | "&& reload_completed | |
8112 | && (! REG_P (operands[2]) | |
8113 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8114 | [(set (match_dup 3) (match_dup 1)) |
8115 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8116 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8117 | (const_int 0))) | |
8118 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8119 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8120 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8121 | (label_ref (match_dup 0)) |
8122 | (pc)))] | |
8123 | "" | |
8124 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8125 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8126 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8127 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8128 | (set_attr "type" "branch") |
8129 | (set (attr "length") | |
8130 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8131 | (const_int 4) (const_int 10)))]) | |
8132 | ||
8133 | (define_insn_and_split "doloop_si31" | |
8134 | [(set (pc) | |
8135 | (if_then_else | |
7e665d18 | 8136 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
8137 | (const_int 1)) |
8138 | (label_ref (match_operand 0 "" "")) | |
8139 | (pc))) | |
7e665d18 | 8140 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 8141 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8142 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8143 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
8144 | "!TARGET_CPU_ZARCH" |
8145 | { | |
8146 | if (which_alternative != 0) | |
8147 | return "#"; | |
8148 | else if (get_attr_length (insn) == 4) | |
8149 | return "brct\t%1,%l0"; | |
0a3bdf9d | 8150 | else |
8d933e31 | 8151 | gcc_unreachable (); |
10bbf137 | 8152 | } |
6590e19a UW |
8153 | "&& reload_completed |
8154 | && (! REG_P (operands[2]) | |
8155 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8156 | [(set (match_dup 3) (match_dup 1)) |
8157 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8158 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8159 | (const_int 0))) | |
8160 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8161 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8162 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8163 | (label_ref (match_dup 0)) |
8164 | (pc)))] | |
8165 | "" | |
0a3bdf9d | 8166 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
8167 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8168 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8169 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 8170 | (set_attr "type" "branch") |
0a3bdf9d | 8171 | (set (attr "length") |
6590e19a UW |
8172 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
8173 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8174 | (const_int 4) (const_int 6)) | |
8175 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8176 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8177 | |
0a3bdf9d UW |
8178 | (define_insn "*doloop_si_long" |
8179 | [(set (pc) | |
8180 | (if_then_else | |
7e665d18 | 8181 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 8182 | (const_int 1)) |
4fe6dea8 | 8183 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 8184 | (pc))) |
7e665d18 | 8185 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 8186 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8187 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 8188 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8189 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8190 | { |
8191 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8192 | return "bctr\t%1,%0"; |
0a3bdf9d | 8193 | else |
d40c829f | 8194 | return "bct\t%1,%a0"; |
10bbf137 | 8195 | } |
c7453384 | 8196 | [(set (attr "op_type") |
0a3bdf9d UW |
8197 | (if_then_else (match_operand 0 "register_operand" "") |
8198 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8199 | (set_attr "type" "branch") |
729e750f | 8200 | (set_attr "atype" "agen") |
65b1d8ea AK |
8201 | (set_attr "z10prop" "z10_c") |
8202 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 8203 | |
6590e19a | 8204 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
8205 | [(set (pc) |
8206 | (if_then_else | |
7e665d18 | 8207 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8208 | (const_int 1)) |
8209 | (label_ref (match_operand 0 "" "")) | |
8210 | (pc))) | |
7e665d18 | 8211 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8212 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 8213 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 8214 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8215 | "TARGET_ZARCH" |
0a3bdf9d UW |
8216 | { |
8217 | if (which_alternative != 0) | |
10bbf137 | 8218 | return "#"; |
0a3bdf9d | 8219 | else if (get_attr_length (insn) == 4) |
d40c829f | 8220 | return "brctg\t%1,%l0"; |
0a3bdf9d | 8221 | else |
545d16ff | 8222 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 8223 | } |
6590e19a | 8224 | "&& reload_completed |
0a3bdf9d UW |
8225 | && (! REG_P (operands[2]) |
8226 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8227 | [(set (match_dup 3) (match_dup 1)) |
8228 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
8229 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
8230 | (const_int 0))) | |
8231 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
8232 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8233 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 8234 | (label_ref (match_dup 0)) |
0a3bdf9d | 8235 | (pc)))] |
6590e19a UW |
8236 | "" |
8237 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8238 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8239 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8240 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8241 | (set_attr "type" "branch") |
8242 | (set (attr "length") | |
8243 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8244 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
8245 | |
8246 | ;; | |
8247 | ;;- Unconditional jump instructions. | |
8248 | ;; | |
8249 | ||
8250 | ; | |
8251 | ; jump instruction pattern(s). | |
8252 | ; | |
8253 | ||
6590e19a UW |
8254 | (define_expand "jump" |
8255 | [(match_operand 0 "" "")] | |
9db1d521 | 8256 | "" |
6590e19a UW |
8257 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
8258 | ||
8259 | (define_insn "*jump64" | |
8260 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8261 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8262 | { |
13e58269 | 8263 | if (get_attr_length (insn) == 4) |
d40c829f | 8264 | return "j\t%l0"; |
6590e19a | 8265 | else |
d40c829f | 8266 | return "jg\t%l0"; |
6590e19a UW |
8267 | } |
8268 | [(set_attr "op_type" "RI") | |
8269 | (set_attr "type" "branch") | |
8270 | (set (attr "length") | |
8271 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8272 | (const_int 4) (const_int 6)))]) | |
8273 | ||
8274 | (define_insn "*jump31" | |
8275 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8276 | "!TARGET_CPU_ZARCH" | |
8277 | { | |
8d933e31 AS |
8278 | gcc_assert (get_attr_length (insn) == 4); |
8279 | return "j\t%l0"; | |
10bbf137 | 8280 | } |
9db1d521 | 8281 | [(set_attr "op_type" "RI") |
077dab3b | 8282 | (set_attr "type" "branch") |
13e58269 | 8283 | (set (attr "length") |
6590e19a UW |
8284 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
8285 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8286 | (const_int 4) (const_int 6)) | |
8287 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8288 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
8289 | |
8290 | ; | |
8291 | ; indirect-jump instruction pattern(s). | |
8292 | ; | |
8293 | ||
8294 | (define_insn "indirect_jump" | |
4fe6dea8 | 8295 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 8296 | "" |
f314b9b1 UW |
8297 | { |
8298 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8299 | return "br\t%0"; |
f314b9b1 | 8300 | else |
d40c829f | 8301 | return "b\t%a0"; |
10bbf137 | 8302 | } |
c7453384 | 8303 | [(set (attr "op_type") |
f314b9b1 UW |
8304 | (if_then_else (match_operand 0 "register_operand" "") |
8305 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8306 | (set_attr "type" "branch") |
729e750f | 8307 | (set_attr "atype" "agen")]) |
9db1d521 HP |
8308 | |
8309 | ; | |
f314b9b1 | 8310 | ; casesi instruction pattern(s). |
9db1d521 HP |
8311 | ; |
8312 | ||
f314b9b1 | 8313 | (define_insn "casesi_jump" |
4fe6dea8 | 8314 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 8315 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 8316 | "" |
9db1d521 | 8317 | { |
f314b9b1 | 8318 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 8319 | return "br\t%0"; |
f314b9b1 | 8320 | else |
d40c829f | 8321 | return "b\t%a0"; |
10bbf137 | 8322 | } |
c7453384 | 8323 | [(set (attr "op_type") |
f314b9b1 UW |
8324 | (if_then_else (match_operand 0 "register_operand" "") |
8325 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8326 | (set_attr "type" "branch") |
8327 | (set_attr "atype" "agen")]) | |
9db1d521 | 8328 | |
f314b9b1 UW |
8329 | (define_expand "casesi" |
8330 | [(match_operand:SI 0 "general_operand" "") | |
8331 | (match_operand:SI 1 "general_operand" "") | |
8332 | (match_operand:SI 2 "general_operand" "") | |
8333 | (label_ref (match_operand 3 "" "")) | |
8334 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 8335 | "" |
f314b9b1 UW |
8336 | { |
8337 | rtx index = gen_reg_rtx (SImode); | |
8338 | rtx base = gen_reg_rtx (Pmode); | |
8339 | rtx target = gen_reg_rtx (Pmode); | |
8340 | ||
8341 | emit_move_insn (index, operands[0]); | |
8342 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
8343 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 8344 | operands[4]); |
f314b9b1 UW |
8345 | |
8346 | if (Pmode != SImode) | |
8347 | index = convert_to_mode (Pmode, index, 1); | |
8348 | if (GET_CODE (index) != REG) | |
8349 | index = copy_to_mode_reg (Pmode, index); | |
8350 | ||
8351 | if (TARGET_64BIT) | |
8352 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
8353 | else | |
a556fd39 | 8354 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 8355 | |
f314b9b1 UW |
8356 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
8357 | ||
542a8afa | 8358 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
8359 | emit_move_insn (target, index); |
8360 | ||
8361 | if (flag_pic) | |
8362 | target = gen_rtx_PLUS (Pmode, base, target); | |
8363 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
8364 | ||
8365 | DONE; | |
10bbf137 | 8366 | }) |
9db1d521 HP |
8367 | |
8368 | ||
8369 | ;; | |
8370 | ;;- Jump to subroutine. | |
8371 | ;; | |
8372 | ;; | |
8373 | ||
8374 | ; | |
8375 | ; untyped call instruction pattern(s). | |
8376 | ; | |
8377 | ||
8378 | ;; Call subroutine returning any type. | |
8379 | (define_expand "untyped_call" | |
8380 | [(parallel [(call (match_operand 0 "" "") | |
8381 | (const_int 0)) | |
8382 | (match_operand 1 "" "") | |
8383 | (match_operand 2 "" "")])] | |
8384 | "" | |
9db1d521 HP |
8385 | { |
8386 | int i; | |
8387 | ||
8388 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
8389 | ||
8390 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
8391 | { | |
8392 | rtx set = XVECEXP (operands[2], 0, i); | |
8393 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
8394 | } | |
8395 | ||
8396 | /* The optimizer does not know that the call sets the function value | |
8397 | registers we stored in the result block. We avoid problems by | |
8398 | claiming that all hard registers are used and clobbered at this | |
8399 | point. */ | |
8400 | emit_insn (gen_blockage ()); | |
8401 | ||
8402 | DONE; | |
10bbf137 | 8403 | }) |
9db1d521 HP |
8404 | |
8405 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
8406 | ;; all of memory. This blocks insns from being moved across this point. | |
8407 | ||
8408 | (define_insn "blockage" | |
10bbf137 | 8409 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 8410 | "" |
4023fb28 | 8411 | "" |
d5869ca0 UW |
8412 | [(set_attr "type" "none") |
8413 | (set_attr "length" "0")]) | |
4023fb28 | 8414 | |
9db1d521 | 8415 | ; |
ed9676cf | 8416 | ; sibcall patterns |
9db1d521 HP |
8417 | ; |
8418 | ||
ed9676cf | 8419 | (define_expand "sibcall" |
44b8152b | 8420 | [(call (match_operand 0 "" "") |
ed9676cf | 8421 | (match_operand 1 "" ""))] |
9db1d521 | 8422 | "" |
9db1d521 | 8423 | { |
ed9676cf AK |
8424 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
8425 | DONE; | |
8426 | }) | |
9db1d521 | 8427 | |
ed9676cf | 8428 | (define_insn "*sibcall_br" |
ae156f85 | 8429 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8430 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 8431 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8432 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
8433 | "br\t%%r1" | |
8434 | [(set_attr "op_type" "RR") | |
8435 | (set_attr "type" "branch") | |
8436 | (set_attr "atype" "agen")]) | |
9db1d521 | 8437 | |
ed9676cf AK |
8438 | (define_insn "*sibcall_brc" |
8439 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8440 | (match_operand 1 "const_int_operand" "n"))] | |
8441 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8442 | "j\t%0" | |
8443 | [(set_attr "op_type" "RI") | |
8444 | (set_attr "type" "branch")]) | |
9db1d521 | 8445 | |
ed9676cf AK |
8446 | (define_insn "*sibcall_brcl" |
8447 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8448 | (match_operand 1 "const_int_operand" "n"))] | |
8449 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8450 | "jg\t%0" | |
8451 | [(set_attr "op_type" "RIL") | |
8452 | (set_attr "type" "branch")]) | |
44b8152b | 8453 | |
ed9676cf AK |
8454 | ; |
8455 | ; sibcall_value patterns | |
8456 | ; | |
9e8327e3 | 8457 | |
ed9676cf AK |
8458 | (define_expand "sibcall_value" |
8459 | [(set (match_operand 0 "" "") | |
8460 | (call (match_operand 1 "" "") | |
8461 | (match_operand 2 "" "")))] | |
8462 | "" | |
8463 | { | |
8464 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 8465 | DONE; |
10bbf137 | 8466 | }) |
9db1d521 | 8467 | |
ed9676cf AK |
8468 | (define_insn "*sibcall_value_br" |
8469 | [(set (match_operand 0 "" "") | |
ae156f85 | 8470 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8471 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 8472 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8473 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
8474 | "br\t%%r1" | |
8475 | [(set_attr "op_type" "RR") | |
8476 | (set_attr "type" "branch") | |
8477 | (set_attr "atype" "agen")]) | |
8478 | ||
8479 | (define_insn "*sibcall_value_brc" | |
8480 | [(set (match_operand 0 "" "") | |
8481 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8482 | (match_operand 2 "const_int_operand" "n")))] | |
8483 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8484 | "j\t%1" | |
8485 | [(set_attr "op_type" "RI") | |
8486 | (set_attr "type" "branch")]) | |
8487 | ||
8488 | (define_insn "*sibcall_value_brcl" | |
8489 | [(set (match_operand 0 "" "") | |
8490 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8491 | (match_operand 2 "const_int_operand" "n")))] | |
8492 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8493 | "jg\t%1" | |
8494 | [(set_attr "op_type" "RIL") | |
8495 | (set_attr "type" "branch")]) | |
8496 | ||
8497 | ||
8498 | ; | |
8499 | ; call instruction pattern(s). | |
8500 | ; | |
8501 | ||
8502 | (define_expand "call" | |
8503 | [(call (match_operand 0 "" "") | |
8504 | (match_operand 1 "" "")) | |
8505 | (use (match_operand 2 "" ""))] | |
44b8152b | 8506 | "" |
ed9676cf | 8507 | { |
2f7e5a0d | 8508 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
8509 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
8510 | DONE; | |
8511 | }) | |
44b8152b | 8512 | |
9e8327e3 UW |
8513 | (define_insn "*bras" |
8514 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8515 | (match_operand 1 "const_int_operand" "n")) | |
8516 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8517 | "!SIBLING_CALL_P (insn) |
8518 | && TARGET_SMALL_EXEC | |
ed9676cf | 8519 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 8520 | "bras\t%2,%0" |
9db1d521 | 8521 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8522 | (set_attr "type" "jsr") |
8523 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8524 | |
9e8327e3 UW |
8525 | (define_insn "*brasl" |
8526 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8527 | (match_operand 1 "const_int_operand" "n")) | |
8528 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8529 | "!SIBLING_CALL_P (insn) |
8530 | && TARGET_CPU_ZARCH | |
ed9676cf | 8531 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8532 | "brasl\t%2,%0" |
8533 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8534 | (set_attr "type" "jsr") |
8535 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8536 | |
9e8327e3 | 8537 | (define_insn "*basr" |
4fe6dea8 | 8538 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
8539 | (match_operand 1 "const_int_operand" "n")) |
8540 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 8541 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8542 | { |
8543 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8544 | return "basr\t%2,%0"; | |
8545 | else | |
8546 | return "bas\t%2,%a0"; | |
8547 | } | |
8548 | [(set (attr "op_type") | |
8549 | (if_then_else (match_operand 0 "register_operand" "") | |
8550 | (const_string "RR") (const_string "RX"))) | |
8551 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8552 | (set_attr "atype" "agen") |
8553 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
8554 | |
8555 | ; | |
8556 | ; call_value instruction pattern(s). | |
8557 | ; | |
8558 | ||
8559 | (define_expand "call_value" | |
44b8152b UW |
8560 | [(set (match_operand 0 "" "") |
8561 | (call (match_operand 1 "" "") | |
8562 | (match_operand 2 "" ""))) | |
8563 | (use (match_operand 3 "" ""))] | |
9db1d521 | 8564 | "" |
9db1d521 | 8565 | { |
2f7e5a0d | 8566 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 8567 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 8568 | DONE; |
10bbf137 | 8569 | }) |
9db1d521 | 8570 | |
9e8327e3 | 8571 | (define_insn "*bras_r" |
c19ec8f9 | 8572 | [(set (match_operand 0 "" "") |
9e8327e3 | 8573 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 8574 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 8575 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
8576 | "!SIBLING_CALL_P (insn) |
8577 | && TARGET_SMALL_EXEC | |
ed9676cf | 8578 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8579 | "bras\t%3,%1" |
9db1d521 | 8580 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8581 | (set_attr "type" "jsr") |
8582 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8583 | |
9e8327e3 | 8584 | (define_insn "*brasl_r" |
c19ec8f9 | 8585 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8586 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8587 | (match_operand 2 "const_int_operand" "n"))) | |
8588 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
8589 | "!SIBLING_CALL_P (insn) |
8590 | && TARGET_CPU_ZARCH | |
ed9676cf | 8591 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8592 | "brasl\t%3,%1" |
8593 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8594 | (set_attr "type" "jsr") |
8595 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8596 | |
9e8327e3 | 8597 | (define_insn "*basr_r" |
c19ec8f9 | 8598 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8599 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8600 | (match_operand 2 "const_int_operand" "n"))) |
8601 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 8602 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8603 | { |
8604 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8605 | return "basr\t%3,%1"; | |
8606 | else | |
8607 | return "bas\t%3,%a1"; | |
8608 | } | |
8609 | [(set (attr "op_type") | |
8610 | (if_then_else (match_operand 1 "register_operand" "") | |
8611 | (const_string "RR") (const_string "RX"))) | |
8612 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8613 | (set_attr "atype" "agen") |
8614 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8615 | |
fd3cd001 UW |
8616 | ;; |
8617 | ;;- Thread-local storage support. | |
8618 | ;; | |
8619 | ||
c5aa1d12 | 8620 | (define_expand "get_tp_64" |
ae156f85 | 8621 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] |
fd3cd001 | 8622 | "TARGET_64BIT" |
c5aa1d12 | 8623 | "") |
fd3cd001 | 8624 | |
c5aa1d12 | 8625 | (define_expand "get_tp_31" |
ae156f85 | 8626 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] |
fd3cd001 | 8627 | "!TARGET_64BIT" |
c5aa1d12 | 8628 | "") |
fd3cd001 | 8629 | |
c5aa1d12 | 8630 | (define_expand "set_tp_64" |
ae156f85 AS |
8631 | [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) |
8632 | (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 8633 | "TARGET_64BIT" |
c5aa1d12 | 8634 | "") |
fd3cd001 | 8635 | |
c5aa1d12 | 8636 | (define_expand "set_tp_31" |
ae156f85 AS |
8637 | [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) |
8638 | (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 8639 | "!TARGET_64BIT" |
c5aa1d12 UW |
8640 | "") |
8641 | ||
8642 | (define_insn "*set_tp" | |
ae156f85 | 8643 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
8644 | "" |
8645 | "" | |
8646 | [(set_attr "type" "none") | |
8647 | (set_attr "length" "0")]) | |
c7453384 | 8648 | |
fd3cd001 UW |
8649 | (define_insn "*tls_load_64" |
8650 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 8651 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
8652 | (match_operand:DI 2 "" "")] |
8653 | UNSPEC_TLS_LOAD))] | |
8654 | "TARGET_64BIT" | |
d40c829f | 8655 | "lg\t%0,%1%J2" |
9381e3f1 WG |
8656 | [(set_attr "op_type" "RXE") |
8657 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
8658 | |
8659 | (define_insn "*tls_load_31" | |
d3632d41 UW |
8660 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
8661 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
8662 | (match_operand:SI 2 "" "")] |
8663 | UNSPEC_TLS_LOAD))] | |
8664 | "!TARGET_64BIT" | |
d3632d41 | 8665 | "@ |
d40c829f UW |
8666 | l\t%0,%1%J2 |
8667 | ly\t%0,%1%J2" | |
9381e3f1 | 8668 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 8669 | (set_attr "type" "load") |
9381e3f1 | 8670 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 8671 | |
9e8327e3 | 8672 | (define_insn "*bras_tls" |
c19ec8f9 | 8673 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8674 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8675 | (match_operand 2 "const_int_operand" "n"))) | |
8676 | (clobber (match_operand 3 "register_operand" "=r")) | |
8677 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8678 | "!SIBLING_CALL_P (insn) |
8679 | && TARGET_SMALL_EXEC | |
ed9676cf | 8680 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8681 | "bras\t%3,%1%J4" |
fd3cd001 | 8682 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8683 | (set_attr "type" "jsr") |
8684 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8685 | |
9e8327e3 | 8686 | (define_insn "*brasl_tls" |
c19ec8f9 | 8687 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8688 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8689 | (match_operand 2 "const_int_operand" "n"))) | |
8690 | (clobber (match_operand 3 "register_operand" "=r")) | |
8691 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
8692 | "!SIBLING_CALL_P (insn) |
8693 | && TARGET_CPU_ZARCH | |
ed9676cf | 8694 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8695 | "brasl\t%3,%1%J4" |
8696 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8697 | (set_attr "type" "jsr") |
8698 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8699 | |
9e8327e3 | 8700 | (define_insn "*basr_tls" |
c19ec8f9 | 8701 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8702 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8703 | (match_operand 2 "const_int_operand" "n"))) |
8704 | (clobber (match_operand 3 "register_operand" "=r")) | |
8705 | (use (match_operand 4 "" ""))] | |
ed9676cf | 8706 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8707 | { |
8708 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8709 | return "basr\t%3,%1%J4"; | |
8710 | else | |
8711 | return "bas\t%3,%a1%J4"; | |
8712 | } | |
8713 | [(set (attr "op_type") | |
8714 | (if_then_else (match_operand 1 "register_operand" "") | |
8715 | (const_string "RR") (const_string "RX"))) | |
8716 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8717 | (set_attr "atype" "agen") |
8718 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 8719 | |
e0374221 AS |
8720 | ;; |
8721 | ;;- Atomic operations | |
8722 | ;; | |
8723 | ||
8724 | ; | |
8725 | ; memory barrier pattern. | |
8726 | ; | |
8727 | ||
8728 | (define_expand "memory_barrier" | |
1a8c13b3 UB |
8729 | [(set (match_dup 0) |
8730 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] | |
e0374221 AS |
8731 | "" |
8732 | { | |
1a8c13b3 | 8733 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); |
e0374221 AS |
8734 | MEM_VOLATILE_P (operands[0]) = 1; |
8735 | }) | |
8736 | ||
8737 | (define_insn "*memory_barrier" | |
8738 | [(set (match_operand:BLK 0 "" "") | |
1a8c13b3 | 8739 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 AS |
8740 | "" |
8741 | "bcr\t15,0" | |
8742 | [(set_attr "op_type" "RR")]) | |
1a8c13b3 | 8743 | |
9381e3f1 WG |
8744 | ; Although bcr is superscalar on Z10, this variant will never become part of |
8745 | ; an execution group. | |
e0374221 AS |
8746 | |
8747 | ; | |
8748 | ; compare and swap patterns. | |
8749 | ; | |
8750 | ||
8006eaa6 AS |
8751 | (define_expand "sync_compare_and_swap<mode>" |
8752 | [(parallel | |
8753 | [(set (match_operand:TDSI 0 "register_operand" "") | |
8754 | (match_operand:TDSI 1 "memory_operand" "")) | |
8755 | (set (match_dup 1) | |
8756 | (unspec_volatile:TDSI | |
8757 | [(match_dup 1) | |
8758 | (match_operand:TDSI 2 "register_operand" "") | |
8759 | (match_operand:TDSI 3 "register_operand" "")] | |
8760 | UNSPECV_CAS)) | |
8761 | (set (reg:CCZ1 CC_REGNUM) | |
8762 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
8763 | "") | |
e0374221 | 8764 | |
3093f076 AS |
8765 | (define_expand "sync_compare_and_swap<mode>" |
8766 | [(parallel | |
8767 | [(set (match_operand:HQI 0 "register_operand" "") | |
8768 | (match_operand:HQI 1 "memory_operand" "")) | |
8769 | (set (match_dup 1) | |
8770 | (unspec_volatile:HQI | |
8771 | [(match_dup 1) | |
8772 | (match_operand:HQI 2 "general_operand" "") | |
8773 | (match_operand:HQI 3 "general_operand" "")] | |
8774 | UNSPECV_CAS)) | |
4a77c72b | 8775 | (clobber (reg:CC CC_REGNUM))])] |
3093f076 | 8776 | "" |
9381e3f1 | 8777 | "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], |
3093f076 AS |
8778 | operands[2], operands[3]); DONE;") |
8779 | ||
43a09b63 | 8780 | ; cds, cdsg |
8006eaa6 | 8781 | (define_insn "*sync_compare_and_swap<mode>" |
9602b6a1 AK |
8782 | [(set (match_operand:DW 0 "register_operand" "=r") |
8783 | (match_operand:DW 1 "memory_operand" "+Q")) | |
8006eaa6 | 8784 | (set (match_dup 1) |
9602b6a1 | 8785 | (unspec_volatile:DW |
8006eaa6 | 8786 | [(match_dup 1) |
9602b6a1 AK |
8787 | (match_operand:DW 2 "register_operand" "0") |
8788 | (match_operand:DW 3 "register_operand" "r")] | |
8006eaa6 AS |
8789 | UNSPECV_CAS)) |
8790 | (set (reg:CCZ1 CC_REGNUM) | |
8791 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
8792 | "" | |
8793 | "cds<tg>\t%0,%3,%S1" | |
8794 | [(set_attr "op_type" "RS<TE>") | |
8795 | (set_attr "type" "sem")]) | |
8796 | ||
43a09b63 | 8797 | ; cs, csg |
8006eaa6 | 8798 | (define_insn "*sync_compare_and_swap<mode>" |
e0374221 AS |
8799 | [(set (match_operand:GPR 0 "register_operand" "=r") |
8800 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
8801 | (set (match_dup 1) | |
8802 | (unspec_volatile:GPR | |
8803 | [(match_dup 1) | |
8804 | (match_operand:GPR 2 "register_operand" "0") | |
8805 | (match_operand:GPR 3 "register_operand" "r")] | |
8806 | UNSPECV_CAS)) | |
69950452 AS |
8807 | (set (reg:CCZ1 CC_REGNUM) |
8808 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 8809 | "" |
e0374221 AS |
8810 | "cs<g>\t%0,%3,%S1" |
8811 | [(set_attr "op_type" "RS<E>") | |
8812 | (set_attr "type" "sem")]) | |
8813 | ||
8814 | ||
45d18331 AS |
8815 | ; |
8816 | ; Other atomic instruction patterns. | |
8817 | ; | |
8818 | ||
8819 | (define_expand "sync_lock_test_and_set<mode>" | |
8820 | [(match_operand:HQI 0 "register_operand") | |
8821 | (match_operand:HQI 1 "memory_operand") | |
8822 | (match_operand:HQI 2 "general_operand")] | |
8823 | "" | |
9381e3f1 | 8824 | "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], |
45d18331 AS |
8825 | operands[2], false); DONE;") |
8826 | ||
65b1d8ea AK |
8827 | ; z196 load and add, xor, or and and instructions |
8828 | ||
8829 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
8830 | (define_insn "sync_<atomic><mode>" | |
8831 | [(parallel | |
8832 | [(set (match_operand:GPR 0 "memory_operand" "+QS") | |
8833 | (unspec_volatile:GPR | |
8834 | [(ATOMIC_Z196:GPR (match_dup 0) | |
8835 | (match_operand:GPR 1 "general_operand" "d"))] | |
8836 | UNSPECV_ATOMIC_OP)) | |
8837 | (clobber (match_scratch:GPR 2 "=d")) | |
8838 | (clobber (reg:CC CC_REGNUM))])] | |
8839 | "TARGET_Z196" | |
8840 | "la<noxa><g>\t%2,%1,%0") | |
8841 | ||
8842 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
8843 | (define_insn "sync_old_<atomic><mode>" | |
8844 | [(parallel | |
8845 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8846 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
8847 | (set (match_dup 1) | |
8848 | (unspec_volatile | |
8849 | [(ATOMIC_Z196:GPR (match_dup 1) | |
8850 | (match_operand:GPR 2 "general_operand" "d"))] | |
8851 | UNSPECV_ATOMIC_OP)) | |
8852 | (clobber (reg:CC CC_REGNUM))])] | |
8853 | "TARGET_Z196" | |
8854 | "la<noxa><g>\t%0,%2,%1") | |
8855 | ||
8856 | ||
45d18331 AS |
8857 | (define_expand "sync_<atomic><mode>" |
8858 | [(set (match_operand:HQI 0 "memory_operand") | |
8859 | (ATOMIC:HQI (match_dup 0) | |
8860 | (match_operand:HQI 1 "general_operand")))] | |
8861 | "" | |
9381e3f1 | 8862 | "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], |
45d18331 AS |
8863 | operands[1], false); DONE;") |
8864 | ||
8865 | (define_expand "sync_old_<atomic><mode>" | |
8866 | [(set (match_operand:HQI 0 "register_operand") | |
8867 | (match_operand:HQI 1 "memory_operand")) | |
8868 | (set (match_dup 1) | |
8869 | (ATOMIC:HQI (match_dup 1) | |
8870 | (match_operand:HQI 2 "general_operand")))] | |
8871 | "" | |
9381e3f1 | 8872 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], |
45d18331 AS |
8873 | operands[2], false); DONE;") |
8874 | ||
8875 | (define_expand "sync_new_<atomic><mode>" | |
8876 | [(set (match_operand:HQI 0 "register_operand") | |
8877 | (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") | |
9381e3f1 | 8878 | (match_operand:HQI 2 "general_operand"))) |
45d18331 AS |
8879 | (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] |
8880 | "" | |
9381e3f1 | 8881 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], |
45d18331 AS |
8882 | operands[2], true); DONE;") |
8883 | ||
9db1d521 HP |
8884 | ;; |
8885 | ;;- Miscellaneous instructions. | |
8886 | ;; | |
8887 | ||
8888 | ; | |
8889 | ; allocate stack instruction pattern(s). | |
8890 | ; | |
8891 | ||
8892 | (define_expand "allocate_stack" | |
ef44a6ff UW |
8893 | [(match_operand 0 "general_operand" "") |
8894 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 8895 | "TARGET_BACKCHAIN" |
9db1d521 | 8896 | { |
ef44a6ff | 8897 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 8898 | |
ef44a6ff UW |
8899 | emit_move_insn (temp, s390_back_chain_rtx ()); |
8900 | anti_adjust_stack (operands[1]); | |
8901 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 8902 | |
ef44a6ff UW |
8903 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
8904 | DONE; | |
10bbf137 | 8905 | }) |
9db1d521 HP |
8906 | |
8907 | ||
8908 | ; | |
43ab026f | 8909 | ; setjmp instruction pattern. |
9db1d521 HP |
8910 | ; |
8911 | ||
9db1d521 | 8912 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 8913 | [(match_operand 0 "" "")] |
f314b9b1 | 8914 | "flag_pic" |
9db1d521 | 8915 | { |
585539a1 | 8916 | emit_insn (s390_load_got ()); |
c41c1387 | 8917 | emit_use (pic_offset_table_rtx); |
9db1d521 | 8918 | DONE; |
fd7643fb | 8919 | }) |
9db1d521 | 8920 | |
9db1d521 HP |
8921 | ;; These patterns say how to save and restore the stack pointer. We need not |
8922 | ;; save the stack pointer at function level since we are careful to | |
8923 | ;; preserve the backchain. At block level, we have to restore the backchain | |
8924 | ;; when we restore the stack pointer. | |
8925 | ;; | |
8926 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
8927 | ;; backchain and restore both. Note that in the nonlocal case, the | |
8928 | ;; save area is a memory location. | |
8929 | ||
8930 | (define_expand "save_stack_function" | |
8931 | [(match_operand 0 "general_operand" "") | |
8932 | (match_operand 1 "general_operand" "")] | |
8933 | "" | |
8934 | "DONE;") | |
8935 | ||
8936 | (define_expand "restore_stack_function" | |
8937 | [(match_operand 0 "general_operand" "") | |
8938 | (match_operand 1 "general_operand" "")] | |
8939 | "" | |
8940 | "DONE;") | |
8941 | ||
8942 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
8943 | [(match_operand 0 "register_operand" "") |
8944 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 8945 | "TARGET_BACKCHAIN" |
9db1d521 | 8946 | { |
ef44a6ff UW |
8947 | rtx temp = gen_reg_rtx (Pmode); |
8948 | ||
8949 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
8950 | emit_move_insn (operands[0], operands[1]); | |
8951 | emit_move_insn (s390_back_chain_rtx (), temp); | |
8952 | ||
8953 | DONE; | |
10bbf137 | 8954 | }) |
9db1d521 HP |
8955 | |
8956 | (define_expand "save_stack_nonlocal" | |
8957 | [(match_operand 0 "memory_operand" "") | |
8958 | (match_operand 1 "register_operand" "")] | |
8959 | "" | |
9db1d521 | 8960 | { |
ef44a6ff UW |
8961 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
8962 | ||
8963 | /* Copy the backchain to the first word, sp to the second and the | |
8964 | literal pool base to the third. */ | |
8965 | ||
9602b6a1 AK |
8966 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
8967 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
8968 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
8969 | ||
b3d31392 | 8970 | if (TARGET_BACKCHAIN) |
9602b6a1 | 8971 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 8972 | |
9602b6a1 AK |
8973 | emit_move_insn (save_sp, operands[1]); |
8974 | emit_move_insn (save_bp, base); | |
9db1d521 | 8975 | |
9db1d521 | 8976 | DONE; |
10bbf137 | 8977 | }) |
9db1d521 HP |
8978 | |
8979 | (define_expand "restore_stack_nonlocal" | |
8980 | [(match_operand 0 "register_operand" "") | |
8981 | (match_operand 1 "memory_operand" "")] | |
8982 | "" | |
9db1d521 | 8983 | { |
490ceeb4 | 8984 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 8985 | rtx temp = NULL_RTX; |
9db1d521 | 8986 | |
43ab026f | 8987 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 8988 | literal pool base from the third. */ |
43ab026f | 8989 | |
9602b6a1 AK |
8990 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
8991 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
8992 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
8993 | ||
b3d31392 | 8994 | if (TARGET_BACKCHAIN) |
9602b6a1 | 8995 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 8996 | |
9602b6a1 AK |
8997 | emit_move_insn (base, save_bp); |
8998 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
8999 | |
9000 | if (temp) | |
9001 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9002 | ||
c41c1387 | 9003 | emit_use (base); |
9db1d521 | 9004 | DONE; |
10bbf137 | 9005 | }) |
9db1d521 | 9006 | |
7bcebb25 AK |
9007 | (define_expand "exception_receiver" |
9008 | [(const_int 0)] | |
9009 | "" | |
9010 | { | |
9011 | s390_set_has_landing_pad_p (true); | |
9012 | DONE; | |
9013 | }) | |
9db1d521 HP |
9014 | |
9015 | ; | |
9016 | ; nop instruction pattern(s). | |
9017 | ; | |
9018 | ||
9019 | (define_insn "nop" | |
9020 | [(const_int 0)] | |
9021 | "" | |
d40c829f | 9022 | "lr\t0,0" |
729e750f WG |
9023 | [(set_attr "op_type" "RR") |
9024 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 9025 | |
d277db6b WG |
9026 | (define_insn "nop1" |
9027 | [(const_int 1)] | |
9028 | "" | |
9029 | "lr\t1,1" | |
9030 | [(set_attr "op_type" "RR")]) | |
9031 | ||
9db1d521 HP |
9032 | |
9033 | ; | |
9034 | ; Special literal pool access instruction pattern(s). | |
9035 | ; | |
9036 | ||
416cf582 UW |
9037 | (define_insn "*pool_entry" |
9038 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
9039 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 9040 | "" |
9db1d521 | 9041 | { |
416cf582 UW |
9042 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
9043 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 9044 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
9045 | return ""; |
9046 | } | |
b628bd8e | 9047 | [(set (attr "length") |
416cf582 | 9048 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 9049 | |
9bb86f41 UW |
9050 | (define_insn "pool_align" |
9051 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
9052 | UNSPECV_POOL_ALIGN)] | |
9053 | "" | |
9054 | ".align\t%0" | |
b628bd8e | 9055 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 9056 | |
9bb86f41 UW |
9057 | (define_insn "pool_section_start" |
9058 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
9059 | "" | |
9060 | ".section\t.rodata" | |
b628bd8e | 9061 | [(set_attr "length" "0")]) |
b2ccb744 | 9062 | |
9bb86f41 UW |
9063 | (define_insn "pool_section_end" |
9064 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
9065 | "" | |
b2ccb744 | 9066 | ".previous" |
b628bd8e | 9067 | [(set_attr "length" "0")]) |
b2ccb744 | 9068 | |
5af2f3d3 | 9069 | (define_insn "main_base_31_small" |
9e8327e3 UW |
9070 | [(set (match_operand 0 "register_operand" "=a") |
9071 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9072 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9073 | "basr\t%0,0" |
9074 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
9075 | (set_attr "type" "la") |
9076 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9077 | |
9078 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
9079 | [(set (match_operand 0 "register_operand" "=a") |
9080 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 9081 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 9082 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 9083 | "bras\t%0,%2" |
65b1d8ea AK |
9084 | [(set_attr "op_type" "RI") |
9085 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9086 | |
9087 | (define_insn "main_base_64" | |
9e8327e3 UW |
9088 | [(set (match_operand 0 "register_operand" "=a") |
9089 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9090 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9091 | "larl\t%0,%1" |
9092 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 9093 | (set_attr "type" "larl") |
729e750f | 9094 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
9095 | |
9096 | (define_insn "main_pool" | |
585539a1 UW |
9097 | [(set (match_operand 0 "register_operand" "=a") |
9098 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
9099 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
9100 | { |
9101 | gcc_unreachable (); | |
9102 | } | |
9381e3f1 | 9103 | [(set (attr "type") |
ea77e738 UW |
9104 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
9105 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 9106 | |
aee4e0db | 9107 | (define_insn "reload_base_31" |
9e8327e3 UW |
9108 | [(set (match_operand 0 "register_operand" "=a") |
9109 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9110 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9111 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 9112 | [(set_attr "length" "6") |
65b1d8ea AK |
9113 | (set_attr "type" "la") |
9114 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 9115 | |
aee4e0db | 9116 | (define_insn "reload_base_64" |
9e8327e3 UW |
9117 | [(set (match_operand 0 "register_operand" "=a") |
9118 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9119 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9120 | "larl\t%0,%1" |
aee4e0db | 9121 | [(set_attr "op_type" "RIL") |
9381e3f1 | 9122 | (set_attr "type" "larl") |
729e750f | 9123 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 9124 | |
aee4e0db | 9125 | (define_insn "pool" |
fd7643fb | 9126 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 9127 | "" |
8d933e31 AS |
9128 | { |
9129 | gcc_unreachable (); | |
9130 | } | |
b628bd8e | 9131 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 9132 | |
4023fb28 UW |
9133 | ;; |
9134 | ;; Insns related to generating the function prologue and epilogue. | |
9135 | ;; | |
9136 | ||
9137 | ||
9138 | (define_expand "prologue" | |
9139 | [(use (const_int 0))] | |
9140 | "" | |
10bbf137 | 9141 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
9142 | |
9143 | (define_expand "epilogue" | |
9144 | [(use (const_int 1))] | |
9145 | "" | |
ed9676cf AK |
9146 | "s390_emit_epilogue (false); DONE;") |
9147 | ||
9148 | (define_expand "sibcall_epilogue" | |
9149 | [(use (const_int 0))] | |
9150 | "" | |
9151 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 9152 | |
9e8327e3 | 9153 | (define_insn "*return" |
4023fb28 | 9154 | [(return) |
9e8327e3 UW |
9155 | (use (match_operand 0 "register_operand" "a"))] |
9156 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9157 | "br\t%0" |
4023fb28 | 9158 | [(set_attr "op_type" "RR") |
c7453384 | 9159 | (set_attr "type" "jsr") |
077dab3b | 9160 | (set_attr "atype" "agen")]) |
4023fb28 | 9161 | |
4023fb28 | 9162 | |
c7453384 | 9163 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 9164 | ;; pointer. This is used for compatibility. |
c7453384 EC |
9165 | |
9166 | (define_expand "ptr_extend" | |
9167 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9168 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 9169 | "TARGET_64BIT" |
c7453384 | 9170 | { |
c7453384 EC |
9171 | emit_insn (gen_anddi3 (operands[0], |
9172 | gen_lowpart (DImode, operands[1]), | |
9173 | GEN_INT (0x7fffffff))); | |
c7453384 | 9174 | DONE; |
10bbf137 | 9175 | }) |
4798630c D |
9176 | |
9177 | ;; Instruction definition to expand eh_return macro to support | |
9178 | ;; swapping in special linkage return addresses. | |
9179 | ||
9180 | (define_expand "eh_return" | |
9181 | [(use (match_operand 0 "register_operand" ""))] | |
9182 | "TARGET_TPF" | |
9183 | { | |
9184 | s390_emit_tpf_eh_return (operands[0]); | |
9185 | DONE; | |
9186 | }) | |
9187 | ||
7b8acc34 AK |
9188 | ; |
9189 | ; Stack Protector Patterns | |
9190 | ; | |
9191 | ||
9192 | (define_expand "stack_protect_set" | |
9193 | [(set (match_operand 0 "memory_operand" "") | |
9194 | (match_operand 1 "memory_operand" ""))] | |
9195 | "" | |
9196 | { | |
9197 | #ifdef TARGET_THREAD_SSP_OFFSET | |
9198 | operands[1] | |
9199 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9200 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9201 | #endif | |
9202 | if (TARGET_64BIT) | |
9203 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
9204 | else | |
9205 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
9206 | ||
9207 | DONE; | |
9208 | }) | |
9209 | ||
9210 | (define_insn "stack_protect_set<mode>" | |
9211 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
9212 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
9213 | "" | |
9214 | "mvc\t%O0(%G0,%R0),%S1" | |
9215 | [(set_attr "op_type" "SS")]) | |
9216 | ||
9217 | (define_expand "stack_protect_test" | |
9218 | [(set (reg:CC CC_REGNUM) | |
9219 | (compare (match_operand 0 "memory_operand" "") | |
9220 | (match_operand 1 "memory_operand" ""))) | |
9221 | (match_operand 2 "" "")] | |
9222 | "" | |
9223 | { | |
f90b7a5a | 9224 | rtx cc_reg, test; |
7b8acc34 AK |
9225 | #ifdef TARGET_THREAD_SSP_OFFSET |
9226 | operands[1] | |
9227 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9228 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9229 | #endif | |
7b8acc34 AK |
9230 | if (TARGET_64BIT) |
9231 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
9232 | else | |
9233 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
9234 | ||
f90b7a5a PB |
9235 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
9236 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
9237 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
9238 | DONE; |
9239 | }) | |
9240 | ||
9241 | (define_insn "stack_protect_test<mode>" | |
9242 | [(set (reg:CCZ CC_REGNUM) | |
9243 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
9244 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
9245 | "" | |
9246 | "clc\t%O0(%G0,%R0),%S1" | |
9247 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
9248 | |
9249 | ; This is used in s390_emit_prologue in order to prevent insns | |
9250 | ; adjusting the stack pointer to be moved over insns writing stack | |
9251 | ; slots using a copy of the stack pointer in a different register. | |
9252 | (define_insn "stack_tie" | |
9253 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
9254 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
9255 | "" | |
9256 | "" | |
9257 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
9258 | |
9259 | ||
9260 | ; | |
9261 | ; Data prefetch patterns | |
9262 | ; | |
9263 | ||
9264 | (define_insn "prefetch" | |
22d72dbc AK |
9265 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
9266 | (match_operand:SI 1 "const_int_operand" " n,n") | |
9267 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
9268 | "TARGET_Z10" | |
963fc8d0 | 9269 | { |
4fe6dea8 AK |
9270 | switch (which_alternative) |
9271 | { | |
9272 | case 0: | |
4fe6dea8 | 9273 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 9274 | case 1: |
4fe6dea8 AK |
9275 | if (larl_operand (operands[0], Pmode)) |
9276 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
9277 | default: | |
9278 | ||
9279 | /* This might be reached for symbolic operands with an odd | |
9280 | addend. We simply omit the prefetch for such rare cases. */ | |
9281 | ||
9282 | return ""; | |
9283 | } | |
9381e3f1 | 9284 | } |
22d72dbc AK |
9285 | [(set_attr "type" "load,larl") |
9286 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
9287 | (set_attr "z10prop" "z10_super") |
9288 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
9289 | |
9290 | ||
9291 | ; | |
9292 | ; Byte swap instructions | |
9293 | ; | |
9294 | ||
9295 | (define_insn "bswap<mode>2" | |
9296 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
9297 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] | |
677fbff4 | 9298 | "TARGET_CPU_ZARCH" |
07da44ab AK |
9299 | "@ |
9300 | lrv<g>r\t%0,%1 | |
9301 | lrv<g>\t%0,%1" | |
9302 | [(set_attr "type" "*,load") | |
9303 | (set_attr "op_type" "RRE,RXY") | |
9304 | (set_attr "z10prop" "z10_super")]) | |
65b1d8ea AK |
9305 | |
9306 | ||
9307 | ; | |
9308 | ; Population count instruction | |
9309 | ; | |
9310 | ||
9311 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
9312 | ; portions and stores the result in the corresponding bytes in op0. | |
9313 | (define_insn "*popcount<mode>" | |
9314 | [(set (match_operand:INT 0 "register_operand" "=d") | |
9315 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
9316 | (clobber (reg:CC CC_REGNUM))] | |
9317 | "TARGET_Z196" | |
9318 | "popcnt\t%0,%1" | |
9319 | [(set_attr "op_type" "RRE")]) | |
9320 | ||
9321 | (define_expand "popcountdi2" | |
9322 | [; popcnt op0, op1 | |
9323 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
9324 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
9325 | UNSPEC_POPCNT)) | |
9326 | (clobber (reg:CC CC_REGNUM))]) | |
9327 | ; sllg op2, op0, 32 | |
9328 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
9329 | ; agr op0, op2 | |
9330 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9331 | (clobber (reg:CC CC_REGNUM))]) | |
9332 | ; sllg op2, op0, 16 | |
9333 | (set (match_operand:DI 2 "register_operand" "") | |
9334 | (ashift:DI (match_dup 0) (const_int 16))) | |
9335 | ; agr op0, op2 | |
9336 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9337 | (clobber (reg:CC CC_REGNUM))]) | |
9338 | ; sllg op2, op0, 8 | |
9339 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
9340 | ; agr op0, op2 | |
9341 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9342 | (clobber (reg:CC CC_REGNUM))]) | |
9343 | ; srlg op0, op0, 56 | |
9344 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
9345 | "TARGET_Z196 && TARGET_64BIT" | |
9346 | "operands[2] = gen_reg_rtx (DImode);") | |
9347 | ||
9348 | (define_expand "popcountsi2" | |
9349 | [; popcnt op0, op1 | |
9350 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
9351 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
9352 | UNSPEC_POPCNT)) | |
9353 | (clobber (reg:CC CC_REGNUM))]) | |
9354 | ; sllk op2, op0, 16 | |
9355 | (set (match_operand:SI 2 "register_operand" "") | |
9356 | (ashift:SI (match_dup 0) (const_int 16))) | |
9357 | ; ar op0, op2 | |
9358 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9359 | (clobber (reg:CC CC_REGNUM))]) | |
9360 | ; sllk op2, op0, 8 | |
9361 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
9362 | ; ar op0, op2 | |
9363 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9364 | (clobber (reg:CC CC_REGNUM))]) | |
9365 | ; srl op0, op0, 24 | |
9366 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
9367 | "TARGET_Z196" | |
9368 | "operands[2] = gen_reg_rtx (SImode);") | |
9369 | ||
9370 | (define_expand "popcounthi2" | |
9371 | [; popcnt op0, op1 | |
9372 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
9373 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
9374 | UNSPEC_POPCNT)) | |
9375 | (clobber (reg:CC CC_REGNUM))]) | |
9376 | ; sllk op2, op0, 8 | |
9377 | (set (match_operand:SI 2 "register_operand" "") | |
9378 | (ashift:SI (match_dup 0) (const_int 8))) | |
9379 | ; ar op0, op2 | |
9380 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9381 | (clobber (reg:CC CC_REGNUM))]) | |
9382 | ; srl op0, op0, 8 | |
9383 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
9384 | "TARGET_Z196" | |
9385 | "operands[2] = gen_reg_rtx (SImode);") | |
9386 | ||
9387 | (define_expand "popcountqi2" | |
9388 | [; popcnt op0, op1 | |
9389 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
9390 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
9391 | UNSPEC_POPCNT)) | |
9392 | (clobber (reg:CC CC_REGNUM))])] | |
9393 | "TARGET_Z196" | |
9394 | "") | |
9395 | ||
9396 | ;; | |
9397 | ;;- Copy sign instructions | |
9398 | ;; | |
9399 | ||
9400 | (define_insn "copysign<mode>3" | |
9401 | [(set (match_operand:FP 0 "register_operand" "=f") | |
9402 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
9403 | (match_operand:FP 2 "register_operand" "f")] | |
9404 | UNSPEC_COPYSIGN))] | |
9405 | "TARGET_Z196" | |
9406 | "cpsdr\t%0,%2,%1" | |
9407 | [(set_attr "op_type" "RRF") | |
9408 | (set_attr "type" "fsimp<mode>")]) |