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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
85ec4feb | 2 | ;; Copyright (C) 1999-2018 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 | 77 | UNSPEC_LTREL_OFFSET |
30a49b23 AK |
78 | UNSPEC_POOL_OFFSET |
79 | UNSPEC_GOTENT | |
80 | UNSPEC_GOT | |
81 | UNSPEC_GOTOFF | |
82 | UNSPEC_PLT | |
83 | UNSPEC_PLTOFF | |
fd7643fb UW |
84 | |
85 | ; Literal pool | |
30a49b23 AK |
86 | UNSPEC_RELOAD_BASE |
87 | UNSPEC_MAIN_BASE | |
88 | UNSPEC_LTREF | |
89 | UNSPEC_INSN | |
90 | UNSPEC_EXECUTE | |
84b4c7b5 | 91 | UNSPEC_EXECUTE_JUMP |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
76794c52 | 159 | UNSPEC_VEC_LOAD_LEN_R |
3af82a61 AK |
160 | UNSPEC_VEC_MERGEH |
161 | UNSPEC_VEC_MERGEL | |
162 | UNSPEC_VEC_PACK | |
163 | UNSPEC_VEC_PACK_SATURATE | |
164 | UNSPEC_VEC_PACK_SATURATE_CC | |
165 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
168 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
169 | UNSPEC_VEC_PERM | |
170 | UNSPEC_VEC_PERMI | |
171 | UNSPEC_VEC_EXTEND | |
172 | UNSPEC_VEC_STORE_LEN | |
76794c52 AK |
173 | UNSPEC_VEC_STORE_LEN_R |
174 | UNSPEC_VEC_VBPERM | |
3af82a61 AK |
175 | UNSPEC_VEC_UNPACKH |
176 | UNSPEC_VEC_UNPACKH_L | |
177 | UNSPEC_VEC_UNPACKL | |
178 | UNSPEC_VEC_UNPACKL_L | |
179 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
180 | UNSPEC_VEC_ADDE_U128 |
181 | UNSPEC_VEC_ADDEC_U128 | |
182 | UNSPEC_VEC_AVG | |
183 | UNSPEC_VEC_AVGU | |
184 | UNSPEC_VEC_CHECKSUM | |
185 | UNSPEC_VEC_GFMSUM | |
186 | UNSPEC_VEC_GFMSUM_128 | |
187 | UNSPEC_VEC_GFMSUM_ACCUM | |
188 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
189 | UNSPEC_VEC_SET | |
190 | ||
191 | UNSPEC_VEC_VSUMG | |
192 | UNSPEC_VEC_VSUMQ | |
193 | UNSPEC_VEC_VSUM | |
194 | UNSPEC_VEC_RL_MASK | |
195 | UNSPEC_VEC_SLL | |
196 | UNSPEC_VEC_SLB | |
197 | UNSPEC_VEC_SLDB | |
198 | UNSPEC_VEC_SRAL | |
199 | UNSPEC_VEC_SRAB | |
200 | UNSPEC_VEC_SRL | |
201 | UNSPEC_VEC_SRLB | |
202 | ||
3af82a61 | 203 | UNSPEC_VEC_SUBC |
3af82a61 AK |
204 | UNSPEC_VEC_SUBE_U128 |
205 | UNSPEC_VEC_SUBEC_U128 | |
206 | ||
207 | UNSPEC_VEC_TEST_MASK | |
208 | ||
209 | UNSPEC_VEC_VFAE | |
210 | UNSPEC_VEC_VFAECC | |
211 | ||
212 | UNSPEC_VEC_VFEE | |
213 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
214 | UNSPEC_VEC_VFENE |
215 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
216 | |
217 | UNSPEC_VEC_VISTR | |
218 | UNSPEC_VEC_VISTRCC | |
219 | ||
220 | UNSPEC_VEC_VSTRC | |
221 | UNSPEC_VEC_VSTRCCC | |
222 | ||
223 | UNSPEC_VEC_VCDGB | |
224 | UNSPEC_VEC_VCDLGB | |
225 | ||
226 | UNSPEC_VEC_VCGDB | |
227 | UNSPEC_VEC_VCLGDB | |
228 | ||
76794c52 | 229 | UNSPEC_VEC_VFI |
3af82a61 | 230 | |
76794c52 AK |
231 | UNSPEC_VEC_VFLL ; vector fp load lengthened |
232 | UNSPEC_VEC_VFLR ; vector fp load rounded | |
3af82a61 | 233 | |
76794c52 AK |
234 | UNSPEC_VEC_VFTCI |
235 | UNSPEC_VEC_VFTCICC | |
236 | ||
237 | UNSPEC_VEC_MSUM | |
238 | ||
239 | UNSPEC_VEC_VFMIN | |
240 | UNSPEC_VEC_VFMAX | |
085261c8 | 241 | ]) |
fd3cd001 UW |
242 | |
243 | ;; | |
244 | ;; UNSPEC_VOLATILE usage | |
245 | ;; | |
246 | ||
30a49b23 AK |
247 | (define_c_enum "unspecv" [ |
248 | ; Blockage | |
249 | UNSPECV_BLOCKAGE | |
10bbf137 | 250 | |
2f7e5a0d | 251 | ; TPF Support |
30a49b23 AK |
252 | UNSPECV_TPF_PROLOGUE |
253 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 254 | |
10bbf137 | 255 | ; Literal pool |
30a49b23 AK |
256 | UNSPECV_POOL |
257 | UNSPECV_POOL_SECTION | |
258 | UNSPECV_POOL_ALIGN | |
259 | UNSPECV_POOL_ENTRY | |
260 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
261 | |
262 | ; TLS support | |
30a49b23 | 263 | UNSPECV_SET_TP |
e0374221 AS |
264 | |
265 | ; Atomic Support | |
30a49b23 AK |
266 | UNSPECV_CAS |
267 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 268 | |
aad98a61 AK |
269 | ; Non-branch nops used for compare-and-branch adjustments on z10 |
270 | UNSPECV_NOP_LR_0 | |
271 | UNSPECV_NOP_LR_1 | |
272 | ||
f8af0e30 DV |
273 | ; Hotpatching (unremovable NOPs) |
274 | UNSPECV_NOP_2_BYTE | |
275 | UNSPECV_NOP_4_BYTE | |
276 | UNSPECV_NOP_6_BYTE | |
277 | ||
5a3fe9b6 AK |
278 | ; Transactional Execution support |
279 | UNSPECV_TBEGIN | |
2561451d | 280 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
281 | UNSPECV_TBEGINC |
282 | UNSPECV_TEND | |
283 | UNSPECV_TABORT | |
284 | UNSPECV_ETND | |
285 | UNSPECV_NTSTG | |
286 | UNSPECV_PPA | |
004f64e1 AK |
287 | |
288 | ; Set and get floating point control register | |
289 | UNSPECV_SFPC | |
290 | UNSPECV_EFPC | |
4cb4721f MK |
291 | |
292 | ; Split stack support | |
293 | UNSPECV_SPLIT_STACK_CALL | |
294 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
295 | |
296 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
297 | ]) |
298 | ||
ae156f85 AS |
299 | ;; |
300 | ;; Registers | |
301 | ;; | |
302 | ||
35dd9a0e AK |
303 | ; Registers with special meaning |
304 | ||
ae156f85 AS |
305 | (define_constants |
306 | [ | |
307 | ; Sibling call register. | |
308 | (SIBCALL_REGNUM 1) | |
84b4c7b5 AK |
309 | ; A call-clobbered reg which can be used in indirect branch thunks |
310 | (INDIRECT_BRANCH_THUNK_REGNUM 1) | |
ae156f85 AS |
311 | ; Literal pool base register. |
312 | (BASE_REGNUM 13) | |
313 | ; Return address register. | |
314 | (RETURN_REGNUM 14) | |
82c6f58a AK |
315 | ; Stack pointer register. |
316 | (STACK_REGNUM 15) | |
ae156f85 AS |
317 | ; Condition code register. |
318 | (CC_REGNUM 33) | |
f4aa3848 | 319 | ; Thread local storage pointer register. |
ae156f85 AS |
320 | (TP_REGNUM 36) |
321 | ]) | |
322 | ||
35dd9a0e AK |
323 | ; Hardware register names |
324 | ||
325 | (define_constants | |
326 | [ | |
327 | ; General purpose registers | |
328 | (GPR0_REGNUM 0) | |
af344a30 | 329 | (GPR1_REGNUM 1) |
82379bdf AK |
330 | (GPR2_REGNUM 2) |
331 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
332 | ; Floating point registers. |
333 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
334 | (FPR1_REGNUM 20) |
335 | (FPR2_REGNUM 17) | |
336 | (FPR3_REGNUM 21) | |
337 | (FPR4_REGNUM 18) | |
338 | (FPR5_REGNUM 22) | |
339 | (FPR6_REGNUM 19) | |
340 | (FPR7_REGNUM 23) | |
341 | (FPR8_REGNUM 24) | |
342 | (FPR9_REGNUM 28) | |
343 | (FPR10_REGNUM 25) | |
344 | (FPR11_REGNUM 29) | |
345 | (FPR12_REGNUM 26) | |
346 | (FPR13_REGNUM 30) | |
347 | (FPR14_REGNUM 27) | |
348 | (FPR15_REGNUM 31) | |
085261c8 AK |
349 | (VR0_REGNUM 16) |
350 | (VR16_REGNUM 38) | |
351 | (VR23_REGNUM 45) | |
352 | (VR24_REGNUM 46) | |
353 | (VR31_REGNUM 53) | |
35dd9a0e AK |
354 | ]) |
355 | ||
ae8e301e AK |
356 | ; Rounding modes for binary floating point numbers |
357 | (define_constants | |
358 | [(BFP_RND_CURRENT 0) | |
359 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
360 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
361 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
362 | (BFP_RND_TOWARD_0 5) | |
363 | (BFP_RND_TOWARD_INF 6) | |
364 | (BFP_RND_TOWARD_MINF 7)]) | |
365 | ||
366 | ; Rounding modes for decimal floating point numbers | |
367 | ; 1-7 were introduced with the floating point extension facility | |
368 | ; available with z196 | |
369 | ; With these rounding modes (1-7) a quantum exception might occur | |
370 | ; which is suppressed for the other modes. | |
371 | (define_constants | |
372 | [(DFP_RND_CURRENT 0) | |
373 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
374 | (DFP_RND_CURRENT_QUANTEXC 2) | |
375 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
376 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
377 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
378 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
379 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
380 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
381 | (DFP_RND_TOWARD_0 9) | |
382 | (DFP_RND_TOWARD_INF 10) | |
383 | (DFP_RND_TOWARD_MINF 11) | |
384 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
385 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
386 | (DFP_RND_AWAY_FROM_0 14) | |
387 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
388 | ||
35dd9a0e AK |
389 | ;; |
390 | ;; PFPO GPR0 argument format | |
391 | ;; | |
392 | ||
393 | (define_constants | |
394 | [ | |
395 | ; PFPO operation type | |
396 | (PFPO_CONVERT 0x1000000) | |
397 | ; PFPO operand types | |
398 | (PFPO_OP_TYPE_SF 0x5) | |
399 | (PFPO_OP_TYPE_DF 0x6) | |
400 | (PFPO_OP_TYPE_TF 0x7) | |
401 | (PFPO_OP_TYPE_SD 0x8) | |
402 | (PFPO_OP_TYPE_DD 0x9) | |
403 | (PFPO_OP_TYPE_TD 0xa) | |
404 | ; Bitposition of operand types | |
405 | (PFPO_OP0_TYPE_SHIFT 16) | |
406 | (PFPO_OP1_TYPE_SHIFT 8) | |
ced8d882 AK |
407 | ; Decide whether current DFP or BFD rounding mode should be used |
408 | ; for the conversion. | |
409 | (PFPO_RND_MODE_DFP 0) | |
410 | (PFPO_RND_MODE_BFP 1) | |
35dd9a0e AK |
411 | ]) |
412 | ||
291a9e98 AK |
413 | ;; PPA constants |
414 | ||
415 | ; Immediate values which can be used as the third operand to the | |
416 | ; perform processor assist instruction | |
417 | ||
418 | (define_constants | |
419 | [(PPA_TX_ABORT 1) | |
420 | (PPA_OOO_BARRIER 15)]) | |
421 | ||
5a3fe9b6 AK |
422 | ; Immediate operands for tbegin and tbeginc |
423 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
424 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 425 | |
29a74354 UW |
426 | ;; Instruction operand type as used in the Principles of Operation. |
427 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 428 | |
29a74354 | 429 | (define_attr "op_type" |
76794c52 | 430 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" |
b628bd8e | 431 | (const_string "NN")) |
9db1d521 | 432 | |
29a74354 | 433 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 434 | |
077dab3b | 435 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 436 | cs,vs,store,sem,idiv, |
ed0e512a | 437 | imulhi,imulsi,imuldi, |
2cdece44 | 438 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
439 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
440 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 441 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 442 | fmadddf,fmaddsf, |
9381e3f1 WG |
443 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
444 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
445 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
446 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
447 | ftoidfp, other" | |
29a74354 UW |
448 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
449 | (eq_attr "op_type" "SS") (const_string "cs")] | |
450 | (const_string "integer"))) | |
9db1d521 | 451 | |
29a74354 UW |
452 | ;; Another attribute used for scheduling purposes: |
453 | ;; agen: Instruction uses the address generation unit | |
454 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
455 | |
456 | (define_attr "atype" "agen,reg" | |
62d3f261 | 457 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
458 | (const_string "reg") |
459 | (const_string "agen"))) | |
9db1d521 | 460 | |
9381e3f1 WG |
461 | ;; Properties concerning Z10 execution grouping and value forwarding. |
462 | ;; z10_super: instruction is superscalar. | |
463 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
464 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
465 | ;; target register. It can forward this value to a second instruction that reads | |
466 | ;; the same register if that second instruction is issued in the same group. | |
467 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
468 | ;; instruction in the S pipe writes to the register, then the T instruction | |
469 | ;; can immediately read the new value. | |
470 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
471 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
472 | ;; |
473 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
474 | ||
475 | ||
476 | (define_attr "z10prop" "none, | |
477 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
478 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
479 | z10_rec, | |
480 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 481 | z10_c" |
9381e3f1 WG |
482 | (const_string "none")) |
483 | ||
65b1d8ea AK |
484 | ;; Properties concerning Z196 decoding |
485 | ;; z196_alone: must group alone | |
486 | ;; z196_end: ends a group | |
487 | ;; z196_cracked: instruction is cracked or expanded | |
488 | (define_attr "z196prop" "none, | |
489 | z196_alone, z196_ends, | |
490 | z196_cracked" | |
491 | (const_string "none")) | |
9381e3f1 | 492 | |
84b4c7b5 AK |
493 | ; mnemonics which only get defined through if_then_else currently |
494 | ; don't get added to the list values automatically and hence need to | |
495 | ; be listed here. | |
8cc6307c | 496 | (define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 497 | |
9db1d521 HP |
498 | ;; Length in bytes. |
499 | ||
500 | (define_attr "length" "" | |
62d3f261 AK |
501 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
502 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 503 | (const_int 6))) |
9db1d521 | 504 | |
29a74354 UW |
505 | |
506 | ;; Processor type. This attribute must exactly match the processor_type | |
52d4aa4f | 507 | ;; enumeration in s390.h. |
29a74354 | 508 | |
e9e8efc9 | 509 | (define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14" |
90c6fd8a | 510 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 511 | |
b5e0425c | 512 | (define_attr "cpu_facility" |
e9e8efc9 | 513 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe" |
3af8e996 AK |
514 | (const_string "standard")) |
515 | ||
516 | (define_attr "enabled" "" | |
517 | (cond [(eq_attr "cpu_facility" "standard") | |
518 | (const_int 1) | |
519 | ||
520 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 521 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
522 | (const_int 1) |
523 | ||
524 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 525 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
526 | (const_int 1) |
527 | ||
528 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 529 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
530 | (const_int 1) |
531 | ||
532 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 533 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
534 | (const_int 1) |
535 | ||
536 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 537 | (match_test "TARGET_DFP")) |
93538e8e AK |
538 | (const_int 1) |
539 | ||
8cc6307c | 540 | (eq_attr "cpu_facility" "cpu_zarch") |
b5e0425c AK |
541 | (const_int 1) |
542 | ||
93538e8e | 543 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 544 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
545 | (const_int 1) |
546 | ||
547 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 548 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
549 | (const_int 1) |
550 | ||
551 | (and (eq_attr "cpu_facility" "zEC12") | |
552 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
553 | (const_int 1) |
554 | ||
285363a1 | 555 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 556 | (match_test "TARGET_VX")) |
bf749919 DV |
557 | (const_int 1) |
558 | ||
559 | (and (eq_attr "cpu_facility" "z13") | |
560 | (match_test "TARGET_Z13")) | |
561 | (const_int 1) | |
6654e96f | 562 | |
e9e8efc9 AK |
563 | (and (eq_attr "cpu_facility" "z14") |
564 | (match_test "TARGET_Z14")) | |
6654e96f AK |
565 | (const_int 1) |
566 | ||
567 | (and (eq_attr "cpu_facility" "vxe") | |
568 | (match_test "TARGET_VXE")) | |
569 | (const_int 1) | |
bf749919 | 570 | ] |
3af8e996 AK |
571 | (const_int 0))) |
572 | ||
14cfceb7 IL |
573 | ;; Whether an instruction supports relative long addressing. |
574 | ;; Currently this corresponds to RIL-b and RIL-c instruction formats, | |
575 | ;; but having a separate attribute, as opposed to reusing op_type, | |
576 | ;; provides additional flexibility. | |
577 | ||
578 | (define_attr "relative_long" "no,yes" (const_string "no")) | |
579 | ||
52d4aa4f | 580 | ;; Pipeline description for z900. |
29a74354 UW |
581 | (include "2064.md") |
582 | ||
3443392a | 583 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
584 | (include "2084.md") |
585 | ||
9381e3f1 WG |
586 | ;; Pipeline description for z10 |
587 | (include "2097.md") | |
588 | ||
65b1d8ea AK |
589 | ;; Pipeline description for z196 |
590 | (include "2817.md") | |
591 | ||
22ac2c2f AK |
592 | ;; Pipeline description for zEC12 |
593 | (include "2827.md") | |
594 | ||
23902021 AK |
595 | ;; Pipeline description for z13 |
596 | (include "2964.md") | |
597 | ||
0bfc3f69 AS |
598 | ;; Predicates |
599 | (include "predicates.md") | |
600 | ||
cd8dc1f9 WG |
601 | ;; Constraint definitions |
602 | (include "constraints.md") | |
603 | ||
a8ba31f2 EC |
604 | ;; Other includes |
605 | (include "tpf.md") | |
f52c81dd | 606 | |
3abcb3a7 | 607 | ;; Iterators |
f52c81dd | 608 | |
085261c8 AK |
609 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
610 | ||
3abcb3a7 | 611 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 612 | ;; same template. |
f4aa3848 | 613 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 614 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
615 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
616 | (define_mode_iterator BFP [TF DF SF]) | |
617 | (define_mode_iterator DFP [TD DD]) | |
618 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
619 | (define_mode_iterator DSF [DF SF]) | |
620 | (define_mode_iterator SD_SF [SF SD]) | |
621 | (define_mode_iterator DD_DF [DF DD]) | |
622 | (define_mode_iterator TD_TF [TF TD]) | |
623 | ||
3abcb3a7 | 624 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 625 | ;; from the same template. |
9602b6a1 | 626 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 627 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 628 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 629 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 630 | |
3abcb3a7 | 631 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 632 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 633 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 634 | |
78ce265b RH |
635 | ;; These macros refer to the actual word_mode of the configuration. |
636 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
637 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
638 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
639 | ||
6e0d70c9 AK |
640 | ;; Used by the umul pattern to express modes having half the size. |
641 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
642 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
643 | ||
3abcb3a7 | 644 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 645 | ;; the same template. |
3abcb3a7 | 646 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 647 | |
3abcb3a7 | 648 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 649 | ;; same template. |
9602b6a1 | 650 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 651 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 652 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 653 | |
3abcb3a7 | 654 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 655 | ;; the same template. |
3abcb3a7 | 656 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 657 | |
d12a76f3 | 658 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
659 | (define_code_iterator IXOR [ior xor]) |
660 | ||
d12a76f3 AK |
661 | ;; This iterator is used to expand the patterns for the nearest |
662 | ;; integer functions. | |
663 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
664 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
665 | UNSPEC_FPINT_NEARBYINT]) | |
666 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
667 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
668 | (UNSPEC_FPINT_ROUND "round") | |
669 | (UNSPEC_FPINT_CEIL "ceil") | |
670 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
671 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
672 | (UNSPEC_FPINT_BTRUNC "5") | |
673 | (UNSPEC_FPINT_ROUND "1") | |
674 | (UNSPEC_FPINT_CEIL "6") | |
675 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
676 | ||
3abcb3a7 HPN |
677 | ;; This iterator and attribute allow to combine most atomic operations. |
678 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 679 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 680 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 681 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 682 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 683 | |
f4aa3848 | 684 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
685 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
686 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 687 | |
f4aa3848 AK |
688 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
689 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
690 | ;; SDmode. |
691 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 692 | |
609e7e80 | 693 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
694 | ;; Likewise for "<RXe>". |
695 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
696 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
697 | ||
609e7e80 | 698 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 699 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
700 | ;; dfp variants in a single insn definition. |
701 | ||
62d3f261 AK |
702 | ;; These mode attributes are supposed to be used in the `enabled' insn |
703 | ;; attribute to disable certain alternatives for certain modes. | |
704 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
705 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
706 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
707 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
708 | (TD "0") (DD "0") (DD "0") | |
709 | (TI "0") (DI "*") (SI "0")]) | |
2de2b3f9 AK |
710 | (define_mode_attr DF [(TF "0") (DF "*") (SF "0") |
711 | (TD "0") (DD "0") (DD "0") | |
712 | (TI "0") (DI "0") (SI "0")]) | |
713 | (define_mode_attr SF [(TF "0") (DF "0") (SF "*") | |
714 | (TD "0") (DD "0") (DD "0") | |
715 | (TI "0") (DI "0") (SI "0")]) | |
f5905b37 | 716 | |
85dae55a AK |
717 | ;; This attribute is used in the operand constraint list |
718 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
719 | ;; TFmode values are represented by a fp register pair. Since the | |
720 | ;; sign bit instructions only handle single source and target fp registers | |
721 | ;; these instructions can only be used for TFmode values if the source and | |
722 | ;; target operand uses the same fp register. | |
723 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
724 | ||
3abcb3a7 | 725 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
726 | ;; within instruction mnemonics. |
727 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
728 | ||
0387c142 WG |
729 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
730 | ;; modes and to an empty string for bfp modes. | |
731 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
732 | ||
1b48c8cc AS |
733 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
734 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
735 | ;; version only operates on one register. | |
736 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
737 | ||
738 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
739 | ;; version only operates on one register. The DImode version needs an additional | |
740 | ;; register for the assembler output. | |
741 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
742 | |
743 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
744 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
745 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
746 | ||
747 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 748 | ;; pattern itself and the corresponding function calls. |
f337b930 | 749 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
750 | |
751 | ;; This attribute handles differences in the instruction 'type' and will result | |
752 | ;; in "RRE" for DImode and "RR" for SImode. | |
753 | (define_mode_attr E [(DI "E") (SI "")]) | |
754 | ||
3298c037 AK |
755 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
756 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
757 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
758 | ||
8006eaa6 AS |
759 | ;; This attribute handles differences in the instruction 'type' and will result |
760 | ;; in "RSE" for TImode and "RS" for DImode. | |
761 | (define_mode_attr TE [(TI "E") (DI "")]) | |
762 | ||
9a91a21f AS |
763 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
764 | ;; and "lcr" in SImode. | |
765 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 766 | |
3298c037 AK |
767 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
768 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
769 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
770 | ;; variant for long displacements. | |
771 | (define_mode_attr y [(DI "g") (SI "y")]) | |
772 | ||
9602b6a1 | 773 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
774 | ;; and "cds" in DImode. |
775 | (define_mode_attr tg [(TI "g") (DI "")]) | |
776 | ||
78ce265b RH |
777 | ;; In TDI templates, a string like "c<d>sg". |
778 | (define_mode_attr td [(TI "d") (DI "")]) | |
779 | ||
2f8f8434 AS |
780 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
781 | ;; and "cfdbr" in SImode. | |
782 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
783 | ||
65b1d8ea AK |
784 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
785 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
786 | ;; 3 operands shift instructions into the existing patterns. | |
787 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
788 | ||
f52c81dd AS |
789 | ;; ICM mask required to load MODE value into the lowest subreg |
790 | ;; of a SImode register. | |
791 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
792 | ||
f6ee577c AS |
793 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
794 | ;; HImode and "llgc" in QImode. | |
795 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
796 | ||
a1aed706 AS |
797 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
798 | ;; in SImode. | |
799 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
800 | ||
609e7e80 AK |
801 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
802 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
803 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
804 | ||
f52c81dd AS |
805 | ;; Maximum unsigned integer that fits in MODE. |
806 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
807 | ||
75ca1b39 RH |
808 | ;; Start and end field computations for RISBG et al. |
809 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
810 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
811 | ||
2542ef05 RH |
812 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
813 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
814 | ;; 64 - bitsize |
815 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
816 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 817 | |
da0dcab1 DV |
818 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
819 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
820 | ||
177bc204 RS |
821 | ;; Allow return and simple_return to be defined from a single template. |
822 | (define_code_iterator ANY_RETURN [return simple_return]) | |
823 | ||
6e5b5de8 AK |
824 | |
825 | ||
826 | ; Condition code modes generated by vector fp comparisons. These will | |
827 | ; be used also in single element mode. | |
828 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
829 | ; Used with VFCMP to expand part of the mnemonic | |
830 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
831 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 832 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 833 | |
191eb16d AK |
834 | ;; Subst pattern definitions |
835 | (include "subst.md") | |
6e5b5de8 | 836 | |
085261c8 AK |
837 | (include "vector.md") |
838 | ||
9db1d521 HP |
839 | ;; |
840 | ;;- Compare instructions. | |
841 | ;; | |
842 | ||
07893d4f | 843 | ; Test-under-Mask instructions |
9db1d521 | 844 | |
07893d4f | 845 | (define_insn "*tmqi_mem" |
ae156f85 | 846 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
847 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
848 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
849 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 850 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 851 | "@ |
fc0ea003 UW |
852 | tm\t%S0,%b1 |
853 | tmy\t%S0,%b1" | |
9381e3f1 | 854 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 855 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 856 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 857 | |
05b9aaaa | 858 | (define_insn "*tmdi_reg" |
ae156f85 | 859 | [(set (reg CC_REGNUM) |
f19a9af7 | 860 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 861 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
862 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
863 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 864 | "TARGET_ZARCH |
3ed99cc9 | 865 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
866 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
867 | "@ | |
868 | tmhh\t%0,%i1 | |
869 | tmhl\t%0,%i1 | |
870 | tmlh\t%0,%i1 | |
871 | tmll\t%0,%i1" | |
9381e3f1 WG |
872 | [(set_attr "op_type" "RI") |
873 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
874 | |
875 | (define_insn "*tmsi_reg" | |
ae156f85 | 876 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
877 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
878 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
879 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 880 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
881 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
882 | "@ | |
883 | tmh\t%0,%i1 | |
884 | tml\t%0,%i1" | |
729e750f WG |
885 | [(set_attr "op_type" "RI") |
886 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 887 | |
f52c81dd | 888 | (define_insn "*tm<mode>_full" |
ae156f85 | 889 | [(set (reg CC_REGNUM) |
f52c81dd AS |
890 | (compare (match_operand:HQI 0 "register_operand" "d") |
891 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 892 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 893 | "tml\t%0,<max_uint>" |
729e750f WG |
894 | [(set_attr "op_type" "RI") |
895 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 896 | |
07893d4f | 897 | |
08a5aaa2 | 898 | ; |
07893d4f | 899 | ; Load-and-Test instructions |
08a5aaa2 AS |
900 | ; |
901 | ||
c0220ea4 | 902 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
903 | |
904 | (define_insn "*tstdi_sign" | |
ae156f85 | 905 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
906 | (compare |
907 | (ashiftrt:DI | |
908 | (ashift:DI | |
3e4be43f | 909 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
910 | (const_int 32)) (const_int 32)) |
911 | (match_operand:DI 1 "const0_operand" ""))) | |
912 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 913 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 914 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
915 | "ltgfr\t%2,%0 |
916 | ltgf\t%2,%0" | |
917 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
918 | (set_attr "cpu_facility" "*,z10") |
919 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 920 | |
43a09b63 | 921 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 922 | (define_insn "*tst<mode>_extimm" |
ec24698e | 923 | [(set (reg CC_REGNUM) |
3e4be43f | 924 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
925 | (match_operand:GPR 1 "const0_operand" ""))) |
926 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 927 | (match_dup 0))] |
08a5aaa2 | 928 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 929 | "@ |
08a5aaa2 AS |
930 | lt<g>r\t%2,%0 |
931 | lt<g>\t%2,%0" | |
9381e3f1 | 932 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 933 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 934 | |
97160c9b DV |
935 | ; Peephole to combine a load-and-test from volatile memory which combine does |
936 | ; not do. | |
937 | (define_peephole2 | |
938 | [(set (match_operand:GPR 0 "register_operand") | |
939 | (match_operand:GPR 2 "memory_operand")) | |
940 | (set (reg CC_REGNUM) | |
941 | (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] | |
942 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM | |
943 | && GENERAL_REG_P (operands[0]) | |
944 | && satisfies_constraint_T (operands[2])" | |
945 | [(parallel | |
946 | [(set (reg:CCS CC_REGNUM) | |
947 | (compare:CCS (match_dup 2) (match_dup 1))) | |
948 | (set (match_dup 0) (match_dup 2))])]) | |
949 | ||
43a09b63 | 950 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 951 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 952 | [(set (reg CC_REGNUM) |
3e4be43f | 953 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
954 | (match_operand:GPR 1 "const0_operand" ""))) |
955 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
956 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 957 | "@ |
08a5aaa2 AS |
958 | lt<g>r\t%0,%0 |
959 | lt<g>\t%2,%0" | |
9381e3f1 | 960 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 961 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 962 | |
07893d4f | 963 | (define_insn "*tstdi" |
ae156f85 | 964 | [(set (reg CC_REGNUM) |
07893d4f UW |
965 | (compare (match_operand:DI 0 "register_operand" "d") |
966 | (match_operand:DI 1 "const0_operand" ""))) | |
967 | (set (match_operand:DI 2 "register_operand" "=d") | |
968 | (match_dup 0))] | |
9602b6a1 | 969 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 970 | "ltgr\t%2,%0" |
9381e3f1 WG |
971 | [(set_attr "op_type" "RRE") |
972 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 973 | |
07893d4f | 974 | (define_insn "*tstsi" |
ae156f85 | 975 | [(set (reg CC_REGNUM) |
d3632d41 | 976 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 977 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 978 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 979 | (match_dup 0))] |
ec24698e | 980 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 981 | "@ |
d40c829f | 982 | ltr\t%2,%0 |
fc0ea003 UW |
983 | icm\t%2,15,%S0 |
984 | icmy\t%2,15,%S0" | |
9381e3f1 | 985 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 986 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 987 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 988 | |
07893d4f | 989 | (define_insn "*tstsi_cconly" |
ae156f85 | 990 | [(set (reg CC_REGNUM) |
d3632d41 | 991 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 992 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 993 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
994 | "s390_match_ccmode(insn, CCSmode)" |
995 | "@ | |
d40c829f | 996 | ltr\t%0,%0 |
fc0ea003 UW |
997 | icm\t%2,15,%S0 |
998 | icmy\t%2,15,%S0" | |
9381e3f1 | 999 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 1000 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 1001 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 1002 | |
08a5aaa2 AS |
1003 | (define_insn "*tstdi_cconly_31" |
1004 | [(set (reg CC_REGNUM) | |
1005 | (compare (match_operand:DI 0 "register_operand" "d") | |
1006 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 1007 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
1008 | "srda\t%0,0" |
1009 | [(set_attr "op_type" "RS") | |
1010 | (set_attr "atype" "reg")]) | |
1011 | ||
43a09b63 | 1012 | ; ltr, ltgr |
08a5aaa2 | 1013 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 1014 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
1015 | (compare (match_operand:GPR 0 "register_operand" "d") |
1016 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 1017 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 1018 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
1019 | [(set_attr "op_type" "RR<E>") |
1020 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 1021 | |
c0220ea4 | 1022 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 1023 | |
f52c81dd | 1024 | (define_insn "*tst<mode>CCT" |
ae156f85 | 1025 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1026 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
1027 | (match_operand:HQI 1 "const0_operand" ""))) | |
1028 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
1029 | (match_dup 0))] |
1030 | "s390_match_ccmode(insn, CCTmode)" | |
1031 | "@ | |
f52c81dd AS |
1032 | icm\t%2,<icm_lo>,%S0 |
1033 | icmy\t%2,<icm_lo>,%S0 | |
1034 | tml\t%0,<max_uint>" | |
9381e3f1 | 1035 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1036 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1037 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
1038 | |
1039 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 1040 | [(set (reg CC_REGNUM) |
d3632d41 | 1041 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 1042 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 1043 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
1044 | "s390_match_ccmode(insn, CCTmode)" |
1045 | "@ | |
fc0ea003 UW |
1046 | icm\t%2,3,%S0 |
1047 | icmy\t%2,3,%S0 | |
d40c829f | 1048 | tml\t%0,65535" |
9381e3f1 | 1049 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1050 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1051 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 1052 | |
3af97654 | 1053 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1054 | [(set (reg CC_REGNUM) |
d3632d41 | 1055 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1056 | (match_operand:QI 1 "const0_operand" "")))] |
1057 | "s390_match_ccmode(insn, CCTmode)" | |
1058 | "@ | |
fc0ea003 UW |
1059 | cli\t%S0,0 |
1060 | cliy\t%S0,0 | |
d40c829f | 1061 | tml\t%0,255" |
9381e3f1 | 1062 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1063 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1064 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1065 | |
f52c81dd | 1066 | (define_insn "*tst<mode>" |
ae156f85 | 1067 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1068 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1069 | (match_operand:HQI 1 "const0_operand" ""))) | |
1070 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1071 | (match_dup 0))] |
1072 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1073 | "@ |
f52c81dd AS |
1074 | icm\t%2,<icm_lo>,%S0 |
1075 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1076 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1077 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1078 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1079 | |
f52c81dd | 1080 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1081 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1082 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1083 | (match_operand:HQI 1 "const0_operand" ""))) | |
1084 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1085 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1086 | "@ |
f52c81dd AS |
1087 | icm\t%2,<icm_lo>,%S0 |
1088 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1089 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1090 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1091 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1092 | |
9db1d521 | 1093 | |
575f7c2b UW |
1094 | ; Compare (equality) instructions |
1095 | ||
1096 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1097 | [(set (reg CC_REGNUM) |
ec24698e | 1098 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1099 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1100 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1101 | "@ |
1102 | cgr\t%0,%1 | |
f4f41b4e | 1103 | cghi\t%0,%h1 |
ec24698e | 1104 | cgfi\t%0,%1 |
575f7c2b | 1105 | cg\t%0,%1 |
19b63d8e | 1106 | #" |
9381e3f1 WG |
1107 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1108 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1109 | |
1110 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1111 | [(set (reg CC_REGNUM) |
ec24698e UW |
1112 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1113 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1114 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1115 | "@ |
1116 | cr\t%0,%1 | |
f4f41b4e | 1117 | chi\t%0,%h1 |
ec24698e | 1118 | cfi\t%0,%1 |
575f7c2b UW |
1119 | c\t%0,%1 |
1120 | cy\t%0,%1 | |
19b63d8e | 1121 | #" |
9381e3f1 | 1122 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1123 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1124 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1125 | |
07893d4f | 1126 | ; Compare (signed) instructions |
4023fb28 | 1127 | |
07893d4f | 1128 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1129 | [(set (reg CC_REGNUM) |
963fc8d0 | 1130 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1131 | "d,T,b")) |
963fc8d0 | 1132 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1133 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1134 | "@ |
d40c829f | 1135 | cgfr\t%0,%1 |
963fc8d0 AK |
1136 | cgf\t%0,%1 |
1137 | cgfrl\t%0,%1" | |
1138 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1139 | (set_attr "z10prop" "z10_c,*,*") |
14cfceb7 IL |
1140 | (set_attr "type" "*,*,larl") |
1141 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 | 1142 | |
9381e3f1 WG |
1143 | |
1144 | ||
07893d4f | 1145 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1146 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1147 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1148 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1149 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1150 | "@ |
d40c829f | 1151 | ch\t%0,%1 |
963fc8d0 AK |
1152 | chy\t%0,%1 |
1153 | chrl\t%0,%1" | |
1154 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1155 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea | 1156 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1157 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked") |
1158 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 AK |
1159 | |
1160 | (define_insn "*cmphi_ccs_z10" | |
1161 | [(set (reg CC_REGNUM) | |
1162 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1163 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1164 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1165 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1166 | [(set_attr "op_type" "SIL") |
1167 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1168 | |
1169 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1170 | [(set (reg CC_REGNUM) | |
3e4be43f | 1171 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1172 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1173 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1174 | "@ | |
1175 | cgh\t%0,%1 | |
1176 | cghrl\t%0,%1" | |
1177 | [(set_attr "op_type" "RXY,RIL") | |
14cfceb7 IL |
1178 | (set_attr "type" "*,larl") |
1179 | (set_attr "relative_long" "*,yes")]) | |
4023fb28 | 1180 | |
963fc8d0 | 1181 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1182 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1183 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1184 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1185 | "d,d,Q, d,d,d,d") | |
1186 | (match_operand:GPR 1 "general_operand" | |
1187 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1188 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1189 | "@ |
3298c037 AK |
1190 | c<g>r\t%0,%1 |
1191 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1192 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1193 | c<g>fi\t%0,%1 |
1194 | c<g>\t%0,%1 | |
963fc8d0 AK |
1195 | c<y>\t%0,%1 |
1196 | c<g>rl\t%0,%1" | |
1197 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1198 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 | 1199 | (set_attr "type" "*,*,*,*,*,*,larl") |
14cfceb7 IL |
1200 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super") |
1201 | (set_attr "relative_long" "*,*,*,*,*,*,yes")]) | |
c7453384 | 1202 | |
07893d4f UW |
1203 | |
1204 | ; Compare (unsigned) instructions | |
9db1d521 | 1205 | |
963fc8d0 AK |
1206 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1207 | [(set (reg CC_REGNUM) | |
1208 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1209 | "larl_operand" "X"))) | |
1210 | (match_operand:SI 0 "register_operand" "d")))] | |
1211 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1212 | "clhrl\t%0,%1" | |
1213 | [(set_attr "op_type" "RIL") | |
729e750f | 1214 | (set_attr "type" "larl") |
14cfceb7 IL |
1215 | (set_attr "z10prop" "z10_super") |
1216 | (set_attr "relative_long" "yes")]) | |
963fc8d0 AK |
1217 | |
1218 | ; clhrl, clghrl | |
1219 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1220 | [(set (reg CC_REGNUM) | |
1221 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1222 | "larl_operand" "X"))) | |
1223 | (match_operand:GPR 0 "register_operand" "d")))] | |
1224 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1225 | "cl<g>hrl\t%0,%1" | |
1226 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1227 | (set_attr "type" "larl") |
14cfceb7 IL |
1228 | (set_attr "z10prop" "z10_super") |
1229 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 1230 | |
07893d4f | 1231 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1232 | [(set (reg CC_REGNUM) |
963fc8d0 | 1233 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1234 | "d,T,b")) |
1235 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1236 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1237 | "@ |
d40c829f | 1238 | clgfr\t%0,%1 |
963fc8d0 AK |
1239 | clgf\t%0,%1 |
1240 | clgfrl\t%0,%1" | |
1241 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1242 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 | 1243 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1244 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super") |
1245 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 1246 | |
07893d4f | 1247 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1248 | [(set (reg CC_REGNUM) |
963fc8d0 | 1249 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1250 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1251 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1252 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1253 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1254 | "@ |
d40c829f | 1255 | clgr\t%0,%1 |
ec24698e | 1256 | clgfi\t%0,%1 |
963fc8d0 AK |
1257 | clgrl\t%0,%1 |
1258 | clghsi\t%0,%x1 | |
575f7c2b | 1259 | clg\t%0,%1 |
e221ef54 | 1260 | # |
19b63d8e | 1261 | #" |
963fc8d0 AK |
1262 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1263 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 | 1264 | (set_attr "type" "*,*,larl,*,*,*,*") |
14cfceb7 IL |
1265 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*") |
1266 | (set_attr "relative_long" "*,*,yes,*,*,*,*")]) | |
9db1d521 | 1267 | |
07893d4f | 1268 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1269 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1270 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1271 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1272 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1273 | "@ |
d40c829f | 1274 | clr\t%0,%1 |
ec24698e | 1275 | clfi\t%0,%o1 |
963fc8d0 AK |
1276 | clrl\t%0,%1 |
1277 | clfhsi\t%0,%x1 | |
d40c829f | 1278 | cl\t%0,%1 |
575f7c2b | 1279 | cly\t%0,%1 |
e221ef54 | 1280 | # |
19b63d8e | 1281 | #" |
963fc8d0 | 1282 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1283 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 | 1284 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
14cfceb7 IL |
1285 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*") |
1286 | (set_attr "relative_long" "*,*,yes,*,*,*,*,*")]) | |
9db1d521 | 1287 | |
07893d4f | 1288 | (define_insn "*cmphi_ccu" |
ae156f85 | 1289 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1290 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1291 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1292 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1293 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1294 | "@ |
fc0ea003 UW |
1295 | clm\t%0,3,%S1 |
1296 | clmy\t%0,3,%S1 | |
963fc8d0 | 1297 | clhhsi\t%0,%1 |
e221ef54 | 1298 | # |
19b63d8e | 1299 | #" |
963fc8d0 | 1300 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1301 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1302 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1303 | |
1304 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1305 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1306 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1307 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1308 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1309 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1310 | "@ |
fc0ea003 UW |
1311 | clm\t%0,1,%S1 |
1312 | clmy\t%0,1,%S1 | |
1313 | cli\t%S0,%b1 | |
1314 | cliy\t%S0,%b1 | |
e221ef54 | 1315 | # |
19b63d8e | 1316 | #" |
9381e3f1 | 1317 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1318 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1319 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1320 | |
1321 | ||
19b63d8e UW |
1322 | ; Block compare (CLC) instruction patterns. |
1323 | ||
1324 | (define_insn "*clc" | |
ae156f85 | 1325 | [(set (reg CC_REGNUM) |
d4f52f0e | 1326 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1327 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1328 | (use (match_operand 2 "const_int_operand" "n"))] | |
1329 | "s390_match_ccmode (insn, CCUmode) | |
1330 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1331 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1332 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1333 | |
1334 | (define_split | |
ae156f85 | 1335 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1336 | (compare (match_operand 0 "memory_operand" "") |
1337 | (match_operand 1 "memory_operand" "")))] | |
1338 | "reload_completed | |
1339 | && s390_match_ccmode (insn, CCUmode) | |
1340 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1341 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1342 | [(parallel | |
1343 | [(set (match_dup 0) (match_dup 1)) | |
1344 | (use (match_dup 2))])] | |
1345 | { | |
1346 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1347 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1348 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1349 | ||
1350 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1351 | operands[0], operands[1]); | |
1352 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1353 | }) | |
1354 | ||
1355 | ||
609e7e80 | 1356 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1357 | |
e325aba2 AK |
1358 | |
1359 | ; load and test instructions turn SNaN into QNaN what is not | |
1360 | ; acceptable if the target will be used afterwards. On the other hand | |
1361 | ; they are quite convenient for implementing comparisons with 0.0. So | |
1362 | ; try to enable them via splitter if the value isn't needed anymore. | |
1363 | ||
609e7e80 | 1364 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1365 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1366 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1367 | (compare (match_operand:FP 0 "register_operand" "f") |
1368 | (match_operand:FP 1 "const0_operand" ""))) | |
1369 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1370 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1371 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1372 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1373 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1374 | |
e325aba2 AK |
1375 | (define_split |
1376 | [(set (match_operand 0 "cc_reg_operand") | |
1377 | (compare (match_operand:FP 1 "register_operand") | |
1378 | (match_operand:FP 2 "const0_operand")))] | |
1379 | "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])" | |
1380 | [(parallel | |
1381 | [(set (match_dup 0) (match_dup 3)) | |
1382 | (clobber (match_dup 1))])] | |
1383 | { | |
1384 | /* s390_match_ccmode requires the compare to have the same CC mode | |
1385 | as the CC destination register. */ | |
1386 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]), | |
1387 | operands[1], operands[2]); | |
1388 | }) | |
1389 | ||
1390 | ||
2de2b3f9 AK |
1391 | ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb |
1392 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb | |
f5905b37 | 1393 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1394 | [(set (reg CC_REGNUM) |
2de2b3f9 AK |
1395 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") |
1396 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
142cd70f | 1397 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1398 | "@ |
609e7e80 | 1399 | c<xde><bt>r\t%0,%1 |
77c585ca | 1400 | c<xde>b\t%0,%1 |
2de2b3f9 AK |
1401 | wfcdb\t%0,%1 |
1402 | wfcsb\t%0,%1" | |
1403 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1404 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1405 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
963fc8d0 AK |
1406 | |
1407 | ; Compare and Branch instructions | |
1408 | ||
1409 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1410 | ; The following instructions do a complementary access of their second |
1411 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1412 | (define_insn "*cmp_and_br_signed_<mode>" |
1413 | [(set (pc) | |
1414 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1415 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1416 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1417 | (label_ref (match_operand 3 "" "")) | |
1418 | (pc))) | |
1419 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1420 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1421 | { |
1422 | if (get_attr_length (insn) == 6) | |
1423 | return which_alternative ? | |
1424 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1425 | else | |
1426 | return which_alternative ? | |
1427 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1428 | } | |
1429 | [(set_attr "op_type" "RIE") | |
1430 | (set_attr "type" "branch") | |
e3cba5e5 | 1431 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1432 | (set (attr "length") |
1433 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1434 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1435 | ; 10 byte for cgr/jg | |
1436 | ||
1437 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1438 | ; The following instructions do a complementary access of their second |
1439 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1440 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1441 | [(set (pc) | |
1442 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1443 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1444 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1445 | (label_ref (match_operand 3 "" "")) | |
1446 | (pc))) | |
1447 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1448 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1449 | { |
1450 | if (get_attr_length (insn) == 6) | |
1451 | return which_alternative ? | |
1452 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1453 | else | |
1454 | return which_alternative ? | |
1455 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1456 | } | |
1457 | [(set_attr "op_type" "RIE") | |
1458 | (set_attr "type" "branch") | |
e3cba5e5 | 1459 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1460 | (set (attr "length") |
1461 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1462 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1463 | ; 10 byte for clgr/jg | |
1464 | ||
b0f86a7e AK |
1465 | ; And now the same two patterns as above but with a negated CC mask. |
1466 | ||
1467 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1468 | ; The following instructions do a complementary access of their second | |
1469 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1470 | (define_insn "*icmp_and_br_signed_<mode>" | |
1471 | [(set (pc) | |
1472 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1473 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1474 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1475 | (pc) | |
1476 | (label_ref (match_operand 3 "" "")))) | |
1477 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1478 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1479 | { |
1480 | if (get_attr_length (insn) == 6) | |
1481 | return which_alternative ? | |
1482 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1483 | else | |
1484 | return which_alternative ? | |
1485 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1486 | } | |
1487 | [(set_attr "op_type" "RIE") | |
1488 | (set_attr "type" "branch") | |
1489 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1490 | (set (attr "length") | |
1491 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1492 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1493 | ; 10 byte for cgr/jg | |
1494 | ||
1495 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1496 | ; The following instructions do a complementary access of their second | |
1497 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1498 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1499 | [(set (pc) | |
1500 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1501 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1502 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1503 | (pc) | |
1504 | (label_ref (match_operand 3 "" "")))) | |
1505 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1506 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1507 | { |
1508 | if (get_attr_length (insn) == 6) | |
1509 | return which_alternative ? | |
1510 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1511 | else | |
1512 | return which_alternative ? | |
1513 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1514 | } | |
1515 | [(set_attr "op_type" "RIE") | |
1516 | (set_attr "type" "branch") | |
1517 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1518 | (set (attr "length") | |
1519 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1520 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1521 | ; 10 byte for clgr/jg | |
1522 | ||
9db1d521 HP |
1523 | ;; |
1524 | ;;- Move instructions. | |
1525 | ;; | |
1526 | ||
1527 | ; | |
1528 | ; movti instruction pattern(s). | |
1529 | ; | |
1530 | ||
3cb9ee2f AK |
1531 | |
1532 | ; Separate out the register pair alternative since constraints (P) are | |
1533 | ; not able to deal with const_wide_int's. But predicates do. | |
1534 | (define_insn "*movti_bigconst" | |
1535 | [(set (match_operand:TI 0 "register_operand" "=d") | |
1536 | (match_operand:TI 1 "reload_const_wide_int_operand" ""))] | |
1537 | "TARGET_ZARCH" | |
1538 | "#") | |
1539 | ||
085261c8 AK |
1540 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1541 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1542 | (define_insn "movti" |
9f3c21d6 AK |
1543 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R,d, d, d, d, d,o") |
1544 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))] | |
9602b6a1 | 1545 | "TARGET_ZARCH" |
4023fb28 | 1546 | "@ |
fc0ea003 UW |
1547 | lmg\t%0,%N0,%S1 |
1548 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1549 | vlr\t%v0,%v1 |
1550 | vzero\t%v0 | |
1551 | vone\t%v0 | |
1552 | vlvgp\t%v0,%1,%N1 | |
1553 | # | |
1554 | vl\t%v0,%1 | |
1555 | vst\t%v1,%0 | |
4023fb28 | 1556 | # |
9f3c21d6 AK |
1557 | # |
1558 | # | |
1559 | # | |
1560 | # | |
19b63d8e | 1561 | #" |
9f3c21d6 AK |
1562 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*,*,*,*,*") |
1563 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*,*,*,*,*") | |
1564 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*,*,extimm,*,*")]) | |
4023fb28 UW |
1565 | |
1566 | (define_split | |
1567 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1568 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1569 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1570 | && !s_operand (operands[0], TImode) |
1571 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1572 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1573 | [(set (match_dup 2) (match_dup 4)) |
1574 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1575 | { |
dc65c307 UW |
1576 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1577 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1578 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1579 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1580 | }) | |
1581 | ||
1582 | (define_split | |
1583 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1584 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1585 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1586 | && !s_operand (operands[0], TImode) |
1587 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1588 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1589 | [(set (match_dup 2) (match_dup 4)) | |
1590 | (set (match_dup 3) (match_dup 5))] | |
1591 | { | |
1592 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1593 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1594 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1595 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1596 | }) | |
4023fb28 | 1597 | |
085261c8 AK |
1598 | ; Use part of the TImode target reg to perform the address |
1599 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1600 | ; this splitter is not necessary. | |
4023fb28 UW |
1601 | (define_split |
1602 | [(set (match_operand:TI 0 "register_operand" "") | |
1603 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1604 | "TARGET_ZARCH && reload_completed |
085261c8 | 1605 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1606 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1607 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1608 | { |
1609 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1610 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1611 | s390_load_address (addr, XEXP (operands[1], 0)); |
1612 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1613 | }) |
1614 | ||
833cd70a | 1615 | |
085261c8 AK |
1616 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1617 | ; For the higher order bits we do simply a DImode move while the | |
1618 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1619 | (define_split | |
1620 | [(set (match_operand:TI 0 "register_operand" "") | |
1621 | (match_operand:TI 1 "register_operand" ""))] | |
1622 | "TARGET_VX && reload_completed | |
1623 | && GENERAL_REG_P (operands[0]) | |
1624 | && VECTOR_REG_P (operands[1])" | |
1625 | [(set (match_dup 2) (match_dup 4)) | |
1626 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1627 | UNSPEC_VEC_EXTRACT))] | |
1628 | { | |
1629 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1630 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1631 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1632 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1633 | }) | |
1634 | ||
833cd70a AK |
1635 | ; |
1636 | ; Patterns used for secondary reloads | |
1637 | ; | |
1638 | ||
963fc8d0 AK |
1639 | ; z10 provides move instructions accepting larl memory operands. |
1640 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1641 | ; These patterns are also used for unaligned SI and DI accesses. | |
1642 | ||
085261c8 AK |
1643 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1644 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1645 | (match_operand:ALL 1 "register_operand" "=d") | |
1646 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1647 | "TARGET_Z10" |
1648 | { | |
1649 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1650 | DONE; | |
1651 | }) | |
1652 | ||
085261c8 AK |
1653 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1654 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1655 | (match_operand:ALL 1 "memory_operand" "") | |
1656 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1657 | "TARGET_Z10" |
1658 | { | |
1659 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1660 | DONE; | |
1661 | }) | |
1662 | ||
1663 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1664 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1665 | (match_operand:P 1 "larl_operand" "") | |
1666 | (match_operand:P 2 "register_operand" "=a")])] | |
1667 | "TARGET_Z10" | |
1668 | { | |
1669 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1670 | DONE; | |
1671 | }) | |
1672 | ||
833cd70a AK |
1673 | ; Handles loading a PLUS (load address) expression |
1674 | ||
1675 | (define_expand "reload<mode>_plus" | |
1676 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1677 | (match_operand:P 1 "s390_plus_operand" "") | |
1678 | (match_operand:P 2 "register_operand" "=&a")])] | |
1679 | "" | |
1680 | { | |
1681 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1682 | DONE; | |
1683 | }) | |
1684 | ||
085261c8 AK |
1685 | ; Not all the indirect memory access instructions support the full |
1686 | ; format (long disp + index + base). So whenever a move from/to such | |
1687 | ; an address is required and the instruction cannot deal with it we do | |
1688 | ; a load address into a scratch register first and use this as the new | |
1689 | ; base register. | |
1690 | ; This in particular is used for: | |
1691 | ; - non-offsetable memory accesses for multiword moves | |
1692 | ; - full vector reg moves with long displacements | |
833cd70a | 1693 | |
085261c8 | 1694 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1695 | [(parallel [(match_operand 0 "register_operand" "") |
1696 | (match_operand 1 "" "") | |
1697 | (match_operand:P 2 "register_operand" "=&a")])] | |
1698 | "" | |
1699 | { | |
1700 | gcc_assert (MEM_P (operands[1])); | |
1701 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1702 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1703 | emit_move_insn (operands[0], operands[1]); | |
1704 | DONE; | |
1705 | }) | |
1706 | ||
085261c8 | 1707 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1708 | [(parallel [(match_operand 0 "" "") |
1709 | (match_operand 1 "register_operand" "") | |
1710 | (match_operand:P 2 "register_operand" "=&a")])] | |
1711 | "" | |
dc65c307 | 1712 | { |
9c3c3dcc | 1713 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1714 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1715 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1716 | emit_move_insn (operands[0], operands[1]); | |
1717 | DONE; | |
1718 | }) | |
9db1d521 | 1719 | |
1f9e1fc6 AK |
1720 | (define_expand "reload<mode>_PIC_addr" |
1721 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1722 | (match_operand 1 "larl_operand" "") | |
1723 | (match_operand:P 2 "register_operand" "=a")])] | |
1724 | "" | |
1725 | { | |
0a2aaacc KG |
1726 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1727 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1728 | }) |
1729 | ||
9db1d521 HP |
1730 | ; |
1731 | ; movdi instruction pattern(s). | |
1732 | ; | |
1733 | ||
9db1d521 HP |
1734 | (define_expand "movdi" |
1735 | [(set (match_operand:DI 0 "general_operand" "") | |
1736 | (match_operand:DI 1 "general_operand" ""))] | |
1737 | "" | |
9db1d521 | 1738 | { |
fd3cd001 | 1739 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1740 | if (TARGET_64BIT |
1741 | && (SYMBOLIC_CONST (operands[1]) | |
1742 | || (GET_CODE (operands[1]) == PLUS | |
1743 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1744 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1745 | emit_symbolic_move (operands); |
10bbf137 | 1746 | }) |
9db1d521 | 1747 | |
3af8e996 | 1748 | (define_insn "*movdi_64" |
85dae55a | 1749 | [(set (match_operand:DI 0 "nonimmediate_operand" |
b6f51755 | 1750 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d") |
85dae55a | 1751 | (match_operand:DI 1 "general_operand" |
b6f51755 | 1752 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))] |
9602b6a1 | 1753 | "TARGET_ZARCH" |
85dae55a AK |
1754 | "@ |
1755 | lghi\t%0,%h1 | |
1756 | llihh\t%0,%i1 | |
1757 | llihl\t%0,%i1 | |
1758 | llilh\t%0,%i1 | |
1759 | llill\t%0,%i1 | |
1760 | lgfi\t%0,%1 | |
1761 | llihf\t%0,%k1 | |
1762 | llilf\t%0,%k1 | |
1763 | ldgr\t%0,%1 | |
1764 | lgdr\t%0,%1 | |
1765 | lay\t%0,%a1 | |
963fc8d0 | 1766 | lgrl\t%0,%1 |
85dae55a AK |
1767 | lgr\t%0,%1 |
1768 | lg\t%0,%1 | |
1769 | stg\t%1,%0 | |
1770 | ldr\t%0,%1 | |
1771 | ld\t%0,%1 | |
1772 | ldy\t%0,%1 | |
1773 | std\t%1,%0 | |
1774 | stdy\t%1,%0 | |
963fc8d0 AK |
1775 | stgrl\t%1,%0 |
1776 | mvghi\t%0,%1 | |
85dae55a AK |
1777 | # |
1778 | # | |
1779 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1780 | lam\t%0,%N0,%S1 |
1781 | vleig\t%v0,%h1,0 | |
1782 | vlr\t%v0,%v1 | |
1783 | vlvgg\t%v0,%1,0 | |
1784 | vlgvg\t%0,%v1,0 | |
1785 | vleg\t%v0,%1,0 | |
b6f51755 IL |
1786 | vsteg\t%v1,%0,0 |
1787 | larl\t%0,%1" | |
963fc8d0 | 1788 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
b6f51755 IL |
1789 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS, |
1790 | VRX,VRX,RIL") | |
963fc8d0 | 1791 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 | 1792 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
b6f51755 | 1793 | *,*,*,*,*,*,*,larl") |
3af8e996 | 1794 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1795 | z10,*,*,*,*,*,longdisp,*,longdisp, |
b6f51755 | 1796 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx,*") |
9381e3f1 WG |
1797 | (set_attr "z10prop" "z10_fwd_A1, |
1798 | z10_fwd_E1, | |
1799 | z10_fwd_E1, | |
1800 | z10_fwd_E1, | |
1801 | z10_fwd_E1, | |
1802 | z10_fwd_A1, | |
1803 | z10_fwd_E1, | |
1804 | z10_fwd_E1, | |
1805 | *, | |
1806 | *, | |
1807 | z10_fwd_A1, | |
1808 | z10_fwd_A3, | |
1809 | z10_fr_E1, | |
1810 | z10_fwd_A3, | |
1811 | z10_rec, | |
1812 | *, | |
1813 | *, | |
1814 | *, | |
1815 | *, | |
1816 | *, | |
1817 | z10_rec, | |
1818 | z10_super, | |
1819 | *, | |
1820 | *, | |
1821 | *, | |
b6f51755 IL |
1822 | *,*,*,*,*,*,*, |
1823 | z10_super_A1") | |
14cfceb7 IL |
1824 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*, |
1825 | *,yes,*,*,*,*,*,*,*,*, | |
1826 | yes,*,*,*,*,*,*,*,*,*, | |
1827 | *,*,yes") | |
9381e3f1 | 1828 | ]) |
c5aa1d12 UW |
1829 | |
1830 | (define_split | |
1831 | [(set (match_operand:DI 0 "register_operand" "") | |
1832 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1833 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1834 | [(set (match_dup 2) (match_dup 3)) |
1835 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1836 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1837 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1838 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1839 | ||
1840 | (define_split | |
1841 | [(set (match_operand:DI 0 "register_operand" "") | |
1842 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1843 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1844 | && dead_or_set_p (insn, operands[1])" |
1845 | [(set (match_dup 3) (match_dup 2)) | |
1846 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1847 | (set (match_dup 4) (match_dup 2))] | |
1848 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1849 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1850 | ||
1851 | (define_split | |
1852 | [(set (match_operand:DI 0 "register_operand" "") | |
1853 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1854 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1855 | && !dead_or_set_p (insn, operands[1])" |
1856 | [(set (match_dup 3) (match_dup 2)) | |
1857 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1858 | (set (match_dup 4) (match_dup 2)) | |
1859 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1860 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1861 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1862 | |
1863 | (define_insn "*movdi_31" | |
963fc8d0 | 1864 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1865 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1866 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1867 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1868 | "!TARGET_ZARCH" |
4023fb28 | 1869 | "@ |
fc0ea003 | 1870 | lm\t%0,%N0,%S1 |
c4d50129 | 1871 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1872 | stm\t%1,%N1,%S0 |
c4d50129 | 1873 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1874 | # |
1875 | # | |
d40c829f UW |
1876 | ldr\t%0,%1 |
1877 | ld\t%0,%1 | |
1878 | ldy\t%0,%1 | |
1879 | std\t%1,%0 | |
1880 | stdy\t%1,%0 | |
19b63d8e | 1881 | #" |
f2dc2f86 AK |
1882 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1883 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1884 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1885 | |
1886 | ; For a load from a symbol ref we can use one of the target registers | |
1887 | ; together with larl to load the address. | |
1888 | (define_split | |
1889 | [(set (match_operand:DI 0 "register_operand" "") | |
1890 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1891 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1892 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1893 | [(set (match_dup 2) (match_dup 3)) | |
1894 | (set (match_dup 0) (match_dup 1))] | |
1895 | { | |
1896 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1897 | operands[3] = XEXP (operands[1], 0); | |
1898 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1899 | }) | |
4023fb28 UW |
1900 | |
1901 | (define_split | |
1902 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1903 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1904 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1905 | && !s_operand (operands[0], DImode) |
1906 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1907 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1908 | [(set (match_dup 2) (match_dup 4)) |
1909 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1910 | { |
dc65c307 UW |
1911 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1912 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1913 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1914 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1915 | }) | |
1916 | ||
1917 | (define_split | |
1918 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1919 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1920 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1921 | && !s_operand (operands[0], DImode) |
1922 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1923 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1924 | [(set (match_dup 2) (match_dup 4)) | |
1925 | (set (match_dup 3) (match_dup 5))] | |
1926 | { | |
1927 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1928 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1929 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1930 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1931 | }) | |
9db1d521 | 1932 | |
4023fb28 UW |
1933 | (define_split |
1934 | [(set (match_operand:DI 0 "register_operand" "") | |
1935 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1936 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1937 | && !FP_REG_P (operands[0]) |
4023fb28 | 1938 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1939 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1940 | { |
1941 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1942 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1943 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1944 | }) |
1945 | ||
84817c5d UW |
1946 | (define_peephole2 |
1947 | [(set (match_operand:DI 0 "register_operand" "") | |
1948 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1949 | "TARGET_ZARCH |
84817c5d UW |
1950 | && !FP_REG_P (operands[0]) |
1951 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1952 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1953 | && get_pool_mode (operands[1]) == DImode | |
1954 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1955 | [(set (match_dup 0) (match_dup 2))] | |
1956 | "operands[2] = get_pool_constant (operands[1]);") | |
1957 | ||
7bdff56f UW |
1958 | (define_insn "*la_64" |
1959 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1960 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1961 | "TARGET_64BIT" |
1962 | "@ | |
1963 | la\t%0,%a1 | |
1964 | lay\t%0,%a1" | |
1965 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1966 | (set_attr "type" "la") |
3e4be43f | 1967 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1968 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1969 | |
1970 | (define_peephole2 | |
1971 | [(parallel | |
1972 | [(set (match_operand:DI 0 "register_operand" "") | |
1973 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1974 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1975 | "TARGET_64BIT |
e1d5ee28 | 1976 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1977 | [(set (match_dup 0) (match_dup 1))] |
1978 | "") | |
1979 | ||
1980 | (define_peephole2 | |
1981 | [(set (match_operand:DI 0 "register_operand" "") | |
1982 | (match_operand:DI 1 "register_operand" "")) | |
1983 | (parallel | |
1984 | [(set (match_dup 0) | |
1985 | (plus:DI (match_dup 0) | |
1986 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1987 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1988 | "TARGET_64BIT |
1989 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1990 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1991 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1992 | "") | |
1993 | ||
9db1d521 HP |
1994 | ; |
1995 | ; movsi instruction pattern(s). | |
1996 | ; | |
1997 | ||
9db1d521 HP |
1998 | (define_expand "movsi" |
1999 | [(set (match_operand:SI 0 "general_operand" "") | |
2000 | (match_operand:SI 1 "general_operand" ""))] | |
2001 | "" | |
9db1d521 | 2002 | { |
fd3cd001 | 2003 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
2004 | if (!TARGET_64BIT |
2005 | && (SYMBOLIC_CONST (operands[1]) | |
2006 | || (GET_CODE (operands[1]) == PLUS | |
2007 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
2008 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 2009 | emit_symbolic_move (operands); |
10bbf137 | 2010 | }) |
9db1d521 | 2011 | |
9e8327e3 UW |
2012 | (define_insn "*movsi_larl" |
2013 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2014 | (match_operand:SI 1 "larl_operand" "X"))] | |
8cc6307c | 2015 | "!TARGET_64BIT |
9e8327e3 UW |
2016 | && !FP_REG_P (operands[0])" |
2017 | "larl\t%0,%1" | |
2018 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 2019 | (set_attr "type" "larl") |
14cfceb7 IL |
2020 | (set_attr "z10prop" "z10_fwd_A1") |
2021 | (set_attr "relative_long" "yes")]) | |
9e8327e3 | 2022 | |
f19a9af7 | 2023 | (define_insn "*movsi_zarch" |
2f7e5a0d | 2024 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 2025 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 2026 | (match_operand:SI 1 "general_operand" |
3e4be43f | 2027 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 2028 | "TARGET_ZARCH" |
9db1d521 | 2029 | "@ |
f19a9af7 AK |
2030 | lhi\t%0,%h1 |
2031 | llilh\t%0,%i1 | |
2032 | llill\t%0,%i1 | |
ec24698e | 2033 | iilf\t%0,%o1 |
f19a9af7 | 2034 | lay\t%0,%a1 |
963fc8d0 | 2035 | lrl\t%0,%1 |
d40c829f UW |
2036 | lr\t%0,%1 |
2037 | l\t%0,%1 | |
2038 | ly\t%0,%1 | |
2039 | st\t%1,%0 | |
2040 | sty\t%1,%0 | |
ae1c6198 | 2041 | ldr\t%0,%1 |
d40c829f | 2042 | ler\t%0,%1 |
085261c8 | 2043 | lde\t%0,%1 |
d40c829f UW |
2044 | le\t%0,%1 |
2045 | ley\t%0,%1 | |
2046 | ste\t%1,%0 | |
2047 | stey\t%1,%0 | |
c5aa1d12 UW |
2048 | ear\t%0,%1 |
2049 | sar\t%0,%1 | |
2050 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
2051 | strl\t%1,%0 |
2052 | mvhi\t%0,%1 | |
085261c8 AK |
2053 | lam\t%0,%0,%S1 |
2054 | vleif\t%v0,%h1,0 | |
2055 | vlr\t%v0,%v1 | |
2056 | vlvgf\t%v0,%1,0 | |
2057 | vlgvf\t%0,%v1,0 | |
2058 | vlef\t%v0,%1,0 | |
2059 | vstef\t%v1,%0,0" | |
963fc8d0 | 2060 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 2061 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
2062 | (set_attr "type" "*, |
2063 | *, | |
2064 | *, | |
2065 | *, | |
2066 | la, | |
2067 | larl, | |
2068 | lr, | |
2069 | load, | |
2070 | load, | |
2071 | store, | |
2072 | store, | |
2073 | floadsf, | |
2074 | floadsf, | |
2075 | floadsf, | |
085261c8 AK |
2076 | floadsf, |
2077 | floadsf, | |
9381e3f1 WG |
2078 | fstoresf, |
2079 | fstoresf, | |
2080 | *, | |
2081 | *, | |
2082 | *, | |
2083 | larl, | |
2084 | *, | |
085261c8 | 2085 | *,*,*,*,*,*,*") |
963fc8d0 | 2086 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2087 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2088 | (set_attr "z10prop" "z10_fwd_A1, |
2089 | z10_fwd_E1, | |
2090 | z10_fwd_E1, | |
2091 | z10_fwd_A1, | |
2092 | z10_fwd_A1, | |
2093 | z10_fwd_A3, | |
2094 | z10_fr_E1, | |
2095 | z10_fwd_A3, | |
2096 | z10_fwd_A3, | |
729e750f | 2097 | z10_rec, |
9381e3f1 WG |
2098 | z10_rec, |
2099 | *, | |
2100 | *, | |
2101 | *, | |
2102 | *, | |
2103 | *, | |
085261c8 AK |
2104 | *, |
2105 | *, | |
9381e3f1 WG |
2106 | z10_super_E1, |
2107 | z10_super, | |
2108 | *, | |
2109 | z10_rec, | |
2110 | z10_super, | |
14cfceb7 IL |
2111 | *,*,*,*,*,*,*") |
2112 | (set_attr "relative_long" "*,*,*,*,*,yes,*,*,*,*, | |
2113 | *,*,*,*,*,*,*,*,*,*, | |
2114 | *,yes,*,*,*,*,*,*,*,*")]) | |
f19a9af7 AK |
2115 | |
2116 | (define_insn "*movsi_esa" | |
085261c8 AK |
2117 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2118 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2119 | "!TARGET_ZARCH" |
2120 | "@ | |
2121 | lhi\t%0,%h1 | |
2122 | lr\t%0,%1 | |
2123 | l\t%0,%1 | |
2124 | st\t%1,%0 | |
ae1c6198 | 2125 | ldr\t%0,%1 |
f19a9af7 | 2126 | ler\t%0,%1 |
085261c8 | 2127 | lde\t%0,%1 |
f19a9af7 AK |
2128 | le\t%0,%1 |
2129 | ste\t%1,%0 | |
c5aa1d12 UW |
2130 | ear\t%0,%1 |
2131 | sar\t%0,%1 | |
2132 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2133 | lam\t%0,%0,%S1" |
ae1c6198 | 2134 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2135 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2136 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2137 | z10_super,*,*") | |
285363a1 | 2138 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2139 | ]) |
9db1d521 | 2140 | |
84817c5d UW |
2141 | (define_peephole2 |
2142 | [(set (match_operand:SI 0 "register_operand" "") | |
2143 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2144 | "!FP_REG_P (operands[0]) | |
2145 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2146 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2147 | && get_pool_mode (operands[1]) == SImode | |
2148 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2149 | [(set (match_dup 0) (match_dup 2))] | |
2150 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2151 | |
7bdff56f UW |
2152 | (define_insn "*la_31" |
2153 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2154 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2155 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2156 | "@ | |
2157 | la\t%0,%a1 | |
2158 | lay\t%0,%a1" | |
2159 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2160 | (set_attr "type" "la") |
3e4be43f | 2161 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2162 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2163 | |
2164 | (define_peephole2 | |
2165 | [(parallel | |
2166 | [(set (match_operand:SI 0 "register_operand" "") | |
2167 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2168 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2169 | "!TARGET_64BIT |
e1d5ee28 | 2170 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2171 | [(set (match_dup 0) (match_dup 1))] |
2172 | "") | |
2173 | ||
2174 | (define_peephole2 | |
2175 | [(set (match_operand:SI 0 "register_operand" "") | |
2176 | (match_operand:SI 1 "register_operand" "")) | |
2177 | (parallel | |
2178 | [(set (match_dup 0) | |
2179 | (plus:SI (match_dup 0) | |
2180 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2181 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2182 | "!TARGET_64BIT |
2183 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2184 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2185 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2186 | "") | |
2187 | ||
2188 | (define_insn "*la_31_and" | |
2189 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2190 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2191 | (const_int 2147483647)))] |
2192 | "!TARGET_64BIT" | |
2193 | "@ | |
2194 | la\t%0,%a1 | |
2195 | lay\t%0,%a1" | |
2196 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2197 | (set_attr "type" "la") |
3e4be43f | 2198 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2199 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2200 | |
2201 | (define_insn_and_split "*la_31_and_cc" | |
2202 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2203 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2204 | (const_int 2147483647))) | |
ae156f85 | 2205 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2206 | "!TARGET_64BIT" |
2207 | "#" | |
2208 | "&& reload_completed" | |
2209 | [(set (match_dup 0) | |
2210 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2211 | "" | |
2212 | [(set_attr "op_type" "RX") | |
2213 | (set_attr "type" "la")]) | |
2214 | ||
2215 | (define_insn "force_la_31" | |
2216 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2217 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2218 | (use (const_int 0))] |
2219 | "!TARGET_64BIT" | |
2220 | "@ | |
2221 | la\t%0,%a1 | |
2222 | lay\t%0,%a1" | |
2223 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2224 | (set_attr "type" "la") |
3e4be43f | 2225 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2226 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2227 | |
9db1d521 HP |
2228 | ; |
2229 | ; movhi instruction pattern(s). | |
2230 | ; | |
2231 | ||
02ed3c5e UW |
2232 | (define_expand "movhi" |
2233 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2234 | (match_operand:HI 1 "general_operand" ""))] | |
2235 | "" | |
2236 | { | |
2f7e5a0d | 2237 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2238 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2239 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2240 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2241 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2242 | { |
2243 | rtx tmp = gen_reg_rtx (SImode); | |
2244 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2245 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2246 | operands[1] = gen_lowpart (HImode, tmp); |
2247 | } | |
2248 | }) | |
2249 | ||
2250 | (define_insn "*movhi" | |
3e4be43f UW |
2251 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2252 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2253 | "" |
2254 | "@ | |
d40c829f UW |
2255 | lr\t%0,%1 |
2256 | lhi\t%0,%h1 | |
2257 | lh\t%0,%1 | |
2258 | lhy\t%0,%1 | |
963fc8d0 | 2259 | lhrl\t%0,%1 |
d40c829f UW |
2260 | sth\t%1,%0 |
2261 | sthy\t%1,%0 | |
963fc8d0 | 2262 | sthrl\t%1,%0 |
085261c8 AK |
2263 | mvhhi\t%0,%1 |
2264 | vleih\t%v0,%h1,0 | |
2265 | vlr\t%v0,%v1 | |
2266 | vlvgh\t%v0,%1,0 | |
2267 | vlgvh\t%0,%v1,0 | |
2268 | vleh\t%v0,%1,0 | |
2269 | vsteh\t%v1,%0,0" | |
2270 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2271 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2272 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2273 | (set_attr "z10prop" "z10_fr_E1, |
2274 | z10_fwd_A1, | |
2275 | z10_super_E1, | |
2276 | z10_super_E1, | |
2277 | z10_super_E1, | |
729e750f | 2278 | z10_rec, |
9381e3f1 WG |
2279 | z10_rec, |
2280 | z10_rec, | |
14cfceb7 IL |
2281 | z10_super,*,*,*,*,*,*") |
2282 | (set_attr "relative_long" "*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*")]) | |
9db1d521 | 2283 | |
84817c5d UW |
2284 | (define_peephole2 |
2285 | [(set (match_operand:HI 0 "register_operand" "") | |
2286 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2287 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2288 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2289 | && get_pool_mode (operands[1]) == HImode | |
2290 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2291 | [(set (match_dup 0) (match_dup 2))] | |
2292 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2293 | |
9db1d521 HP |
2294 | ; |
2295 | ; movqi instruction pattern(s). | |
2296 | ; | |
2297 | ||
02ed3c5e UW |
2298 | (define_expand "movqi" |
2299 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2300 | (match_operand:QI 1 "general_operand" ""))] | |
2301 | "" | |
2302 | { | |
c19ec8f9 | 2303 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2304 | is just as fast as a QImode load. */ |
b3a13419 | 2305 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2306 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2307 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2308 | { |
9602b6a1 AK |
2309 | rtx tmp = gen_reg_rtx (DImode); |
2310 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2311 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2312 | operands[1] = gen_lowpart (QImode, tmp); |
2313 | } | |
2314 | }) | |
4023fb28 | 2315 | |
02ed3c5e | 2316 | (define_insn "*movqi" |
3e4be43f UW |
2317 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2318 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2319 | "" |
2320 | "@ | |
d40c829f UW |
2321 | lr\t%0,%1 |
2322 | lhi\t%0,%b1 | |
2323 | ic\t%0,%1 | |
2324 | icy\t%0,%1 | |
2325 | stc\t%1,%0 | |
2326 | stcy\t%1,%0 | |
fc0ea003 | 2327 | mvi\t%S0,%b1 |
0a88561f | 2328 | mviy\t%S0,%b1 |
085261c8 AK |
2329 | # |
2330 | vleib\t%v0,%b1,0 | |
2331 | vlr\t%v0,%v1 | |
2332 | vlvgb\t%v0,%1,0 | |
2333 | vlgvb\t%0,%v1,0 | |
2334 | vleb\t%v0,%1,0 | |
2335 | vsteb\t%v1,%0,0" | |
2336 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2337 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2338 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2339 | (set_attr "z10prop" "z10_fr_E1, |
2340 | z10_fwd_A1, | |
2341 | z10_super_E1, | |
2342 | z10_super_E1, | |
729e750f | 2343 | z10_rec, |
9381e3f1 WG |
2344 | z10_rec, |
2345 | z10_super, | |
0a88561f | 2346 | z10_super, |
085261c8 | 2347 | *,*,*,*,*,*,*")]) |
9db1d521 | 2348 | |
84817c5d UW |
2349 | (define_peephole2 |
2350 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2351 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2352 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2353 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2354 | && get_pool_mode (operands[1]) == QImode | |
2355 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2356 | [(set (match_dup 0) (match_dup 2))] | |
2357 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2358 | |
9db1d521 | 2359 | ; |
05b9aaaa | 2360 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2361 | ; |
2362 | ||
2363 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2364 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2365 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2366 | "" |
d3632d41 | 2367 | "@ |
d40c829f UW |
2368 | ic\t%0,%1 |
2369 | icy\t%0,%1" | |
9381e3f1 | 2370 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2371 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2372 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2373 | |
2374 | ; | |
2375 | ; movstricthi instruction pattern(s). | |
2376 | ; | |
2377 | ||
2378 | (define_insn "*movstricthi" | |
d3632d41 | 2379 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2380 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2381 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2382 | "" |
d3632d41 | 2383 | "@ |
fc0ea003 UW |
2384 | icm\t%0,3,%S1 |
2385 | icmy\t%0,3,%S1" | |
9381e3f1 | 2386 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2387 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2388 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2389 | |
2390 | ; | |
2391 | ; movstrictsi instruction pattern(s). | |
2392 | ; | |
2393 | ||
05b9aaaa | 2394 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2395 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2396 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2397 | "TARGET_ZARCH" |
9db1d521 | 2398 | "@ |
d40c829f UW |
2399 | lr\t%0,%1 |
2400 | l\t%0,%1 | |
c5aa1d12 UW |
2401 | ly\t%0,%1 |
2402 | ear\t%0,%1" | |
2403 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2404 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2405 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2406 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2407 | |
f61a2c7d | 2408 | ; |
609e7e80 | 2409 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2410 | ; |
2411 | ||
609e7e80 AK |
2412 | (define_expand "mov<mode>" |
2413 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2414 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2415 | "" |
2416 | "") | |
2417 | ||
609e7e80 | 2418 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2419 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2420 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2421 | "TARGET_ZARCH" |
f61a2c7d | 2422 | "@ |
65b1d8ea | 2423 | lzxr\t%0 |
f61a2c7d AK |
2424 | lxr\t%0,%1 |
2425 | # | |
2426 | # | |
2427 | lmg\t%0,%N0,%S1 | |
2428 | stmg\t%1,%N1,%S0 | |
2429 | # | |
f61a2c7d | 2430 | #" |
65b1d8ea AK |
2431 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2432 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2433 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2434 | |
609e7e80 | 2435 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2436 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2437 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2438 | "!TARGET_ZARCH" |
f61a2c7d | 2439 | "@ |
65b1d8ea | 2440 | lzxr\t%0 |
f61a2c7d AK |
2441 | lxr\t%0,%1 |
2442 | # | |
f61a2c7d | 2443 | #" |
65b1d8ea AK |
2444 | [(set_attr "op_type" "RRE,RRE,*,*") |
2445 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2446 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2447 | |
2448 | ; TFmode in GPRs splitters | |
2449 | ||
2450 | (define_split | |
609e7e80 AK |
2451 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2452 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2453 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2454 | && !s_operand (operands[0], <MODE>mode) |
2455 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2456 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2457 | [(set (match_dup 2) (match_dup 4)) |
2458 | (set (match_dup 3) (match_dup 5))] | |
2459 | { | |
609e7e80 AK |
2460 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2461 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2462 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2463 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2464 | }) |
2465 | ||
2466 | (define_split | |
609e7e80 AK |
2467 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2468 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2469 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2470 | && !s_operand (operands[0], <MODE>mode) |
2471 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2472 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2473 | [(set (match_dup 2) (match_dup 4)) |
2474 | (set (match_dup 3) (match_dup 5))] | |
2475 | { | |
609e7e80 AK |
2476 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2477 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2478 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2479 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2480 | }) |
2481 | ||
2482 | (define_split | |
609e7e80 AK |
2483 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2484 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2485 | "TARGET_ZARCH && reload_completed |
085261c8 | 2486 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2487 | && !s_operand (operands[1], VOIDmode)" |
2488 | [(set (match_dup 0) (match_dup 1))] | |
2489 | { | |
609e7e80 | 2490 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2491 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2492 | s390_load_address (addr, XEXP (operands[1], 0)); |
2493 | operands[1] = replace_equiv_address (operands[1], addr); | |
2494 | }) | |
2495 | ||
7b6baae1 | 2496 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2497 | |
2498 | (define_split | |
609e7e80 AK |
2499 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2500 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2501 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2502 | && FP_REG_P (operands[0])" |
2503 | [(set (match_dup 2) (match_dup 4)) | |
2504 | (set (match_dup 3) (match_dup 5))] | |
2505 | { | |
609e7e80 AK |
2506 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2507 | <MODE>mode, 0); | |
2508 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2509 | <MODE>mode, 8); | |
2510 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2511 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2512 | }) |
2513 | ||
2514 | (define_split | |
609e7e80 AK |
2515 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2516 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2517 | "reload_completed && offsettable_memref_p (operands[0]) |
2518 | && FP_REG_P (operands[1])" | |
2519 | [(set (match_dup 2) (match_dup 4)) | |
2520 | (set (match_dup 3) (match_dup 5))] | |
2521 | { | |
609e7e80 AK |
2522 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2523 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2524 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2525 | <MODE>mode, 0); | |
2526 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2527 | <MODE>mode, 8); | |
f61a2c7d AK |
2528 | }) |
2529 | ||
9db1d521 | 2530 | ; |
609e7e80 | 2531 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2532 | ; |
2533 | ||
609e7e80 AK |
2534 | (define_expand "mov<mode>" |
2535 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2536 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2537 | "" |
13c025c1 | 2538 | "") |
9db1d521 | 2539 | |
609e7e80 AK |
2540 | (define_insn "*mov<mode>_64dfp" |
2541 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2542 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2543 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2544 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2545 | "TARGET_DFP" |
85dae55a | 2546 | "@ |
65b1d8ea | 2547 | lzdr\t%0 |
85dae55a AK |
2548 | ldr\t%0,%1 |
2549 | ldgr\t%0,%1 | |
2550 | lgdr\t%0,%1 | |
2551 | ld\t%0,%1 | |
2552 | ldy\t%0,%1 | |
2553 | std\t%1,%0 | |
2554 | stdy\t%1,%0 | |
45e5214c | 2555 | lghi\t%0,0 |
85dae55a | 2556 | lgr\t%0,%1 |
085261c8 | 2557 | lgrl\t%0,%1 |
85dae55a | 2558 | lg\t%0,%1 |
085261c8 AK |
2559 | stgrl\t%1,%0 |
2560 | stg\t%1,%0 | |
2561 | vlr\t%v0,%v1 | |
590961cf | 2562 | vleig\t%v0,0,0 |
085261c8 AK |
2563 | vlvgg\t%v0,%1,0 |
2564 | vlgvg\t%0,%v1,0 | |
2565 | vleg\t%0,%1,0 | |
2566 | vsteg\t%1,%0,0" | |
590961cf | 2567 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2568 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2569 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2570 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2571 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx") |
2572 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,yes,*,*,*,*,*,*,*")]) | |
85dae55a | 2573 | |
609e7e80 | 2574 | (define_insn "*mov<mode>_64" |
590961cf AK |
2575 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2576 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2577 | "TARGET_ZARCH" |
9db1d521 | 2578 | "@ |
65b1d8ea | 2579 | lzdr\t%0 |
d40c829f UW |
2580 | ldr\t%0,%1 |
2581 | ld\t%0,%1 | |
2582 | ldy\t%0,%1 | |
2583 | std\t%1,%0 | |
2584 | stdy\t%1,%0 | |
45e5214c | 2585 | lghi\t%0,0 |
d40c829f | 2586 | lgr\t%0,%1 |
085261c8 | 2587 | lgrl\t%0,%1 |
d40c829f | 2588 | lg\t%0,%1 |
085261c8 | 2589 | stgrl\t%1,%0 |
590961cf AK |
2590 | stg\t%1,%0" |
2591 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2592 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2593 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2594 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
14cfceb7 IL |
2595 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*") |
2596 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")]) | |
609e7e80 AK |
2597 | |
2598 | (define_insn "*mov<mode>_31" | |
2599 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2600 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2601 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2602 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2603 | "!TARGET_ZARCH" |
9db1d521 | 2604 | "@ |
65b1d8ea | 2605 | lzdr\t%0 |
d40c829f UW |
2606 | ldr\t%0,%1 |
2607 | ld\t%0,%1 | |
2608 | ldy\t%0,%1 | |
2609 | std\t%1,%0 | |
2610 | stdy\t%1,%0 | |
fc0ea003 | 2611 | lm\t%0,%N0,%S1 |
c4d50129 | 2612 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2613 | stm\t%1,%N1,%S0 |
c4d50129 | 2614 | stmy\t%1,%N1,%S0 |
4023fb28 | 2615 | # |
19b63d8e | 2616 | #" |
65b1d8ea AK |
2617 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2618 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2619 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2620 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2621 | |
2622 | (define_split | |
609e7e80 AK |
2623 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2624 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2625 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2626 | && !s_operand (operands[0], <MODE>mode) |
2627 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2628 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2629 | [(set (match_dup 2) (match_dup 4)) |
2630 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2631 | { |
609e7e80 AK |
2632 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2633 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2634 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2635 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2636 | }) |
2637 | ||
2638 | (define_split | |
609e7e80 AK |
2639 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2640 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2641 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2642 | && !s_operand (operands[0], <MODE>mode) |
2643 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2644 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2645 | [(set (match_dup 2) (match_dup 4)) |
2646 | (set (match_dup 3) (match_dup 5))] | |
2647 | { | |
609e7e80 AK |
2648 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2649 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2650 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2651 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2652 | }) |
9db1d521 | 2653 | |
4023fb28 | 2654 | (define_split |
609e7e80 AK |
2655 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2656 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2657 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2658 | && !FP_REG_P (operands[0]) |
4023fb28 | 2659 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2660 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2661 | { |
609e7e80 | 2662 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2663 | s390_load_address (addr, XEXP (operands[1], 0)); |
2664 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2665 | }) |
2666 | ||
9db1d521 | 2667 | ; |
609e7e80 | 2668 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2669 | ; |
2670 | ||
609e7e80 AK |
2671 | (define_insn "mov<mode>" |
2672 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2673 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2674 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2675 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2676 | "" |
9db1d521 | 2677 | "@ |
65b1d8ea | 2678 | lzer\t%0 |
ae1c6198 | 2679 | ldr\t%0,%1 |
d40c829f | 2680 | ler\t%0,%1 |
085261c8 | 2681 | lde\t%0,%1 |
d40c829f UW |
2682 | le\t%0,%1 |
2683 | ley\t%0,%1 | |
2684 | ste\t%1,%0 | |
2685 | stey\t%1,%0 | |
45e5214c | 2686 | lhi\t%0,0 |
d40c829f | 2687 | lr\t%0,%1 |
085261c8 | 2688 | lrl\t%0,%1 |
d40c829f UW |
2689 | l\t%0,%1 |
2690 | ly\t%0,%1 | |
085261c8 | 2691 | strl\t%1,%0 |
d40c829f | 2692 | st\t%1,%0 |
085261c8 AK |
2693 | sty\t%1,%0 |
2694 | vlr\t%v0,%v1 | |
298f4647 | 2695 | vleif\t%v0,0,0 |
085261c8 AK |
2696 | vlvgf\t%v0,%1,0 |
2697 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2698 | vlef\t%0,%1,0 |
2699 | vstef\t%1,%0,0" | |
ae1c6198 | 2700 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2701 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2702 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2703 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2704 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx") |
2705 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2706 | |
9dc62c00 AK |
2707 | ; |
2708 | ; movcc instruction pattern | |
2709 | ; | |
2710 | ||
2711 | (define_insn "movcc" | |
2712 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2713 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2714 | "" |
2715 | "@ | |
2716 | lr\t%0,%1 | |
2717 | tmh\t%1,12288 | |
2718 | ipm\t%0 | |
a71f0749 DV |
2719 | l\t%0,%1 |
2720 | ly\t%0,%1 | |
2721 | st\t%1,%0 | |
2722 | sty\t%1,%0" | |
8dd3b235 | 2723 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2724 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2725 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2726 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2727 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2728 | |
19b63d8e UW |
2729 | ; |
2730 | ; Block move (MVC) patterns. | |
2731 | ; | |
2732 | ||
2733 | (define_insn "*mvc" | |
2734 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2735 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2736 | (use (match_operand 2 "const_int_operand" "n"))] | |
2737 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2738 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2739 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2740 | |
0a88561f AK |
2741 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2742 | ; order to have it implemented with mvc. | |
2743 | ||
2744 | (define_split | |
2745 | [(set (match_operand:QI 0 "memory_operand" "") | |
2746 | (match_operand:QI 1 "memory_operand" ""))] | |
2747 | "reload_completed" | |
2748 | [(parallel | |
2749 | [(set (match_dup 0) (match_dup 1)) | |
2750 | (use (const_int 1))])] | |
2751 | { | |
2752 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2753 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2754 | }) | |
2755 | ||
2756 | ||
19b63d8e UW |
2757 | (define_peephole2 |
2758 | [(parallel | |
2759 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2760 | (match_operand:BLK 1 "memory_operand" "")) | |
2761 | (use (match_operand 2 "const_int_operand" ""))]) | |
2762 | (parallel | |
2763 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2764 | (match_operand:BLK 4 "memory_operand" "")) | |
2765 | (use (match_operand 5 "const_int_operand" ""))])] | |
f9dcf14a AK |
2766 | "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) |
2767 | || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) | |
2768 | && s390_offset_p (operands[0], operands[3], operands[2]) | |
19b63d8e | 2769 | && s390_offset_p (operands[1], operands[4], operands[2]) |
9381e3f1 | 2770 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2771 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2772 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2773 | [(parallel | |
2774 | [(set (match_dup 6) (match_dup 7)) | |
2775 | (use (match_dup 8))])] | |
2776 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2777 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2778 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2779 | ||
f9dcf14a AK |
2780 | (define_peephole2 |
2781 | [(parallel | |
2782 | [(set (match_operand:BLK 0 "plus16_Q_operand" "") | |
2783 | (match_operand:BLK 1 "plus16_Q_operand" "")) | |
2784 | (use (match_operand 2 "const_int_operand" ""))])] | |
2785 | "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" | |
2786 | [(parallel | |
2787 | [(set (match_dup 0) (match_dup 1)) | |
2788 | (use (const_int 16))]) | |
2789 | (parallel | |
2790 | [(set (match_dup 3) (match_dup 4)) | |
2791 | (use (match_dup 5))])] | |
2792 | "operands[3] = change_address (operands[0], VOIDmode, | |
2793 | plus_constant (Pmode, XEXP (operands[0], 0), 16)); | |
2794 | operands[4] = change_address (operands[1], VOIDmode, | |
2795 | plus_constant (Pmode, XEXP (operands[1], 0), 16)); | |
2796 | operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") | |
2797 | ||
19b63d8e | 2798 | |
9db1d521 HP |
2799 | ; |
2800 | ; load_multiple pattern(s). | |
2801 | ; | |
22ea6b4f UW |
2802 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2803 | ; we currently support load_multiple/store_multiple only after reload. | |
2804 | ; | |
9db1d521 HP |
2805 | |
2806 | (define_expand "load_multiple" | |
2807 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2808 | (match_operand 1 "" "")) | |
2809 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2810 | "reload_completed" |
9db1d521 | 2811 | { |
ef4bddc2 | 2812 | machine_mode mode; |
9db1d521 HP |
2813 | int regno; |
2814 | int count; | |
2815 | rtx from; | |
4023fb28 | 2816 | int i, off; |
9db1d521 HP |
2817 | |
2818 | /* Support only loading a constant number of fixed-point registers from | |
2819 | memory and only bother with this if more than two */ | |
2820 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2821 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2822 | || INTVAL (operands[2]) > 16 |
2823 | || GET_CODE (operands[1]) != MEM | |
2824 | || GET_CODE (operands[0]) != REG | |
2825 | || REGNO (operands[0]) >= 16) | |
2826 | FAIL; | |
2827 | ||
2828 | count = INTVAL (operands[2]); | |
2829 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2830 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2831 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2832 | FAIL; |
9db1d521 HP |
2833 | |
2834 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2835 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2836 | { |
2837 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2838 | { | |
2839 | from = XEXP (operands[1], 0); | |
2840 | off = 0; | |
2841 | } | |
2842 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2843 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2844 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2845 | { | |
2846 | from = XEXP (XEXP (operands[1], 0), 0); | |
2847 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2848 | } | |
2849 | else | |
2850 | FAIL; | |
4023fb28 UW |
2851 | } |
2852 | else | |
2853 | { | |
2854 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2855 | off = 0; | |
2856 | } | |
9db1d521 HP |
2857 | |
2858 | for (i = 0; i < count; i++) | |
2859 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2860 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2861 | change_address (operands[1], mode, |
0a81f074 RS |
2862 | plus_constant (Pmode, from, |
2863 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2864 | }) |
9db1d521 HP |
2865 | |
2866 | (define_insn "*load_multiple_di" | |
2867 | [(match_parallel 0 "load_multiple_operation" | |
2868 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2869 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2870 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2871 | { |
2872 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2873 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2874 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2875 | } |
d3632d41 | 2876 | [(set_attr "op_type" "RSY") |
4023fb28 | 2877 | (set_attr "type" "lm")]) |
9db1d521 HP |
2878 | |
2879 | (define_insn "*load_multiple_si" | |
2880 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2881 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2882 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2883 | "reload_completed" |
9db1d521 HP |
2884 | { |
2885 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2886 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2887 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2888 | } |
d3632d41 | 2889 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2890 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2891 | (set_attr "type" "lm")]) |
9db1d521 HP |
2892 | |
2893 | ; | |
c7453384 | 2894 | ; store multiple pattern(s). |
9db1d521 HP |
2895 | ; |
2896 | ||
2897 | (define_expand "store_multiple" | |
2898 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2899 | (match_operand 1 "" "")) | |
2900 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2901 | "reload_completed" |
9db1d521 | 2902 | { |
ef4bddc2 | 2903 | machine_mode mode; |
9db1d521 HP |
2904 | int regno; |
2905 | int count; | |
2906 | rtx to; | |
4023fb28 | 2907 | int i, off; |
9db1d521 HP |
2908 | |
2909 | /* Support only storing a constant number of fixed-point registers to | |
2910 | memory and only bother with this if more than two. */ | |
2911 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2912 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2913 | || INTVAL (operands[2]) > 16 |
2914 | || GET_CODE (operands[0]) != MEM | |
2915 | || GET_CODE (operands[1]) != REG | |
2916 | || REGNO (operands[1]) >= 16) | |
2917 | FAIL; | |
2918 | ||
2919 | count = INTVAL (operands[2]); | |
2920 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2921 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2922 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2923 | FAIL; |
9db1d521 HP |
2924 | |
2925 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2926 | |
b3a13419 | 2927 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2928 | { |
2929 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2930 | { | |
2931 | to = XEXP (operands[0], 0); | |
2932 | off = 0; | |
2933 | } | |
2934 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2935 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2936 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2937 | { | |
2938 | to = XEXP (XEXP (operands[0], 0), 0); | |
2939 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2940 | } | |
2941 | else | |
2942 | FAIL; | |
4023fb28 | 2943 | } |
c7453384 | 2944 | else |
4023fb28 UW |
2945 | { |
2946 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2947 | off = 0; | |
2948 | } | |
9db1d521 HP |
2949 | |
2950 | for (i = 0; i < count; i++) | |
2951 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2952 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2953 | plus_constant (Pmode, to, |
2954 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2955 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2956 | }) |
9db1d521 HP |
2957 | |
2958 | (define_insn "*store_multiple_di" | |
2959 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2960 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2961 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2962 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2963 | { |
2964 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2965 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2966 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2967 | } |
d3632d41 | 2968 | [(set_attr "op_type" "RSY") |
4023fb28 | 2969 | (set_attr "type" "stm")]) |
9db1d521 HP |
2970 | |
2971 | ||
2972 | (define_insn "*store_multiple_si" | |
2973 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2974 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2975 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2976 | "reload_completed" |
9db1d521 HP |
2977 | { |
2978 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2979 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2980 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2981 | } |
d3632d41 | 2982 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2983 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2984 | (set_attr "type" "stm")]) |
9db1d521 HP |
2985 | |
2986 | ;; | |
2987 | ;; String instructions. | |
2988 | ;; | |
2989 | ||
963fc8d0 | 2990 | (define_insn "*execute_rl" |
2771c2f9 | 2991 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2992 | [(unspec [(match_operand 1 "register_operand" "a") |
2993 | (match_operand 2 "" "") | |
2994 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2995 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2996 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2997 | "exrl\t%1,%3" | |
2998 | [(set_attr "op_type" "RIL") | |
14cfceb7 IL |
2999 | (set_attr "type" "cs") |
3000 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 3001 | |
9bb86f41 | 3002 | (define_insn "*execute" |
2771c2f9 | 3003 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
3004 | [(unspec [(match_operand 1 "register_operand" "a") |
3005 | (match_operand:BLK 2 "memory_operand" "R") | |
3006 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
3007 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
3008 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
3009 | "ex\t%1,%2" | |
29a74354 UW |
3010 | [(set_attr "op_type" "RX") |
3011 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
3012 | |
3013 | ||
91d39d71 UW |
3014 | ; |
3015 | ; strlenM instruction pattern(s). | |
3016 | ; | |
3017 | ||
9db2f16d | 3018 | (define_expand "strlen<mode>" |
085261c8 AK |
3019 | [(match_operand:P 0 "register_operand" "") ; result |
3020 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
3021 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
3022 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
3023 | "" | |
3024 | { | |
3025 | if (!TARGET_VX || operands[2] != const0_rtx) | |
3026 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
3027 | operands[2], operands[3])); | |
3028 | else | |
3029 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
3030 | ||
3031 | DONE; | |
3032 | }) | |
3033 | ||
3034 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 3035 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 3036 | (parallel |
91d39d71 | 3037 | [(set (match_dup 4) |
9db2f16d | 3038 | (unspec:P [(const_int 0) |
91d39d71 | 3039 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 3040 | (reg:SI 0) |
91d39d71 | 3041 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3042 | (clobber (scratch:P)) |
ae156f85 | 3043 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 3044 | (parallel |
9db2f16d AS |
3045 | [(set (match_operand:P 0 "register_operand" "") |
3046 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 3047 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 3048 | "" |
91d39d71 | 3049 | { |
9db2f16d AS |
3050 | operands[4] = gen_reg_rtx (Pmode); |
3051 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
3052 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3053 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
3054 | }) | |
3055 | ||
9db2f16d AS |
3056 | (define_insn "*strlen<mode>" |
3057 | [(set (match_operand:P 0 "register_operand" "=a") | |
3058 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
3059 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 3060 | (reg:SI 0) |
91d39d71 | 3061 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3062 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 3063 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 3064 | "" |
91d39d71 | 3065 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
3066 | [(set_attr "length" "8") |
3067 | (set_attr "type" "vs")]) | |
91d39d71 | 3068 | |
ccbdc0d4 AS |
3069 | ; |
3070 | ; cmpstrM instruction pattern(s). | |
3071 | ; | |
3072 | ||
3073 | (define_expand "cmpstrsi" | |
3074 | [(set (reg:SI 0) (const_int 0)) | |
3075 | (parallel | |
3076 | [(clobber (match_operand 3 "" "")) | |
3077 | (clobber (match_dup 4)) | |
3078 | (set (reg:CCU CC_REGNUM) | |
3079 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
3080 | (match_operand:BLK 2 "memory_operand" ""))) | |
3081 | (use (reg:SI 0))]) | |
3082 | (parallel | |
3083 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3084 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
3085 | (clobber (reg:CC CC_REGNUM))])] |
3086 | "" | |
3087 | { | |
3088 | /* As the result of CMPINT is inverted compared to what we need, | |
3089 | we have to swap the operands. */ | |
3090 | rtx op1 = operands[2]; | |
3091 | rtx op2 = operands[1]; | |
3092 | rtx addr1 = gen_reg_rtx (Pmode); | |
3093 | rtx addr2 = gen_reg_rtx (Pmode); | |
3094 | ||
3095 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
3096 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
3097 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
3098 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
3099 | operands[3] = addr1; | |
3100 | operands[4] = addr2; | |
3101 | }) | |
3102 | ||
3103 | (define_insn "*cmpstr<mode>" | |
3104 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3105 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3106 | (set (reg:CCU CC_REGNUM) | |
3107 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3108 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3109 | (use (reg:SI 0))] | |
3110 | "" | |
3111 | "clst\t%0,%1\;jo\t.-4" | |
3112 | [(set_attr "length" "8") | |
3113 | (set_attr "type" "vs")]) | |
9381e3f1 | 3114 | |
742090fc AS |
3115 | ; |
3116 | ; movstr instruction pattern. | |
3117 | ; | |
3118 | ||
3119 | (define_expand "movstr" | |
4a7dec25 DV |
3120 | [(match_operand 0 "register_operand" "") |
3121 | (match_operand 1 "memory_operand" "") | |
3122 | (match_operand 2 "memory_operand" "")] | |
3123 | "" | |
3124 | { | |
3125 | if (TARGET_64BIT) | |
3126 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3127 | else | |
3128 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3129 | DONE; | |
3130 | }) | |
3131 | ||
3132 | (define_expand "movstr<P:mode>" | |
742090fc | 3133 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3134 | (parallel |
742090fc AS |
3135 | [(clobber (match_dup 3)) |
3136 | (set (match_operand:BLK 1 "memory_operand" "") | |
3137 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3138 | (set (match_operand:P 0 "register_operand" "") |
3139 | (unspec:P [(match_dup 1) | |
742090fc AS |
3140 | (match_dup 2) |
3141 | (reg:SI 0)] UNSPEC_MVST)) | |
3142 | (clobber (reg:CC CC_REGNUM))])] | |
3143 | "" | |
3144 | { | |
859a4c0e AK |
3145 | rtx addr1, addr2; |
3146 | ||
3147 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3148 | { | |
3149 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3150 | DONE; | |
3151 | } | |
3152 | ||
3153 | addr1 = gen_reg_rtx (Pmode); | |
3154 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3155 | |
3156 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3157 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3158 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3159 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3160 | operands[3] = addr2; | |
3161 | }) | |
3162 | ||
3163 | (define_insn "*movstr" | |
3164 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3165 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3166 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3167 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3168 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3169 | (mem:BLK (match_dup 3)) |
3170 | (reg:SI 0)] UNSPEC_MVST)) | |
3171 | (clobber (reg:CC CC_REGNUM))] | |
3172 | "" | |
3173 | "mvst\t%1,%2\;jo\t.-4" | |
3174 | [(set_attr "length" "8") | |
3175 | (set_attr "type" "vs")]) | |
9381e3f1 | 3176 | |
742090fc | 3177 | |
9db1d521 | 3178 | ; |
70128ad9 | 3179 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3180 | ; |
3181 | ||
9db2f16d | 3182 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3183 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3184 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3185 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3186 | (match_operand 3 "" "")] |
3187 | "" | |
367d32f3 AK |
3188 | { |
3189 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3190 | DONE; | |
3191 | else | |
3192 | FAIL; | |
3193 | }) | |
9db1d521 | 3194 | |
ecbe845e UW |
3195 | ; Move a block that is up to 256 bytes in length. |
3196 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3197 | |
70128ad9 | 3198 | (define_expand "movmem_short" |
b9404c99 UW |
3199 | [(parallel |
3200 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3201 | (match_operand:BLK 1 "memory_operand" "")) | |
3202 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3203 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3204 | (clobber (match_dup 3))])] |
3205 | "" | |
3206 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3207 | |
70128ad9 | 3208 | (define_insn "*movmem_short" |
963fc8d0 AK |
3209 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3210 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3211 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3212 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3213 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3214 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3215 | "#" |
963fc8d0 | 3216 | [(set_attr "type" "cs") |
b5e0425c | 3217 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3218 | |
9bb86f41 UW |
3219 | (define_split |
3220 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3221 | (match_operand:BLK 1 "memory_operand" "")) | |
3222 | (use (match_operand 2 "const_int_operand" "")) | |
3223 | (use (match_operand 3 "immediate_operand" "")) | |
3224 | (clobber (scratch))] | |
3225 | "reload_completed" | |
3226 | [(parallel | |
3227 | [(set (match_dup 0) (match_dup 1)) | |
3228 | (use (match_dup 2))])] | |
3229 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3230 | |
9bb86f41 UW |
3231 | (define_split |
3232 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3233 | (match_operand:BLK 1 "memory_operand" "")) | |
3234 | (use (match_operand 2 "register_operand" "")) | |
3235 | (use (match_operand 3 "memory_operand" "")) | |
3236 | (clobber (scratch))] | |
3237 | "reload_completed" | |
3238 | [(parallel | |
3239 | [(unspec [(match_dup 2) (match_dup 3) | |
3240 | (const_int 0)] UNSPEC_EXECUTE) | |
3241 | (set (match_dup 0) (match_dup 1)) | |
3242 | (use (const_int 1))])] | |
3243 | "") | |
3244 | ||
963fc8d0 AK |
3245 | (define_split |
3246 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3247 | (match_operand:BLK 1 "memory_operand" "")) | |
3248 | (use (match_operand 2 "register_operand" "")) | |
3249 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3250 | (clobber (scratch))] | |
3251 | "TARGET_Z10 && reload_completed" | |
3252 | [(parallel | |
3253 | [(unspec [(match_dup 2) (const_int 0) | |
3254 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3255 | (set (match_dup 0) (match_dup 1)) | |
3256 | (use (const_int 1))])] | |
3257 | "operands[3] = gen_label_rtx ();") | |
3258 | ||
9bb86f41 UW |
3259 | (define_split |
3260 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3261 | (match_operand:BLK 1 "memory_operand" "")) | |
3262 | (use (match_operand 2 "register_operand" "")) | |
3263 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3264 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3265 | "reload_completed" |
9bb86f41 UW |
3266 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3267 | (parallel | |
9381e3f1 | 3268 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3269 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3270 | (set (match_dup 0) (match_dup 1)) | |
3271 | (use (const_int 1))])] | |
3272 | "operands[4] = gen_label_rtx ();") | |
3273 | ||
a41c6c53 | 3274 | ; Move a block of arbitrary length. |
9db1d521 | 3275 | |
70128ad9 | 3276 | (define_expand "movmem_long" |
b9404c99 UW |
3277 | [(parallel |
3278 | [(clobber (match_dup 2)) | |
3279 | (clobber (match_dup 3)) | |
3280 | (set (match_operand:BLK 0 "memory_operand" "") | |
3281 | (match_operand:BLK 1 "memory_operand" "")) | |
3282 | (use (match_operand 2 "general_operand" "")) | |
3283 | (use (match_dup 3)) | |
ae156f85 | 3284 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3285 | "" |
3286 | { | |
ef4bddc2 RS |
3287 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3288 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3289 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3290 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3291 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3292 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3293 | rtx len0 = gen_lowpart (Pmode, reg0); |
3294 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3295 | ||
c41c1387 | 3296 | emit_clobber (reg0); |
b9404c99 UW |
3297 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3298 | emit_move_insn (len0, operands[2]); | |
3299 | ||
c41c1387 | 3300 | emit_clobber (reg1); |
b9404c99 UW |
3301 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3302 | emit_move_insn (len1, operands[2]); | |
3303 | ||
3304 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3305 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3306 | operands[2] = reg0; | |
3307 | operands[3] = reg1; | |
3308 | }) | |
3309 | ||
a1aed706 AS |
3310 | (define_insn "*movmem_long" |
3311 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3312 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3313 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3314 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3315 | (use (match_dup 2)) |
3316 | (use (match_dup 3)) | |
ae156f85 | 3317 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3318 | "TARGET_64BIT || !TARGET_ZARCH" |
3319 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3320 | [(set_attr "length" "8") | |
3321 | (set_attr "type" "vs")]) | |
3322 | ||
3323 | (define_insn "*movmem_long_31z" | |
3324 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3325 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3326 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3327 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3328 | (use (match_dup 2)) | |
3329 | (use (match_dup 3)) | |
3330 | (clobber (reg:CC CC_REGNUM))] | |
3331 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3332 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3333 | [(set_attr "length" "8") |
3334 | (set_attr "type" "vs")]) | |
9db1d521 | 3335 | |
638e37c2 WG |
3336 | |
3337 | ; | |
3338 | ; Test data class. | |
3339 | ; | |
3340 | ||
0f67fa83 WG |
3341 | (define_expand "signbit<mode>2" |
3342 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3343 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3344 | (match_dup 2)] | |
0f67fa83 WG |
3345 | UNSPEC_TDC_INSN)) |
3346 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3347 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3348 | "TARGET_HARD_FLOAT" |
3349 | { | |
3350 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3351 | }) | |
3352 | ||
638e37c2 WG |
3353 | (define_expand "isinf<mode>2" |
3354 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3355 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3356 | (match_dup 2)] | |
638e37c2 WG |
3357 | UNSPEC_TDC_INSN)) |
3358 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3359 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3360 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3361 | { |
3362 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3363 | }) | |
3364 | ||
085261c8 AK |
3365 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3366 | ; instruction will be issued by reload. The constraint of operand 1 | |
3367 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3368 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3369 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3370 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3371 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3372 | UNSPEC_CC_TO_INT))] | |
3373 | "operands != NULL" | |
3374 | "#" | |
3375 | "reload_completed" | |
3376 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3377 | ||
638e37c2 WG |
3378 | ; This insn is used to generate all variants of the Test Data Class |
3379 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3380 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3381 | ; specifying the required test(s). |
638e37c2 | 3382 | ; |
be5de7a1 | 3383 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3384 | (define_insn "*TDC_insn_<mode>" |
3385 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3386 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3387 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3388 | "TARGET_HARD_FLOAT" |
0387c142 | 3389 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3390 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3391 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3392 | |
638e37c2 WG |
3393 | |
3394 | ||
9db1d521 | 3395 | ; |
57e84f18 | 3396 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3397 | ; |
3398 | ||
57e84f18 | 3399 | (define_expand "setmem<mode>" |
a41c6c53 | 3400 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3401 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3402 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3403 | (match_operand 3 "" "")] |
a41c6c53 | 3404 | "" |
6d057022 | 3405 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3406 | |
a41c6c53 | 3407 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3408 | ; The block length is taken as (operands[1] % 256) + 1. |
3409 | ||
70128ad9 | 3410 | (define_expand "clrmem_short" |
b9404c99 UW |
3411 | [(parallel |
3412 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3413 | (const_int 0)) | |
3414 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3415 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3416 | (clobber (match_dup 2)) |
ae156f85 | 3417 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3418 | "" |
3419 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3420 | |
70128ad9 | 3421 | (define_insn "*clrmem_short" |
963fc8d0 | 3422 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3423 | (const_int 0)) |
963fc8d0 AK |
3424 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3425 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3426 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3427 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3428 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3429 | "#" |
963fc8d0 | 3430 | [(set_attr "type" "cs") |
b5e0425c | 3431 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3432 | |
3433 | (define_split | |
3434 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3435 | (const_int 0)) | |
3436 | (use (match_operand 1 "const_int_operand" "")) | |
3437 | (use (match_operand 2 "immediate_operand" "")) | |
3438 | (clobber (scratch)) | |
ae156f85 | 3439 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3440 | "reload_completed" |
3441 | [(parallel | |
3442 | [(set (match_dup 0) (const_int 0)) | |
3443 | (use (match_dup 1)) | |
ae156f85 | 3444 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3445 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3446 | |
9bb86f41 UW |
3447 | (define_split |
3448 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3449 | (const_int 0)) | |
3450 | (use (match_operand 1 "register_operand" "")) | |
3451 | (use (match_operand 2 "memory_operand" "")) | |
3452 | (clobber (scratch)) | |
ae156f85 | 3453 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3454 | "reload_completed" |
3455 | [(parallel | |
3456 | [(unspec [(match_dup 1) (match_dup 2) | |
3457 | (const_int 0)] UNSPEC_EXECUTE) | |
3458 | (set (match_dup 0) (const_int 0)) | |
3459 | (use (const_int 1)) | |
ae156f85 | 3460 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3461 | "") |
9db1d521 | 3462 | |
963fc8d0 AK |
3463 | (define_split |
3464 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3465 | (const_int 0)) | |
3466 | (use (match_operand 1 "register_operand" "")) | |
3467 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3468 | (clobber (scratch)) | |
3469 | (clobber (reg:CC CC_REGNUM))] | |
3470 | "TARGET_Z10 && reload_completed" | |
3471 | [(parallel | |
3472 | [(unspec [(match_dup 1) (const_int 0) | |
3473 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3474 | (set (match_dup 0) (const_int 0)) | |
3475 | (use (const_int 1)) | |
3476 | (clobber (reg:CC CC_REGNUM))])] | |
3477 | "operands[3] = gen_label_rtx ();") | |
3478 | ||
9bb86f41 UW |
3479 | (define_split |
3480 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3481 | (const_int 0)) | |
3482 | (use (match_operand 1 "register_operand" "")) | |
3483 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3484 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3485 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 3486 | "reload_completed" |
9bb86f41 UW |
3487 | [(set (match_dup 2) (label_ref (match_dup 3))) |
3488 | (parallel | |
9381e3f1 | 3489 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3490 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3491 | (set (match_dup 0) (const_int 0)) | |
3492 | (use (const_int 1)) | |
ae156f85 | 3493 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3494 | "operands[3] = gen_label_rtx ();") |
3495 | ||
9381e3f1 | 3496 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3497 | |
da0dcab1 | 3498 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3499 | [(parallel |
3500 | [(clobber (match_dup 1)) | |
3501 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3502 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3503 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3504 | (use (match_dup 3)) |
ae156f85 | 3505 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3506 | "" |
a41c6c53 | 3507 | { |
ef4bddc2 RS |
3508 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3509 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3510 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3511 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3512 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3513 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3514 | |
c41c1387 | 3515 | emit_clobber (reg0); |
b9404c99 UW |
3516 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3517 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3518 | |
b9404c99 | 3519 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3520 | |
b9404c99 UW |
3521 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3522 | operands[1] = reg0; | |
6d057022 | 3523 | operands[3] = reg1; |
da0dcab1 | 3524 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3525 | }) |
a41c6c53 | 3526 | |
da0dcab1 DV |
3527 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3528 | ||
db340c73 | 3529 | (define_insn "*setmem_long" |
a1aed706 | 3530 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3531 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3532 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3533 | (subreg:P (match_dup 3) <modesize>)] |
3534 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3535 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3536 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3537 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3538 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3539 | [(set_attr "length" "8") |
3540 | (set_attr "type" "vs")]) | |
9db1d521 | 3541 | |
db340c73 AK |
3542 | (define_insn "*setmem_long_and" |
3543 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3544 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3545 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3546 | (subreg:P (match_dup 3) <modesize>)] |
3547 | UNSPEC_REPLICATE_BYTE)) | |
3548 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3549 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3550 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3551 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3552 | [(set_attr "length" "8") | |
3553 | (set_attr "type" "vs")]) | |
3554 | ||
da0dcab1 DV |
3555 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3556 | ; of the SImode subregs. | |
3557 | ||
db340c73 | 3558 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3559 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3560 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3561 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3562 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3563 | (use (match_operand:TI 1 "register_operand" "d")) |
3564 | (clobber (reg:CC CC_REGNUM))] | |
3565 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3566 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3567 | [(set_attr "length" "8") | |
3568 | (set_attr "type" "vs")]) | |
9602b6a1 | 3569 | |
db340c73 AK |
3570 | (define_insn "*setmem_long_and_31z" |
3571 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3572 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3573 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3574 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3575 | (use (match_operand:TI 1 "register_operand" "d")) | |
3576 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3577 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3578 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3579 | [(set_attr "length" "8") | |
3580 | (set_attr "type" "vs")]) | |
3581 | ||
9db1d521 | 3582 | ; |
358b8f01 | 3583 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3584 | ; |
3585 | ||
358b8f01 | 3586 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3587 | [(set (match_operand:SI 0 "register_operand" "") |
3588 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3589 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3590 | (use (match_operand:SI 3 "general_operand" "")) | |
3591 | (use (match_operand:SI 4 "" ""))] | |
3592 | "" | |
367d32f3 AK |
3593 | { |
3594 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3595 | operands[2], operands[3])) | |
3596 | DONE; | |
3597 | else | |
3598 | FAIL; | |
3599 | }) | |
9db1d521 | 3600 | |
a41c6c53 UW |
3601 | ; Compare a block that is up to 256 bytes in length. |
3602 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3603 | |
b9404c99 UW |
3604 | (define_expand "cmpmem_short" |
3605 | [(parallel | |
ae156f85 | 3606 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3607 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3608 | (match_operand:BLK 1 "memory_operand" ""))) |
3609 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3610 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3611 | (clobber (match_dup 3))])] |
3612 | "" | |
3613 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3614 | |
b9404c99 | 3615 | (define_insn "*cmpmem_short" |
ae156f85 | 3616 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3617 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3618 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3619 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3620 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3621 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3622 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3623 | "#" |
963fc8d0 | 3624 | [(set_attr "type" "cs") |
b5e0425c | 3625 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3626 | |
9bb86f41 | 3627 | (define_split |
ae156f85 | 3628 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3629 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3630 | (match_operand:BLK 1 "memory_operand" ""))) | |
3631 | (use (match_operand 2 "const_int_operand" "")) | |
3632 | (use (match_operand 3 "immediate_operand" "")) | |
3633 | (clobber (scratch))] | |
3634 | "reload_completed" | |
3635 | [(parallel | |
ae156f85 | 3636 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3637 | (use (match_dup 2))])] |
3638 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3639 | |
9bb86f41 | 3640 | (define_split |
ae156f85 | 3641 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3642 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3643 | (match_operand:BLK 1 "memory_operand" ""))) | |
3644 | (use (match_operand 2 "register_operand" "")) | |
3645 | (use (match_operand 3 "memory_operand" "")) | |
3646 | (clobber (scratch))] | |
3647 | "reload_completed" | |
3648 | [(parallel | |
3649 | [(unspec [(match_dup 2) (match_dup 3) | |
3650 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3651 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3652 | (use (const_int 1))])] |
3653 | "") | |
3654 | ||
963fc8d0 AK |
3655 | (define_split |
3656 | [(set (reg:CCU CC_REGNUM) | |
3657 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3658 | (match_operand:BLK 1 "memory_operand" ""))) | |
3659 | (use (match_operand 2 "register_operand" "")) | |
3660 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3661 | (clobber (scratch))] | |
3662 | "TARGET_Z10 && reload_completed" | |
3663 | [(parallel | |
3664 | [(unspec [(match_dup 2) (const_int 0) | |
3665 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3666 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3667 | (use (const_int 1))])] | |
3668 | "operands[4] = gen_label_rtx ();") | |
3669 | ||
9bb86f41 | 3670 | (define_split |
ae156f85 | 3671 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3672 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3673 | (match_operand:BLK 1 "memory_operand" ""))) | |
3674 | (use (match_operand 2 "register_operand" "")) | |
3675 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3676 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3677 | "reload_completed" |
9bb86f41 UW |
3678 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3679 | (parallel | |
9381e3f1 | 3680 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3681 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3682 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3683 | (use (const_int 1))])] |
3684 | "operands[4] = gen_label_rtx ();") | |
3685 | ||
a41c6c53 | 3686 | ; Compare a block of arbitrary length. |
9db1d521 | 3687 | |
b9404c99 UW |
3688 | (define_expand "cmpmem_long" |
3689 | [(parallel | |
3690 | [(clobber (match_dup 2)) | |
3691 | (clobber (match_dup 3)) | |
ae156f85 | 3692 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3693 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3694 | (match_operand:BLK 1 "memory_operand" ""))) |
3695 | (use (match_operand 2 "general_operand" "")) | |
3696 | (use (match_dup 3))])] | |
3697 | "" | |
3698 | { | |
ef4bddc2 RS |
3699 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3700 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3701 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3702 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3703 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3704 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3705 | rtx len0 = gen_lowpart (Pmode, reg0); |
3706 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3707 | ||
c41c1387 | 3708 | emit_clobber (reg0); |
b9404c99 UW |
3709 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3710 | emit_move_insn (len0, operands[2]); | |
3711 | ||
c41c1387 | 3712 | emit_clobber (reg1); |
b9404c99 UW |
3713 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3714 | emit_move_insn (len1, operands[2]); | |
3715 | ||
3716 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3717 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3718 | operands[2] = reg0; | |
3719 | operands[3] = reg1; | |
3720 | }) | |
3721 | ||
a1aed706 AS |
3722 | (define_insn "*cmpmem_long" |
3723 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3724 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3725 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3726 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3727 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3728 | (use (match_dup 2)) |
3729 | (use (match_dup 3))] | |
9602b6a1 | 3730 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3731 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3732 | [(set_attr "length" "8") |
3733 | (set_attr "type" "vs")]) | |
9db1d521 | 3734 | |
9602b6a1 AK |
3735 | (define_insn "*cmpmem_long_31z" |
3736 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3737 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3738 | (set (reg:CCU CC_REGNUM) | |
3739 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3740 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3741 | (use (match_dup 2)) | |
3742 | (use (match_dup 3))] | |
3743 | "!TARGET_64BIT && TARGET_ZARCH" | |
3744 | "clcle\t%0,%1,0\;jo\t.-4" | |
3745 | [(set_attr "op_type" "NN") | |
3746 | (set_attr "type" "vs") | |
3747 | (set_attr "length" "8")]) | |
3748 | ||
02887425 UW |
3749 | ; Convert CCUmode condition code to integer. |
3750 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3751 | |
02887425 | 3752 | (define_insn_and_split "cmpint" |
9db1d521 | 3753 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3754 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3755 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3756 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3757 | "" |
02887425 UW |
3758 | "#" |
3759 | "reload_completed" | |
3760 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3761 | (parallel | |
3762 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3763 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3764 | |
3765 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3766 | [(set (reg CC_REGNUM) |
02887425 | 3767 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3768 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3769 | (const_int 0))) |
3770 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3771 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3772 | "s390_match_ccmode (insn, CCSmode)" |
3773 | "#" | |
3774 | "&& reload_completed" | |
3775 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3776 | (parallel | |
3777 | [(set (match_dup 2) (match_dup 3)) | |
3778 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3779 | { |
02887425 UW |
3780 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3781 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3782 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3783 | }) | |
9db1d521 | 3784 | |
02887425 | 3785 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3786 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3787 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3788 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3789 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3790 | "TARGET_ZARCH" |
02887425 UW |
3791 | "#" |
3792 | "&& reload_completed" | |
3793 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3794 | (parallel | |
3795 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3796 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3797 | |
3798 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3799 | [(set (reg CC_REGNUM) |
9381e3f1 | 3800 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3801 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3802 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3803 | (const_int 32)) (const_int 32)) |
3804 | (const_int 0))) | |
3805 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3806 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3807 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3808 | "#" |
3809 | "&& reload_completed" | |
3810 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3811 | (parallel | |
3812 | [(set (match_dup 2) (match_dup 3)) | |
3813 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3814 | { |
02887425 UW |
3815 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3816 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3817 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3818 | }) | |
9db1d521 | 3819 | |
4023fb28 | 3820 | |
9db1d521 HP |
3821 | ;; |
3822 | ;;- Conversion instructions. | |
3823 | ;; | |
3824 | ||
6fa05db6 | 3825 | (define_insn "*sethighpartsi" |
d3632d41 | 3826 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3827 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3828 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3829 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3830 | "" |
d3632d41 | 3831 | "@ |
6fa05db6 AS |
3832 | icm\t%0,%2,%S1 |
3833 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3834 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3835 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3836 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3837 | |
6fa05db6 | 3838 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3839 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3840 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3841 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3842 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3843 | "TARGET_ZARCH" |
6fa05db6 | 3844 | "icmh\t%0,%2,%S1" |
729e750f WG |
3845 | [(set_attr "op_type" "RSY") |
3846 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3847 | |
6fa05db6 | 3848 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3849 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3850 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3851 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3852 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3853 | "!TARGET_ZARCH" |
d3632d41 | 3854 | "@ |
6fa05db6 AS |
3855 | icm\t%0,%2,%S1 |
3856 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3857 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3858 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3859 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3860 | ||
1a2e356e RH |
3861 | ; |
3862 | ; extv instruction patterns | |
3863 | ; | |
3864 | ||
3865 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3866 | ; after resolving some issues with it. | |
3867 | ||
3868 | (define_expand "extzv" | |
3869 | [(parallel | |
3870 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3871 | (zero_extract:DI | |
3872 | (match_operand:DI 1 "register_operand" "d") | |
3873 | (match_operand 2 "const_int_operand" "") ; size | |
3874 | (match_operand 3 "const_int_operand" ""))) ; start | |
3875 | (clobber (reg:CC CC_REGNUM))])] | |
3876 | "TARGET_Z10" | |
3877 | { | |
0f6f72e8 DV |
3878 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3879 | FAIL; | |
1a2e356e RH |
3880 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3881 | if (TARGET_ZEC12) | |
3882 | { | |
3883 | emit_move_insn (operands[0], | |
3884 | gen_rtx_ZERO_EXTRACT (DImode, | |
3885 | operands[1], | |
3886 | operands[2], | |
3887 | operands[3])); | |
3888 | DONE; | |
3889 | } | |
3890 | }) | |
3891 | ||
64c744b9 | 3892 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3893 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3894 | (zero_extract:GPR | |
3895 | (match_operand:GPR 1 "register_operand" "d") | |
3896 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3897 | (match_operand 3 "const_int_operand" ""))) ; start |
3898 | ] | |
0f6f72e8 DV |
3899 | "<z10_or_zEC12_cond> |
3900 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3901 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3902 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3903 | [(set_attr "op_type" "RIE") | |
3904 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3905 | |
64c744b9 DV |
3906 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3907 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3908 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3909 | (match_operand 1 "const_int_operand" "") ; size | |
3910 | (match_operand 2 "const_int_operand" "")) ; start | |
3911 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3912 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3913 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3914 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3915 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3916 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3917 | [(set_attr "op_type" "RIE") | |
3918 | (set_attr "z10prop" "z10_super_E1")]) | |
3919 | ||
3920 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3921 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3922 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3923 | (ior:SI (and:SI | |
3924 | (match_operand:SI 1 "register_operand" "0") | |
3925 | (match_operand:SI 2 "const_int_operand" "")) | |
3926 | (subreg:SI | |
3927 | (zero_extract:DI | |
3928 | (match_operand:DI 3 "register_operand" "d") | |
3929 | (match_operand 4 "const_int_operand" "") ; size | |
3930 | (match_operand 5 "const_int_operand" "")) ; start | |
3931 | 4)))] | |
3932 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3933 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
64c744b9 DV |
3934 | && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))" |
3935 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" | |
3936 | [(set_attr "op_type" "RIE") | |
3937 | (set_attr "z10prop" "z10_super_E1")]) | |
3938 | ||
3939 | ; ((int)foo >> 10) & 1; | |
3940 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3941 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3942 | (ne:DI (zero_extract:DI | |
3943 | (match_operand:DI 1 "register_operand" "d") | |
3944 | (const_int 1) ; size | |
3945 | (match_operand 2 "const_int_operand" "")) ; start | |
3946 | (const_int 0)))] | |
0f6f72e8 DV |
3947 | "<z10_or_zEC12_cond> |
3948 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3949 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3950 | [(set_attr "op_type" "RIE") | |
3951 | (set_attr "z10prop" "z10_super_E1")]) | |
3952 | ||
3953 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3954 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3955 | (and:DI (subreg:DI | |
3956 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3957 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3958 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3959 | "<z10_or_zEC12_cond> | |
3960 | && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))" | |
3961 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift | |
3962 | [(set_attr "op_type" "RIE") | |
3963 | (set_attr "z10prop" "z10_super_E1")]) | |
3964 | ||
3965 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3966 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3967 | (and:DI (subreg:DI | |
3968 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3969 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3970 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3971 | "<z10_or_zEC12_cond> | |
3972 | && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
3973 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
3974 | [(set_attr "op_type" "RIE") | |
3975 | (set_attr "z10prop" "z10_super_E1")]) | |
3976 | ||
3977 | (define_insn "*<risbg_n>_di_and_rot" | |
3978 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3979 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
3980 | (match_operand:DI 2 "const_int_operand" "")) | |
3981 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3982 | "<z10_or_zEC12_cond>" | |
3983 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
3984 | [(set_attr "op_type" "RIE") |
3985 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3986 | |
1a2e356e | 3987 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 3988 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3989 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3990 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3991 | (const_int 0))) |
ae156f85 | 3992 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3993 | "!TARGET_Z10" |
cc7ab9b7 UW |
3994 | "#" |
3995 | "&& reload_completed" | |
4023fb28 | 3996 | [(parallel |
6fa05db6 | 3997 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3998 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3999 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 4000 | { |
6fa05db6 AS |
4001 | int bitsize = INTVAL (operands[2]); |
4002 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
4003 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
4004 | ||
4005 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4006 | set_mem_size (operands[1], size); |
2542ef05 | 4007 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 4008 | operands[3] = GEN_INT (mask); |
b628bd8e | 4009 | }) |
4023fb28 | 4010 | |
1a2e356e | 4011 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 4012 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 4013 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 4014 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 4015 | (const_int 0))) |
ae156f85 | 4016 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 4017 | "" |
cc7ab9b7 UW |
4018 | "#" |
4019 | "&& reload_completed" | |
4023fb28 | 4020 | [(parallel |
6fa05db6 | 4021 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 4022 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
4023 | (parallel |
4024 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
4025 | (clobber (reg:CC CC_REGNUM))])] | |
4026 | { | |
4027 | int bitsize = INTVAL (operands[2]); | |
4028 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
4029 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
4030 | ||
4031 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4032 | set_mem_size (operands[1], size); |
2542ef05 | 4033 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
4034 | operands[3] = GEN_INT (mask); |
4035 | }) | |
4036 | ||
4037 | ; | |
4038 | ; insv instruction patterns | |
4039 | ; | |
4040 | ||
4041 | (define_expand "insv" | |
4042 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
4043 | (match_operand 1 "const_int_operand" "") | |
4044 | (match_operand 2 "const_int_operand" "")) | |
4045 | (match_operand 3 "general_operand" ""))] | |
4046 | "" | |
4023fb28 | 4047 | { |
6fa05db6 AS |
4048 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
4049 | DONE; | |
4050 | FAIL; | |
b628bd8e | 4051 | }) |
4023fb28 | 4052 | |
2542ef05 RH |
4053 | |
4054 | ; The normal RTL expansion will never generate a zero_extract where | |
4055 | ; the location operand isn't word mode. However, we do this in the | |
4056 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 4057 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 4058 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
4059 | (match_operand 1 "const_int_operand" "I") ; size |
4060 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 4061 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 4062 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
4063 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
4064 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 4065 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 4066 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
4067 | [(set_attr "op_type" "RIE") |
4068 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4069 | |
22ac2c2f AK |
4070 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
4071 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
4072 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
4073 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
4074 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 4075 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 4076 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 4077 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
4078 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
4079 | "@ | |
4080 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
4081 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
4082 | [(set_attr "op_type" "RIE") | |
4083 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 4084 | |
64c744b9 DV |
4085 | (define_insn "*insv_z10_noshift_cc" |
4086 | [(set (reg CC_REGNUM) | |
4087 | (compare | |
4088 | (ior:DI | |
4089 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4090 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4091 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4092 | (match_operand:DI 4 "const_int_operand" ""))) | |
4093 | (const_int 0))) | |
4094 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
4095 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
4096 | (and:DI (match_dup 3) (match_dup 4))))] | |
4097 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4098 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4099 | "@ | |
4100 | risbg\t%0,%1,%s2,%e2,0 | |
4101 | risbg\t%0,%3,%s4,%e4,0" | |
4102 | [(set_attr "op_type" "RIE") | |
4103 | (set_attr "z10prop" "z10_super_E1")]) | |
4104 | ||
4105 | (define_insn "*insv_z10_noshift_cconly" | |
4106 | [(set | |
4107 | (reg CC_REGNUM) | |
4108 | (compare | |
4109 | (ior:DI | |
4110 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4111 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4112 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4113 | (match_operand:DI 4 "const_int_operand" ""))) | |
4114 | (const_int 0))) | |
4115 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4116 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4117 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4118 | "@ | |
4119 | risbg\t%0,%1,%s2,%e2,0 | |
4120 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4121 | [(set_attr "op_type" "RIE") |
4122 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4123 | |
3d44ff99 AK |
4124 | ; Implement appending Y on the left of S bits of X |
4125 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4126 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4127 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4128 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4129 | (match_operand:GPR 2 "immediate_operand" "")) | |
4130 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4131 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 DV |
4132 | "<z10_or_zEC12_cond> |
4133 | && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
4134 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" | |
3d44ff99 AK |
4135 | [(set_attr "op_type" "RIE") |
4136 | (set_attr "z10prop" "z10_super_E1")]) | |
4137 | ||
64c744b9 DV |
4138 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4139 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4140 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4141 | (ior:GPR (and:GPR | |
4142 | (match_operand:GPR 1 "register_operand" "0") | |
4143 | (match_operand:GPR 2 "const_int_operand" "")) | |
4144 | (lshiftrt:GPR | |
4145 | (match_operand:GPR 3 "register_operand" "d") | |
4146 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4147 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
4148 | == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
4149 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" | |
4150 | [(set_attr "op_type" "RIE") | |
4151 | (set_attr "z10prop" "z10_super_E1")]) | |
4152 | ||
4153 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4154 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4155 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4156 | (ior:SI (and:SI | |
4157 | (match_operand:SI 1 "register_operand" "0") | |
4158 | (match_operand:SI 2 "const_int_operand" "")) | |
4159 | (subreg:SI | |
4160 | (lshiftrt:DI | |
4161 | (match_operand:DI 3 "register_operand" "d") | |
4162 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4163 | "<z10_or_zEC12_cond> | |
4164 | && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))" | |
4165 | "<risbg_n>\t%0,%3,%4,63,64-%4" | |
4166 | [(set_attr "op_type" "RIE") | |
4167 | (set_attr "z10prop" "z10_super_E1")]) | |
4168 | ||
4169 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4170 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4171 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4172 | (and:SI | |
4173 | (subreg:SI (lshiftrt:DI | |
4174 | (match_operand:DI 1 "register_operand" "d") | |
4175 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4176 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4177 | "<z10_or_zEC12_cond>" | |
4178 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4179 | [(set_attr "op_type" "RIE") |
4180 | (set_attr "z10prop" "z10_super_E1")]) | |
4181 | ||
4182 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4183 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4184 | ; -> z = y >> d; z = risbg; | |
4185 | ||
4186 | (define_split | |
4187 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4188 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4189 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4190 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4191 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4192 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4193 | [(set (match_dup 6) |
3d44ff99 AK |
4194 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4195 | (set (match_dup 0) | |
1d11f7ce | 4196 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4197 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4198 | { | |
4199 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4200 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4201 | { |
4202 | if (!can_create_pseudo_p ()) | |
4203 | FAIL; | |
4204 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4205 | } | |
4206 | else | |
4207 | operands[6] = operands[0]; | |
3d44ff99 AK |
4208 | }) |
4209 | ||
4210 | (define_split | |
4211 | [(parallel | |
4212 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4213 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4214 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4215 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4216 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4217 | (clobber (reg:CC CC_REGNUM))])] | |
4218 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4219 | [(set (match_dup 6) |
3d44ff99 AK |
4220 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4221 | (parallel | |
4222 | [(set (match_dup 0) | |
1d11f7ce | 4223 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4224 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4225 | (clobber (reg:CC CC_REGNUM))])] | |
4226 | { | |
4227 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4228 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4229 | { |
4230 | if (!can_create_pseudo_p ()) | |
4231 | FAIL; | |
4232 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4233 | } | |
4234 | else | |
4235 | operands[6] = operands[0]; | |
3d44ff99 AK |
4236 | }) |
4237 | ||
50dc4eed | 4238 | ; rosbg, rxsbg |
571e408a | 4239 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4240 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4241 | (IXOR:GPR |
4242 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4243 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4244 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4245 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4246 | "TARGET_Z10" |
571e408a RH |
4247 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4248 | [(set_attr "op_type" "RIE")]) | |
4249 | ||
50dc4eed | 4250 | ; rosbg, rxsbg |
571e408a RH |
4251 | (define_insn "*r<noxa>sbg_di_rotl" |
4252 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4253 | (IXOR:DI | |
4254 | (and:DI | |
4255 | (rotate:DI | |
4256 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4257 | (match_operand:DI 3 "const_int_operand" "")) | |
4258 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4259 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4260 | (clobber (reg:CC CC_REGNUM))] | |
4261 | "TARGET_Z10" | |
8c21b0d1 | 4262 | "r<noxa>sbg\t%0,%1,%s2,%e2,%b3" |
571e408a RH |
4263 | [(set_attr "op_type" "RIE")]) |
4264 | ||
50dc4eed | 4265 | ; rosbg, rxsbg |
f3d90045 | 4266 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4267 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4268 | (IXOR:GPR | |
4269 | (and:GPR | |
4270 | (lshiftrt:GPR | |
4271 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4272 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4273 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4274 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4275 | (clobber (reg:CC CC_REGNUM))] | |
4276 | "TARGET_Z10 | |
4277 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4278 | INTVAL (operands[2]))" | |
b9789752 IL |
4279 | { |
4280 | static char buffer[256]; | |
4281 | sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%%<bfstart>2,%%<bfend>2,%ld", | |
4282 | 64 - INTVAL (operands[3])); | |
4283 | return buffer; | |
4284 | } | |
571e408a RH |
4285 | [(set_attr "op_type" "RIE")]) |
4286 | ||
50dc4eed | 4287 | ; rosbg, rxsbg |
f3d90045 | 4288 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4289 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4290 | (IXOR:GPR | |
4291 | (and:GPR | |
4292 | (ashift:GPR | |
4293 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4294 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4295 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4296 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4297 | (clobber (reg:CC CC_REGNUM))] | |
4298 | "TARGET_Z10 | |
4299 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4300 | INTVAL (operands[2]))" | |
4301 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4302 | [(set_attr "op_type" "RIE")]) |
4303 | ||
f3d90045 DV |
4304 | ;; unsigned {int,long} a, b |
4305 | ;; a = a | (b << const_int) | |
4306 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4307 | ; rosbg, rxsbg |
f3d90045 DV |
4308 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4309 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4310 | (IXOR:GPR | |
4311 | (ashift:GPR | |
4312 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4313 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4314 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4315 | (clobber (reg:CC CC_REGNUM))] | |
4316 | "TARGET_Z10" | |
b9789752 IL |
4317 | { |
4318 | static char buffer[256]; | |
4319 | sprintf (buffer, "r<noxa>sbg\t%%0,%%1,<bitoff>,%ld,%%2", | |
4320 | 63 - INTVAL (operands[2])); | |
4321 | return buffer; | |
4322 | } | |
f3d90045 DV |
4323 | [(set_attr "op_type" "RIE")]) |
4324 | ||
4325 | ;; unsigned {int,long} a, b | |
4326 | ;; a = a | (b >> const_int) | |
4327 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4328 | ; rosbg, rxsbg |
f3d90045 DV |
4329 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4330 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4331 | (IXOR:GPR | |
4332 | (lshiftrt:GPR | |
4333 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4334 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4335 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4336 | (clobber (reg:CC CC_REGNUM))] | |
4337 | "TARGET_Z10" | |
b9789752 IL |
4338 | { |
4339 | static char buffer[256]; | |
4340 | sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%ld,63,%ld", | |
4341 | <bitoff_plus> INTVAL (operands[2]), 64 - INTVAL (operands[2])); | |
4342 | return buffer; | |
4343 | } | |
4344 | [(set_attr "op_type" "RIE")]) | |
4345 | ||
4346 | ; rosbg, rxsbg | |
4347 | (define_insn "*r<noxa>sbg_sidi_srl" | |
4348 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
4349 | (IXOR:SI | |
4350 | (subreg:SI | |
4351 | (zero_extract:DI | |
4352 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4353 | (const_int 32) | |
4354 | (match_operand:DI 2 "immediate_operand" "")) | |
4355 | 4) | |
4356 | (match_operand:SI 3 "nonimmediate_operand" "0"))) | |
4357 | (clobber (reg:CC CC_REGNUM))] | |
4358 | "TARGET_Z10" | |
4359 | { | |
4360 | static char buffer[256]; | |
4361 | sprintf (buffer, "r<noxa>sbg\t%%0,%%1,%ld,63,%ld", | |
4362 | 64 - INTVAL (operands[2]), 32 + INTVAL (operands[2])); | |
4363 | return buffer; | |
4364 | } | |
f3d90045 DV |
4365 | [(set_attr "op_type" "RIE")]) |
4366 | ||
5bb33936 RH |
4367 | ;; These two are generated by combine for s.bf &= val. |
4368 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4369 | ;; shifts and ands, which results in some truly awful patterns | |
4370 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4371 | ;; Instead of | |
4372 | ;; | |
4373 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4374 | ;; (const_int 24 [0x18]) | |
4375 | ;; (const_int 0 [0])) | |
4376 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4377 | ;; (const_int 40 [0x28])) 4) | |
4378 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4379 | ;; | |
4380 | ;; we should instead generate | |
4381 | ;; | |
4382 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4383 | ;; (const_int 24 [0x18]) | |
4384 | ;; (const_int 0 [0])) | |
4385 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4386 | ;; (const_int 40 [0x28])) | |
4387 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4388 | ;; | |
4389 | ;; by noticing that we can push down the outer paradoxical subreg | |
4390 | ;; into the operation. | |
4391 | ||
4392 | (define_insn "*insv_rnsbg_noshift" | |
4393 | [(set (zero_extract:DI | |
4394 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4395 | (match_operand 1 "const_int_operand" "") | |
4396 | (match_operand 2 "const_int_operand" "")) | |
4397 | (and:DI | |
4398 | (match_dup 0) | |
4399 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4400 | (clobber (reg:CC CC_REGNUM))] | |
4401 | "TARGET_Z10 | |
0f6f72e8 | 4402 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4403 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4404 | "rnsbg\t%0,%3,%2,63,0" | |
4405 | [(set_attr "op_type" "RIE")]) | |
4406 | ||
4407 | (define_insn "*insv_rnsbg_srl" | |
4408 | [(set (zero_extract:DI | |
4409 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4410 | (match_operand 1 "const_int_operand" "") | |
4411 | (match_operand 2 "const_int_operand" "")) | |
4412 | (and:DI | |
4413 | (lshiftrt:DI | |
4414 | (match_dup 0) | |
4415 | (match_operand 3 "const_int_operand" "")) | |
4416 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4417 | (clobber (reg:CC CC_REGNUM))] | |
4418 | "TARGET_Z10 | |
0f6f72e8 | 4419 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4420 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4421 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4422 | [(set_attr "op_type" "RIE")]) | |
4423 | ||
6fa05db6 | 4424 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4425 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4426 | (match_operand 1 "const_int_operand" "n,n") |
4427 | (const_int 0)) | |
9602b6a1 | 4428 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4429 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4430 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4431 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4432 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4433 | { | |
4434 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4435 | ||
4436 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4437 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4438 | : "stcmy\t%2,%1,%S0"; |
4439 | } | |
9381e3f1 | 4440 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4441 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4442 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4443 | |
4444 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4445 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4446 | (match_operand 1 "const_int_operand" "n") |
4447 | (const_int 0)) | |
4448 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4449 | (const_int 32)))] | |
9602b6a1 | 4450 | "TARGET_ZARCH |
0f6f72e8 | 4451 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4452 | && INTVAL (operands[1]) > 0 |
4453 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4454 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4455 | { | |
4456 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4457 | ||
4458 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4459 | return "stcmh\t%2,%1,%S0"; | |
4460 | } | |
9381e3f1 WG |
4461 | [(set_attr "op_type" "RSY") |
4462 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4463 | |
9602b6a1 AK |
4464 | (define_insn "*insvdi_reg_imm" |
4465 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4466 | (const_int 16) | |
4467 | (match_operand 1 "const_int_operand" "n")) | |
4468 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4469 | "TARGET_ZARCH |
0f6f72e8 | 4470 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4471 | && INTVAL (operands[1]) >= 0 |
4472 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4473 | && INTVAL (operands[1]) % 16 == 0" | |
4474 | { | |
4475 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4476 | { | |
4477 | case 64: return "iihh\t%0,%x2"; break; | |
4478 | case 48: return "iihl\t%0,%x2"; break; | |
4479 | case 32: return "iilh\t%0,%x2"; break; | |
4480 | case 16: return "iill\t%0,%x2"; break; | |
4481 | default: gcc_unreachable(); | |
4482 | } | |
4483 | } | |
9381e3f1 WG |
4484 | [(set_attr "op_type" "RI") |
4485 | (set_attr "z10prop" "z10_super_E1")]) | |
4486 | ||
9fec758d WG |
4487 | ; Update the left-most 32 bit of a DI. |
4488 | (define_insn "*insv_h_di_reg_extimm" | |
4489 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4490 | (const_int 32) | |
4491 | (const_int 0)) | |
4492 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4493 | "TARGET_EXTIMM" | |
4494 | "iihf\t%0,%o1" | |
4495 | [(set_attr "op_type" "RIL") | |
4496 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4497 | |
d378b983 RH |
4498 | ; Update the right-most 32 bit of a DI. |
4499 | (define_insn "*insv_l_di_reg_extimm" | |
4500 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4501 | (const_int 32) | |
4502 | (const_int 32)) | |
4503 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4504 | "TARGET_EXTIMM" | |
4505 | "iilf\t%0,%o1" | |
9381e3f1 | 4506 | [(set_attr "op_type" "RIL") |
9fec758d | 4507 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4508 | |
9db1d521 HP |
4509 | ; |
4510 | ; extendsidi2 instruction pattern(s). | |
4511 | ; | |
4512 | ||
4023fb28 UW |
4513 | (define_expand "extendsidi2" |
4514 | [(set (match_operand:DI 0 "register_operand" "") | |
4515 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4516 | "" | |
4023fb28 | 4517 | { |
9602b6a1 | 4518 | if (!TARGET_ZARCH) |
4023fb28 | 4519 | { |
c41c1387 | 4520 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4521 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4522 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4523 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4524 | DONE; |
4525 | } | |
ec24698e | 4526 | }) |
4023fb28 UW |
4527 | |
4528 | (define_insn "*extendsidi2" | |
963fc8d0 | 4529 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4530 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4531 | "TARGET_ZARCH" |
9db1d521 | 4532 | "@ |
d40c829f | 4533 | lgfr\t%0,%1 |
963fc8d0 AK |
4534 | lgf\t%0,%1 |
4535 | lgfrl\t%0,%1" | |
4536 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4537 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4538 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4539 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4540 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4541 | |
9db1d521 | 4542 | ; |
56477c21 | 4543 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4544 | ; |
4545 | ||
56477c21 AS |
4546 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4547 | [(set (match_operand:DSI 0 "register_operand" "") | |
4548 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4549 | "" |
4023fb28 | 4550 | { |
9602b6a1 | 4551 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4552 | { |
4553 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4554 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4555 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4556 | DONE; | |
4557 | } | |
ec24698e | 4558 | else if (!TARGET_EXTIMM) |
4023fb28 | 4559 | { |
2542ef05 | 4560 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4561 | |
4562 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4563 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4564 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4565 | DONE; |
4566 | } | |
ec24698e UW |
4567 | }) |
4568 | ||
56477c21 AS |
4569 | ; |
4570 | ; extendhidi2 instruction pattern(s). | |
4571 | ; | |
4572 | ||
ec24698e | 4573 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4574 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4575 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4576 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4577 | "@ |
4578 | lghr\t%0,%1 | |
963fc8d0 AK |
4579 | lgh\t%0,%1 |
4580 | lghrl\t%0,%1" | |
4581 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4582 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4583 | (set_attr "cpu_facility" "extimm,extimm,z10") |
14cfceb7 IL |
4584 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4585 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 UW |
4586 | |
4587 | (define_insn "*extendhidi2" | |
9db1d521 | 4588 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4589 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4590 | "TARGET_ZARCH" |
d40c829f | 4591 | "lgh\t%0,%1" |
9381e3f1 WG |
4592 | [(set_attr "op_type" "RXY") |
4593 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4594 | |
9db1d521 | 4595 | ; |
56477c21 | 4596 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4597 | ; |
4598 | ||
ec24698e | 4599 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4600 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4601 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4602 | "TARGET_EXTIMM" |
4603 | "@ | |
4604 | lhr\t%0,%1 | |
4605 | lh\t%0,%1 | |
963fc8d0 AK |
4606 | lhy\t%0,%1 |
4607 | lhrl\t%0,%1" | |
4608 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4609 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 | 4610 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
14cfceb7 IL |
4611 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1") |
4612 | (set_attr "relative_long" "*,*,*,yes")]) | |
9db1d521 | 4613 | |
4023fb28 | 4614 | (define_insn "*extendhisi2" |
d3632d41 UW |
4615 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4616 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4617 | "!TARGET_EXTIMM" |
d3632d41 | 4618 | "@ |
d40c829f UW |
4619 | lh\t%0,%1 |
4620 | lhy\t%0,%1" | |
9381e3f1 | 4621 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4622 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4623 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4624 | |
56477c21 AS |
4625 | ; |
4626 | ; extendqi(si|di)2 instruction pattern(s). | |
4627 | ; | |
4628 | ||
43a09b63 | 4629 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4630 | (define_insn "*extendqi<mode>2_extimm" |
4631 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4632 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4633 | "TARGET_EXTIMM" |
4634 | "@ | |
56477c21 AS |
4635 | l<g>br\t%0,%1 |
4636 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4637 | [(set_attr "op_type" "RRE,RXY") |
4638 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4639 | |
43a09b63 | 4640 | ; lb, lgb |
56477c21 AS |
4641 | (define_insn "*extendqi<mode>2" |
4642 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4643 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4644 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4645 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4646 | [(set_attr "op_type" "RXY") |
4647 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4648 | |
56477c21 AS |
4649 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4650 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4651 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4652 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4653 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4654 | "#" |
4655 | "&& reload_completed" | |
4023fb28 | 4656 | [(parallel |
56477c21 | 4657 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4658 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4659 | (parallel |
56477c21 | 4660 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4661 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4662 | { |
4663 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4664 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4665 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4666 | }) |
9db1d521 | 4667 | |
9db1d521 HP |
4668 | ; |
4669 | ; zero_extendsidi2 instruction pattern(s). | |
4670 | ; | |
4671 | ||
4023fb28 UW |
4672 | (define_expand "zero_extendsidi2" |
4673 | [(set (match_operand:DI 0 "register_operand" "") | |
4674 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4675 | "" | |
4023fb28 | 4676 | { |
9602b6a1 | 4677 | if (!TARGET_ZARCH) |
4023fb28 | 4678 | { |
c41c1387 | 4679 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4680 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4681 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4682 | DONE; |
4683 | } | |
ec24698e | 4684 | }) |
4023fb28 UW |
4685 | |
4686 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4687 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4688 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4689 | "TARGET_ZARCH" |
9db1d521 | 4690 | "@ |
d40c829f | 4691 | llgfr\t%0,%1 |
963fc8d0 AK |
4692 | llgf\t%0,%1 |
4693 | llgfrl\t%0,%1" | |
4694 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4695 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4696 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4697 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3") |
4698 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4699 | |
288e517f AK |
4700 | ; |
4701 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4702 | ; | |
4703 | ||
d6083c7d UW |
4704 | (define_insn "*llgt_sidi" |
4705 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4706 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4707 | (const_int 2147483647)))] |
9602b6a1 | 4708 | "TARGET_ZARCH" |
d6083c7d | 4709 | "llgt\t%0,%1" |
9381e3f1 WG |
4710 | [(set_attr "op_type" "RXE") |
4711 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4712 | |
4713 | (define_insn_and_split "*llgt_sidi_split" | |
4714 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4715 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4716 | (const_int 2147483647))) |
ae156f85 | 4717 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4718 | "TARGET_ZARCH" |
d6083c7d UW |
4719 | "#" |
4720 | "&& reload_completed" | |
4721 | [(set (match_dup 0) | |
4722 | (and:DI (subreg:DI (match_dup 1) 0) | |
4723 | (const_int 2147483647)))] | |
4724 | "") | |
4725 | ||
288e517f AK |
4726 | (define_insn "*llgt_sisi" |
4727 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4728 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4729 | (const_int 2147483647)))] |
c4d50129 | 4730 | "TARGET_ZARCH" |
288e517f AK |
4731 | "@ |
4732 | llgtr\t%0,%1 | |
4733 | llgt\t%0,%1" | |
9381e3f1 WG |
4734 | [(set_attr "op_type" "RRE,RXE") |
4735 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4736 | |
288e517f AK |
4737 | (define_insn "*llgt_didi" |
4738 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4739 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4740 | (const_int 2147483647)))] | |
9602b6a1 | 4741 | "TARGET_ZARCH" |
288e517f AK |
4742 | "@ |
4743 | llgtr\t%0,%1 | |
4744 | llgt\t%0,%N1" | |
9381e3f1 WG |
4745 | [(set_attr "op_type" "RRE,RXE") |
4746 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4747 | |
f19a9af7 | 4748 | (define_split |
9602b6a1 AK |
4749 | [(set (match_operand:DSI 0 "register_operand" "") |
4750 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4751 | (const_int 2147483647))) |
ae156f85 | 4752 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4753 | "TARGET_ZARCH && reload_completed" |
288e517f | 4754 | [(set (match_dup 0) |
9602b6a1 | 4755 | (and:DSI (match_dup 1) |
f6ee577c | 4756 | (const_int 2147483647)))] |
288e517f AK |
4757 | "") |
4758 | ||
9db1d521 | 4759 | ; |
56477c21 | 4760 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4761 | ; |
4762 | ||
56477c21 AS |
4763 | (define_expand "zero_extend<mode>di2" |
4764 | [(set (match_operand:DI 0 "register_operand" "") | |
4765 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4766 | "" | |
4767 | { | |
9602b6a1 | 4768 | if (!TARGET_ZARCH) |
56477c21 AS |
4769 | { |
4770 | rtx tmp = gen_reg_rtx (SImode); | |
4771 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4772 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4773 | DONE; | |
4774 | } | |
4775 | else if (!TARGET_EXTIMM) | |
4776 | { | |
2542ef05 | 4777 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4778 | operands[1] = gen_lowpart (DImode, operands[1]); |
4779 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4780 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4781 | DONE; | |
4782 | } | |
4783 | }) | |
4784 | ||
f6ee577c | 4785 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4786 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4787 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4788 | "" |
4023fb28 | 4789 | { |
ec24698e UW |
4790 | if (!TARGET_EXTIMM) |
4791 | { | |
4792 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4793 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4794 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4795 | DONE; |
56477c21 | 4796 | } |
ec24698e UW |
4797 | }) |
4798 | ||
963fc8d0 AK |
4799 | ; llhrl, llghrl |
4800 | (define_insn "*zero_extendhi<mode>2_z10" | |
4801 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4802 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4803 | "TARGET_Z10" |
4804 | "@ | |
4805 | ll<g>hr\t%0,%1 | |
4806 | ll<g>h\t%0,%1 | |
4807 | ll<g>hrl\t%0,%1" | |
4808 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4809 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4810 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4811 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3") |
4812 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 | 4813 | |
43a09b63 | 4814 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4815 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4816 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4817 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4818 | "TARGET_EXTIMM" |
4819 | "@ | |
56477c21 AS |
4820 | ll<g><hc>r\t%0,%1 |
4821 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4822 | [(set_attr "op_type" "RRE,RXY") |
4823 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4824 | |
43a09b63 | 4825 | ; llgh, llgc |
56477c21 AS |
4826 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4827 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4828 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4829 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4830 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4831 | [(set_attr "op_type" "RXY") |
4832 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4833 | |
4834 | (define_insn_and_split "*zero_extendhisi2_31" | |
4835 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4836 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4837 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4838 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4839 | "#" |
4840 | "&& reload_completed" | |
4841 | [(set (match_dup 0) (const_int 0)) | |
4842 | (parallel | |
4843 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4844 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4845 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4846 | |
cc7ab9b7 UW |
4847 | (define_insn_and_split "*zero_extendqisi2_31" |
4848 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4849 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4850 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4851 | "#" |
4852 | "&& reload_completed" | |
4853 | [(set (match_dup 0) (const_int 0)) | |
4854 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4855 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4856 | |
9db1d521 HP |
4857 | ; |
4858 | ; zero_extendqihi2 instruction pattern(s). | |
4859 | ; | |
4860 | ||
9db1d521 HP |
4861 | (define_expand "zero_extendqihi2" |
4862 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4863 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4864 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4865 | { |
4023fb28 UW |
4866 | operands[1] = gen_lowpart (HImode, operands[1]); |
4867 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4868 | DONE; | |
ec24698e | 4869 | }) |
9db1d521 | 4870 | |
4023fb28 | 4871 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4872 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4873 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4874 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4875 | "llgc\t%0,%1" |
9381e3f1 WG |
4876 | [(set_attr "op_type" "RXY") |
4877 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4878 | |
cc7ab9b7 UW |
4879 | (define_insn_and_split "*zero_extendqihi2_31" |
4880 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4881 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4882 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4883 | "#" |
4884 | "&& reload_completed" | |
4885 | [(set (match_dup 0) (const_int 0)) | |
4886 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4887 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4888 | |
609e7e80 | 4889 | ; |
9751ad6e | 4890 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4891 | ; |
4892 | ||
9751ad6e AK |
4893 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4894 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4895 | ; or emits the default pattern otherwise. | |
4896 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4897 | [(parallel |
9751ad6e AK |
4898 | [(set (match_operand:GPR 0 "register_operand" "") |
4899 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4900 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4901 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4902 | "TARGET_HARD_FLOAT" |
609e7e80 | 4903 | { |
65b1d8ea AK |
4904 | if (!TARGET_Z196) |
4905 | { | |
9751ad6e AK |
4906 | /* We don't provide emulation for TD|DD->SI. */ |
4907 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4908 | && <GPR:MODE>mode == SImode) | |
4909 | FAIL; | |
4910 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4911 | operands[1])); | |
65b1d8ea AK |
4912 | DONE; |
4913 | } | |
9751ad6e AK |
4914 | |
4915 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4916 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4917 | else | |
4918 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4919 | }) |
4920 | ||
9751ad6e AK |
4921 | ; (sf|df|tf)->unsigned (si|di) |
4922 | ||
4923 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4924 | ; machines. | |
4925 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4926 | [(parallel | |
4927 | [(set (match_operand:GPR 0 "register_operand" "") | |
4928 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4929 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4930 | (clobber (reg:CC CC_REGNUM))])] | |
4931 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4932 | { | |
4933 | rtx_code_label *label1 = gen_label_rtx (); | |
4934 | rtx_code_label *label2 = gen_label_rtx (); | |
4935 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4936 | REAL_VALUE_TYPE cmp, sub; | |
4937 | ||
4938 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4939 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4940 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4941 | ||
4942 | emit_cmp_and_jump_insns (operands[1], | |
4943 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4944 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4945 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4946 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4947 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4948 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
4949 | emit_jump (label2); | |
4950 | ||
4951 | emit_label (label1); | |
4952 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4953 | operands[1], | |
4954 | GEN_INT (BFP_RND_TOWARD_0))); | |
4955 | emit_label (label2); | |
4956 | DONE; | |
4957 | }) | |
4958 | ||
4959 | ; dd->unsigned di | |
4960 | ||
4961 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4962 | ; machines. | |
4963 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
4964 | [(parallel |
4965 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 4966 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 4967 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4968 | (clobber (reg:CC CC_REGNUM))])] |
4969 | ||
9751ad6e | 4970 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 4971 | { |
9751ad6e AK |
4972 | rtx_code_label *label1 = gen_label_rtx (); |
4973 | rtx_code_label *label2 = gen_label_rtx (); | |
4974 | rtx temp = gen_reg_rtx (TDmode); | |
4975 | REAL_VALUE_TYPE cmp, sub; | |
4976 | ||
4977 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4978 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4979 | ||
4980 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4981 | solution is doing the check and the subtraction in TD mode and using a | |
4982 | TD -> DI convert afterwards. */ | |
4983 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4984 | temp = force_reg (TDmode, temp); | |
4985 | emit_cmp_and_jump_insns (temp, | |
4986 | const_double_from_real_value (cmp, TDmode), | |
4987 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4988 | emit_insn (gen_subtd3 (temp, temp, | |
4989 | const_double_from_real_value (sub, TDmode))); | |
4990 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4991 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4992 | emit_jump (label2); | |
4993 | ||
4994 | emit_label (label1); | |
4995 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
4996 | GEN_INT (DFP_RND_TOWARD_0))); | |
4997 | emit_label (label2); | |
4998 | DONE; | |
609e7e80 | 4999 | }) |
cc7ab9b7 | 5000 | |
9751ad6e | 5001 | ; td->unsigned di |
9db1d521 | 5002 | |
9751ad6e AK |
5003 | ; Emulate the unsigned conversion with the signed version for pre z196 |
5004 | ; machines. | |
5005 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 5006 | [(parallel |
9751ad6e AK |
5007 | [(set (match_operand:DI 0 "register_operand" "") |
5008 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
5009 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 5010 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5011 | |
5012 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 5013 | { |
9751ad6e AK |
5014 | rtx_code_label *label1 = gen_label_rtx (); |
5015 | rtx_code_label *label2 = gen_label_rtx (); | |
5016 | rtx temp = gen_reg_rtx (TDmode); | |
5017 | REAL_VALUE_TYPE cmp, sub; | |
5018 | ||
5019 | operands[1] = force_reg (TDmode, operands[1]); | |
5020 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
5021 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
5022 | ||
5023 | emit_cmp_and_jump_insns (operands[1], | |
5024 | const_double_from_real_value (cmp, TDmode), | |
5025 | LT, NULL_RTX, VOIDmode, 0, label1); | |
5026 | emit_insn (gen_subtd3 (temp, operands[1], | |
5027 | const_double_from_real_value (sub, TDmode))); | |
5028 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
5029 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
5030 | emit_jump (label2); | |
5031 | ||
5032 | emit_label (label1); | |
5033 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
5034 | GEN_INT (DFP_RND_TOWARD_0))); | |
5035 | emit_label (label2); | |
5036 | DONE; | |
10bbf137 | 5037 | }) |
9db1d521 | 5038 | |
9751ad6e AK |
5039 | ; Just a dummy to make the code in the first expander a bit easier. |
5040 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
5041 | [(parallel |
5042 | [(set (match_operand:SI 0 "register_operand" "") | |
5043 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 5044 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 5045 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5046 | |
5047 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
5048 | { | |
5049 | FAIL; | |
5050 | }) | |
5051 | ||
65b1d8ea AK |
5052 | |
5053 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
5054 | ||
9751ad6e AK |
5055 | ; df -> unsigned di |
5056 | (define_insn "*fixuns_truncdfdi2_vx" | |
6e5b5de8 AK |
5057 | [(set (match_operand:DI 0 "register_operand" "=d,v") |
5058 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5059 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5060 | (clobber (reg:CC CC_REGNUM))] | |
9751ad6e AK |
5061 | "TARGET_VX && TARGET_HARD_FLOAT" |
5062 | "@ | |
5063 | clgdbr\t%0,%h2,%1,0 | |
5064 | wclgdb\t%v0,%v1,0,%h2" | |
5065 | [(set_attr "op_type" "RRF,VRR") | |
5066 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 5067 | |
9751ad6e | 5068 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
5069 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
5070 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
5071 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
5072 | [(set (match_operand:GPR 0 "register_operand" "=d") |
5073 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
5074 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 5075 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 5076 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 5077 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
5078 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
5079 | [(set_attr "op_type" "RRF") | |
5080 | (set_attr "type" "ftoi")]) | |
5081 | ||
b60cb710 AK |
5082 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
5083 | [(set (match_operand:GPR 0 "register_operand" "") | |
5084 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
5085 | "TARGET_HARD_FLOAT" | |
9db1d521 | 5086 | { |
b60cb710 | 5087 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 5088 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 5089 | DONE; |
10bbf137 | 5090 | }) |
9db1d521 | 5091 | |
6e5b5de8 AK |
5092 | (define_insn "*fix_truncdfdi2_bfp_z13" |
5093 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
5094 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5095 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5096 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 5097 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5098 | "@ |
5099 | cgdbr\t%0,%h2,%1 | |
5100 | wcgdb\t%v0,%v1,0,%h2" | |
5101 | [(set_attr "op_type" "RRE,VRR") | |
5102 | (set_attr "type" "ftoi")]) | |
5103 | ||
43a09b63 | 5104 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
5105 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5106 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5107 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5108 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 5109 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
5110 | "TARGET_HARD_FLOAT |
5111 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 5112 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 5113 | [(set_attr "op_type" "RRE") |
077dab3b | 5114 | (set_attr "type" "ftoi")]) |
9db1d521 | 5115 | |
6e5b5de8 AK |
5116 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5117 | [(parallel | |
5118 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5119 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5120 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5121 | (clobber (reg:CC CC_REGNUM))])] | |
5122 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
5123 | ; |
5124 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
5125 | ; | |
5126 | ||
99cd7dd0 AK |
5127 | (define_expand "fix_trunc<mode>di2" |
5128 | [(set (match_operand:DI 0 "register_operand" "") | |
5129 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 5130 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
5131 | { |
5132 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
5133 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 5134 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
5135 | DONE; |
5136 | }) | |
5137 | ||
609e7e80 | 5138 | ; cgxtr, cgdtr |
99cd7dd0 | 5139 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
5140 | [(set (match_operand:DI 0 "register_operand" "=d") |
5141 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
5142 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5143 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5144 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5145 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5146 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5147 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5148 | |
5149 | ||
f61a2c7d AK |
5150 | ; |
5151 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5152 | ; | |
5153 | ||
5154 | (define_expand "fix_trunctf<mode>2" | |
5155 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5156 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5157 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5158 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5159 | "TARGET_HARD_FLOAT" |
142cd70f | 5160 | "") |
9db1d521 | 5161 | |
9db1d521 | 5162 | |
9db1d521 | 5163 | ; |
142cd70f | 5164 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5165 | ; |
5166 | ||
609e7e80 | 5167 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5168 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5169 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5170 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5171 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5172 | "@ |
5173 | c<xde>g<bt>r\t%0,%1 | |
5174 | wcdgb\t%v0,%v1,0,0" | |
5175 | [(set_attr "op_type" "RRE,VRR") | |
5176 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5177 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5178 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5179 | |
43a09b63 | 5180 | ; cxfbr, cdfbr, cefbr |
142cd70f | 5181 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
5182 | [(set (match_operand:BFP 0 "register_operand" "=f") |
5183 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 5184 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
5185 | "c<xde>fbr\t%0,%1" |
5186 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 5187 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 5188 | |
65b1d8ea AK |
5189 | ; cxftr, cdftr |
5190 | (define_insn "floatsi<mode>2" | |
5191 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5192 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5193 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5194 | "c<xde>ftr\t%0,0,%1,0" | |
5195 | [(set_attr "op_type" "RRE") | |
5196 | (set_attr "type" "itof<mode>" )]) | |
5197 | ||
5198 | ; | |
5199 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5200 | ; | |
5201 | ||
6e5b5de8 AK |
5202 | (define_insn "*floatunsdidf2_z13" |
5203 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
5204 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
a579871b | 5205 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5206 | "@ |
5207 | cdlgbr\t%0,0,%1,0 | |
5208 | wcdlgb\t%v0,%v1,0,0" | |
5209 | [(set_attr "op_type" "RRE,VRR") | |
5210 | (set_attr "type" "itofdf")]) | |
5211 | ||
65b1d8ea AK |
5212 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5213 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5214 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5215 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5216 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5217 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5218 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5219 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5220 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5221 | (set_attr "type" "itof<FP:mode>")]) |
5222 | ||
5223 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5224 | [(set (match_operand:FP 0 "register_operand" "") | |
5225 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5226 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5227 | |
9db1d521 HP |
5228 | ; |
5229 | ; truncdfsf2 instruction pattern(s). | |
5230 | ; | |
5231 | ||
142cd70f | 5232 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5233 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5234 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5235 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5236 | "@ |
5237 | ledbr\t%0,%1 | |
5238 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5239 | ; According to BFP rounding mode | |
5240 | [(set_attr "op_type" "RRE,VRR") | |
5241 | (set_attr "type" "ftruncdf") | |
285363a1 | 5242 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5243 | |
f61a2c7d | 5244 | ; |
142cd70f | 5245 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5246 | ; |
5247 | ||
142cd70f AK |
5248 | ; ldxbr, lexbr |
5249 | (define_insn "trunctf<mode>2" | |
5250 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5251 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5252 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5253 | "TARGET_HARD_FLOAT" |
5254 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5255 | [(set_attr "length" "6") |
9381e3f1 | 5256 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5257 | |
609e7e80 AK |
5258 | ; |
5259 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5260 | ; | |
5261 | ||
432d4670 AK |
5262 | |
5263 | (define_expand "trunctddd2" | |
5264 | [(parallel | |
5265 | [(set (match_operand:DD 0 "register_operand" "") | |
5266 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5267 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5268 | (clobber (scratch:TD))])] | |
5269 | "TARGET_HARD_DFP") | |
5270 | ||
5271 | (define_insn "*trunctddd2" | |
609e7e80 | 5272 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5273 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5274 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5275 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5276 | "TARGET_HARD_DFP" |
432d4670 | 5277 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5278 | [(set_attr "length" "6") |
9381e3f1 | 5279 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5280 | |
5281 | (define_insn "truncddsd2" | |
5282 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5283 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5284 | "TARGET_HARD_DFP" |
609e7e80 AK |
5285 | "ledtr\t%0,0,%1,0" |
5286 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5287 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5288 | |
feade5a8 AK |
5289 | (define_expand "trunctdsd2" |
5290 | [(parallel | |
d5a216fa | 5291 | [(set (match_dup 2) |
feade5a8 | 5292 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5293 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5294 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5295 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5296 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5297 | "TARGET_HARD_DFP" |
5298 | { | |
d5a216fa | 5299 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5300 | }) |
5301 | ||
9db1d521 | 5302 | ; |
142cd70f | 5303 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5304 | ; |
5305 | ||
2de2b3f9 | 5306 | ; wflls |
6e5b5de8 AK |
5307 | (define_insn "*extendsfdf2_z13" |
5308 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5309 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5310 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5311 | "@ |
5312 | ldebr\t%0,%1 | |
5313 | ldeb\t%0,%1 | |
5314 | wldeb\t%v0,%v1" | |
5315 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5316 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5317 | ||
142cd70f | 5318 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5319 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5320 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5321 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5322 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5323 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5324 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5325 | "@ |
142cd70f AK |
5326 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5327 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5328 | [(set_attr "op_type" "RRE,RXE") |
5329 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5330 | ||
5331 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5332 | [(set (match_operand:BFP 0 "register_operand" "") | |
5333 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5334 | "TARGET_HARD_FLOAT | |
5335 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5336 | |
609e7e80 AK |
5337 | ; |
5338 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5339 | ; | |
5340 | ||
5341 | (define_insn "extendddtd2" | |
5342 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5343 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5344 | "TARGET_HARD_DFP" |
609e7e80 AK |
5345 | "lxdtr\t%0,%1,0" |
5346 | [(set_attr "op_type" "RRF") | |
5347 | (set_attr "type" "fsimptf")]) | |
5348 | ||
5349 | (define_insn "extendsddd2" | |
5350 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5351 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5352 | "TARGET_HARD_DFP" |
609e7e80 AK |
5353 | "ldetr\t%0,%1,0" |
5354 | [(set_attr "op_type" "RRF") | |
5355 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5356 | |
feade5a8 AK |
5357 | (define_expand "extendsdtd2" |
5358 | [(set (match_dup 2) | |
5359 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5360 | (set (match_operand:TD 0 "register_operand" "") | |
5361 | (float_extend:TD (match_dup 2)))] | |
5362 | "TARGET_HARD_DFP" | |
5363 | { | |
5364 | operands[2] = gen_reg_rtx (DDmode); | |
5365 | }) | |
5366 | ||
d12a76f3 AK |
5367 | ; Binary Floating Point - load fp integer |
5368 | ||
5369 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5370 | ; For all of them the inexact exceptions are suppressed. | |
5371 | ||
5372 | ; fiebra, fidbra, fixbra | |
5373 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5374 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5375 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5376 | FPINT))] | |
5377 | "TARGET_Z196" | |
5378 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5379 | [(set_attr "op_type" "RRF") | |
5380 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5381 | ||
5382 | ; rint is supposed to raise an inexact exception so we can use the | |
5383 | ; older instructions. | |
5384 | ||
5385 | ; fiebr, fidbr, fixbr | |
5386 | (define_insn "rint<BFP:mode>2" | |
5387 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5388 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5389 | UNSPEC_FPINT_RINT))] | |
5390 | "" | |
5391 | "fi<BFP:xde>br\t%0,0,%1" | |
5392 | [(set_attr "op_type" "RRF") | |
5393 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5394 | ||
5395 | ||
5396 | ; Decimal Floating Point - load fp integer | |
5397 | ||
5398 | ; fidtr, fixtr | |
5399 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5400 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5401 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5402 | FPINT))] | |
5403 | "TARGET_HARD_DFP" | |
5404 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5405 | [(set_attr "op_type" "RRF") | |
5406 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5407 | ||
5408 | ; fidtr, fixtr | |
5409 | (define_insn "rint<DFP:mode>2" | |
5410 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5411 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5412 | UNSPEC_FPINT_RINT))] | |
5413 | "TARGET_HARD_DFP" | |
5414 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5415 | [(set_attr "op_type" "RRF") | |
5416 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5417 | ||
5418 | ; | |
35dd9a0e AK |
5419 | ; Binary <-> Decimal floating point trunc patterns |
5420 | ; | |
5421 | ||
5422 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5423 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5424 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5425 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5426 | (clobber (reg:CC CC_REGNUM)) |
5427 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5428 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5429 | "pfpo") |
5430 | ||
5431 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5432 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5433 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5434 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5435 | (clobber (reg:CC CC_REGNUM)) |
5436 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5437 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5438 | "pfpo") |
5439 | ||
5440 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5441 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5442 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5443 | (parallel | |
5444 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5445 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5446 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5447 | (clobber (reg:CC CC_REGNUM)) |
5448 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5449 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5450 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5451 | "TARGET_HARD_DFP |
35dd9a0e AK |
5452 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5453 | { | |
5454 | HOST_WIDE_INT flags; | |
5455 | ||
ced8d882 AK |
5456 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5457 | rounding mode of the target format needs to be used. */ | |
5458 | ||
35dd9a0e AK |
5459 | flags = (PFPO_CONVERT | |
5460 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5461 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5462 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5463 | |
5464 | operands[2] = GEN_INT (flags); | |
5465 | }) | |
5466 | ||
5467 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5468 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5469 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5470 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5471 | (parallel | |
2cf4c39e | 5472 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5473 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5474 | (clobber (reg:CC CC_REGNUM)) |
5475 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5476 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5477 | "TARGET_HARD_DFP |
35dd9a0e AK |
5478 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5479 | { | |
5480 | HOST_WIDE_INT flags; | |
5481 | ||
ced8d882 AK |
5482 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5483 | rounding mode of the target format needs to be used. */ | |
5484 | ||
35dd9a0e AK |
5485 | flags = (PFPO_CONVERT | |
5486 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5487 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5488 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5489 | |
5490 | operands[2] = GEN_INT (flags); | |
5491 | }) | |
5492 | ||
5493 | ; | |
5494 | ; Binary <-> Decimal floating point extend patterns | |
5495 | ; | |
5496 | ||
5497 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5498 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5499 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5500 | (clobber (reg:CC CC_REGNUM)) |
5501 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5502 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5503 | "pfpo") |
5504 | ||
5505 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5506 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5507 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5508 | (clobber (reg:CC CC_REGNUM)) |
5509 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5510 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5511 | "pfpo") |
5512 | ||
5513 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5514 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5515 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5516 | (parallel | |
5517 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5518 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5519 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5520 | (clobber (reg:CC CC_REGNUM)) |
5521 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5522 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5523 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5524 | "TARGET_HARD_DFP |
35dd9a0e AK |
5525 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5526 | { | |
5527 | HOST_WIDE_INT flags; | |
5528 | ||
ced8d882 AK |
5529 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5530 | rounding mode of the target format needs to be used. */ | |
5531 | ||
35dd9a0e AK |
5532 | flags = (PFPO_CONVERT | |
5533 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5534 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5535 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5536 | |
5537 | operands[2] = GEN_INT (flags); | |
5538 | }) | |
5539 | ||
5540 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5541 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5542 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5543 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5544 | (parallel | |
2cf4c39e | 5545 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5546 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5547 | (clobber (reg:CC CC_REGNUM)) |
5548 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5549 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5550 | "TARGET_HARD_DFP |
35dd9a0e AK |
5551 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5552 | { | |
5553 | HOST_WIDE_INT flags; | |
5554 | ||
ced8d882 AK |
5555 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5556 | rounding mode of the target format needs to be used. */ | |
5557 | ||
35dd9a0e AK |
5558 | flags = (PFPO_CONVERT | |
5559 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5560 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5561 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5562 | |
5563 | operands[2] = GEN_INT (flags); | |
5564 | }) | |
5565 | ||
5566 | ||
9db1d521 | 5567 | ;; |
fae778eb | 5568 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5569 | ;; |
fae778eb | 5570 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5571 | ; because of unpredictable Bits in Register for Halfword and Byte |
5572 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5573 | ||
07893d4f UW |
5574 | ;; |
5575 | ;;- Add instructions. | |
5576 | ;; | |
5577 | ||
1c7b1b7e UW |
5578 | ; |
5579 | ; addti3 instruction pattern(s). | |
5580 | ; | |
5581 | ||
085261c8 AK |
5582 | (define_expand "addti3" |
5583 | [(parallel | |
5584 | [(set (match_operand:TI 0 "register_operand" "") | |
5585 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5586 | (match_operand:TI 2 "general_operand" "") ) ) | |
5587 | (clobber (reg:CC CC_REGNUM))])] | |
5588 | "TARGET_ZARCH" | |
5589 | { | |
5590 | /* For z13 we have vaq which doesn't set CC. */ | |
5591 | if (TARGET_VX) | |
5592 | { | |
5593 | emit_insn (gen_rtx_SET (operands[0], | |
5594 | gen_rtx_PLUS (TImode, | |
5595 | copy_to_mode_reg (TImode, operands[1]), | |
5596 | copy_to_mode_reg (TImode, operands[2])))); | |
5597 | DONE; | |
5598 | } | |
5599 | }) | |
5600 | ||
5601 | (define_insn_and_split "*addti3" | |
5602 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5603 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5604 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5605 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5606 | "TARGET_ZARCH" |
1c7b1b7e UW |
5607 | "#" |
5608 | "&& reload_completed" | |
5609 | [(parallel | |
ae156f85 | 5610 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5611 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5612 | (match_dup 7))) | |
5613 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5614 | (parallel | |
a94a76a7 UW |
5615 | [(set (match_dup 3) (plus:DI |
5616 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5617 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5618 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5619 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5620 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5621 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5622 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5623 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5624 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5625 | [(set_attr "op_type" "*") | |
5626 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5627 | |
07893d4f UW |
5628 | ; |
5629 | ; adddi3 instruction pattern(s). | |
5630 | ; | |
5631 | ||
3298c037 AK |
5632 | (define_expand "adddi3" |
5633 | [(parallel | |
963fc8d0 | 5634 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5635 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5636 | (match_operand:DI 2 "general_operand" ""))) | |
5637 | (clobber (reg:CC CC_REGNUM))])] | |
5638 | "" | |
5639 | "") | |
5640 | ||
07893d4f UW |
5641 | (define_insn "*adddi3_sign" |
5642 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5643 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5644 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5645 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5646 | "TARGET_ZARCH" |
07893d4f | 5647 | "@ |
d40c829f UW |
5648 | agfr\t%0,%2 |
5649 | agf\t%0,%2" | |
65b1d8ea AK |
5650 | [(set_attr "op_type" "RRE,RXY") |
5651 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5652 | |
5653 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5654 | [(set (reg CC_REGNUM) |
3e4be43f | 5655 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5656 | (match_operand:DI 1 "register_operand" "0,0")) |
5657 | (const_int 0))) | |
5658 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5659 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5660 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5661 | "@ |
d40c829f UW |
5662 | algfr\t%0,%2 |
5663 | algf\t%0,%2" | |
9381e3f1 WG |
5664 | [(set_attr "op_type" "RRE,RXY") |
5665 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5666 | |
5667 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5668 | [(set (reg CC_REGNUM) |
3e4be43f | 5669 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5670 | (match_operand:DI 1 "register_operand" "0,0")) |
5671 | (const_int 0))) | |
5672 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5673 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5674 | "@ |
d40c829f UW |
5675 | algfr\t%0,%2 |
5676 | algf\t%0,%2" | |
9381e3f1 WG |
5677 | [(set_attr "op_type" "RRE,RXY") |
5678 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5679 | |
5680 | (define_insn "*adddi3_zero" | |
5681 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5682 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5683 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5684 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5685 | "TARGET_ZARCH" |
07893d4f | 5686 | "@ |
d40c829f UW |
5687 | algfr\t%0,%2 |
5688 | algf\t%0,%2" | |
9381e3f1 WG |
5689 | [(set_attr "op_type" "RRE,RXY") |
5690 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5691 | |
e69166de | 5692 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5693 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5694 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5695 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5696 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 5697 | "!TARGET_ZARCH" |
e69166de UW |
5698 | "#" |
5699 | "&& reload_completed" | |
5700 | [(parallel | |
ae156f85 | 5701 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5702 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5703 | (match_dup 7))) | |
5704 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5705 | (parallel | |
a94a76a7 UW |
5706 | [(set (match_dup 3) (plus:SI |
5707 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5708 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5709 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5710 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5711 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5712 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5713 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5714 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5715 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5716 | |
3298c037 AK |
5717 | ; |
5718 | ; addsi3 instruction pattern(s). | |
5719 | ; | |
5720 | ||
5721 | (define_expand "addsi3" | |
07893d4f | 5722 | [(parallel |
963fc8d0 | 5723 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5724 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5725 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5726 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5727 | "" |
07893d4f | 5728 | "") |
9db1d521 | 5729 | |
3298c037 AK |
5730 | (define_insn "*addsi3_sign" |
5731 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5732 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5733 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5734 | (clobber (reg:CC CC_REGNUM))] | |
5735 | "" | |
5736 | "@ | |
5737 | ah\t%0,%2 | |
5738 | ahy\t%0,%2" | |
65b1d8ea | 5739 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5740 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5741 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5742 | |
9db1d521 | 5743 | ; |
3298c037 | 5744 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5745 | ; |
9db1d521 | 5746 | |
65b1d8ea | 5747 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5748 | (define_insn "*add<mode>3" |
3e4be43f UW |
5749 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5750 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5751 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5752 | (clobber (reg:CC CC_REGNUM))] |
5753 | "" | |
ec24698e | 5754 | "@ |
3298c037 | 5755 | a<g>r\t%0,%2 |
65b1d8ea | 5756 | a<g>rk\t%0,%1,%2 |
3298c037 | 5757 | a<g>hi\t%0,%h2 |
65b1d8ea | 5758 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5759 | al<g>fi\t%0,%2 |
5760 | sl<g>fi\t%0,%n2 | |
5761 | a<g>\t%0,%2 | |
963fc8d0 AK |
5762 | a<y>\t%0,%2 |
5763 | a<g>si\t%0,%c2" | |
65b1d8ea | 5764 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5765 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5766 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5767 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5768 | |
65b1d8ea | 5769 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5770 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5771 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5772 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5773 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5774 | (match_dup 1))) |
65b1d8ea | 5775 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5776 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5777 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5778 | "@ |
3298c037 | 5779 | al<g>r\t%0,%2 |
65b1d8ea | 5780 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5781 | al<g>fi\t%0,%2 |
5782 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5783 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5784 | al<g>\t%0,%2 |
963fc8d0 AK |
5785 | al<y>\t%0,%2 |
5786 | al<g>si\t%0,%c2" | |
65b1d8ea | 5787 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5788 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5789 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5790 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5791 | |
65b1d8ea | 5792 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5793 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5794 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5795 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5796 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5797 | (match_dup 1))) |
65b1d8ea | 5798 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5799 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5800 | "@ |
3298c037 | 5801 | al<g>r\t%0,%2 |
65b1d8ea | 5802 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5803 | al<g>\t%0,%2 |
5804 | al<y>\t%0,%2" | |
65b1d8ea | 5805 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5806 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5807 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5808 | |
65b1d8ea | 5809 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5810 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5811 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5812 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5813 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5814 | (match_dup 2))) |
3e4be43f | 5815 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5816 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5817 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5818 | "@ |
3298c037 | 5819 | al<g>r\t%0,%2 |
65b1d8ea | 5820 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5821 | al<g>fi\t%0,%2 |
5822 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5823 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5824 | al<g>\t%0,%2 |
963fc8d0 AK |
5825 | al<y>\t%0,%2 |
5826 | al<g>si\t%0,%c2" | |
65b1d8ea | 5827 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5828 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5829 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5830 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5831 | |
65b1d8ea | 5832 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5833 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5834 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5835 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5836 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5837 | (match_dup 2))) |
65b1d8ea | 5838 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5839 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5840 | "@ |
3298c037 | 5841 | al<g>r\t%0,%2 |
65b1d8ea | 5842 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5843 | al<g>\t%0,%2 |
5844 | al<y>\t%0,%2" | |
65b1d8ea | 5845 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5846 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5847 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5848 | |
65b1d8ea | 5849 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5850 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5851 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5852 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5853 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5854 | (const_int 0))) |
3e4be43f | 5855 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5856 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5857 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5858 | "@ |
3298c037 | 5859 | al<g>r\t%0,%2 |
65b1d8ea | 5860 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5861 | al<g>fi\t%0,%2 |
5862 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5863 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5864 | al<g>\t%0,%2 |
963fc8d0 AK |
5865 | al<y>\t%0,%2 |
5866 | al<g>si\t%0,%c2" | |
65b1d8ea | 5867 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5868 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5869 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5870 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5871 | |
65b1d8ea | 5872 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5873 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5874 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5875 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5876 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5877 | (const_int 0))) |
65b1d8ea | 5878 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5879 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5880 | "@ |
3298c037 | 5881 | al<g>r\t%0,%2 |
65b1d8ea | 5882 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5883 | al<g>\t%0,%2 |
5884 | al<y>\t%0,%2" | |
65b1d8ea | 5885 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5886 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5887 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5888 | |
65b1d8ea | 5889 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5890 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5891 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5892 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5893 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5894 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5895 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5896 | "@ |
3298c037 | 5897 | al<g>r\t%0,%2 |
65b1d8ea | 5898 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5899 | al<g>\t%0,%2 |
5900 | al<y>\t%0,%2" | |
65b1d8ea | 5901 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5902 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5903 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5904 | |
963fc8d0 | 5905 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5906 | (define_insn "*add<mode>3_imm_cc" |
5907 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5908 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5909 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5910 | (const_int 0))) |
3e4be43f | 5911 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5912 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5913 | "s390_match_ccmode (insn, CCAmode) | |
5914 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5915 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5916 | /* Avoid INT32_MIN on 32 bit. */ | |
5917 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5918 | "@ |
3298c037 | 5919 | a<g>hi\t%0,%h2 |
65b1d8ea | 5920 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5921 | a<g>fi\t%0,%2 |
5922 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5923 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5924 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5925 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5926 | |
7d2fd075 AK |
5927 | (define_insn "*adddi3_sign" |
5928 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5929 | (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
5930 | (match_operand:DI 1 "register_operand" "0"))) | |
5931 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 5932 | "TARGET_Z14" |
7d2fd075 AK |
5933 | "agh\t%0,%2" |
5934 | [(set_attr "op_type" "RXY")]) | |
5935 | ||
9db1d521 | 5936 | ; |
609e7e80 | 5937 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5938 | ; |
5939 | ||
609e7e80 | 5940 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5941 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5942 | (define_insn "add<mode>3" |
2de2b3f9 AK |
5943 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
5944 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
5945 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 5946 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5947 | "TARGET_HARD_FLOAT" |
9db1d521 | 5948 | "@ |
62d3f261 AK |
5949 | a<xde>tr\t%0,%1,%2 |
5950 | a<xde>br\t%0,%2 | |
6e5b5de8 | 5951 | a<xde>b\t%0,%2 |
2de2b3f9 AK |
5952 | wfadb\t%v0,%v1,%v2 |
5953 | wfasb\t%v0,%v1,%v2" | |
5954 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 5955 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
5956 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
5957 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 5958 | |
609e7e80 | 5959 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5960 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5961 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5962 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5963 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5964 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5965 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5966 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5967 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5968 | "@ |
62d3f261 AK |
5969 | a<xde>tr\t%0,%1,%2 |
5970 | a<xde>br\t%0,%2 | |
f61a2c7d | 5971 | a<xde>b\t%0,%2" |
62d3f261 AK |
5972 | [(set_attr "op_type" "RRF,RRE,RXE") |
5973 | (set_attr "type" "fsimp<mode>") | |
5974 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5975 | |
609e7e80 | 5976 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5977 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5978 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5979 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5980 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5981 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5982 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5983 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5984 | "@ |
62d3f261 AK |
5985 | a<xde>tr\t%0,%1,%2 |
5986 | a<xde>br\t%0,%2 | |
f61a2c7d | 5987 | a<xde>b\t%0,%2" |
62d3f261 AK |
5988 | [(set_attr "op_type" "RRF,RRE,RXE") |
5989 | (set_attr "type" "fsimp<mode>") | |
5990 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5991 | |
72a4ddf2 AK |
5992 | ; |
5993 | ; Pointer add instruction patterns | |
5994 | ; | |
5995 | ||
5996 | ; This will match "*la_64" | |
5997 | (define_expand "addptrdi3" | |
5998 | [(set (match_operand:DI 0 "register_operand" "") | |
5999 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
6000 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
6001 | "TARGET_64BIT" | |
6002 | { | |
72a4ddf2 AK |
6003 | if (GET_CODE (operands[2]) == CONST_INT) |
6004 | { | |
357ddc7d TV |
6005 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6006 | ||
72a4ddf2 AK |
6007 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6008 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6009 | { | |
6010 | operands[2] = force_const_mem (DImode, operands[2]); | |
6011 | operands[2] = force_reg (DImode, operands[2]); | |
6012 | } | |
6013 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6014 | operands[2] = force_reg (DImode, operands[2]); | |
6015 | } | |
6016 | }) | |
6017 | ||
6018 | ; For 31 bit we have to prevent the generated pattern from matching | |
6019 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
6020 | ; match "force_la_31". | |
6021 | (define_expand "addptrsi3" | |
6022 | [(parallel | |
6023 | [(set (match_operand:SI 0 "register_operand" "") | |
6024 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
6025 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
6026 | (use (const_int 0))])] | |
6027 | "!TARGET_64BIT" | |
6028 | { | |
72a4ddf2 AK |
6029 | if (GET_CODE (operands[2]) == CONST_INT) |
6030 | { | |
357ddc7d TV |
6031 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6032 | ||
72a4ddf2 AK |
6033 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6034 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6035 | { | |
6036 | operands[2] = force_const_mem (SImode, operands[2]); | |
6037 | operands[2] = force_reg (SImode, operands[2]); | |
6038 | } | |
6039 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6040 | operands[2] = force_reg (SImode, operands[2]); | |
6041 | } | |
6042 | }) | |
9db1d521 HP |
6043 | |
6044 | ;; | |
6045 | ;;- Subtract instructions. | |
6046 | ;; | |
6047 | ||
1c7b1b7e UW |
6048 | ; |
6049 | ; subti3 instruction pattern(s). | |
6050 | ; | |
6051 | ||
085261c8 AK |
6052 | (define_expand "subti3" |
6053 | [(parallel | |
6054 | [(set (match_operand:TI 0 "register_operand" "") | |
6055 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
6056 | (match_operand:TI 2 "general_operand" "") ) ) | |
6057 | (clobber (reg:CC CC_REGNUM))])] | |
6058 | "TARGET_ZARCH" | |
6059 | { | |
2d71f118 | 6060 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
6061 | if (TARGET_VX) |
6062 | { | |
6063 | emit_insn (gen_rtx_SET (operands[0], | |
6064 | gen_rtx_MINUS (TImode, | |
6065 | operands[1], | |
6066 | copy_to_mode_reg (TImode, operands[2])))); | |
6067 | DONE; | |
6068 | } | |
6069 | }) | |
6070 | ||
6071 | (define_insn_and_split "*subti3" | |
6072 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
6073 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
6074 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 6075 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6076 | "TARGET_ZARCH" |
1c7b1b7e UW |
6077 | "#" |
6078 | "&& reload_completed" | |
6079 | [(parallel | |
ae156f85 | 6080 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
6081 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
6082 | (match_dup 7))) | |
6083 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
6084 | (parallel | |
6085 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6086 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6087 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
6088 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
6089 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
6090 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
6091 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
6092 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
6093 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
6094 | [(set_attr "op_type" "*") | |
6095 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 6096 | |
9db1d521 HP |
6097 | ; |
6098 | ; subdi3 instruction pattern(s). | |
6099 | ; | |
6100 | ||
3298c037 AK |
6101 | (define_expand "subdi3" |
6102 | [(parallel | |
6103 | [(set (match_operand:DI 0 "register_operand" "") | |
6104 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
6105 | (match_operand:DI 2 "general_operand" ""))) | |
6106 | (clobber (reg:CC CC_REGNUM))])] | |
6107 | "" | |
6108 | "") | |
6109 | ||
07893d4f UW |
6110 | (define_insn "*subdi3_sign" |
6111 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6112 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6113 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6114 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6115 | "TARGET_ZARCH" |
07893d4f | 6116 | "@ |
d40c829f UW |
6117 | sgfr\t%0,%2 |
6118 | sgf\t%0,%2" | |
9381e3f1 | 6119 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
6120 | (set_attr "z10prop" "z10_c,*") |
6121 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
6122 | |
6123 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 6124 | [(set (reg CC_REGNUM) |
07893d4f | 6125 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6126 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6127 | (const_int 0))) |
6128 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6129 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 6130 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6131 | "@ |
d40c829f UW |
6132 | slgfr\t%0,%2 |
6133 | slgf\t%0,%2" | |
9381e3f1 WG |
6134 | [(set_attr "op_type" "RRE,RXY") |
6135 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6136 | |
6137 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 6138 | [(set (reg CC_REGNUM) |
07893d4f | 6139 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6140 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6141 | (const_int 0))) |
6142 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6143 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6144 | "@ |
d40c829f UW |
6145 | slgfr\t%0,%2 |
6146 | slgf\t%0,%2" | |
9381e3f1 WG |
6147 | [(set_attr "op_type" "RRE,RXY") |
6148 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6149 | |
6150 | (define_insn "*subdi3_zero" | |
6151 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6152 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6153 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6154 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6155 | "TARGET_ZARCH" |
07893d4f | 6156 | "@ |
d40c829f UW |
6157 | slgfr\t%0,%2 |
6158 | slgf\t%0,%2" | |
9381e3f1 WG |
6159 | [(set_attr "op_type" "RRE,RXY") |
6160 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6161 | |
e69166de UW |
6162 | (define_insn_and_split "*subdi3_31z" |
6163 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6164 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6165 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6166 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6167 | "!TARGET_ZARCH" |
e69166de UW |
6168 | "#" |
6169 | "&& reload_completed" | |
6170 | [(parallel | |
ae156f85 | 6171 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6172 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6173 | (match_dup 7))) | |
6174 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6175 | (parallel | |
6176 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6177 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6178 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6179 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6180 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6181 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6182 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6183 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6184 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6185 | |
3298c037 AK |
6186 | ; |
6187 | ; subsi3 instruction pattern(s). | |
6188 | ; | |
6189 | ||
6190 | (define_expand "subsi3" | |
07893d4f | 6191 | [(parallel |
3298c037 AK |
6192 | [(set (match_operand:SI 0 "register_operand" "") |
6193 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6194 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6195 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6196 | "" |
07893d4f | 6197 | "") |
9db1d521 | 6198 | |
3298c037 AK |
6199 | (define_insn "*subsi3_sign" |
6200 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6201 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6202 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6203 | (clobber (reg:CC CC_REGNUM))] | |
6204 | "" | |
6205 | "@ | |
6206 | sh\t%0,%2 | |
6207 | shy\t%0,%2" | |
65b1d8ea | 6208 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6209 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6210 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6211 | |
9db1d521 | 6212 | ; |
3298c037 | 6213 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6214 | ; |
6215 | ||
65b1d8ea | 6216 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6217 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6218 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6219 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6220 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6221 | (clobber (reg:CC CC_REGNUM))] |
6222 | "" | |
6223 | "@ | |
6224 | s<g>r\t%0,%2 | |
65b1d8ea | 6225 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6226 | s<g>\t%0,%2 |
6227 | s<y>\t%0,%2" | |
65b1d8ea | 6228 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6229 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6230 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6231 | |
65b1d8ea | 6232 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6233 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6234 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6235 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6236 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6237 | (match_dup 1))) |
65b1d8ea | 6238 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6239 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6240 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6241 | "@ |
3298c037 | 6242 | sl<g>r\t%0,%2 |
65b1d8ea | 6243 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6244 | sl<g>\t%0,%2 |
6245 | sl<y>\t%0,%2" | |
65b1d8ea | 6246 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6247 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6248 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6249 | |
65b1d8ea | 6250 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6251 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6252 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6253 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6254 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6255 | (match_dup 1))) |
65b1d8ea | 6256 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6257 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6258 | "@ |
3298c037 | 6259 | sl<g>r\t%0,%2 |
65b1d8ea | 6260 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6261 | sl<g>\t%0,%2 |
6262 | sl<y>\t%0,%2" | |
65b1d8ea | 6263 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6264 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6265 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6266 | |
65b1d8ea | 6267 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6268 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6269 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6270 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6271 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6272 | (const_int 0))) |
65b1d8ea | 6273 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6274 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6275 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6276 | "@ |
3298c037 | 6277 | sl<g>r\t%0,%2 |
65b1d8ea | 6278 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6279 | sl<g>\t%0,%2 |
6280 | sl<y>\t%0,%2" | |
65b1d8ea | 6281 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6282 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6283 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6284 | |
65b1d8ea | 6285 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6286 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6287 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6288 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6289 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6290 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6291 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6292 | "s390_match_ccmode (insn, CCL3mode)" |
6293 | "@ | |
3298c037 | 6294 | sl<g>r\t%0,%2 |
65b1d8ea | 6295 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6296 | sl<g>\t%0,%2 |
6297 | sl<y>\t%0,%2" | |
65b1d8ea | 6298 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6299 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6300 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6301 | |
65b1d8ea | 6302 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6303 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6304 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6305 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6306 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6307 | (const_int 0))) |
65b1d8ea | 6308 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6309 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6310 | "@ |
3298c037 | 6311 | sl<g>r\t%0,%2 |
65b1d8ea | 6312 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6313 | sl<g>\t%0,%2 |
6314 | sl<y>\t%0,%2" | |
65b1d8ea | 6315 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6316 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6317 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6318 | |
9db1d521 | 6319 | |
65b1d8ea | 6320 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6321 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6322 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6323 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6324 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6325 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6326 | "s390_match_ccmode (insn, CCL3mode)" |
6327 | "@ | |
3298c037 | 6328 | sl<g>r\t%0,%2 |
65b1d8ea | 6329 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6330 | sl<g>\t%0,%2 |
6331 | sl<y>\t%0,%2" | |
65b1d8ea | 6332 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6333 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6334 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6335 | |
7d2fd075 AK |
6336 | (define_insn "*subdi3_sign" |
6337 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6338 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6339 | (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) | |
6340 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 6341 | "TARGET_Z14" |
7d2fd075 AK |
6342 | "sgh\t%0,%2" |
6343 | [(set_attr "op_type" "RXY")]) | |
6344 | ||
9db1d521 HP |
6345 | |
6346 | ; | |
609e7e80 | 6347 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6348 | ; |
6349 | ||
2de2b3f9 | 6350 | ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? |
d46f24b6 | 6351 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6352 | (define_insn "sub<mode>3" |
2de2b3f9 AK |
6353 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6354 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
6355 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6356 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6357 | "TARGET_HARD_FLOAT" |
9db1d521 | 6358 | "@ |
62d3f261 AK |
6359 | s<xde>tr\t%0,%1,%2 |
6360 | s<xde>br\t%0,%2 | |
6e5b5de8 | 6361 | s<xde>b\t%0,%2 |
2de2b3f9 AK |
6362 | wfsdb\t%v0,%v1,%v2 |
6363 | wfssb\t%v0,%v1,%v2" | |
6364 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6365 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6366 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6367 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6368 | |
d46f24b6 | 6369 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6370 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6371 | [(set (reg CC_REGNUM) |
62d3f261 | 6372 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
2de2b3f9 | 6373 | (match_operand:FP 2 "general_operand" "f,f,R")) |
609e7e80 | 6374 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6375 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6376 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6377 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6378 | "@ |
62d3f261 AK |
6379 | s<xde>tr\t%0,%1,%2 |
6380 | s<xde>br\t%0,%2 | |
f61a2c7d | 6381 | s<xde>b\t%0,%2" |
62d3f261 AK |
6382 | [(set_attr "op_type" "RRF,RRE,RXE") |
6383 | (set_attr "type" "fsimp<mode>") | |
6384 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6385 | |
d46f24b6 | 6386 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6387 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6388 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6389 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6390 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6391 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6392 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6393 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6394 | "@ |
62d3f261 AK |
6395 | s<xde>tr\t%0,%1,%2 |
6396 | s<xde>br\t%0,%2 | |
f61a2c7d | 6397 | s<xde>b\t%0,%2" |
62d3f261 AK |
6398 | [(set_attr "op_type" "RRF,RRE,RXE") |
6399 | (set_attr "type" "fsimp<mode>") | |
6400 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6401 | |
9db1d521 | 6402 | |
e69166de UW |
6403 | ;; |
6404 | ;;- Conditional add/subtract instructions. | |
6405 | ;; | |
6406 | ||
6407 | ; | |
9a91a21f | 6408 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6409 | ; |
6410 | ||
a996720c UW |
6411 | ; the following 4 patterns are used when the result of an add with |
6412 | ; carry is checked for an overflow condition | |
6413 | ||
6414 | ; op1 + op2 + c < op1 | |
6415 | ||
6416 | ; alcr, alc, alcgr, alcg | |
6417 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6418 | [(set (reg CC_REGNUM) | |
6419 | (compare | |
6420 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6421 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6422 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6423 | (match_dup 1))) |
6424 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6425 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6426 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6427 | "@ |
6428 | alc<g>r\t%0,%2 | |
6429 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6430 | [(set_attr "op_type" "RRE,RXY") |
6431 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6432 | |
6433 | ; alcr, alc, alcgr, alcg | |
6434 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6435 | [(set (reg CC_REGNUM) | |
6436 | (compare | |
6437 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6438 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6439 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6440 | (match_dup 1))) |
6441 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6442 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6443 | "@ |
6444 | alc<g>r\t%0,%2 | |
6445 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6446 | [(set_attr "op_type" "RRE,RXY") |
6447 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6448 | |
6449 | ; op1 + op2 + c < op2 | |
6450 | ||
6451 | ; alcr, alc, alcgr, alcg | |
6452 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6453 | [(set (reg CC_REGNUM) | |
6454 | (compare | |
6455 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6456 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6457 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6458 | (match_dup 2))) |
6459 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6460 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6461 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6462 | "@ |
6463 | alc<g>r\t%0,%2 | |
6464 | alc<g>\t%0,%2" | |
6465 | [(set_attr "op_type" "RRE,RXY")]) | |
6466 | ||
6467 | ; alcr, alc, alcgr, alcg | |
6468 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6469 | [(set (reg CC_REGNUM) | |
6470 | (compare | |
6471 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6472 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6473 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6474 | (match_dup 2))) |
6475 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6476 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6477 | "@ |
6478 | alc<g>r\t%0,%2 | |
6479 | alc<g>\t%0,%2" | |
6480 | [(set_attr "op_type" "RRE,RXY")]) | |
6481 | ||
43a09b63 | 6482 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6483 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6484 | [(set (reg CC_REGNUM) |
e69166de | 6485 | (compare |
a94a76a7 UW |
6486 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6487 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6488 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6489 | (const_int 0))) |
9a91a21f | 6490 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6491 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
8cc6307c | 6492 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6493 | "@ |
9a91a21f AS |
6494 | alc<g>r\t%0,%2 |
6495 | alc<g>\t%0,%2" | |
e69166de UW |
6496 | [(set_attr "op_type" "RRE,RXY")]) |
6497 | ||
43a09b63 | 6498 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6499 | (define_insn "*add<mode>3_alc" |
6500 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6501 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6502 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6503 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6504 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6505 | "" |
e69166de | 6506 | "@ |
9a91a21f AS |
6507 | alc<g>r\t%0,%2 |
6508 | alc<g>\t%0,%2" | |
e69166de UW |
6509 | [(set_attr "op_type" "RRE,RXY")]) |
6510 | ||
43a09b63 | 6511 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6512 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6513 | [(set (reg CC_REGNUM) |
e69166de | 6514 | (compare |
9a91a21f | 6515 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6516 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6517 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6518 | (const_int 0))) |
9a91a21f AS |
6519 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6520 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
8cc6307c | 6521 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6522 | "@ |
9a91a21f AS |
6523 | slb<g>r\t%0,%2 |
6524 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6525 | [(set_attr "op_type" "RRE,RXY") |
6526 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6527 | |
43a09b63 | 6528 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6529 | (define_insn "*sub<mode>3_slb" |
6530 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6531 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6532 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6533 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6534 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6535 | "" |
e69166de | 6536 | "@ |
9a91a21f AS |
6537 | slb<g>r\t%0,%2 |
6538 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6539 | [(set_attr "op_type" "RRE,RXY") |
6540 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6541 | |
9a91a21f AS |
6542 | (define_expand "add<mode>cc" |
6543 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6544 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6545 | (match_operand:GPR 2 "register_operand" "") |
6546 | (match_operand:GPR 3 "const_int_operand" "")] | |
8cc6307c | 6547 | "" |
9381e3f1 | 6548 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6549 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6550 | operands[0], operands[2], |
5d880bd2 UW |
6551 | operands[3])) FAIL; DONE;") |
6552 | ||
6553 | ; | |
6554 | ; scond instruction pattern(s). | |
6555 | ; | |
6556 | ||
9a91a21f AS |
6557 | (define_insn_and_split "*scond<mode>" |
6558 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6559 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6560 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6561 | "" |
5d880bd2 UW |
6562 | "#" |
6563 | "&& reload_completed" | |
6564 | [(set (match_dup 0) (const_int 0)) | |
6565 | (parallel | |
a94a76a7 UW |
6566 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6567 | (match_dup 0))) | |
ae156f85 | 6568 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6569 | "") |
5d880bd2 | 6570 | |
9a91a21f AS |
6571 | (define_insn_and_split "*scond<mode>_neg" |
6572 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6573 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6574 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6575 | "" |
5d880bd2 UW |
6576 | "#" |
6577 | "&& reload_completed" | |
6578 | [(set (match_dup 0) (const_int 0)) | |
6579 | (parallel | |
9a91a21f AS |
6580 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6581 | (match_dup 1))) | |
ae156f85 | 6582 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6583 | (parallel |
9a91a21f | 6584 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6585 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6586 | "") |
5d880bd2 | 6587 | |
5d880bd2 | 6588 | |
f90b7a5a | 6589 | (define_expand "cstore<mode>4" |
9a91a21f | 6590 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6591 | (match_operator:SI 1 "s390_scond_operator" |
6592 | [(match_operand:GPR 2 "register_operand" "") | |
6593 | (match_operand:GPR 3 "general_operand" "")]))] | |
8cc6307c | 6594 | "" |
f90b7a5a | 6595 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6596 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6597 | ||
f90b7a5a | 6598 | (define_expand "cstorecc4" |
69950452 | 6599 | [(parallel |
f90b7a5a PB |
6600 | [(set (match_operand:SI 0 "register_operand" "") |
6601 | (match_operator:SI 1 "s390_eqne_operator" | |
3ea685e7 | 6602 | [(match_operand 2 "cc_reg_operand") |
f90b7a5a | 6603 | (match_operand 3 "const0_operand")])) |
69950452 AS |
6604 | (clobber (reg:CC CC_REGNUM))])] |
6605 | "" | |
3ea685e7 DV |
6606 | "machine_mode mode = GET_MODE (operands[2]); |
6607 | if (TARGET_Z196) | |
6608 | { | |
6609 | rtx cond, ite; | |
6610 | ||
6611 | if (GET_CODE (operands[1]) == NE) | |
6612 | cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); | |
6613 | else | |
6614 | cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); | |
6615 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); | |
6616 | emit_insn (gen_rtx_SET (operands[0], ite)); | |
6617 | } | |
6618 | else | |
6619 | { | |
6620 | if (mode != CCZ1mode) | |
6621 | FAIL; | |
6622 | emit_insn (gen_sne (operands[0], operands[2])); | |
6623 | if (GET_CODE (operands[1]) == EQ) | |
6624 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6625 | } | |
f90b7a5a | 6626 | DONE;") |
69950452 | 6627 | |
f90b7a5a | 6628 | (define_insn_and_split "sne" |
69950452 | 6629 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6630 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6631 | (const_int 0))) |
6632 | (clobber (reg:CC CC_REGNUM))] | |
6633 | "" | |
6634 | "#" | |
6635 | "reload_completed" | |
6636 | [(parallel | |
6637 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6638 | (clobber (reg:CC CC_REGNUM))])]) | |
6639 | ||
e69166de | 6640 | |
65b1d8ea AK |
6641 | ;; |
6642 | ;; - Conditional move instructions (introduced with z196) | |
6643 | ;; | |
6644 | ||
6645 | (define_expand "mov<mode>cc" | |
6646 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6647 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
88e845c0 RD |
6648 | (match_operand:GPR 2 "loc_operand" "") |
6649 | (match_operand:GPR 3 "loc_operand" "")))] | |
65b1d8ea | 6650 | "TARGET_Z196" |
7477de01 | 6651 | { |
88e845c0 RD |
6652 | if (!TARGET_Z13 && CONSTANT_P (operands[2])) |
6653 | operands[2] = force_reg (<MODE>mode, operands[2]); | |
6654 | ||
6655 | if (!TARGET_Z13 && CONSTANT_P (operands[3])) | |
6656 | operands[3] = force_reg (<MODE>mode, operands[3]); | |
6657 | ||
7477de01 AK |
6658 | /* Emit the comparison insn in case we do not already have a comparison result. */ |
6659 | if (!s390_comparison (operands[1], VOIDmode)) | |
6660 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6661 | XEXP (operands[1], 0), | |
6662 | XEXP (operands[1], 1)); | |
6663 | }) | |
65b1d8ea | 6664 | |
d8928886 RD |
6665 | ;; |
6666 | ;; - We do not have instructions for QImode or HImode but still | |
6667 | ;; enable load on condition/if conversion for them. | |
6668 | (define_expand "mov<mode>cc" | |
6669 | [(set (match_operand:HQI 0 "nonimmediate_operand" "") | |
6670 | (if_then_else:HQI (match_operand 1 "comparison_operator" "") | |
6671 | (match_operand:HQI 2 "loc_operand" "") | |
6672 | (match_operand:HQI 3 "loc_operand" "")))] | |
6673 | "TARGET_Z196" | |
6674 | { | |
6675 | /* Emit the comparison insn in case we do not already have a comparison | |
6676 | result. */ | |
6677 | if (!s390_comparison (operands[1], VOIDmode)) | |
6678 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6679 | XEXP (operands[1], 0), | |
6680 | XEXP (operands[1], 1)); | |
6681 | ||
6682 | rtx then = operands[2]; | |
6683 | rtx els = operands[3]; | |
6684 | ||
6685 | if ((!TARGET_Z13 && CONSTANT_P (then)) || MEM_P (then)) | |
6686 | then = force_reg (<MODE>mode, then); | |
6687 | if ((!TARGET_Z13 && CONSTANT_P (els)) || MEM_P (els)) | |
6688 | els = force_reg (<MODE>mode, els); | |
6689 | ||
6690 | if (!CONSTANT_P (then)) | |
6691 | then = simplify_gen_subreg (E_SImode, then, <MODE>mode, 0); | |
6692 | if (!CONSTANT_P (els)) | |
6693 | els = simplify_gen_subreg (E_SImode, els, <MODE>mode, 0); | |
6694 | ||
6695 | rtx tmp_target = gen_reg_rtx (E_SImode); | |
6696 | emit_insn (gen_movsicc (tmp_target, operands[1], then, els)); | |
6697 | emit_move_insn (operands[0], gen_lowpart (<MODE>mode, tmp_target)); | |
6698 | DONE; | |
6699 | }) | |
6700 | ||
6701 | ||
6702 | ||
bf749919 | 6703 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi |
561f6312 AK |
6704 | (define_insn "*mov<mode>cc" |
6705 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S") | |
65b1d8ea AK |
6706 | (if_then_else:GPR |
6707 | (match_operator 1 "s390_comparison" | |
561f6312 | 6708 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c") |
5a3fe9b6 | 6709 | (match_operand 5 "const_int_operand" "")]) |
561f6312 AK |
6710 | (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0") |
6711 | (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))] | |
65b1d8ea AK |
6712 | "TARGET_Z196" |
6713 | "@ | |
6714 | loc<g>r%C1\t%0,%3 | |
6715 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6716 | loc<g>%C1\t%0,%3 |
6717 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6718 | loc<g>hi%C1\t%0,%h3 |
6719 | loc<g>hi%D1\t%0,%h4 | |
a6510374 | 6720 | stoc<g>%C1\t%3,%0 |
561f6312 AK |
6721 | stoc<g>%D1\t%4,%0" |
6722 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") | |
6723 | (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")]) | |
65b1d8ea | 6724 | |
9db1d521 HP |
6725 | ;; |
6726 | ;;- Multiply instructions. | |
6727 | ;; | |
6728 | ||
4023fb28 UW |
6729 | ; |
6730 | ; muldi3 instruction pattern(s). | |
6731 | ; | |
9db1d521 | 6732 | |
7d2fd075 AK |
6733 | (define_expand "muldi3" |
6734 | [(parallel | |
6735 | [(set (match_operand:DI 0 "register_operand") | |
6736 | (mult:DI (match_operand:DI 1 "nonimmediate_operand") | |
6737 | (match_operand:DI 2 "general_operand"))) | |
6738 | (clobber (reg:CC CC_REGNUM))])] | |
6739 | "TARGET_ZARCH") | |
6740 | ||
07893d4f UW |
6741 | (define_insn "*muldi3_sign" |
6742 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6743 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6744 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6745 | "TARGET_ZARCH" |
07893d4f | 6746 | "@ |
d40c829f UW |
6747 | msgfr\t%0,%2 |
6748 | msgf\t%0,%2" | |
963fc8d0 AK |
6749 | [(set_attr "op_type" "RRE,RXY") |
6750 | (set_attr "type" "imuldi")]) | |
07893d4f | 6751 | |
7d2fd075 AK |
6752 | (define_insn "*muldi3" |
6753 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") | |
6754 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") | |
6755 | (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) | |
6756 | (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] | |
9602b6a1 | 6757 | "TARGET_ZARCH" |
9db1d521 | 6758 | "@ |
d40c829f | 6759 | msgr\t%0,%2 |
7d2fd075 | 6760 | msgrkc\t%0,%1,%2 |
d40c829f | 6761 | mghi\t%0,%h2 |
963fc8d0 AK |
6762 | msg\t%0,%2 |
6763 | msgfi\t%0,%2" | |
7d2fd075 | 6764 | [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") |
963fc8d0 | 6765 | (set_attr "type" "imuldi") |
e9e8efc9 | 6766 | (set_attr "cpu_facility" "*,z14,*,*,z10")]) |
7d2fd075 AK |
6767 | |
6768 | (define_insn "mulditi3" | |
6769 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6770 | (mult:TI (sign_extend:TI | |
6771 | (match_operand:DI 1 "register_operand" "%d,0")) | |
6772 | (sign_extend:TI | |
6773 | (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] | |
e9e8efc9 | 6774 | "TARGET_Z14" |
7d2fd075 AK |
6775 | "@ |
6776 | mgrk\t%0,%1,%2 | |
6777 | mg\t%0,%2" | |
6778 | [(set_attr "op_type" "RRF,RXY")]) | |
6779 | ||
6780 | ; Combine likes op1 and op2 to be swapped sometimes. | |
6781 | (define_insn "mulditi3_2" | |
6782 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6783 | (mult:TI (sign_extend:TI | |
6784 | (match_operand:DI 1 "nonimmediate_operand" "%d,T")) | |
6785 | (sign_extend:TI | |
6786 | (match_operand:DI 2 "register_operand" " d,0"))))] | |
e9e8efc9 | 6787 | "TARGET_Z14" |
7d2fd075 AK |
6788 | "@ |
6789 | mgrk\t%0,%1,%2 | |
6790 | mg\t%0,%1" | |
6791 | [(set_attr "op_type" "RRF,RXY")]) | |
6792 | ||
6793 | (define_insn "*muldi3_sign" | |
6794 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6795 | (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
6796 | (match_operand:DI 1 "register_operand" "0")))] | |
e9e8efc9 | 6797 | "TARGET_Z14" |
7d2fd075 AK |
6798 | "mgh\t%0,%2" |
6799 | [(set_attr "op_type" "RXY")]) | |
6800 | ||
f2d3c02a | 6801 | |
9db1d521 HP |
6802 | ; |
6803 | ; mulsi3 instruction pattern(s). | |
6804 | ; | |
6805 | ||
7d2fd075 AK |
6806 | (define_expand "mulsi3" |
6807 | [(parallel | |
6808 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6809 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6810 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6811 | (clobber (reg:CC CC_REGNUM))])] | |
6812 | "") | |
6813 | ||
f1e77d83 | 6814 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6815 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6816 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6817 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6818 | "" |
963fc8d0 AK |
6819 | "@ |
6820 | mh\t%0,%2 | |
6821 | mhy\t%0,%2" | |
6822 | [(set_attr "op_type" "RX,RXY") | |
6823 | (set_attr "type" "imulhi") | |
6824 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6825 | |
7d2fd075 AK |
6826 | (define_insn "*mulsi3" |
6827 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6828 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6829 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6830 | (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] | |
9db1d521 HP |
6831 | "" |
6832 | "@ | |
d40c829f | 6833 | msr\t%0,%2 |
7d2fd075 | 6834 | msrkc\t%0,%1,%2 |
d40c829f UW |
6835 | mhi\t%0,%h2 |
6836 | ms\t%0,%2 | |
963fc8d0 AK |
6837 | msy\t%0,%2 |
6838 | msfi\t%0,%2" | |
7d2fd075 AK |
6839 | [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") |
6840 | (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") | |
e9e8efc9 | 6841 | (set_attr "cpu_facility" "*,z14,*,*,longdisp,z10")]) |
9db1d521 | 6842 | |
4023fb28 UW |
6843 | ; |
6844 | ; mulsidi3 instruction pattern(s). | |
6845 | ; | |
6846 | ||
f1e77d83 | 6847 | (define_insn "mulsidi3" |
963fc8d0 | 6848 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6849 | (mult:DI (sign_extend:DI |
963fc8d0 | 6850 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6851 | (sign_extend:DI |
963fc8d0 | 6852 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6853 | "!TARGET_ZARCH" |
f1e77d83 UW |
6854 | "@ |
6855 | mr\t%0,%2 | |
963fc8d0 AK |
6856 | m\t%0,%2 |
6857 | mfy\t%0,%2" | |
6858 | [(set_attr "op_type" "RR,RX,RXY") | |
6859 | (set_attr "type" "imulsi") | |
6860 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6861 | |
f1e77d83 | 6862 | ; |
6e0d70c9 | 6863 | ; umul instruction pattern(s). |
f1e77d83 | 6864 | ; |
c7453384 | 6865 | |
6e0d70c9 AK |
6866 | ; mlr, ml, mlgr, mlg |
6867 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 6868 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 6869 | (mult:DW (zero_extend:DW |
3e4be43f | 6870 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 6871 | (zero_extend:DW |
3e4be43f | 6872 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
8cc6307c | 6873 | "" |
f1e77d83 | 6874 | "@ |
6e0d70c9 AK |
6875 | ml<tg>r\t%0,%2 |
6876 | ml<tg>\t%0,%2" | |
f1e77d83 | 6877 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6878 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6879 | |
9db1d521 | 6880 | ; |
609e7e80 | 6881 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6882 | ; |
6883 | ||
9381e3f1 | 6884 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6885 | (define_insn "mul<mode>3" |
2de2b3f9 AK |
6886 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6887 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
6888 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 6889 | "TARGET_HARD_FLOAT" |
9db1d521 | 6890 | "@ |
62d3f261 AK |
6891 | m<xdee>tr\t%0,%1,%2 |
6892 | m<xdee>br\t%0,%2 | |
6e5b5de8 | 6893 | m<xdee>b\t%0,%2 |
2de2b3f9 AK |
6894 | wfmdb\t%v0,%v1,%v2 |
6895 | wfmsb\t%v0,%v1,%v2" | |
6896 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6897 | (set_attr "type" "fmul<mode>") |
2de2b3f9 AK |
6898 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6899 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6900 | |
9381e3f1 | 6901 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6902 | (define_insn "fma<mode>4" |
2de2b3f9 AK |
6903 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6904 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6905 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6906 | (match_operand:DSF 3 "register_operand" "0,0,v,v")))] | |
d7ecb504 | 6907 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6908 | "@ |
f61a2c7d | 6909 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 | 6910 | ma<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6911 | wfmadb\t%v0,%v1,%v2,%v3 |
6912 | wfmasb\t%v0,%v1,%v2,%v3" | |
6913 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6914 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6915 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6916 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
a1b892b5 | 6917 | |
43a09b63 | 6918 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6919 | (define_insn "fms<mode>4" |
2de2b3f9 AK |
6920 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6921 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6922 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6923 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] | |
d7ecb504 | 6924 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6925 | "@ |
f61a2c7d | 6926 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 | 6927 | ms<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6928 | wfmsdb\t%v0,%v1,%v2,%v3 |
6929 | wfmssb\t%v0,%v1,%v2,%v3" | |
6930 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6931 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6932 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6933 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
9db1d521 HP |
6934 | |
6935 | ;; | |
6936 | ;;- Divide and modulo instructions. | |
6937 | ;; | |
6938 | ||
6939 | ; | |
4023fb28 | 6940 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6941 | ; |
6942 | ||
4023fb28 UW |
6943 | (define_expand "divmoddi4" |
6944 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6945 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6946 | (match_operand:DI 2 "general_operand" ""))) |
6947 | (set (match_operand:DI 3 "general_operand" "") | |
6948 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6949 | (clobber (match_dup 4))] | |
9602b6a1 | 6950 | "TARGET_ZARCH" |
9db1d521 | 6951 | { |
d8485bdb TS |
6952 | rtx div_equal, mod_equal; |
6953 | rtx_insn *insn; | |
4023fb28 UW |
6954 | |
6955 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6956 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6957 | |
6958 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6959 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6960 | |
6961 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6962 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6963 | |
6964 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6965 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6966 | |
9db1d521 | 6967 | DONE; |
10bbf137 | 6968 | }) |
9db1d521 HP |
6969 | |
6970 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6971 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6972 | (ior:TI | |
4023fb28 UW |
6973 | (ashift:TI |
6974 | (zero_extend:TI | |
5665e398 | 6975 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6976 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
6977 | (const_int 64)) |
6978 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6979 | "TARGET_ZARCH" |
9db1d521 | 6980 | "@ |
d40c829f UW |
6981 | dsgr\t%0,%2 |
6982 | dsg\t%0,%2" | |
d3632d41 | 6983 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6984 | (set_attr "type" "idiv")]) |
9db1d521 | 6985 | |
4023fb28 UW |
6986 | (define_insn "divmodtisi3" |
6987 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6988 | (ior:TI | |
4023fb28 UW |
6989 | (ashift:TI |
6990 | (zero_extend:TI | |
5665e398 | 6991 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6992 | (sign_extend:DI |
3e4be43f | 6993 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
6994 | (const_int 64)) |
6995 | (zero_extend:TI | |
6996 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6997 | "TARGET_ZARCH" |
4023fb28 | 6998 | "@ |
d40c829f UW |
6999 | dsgfr\t%0,%2 |
7000 | dsgf\t%0,%2" | |
d3632d41 | 7001 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7002 | (set_attr "type" "idiv")]) |
9db1d521 | 7003 | |
4023fb28 UW |
7004 | ; |
7005 | ; udivmoddi4 instruction pattern(s). | |
7006 | ; | |
9db1d521 | 7007 | |
4023fb28 UW |
7008 | (define_expand "udivmoddi4" |
7009 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
7010 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
7011 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7012 | (set (match_operand:DI 3 "general_operand" "") | |
7013 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
7014 | (clobber (match_dup 4))] | |
9602b6a1 | 7015 | "TARGET_ZARCH" |
9db1d521 | 7016 | { |
d8485bdb TS |
7017 | rtx div_equal, mod_equal, equal; |
7018 | rtx_insn *insn; | |
4023fb28 UW |
7019 | |
7020 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
7021 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
7022 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
7023 | gen_rtx_ASHIFT (TImode, |
7024 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
7025 | GEN_INT (64)), |
7026 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
7027 | |
7028 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 7029 | emit_clobber (operands[4]); |
4023fb28 UW |
7030 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
7031 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 7032 | |
4023fb28 | 7033 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7034 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7035 | |
7036 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 7037 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7038 | |
7039 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 7040 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7041 | |
9db1d521 | 7042 | DONE; |
10bbf137 | 7043 | }) |
9db1d521 HP |
7044 | |
7045 | (define_insn "udivmodtidi3" | |
4023fb28 | 7046 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 7047 | (ior:TI |
5665e398 UW |
7048 | (ashift:TI |
7049 | (zero_extend:TI | |
7050 | (truncate:DI | |
2f7e5a0d EC |
7051 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
7052 | (zero_extend:TI | |
3e4be43f | 7053 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7054 | (const_int 64)) |
7055 | (zero_extend:TI | |
7056 | (truncate:DI | |
7057 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 7058 | "TARGET_ZARCH" |
9db1d521 | 7059 | "@ |
d40c829f UW |
7060 | dlgr\t%0,%2 |
7061 | dlg\t%0,%2" | |
d3632d41 | 7062 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7063 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7064 | |
7065 | ; | |
4023fb28 | 7066 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
7067 | ; |
7068 | ||
4023fb28 UW |
7069 | (define_expand "divmodsi4" |
7070 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7071 | (div:SI (match_operand:SI 1 "general_operand" "") | |
7072 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7073 | (set (match_operand:SI 3 "general_operand" "") | |
7074 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
7075 | (clobber (match_dup 4))] | |
9602b6a1 | 7076 | "!TARGET_ZARCH" |
9db1d521 | 7077 | { |
d8485bdb TS |
7078 | rtx div_equal, mod_equal, equal; |
7079 | rtx_insn *insn; | |
4023fb28 UW |
7080 | |
7081 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
7082 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
7083 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7084 | gen_rtx_ASHIFT (DImode, |
7085 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7086 | GEN_INT (32)), |
7087 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
7088 | |
7089 | operands[4] = gen_reg_rtx(DImode); | |
7090 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 7091 | |
4023fb28 | 7092 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7093 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7094 | |
7095 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7096 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7097 | |
7098 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7099 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7100 | |
9db1d521 | 7101 | DONE; |
10bbf137 | 7102 | }) |
9db1d521 HP |
7103 | |
7104 | (define_insn "divmoddisi3" | |
4023fb28 | 7105 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 7106 | (ior:DI |
5665e398 UW |
7107 | (ashift:DI |
7108 | (zero_extend:DI | |
7109 | (truncate:SI | |
2f7e5a0d EC |
7110 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
7111 | (sign_extend:DI | |
5665e398 UW |
7112 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
7113 | (const_int 32)) | |
7114 | (zero_extend:DI | |
7115 | (truncate:SI | |
7116 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7117 | "!TARGET_ZARCH" |
9db1d521 | 7118 | "@ |
d40c829f UW |
7119 | dr\t%0,%2 |
7120 | d\t%0,%2" | |
9db1d521 | 7121 | [(set_attr "op_type" "RR,RX") |
077dab3b | 7122 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7123 | |
7124 | ; | |
7125 | ; udivsi3 and umodsi3 instruction pattern(s). | |
7126 | ; | |
7127 | ||
f1e77d83 UW |
7128 | (define_expand "udivmodsi4" |
7129 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7130 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
7131 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7132 | (set (match_operand:SI 3 "general_operand" "") | |
7133 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
7134 | (clobber (match_dup 4))] | |
8cc6307c | 7135 | "!TARGET_ZARCH" |
f1e77d83 | 7136 | { |
d8485bdb TS |
7137 | rtx div_equal, mod_equal, equal; |
7138 | rtx_insn *insn; | |
f1e77d83 UW |
7139 | |
7140 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7141 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7142 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
7143 | gen_rtx_ASHIFT (DImode, |
7144 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7145 | GEN_INT (32)), |
7146 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
7147 | |
7148 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 7149 | emit_clobber (operands[4]); |
f1e77d83 UW |
7150 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
7151 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 7152 | |
f1e77d83 | 7153 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7154 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
7155 | |
7156 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7157 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
7158 | |
7159 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7160 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
7161 | |
7162 | DONE; | |
7163 | }) | |
7164 | ||
7165 | (define_insn "udivmoddisi3" | |
7166 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 7167 | (ior:DI |
5665e398 UW |
7168 | (ashift:DI |
7169 | (zero_extend:DI | |
7170 | (truncate:SI | |
2f7e5a0d EC |
7171 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
7172 | (zero_extend:DI | |
3e4be43f | 7173 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7174 | (const_int 32)) |
7175 | (zero_extend:DI | |
7176 | (truncate:SI | |
7177 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
8cc6307c | 7178 | "!TARGET_ZARCH" |
f1e77d83 UW |
7179 | "@ |
7180 | dlr\t%0,%2 | |
7181 | dl\t%0,%2" | |
7182 | [(set_attr "op_type" "RRE,RXY") | |
7183 | (set_attr "type" "idiv")]) | |
4023fb28 | 7184 | |
9db1d521 | 7185 | ; |
f5905b37 | 7186 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7187 | ; |
7188 | ||
609e7e80 | 7189 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7190 | (define_insn "div<mode>3" |
2de2b3f9 AK |
7191 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7192 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
7193 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7194 | "TARGET_HARD_FLOAT" |
9db1d521 | 7195 | "@ |
62d3f261 AK |
7196 | d<xde>tr\t%0,%1,%2 |
7197 | d<xde>br\t%0,%2 | |
6e5b5de8 | 7198 | d<xde>b\t%0,%2 |
2de2b3f9 AK |
7199 | wfddb\t%v0,%v1,%v2 |
7200 | wfdsb\t%v0,%v1,%v2" | |
7201 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7202 | (set_attr "type" "fdiv<mode>") |
2de2b3f9 AK |
7203 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7204 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7205 | |
9db1d521 HP |
7206 | |
7207 | ;; | |
7208 | ;;- And instructions. | |
7209 | ;; | |
7210 | ||
047d35ed AS |
7211 | (define_expand "and<mode>3" |
7212 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7213 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7214 | (match_operand:INT 2 "general_operand" ""))) | |
7215 | (clobber (reg:CC CC_REGNUM))] | |
7216 | "" | |
7217 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7218 | ||
9db1d521 HP |
7219 | ; |
7220 | ; anddi3 instruction pattern(s). | |
7221 | ; | |
7222 | ||
7223 | (define_insn "*anddi3_cc" | |
ae156f85 | 7224 | [(set (reg CC_REGNUM) |
e3140518 | 7225 | (compare |
3e4be43f | 7226 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7227 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7228 | (const_int 0))) |
3e4be43f | 7229 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7230 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7231 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7232 | "@ |
d40c829f | 7233 | ngr\t%0,%2 |
65b1d8ea | 7234 | ngrk\t%0,%1,%2 |
e3140518 RH |
7235 | ng\t%0,%2 |
7236 | risbg\t%0,%1,%s2,128+%e2,0" | |
7237 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7238 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7239 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7240 | |
7241 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7242 | [(set (reg CC_REGNUM) |
e3140518 | 7243 | (compare |
3e4be43f | 7244 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7245 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7246 | (const_int 0))) |
3e4be43f | 7247 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7248 | "TARGET_ZARCH |
7249 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7250 | /* Do not steal TM patterns. */ |
7251 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7252 | "@ |
d40c829f | 7253 | ngr\t%0,%2 |
65b1d8ea | 7254 | ngrk\t%0,%1,%2 |
e3140518 RH |
7255 | ng\t%0,%2 |
7256 | risbg\t%0,%1,%s2,128+%e2,0" | |
7257 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7258 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7259 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7260 | |
3af8e996 | 7261 | (define_insn "*anddi3" |
65b1d8ea | 7262 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7263 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7264 | (and:DI |
7265 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7266 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7267 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7268 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7269 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7270 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7271 | "@ |
7272 | # | |
7273 | # | |
7274 | nihh\t%0,%j2 | |
7275 | nihl\t%0,%j2 | |
7276 | nilh\t%0,%j2 | |
7277 | nill\t%0,%j2 | |
7278 | nihf\t%0,%m2 | |
7279 | nilf\t%0,%m2 | |
7280 | ngr\t%0,%2 | |
65b1d8ea | 7281 | ngrk\t%0,%1,%2 |
ec24698e | 7282 | ng\t%0,%2 |
e3140518 | 7283 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7284 | # |
7285 | #" | |
e3140518 RH |
7286 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7287 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7288 | (set_attr "z10prop" "*, |
7289 | *, | |
7290 | z10_super_E1, | |
7291 | z10_super_E1, | |
7292 | z10_super_E1, | |
7293 | z10_super_E1, | |
7294 | z10_super_E1, | |
7295 | z10_super_E1, | |
7296 | z10_super_E1, | |
65b1d8ea | 7297 | *, |
9381e3f1 | 7298 | z10_super_E1, |
e3140518 | 7299 | z10_super_E1, |
9381e3f1 WG |
7300 | *, |
7301 | *")]) | |
0dfa6c5e UW |
7302 | |
7303 | (define_split | |
7304 | [(set (match_operand:DI 0 "s_operand" "") | |
7305 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7306 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7307 | "reload_completed" |
7308 | [(parallel | |
7309 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7310 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7311 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7312 | |
1a2e356e | 7313 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7314 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7315 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7316 | (and:GPR (lshiftrt:GPR | |
7317 | (match_operand:GPR 1 "register_operand" "d") | |
7318 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7319 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7320 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7321 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7322 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7323 | INTVAL (operands[3]))" | |
64c744b9 | 7324 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7325 | [(set_attr "op_type" "RIE") |
7326 | (set_attr "z10prop" "z10_super_E1")]) | |
7327 | ||
64c744b9 | 7328 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7329 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7330 | (and:GPR (ashift:GPR | |
7331 | (match_operand:GPR 1 "register_operand" "d") | |
7332 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7333 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7334 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7335 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7336 | INTVAL (operands[3]))" | |
64c744b9 | 7337 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7338 | [(set_attr "op_type" "RIE") |
7339 | (set_attr "z10prop" "z10_super_E1")]) | |
7340 | ||
9db1d521 HP |
7341 | |
7342 | ; | |
7343 | ; andsi3 instruction pattern(s). | |
7344 | ; | |
7345 | ||
7346 | (define_insn "*andsi3_cc" | |
ae156f85 | 7347 | [(set (reg CC_REGNUM) |
e3140518 RH |
7348 | (compare |
7349 | (and:SI | |
7350 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7351 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7352 | (const_int 0))) | |
7353 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7354 | (and:SI (match_dup 1) (match_dup 2)))] |
7355 | "s390_match_ccmode(insn, CCTmode)" | |
7356 | "@ | |
ec24698e | 7357 | nilf\t%0,%o2 |
d40c829f | 7358 | nr\t%0,%2 |
65b1d8ea | 7359 | nrk\t%0,%1,%2 |
d40c829f | 7360 | n\t%0,%2 |
e3140518 RH |
7361 | ny\t%0,%2 |
7362 | risbg\t%0,%1,%t2,128+%f2,0" | |
7363 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7364 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7365 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7366 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7367 | |
7368 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7369 | [(set (reg CC_REGNUM) |
e3140518 RH |
7370 | (compare |
7371 | (and:SI | |
7372 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7373 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7374 | (const_int 0))) | |
7375 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7376 | "s390_match_ccmode(insn, CCTmode) |
7377 | /* Do not steal TM patterns. */ | |
7378 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7379 | "@ |
ec24698e | 7380 | nilf\t%0,%o2 |
d40c829f | 7381 | nr\t%0,%2 |
65b1d8ea | 7382 | nrk\t%0,%1,%2 |
d40c829f | 7383 | n\t%0,%2 |
e3140518 RH |
7384 | ny\t%0,%2 |
7385 | risbg\t%0,%1,%t2,128+%f2,0" | |
7386 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7387 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7388 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7389 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7390 | |
f19a9af7 | 7391 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7392 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7393 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7394 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7395 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7396 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7397 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7398 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7399 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7400 | "@ |
f19a9af7 AK |
7401 | # |
7402 | # | |
7403 | nilh\t%0,%j2 | |
2f7e5a0d | 7404 | nill\t%0,%j2 |
ec24698e | 7405 | nilf\t%0,%o2 |
d40c829f | 7406 | nr\t%0,%2 |
65b1d8ea | 7407 | nrk\t%0,%1,%2 |
d40c829f | 7408 | n\t%0,%2 |
8cb66696 | 7409 | ny\t%0,%2 |
e3140518 | 7410 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7411 | # |
19b63d8e | 7412 | #" |
e3140518 | 7413 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7414 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7415 | (set_attr "z10prop" "*, |
7416 | *, | |
7417 | z10_super_E1, | |
7418 | z10_super_E1, | |
7419 | z10_super_E1, | |
7420 | z10_super_E1, | |
65b1d8ea | 7421 | *, |
9381e3f1 WG |
7422 | z10_super_E1, |
7423 | z10_super_E1, | |
e3140518 | 7424 | z10_super_E1, |
9381e3f1 WG |
7425 | *, |
7426 | *")]) | |
f19a9af7 AK |
7427 | |
7428 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7429 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7430 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7431 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7432 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7433 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7434 | "@ |
7435 | nr\t%0,%2 | |
8cb66696 | 7436 | n\t%0,%2 |
0dfa6c5e | 7437 | # |
19b63d8e | 7438 | #" |
9381e3f1 WG |
7439 | [(set_attr "op_type" "RR,RX,SI,SS") |
7440 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7441 | ||
0dfa6c5e UW |
7442 | |
7443 | (define_split | |
7444 | [(set (match_operand:SI 0 "s_operand" "") | |
7445 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7446 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7447 | "reload_completed" |
7448 | [(parallel | |
7449 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7450 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7451 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7452 | |
9db1d521 HP |
7453 | ; |
7454 | ; andhi3 instruction pattern(s). | |
7455 | ; | |
7456 | ||
8cb66696 | 7457 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7458 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7459 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7460 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7461 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7462 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7463 | "@ |
d40c829f | 7464 | nr\t%0,%2 |
65b1d8ea | 7465 | nrk\t%0,%1,%2 |
8cb66696 | 7466 | nill\t%0,%x2 |
0dfa6c5e | 7467 | # |
19b63d8e | 7468 | #" |
65b1d8ea AK |
7469 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7470 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7471 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7472 | ]) |
8cb66696 UW |
7473 | |
7474 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7475 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7476 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7477 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7478 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7479 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7480 | "@ | |
7481 | nr\t%0,%2 | |
0dfa6c5e | 7482 | # |
19b63d8e | 7483 | #" |
9381e3f1 WG |
7484 | [(set_attr "op_type" "RR,SI,SS") |
7485 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7486 | ]) | |
0dfa6c5e UW |
7487 | |
7488 | (define_split | |
7489 | [(set (match_operand:HI 0 "s_operand" "") | |
7490 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7491 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7492 | "reload_completed" |
7493 | [(parallel | |
7494 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7495 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7496 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7497 | |
9db1d521 HP |
7498 | ; |
7499 | ; andqi3 instruction pattern(s). | |
7500 | ; | |
7501 | ||
8cb66696 | 7502 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7503 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7504 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7505 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7506 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7507 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7508 | "@ |
d40c829f | 7509 | nr\t%0,%2 |
65b1d8ea | 7510 | nrk\t%0,%1,%2 |
8cb66696 | 7511 | nill\t%0,%b2 |
fc0ea003 UW |
7512 | ni\t%S0,%b2 |
7513 | niy\t%S0,%b2 | |
19b63d8e | 7514 | #" |
65b1d8ea | 7515 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7516 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7517 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7518 | |
7519 | (define_insn "*andqi3_esa" | |
7520 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7521 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7522 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7523 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7524 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7525 | "@ |
8cb66696 | 7526 | nr\t%0,%2 |
fc0ea003 | 7527 | ni\t%S0,%b2 |
19b63d8e | 7528 | #" |
9381e3f1 WG |
7529 | [(set_attr "op_type" "RR,SI,SS") |
7530 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7531 | |
deb9351f DV |
7532 | ; |
7533 | ; And with complement | |
7534 | ; | |
7535 | ; c = ~b & a = (b & a) ^ a | |
7536 | ||
7537 | (define_insn_and_split "*andc_split_<mode>" | |
7538 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7539 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7540 | (match_operand:GPR 2 "general_operand" ""))) | |
7541 | (clobber (reg:CC CC_REGNUM))] | |
ad7ab32e DV |
7542 | "! reload_completed |
7543 | && (GET_CODE (operands[0]) != MEM | |
7544 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7545 | on the split xor if (b & a) is stored into a pseudo. */ | |
7546 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7547 | "#" |
7548 | "&& 1" | |
7549 | [ | |
7550 | (parallel | |
7551 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7552 | (clobber (reg:CC CC_REGNUM))]) | |
7553 | (parallel | |
7554 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7555 | (clobber (reg:CC CC_REGNUM))])] | |
7556 | { | |
7557 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7558 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7559 | else | |
7560 | operands[3] = operands[0]; | |
7561 | }) | |
7562 | ||
19b63d8e UW |
7563 | ; |
7564 | ; Block and (NC) patterns. | |
7565 | ; | |
7566 | ||
7567 | (define_insn "*nc" | |
7568 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7569 | (and:BLK (match_dup 0) | |
7570 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7571 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7572 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7573 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7574 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7575 | [(set_attr "op_type" "SS") |
7576 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7577 | |
7578 | (define_split | |
7579 | [(set (match_operand 0 "memory_operand" "") | |
7580 | (and (match_dup 0) | |
7581 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7582 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7583 | "reload_completed |
7584 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7585 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7586 | [(parallel | |
7587 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7588 | (use (match_dup 2)) | |
ae156f85 | 7589 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7590 | { |
7591 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7592 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7593 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7594 | }) | |
7595 | ||
7596 | (define_peephole2 | |
7597 | [(parallel | |
7598 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7599 | (and:BLK (match_dup 0) | |
7600 | (match_operand:BLK 1 "memory_operand" ""))) | |
7601 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7602 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7603 | (parallel |
7604 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7605 | (and:BLK (match_dup 3) | |
7606 | (match_operand:BLK 4 "memory_operand" ""))) | |
7607 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7608 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7609 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7610 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7611 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7612 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7613 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7614 | [(parallel | |
7615 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7616 | (use (match_dup 8)) | |
ae156f85 | 7617 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7618 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7619 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7620 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7621 | ||
9db1d521 HP |
7622 | |
7623 | ;; | |
7624 | ;;- Bit set (inclusive or) instructions. | |
7625 | ;; | |
7626 | ||
047d35ed AS |
7627 | (define_expand "ior<mode>3" |
7628 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7629 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7630 | (match_operand:INT 2 "general_operand" ""))) | |
7631 | (clobber (reg:CC CC_REGNUM))] | |
7632 | "" | |
7633 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7634 | ||
9db1d521 HP |
7635 | ; |
7636 | ; iordi3 instruction pattern(s). | |
7637 | ; | |
7638 | ||
4023fb28 | 7639 | (define_insn "*iordi3_cc" |
ae156f85 | 7640 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7641 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7642 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7643 | (const_int 0))) |
3e4be43f | 7644 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7645 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7646 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7647 | "@ |
d40c829f | 7648 | ogr\t%0,%2 |
65b1d8ea | 7649 | ogrk\t%0,%1,%2 |
d40c829f | 7650 | og\t%0,%2" |
65b1d8ea AK |
7651 | [(set_attr "op_type" "RRE,RRF,RXY") |
7652 | (set_attr "cpu_facility" "*,z196,*") | |
7653 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7654 | |
7655 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7656 | [(set (reg CC_REGNUM) |
65b1d8ea | 7657 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7658 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7659 | (const_int 0))) |
65b1d8ea | 7660 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7661 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7662 | "@ |
d40c829f | 7663 | ogr\t%0,%2 |
65b1d8ea | 7664 | ogrk\t%0,%1,%2 |
d40c829f | 7665 | og\t%0,%2" |
65b1d8ea AK |
7666 | [(set_attr "op_type" "RRE,RRF,RXY") |
7667 | (set_attr "cpu_facility" "*,z196,*") | |
7668 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7669 | |
3af8e996 | 7670 | (define_insn "*iordi3" |
65b1d8ea | 7671 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7672 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7673 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7674 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7675 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7676 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7677 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7678 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7679 | "@ |
7680 | oihh\t%0,%i2 | |
7681 | oihl\t%0,%i2 | |
7682 | oilh\t%0,%i2 | |
7683 | oill\t%0,%i2 | |
7684 | oihf\t%0,%k2 | |
7685 | oilf\t%0,%k2 | |
7686 | ogr\t%0,%2 | |
65b1d8ea | 7687 | ogrk\t%0,%1,%2 |
ec24698e UW |
7688 | og\t%0,%2 |
7689 | # | |
7690 | #" | |
65b1d8ea AK |
7691 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7692 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7693 | (set_attr "z10prop" "z10_super_E1, |
7694 | z10_super_E1, | |
7695 | z10_super_E1, | |
7696 | z10_super_E1, | |
7697 | z10_super_E1, | |
7698 | z10_super_E1, | |
7699 | z10_super_E1, | |
65b1d8ea | 7700 | *, |
9381e3f1 WG |
7701 | z10_super_E1, |
7702 | *, | |
7703 | *")]) | |
0dfa6c5e UW |
7704 | |
7705 | (define_split | |
7706 | [(set (match_operand:DI 0 "s_operand" "") | |
7707 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7708 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7709 | "reload_completed" |
7710 | [(parallel | |
7711 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7712 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7713 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7714 | |
9db1d521 HP |
7715 | ; |
7716 | ; iorsi3 instruction pattern(s). | |
7717 | ; | |
7718 | ||
4023fb28 | 7719 | (define_insn "*iorsi3_cc" |
ae156f85 | 7720 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7721 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7722 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7723 | (const_int 0))) |
65b1d8ea | 7724 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7725 | (ior:SI (match_dup 1) (match_dup 2)))] |
7726 | "s390_match_ccmode(insn, CCTmode)" | |
7727 | "@ | |
ec24698e | 7728 | oilf\t%0,%o2 |
d40c829f | 7729 | or\t%0,%2 |
65b1d8ea | 7730 | ork\t%0,%1,%2 |
d40c829f UW |
7731 | o\t%0,%2 |
7732 | oy\t%0,%2" | |
65b1d8ea | 7733 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7734 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7735 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7736 | |
7737 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7738 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7739 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7740 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7741 | (const_int 0))) |
65b1d8ea | 7742 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7743 | "s390_match_ccmode(insn, CCTmode)" |
7744 | "@ | |
ec24698e | 7745 | oilf\t%0,%o2 |
d40c829f | 7746 | or\t%0,%2 |
65b1d8ea | 7747 | ork\t%0,%1,%2 |
d40c829f UW |
7748 | o\t%0,%2 |
7749 | oy\t%0,%2" | |
65b1d8ea | 7750 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7751 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7752 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7753 | |
8cb66696 | 7754 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7755 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7756 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7757 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7758 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7759 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7760 | "@ |
f19a9af7 AK |
7761 | oilh\t%0,%i2 |
7762 | oill\t%0,%i2 | |
ec24698e | 7763 | oilf\t%0,%o2 |
d40c829f | 7764 | or\t%0,%2 |
65b1d8ea | 7765 | ork\t%0,%1,%2 |
d40c829f | 7766 | o\t%0,%2 |
8cb66696 | 7767 | oy\t%0,%2 |
0dfa6c5e | 7768 | # |
19b63d8e | 7769 | #" |
65b1d8ea | 7770 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7771 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7772 | (set_attr "z10prop" "z10_super_E1, |
7773 | z10_super_E1, | |
7774 | z10_super_E1, | |
7775 | z10_super_E1, | |
65b1d8ea | 7776 | *, |
9381e3f1 WG |
7777 | z10_super_E1, |
7778 | z10_super_E1, | |
7779 | *, | |
7780 | *")]) | |
8cb66696 UW |
7781 | |
7782 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7783 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7784 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7785 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7786 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7787 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7788 | "@ |
7789 | or\t%0,%2 | |
8cb66696 | 7790 | o\t%0,%2 |
0dfa6c5e | 7791 | # |
19b63d8e | 7792 | #" |
9381e3f1 WG |
7793 | [(set_attr "op_type" "RR,RX,SI,SS") |
7794 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7795 | |
7796 | (define_split | |
7797 | [(set (match_operand:SI 0 "s_operand" "") | |
7798 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7799 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7800 | "reload_completed" |
7801 | [(parallel | |
7802 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7803 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7804 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7805 | |
4023fb28 UW |
7806 | ; |
7807 | ; iorhi3 instruction pattern(s). | |
7808 | ; | |
7809 | ||
8cb66696 | 7810 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7811 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7812 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7813 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7814 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7815 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7816 | "@ |
d40c829f | 7817 | or\t%0,%2 |
65b1d8ea | 7818 | ork\t%0,%1,%2 |
8cb66696 | 7819 | oill\t%0,%x2 |
0dfa6c5e | 7820 | # |
19b63d8e | 7821 | #" |
65b1d8ea AK |
7822 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7823 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7824 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7825 | |
7826 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7827 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7828 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7829 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7830 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7831 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7832 | "@ | |
7833 | or\t%0,%2 | |
0dfa6c5e | 7834 | # |
19b63d8e | 7835 | #" |
9381e3f1 WG |
7836 | [(set_attr "op_type" "RR,SI,SS") |
7837 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7838 | |
7839 | (define_split | |
7840 | [(set (match_operand:HI 0 "s_operand" "") | |
7841 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7842 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7843 | "reload_completed" |
7844 | [(parallel | |
7845 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7846 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7847 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7848 | |
9db1d521 | 7849 | ; |
4023fb28 | 7850 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7851 | ; |
7852 | ||
8cb66696 | 7853 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7854 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7855 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7856 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7857 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7858 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7859 | "@ |
d40c829f | 7860 | or\t%0,%2 |
65b1d8ea | 7861 | ork\t%0,%1,%2 |
8cb66696 | 7862 | oill\t%0,%b2 |
fc0ea003 UW |
7863 | oi\t%S0,%b2 |
7864 | oiy\t%S0,%b2 | |
19b63d8e | 7865 | #" |
65b1d8ea | 7866 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7867 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
7868 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
7869 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7870 | |
7871 | (define_insn "*iorqi3_esa" | |
7872 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7873 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7874 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7875 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7876 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7877 | "@ |
8cb66696 | 7878 | or\t%0,%2 |
fc0ea003 | 7879 | oi\t%S0,%b2 |
19b63d8e | 7880 | #" |
9381e3f1 WG |
7881 | [(set_attr "op_type" "RR,SI,SS") |
7882 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7883 | |
19b63d8e UW |
7884 | ; |
7885 | ; Block inclusive or (OC) patterns. | |
7886 | ; | |
7887 | ||
7888 | (define_insn "*oc" | |
7889 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7890 | (ior:BLK (match_dup 0) | |
7891 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7892 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7893 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7894 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7895 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7896 | [(set_attr "op_type" "SS") |
7897 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7898 | |
7899 | (define_split | |
7900 | [(set (match_operand 0 "memory_operand" "") | |
7901 | (ior (match_dup 0) | |
7902 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7903 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7904 | "reload_completed |
7905 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7906 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7907 | [(parallel | |
7908 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7909 | (use (match_dup 2)) | |
ae156f85 | 7910 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7911 | { |
7912 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7913 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7914 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7915 | }) | |
7916 | ||
7917 | (define_peephole2 | |
7918 | [(parallel | |
7919 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7920 | (ior:BLK (match_dup 0) | |
7921 | (match_operand:BLK 1 "memory_operand" ""))) | |
7922 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7923 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7924 | (parallel |
7925 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7926 | (ior:BLK (match_dup 3) | |
7927 | (match_operand:BLK 4 "memory_operand" ""))) | |
7928 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7929 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7930 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7931 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7932 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7933 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7934 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7935 | [(parallel | |
7936 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7937 | (use (match_dup 8)) | |
ae156f85 | 7938 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7939 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7940 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7941 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7942 | ||
9db1d521 HP |
7943 | |
7944 | ;; | |
7945 | ;;- Xor instructions. | |
7946 | ;; | |
7947 | ||
047d35ed AS |
7948 | (define_expand "xor<mode>3" |
7949 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7950 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7951 | (match_operand:INT 2 "general_operand" ""))) | |
7952 | (clobber (reg:CC CC_REGNUM))] | |
7953 | "" | |
7954 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7955 | ||
3c91f126 AK |
7956 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7957 | ; simplifications. So its better to have something matching. | |
7958 | (define_split | |
7959 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7960 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7961 | "" | |
7962 | [(parallel | |
7963 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7964 | (clobber (reg:CC CC_REGNUM))])] | |
7965 | { | |
7966 | operands[2] = constm1_rtx; | |
7967 | if (!s390_logical_operator_ok_p (operands)) | |
7968 | FAIL; | |
7969 | }) | |
7970 | ||
9db1d521 HP |
7971 | ; |
7972 | ; xordi3 instruction pattern(s). | |
7973 | ; | |
7974 | ||
4023fb28 | 7975 | (define_insn "*xordi3_cc" |
ae156f85 | 7976 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7977 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7978 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7979 | (const_int 0))) |
3e4be43f | 7980 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7981 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7982 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7983 | "@ |
d40c829f | 7984 | xgr\t%0,%2 |
65b1d8ea | 7985 | xgrk\t%0,%1,%2 |
d40c829f | 7986 | xg\t%0,%2" |
65b1d8ea | 7987 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7988 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7989 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7990 | |
7991 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7992 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7993 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7994 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7995 | (const_int 0))) |
3e4be43f | 7996 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7997 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7998 | "@ |
d40c829f | 7999 | xgr\t%0,%2 |
65b1d8ea | 8000 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 8001 | xg\t%0,%2" |
65b1d8ea AK |
8002 | [(set_attr "op_type" "RRE,RRF,RXY") |
8003 | (set_attr "cpu_facility" "*,z196,*") | |
8004 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 8005 | |
3af8e996 | 8006 | (define_insn "*xordi3" |
3e4be43f UW |
8007 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
8008 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
8009 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 8010 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8011 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
8012 | "@ |
8013 | xihf\t%0,%k2 | |
8014 | xilf\t%0,%k2 | |
8015 | xgr\t%0,%2 | |
65b1d8ea | 8016 | xgrk\t%0,%1,%2 |
ec24698e UW |
8017 | xg\t%0,%2 |
8018 | # | |
8019 | #" | |
65b1d8ea AK |
8020 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
8021 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
8022 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
8023 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8024 | |
8025 | (define_split | |
8026 | [(set (match_operand:DI 0 "s_operand" "") | |
8027 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 8028 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8029 | "reload_completed" |
8030 | [(parallel | |
8031 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8032 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8033 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 8034 | |
9db1d521 HP |
8035 | ; |
8036 | ; xorsi3 instruction pattern(s). | |
8037 | ; | |
8038 | ||
4023fb28 | 8039 | (define_insn "*xorsi3_cc" |
ae156f85 | 8040 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8041 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8042 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8043 | (const_int 0))) |
65b1d8ea | 8044 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
8045 | (xor:SI (match_dup 1) (match_dup 2)))] |
8046 | "s390_match_ccmode(insn, CCTmode)" | |
8047 | "@ | |
ec24698e | 8048 | xilf\t%0,%o2 |
d40c829f | 8049 | xr\t%0,%2 |
65b1d8ea | 8050 | xrk\t%0,%1,%2 |
d40c829f UW |
8051 | x\t%0,%2 |
8052 | xy\t%0,%2" | |
65b1d8ea | 8053 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8054 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8055 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8056 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
8057 | |
8058 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 8059 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8060 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8061 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8062 | (const_int 0))) |
65b1d8ea | 8063 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
8064 | "s390_match_ccmode(insn, CCTmode)" |
8065 | "@ | |
ec24698e | 8066 | xilf\t%0,%o2 |
d40c829f | 8067 | xr\t%0,%2 |
65b1d8ea | 8068 | xrk\t%0,%1,%2 |
d40c829f UW |
8069 | x\t%0,%2 |
8070 | xy\t%0,%2" | |
65b1d8ea | 8071 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8072 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8073 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8074 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 8075 | |
8cb66696 | 8076 | (define_insn "*xorsi3" |
65b1d8ea AK |
8077 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
8078 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
8079 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 8080 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8081 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8082 | "@ |
ec24698e | 8083 | xilf\t%0,%o2 |
d40c829f | 8084 | xr\t%0,%2 |
65b1d8ea | 8085 | xrk\t%0,%1,%2 |
d40c829f | 8086 | x\t%0,%2 |
8cb66696 | 8087 | xy\t%0,%2 |
0dfa6c5e | 8088 | # |
19b63d8e | 8089 | #" |
65b1d8ea | 8090 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8091 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8092 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8093 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8094 | |
8095 | (define_split | |
8096 | [(set (match_operand:SI 0 "s_operand" "") | |
8097 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8098 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8099 | "reload_completed" |
8100 | [(parallel | |
8101 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8102 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8103 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8104 | |
9db1d521 HP |
8105 | ; |
8106 | ; xorhi3 instruction pattern(s). | |
8107 | ; | |
8108 | ||
8cb66696 | 8109 | (define_insn "*xorhi3" |
65b1d8ea AK |
8110 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8111 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8112 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8113 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8114 | "s390_logical_operator_ok_p (operands)" |
8115 | "@ | |
ec24698e | 8116 | xilf\t%0,%x2 |
8cb66696 | 8117 | xr\t%0,%2 |
65b1d8ea | 8118 | xrk\t%0,%1,%2 |
0dfa6c5e | 8119 | # |
19b63d8e | 8120 | #" |
65b1d8ea AK |
8121 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8122 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8123 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8124 | |
8125 | (define_split | |
8126 | [(set (match_operand:HI 0 "s_operand" "") | |
8127 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8128 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8129 | "reload_completed" |
8130 | [(parallel | |
8131 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8132 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8133 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8134 | |
9db1d521 HP |
8135 | ; |
8136 | ; xorqi3 instruction pattern(s). | |
8137 | ; | |
8138 | ||
8cb66696 | 8139 | (define_insn "*xorqi3" |
65b1d8ea AK |
8140 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8141 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8142 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8143 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8144 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8145 | "@ |
ec24698e | 8146 | xilf\t%0,%b2 |
8cb66696 | 8147 | xr\t%0,%2 |
65b1d8ea | 8148 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8149 | xi\t%S0,%b2 |
8150 | xiy\t%S0,%b2 | |
19b63d8e | 8151 | #" |
65b1d8ea | 8152 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8153 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8154 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8155 | |
4023fb28 | 8156 | |
19b63d8e UW |
8157 | ; |
8158 | ; Block exclusive or (XC) patterns. | |
8159 | ; | |
8160 | ||
8161 | (define_insn "*xc" | |
8162 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8163 | (xor:BLK (match_dup 0) | |
8164 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8165 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8166 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8167 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8168 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8169 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8170 | |
8171 | (define_split | |
8172 | [(set (match_operand 0 "memory_operand" "") | |
8173 | (xor (match_dup 0) | |
8174 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8175 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8176 | "reload_completed |
8177 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8178 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8179 | [(parallel | |
8180 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8181 | (use (match_dup 2)) | |
ae156f85 | 8182 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8183 | { |
8184 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8185 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8186 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8187 | }) | |
8188 | ||
8189 | (define_peephole2 | |
8190 | [(parallel | |
8191 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8192 | (xor:BLK (match_dup 0) | |
8193 | (match_operand:BLK 1 "memory_operand" ""))) | |
8194 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8195 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8196 | (parallel |
8197 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8198 | (xor:BLK (match_dup 3) | |
8199 | (match_operand:BLK 4 "memory_operand" ""))) | |
8200 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8201 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8202 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8203 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8204 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8205 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8206 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8207 | [(parallel | |
8208 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8209 | (use (match_dup 8)) | |
ae156f85 | 8210 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8211 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8212 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8213 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8214 | ||
8215 | ; | |
8216 | ; Block xor (XC) patterns with src == dest. | |
8217 | ; | |
8218 | ||
8219 | (define_insn "*xc_zero" | |
8220 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8221 | (const_int 0)) | |
8222 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8223 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8224 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8225 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8226 | [(set_attr "op_type" "SS") |
8227 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8228 | |
8229 | (define_peephole2 | |
8230 | [(parallel | |
8231 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8232 | (const_int 0)) | |
8233 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8234 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8235 | (parallel |
8236 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8237 | (const_int 0)) | |
8238 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8239 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8240 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8241 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8242 | [(parallel | |
8243 | [(set (match_dup 4) (const_int 0)) | |
8244 | (use (match_dup 5)) | |
ae156f85 | 8245 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8246 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8247 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8248 | ||
9db1d521 HP |
8249 | |
8250 | ;; | |
8251 | ;;- Negate instructions. | |
8252 | ;; | |
8253 | ||
8254 | ; | |
9a91a21f | 8255 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8256 | ; |
8257 | ||
9a91a21f | 8258 | (define_expand "neg<mode>2" |
9db1d521 | 8259 | [(parallel |
9a91a21f AS |
8260 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8261 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8262 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8263 | "" |
8264 | "") | |
8265 | ||
26a89301 | 8266 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8267 | [(set (reg CC_REGNUM) |
26a89301 UW |
8268 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8269 | (match_operand:SI 1 "register_operand" "d") 0) | |
8270 | (const_int 32)) (const_int 32))) | |
8271 | (const_int 0))) | |
8272 | (set (match_operand:DI 0 "register_operand" "=d") | |
8273 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8274 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8275 | "lcgfr\t%0,%1" |
729e750f WG |
8276 | [(set_attr "op_type" "RRE") |
8277 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8278 | |
26a89301 UW |
8279 | (define_insn "*negdi2_sign" |
8280 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8281 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8282 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8283 | "TARGET_ZARCH" |
26a89301 | 8284 | "lcgfr\t%0,%1" |
729e750f WG |
8285 | [(set_attr "op_type" "RRE") |
8286 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8287 | |
43a09b63 | 8288 | ; lcr, lcgr |
9a91a21f | 8289 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8290 | [(set (reg CC_REGNUM) |
9a91a21f | 8291 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8292 | (const_int 0))) |
9a91a21f AS |
8293 | (set (match_operand:GPR 0 "register_operand" "=d") |
8294 | (neg:GPR (match_dup 1)))] | |
8295 | "s390_match_ccmode (insn, CCAmode)" | |
8296 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8297 | [(set_attr "op_type" "RR<E>") |
8298 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8299 | |
8300 | ; lcr, lcgr | |
9a91a21f | 8301 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8302 | [(set (reg CC_REGNUM) |
9a91a21f | 8303 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8304 | (const_int 0))) |
9a91a21f AS |
8305 | (clobber (match_scratch:GPR 0 "=d"))] |
8306 | "s390_match_ccmode (insn, CCAmode)" | |
8307 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8308 | [(set_attr "op_type" "RR<E>") |
8309 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8310 | |
8311 | ; lcr, lcgr | |
9a91a21f AS |
8312 | (define_insn "*neg<mode>2" |
8313 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8314 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8315 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8316 | "" |
8317 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8318 | [(set_attr "op_type" "RR<E>") |
8319 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8320 | |
b7d19263 | 8321 | (define_insn "*negdi2_31" |
9db1d521 HP |
8322 | [(set (match_operand:DI 0 "register_operand" "=d") |
8323 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8324 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8325 | "!TARGET_ZARCH" |
b7d19263 AK |
8326 | "#") |
8327 | ||
8328 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8329 | ||
8330 | ; Doing the twos complement separately on the SImode parts does an | |
8331 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8332 | ; ... unless the +1 on the low part created an overflow. | |
8333 | ||
8334 | (define_split | |
8335 | [(set (match_operand:DI 0 "register_operand" "") | |
8336 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8337 | (clobber (reg:CC CC_REGNUM))] | |
8338 | "!TARGET_ZARCH | |
8339 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8340 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8341 | && reload_completed" | |
26a89301 UW |
8342 | [(parallel |
8343 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8344 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8345 | (parallel |
ae156f85 | 8346 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8347 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8348 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8349 | (set (pc) | |
ae156f85 | 8350 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8351 | (pc) |
8352 | (label_ref (match_dup 6)))) | |
8353 | (parallel | |
8354 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8355 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8356 | (match_dup 6)] |
8357 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8358 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8359 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8360 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8361 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8362 | |
b7d19263 AK |
8363 | ; Like above but first make a copy of the low part of the src operand |
8364 | ; since it might overlap with the high part of the destination. | |
8365 | ||
8366 | (define_split | |
8367 | [(set (match_operand:DI 0 "register_operand" "") | |
8368 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8369 | (clobber (reg:CC CC_REGNUM))] | |
8370 | "!TARGET_ZARCH | |
8371 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8372 | && reload_completed" | |
8373 | [; Make a backup of op5 first | |
8374 | (set (match_dup 4) (match_dup 5)) | |
8375 | ; Setting op2 here might clobber op5 | |
8376 | (parallel | |
8377 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8378 | (clobber (reg:CC CC_REGNUM))]) | |
8379 | (parallel | |
8380 | [(set (reg:CCAP CC_REGNUM) | |
8381 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8382 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8383 | (set (pc) | |
8384 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8385 | (pc) | |
8386 | (label_ref (match_dup 6)))) | |
8387 | (parallel | |
8388 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8389 | (clobber (reg:CC CC_REGNUM))]) | |
8390 | (match_dup 6)] | |
8391 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8392 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8393 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8394 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8395 | operands[6] = gen_label_rtx ();") | |
8396 | ||
9db1d521 | 8397 | ; |
f5905b37 | 8398 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8399 | ; |
8400 | ||
f5905b37 | 8401 | (define_expand "neg<mode>2" |
9db1d521 | 8402 | [(parallel |
2de2b3f9 AK |
8403 | [(set (match_operand:BFP 0 "register_operand") |
8404 | (neg:BFP (match_operand:BFP 1 "register_operand"))) | |
ae156f85 | 8405 | (clobber (reg:CC CC_REGNUM))])] |
2de2b3f9 | 8406 | "TARGET_HARD_FLOAT") |
9db1d521 | 8407 | |
43a09b63 | 8408 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8409 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8410 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8411 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8412 | (match_operand:BFP 2 "const0_operand" ""))) | |
8413 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8414 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8415 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8416 | "lc<xde>br\t%0,%1" |
26a89301 | 8417 | [(set_attr "op_type" "RRE") |
f5905b37 | 8418 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8419 | |
8420 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8421 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8422 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8423 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8424 | (match_operand:BFP 2 "const0_operand" ""))) | |
8425 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8426 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8427 | "lc<xde>br\t%0,%1" |
26a89301 | 8428 | [(set_attr "op_type" "RRE") |
f5905b37 | 8429 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8430 | |
85dae55a AK |
8431 | ; lcdfr |
8432 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8433 | [(set (match_operand:FP 0 "register_operand" "=f") |
8434 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8435 | "TARGET_DFP" |
85dae55a AK |
8436 | "lcdfr\t%0,%1" |
8437 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8438 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8439 | |
43a09b63 | 8440 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8441 | ; FIXME: wflcdb does not clobber cc |
2de2b3f9 | 8442 | ; FIXME: Does wflcdb ever match here? |
f5905b37 | 8443 | (define_insn "*neg<mode>2" |
2de2b3f9 AK |
8444 | [(set (match_operand:BFP 0 "register_operand" "=f,v,v") |
8445 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) | |
ae156f85 | 8446 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8447 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8448 | "@ |
8449 | lc<xde>br\t%0,%1 | |
2de2b3f9 AK |
8450 | wflcdb\t%0,%1 |
8451 | wflcsb\t%0,%1" | |
8452 | [(set_attr "op_type" "RRE,VRR,VRR") | |
8453 | (set_attr "cpu_facility" "*,vx,vxe") | |
8454 | (set_attr "type" "fsimp<mode>,*,*") | |
8455 | (set_attr "enabled" "*,<DF>,<SF>")]) | |
9db1d521 | 8456 | |
9db1d521 HP |
8457 | |
8458 | ;; | |
8459 | ;;- Absolute value instructions. | |
8460 | ;; | |
8461 | ||
8462 | ; | |
9a91a21f | 8463 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8464 | ; |
8465 | ||
26a89301 | 8466 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8467 | [(set (reg CC_REGNUM) |
26a89301 UW |
8468 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8469 | (match_operand:SI 1 "register_operand" "d") 0) | |
8470 | (const_int 32)) (const_int 32))) | |
8471 | (const_int 0))) | |
8472 | (set (match_operand:DI 0 "register_operand" "=d") | |
8473 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8474 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8475 | "lpgfr\t%0,%1" |
729e750f WG |
8476 | [(set_attr "op_type" "RRE") |
8477 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8478 | |
8479 | (define_insn "*absdi2_sign" | |
8480 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8481 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8482 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8483 | "TARGET_ZARCH" |
26a89301 | 8484 | "lpgfr\t%0,%1" |
729e750f WG |
8485 | [(set_attr "op_type" "RRE") |
8486 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8487 | |
43a09b63 | 8488 | ; lpr, lpgr |
9a91a21f | 8489 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8490 | [(set (reg CC_REGNUM) |
9a91a21f | 8491 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8492 | (const_int 0))) |
9a91a21f AS |
8493 | (set (match_operand:GPR 0 "register_operand" "=d") |
8494 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8495 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8496 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8497 | [(set_attr "op_type" "RR<E>") |
8498 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8499 | |
9381e3f1 | 8500 | ; lpr, lpgr |
9a91a21f | 8501 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8502 | [(set (reg CC_REGNUM) |
9a91a21f | 8503 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8504 | (const_int 0))) |
9a91a21f | 8505 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8506 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8507 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8508 | [(set_attr "op_type" "RR<E>") |
8509 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8510 | |
8511 | ; lpr, lpgr | |
9a91a21f AS |
8512 | (define_insn "abs<mode>2" |
8513 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8514 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8515 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8516 | "" |
9a91a21f | 8517 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8518 | [(set_attr "op_type" "RR<E>") |
8519 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8520 | |
9db1d521 | 8521 | ; |
f5905b37 | 8522 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8523 | ; |
8524 | ||
f5905b37 | 8525 | (define_expand "abs<mode>2" |
9db1d521 | 8526 | [(parallel |
7b6baae1 AK |
8527 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8528 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8529 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8530 | "TARGET_HARD_FLOAT" |
8531 | "") | |
8532 | ||
43a09b63 | 8533 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8534 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8535 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8536 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8537 | (match_operand:BFP 2 "const0_operand" ""))) | |
8538 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8539 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8540 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8541 | "lp<xde>br\t%0,%1" |
26a89301 | 8542 | [(set_attr "op_type" "RRE") |
f5905b37 | 8543 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8544 | |
8545 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8546 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8547 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8548 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8549 | (match_operand:BFP 2 "const0_operand" ""))) | |
8550 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8551 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8552 | "lp<xde>br\t%0,%1" |
26a89301 | 8553 | [(set_attr "op_type" "RRE") |
f5905b37 | 8554 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8555 | |
85dae55a AK |
8556 | ; lpdfr |
8557 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8558 | [(set (match_operand:FP 0 "register_operand" "=f") |
8559 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8560 | "TARGET_DFP" |
85dae55a AK |
8561 | "lpdfr\t%0,%1" |
8562 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8563 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8564 | |
43a09b63 | 8565 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8566 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8567 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8568 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8569 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8570 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8571 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8572 | "@ |
8573 | lp<xde>br\t%0,%1 | |
8574 | wflpdb\t%0,%1" | |
8575 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8576 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8577 | (set_attr "type" "fsimp<mode>,*") |
8578 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8579 | |
9db1d521 | 8580 | |
3ef093a8 AK |
8581 | ;; |
8582 | ;;- Negated absolute value instructions | |
8583 | ;; | |
8584 | ||
8585 | ; | |
8586 | ; Integer | |
8587 | ; | |
8588 | ||
26a89301 | 8589 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8590 | [(set (reg CC_REGNUM) |
26a89301 UW |
8591 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8592 | (match_operand:SI 1 "register_operand" "d") 0) | |
8593 | (const_int 32)) (const_int 32)))) | |
8594 | (const_int 0))) | |
8595 | (set (match_operand:DI 0 "register_operand" "=d") | |
8596 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8597 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8598 | "lngfr\t%0,%1" |
729e750f WG |
8599 | [(set_attr "op_type" "RRE") |
8600 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8601 | |
26a89301 UW |
8602 | (define_insn "*negabsdi2_sign" |
8603 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8604 | (neg:DI (abs:DI (sign_extend:DI | |
8605 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8606 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8607 | "TARGET_ZARCH" |
26a89301 | 8608 | "lngfr\t%0,%1" |
729e750f WG |
8609 | [(set_attr "op_type" "RRE") |
8610 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8611 | |
43a09b63 | 8612 | ; lnr, lngr |
9a91a21f | 8613 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8614 | [(set (reg CC_REGNUM) |
9a91a21f | 8615 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8616 | (const_int 0))) |
9a91a21f AS |
8617 | (set (match_operand:GPR 0 "register_operand" "=d") |
8618 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8619 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8620 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8621 | [(set_attr "op_type" "RR<E>") |
8622 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8623 | |
8624 | ; lnr, lngr | |
9a91a21f | 8625 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8626 | [(set (reg CC_REGNUM) |
9a91a21f | 8627 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8628 | (const_int 0))) |
9a91a21f | 8629 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8630 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8631 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8632 | [(set_attr "op_type" "RR<E>") |
8633 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8634 | |
8635 | ; lnr, lngr | |
9a91a21f AS |
8636 | (define_insn "*negabs<mode>2" |
8637 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8638 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8639 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8640 | "" |
9a91a21f | 8641 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8642 | [(set_attr "op_type" "RR<E>") |
8643 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8644 | |
3ef093a8 AK |
8645 | ; |
8646 | ; Floating point | |
8647 | ; | |
8648 | ||
43a09b63 | 8649 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8650 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8651 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8652 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8653 | (match_operand:BFP 2 "const0_operand" ""))) | |
8654 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8655 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8656 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8657 | "ln<xde>br\t%0,%1" |
26a89301 | 8658 | [(set_attr "op_type" "RRE") |
f5905b37 | 8659 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8660 | |
8661 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8662 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8663 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8664 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8665 | (match_operand:BFP 2 "const0_operand" ""))) | |
8666 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8667 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8668 | "ln<xde>br\t%0,%1" |
26a89301 | 8669 | [(set_attr "op_type" "RRE") |
f5905b37 | 8670 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8671 | |
85dae55a AK |
8672 | ; lndfr |
8673 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8674 | [(set (match_operand:FP 0 "register_operand" "=f") |
8675 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8676 | "TARGET_DFP" |
85dae55a AK |
8677 | "lndfr\t%0,%1" |
8678 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8679 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8680 | |
43a09b63 | 8681 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8682 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8683 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8684 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8685 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8686 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8687 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8688 | "@ |
8689 | ln<xde>br\t%0,%1 | |
8690 | wflndb\t%0,%1" | |
8691 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8692 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8693 | (set_attr "type" "fsimp<mode>,*") |
8694 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8695 | |
4023fb28 UW |
8696 | ;; |
8697 | ;;- Square root instructions. | |
8698 | ;; | |
8699 | ||
8700 | ; | |
f5905b37 | 8701 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8702 | ; |
8703 | ||
9381e3f1 | 8704 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8705 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8706 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8707 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8708 | "TARGET_HARD_FLOAT" |
4023fb28 | 8709 | "@ |
f61a2c7d | 8710 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8711 | sq<xde>b\t%0,%1 |
8712 | wfsqdb\t%v0,%v1" | |
8713 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8714 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 8715 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 8716 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 8717 | |
9db1d521 HP |
8718 | |
8719 | ;; | |
8720 | ;;- One complement instructions. | |
8721 | ;; | |
8722 | ||
8723 | ; | |
342cf42b | 8724 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8725 | ; |
c7453384 | 8726 | |
342cf42b | 8727 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8728 | [(parallel |
342cf42b AS |
8729 | [(set (match_operand:INT 0 "register_operand" "") |
8730 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8731 | (const_int -1))) | |
ae156f85 | 8732 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8733 | "" |
4023fb28 | 8734 | "") |
9db1d521 HP |
8735 | |
8736 | ||
ec24698e UW |
8737 | ;; |
8738 | ;; Find leftmost bit instructions. | |
8739 | ;; | |
8740 | ||
8741 | (define_expand "clzdi2" | |
8742 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8743 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8744 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 8745 | { |
d8485bdb TS |
8746 | rtx_insn *insn; |
8747 | rtx clz_equal; | |
ec24698e | 8748 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 8749 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
8750 | |
8751 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8752 | ||
8753 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8754 | ||
9381e3f1 | 8755 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8756 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8757 | |
8758 | DONE; | |
8759 | }) | |
8760 | ||
8761 | (define_insn "clztidi2" | |
8762 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8763 | (ior:TI | |
9381e3f1 WG |
8764 | (ashift:TI |
8765 | (zero_extend:TI | |
ec24698e UW |
8766 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8767 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8768 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8769 | |
ec24698e UW |
8770 | (const_int 64)) |
8771 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8772 | (clobber (reg:CC CC_REGNUM))] | |
406fde6e | 8773 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 8774 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8775 | "flogr\t%0,%1" |
8776 | [(set_attr "op_type" "RRE")]) | |
8777 | ||
8778 | ||
9db1d521 HP |
8779 | ;; |
8780 | ;;- Rotate instructions. | |
8781 | ;; | |
8782 | ||
8783 | ; | |
9a91a21f | 8784 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8785 | ; |
8786 | ||
191eb16d AK |
8787 | (define_expand "rotl<mode>3" |
8788 | [(set (match_operand:GPR 0 "register_operand" "") | |
8789 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8790 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
8cc6307c | 8791 | "" |
191eb16d | 8792 | "") |
9db1d521 | 8793 | |
43a09b63 | 8794 | ; rll, rllg |
191eb16d AK |
8795 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8796 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8797 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8798 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8cc6307c | 8799 | "" |
191eb16d | 8800 | "rll<g>\t%0,%1,<addr_style_op_ops>" |
4989e88a | 8801 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8802 | (set_attr "atype" "reg") |
191eb16d | 8803 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8804 | |
9db1d521 HP |
8805 | |
8806 | ;; | |
f337b930 | 8807 | ;;- Shift instructions. |
9db1d521 | 8808 | ;; |
9db1d521 HP |
8809 | |
8810 | ; | |
1b48c8cc | 8811 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8812 | ; Left shifts and logical right shifts |
9db1d521 | 8813 | |
1b48c8cc AS |
8814 | (define_expand "<shift><mode>3" |
8815 | [(set (match_operand:DSI 0 "register_operand" "") | |
8816 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8817 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8818 | "" |
8819 | "") | |
8820 | ||
adf22b3f | 8821 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8822 | ; sldl, srdl |
adf22b3f AK |
8823 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8824 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8825 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8826 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8827 | "!TARGET_ZARCH" |
adf22b3f | 8828 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8829 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8830 | (set_attr "atype" "reg") |
8831 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8832 | |
adf22b3f AK |
8833 | |
8834 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8835 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8836 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8837 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8838 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8839 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8840 | "" |
65b1d8ea | 8841 | "@ |
adf22b3f AK |
8842 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8843 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8844 | [(set_attr "op_type" "RS<E>,RSY") |
8845 | (set_attr "atype" "reg,reg") | |
8846 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8847 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8848 | |
9db1d521 | 8849 | ; |
1b48c8cc | 8850 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8851 | ; Arithmetic right shifts |
9db1d521 | 8852 | |
1b48c8cc | 8853 | (define_expand "ashr<mode>3" |
9db1d521 | 8854 | [(parallel |
1b48c8cc AS |
8855 | [(set (match_operand:DSI 0 "register_operand" "") |
8856 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8857 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8858 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8859 | "" |
8860 | "") | |
8861 | ||
a9fcf821 AK |
8862 | ; FIXME: The number of alternatives is doubled here to match the fix |
8863 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8864 | ; The right fix should be to support match_scratch in the output | |
8865 | ; pattern of a define_subst. | |
8866 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8867 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8868 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8869 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8870 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8871 | "!TARGET_ZARCH" |
65b1d8ea | 8872 | "@ |
a9fcf821 AK |
8873 | srda\t%0,<addr_style_op_cc_ops> |
8874 | srda\t%0,<addr_style_op_cc_ops>" | |
8875 | [(set_attr "op_type" "RS") | |
8876 | (set_attr "atype" "reg")]) | |
ecbe845e | 8877 | |
ecbe845e | 8878 | |
43a09b63 | 8879 | ; sra, srag |
a9fcf821 AK |
8880 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8881 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8882 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8883 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8884 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8885 | "" |
65b1d8ea | 8886 | "@ |
a9fcf821 AK |
8887 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8888 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8889 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8890 | (set_attr "atype" "reg") |
01496eca | 8891 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8892 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8893 | |
9db1d521 | 8894 | |
9db1d521 HP |
8895 | ;; |
8896 | ;; Branch instruction patterns. | |
8897 | ;; | |
8898 | ||
f90b7a5a | 8899 | (define_expand "cbranch<mode>4" |
fa77b251 | 8900 | [(set (pc) |
f90b7a5a PB |
8901 | (if_then_else (match_operator 0 "comparison_operator" |
8902 | [(match_operand:GPR 1 "register_operand" "") | |
8903 | (match_operand:GPR 2 "general_operand" "")]) | |
8904 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8905 | (pc)))] |
ba956982 | 8906 | "" |
f90b7a5a PB |
8907 | "s390_emit_jump (operands[3], |
8908 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8909 | DONE;") | |
8910 | ||
8911 | (define_expand "cbranch<mode>4" | |
8912 | [(set (pc) | |
8913 | (if_then_else (match_operator 0 "comparison_operator" | |
8914 | [(match_operand:FP 1 "register_operand" "") | |
8915 | (match_operand:FP 2 "general_operand" "")]) | |
8916 | (label_ref (match_operand 3 "" "")) | |
8917 | (pc)))] | |
8918 | "TARGET_HARD_FLOAT" | |
8919 | "s390_emit_jump (operands[3], | |
8920 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8921 | DONE;") | |
8922 | ||
8923 | (define_expand "cbranchcc4" | |
8924 | [(set (pc) | |
de6fba39 | 8925 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8926 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8927 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8928 | (label_ref (match_operand 3 "" "")) |
8929 | (pc)))] | |
de6fba39 UW |
8930 | "" |
8931 | "") | |
ba956982 | 8932 | |
9db1d521 HP |
8933 | |
8934 | ;; | |
8935 | ;;- Conditional jump instructions. | |
8936 | ;; | |
8937 | ||
6590e19a UW |
8938 | (define_insn "*cjump_64" |
8939 | [(set (pc) | |
8940 | (if_then_else | |
5a3fe9b6 AK |
8941 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8942 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8943 | (label_ref (match_operand 0 "" "")) |
8944 | (pc)))] | |
8cc6307c | 8945 | "" |
9db1d521 | 8946 | { |
13e58269 | 8947 | if (get_attr_length (insn) == 4) |
d40c829f | 8948 | return "j%C1\t%l0"; |
6590e19a | 8949 | else |
d40c829f | 8950 | return "jg%C1\t%l0"; |
6590e19a UW |
8951 | } |
8952 | [(set_attr "op_type" "RI") | |
8953 | (set_attr "type" "branch") | |
8954 | (set (attr "length") | |
8955 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8956 | (const_int 4) (const_int 6)))]) | |
8957 | ||
f314b9b1 | 8958 | (define_insn "*cjump_long" |
6590e19a UW |
8959 | [(set (pc) |
8960 | (if_then_else | |
ae156f85 | 8961 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8962 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8963 | (pc)))] |
84b4c7b5 | 8964 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
8965 | { |
8966 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8967 | return "b%C1r\t%0"; |
f314b9b1 | 8968 | else |
d40c829f | 8969 | return "b%C1\t%a0"; |
10bbf137 | 8970 | } |
c7453384 | 8971 | [(set (attr "op_type") |
f314b9b1 UW |
8972 | (if_then_else (match_operand 0 "register_operand" "") |
8973 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
8974 | (set (attr "mnemonic") |
8975 | (if_then_else (match_operand 0 "register_operand" "") | |
8976 | (const_string "bcr") (const_string "bc"))) | |
6590e19a | 8977 | (set_attr "type" "branch") |
077dab3b | 8978 | (set_attr "atype" "agen")]) |
9db1d521 | 8979 | |
177bc204 RS |
8980 | ;; A conditional return instruction. |
8981 | (define_insn "*c<code>" | |
8982 | [(set (pc) | |
8983 | (if_then_else | |
8984 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8985 | (ANY_RETURN) | |
8986 | (pc)))] | |
8987 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
8988 | { |
8989 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
8990 | { | |
8991 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
8992 | INVALID_REGNUM, | |
8993 | operands[0], | |
8994 | s390_indirect_branch_type_return); | |
8995 | return ""; | |
8996 | } | |
8997 | else | |
8998 | return "b%C0r\t%%r14"; | |
8999 | } | |
9000 | [(set (attr "op_type") | |
9001 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9002 | (const_string "RIL") | |
9003 | (const_string "RR"))) | |
9004 | (set (attr "mnemonic") | |
9005 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9006 | (const_string "brcl") | |
9007 | (const_string "bcr"))) | |
177bc204 RS |
9008 | (set_attr "type" "jsr") |
9009 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
9010 | |
9011 | ;; | |
9012 | ;;- Negated conditional jump instructions. | |
9013 | ;; | |
9014 | ||
6590e19a UW |
9015 | (define_insn "*icjump_64" |
9016 | [(set (pc) | |
9017 | (if_then_else | |
ae156f85 | 9018 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9019 | (pc) |
9020 | (label_ref (match_operand 0 "" ""))))] | |
8cc6307c | 9021 | "" |
c7453384 | 9022 | { |
13e58269 | 9023 | if (get_attr_length (insn) == 4) |
d40c829f | 9024 | return "j%D1\t%l0"; |
6590e19a | 9025 | else |
d40c829f | 9026 | return "jg%D1\t%l0"; |
6590e19a UW |
9027 | } |
9028 | [(set_attr "op_type" "RI") | |
9029 | (set_attr "type" "branch") | |
9030 | (set (attr "length") | |
9031 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9032 | (const_int 4) (const_int 6)))]) | |
9033 | ||
f314b9b1 | 9034 | (define_insn "*icjump_long" |
6590e19a UW |
9035 | [(set (pc) |
9036 | (if_then_else | |
ae156f85 | 9037 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 9038 | (pc) |
4fe6dea8 | 9039 | (match_operand 0 "address_operand" "ZQZR")))] |
84b4c7b5 | 9040 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9041 | { |
9042 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9043 | return "b%D1r\t%0"; |
f314b9b1 | 9044 | else |
d40c829f | 9045 | return "b%D1\t%a0"; |
10bbf137 | 9046 | } |
c7453384 | 9047 | [(set (attr "op_type") |
f314b9b1 UW |
9048 | (if_then_else (match_operand 0 "register_operand" "") |
9049 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9050 | (set (attr "mnemonic") |
9051 | (if_then_else (match_operand 0 "register_operand" "") | |
9052 | (const_string "bcr") (const_string "bc"))) | |
077dab3b HP |
9053 | (set_attr "type" "branch") |
9054 | (set_attr "atype" "agen")]) | |
9db1d521 | 9055 | |
4456530d HP |
9056 | ;; |
9057 | ;;- Trap instructions. | |
9058 | ;; | |
9059 | ||
9060 | (define_insn "trap" | |
9061 | [(trap_if (const_int 1) (const_int 0))] | |
9062 | "" | |
d40c829f | 9063 | "j\t.+2" |
6590e19a | 9064 | [(set_attr "op_type" "RI") |
077dab3b | 9065 | (set_attr "type" "branch")]) |
4456530d | 9066 | |
f90b7a5a PB |
9067 | (define_expand "ctrap<mode>4" |
9068 | [(trap_if (match_operator 0 "comparison_operator" | |
9069 | [(match_operand:GPR 1 "register_operand" "") | |
9070 | (match_operand:GPR 2 "general_operand" "")]) | |
9071 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 9072 | "" |
f90b7a5a PB |
9073 | { |
9074 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9075 | operands[1], operands[2]); | |
9076 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9077 | DONE; | |
9078 | }) | |
9079 | ||
9080 | (define_expand "ctrap<mode>4" | |
9081 | [(trap_if (match_operator 0 "comparison_operator" | |
9082 | [(match_operand:FP 1 "register_operand" "") | |
9083 | (match_operand:FP 2 "general_operand" "")]) | |
9084 | (match_operand 3 "const0_operand" ""))] | |
9085 | "" | |
9086 | { | |
9087 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9088 | operands[1], operands[2]); | |
9089 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9090 | DONE; | |
9091 | }) | |
4456530d | 9092 | |
f90b7a5a PB |
9093 | (define_insn "condtrap" |
9094 | [(trap_if (match_operator 0 "s390_comparison" | |
9095 | [(match_operand 1 "cc_reg_operand" "c") | |
9096 | (const_int 0)]) | |
4456530d HP |
9097 | (const_int 0))] |
9098 | "" | |
d40c829f | 9099 | "j%C0\t.+2"; |
077dab3b HP |
9100 | [(set_attr "op_type" "RI") |
9101 | (set_attr "type" "branch")]) | |
9db1d521 | 9102 | |
963fc8d0 AK |
9103 | ; crt, cgrt, cit, cgit |
9104 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9105 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9106 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9107 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9108 | (const_int 0))] | |
9109 | "TARGET_Z10" | |
9110 | "@ | |
9111 | c<g>rt%C0\t%1,%2 | |
9112 | c<g>it%C0\t%1,%h2" | |
9113 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9114 | (set_attr "type" "branch") |
729e750f | 9115 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9116 | |
22ac2c2f | 9117 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9118 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9119 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9120 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9121 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9122 | (const_int 0))] |
9123 | "TARGET_Z10" | |
9124 | "@ | |
9125 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9126 | cl<gf>it%C0\t%1,%x2 |
9127 | cl<g>t%C0\t%1,%2" | |
9128 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9129 | (set_attr "type" "branch") | |
9130 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9131 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9132 | ||
9133 | ; lat, lgat | |
9134 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9135 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9136 | (const_int 0)) |
9137 | (const_int 0)) | |
9138 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9139 | (match_dup 0))] | |
9140 | "TARGET_ZEC12" | |
9141 | "l<g>at\t%1,%0" | |
9142 | [(set_attr "op_type" "RXY")]) | |
9143 | ||
963fc8d0 | 9144 | |
9db1d521 | 9145 | ;; |
0a3bdf9d | 9146 | ;;- Loop instructions. |
9db1d521 | 9147 | ;; |
0a3bdf9d UW |
9148 | ;; This is all complicated by the fact that since this is a jump insn |
9149 | ;; we must handle our own output reloads. | |
c7453384 | 9150 | |
f1149235 AK |
9151 | ;; branch on index |
9152 | ||
9153 | ; This splitter will be matched by combine and has to add the 2 moves | |
9154 | ; necessary to load the compare and the increment values into a | |
9155 | ; register pair as needed by brxle. | |
9156 | ||
9157 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9158 | [(set (pc) | |
9159 | (if_then_else | |
9160 | (match_operator 6 "s390_brx_operator" | |
9161 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9162 | (match_operand:GPR 2 "general_operand" "")) | |
9163 | (match_operand:GPR 3 "register_operand" "")]) | |
9164 | (label_ref (match_operand 0 "" "")) | |
9165 | (pc))) | |
9166 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9167 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9168 | (clobber (match_scratch:GPR 5 ""))] | |
8cc6307c | 9169 | "" |
f1149235 AK |
9170 | "#" |
9171 | "!reload_completed && !reload_in_progress" | |
9172 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9173 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9174 | (parallel [(set (pc) | |
9175 | (if_then_else | |
9176 | (match_op_dup 6 | |
9177 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9178 | (match_dup 8)]) | |
9179 | (label_ref (match_dup 0)) | |
9180 | (pc))) | |
9181 | (set (match_dup 4) | |
9182 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9183 | (clobber (match_dup 5)) | |
9184 | (clobber (reg:CC CC_REGNUM))])] | |
9185 | { | |
9186 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9187 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9188 | gen_highpart (word_mode, dreg)); | |
9189 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9190 | gen_lowpart (word_mode, dreg)); | |
9191 | }) | |
9192 | ||
9193 | ; brxlg, brxhg | |
9194 | ||
9195 | (define_insn_and_split "*brxg_64bit" | |
9196 | [(set (pc) | |
9197 | (if_then_else | |
9198 | (match_operator 5 "s390_brx_operator" | |
9199 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9200 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9201 | (subreg:DI (match_dup 2) 8)]) | |
9202 | (label_ref (match_operand 0 "" "")) | |
9203 | (pc))) | |
9204 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9205 | (plus:DI (match_dup 1) | |
9206 | (subreg:DI (match_dup 2) 0))) | |
9207 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9208 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9209 | "TARGET_ZARCH" |
f1149235 AK |
9210 | { |
9211 | if (which_alternative != 0) | |
9212 | return "#"; | |
9213 | else if (get_attr_length (insn) == 6) | |
9214 | return "brx%E5g\t%1,%2,%l0"; | |
9215 | else | |
9216 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9217 | } | |
9218 | "&& reload_completed | |
9219 | && (!REG_P (operands[3]) | |
9220 | || !rtx_equal_p (operands[1], operands[3]))" | |
9221 | [(set (match_dup 4) (match_dup 1)) | |
9222 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9223 | (clobber (reg:CC CC_REGNUM))]) | |
9224 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9225 | (set (match_dup 3) (match_dup 4)) | |
9226 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9227 | (label_ref (match_dup 0)) | |
9228 | (pc)))] | |
9229 | "" | |
9230 | [(set_attr "op_type" "RIE") | |
9231 | (set_attr "type" "branch") | |
9232 | (set (attr "length") | |
9233 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9234 | (const_int 6) (const_int 16)))]) | |
9235 | ||
9236 | ; brxle, brxh | |
9237 | ||
9238 | (define_insn_and_split "*brx_64bit" | |
9239 | [(set (pc) | |
9240 | (if_then_else | |
9241 | (match_operator 5 "s390_brx_operator" | |
9242 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9243 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9244 | (subreg:SI (match_dup 2) 12)]) | |
9245 | (label_ref (match_operand 0 "" "")) | |
9246 | (pc))) | |
9247 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9248 | (plus:SI (match_dup 1) | |
9249 | (subreg:SI (match_dup 2) 4))) | |
9250 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9251 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9252 | "TARGET_ZARCH" |
f1149235 AK |
9253 | { |
9254 | if (which_alternative != 0) | |
9255 | return "#"; | |
9256 | else if (get_attr_length (insn) == 6) | |
9257 | return "brx%C5\t%1,%2,%l0"; | |
9258 | else | |
9259 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9260 | } | |
9261 | "&& reload_completed | |
9262 | && (!REG_P (operands[3]) | |
9263 | || !rtx_equal_p (operands[1], operands[3]))" | |
9264 | [(set (match_dup 4) (match_dup 1)) | |
9265 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9266 | (clobber (reg:CC CC_REGNUM))]) | |
9267 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9268 | (set (match_dup 3) (match_dup 4)) | |
9269 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9270 | (label_ref (match_dup 0)) | |
9271 | (pc)))] | |
9272 | "" | |
9273 | [(set_attr "op_type" "RSI") | |
9274 | (set_attr "type" "branch") | |
9275 | (set (attr "length") | |
9276 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9277 | (const_int 6) (const_int 14)))]) | |
9278 | ||
9279 | ; brxle, brxh | |
9280 | ||
9281 | (define_insn_and_split "*brx_31bit" | |
9282 | [(set (pc) | |
9283 | (if_then_else | |
9284 | (match_operator 5 "s390_brx_operator" | |
9285 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9286 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9287 | (subreg:SI (match_dup 2) 4)]) | |
9288 | (label_ref (match_operand 0 "" "")) | |
9289 | (pc))) | |
9290 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9291 | (plus:SI (match_dup 1) | |
9292 | (subreg:SI (match_dup 2) 0))) | |
9293 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9294 | (clobber (reg:CC CC_REGNUM))] | |
8cc6307c | 9295 | "!TARGET_ZARCH" |
f1149235 AK |
9296 | { |
9297 | if (which_alternative != 0) | |
9298 | return "#"; | |
9299 | else if (get_attr_length (insn) == 6) | |
9300 | return "brx%C5\t%1,%2,%l0"; | |
9301 | else | |
9302 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9303 | } | |
9304 | "&& reload_completed | |
9305 | && (!REG_P (operands[3]) | |
9306 | || !rtx_equal_p (operands[1], operands[3]))" | |
9307 | [(set (match_dup 4) (match_dup 1)) | |
9308 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9309 | (clobber (reg:CC CC_REGNUM))]) | |
9310 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9311 | (set (match_dup 3) (match_dup 4)) | |
9312 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9313 | (label_ref (match_dup 0)) | |
9314 | (pc)))] | |
9315 | "" | |
9316 | [(set_attr "op_type" "RSI") | |
9317 | (set_attr "type" "branch") | |
9318 | (set (attr "length") | |
9319 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9320 | (const_int 6) (const_int 14)))]) | |
9321 | ||
9322 | ||
9323 | ;; branch on count | |
9324 | ||
0a3bdf9d UW |
9325 | (define_expand "doloop_end" |
9326 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9327 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9328 | "" |
0a3bdf9d | 9329 | { |
8cc6307c | 9330 | if (GET_MODE (operands[0]) == SImode) |
1d0216c8 | 9331 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9332 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9333 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9334 | else |
9335 | FAIL; | |
9336 | ||
9337 | DONE; | |
10bbf137 | 9338 | }) |
0a3bdf9d | 9339 | |
6590e19a | 9340 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9341 | [(set (pc) |
9342 | (if_then_else | |
7e665d18 | 9343 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9344 | (const_int 1)) |
9345 | (label_ref (match_operand 0 "" "")) | |
9346 | (pc))) | |
7e665d18 | 9347 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9348 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9349 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9350 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 9351 | "" |
0a3bdf9d UW |
9352 | { |
9353 | if (which_alternative != 0) | |
10bbf137 | 9354 | return "#"; |
0a3bdf9d | 9355 | else if (get_attr_length (insn) == 4) |
d40c829f | 9356 | return "brct\t%1,%l0"; |
6590e19a | 9357 | else |
545d16ff | 9358 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9359 | } |
9360 | "&& reload_completed | |
9361 | && (! REG_P (operands[2]) | |
9362 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9363 | [(set (match_dup 3) (match_dup 1)) |
9364 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9365 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9366 | (const_int 0))) | |
9367 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9368 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9369 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9370 | (label_ref (match_dup 0)) |
9371 | (pc)))] | |
9372 | "" | |
9373 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9374 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9375 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9376 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9377 | (set_attr "type" "branch") |
9378 | (set (attr "length") | |
9379 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9380 | (const_int 4) (const_int 10)))]) | |
9381 | ||
6590e19a | 9382 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9383 | [(set (pc) |
9384 | (if_then_else | |
7e665d18 | 9385 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9386 | (const_int 1)) |
9387 | (label_ref (match_operand 0 "" "")) | |
9388 | (pc))) | |
7e665d18 | 9389 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9390 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9391 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9392 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9393 | "TARGET_ZARCH" |
0a3bdf9d UW |
9394 | { |
9395 | if (which_alternative != 0) | |
10bbf137 | 9396 | return "#"; |
0a3bdf9d | 9397 | else if (get_attr_length (insn) == 4) |
d40c829f | 9398 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9399 | else |
545d16ff | 9400 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9401 | } |
6590e19a | 9402 | "&& reload_completed |
0a3bdf9d UW |
9403 | && (! REG_P (operands[2]) |
9404 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9405 | [(set (match_dup 3) (match_dup 1)) |
9406 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9407 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9408 | (const_int 0))) | |
9409 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9410 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9411 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9412 | (label_ref (match_dup 0)) |
0a3bdf9d | 9413 | (pc)))] |
6590e19a UW |
9414 | "" |
9415 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9416 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9417 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9418 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9419 | (set_attr "type" "branch") |
9420 | (set (attr "length") | |
9421 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9422 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9423 | |
9424 | ;; | |
9425 | ;;- Unconditional jump instructions. | |
9426 | ;; | |
9427 | ||
9428 | ; | |
9429 | ; jump instruction pattern(s). | |
9430 | ; | |
9431 | ||
6590e19a UW |
9432 | (define_expand "jump" |
9433 | [(match_operand 0 "" "")] | |
9db1d521 | 9434 | "" |
6590e19a UW |
9435 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9436 | ||
9437 | (define_insn "*jump64" | |
9438 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8cc6307c | 9439 | "" |
9db1d521 | 9440 | { |
13e58269 | 9441 | if (get_attr_length (insn) == 4) |
d40c829f | 9442 | return "j\t%l0"; |
6590e19a | 9443 | else |
d40c829f | 9444 | return "jg\t%l0"; |
6590e19a UW |
9445 | } |
9446 | [(set_attr "op_type" "RI") | |
9447 | (set_attr "type" "branch") | |
9448 | (set (attr "length") | |
9449 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9450 | (const_int 4) (const_int 6)))]) | |
9451 | ||
9db1d521 HP |
9452 | ; |
9453 | ; indirect-jump instruction pattern(s). | |
9454 | ; | |
9455 | ||
2841f550 AK |
9456 | (define_expand "indirect_jump" |
9457 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9458 | "" |
f314b9b1 | 9459 | { |
2841f550 AK |
9460 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9461 | ; | |
e9e8efc9 | 9462 | else if (TARGET_Z14 |
2841f550 AK |
9463 | && GET_MODE (operands[0]) == Pmode |
9464 | && memory_operand (operands[0], Pmode)) | |
9465 | ; | |
f314b9b1 | 9466 | else |
2841f550 | 9467 | operands[0] = force_reg (Pmode, operands[0]); |
84b4c7b5 AK |
9468 | |
9469 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9470 | { | |
9471 | operands[0] = force_reg (Pmode, operands[0]); | |
9472 | if (TARGET_CPU_Z10) | |
9473 | { | |
9474 | if (TARGET_64BIT) | |
9475 | emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); | |
9476 | else | |
9477 | emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); | |
9478 | } | |
9479 | else | |
9480 | { | |
9481 | if (TARGET_64BIT) | |
9482 | emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); | |
9483 | else | |
9484 | emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); | |
9485 | } | |
9486 | DONE; | |
9487 | } | |
9488 | ||
9489 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9490 | { | |
9491 | operands[0] = force_reg (Pmode, operands[0]); | |
9492 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9493 | if (TARGET_CPU_Z10) | |
9494 | { | |
9495 | if (TARGET_64BIT) | |
9496 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], | |
9497 | label_ref)); | |
9498 | else | |
9499 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], | |
9500 | label_ref)); | |
9501 | } | |
9502 | else | |
9503 | { | |
9504 | if (TARGET_64BIT) | |
9505 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], | |
9506 | label_ref, | |
9507 | force_reg (Pmode, label_ref))); | |
9508 | else | |
9509 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], | |
9510 | label_ref, | |
9511 | force_reg (Pmode, label_ref))); | |
9512 | } | |
9513 | DONE; | |
9514 | } | |
2841f550 AK |
9515 | }) |
9516 | ||
9517 | (define_insn "*indirect_jump" | |
9518 | [(set (pc) | |
84b4c7b5 AK |
9519 | (match_operand 0 "address_operand" "ZR"))] |
9520 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9521 | { | |
9522 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9523 | return "br\t%0"; | |
9524 | else | |
9525 | return "b\t%a0"; | |
9526 | } | |
9527 | [(set (attr "op_type") | |
9528 | (if_then_else (match_operand 0 "register_operand" "") | |
9529 | (const_string "RR") (const_string "RX"))) | |
9530 | (set (attr "mnemonic") | |
9531 | (if_then_else (match_operand 0 "register_operand" "") | |
9532 | (const_string "br") (const_string "b"))) | |
2841f550 | 9533 | (set_attr "type" "branch") |
84b4c7b5 AK |
9534 | (set_attr "atype" "agen")]) |
9535 | ||
9536 | (define_insn "indirect_jump_via_thunk<mode>_z10" | |
9537 | [(set (pc) | |
9538 | (match_operand:P 0 "register_operand" "a"))] | |
9539 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9540 | && TARGET_CPU_Z10" | |
9541 | { | |
9542 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9543 | INVALID_REGNUM, | |
9544 | NULL_RTX, | |
9545 | s390_indirect_branch_type_jump); | |
9546 | return ""; | |
9547 | } | |
9548 | [(set_attr "op_type" "RIL") | |
9549 | (set_attr "mnemonic" "jg") | |
9550 | (set_attr "type" "branch") | |
9551 | (set_attr "atype" "agen")]) | |
9552 | ||
9553 | (define_insn "indirect_jump_via_thunk<mode>" | |
9554 | [(set (pc) | |
9555 | (match_operand:P 0 "register_operand" " a")) | |
9556 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9557 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9558 | && !TARGET_CPU_Z10" | |
9559 | { | |
9560 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9561 | INVALID_REGNUM, | |
9562 | NULL_RTX, | |
9563 | s390_indirect_branch_type_jump); | |
9564 | return ""; | |
9565 | } | |
9566 | [(set_attr "op_type" "RIL") | |
9567 | (set_attr "mnemonic" "jg") | |
9568 | (set_attr "type" "branch") | |
9569 | (set_attr "atype" "agen")]) | |
9570 | ||
9571 | ||
9572 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9573 | ; from mark_jump_label. Without this the label_ref would become the | |
9574 | ; ONLY jump target of that jump breaking the control flow graph. | |
9575 | (define_insn "indirect_jump_via_inlinethunk<mode>_z10" | |
9576 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9577 | (const_int 0) | |
9578 | (const_int 0)) | |
9579 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9580 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9581 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9582 | && TARGET_CPU_Z10" | |
9583 | { | |
9584 | s390_indirect_branch_via_inline_thunk (operands[1]); | |
9585 | return ""; | |
9586 | } | |
9587 | [(set_attr "op_type" "RIL") | |
9588 | (set_attr "type" "branch") | |
9589 | (set_attr "length" "10")]) | |
9590 | ||
9591 | (define_insn "indirect_jump_via_inlinethunk<mode>" | |
9592 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9593 | (const_int 0) | |
9594 | (const_int 0)) | |
9595 | (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9596 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9597 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9598 | && !TARGET_CPU_Z10" | |
9599 | { | |
9600 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9601 | return ""; | |
9602 | } | |
9603 | [(set_attr "op_type" "RX") | |
9604 | (set_attr "type" "branch") | |
9605 | (set_attr "length" "8")]) | |
2841f550 AK |
9606 | |
9607 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9608 | ; checked against address constraints like ZR above. So make this a | |
9609 | ; separate pattern for now. | |
9610 | (define_insn "*indirect2_jump" | |
9611 | [(set (pc) | |
9612 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
84b4c7b5 | 9613 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
2841f550 AK |
9614 | "@ |
9615 | br\t%0 | |
9616 | bi\t%0" | |
9617 | [(set_attr "op_type" "RR,RXY") | |
9618 | (set_attr "type" "branch") | |
9619 | (set_attr "atype" "agen") | |
e9e8efc9 | 9620 | (set_attr "cpu_facility" "*,z14")]) |
9db1d521 HP |
9621 | |
9622 | ; | |
f314b9b1 | 9623 | ; casesi instruction pattern(s). |
9db1d521 HP |
9624 | ; |
9625 | ||
84b4c7b5 AK |
9626 | (define_expand "casesi_jump" |
9627 | [(parallel | |
9628 | [(set (pc) (match_operand 0 "address_operand")) | |
9629 | (use (label_ref (match_operand 1 "")))])] | |
9db1d521 | 9630 | "" |
84b4c7b5 AK |
9631 | { |
9632 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9633 | { | |
9634 | operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); | |
9635 | ||
9636 | if (TARGET_CPU_Z10) | |
9637 | { | |
9638 | if (TARGET_64BIT) | |
9639 | emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], | |
9640 | operands[1])); | |
9641 | else | |
9642 | emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], | |
9643 | operands[1])); | |
9644 | } | |
9645 | else | |
9646 | { | |
9647 | if (TARGET_64BIT) | |
9648 | emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], | |
9649 | operands[1])); | |
9650 | else | |
9651 | emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], | |
9652 | operands[1])); | |
9653 | } | |
9654 | DONE; | |
9655 | } | |
9656 | ||
9657 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9658 | { | |
9659 | operands[0] = force_reg (Pmode, operands[0]); | |
9660 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9661 | if (TARGET_CPU_Z10) | |
9662 | { | |
9663 | if (TARGET_64BIT) | |
9664 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], | |
9665 | operands[1], | |
9666 | label_ref)); | |
9667 | else | |
9668 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], | |
9669 | operands[1], | |
9670 | label_ref)); | |
9671 | } | |
9672 | else | |
9673 | { | |
9674 | if (TARGET_64BIT) | |
9675 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], | |
9676 | operands[1], | |
9677 | label_ref, | |
9678 | force_reg (Pmode, label_ref))); | |
9679 | else | |
9680 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], | |
9681 | operands[1], | |
9682 | label_ref, | |
9683 | force_reg (Pmode, label_ref))); | |
9684 | } | |
9685 | DONE; | |
9686 | } | |
9687 | }) | |
9688 | ||
9689 | (define_insn "*casesi_jump" | |
9690 | [(set (pc) (match_operand 0 "address_operand" "ZR")) | |
9691 | (use (label_ref (match_operand 1 "" "")))] | |
9692 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9db1d521 | 9693 | { |
f314b9b1 | 9694 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9695 | return "br\t%0"; |
f314b9b1 | 9696 | else |
d40c829f | 9697 | return "b\t%a0"; |
10bbf137 | 9698 | } |
c7453384 | 9699 | [(set (attr "op_type") |
f314b9b1 UW |
9700 | (if_then_else (match_operand 0 "register_operand" "") |
9701 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9702 | (set (attr "mnemonic") |
9703 | (if_then_else (match_operand 0 "register_operand" "") | |
9704 | (const_string "br") (const_string "b"))) | |
9705 | (set_attr "type" "branch") | |
9706 | (set_attr "atype" "agen")]) | |
9707 | ||
9708 | (define_insn "casesi_jump_via_thunk<mode>_z10" | |
9709 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9710 | (use (label_ref (match_operand 1 "" "")))] | |
9711 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9712 | && TARGET_CPU_Z10" | |
9713 | { | |
9714 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9715 | INVALID_REGNUM, | |
9716 | NULL_RTX, | |
9717 | s390_indirect_branch_type_jump); | |
9718 | return ""; | |
9719 | } | |
9720 | [(set_attr "op_type" "RIL") | |
9721 | (set_attr "mnemonic" "jg") | |
9722 | (set_attr "type" "branch") | |
9723 | (set_attr "atype" "agen")]) | |
9724 | ||
9725 | (define_insn "casesi_jump_via_thunk<mode>" | |
9726 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9727 | (use (label_ref (match_operand 1 "" ""))) | |
9728 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9729 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9730 | && !TARGET_CPU_Z10" | |
9731 | { | |
9732 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9733 | INVALID_REGNUM, | |
9734 | NULL_RTX, | |
9735 | s390_indirect_branch_type_jump); | |
9736 | return ""; | |
9737 | } | |
9738 | [(set_attr "op_type" "RIL") | |
9739 | (set_attr "mnemonic" "jg") | |
077dab3b HP |
9740 | (set_attr "type" "branch") |
9741 | (set_attr "atype" "agen")]) | |
9db1d521 | 9742 | |
84b4c7b5 AK |
9743 | |
9744 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9745 | ; from mark_jump_label. Without this the label_ref would become the | |
9746 | ; ONLY jump target of that jump breaking the control flow graph. | |
9747 | (define_insn "casesi_jump_via_inlinethunk<mode>_z10" | |
9748 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9749 | (const_int 0) | |
9750 | (const_int 0)) | |
9751 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9752 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9753 | (use (label_ref (match_operand 1 "" "")))] | |
9754 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9755 | && TARGET_CPU_Z10" | |
9756 | { | |
9757 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9758 | return ""; | |
9759 | } | |
9760 | [(set_attr "op_type" "RIL") | |
9761 | (set_attr "type" "cs") | |
9762 | (set_attr "length" "10")]) | |
9763 | ||
9764 | (define_insn "casesi_jump_via_inlinethunk<mode>" | |
9765 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9766 | (const_int 0) | |
9767 | (const_int 0)) | |
9768 | (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9769 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9770 | (use (label_ref (match_operand 1 "" "")))] | |
9771 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9772 | && !TARGET_CPU_Z10" | |
9773 | { | |
9774 | s390_indirect_branch_via_inline_thunk (operands[3]); | |
9775 | return ""; | |
9776 | } | |
9777 | [(set_attr "op_type" "RX") | |
9778 | (set_attr "type" "cs") | |
9779 | (set_attr "length" "8")]) | |
9780 | ||
f314b9b1 UW |
9781 | (define_expand "casesi" |
9782 | [(match_operand:SI 0 "general_operand" "") | |
9783 | (match_operand:SI 1 "general_operand" "") | |
9784 | (match_operand:SI 2 "general_operand" "") | |
9785 | (label_ref (match_operand 3 "" "")) | |
9786 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9787 | "" |
f314b9b1 UW |
9788 | { |
9789 | rtx index = gen_reg_rtx (SImode); | |
9790 | rtx base = gen_reg_rtx (Pmode); | |
9791 | rtx target = gen_reg_rtx (Pmode); | |
9792 | ||
9793 | emit_move_insn (index, operands[0]); | |
9794 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9795 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9796 | operands[4]); |
f314b9b1 UW |
9797 | |
9798 | if (Pmode != SImode) | |
9799 | index = convert_to_mode (Pmode, index, 1); | |
9800 | if (GET_CODE (index) != REG) | |
9801 | index = copy_to_mode_reg (Pmode, index); | |
9802 | ||
9803 | if (TARGET_64BIT) | |
9804 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9805 | else | |
a556fd39 | 9806 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9807 | |
f314b9b1 UW |
9808 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9809 | ||
542a8afa | 9810 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9811 | emit_move_insn (target, index); |
9812 | ||
9813 | if (flag_pic) | |
9814 | target = gen_rtx_PLUS (Pmode, base, target); | |
9815 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9816 | ||
9817 | DONE; | |
10bbf137 | 9818 | }) |
9db1d521 HP |
9819 | |
9820 | ||
9821 | ;; | |
9822 | ;;- Jump to subroutine. | |
9823 | ;; | |
9824 | ;; | |
9825 | ||
9826 | ; | |
9827 | ; untyped call instruction pattern(s). | |
9828 | ; | |
9829 | ||
9830 | ;; Call subroutine returning any type. | |
9831 | (define_expand "untyped_call" | |
9832 | [(parallel [(call (match_operand 0 "" "") | |
9833 | (const_int 0)) | |
9834 | (match_operand 1 "" "") | |
9835 | (match_operand 2 "" "")])] | |
9836 | "" | |
9db1d521 HP |
9837 | { |
9838 | int i; | |
9839 | ||
9840 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9841 | ||
9842 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9843 | { | |
9844 | rtx set = XVECEXP (operands[2], 0, i); | |
9845 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9846 | } | |
9847 | ||
9848 | /* The optimizer does not know that the call sets the function value | |
9849 | registers we stored in the result block. We avoid problems by | |
9850 | claiming that all hard registers are used and clobbered at this | |
9851 | point. */ | |
9852 | emit_insn (gen_blockage ()); | |
9853 | ||
9854 | DONE; | |
10bbf137 | 9855 | }) |
9db1d521 HP |
9856 | |
9857 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9858 | ;; all of memory. This blocks insns from being moved across this point. | |
9859 | ||
9860 | (define_insn "blockage" | |
10bbf137 | 9861 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9862 | "" |
4023fb28 | 9863 | "" |
d5869ca0 UW |
9864 | [(set_attr "type" "none") |
9865 | (set_attr "length" "0")]) | |
4023fb28 | 9866 | |
9db1d521 | 9867 | ; |
ed9676cf | 9868 | ; sibcall patterns |
9db1d521 HP |
9869 | ; |
9870 | ||
ed9676cf | 9871 | (define_expand "sibcall" |
44b8152b | 9872 | [(call (match_operand 0 "" "") |
ed9676cf | 9873 | (match_operand 1 "" ""))] |
9db1d521 | 9874 | "" |
9db1d521 | 9875 | { |
ed9676cf AK |
9876 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9877 | DONE; | |
9878 | }) | |
9db1d521 | 9879 | |
ed9676cf | 9880 | (define_insn "*sibcall_br" |
ae156f85 | 9881 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9882 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9883 | "SIBLING_CALL_P (insn) |
ed9676cf | 9884 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
84b4c7b5 AK |
9885 | { |
9886 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
9887 | { | |
9888 | gcc_assert (TARGET_CPU_Z10); | |
9889 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
9890 | INVALID_REGNUM, | |
9891 | NULL_RTX, | |
9892 | s390_indirect_branch_type_call); | |
9893 | return ""; | |
9894 | } | |
9895 | else | |
9896 | return "br\t%%r1"; | |
9897 | } | |
9898 | [(set (attr "op_type") | |
9899 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9900 | (const_string "RIL") | |
9901 | (const_string "RR"))) | |
9902 | (set (attr "mnemonic") | |
9903 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9904 | (const_string "jg") | |
9905 | (const_string "br"))) | |
ed9676cf AK |
9906 | (set_attr "type" "branch") |
9907 | (set_attr "atype" "agen")]) | |
9db1d521 | 9908 | |
ed9676cf AK |
9909 | (define_insn "*sibcall_brc" |
9910 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9911 | (match_operand 1 "const_int_operand" "n"))] | |
9912 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9913 | "j\t%0" | |
9914 | [(set_attr "op_type" "RI") | |
9915 | (set_attr "type" "branch")]) | |
9db1d521 | 9916 | |
ed9676cf AK |
9917 | (define_insn "*sibcall_brcl" |
9918 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9919 | (match_operand 1 "const_int_operand" "n"))] | |
8cc6307c | 9920 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
9921 | "jg\t%0" |
9922 | [(set_attr "op_type" "RIL") | |
9923 | (set_attr "type" "branch")]) | |
44b8152b | 9924 | |
ed9676cf AK |
9925 | ; |
9926 | ; sibcall_value patterns | |
9927 | ; | |
9e8327e3 | 9928 | |
ed9676cf AK |
9929 | (define_expand "sibcall_value" |
9930 | [(set (match_operand 0 "" "") | |
9931 | (call (match_operand 1 "" "") | |
9932 | (match_operand 2 "" "")))] | |
9933 | "" | |
9934 | { | |
9935 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9936 | DONE; |
10bbf137 | 9937 | }) |
9db1d521 | 9938 | |
ed9676cf AK |
9939 | (define_insn "*sibcall_value_br" |
9940 | [(set (match_operand 0 "" "") | |
ae156f85 | 9941 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9942 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9943 | "SIBLING_CALL_P (insn) |
ed9676cf | 9944 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
84b4c7b5 AK |
9945 | { |
9946 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
9947 | { | |
9948 | gcc_assert (TARGET_CPU_Z10); | |
9949 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
9950 | INVALID_REGNUM, | |
9951 | NULL_RTX, | |
9952 | s390_indirect_branch_type_call); | |
9953 | return ""; | |
9954 | } | |
9955 | else | |
9956 | return "br\t%%r1"; | |
9957 | } | |
9958 | [(set (attr "op_type") | |
9959 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9960 | (const_string "RIL") | |
9961 | (const_string "RR"))) | |
9962 | (set (attr "mnemonic") | |
9963 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9964 | (const_string "jg") | |
9965 | (const_string "br"))) | |
ed9676cf AK |
9966 | (set_attr "type" "branch") |
9967 | (set_attr "atype" "agen")]) | |
9968 | ||
9969 | (define_insn "*sibcall_value_brc" | |
9970 | [(set (match_operand 0 "" "") | |
9971 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9972 | (match_operand 2 "const_int_operand" "n")))] | |
9973 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9974 | "j\t%1" | |
9975 | [(set_attr "op_type" "RI") | |
9976 | (set_attr "type" "branch")]) | |
9977 | ||
9978 | (define_insn "*sibcall_value_brcl" | |
9979 | [(set (match_operand 0 "" "") | |
9980 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9981 | (match_operand 2 "const_int_operand" "n")))] | |
8cc6307c | 9982 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
9983 | "jg\t%1" |
9984 | [(set_attr "op_type" "RIL") | |
9985 | (set_attr "type" "branch")]) | |
9986 | ||
9987 | ||
9988 | ; | |
9989 | ; call instruction pattern(s). | |
9990 | ; | |
9991 | ||
9992 | (define_expand "call" | |
9993 | [(call (match_operand 0 "" "") | |
9994 | (match_operand 1 "" "")) | |
9995 | (use (match_operand 2 "" ""))] | |
44b8152b | 9996 | "" |
ed9676cf | 9997 | { |
2f7e5a0d | 9998 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9999 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
10000 | DONE; | |
10001 | }) | |
44b8152b | 10002 | |
9e8327e3 UW |
10003 | (define_insn "*bras" |
10004 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10005 | (match_operand 1 "const_int_operand" "n")) | |
10006 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
10007 | "!SIBLING_CALL_P (insn) |
10008 | && TARGET_SMALL_EXEC | |
ed9676cf | 10009 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 10010 | "bras\t%2,%0" |
9db1d521 | 10011 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10012 | (set_attr "type" "jsr") |
10013 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10014 | |
9e8327e3 UW |
10015 | (define_insn "*brasl" |
10016 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10017 | (match_operand 1 "const_int_operand" "n")) | |
10018 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d | 10019 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10020 | |
ed9676cf | 10021 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
10022 | "brasl\t%2,%0" |
10023 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10024 | (set_attr "type" "jsr") |
14cfceb7 IL |
10025 | (set_attr "z196prop" "z196_cracked") |
10026 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10027 | |
9e8327e3 | 10028 | (define_insn "*basr" |
3e4be43f | 10029 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
10030 | (match_operand 1 "const_int_operand" "n")) |
10031 | (clobber (match_operand 2 "register_operand" "=r"))] | |
84b4c7b5 AK |
10032 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10033 | && !SIBLING_CALL_P (insn) | |
10034 | && GET_MODE (operands[2]) == Pmode" | |
9e8327e3 UW |
10035 | { |
10036 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10037 | return "basr\t%2,%0"; | |
10038 | else | |
10039 | return "bas\t%2,%a0"; | |
10040 | } | |
10041 | [(set (attr "op_type") | |
10042 | (if_then_else (match_operand 0 "register_operand" "") | |
10043 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10044 | (set (attr "mnemonic") |
10045 | (if_then_else (match_operand 0 "register_operand" "") | |
10046 | (const_string "basr") (const_string "bas"))) | |
10047 | (set_attr "type" "jsr") | |
10048 | (set_attr "atype" "agen") | |
10049 | (set_attr "z196prop" "z196_cracked")]) | |
10050 | ||
10051 | (define_insn "*basr_via_thunk<mode>_z10" | |
10052 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10053 | (match_operand 1 "const_int_operand" "n")) | |
10054 | (clobber (match_operand:P 2 "register_operand" "=&r"))] | |
10055 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10056 | && TARGET_CPU_Z10 | |
10057 | && !SIBLING_CALL_P (insn)" | |
10058 | { | |
10059 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10060 | REGNO (operands[2]), | |
10061 | NULL_RTX, | |
10062 | s390_indirect_branch_type_call); | |
10063 | return ""; | |
10064 | } | |
10065 | [(set_attr "op_type" "RIL") | |
10066 | (set_attr "mnemonic" "brasl") | |
10067 | (set_attr "type" "jsr") | |
10068 | (set_attr "atype" "agen") | |
10069 | (set_attr "z196prop" "z196_cracked")]) | |
10070 | ||
10071 | (define_insn "*basr_via_thunk<mode>" | |
10072 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10073 | (match_operand 1 "const_int_operand" "n")) | |
10074 | (clobber (match_operand:P 2 "register_operand" "=&r")) | |
10075 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10076 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10077 | && !TARGET_CPU_Z10 | |
10078 | && !SIBLING_CALL_P (insn)" | |
10079 | { | |
10080 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10081 | REGNO (operands[2]), | |
10082 | NULL_RTX, | |
10083 | s390_indirect_branch_type_call); | |
10084 | return ""; | |
10085 | } | |
10086 | [(set_attr "op_type" "RIL") | |
10087 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10088 | (set_attr "type" "jsr") |
65b1d8ea AK |
10089 | (set_attr "atype" "agen") |
10090 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
10091 | |
10092 | ; | |
10093 | ; call_value instruction pattern(s). | |
10094 | ; | |
10095 | ||
10096 | (define_expand "call_value" | |
44b8152b UW |
10097 | [(set (match_operand 0 "" "") |
10098 | (call (match_operand 1 "" "") | |
10099 | (match_operand 2 "" ""))) | |
10100 | (use (match_operand 3 "" ""))] | |
9db1d521 | 10101 | "" |
9db1d521 | 10102 | { |
2f7e5a0d | 10103 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 10104 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 10105 | DONE; |
10bbf137 | 10106 | }) |
9db1d521 | 10107 | |
9e8327e3 | 10108 | (define_insn "*bras_r" |
c19ec8f9 | 10109 | [(set (match_operand 0 "" "") |
9e8327e3 | 10110 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 10111 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 10112 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
10113 | "!SIBLING_CALL_P (insn) |
10114 | && TARGET_SMALL_EXEC | |
ed9676cf | 10115 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10116 | "bras\t%3,%1" |
9db1d521 | 10117 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10118 | (set_attr "type" "jsr") |
10119 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10120 | |
9e8327e3 | 10121 | (define_insn "*brasl_r" |
c19ec8f9 | 10122 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10123 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10124 | (match_operand 2 "const_int_operand" "n"))) | |
10125 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d | 10126 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10127 | |
ed9676cf | 10128 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10129 | "brasl\t%3,%1" |
10130 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10131 | (set_attr "type" "jsr") |
14cfceb7 IL |
10132 | (set_attr "z196prop" "z196_cracked") |
10133 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10134 | |
9e8327e3 | 10135 | (define_insn "*basr_r" |
c19ec8f9 | 10136 | [(set (match_operand 0 "" "") |
3e4be43f | 10137 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10138 | (match_operand 2 "const_int_operand" "n"))) |
10139 | (clobber (match_operand 3 "register_operand" "=r"))] | |
84b4c7b5 AK |
10140 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10141 | && !SIBLING_CALL_P (insn) | |
10142 | && GET_MODE (operands[3]) == Pmode" | |
9e8327e3 UW |
10143 | { |
10144 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10145 | return "basr\t%3,%1"; | |
10146 | else | |
10147 | return "bas\t%3,%a1"; | |
10148 | } | |
10149 | [(set (attr "op_type") | |
10150 | (if_then_else (match_operand 1 "register_operand" "") | |
10151 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10152 | (set (attr "mnemonic") |
10153 | (if_then_else (match_operand 1 "register_operand" "") | |
10154 | (const_string "basr") (const_string "bas"))) | |
10155 | (set_attr "type" "jsr") | |
10156 | (set_attr "atype" "agen") | |
10157 | (set_attr "z196prop" "z196_cracked")]) | |
10158 | ||
10159 | (define_insn "*basr_r_via_thunk_z10" | |
10160 | [(set (match_operand 0 "" "") | |
10161 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10162 | (match_operand 2 "const_int_operand" "n"))) | |
10163 | (clobber (match_operand 3 "register_operand" "=&r"))] | |
10164 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10165 | && TARGET_CPU_Z10 | |
10166 | && !SIBLING_CALL_P (insn) | |
10167 | && GET_MODE (operands[3]) == Pmode" | |
10168 | { | |
10169 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10170 | REGNO (operands[3]), | |
10171 | NULL_RTX, | |
10172 | s390_indirect_branch_type_call); | |
10173 | return ""; | |
10174 | } | |
10175 | [(set_attr "op_type" "RIL") | |
10176 | (set_attr "mnemonic" "brasl") | |
10177 | (set_attr "type" "jsr") | |
10178 | (set_attr "atype" "agen") | |
10179 | (set_attr "z196prop" "z196_cracked")]) | |
10180 | ||
10181 | (define_insn "*basr_r_via_thunk" | |
10182 | [(set (match_operand 0 "" "") | |
10183 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10184 | (match_operand 2 "const_int_operand" "n"))) | |
10185 | (clobber (match_operand 3 "register_operand" "=&r")) | |
10186 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10187 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10188 | && !TARGET_CPU_Z10 | |
10189 | && !SIBLING_CALL_P (insn) | |
10190 | && GET_MODE (operands[3]) == Pmode" | |
10191 | { | |
10192 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10193 | REGNO (operands[3]), | |
10194 | NULL_RTX, | |
10195 | s390_indirect_branch_type_call); | |
10196 | return ""; | |
10197 | } | |
10198 | [(set_attr "op_type" "RIL") | |
10199 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10200 | (set_attr "type" "jsr") |
65b1d8ea AK |
10201 | (set_attr "atype" "agen") |
10202 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10203 | |
fd3cd001 UW |
10204 | ;; |
10205 | ;;- Thread-local storage support. | |
10206 | ;; | |
10207 | ||
f959607b CLT |
10208 | (define_expand "get_thread_pointer<mode>" |
10209 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
10210 | "" | |
c5aa1d12 | 10211 | "") |
fd3cd001 | 10212 | |
f959607b CLT |
10213 | (define_expand "set_thread_pointer<mode>" |
10214 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
10215 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
10216 | "" | |
c5aa1d12 UW |
10217 | "") |
10218 | ||
10219 | (define_insn "*set_tp" | |
ae156f85 | 10220 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
10221 | "" |
10222 | "" | |
10223 | [(set_attr "type" "none") | |
10224 | (set_attr "length" "0")]) | |
c7453384 | 10225 | |
fd3cd001 UW |
10226 | (define_insn "*tls_load_64" |
10227 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 10228 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
10229 | (match_operand:DI 2 "" "")] |
10230 | UNSPEC_TLS_LOAD))] | |
10231 | "TARGET_64BIT" | |
d40c829f | 10232 | "lg\t%0,%1%J2" |
9381e3f1 WG |
10233 | [(set_attr "op_type" "RXE") |
10234 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
10235 | |
10236 | (define_insn "*tls_load_31" | |
d3632d41 UW |
10237 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10238 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
10239 | (match_operand:SI 2 "" "")] |
10240 | UNSPEC_TLS_LOAD))] | |
10241 | "!TARGET_64BIT" | |
d3632d41 | 10242 | "@ |
d40c829f UW |
10243 | l\t%0,%1%J2 |
10244 | ly\t%0,%1%J2" | |
9381e3f1 | 10245 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 10246 | (set_attr "type" "load") |
3e4be43f | 10247 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 10248 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 10249 | |
9e8327e3 | 10250 | (define_insn "*bras_tls" |
c19ec8f9 | 10251 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10252 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10253 | (match_operand 2 "const_int_operand" "n"))) | |
10254 | (clobber (match_operand 3 "register_operand" "=r")) | |
10255 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10256 | "!SIBLING_CALL_P (insn) |
10257 | && TARGET_SMALL_EXEC | |
ed9676cf | 10258 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10259 | "bras\t%3,%1%J4" |
fd3cd001 | 10260 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10261 | (set_attr "type" "jsr") |
10262 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10263 | |
9e8327e3 | 10264 | (define_insn "*brasl_tls" |
c19ec8f9 | 10265 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10266 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10267 | (match_operand 2 "const_int_operand" "n"))) | |
10268 | (clobber (match_operand 3 "register_operand" "=r")) | |
10269 | (use (match_operand 4 "" ""))] | |
2f7e5a0d | 10270 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10271 | |
ed9676cf | 10272 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10273 | "brasl\t%3,%1%J4" |
10274 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10275 | (set_attr "type" "jsr") |
14cfceb7 IL |
10276 | (set_attr "z196prop" "z196_cracked") |
10277 | (set_attr "relative_long" "yes")]) | |
fd3cd001 | 10278 | |
9e8327e3 | 10279 | (define_insn "*basr_tls" |
c19ec8f9 | 10280 | [(set (match_operand 0 "" "") |
3e4be43f | 10281 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10282 | (match_operand 2 "const_int_operand" "n"))) |
10283 | (clobber (match_operand 3 "register_operand" "=r")) | |
10284 | (use (match_operand 4 "" ""))] | |
ed9676cf | 10285 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10286 | { |
10287 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10288 | return "basr\t%3,%1%J4"; | |
10289 | else | |
10290 | return "bas\t%3,%a1%J4"; | |
10291 | } | |
10292 | [(set (attr "op_type") | |
10293 | (if_then_else (match_operand 1 "register_operand" "") | |
10294 | (const_string "RR") (const_string "RX"))) | |
10295 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10296 | (set_attr "atype" "agen") |
10297 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10298 | |
e0374221 AS |
10299 | ;; |
10300 | ;;- Atomic operations | |
10301 | ;; | |
10302 | ||
10303 | ; | |
78ce265b | 10304 | ; memory barrier patterns. |
e0374221 AS |
10305 | ; |
10306 | ||
78ce265b RH |
10307 | (define_expand "mem_thread_fence" |
10308 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
10309 | "" | |
10310 | { | |
10311 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
10312 | enough not to require barriers of any kind. */ | |
46b35980 | 10313 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
10314 | { |
10315 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
10316 | MEM_VOLATILE_P (mem) = 1; | |
10317 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
10318 | } | |
10319 | DONE; | |
e0374221 AS |
10320 | }) |
10321 | ||
78ce265b RH |
10322 | ; Although bcr is superscalar on Z10, this variant will never |
10323 | ; become part of an execution group. | |
a9cc3f58 AK |
10324 | ; With z196 we can make use of the fast-BCR-serialization facility. |
10325 | ; This allows for a slightly faster sync which is sufficient for our | |
10326 | ; purposes. | |
78ce265b | 10327 | (define_insn "mem_thread_fence_1" |
e0374221 | 10328 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 10329 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 10330 | "" |
a9cc3f58 AK |
10331 | { |
10332 | if (TARGET_Z196) | |
10333 | return "bcr\t14,0"; | |
10334 | else | |
10335 | return "bcr\t15,0"; | |
10336 | } | |
10337 | [(set_attr "op_type" "RR") | |
10338 | (set_attr "mnemonic" "bcr_flush") | |
10339 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10340 | |
78ce265b RH |
10341 | ; |
10342 | ; atomic load/store operations | |
10343 | ; | |
10344 | ||
10345 | ; Atomic loads need not examine the memory model at all. | |
10346 | (define_expand "atomic_load<mode>" | |
10347 | [(match_operand:DINT 0 "register_operand") ;; output | |
10348 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10349 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10350 | "" | |
10351 | { | |
75cc21e2 AK |
10352 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10353 | FAIL; | |
10354 | ||
78ce265b RH |
10355 | if (<MODE>mode == TImode) |
10356 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10357 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10358 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10359 | else | |
10360 | emit_move_insn (operands[0], operands[1]); | |
10361 | DONE; | |
10362 | }) | |
10363 | ||
10364 | ; Different from movdi_31 in that we want no splitters. | |
10365 | (define_insn "atomic_loaddi_1" | |
10366 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10367 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10368 | UNSPEC_MOVA))] | |
10369 | "!TARGET_ZARCH" | |
10370 | "@ | |
10371 | lm\t%0,%M0,%S1 | |
10372 | lmy\t%0,%M0,%S1 | |
10373 | ld\t%0,%1 | |
10374 | ldy\t%0,%1" | |
10375 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10376 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10377 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10378 | ||
10379 | (define_insn "atomic_loadti_1" | |
10380 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10381 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10382 | UNSPEC_MOVA))] |
10383 | "TARGET_ZARCH" | |
10384 | "lpq\t%0,%1" | |
10385 | [(set_attr "op_type" "RXY") | |
10386 | (set_attr "type" "other")]) | |
10387 | ||
10388 | ; Atomic stores must(?) enforce sequential consistency. | |
10389 | (define_expand "atomic_store<mode>" | |
10390 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10391 | (match_operand:DINT 1 "register_operand") ;; input | |
10392 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10393 | "" | |
10394 | { | |
46b35980 | 10395 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10396 | |
75cc21e2 AK |
10397 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10398 | FAIL; | |
10399 | ||
78ce265b RH |
10400 | if (<MODE>mode == TImode) |
10401 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10402 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10403 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10404 | else | |
10405 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10406 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10407 | emit_insn (gen_mem_thread_fence (operands[2])); |
10408 | DONE; | |
10409 | }) | |
10410 | ||
10411 | ; Different from movdi_31 in that we want no splitters. | |
10412 | (define_insn "atomic_storedi_1" | |
10413 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10414 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10415 | UNSPEC_MOVA))] | |
10416 | "!TARGET_ZARCH" | |
10417 | "@ | |
10418 | stm\t%1,%N1,%S0 | |
10419 | stmy\t%1,%N1,%S0 | |
10420 | std %1,%0 | |
10421 | stdy %1,%0" | |
10422 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10423 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10424 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10425 | ||
10426 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10427 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10428 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10429 | UNSPEC_MOVA))] | |
10430 | "TARGET_ZARCH" | |
10431 | "stpq\t%1,%0" | |
10432 | [(set_attr "op_type" "RXY") | |
10433 | (set_attr "type" "other")]) | |
e0374221 AS |
10434 | |
10435 | ; | |
10436 | ; compare and swap patterns. | |
10437 | ; | |
10438 | ||
78ce265b RH |
10439 | (define_expand "atomic_compare_and_swap<mode>" |
10440 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
03db9ab5 DV |
10441 | (match_operand:DINT 1 "nonimmediate_operand");; oldval output |
10442 | (match_operand:DINT 2 "s_operand") ;; memory | |
10443 | (match_operand:DINT 3 "general_operand") ;; expected intput | |
10444 | (match_operand:DINT 4 "general_operand") ;; newval intput | |
78ce265b RH |
10445 | (match_operand:SI 5 "const_int_operand") ;; is_weak |
10446 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10447 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10448 | "" | |
10449 | { | |
03db9ab5 DV |
10450 | if (GET_MODE_BITSIZE (<MODE>mode) >= 16 |
10451 | && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) | |
75cc21e2 AK |
10452 | FAIL; |
10453 | ||
03db9ab5 DV |
10454 | s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], |
10455 | operands[3], operands[4], INTVAL (operands[5])); | |
10456 | DONE;}) | |
3093f076 | 10457 | |
78ce265b RH |
10458 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10459 | [(parallel | |
10460 | [(set (match_operand:DGPR 0 "register_operand") | |
03db9ab5 | 10461 | (match_operand:DGPR 1 "s_operand")) |
78ce265b RH |
10462 | (set (match_dup 1) |
10463 | (unspec_volatile:DGPR | |
10464 | [(match_dup 1) | |
10465 | (match_operand:DGPR 2 "register_operand") | |
10466 | (match_operand:DGPR 3 "register_operand")] | |
10467 | UNSPECV_CAS)) | |
03db9ab5 DV |
10468 | (set (match_operand 4 "cc_reg_operand") |
10469 | (match_dup 5))])] | |
10470 | "GET_MODE (operands[4]) == CCZmode | |
10471 | || GET_MODE (operands[4]) == CCZ1mode" | |
10472 | { | |
10473 | operands[5] | |
10474 | = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); | |
10475 | }) | |
78ce265b RH |
10476 | |
10477 | ; cdsg, csg | |
10478 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10479 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
bdb57bcb | 10480 | (match_operand:TDI 1 "nonsym_memory_operand" "+S")) |
8006eaa6 | 10481 | (set (match_dup 1) |
78ce265b | 10482 | (unspec_volatile:TDI |
8006eaa6 | 10483 | [(match_dup 1) |
78ce265b RH |
10484 | (match_operand:TDI 2 "register_operand" "0") |
10485 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 | 10486 | UNSPECV_CAS)) |
03db9ab5 DV |
10487 | (set (reg CC_REGNUM) |
10488 | (compare (match_dup 1) (match_dup 2)))] | |
10489 | "TARGET_ZARCH | |
10490 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10491 | "c<td>sg\t%0,%3,%S1" |
10492 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10493 | (set_attr "type" "sem")]) |
10494 | ||
78ce265b RH |
10495 | ; cds, cdsy |
10496 | (define_insn "*atomic_compare_and_swapdi_2" | |
10497 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
bdb57bcb | 10498 | (match_operand:DI 1 "nonsym_memory_operand" "+Q,S")) |
e0374221 | 10499 | (set (match_dup 1) |
78ce265b RH |
10500 | (unspec_volatile:DI |
10501 | [(match_dup 1) | |
10502 | (match_operand:DI 2 "register_operand" "0,0") | |
10503 | (match_operand:DI 3 "register_operand" "r,r")] | |
10504 | UNSPECV_CAS)) | |
03db9ab5 DV |
10505 | (set (reg CC_REGNUM) |
10506 | (compare (match_dup 1) (match_dup 2)))] | |
10507 | "!TARGET_ZARCH | |
10508 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10509 | "@ |
10510 | cds\t%0,%3,%S1 | |
10511 | cdsy\t%0,%3,%S1" | |
10512 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10513 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10514 | (set_attr "type" "sem")]) |
10515 | ||
10516 | ; cs, csy | |
10517 | (define_insn "*atomic_compare_and_swapsi_3" | |
10518 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
bdb57bcb | 10519 | (match_operand:SI 1 "nonsym_memory_operand" "+Q,S")) |
78ce265b RH |
10520 | (set (match_dup 1) |
10521 | (unspec_volatile:SI | |
e0374221 | 10522 | [(match_dup 1) |
78ce265b RH |
10523 | (match_operand:SI 2 "register_operand" "0,0") |
10524 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10525 | UNSPECV_CAS)) |
03db9ab5 DV |
10526 | (set (reg CC_REGNUM) |
10527 | (compare (match_dup 1) (match_dup 2)))] | |
10528 | "s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10529 | "@ |
10530 | cs\t%0,%3,%S1 | |
10531 | csy\t%0,%3,%S1" | |
10532 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10533 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10534 | (set_attr "type" "sem")]) |
10535 | ||
45d18331 AS |
10536 | ; |
10537 | ; Other atomic instruction patterns. | |
10538 | ; | |
10539 | ||
65b1d8ea AK |
10540 | ; z196 load and add, xor, or and and instructions |
10541 | ||
78ce265b RH |
10542 | (define_expand "atomic_fetch_<atomic><mode>" |
10543 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10544 | (ATOMIC_Z196:GPR | |
10545 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10546 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10547 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10548 | "TARGET_Z196" |
78ce265b | 10549 | { |
75cc21e2 AK |
10550 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10551 | FAIL; | |
10552 | ||
78ce265b RH |
10553 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10554 | (operands[0], operands[1], operands[2])); | |
10555 | DONE; | |
10556 | }) | |
65b1d8ea AK |
10557 | |
10558 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10559 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10560 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10561 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10562 | (set (match_dup 1) |
10563 | (unspec_volatile:GPR | |
10564 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10565 | (match_operand:GPR 2 "general_operand" "d"))] | |
10566 | UNSPECV_ATOMIC_OP)) | |
10567 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10568 | "TARGET_Z196" |
78ce265b RH |
10569 | "la<noxa><g>\t%0,%2,%1" |
10570 | [(set_attr "op_type" "RSY") | |
10571 | (set_attr "type" "sem")]) | |
65b1d8ea | 10572 | |
78ce265b RH |
10573 | ;; For SImode and larger, the optabs.c code will do just fine in |
10574 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10575 | ;; better by expanding our own loop. | |
65b1d8ea | 10576 | |
78ce265b RH |
10577 | (define_expand "atomic_<atomic><mode>" |
10578 | [(ATOMIC:HQI | |
10579 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10580 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10581 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10582 | "" |
78ce265b RH |
10583 | { |
10584 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10585 | operands[1], false); | |
10586 | DONE; | |
10587 | }) | |
45d18331 | 10588 | |
78ce265b RH |
10589 | (define_expand "atomic_fetch_<atomic><mode>" |
10590 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10591 | (ATOMIC:HQI | |
10592 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10593 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10594 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10595 | "" |
78ce265b RH |
10596 | { |
10597 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10598 | operands[2], false); | |
10599 | DONE; | |
10600 | }) | |
10601 | ||
10602 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10603 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10604 | (ATOMIC:HQI | |
10605 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10606 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10607 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10608 | "" | |
10609 | { | |
10610 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10611 | operands[2], true); | |
10612 | DONE; | |
10613 | }) | |
10614 | ||
03db9ab5 DV |
10615 | ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code |
10616 | ;; generated by the middleend is not good. | |
78ce265b | 10617 | (define_expand "atomic_exchange<mode>" |
03db9ab5 DV |
10618 | [(match_operand:DINT 0 "register_operand") ;; val out |
10619 | (match_operand:DINT 1 "s_operand") ;; memory | |
10620 | (match_operand:DINT 2 "general_operand") ;; val in | |
78ce265b | 10621 | (match_operand:SI 3 "const_int_operand")] ;; model |
45d18331 | 10622 | "" |
78ce265b | 10623 | { |
03db9ab5 DV |
10624 | if (<MODE>mode != QImode |
10625 | && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) | |
10626 | FAIL; | |
10627 | if (<MODE>mode == HImode || <MODE>mode == QImode) | |
10628 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], | |
10629 | false); | |
10630 | else if (<MODE>mode == SImode || TARGET_ZARCH) | |
10631 | s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); | |
10632 | else | |
10633 | FAIL; | |
78ce265b RH |
10634 | DONE; |
10635 | }) | |
45d18331 | 10636 | |
9db1d521 HP |
10637 | ;; |
10638 | ;;- Miscellaneous instructions. | |
10639 | ;; | |
10640 | ||
10641 | ; | |
10642 | ; allocate stack instruction pattern(s). | |
10643 | ; | |
10644 | ||
10645 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10646 | [(match_operand 0 "general_operand" "") |
10647 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10648 | "TARGET_BACKCHAIN" |
9db1d521 | 10649 | { |
ef44a6ff | 10650 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10651 | |
ef44a6ff UW |
10652 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10653 | anti_adjust_stack (operands[1]); | |
10654 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10655 | |
ef44a6ff UW |
10656 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10657 | DONE; | |
10bbf137 | 10658 | }) |
9db1d521 HP |
10659 | |
10660 | ||
10661 | ; | |
43ab026f | 10662 | ; setjmp instruction pattern. |
9db1d521 HP |
10663 | ; |
10664 | ||
9db1d521 | 10665 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10666 | [(match_operand 0 "" "")] |
f314b9b1 | 10667 | "flag_pic" |
9db1d521 | 10668 | { |
585539a1 | 10669 | emit_insn (s390_load_got ()); |
c41c1387 | 10670 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10671 | DONE; |
fd7643fb | 10672 | }) |
9db1d521 | 10673 | |
9db1d521 HP |
10674 | ;; These patterns say how to save and restore the stack pointer. We need not |
10675 | ;; save the stack pointer at function level since we are careful to | |
10676 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10677 | ;; when we restore the stack pointer. | |
10678 | ;; | |
10679 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10680 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10681 | ;; save area is a memory location. | |
10682 | ||
10683 | (define_expand "save_stack_function" | |
10684 | [(match_operand 0 "general_operand" "") | |
10685 | (match_operand 1 "general_operand" "")] | |
10686 | "" | |
10687 | "DONE;") | |
10688 | ||
10689 | (define_expand "restore_stack_function" | |
10690 | [(match_operand 0 "general_operand" "") | |
10691 | (match_operand 1 "general_operand" "")] | |
10692 | "" | |
10693 | "DONE;") | |
10694 | ||
10695 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10696 | [(match_operand 0 "register_operand" "") |
10697 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10698 | "TARGET_BACKCHAIN" |
9db1d521 | 10699 | { |
ef44a6ff UW |
10700 | rtx temp = gen_reg_rtx (Pmode); |
10701 | ||
10702 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10703 | emit_move_insn (operands[0], operands[1]); | |
10704 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10705 | ||
10706 | DONE; | |
10bbf137 | 10707 | }) |
9db1d521 HP |
10708 | |
10709 | (define_expand "save_stack_nonlocal" | |
10710 | [(match_operand 0 "memory_operand" "") | |
10711 | (match_operand 1 "register_operand" "")] | |
10712 | "" | |
9db1d521 | 10713 | { |
ef44a6ff UW |
10714 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10715 | ||
10716 | /* Copy the backchain to the first word, sp to the second and the | |
10717 | literal pool base to the third. */ | |
10718 | ||
9602b6a1 AK |
10719 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10720 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10721 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10722 | ||
b3d31392 | 10723 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10724 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10725 | |
9602b6a1 AK |
10726 | emit_move_insn (save_sp, operands[1]); |
10727 | emit_move_insn (save_bp, base); | |
9db1d521 | 10728 | |
9db1d521 | 10729 | DONE; |
10bbf137 | 10730 | }) |
9db1d521 HP |
10731 | |
10732 | (define_expand "restore_stack_nonlocal" | |
10733 | [(match_operand 0 "register_operand" "") | |
10734 | (match_operand 1 "memory_operand" "")] | |
10735 | "" | |
9db1d521 | 10736 | { |
490ceeb4 | 10737 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10738 | rtx temp = NULL_RTX; |
9db1d521 | 10739 | |
43ab026f | 10740 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10741 | literal pool base from the third. */ |
43ab026f | 10742 | |
9602b6a1 AK |
10743 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10744 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10745 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10746 | ||
b3d31392 | 10747 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10748 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10749 | |
9602b6a1 AK |
10750 | emit_move_insn (base, save_bp); |
10751 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10752 | |
10753 | if (temp) | |
10754 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10755 | ||
c41c1387 | 10756 | emit_use (base); |
9db1d521 | 10757 | DONE; |
10bbf137 | 10758 | }) |
9db1d521 | 10759 | |
7bcebb25 AK |
10760 | (define_expand "exception_receiver" |
10761 | [(const_int 0)] | |
10762 | "" | |
10763 | { | |
10764 | s390_set_has_landing_pad_p (true); | |
10765 | DONE; | |
10766 | }) | |
9db1d521 HP |
10767 | |
10768 | ; | |
10769 | ; nop instruction pattern(s). | |
10770 | ; | |
10771 | ||
10772 | (define_insn "nop" | |
10773 | [(const_int 0)] | |
10774 | "" | |
aad98a61 AK |
10775 | "nopr\t%%r0" |
10776 | [(set_attr "op_type" "RR")]) | |
10777 | ||
10778 | ; non-branch NOPs required for optimizing compare-and-branch patterns | |
10779 | ; on z10 | |
10780 | ||
10781 | (define_insn "nop_lr0" | |
10782 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] | |
10783 | "" | |
d40c829f | 10784 | "lr\t0,0" |
729e750f WG |
10785 | [(set_attr "op_type" "RR") |
10786 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10787 | |
aad98a61 AK |
10788 | (define_insn "nop_lr1" |
10789 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] | |
d277db6b WG |
10790 | "" |
10791 | "lr\t1,1" | |
10792 | [(set_attr "op_type" "RR")]) | |
10793 | ||
f8af0e30 DV |
10794 | ;;- Undeletable nops (used for hotpatching) |
10795 | ||
10796 | (define_insn "nop_2_byte" | |
10797 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10798 | "" | |
4bbc8970 | 10799 | "nopr\t%%r0" |
f8af0e30 DV |
10800 | [(set_attr "op_type" "RR")]) |
10801 | ||
10802 | (define_insn "nop_4_byte" | |
10803 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10804 | "" | |
10805 | "nop\t0" | |
10806 | [(set_attr "op_type" "RX")]) | |
10807 | ||
10808 | (define_insn "nop_6_byte" | |
10809 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
8cc6307c | 10810 | "" |
f8af0e30 | 10811 | "brcl\t0, 0" |
14cfceb7 IL |
10812 | [(set_attr "op_type" "RIL") |
10813 | (set_attr "relative_long" "yes")]) | |
f8af0e30 | 10814 | |
9db1d521 HP |
10815 | |
10816 | ; | |
10817 | ; Special literal pool access instruction pattern(s). | |
10818 | ; | |
10819 | ||
416cf582 UW |
10820 | (define_insn "*pool_entry" |
10821 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10822 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10823 | "" |
9db1d521 | 10824 | { |
ef4bddc2 | 10825 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10826 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10827 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10828 | return ""; |
10829 | } | |
b628bd8e | 10830 | [(set (attr "length") |
416cf582 | 10831 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10832 | |
9bb86f41 UW |
10833 | (define_insn "pool_align" |
10834 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10835 | UNSPECV_POOL_ALIGN)] | |
10836 | "" | |
10837 | ".align\t%0" | |
b628bd8e | 10838 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10839 | |
9bb86f41 UW |
10840 | (define_insn "pool_section_start" |
10841 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10842 | "" | |
b929b470 MK |
10843 | { |
10844 | switch_to_section (targetm.asm_out.function_rodata_section | |
10845 | (current_function_decl)); | |
10846 | return ""; | |
10847 | } | |
b628bd8e | 10848 | [(set_attr "length" "0")]) |
b2ccb744 | 10849 | |
9bb86f41 UW |
10850 | (define_insn "pool_section_end" |
10851 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10852 | "" | |
b929b470 MK |
10853 | { |
10854 | switch_to_section (current_function_section ()); | |
10855 | return ""; | |
10856 | } | |
b628bd8e | 10857 | [(set_attr "length" "0")]) |
b2ccb744 | 10858 | |
5af2f3d3 | 10859 | (define_insn "main_base_64" |
9e8327e3 UW |
10860 | [(set (match_operand 0 "register_operand" "=a") |
10861 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8cc6307c | 10862 | "GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
10863 | "larl\t%0,%1" |
10864 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10865 | (set_attr "type" "larl") |
14cfceb7 IL |
10866 | (set_attr "z10prop" "z10_fwd_A1") |
10867 | (set_attr "relative_long" "yes")]) | |
5af2f3d3 UW |
10868 | |
10869 | (define_insn "main_pool" | |
585539a1 UW |
10870 | [(set (match_operand 0 "register_operand" "=a") |
10871 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10872 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10873 | { |
10874 | gcc_unreachable (); | |
10875 | } | |
9381e3f1 | 10876 | [(set (attr "type") |
8cc6307c | 10877 | (const_string "larl"))]) |
b2ccb744 | 10878 | |
aee4e0db | 10879 | (define_insn "reload_base_64" |
9e8327e3 UW |
10880 | [(set (match_operand 0 "register_operand" "=a") |
10881 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8cc6307c | 10882 | "GET_MODE (operands[0]) == Pmode" |
d40c829f | 10883 | "larl\t%0,%1" |
aee4e0db | 10884 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10885 | (set_attr "type" "larl") |
729e750f | 10886 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10887 | |
aee4e0db | 10888 | (define_insn "pool" |
fd7643fb | 10889 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10890 | "" |
8d933e31 AS |
10891 | { |
10892 | gcc_unreachable (); | |
10893 | } | |
b628bd8e | 10894 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10895 | |
4023fb28 UW |
10896 | ;; |
10897 | ;; Insns related to generating the function prologue and epilogue. | |
10898 | ;; | |
10899 | ||
10900 | ||
10901 | (define_expand "prologue" | |
10902 | [(use (const_int 0))] | |
10903 | "" | |
10bbf137 | 10904 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10905 | |
10906 | (define_expand "epilogue" | |
10907 | [(use (const_int 1))] | |
10908 | "" | |
ed9676cf AK |
10909 | "s390_emit_epilogue (false); DONE;") |
10910 | ||
10911 | (define_expand "sibcall_epilogue" | |
10912 | [(use (const_int 0))] | |
10913 | "" | |
10914 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10915 | |
177bc204 RS |
10916 | ;; A direct return instruction, without using an epilogue. |
10917 | (define_insn "<code>" | |
10918 | [(ANY_RETURN)] | |
10919 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
10920 | { |
10921 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10922 | { | |
10923 | /* The target is always r14 so there is no clobber | |
10924 | of r1 needed for pre z10 targets. */ | |
10925 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
10926 | INVALID_REGNUM, | |
10927 | NULL_RTX, | |
10928 | s390_indirect_branch_type_return); | |
10929 | return ""; | |
10930 | } | |
10931 | else | |
10932 | return "br\t%%r14"; | |
10933 | } | |
10934 | [(set (attr "op_type") | |
10935 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10936 | (const_string "RIL") | |
10937 | (const_string "RR"))) | |
10938 | (set (attr "mnemonic") | |
10939 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10940 | (const_string "jg") | |
10941 | (const_string "br"))) | |
177bc204 RS |
10942 | (set_attr "type" "jsr") |
10943 | (set_attr "atype" "agen")]) | |
10944 | ||
84b4c7b5 AK |
10945 | |
10946 | (define_expand "return_use" | |
10947 | [(parallel | |
10948 | [(return) | |
10949 | (use (match_operand 0 "register_operand" "a"))])] | |
10950 | "" | |
10951 | { | |
10952 | if (!TARGET_CPU_Z10 | |
10953 | && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) | |
10954 | { | |
10955 | if (TARGET_64BIT) | |
10956 | emit_jump_insn (gen_returndi_prez10 (operands[0])); | |
10957 | else | |
10958 | emit_jump_insn (gen_returnsi_prez10 (operands[0])); | |
10959 | DONE; | |
10960 | } | |
10961 | }) | |
10962 | ||
10963 | (define_insn "*return<mode>" | |
4023fb28 | 10964 | [(return) |
84b4c7b5 AK |
10965 | (use (match_operand:P 0 "register_operand" "a"))] |
10966 | "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
10967 | { | |
10968 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10969 | { | |
10970 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10971 | INVALID_REGNUM, | |
10972 | NULL_RTX, | |
10973 | s390_indirect_branch_type_return); | |
10974 | return ""; | |
10975 | } | |
10976 | else | |
10977 | return "br\t%0"; | |
10978 | } | |
10979 | [(set (attr "op_type") | |
10980 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10981 | (const_string "RIL") | |
10982 | (const_string "RR"))) | |
10983 | (set (attr "mnemonic") | |
10984 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10985 | (const_string "jg") | |
10986 | (const_string "br"))) | |
10987 | (set_attr "type" "jsr") | |
10988 | (set_attr "atype" "agen")]) | |
10989 | ||
10990 | (define_insn "return<mode>_prez10" | |
10991 | [(return) | |
10992 | (use (match_operand:P 0 "register_operand" "a")) | |
10993 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10994 | "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
10995 | { | |
10996 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10997 | { | |
10998 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10999 | INVALID_REGNUM, | |
11000 | NULL_RTX, | |
11001 | s390_indirect_branch_type_return); | |
11002 | return ""; | |
11003 | } | |
11004 | else | |
11005 | return "br\t%0"; | |
11006 | } | |
11007 | [(set (attr "op_type") | |
11008 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11009 | (const_string "RIL") | |
11010 | (const_string "RR"))) | |
11011 | (set (attr "mnemonic") | |
11012 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11013 | (const_string "jg") | |
11014 | (const_string "br"))) | |
c7453384 | 11015 | (set_attr "type" "jsr") |
077dab3b | 11016 | (set_attr "atype" "agen")]) |
4023fb28 | 11017 | |
4023fb28 | 11018 | |
c7453384 | 11019 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 11020 | ;; pointer. This is used for compatibility. |
c7453384 EC |
11021 | |
11022 | (define_expand "ptr_extend" | |
11023 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11024 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 11025 | "TARGET_64BIT" |
c7453384 | 11026 | { |
c7453384 EC |
11027 | emit_insn (gen_anddi3 (operands[0], |
11028 | gen_lowpart (DImode, operands[1]), | |
11029 | GEN_INT (0x7fffffff))); | |
c7453384 | 11030 | DONE; |
10bbf137 | 11031 | }) |
4798630c D |
11032 | |
11033 | ;; Instruction definition to expand eh_return macro to support | |
11034 | ;; swapping in special linkage return addresses. | |
11035 | ||
11036 | (define_expand "eh_return" | |
11037 | [(use (match_operand 0 "register_operand" ""))] | |
11038 | "TARGET_TPF" | |
11039 | { | |
11040 | s390_emit_tpf_eh_return (operands[0]); | |
11041 | DONE; | |
11042 | }) | |
11043 | ||
7b8acc34 AK |
11044 | ; |
11045 | ; Stack Protector Patterns | |
11046 | ; | |
11047 | ||
11048 | (define_expand "stack_protect_set" | |
11049 | [(set (match_operand 0 "memory_operand" "") | |
11050 | (match_operand 1 "memory_operand" ""))] | |
11051 | "" | |
11052 | { | |
11053 | #ifdef TARGET_THREAD_SSP_OFFSET | |
11054 | operands[1] | |
11055 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11056 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11057 | #endif | |
11058 | if (TARGET_64BIT) | |
11059 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
11060 | else | |
11061 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
11062 | ||
11063 | DONE; | |
11064 | }) | |
11065 | ||
11066 | (define_insn "stack_protect_set<mode>" | |
11067 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
11068 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
11069 | "" | |
11070 | "mvc\t%O0(%G0,%R0),%S1" | |
11071 | [(set_attr "op_type" "SS")]) | |
11072 | ||
11073 | (define_expand "stack_protect_test" | |
11074 | [(set (reg:CC CC_REGNUM) | |
11075 | (compare (match_operand 0 "memory_operand" "") | |
11076 | (match_operand 1 "memory_operand" ""))) | |
11077 | (match_operand 2 "" "")] | |
11078 | "" | |
11079 | { | |
f90b7a5a | 11080 | rtx cc_reg, test; |
7b8acc34 AK |
11081 | #ifdef TARGET_THREAD_SSP_OFFSET |
11082 | operands[1] | |
11083 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11084 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11085 | #endif | |
7b8acc34 AK |
11086 | if (TARGET_64BIT) |
11087 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
11088 | else | |
11089 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
11090 | ||
f90b7a5a PB |
11091 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
11092 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
11093 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
11094 | DONE; |
11095 | }) | |
11096 | ||
11097 | (define_insn "stack_protect_test<mode>" | |
11098 | [(set (reg:CCZ CC_REGNUM) | |
11099 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
11100 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
11101 | "" | |
11102 | "clc\t%O0(%G0,%R0),%S1" | |
11103 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
11104 | |
11105 | ; This is used in s390_emit_prologue in order to prevent insns | |
11106 | ; adjusting the stack pointer to be moved over insns writing stack | |
11107 | ; slots using a copy of the stack pointer in a different register. | |
11108 | (define_insn "stack_tie" | |
11109 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
11110 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
11111 | "" | |
11112 | "" | |
11113 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
11114 | |
11115 | ||
82c6f58a AK |
11116 | (define_insn "stack_restore_from_fpr" |
11117 | [(set (reg:DI STACK_REGNUM) | |
11118 | (match_operand:DI 0 "register_operand" "f")) | |
11119 | (clobber (mem:BLK (scratch)))] | |
11120 | "TARGET_Z10" | |
11121 | "lgdr\t%%r15,%0" | |
11122 | [(set_attr "op_type" "RRE")]) | |
11123 | ||
963fc8d0 AK |
11124 | ; |
11125 | ; Data prefetch patterns | |
11126 | ; | |
11127 | ||
11128 | (define_insn "prefetch" | |
3e4be43f UW |
11129 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
11130 | (match_operand:SI 1 "const_int_operand" " n,n") | |
11131 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 11132 | "TARGET_Z10" |
963fc8d0 | 11133 | { |
4fe6dea8 AK |
11134 | switch (which_alternative) |
11135 | { | |
11136 | case 0: | |
4fe6dea8 | 11137 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 11138 | case 1: |
4fe6dea8 AK |
11139 | if (larl_operand (operands[0], Pmode)) |
11140 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 11141 | /* fallthrough */ |
4fe6dea8 AK |
11142 | default: |
11143 | ||
11144 | /* This might be reached for symbolic operands with an odd | |
11145 | addend. We simply omit the prefetch for such rare cases. */ | |
11146 | ||
11147 | return ""; | |
11148 | } | |
9381e3f1 | 11149 | } |
22d72dbc AK |
11150 | [(set_attr "type" "load,larl") |
11151 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea | 11152 | (set_attr "z10prop" "z10_super") |
14cfceb7 IL |
11153 | (set_attr "z196prop" "z196_alone") |
11154 | (set_attr "relative_long" "yes")]) | |
07da44ab AK |
11155 | |
11156 | ||
11157 | ; | |
11158 | ; Byte swap instructions | |
11159 | ; | |
11160 | ||
511f5bb1 AK |
11161 | ; FIXME: There is also mvcin but we cannot use it since src and target |
11162 | ; may overlap. | |
50dc4eed | 11163 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 11164 | (define_insn "bswap<mode>2" |
3e4be43f UW |
11165 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
11166 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11167 | "" |
07da44ab AK |
11168 | "@ |
11169 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
11170 | lrv<g>\t%0,%1 |
11171 | strv<g>\t%1,%0" | |
11172 | [(set_attr "type" "*,load,store") | |
11173 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 11174 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11175 | |
511f5bb1 | 11176 | (define_insn "bswaphi2" |
3e4be43f UW |
11177 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
11178 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11179 | "" |
6f5a59d1 AK |
11180 | "@ |
11181 | # | |
11182 | lrvh\t%0,%1 | |
11183 | strvh\t%1,%0" | |
11184 | [(set_attr "type" "*,load,store") | |
11185 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 11186 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11187 | |
6f5a59d1 AK |
11188 | (define_split |
11189 | [(set (match_operand:HI 0 "register_operand" "") | |
11190 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
8cc6307c | 11191 | "" |
6f5a59d1 | 11192 | [(set (match_dup 2) (bswap:SI (match_dup 3))) |
9060e335 | 11193 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 11194 | { |
9060e335 | 11195 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
11196 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
11197 | }) | |
11198 | ||
11199 | ||
65b1d8ea AK |
11200 | ; |
11201 | ; Population count instruction | |
11202 | ; | |
11203 | ||
11204 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
11205 | ; portions and stores the result in the corresponding bytes in op0. | |
11206 | (define_insn "*popcount<mode>" | |
11207 | [(set (match_operand:INT 0 "register_operand" "=d") | |
11208 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
11209 | (clobber (reg:CC CC_REGNUM))] | |
11210 | "TARGET_Z196" | |
11211 | "popcnt\t%0,%1" | |
11212 | [(set_attr "op_type" "RRE")]) | |
11213 | ||
11214 | (define_expand "popcountdi2" | |
11215 | [; popcnt op0, op1 | |
11216 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
11217 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
11218 | UNSPEC_POPCNT)) | |
11219 | (clobber (reg:CC CC_REGNUM))]) | |
11220 | ; sllg op2, op0, 32 | |
11221 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
11222 | ; agr op0, op2 | |
11223 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11224 | (clobber (reg:CC CC_REGNUM))]) | |
11225 | ; sllg op2, op0, 16 | |
17465c6e | 11226 | (set (match_dup 2) |
65b1d8ea AK |
11227 | (ashift:DI (match_dup 0) (const_int 16))) |
11228 | ; agr op0, op2 | |
11229 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11230 | (clobber (reg:CC CC_REGNUM))]) | |
11231 | ; sllg op2, op0, 8 | |
11232 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
11233 | ; agr op0, op2 | |
11234 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11235 | (clobber (reg:CC CC_REGNUM))]) | |
11236 | ; srlg op0, op0, 56 | |
11237 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
11238 | "TARGET_Z196 && TARGET_64BIT" | |
11239 | "operands[2] = gen_reg_rtx (DImode);") | |
11240 | ||
11241 | (define_expand "popcountsi2" | |
11242 | [; popcnt op0, op1 | |
11243 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
11244 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
11245 | UNSPEC_POPCNT)) | |
11246 | (clobber (reg:CC CC_REGNUM))]) | |
11247 | ; sllk op2, op0, 16 | |
17465c6e | 11248 | (set (match_dup 2) |
65b1d8ea AK |
11249 | (ashift:SI (match_dup 0) (const_int 16))) |
11250 | ; ar op0, op2 | |
11251 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11252 | (clobber (reg:CC CC_REGNUM))]) | |
11253 | ; sllk op2, op0, 8 | |
11254 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
11255 | ; ar op0, op2 | |
11256 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11257 | (clobber (reg:CC CC_REGNUM))]) | |
11258 | ; srl op0, op0, 24 | |
11259 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
11260 | "TARGET_Z196" | |
11261 | "operands[2] = gen_reg_rtx (SImode);") | |
11262 | ||
11263 | (define_expand "popcounthi2" | |
11264 | [; popcnt op0, op1 | |
11265 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
11266 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
11267 | UNSPEC_POPCNT)) | |
11268 | (clobber (reg:CC CC_REGNUM))]) | |
11269 | ; sllk op2, op0, 8 | |
17465c6e | 11270 | (set (match_dup 2) |
65b1d8ea AK |
11271 | (ashift:SI (match_dup 0) (const_int 8))) |
11272 | ; ar op0, op2 | |
11273 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11274 | (clobber (reg:CC CC_REGNUM))]) | |
11275 | ; srl op0, op0, 8 | |
11276 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
11277 | "TARGET_Z196" | |
11278 | "operands[2] = gen_reg_rtx (SImode);") | |
11279 | ||
11280 | (define_expand "popcountqi2" | |
11281 | [; popcnt op0, op1 | |
11282 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
11283 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
11284 | UNSPEC_POPCNT)) | |
11285 | (clobber (reg:CC CC_REGNUM))])] | |
11286 | "TARGET_Z196" | |
11287 | "") | |
11288 | ||
11289 | ;; | |
11290 | ;;- Copy sign instructions | |
11291 | ;; | |
11292 | ||
11293 | (define_insn "copysign<mode>3" | |
11294 | [(set (match_operand:FP 0 "register_operand" "=f") | |
11295 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
11296 | (match_operand:FP 2 "register_operand" "f")] | |
11297 | UNSPEC_COPYSIGN))] | |
11298 | "TARGET_Z196" | |
11299 | "cpsdr\t%0,%2,%1" | |
11300 | [(set_attr "op_type" "RRF") | |
11301 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
11302 | |
11303 | ||
11304 | ;; | |
11305 | ;;- Transactional execution instructions | |
11306 | ;; | |
11307 | ||
11308 | ; This splitter helps combine to make use of CC directly when | |
11309 | ; comparing the integer result of a tbegin builtin with a constant. | |
11310 | ; The unspec is already removed by canonicalize_comparison. So this | |
11311 | ; splitters only job is to turn the PARALLEL into separate insns | |
11312 | ; again. Unfortunately this only works with the very first cc/int | |
11313 | ; compare since combine is not able to deal with data flow across | |
11314 | ; basic block boundaries. | |
11315 | ||
11316 | ; It needs to be an insn pattern as well since combine does not apply | |
11317 | ; the splitter directly. Combine would only use it if it actually | |
11318 | ; would reduce the number of instructions. | |
11319 | (define_insn_and_split "*ccraw_to_int" | |
11320 | [(set (pc) | |
11321 | (if_then_else | |
11322 | (match_operator 0 "s390_eqne_operator" | |
11323 | [(reg:CCRAW CC_REGNUM) | |
11324 | (match_operand 1 "const_int_operand" "")]) | |
11325 | (label_ref (match_operand 2 "" "")) | |
11326 | (pc))) | |
11327 | (set (match_operand:SI 3 "register_operand" "=d") | |
11328 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
11329 | "" | |
11330 | "#" | |
11331 | "" | |
11332 | [(set (match_dup 3) | |
11333 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
11334 | (set (pc) | |
11335 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
11336 | (label_ref (match_dup 2)) | |
11337 | (pc)))] | |
11338 | "") | |
11339 | ||
11340 | ; Non-constrained transaction begin | |
11341 | ||
11342 | (define_expand "tbegin" | |
ee163e72 AK |
11343 | [(match_operand:SI 0 "register_operand" "") |
11344 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11345 | "TARGET_HTM" |
11346 | { | |
11347 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
11348 | DONE; | |
11349 | }) | |
11350 | ||
11351 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
11352 | [(match_operand:SI 0 "register_operand" "") |
11353 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11354 | "TARGET_HTM" |
11355 | { | |
11356 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
11357 | DONE; | |
11358 | }) | |
11359 | ||
11360 | (define_expand "tbegin_retry" | |
ee163e72 AK |
11361 | [(match_operand:SI 0 "register_operand" "") |
11362 | (match_operand:BLK 1 "memory_operand" "") | |
11363 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11364 | "TARGET_HTM" |
11365 | { | |
11366 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
11367 | DONE; | |
11368 | }) | |
11369 | ||
11370 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
11371 | [(match_operand:SI 0 "register_operand" "") |
11372 | (match_operand:BLK 1 "memory_operand" "") | |
11373 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11374 | "TARGET_HTM" |
11375 | { | |
11376 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
11377 | DONE; | |
11378 | }) | |
11379 | ||
c914ac45 AK |
11380 | ; Clobber VRs since they don't get restored |
11381 | (define_insn "tbegin_1_z13" | |
11382 | [(set (reg:CCRAW CC_REGNUM) | |
11383 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
11384 | UNSPECV_TBEGIN)) | |
11385 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11386 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
11387 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11388 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11389 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11390 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11391 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11392 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11393 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11394 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11395 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11396 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11397 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11398 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11399 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11400 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11401 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11402 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11403 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11404 | ; not supposed to be used for immediates (see genpreds.c). | |
11405 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11406 | "tbegin\t%1,%x0" | |
11407 | [(set_attr "op_type" "SIL")]) | |
11408 | ||
5a3fe9b6 AK |
11409 | (define_insn "tbegin_1" |
11410 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11411 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11412 | UNSPECV_TBEGIN)) |
2561451d AK |
11413 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11414 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11415 | (clobber (reg:DF 16)) |
11416 | (clobber (reg:DF 17)) | |
11417 | (clobber (reg:DF 18)) | |
11418 | (clobber (reg:DF 19)) | |
11419 | (clobber (reg:DF 20)) | |
11420 | (clobber (reg:DF 21)) | |
11421 | (clobber (reg:DF 22)) | |
11422 | (clobber (reg:DF 23)) | |
11423 | (clobber (reg:DF 24)) | |
11424 | (clobber (reg:DF 25)) | |
11425 | (clobber (reg:DF 26)) | |
11426 | (clobber (reg:DF 27)) | |
11427 | (clobber (reg:DF 28)) | |
11428 | (clobber (reg:DF 29)) | |
11429 | (clobber (reg:DF 30)) | |
11430 | (clobber (reg:DF 31))] | |
11431 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11432 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11433 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11434 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11435 | [(set_attr "op_type" "SIL")]) |
11436 | ||
11437 | ; Same as above but without the FPR clobbers | |
11438 | (define_insn "tbegin_nofloat_1" | |
11439 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11440 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11441 | UNSPECV_TBEGIN)) | |
11442 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11443 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11444 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11445 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11446 | [(set_attr "op_type" "SIL")]) |
11447 | ||
11448 | ||
11449 | ; Constrained transaction begin | |
11450 | ||
11451 | (define_expand "tbeginc" | |
11452 | [(set (reg:CCRAW CC_REGNUM) | |
11453 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11454 | UNSPECV_TBEGINC))] | |
11455 | "TARGET_HTM" | |
11456 | "") | |
11457 | ||
11458 | (define_insn "*tbeginc_1" | |
11459 | [(set (reg:CCRAW CC_REGNUM) | |
11460 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11461 | UNSPECV_TBEGINC))] | |
11462 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11463 | "tbeginc\t0,%x0" | |
11464 | [(set_attr "op_type" "SIL")]) | |
11465 | ||
11466 | ; Transaction end | |
11467 | ||
11468 | (define_expand "tend" | |
11469 | [(set (reg:CCRAW CC_REGNUM) | |
11470 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11471 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11472 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11473 | "TARGET_HTM" | |
11474 | "") | |
11475 | ||
11476 | (define_insn "*tend_1" | |
11477 | [(set (reg:CCRAW CC_REGNUM) | |
11478 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11479 | "TARGET_HTM" | |
11480 | "tend" | |
11481 | [(set_attr "op_type" "S")]) | |
11482 | ||
11483 | ; Transaction abort | |
11484 | ||
11485 | (define_expand "tabort" | |
eae48192 | 11486 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11487 | UNSPECV_TABORT)] |
11488 | "TARGET_HTM && operands != NULL" | |
11489 | { | |
11490 | if (CONST_INT_P (operands[0]) | |
11491 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11492 | { | |
f3981e7e | 11493 | error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC |
5a3fe9b6 AK |
11494 | ". Values in range 0 through 255 are reserved.", |
11495 | INTVAL (operands[0])); | |
11496 | FAIL; | |
11497 | } | |
11498 | }) | |
11499 | ||
11500 | (define_insn "*tabort_1" | |
eae48192 | 11501 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11502 | UNSPECV_TABORT)] |
11503 | "TARGET_HTM && operands != NULL" | |
11504 | "tabort\t%Y0" | |
11505 | [(set_attr "op_type" "S")]) | |
11506 | ||
eae48192 AK |
11507 | (define_insn "*tabort_1_plus" |
11508 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11509 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11510 | UNSPECV_TABORT)] | |
11511 | "TARGET_HTM && operands != NULL | |
11512 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11513 | "tabort\t%1(%0)" | |
11514 | [(set_attr "op_type" "S")]) | |
11515 | ||
5a3fe9b6 AK |
11516 | ; Transaction extract nesting depth |
11517 | ||
11518 | (define_insn "etnd" | |
11519 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11520 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11521 | "TARGET_HTM" | |
11522 | "etnd\t%0" | |
11523 | [(set_attr "op_type" "RRE")]) | |
11524 | ||
11525 | ; Non-transactional store | |
11526 | ||
11527 | (define_insn "ntstg" | |
3e4be43f | 11528 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11529 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11530 | UNSPECV_NTSTG))] | |
11531 | "TARGET_HTM" | |
11532 | "ntstg\t%1,%0" | |
11533 | [(set_attr "op_type" "RXY")]) | |
11534 | ||
11535 | ; Transaction perform processor assist | |
11536 | ||
11537 | (define_expand "tx_assist" | |
2561451d AK |
11538 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11539 | (reg:SI GPR0_REGNUM) | |
291a9e98 | 11540 | (const_int PPA_TX_ABORT)] |
5a3fe9b6 AK |
11541 | UNSPECV_PPA)] |
11542 | "TARGET_HTM" | |
2561451d | 11543 | "") |
5a3fe9b6 AK |
11544 | |
11545 | (define_insn "*ppa" | |
11546 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11547 | (match_operand:SI 1 "register_operand" "d") | |
11548 | (match_operand 2 "const_int_operand" "I")] | |
11549 | UNSPECV_PPA)] | |
291a9e98 | 11550 | "(TARGET_ZEC12 || TARGET_HTM) && INTVAL (operands[2]) < 16" |
2561451d | 11551 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11552 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11553 | |
11554 | ||
11555 | ; Set and get floating point control register | |
11556 | ||
3af82a61 | 11557 | (define_insn "sfpc" |
004f64e1 AK |
11558 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11559 | UNSPECV_SFPC)] | |
11560 | "TARGET_HARD_FLOAT" | |
11561 | "sfpc\t%0") | |
11562 | ||
3af82a61 | 11563 | (define_insn "efpc" |
004f64e1 AK |
11564 | [(set (match_operand:SI 0 "register_operand" "=d") |
11565 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11566 | "TARGET_HARD_FLOAT" | |
11567 | "efpc\t%0") | |
3af82a61 AK |
11568 | |
11569 | ||
11570 | ; Load count to block boundary | |
11571 | ||
11572 | (define_insn "lcbb" | |
11573 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11574 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11575 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11576 | (clobber (reg:CC CC_REGNUM))] | |
11577 | "TARGET_Z13" | |
9a36359e | 11578 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11579 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11580 | |
11581 | ; Handle -fsplit-stack. | |
11582 | ||
11583 | (define_expand "split_stack_prologue" | |
11584 | [(const_int 0)] | |
11585 | "" | |
11586 | { | |
11587 | s390_expand_split_stack_prologue (); | |
11588 | DONE; | |
11589 | }) | |
11590 | ||
11591 | ;; If there are operand 0 bytes available on the stack, jump to | |
11592 | ;; operand 1. | |
11593 | ||
11594 | (define_expand "split_stack_space_check" | |
11595 | [(set (pc) (if_then_else | |
11596 | (ltu (minus (reg 15) | |
11597 | (match_operand 0 "register_operand")) | |
11598 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11599 | (label_ref (match_operand 1)) | |
11600 | (pc)))] | |
11601 | "" | |
11602 | { | |
11603 | /* Offset from thread pointer to __private_ss. */ | |
11604 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11605 | rtx tp = s390_get_thread_pointer (); | |
11606 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11607 | rtx reg = gen_reg_rtx (Pmode); | |
11608 | rtx cc; | |
11609 | if (TARGET_64BIT) | |
11610 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11611 | else | |
11612 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11613 | cc = s390_emit_compare (GT, reg, guard); | |
11614 | s390_emit_jump (operands[1], cc); | |
11615 | ||
11616 | DONE; | |
11617 | }) | |
11618 | ||
11619 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
11620 | ;; parameter block label, label to be called by __morestack, frame size, | |
11621 | ;; stack parameter size. | |
11622 | ||
11623 | (define_insn "split_stack_data" | |
11624 | [(unspec_volatile [(match_operand 0 "" "X") | |
11625 | (match_operand 1 "" "X") | |
11626 | (match_operand 2 "const_int_operand" "X") | |
11627 | (match_operand 3 "const_int_operand" "X")] | |
11628 | UNSPECV_SPLIT_STACK_DATA)] | |
8cc6307c | 11629 | "" |
4cb4721f MK |
11630 | { |
11631 | switch_to_section (targetm.asm_out.function_rodata_section | |
11632 | (current_function_decl)); | |
11633 | ||
11634 | if (TARGET_64BIT) | |
11635 | output_asm_insn (".align\t8", operands); | |
11636 | else | |
11637 | output_asm_insn (".align\t4", operands); | |
11638 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11639 | CODE_LABEL_NUMBER (operands[0])); | |
11640 | if (TARGET_64BIT) | |
11641 | { | |
11642 | output_asm_insn (".quad\t%2", operands); | |
11643 | output_asm_insn (".quad\t%3", operands); | |
11644 | output_asm_insn (".quad\t%1-%0", operands); | |
11645 | } | |
11646 | else | |
11647 | { | |
11648 | output_asm_insn (".long\t%2", operands); | |
11649 | output_asm_insn (".long\t%3", operands); | |
11650 | output_asm_insn (".long\t%1-%0", operands); | |
11651 | } | |
11652 | ||
11653 | switch_to_section (current_function_section ()); | |
11654 | return ""; | |
11655 | } | |
11656 | [(set_attr "length" "0")]) | |
11657 | ||
11658 | ||
11659 | ;; A jg with minimal fuss for use in split stack prologue. | |
11660 | ||
11661 | (define_expand "split_stack_call" | |
11662 | [(match_operand 0 "bras_sym_operand" "X") | |
11663 | (match_operand 1 "" "")] | |
8cc6307c | 11664 | "" |
4cb4721f MK |
11665 | { |
11666 | if (TARGET_64BIT) | |
11667 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11668 | else | |
11669 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11670 | DONE; | |
11671 | }) | |
11672 | ||
11673 | (define_insn "split_stack_call_<mode>" | |
11674 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11675 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11676 | (reg:P 1)] | |
11677 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 11678 | "" |
4cb4721f MK |
11679 | "jg\t%0" |
11680 | [(set_attr "op_type" "RIL") | |
11681 | (set_attr "type" "branch")]) | |
11682 | ||
11683 | ;; Also a conditional one. | |
11684 | ||
11685 | (define_expand "split_stack_cond_call" | |
11686 | [(match_operand 0 "bras_sym_operand" "X") | |
11687 | (match_operand 1 "" "") | |
11688 | (match_operand 2 "" "")] | |
8cc6307c | 11689 | "" |
4cb4721f MK |
11690 | { |
11691 | if (TARGET_64BIT) | |
11692 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11693 | else | |
11694 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11695 | DONE; | |
11696 | }) | |
11697 | ||
11698 | (define_insn "split_stack_cond_call_<mode>" | |
11699 | [(set (pc) | |
11700 | (if_then_else | |
11701 | (match_operand 1 "" "") | |
11702 | (label_ref (match_operand 2 "" "")) | |
11703 | (pc))) | |
11704 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11705 | (reg:P 1)] | |
11706 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 11707 | "" |
4cb4721f MK |
11708 | "jg%C1\t%0" |
11709 | [(set_attr "op_type" "RIL") | |
11710 | (set_attr "type" "branch")]) | |
539405d5 AK |
11711 | |
11712 | (define_insn "osc_break" | |
11713 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
11714 | "" | |
11715 | "bcr\t7,%%r0" | |
11716 | [(set_attr "op_type" "RR")]) | |
291a9e98 AK |
11717 | |
11718 | (define_expand "speculation_barrier" | |
11719 | [(unspec_volatile [(reg:SI GPR0_REGNUM) | |
11720 | (reg:SI GPR0_REGNUM) | |
11721 | (const_int PPA_OOO_BARRIER)] | |
11722 | UNSPECV_PPA)] | |
11723 | "TARGET_ZEC12" | |
11724 | "") |