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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
85ec4feb | 2 | ;; Copyright (C) 1999-2018 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
77 | UNSPEC_LTREL_OFFSET |
78 | UNSPEC_LTREL_BASE | |
79 | UNSPEC_POOL_OFFSET | |
80 | UNSPEC_GOTENT | |
81 | UNSPEC_GOT | |
82 | UNSPEC_GOTOFF | |
83 | UNSPEC_PLT | |
84 | UNSPEC_PLTOFF | |
fd7643fb UW |
85 | |
86 | ; Literal pool | |
30a49b23 AK |
87 | UNSPEC_RELOAD_BASE |
88 | UNSPEC_MAIN_BASE | |
89 | UNSPEC_LTREF | |
90 | UNSPEC_INSN | |
91 | UNSPEC_EXECUTE | |
84b4c7b5 | 92 | UNSPEC_EXECUTE_JUMP |
fd7643fb | 93 | |
1a8c13b3 | 94 | ; Atomic Support |
30a49b23 | 95 | UNSPEC_MB |
78ce265b | 96 | UNSPEC_MOVA |
1a8c13b3 | 97 | |
fd7643fb | 98 | ; TLS relocation specifiers |
30a49b23 AK |
99 | UNSPEC_TLSGD |
100 | UNSPEC_TLSLDM | |
101 | UNSPEC_NTPOFF | |
102 | UNSPEC_DTPOFF | |
103 | UNSPEC_GOTNTPOFF | |
104 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
105 | |
106 | ; TLS support | |
30a49b23 AK |
107 | UNSPEC_TLSLDM_NTPOFF |
108 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
109 | |
110 | ; String Functions | |
30a49b23 AK |
111 | UNSPEC_SRST |
112 | UNSPEC_MVST | |
638e37c2 | 113 | |
7b8acc34 | 114 | ; Stack Smashing Protector |
30a49b23 AK |
115 | UNSPEC_SP_SET |
116 | UNSPEC_SP_TEST | |
85dae55a | 117 | |
4cb4721f MK |
118 | ; Split stack support |
119 | UNSPEC_STACK_CHECK | |
120 | ||
638e37c2 | 121 | ; Test Data Class (TDC) |
30a49b23 | 122 | UNSPEC_TDC_INSN |
65b1d8ea AK |
123 | |
124 | ; Population Count | |
30a49b23 AK |
125 | UNSPEC_POPCNT |
126 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
127 | |
128 | ; Load FP Integer | |
129 | UNSPEC_FPINT_FLOOR | |
130 | UNSPEC_FPINT_BTRUNC | |
131 | UNSPEC_FPINT_ROUND | |
132 | UNSPEC_FPINT_CEIL | |
133 | UNSPEC_FPINT_NEARBYINT | |
134 | UNSPEC_FPINT_RINT | |
085261c8 | 135 | |
3af82a61 AK |
136 | UNSPEC_LCBB |
137 | ||
085261c8 | 138 | ; Vector |
3af82a61 AK |
139 | UNSPEC_VEC_SMULT_HI |
140 | UNSPEC_VEC_UMULT_HI | |
141 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
142 | UNSPEC_VEC_SMULT_EVEN |
143 | UNSPEC_VEC_UMULT_EVEN | |
144 | UNSPEC_VEC_SMULT_ODD | |
145 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
146 | |
147 | UNSPEC_VEC_VMAL | |
148 | UNSPEC_VEC_VMAH | |
149 | UNSPEC_VEC_VMALH | |
150 | UNSPEC_VEC_VMAE | |
151 | UNSPEC_VEC_VMALE | |
152 | UNSPEC_VEC_VMAO | |
153 | UNSPEC_VEC_VMALO | |
154 | ||
155 | UNSPEC_VEC_GATHER | |
156 | UNSPEC_VEC_EXTRACT | |
157 | UNSPEC_VEC_INSERT_AND_ZERO | |
158 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 159 | UNSPEC_VEC_LOAD_LEN |
76794c52 | 160 | UNSPEC_VEC_LOAD_LEN_R |
3af82a61 AK |
161 | UNSPEC_VEC_MERGEH |
162 | UNSPEC_VEC_MERGEL | |
163 | UNSPEC_VEC_PACK | |
164 | UNSPEC_VEC_PACK_SATURATE | |
165 | UNSPEC_VEC_PACK_SATURATE_CC | |
166 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
168 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
169 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
170 | UNSPEC_VEC_PERM | |
171 | UNSPEC_VEC_PERMI | |
172 | UNSPEC_VEC_EXTEND | |
173 | UNSPEC_VEC_STORE_LEN | |
76794c52 AK |
174 | UNSPEC_VEC_STORE_LEN_R |
175 | UNSPEC_VEC_VBPERM | |
3af82a61 AK |
176 | UNSPEC_VEC_UNPACKH |
177 | UNSPEC_VEC_UNPACKH_L | |
178 | UNSPEC_VEC_UNPACKL | |
179 | UNSPEC_VEC_UNPACKL_L | |
180 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
181 | UNSPEC_VEC_ADDE_U128 |
182 | UNSPEC_VEC_ADDEC_U128 | |
183 | UNSPEC_VEC_AVG | |
184 | UNSPEC_VEC_AVGU | |
185 | UNSPEC_VEC_CHECKSUM | |
186 | UNSPEC_VEC_GFMSUM | |
187 | UNSPEC_VEC_GFMSUM_128 | |
188 | UNSPEC_VEC_GFMSUM_ACCUM | |
189 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
190 | UNSPEC_VEC_SET | |
191 | ||
192 | UNSPEC_VEC_VSUMG | |
193 | UNSPEC_VEC_VSUMQ | |
194 | UNSPEC_VEC_VSUM | |
195 | UNSPEC_VEC_RL_MASK | |
196 | UNSPEC_VEC_SLL | |
197 | UNSPEC_VEC_SLB | |
198 | UNSPEC_VEC_SLDB | |
199 | UNSPEC_VEC_SRAL | |
200 | UNSPEC_VEC_SRAB | |
201 | UNSPEC_VEC_SRL | |
202 | UNSPEC_VEC_SRLB | |
203 | ||
3af82a61 | 204 | UNSPEC_VEC_SUBC |
3af82a61 AK |
205 | UNSPEC_VEC_SUBE_U128 |
206 | UNSPEC_VEC_SUBEC_U128 | |
207 | ||
208 | UNSPEC_VEC_TEST_MASK | |
209 | ||
210 | UNSPEC_VEC_VFAE | |
211 | UNSPEC_VEC_VFAECC | |
212 | ||
213 | UNSPEC_VEC_VFEE | |
214 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
215 | UNSPEC_VEC_VFENE |
216 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
217 | |
218 | UNSPEC_VEC_VISTR | |
219 | UNSPEC_VEC_VISTRCC | |
220 | ||
221 | UNSPEC_VEC_VSTRC | |
222 | UNSPEC_VEC_VSTRCCC | |
223 | ||
224 | UNSPEC_VEC_VCDGB | |
225 | UNSPEC_VEC_VCDLGB | |
226 | ||
227 | UNSPEC_VEC_VCGDB | |
228 | UNSPEC_VEC_VCLGDB | |
229 | ||
76794c52 | 230 | UNSPEC_VEC_VFI |
3af82a61 | 231 | |
76794c52 AK |
232 | UNSPEC_VEC_VFLL ; vector fp load lengthened |
233 | UNSPEC_VEC_VFLR ; vector fp load rounded | |
3af82a61 | 234 | |
76794c52 AK |
235 | UNSPEC_VEC_VFTCI |
236 | UNSPEC_VEC_VFTCICC | |
237 | ||
238 | UNSPEC_VEC_MSUM | |
239 | ||
240 | UNSPEC_VEC_VFMIN | |
241 | UNSPEC_VEC_VFMAX | |
085261c8 | 242 | ]) |
fd3cd001 UW |
243 | |
244 | ;; | |
245 | ;; UNSPEC_VOLATILE usage | |
246 | ;; | |
247 | ||
30a49b23 AK |
248 | (define_c_enum "unspecv" [ |
249 | ; Blockage | |
250 | UNSPECV_BLOCKAGE | |
10bbf137 | 251 | |
2f7e5a0d | 252 | ; TPF Support |
30a49b23 AK |
253 | UNSPECV_TPF_PROLOGUE |
254 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 255 | |
10bbf137 | 256 | ; Literal pool |
30a49b23 AK |
257 | UNSPECV_POOL |
258 | UNSPECV_POOL_SECTION | |
259 | UNSPECV_POOL_ALIGN | |
260 | UNSPECV_POOL_ENTRY | |
261 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
262 | |
263 | ; TLS support | |
30a49b23 | 264 | UNSPECV_SET_TP |
e0374221 AS |
265 | |
266 | ; Atomic Support | |
30a49b23 AK |
267 | UNSPECV_CAS |
268 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 269 | |
aad98a61 AK |
270 | ; Non-branch nops used for compare-and-branch adjustments on z10 |
271 | UNSPECV_NOP_LR_0 | |
272 | UNSPECV_NOP_LR_1 | |
273 | ||
f8af0e30 DV |
274 | ; Hotpatching (unremovable NOPs) |
275 | UNSPECV_NOP_2_BYTE | |
276 | UNSPECV_NOP_4_BYTE | |
277 | UNSPECV_NOP_6_BYTE | |
278 | ||
5a3fe9b6 AK |
279 | ; Transactional Execution support |
280 | UNSPECV_TBEGIN | |
2561451d | 281 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
282 | UNSPECV_TBEGINC |
283 | UNSPECV_TEND | |
284 | UNSPECV_TABORT | |
285 | UNSPECV_ETND | |
286 | UNSPECV_NTSTG | |
287 | UNSPECV_PPA | |
004f64e1 AK |
288 | |
289 | ; Set and get floating point control register | |
290 | UNSPECV_SFPC | |
291 | UNSPECV_EFPC | |
4cb4721f MK |
292 | |
293 | ; Split stack support | |
294 | UNSPECV_SPLIT_STACK_CALL | |
295 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
296 | |
297 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
298 | ]) |
299 | ||
ae156f85 AS |
300 | ;; |
301 | ;; Registers | |
302 | ;; | |
303 | ||
35dd9a0e AK |
304 | ; Registers with special meaning |
305 | ||
ae156f85 AS |
306 | (define_constants |
307 | [ | |
308 | ; Sibling call register. | |
309 | (SIBCALL_REGNUM 1) | |
84b4c7b5 AK |
310 | ; A call-clobbered reg which can be used in indirect branch thunks |
311 | (INDIRECT_BRANCH_THUNK_REGNUM 1) | |
ae156f85 AS |
312 | ; Literal pool base register. |
313 | (BASE_REGNUM 13) | |
314 | ; Return address register. | |
315 | (RETURN_REGNUM 14) | |
82c6f58a AK |
316 | ; Stack pointer register. |
317 | (STACK_REGNUM 15) | |
ae156f85 AS |
318 | ; Condition code register. |
319 | (CC_REGNUM 33) | |
f4aa3848 | 320 | ; Thread local storage pointer register. |
ae156f85 AS |
321 | (TP_REGNUM 36) |
322 | ]) | |
323 | ||
35dd9a0e AK |
324 | ; Hardware register names |
325 | ||
326 | (define_constants | |
327 | [ | |
328 | ; General purpose registers | |
329 | (GPR0_REGNUM 0) | |
af344a30 | 330 | (GPR1_REGNUM 1) |
82379bdf AK |
331 | (GPR2_REGNUM 2) |
332 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
333 | ; Floating point registers. |
334 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
335 | (FPR1_REGNUM 20) |
336 | (FPR2_REGNUM 17) | |
337 | (FPR3_REGNUM 21) | |
338 | (FPR4_REGNUM 18) | |
339 | (FPR5_REGNUM 22) | |
340 | (FPR6_REGNUM 19) | |
341 | (FPR7_REGNUM 23) | |
342 | (FPR8_REGNUM 24) | |
343 | (FPR9_REGNUM 28) | |
344 | (FPR10_REGNUM 25) | |
345 | (FPR11_REGNUM 29) | |
346 | (FPR12_REGNUM 26) | |
347 | (FPR13_REGNUM 30) | |
348 | (FPR14_REGNUM 27) | |
349 | (FPR15_REGNUM 31) | |
085261c8 AK |
350 | (VR0_REGNUM 16) |
351 | (VR16_REGNUM 38) | |
352 | (VR23_REGNUM 45) | |
353 | (VR24_REGNUM 46) | |
354 | (VR31_REGNUM 53) | |
35dd9a0e AK |
355 | ]) |
356 | ||
ae8e301e AK |
357 | ; Rounding modes for binary floating point numbers |
358 | (define_constants | |
359 | [(BFP_RND_CURRENT 0) | |
360 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
361 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
362 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
363 | (BFP_RND_TOWARD_0 5) | |
364 | (BFP_RND_TOWARD_INF 6) | |
365 | (BFP_RND_TOWARD_MINF 7)]) | |
366 | ||
367 | ; Rounding modes for decimal floating point numbers | |
368 | ; 1-7 were introduced with the floating point extension facility | |
369 | ; available with z196 | |
370 | ; With these rounding modes (1-7) a quantum exception might occur | |
371 | ; which is suppressed for the other modes. | |
372 | (define_constants | |
373 | [(DFP_RND_CURRENT 0) | |
374 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
375 | (DFP_RND_CURRENT_QUANTEXC 2) | |
376 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
377 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
378 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
379 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
380 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
381 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
382 | (DFP_RND_TOWARD_0 9) | |
383 | (DFP_RND_TOWARD_INF 10) | |
384 | (DFP_RND_TOWARD_MINF 11) | |
385 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
386 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
387 | (DFP_RND_AWAY_FROM_0 14) | |
388 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
389 | ||
35dd9a0e AK |
390 | ;; |
391 | ;; PFPO GPR0 argument format | |
392 | ;; | |
393 | ||
394 | (define_constants | |
395 | [ | |
396 | ; PFPO operation type | |
397 | (PFPO_CONVERT 0x1000000) | |
398 | ; PFPO operand types | |
399 | (PFPO_OP_TYPE_SF 0x5) | |
400 | (PFPO_OP_TYPE_DF 0x6) | |
401 | (PFPO_OP_TYPE_TF 0x7) | |
402 | (PFPO_OP_TYPE_SD 0x8) | |
403 | (PFPO_OP_TYPE_DD 0x9) | |
404 | (PFPO_OP_TYPE_TD 0xa) | |
405 | ; Bitposition of operand types | |
406 | (PFPO_OP0_TYPE_SHIFT 16) | |
407 | (PFPO_OP1_TYPE_SHIFT 8) | |
408 | ]) | |
409 | ||
5a3fe9b6 AK |
410 | ; Immediate operands for tbegin and tbeginc |
411 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
412 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 413 | |
29a74354 UW |
414 | ;; Instruction operand type as used in the Principles of Operation. |
415 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 416 | |
29a74354 | 417 | (define_attr "op_type" |
76794c52 | 418 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" |
b628bd8e | 419 | (const_string "NN")) |
9db1d521 | 420 | |
29a74354 | 421 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 422 | |
077dab3b | 423 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 424 | cs,vs,store,sem,idiv, |
ed0e512a | 425 | imulhi,imulsi,imuldi, |
2cdece44 | 426 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
427 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
428 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 429 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 430 | fmadddf,fmaddsf, |
9381e3f1 WG |
431 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
432 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
433 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
434 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
435 | ftoidfp, other" | |
29a74354 UW |
436 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
437 | (eq_attr "op_type" "SS") (const_string "cs")] | |
438 | (const_string "integer"))) | |
9db1d521 | 439 | |
29a74354 UW |
440 | ;; Another attribute used for scheduling purposes: |
441 | ;; agen: Instruction uses the address generation unit | |
442 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
443 | |
444 | (define_attr "atype" "agen,reg" | |
62d3f261 | 445 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
446 | (const_string "reg") |
447 | (const_string "agen"))) | |
9db1d521 | 448 | |
9381e3f1 WG |
449 | ;; Properties concerning Z10 execution grouping and value forwarding. |
450 | ;; z10_super: instruction is superscalar. | |
451 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
452 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
453 | ;; target register. It can forward this value to a second instruction that reads | |
454 | ;; the same register if that second instruction is issued in the same group. | |
455 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
456 | ;; instruction in the S pipe writes to the register, then the T instruction | |
457 | ;; can immediately read the new value. | |
458 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
459 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
460 | ;; |
461 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
462 | ||
463 | ||
464 | (define_attr "z10prop" "none, | |
465 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
466 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
467 | z10_rec, | |
468 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 469 | z10_c" |
9381e3f1 WG |
470 | (const_string "none")) |
471 | ||
65b1d8ea AK |
472 | ;; Properties concerning Z196 decoding |
473 | ;; z196_alone: must group alone | |
474 | ;; z196_end: ends a group | |
475 | ;; z196_cracked: instruction is cracked or expanded | |
476 | (define_attr "z196prop" "none, | |
477 | z196_alone, z196_ends, | |
478 | z196_cracked" | |
479 | (const_string "none")) | |
9381e3f1 | 480 | |
84b4c7b5 AK |
481 | ; mnemonics which only get defined through if_then_else currently |
482 | ; don't get added to the list values automatically and hence need to | |
483 | ; be listed here. | |
484 | (define_attr "mnemonic" "b,bas,bc,bcr_flush,unknown" (const_string "unknown")) | |
22ac2c2f | 485 | |
9db1d521 HP |
486 | ;; Length in bytes. |
487 | ||
488 | (define_attr "length" "" | |
62d3f261 AK |
489 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
490 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 491 | (const_int 6))) |
9db1d521 | 492 | |
29a74354 UW |
493 | |
494 | ;; Processor type. This attribute must exactly match the processor_type | |
495 | ;; enumeration in s390.h. The current machine description does not | |
496 | ;; distinguish between g5 and g6, but there are differences between the two | |
497 | ;; CPUs could in theory be modeled. | |
498 | ||
6654e96f | 499 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,arch12" |
90c6fd8a | 500 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 501 | |
b5e0425c | 502 | (define_attr "cpu_facility" |
6654e96f | 503 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,arch12,vxe" |
3af8e996 AK |
504 | (const_string "standard")) |
505 | ||
506 | (define_attr "enabled" "" | |
507 | (cond [(eq_attr "cpu_facility" "standard") | |
508 | (const_int 1) | |
509 | ||
510 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 511 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
512 | (const_int 1) |
513 | ||
514 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 515 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
516 | (const_int 1) |
517 | ||
518 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 519 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
520 | (const_int 1) |
521 | ||
522 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 523 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
524 | (const_int 1) |
525 | ||
526 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 527 | (match_test "TARGET_DFP")) |
93538e8e AK |
528 | (const_int 1) |
529 | ||
b5e0425c AK |
530 | (and (eq_attr "cpu_facility" "cpu_zarch") |
531 | (match_test "TARGET_CPU_ZARCH")) | |
532 | (const_int 1) | |
533 | ||
93538e8e | 534 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 535 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
536 | (const_int 1) |
537 | ||
538 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 539 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
540 | (const_int 1) |
541 | ||
542 | (and (eq_attr "cpu_facility" "zEC12") | |
543 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
544 | (const_int 1) |
545 | ||
285363a1 | 546 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 547 | (match_test "TARGET_VX")) |
bf749919 DV |
548 | (const_int 1) |
549 | ||
550 | (and (eq_attr "cpu_facility" "z13") | |
551 | (match_test "TARGET_Z13")) | |
552 | (const_int 1) | |
6654e96f AK |
553 | |
554 | (and (eq_attr "cpu_facility" "arch12") | |
555 | (match_test "TARGET_ARCH12")) | |
556 | (const_int 1) | |
557 | ||
558 | (and (eq_attr "cpu_facility" "vxe") | |
559 | (match_test "TARGET_VXE")) | |
560 | (const_int 1) | |
bf749919 | 561 | ] |
3af8e996 AK |
562 | (const_int 0))) |
563 | ||
29a74354 UW |
564 | ;; Pipeline description for z900. For lack of anything better, |
565 | ;; this description is also used for the g5 and g6. | |
566 | (include "2064.md") | |
567 | ||
3443392a | 568 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
569 | (include "2084.md") |
570 | ||
9381e3f1 WG |
571 | ;; Pipeline description for z10 |
572 | (include "2097.md") | |
573 | ||
65b1d8ea AK |
574 | ;; Pipeline description for z196 |
575 | (include "2817.md") | |
576 | ||
22ac2c2f AK |
577 | ;; Pipeline description for zEC12 |
578 | (include "2827.md") | |
579 | ||
23902021 AK |
580 | ;; Pipeline description for z13 |
581 | (include "2964.md") | |
582 | ||
0bfc3f69 AS |
583 | ;; Predicates |
584 | (include "predicates.md") | |
585 | ||
cd8dc1f9 WG |
586 | ;; Constraint definitions |
587 | (include "constraints.md") | |
588 | ||
a8ba31f2 EC |
589 | ;; Other includes |
590 | (include "tpf.md") | |
f52c81dd | 591 | |
3abcb3a7 | 592 | ;; Iterators |
f52c81dd | 593 | |
085261c8 AK |
594 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
595 | ||
3abcb3a7 | 596 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 597 | ;; same template. |
f4aa3848 | 598 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 599 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
600 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
601 | (define_mode_iterator BFP [TF DF SF]) | |
602 | (define_mode_iterator DFP [TD DD]) | |
603 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
604 | (define_mode_iterator DSF [DF SF]) | |
605 | (define_mode_iterator SD_SF [SF SD]) | |
606 | (define_mode_iterator DD_DF [DF DD]) | |
607 | (define_mode_iterator TD_TF [TF TD]) | |
608 | ||
3abcb3a7 | 609 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 610 | ;; from the same template. |
9602b6a1 | 611 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 612 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 613 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 614 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 615 | |
3abcb3a7 | 616 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 617 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 618 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 619 | |
78ce265b RH |
620 | ;; These macros refer to the actual word_mode of the configuration. |
621 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
622 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
623 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
624 | ||
6e0d70c9 AK |
625 | ;; Used by the umul pattern to express modes having half the size. |
626 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
627 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
628 | ||
3abcb3a7 | 629 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 630 | ;; the same template. |
3abcb3a7 | 631 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 632 | |
3abcb3a7 | 633 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 634 | ;; same template. |
9602b6a1 | 635 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 636 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 637 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 638 | |
3abcb3a7 | 639 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 640 | ;; the same template. |
3abcb3a7 | 641 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 642 | |
d12a76f3 | 643 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
644 | (define_code_iterator IXOR [ior xor]) |
645 | ||
d12a76f3 AK |
646 | ;; This iterator is used to expand the patterns for the nearest |
647 | ;; integer functions. | |
648 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
649 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
650 | UNSPEC_FPINT_NEARBYINT]) | |
651 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
652 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
653 | (UNSPEC_FPINT_ROUND "round") | |
654 | (UNSPEC_FPINT_CEIL "ceil") | |
655 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
656 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
657 | (UNSPEC_FPINT_BTRUNC "5") | |
658 | (UNSPEC_FPINT_ROUND "1") | |
659 | (UNSPEC_FPINT_CEIL "6") | |
660 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
661 | ||
3abcb3a7 HPN |
662 | ;; This iterator and attribute allow to combine most atomic operations. |
663 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 664 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 665 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 666 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 667 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 668 | |
f4aa3848 | 669 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
670 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
671 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 672 | |
f4aa3848 AK |
673 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
674 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
675 | ;; SDmode. |
676 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 677 | |
609e7e80 | 678 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
679 | ;; Likewise for "<RXe>". |
680 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
681 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
682 | ||
609e7e80 | 683 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 684 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
685 | ;; dfp variants in a single insn definition. |
686 | ||
62d3f261 AK |
687 | ;; These mode attributes are supposed to be used in the `enabled' insn |
688 | ;; attribute to disable certain alternatives for certain modes. | |
689 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
690 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
691 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
692 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
693 | (TD "0") (DD "0") (DD "0") | |
694 | (TI "0") (DI "*") (SI "0")]) | |
2de2b3f9 AK |
695 | (define_mode_attr DF [(TF "0") (DF "*") (SF "0") |
696 | (TD "0") (DD "0") (DD "0") | |
697 | (TI "0") (DI "0") (SI "0")]) | |
698 | (define_mode_attr SF [(TF "0") (DF "0") (SF "*") | |
699 | (TD "0") (DD "0") (DD "0") | |
700 | (TI "0") (DI "0") (SI "0")]) | |
f5905b37 | 701 | |
85dae55a AK |
702 | ;; This attribute is used in the operand constraint list |
703 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
704 | ;; TFmode values are represented by a fp register pair. Since the | |
705 | ;; sign bit instructions only handle single source and target fp registers | |
706 | ;; these instructions can only be used for TFmode values if the source and | |
707 | ;; target operand uses the same fp register. | |
708 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
709 | ||
3abcb3a7 | 710 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
711 | ;; within instruction mnemonics. |
712 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
713 | ||
0387c142 WG |
714 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
715 | ;; modes and to an empty string for bfp modes. | |
716 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
717 | ||
1b48c8cc AS |
718 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
719 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
720 | ;; version only operates on one register. | |
721 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
722 | ||
723 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
724 | ;; version only operates on one register. The DImode version needs an additional | |
725 | ;; register for the assembler output. | |
726 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
727 | |
728 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
729 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
730 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
731 | ||
732 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 733 | ;; pattern itself and the corresponding function calls. |
f337b930 | 734 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
735 | |
736 | ;; This attribute handles differences in the instruction 'type' and will result | |
737 | ;; in "RRE" for DImode and "RR" for SImode. | |
738 | (define_mode_attr E [(DI "E") (SI "")]) | |
739 | ||
3298c037 AK |
740 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
741 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
742 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
743 | ||
8006eaa6 AS |
744 | ;; This attribute handles differences in the instruction 'type' and will result |
745 | ;; in "RSE" for TImode and "RS" for DImode. | |
746 | (define_mode_attr TE [(TI "E") (DI "")]) | |
747 | ||
9a91a21f AS |
748 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
749 | ;; and "lcr" in SImode. | |
750 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 751 | |
3298c037 AK |
752 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
753 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
754 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
755 | ;; variant for long displacements. | |
756 | (define_mode_attr y [(DI "g") (SI "y")]) | |
757 | ||
9602b6a1 | 758 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
759 | ;; and "cds" in DImode. |
760 | (define_mode_attr tg [(TI "g") (DI "")]) | |
761 | ||
78ce265b RH |
762 | ;; In TDI templates, a string like "c<d>sg". |
763 | (define_mode_attr td [(TI "d") (DI "")]) | |
764 | ||
2f8f8434 AS |
765 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
766 | ;; and "cfdbr" in SImode. | |
767 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
768 | ||
65b1d8ea AK |
769 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
770 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
771 | ;; 3 operands shift instructions into the existing patterns. | |
772 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
773 | ||
f52c81dd AS |
774 | ;; ICM mask required to load MODE value into the lowest subreg |
775 | ;; of a SImode register. | |
776 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
777 | ||
f6ee577c AS |
778 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
779 | ;; HImode and "llgc" in QImode. | |
780 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
781 | ||
a1aed706 AS |
782 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
783 | ;; in SImode. | |
784 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
785 | ||
609e7e80 AK |
786 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
787 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
788 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
789 | ||
f52c81dd AS |
790 | ;; Maximum unsigned integer that fits in MODE. |
791 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
792 | ||
75ca1b39 RH |
793 | ;; Start and end field computations for RISBG et al. |
794 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
795 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
796 | ||
2542ef05 RH |
797 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
798 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
799 | ;; 64 - bitsize |
800 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
801 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 802 | |
da0dcab1 DV |
803 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
804 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
805 | ||
177bc204 RS |
806 | ;; Allow return and simple_return to be defined from a single template. |
807 | (define_code_iterator ANY_RETURN [return simple_return]) | |
808 | ||
6e5b5de8 AK |
809 | |
810 | ||
811 | ; Condition code modes generated by vector fp comparisons. These will | |
812 | ; be used also in single element mode. | |
813 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
814 | ; Used with VFCMP to expand part of the mnemonic | |
815 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
816 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 817 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 818 | |
191eb16d AK |
819 | ;; Subst pattern definitions |
820 | (include "subst.md") | |
6e5b5de8 | 821 | |
085261c8 AK |
822 | (include "vector.md") |
823 | ||
9db1d521 HP |
824 | ;; |
825 | ;;- Compare instructions. | |
826 | ;; | |
827 | ||
07893d4f | 828 | ; Test-under-Mask instructions |
9db1d521 | 829 | |
07893d4f | 830 | (define_insn "*tmqi_mem" |
ae156f85 | 831 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
832 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
833 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
834 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 835 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 836 | "@ |
fc0ea003 UW |
837 | tm\t%S0,%b1 |
838 | tmy\t%S0,%b1" | |
9381e3f1 | 839 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 840 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 841 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 842 | |
05b9aaaa | 843 | (define_insn "*tmdi_reg" |
ae156f85 | 844 | [(set (reg CC_REGNUM) |
f19a9af7 | 845 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 846 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
847 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
848 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 849 | "TARGET_ZARCH |
3ed99cc9 | 850 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
851 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
852 | "@ | |
853 | tmhh\t%0,%i1 | |
854 | tmhl\t%0,%i1 | |
855 | tmlh\t%0,%i1 | |
856 | tmll\t%0,%i1" | |
9381e3f1 WG |
857 | [(set_attr "op_type" "RI") |
858 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
859 | |
860 | (define_insn "*tmsi_reg" | |
ae156f85 | 861 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
862 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
863 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
864 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 865 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
866 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
867 | "@ | |
868 | tmh\t%0,%i1 | |
869 | tml\t%0,%i1" | |
729e750f WG |
870 | [(set_attr "op_type" "RI") |
871 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 872 | |
f52c81dd | 873 | (define_insn "*tm<mode>_full" |
ae156f85 | 874 | [(set (reg CC_REGNUM) |
f52c81dd AS |
875 | (compare (match_operand:HQI 0 "register_operand" "d") |
876 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 877 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 878 | "tml\t%0,<max_uint>" |
729e750f WG |
879 | [(set_attr "op_type" "RI") |
880 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 881 | |
07893d4f | 882 | |
08a5aaa2 | 883 | ; |
07893d4f | 884 | ; Load-and-Test instructions |
08a5aaa2 AS |
885 | ; |
886 | ||
c0220ea4 | 887 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
888 | |
889 | (define_insn "*tstdi_sign" | |
ae156f85 | 890 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
891 | (compare |
892 | (ashiftrt:DI | |
893 | (ashift:DI | |
3e4be43f | 894 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
895 | (const_int 32)) (const_int 32)) |
896 | (match_operand:DI 1 "const0_operand" ""))) | |
897 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 898 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 899 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
900 | "ltgfr\t%2,%0 |
901 | ltgf\t%2,%0" | |
902 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
903 | (set_attr "cpu_facility" "*,z10") |
904 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 905 | |
43a09b63 | 906 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 907 | (define_insn "*tst<mode>_extimm" |
ec24698e | 908 | [(set (reg CC_REGNUM) |
3e4be43f | 909 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
910 | (match_operand:GPR 1 "const0_operand" ""))) |
911 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 912 | (match_dup 0))] |
08a5aaa2 | 913 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 914 | "@ |
08a5aaa2 AS |
915 | lt<g>r\t%2,%0 |
916 | lt<g>\t%2,%0" | |
9381e3f1 | 917 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 918 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 919 | |
97160c9b DV |
920 | ; Peephole to combine a load-and-test from volatile memory which combine does |
921 | ; not do. | |
922 | (define_peephole2 | |
923 | [(set (match_operand:GPR 0 "register_operand") | |
924 | (match_operand:GPR 2 "memory_operand")) | |
925 | (set (reg CC_REGNUM) | |
926 | (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] | |
927 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM | |
928 | && GENERAL_REG_P (operands[0]) | |
929 | && satisfies_constraint_T (operands[2])" | |
930 | [(parallel | |
931 | [(set (reg:CCS CC_REGNUM) | |
932 | (compare:CCS (match_dup 2) (match_dup 1))) | |
933 | (set (match_dup 0) (match_dup 2))])]) | |
934 | ||
43a09b63 | 935 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 936 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 937 | [(set (reg CC_REGNUM) |
3e4be43f | 938 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
939 | (match_operand:GPR 1 "const0_operand" ""))) |
940 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
941 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 942 | "@ |
08a5aaa2 AS |
943 | lt<g>r\t%0,%0 |
944 | lt<g>\t%2,%0" | |
9381e3f1 | 945 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 946 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 947 | |
07893d4f | 948 | (define_insn "*tstdi" |
ae156f85 | 949 | [(set (reg CC_REGNUM) |
07893d4f UW |
950 | (compare (match_operand:DI 0 "register_operand" "d") |
951 | (match_operand:DI 1 "const0_operand" ""))) | |
952 | (set (match_operand:DI 2 "register_operand" "=d") | |
953 | (match_dup 0))] | |
9602b6a1 | 954 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 955 | "ltgr\t%2,%0" |
9381e3f1 WG |
956 | [(set_attr "op_type" "RRE") |
957 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 958 | |
07893d4f | 959 | (define_insn "*tstsi" |
ae156f85 | 960 | [(set (reg CC_REGNUM) |
d3632d41 | 961 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 962 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 963 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 964 | (match_dup 0))] |
ec24698e | 965 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 966 | "@ |
d40c829f | 967 | ltr\t%2,%0 |
fc0ea003 UW |
968 | icm\t%2,15,%S0 |
969 | icmy\t%2,15,%S0" | |
9381e3f1 | 970 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 971 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 972 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 973 | |
07893d4f | 974 | (define_insn "*tstsi_cconly" |
ae156f85 | 975 | [(set (reg CC_REGNUM) |
d3632d41 | 976 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 977 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 978 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
979 | "s390_match_ccmode(insn, CCSmode)" |
980 | "@ | |
d40c829f | 981 | ltr\t%0,%0 |
fc0ea003 UW |
982 | icm\t%2,15,%S0 |
983 | icmy\t%2,15,%S0" | |
9381e3f1 | 984 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 985 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 986 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 987 | |
08a5aaa2 AS |
988 | (define_insn "*tstdi_cconly_31" |
989 | [(set (reg CC_REGNUM) | |
990 | (compare (match_operand:DI 0 "register_operand" "d") | |
991 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 992 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
993 | "srda\t%0,0" |
994 | [(set_attr "op_type" "RS") | |
995 | (set_attr "atype" "reg")]) | |
996 | ||
43a09b63 | 997 | ; ltr, ltgr |
08a5aaa2 | 998 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 999 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
1000 | (compare (match_operand:GPR 0 "register_operand" "d") |
1001 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 1002 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 1003 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
1004 | [(set_attr "op_type" "RR<E>") |
1005 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 1006 | |
c0220ea4 | 1007 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 1008 | |
f52c81dd | 1009 | (define_insn "*tst<mode>CCT" |
ae156f85 | 1010 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1011 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
1012 | (match_operand:HQI 1 "const0_operand" ""))) | |
1013 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
1014 | (match_dup 0))] |
1015 | "s390_match_ccmode(insn, CCTmode)" | |
1016 | "@ | |
f52c81dd AS |
1017 | icm\t%2,<icm_lo>,%S0 |
1018 | icmy\t%2,<icm_lo>,%S0 | |
1019 | tml\t%0,<max_uint>" | |
9381e3f1 | 1020 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1021 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1022 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
1023 | |
1024 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 1025 | [(set (reg CC_REGNUM) |
d3632d41 | 1026 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 1027 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 1028 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
1029 | "s390_match_ccmode(insn, CCTmode)" |
1030 | "@ | |
fc0ea003 UW |
1031 | icm\t%2,3,%S0 |
1032 | icmy\t%2,3,%S0 | |
d40c829f | 1033 | tml\t%0,65535" |
9381e3f1 | 1034 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1035 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1036 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 1037 | |
3af97654 | 1038 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1039 | [(set (reg CC_REGNUM) |
d3632d41 | 1040 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1041 | (match_operand:QI 1 "const0_operand" "")))] |
1042 | "s390_match_ccmode(insn, CCTmode)" | |
1043 | "@ | |
fc0ea003 UW |
1044 | cli\t%S0,0 |
1045 | cliy\t%S0,0 | |
d40c829f | 1046 | tml\t%0,255" |
9381e3f1 | 1047 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1048 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1049 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1050 | |
f52c81dd | 1051 | (define_insn "*tst<mode>" |
ae156f85 | 1052 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1053 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1054 | (match_operand:HQI 1 "const0_operand" ""))) | |
1055 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1056 | (match_dup 0))] |
1057 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1058 | "@ |
f52c81dd AS |
1059 | icm\t%2,<icm_lo>,%S0 |
1060 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1061 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1062 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1063 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1064 | |
f52c81dd | 1065 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1066 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1067 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1068 | (match_operand:HQI 1 "const0_operand" ""))) | |
1069 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1070 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1071 | "@ |
f52c81dd AS |
1072 | icm\t%2,<icm_lo>,%S0 |
1073 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1074 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1075 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1076 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1077 | |
9db1d521 | 1078 | |
575f7c2b UW |
1079 | ; Compare (equality) instructions |
1080 | ||
1081 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1082 | [(set (reg CC_REGNUM) |
ec24698e | 1083 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1084 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1085 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1086 | "@ |
1087 | cgr\t%0,%1 | |
f4f41b4e | 1088 | cghi\t%0,%h1 |
ec24698e | 1089 | cgfi\t%0,%1 |
575f7c2b | 1090 | cg\t%0,%1 |
19b63d8e | 1091 | #" |
9381e3f1 WG |
1092 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1093 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1094 | |
1095 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1096 | [(set (reg CC_REGNUM) |
ec24698e UW |
1097 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1098 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1099 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1100 | "@ |
1101 | cr\t%0,%1 | |
f4f41b4e | 1102 | chi\t%0,%h1 |
ec24698e | 1103 | cfi\t%0,%1 |
575f7c2b UW |
1104 | c\t%0,%1 |
1105 | cy\t%0,%1 | |
19b63d8e | 1106 | #" |
9381e3f1 | 1107 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1108 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1109 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1110 | |
07893d4f | 1111 | ; Compare (signed) instructions |
4023fb28 | 1112 | |
07893d4f | 1113 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1114 | [(set (reg CC_REGNUM) |
963fc8d0 | 1115 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1116 | "d,T,b")) |
963fc8d0 | 1117 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1118 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1119 | "@ |
d40c829f | 1120 | cgfr\t%0,%1 |
963fc8d0 AK |
1121 | cgf\t%0,%1 |
1122 | cgfrl\t%0,%1" | |
1123 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1124 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1125 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1126 | |
9381e3f1 WG |
1127 | |
1128 | ||
07893d4f | 1129 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1130 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1131 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1132 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1133 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1134 | "@ |
d40c829f | 1135 | ch\t%0,%1 |
963fc8d0 AK |
1136 | chy\t%0,%1 |
1137 | chrl\t%0,%1" | |
1138 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1139 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea AK |
1140 | (set_attr "type" "*,*,larl") |
1141 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1142 | |
1143 | (define_insn "*cmphi_ccs_z10" | |
1144 | [(set (reg CC_REGNUM) | |
1145 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1146 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1147 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1148 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1149 | [(set_attr "op_type" "SIL") |
1150 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1151 | |
1152 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1153 | [(set (reg CC_REGNUM) | |
3e4be43f | 1154 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1155 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1156 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1157 | "@ | |
1158 | cgh\t%0,%1 | |
1159 | cghrl\t%0,%1" | |
1160 | [(set_attr "op_type" "RXY,RIL") | |
1161 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1162 | |
963fc8d0 | 1163 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1164 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1165 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1166 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1167 | "d,d,Q, d,d,d,d") | |
1168 | (match_operand:GPR 1 "general_operand" | |
1169 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1170 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1171 | "@ |
3298c037 AK |
1172 | c<g>r\t%0,%1 |
1173 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1174 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1175 | c<g>fi\t%0,%1 |
1176 | c<g>\t%0,%1 | |
963fc8d0 AK |
1177 | c<y>\t%0,%1 |
1178 | c<g>rl\t%0,%1" | |
1179 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1180 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 WG |
1181 | (set_attr "type" "*,*,*,*,*,*,larl") |
1182 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1183 | |
07893d4f UW |
1184 | |
1185 | ; Compare (unsigned) instructions | |
9db1d521 | 1186 | |
963fc8d0 AK |
1187 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1188 | [(set (reg CC_REGNUM) | |
1189 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1190 | "larl_operand" "X"))) | |
1191 | (match_operand:SI 0 "register_operand" "d")))] | |
1192 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1193 | "clhrl\t%0,%1" | |
1194 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1195 | (set_attr "type" "larl") |
1196 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1197 | |
1198 | ; clhrl, clghrl | |
1199 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1200 | [(set (reg CC_REGNUM) | |
1201 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1202 | "larl_operand" "X"))) | |
1203 | (match_operand:GPR 0 "register_operand" "d")))] | |
1204 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1205 | "cl<g>hrl\t%0,%1" | |
1206 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1207 | (set_attr "type" "larl") |
1208 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1209 | |
07893d4f | 1210 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1211 | [(set (reg CC_REGNUM) |
963fc8d0 | 1212 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1213 | "d,T,b")) |
1214 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1215 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1216 | "@ |
d40c829f | 1217 | clgfr\t%0,%1 |
963fc8d0 AK |
1218 | clgf\t%0,%1 |
1219 | clgfrl\t%0,%1" | |
1220 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1221 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1222 | (set_attr "type" "*,*,larl") |
1223 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1224 | |
07893d4f | 1225 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1226 | [(set (reg CC_REGNUM) |
963fc8d0 | 1227 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1228 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1229 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1230 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1231 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1232 | "@ |
d40c829f | 1233 | clgr\t%0,%1 |
ec24698e | 1234 | clgfi\t%0,%1 |
963fc8d0 AK |
1235 | clgrl\t%0,%1 |
1236 | clghsi\t%0,%x1 | |
575f7c2b | 1237 | clg\t%0,%1 |
e221ef54 | 1238 | # |
19b63d8e | 1239 | #" |
963fc8d0 AK |
1240 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1241 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1242 | (set_attr "type" "*,*,larl,*,*,*,*") |
1243 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1244 | |
07893d4f | 1245 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1246 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1247 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1248 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1249 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1250 | "@ |
d40c829f | 1251 | clr\t%0,%1 |
ec24698e | 1252 | clfi\t%0,%o1 |
963fc8d0 AK |
1253 | clrl\t%0,%1 |
1254 | clfhsi\t%0,%x1 | |
d40c829f | 1255 | cl\t%0,%1 |
575f7c2b | 1256 | cly\t%0,%1 |
e221ef54 | 1257 | # |
19b63d8e | 1258 | #" |
963fc8d0 | 1259 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1260 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 WG |
1261 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1262 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1263 | |
07893d4f | 1264 | (define_insn "*cmphi_ccu" |
ae156f85 | 1265 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1266 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1267 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1268 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1269 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1270 | "@ |
fc0ea003 UW |
1271 | clm\t%0,3,%S1 |
1272 | clmy\t%0,3,%S1 | |
963fc8d0 | 1273 | clhhsi\t%0,%1 |
e221ef54 | 1274 | # |
19b63d8e | 1275 | #" |
963fc8d0 | 1276 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1277 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1278 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1279 | |
1280 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1281 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1282 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1283 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1284 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1285 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1286 | "@ |
fc0ea003 UW |
1287 | clm\t%0,1,%S1 |
1288 | clmy\t%0,1,%S1 | |
1289 | cli\t%S0,%b1 | |
1290 | cliy\t%S0,%b1 | |
e221ef54 | 1291 | # |
19b63d8e | 1292 | #" |
9381e3f1 | 1293 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1294 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1295 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1296 | |
1297 | ||
19b63d8e UW |
1298 | ; Block compare (CLC) instruction patterns. |
1299 | ||
1300 | (define_insn "*clc" | |
ae156f85 | 1301 | [(set (reg CC_REGNUM) |
d4f52f0e | 1302 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1303 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1304 | (use (match_operand 2 "const_int_operand" "n"))] | |
1305 | "s390_match_ccmode (insn, CCUmode) | |
1306 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1307 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1308 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1309 | |
1310 | (define_split | |
ae156f85 | 1311 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1312 | (compare (match_operand 0 "memory_operand" "") |
1313 | (match_operand 1 "memory_operand" "")))] | |
1314 | "reload_completed | |
1315 | && s390_match_ccmode (insn, CCUmode) | |
1316 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1317 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1318 | [(parallel | |
1319 | [(set (match_dup 0) (match_dup 1)) | |
1320 | (use (match_dup 2))])] | |
1321 | { | |
1322 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1323 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1324 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1325 | ||
1326 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1327 | operands[0], operands[1]); | |
1328 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1329 | }) | |
1330 | ||
1331 | ||
609e7e80 | 1332 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1333 | |
e325aba2 AK |
1334 | |
1335 | ; load and test instructions turn SNaN into QNaN what is not | |
1336 | ; acceptable if the target will be used afterwards. On the other hand | |
1337 | ; they are quite convenient for implementing comparisons with 0.0. So | |
1338 | ; try to enable them via splitter if the value isn't needed anymore. | |
1339 | ||
609e7e80 | 1340 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1341 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1342 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1343 | (compare (match_operand:FP 0 "register_operand" "f") |
1344 | (match_operand:FP 1 "const0_operand" ""))) | |
1345 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1346 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1347 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1348 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1349 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1350 | |
e325aba2 AK |
1351 | (define_split |
1352 | [(set (match_operand 0 "cc_reg_operand") | |
1353 | (compare (match_operand:FP 1 "register_operand") | |
1354 | (match_operand:FP 2 "const0_operand")))] | |
1355 | "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])" | |
1356 | [(parallel | |
1357 | [(set (match_dup 0) (match_dup 3)) | |
1358 | (clobber (match_dup 1))])] | |
1359 | { | |
1360 | /* s390_match_ccmode requires the compare to have the same CC mode | |
1361 | as the CC destination register. */ | |
1362 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]), | |
1363 | operands[1], operands[2]); | |
1364 | }) | |
1365 | ||
1366 | ||
2de2b3f9 AK |
1367 | ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb |
1368 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb | |
f5905b37 | 1369 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1370 | [(set (reg CC_REGNUM) |
2de2b3f9 AK |
1371 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") |
1372 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
142cd70f | 1373 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1374 | "@ |
609e7e80 | 1375 | c<xde><bt>r\t%0,%1 |
77c585ca | 1376 | c<xde>b\t%0,%1 |
2de2b3f9 AK |
1377 | wfcdb\t%0,%1 |
1378 | wfcsb\t%0,%1" | |
1379 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1380 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1381 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
963fc8d0 AK |
1382 | |
1383 | ; Compare and Branch instructions | |
1384 | ||
1385 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1386 | ; The following instructions do a complementary access of their second |
1387 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1388 | (define_insn "*cmp_and_br_signed_<mode>" |
1389 | [(set (pc) | |
1390 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1391 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1392 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1393 | (label_ref (match_operand 3 "" "")) | |
1394 | (pc))) | |
1395 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1396 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1397 | { |
1398 | if (get_attr_length (insn) == 6) | |
1399 | return which_alternative ? | |
1400 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1401 | else | |
1402 | return which_alternative ? | |
1403 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1404 | } | |
1405 | [(set_attr "op_type" "RIE") | |
1406 | (set_attr "type" "branch") | |
e3cba5e5 | 1407 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1408 | (set (attr "length") |
1409 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1410 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1411 | ; 10 byte for cgr/jg | |
1412 | ||
1413 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1414 | ; The following instructions do a complementary access of their second |
1415 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1416 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1417 | [(set (pc) | |
1418 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1419 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1420 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1421 | (label_ref (match_operand 3 "" "")) | |
1422 | (pc))) | |
1423 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1424 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1425 | { |
1426 | if (get_attr_length (insn) == 6) | |
1427 | return which_alternative ? | |
1428 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1429 | else | |
1430 | return which_alternative ? | |
1431 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1432 | } | |
1433 | [(set_attr "op_type" "RIE") | |
1434 | (set_attr "type" "branch") | |
e3cba5e5 | 1435 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1436 | (set (attr "length") |
1437 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1438 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1439 | ; 10 byte for clgr/jg | |
1440 | ||
b0f86a7e AK |
1441 | ; And now the same two patterns as above but with a negated CC mask. |
1442 | ||
1443 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1444 | ; The following instructions do a complementary access of their second | |
1445 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1446 | (define_insn "*icmp_and_br_signed_<mode>" | |
1447 | [(set (pc) | |
1448 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1449 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1450 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1451 | (pc) | |
1452 | (label_ref (match_operand 3 "" "")))) | |
1453 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1454 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1455 | { |
1456 | if (get_attr_length (insn) == 6) | |
1457 | return which_alternative ? | |
1458 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1459 | else | |
1460 | return which_alternative ? | |
1461 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1462 | } | |
1463 | [(set_attr "op_type" "RIE") | |
1464 | (set_attr "type" "branch") | |
1465 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1466 | (set (attr "length") | |
1467 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1468 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1469 | ; 10 byte for cgr/jg | |
1470 | ||
1471 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1472 | ; The following instructions do a complementary access of their second | |
1473 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1474 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1475 | [(set (pc) | |
1476 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1477 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1478 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1479 | (pc) | |
1480 | (label_ref (match_operand 3 "" "")))) | |
1481 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1482 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1483 | { |
1484 | if (get_attr_length (insn) == 6) | |
1485 | return which_alternative ? | |
1486 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1487 | else | |
1488 | return which_alternative ? | |
1489 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1490 | } | |
1491 | [(set_attr "op_type" "RIE") | |
1492 | (set_attr "type" "branch") | |
1493 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1494 | (set (attr "length") | |
1495 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1496 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1497 | ; 10 byte for clgr/jg | |
1498 | ||
9db1d521 HP |
1499 | ;; |
1500 | ;;- Move instructions. | |
1501 | ;; | |
1502 | ||
1503 | ; | |
1504 | ; movti instruction pattern(s). | |
1505 | ; | |
1506 | ||
3cb9ee2f AK |
1507 | |
1508 | ; Separate out the register pair alternative since constraints (P) are | |
1509 | ; not able to deal with const_wide_int's. But predicates do. | |
1510 | (define_insn "*movti_bigconst" | |
1511 | [(set (match_operand:TI 0 "register_operand" "=d") | |
1512 | (match_operand:TI 1 "reload_const_wide_int_operand" ""))] | |
1513 | "TARGET_ZARCH" | |
1514 | "#") | |
1515 | ||
085261c8 AK |
1516 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1517 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1518 | (define_insn "movti" |
3cb9ee2f AK |
1519 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o") |
1520 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dT,d"))] | |
9602b6a1 | 1521 | "TARGET_ZARCH" |
4023fb28 | 1522 | "@ |
fc0ea003 UW |
1523 | lmg\t%0,%N0,%S1 |
1524 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1525 | vlr\t%v0,%v1 |
1526 | vzero\t%v0 | |
1527 | vone\t%v0 | |
1528 | vlvgp\t%v0,%1,%N1 | |
1529 | # | |
1530 | vl\t%v0,%1 | |
1531 | vst\t%v1,%0 | |
4023fb28 | 1532 | # |
19b63d8e | 1533 | #" |
085261c8 AK |
1534 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1535 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
285363a1 | 1536 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")]) |
4023fb28 UW |
1537 | |
1538 | (define_split | |
1539 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1540 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1541 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1542 | && !s_operand (operands[0], TImode) |
1543 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1544 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1545 | [(set (match_dup 2) (match_dup 4)) |
1546 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1547 | { |
dc65c307 UW |
1548 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1549 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1550 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1551 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1552 | }) | |
1553 | ||
1554 | (define_split | |
1555 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1556 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1557 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1558 | && !s_operand (operands[0], TImode) |
1559 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1560 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1561 | [(set (match_dup 2) (match_dup 4)) | |
1562 | (set (match_dup 3) (match_dup 5))] | |
1563 | { | |
1564 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1565 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1566 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1567 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1568 | }) | |
4023fb28 | 1569 | |
085261c8 AK |
1570 | ; Use part of the TImode target reg to perform the address |
1571 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1572 | ; this splitter is not necessary. | |
4023fb28 UW |
1573 | (define_split |
1574 | [(set (match_operand:TI 0 "register_operand" "") | |
1575 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1576 | "TARGET_ZARCH && reload_completed |
085261c8 | 1577 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1578 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1579 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1580 | { |
1581 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1582 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1583 | s390_load_address (addr, XEXP (operands[1], 0)); |
1584 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1585 | }) |
1586 | ||
833cd70a | 1587 | |
085261c8 AK |
1588 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1589 | ; For the higher order bits we do simply a DImode move while the | |
1590 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1591 | (define_split | |
1592 | [(set (match_operand:TI 0 "register_operand" "") | |
1593 | (match_operand:TI 1 "register_operand" ""))] | |
1594 | "TARGET_VX && reload_completed | |
1595 | && GENERAL_REG_P (operands[0]) | |
1596 | && VECTOR_REG_P (operands[1])" | |
1597 | [(set (match_dup 2) (match_dup 4)) | |
1598 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1599 | UNSPEC_VEC_EXTRACT))] | |
1600 | { | |
1601 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1602 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1603 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1604 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1605 | }) | |
1606 | ||
833cd70a AK |
1607 | ; |
1608 | ; Patterns used for secondary reloads | |
1609 | ; | |
1610 | ||
963fc8d0 AK |
1611 | ; z10 provides move instructions accepting larl memory operands. |
1612 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1613 | ; These patterns are also used for unaligned SI and DI accesses. | |
1614 | ||
085261c8 AK |
1615 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1616 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1617 | (match_operand:ALL 1 "register_operand" "=d") | |
1618 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1619 | "TARGET_Z10" |
1620 | { | |
1621 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1622 | DONE; | |
1623 | }) | |
1624 | ||
085261c8 AK |
1625 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1626 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1627 | (match_operand:ALL 1 "memory_operand" "") | |
1628 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1629 | "TARGET_Z10" |
1630 | { | |
1631 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1632 | DONE; | |
1633 | }) | |
1634 | ||
1635 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1636 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1637 | (match_operand:P 1 "larl_operand" "") | |
1638 | (match_operand:P 2 "register_operand" "=a")])] | |
1639 | "TARGET_Z10" | |
1640 | { | |
1641 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1642 | DONE; | |
1643 | }) | |
1644 | ||
833cd70a AK |
1645 | ; Handles loading a PLUS (load address) expression |
1646 | ||
1647 | (define_expand "reload<mode>_plus" | |
1648 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1649 | (match_operand:P 1 "s390_plus_operand" "") | |
1650 | (match_operand:P 2 "register_operand" "=&a")])] | |
1651 | "" | |
1652 | { | |
1653 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1654 | DONE; | |
1655 | }) | |
1656 | ||
085261c8 AK |
1657 | ; Not all the indirect memory access instructions support the full |
1658 | ; format (long disp + index + base). So whenever a move from/to such | |
1659 | ; an address is required and the instruction cannot deal with it we do | |
1660 | ; a load address into a scratch register first and use this as the new | |
1661 | ; base register. | |
1662 | ; This in particular is used for: | |
1663 | ; - non-offsetable memory accesses for multiword moves | |
1664 | ; - full vector reg moves with long displacements | |
833cd70a | 1665 | |
085261c8 | 1666 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1667 | [(parallel [(match_operand 0 "register_operand" "") |
1668 | (match_operand 1 "" "") | |
1669 | (match_operand:P 2 "register_operand" "=&a")])] | |
1670 | "" | |
1671 | { | |
1672 | gcc_assert (MEM_P (operands[1])); | |
1673 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1674 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1675 | emit_move_insn (operands[0], operands[1]); | |
1676 | DONE; | |
1677 | }) | |
1678 | ||
085261c8 | 1679 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1680 | [(parallel [(match_operand 0 "" "") |
1681 | (match_operand 1 "register_operand" "") | |
1682 | (match_operand:P 2 "register_operand" "=&a")])] | |
1683 | "" | |
dc65c307 | 1684 | { |
9c3c3dcc | 1685 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1686 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1687 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1688 | emit_move_insn (operands[0], operands[1]); | |
1689 | DONE; | |
1690 | }) | |
9db1d521 | 1691 | |
1f9e1fc6 AK |
1692 | (define_expand "reload<mode>_PIC_addr" |
1693 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1694 | (match_operand 1 "larl_operand" "") | |
1695 | (match_operand:P 2 "register_operand" "=a")])] | |
1696 | "" | |
1697 | { | |
0a2aaacc KG |
1698 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1699 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1700 | }) |
1701 | ||
9db1d521 HP |
1702 | ; |
1703 | ; movdi instruction pattern(s). | |
1704 | ; | |
1705 | ||
9db1d521 HP |
1706 | (define_expand "movdi" |
1707 | [(set (match_operand:DI 0 "general_operand" "") | |
1708 | (match_operand:DI 1 "general_operand" ""))] | |
1709 | "" | |
9db1d521 | 1710 | { |
fd3cd001 | 1711 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1712 | if (TARGET_64BIT |
1713 | && (SYMBOLIC_CONST (operands[1]) | |
1714 | || (GET_CODE (operands[1]) == PLUS | |
1715 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1716 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1717 | emit_symbolic_move (operands); |
10bbf137 | 1718 | }) |
9db1d521 | 1719 | |
4023fb28 UW |
1720 | (define_insn "*movdi_larl" |
1721 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1722 | (match_operand:DI 1 "larl_operand" "X"))] | |
1723 | "TARGET_64BIT | |
8e509cf9 | 1724 | && !FP_REG_P (operands[0])" |
d40c829f | 1725 | "larl\t%0,%1" |
4023fb28 | 1726 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1727 | (set_attr "type" "larl") |
1728 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1729 | |
3af8e996 | 1730 | (define_insn "*movdi_64" |
85dae55a | 1731 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1732 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R") |
85dae55a | 1733 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1734 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))] |
9602b6a1 | 1735 | "TARGET_ZARCH" |
85dae55a AK |
1736 | "@ |
1737 | lghi\t%0,%h1 | |
1738 | llihh\t%0,%i1 | |
1739 | llihl\t%0,%i1 | |
1740 | llilh\t%0,%i1 | |
1741 | llill\t%0,%i1 | |
1742 | lgfi\t%0,%1 | |
1743 | llihf\t%0,%k1 | |
1744 | llilf\t%0,%k1 | |
1745 | ldgr\t%0,%1 | |
1746 | lgdr\t%0,%1 | |
1747 | lay\t%0,%a1 | |
963fc8d0 | 1748 | lgrl\t%0,%1 |
85dae55a AK |
1749 | lgr\t%0,%1 |
1750 | lg\t%0,%1 | |
1751 | stg\t%1,%0 | |
1752 | ldr\t%0,%1 | |
1753 | ld\t%0,%1 | |
1754 | ldy\t%0,%1 | |
1755 | std\t%1,%0 | |
1756 | stdy\t%1,%0 | |
963fc8d0 AK |
1757 | stgrl\t%1,%0 |
1758 | mvghi\t%0,%1 | |
85dae55a AK |
1759 | # |
1760 | # | |
1761 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1762 | lam\t%0,%N0,%S1 |
1763 | vleig\t%v0,%h1,0 | |
1764 | vlr\t%v0,%v1 | |
1765 | vlvgg\t%v0,%1,0 | |
1766 | vlgvg\t%0,%v1,0 | |
1767 | vleg\t%v0,%1,0 | |
1768 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1769 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1770 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1771 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1772 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1773 | *,*,*,*,*,*,*") | |
3af8e996 | 1774 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1775 | z10,*,*,*,*,*,longdisp,*,longdisp, |
285363a1 | 1776 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
1777 | (set_attr "z10prop" "z10_fwd_A1, |
1778 | z10_fwd_E1, | |
1779 | z10_fwd_E1, | |
1780 | z10_fwd_E1, | |
1781 | z10_fwd_E1, | |
1782 | z10_fwd_A1, | |
1783 | z10_fwd_E1, | |
1784 | z10_fwd_E1, | |
1785 | *, | |
1786 | *, | |
1787 | z10_fwd_A1, | |
1788 | z10_fwd_A3, | |
1789 | z10_fr_E1, | |
1790 | z10_fwd_A3, | |
1791 | z10_rec, | |
1792 | *, | |
1793 | *, | |
1794 | *, | |
1795 | *, | |
1796 | *, | |
1797 | z10_rec, | |
1798 | z10_super, | |
1799 | *, | |
1800 | *, | |
1801 | *, | |
085261c8 | 1802 | *,*,*,*,*,*,*") |
9381e3f1 | 1803 | ]) |
c5aa1d12 UW |
1804 | |
1805 | (define_split | |
1806 | [(set (match_operand:DI 0 "register_operand" "") | |
1807 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1808 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1809 | [(set (match_dup 2) (match_dup 3)) |
1810 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1811 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1812 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1813 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1814 | ||
1815 | (define_split | |
1816 | [(set (match_operand:DI 0 "register_operand" "") | |
1817 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1818 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1819 | && dead_or_set_p (insn, operands[1])" |
1820 | [(set (match_dup 3) (match_dup 2)) | |
1821 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1822 | (set (match_dup 4) (match_dup 2))] | |
1823 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1824 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1825 | ||
1826 | (define_split | |
1827 | [(set (match_operand:DI 0 "register_operand" "") | |
1828 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1829 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1830 | && !dead_or_set_p (insn, operands[1])" |
1831 | [(set (match_dup 3) (match_dup 2)) | |
1832 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1833 | (set (match_dup 4) (match_dup 2)) | |
1834 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1835 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1836 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1837 | |
1838 | (define_insn "*movdi_31" | |
963fc8d0 | 1839 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1840 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1841 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1842 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1843 | "!TARGET_ZARCH" |
4023fb28 | 1844 | "@ |
fc0ea003 | 1845 | lm\t%0,%N0,%S1 |
c4d50129 | 1846 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1847 | stm\t%1,%N1,%S0 |
c4d50129 | 1848 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1849 | # |
1850 | # | |
d40c829f UW |
1851 | ldr\t%0,%1 |
1852 | ld\t%0,%1 | |
1853 | ldy\t%0,%1 | |
1854 | std\t%1,%0 | |
1855 | stdy\t%1,%0 | |
19b63d8e | 1856 | #" |
f2dc2f86 AK |
1857 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1858 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1859 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1860 | |
1861 | ; For a load from a symbol ref we can use one of the target registers | |
1862 | ; together with larl to load the address. | |
1863 | (define_split | |
1864 | [(set (match_operand:DI 0 "register_operand" "") | |
1865 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1866 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1867 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1868 | [(set (match_dup 2) (match_dup 3)) | |
1869 | (set (match_dup 0) (match_dup 1))] | |
1870 | { | |
1871 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1872 | operands[3] = XEXP (operands[1], 0); | |
1873 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1874 | }) | |
4023fb28 UW |
1875 | |
1876 | (define_split | |
1877 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1878 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1879 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1880 | && !s_operand (operands[0], DImode) |
1881 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1882 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1883 | [(set (match_dup 2) (match_dup 4)) |
1884 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1885 | { |
dc65c307 UW |
1886 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1887 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1888 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1889 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1890 | }) | |
1891 | ||
1892 | (define_split | |
1893 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1894 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1895 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1896 | && !s_operand (operands[0], DImode) |
1897 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1898 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1899 | [(set (match_dup 2) (match_dup 4)) | |
1900 | (set (match_dup 3) (match_dup 5))] | |
1901 | { | |
1902 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1903 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1904 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1905 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1906 | }) | |
9db1d521 | 1907 | |
4023fb28 UW |
1908 | (define_split |
1909 | [(set (match_operand:DI 0 "register_operand" "") | |
1910 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1911 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1912 | && !FP_REG_P (operands[0]) |
4023fb28 | 1913 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1914 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1915 | { |
1916 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1917 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1918 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1919 | }) |
1920 | ||
84817c5d UW |
1921 | (define_peephole2 |
1922 | [(set (match_operand:DI 0 "register_operand" "") | |
1923 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1924 | "TARGET_ZARCH |
84817c5d UW |
1925 | && !FP_REG_P (operands[0]) |
1926 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1927 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1928 | && get_pool_mode (operands[1]) == DImode | |
1929 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1930 | [(set (match_dup 0) (match_dup 2))] | |
1931 | "operands[2] = get_pool_constant (operands[1]);") | |
1932 | ||
7bdff56f UW |
1933 | (define_insn "*la_64" |
1934 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1935 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1936 | "TARGET_64BIT" |
1937 | "@ | |
1938 | la\t%0,%a1 | |
1939 | lay\t%0,%a1" | |
1940 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1941 | (set_attr "type" "la") |
3e4be43f | 1942 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1943 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1944 | |
1945 | (define_peephole2 | |
1946 | [(parallel | |
1947 | [(set (match_operand:DI 0 "register_operand" "") | |
1948 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1949 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1950 | "TARGET_64BIT |
e1d5ee28 | 1951 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1952 | [(set (match_dup 0) (match_dup 1))] |
1953 | "") | |
1954 | ||
1955 | (define_peephole2 | |
1956 | [(set (match_operand:DI 0 "register_operand" "") | |
1957 | (match_operand:DI 1 "register_operand" "")) | |
1958 | (parallel | |
1959 | [(set (match_dup 0) | |
1960 | (plus:DI (match_dup 0) | |
1961 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1962 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1963 | "TARGET_64BIT |
1964 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1965 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1966 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1967 | "") | |
1968 | ||
9db1d521 HP |
1969 | ; |
1970 | ; movsi instruction pattern(s). | |
1971 | ; | |
1972 | ||
9db1d521 HP |
1973 | (define_expand "movsi" |
1974 | [(set (match_operand:SI 0 "general_operand" "") | |
1975 | (match_operand:SI 1 "general_operand" ""))] | |
1976 | "" | |
9db1d521 | 1977 | { |
fd3cd001 | 1978 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1979 | if (!TARGET_64BIT |
1980 | && (SYMBOLIC_CONST (operands[1]) | |
1981 | || (GET_CODE (operands[1]) == PLUS | |
1982 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1983 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1984 | emit_symbolic_move (operands); |
10bbf137 | 1985 | }) |
9db1d521 | 1986 | |
9e8327e3 UW |
1987 | (define_insn "*movsi_larl" |
1988 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1989 | (match_operand:SI 1 "larl_operand" "X"))] | |
1990 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1991 | && !FP_REG_P (operands[0])" | |
1992 | "larl\t%0,%1" | |
1993 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1994 | (set_attr "type" "larl") |
729e750f | 1995 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1996 | |
f19a9af7 | 1997 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1998 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 1999 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 2000 | (match_operand:SI 1 "general_operand" |
3e4be43f | 2001 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 2002 | "TARGET_ZARCH" |
9db1d521 | 2003 | "@ |
f19a9af7 AK |
2004 | lhi\t%0,%h1 |
2005 | llilh\t%0,%i1 | |
2006 | llill\t%0,%i1 | |
ec24698e | 2007 | iilf\t%0,%o1 |
f19a9af7 | 2008 | lay\t%0,%a1 |
963fc8d0 | 2009 | lrl\t%0,%1 |
d40c829f UW |
2010 | lr\t%0,%1 |
2011 | l\t%0,%1 | |
2012 | ly\t%0,%1 | |
2013 | st\t%1,%0 | |
2014 | sty\t%1,%0 | |
ae1c6198 | 2015 | ldr\t%0,%1 |
d40c829f | 2016 | ler\t%0,%1 |
085261c8 | 2017 | lde\t%0,%1 |
d40c829f UW |
2018 | le\t%0,%1 |
2019 | ley\t%0,%1 | |
2020 | ste\t%1,%0 | |
2021 | stey\t%1,%0 | |
c5aa1d12 UW |
2022 | ear\t%0,%1 |
2023 | sar\t%0,%1 | |
2024 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
2025 | strl\t%1,%0 |
2026 | mvhi\t%0,%1 | |
085261c8 AK |
2027 | lam\t%0,%0,%S1 |
2028 | vleif\t%v0,%h1,0 | |
2029 | vlr\t%v0,%v1 | |
2030 | vlvgf\t%v0,%1,0 | |
2031 | vlgvf\t%0,%v1,0 | |
2032 | vlef\t%v0,%1,0 | |
2033 | vstef\t%v1,%0,0" | |
963fc8d0 | 2034 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 2035 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
2036 | (set_attr "type" "*, |
2037 | *, | |
2038 | *, | |
2039 | *, | |
2040 | la, | |
2041 | larl, | |
2042 | lr, | |
2043 | load, | |
2044 | load, | |
2045 | store, | |
2046 | store, | |
2047 | floadsf, | |
2048 | floadsf, | |
2049 | floadsf, | |
085261c8 AK |
2050 | floadsf, |
2051 | floadsf, | |
9381e3f1 WG |
2052 | fstoresf, |
2053 | fstoresf, | |
2054 | *, | |
2055 | *, | |
2056 | *, | |
2057 | larl, | |
2058 | *, | |
085261c8 | 2059 | *,*,*,*,*,*,*") |
963fc8d0 | 2060 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2061 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2062 | (set_attr "z10prop" "z10_fwd_A1, |
2063 | z10_fwd_E1, | |
2064 | z10_fwd_E1, | |
2065 | z10_fwd_A1, | |
2066 | z10_fwd_A1, | |
2067 | z10_fwd_A3, | |
2068 | z10_fr_E1, | |
2069 | z10_fwd_A3, | |
2070 | z10_fwd_A3, | |
729e750f | 2071 | z10_rec, |
9381e3f1 WG |
2072 | z10_rec, |
2073 | *, | |
2074 | *, | |
2075 | *, | |
2076 | *, | |
2077 | *, | |
085261c8 AK |
2078 | *, |
2079 | *, | |
9381e3f1 WG |
2080 | z10_super_E1, |
2081 | z10_super, | |
2082 | *, | |
2083 | z10_rec, | |
2084 | z10_super, | |
085261c8 | 2085 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
2086 | |
2087 | (define_insn "*movsi_esa" | |
085261c8 AK |
2088 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2089 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2090 | "!TARGET_ZARCH" |
2091 | "@ | |
2092 | lhi\t%0,%h1 | |
2093 | lr\t%0,%1 | |
2094 | l\t%0,%1 | |
2095 | st\t%1,%0 | |
ae1c6198 | 2096 | ldr\t%0,%1 |
f19a9af7 | 2097 | ler\t%0,%1 |
085261c8 | 2098 | lde\t%0,%1 |
f19a9af7 AK |
2099 | le\t%0,%1 |
2100 | ste\t%1,%0 | |
c5aa1d12 UW |
2101 | ear\t%0,%1 |
2102 | sar\t%0,%1 | |
2103 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2104 | lam\t%0,%0,%S1" |
ae1c6198 | 2105 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2106 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2107 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2108 | z10_super,*,*") | |
285363a1 | 2109 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2110 | ]) |
9db1d521 | 2111 | |
84817c5d UW |
2112 | (define_peephole2 |
2113 | [(set (match_operand:SI 0 "register_operand" "") | |
2114 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2115 | "!FP_REG_P (operands[0]) | |
2116 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2117 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2118 | && get_pool_mode (operands[1]) == SImode | |
2119 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2120 | [(set (match_dup 0) (match_dup 2))] | |
2121 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2122 | |
7bdff56f UW |
2123 | (define_insn "*la_31" |
2124 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2125 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2126 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2127 | "@ | |
2128 | la\t%0,%a1 | |
2129 | lay\t%0,%a1" | |
2130 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2131 | (set_attr "type" "la") |
3e4be43f | 2132 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2133 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2134 | |
2135 | (define_peephole2 | |
2136 | [(parallel | |
2137 | [(set (match_operand:SI 0 "register_operand" "") | |
2138 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2139 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2140 | "!TARGET_64BIT |
e1d5ee28 | 2141 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2142 | [(set (match_dup 0) (match_dup 1))] |
2143 | "") | |
2144 | ||
2145 | (define_peephole2 | |
2146 | [(set (match_operand:SI 0 "register_operand" "") | |
2147 | (match_operand:SI 1 "register_operand" "")) | |
2148 | (parallel | |
2149 | [(set (match_dup 0) | |
2150 | (plus:SI (match_dup 0) | |
2151 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2152 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2153 | "!TARGET_64BIT |
2154 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2155 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2156 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2157 | "") | |
2158 | ||
2159 | (define_insn "*la_31_and" | |
2160 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2161 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2162 | (const_int 2147483647)))] |
2163 | "!TARGET_64BIT" | |
2164 | "@ | |
2165 | la\t%0,%a1 | |
2166 | lay\t%0,%a1" | |
2167 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2168 | (set_attr "type" "la") |
3e4be43f | 2169 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2170 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2171 | |
2172 | (define_insn_and_split "*la_31_and_cc" | |
2173 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2174 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2175 | (const_int 2147483647))) | |
ae156f85 | 2176 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2177 | "!TARGET_64BIT" |
2178 | "#" | |
2179 | "&& reload_completed" | |
2180 | [(set (match_dup 0) | |
2181 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2182 | "" | |
2183 | [(set_attr "op_type" "RX") | |
2184 | (set_attr "type" "la")]) | |
2185 | ||
2186 | (define_insn "force_la_31" | |
2187 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2188 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2189 | (use (const_int 0))] |
2190 | "!TARGET_64BIT" | |
2191 | "@ | |
2192 | la\t%0,%a1 | |
2193 | lay\t%0,%a1" | |
2194 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2195 | (set_attr "type" "la") |
3e4be43f | 2196 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2197 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2198 | |
9db1d521 HP |
2199 | ; |
2200 | ; movhi instruction pattern(s). | |
2201 | ; | |
2202 | ||
02ed3c5e UW |
2203 | (define_expand "movhi" |
2204 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2205 | (match_operand:HI 1 "general_operand" ""))] | |
2206 | "" | |
2207 | { | |
2f7e5a0d | 2208 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2209 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2210 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2211 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2212 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2213 | { |
2214 | rtx tmp = gen_reg_rtx (SImode); | |
2215 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2216 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2217 | operands[1] = gen_lowpart (HImode, tmp); |
2218 | } | |
2219 | }) | |
2220 | ||
2221 | (define_insn "*movhi" | |
3e4be43f UW |
2222 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2223 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2224 | "" |
2225 | "@ | |
d40c829f UW |
2226 | lr\t%0,%1 |
2227 | lhi\t%0,%h1 | |
2228 | lh\t%0,%1 | |
2229 | lhy\t%0,%1 | |
963fc8d0 | 2230 | lhrl\t%0,%1 |
d40c829f UW |
2231 | sth\t%1,%0 |
2232 | sthy\t%1,%0 | |
963fc8d0 | 2233 | sthrl\t%1,%0 |
085261c8 AK |
2234 | mvhhi\t%0,%1 |
2235 | vleih\t%v0,%h1,0 | |
2236 | vlr\t%v0,%v1 | |
2237 | vlvgh\t%v0,%1,0 | |
2238 | vlgvh\t%0,%v1,0 | |
2239 | vleh\t%v0,%1,0 | |
2240 | vsteh\t%v1,%0,0" | |
2241 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2242 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2243 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2244 | (set_attr "z10prop" "z10_fr_E1, |
2245 | z10_fwd_A1, | |
2246 | z10_super_E1, | |
2247 | z10_super_E1, | |
2248 | z10_super_E1, | |
729e750f | 2249 | z10_rec, |
9381e3f1 WG |
2250 | z10_rec, |
2251 | z10_rec, | |
085261c8 | 2252 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2253 | |
84817c5d UW |
2254 | (define_peephole2 |
2255 | [(set (match_operand:HI 0 "register_operand" "") | |
2256 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2257 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2258 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2259 | && get_pool_mode (operands[1]) == HImode | |
2260 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2261 | [(set (match_dup 0) (match_dup 2))] | |
2262 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2263 | |
9db1d521 HP |
2264 | ; |
2265 | ; movqi instruction pattern(s). | |
2266 | ; | |
2267 | ||
02ed3c5e UW |
2268 | (define_expand "movqi" |
2269 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2270 | (match_operand:QI 1 "general_operand" ""))] | |
2271 | "" | |
2272 | { | |
c19ec8f9 | 2273 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2274 | is just as fast as a QImode load. */ |
b3a13419 | 2275 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2276 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2277 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2278 | { |
9602b6a1 AK |
2279 | rtx tmp = gen_reg_rtx (DImode); |
2280 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2281 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2282 | operands[1] = gen_lowpart (QImode, tmp); |
2283 | } | |
2284 | }) | |
4023fb28 | 2285 | |
02ed3c5e | 2286 | (define_insn "*movqi" |
3e4be43f UW |
2287 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2288 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2289 | "" |
2290 | "@ | |
d40c829f UW |
2291 | lr\t%0,%1 |
2292 | lhi\t%0,%b1 | |
2293 | ic\t%0,%1 | |
2294 | icy\t%0,%1 | |
2295 | stc\t%1,%0 | |
2296 | stcy\t%1,%0 | |
fc0ea003 | 2297 | mvi\t%S0,%b1 |
0a88561f | 2298 | mviy\t%S0,%b1 |
085261c8 AK |
2299 | # |
2300 | vleib\t%v0,%b1,0 | |
2301 | vlr\t%v0,%v1 | |
2302 | vlvgb\t%v0,%1,0 | |
2303 | vlgvb\t%0,%v1,0 | |
2304 | vleb\t%v0,%1,0 | |
2305 | vsteb\t%v1,%0,0" | |
2306 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2307 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2308 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2309 | (set_attr "z10prop" "z10_fr_E1, |
2310 | z10_fwd_A1, | |
2311 | z10_super_E1, | |
2312 | z10_super_E1, | |
729e750f | 2313 | z10_rec, |
9381e3f1 WG |
2314 | z10_rec, |
2315 | z10_super, | |
0a88561f | 2316 | z10_super, |
085261c8 | 2317 | *,*,*,*,*,*,*")]) |
9db1d521 | 2318 | |
84817c5d UW |
2319 | (define_peephole2 |
2320 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2321 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2322 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2323 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2324 | && get_pool_mode (operands[1]) == QImode | |
2325 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2326 | [(set (match_dup 0) (match_dup 2))] | |
2327 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2328 | |
9db1d521 | 2329 | ; |
05b9aaaa | 2330 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2331 | ; |
2332 | ||
2333 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2334 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2335 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2336 | "" |
d3632d41 | 2337 | "@ |
d40c829f UW |
2338 | ic\t%0,%1 |
2339 | icy\t%0,%1" | |
9381e3f1 | 2340 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2341 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2342 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2343 | |
2344 | ; | |
2345 | ; movstricthi instruction pattern(s). | |
2346 | ; | |
2347 | ||
2348 | (define_insn "*movstricthi" | |
d3632d41 | 2349 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2350 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2351 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2352 | "" |
d3632d41 | 2353 | "@ |
fc0ea003 UW |
2354 | icm\t%0,3,%S1 |
2355 | icmy\t%0,3,%S1" | |
9381e3f1 | 2356 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2357 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2358 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2359 | |
2360 | ; | |
2361 | ; movstrictsi instruction pattern(s). | |
2362 | ; | |
2363 | ||
05b9aaaa | 2364 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2365 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2366 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2367 | "TARGET_ZARCH" |
9db1d521 | 2368 | "@ |
d40c829f UW |
2369 | lr\t%0,%1 |
2370 | l\t%0,%1 | |
c5aa1d12 UW |
2371 | ly\t%0,%1 |
2372 | ear\t%0,%1" | |
2373 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2374 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2375 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2376 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2377 | |
f61a2c7d | 2378 | ; |
609e7e80 | 2379 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2380 | ; |
2381 | ||
609e7e80 AK |
2382 | (define_expand "mov<mode>" |
2383 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2384 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2385 | "" |
2386 | "") | |
2387 | ||
609e7e80 | 2388 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2389 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2390 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2391 | "TARGET_ZARCH" |
f61a2c7d | 2392 | "@ |
65b1d8ea | 2393 | lzxr\t%0 |
f61a2c7d AK |
2394 | lxr\t%0,%1 |
2395 | # | |
2396 | # | |
2397 | lmg\t%0,%N0,%S1 | |
2398 | stmg\t%1,%N1,%S0 | |
2399 | # | |
f61a2c7d | 2400 | #" |
65b1d8ea AK |
2401 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2402 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2403 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2404 | |
609e7e80 | 2405 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2406 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2407 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2408 | "!TARGET_ZARCH" |
f61a2c7d | 2409 | "@ |
65b1d8ea | 2410 | lzxr\t%0 |
f61a2c7d AK |
2411 | lxr\t%0,%1 |
2412 | # | |
f61a2c7d | 2413 | #" |
65b1d8ea AK |
2414 | [(set_attr "op_type" "RRE,RRE,*,*") |
2415 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2416 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2417 | |
2418 | ; TFmode in GPRs splitters | |
2419 | ||
2420 | (define_split | |
609e7e80 AK |
2421 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2422 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2423 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2424 | && !s_operand (operands[0], <MODE>mode) |
2425 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2426 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2427 | [(set (match_dup 2) (match_dup 4)) |
2428 | (set (match_dup 3) (match_dup 5))] | |
2429 | { | |
609e7e80 AK |
2430 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2431 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2432 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2433 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2434 | }) |
2435 | ||
2436 | (define_split | |
609e7e80 AK |
2437 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2438 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2439 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2440 | && !s_operand (operands[0], <MODE>mode) |
2441 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2442 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2443 | [(set (match_dup 2) (match_dup 4)) |
2444 | (set (match_dup 3) (match_dup 5))] | |
2445 | { | |
609e7e80 AK |
2446 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2447 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2448 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2449 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2450 | }) |
2451 | ||
2452 | (define_split | |
609e7e80 AK |
2453 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2454 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2455 | "TARGET_ZARCH && reload_completed |
085261c8 | 2456 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2457 | && !s_operand (operands[1], VOIDmode)" |
2458 | [(set (match_dup 0) (match_dup 1))] | |
2459 | { | |
609e7e80 | 2460 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2461 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2462 | s390_load_address (addr, XEXP (operands[1], 0)); |
2463 | operands[1] = replace_equiv_address (operands[1], addr); | |
2464 | }) | |
2465 | ||
7b6baae1 | 2466 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2467 | |
2468 | (define_split | |
609e7e80 AK |
2469 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2470 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2471 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2472 | && FP_REG_P (operands[0])" |
2473 | [(set (match_dup 2) (match_dup 4)) | |
2474 | (set (match_dup 3) (match_dup 5))] | |
2475 | { | |
609e7e80 AK |
2476 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2477 | <MODE>mode, 0); | |
2478 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2479 | <MODE>mode, 8); | |
2480 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2481 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2482 | }) |
2483 | ||
2484 | (define_split | |
609e7e80 AK |
2485 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2486 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2487 | "reload_completed && offsettable_memref_p (operands[0]) |
2488 | && FP_REG_P (operands[1])" | |
2489 | [(set (match_dup 2) (match_dup 4)) | |
2490 | (set (match_dup 3) (match_dup 5))] | |
2491 | { | |
609e7e80 AK |
2492 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2493 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2494 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2495 | <MODE>mode, 0); | |
2496 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2497 | <MODE>mode, 8); | |
f61a2c7d AK |
2498 | }) |
2499 | ||
9db1d521 | 2500 | ; |
609e7e80 | 2501 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2502 | ; |
2503 | ||
609e7e80 AK |
2504 | (define_expand "mov<mode>" |
2505 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2506 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2507 | "" |
13c025c1 | 2508 | "") |
9db1d521 | 2509 | |
609e7e80 AK |
2510 | (define_insn "*mov<mode>_64dfp" |
2511 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2512 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2513 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2514 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2515 | "TARGET_DFP" |
85dae55a | 2516 | "@ |
65b1d8ea | 2517 | lzdr\t%0 |
85dae55a AK |
2518 | ldr\t%0,%1 |
2519 | ldgr\t%0,%1 | |
2520 | lgdr\t%0,%1 | |
2521 | ld\t%0,%1 | |
2522 | ldy\t%0,%1 | |
2523 | std\t%1,%0 | |
2524 | stdy\t%1,%0 | |
45e5214c | 2525 | lghi\t%0,0 |
85dae55a | 2526 | lgr\t%0,%1 |
085261c8 | 2527 | lgrl\t%0,%1 |
85dae55a | 2528 | lg\t%0,%1 |
085261c8 AK |
2529 | stgrl\t%1,%0 |
2530 | stg\t%1,%0 | |
2531 | vlr\t%v0,%v1 | |
590961cf | 2532 | vleig\t%v0,0,0 |
085261c8 AK |
2533 | vlvgg\t%v0,%1,0 |
2534 | vlgvg\t%0,%v1,0 | |
2535 | vleg\t%0,%1,0 | |
2536 | vsteg\t%1,%0,0" | |
590961cf | 2537 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2538 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2539 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2540 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
2541 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")]) | |
85dae55a | 2542 | |
609e7e80 | 2543 | (define_insn "*mov<mode>_64" |
590961cf AK |
2544 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2545 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2546 | "TARGET_ZARCH" |
9db1d521 | 2547 | "@ |
65b1d8ea | 2548 | lzdr\t%0 |
d40c829f UW |
2549 | ldr\t%0,%1 |
2550 | ld\t%0,%1 | |
2551 | ldy\t%0,%1 | |
2552 | std\t%1,%0 | |
2553 | stdy\t%1,%0 | |
45e5214c | 2554 | lghi\t%0,0 |
d40c829f | 2555 | lgr\t%0,%1 |
085261c8 | 2556 | lgrl\t%0,%1 |
d40c829f | 2557 | lg\t%0,%1 |
085261c8 | 2558 | stgrl\t%1,%0 |
590961cf AK |
2559 | stg\t%1,%0" |
2560 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2561 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2562 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2563 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2564 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")]) | |
609e7e80 AK |
2565 | |
2566 | (define_insn "*mov<mode>_31" | |
2567 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2568 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2569 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2570 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2571 | "!TARGET_ZARCH" |
9db1d521 | 2572 | "@ |
65b1d8ea | 2573 | lzdr\t%0 |
d40c829f UW |
2574 | ldr\t%0,%1 |
2575 | ld\t%0,%1 | |
2576 | ldy\t%0,%1 | |
2577 | std\t%1,%0 | |
2578 | stdy\t%1,%0 | |
fc0ea003 | 2579 | lm\t%0,%N0,%S1 |
c4d50129 | 2580 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2581 | stm\t%1,%N1,%S0 |
c4d50129 | 2582 | stmy\t%1,%N1,%S0 |
4023fb28 | 2583 | # |
19b63d8e | 2584 | #" |
65b1d8ea AK |
2585 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2586 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2587 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2588 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2589 | |
2590 | (define_split | |
609e7e80 AK |
2591 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2592 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2593 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2594 | && !s_operand (operands[0], <MODE>mode) |
2595 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2596 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2597 | [(set (match_dup 2) (match_dup 4)) |
2598 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2599 | { |
609e7e80 AK |
2600 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2601 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2602 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2603 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2604 | }) |
2605 | ||
2606 | (define_split | |
609e7e80 AK |
2607 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2608 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2609 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2610 | && !s_operand (operands[0], <MODE>mode) |
2611 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2612 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2613 | [(set (match_dup 2) (match_dup 4)) |
2614 | (set (match_dup 3) (match_dup 5))] | |
2615 | { | |
609e7e80 AK |
2616 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2617 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2618 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2619 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2620 | }) |
9db1d521 | 2621 | |
4023fb28 | 2622 | (define_split |
609e7e80 AK |
2623 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2624 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2625 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2626 | && !FP_REG_P (operands[0]) |
4023fb28 | 2627 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2628 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2629 | { |
609e7e80 | 2630 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2631 | s390_load_address (addr, XEXP (operands[1], 0)); |
2632 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2633 | }) |
2634 | ||
9db1d521 | 2635 | ; |
609e7e80 | 2636 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2637 | ; |
2638 | ||
609e7e80 AK |
2639 | (define_insn "mov<mode>" |
2640 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2641 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2642 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2643 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2644 | "" |
9db1d521 | 2645 | "@ |
65b1d8ea | 2646 | lzer\t%0 |
ae1c6198 | 2647 | ldr\t%0,%1 |
d40c829f | 2648 | ler\t%0,%1 |
085261c8 | 2649 | lde\t%0,%1 |
d40c829f UW |
2650 | le\t%0,%1 |
2651 | ley\t%0,%1 | |
2652 | ste\t%1,%0 | |
2653 | stey\t%1,%0 | |
45e5214c | 2654 | lhi\t%0,0 |
d40c829f | 2655 | lr\t%0,%1 |
085261c8 | 2656 | lrl\t%0,%1 |
d40c829f UW |
2657 | l\t%0,%1 |
2658 | ly\t%0,%1 | |
085261c8 | 2659 | strl\t%1,%0 |
d40c829f | 2660 | st\t%1,%0 |
085261c8 AK |
2661 | sty\t%1,%0 |
2662 | vlr\t%v0,%v1 | |
298f4647 | 2663 | vleif\t%v0,0,0 |
085261c8 AK |
2664 | vlvgf\t%v0,%1,0 |
2665 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2666 | vlef\t%0,%1,0 |
2667 | vstef\t%1,%0,0" | |
ae1c6198 | 2668 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2669 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2670 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2671 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
285363a1 | 2672 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")]) |
4023fb28 | 2673 | |
9dc62c00 AK |
2674 | ; |
2675 | ; movcc instruction pattern | |
2676 | ; | |
2677 | ||
2678 | (define_insn "movcc" | |
2679 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2680 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2681 | "" |
2682 | "@ | |
2683 | lr\t%0,%1 | |
2684 | tmh\t%1,12288 | |
2685 | ipm\t%0 | |
a71f0749 DV |
2686 | l\t%0,%1 |
2687 | ly\t%0,%1 | |
2688 | st\t%1,%0 | |
2689 | sty\t%1,%0" | |
8dd3b235 | 2690 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2691 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2692 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2693 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2694 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2695 | |
19b63d8e UW |
2696 | ; |
2697 | ; Block move (MVC) patterns. | |
2698 | ; | |
2699 | ||
2700 | (define_insn "*mvc" | |
2701 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2702 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2703 | (use (match_operand 2 "const_int_operand" "n"))] | |
2704 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2705 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2706 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2707 | |
0a88561f AK |
2708 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2709 | ; order to have it implemented with mvc. | |
2710 | ||
2711 | (define_split | |
2712 | [(set (match_operand:QI 0 "memory_operand" "") | |
2713 | (match_operand:QI 1 "memory_operand" ""))] | |
2714 | "reload_completed" | |
2715 | [(parallel | |
2716 | [(set (match_dup 0) (match_dup 1)) | |
2717 | (use (const_int 1))])] | |
2718 | { | |
2719 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2720 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2721 | }) | |
2722 | ||
2723 | ||
19b63d8e UW |
2724 | (define_peephole2 |
2725 | [(parallel | |
2726 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2727 | (match_operand:BLK 1 "memory_operand" "")) | |
2728 | (use (match_operand 2 "const_int_operand" ""))]) | |
2729 | (parallel | |
2730 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2731 | (match_operand:BLK 4 "memory_operand" "")) | |
2732 | (use (match_operand 5 "const_int_operand" ""))])] | |
f9dcf14a AK |
2733 | "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) |
2734 | || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) | |
2735 | && s390_offset_p (operands[0], operands[3], operands[2]) | |
19b63d8e | 2736 | && s390_offset_p (operands[1], operands[4], operands[2]) |
9381e3f1 | 2737 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2738 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2739 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2740 | [(parallel | |
2741 | [(set (match_dup 6) (match_dup 7)) | |
2742 | (use (match_dup 8))])] | |
2743 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2744 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2745 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2746 | ||
f9dcf14a AK |
2747 | (define_peephole2 |
2748 | [(parallel | |
2749 | [(set (match_operand:BLK 0 "plus16_Q_operand" "") | |
2750 | (match_operand:BLK 1 "plus16_Q_operand" "")) | |
2751 | (use (match_operand 2 "const_int_operand" ""))])] | |
2752 | "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" | |
2753 | [(parallel | |
2754 | [(set (match_dup 0) (match_dup 1)) | |
2755 | (use (const_int 16))]) | |
2756 | (parallel | |
2757 | [(set (match_dup 3) (match_dup 4)) | |
2758 | (use (match_dup 5))])] | |
2759 | "operands[3] = change_address (operands[0], VOIDmode, | |
2760 | plus_constant (Pmode, XEXP (operands[0], 0), 16)); | |
2761 | operands[4] = change_address (operands[1], VOIDmode, | |
2762 | plus_constant (Pmode, XEXP (operands[1], 0), 16)); | |
2763 | operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") | |
2764 | ||
19b63d8e | 2765 | |
9db1d521 HP |
2766 | ; |
2767 | ; load_multiple pattern(s). | |
2768 | ; | |
22ea6b4f UW |
2769 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2770 | ; we currently support load_multiple/store_multiple only after reload. | |
2771 | ; | |
9db1d521 HP |
2772 | |
2773 | (define_expand "load_multiple" | |
2774 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2775 | (match_operand 1 "" "")) | |
2776 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2777 | "reload_completed" |
9db1d521 | 2778 | { |
ef4bddc2 | 2779 | machine_mode mode; |
9db1d521 HP |
2780 | int regno; |
2781 | int count; | |
2782 | rtx from; | |
4023fb28 | 2783 | int i, off; |
9db1d521 HP |
2784 | |
2785 | /* Support only loading a constant number of fixed-point registers from | |
2786 | memory and only bother with this if more than two */ | |
2787 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2788 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2789 | || INTVAL (operands[2]) > 16 |
2790 | || GET_CODE (operands[1]) != MEM | |
2791 | || GET_CODE (operands[0]) != REG | |
2792 | || REGNO (operands[0]) >= 16) | |
2793 | FAIL; | |
2794 | ||
2795 | count = INTVAL (operands[2]); | |
2796 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2797 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2798 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2799 | FAIL; |
9db1d521 HP |
2800 | |
2801 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2802 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2803 | { |
2804 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2805 | { | |
2806 | from = XEXP (operands[1], 0); | |
2807 | off = 0; | |
2808 | } | |
2809 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2810 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2811 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2812 | { | |
2813 | from = XEXP (XEXP (operands[1], 0), 0); | |
2814 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2815 | } | |
2816 | else | |
2817 | FAIL; | |
4023fb28 UW |
2818 | } |
2819 | else | |
2820 | { | |
2821 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2822 | off = 0; | |
2823 | } | |
9db1d521 HP |
2824 | |
2825 | for (i = 0; i < count; i++) | |
2826 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2827 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2828 | change_address (operands[1], mode, |
0a81f074 RS |
2829 | plus_constant (Pmode, from, |
2830 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2831 | }) |
9db1d521 HP |
2832 | |
2833 | (define_insn "*load_multiple_di" | |
2834 | [(match_parallel 0 "load_multiple_operation" | |
2835 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2836 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2837 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2838 | { |
2839 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2840 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2841 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2842 | } |
d3632d41 | 2843 | [(set_attr "op_type" "RSY") |
4023fb28 | 2844 | (set_attr "type" "lm")]) |
9db1d521 HP |
2845 | |
2846 | (define_insn "*load_multiple_si" | |
2847 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2848 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2849 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2850 | "reload_completed" |
9db1d521 HP |
2851 | { |
2852 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2853 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2854 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2855 | } |
d3632d41 | 2856 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2857 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2858 | (set_attr "type" "lm")]) |
9db1d521 HP |
2859 | |
2860 | ; | |
c7453384 | 2861 | ; store multiple pattern(s). |
9db1d521 HP |
2862 | ; |
2863 | ||
2864 | (define_expand "store_multiple" | |
2865 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2866 | (match_operand 1 "" "")) | |
2867 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2868 | "reload_completed" |
9db1d521 | 2869 | { |
ef4bddc2 | 2870 | machine_mode mode; |
9db1d521 HP |
2871 | int regno; |
2872 | int count; | |
2873 | rtx to; | |
4023fb28 | 2874 | int i, off; |
9db1d521 HP |
2875 | |
2876 | /* Support only storing a constant number of fixed-point registers to | |
2877 | memory and only bother with this if more than two. */ | |
2878 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2879 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2880 | || INTVAL (operands[2]) > 16 |
2881 | || GET_CODE (operands[0]) != MEM | |
2882 | || GET_CODE (operands[1]) != REG | |
2883 | || REGNO (operands[1]) >= 16) | |
2884 | FAIL; | |
2885 | ||
2886 | count = INTVAL (operands[2]); | |
2887 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2888 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2889 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2890 | FAIL; |
9db1d521 HP |
2891 | |
2892 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2893 | |
b3a13419 | 2894 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2895 | { |
2896 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2897 | { | |
2898 | to = XEXP (operands[0], 0); | |
2899 | off = 0; | |
2900 | } | |
2901 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2902 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2903 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2904 | { | |
2905 | to = XEXP (XEXP (operands[0], 0), 0); | |
2906 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2907 | } | |
2908 | else | |
2909 | FAIL; | |
4023fb28 | 2910 | } |
c7453384 | 2911 | else |
4023fb28 UW |
2912 | { |
2913 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2914 | off = 0; | |
2915 | } | |
9db1d521 HP |
2916 | |
2917 | for (i = 0; i < count; i++) | |
2918 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2919 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2920 | plus_constant (Pmode, to, |
2921 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2922 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2923 | }) |
9db1d521 HP |
2924 | |
2925 | (define_insn "*store_multiple_di" | |
2926 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2927 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2928 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2929 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2930 | { |
2931 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2932 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2933 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2934 | } |
d3632d41 | 2935 | [(set_attr "op_type" "RSY") |
4023fb28 | 2936 | (set_attr "type" "stm")]) |
9db1d521 HP |
2937 | |
2938 | ||
2939 | (define_insn "*store_multiple_si" | |
2940 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2941 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2942 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2943 | "reload_completed" |
9db1d521 HP |
2944 | { |
2945 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2946 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2947 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2948 | } |
d3632d41 | 2949 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2950 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2951 | (set_attr "type" "stm")]) |
9db1d521 HP |
2952 | |
2953 | ;; | |
2954 | ;; String instructions. | |
2955 | ;; | |
2956 | ||
963fc8d0 | 2957 | (define_insn "*execute_rl" |
2771c2f9 | 2958 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2959 | [(unspec [(match_operand 1 "register_operand" "a") |
2960 | (match_operand 2 "" "") | |
2961 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2962 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2963 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2964 | "exrl\t%1,%3" | |
2965 | [(set_attr "op_type" "RIL") | |
2966 | (set_attr "type" "cs")]) | |
2967 | ||
9bb86f41 | 2968 | (define_insn "*execute" |
2771c2f9 | 2969 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2970 | [(unspec [(match_operand 1 "register_operand" "a") |
2971 | (match_operand:BLK 2 "memory_operand" "R") | |
2972 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2973 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2974 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2975 | "ex\t%1,%2" | |
29a74354 UW |
2976 | [(set_attr "op_type" "RX") |
2977 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2978 | |
2979 | ||
91d39d71 UW |
2980 | ; |
2981 | ; strlenM instruction pattern(s). | |
2982 | ; | |
2983 | ||
9db2f16d | 2984 | (define_expand "strlen<mode>" |
085261c8 AK |
2985 | [(match_operand:P 0 "register_operand" "") ; result |
2986 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2987 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2988 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2989 | "" | |
2990 | { | |
2991 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2992 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2993 | operands[2], operands[3])); | |
2994 | else | |
2995 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2996 | ||
2997 | DONE; | |
2998 | }) | |
2999 | ||
3000 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 3001 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 3002 | (parallel |
91d39d71 | 3003 | [(set (match_dup 4) |
9db2f16d | 3004 | (unspec:P [(const_int 0) |
91d39d71 | 3005 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 3006 | (reg:SI 0) |
91d39d71 | 3007 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3008 | (clobber (scratch:P)) |
ae156f85 | 3009 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 3010 | (parallel |
9db2f16d AS |
3011 | [(set (match_operand:P 0 "register_operand" "") |
3012 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 3013 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 3014 | "" |
91d39d71 | 3015 | { |
9db2f16d AS |
3016 | operands[4] = gen_reg_rtx (Pmode); |
3017 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
3018 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3019 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
3020 | }) | |
3021 | ||
9db2f16d AS |
3022 | (define_insn "*strlen<mode>" |
3023 | [(set (match_operand:P 0 "register_operand" "=a") | |
3024 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
3025 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 3026 | (reg:SI 0) |
91d39d71 | 3027 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3028 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 3029 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 3030 | "" |
91d39d71 | 3031 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
3032 | [(set_attr "length" "8") |
3033 | (set_attr "type" "vs")]) | |
91d39d71 | 3034 | |
ccbdc0d4 AS |
3035 | ; |
3036 | ; cmpstrM instruction pattern(s). | |
3037 | ; | |
3038 | ||
3039 | (define_expand "cmpstrsi" | |
3040 | [(set (reg:SI 0) (const_int 0)) | |
3041 | (parallel | |
3042 | [(clobber (match_operand 3 "" "")) | |
3043 | (clobber (match_dup 4)) | |
3044 | (set (reg:CCU CC_REGNUM) | |
3045 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
3046 | (match_operand:BLK 2 "memory_operand" ""))) | |
3047 | (use (reg:SI 0))]) | |
3048 | (parallel | |
3049 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3050 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
3051 | (clobber (reg:CC CC_REGNUM))])] |
3052 | "" | |
3053 | { | |
3054 | /* As the result of CMPINT is inverted compared to what we need, | |
3055 | we have to swap the operands. */ | |
3056 | rtx op1 = operands[2]; | |
3057 | rtx op2 = operands[1]; | |
3058 | rtx addr1 = gen_reg_rtx (Pmode); | |
3059 | rtx addr2 = gen_reg_rtx (Pmode); | |
3060 | ||
3061 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
3062 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
3063 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
3064 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
3065 | operands[3] = addr1; | |
3066 | operands[4] = addr2; | |
3067 | }) | |
3068 | ||
3069 | (define_insn "*cmpstr<mode>" | |
3070 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3071 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3072 | (set (reg:CCU CC_REGNUM) | |
3073 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3074 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3075 | (use (reg:SI 0))] | |
3076 | "" | |
3077 | "clst\t%0,%1\;jo\t.-4" | |
3078 | [(set_attr "length" "8") | |
3079 | (set_attr "type" "vs")]) | |
9381e3f1 | 3080 | |
742090fc AS |
3081 | ; |
3082 | ; movstr instruction pattern. | |
3083 | ; | |
3084 | ||
3085 | (define_expand "movstr" | |
4a7dec25 DV |
3086 | [(match_operand 0 "register_operand" "") |
3087 | (match_operand 1 "memory_operand" "") | |
3088 | (match_operand 2 "memory_operand" "")] | |
3089 | "" | |
3090 | { | |
3091 | if (TARGET_64BIT) | |
3092 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3093 | else | |
3094 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3095 | DONE; | |
3096 | }) | |
3097 | ||
3098 | (define_expand "movstr<P:mode>" | |
742090fc | 3099 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3100 | (parallel |
742090fc AS |
3101 | [(clobber (match_dup 3)) |
3102 | (set (match_operand:BLK 1 "memory_operand" "") | |
3103 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3104 | (set (match_operand:P 0 "register_operand" "") |
3105 | (unspec:P [(match_dup 1) | |
742090fc AS |
3106 | (match_dup 2) |
3107 | (reg:SI 0)] UNSPEC_MVST)) | |
3108 | (clobber (reg:CC CC_REGNUM))])] | |
3109 | "" | |
3110 | { | |
859a4c0e AK |
3111 | rtx addr1, addr2; |
3112 | ||
3113 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3114 | { | |
3115 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3116 | DONE; | |
3117 | } | |
3118 | ||
3119 | addr1 = gen_reg_rtx (Pmode); | |
3120 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3121 | |
3122 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3123 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3124 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3125 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3126 | operands[3] = addr2; | |
3127 | }) | |
3128 | ||
3129 | (define_insn "*movstr" | |
3130 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3131 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3132 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3133 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3134 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3135 | (mem:BLK (match_dup 3)) |
3136 | (reg:SI 0)] UNSPEC_MVST)) | |
3137 | (clobber (reg:CC CC_REGNUM))] | |
3138 | "" | |
3139 | "mvst\t%1,%2\;jo\t.-4" | |
3140 | [(set_attr "length" "8") | |
3141 | (set_attr "type" "vs")]) | |
9381e3f1 | 3142 | |
742090fc | 3143 | |
9db1d521 | 3144 | ; |
70128ad9 | 3145 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3146 | ; |
3147 | ||
9db2f16d | 3148 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3149 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3150 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3151 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3152 | (match_operand 3 "" "")] |
3153 | "" | |
367d32f3 AK |
3154 | { |
3155 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3156 | DONE; | |
3157 | else | |
3158 | FAIL; | |
3159 | }) | |
9db1d521 | 3160 | |
ecbe845e UW |
3161 | ; Move a block that is up to 256 bytes in length. |
3162 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3163 | |
70128ad9 | 3164 | (define_expand "movmem_short" |
b9404c99 UW |
3165 | [(parallel |
3166 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3167 | (match_operand:BLK 1 "memory_operand" "")) | |
3168 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3169 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3170 | (clobber (match_dup 3))])] |
3171 | "" | |
3172 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3173 | |
70128ad9 | 3174 | (define_insn "*movmem_short" |
963fc8d0 AK |
3175 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3176 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3177 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3178 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3179 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3180 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3181 | "#" |
963fc8d0 | 3182 | [(set_attr "type" "cs") |
b5e0425c | 3183 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3184 | |
9bb86f41 UW |
3185 | (define_split |
3186 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3187 | (match_operand:BLK 1 "memory_operand" "")) | |
3188 | (use (match_operand 2 "const_int_operand" "")) | |
3189 | (use (match_operand 3 "immediate_operand" "")) | |
3190 | (clobber (scratch))] | |
3191 | "reload_completed" | |
3192 | [(parallel | |
3193 | [(set (match_dup 0) (match_dup 1)) | |
3194 | (use (match_dup 2))])] | |
3195 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3196 | |
9bb86f41 UW |
3197 | (define_split |
3198 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3199 | (match_operand:BLK 1 "memory_operand" "")) | |
3200 | (use (match_operand 2 "register_operand" "")) | |
3201 | (use (match_operand 3 "memory_operand" "")) | |
3202 | (clobber (scratch))] | |
3203 | "reload_completed" | |
3204 | [(parallel | |
3205 | [(unspec [(match_dup 2) (match_dup 3) | |
3206 | (const_int 0)] UNSPEC_EXECUTE) | |
3207 | (set (match_dup 0) (match_dup 1)) | |
3208 | (use (const_int 1))])] | |
3209 | "") | |
3210 | ||
963fc8d0 AK |
3211 | (define_split |
3212 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3213 | (match_operand:BLK 1 "memory_operand" "")) | |
3214 | (use (match_operand 2 "register_operand" "")) | |
3215 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3216 | (clobber (scratch))] | |
3217 | "TARGET_Z10 && reload_completed" | |
3218 | [(parallel | |
3219 | [(unspec [(match_dup 2) (const_int 0) | |
3220 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3221 | (set (match_dup 0) (match_dup 1)) | |
3222 | (use (const_int 1))])] | |
3223 | "operands[3] = gen_label_rtx ();") | |
3224 | ||
9bb86f41 UW |
3225 | (define_split |
3226 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3227 | (match_operand:BLK 1 "memory_operand" "")) | |
3228 | (use (match_operand 2 "register_operand" "")) | |
3229 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3230 | (clobber (match_operand 3 "register_operand" ""))] | |
3231 | "reload_completed && TARGET_CPU_ZARCH" | |
3232 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3233 | (parallel | |
9381e3f1 | 3234 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3235 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3236 | (set (match_dup 0) (match_dup 1)) | |
3237 | (use (const_int 1))])] | |
3238 | "operands[4] = gen_label_rtx ();") | |
3239 | ||
a41c6c53 | 3240 | ; Move a block of arbitrary length. |
9db1d521 | 3241 | |
70128ad9 | 3242 | (define_expand "movmem_long" |
b9404c99 UW |
3243 | [(parallel |
3244 | [(clobber (match_dup 2)) | |
3245 | (clobber (match_dup 3)) | |
3246 | (set (match_operand:BLK 0 "memory_operand" "") | |
3247 | (match_operand:BLK 1 "memory_operand" "")) | |
3248 | (use (match_operand 2 "general_operand" "")) | |
3249 | (use (match_dup 3)) | |
ae156f85 | 3250 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3251 | "" |
3252 | { | |
ef4bddc2 RS |
3253 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3254 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3255 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3256 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3257 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3258 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3259 | rtx len0 = gen_lowpart (Pmode, reg0); |
3260 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3261 | ||
c41c1387 | 3262 | emit_clobber (reg0); |
b9404c99 UW |
3263 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3264 | emit_move_insn (len0, operands[2]); | |
3265 | ||
c41c1387 | 3266 | emit_clobber (reg1); |
b9404c99 UW |
3267 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3268 | emit_move_insn (len1, operands[2]); | |
3269 | ||
3270 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3271 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3272 | operands[2] = reg0; | |
3273 | operands[3] = reg1; | |
3274 | }) | |
3275 | ||
a1aed706 AS |
3276 | (define_insn "*movmem_long" |
3277 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3278 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3279 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3280 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3281 | (use (match_dup 2)) |
3282 | (use (match_dup 3)) | |
ae156f85 | 3283 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3284 | "TARGET_64BIT || !TARGET_ZARCH" |
3285 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3286 | [(set_attr "length" "8") | |
3287 | (set_attr "type" "vs")]) | |
3288 | ||
3289 | (define_insn "*movmem_long_31z" | |
3290 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3291 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3292 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3293 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3294 | (use (match_dup 2)) | |
3295 | (use (match_dup 3)) | |
3296 | (clobber (reg:CC CC_REGNUM))] | |
3297 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3298 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3299 | [(set_attr "length" "8") |
3300 | (set_attr "type" "vs")]) | |
9db1d521 | 3301 | |
638e37c2 WG |
3302 | |
3303 | ; | |
3304 | ; Test data class. | |
3305 | ; | |
3306 | ||
0f67fa83 WG |
3307 | (define_expand "signbit<mode>2" |
3308 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3309 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3310 | (match_dup 2)] | |
0f67fa83 WG |
3311 | UNSPEC_TDC_INSN)) |
3312 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3313 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3314 | "TARGET_HARD_FLOAT" |
3315 | { | |
3316 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3317 | }) | |
3318 | ||
638e37c2 WG |
3319 | (define_expand "isinf<mode>2" |
3320 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3321 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3322 | (match_dup 2)] | |
638e37c2 WG |
3323 | UNSPEC_TDC_INSN)) |
3324 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3325 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3326 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3327 | { |
3328 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3329 | }) | |
3330 | ||
085261c8 AK |
3331 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3332 | ; instruction will be issued by reload. The constraint of operand 1 | |
3333 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3334 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3335 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3336 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3337 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3338 | UNSPEC_CC_TO_INT))] | |
3339 | "operands != NULL" | |
3340 | "#" | |
3341 | "reload_completed" | |
3342 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3343 | ||
638e37c2 WG |
3344 | ; This insn is used to generate all variants of the Test Data Class |
3345 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3346 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3347 | ; specifying the required test(s). |
638e37c2 | 3348 | ; |
be5de7a1 | 3349 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3350 | (define_insn "*TDC_insn_<mode>" |
3351 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3352 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3353 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3354 | "TARGET_HARD_FLOAT" |
0387c142 | 3355 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3356 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3357 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3358 | |
638e37c2 WG |
3359 | |
3360 | ||
9db1d521 | 3361 | ; |
57e84f18 | 3362 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3363 | ; |
3364 | ||
57e84f18 | 3365 | (define_expand "setmem<mode>" |
a41c6c53 | 3366 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3367 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3368 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3369 | (match_operand 3 "" "")] |
a41c6c53 | 3370 | "" |
6d057022 | 3371 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3372 | |
a41c6c53 | 3373 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3374 | ; The block length is taken as (operands[1] % 256) + 1. |
3375 | ||
70128ad9 | 3376 | (define_expand "clrmem_short" |
b9404c99 UW |
3377 | [(parallel |
3378 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3379 | (const_int 0)) | |
3380 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3381 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3382 | (clobber (match_dup 2)) |
ae156f85 | 3383 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3384 | "" |
3385 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3386 | |
70128ad9 | 3387 | (define_insn "*clrmem_short" |
963fc8d0 | 3388 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3389 | (const_int 0)) |
963fc8d0 AK |
3390 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3391 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3392 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3393 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3394 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3395 | "#" |
963fc8d0 | 3396 | [(set_attr "type" "cs") |
b5e0425c | 3397 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3398 | |
3399 | (define_split | |
3400 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3401 | (const_int 0)) | |
3402 | (use (match_operand 1 "const_int_operand" "")) | |
3403 | (use (match_operand 2 "immediate_operand" "")) | |
3404 | (clobber (scratch)) | |
ae156f85 | 3405 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3406 | "reload_completed" |
3407 | [(parallel | |
3408 | [(set (match_dup 0) (const_int 0)) | |
3409 | (use (match_dup 1)) | |
ae156f85 | 3410 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3411 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3412 | |
9bb86f41 UW |
3413 | (define_split |
3414 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3415 | (const_int 0)) | |
3416 | (use (match_operand 1 "register_operand" "")) | |
3417 | (use (match_operand 2 "memory_operand" "")) | |
3418 | (clobber (scratch)) | |
ae156f85 | 3419 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3420 | "reload_completed" |
3421 | [(parallel | |
3422 | [(unspec [(match_dup 1) (match_dup 2) | |
3423 | (const_int 0)] UNSPEC_EXECUTE) | |
3424 | (set (match_dup 0) (const_int 0)) | |
3425 | (use (const_int 1)) | |
ae156f85 | 3426 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3427 | "") |
9db1d521 | 3428 | |
963fc8d0 AK |
3429 | (define_split |
3430 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3431 | (const_int 0)) | |
3432 | (use (match_operand 1 "register_operand" "")) | |
3433 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3434 | (clobber (scratch)) | |
3435 | (clobber (reg:CC CC_REGNUM))] | |
3436 | "TARGET_Z10 && reload_completed" | |
3437 | [(parallel | |
3438 | [(unspec [(match_dup 1) (const_int 0) | |
3439 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3440 | (set (match_dup 0) (const_int 0)) | |
3441 | (use (const_int 1)) | |
3442 | (clobber (reg:CC CC_REGNUM))])] | |
3443 | "operands[3] = gen_label_rtx ();") | |
3444 | ||
9bb86f41 UW |
3445 | (define_split |
3446 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3447 | (const_int 0)) | |
3448 | (use (match_operand 1 "register_operand" "")) | |
3449 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3450 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3451 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3452 | "reload_completed && TARGET_CPU_ZARCH" |
3453 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3454 | (parallel | |
9381e3f1 | 3455 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3456 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3457 | (set (match_dup 0) (const_int 0)) | |
3458 | (use (const_int 1)) | |
ae156f85 | 3459 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3460 | "operands[3] = gen_label_rtx ();") |
3461 | ||
9381e3f1 | 3462 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3463 | |
da0dcab1 | 3464 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3465 | [(parallel |
3466 | [(clobber (match_dup 1)) | |
3467 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3468 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3469 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3470 | (use (match_dup 3)) |
ae156f85 | 3471 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3472 | "" |
a41c6c53 | 3473 | { |
ef4bddc2 RS |
3474 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3475 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3476 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3477 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3478 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3479 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3480 | |
c41c1387 | 3481 | emit_clobber (reg0); |
b9404c99 UW |
3482 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3483 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3484 | |
b9404c99 | 3485 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3486 | |
b9404c99 UW |
3487 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3488 | operands[1] = reg0; | |
6d057022 | 3489 | operands[3] = reg1; |
da0dcab1 | 3490 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3491 | }) |
a41c6c53 | 3492 | |
da0dcab1 DV |
3493 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3494 | ||
db340c73 | 3495 | (define_insn "*setmem_long" |
a1aed706 | 3496 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3497 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3498 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3499 | (subreg:P (match_dup 3) <modesize>)] |
3500 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3501 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3502 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3503 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3504 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3505 | [(set_attr "length" "8") |
3506 | (set_attr "type" "vs")]) | |
9db1d521 | 3507 | |
db340c73 AK |
3508 | (define_insn "*setmem_long_and" |
3509 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3510 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3511 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3512 | (subreg:P (match_dup 3) <modesize>)] |
3513 | UNSPEC_REPLICATE_BYTE)) | |
3514 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3515 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3516 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3517 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3518 | [(set_attr "length" "8") | |
3519 | (set_attr "type" "vs")]) | |
3520 | ||
da0dcab1 DV |
3521 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3522 | ; of the SImode subregs. | |
3523 | ||
db340c73 | 3524 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3525 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3526 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3527 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3528 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3529 | (use (match_operand:TI 1 "register_operand" "d")) |
3530 | (clobber (reg:CC CC_REGNUM))] | |
3531 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3532 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3533 | [(set_attr "length" "8") | |
3534 | (set_attr "type" "vs")]) | |
9602b6a1 | 3535 | |
db340c73 AK |
3536 | (define_insn "*setmem_long_and_31z" |
3537 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3538 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3539 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3540 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3541 | (use (match_operand:TI 1 "register_operand" "d")) | |
3542 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3543 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3544 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3545 | [(set_attr "length" "8") | |
3546 | (set_attr "type" "vs")]) | |
3547 | ||
9db1d521 | 3548 | ; |
358b8f01 | 3549 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3550 | ; |
3551 | ||
358b8f01 | 3552 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3553 | [(set (match_operand:SI 0 "register_operand" "") |
3554 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3555 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3556 | (use (match_operand:SI 3 "general_operand" "")) | |
3557 | (use (match_operand:SI 4 "" ""))] | |
3558 | "" | |
367d32f3 AK |
3559 | { |
3560 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3561 | operands[2], operands[3])) | |
3562 | DONE; | |
3563 | else | |
3564 | FAIL; | |
3565 | }) | |
9db1d521 | 3566 | |
a41c6c53 UW |
3567 | ; Compare a block that is up to 256 bytes in length. |
3568 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3569 | |
b9404c99 UW |
3570 | (define_expand "cmpmem_short" |
3571 | [(parallel | |
ae156f85 | 3572 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3573 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3574 | (match_operand:BLK 1 "memory_operand" ""))) |
3575 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3576 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3577 | (clobber (match_dup 3))])] |
3578 | "" | |
3579 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3580 | |
b9404c99 | 3581 | (define_insn "*cmpmem_short" |
ae156f85 | 3582 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3583 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3584 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3585 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3586 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3587 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3588 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3589 | "#" |
963fc8d0 | 3590 | [(set_attr "type" "cs") |
b5e0425c | 3591 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3592 | |
9bb86f41 | 3593 | (define_split |
ae156f85 | 3594 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3595 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3596 | (match_operand:BLK 1 "memory_operand" ""))) | |
3597 | (use (match_operand 2 "const_int_operand" "")) | |
3598 | (use (match_operand 3 "immediate_operand" "")) | |
3599 | (clobber (scratch))] | |
3600 | "reload_completed" | |
3601 | [(parallel | |
ae156f85 | 3602 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3603 | (use (match_dup 2))])] |
3604 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3605 | |
9bb86f41 | 3606 | (define_split |
ae156f85 | 3607 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3608 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3609 | (match_operand:BLK 1 "memory_operand" ""))) | |
3610 | (use (match_operand 2 "register_operand" "")) | |
3611 | (use (match_operand 3 "memory_operand" "")) | |
3612 | (clobber (scratch))] | |
3613 | "reload_completed" | |
3614 | [(parallel | |
3615 | [(unspec [(match_dup 2) (match_dup 3) | |
3616 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3617 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3618 | (use (const_int 1))])] |
3619 | "") | |
3620 | ||
963fc8d0 AK |
3621 | (define_split |
3622 | [(set (reg:CCU CC_REGNUM) | |
3623 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3624 | (match_operand:BLK 1 "memory_operand" ""))) | |
3625 | (use (match_operand 2 "register_operand" "")) | |
3626 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3627 | (clobber (scratch))] | |
3628 | "TARGET_Z10 && reload_completed" | |
3629 | [(parallel | |
3630 | [(unspec [(match_dup 2) (const_int 0) | |
3631 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3632 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3633 | (use (const_int 1))])] | |
3634 | "operands[4] = gen_label_rtx ();") | |
3635 | ||
9bb86f41 | 3636 | (define_split |
ae156f85 | 3637 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3638 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3639 | (match_operand:BLK 1 "memory_operand" ""))) | |
3640 | (use (match_operand 2 "register_operand" "")) | |
3641 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3642 | (clobber (match_operand 3 "register_operand" ""))] | |
3643 | "reload_completed && TARGET_CPU_ZARCH" | |
3644 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3645 | (parallel | |
9381e3f1 | 3646 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3647 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3648 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3649 | (use (const_int 1))])] |
3650 | "operands[4] = gen_label_rtx ();") | |
3651 | ||
a41c6c53 | 3652 | ; Compare a block of arbitrary length. |
9db1d521 | 3653 | |
b9404c99 UW |
3654 | (define_expand "cmpmem_long" |
3655 | [(parallel | |
3656 | [(clobber (match_dup 2)) | |
3657 | (clobber (match_dup 3)) | |
ae156f85 | 3658 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3659 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3660 | (match_operand:BLK 1 "memory_operand" ""))) |
3661 | (use (match_operand 2 "general_operand" "")) | |
3662 | (use (match_dup 3))])] | |
3663 | "" | |
3664 | { | |
ef4bddc2 RS |
3665 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3666 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3667 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3668 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3669 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3670 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3671 | rtx len0 = gen_lowpart (Pmode, reg0); |
3672 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3673 | ||
c41c1387 | 3674 | emit_clobber (reg0); |
b9404c99 UW |
3675 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3676 | emit_move_insn (len0, operands[2]); | |
3677 | ||
c41c1387 | 3678 | emit_clobber (reg1); |
b9404c99 UW |
3679 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3680 | emit_move_insn (len1, operands[2]); | |
3681 | ||
3682 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3683 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3684 | operands[2] = reg0; | |
3685 | operands[3] = reg1; | |
3686 | }) | |
3687 | ||
a1aed706 AS |
3688 | (define_insn "*cmpmem_long" |
3689 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3690 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3691 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3692 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3693 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3694 | (use (match_dup 2)) |
3695 | (use (match_dup 3))] | |
9602b6a1 | 3696 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3697 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3698 | [(set_attr "length" "8") |
3699 | (set_attr "type" "vs")]) | |
9db1d521 | 3700 | |
9602b6a1 AK |
3701 | (define_insn "*cmpmem_long_31z" |
3702 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3703 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3704 | (set (reg:CCU CC_REGNUM) | |
3705 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3706 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3707 | (use (match_dup 2)) | |
3708 | (use (match_dup 3))] | |
3709 | "!TARGET_64BIT && TARGET_ZARCH" | |
3710 | "clcle\t%0,%1,0\;jo\t.-4" | |
3711 | [(set_attr "op_type" "NN") | |
3712 | (set_attr "type" "vs") | |
3713 | (set_attr "length" "8")]) | |
3714 | ||
02887425 UW |
3715 | ; Convert CCUmode condition code to integer. |
3716 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3717 | |
02887425 | 3718 | (define_insn_and_split "cmpint" |
9db1d521 | 3719 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3720 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3721 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3722 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3723 | "" |
02887425 UW |
3724 | "#" |
3725 | "reload_completed" | |
3726 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3727 | (parallel | |
3728 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3729 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3730 | |
3731 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3732 | [(set (reg CC_REGNUM) |
02887425 | 3733 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3734 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3735 | (const_int 0))) |
3736 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3737 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3738 | "s390_match_ccmode (insn, CCSmode)" |
3739 | "#" | |
3740 | "&& reload_completed" | |
3741 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3742 | (parallel | |
3743 | [(set (match_dup 2) (match_dup 3)) | |
3744 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3745 | { |
02887425 UW |
3746 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3747 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3748 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3749 | }) | |
9db1d521 | 3750 | |
02887425 | 3751 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3752 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3753 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3754 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3755 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3756 | "TARGET_ZARCH" |
02887425 UW |
3757 | "#" |
3758 | "&& reload_completed" | |
3759 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3760 | (parallel | |
3761 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3762 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3763 | |
3764 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3765 | [(set (reg CC_REGNUM) |
9381e3f1 | 3766 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3767 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3768 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3769 | (const_int 32)) (const_int 32)) |
3770 | (const_int 0))) | |
3771 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3772 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3773 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3774 | "#" |
3775 | "&& reload_completed" | |
3776 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3777 | (parallel | |
3778 | [(set (match_dup 2) (match_dup 3)) | |
3779 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3780 | { |
02887425 UW |
3781 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3782 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3783 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3784 | }) | |
9db1d521 | 3785 | |
4023fb28 | 3786 | |
9db1d521 HP |
3787 | ;; |
3788 | ;;- Conversion instructions. | |
3789 | ;; | |
3790 | ||
6fa05db6 | 3791 | (define_insn "*sethighpartsi" |
d3632d41 | 3792 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3793 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3794 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3795 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3796 | "" |
d3632d41 | 3797 | "@ |
6fa05db6 AS |
3798 | icm\t%0,%2,%S1 |
3799 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3800 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3801 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3802 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3803 | |
6fa05db6 | 3804 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3805 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3806 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3807 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3808 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3809 | "TARGET_ZARCH" |
6fa05db6 | 3810 | "icmh\t%0,%2,%S1" |
729e750f WG |
3811 | [(set_attr "op_type" "RSY") |
3812 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3813 | |
6fa05db6 | 3814 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3815 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3816 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3817 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3818 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3819 | "!TARGET_ZARCH" |
d3632d41 | 3820 | "@ |
6fa05db6 AS |
3821 | icm\t%0,%2,%S1 |
3822 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3823 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3824 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3825 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3826 | ||
1a2e356e RH |
3827 | ; |
3828 | ; extv instruction patterns | |
3829 | ; | |
3830 | ||
3831 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3832 | ; after resolving some issues with it. | |
3833 | ||
3834 | (define_expand "extzv" | |
3835 | [(parallel | |
3836 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3837 | (zero_extract:DI | |
3838 | (match_operand:DI 1 "register_operand" "d") | |
3839 | (match_operand 2 "const_int_operand" "") ; size | |
3840 | (match_operand 3 "const_int_operand" ""))) ; start | |
3841 | (clobber (reg:CC CC_REGNUM))])] | |
3842 | "TARGET_Z10" | |
3843 | { | |
0f6f72e8 DV |
3844 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3845 | FAIL; | |
1a2e356e RH |
3846 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3847 | if (TARGET_ZEC12) | |
3848 | { | |
3849 | emit_move_insn (operands[0], | |
3850 | gen_rtx_ZERO_EXTRACT (DImode, | |
3851 | operands[1], | |
3852 | operands[2], | |
3853 | operands[3])); | |
3854 | DONE; | |
3855 | } | |
3856 | }) | |
3857 | ||
64c744b9 | 3858 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3859 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3860 | (zero_extract:GPR | |
3861 | (match_operand:GPR 1 "register_operand" "d") | |
3862 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3863 | (match_operand 3 "const_int_operand" ""))) ; start |
3864 | ] | |
0f6f72e8 DV |
3865 | "<z10_or_zEC12_cond> |
3866 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3867 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3868 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3869 | [(set_attr "op_type" "RIE") | |
3870 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3871 | |
64c744b9 DV |
3872 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3873 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3874 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3875 | (match_operand 1 "const_int_operand" "") ; size | |
3876 | (match_operand 2 "const_int_operand" "")) ; start | |
3877 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3878 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3879 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3880 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3881 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3882 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3883 | [(set_attr "op_type" "RIE") | |
3884 | (set_attr "z10prop" "z10_super_E1")]) | |
3885 | ||
3886 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3887 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3888 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3889 | (ior:SI (and:SI | |
3890 | (match_operand:SI 1 "register_operand" "0") | |
3891 | (match_operand:SI 2 "const_int_operand" "")) | |
3892 | (subreg:SI | |
3893 | (zero_extract:DI | |
3894 | (match_operand:DI 3 "register_operand" "d") | |
3895 | (match_operand 4 "const_int_operand" "") ; size | |
3896 | (match_operand 5 "const_int_operand" "")) ; start | |
3897 | 4)))] | |
3898 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3899 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
64c744b9 DV |
3900 | && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))" |
3901 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" | |
3902 | [(set_attr "op_type" "RIE") | |
3903 | (set_attr "z10prop" "z10_super_E1")]) | |
3904 | ||
3905 | ; ((int)foo >> 10) & 1; | |
3906 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3907 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3908 | (ne:DI (zero_extract:DI | |
3909 | (match_operand:DI 1 "register_operand" "d") | |
3910 | (const_int 1) ; size | |
3911 | (match_operand 2 "const_int_operand" "")) ; start | |
3912 | (const_int 0)))] | |
0f6f72e8 DV |
3913 | "<z10_or_zEC12_cond> |
3914 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3915 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3916 | [(set_attr "op_type" "RIE") | |
3917 | (set_attr "z10prop" "z10_super_E1")]) | |
3918 | ||
3919 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3920 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3921 | (and:DI (subreg:DI | |
3922 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3923 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3924 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3925 | "<z10_or_zEC12_cond> | |
3926 | && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))" | |
3927 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift | |
3928 | [(set_attr "op_type" "RIE") | |
3929 | (set_attr "z10prop" "z10_super_E1")]) | |
3930 | ||
3931 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3932 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3933 | (and:DI (subreg:DI | |
3934 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3935 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3936 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3937 | "<z10_or_zEC12_cond> | |
3938 | && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
3939 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
3940 | [(set_attr "op_type" "RIE") | |
3941 | (set_attr "z10prop" "z10_super_E1")]) | |
3942 | ||
3943 | (define_insn "*<risbg_n>_di_and_rot" | |
3944 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3945 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
3946 | (match_operand:DI 2 "const_int_operand" "")) | |
3947 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3948 | "<z10_or_zEC12_cond>" | |
3949 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
3950 | [(set_attr "op_type" "RIE") |
3951 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3952 | |
1a2e356e | 3953 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 3954 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3955 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3956 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3957 | (const_int 0))) |
ae156f85 | 3958 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3959 | "!TARGET_Z10" |
cc7ab9b7 UW |
3960 | "#" |
3961 | "&& reload_completed" | |
4023fb28 | 3962 | [(parallel |
6fa05db6 | 3963 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3964 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3965 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3966 | { |
6fa05db6 AS |
3967 | int bitsize = INTVAL (operands[2]); |
3968 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3969 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3970 | ||
3971 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3972 | set_mem_size (operands[1], size); |
2542ef05 | 3973 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3974 | operands[3] = GEN_INT (mask); |
b628bd8e | 3975 | }) |
4023fb28 | 3976 | |
1a2e356e | 3977 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 3978 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3979 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3980 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3981 | (const_int 0))) |
ae156f85 | 3982 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3983 | "" |
cc7ab9b7 UW |
3984 | "#" |
3985 | "&& reload_completed" | |
4023fb28 | 3986 | [(parallel |
6fa05db6 | 3987 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3988 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3989 | (parallel |
3990 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3991 | (clobber (reg:CC CC_REGNUM))])] | |
3992 | { | |
3993 | int bitsize = INTVAL (operands[2]); | |
3994 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3995 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3996 | ||
3997 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3998 | set_mem_size (operands[1], size); |
2542ef05 | 3999 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
4000 | operands[3] = GEN_INT (mask); |
4001 | }) | |
4002 | ||
4003 | ; | |
4004 | ; insv instruction patterns | |
4005 | ; | |
4006 | ||
4007 | (define_expand "insv" | |
4008 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
4009 | (match_operand 1 "const_int_operand" "") | |
4010 | (match_operand 2 "const_int_operand" "")) | |
4011 | (match_operand 3 "general_operand" ""))] | |
4012 | "" | |
4023fb28 | 4013 | { |
6fa05db6 AS |
4014 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
4015 | DONE; | |
4016 | FAIL; | |
b628bd8e | 4017 | }) |
4023fb28 | 4018 | |
2542ef05 RH |
4019 | |
4020 | ; The normal RTL expansion will never generate a zero_extract where | |
4021 | ; the location operand isn't word mode. However, we do this in the | |
4022 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 4023 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 4024 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
4025 | (match_operand 1 "const_int_operand" "I") ; size |
4026 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 4027 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 4028 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
4029 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
4030 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 4031 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 4032 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
4033 | [(set_attr "op_type" "RIE") |
4034 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4035 | |
22ac2c2f AK |
4036 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
4037 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
4038 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
4039 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
4040 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 4041 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 4042 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 4043 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
4044 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
4045 | "@ | |
4046 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
4047 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
4048 | [(set_attr "op_type" "RIE") | |
4049 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 4050 | |
64c744b9 DV |
4051 | (define_insn "*insv_z10_noshift_cc" |
4052 | [(set (reg CC_REGNUM) | |
4053 | (compare | |
4054 | (ior:DI | |
4055 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4056 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4057 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4058 | (match_operand:DI 4 "const_int_operand" ""))) | |
4059 | (const_int 0))) | |
4060 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
4061 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
4062 | (and:DI (match_dup 3) (match_dup 4))))] | |
4063 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4064 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4065 | "@ | |
4066 | risbg\t%0,%1,%s2,%e2,0 | |
4067 | risbg\t%0,%3,%s4,%e4,0" | |
4068 | [(set_attr "op_type" "RIE") | |
4069 | (set_attr "z10prop" "z10_super_E1")]) | |
4070 | ||
4071 | (define_insn "*insv_z10_noshift_cconly" | |
4072 | [(set | |
4073 | (reg CC_REGNUM) | |
4074 | (compare | |
4075 | (ior:DI | |
4076 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4077 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4078 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4079 | (match_operand:DI 4 "const_int_operand" ""))) | |
4080 | (const_int 0))) | |
4081 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4082 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4083 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4084 | "@ | |
4085 | risbg\t%0,%1,%s2,%e2,0 | |
4086 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4087 | [(set_attr "op_type" "RIE") |
4088 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4089 | |
3d44ff99 AK |
4090 | ; Implement appending Y on the left of S bits of X |
4091 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4092 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4093 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4094 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4095 | (match_operand:GPR 2 "immediate_operand" "")) | |
4096 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4097 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 DV |
4098 | "<z10_or_zEC12_cond> |
4099 | && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
4100 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" | |
3d44ff99 AK |
4101 | [(set_attr "op_type" "RIE") |
4102 | (set_attr "z10prop" "z10_super_E1")]) | |
4103 | ||
64c744b9 DV |
4104 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4105 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4106 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4107 | (ior:GPR (and:GPR | |
4108 | (match_operand:GPR 1 "register_operand" "0") | |
4109 | (match_operand:GPR 2 "const_int_operand" "")) | |
4110 | (lshiftrt:GPR | |
4111 | (match_operand:GPR 3 "register_operand" "d") | |
4112 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4113 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
4114 | == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
4115 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" | |
4116 | [(set_attr "op_type" "RIE") | |
4117 | (set_attr "z10prop" "z10_super_E1")]) | |
4118 | ||
4119 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4120 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4121 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4122 | (ior:SI (and:SI | |
4123 | (match_operand:SI 1 "register_operand" "0") | |
4124 | (match_operand:SI 2 "const_int_operand" "")) | |
4125 | (subreg:SI | |
4126 | (lshiftrt:DI | |
4127 | (match_operand:DI 3 "register_operand" "d") | |
4128 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4129 | "<z10_or_zEC12_cond> | |
4130 | && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))" | |
4131 | "<risbg_n>\t%0,%3,%4,63,64-%4" | |
4132 | [(set_attr "op_type" "RIE") | |
4133 | (set_attr "z10prop" "z10_super_E1")]) | |
4134 | ||
4135 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4136 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4137 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4138 | (and:SI | |
4139 | (subreg:SI (lshiftrt:DI | |
4140 | (match_operand:DI 1 "register_operand" "d") | |
4141 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4142 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4143 | "<z10_or_zEC12_cond>" | |
4144 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4145 | [(set_attr "op_type" "RIE") |
4146 | (set_attr "z10prop" "z10_super_E1")]) | |
4147 | ||
4148 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4149 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4150 | ; -> z = y >> d; z = risbg; | |
4151 | ||
4152 | (define_split | |
4153 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4154 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4155 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4156 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4157 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4158 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4159 | [(set (match_dup 6) |
3d44ff99 AK |
4160 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4161 | (set (match_dup 0) | |
1d11f7ce | 4162 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4163 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4164 | { | |
4165 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4166 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4167 | { |
4168 | if (!can_create_pseudo_p ()) | |
4169 | FAIL; | |
4170 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4171 | } | |
4172 | else | |
4173 | operands[6] = operands[0]; | |
3d44ff99 AK |
4174 | }) |
4175 | ||
4176 | (define_split | |
4177 | [(parallel | |
4178 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4179 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4180 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4181 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4182 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4183 | (clobber (reg:CC CC_REGNUM))])] | |
4184 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4185 | [(set (match_dup 6) |
3d44ff99 AK |
4186 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4187 | (parallel | |
4188 | [(set (match_dup 0) | |
1d11f7ce | 4189 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4190 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4191 | (clobber (reg:CC CC_REGNUM))])] | |
4192 | { | |
4193 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4194 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4195 | { |
4196 | if (!can_create_pseudo_p ()) | |
4197 | FAIL; | |
4198 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4199 | } | |
4200 | else | |
4201 | operands[6] = operands[0]; | |
3d44ff99 AK |
4202 | }) |
4203 | ||
50dc4eed | 4204 | ; rosbg, rxsbg |
571e408a | 4205 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4206 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4207 | (IXOR:GPR |
4208 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4209 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4210 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4211 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4212 | "TARGET_Z10" |
571e408a RH |
4213 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4214 | [(set_attr "op_type" "RIE")]) | |
4215 | ||
50dc4eed | 4216 | ; rosbg, rxsbg |
571e408a RH |
4217 | (define_insn "*r<noxa>sbg_di_rotl" |
4218 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4219 | (IXOR:DI | |
4220 | (and:DI | |
4221 | (rotate:DI | |
4222 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4223 | (match_operand:DI 3 "const_int_operand" "")) | |
4224 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4225 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4226 | (clobber (reg:CC CC_REGNUM))] | |
4227 | "TARGET_Z10" | |
4228 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
4229 | [(set_attr "op_type" "RIE")]) | |
4230 | ||
50dc4eed | 4231 | ; rosbg, rxsbg |
f3d90045 | 4232 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4233 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4234 | (IXOR:GPR | |
4235 | (and:GPR | |
4236 | (lshiftrt:GPR | |
4237 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4238 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4239 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4240 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4241 | (clobber (reg:CC CC_REGNUM))] | |
4242 | "TARGET_Z10 | |
4243 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4244 | INTVAL (operands[2]))" | |
4245 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
4246 | [(set_attr "op_type" "RIE")]) | |
4247 | ||
50dc4eed | 4248 | ; rosbg, rxsbg |
f3d90045 | 4249 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4250 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4251 | (IXOR:GPR | |
4252 | (and:GPR | |
4253 | (ashift:GPR | |
4254 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4255 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4256 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4257 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4258 | (clobber (reg:CC CC_REGNUM))] | |
4259 | "TARGET_Z10 | |
4260 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4261 | INTVAL (operands[2]))" | |
4262 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4263 | [(set_attr "op_type" "RIE")]) |
4264 | ||
f3d90045 DV |
4265 | ;; unsigned {int,long} a, b |
4266 | ;; a = a | (b << const_int) | |
4267 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4268 | ; rosbg, rxsbg |
f3d90045 DV |
4269 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4270 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4271 | (IXOR:GPR | |
4272 | (ashift:GPR | |
4273 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4274 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4275 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4276 | (clobber (reg:CC CC_REGNUM))] | |
4277 | "TARGET_Z10" | |
576987fc | 4278 | "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2" |
f3d90045 DV |
4279 | [(set_attr "op_type" "RIE")]) |
4280 | ||
4281 | ;; unsigned {int,long} a, b | |
4282 | ;; a = a | (b >> const_int) | |
4283 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4284 | ; rosbg, rxsbg |
f3d90045 DV |
4285 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4286 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4287 | (IXOR:GPR | |
4288 | (lshiftrt:GPR | |
4289 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4290 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4291 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4292 | (clobber (reg:CC CC_REGNUM))] | |
4293 | "TARGET_Z10" | |
576987fc | 4294 | "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2" |
f3d90045 DV |
4295 | [(set_attr "op_type" "RIE")]) |
4296 | ||
5bb33936 RH |
4297 | ;; These two are generated by combine for s.bf &= val. |
4298 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4299 | ;; shifts and ands, which results in some truly awful patterns | |
4300 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4301 | ;; Instead of | |
4302 | ;; | |
4303 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4304 | ;; (const_int 24 [0x18]) | |
4305 | ;; (const_int 0 [0])) | |
4306 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4307 | ;; (const_int 40 [0x28])) 4) | |
4308 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4309 | ;; | |
4310 | ;; we should instead generate | |
4311 | ;; | |
4312 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4313 | ;; (const_int 24 [0x18]) | |
4314 | ;; (const_int 0 [0])) | |
4315 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4316 | ;; (const_int 40 [0x28])) | |
4317 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4318 | ;; | |
4319 | ;; by noticing that we can push down the outer paradoxical subreg | |
4320 | ;; into the operation. | |
4321 | ||
4322 | (define_insn "*insv_rnsbg_noshift" | |
4323 | [(set (zero_extract:DI | |
4324 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4325 | (match_operand 1 "const_int_operand" "") | |
4326 | (match_operand 2 "const_int_operand" "")) | |
4327 | (and:DI | |
4328 | (match_dup 0) | |
4329 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4330 | (clobber (reg:CC CC_REGNUM))] | |
4331 | "TARGET_Z10 | |
0f6f72e8 | 4332 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4333 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4334 | "rnsbg\t%0,%3,%2,63,0" | |
4335 | [(set_attr "op_type" "RIE")]) | |
4336 | ||
4337 | (define_insn "*insv_rnsbg_srl" | |
4338 | [(set (zero_extract:DI | |
4339 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4340 | (match_operand 1 "const_int_operand" "") | |
4341 | (match_operand 2 "const_int_operand" "")) | |
4342 | (and:DI | |
4343 | (lshiftrt:DI | |
4344 | (match_dup 0) | |
4345 | (match_operand 3 "const_int_operand" "")) | |
4346 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4347 | (clobber (reg:CC CC_REGNUM))] | |
4348 | "TARGET_Z10 | |
0f6f72e8 | 4349 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4350 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4351 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4352 | [(set_attr "op_type" "RIE")]) | |
4353 | ||
6fa05db6 | 4354 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4355 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4356 | (match_operand 1 "const_int_operand" "n,n") |
4357 | (const_int 0)) | |
9602b6a1 | 4358 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4359 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4360 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4361 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4362 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4363 | { | |
4364 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4365 | ||
4366 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4367 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4368 | : "stcmy\t%2,%1,%S0"; |
4369 | } | |
9381e3f1 | 4370 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4371 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4372 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4373 | |
4374 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4375 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4376 | (match_operand 1 "const_int_operand" "n") |
4377 | (const_int 0)) | |
4378 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4379 | (const_int 32)))] | |
9602b6a1 | 4380 | "TARGET_ZARCH |
0f6f72e8 | 4381 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4382 | && INTVAL (operands[1]) > 0 |
4383 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4384 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4385 | { | |
4386 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4387 | ||
4388 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4389 | return "stcmh\t%2,%1,%S0"; | |
4390 | } | |
9381e3f1 WG |
4391 | [(set_attr "op_type" "RSY") |
4392 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4393 | |
9602b6a1 AK |
4394 | (define_insn "*insvdi_reg_imm" |
4395 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4396 | (const_int 16) | |
4397 | (match_operand 1 "const_int_operand" "n")) | |
4398 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4399 | "TARGET_ZARCH |
0f6f72e8 | 4400 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4401 | && INTVAL (operands[1]) >= 0 |
4402 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4403 | && INTVAL (operands[1]) % 16 == 0" | |
4404 | { | |
4405 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4406 | { | |
4407 | case 64: return "iihh\t%0,%x2"; break; | |
4408 | case 48: return "iihl\t%0,%x2"; break; | |
4409 | case 32: return "iilh\t%0,%x2"; break; | |
4410 | case 16: return "iill\t%0,%x2"; break; | |
4411 | default: gcc_unreachable(); | |
4412 | } | |
4413 | } | |
9381e3f1 WG |
4414 | [(set_attr "op_type" "RI") |
4415 | (set_attr "z10prop" "z10_super_E1")]) | |
4416 | ||
9fec758d WG |
4417 | ; Update the left-most 32 bit of a DI. |
4418 | (define_insn "*insv_h_di_reg_extimm" | |
4419 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4420 | (const_int 32) | |
4421 | (const_int 0)) | |
4422 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4423 | "TARGET_EXTIMM" | |
4424 | "iihf\t%0,%o1" | |
4425 | [(set_attr "op_type" "RIL") | |
4426 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4427 | |
d378b983 RH |
4428 | ; Update the right-most 32 bit of a DI. |
4429 | (define_insn "*insv_l_di_reg_extimm" | |
4430 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4431 | (const_int 32) | |
4432 | (const_int 32)) | |
4433 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4434 | "TARGET_EXTIMM" | |
4435 | "iilf\t%0,%o1" | |
9381e3f1 | 4436 | [(set_attr "op_type" "RIL") |
9fec758d | 4437 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4438 | |
9db1d521 HP |
4439 | ; |
4440 | ; extendsidi2 instruction pattern(s). | |
4441 | ; | |
4442 | ||
4023fb28 UW |
4443 | (define_expand "extendsidi2" |
4444 | [(set (match_operand:DI 0 "register_operand" "") | |
4445 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4446 | "" | |
4023fb28 | 4447 | { |
9602b6a1 | 4448 | if (!TARGET_ZARCH) |
4023fb28 | 4449 | { |
c41c1387 | 4450 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4451 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4452 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4453 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4454 | DONE; |
4455 | } | |
ec24698e | 4456 | }) |
4023fb28 UW |
4457 | |
4458 | (define_insn "*extendsidi2" | |
963fc8d0 | 4459 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4460 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4461 | "TARGET_ZARCH" |
9db1d521 | 4462 | "@ |
d40c829f | 4463 | lgfr\t%0,%1 |
963fc8d0 AK |
4464 | lgf\t%0,%1 |
4465 | lgfrl\t%0,%1" | |
4466 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4467 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4468 | (set_attr "cpu_facility" "*,*,z10") |
4469 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4470 | |
9db1d521 | 4471 | ; |
56477c21 | 4472 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4473 | ; |
4474 | ||
56477c21 AS |
4475 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4476 | [(set (match_operand:DSI 0 "register_operand" "") | |
4477 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4478 | "" |
4023fb28 | 4479 | { |
9602b6a1 | 4480 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4481 | { |
4482 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4483 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4484 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4485 | DONE; | |
4486 | } | |
ec24698e | 4487 | else if (!TARGET_EXTIMM) |
4023fb28 | 4488 | { |
2542ef05 | 4489 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4490 | |
4491 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4492 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4493 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4494 | DONE; |
4495 | } | |
ec24698e UW |
4496 | }) |
4497 | ||
56477c21 AS |
4498 | ; |
4499 | ; extendhidi2 instruction pattern(s). | |
4500 | ; | |
4501 | ||
ec24698e | 4502 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4503 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4504 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4505 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4506 | "@ |
4507 | lghr\t%0,%1 | |
963fc8d0 AK |
4508 | lgh\t%0,%1 |
4509 | lghrl\t%0,%1" | |
4510 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4511 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4512 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4513 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4514 | |
4515 | (define_insn "*extendhidi2" | |
9db1d521 | 4516 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4517 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4518 | "TARGET_ZARCH" |
d40c829f | 4519 | "lgh\t%0,%1" |
9381e3f1 WG |
4520 | [(set_attr "op_type" "RXY") |
4521 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4522 | |
9db1d521 | 4523 | ; |
56477c21 | 4524 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4525 | ; |
4526 | ||
ec24698e | 4527 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4528 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4529 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4530 | "TARGET_EXTIMM" |
4531 | "@ | |
4532 | lhr\t%0,%1 | |
4533 | lh\t%0,%1 | |
963fc8d0 AK |
4534 | lhy\t%0,%1 |
4535 | lhrl\t%0,%1" | |
4536 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4537 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4538 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4539 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4540 | |
4023fb28 | 4541 | (define_insn "*extendhisi2" |
d3632d41 UW |
4542 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4543 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4544 | "!TARGET_EXTIMM" |
d3632d41 | 4545 | "@ |
d40c829f UW |
4546 | lh\t%0,%1 |
4547 | lhy\t%0,%1" | |
9381e3f1 | 4548 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4549 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4550 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4551 | |
56477c21 AS |
4552 | ; |
4553 | ; extendqi(si|di)2 instruction pattern(s). | |
4554 | ; | |
4555 | ||
43a09b63 | 4556 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4557 | (define_insn "*extendqi<mode>2_extimm" |
4558 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4559 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4560 | "TARGET_EXTIMM" |
4561 | "@ | |
56477c21 AS |
4562 | l<g>br\t%0,%1 |
4563 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4564 | [(set_attr "op_type" "RRE,RXY") |
4565 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4566 | |
43a09b63 | 4567 | ; lb, lgb |
56477c21 AS |
4568 | (define_insn "*extendqi<mode>2" |
4569 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4570 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4571 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4572 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4573 | [(set_attr "op_type" "RXY") |
4574 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4575 | |
56477c21 AS |
4576 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4577 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4578 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4579 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4580 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4581 | "#" |
4582 | "&& reload_completed" | |
4023fb28 | 4583 | [(parallel |
56477c21 | 4584 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4585 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4586 | (parallel |
56477c21 | 4587 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4588 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4589 | { |
4590 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4591 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4592 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4593 | }) |
9db1d521 | 4594 | |
9db1d521 HP |
4595 | ; |
4596 | ; zero_extendsidi2 instruction pattern(s). | |
4597 | ; | |
4598 | ||
4023fb28 UW |
4599 | (define_expand "zero_extendsidi2" |
4600 | [(set (match_operand:DI 0 "register_operand" "") | |
4601 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4602 | "" | |
4023fb28 | 4603 | { |
9602b6a1 | 4604 | if (!TARGET_ZARCH) |
4023fb28 | 4605 | { |
c41c1387 | 4606 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4607 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4608 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4609 | DONE; |
4610 | } | |
ec24698e | 4611 | }) |
4023fb28 UW |
4612 | |
4613 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4614 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4615 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4616 | "TARGET_ZARCH" |
9db1d521 | 4617 | "@ |
d40c829f | 4618 | llgfr\t%0,%1 |
963fc8d0 AK |
4619 | llgf\t%0,%1 |
4620 | llgfrl\t%0,%1" | |
4621 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4622 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4623 | (set_attr "cpu_facility" "*,*,z10") |
4624 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4625 | |
288e517f AK |
4626 | ; |
4627 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4628 | ; | |
4629 | ||
d6083c7d UW |
4630 | (define_insn "*llgt_sidi" |
4631 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4632 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4633 | (const_int 2147483647)))] |
9602b6a1 | 4634 | "TARGET_ZARCH" |
d6083c7d | 4635 | "llgt\t%0,%1" |
9381e3f1 WG |
4636 | [(set_attr "op_type" "RXE") |
4637 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4638 | |
4639 | (define_insn_and_split "*llgt_sidi_split" | |
4640 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4641 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4642 | (const_int 2147483647))) |
ae156f85 | 4643 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4644 | "TARGET_ZARCH" |
d6083c7d UW |
4645 | "#" |
4646 | "&& reload_completed" | |
4647 | [(set (match_dup 0) | |
4648 | (and:DI (subreg:DI (match_dup 1) 0) | |
4649 | (const_int 2147483647)))] | |
4650 | "") | |
4651 | ||
288e517f AK |
4652 | (define_insn "*llgt_sisi" |
4653 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4654 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4655 | (const_int 2147483647)))] |
c4d50129 | 4656 | "TARGET_ZARCH" |
288e517f AK |
4657 | "@ |
4658 | llgtr\t%0,%1 | |
4659 | llgt\t%0,%1" | |
9381e3f1 WG |
4660 | [(set_attr "op_type" "RRE,RXE") |
4661 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4662 | |
288e517f AK |
4663 | (define_insn "*llgt_didi" |
4664 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4665 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4666 | (const_int 2147483647)))] | |
9602b6a1 | 4667 | "TARGET_ZARCH" |
288e517f AK |
4668 | "@ |
4669 | llgtr\t%0,%1 | |
4670 | llgt\t%0,%N1" | |
9381e3f1 WG |
4671 | [(set_attr "op_type" "RRE,RXE") |
4672 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4673 | |
f19a9af7 | 4674 | (define_split |
9602b6a1 AK |
4675 | [(set (match_operand:DSI 0 "register_operand" "") |
4676 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4677 | (const_int 2147483647))) |
ae156f85 | 4678 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4679 | "TARGET_ZARCH && reload_completed" |
288e517f | 4680 | [(set (match_dup 0) |
9602b6a1 | 4681 | (and:DSI (match_dup 1) |
f6ee577c | 4682 | (const_int 2147483647)))] |
288e517f AK |
4683 | "") |
4684 | ||
9db1d521 | 4685 | ; |
56477c21 | 4686 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4687 | ; |
4688 | ||
56477c21 AS |
4689 | (define_expand "zero_extend<mode>di2" |
4690 | [(set (match_operand:DI 0 "register_operand" "") | |
4691 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4692 | "" | |
4693 | { | |
9602b6a1 | 4694 | if (!TARGET_ZARCH) |
56477c21 AS |
4695 | { |
4696 | rtx tmp = gen_reg_rtx (SImode); | |
4697 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4698 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4699 | DONE; | |
4700 | } | |
4701 | else if (!TARGET_EXTIMM) | |
4702 | { | |
2542ef05 | 4703 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4704 | operands[1] = gen_lowpart (DImode, operands[1]); |
4705 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4706 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4707 | DONE; | |
4708 | } | |
4709 | }) | |
4710 | ||
f6ee577c | 4711 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4712 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4713 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4714 | "" |
4023fb28 | 4715 | { |
ec24698e UW |
4716 | if (!TARGET_EXTIMM) |
4717 | { | |
4718 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4719 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4720 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4721 | DONE; |
56477c21 | 4722 | } |
ec24698e UW |
4723 | }) |
4724 | ||
963fc8d0 AK |
4725 | ; llhrl, llghrl |
4726 | (define_insn "*zero_extendhi<mode>2_z10" | |
4727 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4728 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4729 | "TARGET_Z10" |
4730 | "@ | |
4731 | ll<g>hr\t%0,%1 | |
4732 | ll<g>h\t%0,%1 | |
4733 | ll<g>hrl\t%0,%1" | |
4734 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4735 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4736 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4737 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4738 | |
43a09b63 | 4739 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4740 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4741 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4742 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4743 | "TARGET_EXTIMM" |
4744 | "@ | |
56477c21 AS |
4745 | ll<g><hc>r\t%0,%1 |
4746 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4747 | [(set_attr "op_type" "RRE,RXY") |
4748 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4749 | |
43a09b63 | 4750 | ; llgh, llgc |
56477c21 AS |
4751 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4752 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4753 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4754 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4755 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4756 | [(set_attr "op_type" "RXY") |
4757 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4758 | |
4759 | (define_insn_and_split "*zero_extendhisi2_31" | |
4760 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4761 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4762 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4763 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4764 | "#" |
4765 | "&& reload_completed" | |
4766 | [(set (match_dup 0) (const_int 0)) | |
4767 | (parallel | |
4768 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4769 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4770 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4771 | |
cc7ab9b7 UW |
4772 | (define_insn_and_split "*zero_extendqisi2_31" |
4773 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4774 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4775 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4776 | "#" |
4777 | "&& reload_completed" | |
4778 | [(set (match_dup 0) (const_int 0)) | |
4779 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4780 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4781 | |
9db1d521 HP |
4782 | ; |
4783 | ; zero_extendqihi2 instruction pattern(s). | |
4784 | ; | |
4785 | ||
9db1d521 HP |
4786 | (define_expand "zero_extendqihi2" |
4787 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4788 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4789 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4790 | { |
4023fb28 UW |
4791 | operands[1] = gen_lowpart (HImode, operands[1]); |
4792 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4793 | DONE; | |
ec24698e | 4794 | }) |
9db1d521 | 4795 | |
4023fb28 | 4796 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4797 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4798 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4799 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4800 | "llgc\t%0,%1" |
9381e3f1 WG |
4801 | [(set_attr "op_type" "RXY") |
4802 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4803 | |
cc7ab9b7 UW |
4804 | (define_insn_and_split "*zero_extendqihi2_31" |
4805 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4806 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4807 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4808 | "#" |
4809 | "&& reload_completed" | |
4810 | [(set (match_dup 0) (const_int 0)) | |
4811 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4812 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4813 | |
609e7e80 | 4814 | ; |
9751ad6e | 4815 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4816 | ; |
4817 | ||
9751ad6e AK |
4818 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4819 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4820 | ; or emits the default pattern otherwise. | |
4821 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4822 | [(parallel |
9751ad6e AK |
4823 | [(set (match_operand:GPR 0 "register_operand" "") |
4824 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4825 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4826 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4827 | "TARGET_HARD_FLOAT" |
609e7e80 | 4828 | { |
65b1d8ea AK |
4829 | if (!TARGET_Z196) |
4830 | { | |
9751ad6e AK |
4831 | /* We don't provide emulation for TD|DD->SI. */ |
4832 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4833 | && <GPR:MODE>mode == SImode) | |
4834 | FAIL; | |
4835 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4836 | operands[1])); | |
65b1d8ea AK |
4837 | DONE; |
4838 | } | |
9751ad6e AK |
4839 | |
4840 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4841 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4842 | else | |
4843 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4844 | }) |
4845 | ||
9751ad6e AK |
4846 | ; (sf|df|tf)->unsigned (si|di) |
4847 | ||
4848 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4849 | ; machines. | |
4850 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4851 | [(parallel | |
4852 | [(set (match_operand:GPR 0 "register_operand" "") | |
4853 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4854 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4855 | (clobber (reg:CC CC_REGNUM))])] | |
4856 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4857 | { | |
4858 | rtx_code_label *label1 = gen_label_rtx (); | |
4859 | rtx_code_label *label2 = gen_label_rtx (); | |
4860 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4861 | REAL_VALUE_TYPE cmp, sub; | |
4862 | ||
4863 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4864 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4865 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4866 | ||
4867 | emit_cmp_and_jump_insns (operands[1], | |
4868 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4869 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4870 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4871 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4872 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4873 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
4874 | emit_jump (label2); | |
4875 | ||
4876 | emit_label (label1); | |
4877 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4878 | operands[1], | |
4879 | GEN_INT (BFP_RND_TOWARD_0))); | |
4880 | emit_label (label2); | |
4881 | DONE; | |
4882 | }) | |
4883 | ||
4884 | ; dd->unsigned di | |
4885 | ||
4886 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4887 | ; machines. | |
4888 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
4889 | [(parallel |
4890 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 4891 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 4892 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4893 | (clobber (reg:CC CC_REGNUM))])] |
4894 | ||
9751ad6e | 4895 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 4896 | { |
9751ad6e AK |
4897 | rtx_code_label *label1 = gen_label_rtx (); |
4898 | rtx_code_label *label2 = gen_label_rtx (); | |
4899 | rtx temp = gen_reg_rtx (TDmode); | |
4900 | REAL_VALUE_TYPE cmp, sub; | |
4901 | ||
4902 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4903 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4904 | ||
4905 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4906 | solution is doing the check and the subtraction in TD mode and using a | |
4907 | TD -> DI convert afterwards. */ | |
4908 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4909 | temp = force_reg (TDmode, temp); | |
4910 | emit_cmp_and_jump_insns (temp, | |
4911 | const_double_from_real_value (cmp, TDmode), | |
4912 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4913 | emit_insn (gen_subtd3 (temp, temp, | |
4914 | const_double_from_real_value (sub, TDmode))); | |
4915 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4916 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4917 | emit_jump (label2); | |
4918 | ||
4919 | emit_label (label1); | |
4920 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
4921 | GEN_INT (DFP_RND_TOWARD_0))); | |
4922 | emit_label (label2); | |
4923 | DONE; | |
609e7e80 | 4924 | }) |
cc7ab9b7 | 4925 | |
9751ad6e | 4926 | ; td->unsigned di |
9db1d521 | 4927 | |
9751ad6e AK |
4928 | ; Emulate the unsigned conversion with the signed version for pre z196 |
4929 | ; machines. | |
4930 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 4931 | [(parallel |
9751ad6e AK |
4932 | [(set (match_operand:DI 0 "register_operand" "") |
4933 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4934 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 4935 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4936 | |
4937 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 4938 | { |
9751ad6e AK |
4939 | rtx_code_label *label1 = gen_label_rtx (); |
4940 | rtx_code_label *label2 = gen_label_rtx (); | |
4941 | rtx temp = gen_reg_rtx (TDmode); | |
4942 | REAL_VALUE_TYPE cmp, sub; | |
4943 | ||
4944 | operands[1] = force_reg (TDmode, operands[1]); | |
4945 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4946 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4947 | ||
4948 | emit_cmp_and_jump_insns (operands[1], | |
4949 | const_double_from_real_value (cmp, TDmode), | |
4950 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4951 | emit_insn (gen_subtd3 (temp, operands[1], | |
4952 | const_double_from_real_value (sub, TDmode))); | |
4953 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4954 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4955 | emit_jump (label2); | |
4956 | ||
4957 | emit_label (label1); | |
4958 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
4959 | GEN_INT (DFP_RND_TOWARD_0))); | |
4960 | emit_label (label2); | |
4961 | DONE; | |
10bbf137 | 4962 | }) |
9db1d521 | 4963 | |
9751ad6e AK |
4964 | ; Just a dummy to make the code in the first expander a bit easier. |
4965 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
4966 | [(parallel |
4967 | [(set (match_operand:SI 0 "register_operand" "") | |
4968 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 4969 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4970 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4971 | |
4972 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
4973 | { | |
4974 | FAIL; | |
4975 | }) | |
4976 | ||
65b1d8ea AK |
4977 | |
4978 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4979 | ||
9751ad6e AK |
4980 | ; df -> unsigned di |
4981 | (define_insn "*fixuns_truncdfdi2_vx" | |
6e5b5de8 AK |
4982 | [(set (match_operand:DI 0 "register_operand" "=d,v") |
4983 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4984 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4985 | (clobber (reg:CC CC_REGNUM))] | |
9751ad6e AK |
4986 | "TARGET_VX && TARGET_HARD_FLOAT" |
4987 | "@ | |
4988 | clgdbr\t%0,%h2,%1,0 | |
4989 | wclgdb\t%v0,%v1,0,%h2" | |
4990 | [(set_attr "op_type" "RRF,VRR") | |
4991 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 4992 | |
9751ad6e | 4993 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
4994 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4995 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4996 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4997 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4998 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4999 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 5000 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 5001 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 5002 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
5003 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
5004 | [(set_attr "op_type" "RRF") | |
5005 | (set_attr "type" "ftoi")]) | |
5006 | ||
b60cb710 AK |
5007 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
5008 | [(set (match_operand:GPR 0 "register_operand" "") | |
5009 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
5010 | "TARGET_HARD_FLOAT" | |
9db1d521 | 5011 | { |
b60cb710 | 5012 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 5013 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 5014 | DONE; |
10bbf137 | 5015 | }) |
9db1d521 | 5016 | |
6e5b5de8 AK |
5017 | (define_insn "*fix_truncdfdi2_bfp_z13" |
5018 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
5019 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5020 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5021 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 5022 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5023 | "@ |
5024 | cgdbr\t%0,%h2,%1 | |
5025 | wcgdb\t%v0,%v1,0,%h2" | |
5026 | [(set_attr "op_type" "RRE,VRR") | |
5027 | (set_attr "type" "ftoi")]) | |
5028 | ||
43a09b63 | 5029 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
5030 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5031 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5032 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5033 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 5034 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
5035 | "TARGET_HARD_FLOAT |
5036 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 5037 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 5038 | [(set_attr "op_type" "RRE") |
077dab3b | 5039 | (set_attr "type" "ftoi")]) |
9db1d521 | 5040 | |
6e5b5de8 AK |
5041 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5042 | [(parallel | |
5043 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5044 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5045 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5046 | (clobber (reg:CC CC_REGNUM))])] | |
5047 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
5048 | ; |
5049 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
5050 | ; | |
5051 | ||
99cd7dd0 AK |
5052 | (define_expand "fix_trunc<mode>di2" |
5053 | [(set (match_operand:DI 0 "register_operand" "") | |
5054 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 5055 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
5056 | { |
5057 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
5058 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 5059 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
5060 | DONE; |
5061 | }) | |
5062 | ||
609e7e80 | 5063 | ; cgxtr, cgdtr |
99cd7dd0 | 5064 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
5065 | [(set (match_operand:DI 0 "register_operand" "=d") |
5066 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
5067 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5068 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5069 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5070 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5071 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5072 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5073 | |
5074 | ||
f61a2c7d AK |
5075 | ; |
5076 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5077 | ; | |
5078 | ||
5079 | (define_expand "fix_trunctf<mode>2" | |
5080 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5081 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5082 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5083 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5084 | "TARGET_HARD_FLOAT" |
142cd70f | 5085 | "") |
9db1d521 | 5086 | |
9db1d521 | 5087 | |
9db1d521 | 5088 | ; |
142cd70f | 5089 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5090 | ; |
5091 | ||
609e7e80 | 5092 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5093 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5094 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5095 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5096 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5097 | "@ |
5098 | c<xde>g<bt>r\t%0,%1 | |
5099 | wcdgb\t%v0,%v1,0,0" | |
5100 | [(set_attr "op_type" "RRE,VRR") | |
5101 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5102 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5103 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5104 | |
43a09b63 | 5105 | ; cxfbr, cdfbr, cefbr |
142cd70f | 5106 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
5107 | [(set (match_operand:BFP 0 "register_operand" "=f") |
5108 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 5109 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
5110 | "c<xde>fbr\t%0,%1" |
5111 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 5112 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 5113 | |
65b1d8ea AK |
5114 | ; cxftr, cdftr |
5115 | (define_insn "floatsi<mode>2" | |
5116 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5117 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5118 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5119 | "c<xde>ftr\t%0,0,%1,0" | |
5120 | [(set_attr "op_type" "RRE") | |
5121 | (set_attr "type" "itof<mode>" )]) | |
5122 | ||
5123 | ; | |
5124 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5125 | ; | |
5126 | ||
6e5b5de8 AK |
5127 | (define_insn "*floatunsdidf2_z13" |
5128 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
5129 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
a579871b | 5130 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5131 | "@ |
5132 | cdlgbr\t%0,0,%1,0 | |
5133 | wcdlgb\t%v0,%v1,0,0" | |
5134 | [(set_attr "op_type" "RRE,VRR") | |
5135 | (set_attr "type" "itofdf")]) | |
5136 | ||
65b1d8ea AK |
5137 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5138 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5139 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5140 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5141 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5142 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5143 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5144 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5145 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5146 | (set_attr "type" "itof<FP:mode>")]) |
5147 | ||
5148 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5149 | [(set (match_operand:FP 0 "register_operand" "") | |
5150 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5151 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5152 | |
9db1d521 HP |
5153 | ; |
5154 | ; truncdfsf2 instruction pattern(s). | |
5155 | ; | |
5156 | ||
142cd70f | 5157 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5158 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5159 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5160 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5161 | "@ |
5162 | ledbr\t%0,%1 | |
5163 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5164 | ; According to BFP rounding mode | |
5165 | [(set_attr "op_type" "RRE,VRR") | |
5166 | (set_attr "type" "ftruncdf") | |
285363a1 | 5167 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5168 | |
f61a2c7d | 5169 | ; |
142cd70f | 5170 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5171 | ; |
5172 | ||
142cd70f AK |
5173 | ; ldxbr, lexbr |
5174 | (define_insn "trunctf<mode>2" | |
5175 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5176 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5177 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5178 | "TARGET_HARD_FLOAT" |
5179 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5180 | [(set_attr "length" "6") |
9381e3f1 | 5181 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5182 | |
609e7e80 AK |
5183 | ; |
5184 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5185 | ; | |
5186 | ||
432d4670 AK |
5187 | |
5188 | (define_expand "trunctddd2" | |
5189 | [(parallel | |
5190 | [(set (match_operand:DD 0 "register_operand" "") | |
5191 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5192 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5193 | (clobber (scratch:TD))])] | |
5194 | "TARGET_HARD_DFP") | |
5195 | ||
5196 | (define_insn "*trunctddd2" | |
609e7e80 | 5197 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5198 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5199 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5200 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5201 | "TARGET_HARD_DFP" |
432d4670 | 5202 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5203 | [(set_attr "length" "6") |
9381e3f1 | 5204 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5205 | |
5206 | (define_insn "truncddsd2" | |
5207 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5208 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5209 | "TARGET_HARD_DFP" |
609e7e80 AK |
5210 | "ledtr\t%0,0,%1,0" |
5211 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5212 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5213 | |
feade5a8 AK |
5214 | (define_expand "trunctdsd2" |
5215 | [(parallel | |
d5a216fa | 5216 | [(set (match_dup 2) |
feade5a8 | 5217 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5218 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5219 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5220 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5221 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5222 | "TARGET_HARD_DFP" |
5223 | { | |
d5a216fa | 5224 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5225 | }) |
5226 | ||
9db1d521 | 5227 | ; |
142cd70f | 5228 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5229 | ; |
5230 | ||
2de2b3f9 | 5231 | ; wflls |
6e5b5de8 AK |
5232 | (define_insn "*extendsfdf2_z13" |
5233 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5234 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5235 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5236 | "@ |
5237 | ldebr\t%0,%1 | |
5238 | ldeb\t%0,%1 | |
5239 | wldeb\t%v0,%v1" | |
5240 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5241 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5242 | ||
142cd70f | 5243 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5244 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5245 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5246 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5247 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5248 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5249 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5250 | "@ |
142cd70f AK |
5251 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5252 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5253 | [(set_attr "op_type" "RRE,RXE") |
5254 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5255 | ||
5256 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5257 | [(set (match_operand:BFP 0 "register_operand" "") | |
5258 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5259 | "TARGET_HARD_FLOAT | |
5260 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5261 | |
609e7e80 AK |
5262 | ; |
5263 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5264 | ; | |
5265 | ||
5266 | (define_insn "extendddtd2" | |
5267 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5268 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5269 | "TARGET_HARD_DFP" |
609e7e80 AK |
5270 | "lxdtr\t%0,%1,0" |
5271 | [(set_attr "op_type" "RRF") | |
5272 | (set_attr "type" "fsimptf")]) | |
5273 | ||
5274 | (define_insn "extendsddd2" | |
5275 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5276 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5277 | "TARGET_HARD_DFP" |
609e7e80 AK |
5278 | "ldetr\t%0,%1,0" |
5279 | [(set_attr "op_type" "RRF") | |
5280 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5281 | |
feade5a8 AK |
5282 | (define_expand "extendsdtd2" |
5283 | [(set (match_dup 2) | |
5284 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5285 | (set (match_operand:TD 0 "register_operand" "") | |
5286 | (float_extend:TD (match_dup 2)))] | |
5287 | "TARGET_HARD_DFP" | |
5288 | { | |
5289 | operands[2] = gen_reg_rtx (DDmode); | |
5290 | }) | |
5291 | ||
d12a76f3 AK |
5292 | ; Binary Floating Point - load fp integer |
5293 | ||
5294 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5295 | ; For all of them the inexact exceptions are suppressed. | |
5296 | ||
5297 | ; fiebra, fidbra, fixbra | |
5298 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5299 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5300 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5301 | FPINT))] | |
5302 | "TARGET_Z196" | |
5303 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5304 | [(set_attr "op_type" "RRF") | |
5305 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5306 | ||
5307 | ; rint is supposed to raise an inexact exception so we can use the | |
5308 | ; older instructions. | |
5309 | ||
5310 | ; fiebr, fidbr, fixbr | |
5311 | (define_insn "rint<BFP:mode>2" | |
5312 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5313 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5314 | UNSPEC_FPINT_RINT))] | |
5315 | "" | |
5316 | "fi<BFP:xde>br\t%0,0,%1" | |
5317 | [(set_attr "op_type" "RRF") | |
5318 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5319 | ||
5320 | ||
5321 | ; Decimal Floating Point - load fp integer | |
5322 | ||
5323 | ; fidtr, fixtr | |
5324 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5325 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5326 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5327 | FPINT))] | |
5328 | "TARGET_HARD_DFP" | |
5329 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5330 | [(set_attr "op_type" "RRF") | |
5331 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5332 | ||
5333 | ; fidtr, fixtr | |
5334 | (define_insn "rint<DFP:mode>2" | |
5335 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5336 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5337 | UNSPEC_FPINT_RINT))] | |
5338 | "TARGET_HARD_DFP" | |
5339 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5340 | [(set_attr "op_type" "RRF") | |
5341 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5342 | ||
5343 | ; | |
35dd9a0e AK |
5344 | ; Binary <-> Decimal floating point trunc patterns |
5345 | ; | |
5346 | ||
5347 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5348 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5349 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5350 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5351 | (clobber (reg:CC CC_REGNUM)) |
5352 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5353 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5354 | "pfpo") |
5355 | ||
5356 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5357 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5358 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5359 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5360 | (clobber (reg:CC CC_REGNUM)) |
5361 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5362 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5363 | "pfpo") |
5364 | ||
5365 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5366 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5367 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5368 | (parallel | |
5369 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5370 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5371 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5372 | (clobber (reg:CC CC_REGNUM)) |
5373 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5374 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5375 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5376 | "TARGET_HARD_DFP |
35dd9a0e AK |
5377 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5378 | { | |
5379 | HOST_WIDE_INT flags; | |
5380 | ||
5381 | flags = (PFPO_CONVERT | | |
5382 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5383 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5384 | ||
5385 | operands[2] = GEN_INT (flags); | |
5386 | }) | |
5387 | ||
5388 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5389 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5390 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5391 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5392 | (parallel | |
2cf4c39e | 5393 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5394 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5395 | (clobber (reg:CC CC_REGNUM)) |
5396 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5397 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5398 | "TARGET_HARD_DFP |
35dd9a0e AK |
5399 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5400 | { | |
5401 | HOST_WIDE_INT flags; | |
5402 | ||
5403 | flags = (PFPO_CONVERT | | |
5404 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5405 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5406 | ||
5407 | operands[2] = GEN_INT (flags); | |
5408 | }) | |
5409 | ||
5410 | ; | |
5411 | ; Binary <-> Decimal floating point extend patterns | |
5412 | ; | |
5413 | ||
5414 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5415 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5416 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5417 | (clobber (reg:CC CC_REGNUM)) |
5418 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5419 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5420 | "pfpo") |
5421 | ||
5422 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5423 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5424 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5425 | (clobber (reg:CC CC_REGNUM)) |
5426 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5427 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5428 | "pfpo") |
5429 | ||
5430 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5431 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5432 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5433 | (parallel | |
5434 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5435 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5436 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5437 | (clobber (reg:CC CC_REGNUM)) |
5438 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5439 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5440 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5441 | "TARGET_HARD_DFP |
35dd9a0e AK |
5442 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5443 | { | |
5444 | HOST_WIDE_INT flags; | |
5445 | ||
5446 | flags = (PFPO_CONVERT | | |
5447 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5448 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5449 | ||
5450 | operands[2] = GEN_INT (flags); | |
5451 | }) | |
5452 | ||
5453 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5454 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5455 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5456 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5457 | (parallel | |
2cf4c39e | 5458 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5459 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5460 | (clobber (reg:CC CC_REGNUM)) |
5461 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5462 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5463 | "TARGET_HARD_DFP |
35dd9a0e AK |
5464 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5465 | { | |
5466 | HOST_WIDE_INT flags; | |
5467 | ||
5468 | flags = (PFPO_CONVERT | | |
5469 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5470 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5471 | ||
5472 | operands[2] = GEN_INT (flags); | |
5473 | }) | |
5474 | ||
5475 | ||
9db1d521 | 5476 | ;; |
fae778eb | 5477 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5478 | ;; |
fae778eb | 5479 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5480 | ; because of unpredictable Bits in Register for Halfword and Byte |
5481 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5482 | ||
07893d4f UW |
5483 | ;; |
5484 | ;;- Add instructions. | |
5485 | ;; | |
5486 | ||
1c7b1b7e UW |
5487 | ; |
5488 | ; addti3 instruction pattern(s). | |
5489 | ; | |
5490 | ||
085261c8 AK |
5491 | (define_expand "addti3" |
5492 | [(parallel | |
5493 | [(set (match_operand:TI 0 "register_operand" "") | |
5494 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5495 | (match_operand:TI 2 "general_operand" "") ) ) | |
5496 | (clobber (reg:CC CC_REGNUM))])] | |
5497 | "TARGET_ZARCH" | |
5498 | { | |
5499 | /* For z13 we have vaq which doesn't set CC. */ | |
5500 | if (TARGET_VX) | |
5501 | { | |
5502 | emit_insn (gen_rtx_SET (operands[0], | |
5503 | gen_rtx_PLUS (TImode, | |
5504 | copy_to_mode_reg (TImode, operands[1]), | |
5505 | copy_to_mode_reg (TImode, operands[2])))); | |
5506 | DONE; | |
5507 | } | |
5508 | }) | |
5509 | ||
5510 | (define_insn_and_split "*addti3" | |
5511 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5512 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5513 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5514 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5515 | "TARGET_ZARCH" |
1c7b1b7e UW |
5516 | "#" |
5517 | "&& reload_completed" | |
5518 | [(parallel | |
ae156f85 | 5519 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5520 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5521 | (match_dup 7))) | |
5522 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5523 | (parallel | |
a94a76a7 UW |
5524 | [(set (match_dup 3) (plus:DI |
5525 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5526 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5527 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5528 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5529 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5530 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5531 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5532 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5533 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5534 | [(set_attr "op_type" "*") | |
5535 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5536 | |
07893d4f UW |
5537 | ; |
5538 | ; adddi3 instruction pattern(s). | |
5539 | ; | |
5540 | ||
3298c037 AK |
5541 | (define_expand "adddi3" |
5542 | [(parallel | |
963fc8d0 | 5543 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5544 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5545 | (match_operand:DI 2 "general_operand" ""))) | |
5546 | (clobber (reg:CC CC_REGNUM))])] | |
5547 | "" | |
5548 | "") | |
5549 | ||
07893d4f UW |
5550 | (define_insn "*adddi3_sign" |
5551 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5552 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5553 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5554 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5555 | "TARGET_ZARCH" |
07893d4f | 5556 | "@ |
d40c829f UW |
5557 | agfr\t%0,%2 |
5558 | agf\t%0,%2" | |
65b1d8ea AK |
5559 | [(set_attr "op_type" "RRE,RXY") |
5560 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5561 | |
5562 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5563 | [(set (reg CC_REGNUM) |
3e4be43f | 5564 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5565 | (match_operand:DI 1 "register_operand" "0,0")) |
5566 | (const_int 0))) | |
5567 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5568 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5569 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5570 | "@ |
d40c829f UW |
5571 | algfr\t%0,%2 |
5572 | algf\t%0,%2" | |
9381e3f1 WG |
5573 | [(set_attr "op_type" "RRE,RXY") |
5574 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5575 | |
5576 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5577 | [(set (reg CC_REGNUM) |
3e4be43f | 5578 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5579 | (match_operand:DI 1 "register_operand" "0,0")) |
5580 | (const_int 0))) | |
5581 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5582 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5583 | "@ |
d40c829f UW |
5584 | algfr\t%0,%2 |
5585 | algf\t%0,%2" | |
9381e3f1 WG |
5586 | [(set_attr "op_type" "RRE,RXY") |
5587 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5588 | |
5589 | (define_insn "*adddi3_zero" | |
5590 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5591 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5592 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5593 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5594 | "TARGET_ZARCH" |
07893d4f | 5595 | "@ |
d40c829f UW |
5596 | algfr\t%0,%2 |
5597 | algf\t%0,%2" | |
9381e3f1 WG |
5598 | [(set_attr "op_type" "RRE,RXY") |
5599 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5600 | |
e69166de | 5601 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5602 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5603 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5604 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5605 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5606 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5607 | "#" |
5608 | "&& reload_completed" | |
5609 | [(parallel | |
ae156f85 | 5610 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5611 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5612 | (match_dup 7))) | |
5613 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5614 | (parallel | |
a94a76a7 UW |
5615 | [(set (match_dup 3) (plus:SI |
5616 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5617 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5618 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5619 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5620 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5621 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5622 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5623 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5624 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5625 | |
07893d4f | 5626 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 5627 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 5628 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 5629 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5630 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5631 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5632 | "#" |
5633 | "&& reload_completed" | |
5634 | [(parallel | |
5635 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5636 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5637 | (parallel |
ae156f85 | 5638 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
5639 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5640 | (match_dup 7))) | |
5641 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5642 | (set (pc) | |
ae156f85 | 5643 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5644 | (pc) |
5645 | (label_ref (match_dup 9)))) | |
5646 | (parallel | |
5647 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 5648 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5649 | (match_dup 9)] |
97c6f7ad UW |
5650 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5651 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5652 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5653 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5654 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5655 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5656 | operands[9] = gen_label_rtx ();") |
9db1d521 | 5657 | |
3298c037 AK |
5658 | ; |
5659 | ; addsi3 instruction pattern(s). | |
5660 | ; | |
5661 | ||
5662 | (define_expand "addsi3" | |
07893d4f | 5663 | [(parallel |
963fc8d0 | 5664 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5665 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5666 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5667 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5668 | "" |
07893d4f | 5669 | "") |
9db1d521 | 5670 | |
3298c037 AK |
5671 | (define_insn "*addsi3_sign" |
5672 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5673 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5674 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5675 | (clobber (reg:CC CC_REGNUM))] | |
5676 | "" | |
5677 | "@ | |
5678 | ah\t%0,%2 | |
5679 | ahy\t%0,%2" | |
65b1d8ea | 5680 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5681 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5682 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5683 | |
9db1d521 | 5684 | ; |
3298c037 | 5685 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5686 | ; |
9db1d521 | 5687 | |
65b1d8ea | 5688 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5689 | (define_insn "*add<mode>3" |
3e4be43f UW |
5690 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5691 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5692 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5693 | (clobber (reg:CC CC_REGNUM))] |
5694 | "" | |
ec24698e | 5695 | "@ |
3298c037 | 5696 | a<g>r\t%0,%2 |
65b1d8ea | 5697 | a<g>rk\t%0,%1,%2 |
3298c037 | 5698 | a<g>hi\t%0,%h2 |
65b1d8ea | 5699 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5700 | al<g>fi\t%0,%2 |
5701 | sl<g>fi\t%0,%n2 | |
5702 | a<g>\t%0,%2 | |
963fc8d0 AK |
5703 | a<y>\t%0,%2 |
5704 | a<g>si\t%0,%c2" | |
65b1d8ea | 5705 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5706 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5707 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5708 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5709 | |
65b1d8ea | 5710 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5711 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5712 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5713 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5714 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5715 | (match_dup 1))) |
65b1d8ea | 5716 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5717 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5718 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5719 | "@ |
3298c037 | 5720 | al<g>r\t%0,%2 |
65b1d8ea | 5721 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5722 | al<g>fi\t%0,%2 |
5723 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5724 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5725 | al<g>\t%0,%2 |
963fc8d0 AK |
5726 | al<y>\t%0,%2 |
5727 | al<g>si\t%0,%c2" | |
65b1d8ea | 5728 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5729 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5730 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5731 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5732 | |
65b1d8ea | 5733 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5734 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5735 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5736 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5737 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5738 | (match_dup 1))) |
65b1d8ea | 5739 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5740 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5741 | "@ |
3298c037 | 5742 | al<g>r\t%0,%2 |
65b1d8ea | 5743 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5744 | al<g>\t%0,%2 |
5745 | al<y>\t%0,%2" | |
65b1d8ea | 5746 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5747 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5748 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5749 | |
65b1d8ea | 5750 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5751 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5752 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5753 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5754 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5755 | (match_dup 2))) |
3e4be43f | 5756 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5757 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5758 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5759 | "@ |
3298c037 | 5760 | al<g>r\t%0,%2 |
65b1d8ea | 5761 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5762 | al<g>fi\t%0,%2 |
5763 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5764 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5765 | al<g>\t%0,%2 |
963fc8d0 AK |
5766 | al<y>\t%0,%2 |
5767 | al<g>si\t%0,%c2" | |
65b1d8ea | 5768 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5769 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5770 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5771 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5772 | |
65b1d8ea | 5773 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5774 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5775 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5776 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5777 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5778 | (match_dup 2))) |
65b1d8ea | 5779 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5780 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5781 | "@ |
3298c037 | 5782 | al<g>r\t%0,%2 |
65b1d8ea | 5783 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5784 | al<g>\t%0,%2 |
5785 | al<y>\t%0,%2" | |
65b1d8ea | 5786 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5787 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5788 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5789 | |
65b1d8ea | 5790 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5791 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5792 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5793 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5794 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5795 | (const_int 0))) |
3e4be43f | 5796 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5797 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5798 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5799 | "@ |
3298c037 | 5800 | al<g>r\t%0,%2 |
65b1d8ea | 5801 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5802 | al<g>fi\t%0,%2 |
5803 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5804 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5805 | al<g>\t%0,%2 |
963fc8d0 AK |
5806 | al<y>\t%0,%2 |
5807 | al<g>si\t%0,%c2" | |
65b1d8ea | 5808 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5809 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5810 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5811 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5812 | |
65b1d8ea | 5813 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5814 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5815 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5816 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5817 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5818 | (const_int 0))) |
65b1d8ea | 5819 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5820 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5821 | "@ |
3298c037 | 5822 | al<g>r\t%0,%2 |
65b1d8ea | 5823 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5824 | al<g>\t%0,%2 |
5825 | al<y>\t%0,%2" | |
65b1d8ea | 5826 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5827 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5828 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5829 | |
65b1d8ea | 5830 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5831 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5832 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5833 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5834 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5835 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5836 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5837 | "@ |
3298c037 | 5838 | al<g>r\t%0,%2 |
65b1d8ea | 5839 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5840 | al<g>\t%0,%2 |
5841 | al<y>\t%0,%2" | |
65b1d8ea | 5842 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5843 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5844 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5845 | |
963fc8d0 | 5846 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5847 | (define_insn "*add<mode>3_imm_cc" |
5848 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5849 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5850 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5851 | (const_int 0))) |
3e4be43f | 5852 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5853 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5854 | "s390_match_ccmode (insn, CCAmode) | |
5855 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5856 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5857 | /* Avoid INT32_MIN on 32 bit. */ | |
5858 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5859 | "@ |
3298c037 | 5860 | a<g>hi\t%0,%h2 |
65b1d8ea | 5861 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5862 | a<g>fi\t%0,%2 |
5863 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5864 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5865 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5866 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5867 | |
7d2fd075 AK |
5868 | (define_insn "*adddi3_sign" |
5869 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5870 | (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
5871 | (match_operand:DI 1 "register_operand" "0"))) | |
5872 | (clobber (reg:CC CC_REGNUM))] | |
5873 | "TARGET_ARCH12" | |
5874 | "agh\t%0,%2" | |
5875 | [(set_attr "op_type" "RXY")]) | |
5876 | ||
9db1d521 | 5877 | ; |
609e7e80 | 5878 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5879 | ; |
5880 | ||
609e7e80 | 5881 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5882 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5883 | (define_insn "add<mode>3" |
2de2b3f9 AK |
5884 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
5885 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
5886 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 5887 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5888 | "TARGET_HARD_FLOAT" |
9db1d521 | 5889 | "@ |
62d3f261 AK |
5890 | a<xde>tr\t%0,%1,%2 |
5891 | a<xde>br\t%0,%2 | |
6e5b5de8 | 5892 | a<xde>b\t%0,%2 |
2de2b3f9 AK |
5893 | wfadb\t%v0,%v1,%v2 |
5894 | wfasb\t%v0,%v1,%v2" | |
5895 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 5896 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
5897 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
5898 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 5899 | |
609e7e80 | 5900 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5901 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5902 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5903 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5904 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5905 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5906 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5907 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5908 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5909 | "@ |
62d3f261 AK |
5910 | a<xde>tr\t%0,%1,%2 |
5911 | a<xde>br\t%0,%2 | |
f61a2c7d | 5912 | a<xde>b\t%0,%2" |
62d3f261 AK |
5913 | [(set_attr "op_type" "RRF,RRE,RXE") |
5914 | (set_attr "type" "fsimp<mode>") | |
5915 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5916 | |
609e7e80 | 5917 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5918 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5919 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5920 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5921 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5922 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5923 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5924 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5925 | "@ |
62d3f261 AK |
5926 | a<xde>tr\t%0,%1,%2 |
5927 | a<xde>br\t%0,%2 | |
f61a2c7d | 5928 | a<xde>b\t%0,%2" |
62d3f261 AK |
5929 | [(set_attr "op_type" "RRF,RRE,RXE") |
5930 | (set_attr "type" "fsimp<mode>") | |
5931 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5932 | |
72a4ddf2 AK |
5933 | ; |
5934 | ; Pointer add instruction patterns | |
5935 | ; | |
5936 | ||
5937 | ; This will match "*la_64" | |
5938 | (define_expand "addptrdi3" | |
5939 | [(set (match_operand:DI 0 "register_operand" "") | |
5940 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5941 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5942 | "TARGET_64BIT" | |
5943 | { | |
72a4ddf2 AK |
5944 | if (GET_CODE (operands[2]) == CONST_INT) |
5945 | { | |
357ddc7d TV |
5946 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5947 | ||
72a4ddf2 AK |
5948 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5949 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5950 | { | |
5951 | operands[2] = force_const_mem (DImode, operands[2]); | |
5952 | operands[2] = force_reg (DImode, operands[2]); | |
5953 | } | |
5954 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5955 | operands[2] = force_reg (DImode, operands[2]); | |
5956 | } | |
5957 | }) | |
5958 | ||
5959 | ; For 31 bit we have to prevent the generated pattern from matching | |
5960 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5961 | ; match "force_la_31". | |
5962 | (define_expand "addptrsi3" | |
5963 | [(parallel | |
5964 | [(set (match_operand:SI 0 "register_operand" "") | |
5965 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5966 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5967 | (use (const_int 0))])] | |
5968 | "!TARGET_64BIT" | |
5969 | { | |
72a4ddf2 AK |
5970 | if (GET_CODE (operands[2]) == CONST_INT) |
5971 | { | |
357ddc7d TV |
5972 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5973 | ||
72a4ddf2 AK |
5974 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5975 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5976 | { | |
5977 | operands[2] = force_const_mem (SImode, operands[2]); | |
5978 | operands[2] = force_reg (SImode, operands[2]); | |
5979 | } | |
5980 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5981 | operands[2] = force_reg (SImode, operands[2]); | |
5982 | } | |
5983 | }) | |
9db1d521 HP |
5984 | |
5985 | ;; | |
5986 | ;;- Subtract instructions. | |
5987 | ;; | |
5988 | ||
1c7b1b7e UW |
5989 | ; |
5990 | ; subti3 instruction pattern(s). | |
5991 | ; | |
5992 | ||
085261c8 AK |
5993 | (define_expand "subti3" |
5994 | [(parallel | |
5995 | [(set (match_operand:TI 0 "register_operand" "") | |
5996 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5997 | (match_operand:TI 2 "general_operand" "") ) ) | |
5998 | (clobber (reg:CC CC_REGNUM))])] | |
5999 | "TARGET_ZARCH" | |
6000 | { | |
2d71f118 | 6001 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
6002 | if (TARGET_VX) |
6003 | { | |
6004 | emit_insn (gen_rtx_SET (operands[0], | |
6005 | gen_rtx_MINUS (TImode, | |
6006 | operands[1], | |
6007 | copy_to_mode_reg (TImode, operands[2])))); | |
6008 | DONE; | |
6009 | } | |
6010 | }) | |
6011 | ||
6012 | (define_insn_and_split "*subti3" | |
6013 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
6014 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
6015 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 6016 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6017 | "TARGET_ZARCH" |
1c7b1b7e UW |
6018 | "#" |
6019 | "&& reload_completed" | |
6020 | [(parallel | |
ae156f85 | 6021 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
6022 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
6023 | (match_dup 7))) | |
6024 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
6025 | (parallel | |
6026 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6027 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6028 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
6029 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
6030 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
6031 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
6032 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
6033 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
6034 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
6035 | [(set_attr "op_type" "*") | |
6036 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 6037 | |
9db1d521 HP |
6038 | ; |
6039 | ; subdi3 instruction pattern(s). | |
6040 | ; | |
6041 | ||
3298c037 AK |
6042 | (define_expand "subdi3" |
6043 | [(parallel | |
6044 | [(set (match_operand:DI 0 "register_operand" "") | |
6045 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
6046 | (match_operand:DI 2 "general_operand" ""))) | |
6047 | (clobber (reg:CC CC_REGNUM))])] | |
6048 | "" | |
6049 | "") | |
6050 | ||
07893d4f UW |
6051 | (define_insn "*subdi3_sign" |
6052 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6053 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6054 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6055 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6056 | "TARGET_ZARCH" |
07893d4f | 6057 | "@ |
d40c829f UW |
6058 | sgfr\t%0,%2 |
6059 | sgf\t%0,%2" | |
9381e3f1 | 6060 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
6061 | (set_attr "z10prop" "z10_c,*") |
6062 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
6063 | |
6064 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 6065 | [(set (reg CC_REGNUM) |
07893d4f | 6066 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6067 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6068 | (const_int 0))) |
6069 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6070 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 6071 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6072 | "@ |
d40c829f UW |
6073 | slgfr\t%0,%2 |
6074 | slgf\t%0,%2" | |
9381e3f1 WG |
6075 | [(set_attr "op_type" "RRE,RXY") |
6076 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6077 | |
6078 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 6079 | [(set (reg CC_REGNUM) |
07893d4f | 6080 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6081 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6082 | (const_int 0))) |
6083 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6084 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6085 | "@ |
d40c829f UW |
6086 | slgfr\t%0,%2 |
6087 | slgf\t%0,%2" | |
9381e3f1 WG |
6088 | [(set_attr "op_type" "RRE,RXY") |
6089 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6090 | |
6091 | (define_insn "*subdi3_zero" | |
6092 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6093 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6094 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6095 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6096 | "TARGET_ZARCH" |
07893d4f | 6097 | "@ |
d40c829f UW |
6098 | slgfr\t%0,%2 |
6099 | slgf\t%0,%2" | |
9381e3f1 WG |
6100 | [(set_attr "op_type" "RRE,RXY") |
6101 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6102 | |
e69166de UW |
6103 | (define_insn_and_split "*subdi3_31z" |
6104 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6105 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6106 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6107 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6108 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
6109 | "#" |
6110 | "&& reload_completed" | |
6111 | [(parallel | |
ae156f85 | 6112 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6113 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6114 | (match_dup 7))) | |
6115 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6116 | (parallel | |
6117 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6118 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6119 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6120 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6121 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6122 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6123 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6124 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6125 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6126 | |
07893d4f UW |
6127 | (define_insn_and_split "*subdi3_31" |
6128 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6129 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 6130 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 6131 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 6132 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
6133 | "#" |
6134 | "&& reload_completed" | |
6135 | [(parallel | |
6136 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 6137 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 6138 | (parallel |
ae156f85 | 6139 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
6140 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6141 | (match_dup 7))) | |
6142 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6143 | (set (pc) | |
ae156f85 | 6144 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
6145 | (pc) |
6146 | (label_ref (match_dup 9)))) | |
6147 | (parallel | |
6148 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 6149 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 6150 | (match_dup 9)] |
97c6f7ad UW |
6151 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6152 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6153 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6154 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6155 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
6156 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 6157 | operands[9] = gen_label_rtx ();") |
07893d4f | 6158 | |
3298c037 AK |
6159 | ; |
6160 | ; subsi3 instruction pattern(s). | |
6161 | ; | |
6162 | ||
6163 | (define_expand "subsi3" | |
07893d4f | 6164 | [(parallel |
3298c037 AK |
6165 | [(set (match_operand:SI 0 "register_operand" "") |
6166 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6167 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6168 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6169 | "" |
07893d4f | 6170 | "") |
9db1d521 | 6171 | |
3298c037 AK |
6172 | (define_insn "*subsi3_sign" |
6173 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6174 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6175 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6176 | (clobber (reg:CC CC_REGNUM))] | |
6177 | "" | |
6178 | "@ | |
6179 | sh\t%0,%2 | |
6180 | shy\t%0,%2" | |
65b1d8ea | 6181 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6182 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6183 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6184 | |
9db1d521 | 6185 | ; |
3298c037 | 6186 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6187 | ; |
6188 | ||
65b1d8ea | 6189 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6190 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6191 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6192 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6193 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6194 | (clobber (reg:CC CC_REGNUM))] |
6195 | "" | |
6196 | "@ | |
6197 | s<g>r\t%0,%2 | |
65b1d8ea | 6198 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6199 | s<g>\t%0,%2 |
6200 | s<y>\t%0,%2" | |
65b1d8ea | 6201 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6202 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6203 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6204 | |
65b1d8ea | 6205 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6206 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6207 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6208 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6209 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6210 | (match_dup 1))) |
65b1d8ea | 6211 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6212 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6213 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6214 | "@ |
3298c037 | 6215 | sl<g>r\t%0,%2 |
65b1d8ea | 6216 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6217 | sl<g>\t%0,%2 |
6218 | sl<y>\t%0,%2" | |
65b1d8ea | 6219 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6220 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6221 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6222 | |
65b1d8ea | 6223 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6224 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6225 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6226 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6227 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6228 | (match_dup 1))) |
65b1d8ea | 6229 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6230 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6231 | "@ |
3298c037 | 6232 | sl<g>r\t%0,%2 |
65b1d8ea | 6233 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6234 | sl<g>\t%0,%2 |
6235 | sl<y>\t%0,%2" | |
65b1d8ea | 6236 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6237 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6238 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6239 | |
65b1d8ea | 6240 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6241 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6242 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6243 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6244 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6245 | (const_int 0))) |
65b1d8ea | 6246 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6247 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6248 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6249 | "@ |
3298c037 | 6250 | sl<g>r\t%0,%2 |
65b1d8ea | 6251 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6252 | sl<g>\t%0,%2 |
6253 | sl<y>\t%0,%2" | |
65b1d8ea | 6254 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6255 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6256 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6257 | |
65b1d8ea | 6258 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6259 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6260 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6261 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6262 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6263 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6264 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6265 | "s390_match_ccmode (insn, CCL3mode)" |
6266 | "@ | |
3298c037 | 6267 | sl<g>r\t%0,%2 |
65b1d8ea | 6268 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6269 | sl<g>\t%0,%2 |
6270 | sl<y>\t%0,%2" | |
65b1d8ea | 6271 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6272 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6273 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6274 | |
65b1d8ea | 6275 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6276 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6277 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6278 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6279 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6280 | (const_int 0))) |
65b1d8ea | 6281 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6282 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6283 | "@ |
3298c037 | 6284 | sl<g>r\t%0,%2 |
65b1d8ea | 6285 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6286 | sl<g>\t%0,%2 |
6287 | sl<y>\t%0,%2" | |
65b1d8ea | 6288 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6289 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6290 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6291 | |
9db1d521 | 6292 | |
65b1d8ea | 6293 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6294 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6295 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6296 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6297 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6298 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6299 | "s390_match_ccmode (insn, CCL3mode)" |
6300 | "@ | |
3298c037 | 6301 | sl<g>r\t%0,%2 |
65b1d8ea | 6302 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6303 | sl<g>\t%0,%2 |
6304 | sl<y>\t%0,%2" | |
65b1d8ea | 6305 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6306 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6307 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6308 | |
7d2fd075 AK |
6309 | (define_insn "*subdi3_sign" |
6310 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6311 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6312 | (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) | |
6313 | (clobber (reg:CC CC_REGNUM))] | |
6314 | "TARGET_ARCH12" | |
6315 | "sgh\t%0,%2" | |
6316 | [(set_attr "op_type" "RXY")]) | |
6317 | ||
9db1d521 HP |
6318 | |
6319 | ; | |
609e7e80 | 6320 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6321 | ; |
6322 | ||
2de2b3f9 | 6323 | ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? |
d46f24b6 | 6324 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6325 | (define_insn "sub<mode>3" |
2de2b3f9 AK |
6326 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6327 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
6328 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6329 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6330 | "TARGET_HARD_FLOAT" |
9db1d521 | 6331 | "@ |
62d3f261 AK |
6332 | s<xde>tr\t%0,%1,%2 |
6333 | s<xde>br\t%0,%2 | |
6e5b5de8 | 6334 | s<xde>b\t%0,%2 |
2de2b3f9 AK |
6335 | wfsdb\t%v0,%v1,%v2 |
6336 | wfssb\t%v0,%v1,%v2" | |
6337 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6338 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6339 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6340 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6341 | |
d46f24b6 | 6342 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6343 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6344 | [(set (reg CC_REGNUM) |
62d3f261 | 6345 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
2de2b3f9 | 6346 | (match_operand:FP 2 "general_operand" "f,f,R")) |
609e7e80 | 6347 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6348 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6349 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6350 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6351 | "@ |
62d3f261 AK |
6352 | s<xde>tr\t%0,%1,%2 |
6353 | s<xde>br\t%0,%2 | |
f61a2c7d | 6354 | s<xde>b\t%0,%2" |
62d3f261 AK |
6355 | [(set_attr "op_type" "RRF,RRE,RXE") |
6356 | (set_attr "type" "fsimp<mode>") | |
6357 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6358 | |
d46f24b6 | 6359 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6360 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6361 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6362 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6363 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6364 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6365 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6366 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6367 | "@ |
62d3f261 AK |
6368 | s<xde>tr\t%0,%1,%2 |
6369 | s<xde>br\t%0,%2 | |
f61a2c7d | 6370 | s<xde>b\t%0,%2" |
62d3f261 AK |
6371 | [(set_attr "op_type" "RRF,RRE,RXE") |
6372 | (set_attr "type" "fsimp<mode>") | |
6373 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6374 | |
9db1d521 | 6375 | |
e69166de UW |
6376 | ;; |
6377 | ;;- Conditional add/subtract instructions. | |
6378 | ;; | |
6379 | ||
6380 | ; | |
9a91a21f | 6381 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6382 | ; |
6383 | ||
a996720c UW |
6384 | ; the following 4 patterns are used when the result of an add with |
6385 | ; carry is checked for an overflow condition | |
6386 | ||
6387 | ; op1 + op2 + c < op1 | |
6388 | ||
6389 | ; alcr, alc, alcgr, alcg | |
6390 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6391 | [(set (reg CC_REGNUM) | |
6392 | (compare | |
6393 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6394 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6395 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6396 | (match_dup 1))) |
6397 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6398 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6399 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6400 | "@ | |
6401 | alc<g>r\t%0,%2 | |
6402 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6403 | [(set_attr "op_type" "RRE,RXY") |
6404 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6405 | |
6406 | ; alcr, alc, alcgr, alcg | |
6407 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6408 | [(set (reg CC_REGNUM) | |
6409 | (compare | |
6410 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6411 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6412 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6413 | (match_dup 1))) |
6414 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6415 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6416 | "@ | |
6417 | alc<g>r\t%0,%2 | |
6418 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6419 | [(set_attr "op_type" "RRE,RXY") |
6420 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6421 | |
6422 | ; op1 + op2 + c < op2 | |
6423 | ||
6424 | ; alcr, alc, alcgr, alcg | |
6425 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6426 | [(set (reg CC_REGNUM) | |
6427 | (compare | |
6428 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6429 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6430 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6431 | (match_dup 2))) |
6432 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6433 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6434 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6435 | "@ | |
6436 | alc<g>r\t%0,%2 | |
6437 | alc<g>\t%0,%2" | |
6438 | [(set_attr "op_type" "RRE,RXY")]) | |
6439 | ||
6440 | ; alcr, alc, alcgr, alcg | |
6441 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6442 | [(set (reg CC_REGNUM) | |
6443 | (compare | |
6444 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6445 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6446 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6447 | (match_dup 2))) |
6448 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6449 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6450 | "@ | |
6451 | alc<g>r\t%0,%2 | |
6452 | alc<g>\t%0,%2" | |
6453 | [(set_attr "op_type" "RRE,RXY")]) | |
6454 | ||
43a09b63 | 6455 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6456 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6457 | [(set (reg CC_REGNUM) |
e69166de | 6458 | (compare |
a94a76a7 UW |
6459 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6460 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6461 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6462 | (const_int 0))) |
9a91a21f | 6463 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6464 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 6465 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6466 | "@ |
9a91a21f AS |
6467 | alc<g>r\t%0,%2 |
6468 | alc<g>\t%0,%2" | |
e69166de UW |
6469 | [(set_attr "op_type" "RRE,RXY")]) |
6470 | ||
43a09b63 | 6471 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6472 | (define_insn "*add<mode>3_alc" |
6473 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6474 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6475 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6476 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6477 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6478 | "TARGET_CPU_ZARCH" |
e69166de | 6479 | "@ |
9a91a21f AS |
6480 | alc<g>r\t%0,%2 |
6481 | alc<g>\t%0,%2" | |
e69166de UW |
6482 | [(set_attr "op_type" "RRE,RXY")]) |
6483 | ||
43a09b63 | 6484 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6485 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6486 | [(set (reg CC_REGNUM) |
e69166de | 6487 | (compare |
9a91a21f | 6488 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6489 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6490 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6491 | (const_int 0))) |
9a91a21f AS |
6492 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6493 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 6494 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6495 | "@ |
9a91a21f AS |
6496 | slb<g>r\t%0,%2 |
6497 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6498 | [(set_attr "op_type" "RRE,RXY") |
6499 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6500 | |
43a09b63 | 6501 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6502 | (define_insn "*sub<mode>3_slb" |
6503 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6504 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6505 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6506 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6507 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6508 | "TARGET_CPU_ZARCH" |
e69166de | 6509 | "@ |
9a91a21f AS |
6510 | slb<g>r\t%0,%2 |
6511 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6512 | [(set_attr "op_type" "RRE,RXY") |
6513 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6514 | |
9a91a21f AS |
6515 | (define_expand "add<mode>cc" |
6516 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6517 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6518 | (match_operand:GPR 2 "register_operand" "") |
6519 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 6520 | "TARGET_CPU_ZARCH" |
9381e3f1 | 6521 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6522 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6523 | operands[0], operands[2], |
5d880bd2 UW |
6524 | operands[3])) FAIL; DONE;") |
6525 | ||
6526 | ; | |
6527 | ; scond instruction pattern(s). | |
6528 | ; | |
6529 | ||
9a91a21f AS |
6530 | (define_insn_and_split "*scond<mode>" |
6531 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6532 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6533 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6534 | "TARGET_CPU_ZARCH" |
6535 | "#" | |
6536 | "&& reload_completed" | |
6537 | [(set (match_dup 0) (const_int 0)) | |
6538 | (parallel | |
a94a76a7 UW |
6539 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6540 | (match_dup 0))) | |
ae156f85 | 6541 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6542 | "") |
5d880bd2 | 6543 | |
9a91a21f AS |
6544 | (define_insn_and_split "*scond<mode>_neg" |
6545 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6546 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6547 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6548 | "TARGET_CPU_ZARCH" |
6549 | "#" | |
6550 | "&& reload_completed" | |
6551 | [(set (match_dup 0) (const_int 0)) | |
6552 | (parallel | |
9a91a21f AS |
6553 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6554 | (match_dup 1))) | |
ae156f85 | 6555 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6556 | (parallel |
9a91a21f | 6557 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6558 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6559 | "") |
5d880bd2 | 6560 | |
5d880bd2 | 6561 | |
f90b7a5a | 6562 | (define_expand "cstore<mode>4" |
9a91a21f | 6563 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6564 | (match_operator:SI 1 "s390_scond_operator" |
6565 | [(match_operand:GPR 2 "register_operand" "") | |
6566 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 6567 | "TARGET_CPU_ZARCH" |
f90b7a5a | 6568 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6569 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6570 | ||
f90b7a5a | 6571 | (define_expand "cstorecc4" |
69950452 | 6572 | [(parallel |
f90b7a5a PB |
6573 | [(set (match_operand:SI 0 "register_operand" "") |
6574 | (match_operator:SI 1 "s390_eqne_operator" | |
3ea685e7 | 6575 | [(match_operand 2 "cc_reg_operand") |
f90b7a5a | 6576 | (match_operand 3 "const0_operand")])) |
69950452 AS |
6577 | (clobber (reg:CC CC_REGNUM))])] |
6578 | "" | |
3ea685e7 DV |
6579 | "machine_mode mode = GET_MODE (operands[2]); |
6580 | if (TARGET_Z196) | |
6581 | { | |
6582 | rtx cond, ite; | |
6583 | ||
6584 | if (GET_CODE (operands[1]) == NE) | |
6585 | cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); | |
6586 | else | |
6587 | cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); | |
6588 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); | |
6589 | emit_insn (gen_rtx_SET (operands[0], ite)); | |
6590 | } | |
6591 | else | |
6592 | { | |
6593 | if (mode != CCZ1mode) | |
6594 | FAIL; | |
6595 | emit_insn (gen_sne (operands[0], operands[2])); | |
6596 | if (GET_CODE (operands[1]) == EQ) | |
6597 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6598 | } | |
f90b7a5a | 6599 | DONE;") |
69950452 | 6600 | |
f90b7a5a | 6601 | (define_insn_and_split "sne" |
69950452 | 6602 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6603 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6604 | (const_int 0))) |
6605 | (clobber (reg:CC CC_REGNUM))] | |
6606 | "" | |
6607 | "#" | |
6608 | "reload_completed" | |
6609 | [(parallel | |
6610 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6611 | (clobber (reg:CC CC_REGNUM))])]) | |
6612 | ||
e69166de | 6613 | |
65b1d8ea AK |
6614 | ;; |
6615 | ;; - Conditional move instructions (introduced with z196) | |
6616 | ;; | |
6617 | ||
6618 | (define_expand "mov<mode>cc" | |
6619 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6620 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6621 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6622 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6623 | "TARGET_Z196" | |
7477de01 AK |
6624 | { |
6625 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6626 | if (!s390_comparison (operands[1], VOIDmode)) | |
6627 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6628 | XEXP (operands[1], 0), | |
6629 | XEXP (operands[1], 1)); | |
6630 | }) | |
65b1d8ea | 6631 | |
bf749919 | 6632 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi |
561f6312 AK |
6633 | (define_insn "*mov<mode>cc" |
6634 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S") | |
65b1d8ea AK |
6635 | (if_then_else:GPR |
6636 | (match_operator 1 "s390_comparison" | |
561f6312 | 6637 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c") |
5a3fe9b6 | 6638 | (match_operand 5 "const_int_operand" "")]) |
561f6312 AK |
6639 | (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0") |
6640 | (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))] | |
65b1d8ea AK |
6641 | "TARGET_Z196" |
6642 | "@ | |
6643 | loc<g>r%C1\t%0,%3 | |
6644 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6645 | loc<g>%C1\t%0,%3 |
6646 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6647 | loc<g>hi%C1\t%0,%h3 |
6648 | loc<g>hi%D1\t%0,%h4 | |
a6510374 | 6649 | stoc<g>%C1\t%3,%0 |
561f6312 AK |
6650 | stoc<g>%D1\t%4,%0" |
6651 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") | |
6652 | (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")]) | |
65b1d8ea | 6653 | |
9db1d521 HP |
6654 | ;; |
6655 | ;;- Multiply instructions. | |
6656 | ;; | |
6657 | ||
4023fb28 UW |
6658 | ; |
6659 | ; muldi3 instruction pattern(s). | |
6660 | ; | |
9db1d521 | 6661 | |
7d2fd075 AK |
6662 | (define_expand "muldi3" |
6663 | [(parallel | |
6664 | [(set (match_operand:DI 0 "register_operand") | |
6665 | (mult:DI (match_operand:DI 1 "nonimmediate_operand") | |
6666 | (match_operand:DI 2 "general_operand"))) | |
6667 | (clobber (reg:CC CC_REGNUM))])] | |
6668 | "TARGET_ZARCH") | |
6669 | ||
07893d4f UW |
6670 | (define_insn "*muldi3_sign" |
6671 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6672 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6673 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6674 | "TARGET_ZARCH" |
07893d4f | 6675 | "@ |
d40c829f UW |
6676 | msgfr\t%0,%2 |
6677 | msgf\t%0,%2" | |
963fc8d0 AK |
6678 | [(set_attr "op_type" "RRE,RXY") |
6679 | (set_attr "type" "imuldi")]) | |
07893d4f | 6680 | |
7d2fd075 AK |
6681 | (define_insn "*muldi3" |
6682 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") | |
6683 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") | |
6684 | (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) | |
6685 | (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] | |
9602b6a1 | 6686 | "TARGET_ZARCH" |
9db1d521 | 6687 | "@ |
d40c829f | 6688 | msgr\t%0,%2 |
7d2fd075 | 6689 | msgrkc\t%0,%1,%2 |
d40c829f | 6690 | mghi\t%0,%h2 |
963fc8d0 AK |
6691 | msg\t%0,%2 |
6692 | msgfi\t%0,%2" | |
7d2fd075 | 6693 | [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") |
963fc8d0 | 6694 | (set_attr "type" "imuldi") |
7d2fd075 AK |
6695 | (set_attr "cpu_facility" "*,arch12,*,*,z10")]) |
6696 | ||
6697 | (define_insn "mulditi3" | |
6698 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6699 | (mult:TI (sign_extend:TI | |
6700 | (match_operand:DI 1 "register_operand" "%d,0")) | |
6701 | (sign_extend:TI | |
6702 | (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] | |
6703 | "TARGET_ARCH12" | |
6704 | "@ | |
6705 | mgrk\t%0,%1,%2 | |
6706 | mg\t%0,%2" | |
6707 | [(set_attr "op_type" "RRF,RXY")]) | |
6708 | ||
6709 | ; Combine likes op1 and op2 to be swapped sometimes. | |
6710 | (define_insn "mulditi3_2" | |
6711 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6712 | (mult:TI (sign_extend:TI | |
6713 | (match_operand:DI 1 "nonimmediate_operand" "%d,T")) | |
6714 | (sign_extend:TI | |
6715 | (match_operand:DI 2 "register_operand" " d,0"))))] | |
6716 | "TARGET_ARCH12" | |
6717 | "@ | |
6718 | mgrk\t%0,%1,%2 | |
6719 | mg\t%0,%1" | |
6720 | [(set_attr "op_type" "RRF,RXY")]) | |
6721 | ||
6722 | (define_insn "*muldi3_sign" | |
6723 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6724 | (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
6725 | (match_operand:DI 1 "register_operand" "0")))] | |
6726 | "TARGET_ARCH12" | |
6727 | "mgh\t%0,%2" | |
6728 | [(set_attr "op_type" "RXY")]) | |
6729 | ||
f2d3c02a | 6730 | |
9db1d521 HP |
6731 | ; |
6732 | ; mulsi3 instruction pattern(s). | |
6733 | ; | |
6734 | ||
7d2fd075 AK |
6735 | (define_expand "mulsi3" |
6736 | [(parallel | |
6737 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6738 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6739 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6740 | (clobber (reg:CC CC_REGNUM))])] | |
6741 | "") | |
6742 | ||
f1e77d83 | 6743 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6744 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6745 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6746 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6747 | "" |
963fc8d0 AK |
6748 | "@ |
6749 | mh\t%0,%2 | |
6750 | mhy\t%0,%2" | |
6751 | [(set_attr "op_type" "RX,RXY") | |
6752 | (set_attr "type" "imulhi") | |
6753 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6754 | |
7d2fd075 AK |
6755 | (define_insn "*mulsi3" |
6756 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6757 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6758 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6759 | (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] | |
9db1d521 HP |
6760 | "" |
6761 | "@ | |
d40c829f | 6762 | msr\t%0,%2 |
7d2fd075 | 6763 | msrkc\t%0,%1,%2 |
d40c829f UW |
6764 | mhi\t%0,%h2 |
6765 | ms\t%0,%2 | |
963fc8d0 AK |
6766 | msy\t%0,%2 |
6767 | msfi\t%0,%2" | |
7d2fd075 AK |
6768 | [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") |
6769 | (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") | |
6770 | (set_attr "cpu_facility" "*,arch12,*,*,longdisp,z10")]) | |
9db1d521 | 6771 | |
4023fb28 UW |
6772 | ; |
6773 | ; mulsidi3 instruction pattern(s). | |
6774 | ; | |
6775 | ||
f1e77d83 | 6776 | (define_insn "mulsidi3" |
963fc8d0 | 6777 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6778 | (mult:DI (sign_extend:DI |
963fc8d0 | 6779 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6780 | (sign_extend:DI |
963fc8d0 | 6781 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6782 | "!TARGET_ZARCH" |
f1e77d83 UW |
6783 | "@ |
6784 | mr\t%0,%2 | |
963fc8d0 AK |
6785 | m\t%0,%2 |
6786 | mfy\t%0,%2" | |
6787 | [(set_attr "op_type" "RR,RX,RXY") | |
6788 | (set_attr "type" "imulsi") | |
6789 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6790 | |
f1e77d83 | 6791 | ; |
6e0d70c9 | 6792 | ; umul instruction pattern(s). |
f1e77d83 | 6793 | ; |
c7453384 | 6794 | |
6e0d70c9 AK |
6795 | ; mlr, ml, mlgr, mlg |
6796 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 6797 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 6798 | (mult:DW (zero_extend:DW |
3e4be43f | 6799 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 6800 | (zero_extend:DW |
3e4be43f | 6801 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
6e0d70c9 | 6802 | "TARGET_CPU_ZARCH" |
f1e77d83 | 6803 | "@ |
6e0d70c9 AK |
6804 | ml<tg>r\t%0,%2 |
6805 | ml<tg>\t%0,%2" | |
f1e77d83 | 6806 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6807 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6808 | |
9db1d521 | 6809 | ; |
609e7e80 | 6810 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6811 | ; |
6812 | ||
9381e3f1 | 6813 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6814 | (define_insn "mul<mode>3" |
2de2b3f9 AK |
6815 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6816 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
6817 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 6818 | "TARGET_HARD_FLOAT" |
9db1d521 | 6819 | "@ |
62d3f261 AK |
6820 | m<xdee>tr\t%0,%1,%2 |
6821 | m<xdee>br\t%0,%2 | |
6e5b5de8 | 6822 | m<xdee>b\t%0,%2 |
2de2b3f9 AK |
6823 | wfmdb\t%v0,%v1,%v2 |
6824 | wfmsb\t%v0,%v1,%v2" | |
6825 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6826 | (set_attr "type" "fmul<mode>") |
2de2b3f9 AK |
6827 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6828 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6829 | |
9381e3f1 | 6830 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6831 | (define_insn "fma<mode>4" |
2de2b3f9 AK |
6832 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6833 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6834 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6835 | (match_operand:DSF 3 "register_operand" "0,0,v,v")))] | |
d7ecb504 | 6836 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6837 | "@ |
f61a2c7d | 6838 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 | 6839 | ma<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6840 | wfmadb\t%v0,%v1,%v2,%v3 |
6841 | wfmasb\t%v0,%v1,%v2,%v3" | |
6842 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6843 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6844 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6845 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
a1b892b5 | 6846 | |
43a09b63 | 6847 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6848 | (define_insn "fms<mode>4" |
2de2b3f9 AK |
6849 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6850 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6851 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6852 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] | |
d7ecb504 | 6853 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6854 | "@ |
f61a2c7d | 6855 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 | 6856 | ms<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6857 | wfmsdb\t%v0,%v1,%v2,%v3 |
6858 | wfmssb\t%v0,%v1,%v2,%v3" | |
6859 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6860 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6861 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6862 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
9db1d521 HP |
6863 | |
6864 | ;; | |
6865 | ;;- Divide and modulo instructions. | |
6866 | ;; | |
6867 | ||
6868 | ; | |
4023fb28 | 6869 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6870 | ; |
6871 | ||
4023fb28 UW |
6872 | (define_expand "divmoddi4" |
6873 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6874 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6875 | (match_operand:DI 2 "general_operand" ""))) |
6876 | (set (match_operand:DI 3 "general_operand" "") | |
6877 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6878 | (clobber (match_dup 4))] | |
9602b6a1 | 6879 | "TARGET_ZARCH" |
9db1d521 | 6880 | { |
d8485bdb TS |
6881 | rtx div_equal, mod_equal; |
6882 | rtx_insn *insn; | |
4023fb28 UW |
6883 | |
6884 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6885 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6886 | |
6887 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6888 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6889 | |
6890 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6891 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6892 | |
6893 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6894 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6895 | |
9db1d521 | 6896 | DONE; |
10bbf137 | 6897 | }) |
9db1d521 HP |
6898 | |
6899 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6900 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6901 | (ior:TI | |
4023fb28 UW |
6902 | (ashift:TI |
6903 | (zero_extend:TI | |
5665e398 | 6904 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6905 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
6906 | (const_int 64)) |
6907 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6908 | "TARGET_ZARCH" |
9db1d521 | 6909 | "@ |
d40c829f UW |
6910 | dsgr\t%0,%2 |
6911 | dsg\t%0,%2" | |
d3632d41 | 6912 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6913 | (set_attr "type" "idiv")]) |
9db1d521 | 6914 | |
4023fb28 UW |
6915 | (define_insn "divmodtisi3" |
6916 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6917 | (ior:TI | |
4023fb28 UW |
6918 | (ashift:TI |
6919 | (zero_extend:TI | |
5665e398 | 6920 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6921 | (sign_extend:DI |
3e4be43f | 6922 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
6923 | (const_int 64)) |
6924 | (zero_extend:TI | |
6925 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6926 | "TARGET_ZARCH" |
4023fb28 | 6927 | "@ |
d40c829f UW |
6928 | dsgfr\t%0,%2 |
6929 | dsgf\t%0,%2" | |
d3632d41 | 6930 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6931 | (set_attr "type" "idiv")]) |
9db1d521 | 6932 | |
4023fb28 UW |
6933 | ; |
6934 | ; udivmoddi4 instruction pattern(s). | |
6935 | ; | |
9db1d521 | 6936 | |
4023fb28 UW |
6937 | (define_expand "udivmoddi4" |
6938 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6939 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6940 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6941 | (set (match_operand:DI 3 "general_operand" "") | |
6942 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6943 | (clobber (match_dup 4))] | |
9602b6a1 | 6944 | "TARGET_ZARCH" |
9db1d521 | 6945 | { |
d8485bdb TS |
6946 | rtx div_equal, mod_equal, equal; |
6947 | rtx_insn *insn; | |
4023fb28 UW |
6948 | |
6949 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6950 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6951 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6952 | gen_rtx_ASHIFT (TImode, |
6953 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6954 | GEN_INT (64)), |
6955 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6956 | |
6957 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6958 | emit_clobber (operands[4]); |
4023fb28 UW |
6959 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6960 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6961 | |
4023fb28 | 6962 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6963 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6964 | |
6965 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6966 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6967 | |
6968 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6969 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6970 | |
9db1d521 | 6971 | DONE; |
10bbf137 | 6972 | }) |
9db1d521 HP |
6973 | |
6974 | (define_insn "udivmodtidi3" | |
4023fb28 | 6975 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6976 | (ior:TI |
5665e398 UW |
6977 | (ashift:TI |
6978 | (zero_extend:TI | |
6979 | (truncate:DI | |
2f7e5a0d EC |
6980 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6981 | (zero_extend:TI | |
3e4be43f | 6982 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
6983 | (const_int 64)) |
6984 | (zero_extend:TI | |
6985 | (truncate:DI | |
6986 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6987 | "TARGET_ZARCH" |
9db1d521 | 6988 | "@ |
d40c829f UW |
6989 | dlgr\t%0,%2 |
6990 | dlg\t%0,%2" | |
d3632d41 | 6991 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6992 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6993 | |
6994 | ; | |
4023fb28 | 6995 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6996 | ; |
6997 | ||
4023fb28 UW |
6998 | (define_expand "divmodsi4" |
6999 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7000 | (div:SI (match_operand:SI 1 "general_operand" "") | |
7001 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7002 | (set (match_operand:SI 3 "general_operand" "") | |
7003 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
7004 | (clobber (match_dup 4))] | |
9602b6a1 | 7005 | "!TARGET_ZARCH" |
9db1d521 | 7006 | { |
d8485bdb TS |
7007 | rtx div_equal, mod_equal, equal; |
7008 | rtx_insn *insn; | |
4023fb28 UW |
7009 | |
7010 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
7011 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
7012 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7013 | gen_rtx_ASHIFT (DImode, |
7014 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7015 | GEN_INT (32)), |
7016 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
7017 | |
7018 | operands[4] = gen_reg_rtx(DImode); | |
7019 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 7020 | |
4023fb28 | 7021 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7022 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7023 | |
7024 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7025 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7026 | |
7027 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7028 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7029 | |
9db1d521 | 7030 | DONE; |
10bbf137 | 7031 | }) |
9db1d521 HP |
7032 | |
7033 | (define_insn "divmoddisi3" | |
4023fb28 | 7034 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 7035 | (ior:DI |
5665e398 UW |
7036 | (ashift:DI |
7037 | (zero_extend:DI | |
7038 | (truncate:SI | |
2f7e5a0d EC |
7039 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
7040 | (sign_extend:DI | |
5665e398 UW |
7041 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
7042 | (const_int 32)) | |
7043 | (zero_extend:DI | |
7044 | (truncate:SI | |
7045 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7046 | "!TARGET_ZARCH" |
9db1d521 | 7047 | "@ |
d40c829f UW |
7048 | dr\t%0,%2 |
7049 | d\t%0,%2" | |
9db1d521 | 7050 | [(set_attr "op_type" "RR,RX") |
077dab3b | 7051 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7052 | |
7053 | ; | |
7054 | ; udivsi3 and umodsi3 instruction pattern(s). | |
7055 | ; | |
7056 | ||
f1e77d83 UW |
7057 | (define_expand "udivmodsi4" |
7058 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7059 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
7060 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7061 | (set (match_operand:SI 3 "general_operand" "") | |
7062 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
7063 | (clobber (match_dup 4))] | |
9602b6a1 | 7064 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 | 7065 | { |
d8485bdb TS |
7066 | rtx div_equal, mod_equal, equal; |
7067 | rtx_insn *insn; | |
f1e77d83 UW |
7068 | |
7069 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7070 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7071 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
7072 | gen_rtx_ASHIFT (DImode, |
7073 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7074 | GEN_INT (32)), |
7075 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
7076 | |
7077 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 7078 | emit_clobber (operands[4]); |
f1e77d83 UW |
7079 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
7080 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 7081 | |
f1e77d83 | 7082 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7083 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
7084 | |
7085 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7086 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
7087 | |
7088 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7089 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
7090 | |
7091 | DONE; | |
7092 | }) | |
7093 | ||
7094 | (define_insn "udivmoddisi3" | |
7095 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 7096 | (ior:DI |
5665e398 UW |
7097 | (ashift:DI |
7098 | (zero_extend:DI | |
7099 | (truncate:SI | |
2f7e5a0d EC |
7100 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
7101 | (zero_extend:DI | |
3e4be43f | 7102 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7103 | (const_int 32)) |
7104 | (zero_extend:DI | |
7105 | (truncate:SI | |
7106 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7107 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
7108 | "@ |
7109 | dlr\t%0,%2 | |
7110 | dl\t%0,%2" | |
7111 | [(set_attr "op_type" "RRE,RXY") | |
7112 | (set_attr "type" "idiv")]) | |
4023fb28 | 7113 | |
9db1d521 HP |
7114 | (define_expand "udivsi3" |
7115 | [(set (match_operand:SI 0 "register_operand" "=d") | |
7116 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
7117 | (match_operand:SI 2 "general_operand" ""))) |
7118 | (clobber (match_dup 3))] | |
9602b6a1 | 7119 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 7120 | { |
d8485bdb TS |
7121 | rtx udiv_equal, umod_equal, equal; |
7122 | rtx_insn *insn; | |
4023fb28 UW |
7123 | |
7124 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7125 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7126 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7127 | gen_rtx_ASHIFT (DImode, |
7128 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
7129 | GEN_INT (32)), |
7130 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 7131 | |
4023fb28 | 7132 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
7133 | |
7134 | if (CONSTANT_P (operands[2])) | |
7135 | { | |
7136 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
7137 | { | |
19f8b229 | 7138 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 7139 | |
4023fb28 UW |
7140 | operands[1] = make_safe_from (operands[1], operands[0]); |
7141 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
7142 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
7143 | SImode, 1, label1); | |
4023fb28 | 7144 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
7145 | emit_label (label1); |
7146 | } | |
7147 | else | |
7148 | { | |
c7453384 EC |
7149 | operands[2] = force_reg (SImode, operands[2]); |
7150 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7151 | |
7152 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
7153 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7154 | operands[2])); | |
bd94cb6e | 7155 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7156 | |
7157 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7158 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 7159 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
7160 | } |
7161 | } | |
7162 | else | |
c7453384 | 7163 | { |
19f8b229 TS |
7164 | rtx_code_label *label1 = gen_label_rtx (); |
7165 | rtx_code_label *label2 = gen_label_rtx (); | |
7166 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 7167 | |
c7453384 EC |
7168 | operands[1] = force_reg (SImode, operands[1]); |
7169 | operands[1] = make_safe_from (operands[1], operands[0]); | |
7170 | operands[2] = force_reg (SImode, operands[2]); | |
7171 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7172 | |
7173 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
7174 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
7175 | SImode, 1, label3); | |
7176 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
7177 | SImode, 0, label2); | |
7178 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
7179 | SImode, 0, label1); | |
4023fb28 UW |
7180 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
7181 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7182 | operands[2])); | |
bd94cb6e | 7183 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7184 | |
7185 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7186 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
7187 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
7188 | ||
f314b9b1 | 7189 | emit_jump (label3); |
9db1d521 | 7190 | emit_label (label1); |
4023fb28 | 7191 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 7192 | emit_jump (label3); |
9db1d521 | 7193 | emit_label (label2); |
4023fb28 | 7194 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
7195 | emit_label (label3); |
7196 | } | |
c7453384 | 7197 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 7198 | DONE; |
10bbf137 | 7199 | }) |
9db1d521 HP |
7200 | |
7201 | (define_expand "umodsi3" | |
7202 | [(set (match_operand:SI 0 "register_operand" "=d") | |
7203 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
7204 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
7205 | (clobber (match_dup 3))] | |
9602b6a1 | 7206 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 7207 | { |
d8485bdb TS |
7208 | rtx udiv_equal, umod_equal, equal; |
7209 | rtx_insn *insn; | |
4023fb28 UW |
7210 | |
7211 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7212 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7213 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7214 | gen_rtx_ASHIFT (DImode, |
7215 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
7216 | GEN_INT (32)), |
7217 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 7218 | |
4023fb28 | 7219 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
7220 | |
7221 | if (CONSTANT_P (operands[2])) | |
7222 | { | |
7223 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
7224 | { | |
19f8b229 | 7225 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 7226 | |
4023fb28 UW |
7227 | operands[1] = make_safe_from (operands[1], operands[0]); |
7228 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
7229 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
7230 | SImode, 1, label1); | |
4023fb28 UW |
7231 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
7232 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
7233 | emit_label (label1); |
7234 | } | |
7235 | else | |
7236 | { | |
c7453384 EC |
7237 | operands[2] = force_reg (SImode, operands[2]); |
7238 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7239 | |
7240 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
7241 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7242 | operands[2])); | |
bd94cb6e | 7243 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7244 | |
7245 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7246 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 7247 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
7248 | } |
7249 | } | |
7250 | else | |
7251 | { | |
19f8b229 TS |
7252 | rtx_code_label *label1 = gen_label_rtx (); |
7253 | rtx_code_label *label2 = gen_label_rtx (); | |
7254 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 7255 | |
c7453384 EC |
7256 | operands[1] = force_reg (SImode, operands[1]); |
7257 | operands[1] = make_safe_from (operands[1], operands[0]); | |
7258 | operands[2] = force_reg (SImode, operands[2]); | |
7259 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 7260 | |
c7453384 | 7261 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
7262 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
7263 | SImode, 1, label3); | |
7264 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
7265 | SImode, 0, label2); | |
7266 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
7267 | SImode, 0, label1); | |
4023fb28 UW |
7268 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
7269 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7270 | operands[2])); | |
bd94cb6e | 7271 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7272 | |
7273 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7274 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
7275 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
7276 | ||
f314b9b1 | 7277 | emit_jump (label3); |
9db1d521 | 7278 | emit_label (label1); |
4023fb28 | 7279 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 7280 | emit_jump (label3); |
9db1d521 | 7281 | emit_label (label2); |
4023fb28 | 7282 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
7283 | emit_label (label3); |
7284 | } | |
9db1d521 | 7285 | DONE; |
10bbf137 | 7286 | }) |
9db1d521 HP |
7287 | |
7288 | ; | |
f5905b37 | 7289 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7290 | ; |
7291 | ||
609e7e80 | 7292 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7293 | (define_insn "div<mode>3" |
2de2b3f9 AK |
7294 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7295 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
7296 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7297 | "TARGET_HARD_FLOAT" |
9db1d521 | 7298 | "@ |
62d3f261 AK |
7299 | d<xde>tr\t%0,%1,%2 |
7300 | d<xde>br\t%0,%2 | |
6e5b5de8 | 7301 | d<xde>b\t%0,%2 |
2de2b3f9 AK |
7302 | wfddb\t%v0,%v1,%v2 |
7303 | wfdsb\t%v0,%v1,%v2" | |
7304 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7305 | (set_attr "type" "fdiv<mode>") |
2de2b3f9 AK |
7306 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7307 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7308 | |
9db1d521 HP |
7309 | |
7310 | ;; | |
7311 | ;;- And instructions. | |
7312 | ;; | |
7313 | ||
047d35ed AS |
7314 | (define_expand "and<mode>3" |
7315 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7316 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7317 | (match_operand:INT 2 "general_operand" ""))) | |
7318 | (clobber (reg:CC CC_REGNUM))] | |
7319 | "" | |
7320 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7321 | ||
9db1d521 HP |
7322 | ; |
7323 | ; anddi3 instruction pattern(s). | |
7324 | ; | |
7325 | ||
7326 | (define_insn "*anddi3_cc" | |
ae156f85 | 7327 | [(set (reg CC_REGNUM) |
e3140518 | 7328 | (compare |
3e4be43f | 7329 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7330 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7331 | (const_int 0))) |
3e4be43f | 7332 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7333 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7334 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7335 | "@ |
d40c829f | 7336 | ngr\t%0,%2 |
65b1d8ea | 7337 | ngrk\t%0,%1,%2 |
e3140518 RH |
7338 | ng\t%0,%2 |
7339 | risbg\t%0,%1,%s2,128+%e2,0" | |
7340 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7341 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7342 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7343 | |
7344 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7345 | [(set (reg CC_REGNUM) |
e3140518 | 7346 | (compare |
3e4be43f | 7347 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7348 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7349 | (const_int 0))) |
3e4be43f | 7350 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7351 | "TARGET_ZARCH |
7352 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7353 | /* Do not steal TM patterns. */ |
7354 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7355 | "@ |
d40c829f | 7356 | ngr\t%0,%2 |
65b1d8ea | 7357 | ngrk\t%0,%1,%2 |
e3140518 RH |
7358 | ng\t%0,%2 |
7359 | risbg\t%0,%1,%s2,128+%e2,0" | |
7360 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7361 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7362 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7363 | |
3af8e996 | 7364 | (define_insn "*anddi3" |
65b1d8ea | 7365 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7366 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7367 | (and:DI |
7368 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7369 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7370 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7371 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7372 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7373 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7374 | "@ |
7375 | # | |
7376 | # | |
7377 | nihh\t%0,%j2 | |
7378 | nihl\t%0,%j2 | |
7379 | nilh\t%0,%j2 | |
7380 | nill\t%0,%j2 | |
7381 | nihf\t%0,%m2 | |
7382 | nilf\t%0,%m2 | |
7383 | ngr\t%0,%2 | |
65b1d8ea | 7384 | ngrk\t%0,%1,%2 |
ec24698e | 7385 | ng\t%0,%2 |
e3140518 | 7386 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7387 | # |
7388 | #" | |
e3140518 RH |
7389 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7390 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7391 | (set_attr "z10prop" "*, |
7392 | *, | |
7393 | z10_super_E1, | |
7394 | z10_super_E1, | |
7395 | z10_super_E1, | |
7396 | z10_super_E1, | |
7397 | z10_super_E1, | |
7398 | z10_super_E1, | |
7399 | z10_super_E1, | |
65b1d8ea | 7400 | *, |
9381e3f1 | 7401 | z10_super_E1, |
e3140518 | 7402 | z10_super_E1, |
9381e3f1 WG |
7403 | *, |
7404 | *")]) | |
0dfa6c5e UW |
7405 | |
7406 | (define_split | |
7407 | [(set (match_operand:DI 0 "s_operand" "") | |
7408 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7409 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7410 | "reload_completed" |
7411 | [(parallel | |
7412 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7413 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7414 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7415 | |
1a2e356e | 7416 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7417 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7418 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7419 | (and:GPR (lshiftrt:GPR | |
7420 | (match_operand:GPR 1 "register_operand" "d") | |
7421 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7422 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7423 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7424 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7425 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7426 | INTVAL (operands[3]))" | |
64c744b9 | 7427 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7428 | [(set_attr "op_type" "RIE") |
7429 | (set_attr "z10prop" "z10_super_E1")]) | |
7430 | ||
64c744b9 | 7431 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7432 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7433 | (and:GPR (ashift:GPR | |
7434 | (match_operand:GPR 1 "register_operand" "d") | |
7435 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7436 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7437 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7438 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7439 | INTVAL (operands[3]))" | |
64c744b9 | 7440 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7441 | [(set_attr "op_type" "RIE") |
7442 | (set_attr "z10prop" "z10_super_E1")]) | |
7443 | ||
9db1d521 HP |
7444 | |
7445 | ; | |
7446 | ; andsi3 instruction pattern(s). | |
7447 | ; | |
7448 | ||
7449 | (define_insn "*andsi3_cc" | |
ae156f85 | 7450 | [(set (reg CC_REGNUM) |
e3140518 RH |
7451 | (compare |
7452 | (and:SI | |
7453 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7454 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7455 | (const_int 0))) | |
7456 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7457 | (and:SI (match_dup 1) (match_dup 2)))] |
7458 | "s390_match_ccmode(insn, CCTmode)" | |
7459 | "@ | |
ec24698e | 7460 | nilf\t%0,%o2 |
d40c829f | 7461 | nr\t%0,%2 |
65b1d8ea | 7462 | nrk\t%0,%1,%2 |
d40c829f | 7463 | n\t%0,%2 |
e3140518 RH |
7464 | ny\t%0,%2 |
7465 | risbg\t%0,%1,%t2,128+%f2,0" | |
7466 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7467 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7468 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7469 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7470 | |
7471 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7472 | [(set (reg CC_REGNUM) |
e3140518 RH |
7473 | (compare |
7474 | (and:SI | |
7475 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7476 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7477 | (const_int 0))) | |
7478 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7479 | "s390_match_ccmode(insn, CCTmode) |
7480 | /* Do not steal TM patterns. */ | |
7481 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7482 | "@ |
ec24698e | 7483 | nilf\t%0,%o2 |
d40c829f | 7484 | nr\t%0,%2 |
65b1d8ea | 7485 | nrk\t%0,%1,%2 |
d40c829f | 7486 | n\t%0,%2 |
e3140518 RH |
7487 | ny\t%0,%2 |
7488 | risbg\t%0,%1,%t2,128+%f2,0" | |
7489 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7490 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7491 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7492 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7493 | |
f19a9af7 | 7494 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7495 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7496 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7497 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7498 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7499 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7500 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7501 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7502 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7503 | "@ |
f19a9af7 AK |
7504 | # |
7505 | # | |
7506 | nilh\t%0,%j2 | |
2f7e5a0d | 7507 | nill\t%0,%j2 |
ec24698e | 7508 | nilf\t%0,%o2 |
d40c829f | 7509 | nr\t%0,%2 |
65b1d8ea | 7510 | nrk\t%0,%1,%2 |
d40c829f | 7511 | n\t%0,%2 |
8cb66696 | 7512 | ny\t%0,%2 |
e3140518 | 7513 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7514 | # |
19b63d8e | 7515 | #" |
e3140518 | 7516 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7517 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7518 | (set_attr "z10prop" "*, |
7519 | *, | |
7520 | z10_super_E1, | |
7521 | z10_super_E1, | |
7522 | z10_super_E1, | |
7523 | z10_super_E1, | |
65b1d8ea | 7524 | *, |
9381e3f1 WG |
7525 | z10_super_E1, |
7526 | z10_super_E1, | |
e3140518 | 7527 | z10_super_E1, |
9381e3f1 WG |
7528 | *, |
7529 | *")]) | |
f19a9af7 AK |
7530 | |
7531 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7532 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7533 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7534 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7535 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7536 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7537 | "@ |
7538 | nr\t%0,%2 | |
8cb66696 | 7539 | n\t%0,%2 |
0dfa6c5e | 7540 | # |
19b63d8e | 7541 | #" |
9381e3f1 WG |
7542 | [(set_attr "op_type" "RR,RX,SI,SS") |
7543 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7544 | ||
0dfa6c5e UW |
7545 | |
7546 | (define_split | |
7547 | [(set (match_operand:SI 0 "s_operand" "") | |
7548 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7549 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7550 | "reload_completed" |
7551 | [(parallel | |
7552 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7553 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7554 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7555 | |
9db1d521 HP |
7556 | ; |
7557 | ; andhi3 instruction pattern(s). | |
7558 | ; | |
7559 | ||
8cb66696 | 7560 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7561 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7562 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7563 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7564 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7565 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7566 | "@ |
d40c829f | 7567 | nr\t%0,%2 |
65b1d8ea | 7568 | nrk\t%0,%1,%2 |
8cb66696 | 7569 | nill\t%0,%x2 |
0dfa6c5e | 7570 | # |
19b63d8e | 7571 | #" |
65b1d8ea AK |
7572 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7573 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7574 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7575 | ]) |
8cb66696 UW |
7576 | |
7577 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7578 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7579 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7580 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7581 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7582 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7583 | "@ | |
7584 | nr\t%0,%2 | |
0dfa6c5e | 7585 | # |
19b63d8e | 7586 | #" |
9381e3f1 WG |
7587 | [(set_attr "op_type" "RR,SI,SS") |
7588 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7589 | ]) | |
0dfa6c5e UW |
7590 | |
7591 | (define_split | |
7592 | [(set (match_operand:HI 0 "s_operand" "") | |
7593 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7594 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7595 | "reload_completed" |
7596 | [(parallel | |
7597 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7598 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7599 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7600 | |
9db1d521 HP |
7601 | ; |
7602 | ; andqi3 instruction pattern(s). | |
7603 | ; | |
7604 | ||
8cb66696 | 7605 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7606 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7607 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7608 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7609 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7610 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7611 | "@ |
d40c829f | 7612 | nr\t%0,%2 |
65b1d8ea | 7613 | nrk\t%0,%1,%2 |
8cb66696 | 7614 | nill\t%0,%b2 |
fc0ea003 UW |
7615 | ni\t%S0,%b2 |
7616 | niy\t%S0,%b2 | |
19b63d8e | 7617 | #" |
65b1d8ea | 7618 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7619 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7620 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7621 | |
7622 | (define_insn "*andqi3_esa" | |
7623 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7624 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7625 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7626 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7627 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7628 | "@ |
8cb66696 | 7629 | nr\t%0,%2 |
fc0ea003 | 7630 | ni\t%S0,%b2 |
19b63d8e | 7631 | #" |
9381e3f1 WG |
7632 | [(set_attr "op_type" "RR,SI,SS") |
7633 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7634 | |
deb9351f DV |
7635 | ; |
7636 | ; And with complement | |
7637 | ; | |
7638 | ; c = ~b & a = (b & a) ^ a | |
7639 | ||
7640 | (define_insn_and_split "*andc_split_<mode>" | |
7641 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7642 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7643 | (match_operand:GPR 2 "general_operand" ""))) | |
7644 | (clobber (reg:CC CC_REGNUM))] | |
ad7ab32e DV |
7645 | "! reload_completed |
7646 | && (GET_CODE (operands[0]) != MEM | |
7647 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7648 | on the split xor if (b & a) is stored into a pseudo. */ | |
7649 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7650 | "#" |
7651 | "&& 1" | |
7652 | [ | |
7653 | (parallel | |
7654 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7655 | (clobber (reg:CC CC_REGNUM))]) | |
7656 | (parallel | |
7657 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7658 | (clobber (reg:CC CC_REGNUM))])] | |
7659 | { | |
7660 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7661 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7662 | else | |
7663 | operands[3] = operands[0]; | |
7664 | }) | |
7665 | ||
19b63d8e UW |
7666 | ; |
7667 | ; Block and (NC) patterns. | |
7668 | ; | |
7669 | ||
7670 | (define_insn "*nc" | |
7671 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7672 | (and:BLK (match_dup 0) | |
7673 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7674 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7675 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7676 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7677 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7678 | [(set_attr "op_type" "SS") |
7679 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7680 | |
7681 | (define_split | |
7682 | [(set (match_operand 0 "memory_operand" "") | |
7683 | (and (match_dup 0) | |
7684 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7685 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7686 | "reload_completed |
7687 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7688 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7689 | [(parallel | |
7690 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7691 | (use (match_dup 2)) | |
ae156f85 | 7692 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7693 | { |
7694 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7695 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7696 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7697 | }) | |
7698 | ||
7699 | (define_peephole2 | |
7700 | [(parallel | |
7701 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7702 | (and:BLK (match_dup 0) | |
7703 | (match_operand:BLK 1 "memory_operand" ""))) | |
7704 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7705 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7706 | (parallel |
7707 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7708 | (and:BLK (match_dup 3) | |
7709 | (match_operand:BLK 4 "memory_operand" ""))) | |
7710 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7711 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7712 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7713 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7714 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7715 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7716 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7717 | [(parallel | |
7718 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7719 | (use (match_dup 8)) | |
ae156f85 | 7720 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7721 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7722 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7723 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7724 | ||
9db1d521 HP |
7725 | |
7726 | ;; | |
7727 | ;;- Bit set (inclusive or) instructions. | |
7728 | ;; | |
7729 | ||
047d35ed AS |
7730 | (define_expand "ior<mode>3" |
7731 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7732 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7733 | (match_operand:INT 2 "general_operand" ""))) | |
7734 | (clobber (reg:CC CC_REGNUM))] | |
7735 | "" | |
7736 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7737 | ||
9db1d521 HP |
7738 | ; |
7739 | ; iordi3 instruction pattern(s). | |
7740 | ; | |
7741 | ||
4023fb28 | 7742 | (define_insn "*iordi3_cc" |
ae156f85 | 7743 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7744 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7745 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7746 | (const_int 0))) |
3e4be43f | 7747 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7748 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7749 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7750 | "@ |
d40c829f | 7751 | ogr\t%0,%2 |
65b1d8ea | 7752 | ogrk\t%0,%1,%2 |
d40c829f | 7753 | og\t%0,%2" |
65b1d8ea AK |
7754 | [(set_attr "op_type" "RRE,RRF,RXY") |
7755 | (set_attr "cpu_facility" "*,z196,*") | |
7756 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7757 | |
7758 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7759 | [(set (reg CC_REGNUM) |
65b1d8ea | 7760 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7761 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7762 | (const_int 0))) |
65b1d8ea | 7763 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7764 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7765 | "@ |
d40c829f | 7766 | ogr\t%0,%2 |
65b1d8ea | 7767 | ogrk\t%0,%1,%2 |
d40c829f | 7768 | og\t%0,%2" |
65b1d8ea AK |
7769 | [(set_attr "op_type" "RRE,RRF,RXY") |
7770 | (set_attr "cpu_facility" "*,z196,*") | |
7771 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7772 | |
3af8e996 | 7773 | (define_insn "*iordi3" |
65b1d8ea | 7774 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7775 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7776 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7777 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7778 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7779 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7780 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7781 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7782 | "@ |
7783 | oihh\t%0,%i2 | |
7784 | oihl\t%0,%i2 | |
7785 | oilh\t%0,%i2 | |
7786 | oill\t%0,%i2 | |
7787 | oihf\t%0,%k2 | |
7788 | oilf\t%0,%k2 | |
7789 | ogr\t%0,%2 | |
65b1d8ea | 7790 | ogrk\t%0,%1,%2 |
ec24698e UW |
7791 | og\t%0,%2 |
7792 | # | |
7793 | #" | |
65b1d8ea AK |
7794 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7795 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7796 | (set_attr "z10prop" "z10_super_E1, |
7797 | z10_super_E1, | |
7798 | z10_super_E1, | |
7799 | z10_super_E1, | |
7800 | z10_super_E1, | |
7801 | z10_super_E1, | |
7802 | z10_super_E1, | |
65b1d8ea | 7803 | *, |
9381e3f1 WG |
7804 | z10_super_E1, |
7805 | *, | |
7806 | *")]) | |
0dfa6c5e UW |
7807 | |
7808 | (define_split | |
7809 | [(set (match_operand:DI 0 "s_operand" "") | |
7810 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7811 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7812 | "reload_completed" |
7813 | [(parallel | |
7814 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7815 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7816 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7817 | |
9db1d521 HP |
7818 | ; |
7819 | ; iorsi3 instruction pattern(s). | |
7820 | ; | |
7821 | ||
4023fb28 | 7822 | (define_insn "*iorsi3_cc" |
ae156f85 | 7823 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7824 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7825 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7826 | (const_int 0))) |
65b1d8ea | 7827 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7828 | (ior:SI (match_dup 1) (match_dup 2)))] |
7829 | "s390_match_ccmode(insn, CCTmode)" | |
7830 | "@ | |
ec24698e | 7831 | oilf\t%0,%o2 |
d40c829f | 7832 | or\t%0,%2 |
65b1d8ea | 7833 | ork\t%0,%1,%2 |
d40c829f UW |
7834 | o\t%0,%2 |
7835 | oy\t%0,%2" | |
65b1d8ea | 7836 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7837 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7838 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7839 | |
7840 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7841 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7842 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7843 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7844 | (const_int 0))) |
65b1d8ea | 7845 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7846 | "s390_match_ccmode(insn, CCTmode)" |
7847 | "@ | |
ec24698e | 7848 | oilf\t%0,%o2 |
d40c829f | 7849 | or\t%0,%2 |
65b1d8ea | 7850 | ork\t%0,%1,%2 |
d40c829f UW |
7851 | o\t%0,%2 |
7852 | oy\t%0,%2" | |
65b1d8ea | 7853 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7854 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7855 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7856 | |
8cb66696 | 7857 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7858 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7859 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7860 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7861 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7862 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7863 | "@ |
f19a9af7 AK |
7864 | oilh\t%0,%i2 |
7865 | oill\t%0,%i2 | |
ec24698e | 7866 | oilf\t%0,%o2 |
d40c829f | 7867 | or\t%0,%2 |
65b1d8ea | 7868 | ork\t%0,%1,%2 |
d40c829f | 7869 | o\t%0,%2 |
8cb66696 | 7870 | oy\t%0,%2 |
0dfa6c5e | 7871 | # |
19b63d8e | 7872 | #" |
65b1d8ea | 7873 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7874 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7875 | (set_attr "z10prop" "z10_super_E1, |
7876 | z10_super_E1, | |
7877 | z10_super_E1, | |
7878 | z10_super_E1, | |
65b1d8ea | 7879 | *, |
9381e3f1 WG |
7880 | z10_super_E1, |
7881 | z10_super_E1, | |
7882 | *, | |
7883 | *")]) | |
8cb66696 UW |
7884 | |
7885 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7886 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7887 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7888 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7889 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7890 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7891 | "@ |
7892 | or\t%0,%2 | |
8cb66696 | 7893 | o\t%0,%2 |
0dfa6c5e | 7894 | # |
19b63d8e | 7895 | #" |
9381e3f1 WG |
7896 | [(set_attr "op_type" "RR,RX,SI,SS") |
7897 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7898 | |
7899 | (define_split | |
7900 | [(set (match_operand:SI 0 "s_operand" "") | |
7901 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7902 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7903 | "reload_completed" |
7904 | [(parallel | |
7905 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7906 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7907 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7908 | |
4023fb28 UW |
7909 | ; |
7910 | ; iorhi3 instruction pattern(s). | |
7911 | ; | |
7912 | ||
8cb66696 | 7913 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7914 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7915 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7916 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7917 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7918 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7919 | "@ |
d40c829f | 7920 | or\t%0,%2 |
65b1d8ea | 7921 | ork\t%0,%1,%2 |
8cb66696 | 7922 | oill\t%0,%x2 |
0dfa6c5e | 7923 | # |
19b63d8e | 7924 | #" |
65b1d8ea AK |
7925 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7926 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7927 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7928 | |
7929 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7930 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7931 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7932 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7933 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7934 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7935 | "@ | |
7936 | or\t%0,%2 | |
0dfa6c5e | 7937 | # |
19b63d8e | 7938 | #" |
9381e3f1 WG |
7939 | [(set_attr "op_type" "RR,SI,SS") |
7940 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7941 | |
7942 | (define_split | |
7943 | [(set (match_operand:HI 0 "s_operand" "") | |
7944 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7945 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7946 | "reload_completed" |
7947 | [(parallel | |
7948 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7949 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7950 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7951 | |
9db1d521 | 7952 | ; |
4023fb28 | 7953 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7954 | ; |
7955 | ||
8cb66696 | 7956 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7957 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7958 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7959 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7960 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7961 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7962 | "@ |
d40c829f | 7963 | or\t%0,%2 |
65b1d8ea | 7964 | ork\t%0,%1,%2 |
8cb66696 | 7965 | oill\t%0,%b2 |
fc0ea003 UW |
7966 | oi\t%S0,%b2 |
7967 | oiy\t%S0,%b2 | |
19b63d8e | 7968 | #" |
65b1d8ea | 7969 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7970 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
7971 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
7972 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7973 | |
7974 | (define_insn "*iorqi3_esa" | |
7975 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7976 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7977 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7978 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7979 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7980 | "@ |
8cb66696 | 7981 | or\t%0,%2 |
fc0ea003 | 7982 | oi\t%S0,%b2 |
19b63d8e | 7983 | #" |
9381e3f1 WG |
7984 | [(set_attr "op_type" "RR,SI,SS") |
7985 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7986 | |
19b63d8e UW |
7987 | ; |
7988 | ; Block inclusive or (OC) patterns. | |
7989 | ; | |
7990 | ||
7991 | (define_insn "*oc" | |
7992 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7993 | (ior:BLK (match_dup 0) | |
7994 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7995 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7996 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7997 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7998 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7999 | [(set_attr "op_type" "SS") |
8000 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8001 | |
8002 | (define_split | |
8003 | [(set (match_operand 0 "memory_operand" "") | |
8004 | (ior (match_dup 0) | |
8005 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8006 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8007 | "reload_completed |
8008 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8009 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8010 | [(parallel | |
8011 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
8012 | (use (match_dup 2)) | |
ae156f85 | 8013 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8014 | { |
8015 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8016 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8017 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8018 | }) | |
8019 | ||
8020 | (define_peephole2 | |
8021 | [(parallel | |
8022 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8023 | (ior:BLK (match_dup 0) | |
8024 | (match_operand:BLK 1 "memory_operand" ""))) | |
8025 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8026 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8027 | (parallel |
8028 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8029 | (ior:BLK (match_dup 3) | |
8030 | (match_operand:BLK 4 "memory_operand" ""))) | |
8031 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8032 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8033 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8034 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8035 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8036 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8037 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8038 | [(parallel | |
8039 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
8040 | (use (match_dup 8)) | |
ae156f85 | 8041 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8042 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8043 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8044 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8045 | ||
9db1d521 HP |
8046 | |
8047 | ;; | |
8048 | ;;- Xor instructions. | |
8049 | ;; | |
8050 | ||
047d35ed AS |
8051 | (define_expand "xor<mode>3" |
8052 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
8053 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
8054 | (match_operand:INT 2 "general_operand" ""))) | |
8055 | (clobber (reg:CC CC_REGNUM))] | |
8056 | "" | |
8057 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
8058 | ||
3c91f126 AK |
8059 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
8060 | ; simplifications. So its better to have something matching. | |
8061 | (define_split | |
8062 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
8063 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
8064 | "" | |
8065 | [(parallel | |
8066 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
8067 | (clobber (reg:CC CC_REGNUM))])] | |
8068 | { | |
8069 | operands[2] = constm1_rtx; | |
8070 | if (!s390_logical_operator_ok_p (operands)) | |
8071 | FAIL; | |
8072 | }) | |
8073 | ||
9db1d521 HP |
8074 | ; |
8075 | ; xordi3 instruction pattern(s). | |
8076 | ; | |
8077 | ||
4023fb28 | 8078 | (define_insn "*xordi3_cc" |
ae156f85 | 8079 | [(set (reg CC_REGNUM) |
3e4be43f UW |
8080 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
8081 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 8082 | (const_int 0))) |
3e4be43f | 8083 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 8084 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 8085 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 8086 | "@ |
d40c829f | 8087 | xgr\t%0,%2 |
65b1d8ea | 8088 | xgrk\t%0,%1,%2 |
d40c829f | 8089 | xg\t%0,%2" |
65b1d8ea | 8090 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 8091 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 8092 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
8093 | |
8094 | (define_insn "*xordi3_cconly" | |
ae156f85 | 8095 | [(set (reg CC_REGNUM) |
3e4be43f UW |
8096 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
8097 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 8098 | (const_int 0))) |
3e4be43f | 8099 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 8100 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 8101 | "@ |
d40c829f | 8102 | xgr\t%0,%2 |
65b1d8ea | 8103 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 8104 | xg\t%0,%2" |
65b1d8ea AK |
8105 | [(set_attr "op_type" "RRE,RRF,RXY") |
8106 | (set_attr "cpu_facility" "*,z196,*") | |
8107 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 8108 | |
3af8e996 | 8109 | (define_insn "*xordi3" |
3e4be43f UW |
8110 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
8111 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
8112 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 8113 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8114 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
8115 | "@ |
8116 | xihf\t%0,%k2 | |
8117 | xilf\t%0,%k2 | |
8118 | xgr\t%0,%2 | |
65b1d8ea | 8119 | xgrk\t%0,%1,%2 |
ec24698e UW |
8120 | xg\t%0,%2 |
8121 | # | |
8122 | #" | |
65b1d8ea AK |
8123 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
8124 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
8125 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
8126 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8127 | |
8128 | (define_split | |
8129 | [(set (match_operand:DI 0 "s_operand" "") | |
8130 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 8131 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8132 | "reload_completed" |
8133 | [(parallel | |
8134 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8135 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8136 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 8137 | |
9db1d521 HP |
8138 | ; |
8139 | ; xorsi3 instruction pattern(s). | |
8140 | ; | |
8141 | ||
4023fb28 | 8142 | (define_insn "*xorsi3_cc" |
ae156f85 | 8143 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8144 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8145 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8146 | (const_int 0))) |
65b1d8ea | 8147 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
8148 | (xor:SI (match_dup 1) (match_dup 2)))] |
8149 | "s390_match_ccmode(insn, CCTmode)" | |
8150 | "@ | |
ec24698e | 8151 | xilf\t%0,%o2 |
d40c829f | 8152 | xr\t%0,%2 |
65b1d8ea | 8153 | xrk\t%0,%1,%2 |
d40c829f UW |
8154 | x\t%0,%2 |
8155 | xy\t%0,%2" | |
65b1d8ea | 8156 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8157 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8158 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8159 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
8160 | |
8161 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 8162 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8163 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8164 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8165 | (const_int 0))) |
65b1d8ea | 8166 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
8167 | "s390_match_ccmode(insn, CCTmode)" |
8168 | "@ | |
ec24698e | 8169 | xilf\t%0,%o2 |
d40c829f | 8170 | xr\t%0,%2 |
65b1d8ea | 8171 | xrk\t%0,%1,%2 |
d40c829f UW |
8172 | x\t%0,%2 |
8173 | xy\t%0,%2" | |
65b1d8ea | 8174 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8175 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8176 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8177 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 8178 | |
8cb66696 | 8179 | (define_insn "*xorsi3" |
65b1d8ea AK |
8180 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
8181 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
8182 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 8183 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8184 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8185 | "@ |
ec24698e | 8186 | xilf\t%0,%o2 |
d40c829f | 8187 | xr\t%0,%2 |
65b1d8ea | 8188 | xrk\t%0,%1,%2 |
d40c829f | 8189 | x\t%0,%2 |
8cb66696 | 8190 | xy\t%0,%2 |
0dfa6c5e | 8191 | # |
19b63d8e | 8192 | #" |
65b1d8ea | 8193 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8194 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8195 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8196 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8197 | |
8198 | (define_split | |
8199 | [(set (match_operand:SI 0 "s_operand" "") | |
8200 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8201 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8202 | "reload_completed" |
8203 | [(parallel | |
8204 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8205 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8206 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8207 | |
9db1d521 HP |
8208 | ; |
8209 | ; xorhi3 instruction pattern(s). | |
8210 | ; | |
8211 | ||
8cb66696 | 8212 | (define_insn "*xorhi3" |
65b1d8ea AK |
8213 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8214 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8215 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8216 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8217 | "s390_logical_operator_ok_p (operands)" |
8218 | "@ | |
ec24698e | 8219 | xilf\t%0,%x2 |
8cb66696 | 8220 | xr\t%0,%2 |
65b1d8ea | 8221 | xrk\t%0,%1,%2 |
0dfa6c5e | 8222 | # |
19b63d8e | 8223 | #" |
65b1d8ea AK |
8224 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8225 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8226 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8227 | |
8228 | (define_split | |
8229 | [(set (match_operand:HI 0 "s_operand" "") | |
8230 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8231 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8232 | "reload_completed" |
8233 | [(parallel | |
8234 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8235 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8236 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8237 | |
9db1d521 HP |
8238 | ; |
8239 | ; xorqi3 instruction pattern(s). | |
8240 | ; | |
8241 | ||
8cb66696 | 8242 | (define_insn "*xorqi3" |
65b1d8ea AK |
8243 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8244 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8245 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8246 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8247 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8248 | "@ |
ec24698e | 8249 | xilf\t%0,%b2 |
8cb66696 | 8250 | xr\t%0,%2 |
65b1d8ea | 8251 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8252 | xi\t%S0,%b2 |
8253 | xiy\t%S0,%b2 | |
19b63d8e | 8254 | #" |
65b1d8ea | 8255 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8256 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8257 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8258 | |
4023fb28 | 8259 | |
19b63d8e UW |
8260 | ; |
8261 | ; Block exclusive or (XC) patterns. | |
8262 | ; | |
8263 | ||
8264 | (define_insn "*xc" | |
8265 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8266 | (xor:BLK (match_dup 0) | |
8267 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8268 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8269 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8270 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8271 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8272 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8273 | |
8274 | (define_split | |
8275 | [(set (match_operand 0 "memory_operand" "") | |
8276 | (xor (match_dup 0) | |
8277 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8278 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8279 | "reload_completed |
8280 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8281 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8282 | [(parallel | |
8283 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8284 | (use (match_dup 2)) | |
ae156f85 | 8285 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8286 | { |
8287 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8288 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8289 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8290 | }) | |
8291 | ||
8292 | (define_peephole2 | |
8293 | [(parallel | |
8294 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8295 | (xor:BLK (match_dup 0) | |
8296 | (match_operand:BLK 1 "memory_operand" ""))) | |
8297 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8298 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8299 | (parallel |
8300 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8301 | (xor:BLK (match_dup 3) | |
8302 | (match_operand:BLK 4 "memory_operand" ""))) | |
8303 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8304 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8305 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8306 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8307 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8308 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8309 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8310 | [(parallel | |
8311 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8312 | (use (match_dup 8)) | |
ae156f85 | 8313 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8314 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8315 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8316 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8317 | ||
8318 | ; | |
8319 | ; Block xor (XC) patterns with src == dest. | |
8320 | ; | |
8321 | ||
8322 | (define_insn "*xc_zero" | |
8323 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8324 | (const_int 0)) | |
8325 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8326 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8327 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8328 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8329 | [(set_attr "op_type" "SS") |
8330 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8331 | |
8332 | (define_peephole2 | |
8333 | [(parallel | |
8334 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8335 | (const_int 0)) | |
8336 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8337 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8338 | (parallel |
8339 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8340 | (const_int 0)) | |
8341 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8342 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8343 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8344 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8345 | [(parallel | |
8346 | [(set (match_dup 4) (const_int 0)) | |
8347 | (use (match_dup 5)) | |
ae156f85 | 8348 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8349 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8350 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8351 | ||
9db1d521 HP |
8352 | |
8353 | ;; | |
8354 | ;;- Negate instructions. | |
8355 | ;; | |
8356 | ||
8357 | ; | |
9a91a21f | 8358 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8359 | ; |
8360 | ||
9a91a21f | 8361 | (define_expand "neg<mode>2" |
9db1d521 | 8362 | [(parallel |
9a91a21f AS |
8363 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8364 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8365 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8366 | "" |
8367 | "") | |
8368 | ||
26a89301 | 8369 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8370 | [(set (reg CC_REGNUM) |
26a89301 UW |
8371 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8372 | (match_operand:SI 1 "register_operand" "d") 0) | |
8373 | (const_int 32)) (const_int 32))) | |
8374 | (const_int 0))) | |
8375 | (set (match_operand:DI 0 "register_operand" "=d") | |
8376 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8377 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8378 | "lcgfr\t%0,%1" |
729e750f WG |
8379 | [(set_attr "op_type" "RRE") |
8380 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8381 | |
26a89301 UW |
8382 | (define_insn "*negdi2_sign" |
8383 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8384 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8385 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8386 | "TARGET_ZARCH" |
26a89301 | 8387 | "lcgfr\t%0,%1" |
729e750f WG |
8388 | [(set_attr "op_type" "RRE") |
8389 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8390 | |
43a09b63 | 8391 | ; lcr, lcgr |
9a91a21f | 8392 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8393 | [(set (reg CC_REGNUM) |
9a91a21f | 8394 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8395 | (const_int 0))) |
9a91a21f AS |
8396 | (set (match_operand:GPR 0 "register_operand" "=d") |
8397 | (neg:GPR (match_dup 1)))] | |
8398 | "s390_match_ccmode (insn, CCAmode)" | |
8399 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8400 | [(set_attr "op_type" "RR<E>") |
8401 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8402 | |
8403 | ; lcr, lcgr | |
9a91a21f | 8404 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8405 | [(set (reg CC_REGNUM) |
9a91a21f | 8406 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8407 | (const_int 0))) |
9a91a21f AS |
8408 | (clobber (match_scratch:GPR 0 "=d"))] |
8409 | "s390_match_ccmode (insn, CCAmode)" | |
8410 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8411 | [(set_attr "op_type" "RR<E>") |
8412 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8413 | |
8414 | ; lcr, lcgr | |
9a91a21f AS |
8415 | (define_insn "*neg<mode>2" |
8416 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8417 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8418 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8419 | "" |
8420 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8421 | [(set_attr "op_type" "RR<E>") |
8422 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8423 | |
b7d19263 | 8424 | (define_insn "*negdi2_31" |
9db1d521 HP |
8425 | [(set (match_operand:DI 0 "register_operand" "=d") |
8426 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8427 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8428 | "!TARGET_ZARCH" |
b7d19263 AK |
8429 | "#") |
8430 | ||
8431 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8432 | ||
8433 | ; Doing the twos complement separately on the SImode parts does an | |
8434 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8435 | ; ... unless the +1 on the low part created an overflow. | |
8436 | ||
8437 | (define_split | |
8438 | [(set (match_operand:DI 0 "register_operand" "") | |
8439 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8440 | (clobber (reg:CC CC_REGNUM))] | |
8441 | "!TARGET_ZARCH | |
8442 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8443 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8444 | && reload_completed" | |
26a89301 UW |
8445 | [(parallel |
8446 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8447 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8448 | (parallel |
ae156f85 | 8449 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8450 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8451 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8452 | (set (pc) | |
ae156f85 | 8453 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8454 | (pc) |
8455 | (label_ref (match_dup 6)))) | |
8456 | (parallel | |
8457 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8458 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8459 | (match_dup 6)] |
8460 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8461 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8462 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8463 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8464 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8465 | |
b7d19263 AK |
8466 | ; Like above but first make a copy of the low part of the src operand |
8467 | ; since it might overlap with the high part of the destination. | |
8468 | ||
8469 | (define_split | |
8470 | [(set (match_operand:DI 0 "register_operand" "") | |
8471 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8472 | (clobber (reg:CC CC_REGNUM))] | |
8473 | "!TARGET_ZARCH | |
8474 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8475 | && reload_completed" | |
8476 | [; Make a backup of op5 first | |
8477 | (set (match_dup 4) (match_dup 5)) | |
8478 | ; Setting op2 here might clobber op5 | |
8479 | (parallel | |
8480 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8481 | (clobber (reg:CC CC_REGNUM))]) | |
8482 | (parallel | |
8483 | [(set (reg:CCAP CC_REGNUM) | |
8484 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8485 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8486 | (set (pc) | |
8487 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8488 | (pc) | |
8489 | (label_ref (match_dup 6)))) | |
8490 | (parallel | |
8491 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8492 | (clobber (reg:CC CC_REGNUM))]) | |
8493 | (match_dup 6)] | |
8494 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8495 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8496 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8497 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8498 | operands[6] = gen_label_rtx ();") | |
8499 | ||
9db1d521 | 8500 | ; |
f5905b37 | 8501 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8502 | ; |
8503 | ||
f5905b37 | 8504 | (define_expand "neg<mode>2" |
9db1d521 | 8505 | [(parallel |
2de2b3f9 AK |
8506 | [(set (match_operand:BFP 0 "register_operand") |
8507 | (neg:BFP (match_operand:BFP 1 "register_operand"))) | |
ae156f85 | 8508 | (clobber (reg:CC CC_REGNUM))])] |
2de2b3f9 | 8509 | "TARGET_HARD_FLOAT") |
9db1d521 | 8510 | |
43a09b63 | 8511 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8512 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8513 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8514 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8515 | (match_operand:BFP 2 "const0_operand" ""))) | |
8516 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8517 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8518 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8519 | "lc<xde>br\t%0,%1" |
26a89301 | 8520 | [(set_attr "op_type" "RRE") |
f5905b37 | 8521 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8522 | |
8523 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8524 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8525 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8526 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8527 | (match_operand:BFP 2 "const0_operand" ""))) | |
8528 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8529 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8530 | "lc<xde>br\t%0,%1" |
26a89301 | 8531 | [(set_attr "op_type" "RRE") |
f5905b37 | 8532 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8533 | |
85dae55a AK |
8534 | ; lcdfr |
8535 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8536 | [(set (match_operand:FP 0 "register_operand" "=f") |
8537 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8538 | "TARGET_DFP" |
85dae55a AK |
8539 | "lcdfr\t%0,%1" |
8540 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8541 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8542 | |
43a09b63 | 8543 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8544 | ; FIXME: wflcdb does not clobber cc |
2de2b3f9 | 8545 | ; FIXME: Does wflcdb ever match here? |
f5905b37 | 8546 | (define_insn "*neg<mode>2" |
2de2b3f9 AK |
8547 | [(set (match_operand:BFP 0 "register_operand" "=f,v,v") |
8548 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) | |
ae156f85 | 8549 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8550 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8551 | "@ |
8552 | lc<xde>br\t%0,%1 | |
2de2b3f9 AK |
8553 | wflcdb\t%0,%1 |
8554 | wflcsb\t%0,%1" | |
8555 | [(set_attr "op_type" "RRE,VRR,VRR") | |
8556 | (set_attr "cpu_facility" "*,vx,vxe") | |
8557 | (set_attr "type" "fsimp<mode>,*,*") | |
8558 | (set_attr "enabled" "*,<DF>,<SF>")]) | |
9db1d521 | 8559 | |
9db1d521 HP |
8560 | |
8561 | ;; | |
8562 | ;;- Absolute value instructions. | |
8563 | ;; | |
8564 | ||
8565 | ; | |
9a91a21f | 8566 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8567 | ; |
8568 | ||
26a89301 | 8569 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8570 | [(set (reg CC_REGNUM) |
26a89301 UW |
8571 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8572 | (match_operand:SI 1 "register_operand" "d") 0) | |
8573 | (const_int 32)) (const_int 32))) | |
8574 | (const_int 0))) | |
8575 | (set (match_operand:DI 0 "register_operand" "=d") | |
8576 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8577 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8578 | "lpgfr\t%0,%1" |
729e750f WG |
8579 | [(set_attr "op_type" "RRE") |
8580 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8581 | |
8582 | (define_insn "*absdi2_sign" | |
8583 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8584 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8585 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8586 | "TARGET_ZARCH" |
26a89301 | 8587 | "lpgfr\t%0,%1" |
729e750f WG |
8588 | [(set_attr "op_type" "RRE") |
8589 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8590 | |
43a09b63 | 8591 | ; lpr, lpgr |
9a91a21f | 8592 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8593 | [(set (reg CC_REGNUM) |
9a91a21f | 8594 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8595 | (const_int 0))) |
9a91a21f AS |
8596 | (set (match_operand:GPR 0 "register_operand" "=d") |
8597 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8598 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8599 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8600 | [(set_attr "op_type" "RR<E>") |
8601 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8602 | |
9381e3f1 | 8603 | ; lpr, lpgr |
9a91a21f | 8604 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8605 | [(set (reg CC_REGNUM) |
9a91a21f | 8606 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8607 | (const_int 0))) |
9a91a21f | 8608 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8609 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8610 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8611 | [(set_attr "op_type" "RR<E>") |
8612 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8613 | |
8614 | ; lpr, lpgr | |
9a91a21f AS |
8615 | (define_insn "abs<mode>2" |
8616 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8617 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8618 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8619 | "" |
9a91a21f | 8620 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8621 | [(set_attr "op_type" "RR<E>") |
8622 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8623 | |
9db1d521 | 8624 | ; |
f5905b37 | 8625 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8626 | ; |
8627 | ||
f5905b37 | 8628 | (define_expand "abs<mode>2" |
9db1d521 | 8629 | [(parallel |
7b6baae1 AK |
8630 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8631 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8632 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8633 | "TARGET_HARD_FLOAT" |
8634 | "") | |
8635 | ||
43a09b63 | 8636 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8637 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8638 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8639 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8640 | (match_operand:BFP 2 "const0_operand" ""))) | |
8641 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8642 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8643 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8644 | "lp<xde>br\t%0,%1" |
26a89301 | 8645 | [(set_attr "op_type" "RRE") |
f5905b37 | 8646 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8647 | |
8648 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8649 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8650 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8651 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8652 | (match_operand:BFP 2 "const0_operand" ""))) | |
8653 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8654 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8655 | "lp<xde>br\t%0,%1" |
26a89301 | 8656 | [(set_attr "op_type" "RRE") |
f5905b37 | 8657 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8658 | |
85dae55a AK |
8659 | ; lpdfr |
8660 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8661 | [(set (match_operand:FP 0 "register_operand" "=f") |
8662 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8663 | "TARGET_DFP" |
85dae55a AK |
8664 | "lpdfr\t%0,%1" |
8665 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8666 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8667 | |
43a09b63 | 8668 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8669 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8670 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8671 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8672 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8673 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8674 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8675 | "@ |
8676 | lp<xde>br\t%0,%1 | |
8677 | wflpdb\t%0,%1" | |
8678 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8679 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8680 | (set_attr "type" "fsimp<mode>,*") |
8681 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8682 | |
9db1d521 | 8683 | |
3ef093a8 AK |
8684 | ;; |
8685 | ;;- Negated absolute value instructions | |
8686 | ;; | |
8687 | ||
8688 | ; | |
8689 | ; Integer | |
8690 | ; | |
8691 | ||
26a89301 | 8692 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8693 | [(set (reg CC_REGNUM) |
26a89301 UW |
8694 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8695 | (match_operand:SI 1 "register_operand" "d") 0) | |
8696 | (const_int 32)) (const_int 32)))) | |
8697 | (const_int 0))) | |
8698 | (set (match_operand:DI 0 "register_operand" "=d") | |
8699 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8700 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8701 | "lngfr\t%0,%1" |
729e750f WG |
8702 | [(set_attr "op_type" "RRE") |
8703 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8704 | |
26a89301 UW |
8705 | (define_insn "*negabsdi2_sign" |
8706 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8707 | (neg:DI (abs:DI (sign_extend:DI | |
8708 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8709 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8710 | "TARGET_ZARCH" |
26a89301 | 8711 | "lngfr\t%0,%1" |
729e750f WG |
8712 | [(set_attr "op_type" "RRE") |
8713 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8714 | |
43a09b63 | 8715 | ; lnr, lngr |
9a91a21f | 8716 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8717 | [(set (reg CC_REGNUM) |
9a91a21f | 8718 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8719 | (const_int 0))) |
9a91a21f AS |
8720 | (set (match_operand:GPR 0 "register_operand" "=d") |
8721 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8722 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8723 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8724 | [(set_attr "op_type" "RR<E>") |
8725 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8726 | |
8727 | ; lnr, lngr | |
9a91a21f | 8728 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8729 | [(set (reg CC_REGNUM) |
9a91a21f | 8730 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8731 | (const_int 0))) |
9a91a21f | 8732 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8733 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8734 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8735 | [(set_attr "op_type" "RR<E>") |
8736 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8737 | |
8738 | ; lnr, lngr | |
9a91a21f AS |
8739 | (define_insn "*negabs<mode>2" |
8740 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8741 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8742 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8743 | "" |
9a91a21f | 8744 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8745 | [(set_attr "op_type" "RR<E>") |
8746 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8747 | |
3ef093a8 AK |
8748 | ; |
8749 | ; Floating point | |
8750 | ; | |
8751 | ||
43a09b63 | 8752 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8753 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8754 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8755 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8756 | (match_operand:BFP 2 "const0_operand" ""))) | |
8757 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8758 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8759 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8760 | "ln<xde>br\t%0,%1" |
26a89301 | 8761 | [(set_attr "op_type" "RRE") |
f5905b37 | 8762 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8763 | |
8764 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8765 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8766 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8767 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8768 | (match_operand:BFP 2 "const0_operand" ""))) | |
8769 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8770 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8771 | "ln<xde>br\t%0,%1" |
26a89301 | 8772 | [(set_attr "op_type" "RRE") |
f5905b37 | 8773 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8774 | |
85dae55a AK |
8775 | ; lndfr |
8776 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8777 | [(set (match_operand:FP 0 "register_operand" "=f") |
8778 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8779 | "TARGET_DFP" |
85dae55a AK |
8780 | "lndfr\t%0,%1" |
8781 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8782 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8783 | |
43a09b63 | 8784 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8785 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8786 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8787 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8788 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8789 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8790 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8791 | "@ |
8792 | ln<xde>br\t%0,%1 | |
8793 | wflndb\t%0,%1" | |
8794 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8795 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8796 | (set_attr "type" "fsimp<mode>,*") |
8797 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8798 | |
4023fb28 UW |
8799 | ;; |
8800 | ;;- Square root instructions. | |
8801 | ;; | |
8802 | ||
8803 | ; | |
f5905b37 | 8804 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8805 | ; |
8806 | ||
9381e3f1 | 8807 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8808 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8809 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8810 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8811 | "TARGET_HARD_FLOAT" |
4023fb28 | 8812 | "@ |
f61a2c7d | 8813 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8814 | sq<xde>b\t%0,%1 |
8815 | wfsqdb\t%v0,%v1" | |
8816 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8817 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 8818 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 8819 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 8820 | |
9db1d521 HP |
8821 | |
8822 | ;; | |
8823 | ;;- One complement instructions. | |
8824 | ;; | |
8825 | ||
8826 | ; | |
342cf42b | 8827 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8828 | ; |
c7453384 | 8829 | |
342cf42b | 8830 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8831 | [(parallel |
342cf42b AS |
8832 | [(set (match_operand:INT 0 "register_operand" "") |
8833 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8834 | (const_int -1))) | |
ae156f85 | 8835 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8836 | "" |
4023fb28 | 8837 | "") |
9db1d521 HP |
8838 | |
8839 | ||
ec24698e UW |
8840 | ;; |
8841 | ;; Find leftmost bit instructions. | |
8842 | ;; | |
8843 | ||
8844 | (define_expand "clzdi2" | |
8845 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8846 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8847 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 8848 | { |
d8485bdb TS |
8849 | rtx_insn *insn; |
8850 | rtx clz_equal; | |
ec24698e | 8851 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 8852 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
8853 | |
8854 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8855 | ||
8856 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8857 | ||
9381e3f1 | 8858 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8859 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8860 | |
8861 | DONE; | |
8862 | }) | |
8863 | ||
8864 | (define_insn "clztidi2" | |
8865 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8866 | (ior:TI | |
9381e3f1 WG |
8867 | (ashift:TI |
8868 | (zero_extend:TI | |
ec24698e UW |
8869 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8870 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8871 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8872 | |
ec24698e UW |
8873 | (const_int 64)) |
8874 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8875 | (clobber (reg:CC CC_REGNUM))] | |
406fde6e | 8876 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 8877 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8878 | "flogr\t%0,%1" |
8879 | [(set_attr "op_type" "RRE")]) | |
8880 | ||
8881 | ||
9db1d521 HP |
8882 | ;; |
8883 | ;;- Rotate instructions. | |
8884 | ;; | |
8885 | ||
8886 | ; | |
9a91a21f | 8887 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8888 | ; |
8889 | ||
191eb16d AK |
8890 | (define_expand "rotl<mode>3" |
8891 | [(set (match_operand:GPR 0 "register_operand" "") | |
8892 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8893 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
9e8327e3 | 8894 | "TARGET_CPU_ZARCH" |
191eb16d | 8895 | "") |
9db1d521 | 8896 | |
43a09b63 | 8897 | ; rll, rllg |
191eb16d AK |
8898 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8899 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8900 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8901 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8902 | "TARGET_CPU_ZARCH" | |
8903 | "rll<g>\t%0,%1,<addr_style_op_ops>" | |
4989e88a | 8904 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8905 | (set_attr "atype" "reg") |
191eb16d | 8906 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8907 | |
9db1d521 HP |
8908 | |
8909 | ;; | |
f337b930 | 8910 | ;;- Shift instructions. |
9db1d521 | 8911 | ;; |
9db1d521 HP |
8912 | |
8913 | ; | |
1b48c8cc | 8914 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8915 | ; Left shifts and logical right shifts |
9db1d521 | 8916 | |
1b48c8cc AS |
8917 | (define_expand "<shift><mode>3" |
8918 | [(set (match_operand:DSI 0 "register_operand" "") | |
8919 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8920 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8921 | "" |
8922 | "") | |
8923 | ||
adf22b3f | 8924 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8925 | ; sldl, srdl |
adf22b3f AK |
8926 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8927 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8928 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8929 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8930 | "!TARGET_ZARCH" |
adf22b3f | 8931 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8932 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8933 | (set_attr "atype" "reg") |
8934 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8935 | |
adf22b3f AK |
8936 | |
8937 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8938 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8939 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8940 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8941 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8942 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8943 | "" |
65b1d8ea | 8944 | "@ |
adf22b3f AK |
8945 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8946 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8947 | [(set_attr "op_type" "RS<E>,RSY") |
8948 | (set_attr "atype" "reg,reg") | |
8949 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8950 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8951 | |
9db1d521 | 8952 | ; |
1b48c8cc | 8953 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8954 | ; Arithmetic right shifts |
9db1d521 | 8955 | |
1b48c8cc | 8956 | (define_expand "ashr<mode>3" |
9db1d521 | 8957 | [(parallel |
1b48c8cc AS |
8958 | [(set (match_operand:DSI 0 "register_operand" "") |
8959 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8960 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8961 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8962 | "" |
8963 | "") | |
8964 | ||
a9fcf821 AK |
8965 | ; FIXME: The number of alternatives is doubled here to match the fix |
8966 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8967 | ; The right fix should be to support match_scratch in the output | |
8968 | ; pattern of a define_subst. | |
8969 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8970 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8971 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8972 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8973 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8974 | "!TARGET_ZARCH" |
65b1d8ea | 8975 | "@ |
a9fcf821 AK |
8976 | srda\t%0,<addr_style_op_cc_ops> |
8977 | srda\t%0,<addr_style_op_cc_ops>" | |
8978 | [(set_attr "op_type" "RS") | |
8979 | (set_attr "atype" "reg")]) | |
ecbe845e | 8980 | |
ecbe845e | 8981 | |
43a09b63 | 8982 | ; sra, srag |
a9fcf821 AK |
8983 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8984 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8985 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8986 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8987 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8988 | "" |
65b1d8ea | 8989 | "@ |
a9fcf821 AK |
8990 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8991 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8992 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8993 | (set_attr "atype" "reg") |
01496eca | 8994 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8995 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8996 | |
9db1d521 | 8997 | |
9db1d521 HP |
8998 | ;; |
8999 | ;; Branch instruction patterns. | |
9000 | ;; | |
9001 | ||
f90b7a5a | 9002 | (define_expand "cbranch<mode>4" |
fa77b251 | 9003 | [(set (pc) |
f90b7a5a PB |
9004 | (if_then_else (match_operator 0 "comparison_operator" |
9005 | [(match_operand:GPR 1 "register_operand" "") | |
9006 | (match_operand:GPR 2 "general_operand" "")]) | |
9007 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 9008 | (pc)))] |
ba956982 | 9009 | "" |
f90b7a5a PB |
9010 | "s390_emit_jump (operands[3], |
9011 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
9012 | DONE;") | |
9013 | ||
9014 | (define_expand "cbranch<mode>4" | |
9015 | [(set (pc) | |
9016 | (if_then_else (match_operator 0 "comparison_operator" | |
9017 | [(match_operand:FP 1 "register_operand" "") | |
9018 | (match_operand:FP 2 "general_operand" "")]) | |
9019 | (label_ref (match_operand 3 "" "")) | |
9020 | (pc)))] | |
9021 | "TARGET_HARD_FLOAT" | |
9022 | "s390_emit_jump (operands[3], | |
9023 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
9024 | DONE;") | |
9025 | ||
9026 | (define_expand "cbranchcc4" | |
9027 | [(set (pc) | |
de6fba39 | 9028 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 9029 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 9030 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
9031 | (label_ref (match_operand 3 "" "")) |
9032 | (pc)))] | |
de6fba39 UW |
9033 | "" |
9034 | "") | |
ba956982 | 9035 | |
9db1d521 HP |
9036 | |
9037 | ;; | |
9038 | ;;- Conditional jump instructions. | |
9039 | ;; | |
9040 | ||
6590e19a UW |
9041 | (define_insn "*cjump_64" |
9042 | [(set (pc) | |
9043 | (if_then_else | |
5a3fe9b6 AK |
9044 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
9045 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
9046 | (label_ref (match_operand 0 "" "")) |
9047 | (pc)))] | |
9048 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9049 | { |
13e58269 | 9050 | if (get_attr_length (insn) == 4) |
d40c829f | 9051 | return "j%C1\t%l0"; |
6590e19a | 9052 | else |
d40c829f | 9053 | return "jg%C1\t%l0"; |
6590e19a UW |
9054 | } |
9055 | [(set_attr "op_type" "RI") | |
9056 | (set_attr "type" "branch") | |
9057 | (set (attr "length") | |
9058 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9059 | (const_int 4) (const_int 6)))]) | |
9060 | ||
9061 | (define_insn "*cjump_31" | |
9062 | [(set (pc) | |
9063 | (if_then_else | |
5a3fe9b6 AK |
9064 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
9065 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
9066 | (label_ref (match_operand 0 "" "")) |
9067 | (pc)))] | |
9068 | "!TARGET_CPU_ZARCH" | |
9069 | { | |
8d933e31 AS |
9070 | gcc_assert (get_attr_length (insn) == 4); |
9071 | return "j%C1\t%l0"; | |
10bbf137 | 9072 | } |
9db1d521 | 9073 | [(set_attr "op_type" "RI") |
077dab3b | 9074 | (set_attr "type" "branch") |
13e58269 | 9075 | (set (attr "length") |
d7f99b2c | 9076 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9077 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9078 | (const_int 4) (const_int 6)) | |
9079 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9080 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9081 | |
f314b9b1 | 9082 | (define_insn "*cjump_long" |
6590e19a UW |
9083 | [(set (pc) |
9084 | (if_then_else | |
ae156f85 | 9085 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 9086 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 9087 | (pc)))] |
84b4c7b5 | 9088 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9089 | { |
9090 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9091 | return "b%C1r\t%0"; |
f314b9b1 | 9092 | else |
d40c829f | 9093 | return "b%C1\t%a0"; |
10bbf137 | 9094 | } |
c7453384 | 9095 | [(set (attr "op_type") |
f314b9b1 UW |
9096 | (if_then_else (match_operand 0 "register_operand" "") |
9097 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9098 | (set (attr "mnemonic") |
9099 | (if_then_else (match_operand 0 "register_operand" "") | |
9100 | (const_string "bcr") (const_string "bc"))) | |
6590e19a | 9101 | (set_attr "type" "branch") |
077dab3b | 9102 | (set_attr "atype" "agen")]) |
9db1d521 | 9103 | |
177bc204 RS |
9104 | ;; A conditional return instruction. |
9105 | (define_insn "*c<code>" | |
9106 | [(set (pc) | |
9107 | (if_then_else | |
9108 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
9109 | (ANY_RETURN) | |
9110 | (pc)))] | |
9111 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
9112 | { |
9113 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
9114 | { | |
9115 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
9116 | INVALID_REGNUM, | |
9117 | operands[0], | |
9118 | s390_indirect_branch_type_return); | |
9119 | return ""; | |
9120 | } | |
9121 | else | |
9122 | return "b%C0r\t%%r14"; | |
9123 | } | |
9124 | [(set (attr "op_type") | |
9125 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9126 | (const_string "RIL") | |
9127 | (const_string "RR"))) | |
9128 | (set (attr "mnemonic") | |
9129 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9130 | (const_string "brcl") | |
9131 | (const_string "bcr"))) | |
177bc204 RS |
9132 | (set_attr "type" "jsr") |
9133 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
9134 | |
9135 | ;; | |
9136 | ;;- Negated conditional jump instructions. | |
9137 | ;; | |
9138 | ||
6590e19a UW |
9139 | (define_insn "*icjump_64" |
9140 | [(set (pc) | |
9141 | (if_then_else | |
ae156f85 | 9142 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9143 | (pc) |
9144 | (label_ref (match_operand 0 "" ""))))] | |
9145 | "TARGET_CPU_ZARCH" | |
c7453384 | 9146 | { |
13e58269 | 9147 | if (get_attr_length (insn) == 4) |
d40c829f | 9148 | return "j%D1\t%l0"; |
6590e19a | 9149 | else |
d40c829f | 9150 | return "jg%D1\t%l0"; |
6590e19a UW |
9151 | } |
9152 | [(set_attr "op_type" "RI") | |
9153 | (set_attr "type" "branch") | |
9154 | (set (attr "length") | |
9155 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9156 | (const_int 4) (const_int 6)))]) | |
9157 | ||
9158 | (define_insn "*icjump_31" | |
9159 | [(set (pc) | |
9160 | (if_then_else | |
ae156f85 | 9161 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9162 | (pc) |
9163 | (label_ref (match_operand 0 "" ""))))] | |
9164 | "!TARGET_CPU_ZARCH" | |
9165 | { | |
8d933e31 AS |
9166 | gcc_assert (get_attr_length (insn) == 4); |
9167 | return "j%D1\t%l0"; | |
10bbf137 | 9168 | } |
9db1d521 | 9169 | [(set_attr "op_type" "RI") |
077dab3b | 9170 | (set_attr "type" "branch") |
13e58269 | 9171 | (set (attr "length") |
d7f99b2c | 9172 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9173 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9174 | (const_int 4) (const_int 6)) | |
9175 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9176 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9177 | |
f314b9b1 | 9178 | (define_insn "*icjump_long" |
6590e19a UW |
9179 | [(set (pc) |
9180 | (if_then_else | |
ae156f85 | 9181 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 9182 | (pc) |
4fe6dea8 | 9183 | (match_operand 0 "address_operand" "ZQZR")))] |
84b4c7b5 | 9184 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9185 | { |
9186 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9187 | return "b%D1r\t%0"; |
f314b9b1 | 9188 | else |
d40c829f | 9189 | return "b%D1\t%a0"; |
10bbf137 | 9190 | } |
c7453384 | 9191 | [(set (attr "op_type") |
f314b9b1 UW |
9192 | (if_then_else (match_operand 0 "register_operand" "") |
9193 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9194 | (set (attr "mnemonic") |
9195 | (if_then_else (match_operand 0 "register_operand" "") | |
9196 | (const_string "bcr") (const_string "bc"))) | |
077dab3b HP |
9197 | (set_attr "type" "branch") |
9198 | (set_attr "atype" "agen")]) | |
9db1d521 | 9199 | |
4456530d HP |
9200 | ;; |
9201 | ;;- Trap instructions. | |
9202 | ;; | |
9203 | ||
9204 | (define_insn "trap" | |
9205 | [(trap_if (const_int 1) (const_int 0))] | |
9206 | "" | |
d40c829f | 9207 | "j\t.+2" |
6590e19a | 9208 | [(set_attr "op_type" "RI") |
077dab3b | 9209 | (set_attr "type" "branch")]) |
4456530d | 9210 | |
f90b7a5a PB |
9211 | (define_expand "ctrap<mode>4" |
9212 | [(trap_if (match_operator 0 "comparison_operator" | |
9213 | [(match_operand:GPR 1 "register_operand" "") | |
9214 | (match_operand:GPR 2 "general_operand" "")]) | |
9215 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 9216 | "" |
f90b7a5a PB |
9217 | { |
9218 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9219 | operands[1], operands[2]); | |
9220 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9221 | DONE; | |
9222 | }) | |
9223 | ||
9224 | (define_expand "ctrap<mode>4" | |
9225 | [(trap_if (match_operator 0 "comparison_operator" | |
9226 | [(match_operand:FP 1 "register_operand" "") | |
9227 | (match_operand:FP 2 "general_operand" "")]) | |
9228 | (match_operand 3 "const0_operand" ""))] | |
9229 | "" | |
9230 | { | |
9231 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9232 | operands[1], operands[2]); | |
9233 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9234 | DONE; | |
9235 | }) | |
4456530d | 9236 | |
f90b7a5a PB |
9237 | (define_insn "condtrap" |
9238 | [(trap_if (match_operator 0 "s390_comparison" | |
9239 | [(match_operand 1 "cc_reg_operand" "c") | |
9240 | (const_int 0)]) | |
4456530d HP |
9241 | (const_int 0))] |
9242 | "" | |
d40c829f | 9243 | "j%C0\t.+2"; |
077dab3b HP |
9244 | [(set_attr "op_type" "RI") |
9245 | (set_attr "type" "branch")]) | |
9db1d521 | 9246 | |
963fc8d0 AK |
9247 | ; crt, cgrt, cit, cgit |
9248 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9249 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9250 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9251 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9252 | (const_int 0))] | |
9253 | "TARGET_Z10" | |
9254 | "@ | |
9255 | c<g>rt%C0\t%1,%2 | |
9256 | c<g>it%C0\t%1,%h2" | |
9257 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9258 | (set_attr "type" "branch") |
729e750f | 9259 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9260 | |
22ac2c2f | 9261 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9262 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9263 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9264 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9265 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9266 | (const_int 0))] |
9267 | "TARGET_Z10" | |
9268 | "@ | |
9269 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9270 | cl<gf>it%C0\t%1,%x2 |
9271 | cl<g>t%C0\t%1,%2" | |
9272 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9273 | (set_attr "type" "branch") | |
9274 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9275 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9276 | ||
9277 | ; lat, lgat | |
9278 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9279 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9280 | (const_int 0)) |
9281 | (const_int 0)) | |
9282 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9283 | (match_dup 0))] | |
9284 | "TARGET_ZEC12" | |
9285 | "l<g>at\t%1,%0" | |
9286 | [(set_attr "op_type" "RXY")]) | |
9287 | ||
963fc8d0 | 9288 | |
9db1d521 | 9289 | ;; |
0a3bdf9d | 9290 | ;;- Loop instructions. |
9db1d521 | 9291 | ;; |
0a3bdf9d UW |
9292 | ;; This is all complicated by the fact that since this is a jump insn |
9293 | ;; we must handle our own output reloads. | |
c7453384 | 9294 | |
f1149235 AK |
9295 | ;; branch on index |
9296 | ||
9297 | ; This splitter will be matched by combine and has to add the 2 moves | |
9298 | ; necessary to load the compare and the increment values into a | |
9299 | ; register pair as needed by brxle. | |
9300 | ||
9301 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9302 | [(set (pc) | |
9303 | (if_then_else | |
9304 | (match_operator 6 "s390_brx_operator" | |
9305 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9306 | (match_operand:GPR 2 "general_operand" "")) | |
9307 | (match_operand:GPR 3 "register_operand" "")]) | |
9308 | (label_ref (match_operand 0 "" "")) | |
9309 | (pc))) | |
9310 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9311 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9312 | (clobber (match_scratch:GPR 5 ""))] | |
9313 | "TARGET_CPU_ZARCH" | |
9314 | "#" | |
9315 | "!reload_completed && !reload_in_progress" | |
9316 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9317 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9318 | (parallel [(set (pc) | |
9319 | (if_then_else | |
9320 | (match_op_dup 6 | |
9321 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9322 | (match_dup 8)]) | |
9323 | (label_ref (match_dup 0)) | |
9324 | (pc))) | |
9325 | (set (match_dup 4) | |
9326 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9327 | (clobber (match_dup 5)) | |
9328 | (clobber (reg:CC CC_REGNUM))])] | |
9329 | { | |
9330 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9331 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9332 | gen_highpart (word_mode, dreg)); | |
9333 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9334 | gen_lowpart (word_mode, dreg)); | |
9335 | }) | |
9336 | ||
9337 | ; brxlg, brxhg | |
9338 | ||
9339 | (define_insn_and_split "*brxg_64bit" | |
9340 | [(set (pc) | |
9341 | (if_then_else | |
9342 | (match_operator 5 "s390_brx_operator" | |
9343 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9344 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9345 | (subreg:DI (match_dup 2) 8)]) | |
9346 | (label_ref (match_operand 0 "" "")) | |
9347 | (pc))) | |
9348 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9349 | (plus:DI (match_dup 1) | |
9350 | (subreg:DI (match_dup 2) 0))) | |
9351 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9352 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9353 | "TARGET_ZARCH" |
f1149235 AK |
9354 | { |
9355 | if (which_alternative != 0) | |
9356 | return "#"; | |
9357 | else if (get_attr_length (insn) == 6) | |
9358 | return "brx%E5g\t%1,%2,%l0"; | |
9359 | else | |
9360 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9361 | } | |
9362 | "&& reload_completed | |
9363 | && (!REG_P (operands[3]) | |
9364 | || !rtx_equal_p (operands[1], operands[3]))" | |
9365 | [(set (match_dup 4) (match_dup 1)) | |
9366 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9367 | (clobber (reg:CC CC_REGNUM))]) | |
9368 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9369 | (set (match_dup 3) (match_dup 4)) | |
9370 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9371 | (label_ref (match_dup 0)) | |
9372 | (pc)))] | |
9373 | "" | |
9374 | [(set_attr "op_type" "RIE") | |
9375 | (set_attr "type" "branch") | |
9376 | (set (attr "length") | |
9377 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9378 | (const_int 6) (const_int 16)))]) | |
9379 | ||
9380 | ; brxle, brxh | |
9381 | ||
9382 | (define_insn_and_split "*brx_64bit" | |
9383 | [(set (pc) | |
9384 | (if_then_else | |
9385 | (match_operator 5 "s390_brx_operator" | |
9386 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9387 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9388 | (subreg:SI (match_dup 2) 12)]) | |
9389 | (label_ref (match_operand 0 "" "")) | |
9390 | (pc))) | |
9391 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9392 | (plus:SI (match_dup 1) | |
9393 | (subreg:SI (match_dup 2) 4))) | |
9394 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9395 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9396 | "TARGET_ZARCH" |
f1149235 AK |
9397 | { |
9398 | if (which_alternative != 0) | |
9399 | return "#"; | |
9400 | else if (get_attr_length (insn) == 6) | |
9401 | return "brx%C5\t%1,%2,%l0"; | |
9402 | else | |
9403 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9404 | } | |
9405 | "&& reload_completed | |
9406 | && (!REG_P (operands[3]) | |
9407 | || !rtx_equal_p (operands[1], operands[3]))" | |
9408 | [(set (match_dup 4) (match_dup 1)) | |
9409 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9410 | (clobber (reg:CC CC_REGNUM))]) | |
9411 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9412 | (set (match_dup 3) (match_dup 4)) | |
9413 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9414 | (label_ref (match_dup 0)) | |
9415 | (pc)))] | |
9416 | "" | |
9417 | [(set_attr "op_type" "RSI") | |
9418 | (set_attr "type" "branch") | |
9419 | (set (attr "length") | |
9420 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9421 | (const_int 6) (const_int 14)))]) | |
9422 | ||
9423 | ; brxle, brxh | |
9424 | ||
9425 | (define_insn_and_split "*brx_31bit" | |
9426 | [(set (pc) | |
9427 | (if_then_else | |
9428 | (match_operator 5 "s390_brx_operator" | |
9429 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9430 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9431 | (subreg:SI (match_dup 2) 4)]) | |
9432 | (label_ref (match_operand 0 "" "")) | |
9433 | (pc))) | |
9434 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9435 | (plus:SI (match_dup 1) | |
9436 | (subreg:SI (match_dup 2) 0))) | |
9437 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9438 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9439 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
9440 | { |
9441 | if (which_alternative != 0) | |
9442 | return "#"; | |
9443 | else if (get_attr_length (insn) == 6) | |
9444 | return "brx%C5\t%1,%2,%l0"; | |
9445 | else | |
9446 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9447 | } | |
9448 | "&& reload_completed | |
9449 | && (!REG_P (operands[3]) | |
9450 | || !rtx_equal_p (operands[1], operands[3]))" | |
9451 | [(set (match_dup 4) (match_dup 1)) | |
9452 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9453 | (clobber (reg:CC CC_REGNUM))]) | |
9454 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9455 | (set (match_dup 3) (match_dup 4)) | |
9456 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9457 | (label_ref (match_dup 0)) | |
9458 | (pc)))] | |
9459 | "" | |
9460 | [(set_attr "op_type" "RSI") | |
9461 | (set_attr "type" "branch") | |
9462 | (set (attr "length") | |
9463 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9464 | (const_int 6) (const_int 14)))]) | |
9465 | ||
9466 | ||
9467 | ;; branch on count | |
9468 | ||
0a3bdf9d UW |
9469 | (define_expand "doloop_end" |
9470 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9471 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9472 | "" |
0a3bdf9d | 9473 | { |
6590e19a | 9474 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 9475 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 9476 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 9477 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9478 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9479 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9480 | else |
9481 | FAIL; | |
9482 | ||
9483 | DONE; | |
10bbf137 | 9484 | }) |
0a3bdf9d | 9485 | |
6590e19a | 9486 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9487 | [(set (pc) |
9488 | (if_then_else | |
7e665d18 | 9489 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9490 | (const_int 1)) |
9491 | (label_ref (match_operand 0 "" "")) | |
9492 | (pc))) | |
7e665d18 | 9493 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9494 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9495 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9496 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9497 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9498 | { |
9499 | if (which_alternative != 0) | |
10bbf137 | 9500 | return "#"; |
0a3bdf9d | 9501 | else if (get_attr_length (insn) == 4) |
d40c829f | 9502 | return "brct\t%1,%l0"; |
6590e19a | 9503 | else |
545d16ff | 9504 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9505 | } |
9506 | "&& reload_completed | |
9507 | && (! REG_P (operands[2]) | |
9508 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9509 | [(set (match_dup 3) (match_dup 1)) |
9510 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9511 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9512 | (const_int 0))) | |
9513 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9514 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9515 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9516 | (label_ref (match_dup 0)) |
9517 | (pc)))] | |
9518 | "" | |
9519 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9520 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9521 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9522 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9523 | (set_attr "type" "branch") |
9524 | (set (attr "length") | |
9525 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9526 | (const_int 4) (const_int 10)))]) | |
9527 | ||
9528 | (define_insn_and_split "doloop_si31" | |
9529 | [(set (pc) | |
9530 | (if_then_else | |
7e665d18 | 9531 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
9532 | (const_int 1)) |
9533 | (label_ref (match_operand 0 "" "")) | |
9534 | (pc))) | |
7e665d18 | 9535 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 9536 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9537 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9538 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
9539 | "!TARGET_CPU_ZARCH" |
9540 | { | |
9541 | if (which_alternative != 0) | |
9542 | return "#"; | |
9543 | else if (get_attr_length (insn) == 4) | |
9544 | return "brct\t%1,%l0"; | |
0a3bdf9d | 9545 | else |
8d933e31 | 9546 | gcc_unreachable (); |
10bbf137 | 9547 | } |
6590e19a UW |
9548 | "&& reload_completed |
9549 | && (! REG_P (operands[2]) | |
9550 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9551 | [(set (match_dup 3) (match_dup 1)) |
9552 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9553 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9554 | (const_int 0))) | |
9555 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9556 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9557 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9558 | (label_ref (match_dup 0)) |
9559 | (pc)))] | |
9560 | "" | |
0a3bdf9d | 9561 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
9562 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9563 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9564 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 9565 | (set_attr "type" "branch") |
0a3bdf9d | 9566 | (set (attr "length") |
d7f99b2c | 9567 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9568 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9569 | (const_int 4) (const_int 6)) | |
9570 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9571 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9572 | |
0a3bdf9d UW |
9573 | (define_insn "*doloop_si_long" |
9574 | [(set (pc) | |
9575 | (if_then_else | |
7e665d18 | 9576 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 9577 | (const_int 1)) |
3e4be43f | 9578 | (match_operand 0 "address_operand" "ZR") |
0a3bdf9d | 9579 | (pc))) |
7e665d18 | 9580 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 9581 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9582 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 9583 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9584 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9585 | { |
9586 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9587 | return "bctr\t%1,%0"; |
0a3bdf9d | 9588 | else |
d40c829f | 9589 | return "bct\t%1,%a0"; |
10bbf137 | 9590 | } |
c7453384 | 9591 | [(set (attr "op_type") |
0a3bdf9d UW |
9592 | (if_then_else (match_operand 0 "register_operand" "") |
9593 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9594 | (set_attr "type" "branch") |
729e750f | 9595 | (set_attr "atype" "agen") |
65b1d8ea AK |
9596 | (set_attr "z10prop" "z10_c") |
9597 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 9598 | |
6590e19a | 9599 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9600 | [(set (pc) |
9601 | (if_then_else | |
7e665d18 | 9602 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9603 | (const_int 1)) |
9604 | (label_ref (match_operand 0 "" "")) | |
9605 | (pc))) | |
7e665d18 | 9606 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9607 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9608 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9609 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9610 | "TARGET_ZARCH" |
0a3bdf9d UW |
9611 | { |
9612 | if (which_alternative != 0) | |
10bbf137 | 9613 | return "#"; |
0a3bdf9d | 9614 | else if (get_attr_length (insn) == 4) |
d40c829f | 9615 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9616 | else |
545d16ff | 9617 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9618 | } |
6590e19a | 9619 | "&& reload_completed |
0a3bdf9d UW |
9620 | && (! REG_P (operands[2]) |
9621 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9622 | [(set (match_dup 3) (match_dup 1)) |
9623 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9624 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9625 | (const_int 0))) | |
9626 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9627 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9628 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9629 | (label_ref (match_dup 0)) |
0a3bdf9d | 9630 | (pc)))] |
6590e19a UW |
9631 | "" |
9632 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9633 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9634 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9635 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9636 | (set_attr "type" "branch") |
9637 | (set (attr "length") | |
9638 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9639 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9640 | |
9641 | ;; | |
9642 | ;;- Unconditional jump instructions. | |
9643 | ;; | |
9644 | ||
9645 | ; | |
9646 | ; jump instruction pattern(s). | |
9647 | ; | |
9648 | ||
6590e19a UW |
9649 | (define_expand "jump" |
9650 | [(match_operand 0 "" "")] | |
9db1d521 | 9651 | "" |
6590e19a UW |
9652 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9653 | ||
9654 | (define_insn "*jump64" | |
9655 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9656 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9657 | { |
13e58269 | 9658 | if (get_attr_length (insn) == 4) |
d40c829f | 9659 | return "j\t%l0"; |
6590e19a | 9660 | else |
d40c829f | 9661 | return "jg\t%l0"; |
6590e19a UW |
9662 | } |
9663 | [(set_attr "op_type" "RI") | |
9664 | (set_attr "type" "branch") | |
9665 | (set (attr "length") | |
9666 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9667 | (const_int 4) (const_int 6)))]) | |
9668 | ||
9669 | (define_insn "*jump31" | |
9670 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9671 | "!TARGET_CPU_ZARCH" | |
9672 | { | |
8d933e31 AS |
9673 | gcc_assert (get_attr_length (insn) == 4); |
9674 | return "j\t%l0"; | |
10bbf137 | 9675 | } |
9db1d521 | 9676 | [(set_attr "op_type" "RI") |
077dab3b | 9677 | (set_attr "type" "branch") |
13e58269 | 9678 | (set (attr "length") |
d7f99b2c | 9679 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9680 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9681 | (const_int 4) (const_int 6)) | |
9682 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9683 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
9684 | |
9685 | ; | |
9686 | ; indirect-jump instruction pattern(s). | |
9687 | ; | |
9688 | ||
2841f550 AK |
9689 | (define_expand "indirect_jump" |
9690 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9691 | "" |
f314b9b1 | 9692 | { |
2841f550 AK |
9693 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9694 | ; | |
9695 | else if (TARGET_ARCH12 | |
9696 | && GET_MODE (operands[0]) == Pmode | |
9697 | && memory_operand (operands[0], Pmode)) | |
9698 | ; | |
f314b9b1 | 9699 | else |
2841f550 | 9700 | operands[0] = force_reg (Pmode, operands[0]); |
84b4c7b5 AK |
9701 | |
9702 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9703 | { | |
9704 | operands[0] = force_reg (Pmode, operands[0]); | |
9705 | if (TARGET_CPU_Z10) | |
9706 | { | |
9707 | if (TARGET_64BIT) | |
9708 | emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); | |
9709 | else | |
9710 | emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); | |
9711 | } | |
9712 | else | |
9713 | { | |
9714 | if (TARGET_64BIT) | |
9715 | emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); | |
9716 | else | |
9717 | emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); | |
9718 | } | |
9719 | DONE; | |
9720 | } | |
9721 | ||
9722 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9723 | { | |
9724 | operands[0] = force_reg (Pmode, operands[0]); | |
9725 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9726 | if (TARGET_CPU_Z10) | |
9727 | { | |
9728 | if (TARGET_64BIT) | |
9729 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], | |
9730 | label_ref)); | |
9731 | else | |
9732 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], | |
9733 | label_ref)); | |
9734 | } | |
9735 | else | |
9736 | { | |
9737 | if (TARGET_64BIT) | |
9738 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], | |
9739 | label_ref, | |
9740 | force_reg (Pmode, label_ref))); | |
9741 | else | |
9742 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], | |
9743 | label_ref, | |
9744 | force_reg (Pmode, label_ref))); | |
9745 | } | |
9746 | DONE; | |
9747 | } | |
2841f550 AK |
9748 | }) |
9749 | ||
9750 | (define_insn "*indirect_jump" | |
9751 | [(set (pc) | |
84b4c7b5 AK |
9752 | (match_operand 0 "address_operand" "ZR"))] |
9753 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9754 | { | |
9755 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9756 | return "br\t%0"; | |
9757 | else | |
9758 | return "b\t%a0"; | |
9759 | } | |
9760 | [(set (attr "op_type") | |
9761 | (if_then_else (match_operand 0 "register_operand" "") | |
9762 | (const_string "RR") (const_string "RX"))) | |
9763 | (set (attr "mnemonic") | |
9764 | (if_then_else (match_operand 0 "register_operand" "") | |
9765 | (const_string "br") (const_string "b"))) | |
2841f550 | 9766 | (set_attr "type" "branch") |
84b4c7b5 AK |
9767 | (set_attr "atype" "agen")]) |
9768 | ||
9769 | (define_insn "indirect_jump_via_thunk<mode>_z10" | |
9770 | [(set (pc) | |
9771 | (match_operand:P 0 "register_operand" "a"))] | |
9772 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9773 | && TARGET_CPU_Z10" | |
9774 | { | |
9775 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9776 | INVALID_REGNUM, | |
9777 | NULL_RTX, | |
9778 | s390_indirect_branch_type_jump); | |
9779 | return ""; | |
9780 | } | |
9781 | [(set_attr "op_type" "RIL") | |
9782 | (set_attr "mnemonic" "jg") | |
9783 | (set_attr "type" "branch") | |
9784 | (set_attr "atype" "agen")]) | |
9785 | ||
9786 | (define_insn "indirect_jump_via_thunk<mode>" | |
9787 | [(set (pc) | |
9788 | (match_operand:P 0 "register_operand" " a")) | |
9789 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9790 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9791 | && !TARGET_CPU_Z10" | |
9792 | { | |
9793 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9794 | INVALID_REGNUM, | |
9795 | NULL_RTX, | |
9796 | s390_indirect_branch_type_jump); | |
9797 | return ""; | |
9798 | } | |
9799 | [(set_attr "op_type" "RIL") | |
9800 | (set_attr "mnemonic" "jg") | |
9801 | (set_attr "type" "branch") | |
9802 | (set_attr "atype" "agen")]) | |
9803 | ||
9804 | ||
9805 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9806 | ; from mark_jump_label. Without this the label_ref would become the | |
9807 | ; ONLY jump target of that jump breaking the control flow graph. | |
9808 | (define_insn "indirect_jump_via_inlinethunk<mode>_z10" | |
9809 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9810 | (const_int 0) | |
9811 | (const_int 0)) | |
9812 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9813 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9814 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9815 | && TARGET_CPU_Z10" | |
9816 | { | |
9817 | s390_indirect_branch_via_inline_thunk (operands[1]); | |
9818 | return ""; | |
9819 | } | |
9820 | [(set_attr "op_type" "RIL") | |
9821 | (set_attr "type" "branch") | |
9822 | (set_attr "length" "10")]) | |
9823 | ||
9824 | (define_insn "indirect_jump_via_inlinethunk<mode>" | |
9825 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9826 | (const_int 0) | |
9827 | (const_int 0)) | |
9828 | (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9829 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9830 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9831 | && !TARGET_CPU_Z10" | |
9832 | { | |
9833 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9834 | return ""; | |
9835 | } | |
9836 | [(set_attr "op_type" "RX") | |
9837 | (set_attr "type" "branch") | |
9838 | (set_attr "length" "8")]) | |
2841f550 AK |
9839 | |
9840 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9841 | ; checked against address constraints like ZR above. So make this a | |
9842 | ; separate pattern for now. | |
9843 | (define_insn "*indirect2_jump" | |
9844 | [(set (pc) | |
9845 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
84b4c7b5 | 9846 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
2841f550 AK |
9847 | "@ |
9848 | br\t%0 | |
9849 | bi\t%0" | |
9850 | [(set_attr "op_type" "RR,RXY") | |
9851 | (set_attr "type" "branch") | |
9852 | (set_attr "atype" "agen") | |
9853 | (set_attr "cpu_facility" "*,arch12")]) | |
9db1d521 HP |
9854 | |
9855 | ; | |
f314b9b1 | 9856 | ; casesi instruction pattern(s). |
9db1d521 HP |
9857 | ; |
9858 | ||
84b4c7b5 AK |
9859 | (define_expand "casesi_jump" |
9860 | [(parallel | |
9861 | [(set (pc) (match_operand 0 "address_operand")) | |
9862 | (use (label_ref (match_operand 1 "")))])] | |
9db1d521 | 9863 | "" |
84b4c7b5 AK |
9864 | { |
9865 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9866 | { | |
9867 | operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); | |
9868 | ||
9869 | if (TARGET_CPU_Z10) | |
9870 | { | |
9871 | if (TARGET_64BIT) | |
9872 | emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], | |
9873 | operands[1])); | |
9874 | else | |
9875 | emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], | |
9876 | operands[1])); | |
9877 | } | |
9878 | else | |
9879 | { | |
9880 | if (TARGET_64BIT) | |
9881 | emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], | |
9882 | operands[1])); | |
9883 | else | |
9884 | emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], | |
9885 | operands[1])); | |
9886 | } | |
9887 | DONE; | |
9888 | } | |
9889 | ||
9890 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9891 | { | |
9892 | operands[0] = force_reg (Pmode, operands[0]); | |
9893 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9894 | if (TARGET_CPU_Z10) | |
9895 | { | |
9896 | if (TARGET_64BIT) | |
9897 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], | |
9898 | operands[1], | |
9899 | label_ref)); | |
9900 | else | |
9901 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], | |
9902 | operands[1], | |
9903 | label_ref)); | |
9904 | } | |
9905 | else | |
9906 | { | |
9907 | if (TARGET_64BIT) | |
9908 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], | |
9909 | operands[1], | |
9910 | label_ref, | |
9911 | force_reg (Pmode, label_ref))); | |
9912 | else | |
9913 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], | |
9914 | operands[1], | |
9915 | label_ref, | |
9916 | force_reg (Pmode, label_ref))); | |
9917 | } | |
9918 | DONE; | |
9919 | } | |
9920 | }) | |
9921 | ||
9922 | (define_insn "*casesi_jump" | |
9923 | [(set (pc) (match_operand 0 "address_operand" "ZR")) | |
9924 | (use (label_ref (match_operand 1 "" "")))] | |
9925 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9db1d521 | 9926 | { |
f314b9b1 | 9927 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9928 | return "br\t%0"; |
f314b9b1 | 9929 | else |
d40c829f | 9930 | return "b\t%a0"; |
10bbf137 | 9931 | } |
c7453384 | 9932 | [(set (attr "op_type") |
f314b9b1 UW |
9933 | (if_then_else (match_operand 0 "register_operand" "") |
9934 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9935 | (set (attr "mnemonic") |
9936 | (if_then_else (match_operand 0 "register_operand" "") | |
9937 | (const_string "br") (const_string "b"))) | |
9938 | (set_attr "type" "branch") | |
9939 | (set_attr "atype" "agen")]) | |
9940 | ||
9941 | (define_insn "casesi_jump_via_thunk<mode>_z10" | |
9942 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9943 | (use (label_ref (match_operand 1 "" "")))] | |
9944 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9945 | && TARGET_CPU_Z10" | |
9946 | { | |
9947 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9948 | INVALID_REGNUM, | |
9949 | NULL_RTX, | |
9950 | s390_indirect_branch_type_jump); | |
9951 | return ""; | |
9952 | } | |
9953 | [(set_attr "op_type" "RIL") | |
9954 | (set_attr "mnemonic" "jg") | |
9955 | (set_attr "type" "branch") | |
9956 | (set_attr "atype" "agen")]) | |
9957 | ||
9958 | (define_insn "casesi_jump_via_thunk<mode>" | |
9959 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9960 | (use (label_ref (match_operand 1 "" ""))) | |
9961 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9962 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9963 | && !TARGET_CPU_Z10" | |
9964 | { | |
9965 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9966 | INVALID_REGNUM, | |
9967 | NULL_RTX, | |
9968 | s390_indirect_branch_type_jump); | |
9969 | return ""; | |
9970 | } | |
9971 | [(set_attr "op_type" "RIL") | |
9972 | (set_attr "mnemonic" "jg") | |
077dab3b HP |
9973 | (set_attr "type" "branch") |
9974 | (set_attr "atype" "agen")]) | |
9db1d521 | 9975 | |
84b4c7b5 AK |
9976 | |
9977 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9978 | ; from mark_jump_label. Without this the label_ref would become the | |
9979 | ; ONLY jump target of that jump breaking the control flow graph. | |
9980 | (define_insn "casesi_jump_via_inlinethunk<mode>_z10" | |
9981 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9982 | (const_int 0) | |
9983 | (const_int 0)) | |
9984 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9985 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9986 | (use (label_ref (match_operand 1 "" "")))] | |
9987 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9988 | && TARGET_CPU_Z10" | |
9989 | { | |
9990 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9991 | return ""; | |
9992 | } | |
9993 | [(set_attr "op_type" "RIL") | |
9994 | (set_attr "type" "cs") | |
9995 | (set_attr "length" "10")]) | |
9996 | ||
9997 | (define_insn "casesi_jump_via_inlinethunk<mode>" | |
9998 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9999 | (const_int 0) | |
10000 | (const_int 0)) | |
10001 | (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
10002 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
10003 | (use (label_ref (match_operand 1 "" "")))] | |
10004 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
10005 | && !TARGET_CPU_Z10" | |
10006 | { | |
10007 | s390_indirect_branch_via_inline_thunk (operands[3]); | |
10008 | return ""; | |
10009 | } | |
10010 | [(set_attr "op_type" "RX") | |
10011 | (set_attr "type" "cs") | |
10012 | (set_attr "length" "8")]) | |
10013 | ||
f314b9b1 UW |
10014 | (define_expand "casesi" |
10015 | [(match_operand:SI 0 "general_operand" "") | |
10016 | (match_operand:SI 1 "general_operand" "") | |
10017 | (match_operand:SI 2 "general_operand" "") | |
10018 | (label_ref (match_operand 3 "" "")) | |
10019 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 10020 | "" |
f314b9b1 UW |
10021 | { |
10022 | rtx index = gen_reg_rtx (SImode); | |
10023 | rtx base = gen_reg_rtx (Pmode); | |
10024 | rtx target = gen_reg_rtx (Pmode); | |
10025 | ||
10026 | emit_move_insn (index, operands[0]); | |
10027 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
10028 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 10029 | operands[4]); |
f314b9b1 UW |
10030 | |
10031 | if (Pmode != SImode) | |
10032 | index = convert_to_mode (Pmode, index, 1); | |
10033 | if (GET_CODE (index) != REG) | |
10034 | index = copy_to_mode_reg (Pmode, index); | |
10035 | ||
10036 | if (TARGET_64BIT) | |
10037 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
10038 | else | |
a556fd39 | 10039 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 10040 | |
f314b9b1 UW |
10041 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
10042 | ||
542a8afa | 10043 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
10044 | emit_move_insn (target, index); |
10045 | ||
10046 | if (flag_pic) | |
10047 | target = gen_rtx_PLUS (Pmode, base, target); | |
10048 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
10049 | ||
10050 | DONE; | |
10bbf137 | 10051 | }) |
9db1d521 HP |
10052 | |
10053 | ||
10054 | ;; | |
10055 | ;;- Jump to subroutine. | |
10056 | ;; | |
10057 | ;; | |
10058 | ||
10059 | ; | |
10060 | ; untyped call instruction pattern(s). | |
10061 | ; | |
10062 | ||
10063 | ;; Call subroutine returning any type. | |
10064 | (define_expand "untyped_call" | |
10065 | [(parallel [(call (match_operand 0 "" "") | |
10066 | (const_int 0)) | |
10067 | (match_operand 1 "" "") | |
10068 | (match_operand 2 "" "")])] | |
10069 | "" | |
9db1d521 HP |
10070 | { |
10071 | int i; | |
10072 | ||
10073 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
10074 | ||
10075 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10076 | { | |
10077 | rtx set = XVECEXP (operands[2], 0, i); | |
10078 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10079 | } | |
10080 | ||
10081 | /* The optimizer does not know that the call sets the function value | |
10082 | registers we stored in the result block. We avoid problems by | |
10083 | claiming that all hard registers are used and clobbered at this | |
10084 | point. */ | |
10085 | emit_insn (gen_blockage ()); | |
10086 | ||
10087 | DONE; | |
10bbf137 | 10088 | }) |
9db1d521 HP |
10089 | |
10090 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
10091 | ;; all of memory. This blocks insns from being moved across this point. | |
10092 | ||
10093 | (define_insn "blockage" | |
10bbf137 | 10094 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 10095 | "" |
4023fb28 | 10096 | "" |
d5869ca0 UW |
10097 | [(set_attr "type" "none") |
10098 | (set_attr "length" "0")]) | |
4023fb28 | 10099 | |
9db1d521 | 10100 | ; |
ed9676cf | 10101 | ; sibcall patterns |
9db1d521 HP |
10102 | ; |
10103 | ||
ed9676cf | 10104 | (define_expand "sibcall" |
44b8152b | 10105 | [(call (match_operand 0 "" "") |
ed9676cf | 10106 | (match_operand 1 "" ""))] |
9db1d521 | 10107 | "" |
9db1d521 | 10108 | { |
ed9676cf AK |
10109 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
10110 | DONE; | |
10111 | }) | |
9db1d521 | 10112 | |
ed9676cf | 10113 | (define_insn "*sibcall_br" |
ae156f85 | 10114 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 10115 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 10116 | "SIBLING_CALL_P (insn) |
ed9676cf | 10117 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
84b4c7b5 AK |
10118 | { |
10119 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
10120 | { | |
10121 | gcc_assert (TARGET_CPU_Z10); | |
10122 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
10123 | INVALID_REGNUM, | |
10124 | NULL_RTX, | |
10125 | s390_indirect_branch_type_call); | |
10126 | return ""; | |
10127 | } | |
10128 | else | |
10129 | return "br\t%%r1"; | |
10130 | } | |
10131 | [(set (attr "op_type") | |
10132 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10133 | (const_string "RIL") | |
10134 | (const_string "RR"))) | |
10135 | (set (attr "mnemonic") | |
10136 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10137 | (const_string "jg") | |
10138 | (const_string "br"))) | |
ed9676cf AK |
10139 | (set_attr "type" "branch") |
10140 | (set_attr "atype" "agen")]) | |
9db1d521 | 10141 | |
ed9676cf AK |
10142 | (define_insn "*sibcall_brc" |
10143 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10144 | (match_operand 1 "const_int_operand" "n"))] | |
10145 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
10146 | "j\t%0" | |
10147 | [(set_attr "op_type" "RI") | |
10148 | (set_attr "type" "branch")]) | |
9db1d521 | 10149 | |
ed9676cf AK |
10150 | (define_insn "*sibcall_brcl" |
10151 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10152 | (match_operand 1 "const_int_operand" "n"))] | |
10153 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
10154 | "jg\t%0" | |
10155 | [(set_attr "op_type" "RIL") | |
10156 | (set_attr "type" "branch")]) | |
44b8152b | 10157 | |
ed9676cf AK |
10158 | ; |
10159 | ; sibcall_value patterns | |
10160 | ; | |
9e8327e3 | 10161 | |
ed9676cf AK |
10162 | (define_expand "sibcall_value" |
10163 | [(set (match_operand 0 "" "") | |
10164 | (call (match_operand 1 "" "") | |
10165 | (match_operand 2 "" "")))] | |
10166 | "" | |
10167 | { | |
10168 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 10169 | DONE; |
10bbf137 | 10170 | }) |
9db1d521 | 10171 | |
ed9676cf AK |
10172 | (define_insn "*sibcall_value_br" |
10173 | [(set (match_operand 0 "" "") | |
ae156f85 | 10174 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 10175 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 10176 | "SIBLING_CALL_P (insn) |
ed9676cf | 10177 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
84b4c7b5 AK |
10178 | { |
10179 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
10180 | { | |
10181 | gcc_assert (TARGET_CPU_Z10); | |
10182 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
10183 | INVALID_REGNUM, | |
10184 | NULL_RTX, | |
10185 | s390_indirect_branch_type_call); | |
10186 | return ""; | |
10187 | } | |
10188 | else | |
10189 | return "br\t%%r1"; | |
10190 | } | |
10191 | [(set (attr "op_type") | |
10192 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10193 | (const_string "RIL") | |
10194 | (const_string "RR"))) | |
10195 | (set (attr "mnemonic") | |
10196 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10197 | (const_string "jg") | |
10198 | (const_string "br"))) | |
ed9676cf AK |
10199 | (set_attr "type" "branch") |
10200 | (set_attr "atype" "agen")]) | |
10201 | ||
10202 | (define_insn "*sibcall_value_brc" | |
10203 | [(set (match_operand 0 "" "") | |
10204 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
10205 | (match_operand 2 "const_int_operand" "n")))] | |
10206 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
10207 | "j\t%1" | |
10208 | [(set_attr "op_type" "RI") | |
10209 | (set_attr "type" "branch")]) | |
10210 | ||
10211 | (define_insn "*sibcall_value_brcl" | |
10212 | [(set (match_operand 0 "" "") | |
10213 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
10214 | (match_operand 2 "const_int_operand" "n")))] | |
10215 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
10216 | "jg\t%1" | |
10217 | [(set_attr "op_type" "RIL") | |
10218 | (set_attr "type" "branch")]) | |
10219 | ||
10220 | ||
10221 | ; | |
10222 | ; call instruction pattern(s). | |
10223 | ; | |
10224 | ||
10225 | (define_expand "call" | |
10226 | [(call (match_operand 0 "" "") | |
10227 | (match_operand 1 "" "")) | |
10228 | (use (match_operand 2 "" ""))] | |
44b8152b | 10229 | "" |
ed9676cf | 10230 | { |
2f7e5a0d | 10231 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
10232 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
10233 | DONE; | |
10234 | }) | |
44b8152b | 10235 | |
9e8327e3 UW |
10236 | (define_insn "*bras" |
10237 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10238 | (match_operand 1 "const_int_operand" "n")) | |
10239 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
10240 | "!SIBLING_CALL_P (insn) |
10241 | && TARGET_SMALL_EXEC | |
ed9676cf | 10242 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 10243 | "bras\t%2,%0" |
9db1d521 | 10244 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10245 | (set_attr "type" "jsr") |
10246 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10247 | |
9e8327e3 UW |
10248 | (define_insn "*brasl" |
10249 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10250 | (match_operand 1 "const_int_operand" "n")) | |
10251 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
10252 | "!SIBLING_CALL_P (insn) |
10253 | && TARGET_CPU_ZARCH | |
ed9676cf | 10254 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
10255 | "brasl\t%2,%0" |
10256 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
10257 | (set_attr "type" "jsr") |
10258 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10259 | |
9e8327e3 | 10260 | (define_insn "*basr" |
3e4be43f | 10261 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
10262 | (match_operand 1 "const_int_operand" "n")) |
10263 | (clobber (match_operand 2 "register_operand" "=r"))] | |
84b4c7b5 AK |
10264 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10265 | && !SIBLING_CALL_P (insn) | |
10266 | && GET_MODE (operands[2]) == Pmode" | |
9e8327e3 UW |
10267 | { |
10268 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10269 | return "basr\t%2,%0"; | |
10270 | else | |
10271 | return "bas\t%2,%a0"; | |
10272 | } | |
10273 | [(set (attr "op_type") | |
10274 | (if_then_else (match_operand 0 "register_operand" "") | |
10275 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10276 | (set (attr "mnemonic") |
10277 | (if_then_else (match_operand 0 "register_operand" "") | |
10278 | (const_string "basr") (const_string "bas"))) | |
10279 | (set_attr "type" "jsr") | |
10280 | (set_attr "atype" "agen") | |
10281 | (set_attr "z196prop" "z196_cracked")]) | |
10282 | ||
10283 | (define_insn "*basr_via_thunk<mode>_z10" | |
10284 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10285 | (match_operand 1 "const_int_operand" "n")) | |
10286 | (clobber (match_operand:P 2 "register_operand" "=&r"))] | |
10287 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10288 | && TARGET_CPU_Z10 | |
10289 | && !SIBLING_CALL_P (insn)" | |
10290 | { | |
10291 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10292 | REGNO (operands[2]), | |
10293 | NULL_RTX, | |
10294 | s390_indirect_branch_type_call); | |
10295 | return ""; | |
10296 | } | |
10297 | [(set_attr "op_type" "RIL") | |
10298 | (set_attr "mnemonic" "brasl") | |
10299 | (set_attr "type" "jsr") | |
10300 | (set_attr "atype" "agen") | |
10301 | (set_attr "z196prop" "z196_cracked")]) | |
10302 | ||
10303 | (define_insn "*basr_via_thunk<mode>" | |
10304 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10305 | (match_operand 1 "const_int_operand" "n")) | |
10306 | (clobber (match_operand:P 2 "register_operand" "=&r")) | |
10307 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10308 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10309 | && !TARGET_CPU_Z10 | |
10310 | && !SIBLING_CALL_P (insn)" | |
10311 | { | |
10312 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10313 | REGNO (operands[2]), | |
10314 | NULL_RTX, | |
10315 | s390_indirect_branch_type_call); | |
10316 | return ""; | |
10317 | } | |
10318 | [(set_attr "op_type" "RIL") | |
10319 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10320 | (set_attr "type" "jsr") |
65b1d8ea AK |
10321 | (set_attr "atype" "agen") |
10322 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
10323 | |
10324 | ; | |
10325 | ; call_value instruction pattern(s). | |
10326 | ; | |
10327 | ||
10328 | (define_expand "call_value" | |
44b8152b UW |
10329 | [(set (match_operand 0 "" "") |
10330 | (call (match_operand 1 "" "") | |
10331 | (match_operand 2 "" ""))) | |
10332 | (use (match_operand 3 "" ""))] | |
9db1d521 | 10333 | "" |
9db1d521 | 10334 | { |
2f7e5a0d | 10335 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 10336 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 10337 | DONE; |
10bbf137 | 10338 | }) |
9db1d521 | 10339 | |
9e8327e3 | 10340 | (define_insn "*bras_r" |
c19ec8f9 | 10341 | [(set (match_operand 0 "" "") |
9e8327e3 | 10342 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 10343 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 10344 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
10345 | "!SIBLING_CALL_P (insn) |
10346 | && TARGET_SMALL_EXEC | |
ed9676cf | 10347 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10348 | "bras\t%3,%1" |
9db1d521 | 10349 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10350 | (set_attr "type" "jsr") |
10351 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10352 | |
9e8327e3 | 10353 | (define_insn "*brasl_r" |
c19ec8f9 | 10354 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10355 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10356 | (match_operand 2 "const_int_operand" "n"))) | |
10357 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
10358 | "!SIBLING_CALL_P (insn) |
10359 | && TARGET_CPU_ZARCH | |
ed9676cf | 10360 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10361 | "brasl\t%3,%1" |
10362 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
10363 | (set_attr "type" "jsr") |
10364 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10365 | |
9e8327e3 | 10366 | (define_insn "*basr_r" |
c19ec8f9 | 10367 | [(set (match_operand 0 "" "") |
3e4be43f | 10368 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10369 | (match_operand 2 "const_int_operand" "n"))) |
10370 | (clobber (match_operand 3 "register_operand" "=r"))] | |
84b4c7b5 AK |
10371 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10372 | && !SIBLING_CALL_P (insn) | |
10373 | && GET_MODE (operands[3]) == Pmode" | |
9e8327e3 UW |
10374 | { |
10375 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10376 | return "basr\t%3,%1"; | |
10377 | else | |
10378 | return "bas\t%3,%a1"; | |
10379 | } | |
10380 | [(set (attr "op_type") | |
10381 | (if_then_else (match_operand 1 "register_operand" "") | |
10382 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10383 | (set (attr "mnemonic") |
10384 | (if_then_else (match_operand 1 "register_operand" "") | |
10385 | (const_string "basr") (const_string "bas"))) | |
10386 | (set_attr "type" "jsr") | |
10387 | (set_attr "atype" "agen") | |
10388 | (set_attr "z196prop" "z196_cracked")]) | |
10389 | ||
10390 | (define_insn "*basr_r_via_thunk_z10" | |
10391 | [(set (match_operand 0 "" "") | |
10392 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10393 | (match_operand 2 "const_int_operand" "n"))) | |
10394 | (clobber (match_operand 3 "register_operand" "=&r"))] | |
10395 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10396 | && TARGET_CPU_Z10 | |
10397 | && !SIBLING_CALL_P (insn) | |
10398 | && GET_MODE (operands[3]) == Pmode" | |
10399 | { | |
10400 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10401 | REGNO (operands[3]), | |
10402 | NULL_RTX, | |
10403 | s390_indirect_branch_type_call); | |
10404 | return ""; | |
10405 | } | |
10406 | [(set_attr "op_type" "RIL") | |
10407 | (set_attr "mnemonic" "brasl") | |
10408 | (set_attr "type" "jsr") | |
10409 | (set_attr "atype" "agen") | |
10410 | (set_attr "z196prop" "z196_cracked")]) | |
10411 | ||
10412 | (define_insn "*basr_r_via_thunk" | |
10413 | [(set (match_operand 0 "" "") | |
10414 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10415 | (match_operand 2 "const_int_operand" "n"))) | |
10416 | (clobber (match_operand 3 "register_operand" "=&r")) | |
10417 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10418 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10419 | && !TARGET_CPU_Z10 | |
10420 | && !SIBLING_CALL_P (insn) | |
10421 | && GET_MODE (operands[3]) == Pmode" | |
10422 | { | |
10423 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10424 | REGNO (operands[3]), | |
10425 | NULL_RTX, | |
10426 | s390_indirect_branch_type_call); | |
10427 | return ""; | |
10428 | } | |
10429 | [(set_attr "op_type" "RIL") | |
10430 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10431 | (set_attr "type" "jsr") |
65b1d8ea AK |
10432 | (set_attr "atype" "agen") |
10433 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10434 | |
fd3cd001 UW |
10435 | ;; |
10436 | ;;- Thread-local storage support. | |
10437 | ;; | |
10438 | ||
f959607b CLT |
10439 | (define_expand "get_thread_pointer<mode>" |
10440 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
10441 | "" | |
c5aa1d12 | 10442 | "") |
fd3cd001 | 10443 | |
f959607b CLT |
10444 | (define_expand "set_thread_pointer<mode>" |
10445 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
10446 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
10447 | "" | |
c5aa1d12 UW |
10448 | "") |
10449 | ||
10450 | (define_insn "*set_tp" | |
ae156f85 | 10451 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
10452 | "" |
10453 | "" | |
10454 | [(set_attr "type" "none") | |
10455 | (set_attr "length" "0")]) | |
c7453384 | 10456 | |
fd3cd001 UW |
10457 | (define_insn "*tls_load_64" |
10458 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 10459 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
10460 | (match_operand:DI 2 "" "")] |
10461 | UNSPEC_TLS_LOAD))] | |
10462 | "TARGET_64BIT" | |
d40c829f | 10463 | "lg\t%0,%1%J2" |
9381e3f1 WG |
10464 | [(set_attr "op_type" "RXE") |
10465 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
10466 | |
10467 | (define_insn "*tls_load_31" | |
d3632d41 UW |
10468 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10469 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
10470 | (match_operand:SI 2 "" "")] |
10471 | UNSPEC_TLS_LOAD))] | |
10472 | "!TARGET_64BIT" | |
d3632d41 | 10473 | "@ |
d40c829f UW |
10474 | l\t%0,%1%J2 |
10475 | ly\t%0,%1%J2" | |
9381e3f1 | 10476 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 10477 | (set_attr "type" "load") |
3e4be43f | 10478 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 10479 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 10480 | |
9e8327e3 | 10481 | (define_insn "*bras_tls" |
c19ec8f9 | 10482 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10483 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10484 | (match_operand 2 "const_int_operand" "n"))) | |
10485 | (clobber (match_operand 3 "register_operand" "=r")) | |
10486 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10487 | "!SIBLING_CALL_P (insn) |
10488 | && TARGET_SMALL_EXEC | |
ed9676cf | 10489 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10490 | "bras\t%3,%1%J4" |
fd3cd001 | 10491 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10492 | (set_attr "type" "jsr") |
10493 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10494 | |
9e8327e3 | 10495 | (define_insn "*brasl_tls" |
c19ec8f9 | 10496 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10497 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10498 | (match_operand 2 "const_int_operand" "n"))) | |
10499 | (clobber (match_operand 3 "register_operand" "=r")) | |
10500 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10501 | "!SIBLING_CALL_P (insn) |
10502 | && TARGET_CPU_ZARCH | |
ed9676cf | 10503 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10504 | "brasl\t%3,%1%J4" |
10505 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
10506 | (set_attr "type" "jsr") |
10507 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10508 | |
9e8327e3 | 10509 | (define_insn "*basr_tls" |
c19ec8f9 | 10510 | [(set (match_operand 0 "" "") |
3e4be43f | 10511 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10512 | (match_operand 2 "const_int_operand" "n"))) |
10513 | (clobber (match_operand 3 "register_operand" "=r")) | |
10514 | (use (match_operand 4 "" ""))] | |
ed9676cf | 10515 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10516 | { |
10517 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10518 | return "basr\t%3,%1%J4"; | |
10519 | else | |
10520 | return "bas\t%3,%a1%J4"; | |
10521 | } | |
10522 | [(set (attr "op_type") | |
10523 | (if_then_else (match_operand 1 "register_operand" "") | |
10524 | (const_string "RR") (const_string "RX"))) | |
10525 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10526 | (set_attr "atype" "agen") |
10527 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10528 | |
e0374221 AS |
10529 | ;; |
10530 | ;;- Atomic operations | |
10531 | ;; | |
10532 | ||
10533 | ; | |
78ce265b | 10534 | ; memory barrier patterns. |
e0374221 AS |
10535 | ; |
10536 | ||
78ce265b RH |
10537 | (define_expand "mem_thread_fence" |
10538 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
10539 | "" | |
10540 | { | |
10541 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
10542 | enough not to require barriers of any kind. */ | |
46b35980 | 10543 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
10544 | { |
10545 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
10546 | MEM_VOLATILE_P (mem) = 1; | |
10547 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
10548 | } | |
10549 | DONE; | |
e0374221 AS |
10550 | }) |
10551 | ||
78ce265b RH |
10552 | ; Although bcr is superscalar on Z10, this variant will never |
10553 | ; become part of an execution group. | |
a9cc3f58 AK |
10554 | ; With z196 we can make use of the fast-BCR-serialization facility. |
10555 | ; This allows for a slightly faster sync which is sufficient for our | |
10556 | ; purposes. | |
78ce265b | 10557 | (define_insn "mem_thread_fence_1" |
e0374221 | 10558 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 10559 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 10560 | "" |
a9cc3f58 AK |
10561 | { |
10562 | if (TARGET_Z196) | |
10563 | return "bcr\t14,0"; | |
10564 | else | |
10565 | return "bcr\t15,0"; | |
10566 | } | |
10567 | [(set_attr "op_type" "RR") | |
10568 | (set_attr "mnemonic" "bcr_flush") | |
10569 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10570 | |
78ce265b RH |
10571 | ; |
10572 | ; atomic load/store operations | |
10573 | ; | |
10574 | ||
10575 | ; Atomic loads need not examine the memory model at all. | |
10576 | (define_expand "atomic_load<mode>" | |
10577 | [(match_operand:DINT 0 "register_operand") ;; output | |
10578 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10579 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10580 | "" | |
10581 | { | |
75cc21e2 AK |
10582 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10583 | FAIL; | |
10584 | ||
78ce265b RH |
10585 | if (<MODE>mode == TImode) |
10586 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10587 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10588 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10589 | else | |
10590 | emit_move_insn (operands[0], operands[1]); | |
10591 | DONE; | |
10592 | }) | |
10593 | ||
10594 | ; Different from movdi_31 in that we want no splitters. | |
10595 | (define_insn "atomic_loaddi_1" | |
10596 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10597 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10598 | UNSPEC_MOVA))] | |
10599 | "!TARGET_ZARCH" | |
10600 | "@ | |
10601 | lm\t%0,%M0,%S1 | |
10602 | lmy\t%0,%M0,%S1 | |
10603 | ld\t%0,%1 | |
10604 | ldy\t%0,%1" | |
10605 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10606 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10607 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10608 | ||
10609 | (define_insn "atomic_loadti_1" | |
10610 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10611 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10612 | UNSPEC_MOVA))] |
10613 | "TARGET_ZARCH" | |
10614 | "lpq\t%0,%1" | |
10615 | [(set_attr "op_type" "RXY") | |
10616 | (set_attr "type" "other")]) | |
10617 | ||
10618 | ; Atomic stores must(?) enforce sequential consistency. | |
10619 | (define_expand "atomic_store<mode>" | |
10620 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10621 | (match_operand:DINT 1 "register_operand") ;; input | |
10622 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10623 | "" | |
10624 | { | |
46b35980 | 10625 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10626 | |
75cc21e2 AK |
10627 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10628 | FAIL; | |
10629 | ||
78ce265b RH |
10630 | if (<MODE>mode == TImode) |
10631 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10632 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10633 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10634 | else | |
10635 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10636 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10637 | emit_insn (gen_mem_thread_fence (operands[2])); |
10638 | DONE; | |
10639 | }) | |
10640 | ||
10641 | ; Different from movdi_31 in that we want no splitters. | |
10642 | (define_insn "atomic_storedi_1" | |
10643 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10644 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10645 | UNSPEC_MOVA))] | |
10646 | "!TARGET_ZARCH" | |
10647 | "@ | |
10648 | stm\t%1,%N1,%S0 | |
10649 | stmy\t%1,%N1,%S0 | |
10650 | std %1,%0 | |
10651 | stdy %1,%0" | |
10652 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10653 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10654 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10655 | ||
10656 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10657 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10658 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10659 | UNSPEC_MOVA))] | |
10660 | "TARGET_ZARCH" | |
10661 | "stpq\t%1,%0" | |
10662 | [(set_attr "op_type" "RXY") | |
10663 | (set_attr "type" "other")]) | |
e0374221 AS |
10664 | |
10665 | ; | |
10666 | ; compare and swap patterns. | |
10667 | ; | |
10668 | ||
78ce265b RH |
10669 | (define_expand "atomic_compare_and_swap<mode>" |
10670 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
03db9ab5 DV |
10671 | (match_operand:DINT 1 "nonimmediate_operand");; oldval output |
10672 | (match_operand:DINT 2 "s_operand") ;; memory | |
10673 | (match_operand:DINT 3 "general_operand") ;; expected intput | |
10674 | (match_operand:DINT 4 "general_operand") ;; newval intput | |
78ce265b RH |
10675 | (match_operand:SI 5 "const_int_operand") ;; is_weak |
10676 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10677 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10678 | "" | |
10679 | { | |
03db9ab5 DV |
10680 | if (GET_MODE_BITSIZE (<MODE>mode) >= 16 |
10681 | && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) | |
75cc21e2 AK |
10682 | FAIL; |
10683 | ||
03db9ab5 DV |
10684 | s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], |
10685 | operands[3], operands[4], INTVAL (operands[5])); | |
10686 | DONE;}) | |
3093f076 | 10687 | |
78ce265b RH |
10688 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10689 | [(parallel | |
10690 | [(set (match_operand:DGPR 0 "register_operand") | |
03db9ab5 | 10691 | (match_operand:DGPR 1 "s_operand")) |
78ce265b RH |
10692 | (set (match_dup 1) |
10693 | (unspec_volatile:DGPR | |
10694 | [(match_dup 1) | |
10695 | (match_operand:DGPR 2 "register_operand") | |
10696 | (match_operand:DGPR 3 "register_operand")] | |
10697 | UNSPECV_CAS)) | |
03db9ab5 DV |
10698 | (set (match_operand 4 "cc_reg_operand") |
10699 | (match_dup 5))])] | |
10700 | "GET_MODE (operands[4]) == CCZmode | |
10701 | || GET_MODE (operands[4]) == CCZ1mode" | |
10702 | { | |
10703 | operands[5] | |
10704 | = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); | |
10705 | }) | |
78ce265b RH |
10706 | |
10707 | ; cdsg, csg | |
10708 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10709 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
58814c76 | 10710 | (match_operand:TDI 1 "memory_operand" "+S")) |
8006eaa6 | 10711 | (set (match_dup 1) |
78ce265b | 10712 | (unspec_volatile:TDI |
8006eaa6 | 10713 | [(match_dup 1) |
78ce265b RH |
10714 | (match_operand:TDI 2 "register_operand" "0") |
10715 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 | 10716 | UNSPECV_CAS)) |
03db9ab5 DV |
10717 | (set (reg CC_REGNUM) |
10718 | (compare (match_dup 1) (match_dup 2)))] | |
10719 | "TARGET_ZARCH | |
10720 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10721 | "c<td>sg\t%0,%3,%S1" |
10722 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10723 | (set_attr "type" "sem")]) |
10724 | ||
78ce265b RH |
10725 | ; cds, cdsy |
10726 | (define_insn "*atomic_compare_and_swapdi_2" | |
10727 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
58814c76 | 10728 | (match_operand:DI 1 "memory_operand" "+Q,S")) |
e0374221 | 10729 | (set (match_dup 1) |
78ce265b RH |
10730 | (unspec_volatile:DI |
10731 | [(match_dup 1) | |
10732 | (match_operand:DI 2 "register_operand" "0,0") | |
10733 | (match_operand:DI 3 "register_operand" "r,r")] | |
10734 | UNSPECV_CAS)) | |
03db9ab5 DV |
10735 | (set (reg CC_REGNUM) |
10736 | (compare (match_dup 1) (match_dup 2)))] | |
10737 | "!TARGET_ZARCH | |
10738 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10739 | "@ |
10740 | cds\t%0,%3,%S1 | |
10741 | cdsy\t%0,%3,%S1" | |
10742 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10743 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10744 | (set_attr "type" "sem")]) |
10745 | ||
10746 | ; cs, csy | |
10747 | (define_insn "*atomic_compare_and_swapsi_3" | |
10748 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
58814c76 | 10749 | (match_operand:SI 1 "memory_operand" "+Q,S")) |
78ce265b RH |
10750 | (set (match_dup 1) |
10751 | (unspec_volatile:SI | |
e0374221 | 10752 | [(match_dup 1) |
78ce265b RH |
10753 | (match_operand:SI 2 "register_operand" "0,0") |
10754 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10755 | UNSPECV_CAS)) |
03db9ab5 DV |
10756 | (set (reg CC_REGNUM) |
10757 | (compare (match_dup 1) (match_dup 2)))] | |
10758 | "s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10759 | "@ |
10760 | cs\t%0,%3,%S1 | |
10761 | csy\t%0,%3,%S1" | |
10762 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10763 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10764 | (set_attr "type" "sem")]) |
10765 | ||
45d18331 AS |
10766 | ; |
10767 | ; Other atomic instruction patterns. | |
10768 | ; | |
10769 | ||
65b1d8ea AK |
10770 | ; z196 load and add, xor, or and and instructions |
10771 | ||
78ce265b RH |
10772 | (define_expand "atomic_fetch_<atomic><mode>" |
10773 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10774 | (ATOMIC_Z196:GPR | |
10775 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10776 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10777 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10778 | "TARGET_Z196" |
78ce265b | 10779 | { |
75cc21e2 AK |
10780 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10781 | FAIL; | |
10782 | ||
78ce265b RH |
10783 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10784 | (operands[0], operands[1], operands[2])); | |
10785 | DONE; | |
10786 | }) | |
65b1d8ea AK |
10787 | |
10788 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10789 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10790 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10791 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10792 | (set (match_dup 1) |
10793 | (unspec_volatile:GPR | |
10794 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10795 | (match_operand:GPR 2 "general_operand" "d"))] | |
10796 | UNSPECV_ATOMIC_OP)) | |
10797 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10798 | "TARGET_Z196" |
78ce265b RH |
10799 | "la<noxa><g>\t%0,%2,%1" |
10800 | [(set_attr "op_type" "RSY") | |
10801 | (set_attr "type" "sem")]) | |
65b1d8ea | 10802 | |
78ce265b RH |
10803 | ;; For SImode and larger, the optabs.c code will do just fine in |
10804 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10805 | ;; better by expanding our own loop. | |
65b1d8ea | 10806 | |
78ce265b RH |
10807 | (define_expand "atomic_<atomic><mode>" |
10808 | [(ATOMIC:HQI | |
10809 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10810 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10811 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10812 | "" |
78ce265b RH |
10813 | { |
10814 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10815 | operands[1], false); | |
10816 | DONE; | |
10817 | }) | |
45d18331 | 10818 | |
78ce265b RH |
10819 | (define_expand "atomic_fetch_<atomic><mode>" |
10820 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10821 | (ATOMIC:HQI | |
10822 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10823 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10824 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10825 | "" |
78ce265b RH |
10826 | { |
10827 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10828 | operands[2], false); | |
10829 | DONE; | |
10830 | }) | |
10831 | ||
10832 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10833 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10834 | (ATOMIC:HQI | |
10835 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10836 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10837 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10838 | "" | |
10839 | { | |
10840 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10841 | operands[2], true); | |
10842 | DONE; | |
10843 | }) | |
10844 | ||
03db9ab5 DV |
10845 | ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code |
10846 | ;; generated by the middleend is not good. | |
78ce265b | 10847 | (define_expand "atomic_exchange<mode>" |
03db9ab5 DV |
10848 | [(match_operand:DINT 0 "register_operand") ;; val out |
10849 | (match_operand:DINT 1 "s_operand") ;; memory | |
10850 | (match_operand:DINT 2 "general_operand") ;; val in | |
78ce265b | 10851 | (match_operand:SI 3 "const_int_operand")] ;; model |
45d18331 | 10852 | "" |
78ce265b | 10853 | { |
03db9ab5 DV |
10854 | if (<MODE>mode != QImode |
10855 | && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) | |
10856 | FAIL; | |
10857 | if (<MODE>mode == HImode || <MODE>mode == QImode) | |
10858 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], | |
10859 | false); | |
10860 | else if (<MODE>mode == SImode || TARGET_ZARCH) | |
10861 | s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); | |
10862 | else | |
10863 | FAIL; | |
78ce265b RH |
10864 | DONE; |
10865 | }) | |
45d18331 | 10866 | |
9db1d521 HP |
10867 | ;; |
10868 | ;;- Miscellaneous instructions. | |
10869 | ;; | |
10870 | ||
10871 | ; | |
10872 | ; allocate stack instruction pattern(s). | |
10873 | ; | |
10874 | ||
10875 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10876 | [(match_operand 0 "general_operand" "") |
10877 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10878 | "TARGET_BACKCHAIN" |
9db1d521 | 10879 | { |
ef44a6ff | 10880 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10881 | |
ef44a6ff UW |
10882 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10883 | anti_adjust_stack (operands[1]); | |
10884 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10885 | |
ef44a6ff UW |
10886 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10887 | DONE; | |
10bbf137 | 10888 | }) |
9db1d521 HP |
10889 | |
10890 | ||
10891 | ; | |
43ab026f | 10892 | ; setjmp instruction pattern. |
9db1d521 HP |
10893 | ; |
10894 | ||
9db1d521 | 10895 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10896 | [(match_operand 0 "" "")] |
f314b9b1 | 10897 | "flag_pic" |
9db1d521 | 10898 | { |
585539a1 | 10899 | emit_insn (s390_load_got ()); |
c41c1387 | 10900 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10901 | DONE; |
fd7643fb | 10902 | }) |
9db1d521 | 10903 | |
9db1d521 HP |
10904 | ;; These patterns say how to save and restore the stack pointer. We need not |
10905 | ;; save the stack pointer at function level since we are careful to | |
10906 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10907 | ;; when we restore the stack pointer. | |
10908 | ;; | |
10909 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10910 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10911 | ;; save area is a memory location. | |
10912 | ||
10913 | (define_expand "save_stack_function" | |
10914 | [(match_operand 0 "general_operand" "") | |
10915 | (match_operand 1 "general_operand" "")] | |
10916 | "" | |
10917 | "DONE;") | |
10918 | ||
10919 | (define_expand "restore_stack_function" | |
10920 | [(match_operand 0 "general_operand" "") | |
10921 | (match_operand 1 "general_operand" "")] | |
10922 | "" | |
10923 | "DONE;") | |
10924 | ||
10925 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10926 | [(match_operand 0 "register_operand" "") |
10927 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10928 | "TARGET_BACKCHAIN" |
9db1d521 | 10929 | { |
ef44a6ff UW |
10930 | rtx temp = gen_reg_rtx (Pmode); |
10931 | ||
10932 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10933 | emit_move_insn (operands[0], operands[1]); | |
10934 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10935 | ||
10936 | DONE; | |
10bbf137 | 10937 | }) |
9db1d521 HP |
10938 | |
10939 | (define_expand "save_stack_nonlocal" | |
10940 | [(match_operand 0 "memory_operand" "") | |
10941 | (match_operand 1 "register_operand" "")] | |
10942 | "" | |
9db1d521 | 10943 | { |
ef44a6ff UW |
10944 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10945 | ||
10946 | /* Copy the backchain to the first word, sp to the second and the | |
10947 | literal pool base to the third. */ | |
10948 | ||
9602b6a1 AK |
10949 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10950 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10951 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10952 | ||
b3d31392 | 10953 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10954 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10955 | |
9602b6a1 AK |
10956 | emit_move_insn (save_sp, operands[1]); |
10957 | emit_move_insn (save_bp, base); | |
9db1d521 | 10958 | |
9db1d521 | 10959 | DONE; |
10bbf137 | 10960 | }) |
9db1d521 HP |
10961 | |
10962 | (define_expand "restore_stack_nonlocal" | |
10963 | [(match_operand 0 "register_operand" "") | |
10964 | (match_operand 1 "memory_operand" "")] | |
10965 | "" | |
9db1d521 | 10966 | { |
490ceeb4 | 10967 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10968 | rtx temp = NULL_RTX; |
9db1d521 | 10969 | |
43ab026f | 10970 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10971 | literal pool base from the third. */ |
43ab026f | 10972 | |
9602b6a1 AK |
10973 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10974 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10975 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10976 | ||
b3d31392 | 10977 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10978 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10979 | |
9602b6a1 AK |
10980 | emit_move_insn (base, save_bp); |
10981 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10982 | |
10983 | if (temp) | |
10984 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10985 | ||
c41c1387 | 10986 | emit_use (base); |
9db1d521 | 10987 | DONE; |
10bbf137 | 10988 | }) |
9db1d521 | 10989 | |
7bcebb25 AK |
10990 | (define_expand "exception_receiver" |
10991 | [(const_int 0)] | |
10992 | "" | |
10993 | { | |
10994 | s390_set_has_landing_pad_p (true); | |
10995 | DONE; | |
10996 | }) | |
9db1d521 HP |
10997 | |
10998 | ; | |
10999 | ; nop instruction pattern(s). | |
11000 | ; | |
11001 | ||
11002 | (define_insn "nop" | |
11003 | [(const_int 0)] | |
11004 | "" | |
aad98a61 AK |
11005 | "nopr\t%%r0" |
11006 | [(set_attr "op_type" "RR")]) | |
11007 | ||
11008 | ; non-branch NOPs required for optimizing compare-and-branch patterns | |
11009 | ; on z10 | |
11010 | ||
11011 | (define_insn "nop_lr0" | |
11012 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] | |
11013 | "" | |
d40c829f | 11014 | "lr\t0,0" |
729e750f WG |
11015 | [(set_attr "op_type" "RR") |
11016 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 11017 | |
aad98a61 AK |
11018 | (define_insn "nop_lr1" |
11019 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] | |
d277db6b WG |
11020 | "" |
11021 | "lr\t1,1" | |
11022 | [(set_attr "op_type" "RR")]) | |
11023 | ||
f8af0e30 DV |
11024 | ;;- Undeletable nops (used for hotpatching) |
11025 | ||
11026 | (define_insn "nop_2_byte" | |
11027 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
11028 | "" | |
4bbc8970 | 11029 | "nopr\t%%r0" |
f8af0e30 DV |
11030 | [(set_attr "op_type" "RR")]) |
11031 | ||
11032 | (define_insn "nop_4_byte" | |
11033 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
11034 | "" | |
11035 | "nop\t0" | |
11036 | [(set_attr "op_type" "RX")]) | |
11037 | ||
11038 | (define_insn "nop_6_byte" | |
11039 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
11040 | "TARGET_CPU_ZARCH" | |
11041 | "brcl\t0, 0" | |
11042 | [(set_attr "op_type" "RIL")]) | |
11043 | ||
9db1d521 HP |
11044 | |
11045 | ; | |
11046 | ; Special literal pool access instruction pattern(s). | |
11047 | ; | |
11048 | ||
416cf582 UW |
11049 | (define_insn "*pool_entry" |
11050 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
11051 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 11052 | "" |
9db1d521 | 11053 | { |
ef4bddc2 | 11054 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 11055 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 11056 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
11057 | return ""; |
11058 | } | |
b628bd8e | 11059 | [(set (attr "length") |
416cf582 | 11060 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 11061 | |
9bb86f41 UW |
11062 | (define_insn "pool_align" |
11063 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
11064 | UNSPECV_POOL_ALIGN)] | |
11065 | "" | |
11066 | ".align\t%0" | |
b628bd8e | 11067 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 11068 | |
9bb86f41 UW |
11069 | (define_insn "pool_section_start" |
11070 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
11071 | "" | |
b929b470 MK |
11072 | { |
11073 | switch_to_section (targetm.asm_out.function_rodata_section | |
11074 | (current_function_decl)); | |
11075 | return ""; | |
11076 | } | |
b628bd8e | 11077 | [(set_attr "length" "0")]) |
b2ccb744 | 11078 | |
9bb86f41 UW |
11079 | (define_insn "pool_section_end" |
11080 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
11081 | "" | |
b929b470 MK |
11082 | { |
11083 | switch_to_section (current_function_section ()); | |
11084 | return ""; | |
11085 | } | |
b628bd8e | 11086 | [(set_attr "length" "0")]) |
b2ccb744 | 11087 | |
5af2f3d3 | 11088 | (define_insn "main_base_31_small" |
9e8327e3 UW |
11089 | [(set (match_operand 0 "register_operand" "=a") |
11090 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
11091 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
11092 | "basr\t%0,0" |
11093 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
11094 | (set_attr "type" "la") |
11095 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
11096 | |
11097 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
11098 | [(set (match_operand 0 "register_operand" "=a") |
11099 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 11100 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 11101 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 11102 | "bras\t%0,%2" |
65b1d8ea AK |
11103 | [(set_attr "op_type" "RI") |
11104 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
11105 | |
11106 | (define_insn "main_base_64" | |
9e8327e3 UW |
11107 | [(set (match_operand 0 "register_operand" "=a") |
11108 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
11109 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
11110 | "larl\t%0,%1" |
11111 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 11112 | (set_attr "type" "larl") |
729e750f | 11113 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
11114 | |
11115 | (define_insn "main_pool" | |
585539a1 UW |
11116 | [(set (match_operand 0 "register_operand" "=a") |
11117 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
11118 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
11119 | { |
11120 | gcc_unreachable (); | |
11121 | } | |
9381e3f1 | 11122 | [(set (attr "type") |
d7f99b2c | 11123 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 11124 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 11125 | |
aee4e0db | 11126 | (define_insn "reload_base_31" |
9e8327e3 UW |
11127 | [(set (match_operand 0 "register_operand" "=a") |
11128 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
11129 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 11130 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 11131 | [(set_attr "length" "6") |
65b1d8ea AK |
11132 | (set_attr "type" "la") |
11133 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 11134 | |
aee4e0db | 11135 | (define_insn "reload_base_64" |
9e8327e3 UW |
11136 | [(set (match_operand 0 "register_operand" "=a") |
11137 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
11138 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 11139 | "larl\t%0,%1" |
aee4e0db | 11140 | [(set_attr "op_type" "RIL") |
9381e3f1 | 11141 | (set_attr "type" "larl") |
729e750f | 11142 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 11143 | |
aee4e0db | 11144 | (define_insn "pool" |
fd7643fb | 11145 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 11146 | "" |
8d933e31 AS |
11147 | { |
11148 | gcc_unreachable (); | |
11149 | } | |
b628bd8e | 11150 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 11151 | |
4023fb28 UW |
11152 | ;; |
11153 | ;; Insns related to generating the function prologue and epilogue. | |
11154 | ;; | |
11155 | ||
11156 | ||
11157 | (define_expand "prologue" | |
11158 | [(use (const_int 0))] | |
11159 | "" | |
10bbf137 | 11160 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
11161 | |
11162 | (define_expand "epilogue" | |
11163 | [(use (const_int 1))] | |
11164 | "" | |
ed9676cf AK |
11165 | "s390_emit_epilogue (false); DONE;") |
11166 | ||
11167 | (define_expand "sibcall_epilogue" | |
11168 | [(use (const_int 0))] | |
11169 | "" | |
11170 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 11171 | |
177bc204 RS |
11172 | ;; A direct return instruction, without using an epilogue. |
11173 | (define_insn "<code>" | |
11174 | [(ANY_RETURN)] | |
11175 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
11176 | { |
11177 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11178 | { | |
11179 | /* The target is always r14 so there is no clobber | |
11180 | of r1 needed for pre z10 targets. */ | |
11181 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
11182 | INVALID_REGNUM, | |
11183 | NULL_RTX, | |
11184 | s390_indirect_branch_type_return); | |
11185 | return ""; | |
11186 | } | |
11187 | else | |
11188 | return "br\t%%r14"; | |
11189 | } | |
11190 | [(set (attr "op_type") | |
11191 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11192 | (const_string "RIL") | |
11193 | (const_string "RR"))) | |
11194 | (set (attr "mnemonic") | |
11195 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11196 | (const_string "jg") | |
11197 | (const_string "br"))) | |
177bc204 RS |
11198 | (set_attr "type" "jsr") |
11199 | (set_attr "atype" "agen")]) | |
11200 | ||
84b4c7b5 AK |
11201 | |
11202 | (define_expand "return_use" | |
11203 | [(parallel | |
11204 | [(return) | |
11205 | (use (match_operand 0 "register_operand" "a"))])] | |
11206 | "" | |
11207 | { | |
11208 | if (!TARGET_CPU_Z10 | |
11209 | && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) | |
11210 | { | |
11211 | if (TARGET_64BIT) | |
11212 | emit_jump_insn (gen_returndi_prez10 (operands[0])); | |
11213 | else | |
11214 | emit_jump_insn (gen_returnsi_prez10 (operands[0])); | |
11215 | DONE; | |
11216 | } | |
11217 | }) | |
11218 | ||
11219 | (define_insn "*return<mode>" | |
4023fb28 | 11220 | [(return) |
84b4c7b5 AK |
11221 | (use (match_operand:P 0 "register_operand" "a"))] |
11222 | "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
11223 | { | |
11224 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11225 | { | |
11226 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
11227 | INVALID_REGNUM, | |
11228 | NULL_RTX, | |
11229 | s390_indirect_branch_type_return); | |
11230 | return ""; | |
11231 | } | |
11232 | else | |
11233 | return "br\t%0"; | |
11234 | } | |
11235 | [(set (attr "op_type") | |
11236 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11237 | (const_string "RIL") | |
11238 | (const_string "RR"))) | |
11239 | (set (attr "mnemonic") | |
11240 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11241 | (const_string "jg") | |
11242 | (const_string "br"))) | |
11243 | (set_attr "type" "jsr") | |
11244 | (set_attr "atype" "agen")]) | |
11245 | ||
11246 | (define_insn "return<mode>_prez10" | |
11247 | [(return) | |
11248 | (use (match_operand:P 0 "register_operand" "a")) | |
11249 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
11250 | "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
11251 | { | |
11252 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11253 | { | |
11254 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
11255 | INVALID_REGNUM, | |
11256 | NULL_RTX, | |
11257 | s390_indirect_branch_type_return); | |
11258 | return ""; | |
11259 | } | |
11260 | else | |
11261 | return "br\t%0"; | |
11262 | } | |
11263 | [(set (attr "op_type") | |
11264 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11265 | (const_string "RIL") | |
11266 | (const_string "RR"))) | |
11267 | (set (attr "mnemonic") | |
11268 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11269 | (const_string "jg") | |
11270 | (const_string "br"))) | |
c7453384 | 11271 | (set_attr "type" "jsr") |
077dab3b | 11272 | (set_attr "atype" "agen")]) |
4023fb28 | 11273 | |
4023fb28 | 11274 | |
c7453384 | 11275 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 11276 | ;; pointer. This is used for compatibility. |
c7453384 EC |
11277 | |
11278 | (define_expand "ptr_extend" | |
11279 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11280 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 11281 | "TARGET_64BIT" |
c7453384 | 11282 | { |
c7453384 EC |
11283 | emit_insn (gen_anddi3 (operands[0], |
11284 | gen_lowpart (DImode, operands[1]), | |
11285 | GEN_INT (0x7fffffff))); | |
c7453384 | 11286 | DONE; |
10bbf137 | 11287 | }) |
4798630c D |
11288 | |
11289 | ;; Instruction definition to expand eh_return macro to support | |
11290 | ;; swapping in special linkage return addresses. | |
11291 | ||
11292 | (define_expand "eh_return" | |
11293 | [(use (match_operand 0 "register_operand" ""))] | |
11294 | "TARGET_TPF" | |
11295 | { | |
11296 | s390_emit_tpf_eh_return (operands[0]); | |
11297 | DONE; | |
11298 | }) | |
11299 | ||
7b8acc34 AK |
11300 | ; |
11301 | ; Stack Protector Patterns | |
11302 | ; | |
11303 | ||
11304 | (define_expand "stack_protect_set" | |
11305 | [(set (match_operand 0 "memory_operand" "") | |
11306 | (match_operand 1 "memory_operand" ""))] | |
11307 | "" | |
11308 | { | |
11309 | #ifdef TARGET_THREAD_SSP_OFFSET | |
11310 | operands[1] | |
11311 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11312 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11313 | #endif | |
11314 | if (TARGET_64BIT) | |
11315 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
11316 | else | |
11317 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
11318 | ||
11319 | DONE; | |
11320 | }) | |
11321 | ||
11322 | (define_insn "stack_protect_set<mode>" | |
11323 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
11324 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
11325 | "" | |
11326 | "mvc\t%O0(%G0,%R0),%S1" | |
11327 | [(set_attr "op_type" "SS")]) | |
11328 | ||
11329 | (define_expand "stack_protect_test" | |
11330 | [(set (reg:CC CC_REGNUM) | |
11331 | (compare (match_operand 0 "memory_operand" "") | |
11332 | (match_operand 1 "memory_operand" ""))) | |
11333 | (match_operand 2 "" "")] | |
11334 | "" | |
11335 | { | |
f90b7a5a | 11336 | rtx cc_reg, test; |
7b8acc34 AK |
11337 | #ifdef TARGET_THREAD_SSP_OFFSET |
11338 | operands[1] | |
11339 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11340 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11341 | #endif | |
7b8acc34 AK |
11342 | if (TARGET_64BIT) |
11343 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
11344 | else | |
11345 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
11346 | ||
f90b7a5a PB |
11347 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
11348 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
11349 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
11350 | DONE; |
11351 | }) | |
11352 | ||
11353 | (define_insn "stack_protect_test<mode>" | |
11354 | [(set (reg:CCZ CC_REGNUM) | |
11355 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
11356 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
11357 | "" | |
11358 | "clc\t%O0(%G0,%R0),%S1" | |
11359 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
11360 | |
11361 | ; This is used in s390_emit_prologue in order to prevent insns | |
11362 | ; adjusting the stack pointer to be moved over insns writing stack | |
11363 | ; slots using a copy of the stack pointer in a different register. | |
11364 | (define_insn "stack_tie" | |
11365 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
11366 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
11367 | "" | |
11368 | "" | |
11369 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
11370 | |
11371 | ||
82c6f58a AK |
11372 | (define_insn "stack_restore_from_fpr" |
11373 | [(set (reg:DI STACK_REGNUM) | |
11374 | (match_operand:DI 0 "register_operand" "f")) | |
11375 | (clobber (mem:BLK (scratch)))] | |
11376 | "TARGET_Z10" | |
11377 | "lgdr\t%%r15,%0" | |
11378 | [(set_attr "op_type" "RRE")]) | |
11379 | ||
963fc8d0 AK |
11380 | ; |
11381 | ; Data prefetch patterns | |
11382 | ; | |
11383 | ||
11384 | (define_insn "prefetch" | |
3e4be43f UW |
11385 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
11386 | (match_operand:SI 1 "const_int_operand" " n,n") | |
11387 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 11388 | "TARGET_Z10" |
963fc8d0 | 11389 | { |
4fe6dea8 AK |
11390 | switch (which_alternative) |
11391 | { | |
11392 | case 0: | |
4fe6dea8 | 11393 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 11394 | case 1: |
4fe6dea8 AK |
11395 | if (larl_operand (operands[0], Pmode)) |
11396 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 11397 | /* fallthrough */ |
4fe6dea8 AK |
11398 | default: |
11399 | ||
11400 | /* This might be reached for symbolic operands with an odd | |
11401 | addend. We simply omit the prefetch for such rare cases. */ | |
11402 | ||
11403 | return ""; | |
11404 | } | |
9381e3f1 | 11405 | } |
22d72dbc AK |
11406 | [(set_attr "type" "load,larl") |
11407 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
11408 | (set_attr "z10prop" "z10_super") |
11409 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
11410 | |
11411 | ||
11412 | ; | |
11413 | ; Byte swap instructions | |
11414 | ; | |
11415 | ||
511f5bb1 AK |
11416 | ; FIXME: There is also mvcin but we cannot use it since src and target |
11417 | ; may overlap. | |
50dc4eed | 11418 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 11419 | (define_insn "bswap<mode>2" |
3e4be43f UW |
11420 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
11421 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
677fbff4 | 11422 | "TARGET_CPU_ZARCH" |
07da44ab AK |
11423 | "@ |
11424 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
11425 | lrv<g>\t%0,%1 |
11426 | strv<g>\t%1,%0" | |
11427 | [(set_attr "type" "*,load,store") | |
11428 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 11429 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11430 | |
511f5bb1 | 11431 | (define_insn "bswaphi2" |
3e4be43f UW |
11432 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
11433 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
511f5bb1 | 11434 | "TARGET_CPU_ZARCH" |
6f5a59d1 AK |
11435 | "@ |
11436 | # | |
11437 | lrvh\t%0,%1 | |
11438 | strvh\t%1,%0" | |
11439 | [(set_attr "type" "*,load,store") | |
11440 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 11441 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11442 | |
6f5a59d1 AK |
11443 | (define_split |
11444 | [(set (match_operand:HI 0 "register_operand" "") | |
11445 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
11446 | "TARGET_CPU_ZARCH" | |
11447 | [(set (match_dup 2) (bswap:SI (match_dup 3))) | |
9060e335 | 11448 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 11449 | { |
9060e335 | 11450 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
11451 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
11452 | }) | |
11453 | ||
11454 | ||
65b1d8ea AK |
11455 | ; |
11456 | ; Population count instruction | |
11457 | ; | |
11458 | ||
11459 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
11460 | ; portions and stores the result in the corresponding bytes in op0. | |
11461 | (define_insn "*popcount<mode>" | |
11462 | [(set (match_operand:INT 0 "register_operand" "=d") | |
11463 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
11464 | (clobber (reg:CC CC_REGNUM))] | |
11465 | "TARGET_Z196" | |
11466 | "popcnt\t%0,%1" | |
11467 | [(set_attr "op_type" "RRE")]) | |
11468 | ||
11469 | (define_expand "popcountdi2" | |
11470 | [; popcnt op0, op1 | |
11471 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
11472 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
11473 | UNSPEC_POPCNT)) | |
11474 | (clobber (reg:CC CC_REGNUM))]) | |
11475 | ; sllg op2, op0, 32 | |
11476 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
11477 | ; agr op0, op2 | |
11478 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11479 | (clobber (reg:CC CC_REGNUM))]) | |
11480 | ; sllg op2, op0, 16 | |
17465c6e | 11481 | (set (match_dup 2) |
65b1d8ea AK |
11482 | (ashift:DI (match_dup 0) (const_int 16))) |
11483 | ; agr op0, op2 | |
11484 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11485 | (clobber (reg:CC CC_REGNUM))]) | |
11486 | ; sllg op2, op0, 8 | |
11487 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
11488 | ; agr op0, op2 | |
11489 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11490 | (clobber (reg:CC CC_REGNUM))]) | |
11491 | ; srlg op0, op0, 56 | |
11492 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
11493 | "TARGET_Z196 && TARGET_64BIT" | |
11494 | "operands[2] = gen_reg_rtx (DImode);") | |
11495 | ||
11496 | (define_expand "popcountsi2" | |
11497 | [; popcnt op0, op1 | |
11498 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
11499 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
11500 | UNSPEC_POPCNT)) | |
11501 | (clobber (reg:CC CC_REGNUM))]) | |
11502 | ; sllk op2, op0, 16 | |
17465c6e | 11503 | (set (match_dup 2) |
65b1d8ea AK |
11504 | (ashift:SI (match_dup 0) (const_int 16))) |
11505 | ; ar op0, op2 | |
11506 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11507 | (clobber (reg:CC CC_REGNUM))]) | |
11508 | ; sllk op2, op0, 8 | |
11509 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
11510 | ; ar op0, op2 | |
11511 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11512 | (clobber (reg:CC CC_REGNUM))]) | |
11513 | ; srl op0, op0, 24 | |
11514 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
11515 | "TARGET_Z196" | |
11516 | "operands[2] = gen_reg_rtx (SImode);") | |
11517 | ||
11518 | (define_expand "popcounthi2" | |
11519 | [; popcnt op0, op1 | |
11520 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
11521 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
11522 | UNSPEC_POPCNT)) | |
11523 | (clobber (reg:CC CC_REGNUM))]) | |
11524 | ; sllk op2, op0, 8 | |
17465c6e | 11525 | (set (match_dup 2) |
65b1d8ea AK |
11526 | (ashift:SI (match_dup 0) (const_int 8))) |
11527 | ; ar op0, op2 | |
11528 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11529 | (clobber (reg:CC CC_REGNUM))]) | |
11530 | ; srl op0, op0, 8 | |
11531 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
11532 | "TARGET_Z196" | |
11533 | "operands[2] = gen_reg_rtx (SImode);") | |
11534 | ||
11535 | (define_expand "popcountqi2" | |
11536 | [; popcnt op0, op1 | |
11537 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
11538 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
11539 | UNSPEC_POPCNT)) | |
11540 | (clobber (reg:CC CC_REGNUM))])] | |
11541 | "TARGET_Z196" | |
11542 | "") | |
11543 | ||
11544 | ;; | |
11545 | ;;- Copy sign instructions | |
11546 | ;; | |
11547 | ||
11548 | (define_insn "copysign<mode>3" | |
11549 | [(set (match_operand:FP 0 "register_operand" "=f") | |
11550 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
11551 | (match_operand:FP 2 "register_operand" "f")] | |
11552 | UNSPEC_COPYSIGN))] | |
11553 | "TARGET_Z196" | |
11554 | "cpsdr\t%0,%2,%1" | |
11555 | [(set_attr "op_type" "RRF") | |
11556 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
11557 | |
11558 | ||
11559 | ;; | |
11560 | ;;- Transactional execution instructions | |
11561 | ;; | |
11562 | ||
11563 | ; This splitter helps combine to make use of CC directly when | |
11564 | ; comparing the integer result of a tbegin builtin with a constant. | |
11565 | ; The unspec is already removed by canonicalize_comparison. So this | |
11566 | ; splitters only job is to turn the PARALLEL into separate insns | |
11567 | ; again. Unfortunately this only works with the very first cc/int | |
11568 | ; compare since combine is not able to deal with data flow across | |
11569 | ; basic block boundaries. | |
11570 | ||
11571 | ; It needs to be an insn pattern as well since combine does not apply | |
11572 | ; the splitter directly. Combine would only use it if it actually | |
11573 | ; would reduce the number of instructions. | |
11574 | (define_insn_and_split "*ccraw_to_int" | |
11575 | [(set (pc) | |
11576 | (if_then_else | |
11577 | (match_operator 0 "s390_eqne_operator" | |
11578 | [(reg:CCRAW CC_REGNUM) | |
11579 | (match_operand 1 "const_int_operand" "")]) | |
11580 | (label_ref (match_operand 2 "" "")) | |
11581 | (pc))) | |
11582 | (set (match_operand:SI 3 "register_operand" "=d") | |
11583 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
11584 | "" | |
11585 | "#" | |
11586 | "" | |
11587 | [(set (match_dup 3) | |
11588 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
11589 | (set (pc) | |
11590 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
11591 | (label_ref (match_dup 2)) | |
11592 | (pc)))] | |
11593 | "") | |
11594 | ||
11595 | ; Non-constrained transaction begin | |
11596 | ||
11597 | (define_expand "tbegin" | |
ee163e72 AK |
11598 | [(match_operand:SI 0 "register_operand" "") |
11599 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11600 | "TARGET_HTM" |
11601 | { | |
11602 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
11603 | DONE; | |
11604 | }) | |
11605 | ||
11606 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
11607 | [(match_operand:SI 0 "register_operand" "") |
11608 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11609 | "TARGET_HTM" |
11610 | { | |
11611 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
11612 | DONE; | |
11613 | }) | |
11614 | ||
11615 | (define_expand "tbegin_retry" | |
ee163e72 AK |
11616 | [(match_operand:SI 0 "register_operand" "") |
11617 | (match_operand:BLK 1 "memory_operand" "") | |
11618 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11619 | "TARGET_HTM" |
11620 | { | |
11621 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
11622 | DONE; | |
11623 | }) | |
11624 | ||
11625 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
11626 | [(match_operand:SI 0 "register_operand" "") |
11627 | (match_operand:BLK 1 "memory_operand" "") | |
11628 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11629 | "TARGET_HTM" |
11630 | { | |
11631 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
11632 | DONE; | |
11633 | }) | |
11634 | ||
c914ac45 AK |
11635 | ; Clobber VRs since they don't get restored |
11636 | (define_insn "tbegin_1_z13" | |
11637 | [(set (reg:CCRAW CC_REGNUM) | |
11638 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
11639 | UNSPECV_TBEGIN)) | |
11640 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11641 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
11642 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11643 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11644 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11645 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11646 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11647 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11648 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11649 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11650 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11651 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11652 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11653 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11654 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11655 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11656 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11657 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11658 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11659 | ; not supposed to be used for immediates (see genpreds.c). | |
11660 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11661 | "tbegin\t%1,%x0" | |
11662 | [(set_attr "op_type" "SIL")]) | |
11663 | ||
5a3fe9b6 AK |
11664 | (define_insn "tbegin_1" |
11665 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11666 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11667 | UNSPECV_TBEGIN)) |
2561451d AK |
11668 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11669 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11670 | (clobber (reg:DF 16)) |
11671 | (clobber (reg:DF 17)) | |
11672 | (clobber (reg:DF 18)) | |
11673 | (clobber (reg:DF 19)) | |
11674 | (clobber (reg:DF 20)) | |
11675 | (clobber (reg:DF 21)) | |
11676 | (clobber (reg:DF 22)) | |
11677 | (clobber (reg:DF 23)) | |
11678 | (clobber (reg:DF 24)) | |
11679 | (clobber (reg:DF 25)) | |
11680 | (clobber (reg:DF 26)) | |
11681 | (clobber (reg:DF 27)) | |
11682 | (clobber (reg:DF 28)) | |
11683 | (clobber (reg:DF 29)) | |
11684 | (clobber (reg:DF 30)) | |
11685 | (clobber (reg:DF 31))] | |
11686 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11687 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11688 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11689 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11690 | [(set_attr "op_type" "SIL")]) |
11691 | ||
11692 | ; Same as above but without the FPR clobbers | |
11693 | (define_insn "tbegin_nofloat_1" | |
11694 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11695 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11696 | UNSPECV_TBEGIN)) | |
11697 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11698 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11699 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11700 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11701 | [(set_attr "op_type" "SIL")]) |
11702 | ||
11703 | ||
11704 | ; Constrained transaction begin | |
11705 | ||
11706 | (define_expand "tbeginc" | |
11707 | [(set (reg:CCRAW CC_REGNUM) | |
11708 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11709 | UNSPECV_TBEGINC))] | |
11710 | "TARGET_HTM" | |
11711 | "") | |
11712 | ||
11713 | (define_insn "*tbeginc_1" | |
11714 | [(set (reg:CCRAW CC_REGNUM) | |
11715 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11716 | UNSPECV_TBEGINC))] | |
11717 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11718 | "tbeginc\t0,%x0" | |
11719 | [(set_attr "op_type" "SIL")]) | |
11720 | ||
11721 | ; Transaction end | |
11722 | ||
11723 | (define_expand "tend" | |
11724 | [(set (reg:CCRAW CC_REGNUM) | |
11725 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11726 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11727 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11728 | "TARGET_HTM" | |
11729 | "") | |
11730 | ||
11731 | (define_insn "*tend_1" | |
11732 | [(set (reg:CCRAW CC_REGNUM) | |
11733 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11734 | "TARGET_HTM" | |
11735 | "tend" | |
11736 | [(set_attr "op_type" "S")]) | |
11737 | ||
11738 | ; Transaction abort | |
11739 | ||
11740 | (define_expand "tabort" | |
eae48192 | 11741 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11742 | UNSPECV_TABORT)] |
11743 | "TARGET_HTM && operands != NULL" | |
11744 | { | |
11745 | if (CONST_INT_P (operands[0]) | |
11746 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11747 | { | |
f3981e7e | 11748 | error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC |
5a3fe9b6 AK |
11749 | ". Values in range 0 through 255 are reserved.", |
11750 | INTVAL (operands[0])); | |
11751 | FAIL; | |
11752 | } | |
11753 | }) | |
11754 | ||
11755 | (define_insn "*tabort_1" | |
eae48192 | 11756 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11757 | UNSPECV_TABORT)] |
11758 | "TARGET_HTM && operands != NULL" | |
11759 | "tabort\t%Y0" | |
11760 | [(set_attr "op_type" "S")]) | |
11761 | ||
eae48192 AK |
11762 | (define_insn "*tabort_1_plus" |
11763 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11764 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11765 | UNSPECV_TABORT)] | |
11766 | "TARGET_HTM && operands != NULL | |
11767 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11768 | "tabort\t%1(%0)" | |
11769 | [(set_attr "op_type" "S")]) | |
11770 | ||
5a3fe9b6 AK |
11771 | ; Transaction extract nesting depth |
11772 | ||
11773 | (define_insn "etnd" | |
11774 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11775 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11776 | "TARGET_HTM" | |
11777 | "etnd\t%0" | |
11778 | [(set_attr "op_type" "RRE")]) | |
11779 | ||
11780 | ; Non-transactional store | |
11781 | ||
11782 | (define_insn "ntstg" | |
3e4be43f | 11783 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11784 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11785 | UNSPECV_NTSTG))] | |
11786 | "TARGET_HTM" | |
11787 | "ntstg\t%1,%0" | |
11788 | [(set_attr "op_type" "RXY")]) | |
11789 | ||
11790 | ; Transaction perform processor assist | |
11791 | ||
11792 | (define_expand "tx_assist" | |
2561451d AK |
11793 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11794 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
11795 | (const_int 1)] |
11796 | UNSPECV_PPA)] | |
11797 | "TARGET_HTM" | |
2561451d | 11798 | "") |
5a3fe9b6 AK |
11799 | |
11800 | (define_insn "*ppa" | |
11801 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11802 | (match_operand:SI 1 "register_operand" "d") | |
11803 | (match_operand 2 "const_int_operand" "I")] | |
11804 | UNSPECV_PPA)] | |
11805 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 11806 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11807 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11808 | |
11809 | ||
11810 | ; Set and get floating point control register | |
11811 | ||
3af82a61 | 11812 | (define_insn "sfpc" |
004f64e1 AK |
11813 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11814 | UNSPECV_SFPC)] | |
11815 | "TARGET_HARD_FLOAT" | |
11816 | "sfpc\t%0") | |
11817 | ||
3af82a61 | 11818 | (define_insn "efpc" |
004f64e1 AK |
11819 | [(set (match_operand:SI 0 "register_operand" "=d") |
11820 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11821 | "TARGET_HARD_FLOAT" | |
11822 | "efpc\t%0") | |
3af82a61 AK |
11823 | |
11824 | ||
11825 | ; Load count to block boundary | |
11826 | ||
11827 | (define_insn "lcbb" | |
11828 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11829 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11830 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11831 | (clobber (reg:CC CC_REGNUM))] | |
11832 | "TARGET_Z13" | |
9a36359e | 11833 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11834 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11835 | |
11836 | ; Handle -fsplit-stack. | |
11837 | ||
11838 | (define_expand "split_stack_prologue" | |
11839 | [(const_int 0)] | |
11840 | "" | |
11841 | { | |
11842 | s390_expand_split_stack_prologue (); | |
11843 | DONE; | |
11844 | }) | |
11845 | ||
11846 | ;; If there are operand 0 bytes available on the stack, jump to | |
11847 | ;; operand 1. | |
11848 | ||
11849 | (define_expand "split_stack_space_check" | |
11850 | [(set (pc) (if_then_else | |
11851 | (ltu (minus (reg 15) | |
11852 | (match_operand 0 "register_operand")) | |
11853 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11854 | (label_ref (match_operand 1)) | |
11855 | (pc)))] | |
11856 | "" | |
11857 | { | |
11858 | /* Offset from thread pointer to __private_ss. */ | |
11859 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11860 | rtx tp = s390_get_thread_pointer (); | |
11861 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11862 | rtx reg = gen_reg_rtx (Pmode); | |
11863 | rtx cc; | |
11864 | if (TARGET_64BIT) | |
11865 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11866 | else | |
11867 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11868 | cc = s390_emit_compare (GT, reg, guard); | |
11869 | s390_emit_jump (operands[1], cc); | |
11870 | ||
11871 | DONE; | |
11872 | }) | |
11873 | ||
11874 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
11875 | ;; parameter block label, label to be called by __morestack, frame size, | |
11876 | ;; stack parameter size. | |
11877 | ||
11878 | (define_insn "split_stack_data" | |
11879 | [(unspec_volatile [(match_operand 0 "" "X") | |
11880 | (match_operand 1 "" "X") | |
11881 | (match_operand 2 "const_int_operand" "X") | |
11882 | (match_operand 3 "const_int_operand" "X")] | |
11883 | UNSPECV_SPLIT_STACK_DATA)] | |
11884 | "TARGET_CPU_ZARCH" | |
11885 | { | |
11886 | switch_to_section (targetm.asm_out.function_rodata_section | |
11887 | (current_function_decl)); | |
11888 | ||
11889 | if (TARGET_64BIT) | |
11890 | output_asm_insn (".align\t8", operands); | |
11891 | else | |
11892 | output_asm_insn (".align\t4", operands); | |
11893 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11894 | CODE_LABEL_NUMBER (operands[0])); | |
11895 | if (TARGET_64BIT) | |
11896 | { | |
11897 | output_asm_insn (".quad\t%2", operands); | |
11898 | output_asm_insn (".quad\t%3", operands); | |
11899 | output_asm_insn (".quad\t%1-%0", operands); | |
11900 | } | |
11901 | else | |
11902 | { | |
11903 | output_asm_insn (".long\t%2", operands); | |
11904 | output_asm_insn (".long\t%3", operands); | |
11905 | output_asm_insn (".long\t%1-%0", operands); | |
11906 | } | |
11907 | ||
11908 | switch_to_section (current_function_section ()); | |
11909 | return ""; | |
11910 | } | |
11911 | [(set_attr "length" "0")]) | |
11912 | ||
11913 | ||
11914 | ;; A jg with minimal fuss for use in split stack prologue. | |
11915 | ||
11916 | (define_expand "split_stack_call" | |
11917 | [(match_operand 0 "bras_sym_operand" "X") | |
11918 | (match_operand 1 "" "")] | |
11919 | "TARGET_CPU_ZARCH" | |
11920 | { | |
11921 | if (TARGET_64BIT) | |
11922 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11923 | else | |
11924 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11925 | DONE; | |
11926 | }) | |
11927 | ||
11928 | (define_insn "split_stack_call_<mode>" | |
11929 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11930 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11931 | (reg:P 1)] | |
11932 | UNSPECV_SPLIT_STACK_CALL))] | |
11933 | "TARGET_CPU_ZARCH" | |
11934 | "jg\t%0" | |
11935 | [(set_attr "op_type" "RIL") | |
11936 | (set_attr "type" "branch")]) | |
11937 | ||
11938 | ;; Also a conditional one. | |
11939 | ||
11940 | (define_expand "split_stack_cond_call" | |
11941 | [(match_operand 0 "bras_sym_operand" "X") | |
11942 | (match_operand 1 "" "") | |
11943 | (match_operand 2 "" "")] | |
11944 | "TARGET_CPU_ZARCH" | |
11945 | { | |
11946 | if (TARGET_64BIT) | |
11947 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11948 | else | |
11949 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11950 | DONE; | |
11951 | }) | |
11952 | ||
11953 | (define_insn "split_stack_cond_call_<mode>" | |
11954 | [(set (pc) | |
11955 | (if_then_else | |
11956 | (match_operand 1 "" "") | |
11957 | (label_ref (match_operand 2 "" "")) | |
11958 | (pc))) | |
11959 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11960 | (reg:P 1)] | |
11961 | UNSPECV_SPLIT_STACK_CALL))] | |
11962 | "TARGET_CPU_ZARCH" | |
11963 | "jg%C1\t%0" | |
11964 | [(set_attr "op_type" "RIL") | |
11965 | (set_attr "type" "branch")]) | |
539405d5 AK |
11966 | |
11967 | (define_insn "osc_break" | |
11968 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
11969 | "" | |
11970 | "bcr\t7,%%r0" | |
11971 | [(set_attr "op_type" "RR")]) |