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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
a5544970 | 2 | ;; Copyright (C) 1999-2019 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 | 77 | UNSPEC_LTREL_OFFSET |
30a49b23 AK |
78 | UNSPEC_POOL_OFFSET |
79 | UNSPEC_GOTENT | |
80 | UNSPEC_GOT | |
81 | UNSPEC_GOTOFF | |
82 | UNSPEC_PLT | |
83 | UNSPEC_PLTOFF | |
fd7643fb UW |
84 | |
85 | ; Literal pool | |
30a49b23 AK |
86 | UNSPEC_RELOAD_BASE |
87 | UNSPEC_MAIN_BASE | |
88 | UNSPEC_LTREF | |
89 | UNSPEC_INSN | |
90 | UNSPEC_EXECUTE | |
84b4c7b5 | 91 | UNSPEC_EXECUTE_JUMP |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
8f4f98f6 | 108 | UNSPEC_GET_TP |
91d39d71 UW |
109 | |
110 | ; String Functions | |
30a49b23 AK |
111 | UNSPEC_SRST |
112 | UNSPEC_MVST | |
638e37c2 | 113 | |
7b8acc34 | 114 | ; Stack Smashing Protector |
30a49b23 AK |
115 | UNSPEC_SP_SET |
116 | UNSPEC_SP_TEST | |
85dae55a | 117 | |
4cb4721f MK |
118 | ; Split stack support |
119 | UNSPEC_STACK_CHECK | |
120 | ||
638e37c2 | 121 | ; Test Data Class (TDC) |
30a49b23 | 122 | UNSPEC_TDC_INSN |
65b1d8ea | 123 | |
25cb5165 | 124 | ; Byte-wise Population Count |
30a49b23 AK |
125 | UNSPEC_POPCNT |
126 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
127 | |
128 | ; Load FP Integer | |
129 | UNSPEC_FPINT_FLOOR | |
130 | UNSPEC_FPINT_BTRUNC | |
131 | UNSPEC_FPINT_ROUND | |
132 | UNSPEC_FPINT_CEIL | |
133 | UNSPEC_FPINT_NEARBYINT | |
134 | UNSPEC_FPINT_RINT | |
085261c8 | 135 | |
3af82a61 AK |
136 | UNSPEC_LCBB |
137 | ||
085261c8 | 138 | ; Vector |
3af82a61 AK |
139 | UNSPEC_VEC_SMULT_HI |
140 | UNSPEC_VEC_UMULT_HI | |
141 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
142 | UNSPEC_VEC_SMULT_EVEN |
143 | UNSPEC_VEC_UMULT_EVEN | |
144 | UNSPEC_VEC_SMULT_ODD | |
145 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
146 | |
147 | UNSPEC_VEC_VMAL | |
148 | UNSPEC_VEC_VMAH | |
149 | UNSPEC_VEC_VMALH | |
150 | UNSPEC_VEC_VMAE | |
151 | UNSPEC_VEC_VMALE | |
152 | UNSPEC_VEC_VMAO | |
153 | UNSPEC_VEC_VMALO | |
154 | ||
155 | UNSPEC_VEC_GATHER | |
156 | UNSPEC_VEC_EXTRACT | |
157 | UNSPEC_VEC_INSERT_AND_ZERO | |
158 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 159 | UNSPEC_VEC_LOAD_LEN |
76794c52 | 160 | UNSPEC_VEC_LOAD_LEN_R |
3af82a61 AK |
161 | UNSPEC_VEC_MERGEH |
162 | UNSPEC_VEC_MERGEL | |
163 | UNSPEC_VEC_PACK | |
164 | UNSPEC_VEC_PACK_SATURATE | |
165 | UNSPEC_VEC_PACK_SATURATE_CC | |
166 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
168 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
169 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
170 | UNSPEC_VEC_PERM | |
171 | UNSPEC_VEC_PERMI | |
172 | UNSPEC_VEC_EXTEND | |
173 | UNSPEC_VEC_STORE_LEN | |
76794c52 AK |
174 | UNSPEC_VEC_STORE_LEN_R |
175 | UNSPEC_VEC_VBPERM | |
3af82a61 AK |
176 | UNSPEC_VEC_UNPACKH |
177 | UNSPEC_VEC_UNPACKH_L | |
178 | UNSPEC_VEC_UNPACKL | |
179 | UNSPEC_VEC_UNPACKL_L | |
180 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
181 | UNSPEC_VEC_ADDE_U128 |
182 | UNSPEC_VEC_ADDEC_U128 | |
183 | UNSPEC_VEC_AVG | |
184 | UNSPEC_VEC_AVGU | |
185 | UNSPEC_VEC_CHECKSUM | |
186 | UNSPEC_VEC_GFMSUM | |
187 | UNSPEC_VEC_GFMSUM_128 | |
188 | UNSPEC_VEC_GFMSUM_ACCUM | |
189 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
190 | UNSPEC_VEC_SET | |
191 | ||
192 | UNSPEC_VEC_VSUMG | |
193 | UNSPEC_VEC_VSUMQ | |
194 | UNSPEC_VEC_VSUM | |
195 | UNSPEC_VEC_RL_MASK | |
196 | UNSPEC_VEC_SLL | |
197 | UNSPEC_VEC_SLB | |
ad7a3e39 AK |
198 | UNSPEC_VEC_SLDBYTE |
199 | UNSPEC_VEC_SLDBIT | |
200 | UNSPEC_VEC_SRDBIT | |
3af82a61 AK |
201 | UNSPEC_VEC_SRAL |
202 | UNSPEC_VEC_SRAB | |
203 | UNSPEC_VEC_SRL | |
204 | UNSPEC_VEC_SRLB | |
205 | ||
3af82a61 | 206 | UNSPEC_VEC_SUBC |
3af82a61 AK |
207 | UNSPEC_VEC_SUBE_U128 |
208 | UNSPEC_VEC_SUBEC_U128 | |
209 | ||
210 | UNSPEC_VEC_TEST_MASK | |
211 | ||
212 | UNSPEC_VEC_VFAE | |
213 | UNSPEC_VEC_VFAECC | |
214 | ||
215 | UNSPEC_VEC_VFEE | |
216 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
217 | UNSPEC_VEC_VFENE |
218 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
219 | |
220 | UNSPEC_VEC_VISTR | |
221 | UNSPEC_VEC_VISTRCC | |
222 | ||
223 | UNSPEC_VEC_VSTRC | |
224 | UNSPEC_VEC_VSTRCCC | |
225 | ||
49adc461 AK |
226 | UNSPEC_VEC_VSTRS |
227 | UNSPEC_VEC_VSTRSCC | |
228 | ||
3af82a61 AK |
229 | UNSPEC_VEC_VCDGB |
230 | UNSPEC_VEC_VCDLGB | |
231 | ||
232 | UNSPEC_VEC_VCGDB | |
233 | UNSPEC_VEC_VCLGDB | |
234 | ||
76794c52 | 235 | UNSPEC_VEC_VFI |
3af82a61 | 236 | |
76794c52 AK |
237 | UNSPEC_VEC_VFLL ; vector fp load lengthened |
238 | UNSPEC_VEC_VFLR ; vector fp load rounded | |
3af82a61 | 239 | |
76794c52 AK |
240 | UNSPEC_VEC_VFTCI |
241 | UNSPEC_VEC_VFTCICC | |
242 | ||
243 | UNSPEC_VEC_MSUM | |
244 | ||
245 | UNSPEC_VEC_VFMIN | |
246 | UNSPEC_VEC_VFMAX | |
3278804e AK |
247 | |
248 | UNSPEC_VEC_ELTSWAP | |
085261c8 | 249 | ]) |
fd3cd001 UW |
250 | |
251 | ;; | |
252 | ;; UNSPEC_VOLATILE usage | |
253 | ;; | |
254 | ||
30a49b23 AK |
255 | (define_c_enum "unspecv" [ |
256 | ; Blockage | |
257 | UNSPECV_BLOCKAGE | |
10bbf137 | 258 | |
2f7e5a0d | 259 | ; TPF Support |
30a49b23 AK |
260 | UNSPECV_TPF_PROLOGUE |
261 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 262 | |
10bbf137 | 263 | ; Literal pool |
30a49b23 AK |
264 | UNSPECV_POOL |
265 | UNSPECV_POOL_SECTION | |
266 | UNSPECV_POOL_ALIGN | |
267 | UNSPECV_POOL_ENTRY | |
268 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
269 | |
270 | ; TLS support | |
30a49b23 | 271 | UNSPECV_SET_TP |
e0374221 AS |
272 | |
273 | ; Atomic Support | |
30a49b23 AK |
274 | UNSPECV_CAS |
275 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 276 | |
aad98a61 AK |
277 | ; Non-branch nops used for compare-and-branch adjustments on z10 |
278 | UNSPECV_NOP_LR_0 | |
279 | UNSPECV_NOP_LR_1 | |
280 | ||
f8af0e30 DV |
281 | ; Hotpatching (unremovable NOPs) |
282 | UNSPECV_NOP_2_BYTE | |
283 | UNSPECV_NOP_4_BYTE | |
284 | UNSPECV_NOP_6_BYTE | |
285 | ||
5a3fe9b6 AK |
286 | ; Transactional Execution support |
287 | UNSPECV_TBEGIN | |
2561451d | 288 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
289 | UNSPECV_TBEGINC |
290 | UNSPECV_TEND | |
291 | UNSPECV_TABORT | |
292 | UNSPECV_ETND | |
293 | UNSPECV_NTSTG | |
294 | UNSPECV_PPA | |
004f64e1 AK |
295 | |
296 | ; Set and get floating point control register | |
297 | UNSPECV_SFPC | |
298 | UNSPECV_EFPC | |
4cb4721f MK |
299 | |
300 | ; Split stack support | |
301 | UNSPECV_SPLIT_STACK_CALL | |
539405d5 AK |
302 | |
303 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
304 | ]) |
305 | ||
ae156f85 AS |
306 | ;; |
307 | ;; Registers | |
308 | ;; | |
309 | ||
35dd9a0e AK |
310 | ; Registers with special meaning |
311 | ||
ae156f85 AS |
312 | (define_constants |
313 | [ | |
314 | ; Sibling call register. | |
315 | (SIBCALL_REGNUM 1) | |
84b4c7b5 AK |
316 | ; A call-clobbered reg which can be used in indirect branch thunks |
317 | (INDIRECT_BRANCH_THUNK_REGNUM 1) | |
ae156f85 AS |
318 | ; Literal pool base register. |
319 | (BASE_REGNUM 13) | |
320 | ; Return address register. | |
321 | (RETURN_REGNUM 14) | |
82c6f58a AK |
322 | ; Stack pointer register. |
323 | (STACK_REGNUM 15) | |
ae156f85 AS |
324 | ; Condition code register. |
325 | (CC_REGNUM 33) | |
f4aa3848 | 326 | ; Thread local storage pointer register. |
ae156f85 AS |
327 | (TP_REGNUM 36) |
328 | ]) | |
329 | ||
35dd9a0e AK |
330 | ; Hardware register names |
331 | ||
332 | (define_constants | |
333 | [ | |
334 | ; General purpose registers | |
335 | (GPR0_REGNUM 0) | |
af344a30 | 336 | (GPR1_REGNUM 1) |
82379bdf AK |
337 | (GPR2_REGNUM 2) |
338 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
339 | ; Floating point registers. |
340 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
341 | (FPR1_REGNUM 20) |
342 | (FPR2_REGNUM 17) | |
343 | (FPR3_REGNUM 21) | |
344 | (FPR4_REGNUM 18) | |
345 | (FPR5_REGNUM 22) | |
346 | (FPR6_REGNUM 19) | |
347 | (FPR7_REGNUM 23) | |
348 | (FPR8_REGNUM 24) | |
349 | (FPR9_REGNUM 28) | |
350 | (FPR10_REGNUM 25) | |
351 | (FPR11_REGNUM 29) | |
352 | (FPR12_REGNUM 26) | |
353 | (FPR13_REGNUM 30) | |
354 | (FPR14_REGNUM 27) | |
355 | (FPR15_REGNUM 31) | |
085261c8 AK |
356 | (VR0_REGNUM 16) |
357 | (VR16_REGNUM 38) | |
358 | (VR23_REGNUM 45) | |
359 | (VR24_REGNUM 46) | |
360 | (VR31_REGNUM 53) | |
35dd9a0e AK |
361 | ]) |
362 | ||
ae8e301e AK |
363 | ; Rounding modes for binary floating point numbers |
364 | (define_constants | |
365 | [(BFP_RND_CURRENT 0) | |
366 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
367 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
368 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
369 | (BFP_RND_TOWARD_0 5) | |
370 | (BFP_RND_TOWARD_INF 6) | |
371 | (BFP_RND_TOWARD_MINF 7)]) | |
372 | ||
373 | ; Rounding modes for decimal floating point numbers | |
374 | ; 1-7 were introduced with the floating point extension facility | |
375 | ; available with z196 | |
376 | ; With these rounding modes (1-7) a quantum exception might occur | |
377 | ; which is suppressed for the other modes. | |
378 | (define_constants | |
379 | [(DFP_RND_CURRENT 0) | |
380 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
381 | (DFP_RND_CURRENT_QUANTEXC 2) | |
382 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
383 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
384 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
385 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
386 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
387 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
388 | (DFP_RND_TOWARD_0 9) | |
389 | (DFP_RND_TOWARD_INF 10) | |
390 | (DFP_RND_TOWARD_MINF 11) | |
391 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
392 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
393 | (DFP_RND_AWAY_FROM_0 14) | |
394 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
395 | ||
35dd9a0e AK |
396 | ;; |
397 | ;; PFPO GPR0 argument format | |
398 | ;; | |
399 | ||
400 | (define_constants | |
401 | [ | |
402 | ; PFPO operation type | |
403 | (PFPO_CONVERT 0x1000000) | |
404 | ; PFPO operand types | |
405 | (PFPO_OP_TYPE_SF 0x5) | |
406 | (PFPO_OP_TYPE_DF 0x6) | |
407 | (PFPO_OP_TYPE_TF 0x7) | |
408 | (PFPO_OP_TYPE_SD 0x8) | |
409 | (PFPO_OP_TYPE_DD 0x9) | |
410 | (PFPO_OP_TYPE_TD 0xa) | |
411 | ; Bitposition of operand types | |
412 | (PFPO_OP0_TYPE_SHIFT 16) | |
413 | (PFPO_OP1_TYPE_SHIFT 8) | |
ced8d882 AK |
414 | ; Decide whether current DFP or BFD rounding mode should be used |
415 | ; for the conversion. | |
416 | (PFPO_RND_MODE_DFP 0) | |
417 | (PFPO_RND_MODE_BFP 1) | |
35dd9a0e AK |
418 | ]) |
419 | ||
291a9e98 AK |
420 | ;; PPA constants |
421 | ||
422 | ; Immediate values which can be used as the third operand to the | |
423 | ; perform processor assist instruction | |
424 | ||
425 | (define_constants | |
426 | [(PPA_TX_ABORT 1) | |
427 | (PPA_OOO_BARRIER 15)]) | |
428 | ||
5a3fe9b6 AK |
429 | ; Immediate operands for tbegin and tbeginc |
430 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
431 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 432 | |
29a74354 UW |
433 | ;; Instruction operand type as used in the Principles of Operation. |
434 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 435 | |
29a74354 | 436 | (define_attr "op_type" |
76794c52 | 437 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" |
b628bd8e | 438 | (const_string "NN")) |
9db1d521 | 439 | |
29a74354 | 440 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 441 | |
077dab3b | 442 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 443 | cs,vs,store,sem,idiv, |
ed0e512a | 444 | imulhi,imulsi,imuldi, |
2cdece44 | 445 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
446 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
447 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 448 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 449 | fmadddf,fmaddsf, |
9381e3f1 WG |
450 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
451 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
452 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
453 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
454 | ftoidfp, other" | |
29a74354 UW |
455 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
456 | (eq_attr "op_type" "SS") (const_string "cs")] | |
457 | (const_string "integer"))) | |
9db1d521 | 458 | |
29a74354 UW |
459 | ;; Another attribute used for scheduling purposes: |
460 | ;; agen: Instruction uses the address generation unit | |
461 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
462 | |
463 | (define_attr "atype" "agen,reg" | |
62d3f261 | 464 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
465 | (const_string "reg") |
466 | (const_string "agen"))) | |
9db1d521 | 467 | |
9381e3f1 WG |
468 | ;; Properties concerning Z10 execution grouping and value forwarding. |
469 | ;; z10_super: instruction is superscalar. | |
470 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
471 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
472 | ;; target register. It can forward this value to a second instruction that reads | |
473 | ;; the same register if that second instruction is issued in the same group. | |
474 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
475 | ;; instruction in the S pipe writes to the register, then the T instruction | |
476 | ;; can immediately read the new value. | |
477 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
478 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
479 | ;; |
480 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
481 | ||
482 | ||
483 | (define_attr "z10prop" "none, | |
484 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
485 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
486 | z10_rec, | |
487 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 488 | z10_c" |
9381e3f1 WG |
489 | (const_string "none")) |
490 | ||
65b1d8ea AK |
491 | ;; Properties concerning Z196 decoding |
492 | ;; z196_alone: must group alone | |
493 | ;; z196_end: ends a group | |
494 | ;; z196_cracked: instruction is cracked or expanded | |
495 | (define_attr "z196prop" "none, | |
496 | z196_alone, z196_ends, | |
497 | z196_cracked" | |
498 | (const_string "none")) | |
9381e3f1 | 499 | |
84b4c7b5 AK |
500 | ; mnemonics which only get defined through if_then_else currently |
501 | ; don't get added to the list values automatically and hence need to | |
502 | ; be listed here. | |
8cc6307c | 503 | (define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 504 | |
9db1d521 HP |
505 | ;; Length in bytes. |
506 | ||
507 | (define_attr "length" "" | |
62d3f261 AK |
508 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
509 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 510 | (const_int 6))) |
9db1d521 | 511 | |
29a74354 UW |
512 | |
513 | ;; Processor type. This attribute must exactly match the processor_type | |
52d4aa4f | 514 | ;; enumeration in s390.h. |
29a74354 | 515 | |
80f8cd77 | 516 | (define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,z15" |
90c6fd8a | 517 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 518 | |
b5e0425c | 519 | (define_attr "cpu_facility" |
80f8cd77 | 520 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,z15,vxe2" |
3af8e996 AK |
521 | (const_string "standard")) |
522 | ||
523 | (define_attr "enabled" "" | |
524 | (cond [(eq_attr "cpu_facility" "standard") | |
525 | (const_int 1) | |
526 | ||
527 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 528 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
529 | (const_int 1) |
530 | ||
531 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 532 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
533 | (const_int 1) |
534 | ||
535 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 536 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
537 | (const_int 1) |
538 | ||
539 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 540 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
541 | (const_int 1) |
542 | ||
543 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 544 | (match_test "TARGET_DFP")) |
93538e8e AK |
545 | (const_int 1) |
546 | ||
8cc6307c | 547 | (eq_attr "cpu_facility" "cpu_zarch") |
b5e0425c AK |
548 | (const_int 1) |
549 | ||
93538e8e | 550 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 551 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
552 | (const_int 1) |
553 | ||
554 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 555 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
556 | (const_int 1) |
557 | ||
558 | (and (eq_attr "cpu_facility" "zEC12") | |
559 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
560 | (const_int 1) |
561 | ||
285363a1 | 562 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 563 | (match_test "TARGET_VX")) |
bf749919 DV |
564 | (const_int 1) |
565 | ||
566 | (and (eq_attr "cpu_facility" "z13") | |
567 | (match_test "TARGET_Z13")) | |
568 | (const_int 1) | |
6654e96f | 569 | |
e9e8efc9 AK |
570 | (and (eq_attr "cpu_facility" "z14") |
571 | (match_test "TARGET_Z14")) | |
6654e96f AK |
572 | (const_int 1) |
573 | ||
574 | (and (eq_attr "cpu_facility" "vxe") | |
575 | (match_test "TARGET_VXE")) | |
576 | (const_int 1) | |
511ea153 | 577 | |
80f8cd77 AK |
578 | (and (eq_attr "cpu_facility" "z15") |
579 | (match_test "TARGET_Z15")) | |
511ea153 AK |
580 | (const_int 1) |
581 | ||
582 | (and (eq_attr "cpu_facility" "vxe2") | |
583 | (match_test "TARGET_VXE2")) | |
584 | (const_int 1) | |
bf749919 | 585 | ] |
3af8e996 AK |
586 | (const_int 0))) |
587 | ||
14cfceb7 IL |
588 | ;; Whether an instruction supports relative long addressing. |
589 | ;; Currently this corresponds to RIL-b and RIL-c instruction formats, | |
590 | ;; but having a separate attribute, as opposed to reusing op_type, | |
591 | ;; provides additional flexibility. | |
592 | ||
593 | (define_attr "relative_long" "no,yes" (const_string "no")) | |
594 | ||
52d4aa4f | 595 | ;; Pipeline description for z900. |
29a74354 UW |
596 | (include "2064.md") |
597 | ||
3443392a | 598 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
599 | (include "2084.md") |
600 | ||
9381e3f1 WG |
601 | ;; Pipeline description for z10 |
602 | (include "2097.md") | |
603 | ||
65b1d8ea AK |
604 | ;; Pipeline description for z196 |
605 | (include "2817.md") | |
606 | ||
22ac2c2f AK |
607 | ;; Pipeline description for zEC12 |
608 | (include "2827.md") | |
609 | ||
23902021 AK |
610 | ;; Pipeline description for z13 |
611 | (include "2964.md") | |
612 | ||
ff99338c RD |
613 | ;; Pipeline description for z14 |
614 | (include "3906.md") | |
615 | ||
80f8cd77 | 616 | ;; Pipeline description for z15 |
375a6bc6 RD |
617 | (include "8561.md") |
618 | ||
0bfc3f69 AS |
619 | ;; Predicates |
620 | (include "predicates.md") | |
621 | ||
cd8dc1f9 WG |
622 | ;; Constraint definitions |
623 | (include "constraints.md") | |
624 | ||
a8ba31f2 EC |
625 | ;; Other includes |
626 | (include "tpf.md") | |
f52c81dd | 627 | |
3abcb3a7 | 628 | ;; Iterators |
f52c81dd | 629 | |
085261c8 AK |
630 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
631 | ||
3abcb3a7 | 632 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 633 | ;; same template. |
f4aa3848 | 634 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 635 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
636 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
637 | (define_mode_iterator BFP [TF DF SF]) | |
638 | (define_mode_iterator DFP [TD DD]) | |
639 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
640 | (define_mode_iterator DSF [DF SF]) | |
641 | (define_mode_iterator SD_SF [SF SD]) | |
642 | (define_mode_iterator DD_DF [DF DD]) | |
643 | (define_mode_iterator TD_TF [TF TD]) | |
644 | ||
80f8cd77 | 645 | ; 32 bit int<->fp conversion instructions are available since VXE2 (z15). |
026bfe89 AK |
646 | (define_mode_iterator VX_CONV_BFP [DF (SF "TARGET_VXE2")]) |
647 | (define_mode_iterator VX_CONV_INT [DI (SI "TARGET_VXE2")]) | |
648 | ||
3abcb3a7 | 649 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 650 | ;; from the same template. |
9602b6a1 | 651 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 652 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 653 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 654 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 655 | |
3abcb3a7 | 656 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 657 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 658 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 659 | |
78ce265b RH |
660 | ;; These macros refer to the actual word_mode of the configuration. |
661 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
662 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
663 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
664 | ||
6e0d70c9 AK |
665 | ;; Used by the umul pattern to express modes having half the size. |
666 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
667 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
668 | ||
3abcb3a7 | 669 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 670 | ;; the same template. |
3abcb3a7 | 671 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 672 | |
3abcb3a7 | 673 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 674 | ;; same template. |
9602b6a1 | 675 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 676 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 677 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 678 | |
3abcb3a7 | 679 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 680 | ;; the same template. |
3abcb3a7 | 681 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 682 | |
d12a76f3 | 683 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
684 | (define_code_iterator IXOR [ior xor]) |
685 | ||
4a9733f3 AK |
686 | ;; This is used for merging the nand/nor and and/or with complement patterns |
687 | (define_code_iterator ANDOR [and ior]) | |
688 | (define_code_attr bitops_name [(and "and") (ior "or")]) | |
689 | (define_code_attr inv_bitops_name [(and "or") (ior "and")]) | |
690 | (define_code_attr inv_no [(and "o") (ior "n")]) | |
691 | ||
d12a76f3 AK |
692 | ;; This iterator is used to expand the patterns for the nearest |
693 | ;; integer functions. | |
694 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
695 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
696 | UNSPEC_FPINT_NEARBYINT]) | |
697 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
698 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
699 | (UNSPEC_FPINT_ROUND "round") | |
700 | (UNSPEC_FPINT_CEIL "ceil") | |
701 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
702 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
703 | (UNSPEC_FPINT_BTRUNC "5") | |
704 | (UNSPEC_FPINT_ROUND "1") | |
705 | (UNSPEC_FPINT_CEIL "6") | |
706 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
707 | ||
3abcb3a7 HPN |
708 | ;; This iterator and attribute allow to combine most atomic operations. |
709 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 710 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 711 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 712 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 713 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 714 | |
f4aa3848 | 715 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 | 716 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
4156b056 | 717 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e") (V4SF "e") (V2DF "d")]) |
f337b930 | 718 | |
f4aa3848 AK |
719 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
720 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
721 | ;; SDmode. |
722 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 723 | |
609e7e80 | 724 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
725 | ;; Likewise for "<RXe>". |
726 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
727 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
728 | ||
609e7e80 | 729 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 730 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
731 | ;; dfp variants in a single insn definition. |
732 | ||
62d3f261 AK |
733 | ;; These mode attributes are supposed to be used in the `enabled' insn |
734 | ;; attribute to disable certain alternatives for certain modes. | |
735 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
736 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
737 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
738 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
739 | (TD "0") (DD "0") (DD "0") | |
740 | (TI "0") (DI "*") (SI "0")]) | |
026bfe89 AK |
741 | (define_mode_attr SFSI [(TF "0") (DF "0") (SF "*") |
742 | (TD "0") (DD "0") (DD "0") | |
743 | (TI "0") (DI "0") (SI "*")]) | |
2de2b3f9 AK |
744 | (define_mode_attr DF [(TF "0") (DF "*") (SF "0") |
745 | (TD "0") (DD "0") (DD "0") | |
746 | (TI "0") (DI "0") (SI "0")]) | |
747 | (define_mode_attr SF [(TF "0") (DF "0") (SF "*") | |
748 | (TD "0") (DD "0") (DD "0") | |
749 | (TI "0") (DI "0") (SI "0")]) | |
f5905b37 | 750 | |
85dae55a AK |
751 | ;; This attribute is used in the operand constraint list |
752 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
753 | ;; TFmode values are represented by a fp register pair. Since the | |
754 | ;; sign bit instructions only handle single source and target fp registers | |
755 | ;; these instructions can only be used for TFmode values if the source and | |
756 | ;; target operand uses the same fp register. | |
757 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
758 | ||
3abcb3a7 | 759 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
760 | ;; within instruction mnemonics. |
761 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
762 | ||
0387c142 WG |
763 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
764 | ;; modes and to an empty string for bfp modes. | |
765 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
766 | ||
1b48c8cc AS |
767 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
768 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
769 | ;; version only operates on one register. | |
770 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
771 | ||
772 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
773 | ;; version only operates on one register. The DImode version needs an additional | |
774 | ;; register for the assembler output. | |
775 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
776 | |
777 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
778 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
779 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
780 | ||
781 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 782 | ;; pattern itself and the corresponding function calls. |
f337b930 | 783 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
784 | |
785 | ;; This attribute handles differences in the instruction 'type' and will result | |
786 | ;; in "RRE" for DImode and "RR" for SImode. | |
787 | (define_mode_attr E [(DI "E") (SI "")]) | |
788 | ||
3298c037 AK |
789 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
790 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
791 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
792 | ||
8006eaa6 AS |
793 | ;; This attribute handles differences in the instruction 'type' and will result |
794 | ;; in "RSE" for TImode and "RS" for DImode. | |
795 | (define_mode_attr TE [(TI "E") (DI "")]) | |
796 | ||
9a91a21f AS |
797 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
798 | ;; and "lcr" in SImode. | |
799 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 800 | |
3298c037 AK |
801 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
802 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
803 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
804 | ;; variant for long displacements. | |
805 | (define_mode_attr y [(DI "g") (SI "y")]) | |
806 | ||
9602b6a1 | 807 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
808 | ;; and "cds" in DImode. |
809 | (define_mode_attr tg [(TI "g") (DI "")]) | |
810 | ||
78ce265b RH |
811 | ;; In TDI templates, a string like "c<d>sg". |
812 | (define_mode_attr td [(TI "d") (DI "")]) | |
813 | ||
2f8f8434 AS |
814 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
815 | ;; and "cfdbr" in SImode. | |
816 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
817 | ||
65b1d8ea AK |
818 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
819 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
820 | ;; 3 operands shift instructions into the existing patterns. | |
821 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
822 | ||
f52c81dd AS |
823 | ;; ICM mask required to load MODE value into the lowest subreg |
824 | ;; of a SImode register. | |
825 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
826 | ||
f6ee577c AS |
827 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
828 | ;; HImode and "llgc" in QImode. | |
829 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
830 | ||
a1aed706 AS |
831 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
832 | ;; in SImode. | |
833 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
834 | ||
609e7e80 AK |
835 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
836 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
837 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
838 | ||
f52c81dd AS |
839 | ;; Maximum unsigned integer that fits in MODE. |
840 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
841 | ||
75ca1b39 RH |
842 | ;; Start and end field computations for RISBG et al. |
843 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
844 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
845 | ||
2542ef05 RH |
846 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
847 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
848 | ;; 64 - bitsize |
849 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
850 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 851 | |
da0dcab1 DV |
852 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
853 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
854 | ||
177bc204 RS |
855 | ;; Allow return and simple_return to be defined from a single template. |
856 | (define_code_iterator ANY_RETURN [return simple_return]) | |
857 | ||
6e5b5de8 AK |
858 | |
859 | ||
860 | ; Condition code modes generated by vector fp comparisons. These will | |
861 | ; be used also in single element mode. | |
862 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
863 | ; Used with VFCMP to expand part of the mnemonic | |
864 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
865 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 866 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 867 | |
191eb16d AK |
868 | ;; Subst pattern definitions |
869 | (include "subst.md") | |
6e5b5de8 | 870 | |
085261c8 AK |
871 | (include "vector.md") |
872 | ||
9db1d521 HP |
873 | ;; |
874 | ;;- Compare instructions. | |
875 | ;; | |
876 | ||
07893d4f | 877 | ; Test-under-Mask instructions |
9db1d521 | 878 | |
07893d4f | 879 | (define_insn "*tmqi_mem" |
ae156f85 | 880 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
881 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
882 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
883 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 884 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 885 | "@ |
fc0ea003 UW |
886 | tm\t%S0,%b1 |
887 | tmy\t%S0,%b1" | |
9381e3f1 | 888 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 889 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 890 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 891 | |
05b9aaaa | 892 | (define_insn "*tmdi_reg" |
ae156f85 | 893 | [(set (reg CC_REGNUM) |
f19a9af7 | 894 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 895 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
896 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
897 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 898 | "TARGET_ZARCH |
3ed99cc9 | 899 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
900 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
901 | "@ | |
902 | tmhh\t%0,%i1 | |
903 | tmhl\t%0,%i1 | |
904 | tmlh\t%0,%i1 | |
905 | tmll\t%0,%i1" | |
9381e3f1 WG |
906 | [(set_attr "op_type" "RI") |
907 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
908 | |
909 | (define_insn "*tmsi_reg" | |
ae156f85 | 910 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
911 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
912 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
913 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 914 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
915 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
916 | "@ | |
917 | tmh\t%0,%i1 | |
918 | tml\t%0,%i1" | |
729e750f WG |
919 | [(set_attr "op_type" "RI") |
920 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 921 | |
f52c81dd | 922 | (define_insn "*tm<mode>_full" |
ae156f85 | 923 | [(set (reg CC_REGNUM) |
f52c81dd AS |
924 | (compare (match_operand:HQI 0 "register_operand" "d") |
925 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 926 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 927 | "tml\t%0,<max_uint>" |
729e750f WG |
928 | [(set_attr "op_type" "RI") |
929 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 930 | |
07893d4f | 931 | |
08a5aaa2 | 932 | ; |
07893d4f | 933 | ; Load-and-Test instructions |
08a5aaa2 AS |
934 | ; |
935 | ||
c0220ea4 | 936 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
937 | |
938 | (define_insn "*tstdi_sign" | |
ae156f85 | 939 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
940 | (compare |
941 | (ashiftrt:DI | |
942 | (ashift:DI | |
3e4be43f | 943 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
944 | (const_int 32)) (const_int 32)) |
945 | (match_operand:DI 1 "const0_operand" ""))) | |
946 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 947 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 948 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
949 | "ltgfr\t%2,%0 |
950 | ltgf\t%2,%0" | |
951 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
952 | (set_attr "cpu_facility" "*,z10") |
953 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 954 | |
43a09b63 | 955 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 956 | (define_insn "*tst<mode>_extimm" |
ec24698e | 957 | [(set (reg CC_REGNUM) |
3e4be43f | 958 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
959 | (match_operand:GPR 1 "const0_operand" ""))) |
960 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 961 | (match_dup 0))] |
08a5aaa2 | 962 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 963 | "@ |
08a5aaa2 AS |
964 | lt<g>r\t%2,%0 |
965 | lt<g>\t%2,%0" | |
9381e3f1 | 966 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 967 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 968 | |
97160c9b DV |
969 | ; Peephole to combine a load-and-test from volatile memory which combine does |
970 | ; not do. | |
971 | (define_peephole2 | |
972 | [(set (match_operand:GPR 0 "register_operand") | |
973 | (match_operand:GPR 2 "memory_operand")) | |
974 | (set (reg CC_REGNUM) | |
975 | (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] | |
976 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM | |
977 | && GENERAL_REG_P (operands[0]) | |
34a249bc IL |
978 | && satisfies_constraint_T (operands[2]) |
979 | && !contains_constant_pool_address_p (operands[2])" | |
97160c9b DV |
980 | [(parallel |
981 | [(set (reg:CCS CC_REGNUM) | |
982 | (compare:CCS (match_dup 2) (match_dup 1))) | |
983 | (set (match_dup 0) (match_dup 2))])]) | |
984 | ||
43a09b63 | 985 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 986 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 987 | [(set (reg CC_REGNUM) |
3e4be43f | 988 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
989 | (match_operand:GPR 1 "const0_operand" ""))) |
990 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
991 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 992 | "@ |
08a5aaa2 AS |
993 | lt<g>r\t%0,%0 |
994 | lt<g>\t%2,%0" | |
9381e3f1 | 995 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 996 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 997 | |
07893d4f | 998 | (define_insn "*tstdi" |
ae156f85 | 999 | [(set (reg CC_REGNUM) |
07893d4f UW |
1000 | (compare (match_operand:DI 0 "register_operand" "d") |
1001 | (match_operand:DI 1 "const0_operand" ""))) | |
1002 | (set (match_operand:DI 2 "register_operand" "=d") | |
1003 | (match_dup 0))] | |
9602b6a1 | 1004 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 1005 | "ltgr\t%2,%0" |
9381e3f1 WG |
1006 | [(set_attr "op_type" "RRE") |
1007 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 1008 | |
07893d4f | 1009 | (define_insn "*tstsi" |
ae156f85 | 1010 | [(set (reg CC_REGNUM) |
d3632d41 | 1011 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 1012 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 1013 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 1014 | (match_dup 0))] |
ec24698e | 1015 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 1016 | "@ |
d40c829f | 1017 | ltr\t%2,%0 |
fc0ea003 UW |
1018 | icm\t%2,15,%S0 |
1019 | icmy\t%2,15,%S0" | |
9381e3f1 | 1020 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 1021 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 1022 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 1023 | |
07893d4f | 1024 | (define_insn "*tstsi_cconly" |
ae156f85 | 1025 | [(set (reg CC_REGNUM) |
d3632d41 | 1026 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 1027 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 1028 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
1029 | "s390_match_ccmode(insn, CCSmode)" |
1030 | "@ | |
d40c829f | 1031 | ltr\t%0,%0 |
fc0ea003 UW |
1032 | icm\t%2,15,%S0 |
1033 | icmy\t%2,15,%S0" | |
9381e3f1 | 1034 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 1035 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 1036 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 1037 | |
08a5aaa2 AS |
1038 | (define_insn "*tstdi_cconly_31" |
1039 | [(set (reg CC_REGNUM) | |
1040 | (compare (match_operand:DI 0 "register_operand" "d") | |
1041 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 1042 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
1043 | "srda\t%0,0" |
1044 | [(set_attr "op_type" "RS") | |
1045 | (set_attr "atype" "reg")]) | |
1046 | ||
43a09b63 | 1047 | ; ltr, ltgr |
08a5aaa2 | 1048 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 1049 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
1050 | (compare (match_operand:GPR 0 "register_operand" "d") |
1051 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 1052 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 1053 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
1054 | [(set_attr "op_type" "RR<E>") |
1055 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 1056 | |
c0220ea4 | 1057 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 1058 | |
f52c81dd | 1059 | (define_insn "*tst<mode>CCT" |
ae156f85 | 1060 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1061 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
1062 | (match_operand:HQI 1 "const0_operand" ""))) | |
1063 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
1064 | (match_dup 0))] |
1065 | "s390_match_ccmode(insn, CCTmode)" | |
1066 | "@ | |
f52c81dd AS |
1067 | icm\t%2,<icm_lo>,%S0 |
1068 | icmy\t%2,<icm_lo>,%S0 | |
1069 | tml\t%0,<max_uint>" | |
9381e3f1 | 1070 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1071 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1072 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
1073 | |
1074 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 1075 | [(set (reg CC_REGNUM) |
d3632d41 | 1076 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 1077 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 1078 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
1079 | "s390_match_ccmode(insn, CCTmode)" |
1080 | "@ | |
fc0ea003 UW |
1081 | icm\t%2,3,%S0 |
1082 | icmy\t%2,3,%S0 | |
d40c829f | 1083 | tml\t%0,65535" |
9381e3f1 | 1084 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1085 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1086 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 1087 | |
3af97654 | 1088 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1089 | [(set (reg CC_REGNUM) |
d3632d41 | 1090 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1091 | (match_operand:QI 1 "const0_operand" "")))] |
1092 | "s390_match_ccmode(insn, CCTmode)" | |
1093 | "@ | |
fc0ea003 UW |
1094 | cli\t%S0,0 |
1095 | cliy\t%S0,0 | |
d40c829f | 1096 | tml\t%0,255" |
9381e3f1 | 1097 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1098 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1099 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1100 | |
f52c81dd | 1101 | (define_insn "*tst<mode>" |
ae156f85 | 1102 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1103 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1104 | (match_operand:HQI 1 "const0_operand" ""))) | |
1105 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1106 | (match_dup 0))] |
1107 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1108 | "@ |
f52c81dd AS |
1109 | icm\t%2,<icm_lo>,%S0 |
1110 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1111 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1112 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1113 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1114 | |
f52c81dd | 1115 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1116 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1117 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1118 | (match_operand:HQI 1 "const0_operand" ""))) | |
1119 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1120 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1121 | "@ |
f52c81dd AS |
1122 | icm\t%2,<icm_lo>,%S0 |
1123 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1124 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1125 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1126 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1127 | |
9db1d521 | 1128 | |
575f7c2b UW |
1129 | ; Compare (equality) instructions |
1130 | ||
1131 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1132 | [(set (reg CC_REGNUM) |
ec24698e | 1133 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1134 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1135 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1136 | "@ |
1137 | cgr\t%0,%1 | |
f4f41b4e | 1138 | cghi\t%0,%h1 |
ec24698e | 1139 | cgfi\t%0,%1 |
575f7c2b | 1140 | cg\t%0,%1 |
19b63d8e | 1141 | #" |
9381e3f1 WG |
1142 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1143 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1144 | |
1145 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1146 | [(set (reg CC_REGNUM) |
ec24698e UW |
1147 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1148 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1149 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1150 | "@ |
1151 | cr\t%0,%1 | |
f4f41b4e | 1152 | chi\t%0,%h1 |
ec24698e | 1153 | cfi\t%0,%1 |
575f7c2b UW |
1154 | c\t%0,%1 |
1155 | cy\t%0,%1 | |
19b63d8e | 1156 | #" |
9381e3f1 | 1157 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1158 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1159 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1160 | |
07893d4f | 1161 | ; Compare (signed) instructions |
4023fb28 | 1162 | |
07893d4f | 1163 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1164 | [(set (reg CC_REGNUM) |
963fc8d0 | 1165 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1166 | "d,T,b")) |
963fc8d0 | 1167 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1168 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1169 | "@ |
d40c829f | 1170 | cgfr\t%0,%1 |
963fc8d0 AK |
1171 | cgf\t%0,%1 |
1172 | cgfrl\t%0,%1" | |
1173 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1174 | (set_attr "z10prop" "z10_c,*,*") |
14cfceb7 IL |
1175 | (set_attr "type" "*,*,larl") |
1176 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 | 1177 | |
9381e3f1 WG |
1178 | |
1179 | ||
07893d4f | 1180 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1181 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1182 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1183 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1184 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1185 | "@ |
d40c829f | 1186 | ch\t%0,%1 |
963fc8d0 AK |
1187 | chy\t%0,%1 |
1188 | chrl\t%0,%1" | |
1189 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1190 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea | 1191 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1192 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked") |
1193 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 AK |
1194 | |
1195 | (define_insn "*cmphi_ccs_z10" | |
1196 | [(set (reg CC_REGNUM) | |
1197 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1198 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1199 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1200 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1201 | [(set_attr "op_type" "SIL") |
1202 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1203 | |
1204 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1205 | [(set (reg CC_REGNUM) | |
3e4be43f | 1206 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1207 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1208 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1209 | "@ | |
1210 | cgh\t%0,%1 | |
1211 | cghrl\t%0,%1" | |
1212 | [(set_attr "op_type" "RXY,RIL") | |
14cfceb7 IL |
1213 | (set_attr "type" "*,larl") |
1214 | (set_attr "relative_long" "*,yes")]) | |
4023fb28 | 1215 | |
963fc8d0 | 1216 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1217 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1218 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1219 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1220 | "d,d,Q, d,d,d,d") | |
1221 | (match_operand:GPR 1 "general_operand" | |
1222 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1223 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1224 | "@ |
3298c037 AK |
1225 | c<g>r\t%0,%1 |
1226 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1227 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1228 | c<g>fi\t%0,%1 |
1229 | c<g>\t%0,%1 | |
963fc8d0 AK |
1230 | c<y>\t%0,%1 |
1231 | c<g>rl\t%0,%1" | |
1232 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1233 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 | 1234 | (set_attr "type" "*,*,*,*,*,*,larl") |
14cfceb7 IL |
1235 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super") |
1236 | (set_attr "relative_long" "*,*,*,*,*,*,yes")]) | |
c7453384 | 1237 | |
07893d4f UW |
1238 | |
1239 | ; Compare (unsigned) instructions | |
9db1d521 | 1240 | |
963fc8d0 AK |
1241 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1242 | [(set (reg CC_REGNUM) | |
1243 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1244 | "larl_operand" "X"))) | |
1245 | (match_operand:SI 0 "register_operand" "d")))] | |
1246 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1247 | "clhrl\t%0,%1" | |
1248 | [(set_attr "op_type" "RIL") | |
729e750f | 1249 | (set_attr "type" "larl") |
14cfceb7 IL |
1250 | (set_attr "z10prop" "z10_super") |
1251 | (set_attr "relative_long" "yes")]) | |
963fc8d0 AK |
1252 | |
1253 | ; clhrl, clghrl | |
1254 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1255 | [(set (reg CC_REGNUM) | |
1256 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1257 | "larl_operand" "X"))) | |
1258 | (match_operand:GPR 0 "register_operand" "d")))] | |
1259 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1260 | "cl<g>hrl\t%0,%1" | |
1261 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1262 | (set_attr "type" "larl") |
14cfceb7 IL |
1263 | (set_attr "z10prop" "z10_super") |
1264 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 1265 | |
07893d4f | 1266 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1267 | [(set (reg CC_REGNUM) |
963fc8d0 | 1268 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1269 | "d,T,b")) |
1270 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1271 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1272 | "@ |
d40c829f | 1273 | clgfr\t%0,%1 |
963fc8d0 AK |
1274 | clgf\t%0,%1 |
1275 | clgfrl\t%0,%1" | |
1276 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1277 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 | 1278 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1279 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super") |
1280 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 1281 | |
07893d4f | 1282 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1283 | [(set (reg CC_REGNUM) |
963fc8d0 | 1284 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1285 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1286 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1287 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1288 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1289 | "@ |
d40c829f | 1290 | clgr\t%0,%1 |
ec24698e | 1291 | clgfi\t%0,%1 |
963fc8d0 AK |
1292 | clgrl\t%0,%1 |
1293 | clghsi\t%0,%x1 | |
575f7c2b | 1294 | clg\t%0,%1 |
e221ef54 | 1295 | # |
19b63d8e | 1296 | #" |
963fc8d0 AK |
1297 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1298 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 | 1299 | (set_attr "type" "*,*,larl,*,*,*,*") |
14cfceb7 IL |
1300 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*") |
1301 | (set_attr "relative_long" "*,*,yes,*,*,*,*")]) | |
9db1d521 | 1302 | |
07893d4f | 1303 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1304 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1305 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1306 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1307 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1308 | "@ |
d40c829f | 1309 | clr\t%0,%1 |
ec24698e | 1310 | clfi\t%0,%o1 |
963fc8d0 AK |
1311 | clrl\t%0,%1 |
1312 | clfhsi\t%0,%x1 | |
d40c829f | 1313 | cl\t%0,%1 |
575f7c2b | 1314 | cly\t%0,%1 |
e221ef54 | 1315 | # |
19b63d8e | 1316 | #" |
963fc8d0 | 1317 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1318 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 | 1319 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
14cfceb7 IL |
1320 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*") |
1321 | (set_attr "relative_long" "*,*,yes,*,*,*,*,*")]) | |
9db1d521 | 1322 | |
07893d4f | 1323 | (define_insn "*cmphi_ccu" |
ae156f85 | 1324 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1325 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1326 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1327 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1328 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1329 | "@ |
fc0ea003 UW |
1330 | clm\t%0,3,%S1 |
1331 | clmy\t%0,3,%S1 | |
963fc8d0 | 1332 | clhhsi\t%0,%1 |
e221ef54 | 1333 | # |
19b63d8e | 1334 | #" |
963fc8d0 | 1335 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1336 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1337 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1338 | |
1339 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1340 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1341 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1342 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1343 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1344 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1345 | "@ |
fc0ea003 UW |
1346 | clm\t%0,1,%S1 |
1347 | clmy\t%0,1,%S1 | |
1348 | cli\t%S0,%b1 | |
1349 | cliy\t%S0,%b1 | |
e221ef54 | 1350 | # |
19b63d8e | 1351 | #" |
9381e3f1 | 1352 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1353 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1354 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1355 | |
1356 | ||
19b63d8e UW |
1357 | ; Block compare (CLC) instruction patterns. |
1358 | ||
1359 | (define_insn "*clc" | |
ae156f85 | 1360 | [(set (reg CC_REGNUM) |
d4f52f0e | 1361 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1362 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1363 | (use (match_operand 2 "const_int_operand" "n"))] | |
1364 | "s390_match_ccmode (insn, CCUmode) | |
1365 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1366 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1367 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1368 | |
1369 | (define_split | |
ae156f85 | 1370 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1371 | (compare (match_operand 0 "memory_operand" "") |
1372 | (match_operand 1 "memory_operand" "")))] | |
1373 | "reload_completed | |
1374 | && s390_match_ccmode (insn, CCUmode) | |
1375 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1376 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1377 | [(parallel | |
1378 | [(set (match_dup 0) (match_dup 1)) | |
1379 | (use (match_dup 2))])] | |
1380 | { | |
1381 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1382 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1383 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1384 | ||
1385 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1386 | operands[0], operands[1]); | |
1387 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1388 | }) | |
1389 | ||
1390 | ||
609e7e80 | 1391 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1392 | |
e325aba2 | 1393 | |
64c8e85a | 1394 | ; FIXME: load and test instructions turn SNaN into QNaN what is not |
e325aba2 AK |
1395 | ; acceptable if the target will be used afterwards. On the other hand |
1396 | ; they are quite convenient for implementing comparisons with 0.0. So | |
64c8e85a AK |
1397 | ; try to enable them via splitter/peephole if the value isn't needed anymore. |
1398 | ; See testcases: load-and-test-fp-1.c and load-and-test-fp-2.c | |
e325aba2 | 1399 | |
609e7e80 | 1400 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1401 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1402 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1403 | (compare (match_operand:FP 0 "register_operand" "f") |
1404 | (match_operand:FP 1 "const0_operand" ""))) | |
1405 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1406 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1407 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1408 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1409 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1410 | |
2de2b3f9 AK |
1411 | ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb |
1412 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb | |
f5905b37 | 1413 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1414 | [(set (reg CC_REGNUM) |
2de2b3f9 AK |
1415 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") |
1416 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
142cd70f | 1417 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1418 | "@ |
609e7e80 | 1419 | c<xde><bt>r\t%0,%1 |
77c585ca | 1420 | c<xde>b\t%0,%1 |
2de2b3f9 AK |
1421 | wfcdb\t%0,%1 |
1422 | wfcsb\t%0,%1" | |
1423 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1424 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1425 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
963fc8d0 | 1426 | |
d0a0caca IL |
1427 | (define_insn "*cmp<mode>_ccsfps" |
1428 | [(set (reg CC_REGNUM) | |
1429 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") | |
1430 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
1431 | "s390_match_ccmode (insn, CCSFPSmode) && TARGET_HARD_FLOAT" | |
1432 | "@ | |
1433 | k<xde><bt>r\t%0,%1 | |
1434 | k<xde>b\t%0,%1 | |
1435 | wfkdb\t%0,%1 | |
1436 | wfksb\t%0,%1" | |
1437 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1438 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1439 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
1440 | ||
963fc8d0 AK |
1441 | ; Compare and Branch instructions |
1442 | ||
1443 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1444 | ; The following instructions do a complementary access of their second |
1445 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1446 | (define_insn "*cmp_and_br_signed_<mode>" |
1447 | [(set (pc) | |
1448 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1449 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1450 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1451 | (label_ref (match_operand 3 "" "")) | |
1452 | (pc))) | |
1453 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1454 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1455 | { |
1456 | if (get_attr_length (insn) == 6) | |
1457 | return which_alternative ? | |
1458 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1459 | else | |
1460 | return which_alternative ? | |
1461 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1462 | } | |
1463 | [(set_attr "op_type" "RIE") | |
1464 | (set_attr "type" "branch") | |
e3cba5e5 | 1465 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1466 | (set (attr "length") |
1467 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1468 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1469 | ; 10 byte for cgr/jg | |
1470 | ||
1471 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1472 | ; The following instructions do a complementary access of their second |
1473 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1474 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1475 | [(set (pc) | |
1476 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1477 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1478 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1479 | (label_ref (match_operand 3 "" "")) | |
1480 | (pc))) | |
1481 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1482 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1483 | { |
1484 | if (get_attr_length (insn) == 6) | |
1485 | return which_alternative ? | |
1486 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1487 | else | |
1488 | return which_alternative ? | |
1489 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1490 | } | |
1491 | [(set_attr "op_type" "RIE") | |
1492 | (set_attr "type" "branch") | |
e3cba5e5 | 1493 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1494 | (set (attr "length") |
1495 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1496 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1497 | ; 10 byte for clgr/jg | |
1498 | ||
b0f86a7e AK |
1499 | ; And now the same two patterns as above but with a negated CC mask. |
1500 | ||
1501 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1502 | ; The following instructions do a complementary access of their second | |
1503 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1504 | (define_insn "*icmp_and_br_signed_<mode>" | |
1505 | [(set (pc) | |
1506 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1507 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1508 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1509 | (pc) | |
1510 | (label_ref (match_operand 3 "" "")))) | |
1511 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1512 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1513 | { |
1514 | if (get_attr_length (insn) == 6) | |
1515 | return which_alternative ? | |
1516 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1517 | else | |
1518 | return which_alternative ? | |
1519 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1520 | } | |
1521 | [(set_attr "op_type" "RIE") | |
1522 | (set_attr "type" "branch") | |
1523 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1524 | (set (attr "length") | |
1525 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1526 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1527 | ; 10 byte for cgr/jg | |
1528 | ||
1529 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1530 | ; The following instructions do a complementary access of their second | |
1531 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1532 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1533 | [(set (pc) | |
1534 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1535 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1536 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1537 | (pc) | |
1538 | (label_ref (match_operand 3 "" "")))) | |
1539 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1540 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1541 | { |
1542 | if (get_attr_length (insn) == 6) | |
1543 | return which_alternative ? | |
1544 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1545 | else | |
1546 | return which_alternative ? | |
1547 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1548 | } | |
1549 | [(set_attr "op_type" "RIE") | |
1550 | (set_attr "type" "branch") | |
1551 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1552 | (set (attr "length") | |
1553 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1554 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1555 | ; 10 byte for clgr/jg | |
1556 | ||
9db1d521 HP |
1557 | ;; |
1558 | ;;- Move instructions. | |
1559 | ;; | |
1560 | ||
1561 | ; | |
1562 | ; movti instruction pattern(s). | |
1563 | ; | |
1564 | ||
3cb9ee2f AK |
1565 | |
1566 | ; Separate out the register pair alternative since constraints (P) are | |
1567 | ; not able to deal with const_wide_int's. But predicates do. | |
1568 | (define_insn "*movti_bigconst" | |
1569 | [(set (match_operand:TI 0 "register_operand" "=d") | |
1570 | (match_operand:TI 1 "reload_const_wide_int_operand" ""))] | |
1571 | "TARGET_ZARCH" | |
1572 | "#") | |
1573 | ||
085261c8 AK |
1574 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1575 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1576 | (define_insn "movti" |
9f3c21d6 AK |
1577 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R,d, d, d, d, d,o") |
1578 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))] | |
9602b6a1 | 1579 | "TARGET_ZARCH" |
4023fb28 | 1580 | "@ |
fc0ea003 UW |
1581 | lmg\t%0,%N0,%S1 |
1582 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1583 | vlr\t%v0,%v1 |
1584 | vzero\t%v0 | |
1585 | vone\t%v0 | |
1586 | vlvgp\t%v0,%1,%N1 | |
1587 | # | |
b8923037 AK |
1588 | vl\t%v0,%1%A1 |
1589 | vst\t%v1,%0%A0 | |
4023fb28 | 1590 | # |
9f3c21d6 AK |
1591 | # |
1592 | # | |
1593 | # | |
1594 | # | |
19b63d8e | 1595 | #" |
9f3c21d6 AK |
1596 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*,*,*,*,*") |
1597 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*,*,*,*,*") | |
1598 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*,*,extimm,*,*")]) | |
4023fb28 UW |
1599 | |
1600 | (define_split | |
1601 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1602 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1603 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1604 | && !s_operand (operands[0], TImode) |
1605 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1606 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1607 | [(set (match_dup 2) (match_dup 4)) |
1608 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1609 | { |
dc65c307 UW |
1610 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1611 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1612 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1613 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1614 | }) | |
1615 | ||
1616 | (define_split | |
1617 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1618 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1619 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1620 | && !s_operand (operands[0], TImode) |
1621 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1622 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1623 | [(set (match_dup 2) (match_dup 4)) | |
1624 | (set (match_dup 3) (match_dup 5))] | |
1625 | { | |
1626 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1627 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1628 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1629 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1630 | }) | |
4023fb28 | 1631 | |
085261c8 AK |
1632 | ; Use part of the TImode target reg to perform the address |
1633 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1634 | ; this splitter is not necessary. | |
4023fb28 UW |
1635 | (define_split |
1636 | [(set (match_operand:TI 0 "register_operand" "") | |
1637 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1638 | "TARGET_ZARCH && reload_completed |
085261c8 | 1639 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1640 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1641 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1642 | { |
1643 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1644 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1645 | s390_load_address (addr, XEXP (operands[1], 0)); |
1646 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1647 | }) |
1648 | ||
833cd70a | 1649 | |
085261c8 AK |
1650 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1651 | ; For the higher order bits we do simply a DImode move while the | |
1652 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1653 | (define_split | |
1654 | [(set (match_operand:TI 0 "register_operand" "") | |
1655 | (match_operand:TI 1 "register_operand" ""))] | |
1656 | "TARGET_VX && reload_completed | |
1657 | && GENERAL_REG_P (operands[0]) | |
1658 | && VECTOR_REG_P (operands[1])" | |
1659 | [(set (match_dup 2) (match_dup 4)) | |
1660 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1661 | UNSPEC_VEC_EXTRACT))] | |
1662 | { | |
1663 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1664 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1665 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1666 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1667 | }) | |
1668 | ||
833cd70a AK |
1669 | ; |
1670 | ; Patterns used for secondary reloads | |
1671 | ; | |
1672 | ||
963fc8d0 AK |
1673 | ; z10 provides move instructions accepting larl memory operands. |
1674 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1675 | ; These patterns are also used for unaligned SI and DI accesses. | |
1676 | ||
085261c8 AK |
1677 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1678 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1679 | (match_operand:ALL 1 "register_operand" "=d") | |
1680 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1681 | "TARGET_Z10" |
1682 | { | |
1683 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1684 | DONE; | |
1685 | }) | |
1686 | ||
085261c8 AK |
1687 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1688 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1689 | (match_operand:ALL 1 "memory_operand" "") | |
1690 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1691 | "TARGET_Z10" |
1692 | { | |
1693 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1694 | DONE; | |
1695 | }) | |
1696 | ||
1697 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1698 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1699 | (match_operand:P 1 "larl_operand" "") | |
1700 | (match_operand:P 2 "register_operand" "=a")])] | |
1701 | "TARGET_Z10" | |
1702 | { | |
1703 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1704 | DONE; | |
1705 | }) | |
1706 | ||
833cd70a AK |
1707 | ; Handles loading a PLUS (load address) expression |
1708 | ||
1709 | (define_expand "reload<mode>_plus" | |
1710 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1711 | (match_operand:P 1 "s390_plus_operand" "") | |
1712 | (match_operand:P 2 "register_operand" "=&a")])] | |
1713 | "" | |
1714 | { | |
1715 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1716 | DONE; | |
1717 | }) | |
1718 | ||
085261c8 AK |
1719 | ; Not all the indirect memory access instructions support the full |
1720 | ; format (long disp + index + base). So whenever a move from/to such | |
1721 | ; an address is required and the instruction cannot deal with it we do | |
1722 | ; a load address into a scratch register first and use this as the new | |
1723 | ; base register. | |
1724 | ; This in particular is used for: | |
1725 | ; - non-offsetable memory accesses for multiword moves | |
1726 | ; - full vector reg moves with long displacements | |
833cd70a | 1727 | |
085261c8 | 1728 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1729 | [(parallel [(match_operand 0 "register_operand" "") |
1730 | (match_operand 1 "" "") | |
1731 | (match_operand:P 2 "register_operand" "=&a")])] | |
1732 | "" | |
1733 | { | |
1734 | gcc_assert (MEM_P (operands[1])); | |
1735 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1736 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1737 | emit_move_insn (operands[0], operands[1]); | |
1738 | DONE; | |
1739 | }) | |
1740 | ||
085261c8 | 1741 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1742 | [(parallel [(match_operand 0 "" "") |
1743 | (match_operand 1 "register_operand" "") | |
1744 | (match_operand:P 2 "register_operand" "=&a")])] | |
1745 | "" | |
dc65c307 | 1746 | { |
9c3c3dcc | 1747 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1748 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1749 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1750 | emit_move_insn (operands[0], operands[1]); | |
1751 | DONE; | |
1752 | }) | |
9db1d521 | 1753 | |
1f9e1fc6 AK |
1754 | (define_expand "reload<mode>_PIC_addr" |
1755 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1756 | (match_operand 1 "larl_operand" "") | |
1757 | (match_operand:P 2 "register_operand" "=a")])] | |
1758 | "" | |
1759 | { | |
0a2aaacc KG |
1760 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1761 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1762 | }) |
1763 | ||
9db1d521 HP |
1764 | ; |
1765 | ; movdi instruction pattern(s). | |
1766 | ; | |
1767 | ||
9db1d521 HP |
1768 | (define_expand "movdi" |
1769 | [(set (match_operand:DI 0 "general_operand" "") | |
1770 | (match_operand:DI 1 "general_operand" ""))] | |
1771 | "" | |
9db1d521 | 1772 | { |
fd3cd001 | 1773 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1774 | if (TARGET_64BIT |
1775 | && (SYMBOLIC_CONST (operands[1]) | |
1776 | || (GET_CODE (operands[1]) == PLUS | |
1777 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1778 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1779 | emit_symbolic_move (operands); |
10bbf137 | 1780 | }) |
9db1d521 | 1781 | |
3af8e996 | 1782 | (define_insn "*movdi_64" |
85dae55a | 1783 | [(set (match_operand:DI 0 "nonimmediate_operand" |
b6f51755 | 1784 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d") |
85dae55a | 1785 | (match_operand:DI 1 "general_operand" |
b6f51755 | 1786 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))] |
9602b6a1 | 1787 | "TARGET_ZARCH" |
85dae55a AK |
1788 | "@ |
1789 | lghi\t%0,%h1 | |
1790 | llihh\t%0,%i1 | |
1791 | llihl\t%0,%i1 | |
1792 | llilh\t%0,%i1 | |
1793 | llill\t%0,%i1 | |
1794 | lgfi\t%0,%1 | |
1795 | llihf\t%0,%k1 | |
1796 | llilf\t%0,%k1 | |
1797 | ldgr\t%0,%1 | |
1798 | lgdr\t%0,%1 | |
1799 | lay\t%0,%a1 | |
963fc8d0 | 1800 | lgrl\t%0,%1 |
85dae55a AK |
1801 | lgr\t%0,%1 |
1802 | lg\t%0,%1 | |
1803 | stg\t%1,%0 | |
1804 | ldr\t%0,%1 | |
1805 | ld\t%0,%1 | |
1806 | ldy\t%0,%1 | |
1807 | std\t%1,%0 | |
1808 | stdy\t%1,%0 | |
963fc8d0 AK |
1809 | stgrl\t%1,%0 |
1810 | mvghi\t%0,%1 | |
85dae55a AK |
1811 | # |
1812 | # | |
1813 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1814 | lam\t%0,%N0,%S1 |
1815 | vleig\t%v0,%h1,0 | |
1816 | vlr\t%v0,%v1 | |
1817 | vlvgg\t%v0,%1,0 | |
1818 | vlgvg\t%0,%v1,0 | |
1819 | vleg\t%v0,%1,0 | |
b6f51755 IL |
1820 | vsteg\t%v1,%0,0 |
1821 | larl\t%0,%1" | |
963fc8d0 | 1822 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
b6f51755 IL |
1823 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS, |
1824 | VRX,VRX,RIL") | |
963fc8d0 | 1825 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 | 1826 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
b6f51755 | 1827 | *,*,*,*,*,*,*,larl") |
3af8e996 | 1828 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1829 | z10,*,*,*,*,*,longdisp,*,longdisp, |
b6f51755 | 1830 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx,*") |
9381e3f1 WG |
1831 | (set_attr "z10prop" "z10_fwd_A1, |
1832 | z10_fwd_E1, | |
1833 | z10_fwd_E1, | |
1834 | z10_fwd_E1, | |
1835 | z10_fwd_E1, | |
1836 | z10_fwd_A1, | |
1837 | z10_fwd_E1, | |
1838 | z10_fwd_E1, | |
1839 | *, | |
1840 | *, | |
1841 | z10_fwd_A1, | |
1842 | z10_fwd_A3, | |
1843 | z10_fr_E1, | |
1844 | z10_fwd_A3, | |
1845 | z10_rec, | |
1846 | *, | |
1847 | *, | |
1848 | *, | |
1849 | *, | |
1850 | *, | |
1851 | z10_rec, | |
1852 | z10_super, | |
1853 | *, | |
1854 | *, | |
1855 | *, | |
b6f51755 IL |
1856 | *,*,*,*,*,*,*, |
1857 | z10_super_A1") | |
14cfceb7 IL |
1858 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*, |
1859 | *,yes,*,*,*,*,*,*,*,*, | |
1860 | yes,*,*,*,*,*,*,*,*,*, | |
1861 | *,*,yes") | |
9381e3f1 | 1862 | ]) |
c5aa1d12 | 1863 | |
8f4f98f6 IL |
1864 | ; Splitters for loading TLS pointer from UNSPEC_GET_TP. |
1865 | ; UNSPEC_GET_TP is used instead of %a0:P, since the latter is a hard register, | |
1866 | ; and those are not handled by Partial Redundancy Elimination (gcse.c), which | |
1867 | ; results in generation of redundant thread pointer loads. | |
0d552c1b | 1868 | |
8f4f98f6 IL |
1869 | (define_insn_and_split "*get_tp_31" |
1870 | [(set (match_operand:SI 0 "register_operand" "=r") | |
1871 | (unspec:SI [(match_operand:SI 1 "register_operand" "t")] | |
1872 | UNSPEC_GET_TP))] | |
1873 | "" | |
1874 | "#" | |
1875 | "&& reload_completed" | |
1876 | [(set (match_dup 0) (match_dup 1))]) | |
1877 | ||
1878 | (define_insn_and_split "*get_tp_64" | |
1879 | [(set (match_operand:DI 0 "register_operand" "=r") | |
1880 | (unspec:DI [(match_operand:DI 1 "register_operand" "t")] | |
1881 | UNSPEC_GET_TP))] | |
1882 | "TARGET_ZARCH" | |
1883 | "#" | |
1884 | "&& reload_completed" | |
c5aa1d12 UW |
1885 | [(set (match_dup 2) (match_dup 3)) |
1886 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1887 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1888 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1889 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1890 | ||
8f4f98f6 IL |
1891 | ; Splitters for storing TLS pointer to %a0:DI. |
1892 | ||
c5aa1d12 UW |
1893 | (define_split |
1894 | [(set (match_operand:DI 0 "register_operand" "") | |
1895 | (match_operand:DI 1 "register_operand" ""))] | |
0d552c1b | 1896 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) && reload_completed |
c5aa1d12 UW |
1897 | && dead_or_set_p (insn, operands[1])" |
1898 | [(set (match_dup 3) (match_dup 2)) | |
1899 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1900 | (set (match_dup 4) (match_dup 2))] | |
1901 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1902 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1903 | ||
1904 | (define_split | |
1905 | [(set (match_operand:DI 0 "register_operand" "") | |
1906 | (match_operand:DI 1 "register_operand" ""))] | |
0d552c1b | 1907 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) && reload_completed |
c5aa1d12 UW |
1908 | && !dead_or_set_p (insn, operands[1])" |
1909 | [(set (match_dup 3) (match_dup 2)) | |
1910 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1911 | (set (match_dup 4) (match_dup 2)) | |
1912 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1913 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1914 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1915 | |
1916 | (define_insn "*movdi_31" | |
963fc8d0 | 1917 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1918 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1919 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1920 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1921 | "!TARGET_ZARCH" |
4023fb28 | 1922 | "@ |
fc0ea003 | 1923 | lm\t%0,%N0,%S1 |
c4d50129 | 1924 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1925 | stm\t%1,%N1,%S0 |
c4d50129 | 1926 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1927 | # |
1928 | # | |
d40c829f UW |
1929 | ldr\t%0,%1 |
1930 | ld\t%0,%1 | |
1931 | ldy\t%0,%1 | |
1932 | std\t%1,%0 | |
1933 | stdy\t%1,%0 | |
19b63d8e | 1934 | #" |
f2dc2f86 AK |
1935 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1936 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1937 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1938 | |
1939 | ; For a load from a symbol ref we can use one of the target registers | |
1940 | ; together with larl to load the address. | |
1941 | (define_split | |
1942 | [(set (match_operand:DI 0 "register_operand" "") | |
1943 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1944 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1945 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1946 | [(set (match_dup 2) (match_dup 3)) | |
1947 | (set (match_dup 0) (match_dup 1))] | |
1948 | { | |
1949 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1950 | operands[3] = XEXP (operands[1], 0); | |
1951 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1952 | }) | |
4023fb28 UW |
1953 | |
1954 | (define_split | |
1955 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1956 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1957 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1958 | && !s_operand (operands[0], DImode) |
1959 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1960 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1961 | [(set (match_dup 2) (match_dup 4)) |
1962 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1963 | { |
dc65c307 UW |
1964 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1965 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1966 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1967 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1968 | }) | |
1969 | ||
1970 | (define_split | |
1971 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1972 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1973 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1974 | && !s_operand (operands[0], DImode) |
1975 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1976 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1977 | [(set (match_dup 2) (match_dup 4)) | |
1978 | (set (match_dup 3) (match_dup 5))] | |
1979 | { | |
1980 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1981 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1982 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1983 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1984 | }) | |
9db1d521 | 1985 | |
4023fb28 UW |
1986 | (define_split |
1987 | [(set (match_operand:DI 0 "register_operand" "") | |
1988 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1989 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1990 | && !FP_REG_P (operands[0]) |
4023fb28 | 1991 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1992 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1993 | { |
1994 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1995 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1996 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1997 | }) |
1998 | ||
84817c5d UW |
1999 | (define_peephole2 |
2000 | [(set (match_operand:DI 0 "register_operand" "") | |
2001 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 2002 | "TARGET_ZARCH |
84817c5d UW |
2003 | && !FP_REG_P (operands[0]) |
2004 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2005 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2006 | && get_pool_mode (operands[1]) == DImode | |
2007 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2008 | [(set (match_dup 0) (match_dup 2))] | |
2009 | "operands[2] = get_pool_constant (operands[1]);") | |
2010 | ||
7bdff56f UW |
2011 | (define_insn "*la_64" |
2012 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 2013 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2014 | "TARGET_64BIT" |
2015 | "@ | |
2016 | la\t%0,%a1 | |
2017 | lay\t%0,%a1" | |
2018 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2019 | (set_attr "type" "la") |
3e4be43f | 2020 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2021 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2022 | |
2023 | (define_peephole2 | |
2024 | [(parallel | |
2025 | [(set (match_operand:DI 0 "register_operand" "") | |
2026 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2027 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2028 | "TARGET_64BIT |
e1d5ee28 | 2029 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2030 | [(set (match_dup 0) (match_dup 1))] |
2031 | "") | |
2032 | ||
2033 | (define_peephole2 | |
2034 | [(set (match_operand:DI 0 "register_operand" "") | |
2035 | (match_operand:DI 1 "register_operand" "")) | |
2036 | (parallel | |
2037 | [(set (match_dup 0) | |
2038 | (plus:DI (match_dup 0) | |
2039 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2040 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2041 | "TARGET_64BIT |
2042 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2043 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2044 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
2045 | "") | |
2046 | ||
9db1d521 HP |
2047 | ; |
2048 | ; movsi instruction pattern(s). | |
2049 | ; | |
2050 | ||
9db1d521 HP |
2051 | (define_expand "movsi" |
2052 | [(set (match_operand:SI 0 "general_operand" "") | |
2053 | (match_operand:SI 1 "general_operand" ""))] | |
2054 | "" | |
9db1d521 | 2055 | { |
fd3cd001 | 2056 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
2057 | if (!TARGET_64BIT |
2058 | && (SYMBOLIC_CONST (operands[1]) | |
2059 | || (GET_CODE (operands[1]) == PLUS | |
2060 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
2061 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 2062 | emit_symbolic_move (operands); |
10bbf137 | 2063 | }) |
9db1d521 | 2064 | |
9e8327e3 UW |
2065 | (define_insn "*movsi_larl" |
2066 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2067 | (match_operand:SI 1 "larl_operand" "X"))] | |
8cc6307c | 2068 | "!TARGET_64BIT |
9e8327e3 UW |
2069 | && !FP_REG_P (operands[0])" |
2070 | "larl\t%0,%1" | |
2071 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 2072 | (set_attr "type" "larl") |
14cfceb7 IL |
2073 | (set_attr "z10prop" "z10_fwd_A1") |
2074 | (set_attr "relative_long" "yes")]) | |
9e8327e3 | 2075 | |
f19a9af7 | 2076 | (define_insn "*movsi_zarch" |
2f7e5a0d | 2077 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 2078 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 2079 | (match_operand:SI 1 "general_operand" |
3e4be43f | 2080 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 2081 | "TARGET_ZARCH" |
9db1d521 | 2082 | "@ |
f19a9af7 AK |
2083 | lhi\t%0,%h1 |
2084 | llilh\t%0,%i1 | |
2085 | llill\t%0,%i1 | |
ec24698e | 2086 | iilf\t%0,%o1 |
f19a9af7 | 2087 | lay\t%0,%a1 |
963fc8d0 | 2088 | lrl\t%0,%1 |
d40c829f UW |
2089 | lr\t%0,%1 |
2090 | l\t%0,%1 | |
2091 | ly\t%0,%1 | |
2092 | st\t%1,%0 | |
2093 | sty\t%1,%0 | |
ae1c6198 | 2094 | ldr\t%0,%1 |
d40c829f | 2095 | ler\t%0,%1 |
085261c8 | 2096 | lde\t%0,%1 |
d40c829f UW |
2097 | le\t%0,%1 |
2098 | ley\t%0,%1 | |
2099 | ste\t%1,%0 | |
2100 | stey\t%1,%0 | |
c5aa1d12 UW |
2101 | ear\t%0,%1 |
2102 | sar\t%0,%1 | |
2103 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
2104 | strl\t%1,%0 |
2105 | mvhi\t%0,%1 | |
085261c8 AK |
2106 | lam\t%0,%0,%S1 |
2107 | vleif\t%v0,%h1,0 | |
2108 | vlr\t%v0,%v1 | |
2109 | vlvgf\t%v0,%1,0 | |
2110 | vlgvf\t%0,%v1,0 | |
2111 | vlef\t%v0,%1,0 | |
2112 | vstef\t%v1,%0,0" | |
963fc8d0 | 2113 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 2114 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
2115 | (set_attr "type" "*, |
2116 | *, | |
2117 | *, | |
2118 | *, | |
2119 | la, | |
2120 | larl, | |
2121 | lr, | |
2122 | load, | |
2123 | load, | |
2124 | store, | |
2125 | store, | |
2126 | floadsf, | |
2127 | floadsf, | |
2128 | floadsf, | |
085261c8 AK |
2129 | floadsf, |
2130 | floadsf, | |
9381e3f1 WG |
2131 | fstoresf, |
2132 | fstoresf, | |
2133 | *, | |
2134 | *, | |
2135 | *, | |
2136 | larl, | |
2137 | *, | |
085261c8 | 2138 | *,*,*,*,*,*,*") |
963fc8d0 | 2139 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2140 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2141 | (set_attr "z10prop" "z10_fwd_A1, |
2142 | z10_fwd_E1, | |
2143 | z10_fwd_E1, | |
2144 | z10_fwd_A1, | |
2145 | z10_fwd_A1, | |
2146 | z10_fwd_A3, | |
2147 | z10_fr_E1, | |
2148 | z10_fwd_A3, | |
2149 | z10_fwd_A3, | |
729e750f | 2150 | z10_rec, |
9381e3f1 WG |
2151 | z10_rec, |
2152 | *, | |
2153 | *, | |
2154 | *, | |
2155 | *, | |
2156 | *, | |
085261c8 AK |
2157 | *, |
2158 | *, | |
9381e3f1 WG |
2159 | z10_super_E1, |
2160 | z10_super, | |
2161 | *, | |
2162 | z10_rec, | |
2163 | z10_super, | |
14cfceb7 IL |
2164 | *,*,*,*,*,*,*") |
2165 | (set_attr "relative_long" "*,*,*,*,*,yes,*,*,*,*, | |
2166 | *,*,*,*,*,*,*,*,*,*, | |
2167 | *,yes,*,*,*,*,*,*,*,*")]) | |
f19a9af7 AK |
2168 | |
2169 | (define_insn "*movsi_esa" | |
085261c8 AK |
2170 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2171 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2172 | "!TARGET_ZARCH" |
2173 | "@ | |
2174 | lhi\t%0,%h1 | |
2175 | lr\t%0,%1 | |
2176 | l\t%0,%1 | |
2177 | st\t%1,%0 | |
ae1c6198 | 2178 | ldr\t%0,%1 |
f19a9af7 | 2179 | ler\t%0,%1 |
085261c8 | 2180 | lde\t%0,%1 |
f19a9af7 AK |
2181 | le\t%0,%1 |
2182 | ste\t%1,%0 | |
c5aa1d12 UW |
2183 | ear\t%0,%1 |
2184 | sar\t%0,%1 | |
2185 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2186 | lam\t%0,%0,%S1" |
ae1c6198 | 2187 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2188 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2189 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2190 | z10_super,*,*") | |
285363a1 | 2191 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2192 | ]) |
9db1d521 | 2193 | |
84817c5d UW |
2194 | (define_peephole2 |
2195 | [(set (match_operand:SI 0 "register_operand" "") | |
2196 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2197 | "!FP_REG_P (operands[0]) | |
2198 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2199 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2200 | && get_pool_mode (operands[1]) == SImode | |
2201 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2202 | [(set (match_dup 0) (match_dup 2))] | |
2203 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2204 | |
7bdff56f UW |
2205 | (define_insn "*la_31" |
2206 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2207 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2208 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2209 | "@ | |
2210 | la\t%0,%a1 | |
2211 | lay\t%0,%a1" | |
2212 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2213 | (set_attr "type" "la") |
3e4be43f | 2214 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2215 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2216 | |
2217 | (define_peephole2 | |
2218 | [(parallel | |
2219 | [(set (match_operand:SI 0 "register_operand" "") | |
2220 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2221 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2222 | "!TARGET_64BIT |
e1d5ee28 | 2223 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2224 | [(set (match_dup 0) (match_dup 1))] |
2225 | "") | |
2226 | ||
2227 | (define_peephole2 | |
2228 | [(set (match_operand:SI 0 "register_operand" "") | |
2229 | (match_operand:SI 1 "register_operand" "")) | |
2230 | (parallel | |
2231 | [(set (match_dup 0) | |
2232 | (plus:SI (match_dup 0) | |
2233 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2234 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2235 | "!TARGET_64BIT |
2236 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2237 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2238 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2239 | "") | |
2240 | ||
2241 | (define_insn "*la_31_and" | |
2242 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2243 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2244 | (const_int 2147483647)))] |
2245 | "!TARGET_64BIT" | |
2246 | "@ | |
2247 | la\t%0,%a1 | |
2248 | lay\t%0,%a1" | |
2249 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2250 | (set_attr "type" "la") |
3e4be43f | 2251 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2252 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2253 | |
2254 | (define_insn_and_split "*la_31_and_cc" | |
2255 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2256 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2257 | (const_int 2147483647))) | |
ae156f85 | 2258 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2259 | "!TARGET_64BIT" |
2260 | "#" | |
2261 | "&& reload_completed" | |
2262 | [(set (match_dup 0) | |
2263 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2264 | "" | |
2265 | [(set_attr "op_type" "RX") | |
2266 | (set_attr "type" "la")]) | |
2267 | ||
2268 | (define_insn "force_la_31" | |
2269 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2270 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2271 | (use (const_int 0))] |
2272 | "!TARGET_64BIT" | |
2273 | "@ | |
2274 | la\t%0,%a1 | |
2275 | lay\t%0,%a1" | |
2276 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2277 | (set_attr "type" "la") |
3e4be43f | 2278 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2279 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2280 | |
9db1d521 HP |
2281 | ; |
2282 | ; movhi instruction pattern(s). | |
2283 | ; | |
2284 | ||
02ed3c5e UW |
2285 | (define_expand "movhi" |
2286 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2287 | (match_operand:HI 1 "general_operand" ""))] | |
2288 | "" | |
2289 | { | |
2f7e5a0d | 2290 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2291 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2292 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2293 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2294 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2295 | { |
2296 | rtx tmp = gen_reg_rtx (SImode); | |
2297 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2298 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2299 | operands[1] = gen_lowpart (HImode, tmp); |
2300 | } | |
2301 | }) | |
2302 | ||
2303 | (define_insn "*movhi" | |
3e4be43f UW |
2304 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2305 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2306 | "" |
2307 | "@ | |
d40c829f UW |
2308 | lr\t%0,%1 |
2309 | lhi\t%0,%h1 | |
2310 | lh\t%0,%1 | |
2311 | lhy\t%0,%1 | |
963fc8d0 | 2312 | lhrl\t%0,%1 |
d40c829f UW |
2313 | sth\t%1,%0 |
2314 | sthy\t%1,%0 | |
963fc8d0 | 2315 | sthrl\t%1,%0 |
085261c8 AK |
2316 | mvhhi\t%0,%1 |
2317 | vleih\t%v0,%h1,0 | |
2318 | vlr\t%v0,%v1 | |
2319 | vlvgh\t%v0,%1,0 | |
2320 | vlgvh\t%0,%v1,0 | |
2321 | vleh\t%v0,%1,0 | |
2322 | vsteh\t%v1,%0,0" | |
2323 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2324 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2325 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2326 | (set_attr "z10prop" "z10_fr_E1, |
2327 | z10_fwd_A1, | |
2328 | z10_super_E1, | |
2329 | z10_super_E1, | |
2330 | z10_super_E1, | |
729e750f | 2331 | z10_rec, |
9381e3f1 WG |
2332 | z10_rec, |
2333 | z10_rec, | |
14cfceb7 IL |
2334 | z10_super,*,*,*,*,*,*") |
2335 | (set_attr "relative_long" "*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*")]) | |
9db1d521 | 2336 | |
84817c5d UW |
2337 | (define_peephole2 |
2338 | [(set (match_operand:HI 0 "register_operand" "") | |
2339 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2340 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2341 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2342 | && get_pool_mode (operands[1]) == HImode | |
2343 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2344 | [(set (match_dup 0) (match_dup 2))] | |
2345 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2346 | |
9db1d521 HP |
2347 | ; |
2348 | ; movqi instruction pattern(s). | |
2349 | ; | |
2350 | ||
02ed3c5e UW |
2351 | (define_expand "movqi" |
2352 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2353 | (match_operand:QI 1 "general_operand" ""))] | |
2354 | "" | |
2355 | { | |
c19ec8f9 | 2356 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2357 | is just as fast as a QImode load. */ |
b3a13419 | 2358 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2359 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2360 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2361 | { |
9602b6a1 AK |
2362 | rtx tmp = gen_reg_rtx (DImode); |
2363 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2364 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2365 | operands[1] = gen_lowpart (QImode, tmp); |
2366 | } | |
2367 | }) | |
4023fb28 | 2368 | |
02ed3c5e | 2369 | (define_insn "*movqi" |
3e4be43f UW |
2370 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2371 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2372 | "" |
2373 | "@ | |
d40c829f UW |
2374 | lr\t%0,%1 |
2375 | lhi\t%0,%b1 | |
2376 | ic\t%0,%1 | |
2377 | icy\t%0,%1 | |
2378 | stc\t%1,%0 | |
2379 | stcy\t%1,%0 | |
fc0ea003 | 2380 | mvi\t%S0,%b1 |
0a88561f | 2381 | mviy\t%S0,%b1 |
085261c8 AK |
2382 | # |
2383 | vleib\t%v0,%b1,0 | |
2384 | vlr\t%v0,%v1 | |
2385 | vlvgb\t%v0,%1,0 | |
2386 | vlgvb\t%0,%v1,0 | |
2387 | vleb\t%v0,%1,0 | |
2388 | vsteb\t%v1,%0,0" | |
2389 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2390 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2391 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2392 | (set_attr "z10prop" "z10_fr_E1, |
2393 | z10_fwd_A1, | |
2394 | z10_super_E1, | |
2395 | z10_super_E1, | |
729e750f | 2396 | z10_rec, |
9381e3f1 WG |
2397 | z10_rec, |
2398 | z10_super, | |
0a88561f | 2399 | z10_super, |
085261c8 | 2400 | *,*,*,*,*,*,*")]) |
9db1d521 | 2401 | |
84817c5d UW |
2402 | (define_peephole2 |
2403 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2404 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2405 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2406 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2407 | && get_pool_mode (operands[1]) == QImode | |
2408 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2409 | [(set (match_dup 0) (match_dup 2))] | |
2410 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2411 | |
9db1d521 | 2412 | ; |
05b9aaaa | 2413 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2414 | ; |
2415 | ||
2416 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2417 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2418 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2419 | "" |
d3632d41 | 2420 | "@ |
d40c829f UW |
2421 | ic\t%0,%1 |
2422 | icy\t%0,%1" | |
9381e3f1 | 2423 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2424 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2425 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2426 | |
2427 | ; | |
2428 | ; movstricthi instruction pattern(s). | |
2429 | ; | |
2430 | ||
2431 | (define_insn "*movstricthi" | |
d3632d41 | 2432 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2433 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2434 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2435 | "" |
d3632d41 | 2436 | "@ |
fc0ea003 UW |
2437 | icm\t%0,3,%S1 |
2438 | icmy\t%0,3,%S1" | |
9381e3f1 | 2439 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2440 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2441 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2442 | |
2443 | ; | |
2444 | ; movstrictsi instruction pattern(s). | |
2445 | ; | |
2446 | ||
05b9aaaa | 2447 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2448 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2449 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2450 | "TARGET_ZARCH" |
9db1d521 | 2451 | "@ |
d40c829f UW |
2452 | lr\t%0,%1 |
2453 | l\t%0,%1 | |
c5aa1d12 UW |
2454 | ly\t%0,%1 |
2455 | ear\t%0,%1" | |
2456 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2457 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2458 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2459 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2460 | |
f61a2c7d | 2461 | ; |
609e7e80 | 2462 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2463 | ; |
2464 | ||
609e7e80 AK |
2465 | (define_expand "mov<mode>" |
2466 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2467 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2468 | "" |
2469 | "") | |
2470 | ||
609e7e80 | 2471 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2472 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2473 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2474 | "TARGET_ZARCH" |
f61a2c7d | 2475 | "@ |
65b1d8ea | 2476 | lzxr\t%0 |
f61a2c7d AK |
2477 | lxr\t%0,%1 |
2478 | # | |
2479 | # | |
2480 | lmg\t%0,%N0,%S1 | |
2481 | stmg\t%1,%N1,%S0 | |
2482 | # | |
f61a2c7d | 2483 | #" |
65b1d8ea AK |
2484 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2485 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2486 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2487 | |
609e7e80 | 2488 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2489 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2490 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2491 | "!TARGET_ZARCH" |
f61a2c7d | 2492 | "@ |
65b1d8ea | 2493 | lzxr\t%0 |
f61a2c7d AK |
2494 | lxr\t%0,%1 |
2495 | # | |
f61a2c7d | 2496 | #" |
65b1d8ea AK |
2497 | [(set_attr "op_type" "RRE,RRE,*,*") |
2498 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2499 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2500 | |
2501 | ; TFmode in GPRs splitters | |
2502 | ||
2503 | (define_split | |
609e7e80 AK |
2504 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2505 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2506 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2507 | && !s_operand (operands[0], <MODE>mode) |
2508 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2509 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2510 | [(set (match_dup 2) (match_dup 4)) |
2511 | (set (match_dup 3) (match_dup 5))] | |
2512 | { | |
609e7e80 AK |
2513 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2514 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2515 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2516 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2517 | }) |
2518 | ||
2519 | (define_split | |
609e7e80 AK |
2520 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2521 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2522 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2523 | && !s_operand (operands[0], <MODE>mode) |
2524 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2525 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2526 | [(set (match_dup 2) (match_dup 4)) |
2527 | (set (match_dup 3) (match_dup 5))] | |
2528 | { | |
609e7e80 AK |
2529 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2530 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2531 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2532 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2533 | }) |
2534 | ||
2535 | (define_split | |
609e7e80 AK |
2536 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2537 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2538 | "TARGET_ZARCH && reload_completed |
085261c8 | 2539 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2540 | && !s_operand (operands[1], VOIDmode)" |
2541 | [(set (match_dup 0) (match_dup 1))] | |
2542 | { | |
609e7e80 | 2543 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2544 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2545 | s390_load_address (addr, XEXP (operands[1], 0)); |
2546 | operands[1] = replace_equiv_address (operands[1], addr); | |
2547 | }) | |
2548 | ||
7b6baae1 | 2549 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2550 | |
2551 | (define_split | |
609e7e80 AK |
2552 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2553 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2554 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2555 | && FP_REG_P (operands[0])" |
2556 | [(set (match_dup 2) (match_dup 4)) | |
2557 | (set (match_dup 3) (match_dup 5))] | |
2558 | { | |
609e7e80 AK |
2559 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2560 | <MODE>mode, 0); | |
2561 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2562 | <MODE>mode, 8); | |
2563 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2564 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2565 | }) |
2566 | ||
2567 | (define_split | |
609e7e80 AK |
2568 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2569 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2570 | "reload_completed && offsettable_memref_p (operands[0]) |
2571 | && FP_REG_P (operands[1])" | |
2572 | [(set (match_dup 2) (match_dup 4)) | |
2573 | (set (match_dup 3) (match_dup 5))] | |
2574 | { | |
609e7e80 AK |
2575 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2576 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2577 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2578 | <MODE>mode, 0); | |
2579 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2580 | <MODE>mode, 8); | |
f61a2c7d AK |
2581 | }) |
2582 | ||
9db1d521 | 2583 | ; |
609e7e80 | 2584 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2585 | ; |
2586 | ||
609e7e80 AK |
2587 | (define_expand "mov<mode>" |
2588 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2589 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2590 | "" |
13c025c1 | 2591 | "") |
9db1d521 | 2592 | |
609e7e80 AK |
2593 | (define_insn "*mov<mode>_64dfp" |
2594 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2595 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2596 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2597 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2598 | "TARGET_DFP" |
85dae55a | 2599 | "@ |
65b1d8ea | 2600 | lzdr\t%0 |
85dae55a AK |
2601 | ldr\t%0,%1 |
2602 | ldgr\t%0,%1 | |
2603 | lgdr\t%0,%1 | |
2604 | ld\t%0,%1 | |
2605 | ldy\t%0,%1 | |
2606 | std\t%1,%0 | |
2607 | stdy\t%1,%0 | |
45e5214c | 2608 | lghi\t%0,0 |
85dae55a | 2609 | lgr\t%0,%1 |
085261c8 | 2610 | lgrl\t%0,%1 |
85dae55a | 2611 | lg\t%0,%1 |
085261c8 AK |
2612 | stgrl\t%1,%0 |
2613 | stg\t%1,%0 | |
2614 | vlr\t%v0,%v1 | |
590961cf | 2615 | vleig\t%v0,0,0 |
085261c8 AK |
2616 | vlvgg\t%v0,%1,0 |
2617 | vlgvg\t%0,%v1,0 | |
2618 | vleg\t%0,%1,0 | |
2619 | vsteg\t%1,%0,0" | |
590961cf | 2620 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2621 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2622 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2623 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2624 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx") |
2625 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,yes,*,*,*,*,*,*,*")]) | |
85dae55a | 2626 | |
609e7e80 | 2627 | (define_insn "*mov<mode>_64" |
590961cf AK |
2628 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2629 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2630 | "TARGET_ZARCH" |
9db1d521 | 2631 | "@ |
65b1d8ea | 2632 | lzdr\t%0 |
d40c829f UW |
2633 | ldr\t%0,%1 |
2634 | ld\t%0,%1 | |
2635 | ldy\t%0,%1 | |
2636 | std\t%1,%0 | |
2637 | stdy\t%1,%0 | |
45e5214c | 2638 | lghi\t%0,0 |
d40c829f | 2639 | lgr\t%0,%1 |
085261c8 | 2640 | lgrl\t%0,%1 |
d40c829f | 2641 | lg\t%0,%1 |
085261c8 | 2642 | stgrl\t%1,%0 |
590961cf AK |
2643 | stg\t%1,%0" |
2644 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2645 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2646 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2647 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
14cfceb7 IL |
2648 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*") |
2649 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")]) | |
609e7e80 AK |
2650 | |
2651 | (define_insn "*mov<mode>_31" | |
2652 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2653 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2654 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2655 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2656 | "!TARGET_ZARCH" |
9db1d521 | 2657 | "@ |
65b1d8ea | 2658 | lzdr\t%0 |
d40c829f UW |
2659 | ldr\t%0,%1 |
2660 | ld\t%0,%1 | |
2661 | ldy\t%0,%1 | |
2662 | std\t%1,%0 | |
2663 | stdy\t%1,%0 | |
fc0ea003 | 2664 | lm\t%0,%N0,%S1 |
c4d50129 | 2665 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2666 | stm\t%1,%N1,%S0 |
c4d50129 | 2667 | stmy\t%1,%N1,%S0 |
4023fb28 | 2668 | # |
19b63d8e | 2669 | #" |
65b1d8ea AK |
2670 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2671 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2672 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2673 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2674 | |
2675 | (define_split | |
609e7e80 AK |
2676 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2677 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2678 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2679 | && !s_operand (operands[0], <MODE>mode) |
2680 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2681 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2682 | [(set (match_dup 2) (match_dup 4)) |
2683 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2684 | { |
609e7e80 AK |
2685 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2686 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2687 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2688 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2689 | }) |
2690 | ||
2691 | (define_split | |
609e7e80 AK |
2692 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2693 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2694 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2695 | && !s_operand (operands[0], <MODE>mode) |
2696 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2697 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2698 | [(set (match_dup 2) (match_dup 4)) |
2699 | (set (match_dup 3) (match_dup 5))] | |
2700 | { | |
609e7e80 AK |
2701 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2702 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2703 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2704 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2705 | }) |
9db1d521 | 2706 | |
4023fb28 | 2707 | (define_split |
609e7e80 AK |
2708 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2709 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2710 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2711 | && !FP_REG_P (operands[0]) |
4023fb28 | 2712 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2713 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2714 | { |
609e7e80 | 2715 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2716 | s390_load_address (addr, XEXP (operands[1], 0)); |
2717 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2718 | }) |
2719 | ||
9db1d521 | 2720 | ; |
609e7e80 | 2721 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2722 | ; |
2723 | ||
609e7e80 AK |
2724 | (define_insn "mov<mode>" |
2725 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2726 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2727 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2728 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2729 | "" |
9db1d521 | 2730 | "@ |
65b1d8ea | 2731 | lzer\t%0 |
ae1c6198 | 2732 | ldr\t%0,%1 |
d40c829f | 2733 | ler\t%0,%1 |
085261c8 | 2734 | lde\t%0,%1 |
d40c829f UW |
2735 | le\t%0,%1 |
2736 | ley\t%0,%1 | |
2737 | ste\t%1,%0 | |
2738 | stey\t%1,%0 | |
45e5214c | 2739 | lhi\t%0,0 |
d40c829f | 2740 | lr\t%0,%1 |
085261c8 | 2741 | lrl\t%0,%1 |
d40c829f UW |
2742 | l\t%0,%1 |
2743 | ly\t%0,%1 | |
085261c8 | 2744 | strl\t%1,%0 |
d40c829f | 2745 | st\t%1,%0 |
085261c8 AK |
2746 | sty\t%1,%0 |
2747 | vlr\t%v0,%v1 | |
298f4647 | 2748 | vleif\t%v0,0,0 |
085261c8 AK |
2749 | vlvgf\t%v0,%1,0 |
2750 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2751 | vlef\t%0,%1,0 |
2752 | vstef\t%1,%0,0" | |
ae1c6198 | 2753 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2754 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2755 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2756 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2757 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx") |
2758 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2759 | |
9dc62c00 AK |
2760 | ; |
2761 | ; movcc instruction pattern | |
2762 | ; | |
2763 | ||
2764 | (define_insn "movcc" | |
2765 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2766 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2767 | "" |
2768 | "@ | |
2769 | lr\t%0,%1 | |
2770 | tmh\t%1,12288 | |
2771 | ipm\t%0 | |
a71f0749 DV |
2772 | l\t%0,%1 |
2773 | ly\t%0,%1 | |
2774 | st\t%1,%0 | |
2775 | sty\t%1,%0" | |
8dd3b235 | 2776 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2777 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2778 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2779 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2780 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2781 | |
19b63d8e UW |
2782 | ; |
2783 | ; Block move (MVC) patterns. | |
2784 | ; | |
2785 | ||
2786 | (define_insn "*mvc" | |
2787 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2788 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2789 | (use (match_operand 2 "const_int_operand" "n"))] | |
2790 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2791 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2792 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2793 | |
0a88561f AK |
2794 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2795 | ; order to have it implemented with mvc. | |
2796 | ||
2797 | (define_split | |
2798 | [(set (match_operand:QI 0 "memory_operand" "") | |
2799 | (match_operand:QI 1 "memory_operand" ""))] | |
2800 | "reload_completed" | |
2801 | [(parallel | |
2802 | [(set (match_dup 0) (match_dup 1)) | |
2803 | (use (const_int 1))])] | |
2804 | { | |
2805 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2806 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2807 | }) | |
2808 | ||
2809 | ||
19b63d8e UW |
2810 | (define_peephole2 |
2811 | [(parallel | |
2812 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2813 | (match_operand:BLK 1 "memory_operand" "")) | |
2814 | (use (match_operand 2 "const_int_operand" ""))]) | |
2815 | (parallel | |
2816 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2817 | (match_operand:BLK 4 "memory_operand" "")) | |
2818 | (use (match_operand 5 "const_int_operand" ""))])] | |
f9dcf14a AK |
2819 | "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) |
2820 | || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) | |
2821 | && s390_offset_p (operands[0], operands[3], operands[2]) | |
19b63d8e | 2822 | && s390_offset_p (operands[1], operands[4], operands[2]) |
9381e3f1 | 2823 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2824 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2825 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2826 | [(parallel | |
2827 | [(set (match_dup 6) (match_dup 7)) | |
2828 | (use (match_dup 8))])] | |
2829 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2830 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2831 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2832 | ||
f9dcf14a AK |
2833 | (define_peephole2 |
2834 | [(parallel | |
2835 | [(set (match_operand:BLK 0 "plus16_Q_operand" "") | |
2836 | (match_operand:BLK 1 "plus16_Q_operand" "")) | |
2837 | (use (match_operand 2 "const_int_operand" ""))])] | |
2838 | "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" | |
2839 | [(parallel | |
2840 | [(set (match_dup 0) (match_dup 1)) | |
2841 | (use (const_int 16))]) | |
2842 | (parallel | |
2843 | [(set (match_dup 3) (match_dup 4)) | |
2844 | (use (match_dup 5))])] | |
2845 | "operands[3] = change_address (operands[0], VOIDmode, | |
2846 | plus_constant (Pmode, XEXP (operands[0], 0), 16)); | |
2847 | operands[4] = change_address (operands[1], VOIDmode, | |
2848 | plus_constant (Pmode, XEXP (operands[1], 0), 16)); | |
2849 | operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") | |
2850 | ||
19b63d8e | 2851 | |
9db1d521 HP |
2852 | ; |
2853 | ; load_multiple pattern(s). | |
2854 | ; | |
22ea6b4f UW |
2855 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2856 | ; we currently support load_multiple/store_multiple only after reload. | |
2857 | ; | |
9db1d521 HP |
2858 | |
2859 | (define_expand "load_multiple" | |
2860 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2861 | (match_operand 1 "" "")) | |
2862 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2863 | "reload_completed" |
9db1d521 | 2864 | { |
ef4bddc2 | 2865 | machine_mode mode; |
9db1d521 HP |
2866 | int regno; |
2867 | int count; | |
2868 | rtx from; | |
4023fb28 | 2869 | int i, off; |
9db1d521 HP |
2870 | |
2871 | /* Support only loading a constant number of fixed-point registers from | |
2872 | memory and only bother with this if more than two */ | |
2873 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2874 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2875 | || INTVAL (operands[2]) > 16 |
2876 | || GET_CODE (operands[1]) != MEM | |
2877 | || GET_CODE (operands[0]) != REG | |
2878 | || REGNO (operands[0]) >= 16) | |
2879 | FAIL; | |
2880 | ||
2881 | count = INTVAL (operands[2]); | |
2882 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2883 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2884 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2885 | FAIL; |
9db1d521 HP |
2886 | |
2887 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2888 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2889 | { |
2890 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2891 | { | |
2892 | from = XEXP (operands[1], 0); | |
2893 | off = 0; | |
2894 | } | |
2895 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2896 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2897 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2898 | { | |
2899 | from = XEXP (XEXP (operands[1], 0), 0); | |
2900 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2901 | } | |
2902 | else | |
2903 | FAIL; | |
4023fb28 UW |
2904 | } |
2905 | else | |
2906 | { | |
2907 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2908 | off = 0; | |
2909 | } | |
9db1d521 HP |
2910 | |
2911 | for (i = 0; i < count; i++) | |
2912 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2913 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2914 | change_address (operands[1], mode, |
0a81f074 RS |
2915 | plus_constant (Pmode, from, |
2916 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2917 | }) |
9db1d521 HP |
2918 | |
2919 | (define_insn "*load_multiple_di" | |
2920 | [(match_parallel 0 "load_multiple_operation" | |
2921 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2922 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2923 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2924 | { |
2925 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2926 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2927 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2928 | } |
d3632d41 | 2929 | [(set_attr "op_type" "RSY") |
4023fb28 | 2930 | (set_attr "type" "lm")]) |
9db1d521 HP |
2931 | |
2932 | (define_insn "*load_multiple_si" | |
2933 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2934 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2935 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2936 | "reload_completed" |
9db1d521 HP |
2937 | { |
2938 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2939 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2940 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2941 | } |
d3632d41 | 2942 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2943 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2944 | (set_attr "type" "lm")]) |
9db1d521 HP |
2945 | |
2946 | ; | |
c7453384 | 2947 | ; store multiple pattern(s). |
9db1d521 HP |
2948 | ; |
2949 | ||
2950 | (define_expand "store_multiple" | |
2951 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2952 | (match_operand 1 "" "")) | |
2953 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2954 | "reload_completed" |
9db1d521 | 2955 | { |
ef4bddc2 | 2956 | machine_mode mode; |
9db1d521 HP |
2957 | int regno; |
2958 | int count; | |
2959 | rtx to; | |
4023fb28 | 2960 | int i, off; |
9db1d521 HP |
2961 | |
2962 | /* Support only storing a constant number of fixed-point registers to | |
2963 | memory and only bother with this if more than two. */ | |
2964 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2965 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2966 | || INTVAL (operands[2]) > 16 |
2967 | || GET_CODE (operands[0]) != MEM | |
2968 | || GET_CODE (operands[1]) != REG | |
2969 | || REGNO (operands[1]) >= 16) | |
2970 | FAIL; | |
2971 | ||
2972 | count = INTVAL (operands[2]); | |
2973 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2974 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2975 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2976 | FAIL; |
9db1d521 HP |
2977 | |
2978 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2979 | |
b3a13419 | 2980 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2981 | { |
2982 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2983 | { | |
2984 | to = XEXP (operands[0], 0); | |
2985 | off = 0; | |
2986 | } | |
2987 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2988 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2989 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2990 | { | |
2991 | to = XEXP (XEXP (operands[0], 0), 0); | |
2992 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2993 | } | |
2994 | else | |
2995 | FAIL; | |
4023fb28 | 2996 | } |
c7453384 | 2997 | else |
4023fb28 UW |
2998 | { |
2999 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
3000 | off = 0; | |
3001 | } | |
9db1d521 HP |
3002 | |
3003 | for (i = 0; i < count; i++) | |
3004 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 3005 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
3006 | plus_constant (Pmode, to, |
3007 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 3008 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 3009 | }) |
9db1d521 HP |
3010 | |
3011 | (define_insn "*store_multiple_di" | |
3012 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 3013 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 3014 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 3015 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
3016 | { |
3017 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 3018 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 3019 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 3020 | } |
d3632d41 | 3021 | [(set_attr "op_type" "RSY") |
4023fb28 | 3022 | (set_attr "type" "stm")]) |
9db1d521 HP |
3023 | |
3024 | ||
3025 | (define_insn "*store_multiple_si" | |
3026 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
3027 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
3028 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 3029 | "reload_completed" |
9db1d521 HP |
3030 | { |
3031 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 3032 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 3033 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 3034 | } |
d3632d41 | 3035 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3036 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 3037 | (set_attr "type" "stm")]) |
9db1d521 HP |
3038 | |
3039 | ;; | |
3040 | ;; String instructions. | |
3041 | ;; | |
3042 | ||
963fc8d0 | 3043 | (define_insn "*execute_rl" |
2771c2f9 | 3044 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
3045 | [(unspec [(match_operand 1 "register_operand" "a") |
3046 | (match_operand 2 "" "") | |
3047 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
3048 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
3049 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
3050 | "exrl\t%1,%3" | |
3051 | [(set_attr "op_type" "RIL") | |
14cfceb7 IL |
3052 | (set_attr "type" "cs") |
3053 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 3054 | |
9bb86f41 | 3055 | (define_insn "*execute" |
2771c2f9 | 3056 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
3057 | [(unspec [(match_operand 1 "register_operand" "a") |
3058 | (match_operand:BLK 2 "memory_operand" "R") | |
3059 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
3060 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
3061 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
3062 | "ex\t%1,%2" | |
29a74354 UW |
3063 | [(set_attr "op_type" "RX") |
3064 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
3065 | |
3066 | ||
91d39d71 UW |
3067 | ; |
3068 | ; strlenM instruction pattern(s). | |
3069 | ; | |
3070 | ||
9db2f16d | 3071 | (define_expand "strlen<mode>" |
085261c8 AK |
3072 | [(match_operand:P 0 "register_operand" "") ; result |
3073 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
3074 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
3075 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
3076 | "" | |
3077 | { | |
3078 | if (!TARGET_VX || operands[2] != const0_rtx) | |
3079 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
3080 | operands[2], operands[3])); | |
3081 | else | |
3082 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
3083 | ||
3084 | DONE; | |
3085 | }) | |
3086 | ||
3087 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 3088 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 3089 | (parallel |
91d39d71 | 3090 | [(set (match_dup 4) |
9db2f16d | 3091 | (unspec:P [(const_int 0) |
91d39d71 | 3092 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 3093 | (reg:SI 0) |
91d39d71 | 3094 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3095 | (clobber (scratch:P)) |
ae156f85 | 3096 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 3097 | (parallel |
9db2f16d AS |
3098 | [(set (match_operand:P 0 "register_operand" "") |
3099 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 3100 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 3101 | "" |
91d39d71 | 3102 | { |
9db2f16d AS |
3103 | operands[4] = gen_reg_rtx (Pmode); |
3104 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
3105 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3106 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
3107 | }) | |
3108 | ||
9db2f16d AS |
3109 | (define_insn "*strlen<mode>" |
3110 | [(set (match_operand:P 0 "register_operand" "=a") | |
3111 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
3112 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 3113 | (reg:SI 0) |
91d39d71 | 3114 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3115 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 3116 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 3117 | "" |
91d39d71 | 3118 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
3119 | [(set_attr "length" "8") |
3120 | (set_attr "type" "vs")]) | |
91d39d71 | 3121 | |
ccbdc0d4 AS |
3122 | ; |
3123 | ; cmpstrM instruction pattern(s). | |
3124 | ; | |
3125 | ||
3126 | (define_expand "cmpstrsi" | |
3127 | [(set (reg:SI 0) (const_int 0)) | |
3128 | (parallel | |
3129 | [(clobber (match_operand 3 "" "")) | |
3130 | (clobber (match_dup 4)) | |
3131 | (set (reg:CCU CC_REGNUM) | |
3132 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
3133 | (match_operand:BLK 2 "memory_operand" ""))) | |
3134 | (use (reg:SI 0))]) | |
3135 | (parallel | |
3136 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3137 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
3138 | (clobber (reg:CC CC_REGNUM))])] |
3139 | "" | |
3140 | { | |
3141 | /* As the result of CMPINT is inverted compared to what we need, | |
3142 | we have to swap the operands. */ | |
3143 | rtx op1 = operands[2]; | |
3144 | rtx op2 = operands[1]; | |
3145 | rtx addr1 = gen_reg_rtx (Pmode); | |
3146 | rtx addr2 = gen_reg_rtx (Pmode); | |
3147 | ||
3148 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
3149 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
3150 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
3151 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
3152 | operands[3] = addr1; | |
3153 | operands[4] = addr2; | |
3154 | }) | |
3155 | ||
3156 | (define_insn "*cmpstr<mode>" | |
3157 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3158 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3159 | (set (reg:CCU CC_REGNUM) | |
3160 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3161 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3162 | (use (reg:SI 0))] | |
3163 | "" | |
3164 | "clst\t%0,%1\;jo\t.-4" | |
3165 | [(set_attr "length" "8") | |
3166 | (set_attr "type" "vs")]) | |
9381e3f1 | 3167 | |
742090fc AS |
3168 | ; |
3169 | ; movstr instruction pattern. | |
3170 | ; | |
3171 | ||
3172 | (define_expand "movstr" | |
4a7dec25 DV |
3173 | [(match_operand 0 "register_operand" "") |
3174 | (match_operand 1 "memory_operand" "") | |
3175 | (match_operand 2 "memory_operand" "")] | |
3176 | "" | |
3177 | { | |
3178 | if (TARGET_64BIT) | |
3179 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3180 | else | |
3181 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3182 | DONE; | |
3183 | }) | |
3184 | ||
3185 | (define_expand "movstr<P:mode>" | |
742090fc | 3186 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3187 | (parallel |
742090fc AS |
3188 | [(clobber (match_dup 3)) |
3189 | (set (match_operand:BLK 1 "memory_operand" "") | |
3190 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3191 | (set (match_operand:P 0 "register_operand" "") |
3192 | (unspec:P [(match_dup 1) | |
742090fc AS |
3193 | (match_dup 2) |
3194 | (reg:SI 0)] UNSPEC_MVST)) | |
3195 | (clobber (reg:CC CC_REGNUM))])] | |
3196 | "" | |
3197 | { | |
859a4c0e AK |
3198 | rtx addr1, addr2; |
3199 | ||
3200 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3201 | { | |
3202 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3203 | DONE; | |
3204 | } | |
3205 | ||
3206 | addr1 = gen_reg_rtx (Pmode); | |
3207 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3208 | |
3209 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3210 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3211 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3212 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3213 | operands[3] = addr2; | |
3214 | }) | |
3215 | ||
3216 | (define_insn "*movstr" | |
3217 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3218 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3219 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3220 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3221 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3222 | (mem:BLK (match_dup 3)) |
3223 | (reg:SI 0)] UNSPEC_MVST)) | |
3224 | (clobber (reg:CC CC_REGNUM))] | |
3225 | "" | |
3226 | "mvst\t%1,%2\;jo\t.-4" | |
3227 | [(set_attr "length" "8") | |
3228 | (set_attr "type" "vs")]) | |
9381e3f1 | 3229 | |
742090fc | 3230 | |
9db1d521 | 3231 | ; |
76715c32 | 3232 | ; cpymemM instruction pattern(s). |
9db1d521 HP |
3233 | ; |
3234 | ||
76715c32 | 3235 | (define_expand "cpymem<mode>" |
963fc8d0 AK |
3236 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3237 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3238 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3239 | (match_operand 3 "" "")] |
3240 | "" | |
367d32f3 | 3241 | { |
76715c32 | 3242 | if (s390_expand_cpymem (operands[0], operands[1], operands[2])) |
367d32f3 AK |
3243 | DONE; |
3244 | else | |
3245 | FAIL; | |
3246 | }) | |
9db1d521 | 3247 | |
ecbe845e UW |
3248 | ; Move a block that is up to 256 bytes in length. |
3249 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3250 | |
76715c32 | 3251 | (define_expand "cpymem_short" |
b9404c99 UW |
3252 | [(parallel |
3253 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3254 | (match_operand:BLK 1 "memory_operand" "")) | |
3255 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3256 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3257 | (clobber (match_dup 3))])] |
3258 | "" | |
3259 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3260 | |
76715c32 | 3261 | (define_insn "*cpymem_short" |
963fc8d0 AK |
3262 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3263 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3264 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3265 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3266 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3267 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3268 | "#" |
963fc8d0 | 3269 | [(set_attr "type" "cs") |
b5e0425c | 3270 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3271 | |
9bb86f41 UW |
3272 | (define_split |
3273 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3274 | (match_operand:BLK 1 "memory_operand" "")) | |
3275 | (use (match_operand 2 "const_int_operand" "")) | |
3276 | (use (match_operand 3 "immediate_operand" "")) | |
3277 | (clobber (scratch))] | |
3278 | "reload_completed" | |
3279 | [(parallel | |
3280 | [(set (match_dup 0) (match_dup 1)) | |
3281 | (use (match_dup 2))])] | |
3282 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3283 | |
9bb86f41 UW |
3284 | (define_split |
3285 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3286 | (match_operand:BLK 1 "memory_operand" "")) | |
3287 | (use (match_operand 2 "register_operand" "")) | |
3288 | (use (match_operand 3 "memory_operand" "")) | |
3289 | (clobber (scratch))] | |
3290 | "reload_completed" | |
3291 | [(parallel | |
3292 | [(unspec [(match_dup 2) (match_dup 3) | |
3293 | (const_int 0)] UNSPEC_EXECUTE) | |
3294 | (set (match_dup 0) (match_dup 1)) | |
3295 | (use (const_int 1))])] | |
3296 | "") | |
3297 | ||
963fc8d0 AK |
3298 | (define_split |
3299 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3300 | (match_operand:BLK 1 "memory_operand" "")) | |
3301 | (use (match_operand 2 "register_operand" "")) | |
3302 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3303 | (clobber (scratch))] | |
3304 | "TARGET_Z10 && reload_completed" | |
3305 | [(parallel | |
3306 | [(unspec [(match_dup 2) (const_int 0) | |
3307 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3308 | (set (match_dup 0) (match_dup 1)) | |
3309 | (use (const_int 1))])] | |
3310 | "operands[3] = gen_label_rtx ();") | |
3311 | ||
9bb86f41 UW |
3312 | (define_split |
3313 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3314 | (match_operand:BLK 1 "memory_operand" "")) | |
3315 | (use (match_operand 2 "register_operand" "")) | |
3316 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3317 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3318 | "reload_completed" |
9bb86f41 UW |
3319 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3320 | (parallel | |
9381e3f1 | 3321 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3322 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3323 | (set (match_dup 0) (match_dup 1)) | |
3324 | (use (const_int 1))])] | |
3325 | "operands[4] = gen_label_rtx ();") | |
3326 | ||
a41c6c53 | 3327 | ; Move a block of arbitrary length. |
9db1d521 | 3328 | |
76715c32 | 3329 | (define_expand "cpymem_long" |
b9404c99 UW |
3330 | [(parallel |
3331 | [(clobber (match_dup 2)) | |
3332 | (clobber (match_dup 3)) | |
3333 | (set (match_operand:BLK 0 "memory_operand" "") | |
3334 | (match_operand:BLK 1 "memory_operand" "")) | |
3335 | (use (match_operand 2 "general_operand" "")) | |
3336 | (use (match_dup 3)) | |
ae156f85 | 3337 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3338 | "" |
3339 | { | |
ef4bddc2 RS |
3340 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3341 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3342 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3343 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3344 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3345 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3346 | rtx len0 = gen_lowpart (Pmode, reg0); |
3347 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3348 | ||
c41c1387 | 3349 | emit_clobber (reg0); |
b9404c99 UW |
3350 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3351 | emit_move_insn (len0, operands[2]); | |
3352 | ||
c41c1387 | 3353 | emit_clobber (reg1); |
b9404c99 UW |
3354 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3355 | emit_move_insn (len1, operands[2]); | |
3356 | ||
3357 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3358 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3359 | operands[2] = reg0; | |
3360 | operands[3] = reg1; | |
3361 | }) | |
3362 | ||
76715c32 | 3363 | (define_insn "*cpymem_long" |
a1aed706 AS |
3364 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
3365 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3366 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3367 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3368 | (use (match_dup 2)) |
3369 | (use (match_dup 3)) | |
ae156f85 | 3370 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3371 | "TARGET_64BIT || !TARGET_ZARCH" |
3372 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3373 | [(set_attr "length" "8") | |
3374 | (set_attr "type" "vs")]) | |
3375 | ||
76715c32 | 3376 | (define_insn "*cpymem_long_31z" |
9602b6a1 AK |
3377 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3378 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3379 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3380 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3381 | (use (match_dup 2)) | |
3382 | (use (match_dup 3)) | |
3383 | (clobber (reg:CC CC_REGNUM))] | |
3384 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3385 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3386 | [(set_attr "length" "8") |
3387 | (set_attr "type" "vs")]) | |
9db1d521 | 3388 | |
638e37c2 WG |
3389 | |
3390 | ; | |
3391 | ; Test data class. | |
3392 | ; | |
3393 | ||
0f67fa83 WG |
3394 | (define_expand "signbit<mode>2" |
3395 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3396 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3397 | (match_dup 2)] | |
0f67fa83 WG |
3398 | UNSPEC_TDC_INSN)) |
3399 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3400 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3401 | "TARGET_HARD_FLOAT" |
3402 | { | |
3403 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3404 | }) | |
3405 | ||
638e37c2 WG |
3406 | (define_expand "isinf<mode>2" |
3407 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3408 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3409 | (match_dup 2)] | |
638e37c2 WG |
3410 | UNSPEC_TDC_INSN)) |
3411 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3412 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3413 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3414 | { |
3415 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3416 | }) | |
3417 | ||
085261c8 AK |
3418 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3419 | ; instruction will be issued by reload. The constraint of operand 1 | |
3420 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3421 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3422 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3423 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3424 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3425 | UNSPEC_CC_TO_INT))] | |
3426 | "operands != NULL" | |
3427 | "#" | |
3428 | "reload_completed" | |
3429 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3430 | ||
638e37c2 WG |
3431 | ; This insn is used to generate all variants of the Test Data Class |
3432 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3433 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3434 | ; specifying the required test(s). |
638e37c2 | 3435 | ; |
be5de7a1 | 3436 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3437 | (define_insn "*TDC_insn_<mode>" |
3438 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3439 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3440 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3441 | "TARGET_HARD_FLOAT" |
0387c142 | 3442 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3443 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3444 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3445 | |
638e37c2 WG |
3446 | |
3447 | ||
9db1d521 | 3448 | ; |
57e84f18 | 3449 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3450 | ; |
3451 | ||
57e84f18 | 3452 | (define_expand "setmem<mode>" |
a41c6c53 | 3453 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3454 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3455 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3456 | (match_operand 3 "" "")] |
a41c6c53 | 3457 | "" |
6d057022 | 3458 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3459 | |
a41c6c53 | 3460 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3461 | ; The block length is taken as (operands[1] % 256) + 1. |
3462 | ||
70128ad9 | 3463 | (define_expand "clrmem_short" |
b9404c99 UW |
3464 | [(parallel |
3465 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3466 | (const_int 0)) | |
3467 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3468 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3469 | (clobber (match_dup 2)) |
ae156f85 | 3470 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3471 | "" |
3472 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3473 | |
70128ad9 | 3474 | (define_insn "*clrmem_short" |
963fc8d0 | 3475 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3476 | (const_int 0)) |
963fc8d0 AK |
3477 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3478 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3479 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3480 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3481 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3482 | "#" |
963fc8d0 | 3483 | [(set_attr "type" "cs") |
b5e0425c | 3484 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3485 | |
3486 | (define_split | |
3487 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3488 | (const_int 0)) | |
3489 | (use (match_operand 1 "const_int_operand" "")) | |
3490 | (use (match_operand 2 "immediate_operand" "")) | |
3491 | (clobber (scratch)) | |
ae156f85 | 3492 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3493 | "reload_completed" |
3494 | [(parallel | |
3495 | [(set (match_dup 0) (const_int 0)) | |
3496 | (use (match_dup 1)) | |
ae156f85 | 3497 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3498 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3499 | |
9bb86f41 UW |
3500 | (define_split |
3501 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3502 | (const_int 0)) | |
3503 | (use (match_operand 1 "register_operand" "")) | |
3504 | (use (match_operand 2 "memory_operand" "")) | |
3505 | (clobber (scratch)) | |
ae156f85 | 3506 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3507 | "reload_completed" |
3508 | [(parallel | |
3509 | [(unspec [(match_dup 1) (match_dup 2) | |
3510 | (const_int 0)] UNSPEC_EXECUTE) | |
3511 | (set (match_dup 0) (const_int 0)) | |
3512 | (use (const_int 1)) | |
ae156f85 | 3513 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3514 | "") |
9db1d521 | 3515 | |
963fc8d0 AK |
3516 | (define_split |
3517 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3518 | (const_int 0)) | |
3519 | (use (match_operand 1 "register_operand" "")) | |
3520 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3521 | (clobber (scratch)) | |
3522 | (clobber (reg:CC CC_REGNUM))] | |
3523 | "TARGET_Z10 && reload_completed" | |
3524 | [(parallel | |
3525 | [(unspec [(match_dup 1) (const_int 0) | |
3526 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3527 | (set (match_dup 0) (const_int 0)) | |
3528 | (use (const_int 1)) | |
3529 | (clobber (reg:CC CC_REGNUM))])] | |
3530 | "operands[3] = gen_label_rtx ();") | |
3531 | ||
9bb86f41 UW |
3532 | (define_split |
3533 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3534 | (const_int 0)) | |
3535 | (use (match_operand 1 "register_operand" "")) | |
3536 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3537 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3538 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 3539 | "reload_completed" |
9bb86f41 UW |
3540 | [(set (match_dup 2) (label_ref (match_dup 3))) |
3541 | (parallel | |
9381e3f1 | 3542 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3543 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3544 | (set (match_dup 0) (const_int 0)) | |
3545 | (use (const_int 1)) | |
ae156f85 | 3546 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3547 | "operands[3] = gen_label_rtx ();") |
3548 | ||
9381e3f1 | 3549 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3550 | |
da0dcab1 | 3551 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3552 | [(parallel |
3553 | [(clobber (match_dup 1)) | |
3554 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3555 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3556 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3557 | (use (match_dup 3)) |
ae156f85 | 3558 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3559 | "" |
a41c6c53 | 3560 | { |
ef4bddc2 RS |
3561 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3562 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3563 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3564 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3565 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3566 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3567 | |
c41c1387 | 3568 | emit_clobber (reg0); |
b9404c99 UW |
3569 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3570 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3571 | |
b9404c99 | 3572 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3573 | |
b9404c99 UW |
3574 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3575 | operands[1] = reg0; | |
6d057022 | 3576 | operands[3] = reg1; |
da0dcab1 | 3577 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3578 | }) |
a41c6c53 | 3579 | |
da0dcab1 DV |
3580 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3581 | ||
db340c73 | 3582 | (define_insn "*setmem_long" |
a1aed706 | 3583 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3584 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3585 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3586 | (subreg:P (match_dup 3) <modesize>)] |
3587 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3588 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3589 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3590 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3591 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3592 | [(set_attr "length" "8") |
3593 | (set_attr "type" "vs")]) | |
9db1d521 | 3594 | |
db340c73 AK |
3595 | (define_insn "*setmem_long_and" |
3596 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3597 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3598 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3599 | (subreg:P (match_dup 3) <modesize>)] |
3600 | UNSPEC_REPLICATE_BYTE)) | |
3601 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3602 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3603 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3604 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3605 | [(set_attr "length" "8") | |
3606 | (set_attr "type" "vs")]) | |
3607 | ||
da0dcab1 DV |
3608 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3609 | ; of the SImode subregs. | |
3610 | ||
db340c73 | 3611 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3612 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3613 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3614 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3615 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3616 | (use (match_operand:TI 1 "register_operand" "d")) |
3617 | (clobber (reg:CC CC_REGNUM))] | |
3618 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3619 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3620 | [(set_attr "length" "8") | |
3621 | (set_attr "type" "vs")]) | |
9602b6a1 | 3622 | |
db340c73 AK |
3623 | (define_insn "*setmem_long_and_31z" |
3624 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3625 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3626 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3627 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3628 | (use (match_operand:TI 1 "register_operand" "d")) | |
3629 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3630 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3631 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3632 | [(set_attr "length" "8") | |
3633 | (set_attr "type" "vs")]) | |
3634 | ||
9db1d521 | 3635 | ; |
358b8f01 | 3636 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3637 | ; |
3638 | ||
358b8f01 | 3639 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3640 | [(set (match_operand:SI 0 "register_operand" "") |
3641 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3642 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3643 | (use (match_operand:SI 3 "general_operand" "")) | |
3644 | (use (match_operand:SI 4 "" ""))] | |
3645 | "" | |
367d32f3 AK |
3646 | { |
3647 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3648 | operands[2], operands[3])) | |
3649 | DONE; | |
3650 | else | |
3651 | FAIL; | |
3652 | }) | |
9db1d521 | 3653 | |
a41c6c53 UW |
3654 | ; Compare a block that is up to 256 bytes in length. |
3655 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3656 | |
b9404c99 UW |
3657 | (define_expand "cmpmem_short" |
3658 | [(parallel | |
ae156f85 | 3659 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3660 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3661 | (match_operand:BLK 1 "memory_operand" ""))) |
3662 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3663 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3664 | (clobber (match_dup 3))])] |
3665 | "" | |
3666 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3667 | |
b9404c99 | 3668 | (define_insn "*cmpmem_short" |
ae156f85 | 3669 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3670 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3671 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3672 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3673 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3674 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3675 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3676 | "#" |
963fc8d0 | 3677 | [(set_attr "type" "cs") |
b5e0425c | 3678 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3679 | |
9bb86f41 | 3680 | (define_split |
ae156f85 | 3681 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3682 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3683 | (match_operand:BLK 1 "memory_operand" ""))) | |
3684 | (use (match_operand 2 "const_int_operand" "")) | |
3685 | (use (match_operand 3 "immediate_operand" "")) | |
3686 | (clobber (scratch))] | |
3687 | "reload_completed" | |
3688 | [(parallel | |
ae156f85 | 3689 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3690 | (use (match_dup 2))])] |
3691 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3692 | |
9bb86f41 | 3693 | (define_split |
ae156f85 | 3694 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3695 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3696 | (match_operand:BLK 1 "memory_operand" ""))) | |
3697 | (use (match_operand 2 "register_operand" "")) | |
3698 | (use (match_operand 3 "memory_operand" "")) | |
3699 | (clobber (scratch))] | |
3700 | "reload_completed" | |
3701 | [(parallel | |
3702 | [(unspec [(match_dup 2) (match_dup 3) | |
3703 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3704 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3705 | (use (const_int 1))])] |
3706 | "") | |
3707 | ||
963fc8d0 AK |
3708 | (define_split |
3709 | [(set (reg:CCU CC_REGNUM) | |
3710 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3711 | (match_operand:BLK 1 "memory_operand" ""))) | |
3712 | (use (match_operand 2 "register_operand" "")) | |
3713 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3714 | (clobber (scratch))] | |
3715 | "TARGET_Z10 && reload_completed" | |
3716 | [(parallel | |
3717 | [(unspec [(match_dup 2) (const_int 0) | |
3718 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3719 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3720 | (use (const_int 1))])] | |
3721 | "operands[4] = gen_label_rtx ();") | |
3722 | ||
9bb86f41 | 3723 | (define_split |
ae156f85 | 3724 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3725 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3726 | (match_operand:BLK 1 "memory_operand" ""))) | |
3727 | (use (match_operand 2 "register_operand" "")) | |
3728 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3729 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3730 | "reload_completed" |
9bb86f41 UW |
3731 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3732 | (parallel | |
9381e3f1 | 3733 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3734 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3735 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3736 | (use (const_int 1))])] |
3737 | "operands[4] = gen_label_rtx ();") | |
3738 | ||
a41c6c53 | 3739 | ; Compare a block of arbitrary length. |
9db1d521 | 3740 | |
b9404c99 UW |
3741 | (define_expand "cmpmem_long" |
3742 | [(parallel | |
3743 | [(clobber (match_dup 2)) | |
3744 | (clobber (match_dup 3)) | |
ae156f85 | 3745 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3746 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3747 | (match_operand:BLK 1 "memory_operand" ""))) |
3748 | (use (match_operand 2 "general_operand" "")) | |
3749 | (use (match_dup 3))])] | |
3750 | "" | |
3751 | { | |
ef4bddc2 RS |
3752 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3753 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3754 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3755 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3756 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3757 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3758 | rtx len0 = gen_lowpart (Pmode, reg0); |
3759 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3760 | ||
c41c1387 | 3761 | emit_clobber (reg0); |
b9404c99 UW |
3762 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3763 | emit_move_insn (len0, operands[2]); | |
3764 | ||
c41c1387 | 3765 | emit_clobber (reg1); |
b9404c99 UW |
3766 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3767 | emit_move_insn (len1, operands[2]); | |
3768 | ||
3769 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3770 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3771 | operands[2] = reg0; | |
3772 | operands[3] = reg1; | |
3773 | }) | |
3774 | ||
a1aed706 AS |
3775 | (define_insn "*cmpmem_long" |
3776 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3777 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3778 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3779 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3780 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3781 | (use (match_dup 2)) |
3782 | (use (match_dup 3))] | |
9602b6a1 | 3783 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3784 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3785 | [(set_attr "length" "8") |
3786 | (set_attr "type" "vs")]) | |
9db1d521 | 3787 | |
9602b6a1 AK |
3788 | (define_insn "*cmpmem_long_31z" |
3789 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3790 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3791 | (set (reg:CCU CC_REGNUM) | |
3792 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3793 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3794 | (use (match_dup 2)) | |
3795 | (use (match_dup 3))] | |
3796 | "!TARGET_64BIT && TARGET_ZARCH" | |
3797 | "clcle\t%0,%1,0\;jo\t.-4" | |
3798 | [(set_attr "op_type" "NN") | |
3799 | (set_attr "type" "vs") | |
3800 | (set_attr "length" "8")]) | |
3801 | ||
02887425 UW |
3802 | ; Convert CCUmode condition code to integer. |
3803 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3804 | |
02887425 | 3805 | (define_insn_and_split "cmpint" |
9db1d521 | 3806 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3807 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3808 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3809 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3810 | "" |
02887425 UW |
3811 | "#" |
3812 | "reload_completed" | |
3813 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3814 | (parallel | |
3815 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3816 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3817 | |
3818 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3819 | [(set (reg CC_REGNUM) |
02887425 | 3820 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3821 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3822 | (const_int 0))) |
3823 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3824 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3825 | "s390_match_ccmode (insn, CCSmode)" |
3826 | "#" | |
3827 | "&& reload_completed" | |
3828 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3829 | (parallel | |
3830 | [(set (match_dup 2) (match_dup 3)) | |
3831 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3832 | { |
02887425 UW |
3833 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3834 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3835 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3836 | }) | |
9db1d521 | 3837 | |
02887425 | 3838 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3839 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3840 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3841 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3842 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3843 | "TARGET_ZARCH" |
02887425 UW |
3844 | "#" |
3845 | "&& reload_completed" | |
3846 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3847 | (parallel | |
3848 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3849 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3850 | |
3851 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3852 | [(set (reg CC_REGNUM) |
9381e3f1 | 3853 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3854 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3855 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3856 | (const_int 32)) (const_int 32)) |
3857 | (const_int 0))) | |
3858 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3859 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3860 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3861 | "#" |
3862 | "&& reload_completed" | |
3863 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3864 | (parallel | |
3865 | [(set (match_dup 2) (match_dup 3)) | |
3866 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3867 | { |
02887425 UW |
3868 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3869 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3870 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3871 | }) | |
9db1d521 | 3872 | |
4023fb28 | 3873 | |
9db1d521 HP |
3874 | ;; |
3875 | ;;- Conversion instructions. | |
3876 | ;; | |
3877 | ||
6fa05db6 | 3878 | (define_insn "*sethighpartsi" |
d3632d41 | 3879 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3880 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3881 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3882 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3883 | "" |
d3632d41 | 3884 | "@ |
6fa05db6 AS |
3885 | icm\t%0,%2,%S1 |
3886 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3887 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3888 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3889 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3890 | |
6fa05db6 | 3891 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3892 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3893 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3894 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3895 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3896 | "TARGET_ZARCH" |
6fa05db6 | 3897 | "icmh\t%0,%2,%S1" |
729e750f WG |
3898 | [(set_attr "op_type" "RSY") |
3899 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3900 | |
6fa05db6 | 3901 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3902 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3903 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3904 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3905 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3906 | "!TARGET_ZARCH" |
d3632d41 | 3907 | "@ |
6fa05db6 AS |
3908 | icm\t%0,%2,%S1 |
3909 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3910 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3911 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3912 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3913 | ||
1a2e356e RH |
3914 | ; |
3915 | ; extv instruction patterns | |
3916 | ; | |
3917 | ||
3918 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3919 | ; after resolving some issues with it. | |
3920 | ||
3921 | (define_expand "extzv" | |
3922 | [(parallel | |
3923 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3924 | (zero_extract:DI | |
3925 | (match_operand:DI 1 "register_operand" "d") | |
3926 | (match_operand 2 "const_int_operand" "") ; size | |
3927 | (match_operand 3 "const_int_operand" ""))) ; start | |
3928 | (clobber (reg:CC CC_REGNUM))])] | |
3929 | "TARGET_Z10" | |
3930 | { | |
0f6f72e8 DV |
3931 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3932 | FAIL; | |
1a2e356e RH |
3933 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3934 | if (TARGET_ZEC12) | |
3935 | { | |
3936 | emit_move_insn (operands[0], | |
3937 | gen_rtx_ZERO_EXTRACT (DImode, | |
3938 | operands[1], | |
3939 | operands[2], | |
3940 | operands[3])); | |
3941 | DONE; | |
3942 | } | |
3943 | }) | |
3944 | ||
64c744b9 | 3945 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3946 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3947 | (zero_extract:GPR | |
3948 | (match_operand:GPR 1 "register_operand" "d") | |
3949 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3950 | (match_operand 3 "const_int_operand" ""))) ; start |
3951 | ] | |
0f6f72e8 DV |
3952 | "<z10_or_zEC12_cond> |
3953 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3954 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3955 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3956 | [(set_attr "op_type" "RIE") | |
3957 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3958 | |
64c744b9 DV |
3959 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3960 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3961 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3962 | (match_operand 1 "const_int_operand" "") ; size | |
3963 | (match_operand 2 "const_int_operand" "")) ; start | |
3964 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3965 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3966 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3967 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3968 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3969 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3970 | [(set_attr "op_type" "RIE") | |
3971 | (set_attr "z10prop" "z10_super_E1")]) | |
3972 | ||
3973 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3974 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3975 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3976 | (ior:SI (and:SI | |
3977 | (match_operand:SI 1 "register_operand" "0") | |
3978 | (match_operand:SI 2 "const_int_operand" "")) | |
3979 | (subreg:SI | |
3980 | (zero_extract:DI | |
3981 | (match_operand:DI 3 "register_operand" "d") | |
3982 | (match_operand 4 "const_int_operand" "") ; size | |
3983 | (match_operand 5 "const_int_operand" "")) ; start | |
3984 | 4)))] | |
3985 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3986 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
14653c37 | 3987 | && UINTVAL (operands[2]) == (HOST_WIDE_INT_M1U << UINTVAL (operands[4]))" |
64c744b9 DV |
3988 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" |
3989 | [(set_attr "op_type" "RIE") | |
3990 | (set_attr "z10prop" "z10_super_E1")]) | |
3991 | ||
3992 | ; ((int)foo >> 10) & 1; | |
3993 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3994 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3995 | (ne:DI (zero_extract:DI | |
3996 | (match_operand:DI 1 "register_operand" "d") | |
3997 | (const_int 1) ; size | |
3998 | (match_operand 2 "const_int_operand" "")) ; start | |
3999 | (const_int 0)))] | |
0f6f72e8 DV |
4000 | "<z10_or_zEC12_cond> |
4001 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
4002 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
4003 | [(set_attr "op_type" "RIE") | |
4004 | (set_attr "z10prop" "z10_super_E1")]) | |
4005 | ||
4006 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
4007 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4008 | (and:DI (subreg:DI | |
4009 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
4010 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
4011 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
4012 | "<z10_or_zEC12_cond> | |
14653c37 JJ |
4013 | && (UINTVAL (operands[3]) |
4014 | < (HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)))" | |
64c744b9 DV |
4015 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift |
4016 | [(set_attr "op_type" "RIE") | |
4017 | (set_attr "z10prop" "z10_super_E1")]) | |
4018 | ||
4019 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
4020 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4021 | (and:DI (subreg:DI | |
4022 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
4023 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
4024 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
4025 | "<z10_or_zEC12_cond> | |
14653c37 JJ |
4026 | && !(UINTVAL (operands[3]) |
4027 | & ((HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
64c744b9 DV |
4028 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift |
4029 | [(set_attr "op_type" "RIE") | |
4030 | (set_attr "z10prop" "z10_super_E1")]) | |
4031 | ||
4032 | (define_insn "*<risbg_n>_di_and_rot" | |
4033 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4034 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
4035 | (match_operand:DI 2 "const_int_operand" "")) | |
4036 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
4037 | "<z10_or_zEC12_cond>" | |
4038 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
4039 | [(set_attr "op_type" "RIE") |
4040 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 4041 | |
1a2e356e | 4042 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 4043 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 4044 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 4045 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 4046 | (const_int 0))) |
ae156f85 | 4047 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 4048 | "!TARGET_Z10" |
cc7ab9b7 UW |
4049 | "#" |
4050 | "&& reload_completed" | |
4023fb28 | 4051 | [(parallel |
6fa05db6 | 4052 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 4053 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 4054 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 4055 | { |
6fa05db6 AS |
4056 | int bitsize = INTVAL (operands[2]); |
4057 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
14653c37 JJ |
4058 | unsigned HOST_WIDE_INT mask |
4059 | = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
6fa05db6 AS |
4060 | |
4061 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4062 | set_mem_size (operands[1], size); |
2542ef05 | 4063 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 4064 | operands[3] = GEN_INT (mask); |
b628bd8e | 4065 | }) |
4023fb28 | 4066 | |
1a2e356e | 4067 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 4068 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 4069 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 4070 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 4071 | (const_int 0))) |
ae156f85 | 4072 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 4073 | "" |
cc7ab9b7 UW |
4074 | "#" |
4075 | "&& reload_completed" | |
4023fb28 | 4076 | [(parallel |
6fa05db6 | 4077 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 4078 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
4079 | (parallel |
4080 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
4081 | (clobber (reg:CC CC_REGNUM))])] | |
4082 | { | |
4083 | int bitsize = INTVAL (operands[2]); | |
4084 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
14653c37 JJ |
4085 | unsigned HOST_WIDE_INT mask |
4086 | = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
6fa05db6 AS |
4087 | |
4088 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4089 | set_mem_size (operands[1], size); |
2542ef05 | 4090 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
4091 | operands[3] = GEN_INT (mask); |
4092 | }) | |
4093 | ||
4094 | ; | |
4095 | ; insv instruction patterns | |
4096 | ; | |
4097 | ||
4098 | (define_expand "insv" | |
4099 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
4100 | (match_operand 1 "const_int_operand" "") | |
4101 | (match_operand 2 "const_int_operand" "")) | |
4102 | (match_operand 3 "general_operand" ""))] | |
4103 | "" | |
4023fb28 | 4104 | { |
6fa05db6 AS |
4105 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
4106 | DONE; | |
4107 | FAIL; | |
b628bd8e | 4108 | }) |
4023fb28 | 4109 | |
2542ef05 RH |
4110 | |
4111 | ; The normal RTL expansion will never generate a zero_extract where | |
4112 | ; the location operand isn't word mode. However, we do this in the | |
4113 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 4114 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 4115 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
4116 | (match_operand 1 "const_int_operand" "I") ; size |
4117 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 4118 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 4119 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
4120 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
4121 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 4122 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 4123 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
4124 | [(set_attr "op_type" "RIE") |
4125 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4126 | |
22ac2c2f AK |
4127 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
4128 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
4129 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
4130 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
4131 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 4132 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 4133 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 4134 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
4135 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
4136 | "@ | |
4137 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
4138 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
4139 | [(set_attr "op_type" "RIE") | |
4140 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 4141 | |
64c744b9 DV |
4142 | (define_insn "*insv_z10_noshift_cc" |
4143 | [(set (reg CC_REGNUM) | |
4144 | (compare | |
4145 | (ior:DI | |
4146 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4147 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4148 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4149 | (match_operand:DI 4 "const_int_operand" ""))) | |
4150 | (const_int 0))) | |
4151 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
4152 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
4153 | (and:DI (match_dup 3) (match_dup 4))))] | |
4154 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4155 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4156 | "@ | |
4157 | risbg\t%0,%1,%s2,%e2,0 | |
4158 | risbg\t%0,%3,%s4,%e4,0" | |
4159 | [(set_attr "op_type" "RIE") | |
4160 | (set_attr "z10prop" "z10_super_E1")]) | |
4161 | ||
4162 | (define_insn "*insv_z10_noshift_cconly" | |
4163 | [(set | |
4164 | (reg CC_REGNUM) | |
4165 | (compare | |
4166 | (ior:DI | |
4167 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4168 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4169 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4170 | (match_operand:DI 4 "const_int_operand" ""))) | |
4171 | (const_int 0))) | |
4172 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4173 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4174 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4175 | "@ | |
4176 | risbg\t%0,%1,%s2,%e2,0 | |
4177 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4178 | [(set_attr "op_type" "RIE") |
4179 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4180 | |
3d44ff99 AK |
4181 | ; Implement appending Y on the left of S bits of X |
4182 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4183 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4184 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4185 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4186 | (match_operand:GPR 2 "immediate_operand" "")) | |
4187 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4188 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 | 4189 | "<z10_or_zEC12_cond> |
14653c37 | 4190 | && UINTVAL (operands[2]) == (HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1" |
64c744b9 | 4191 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" |
3d44ff99 AK |
4192 | [(set_attr "op_type" "RIE") |
4193 | (set_attr "z10prop" "z10_super_E1")]) | |
4194 | ||
64c744b9 DV |
4195 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4196 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4197 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4198 | (ior:GPR (and:GPR | |
4199 | (match_operand:GPR 1 "register_operand" "0") | |
4200 | (match_operand:GPR 2 "const_int_operand" "")) | |
4201 | (lshiftrt:GPR | |
4202 | (match_operand:GPR 3 "register_operand" "d") | |
4203 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4204 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
14653c37 JJ |
4205 | == (HOST_WIDE_INT_M1U |
4206 | << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
64c744b9 DV |
4207 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" |
4208 | [(set_attr "op_type" "RIE") | |
4209 | (set_attr "z10prop" "z10_super_E1")]) | |
4210 | ||
4211 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4212 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4213 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4214 | (ior:SI (and:SI | |
4215 | (match_operand:SI 1 "register_operand" "0") | |
4216 | (match_operand:SI 2 "const_int_operand" "")) | |
4217 | (subreg:SI | |
4218 | (lshiftrt:DI | |
4219 | (match_operand:DI 3 "register_operand" "d") | |
4220 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4221 | "<z10_or_zEC12_cond> | |
14653c37 | 4222 | && UINTVAL (operands[2]) == ~(HOST_WIDE_INT_M1U >> UINTVAL (operands[4]))" |
64c744b9 DV |
4223 | "<risbg_n>\t%0,%3,%4,63,64-%4" |
4224 | [(set_attr "op_type" "RIE") | |
4225 | (set_attr "z10prop" "z10_super_E1")]) | |
4226 | ||
4227 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4228 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4229 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4230 | (and:SI | |
4231 | (subreg:SI (lshiftrt:DI | |
4232 | (match_operand:DI 1 "register_operand" "d") | |
4233 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4234 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4235 | "<z10_or_zEC12_cond>" | |
4236 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4237 | [(set_attr "op_type" "RIE") |
4238 | (set_attr "z10prop" "z10_super_E1")]) | |
4239 | ||
4240 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4241 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4242 | ; -> z = y >> d; z = risbg; | |
4243 | ||
4244 | (define_split | |
4245 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4246 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4247 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4248 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4249 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4250 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4251 | [(set (match_dup 6) |
3d44ff99 AK |
4252 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4253 | (set (match_dup 0) | |
1d11f7ce | 4254 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4255 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4256 | { | |
14653c37 | 4257 | operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); |
3168e073 | 4258 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4259 | { |
4260 | if (!can_create_pseudo_p ()) | |
4261 | FAIL; | |
4262 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4263 | } | |
4264 | else | |
4265 | operands[6] = operands[0]; | |
3d44ff99 AK |
4266 | }) |
4267 | ||
4268 | (define_split | |
4269 | [(parallel | |
4270 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4271 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4272 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4273 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4274 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4275 | (clobber (reg:CC CC_REGNUM))])] | |
4276 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4277 | [(set (match_dup 6) |
3d44ff99 AK |
4278 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4279 | (parallel | |
4280 | [(set (match_dup 0) | |
1d11f7ce | 4281 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4282 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4283 | (clobber (reg:CC CC_REGNUM))])] | |
4284 | { | |
14653c37 | 4285 | operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); |
3168e073 | 4286 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4287 | { |
4288 | if (!can_create_pseudo_p ()) | |
4289 | FAIL; | |
4290 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4291 | } | |
4292 | else | |
4293 | operands[6] = operands[0]; | |
3d44ff99 AK |
4294 | }) |
4295 | ||
50dc4eed | 4296 | ; rosbg, rxsbg |
571e408a | 4297 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4298 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4299 | (IXOR:GPR |
4300 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4301 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4302 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4303 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4304 | "TARGET_Z10" |
571e408a RH |
4305 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4306 | [(set_attr "op_type" "RIE")]) | |
4307 | ||
50dc4eed | 4308 | ; rosbg, rxsbg |
571e408a RH |
4309 | (define_insn "*r<noxa>sbg_di_rotl" |
4310 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4311 | (IXOR:DI | |
4312 | (and:DI | |
4313 | (rotate:DI | |
4314 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4315 | (match_operand:DI 3 "const_int_operand" "")) | |
4316 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4317 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4318 | (clobber (reg:CC CC_REGNUM))] | |
4319 | "TARGET_Z10" | |
8c21b0d1 | 4320 | "r<noxa>sbg\t%0,%1,%s2,%e2,%b3" |
571e408a RH |
4321 | [(set_attr "op_type" "RIE")]) |
4322 | ||
50dc4eed | 4323 | ; rosbg, rxsbg |
f3d90045 | 4324 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4325 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4326 | (IXOR:GPR | |
4327 | (and:GPR | |
4328 | (lshiftrt:GPR | |
4329 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4330 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4331 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4332 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4333 | (clobber (reg:CC CC_REGNUM))] | |
4334 | "TARGET_Z10 | |
4335 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4336 | INTVAL (operands[2]))" | |
b9789752 | 4337 | { |
290dfd9b JJ |
4338 | operands[3] = GEN_INT (64 - INTVAL (operands[3])); |
4339 | return "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"; | |
b9789752 | 4340 | } |
571e408a RH |
4341 | [(set_attr "op_type" "RIE")]) |
4342 | ||
50dc4eed | 4343 | ; rosbg, rxsbg |
f3d90045 | 4344 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4345 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4346 | (IXOR:GPR | |
4347 | (and:GPR | |
4348 | (ashift:GPR | |
4349 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4350 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4351 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4352 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4353 | (clobber (reg:CC CC_REGNUM))] | |
4354 | "TARGET_Z10 | |
4355 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4356 | INTVAL (operands[2]))" | |
4357 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4358 | [(set_attr "op_type" "RIE")]) |
4359 | ||
f3d90045 DV |
4360 | ;; unsigned {int,long} a, b |
4361 | ;; a = a | (b << const_int) | |
4362 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4363 | ; rosbg, rxsbg |
f3d90045 DV |
4364 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4365 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4366 | (IXOR:GPR | |
4367 | (ashift:GPR | |
4368 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4369 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4370 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4371 | (clobber (reg:CC CC_REGNUM))] | |
4372 | "TARGET_Z10" | |
b9789752 | 4373 | { |
290dfd9b JJ |
4374 | operands[3] = GEN_INT (63 - INTVAL (operands[2])); |
4375 | return "r<noxa>sbg\t%0,%1,<bitoff>,%3,%2"; | |
b9789752 | 4376 | } |
f3d90045 DV |
4377 | [(set_attr "op_type" "RIE")]) |
4378 | ||
4379 | ;; unsigned {int,long} a, b | |
4380 | ;; a = a | (b >> const_int) | |
4381 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4382 | ; rosbg, rxsbg |
f3d90045 DV |
4383 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4384 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4385 | (IXOR:GPR | |
4386 | (lshiftrt:GPR | |
4387 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4388 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4389 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4390 | (clobber (reg:CC CC_REGNUM))] | |
4391 | "TARGET_Z10" | |
b9789752 | 4392 | { |
290dfd9b JJ |
4393 | operands[3] = GEN_INT (64 - INTVAL (operands[2])); |
4394 | operands[2] = GEN_INT (<bitoff_plus> INTVAL (operands[2])); | |
4395 | return "r<noxa>sbg\t%0,%1,%2,63,%3"; | |
b9789752 IL |
4396 | } |
4397 | [(set_attr "op_type" "RIE")]) | |
4398 | ||
4399 | ; rosbg, rxsbg | |
4400 | (define_insn "*r<noxa>sbg_sidi_srl" | |
4401 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
4402 | (IXOR:SI | |
4403 | (subreg:SI | |
4404 | (zero_extract:DI | |
4405 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4406 | (const_int 32) | |
4407 | (match_operand:DI 2 "immediate_operand" "")) | |
4408 | 4) | |
4409 | (match_operand:SI 3 "nonimmediate_operand" "0"))) | |
4410 | (clobber (reg:CC CC_REGNUM))] | |
4411 | "TARGET_Z10" | |
4412 | { | |
290dfd9b JJ |
4413 | operands[2] = GEN_INT (32 + INTVAL (operands[2])); |
4414 | return "r<noxa>sbg\t%0,%1,32,63,%2"; | |
b9789752 | 4415 | } |
f3d90045 DV |
4416 | [(set_attr "op_type" "RIE")]) |
4417 | ||
5bb33936 RH |
4418 | ;; These two are generated by combine for s.bf &= val. |
4419 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4420 | ;; shifts and ands, which results in some truly awful patterns | |
4421 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4422 | ;; Instead of | |
4423 | ;; | |
4424 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4425 | ;; (const_int 24 [0x18]) | |
4426 | ;; (const_int 0 [0])) | |
4427 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4428 | ;; (const_int 40 [0x28])) 4) | |
4429 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4430 | ;; | |
4431 | ;; we should instead generate | |
4432 | ;; | |
4433 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4434 | ;; (const_int 24 [0x18]) | |
4435 | ;; (const_int 0 [0])) | |
4436 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4437 | ;; (const_int 40 [0x28])) | |
4438 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4439 | ;; | |
4440 | ;; by noticing that we can push down the outer paradoxical subreg | |
4441 | ;; into the operation. | |
4442 | ||
4443 | (define_insn "*insv_rnsbg_noshift" | |
4444 | [(set (zero_extract:DI | |
4445 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4446 | (match_operand 1 "const_int_operand" "") | |
4447 | (match_operand 2 "const_int_operand" "")) | |
4448 | (and:DI | |
4449 | (match_dup 0) | |
4450 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4451 | (clobber (reg:CC CC_REGNUM))] | |
4452 | "TARGET_Z10 | |
0f6f72e8 | 4453 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4454 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4455 | "rnsbg\t%0,%3,%2,63,0" | |
4456 | [(set_attr "op_type" "RIE")]) | |
4457 | ||
4458 | (define_insn "*insv_rnsbg_srl" | |
4459 | [(set (zero_extract:DI | |
4460 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4461 | (match_operand 1 "const_int_operand" "") | |
4462 | (match_operand 2 "const_int_operand" "")) | |
4463 | (and:DI | |
4464 | (lshiftrt:DI | |
4465 | (match_dup 0) | |
4466 | (match_operand 3 "const_int_operand" "")) | |
4467 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4468 | (clobber (reg:CC CC_REGNUM))] | |
4469 | "TARGET_Z10 | |
0f6f72e8 | 4470 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4471 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4472 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4473 | [(set_attr "op_type" "RIE")]) | |
4474 | ||
6fa05db6 | 4475 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4476 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4477 | (match_operand 1 "const_int_operand" "n,n") |
4478 | (const_int 0)) | |
9602b6a1 | 4479 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4480 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4481 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4482 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4483 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4484 | { | |
4485 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4486 | ||
14653c37 | 4487 | operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1); |
9381e3f1 | 4488 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4489 | : "stcmy\t%2,%1,%S0"; |
4490 | } | |
9381e3f1 | 4491 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4492 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4493 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4494 | |
4495 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4496 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4497 | (match_operand 1 "const_int_operand" "n") |
4498 | (const_int 0)) | |
4499 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4500 | (const_int 32)))] | |
9602b6a1 | 4501 | "TARGET_ZARCH |
0f6f72e8 | 4502 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4503 | && INTVAL (operands[1]) > 0 |
4504 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4505 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4506 | { | |
4507 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4508 | ||
14653c37 | 4509 | operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1); |
6fa05db6 AS |
4510 | return "stcmh\t%2,%1,%S0"; |
4511 | } | |
9381e3f1 WG |
4512 | [(set_attr "op_type" "RSY") |
4513 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4514 | |
9602b6a1 AK |
4515 | (define_insn "*insvdi_reg_imm" |
4516 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4517 | (const_int 16) | |
4518 | (match_operand 1 "const_int_operand" "n")) | |
4519 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4520 | "TARGET_ZARCH |
0f6f72e8 | 4521 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4522 | && INTVAL (operands[1]) >= 0 |
4523 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4524 | && INTVAL (operands[1]) % 16 == 0" | |
4525 | { | |
4526 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4527 | { | |
4528 | case 64: return "iihh\t%0,%x2"; break; | |
4529 | case 48: return "iihl\t%0,%x2"; break; | |
4530 | case 32: return "iilh\t%0,%x2"; break; | |
4531 | case 16: return "iill\t%0,%x2"; break; | |
4532 | default: gcc_unreachable(); | |
4533 | } | |
4534 | } | |
9381e3f1 WG |
4535 | [(set_attr "op_type" "RI") |
4536 | (set_attr "z10prop" "z10_super_E1")]) | |
4537 | ||
9fec758d WG |
4538 | ; Update the left-most 32 bit of a DI. |
4539 | (define_insn "*insv_h_di_reg_extimm" | |
4540 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4541 | (const_int 32) | |
4542 | (const_int 0)) | |
4543 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4544 | "TARGET_EXTIMM" | |
4545 | "iihf\t%0,%o1" | |
4546 | [(set_attr "op_type" "RIL") | |
4547 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4548 | |
d378b983 RH |
4549 | ; Update the right-most 32 bit of a DI. |
4550 | (define_insn "*insv_l_di_reg_extimm" | |
4551 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4552 | (const_int 32) | |
4553 | (const_int 32)) | |
4554 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4555 | "TARGET_EXTIMM" | |
4556 | "iilf\t%0,%o1" | |
9381e3f1 | 4557 | [(set_attr "op_type" "RIL") |
9fec758d | 4558 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4559 | |
9db1d521 HP |
4560 | ; |
4561 | ; extendsidi2 instruction pattern(s). | |
4562 | ; | |
4563 | ||
4023fb28 UW |
4564 | (define_expand "extendsidi2" |
4565 | [(set (match_operand:DI 0 "register_operand" "") | |
4566 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4567 | "" | |
4023fb28 | 4568 | { |
9602b6a1 | 4569 | if (!TARGET_ZARCH) |
4023fb28 | 4570 | { |
c41c1387 | 4571 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4572 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4573 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4574 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4575 | DONE; |
4576 | } | |
ec24698e | 4577 | }) |
4023fb28 UW |
4578 | |
4579 | (define_insn "*extendsidi2" | |
963fc8d0 | 4580 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4581 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4582 | "TARGET_ZARCH" |
9db1d521 | 4583 | "@ |
d40c829f | 4584 | lgfr\t%0,%1 |
963fc8d0 AK |
4585 | lgf\t%0,%1 |
4586 | lgfrl\t%0,%1" | |
4587 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4588 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4589 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4590 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4591 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4592 | |
9db1d521 | 4593 | ; |
56477c21 | 4594 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4595 | ; |
4596 | ||
56477c21 AS |
4597 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4598 | [(set (match_operand:DSI 0 "register_operand" "") | |
4599 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4600 | "" |
4023fb28 | 4601 | { |
9602b6a1 | 4602 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4603 | { |
4604 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4605 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4606 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4607 | DONE; | |
4608 | } | |
ec24698e | 4609 | else if (!TARGET_EXTIMM) |
4023fb28 | 4610 | { |
2542ef05 | 4611 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4612 | |
4613 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4614 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4615 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4616 | DONE; |
4617 | } | |
ec24698e UW |
4618 | }) |
4619 | ||
56477c21 AS |
4620 | ; |
4621 | ; extendhidi2 instruction pattern(s). | |
4622 | ; | |
4623 | ||
ec24698e | 4624 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4625 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4626 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4627 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4628 | "@ |
4629 | lghr\t%0,%1 | |
963fc8d0 AK |
4630 | lgh\t%0,%1 |
4631 | lghrl\t%0,%1" | |
4632 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4633 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4634 | (set_attr "cpu_facility" "extimm,extimm,z10") |
14cfceb7 IL |
4635 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4636 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 UW |
4637 | |
4638 | (define_insn "*extendhidi2" | |
9db1d521 | 4639 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4640 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4641 | "TARGET_ZARCH" |
d40c829f | 4642 | "lgh\t%0,%1" |
9381e3f1 WG |
4643 | [(set_attr "op_type" "RXY") |
4644 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4645 | |
9db1d521 | 4646 | ; |
56477c21 | 4647 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4648 | ; |
4649 | ||
ec24698e | 4650 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4651 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4652 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4653 | "TARGET_EXTIMM" |
4654 | "@ | |
4655 | lhr\t%0,%1 | |
4656 | lh\t%0,%1 | |
963fc8d0 AK |
4657 | lhy\t%0,%1 |
4658 | lhrl\t%0,%1" | |
4659 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4660 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 | 4661 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
14cfceb7 IL |
4662 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1") |
4663 | (set_attr "relative_long" "*,*,*,yes")]) | |
9db1d521 | 4664 | |
4023fb28 | 4665 | (define_insn "*extendhisi2" |
d3632d41 UW |
4666 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4667 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4668 | "!TARGET_EXTIMM" |
d3632d41 | 4669 | "@ |
d40c829f UW |
4670 | lh\t%0,%1 |
4671 | lhy\t%0,%1" | |
9381e3f1 | 4672 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4673 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4674 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4675 | |
56477c21 AS |
4676 | ; |
4677 | ; extendqi(si|di)2 instruction pattern(s). | |
4678 | ; | |
4679 | ||
43a09b63 | 4680 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4681 | (define_insn "*extendqi<mode>2_extimm" |
4682 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4683 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4684 | "TARGET_EXTIMM" |
4685 | "@ | |
56477c21 AS |
4686 | l<g>br\t%0,%1 |
4687 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4688 | [(set_attr "op_type" "RRE,RXY") |
4689 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4690 | |
43a09b63 | 4691 | ; lb, lgb |
56477c21 AS |
4692 | (define_insn "*extendqi<mode>2" |
4693 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4694 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4695 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4696 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4697 | [(set_attr "op_type" "RXY") |
4698 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4699 | |
56477c21 AS |
4700 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4701 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4702 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4703 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4704 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4705 | "#" |
4706 | "&& reload_completed" | |
4023fb28 | 4707 | [(parallel |
56477c21 | 4708 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4709 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4710 | (parallel |
56477c21 | 4711 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4712 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4713 | { |
4714 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4715 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4716 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4717 | }) |
9db1d521 | 4718 | |
9db1d521 HP |
4719 | ; |
4720 | ; zero_extendsidi2 instruction pattern(s). | |
4721 | ; | |
4722 | ||
4023fb28 UW |
4723 | (define_expand "zero_extendsidi2" |
4724 | [(set (match_operand:DI 0 "register_operand" "") | |
4725 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4726 | "" | |
4023fb28 | 4727 | { |
9602b6a1 | 4728 | if (!TARGET_ZARCH) |
4023fb28 | 4729 | { |
c41c1387 | 4730 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4731 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4732 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4733 | DONE; |
4734 | } | |
ec24698e | 4735 | }) |
4023fb28 UW |
4736 | |
4737 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4738 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4739 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4740 | "TARGET_ZARCH" |
9db1d521 | 4741 | "@ |
d40c829f | 4742 | llgfr\t%0,%1 |
963fc8d0 AK |
4743 | llgf\t%0,%1 |
4744 | llgfrl\t%0,%1" | |
4745 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4746 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4747 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4748 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3") |
4749 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4750 | |
288e517f AK |
4751 | ; |
4752 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4753 | ; | |
4754 | ||
d6083c7d UW |
4755 | (define_insn "*llgt_sidi" |
4756 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4757 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4758 | (const_int 2147483647)))] |
9602b6a1 | 4759 | "TARGET_ZARCH" |
d6083c7d | 4760 | "llgt\t%0,%1" |
9381e3f1 WG |
4761 | [(set_attr "op_type" "RXE") |
4762 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4763 | |
4764 | (define_insn_and_split "*llgt_sidi_split" | |
4765 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4766 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4767 | (const_int 2147483647))) |
ae156f85 | 4768 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4769 | "TARGET_ZARCH" |
d6083c7d UW |
4770 | "#" |
4771 | "&& reload_completed" | |
4772 | [(set (match_dup 0) | |
4773 | (and:DI (subreg:DI (match_dup 1) 0) | |
4774 | (const_int 2147483647)))] | |
4775 | "") | |
4776 | ||
288e517f AK |
4777 | (define_insn "*llgt_sisi" |
4778 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4779 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4780 | (const_int 2147483647)))] |
c4d50129 | 4781 | "TARGET_ZARCH" |
288e517f AK |
4782 | "@ |
4783 | llgtr\t%0,%1 | |
4784 | llgt\t%0,%1" | |
9381e3f1 WG |
4785 | [(set_attr "op_type" "RRE,RXE") |
4786 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4787 | |
288e517f AK |
4788 | (define_insn "*llgt_didi" |
4789 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4790 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4791 | (const_int 2147483647)))] | |
9602b6a1 | 4792 | "TARGET_ZARCH" |
288e517f AK |
4793 | "@ |
4794 | llgtr\t%0,%1 | |
4795 | llgt\t%0,%N1" | |
9381e3f1 WG |
4796 | [(set_attr "op_type" "RRE,RXE") |
4797 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4798 | |
f19a9af7 | 4799 | (define_split |
9602b6a1 AK |
4800 | [(set (match_operand:DSI 0 "register_operand" "") |
4801 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4802 | (const_int 2147483647))) |
ae156f85 | 4803 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4804 | "TARGET_ZARCH && reload_completed" |
288e517f | 4805 | [(set (match_dup 0) |
9602b6a1 | 4806 | (and:DSI (match_dup 1) |
f6ee577c | 4807 | (const_int 2147483647)))] |
288e517f AK |
4808 | "") |
4809 | ||
9db1d521 | 4810 | ; |
56477c21 | 4811 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4812 | ; |
4813 | ||
56477c21 AS |
4814 | (define_expand "zero_extend<mode>di2" |
4815 | [(set (match_operand:DI 0 "register_operand" "") | |
4816 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4817 | "" | |
4818 | { | |
9602b6a1 | 4819 | if (!TARGET_ZARCH) |
56477c21 AS |
4820 | { |
4821 | rtx tmp = gen_reg_rtx (SImode); | |
4822 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4823 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4824 | DONE; | |
4825 | } | |
4826 | else if (!TARGET_EXTIMM) | |
4827 | { | |
2542ef05 | 4828 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4829 | operands[1] = gen_lowpart (DImode, operands[1]); |
4830 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4831 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4832 | DONE; | |
4833 | } | |
4834 | }) | |
4835 | ||
f6ee577c | 4836 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4837 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4838 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4839 | "" |
4023fb28 | 4840 | { |
ec24698e UW |
4841 | if (!TARGET_EXTIMM) |
4842 | { | |
4843 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4844 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4845 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4846 | DONE; |
56477c21 | 4847 | } |
ec24698e UW |
4848 | }) |
4849 | ||
963fc8d0 AK |
4850 | ; llhrl, llghrl |
4851 | (define_insn "*zero_extendhi<mode>2_z10" | |
4852 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4853 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4854 | "TARGET_Z10" |
4855 | "@ | |
4856 | ll<g>hr\t%0,%1 | |
4857 | ll<g>h\t%0,%1 | |
4858 | ll<g>hrl\t%0,%1" | |
4859 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4860 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4861 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4862 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3") |
4863 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 | 4864 | |
43a09b63 | 4865 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4866 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4867 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4868 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4869 | "TARGET_EXTIMM" |
4870 | "@ | |
56477c21 AS |
4871 | ll<g><hc>r\t%0,%1 |
4872 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4873 | [(set_attr "op_type" "RRE,RXY") |
4874 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4875 | |
43a09b63 | 4876 | ; llgh, llgc |
56477c21 AS |
4877 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4878 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4879 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4880 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4881 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4882 | [(set_attr "op_type" "RXY") |
4883 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4884 | |
4885 | (define_insn_and_split "*zero_extendhisi2_31" | |
4886 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4887 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4888 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4889 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4890 | "#" |
4891 | "&& reload_completed" | |
4892 | [(set (match_dup 0) (const_int 0)) | |
4893 | (parallel | |
4894 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4895 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4896 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4897 | |
cc7ab9b7 UW |
4898 | (define_insn_and_split "*zero_extendqisi2_31" |
4899 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4900 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4901 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4902 | "#" |
4903 | "&& reload_completed" | |
4904 | [(set (match_dup 0) (const_int 0)) | |
4905 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4906 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4907 | |
9db1d521 HP |
4908 | ; |
4909 | ; zero_extendqihi2 instruction pattern(s). | |
4910 | ; | |
4911 | ||
9db1d521 HP |
4912 | (define_expand "zero_extendqihi2" |
4913 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4914 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4915 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4916 | { |
4023fb28 UW |
4917 | operands[1] = gen_lowpart (HImode, operands[1]); |
4918 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4919 | DONE; | |
ec24698e | 4920 | }) |
9db1d521 | 4921 | |
4023fb28 | 4922 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4923 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4924 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4925 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4926 | "llgc\t%0,%1" |
9381e3f1 WG |
4927 | [(set_attr "op_type" "RXY") |
4928 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4929 | |
cc7ab9b7 UW |
4930 | (define_insn_and_split "*zero_extendqihi2_31" |
4931 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4932 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4933 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4934 | "#" |
4935 | "&& reload_completed" | |
4936 | [(set (match_dup 0) (const_int 0)) | |
4937 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4938 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4939 | |
609e7e80 | 4940 | ; |
9751ad6e | 4941 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4942 | ; |
4943 | ||
9751ad6e AK |
4944 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4945 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4946 | ; or emits the default pattern otherwise. | |
4947 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4948 | [(parallel |
9751ad6e AK |
4949 | [(set (match_operand:GPR 0 "register_operand" "") |
4950 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4951 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4952 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4953 | "TARGET_HARD_FLOAT" |
609e7e80 | 4954 | { |
65b1d8ea AK |
4955 | if (!TARGET_Z196) |
4956 | { | |
9751ad6e AK |
4957 | /* We don't provide emulation for TD|DD->SI. */ |
4958 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4959 | && <GPR:MODE>mode == SImode) | |
4960 | FAIL; | |
4961 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4962 | operands[1])); | |
65b1d8ea AK |
4963 | DONE; |
4964 | } | |
9751ad6e AK |
4965 | |
4966 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4967 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4968 | else | |
4969 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4970 | }) |
4971 | ||
9751ad6e AK |
4972 | ; (sf|df|tf)->unsigned (si|di) |
4973 | ||
4974 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4975 | ; machines. | |
4976 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4977 | [(parallel | |
4978 | [(set (match_operand:GPR 0 "register_operand" "") | |
4979 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4980 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4981 | (clobber (reg:CC CC_REGNUM))])] | |
4982 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4983 | { | |
4984 | rtx_code_label *label1 = gen_label_rtx (); | |
4985 | rtx_code_label *label2 = gen_label_rtx (); | |
4986 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4987 | REAL_VALUE_TYPE cmp, sub; | |
4988 | ||
4989 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4990 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4991 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4992 | ||
4993 | emit_cmp_and_jump_insns (operands[1], | |
4994 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4995 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4996 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4997 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4998 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4999 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
5000 | emit_jump (label2); | |
5001 | ||
5002 | emit_label (label1); | |
5003 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
5004 | operands[1], | |
5005 | GEN_INT (BFP_RND_TOWARD_0))); | |
5006 | emit_label (label2); | |
5007 | DONE; | |
5008 | }) | |
5009 | ||
5010 | ; dd->unsigned di | |
5011 | ||
5012 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
5013 | ; machines. | |
5014 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
5015 | [(parallel |
5016 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 5017 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 5018 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
5019 | (clobber (reg:CC CC_REGNUM))])] |
5020 | ||
9751ad6e | 5021 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 5022 | { |
9751ad6e AK |
5023 | rtx_code_label *label1 = gen_label_rtx (); |
5024 | rtx_code_label *label2 = gen_label_rtx (); | |
5025 | rtx temp = gen_reg_rtx (TDmode); | |
5026 | REAL_VALUE_TYPE cmp, sub; | |
5027 | ||
5028 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
5029 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
5030 | ||
5031 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
5032 | solution is doing the check and the subtraction in TD mode and using a | |
5033 | TD -> DI convert afterwards. */ | |
5034 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
5035 | temp = force_reg (TDmode, temp); | |
5036 | emit_cmp_and_jump_insns (temp, | |
5037 | const_double_from_real_value (cmp, TDmode), | |
5038 | LT, NULL_RTX, VOIDmode, 0, label1); | |
5039 | emit_insn (gen_subtd3 (temp, temp, | |
5040 | const_double_from_real_value (sub, TDmode))); | |
5041 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
5042 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
5043 | emit_jump (label2); | |
5044 | ||
5045 | emit_label (label1); | |
5046 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
5047 | GEN_INT (DFP_RND_TOWARD_0))); | |
5048 | emit_label (label2); | |
5049 | DONE; | |
609e7e80 | 5050 | }) |
cc7ab9b7 | 5051 | |
9751ad6e | 5052 | ; td->unsigned di |
9db1d521 | 5053 | |
9751ad6e AK |
5054 | ; Emulate the unsigned conversion with the signed version for pre z196 |
5055 | ; machines. | |
5056 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 5057 | [(parallel |
9751ad6e AK |
5058 | [(set (match_operand:DI 0 "register_operand" "") |
5059 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
5060 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 5061 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5062 | |
5063 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 5064 | { |
9751ad6e AK |
5065 | rtx_code_label *label1 = gen_label_rtx (); |
5066 | rtx_code_label *label2 = gen_label_rtx (); | |
5067 | rtx temp = gen_reg_rtx (TDmode); | |
5068 | REAL_VALUE_TYPE cmp, sub; | |
5069 | ||
5070 | operands[1] = force_reg (TDmode, operands[1]); | |
5071 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
5072 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
5073 | ||
5074 | emit_cmp_and_jump_insns (operands[1], | |
5075 | const_double_from_real_value (cmp, TDmode), | |
5076 | LT, NULL_RTX, VOIDmode, 0, label1); | |
5077 | emit_insn (gen_subtd3 (temp, operands[1], | |
5078 | const_double_from_real_value (sub, TDmode))); | |
5079 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
5080 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
5081 | emit_jump (label2); | |
5082 | ||
5083 | emit_label (label1); | |
5084 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
5085 | GEN_INT (DFP_RND_TOWARD_0))); | |
5086 | emit_label (label2); | |
5087 | DONE; | |
10bbf137 | 5088 | }) |
9db1d521 | 5089 | |
9751ad6e AK |
5090 | ; Just a dummy to make the code in the first expander a bit easier. |
5091 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
5092 | [(parallel |
5093 | [(set (match_operand:SI 0 "register_operand" "") | |
5094 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 5095 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 5096 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5097 | |
5098 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
5099 | { | |
5100 | FAIL; | |
5101 | }) | |
5102 | ||
65b1d8ea AK |
5103 | |
5104 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
5105 | ||
026bfe89 AK |
5106 | ; df -> unsigned di, vxe2: sf -> unsigned si |
5107 | ; clgdbr, clfebr, wclgdb, wclfeb | |
5108 | (define_insn "*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13" | |
5109 | [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v") | |
5110 | (unsigned_fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v"))) | |
5111 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
6e5b5de8 | 5112 | (clobber (reg:CC CC_REGNUM))] |
026bfe89 AK |
5113 | "TARGET_VX && TARGET_HARD_FLOAT |
5114 | && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" | |
9751ad6e | 5115 | "@ |
026bfe89 AK |
5116 | cl<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1,0 |
5117 | wcl<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2" | |
9751ad6e AK |
5118 | [(set_attr "op_type" "RRF,VRR") |
5119 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 5120 | |
9751ad6e | 5121 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
5122 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
5123 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
5124 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
5125 | [(set (match_operand:GPR 0 "register_operand" "=d") |
5126 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
5127 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 5128 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 5129 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 5130 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
5131 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
5132 | [(set_attr "op_type" "RRF") | |
5133 | (set_attr "type" "ftoi")]) | |
5134 | ||
b60cb710 AK |
5135 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
5136 | [(set (match_operand:GPR 0 "register_operand" "") | |
5137 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
5138 | "TARGET_HARD_FLOAT" | |
9db1d521 | 5139 | { |
b60cb710 | 5140 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 5141 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 5142 | DONE; |
10bbf137 | 5143 | }) |
9db1d521 | 5144 | |
026bfe89 AK |
5145 | ; df -> signed di, vxe2: sf -> signed si |
5146 | ; cgdbr, cfebr, wcgdb, wcfeb | |
5147 | (define_insn "*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13" | |
5148 | [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v") | |
5149 | (fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v"))) | |
5150 | (unspec:VX_CONV_INT [(match_operand:VX_CONV_INT 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
6e5b5de8 | 5151 | (clobber (reg:CC CC_REGNUM))] |
026bfe89 AK |
5152 | "TARGET_VX && TARGET_HARD_FLOAT |
5153 | && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" | |
6e5b5de8 | 5154 | "@ |
026bfe89 AK |
5155 | c<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1 |
5156 | wc<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2" | |
6e5b5de8 AK |
5157 | [(set_attr "op_type" "RRE,VRR") |
5158 | (set_attr "type" "ftoi")]) | |
5159 | ||
43a09b63 | 5160 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
5161 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5162 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5163 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5164 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 5165 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
5166 | "TARGET_HARD_FLOAT |
5167 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 5168 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 5169 | [(set_attr "op_type" "RRE") |
077dab3b | 5170 | (set_attr "type" "ftoi")]) |
9db1d521 | 5171 | |
6e5b5de8 AK |
5172 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5173 | [(parallel | |
5174 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5175 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5176 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5177 | (clobber (reg:CC CC_REGNUM))])] | |
5178 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
5179 | ; |
5180 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
5181 | ; | |
5182 | ||
99cd7dd0 AK |
5183 | (define_expand "fix_trunc<mode>di2" |
5184 | [(set (match_operand:DI 0 "register_operand" "") | |
5185 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 5186 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
5187 | { |
5188 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
5189 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 5190 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
5191 | DONE; |
5192 | }) | |
5193 | ||
609e7e80 | 5194 | ; cgxtr, cgdtr |
99cd7dd0 | 5195 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
5196 | [(set (match_operand:DI 0 "register_operand" "=d") |
5197 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
5198 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5199 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5200 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5201 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5202 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5203 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5204 | |
5205 | ||
f61a2c7d AK |
5206 | ; |
5207 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5208 | ; | |
5209 | ||
5210 | (define_expand "fix_trunctf<mode>2" | |
5211 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5212 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5213 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5214 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5215 | "TARGET_HARD_FLOAT" |
142cd70f | 5216 | "") |
9db1d521 | 5217 | |
9db1d521 | 5218 | |
9db1d521 | 5219 | ; |
142cd70f | 5220 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5221 | ; |
5222 | ||
609e7e80 | 5223 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5224 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5225 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5226 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5227 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5228 | "@ |
5229 | c<xde>g<bt>r\t%0,%1 | |
5230 | wcdgb\t%v0,%v1,0,0" | |
5231 | [(set_attr "op_type" "RRE,VRR") | |
5232 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5233 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5234 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5235 | |
026bfe89 | 5236 | ; cxfbr, cdfbr, cefbr, wcefb |
142cd70f | 5237 | (define_insn "floatsi<mode>2" |
026bfe89 AK |
5238 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
5239 | (float:BFP (match_operand:SI 1 "register_operand" "d,v")))] | |
142cd70f | 5240 | "TARGET_HARD_FLOAT" |
026bfe89 AK |
5241 | "@ |
5242 | c<xde>fbr\t%0,%1 | |
5243 | wcefb\t%v0,%v1,0,0" | |
5244 | [(set_attr "op_type" "RRE,VRR") | |
5245 | (set_attr "type" "itof<mode>" ) | |
5246 | (set_attr "cpu_facility" "*,vxe2") | |
5247 | (set_attr "enabled" "*,<SFSI>")]) | |
f61a2c7d | 5248 | |
65b1d8ea AK |
5249 | ; cxftr, cdftr |
5250 | (define_insn "floatsi<mode>2" | |
5251 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5252 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5253 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5254 | "c<xde>ftr\t%0,0,%1,0" | |
5255 | [(set_attr "op_type" "RRE") | |
5256 | (set_attr "type" "itof<mode>" )]) | |
5257 | ||
5258 | ; | |
5259 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5260 | ; | |
5261 | ||
026bfe89 AK |
5262 | (define_insn "*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13" |
5263 | [(set (match_operand:VX_CONV_BFP 0 "register_operand" "=f,v") | |
5264 | (unsigned_float:VX_CONV_BFP (match_operand:VX_CONV_INT 1 "register_operand" "d,v")))] | |
5265 | "TARGET_VX && TARGET_HARD_FLOAT | |
5266 | && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" | |
6e5b5de8 | 5267 | "@ |
026bfe89 AK |
5268 | c<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>br\t%0,0,%1,0 |
5269 | wc<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>b\t%v0,%v1,0,0" | |
6e5b5de8 AK |
5270 | [(set_attr "op_type" "RRE,VRR") |
5271 | (set_attr "type" "itofdf")]) | |
5272 | ||
65b1d8ea AK |
5273 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5274 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5275 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5276 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5277 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5278 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5279 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5280 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5281 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5282 | (set_attr "type" "itof<FP:mode>")]) |
5283 | ||
5284 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5285 | [(set (match_operand:FP 0 "register_operand" "") | |
5286 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5287 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5288 | |
9db1d521 HP |
5289 | ; |
5290 | ; truncdfsf2 instruction pattern(s). | |
5291 | ; | |
5292 | ||
142cd70f | 5293 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5294 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5295 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5296 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5297 | "@ |
5298 | ledbr\t%0,%1 | |
5299 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5300 | ; According to BFP rounding mode | |
5301 | [(set_attr "op_type" "RRE,VRR") | |
5302 | (set_attr "type" "ftruncdf") | |
285363a1 | 5303 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5304 | |
f61a2c7d | 5305 | ; |
142cd70f | 5306 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5307 | ; |
5308 | ||
142cd70f AK |
5309 | ; ldxbr, lexbr |
5310 | (define_insn "trunctf<mode>2" | |
5311 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5312 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5313 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5314 | "TARGET_HARD_FLOAT" |
5315 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5316 | [(set_attr "length" "6") |
9381e3f1 | 5317 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5318 | |
609e7e80 AK |
5319 | ; |
5320 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5321 | ; | |
5322 | ||
432d4670 AK |
5323 | |
5324 | (define_expand "trunctddd2" | |
5325 | [(parallel | |
5326 | [(set (match_operand:DD 0 "register_operand" "") | |
5327 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5328 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5329 | (clobber (scratch:TD))])] | |
5330 | "TARGET_HARD_DFP") | |
5331 | ||
5332 | (define_insn "*trunctddd2" | |
609e7e80 | 5333 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5334 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5335 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5336 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5337 | "TARGET_HARD_DFP" |
432d4670 | 5338 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5339 | [(set_attr "length" "6") |
9381e3f1 | 5340 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5341 | |
5342 | (define_insn "truncddsd2" | |
5343 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5344 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5345 | "TARGET_HARD_DFP" |
609e7e80 AK |
5346 | "ledtr\t%0,0,%1,0" |
5347 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5348 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5349 | |
feade5a8 AK |
5350 | (define_expand "trunctdsd2" |
5351 | [(parallel | |
d5a216fa | 5352 | [(set (match_dup 2) |
feade5a8 | 5353 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5354 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5355 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5356 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5357 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5358 | "TARGET_HARD_DFP" |
5359 | { | |
d5a216fa | 5360 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5361 | }) |
5362 | ||
9db1d521 | 5363 | ; |
142cd70f | 5364 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5365 | ; |
5366 | ||
2de2b3f9 | 5367 | ; wflls |
6e5b5de8 AK |
5368 | (define_insn "*extendsfdf2_z13" |
5369 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5370 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5371 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5372 | "@ |
5373 | ldebr\t%0,%1 | |
5374 | ldeb\t%0,%1 | |
5375 | wldeb\t%v0,%v1" | |
5376 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5377 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5378 | ||
142cd70f | 5379 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5380 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5381 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5382 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5383 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5384 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5385 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5386 | "@ |
142cd70f AK |
5387 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5388 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5389 | [(set_attr "op_type" "RRE,RXE") |
5390 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5391 | ||
5392 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5393 | [(set (match_operand:BFP 0 "register_operand" "") | |
5394 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5395 | "TARGET_HARD_FLOAT | |
5396 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5397 | |
609e7e80 AK |
5398 | ; |
5399 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5400 | ; | |
5401 | ||
5402 | (define_insn "extendddtd2" | |
5403 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5404 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5405 | "TARGET_HARD_DFP" |
609e7e80 AK |
5406 | "lxdtr\t%0,%1,0" |
5407 | [(set_attr "op_type" "RRF") | |
5408 | (set_attr "type" "fsimptf")]) | |
5409 | ||
5410 | (define_insn "extendsddd2" | |
5411 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5412 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5413 | "TARGET_HARD_DFP" |
609e7e80 AK |
5414 | "ldetr\t%0,%1,0" |
5415 | [(set_attr "op_type" "RRF") | |
5416 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5417 | |
feade5a8 AK |
5418 | (define_expand "extendsdtd2" |
5419 | [(set (match_dup 2) | |
5420 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5421 | (set (match_operand:TD 0 "register_operand" "") | |
5422 | (float_extend:TD (match_dup 2)))] | |
5423 | "TARGET_HARD_DFP" | |
5424 | { | |
5425 | operands[2] = gen_reg_rtx (DDmode); | |
5426 | }) | |
5427 | ||
d12a76f3 AK |
5428 | ; Binary Floating Point - load fp integer |
5429 | ||
5430 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5431 | ; For all of them the inexact exceptions are suppressed. | |
5432 | ||
5433 | ; fiebra, fidbra, fixbra | |
5434 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5435 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5436 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5437 | FPINT))] | |
5438 | "TARGET_Z196" | |
5439 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5440 | [(set_attr "op_type" "RRF") | |
5441 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5442 | ||
5443 | ; rint is supposed to raise an inexact exception so we can use the | |
5444 | ; older instructions. | |
5445 | ||
5446 | ; fiebr, fidbr, fixbr | |
5447 | (define_insn "rint<BFP:mode>2" | |
5448 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5449 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5450 | UNSPEC_FPINT_RINT))] | |
5451 | "" | |
5452 | "fi<BFP:xde>br\t%0,0,%1" | |
5453 | [(set_attr "op_type" "RRF") | |
5454 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5455 | ||
5456 | ||
5457 | ; Decimal Floating Point - load fp integer | |
5458 | ||
5459 | ; fidtr, fixtr | |
5460 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5461 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5462 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5463 | FPINT))] | |
5464 | "TARGET_HARD_DFP" | |
5465 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5466 | [(set_attr "op_type" "RRF") | |
5467 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5468 | ||
5469 | ; fidtr, fixtr | |
5470 | (define_insn "rint<DFP:mode>2" | |
5471 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5472 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5473 | UNSPEC_FPINT_RINT))] | |
5474 | "TARGET_HARD_DFP" | |
5475 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5476 | [(set_attr "op_type" "RRF") | |
5477 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5478 | ||
5479 | ; | |
35dd9a0e AK |
5480 | ; Binary <-> Decimal floating point trunc patterns |
5481 | ; | |
5482 | ||
5483 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5484 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5485 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5486 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5487 | (clobber (reg:CC CC_REGNUM)) |
5488 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5489 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5490 | "pfpo") |
5491 | ||
5492 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5493 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5494 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5495 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5496 | (clobber (reg:CC CC_REGNUM)) |
5497 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5498 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5499 | "pfpo") |
5500 | ||
5501 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5502 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5503 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5504 | (parallel | |
5505 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5506 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5507 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5508 | (clobber (reg:CC CC_REGNUM)) |
5509 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5510 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5511 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5512 | "TARGET_HARD_DFP |
35dd9a0e AK |
5513 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5514 | { | |
5515 | HOST_WIDE_INT flags; | |
5516 | ||
ced8d882 AK |
5517 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5518 | rounding mode of the target format needs to be used. */ | |
5519 | ||
35dd9a0e AK |
5520 | flags = (PFPO_CONVERT | |
5521 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5522 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5523 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5524 | |
5525 | operands[2] = GEN_INT (flags); | |
5526 | }) | |
5527 | ||
5528 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5529 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5530 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5531 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5532 | (parallel | |
2cf4c39e | 5533 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5534 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5535 | (clobber (reg:CC CC_REGNUM)) |
5536 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5537 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5538 | "TARGET_HARD_DFP |
35dd9a0e AK |
5539 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5540 | { | |
5541 | HOST_WIDE_INT flags; | |
5542 | ||
ced8d882 AK |
5543 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5544 | rounding mode of the target format needs to be used. */ | |
5545 | ||
35dd9a0e AK |
5546 | flags = (PFPO_CONVERT | |
5547 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5548 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5549 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5550 | |
5551 | operands[2] = GEN_INT (flags); | |
5552 | }) | |
5553 | ||
5554 | ; | |
5555 | ; Binary <-> Decimal floating point extend patterns | |
5556 | ; | |
5557 | ||
5558 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5559 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5560 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5561 | (clobber (reg:CC CC_REGNUM)) |
5562 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5563 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5564 | "pfpo") |
5565 | ||
5566 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5567 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5568 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5569 | (clobber (reg:CC CC_REGNUM)) |
5570 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5571 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5572 | "pfpo") |
5573 | ||
5574 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5575 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5576 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5577 | (parallel | |
5578 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5579 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5580 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5581 | (clobber (reg:CC CC_REGNUM)) |
5582 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5583 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5584 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5585 | "TARGET_HARD_DFP |
35dd9a0e AK |
5586 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5587 | { | |
5588 | HOST_WIDE_INT flags; | |
5589 | ||
ced8d882 AK |
5590 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5591 | rounding mode of the target format needs to be used. */ | |
5592 | ||
35dd9a0e AK |
5593 | flags = (PFPO_CONVERT | |
5594 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5595 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5596 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5597 | |
5598 | operands[2] = GEN_INT (flags); | |
5599 | }) | |
5600 | ||
5601 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5602 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5603 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5604 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5605 | (parallel | |
2cf4c39e | 5606 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5607 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5608 | (clobber (reg:CC CC_REGNUM)) |
5609 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5610 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5611 | "TARGET_HARD_DFP |
35dd9a0e AK |
5612 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5613 | { | |
5614 | HOST_WIDE_INT flags; | |
5615 | ||
ced8d882 AK |
5616 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5617 | rounding mode of the target format needs to be used. */ | |
5618 | ||
35dd9a0e AK |
5619 | flags = (PFPO_CONVERT | |
5620 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5621 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5622 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5623 | |
5624 | operands[2] = GEN_INT (flags); | |
5625 | }) | |
5626 | ||
5627 | ||
9db1d521 | 5628 | ;; |
fae778eb | 5629 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5630 | ;; |
fae778eb | 5631 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5632 | ; because of unpredictable Bits in Register for Halfword and Byte |
5633 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5634 | ||
07893d4f UW |
5635 | ;; |
5636 | ;;- Add instructions. | |
5637 | ;; | |
5638 | ||
1c7b1b7e UW |
5639 | ; |
5640 | ; addti3 instruction pattern(s). | |
5641 | ; | |
5642 | ||
085261c8 AK |
5643 | (define_expand "addti3" |
5644 | [(parallel | |
5645 | [(set (match_operand:TI 0 "register_operand" "") | |
5646 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5647 | (match_operand:TI 2 "general_operand" "") ) ) | |
5648 | (clobber (reg:CC CC_REGNUM))])] | |
5649 | "TARGET_ZARCH" | |
5650 | { | |
5651 | /* For z13 we have vaq which doesn't set CC. */ | |
5652 | if (TARGET_VX) | |
5653 | { | |
5654 | emit_insn (gen_rtx_SET (operands[0], | |
5655 | gen_rtx_PLUS (TImode, | |
5656 | copy_to_mode_reg (TImode, operands[1]), | |
5657 | copy_to_mode_reg (TImode, operands[2])))); | |
5658 | DONE; | |
5659 | } | |
5660 | }) | |
5661 | ||
5662 | (define_insn_and_split "*addti3" | |
5663 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5664 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5665 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5666 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5667 | "TARGET_ZARCH" |
1c7b1b7e UW |
5668 | "#" |
5669 | "&& reload_completed" | |
5670 | [(parallel | |
ae156f85 | 5671 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5672 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5673 | (match_dup 7))) | |
5674 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5675 | (parallel | |
a94a76a7 UW |
5676 | [(set (match_dup 3) (plus:DI |
5677 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5678 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5679 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5680 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5681 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5682 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5683 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5684 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5685 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5686 | [(set_attr "op_type" "*") | |
5687 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5688 | |
07893d4f UW |
5689 | ; |
5690 | ; adddi3 instruction pattern(s). | |
5691 | ; | |
5692 | ||
3298c037 AK |
5693 | (define_expand "adddi3" |
5694 | [(parallel | |
963fc8d0 | 5695 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5696 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5697 | (match_operand:DI 2 "general_operand" ""))) | |
5698 | (clobber (reg:CC CC_REGNUM))])] | |
5699 | "" | |
5700 | "") | |
5701 | ||
07893d4f UW |
5702 | (define_insn "*adddi3_sign" |
5703 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5704 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5705 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5706 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5707 | "TARGET_ZARCH" |
07893d4f | 5708 | "@ |
d40c829f UW |
5709 | agfr\t%0,%2 |
5710 | agf\t%0,%2" | |
65b1d8ea AK |
5711 | [(set_attr "op_type" "RRE,RXY") |
5712 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5713 | |
5714 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5715 | [(set (reg CC_REGNUM) |
3e4be43f | 5716 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5717 | (match_operand:DI 1 "register_operand" "0,0")) |
5718 | (const_int 0))) | |
5719 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5720 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5721 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5722 | "@ |
d40c829f UW |
5723 | algfr\t%0,%2 |
5724 | algf\t%0,%2" | |
9381e3f1 WG |
5725 | [(set_attr "op_type" "RRE,RXY") |
5726 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5727 | |
5728 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5729 | [(set (reg CC_REGNUM) |
3e4be43f | 5730 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5731 | (match_operand:DI 1 "register_operand" "0,0")) |
5732 | (const_int 0))) | |
5733 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5734 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5735 | "@ |
d40c829f UW |
5736 | algfr\t%0,%2 |
5737 | algf\t%0,%2" | |
9381e3f1 WG |
5738 | [(set_attr "op_type" "RRE,RXY") |
5739 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5740 | |
5741 | (define_insn "*adddi3_zero" | |
5742 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5743 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5744 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5745 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5746 | "TARGET_ZARCH" |
07893d4f | 5747 | "@ |
d40c829f UW |
5748 | algfr\t%0,%2 |
5749 | algf\t%0,%2" | |
9381e3f1 WG |
5750 | [(set_attr "op_type" "RRE,RXY") |
5751 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5752 | |
e69166de | 5753 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5754 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5755 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5756 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5757 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 5758 | "!TARGET_ZARCH" |
e69166de UW |
5759 | "#" |
5760 | "&& reload_completed" | |
5761 | [(parallel | |
ae156f85 | 5762 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5763 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5764 | (match_dup 7))) | |
5765 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5766 | (parallel | |
a94a76a7 UW |
5767 | [(set (match_dup 3) (plus:SI |
5768 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5769 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5770 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5771 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5772 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5773 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5774 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5775 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5776 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5777 | |
3298c037 AK |
5778 | ; |
5779 | ; addsi3 instruction pattern(s). | |
5780 | ; | |
5781 | ||
5782 | (define_expand "addsi3" | |
07893d4f | 5783 | [(parallel |
963fc8d0 | 5784 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5785 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5786 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5787 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5788 | "" |
07893d4f | 5789 | "") |
9db1d521 | 5790 | |
3298c037 AK |
5791 | (define_insn "*addsi3_sign" |
5792 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5793 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5794 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5795 | (clobber (reg:CC CC_REGNUM))] | |
5796 | "" | |
5797 | "@ | |
5798 | ah\t%0,%2 | |
5799 | ahy\t%0,%2" | |
65b1d8ea | 5800 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5801 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5802 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5803 | |
9db1d521 | 5804 | ; |
3298c037 | 5805 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5806 | ; |
9db1d521 | 5807 | |
65b1d8ea | 5808 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5809 | (define_insn "*add<mode>3" |
3e4be43f UW |
5810 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5811 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5812 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5813 | (clobber (reg:CC CC_REGNUM))] |
5814 | "" | |
ec24698e | 5815 | "@ |
3298c037 | 5816 | a<g>r\t%0,%2 |
65b1d8ea | 5817 | a<g>rk\t%0,%1,%2 |
3298c037 | 5818 | a<g>hi\t%0,%h2 |
65b1d8ea | 5819 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5820 | al<g>fi\t%0,%2 |
5821 | sl<g>fi\t%0,%n2 | |
5822 | a<g>\t%0,%2 | |
963fc8d0 AK |
5823 | a<y>\t%0,%2 |
5824 | a<g>si\t%0,%c2" | |
65b1d8ea | 5825 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5826 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5827 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5828 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5829 | |
65b1d8ea | 5830 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5831 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5832 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5833 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5834 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5835 | (match_dup 1))) |
65b1d8ea | 5836 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5837 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5838 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5839 | "@ |
3298c037 | 5840 | al<g>r\t%0,%2 |
65b1d8ea | 5841 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5842 | al<g>fi\t%0,%2 |
5843 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5844 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5845 | al<g>\t%0,%2 |
963fc8d0 AK |
5846 | al<y>\t%0,%2 |
5847 | al<g>si\t%0,%c2" | |
65b1d8ea | 5848 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5849 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5850 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5851 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5852 | |
65b1d8ea | 5853 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5854 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5855 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5856 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5857 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5858 | (match_dup 1))) |
65b1d8ea | 5859 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5860 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5861 | "@ |
3298c037 | 5862 | al<g>r\t%0,%2 |
65b1d8ea | 5863 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5864 | al<g>\t%0,%2 |
5865 | al<y>\t%0,%2" | |
65b1d8ea | 5866 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5867 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5868 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5869 | |
65b1d8ea | 5870 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5871 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5872 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5873 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5874 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5875 | (match_dup 2))) |
3e4be43f | 5876 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5877 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5878 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5879 | "@ |
3298c037 | 5880 | al<g>r\t%0,%2 |
65b1d8ea | 5881 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5882 | al<g>fi\t%0,%2 |
5883 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5884 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5885 | al<g>\t%0,%2 |
963fc8d0 AK |
5886 | al<y>\t%0,%2 |
5887 | al<g>si\t%0,%c2" | |
65b1d8ea | 5888 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5889 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5890 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5891 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5892 | |
65b1d8ea | 5893 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5894 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5895 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5896 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5897 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5898 | (match_dup 2))) |
65b1d8ea | 5899 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5900 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5901 | "@ |
3298c037 | 5902 | al<g>r\t%0,%2 |
65b1d8ea | 5903 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5904 | al<g>\t%0,%2 |
5905 | al<y>\t%0,%2" | |
65b1d8ea | 5906 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5907 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5908 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5909 | |
65b1d8ea | 5910 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5911 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5912 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5913 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5914 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5915 | (const_int 0))) |
3e4be43f | 5916 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5917 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5918 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5919 | "@ |
3298c037 | 5920 | al<g>r\t%0,%2 |
65b1d8ea | 5921 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5922 | al<g>fi\t%0,%2 |
5923 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5924 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5925 | al<g>\t%0,%2 |
963fc8d0 AK |
5926 | al<y>\t%0,%2 |
5927 | al<g>si\t%0,%c2" | |
65b1d8ea | 5928 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5929 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5930 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5931 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5932 | |
65b1d8ea | 5933 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5934 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5935 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5936 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5937 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5938 | (const_int 0))) |
65b1d8ea | 5939 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5940 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5941 | "@ |
3298c037 | 5942 | al<g>r\t%0,%2 |
65b1d8ea | 5943 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5944 | al<g>\t%0,%2 |
5945 | al<y>\t%0,%2" | |
65b1d8ea | 5946 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5947 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5948 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5949 | |
65b1d8ea | 5950 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5951 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5952 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5953 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5954 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5955 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5956 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5957 | "@ |
3298c037 | 5958 | al<g>r\t%0,%2 |
65b1d8ea | 5959 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5960 | al<g>\t%0,%2 |
5961 | al<y>\t%0,%2" | |
65b1d8ea | 5962 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5963 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5964 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5965 | |
963fc8d0 | 5966 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5967 | (define_insn "*add<mode>3_imm_cc" |
5968 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5969 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5970 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5971 | (const_int 0))) |
3e4be43f | 5972 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5973 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5974 | "s390_match_ccmode (insn, CCAmode) | |
5975 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5976 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5977 | /* Avoid INT32_MIN on 32 bit. */ | |
5978 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5979 | "@ |
3298c037 | 5980 | a<g>hi\t%0,%h2 |
65b1d8ea | 5981 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5982 | a<g>fi\t%0,%2 |
5983 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5984 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5985 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5986 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5987 | |
7d2fd075 AK |
5988 | (define_insn "*adddi3_sign" |
5989 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5990 | (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
5991 | (match_operand:DI 1 "register_operand" "0"))) | |
5992 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 5993 | "TARGET_Z14" |
7d2fd075 AK |
5994 | "agh\t%0,%2" |
5995 | [(set_attr "op_type" "RXY")]) | |
5996 | ||
4caa6bab AK |
5997 | |
5998 | ; Jump to label OP3 if OP1 + OP2 results in a signed overflow | |
5999 | ||
6000 | ; addv_const_operand accepts all constants which can be handled | |
6001 | ; without reloads. These will be handled primarily by | |
6002 | ; "*addv<mode>3_ccoverflow_const" which doesn't provide a register | |
6003 | ; alternative. Hence we have to match the operand exactly. | |
6004 | ; For immediates we have to avoid the SIGN_EXTEND around OP2. | |
6005 | (define_expand "addv<mode>4" | |
6006 | [(parallel | |
6007 | [(set (reg:CCO CC_REGNUM) | |
6008 | (compare:CCO (plus:<DBL> | |
6009 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand")) | |
6010 | (match_dup 4)) | |
6011 | (sign_extend:<DBL> (plus:GPR (match_dup 1) | |
6012 | (match_operand:GPR 2 "general_operand"))))) | |
6013 | (set (match_operand:GPR 0 "nonimmediate_operand") | |
6014 | (plus:GPR (match_dup 1) (match_dup 2)))]) | |
6015 | (set (pc) | |
6016 | (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) | |
6017 | (label_ref (match_operand 3)) | |
6018 | (pc)))] | |
6019 | "" | |
6020 | { | |
6021 | if (CONSTANT_P (operands[2]) | |
6022 | && !addv_const_operand (operands[2], GET_MODE (operands[2]))) | |
6023 | operands[2] = force_reg (<GPR:MODE>mode, operands[2]); | |
6024 | ||
6025 | if (GET_MODE (operands[2]) != VOIDmode) | |
6026 | operands[4] = gen_rtx_SIGN_EXTEND (<DBL>mode, operands[2]); | |
6027 | else | |
6028 | /* This is what CSE does when propagating a constant into the pattern. */ | |
6029 | operands[4] = simplify_unary_operation (SIGN_EXTEND, <GPR:DBL>mode, operands[2], <GPR:MODE>mode); | |
6030 | }) | |
6031 | ||
6032 | ; ark, agrk, ar, ahi, ahik, aghik, a, ay, agr, aghi, ag, asi, agsi | |
6033 | (define_insn "*addv<mode>3_ccoverflow" | |
6034 | [(set (reg CC_REGNUM) | |
6035 | (compare (plus:<DBL> | |
6036 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d,0,0,0")) | |
6037 | (sign_extend:<DBL> (match_operand:GPR 2 "general_operand" " d,d,K,K,R,T,C"))) | |
6038 | (sign_extend:<DBL> (plus:GPR (match_dup 1) (match_dup 2))))) | |
6039 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S") | |
6040 | (plus:GPR (match_dup 1) (match_dup 2)))] | |
6041 | "s390_match_ccmode (insn, CCOmode)" | |
6042 | "@ | |
6043 | a<g>r\t%0,%2 | |
6044 | a<g>rk\t%0,%1,%2 | |
6045 | a<g>hi\t%0,%h2 | |
6046 | a<g>hik\t%0,%1,%h2 | |
6047 | a<g>\t%0,%2 | |
6048 | a<y>\t%0,%2 | |
6049 | a<g>si\t%0,%c2" | |
6050 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RX<Y>,RXY,SIY") | |
6051 | (set_attr "cpu_facility" "*,z196,*,z196,*,longdisp,z10") | |
6052 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*, | |
6053 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
6054 | ||
6055 | ; ahi, aghi, ahik, aghik, asi, agsi | |
6056 | (define_insn "*addv<mode>3_ccoverflow_const" | |
6057 | [(set (reg CC_REGNUM) | |
6058 | (compare (plus:<DBL> | |
6059 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0")) | |
6060 | (match_operand:<DBL> 2 "addv_const_operand" "K,K,C")) | |
6061 | (sign_extend:<DBL> (plus:GPR (match_dup 1) (match_dup 2))))) | |
6062 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,S") | |
6063 | (plus:GPR (match_dup 1) (match_dup 2)))] | |
6064 | "s390_match_ccmode (insn, CCOmode)" | |
6065 | "@ | |
6066 | a<g>hi\t%0,%h2 | |
6067 | a<g>hik\t%0,%1,%h2 | |
6068 | a<g>si\t%0,%c2" | |
6069 | [(set_attr "op_type" "RI,RIE,SIY") | |
6070 | (set_attr "cpu_facility" "*,z196,z10") | |
6071 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
6072 | ||
6073 | ||
9db1d521 | 6074 | ; |
609e7e80 | 6075 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6076 | ; |
6077 | ||
609e7e80 | 6078 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 6079 | ; FIXME: wfadb does not clobber cc |
142cd70f | 6080 | (define_insn "add<mode>3" |
2de2b3f9 AK |
6081 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6082 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
6083 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6084 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6085 | "TARGET_HARD_FLOAT" |
9db1d521 | 6086 | "@ |
62d3f261 AK |
6087 | a<xde>tr\t%0,%1,%2 |
6088 | a<xde>br\t%0,%2 | |
6e5b5de8 | 6089 | a<xde>b\t%0,%2 |
2de2b3f9 AK |
6090 | wfadb\t%v0,%v1,%v2 |
6091 | wfasb\t%v0,%v1,%v2" | |
6092 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6093 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6094 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6095 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6096 | |
609e7e80 | 6097 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 6098 | (define_insn "*add<mode>3_cc" |
ae156f85 | 6099 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6100 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
6101 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6102 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6103 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6104 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6105 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6106 | "@ |
62d3f261 AK |
6107 | a<xde>tr\t%0,%1,%2 |
6108 | a<xde>br\t%0,%2 | |
f61a2c7d | 6109 | a<xde>b\t%0,%2" |
62d3f261 AK |
6110 | [(set_attr "op_type" "RRF,RRE,RXE") |
6111 | (set_attr "type" "fsimp<mode>") | |
6112 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6113 | |
609e7e80 | 6114 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 6115 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 6116 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6117 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
6118 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6119 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6120 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6121 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6122 | "@ |
62d3f261 AK |
6123 | a<xde>tr\t%0,%1,%2 |
6124 | a<xde>br\t%0,%2 | |
f61a2c7d | 6125 | a<xde>b\t%0,%2" |
62d3f261 AK |
6126 | [(set_attr "op_type" "RRF,RRE,RXE") |
6127 | (set_attr "type" "fsimp<mode>") | |
6128 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6129 | |
72a4ddf2 AK |
6130 | ; |
6131 | ; Pointer add instruction patterns | |
6132 | ; | |
6133 | ||
6134 | ; This will match "*la_64" | |
6135 | (define_expand "addptrdi3" | |
6136 | [(set (match_operand:DI 0 "register_operand" "") | |
6137 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
6138 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
6139 | "TARGET_64BIT" | |
6140 | { | |
72a4ddf2 AK |
6141 | if (GET_CODE (operands[2]) == CONST_INT) |
6142 | { | |
357ddc7d TV |
6143 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6144 | ||
72a4ddf2 AK |
6145 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6146 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6147 | { | |
6148 | operands[2] = force_const_mem (DImode, operands[2]); | |
6149 | operands[2] = force_reg (DImode, operands[2]); | |
6150 | } | |
6151 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6152 | operands[2] = force_reg (DImode, operands[2]); | |
6153 | } | |
6154 | }) | |
6155 | ||
6156 | ; For 31 bit we have to prevent the generated pattern from matching | |
6157 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
6158 | ; match "force_la_31". | |
6159 | (define_expand "addptrsi3" | |
6160 | [(parallel | |
6161 | [(set (match_operand:SI 0 "register_operand" "") | |
6162 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
6163 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
6164 | (use (const_int 0))])] | |
6165 | "!TARGET_64BIT" | |
6166 | { | |
72a4ddf2 AK |
6167 | if (GET_CODE (operands[2]) == CONST_INT) |
6168 | { | |
357ddc7d TV |
6169 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6170 | ||
72a4ddf2 AK |
6171 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6172 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6173 | { | |
6174 | operands[2] = force_const_mem (SImode, operands[2]); | |
6175 | operands[2] = force_reg (SImode, operands[2]); | |
6176 | } | |
6177 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6178 | operands[2] = force_reg (SImode, operands[2]); | |
6179 | } | |
6180 | }) | |
9db1d521 HP |
6181 | |
6182 | ;; | |
6183 | ;;- Subtract instructions. | |
6184 | ;; | |
6185 | ||
1c7b1b7e UW |
6186 | ; |
6187 | ; subti3 instruction pattern(s). | |
6188 | ; | |
6189 | ||
085261c8 AK |
6190 | (define_expand "subti3" |
6191 | [(parallel | |
6192 | [(set (match_operand:TI 0 "register_operand" "") | |
6193 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
6194 | (match_operand:TI 2 "general_operand" "") ) ) | |
6195 | (clobber (reg:CC CC_REGNUM))])] | |
6196 | "TARGET_ZARCH" | |
6197 | { | |
2d71f118 | 6198 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
6199 | if (TARGET_VX) |
6200 | { | |
6201 | emit_insn (gen_rtx_SET (operands[0], | |
6202 | gen_rtx_MINUS (TImode, | |
6203 | operands[1], | |
6204 | copy_to_mode_reg (TImode, operands[2])))); | |
6205 | DONE; | |
6206 | } | |
6207 | }) | |
6208 | ||
6209 | (define_insn_and_split "*subti3" | |
6210 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
6211 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
6212 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 6213 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6214 | "TARGET_ZARCH" |
1c7b1b7e UW |
6215 | "#" |
6216 | "&& reload_completed" | |
6217 | [(parallel | |
ae156f85 | 6218 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
6219 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
6220 | (match_dup 7))) | |
6221 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
6222 | (parallel | |
6223 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6224 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6225 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
6226 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
6227 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
6228 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
6229 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
6230 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
6231 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
6232 | [(set_attr "op_type" "*") | |
6233 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 6234 | |
9db1d521 HP |
6235 | ; |
6236 | ; subdi3 instruction pattern(s). | |
6237 | ; | |
6238 | ||
3298c037 AK |
6239 | (define_expand "subdi3" |
6240 | [(parallel | |
6241 | [(set (match_operand:DI 0 "register_operand" "") | |
6242 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
6243 | (match_operand:DI 2 "general_operand" ""))) | |
6244 | (clobber (reg:CC CC_REGNUM))])] | |
6245 | "" | |
6246 | "") | |
6247 | ||
07893d4f UW |
6248 | (define_insn "*subdi3_sign" |
6249 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6250 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6251 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6252 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6253 | "TARGET_ZARCH" |
07893d4f | 6254 | "@ |
d40c829f UW |
6255 | sgfr\t%0,%2 |
6256 | sgf\t%0,%2" | |
9381e3f1 | 6257 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
6258 | (set_attr "z10prop" "z10_c,*") |
6259 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
6260 | |
6261 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 6262 | [(set (reg CC_REGNUM) |
07893d4f | 6263 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6264 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6265 | (const_int 0))) |
6266 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6267 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 6268 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6269 | "@ |
d40c829f UW |
6270 | slgfr\t%0,%2 |
6271 | slgf\t%0,%2" | |
9381e3f1 WG |
6272 | [(set_attr "op_type" "RRE,RXY") |
6273 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6274 | |
6275 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 6276 | [(set (reg CC_REGNUM) |
07893d4f | 6277 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6278 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6279 | (const_int 0))) |
6280 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6281 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6282 | "@ |
d40c829f UW |
6283 | slgfr\t%0,%2 |
6284 | slgf\t%0,%2" | |
9381e3f1 WG |
6285 | [(set_attr "op_type" "RRE,RXY") |
6286 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6287 | |
6288 | (define_insn "*subdi3_zero" | |
6289 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6290 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6291 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6292 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6293 | "TARGET_ZARCH" |
07893d4f | 6294 | "@ |
d40c829f UW |
6295 | slgfr\t%0,%2 |
6296 | slgf\t%0,%2" | |
9381e3f1 WG |
6297 | [(set_attr "op_type" "RRE,RXY") |
6298 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6299 | |
e69166de UW |
6300 | (define_insn_and_split "*subdi3_31z" |
6301 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6302 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6303 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6304 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6305 | "!TARGET_ZARCH" |
e69166de UW |
6306 | "#" |
6307 | "&& reload_completed" | |
6308 | [(parallel | |
ae156f85 | 6309 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6310 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6311 | (match_dup 7))) | |
6312 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6313 | (parallel | |
6314 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6315 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6316 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6317 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6318 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6319 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6320 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6321 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6322 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6323 | |
3298c037 AK |
6324 | ; |
6325 | ; subsi3 instruction pattern(s). | |
6326 | ; | |
6327 | ||
6328 | (define_expand "subsi3" | |
07893d4f | 6329 | [(parallel |
3298c037 AK |
6330 | [(set (match_operand:SI 0 "register_operand" "") |
6331 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6332 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6333 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6334 | "" |
07893d4f | 6335 | "") |
9db1d521 | 6336 | |
3298c037 AK |
6337 | (define_insn "*subsi3_sign" |
6338 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6339 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6340 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6341 | (clobber (reg:CC CC_REGNUM))] | |
6342 | "" | |
6343 | "@ | |
6344 | sh\t%0,%2 | |
6345 | shy\t%0,%2" | |
65b1d8ea | 6346 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6347 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6348 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6349 | |
9db1d521 | 6350 | ; |
3298c037 | 6351 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6352 | ; |
6353 | ||
65b1d8ea | 6354 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6355 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6356 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6357 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6358 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6359 | (clobber (reg:CC CC_REGNUM))] |
6360 | "" | |
6361 | "@ | |
6362 | s<g>r\t%0,%2 | |
65b1d8ea | 6363 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6364 | s<g>\t%0,%2 |
6365 | s<y>\t%0,%2" | |
65b1d8ea | 6366 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6367 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6368 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6369 | |
65b1d8ea | 6370 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6371 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6372 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6373 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6374 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6375 | (match_dup 1))) |
65b1d8ea | 6376 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6377 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6378 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6379 | "@ |
3298c037 | 6380 | sl<g>r\t%0,%2 |
65b1d8ea | 6381 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6382 | sl<g>\t%0,%2 |
6383 | sl<y>\t%0,%2" | |
65b1d8ea | 6384 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6385 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6386 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6387 | |
65b1d8ea | 6388 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6389 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6390 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6391 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6392 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6393 | (match_dup 1))) |
65b1d8ea | 6394 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6395 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6396 | "@ |
3298c037 | 6397 | sl<g>r\t%0,%2 |
65b1d8ea | 6398 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6399 | sl<g>\t%0,%2 |
6400 | sl<y>\t%0,%2" | |
65b1d8ea | 6401 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6402 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6403 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6404 | |
65b1d8ea | 6405 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6406 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6407 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6408 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6409 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6410 | (const_int 0))) |
65b1d8ea | 6411 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6412 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6413 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6414 | "@ |
3298c037 | 6415 | sl<g>r\t%0,%2 |
65b1d8ea | 6416 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6417 | sl<g>\t%0,%2 |
6418 | sl<y>\t%0,%2" | |
65b1d8ea | 6419 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6420 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6421 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6422 | |
65b1d8ea | 6423 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6424 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6425 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6426 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6427 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6428 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6429 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6430 | "s390_match_ccmode (insn, CCL3mode)" |
6431 | "@ | |
3298c037 | 6432 | sl<g>r\t%0,%2 |
65b1d8ea | 6433 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6434 | sl<g>\t%0,%2 |
6435 | sl<y>\t%0,%2" | |
65b1d8ea | 6436 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6437 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6438 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6439 | |
65b1d8ea | 6440 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6441 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6442 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6443 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6444 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6445 | (const_int 0))) |
65b1d8ea | 6446 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6447 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6448 | "@ |
3298c037 | 6449 | sl<g>r\t%0,%2 |
65b1d8ea | 6450 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6451 | sl<g>\t%0,%2 |
6452 | sl<y>\t%0,%2" | |
65b1d8ea | 6453 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6454 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6455 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6456 | |
9db1d521 | 6457 | |
65b1d8ea | 6458 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6459 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6460 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6461 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6462 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6463 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6464 | "s390_match_ccmode (insn, CCL3mode)" |
6465 | "@ | |
3298c037 | 6466 | sl<g>r\t%0,%2 |
65b1d8ea | 6467 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6468 | sl<g>\t%0,%2 |
6469 | sl<y>\t%0,%2" | |
65b1d8ea | 6470 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6471 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6472 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6473 | |
7d2fd075 AK |
6474 | (define_insn "*subdi3_sign" |
6475 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6476 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6477 | (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) | |
6478 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 6479 | "TARGET_Z14" |
7d2fd075 AK |
6480 | "sgh\t%0,%2" |
6481 | [(set_attr "op_type" "RXY")]) | |
6482 | ||
4caa6bab AK |
6483 | ; Jump to label OP3 if OP1 - OP2 results in a signed overflow |
6484 | (define_expand "subv<mode>4" | |
6485 | [(parallel | |
6486 | [(set (reg:CCO CC_REGNUM) | |
6487 | (compare:CCO (minus:<DBL> | |
6488 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand")) | |
6489 | (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand"))) | |
6490 | (sign_extend:<DBL> (minus:GPR (match_dup 1) (match_dup 2))))) | |
6491 | (set (match_operand:GPR 0 "nonimmediate_operand") | |
6492 | (minus:GPR (match_dup 1) (match_dup 2)))]) | |
6493 | (set (pc) | |
6494 | (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) | |
6495 | (label_ref (match_operand 3)) | |
6496 | (pc)))] | |
6497 | "") | |
6498 | ||
6499 | ; sr, s, sy, sgr, sg, srk, sgrk | |
6500 | (define_insn "*subv<mode>3_ccoverflow" | |
6501 | [(set (reg CC_REGNUM) | |
6502 | (compare (minus:<DBL> | |
6503 | (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "0,d,0,0")) | |
6504 | (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand" "d,d,R,T"))) | |
6505 | (sign_extend:<DBL> (minus:GPR (match_dup 1) (match_dup 2))))) | |
6506 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
6507 | (minus:GPR (match_dup 1) (match_dup 2)))] | |
6508 | "s390_match_ccmode (insn, CCOmode)" | |
6509 | "@ | |
6510 | s<g>r\t%0,%2 | |
6511 | s<g>rk\t%0,%1,%2 | |
6512 | s<g>\t%0,%2 | |
6513 | s<y>\t%0,%2" | |
6514 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") | |
6515 | (set_attr "cpu_facility" "*,z196,*,longdisp") | |
6516 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
6517 | ||
9db1d521 HP |
6518 | |
6519 | ; | |
609e7e80 | 6520 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6521 | ; |
6522 | ||
2de2b3f9 | 6523 | ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? |
d46f24b6 | 6524 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6525 | (define_insn "sub<mode>3" |
2de2b3f9 AK |
6526 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6527 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
6528 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6529 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6530 | "TARGET_HARD_FLOAT" |
9db1d521 | 6531 | "@ |
62d3f261 AK |
6532 | s<xde>tr\t%0,%1,%2 |
6533 | s<xde>br\t%0,%2 | |
6e5b5de8 | 6534 | s<xde>b\t%0,%2 |
2de2b3f9 AK |
6535 | wfsdb\t%v0,%v1,%v2 |
6536 | wfssb\t%v0,%v1,%v2" | |
6537 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6538 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6539 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6540 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6541 | |
d46f24b6 | 6542 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6543 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6544 | [(set (reg CC_REGNUM) |
62d3f261 | 6545 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
2de2b3f9 | 6546 | (match_operand:FP 2 "general_operand" "f,f,R")) |
609e7e80 | 6547 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6548 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6549 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6550 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6551 | "@ |
62d3f261 AK |
6552 | s<xde>tr\t%0,%1,%2 |
6553 | s<xde>br\t%0,%2 | |
f61a2c7d | 6554 | s<xde>b\t%0,%2" |
62d3f261 AK |
6555 | [(set_attr "op_type" "RRF,RRE,RXE") |
6556 | (set_attr "type" "fsimp<mode>") | |
6557 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6558 | |
d46f24b6 | 6559 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6560 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6561 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6562 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6563 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6564 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6565 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6566 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6567 | "@ |
62d3f261 AK |
6568 | s<xde>tr\t%0,%1,%2 |
6569 | s<xde>br\t%0,%2 | |
f61a2c7d | 6570 | s<xde>b\t%0,%2" |
62d3f261 AK |
6571 | [(set_attr "op_type" "RRF,RRE,RXE") |
6572 | (set_attr "type" "fsimp<mode>") | |
6573 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6574 | |
9db1d521 | 6575 | |
e69166de UW |
6576 | ;; |
6577 | ;;- Conditional add/subtract instructions. | |
6578 | ;; | |
6579 | ||
6580 | ; | |
9a91a21f | 6581 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6582 | ; |
6583 | ||
a996720c UW |
6584 | ; the following 4 patterns are used when the result of an add with |
6585 | ; carry is checked for an overflow condition | |
6586 | ||
6587 | ; op1 + op2 + c < op1 | |
6588 | ||
6589 | ; alcr, alc, alcgr, alcg | |
6590 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6591 | [(set (reg CC_REGNUM) | |
6592 | (compare | |
6593 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6594 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6595 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6596 | (match_dup 1))) |
6597 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6598 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6599 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6600 | "@ |
6601 | alc<g>r\t%0,%2 | |
6602 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6603 | [(set_attr "op_type" "RRE,RXY") |
6604 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6605 | |
6606 | ; alcr, alc, alcgr, alcg | |
6607 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6608 | [(set (reg CC_REGNUM) | |
6609 | (compare | |
6610 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6611 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6612 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6613 | (match_dup 1))) |
6614 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6615 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6616 | "@ |
6617 | alc<g>r\t%0,%2 | |
6618 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6619 | [(set_attr "op_type" "RRE,RXY") |
6620 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6621 | |
6622 | ; op1 + op2 + c < op2 | |
6623 | ||
6624 | ; alcr, alc, alcgr, alcg | |
6625 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6626 | [(set (reg CC_REGNUM) | |
6627 | (compare | |
6628 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6629 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6630 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6631 | (match_dup 2))) |
6632 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6633 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6634 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6635 | "@ |
6636 | alc<g>r\t%0,%2 | |
6637 | alc<g>\t%0,%2" | |
6638 | [(set_attr "op_type" "RRE,RXY")]) | |
6639 | ||
6640 | ; alcr, alc, alcgr, alcg | |
6641 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6642 | [(set (reg CC_REGNUM) | |
6643 | (compare | |
6644 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6645 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6646 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6647 | (match_dup 2))) |
6648 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6649 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6650 | "@ |
6651 | alc<g>r\t%0,%2 | |
6652 | alc<g>\t%0,%2" | |
6653 | [(set_attr "op_type" "RRE,RXY")]) | |
6654 | ||
43a09b63 | 6655 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6656 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6657 | [(set (reg CC_REGNUM) |
e69166de | 6658 | (compare |
a94a76a7 UW |
6659 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6660 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6661 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6662 | (const_int 0))) |
9a91a21f | 6663 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6664 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
8cc6307c | 6665 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6666 | "@ |
9a91a21f AS |
6667 | alc<g>r\t%0,%2 |
6668 | alc<g>\t%0,%2" | |
e69166de UW |
6669 | [(set_attr "op_type" "RRE,RXY")]) |
6670 | ||
43a09b63 | 6671 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6672 | (define_insn "*add<mode>3_alc" |
6673 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6674 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6675 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6676 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6677 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6678 | "" |
e69166de | 6679 | "@ |
9a91a21f AS |
6680 | alc<g>r\t%0,%2 |
6681 | alc<g>\t%0,%2" | |
e69166de UW |
6682 | [(set_attr "op_type" "RRE,RXY")]) |
6683 | ||
43a09b63 | 6684 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6685 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6686 | [(set (reg CC_REGNUM) |
e69166de | 6687 | (compare |
9a91a21f | 6688 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6689 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6690 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6691 | (const_int 0))) |
9a91a21f AS |
6692 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6693 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
8cc6307c | 6694 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6695 | "@ |
9a91a21f AS |
6696 | slb<g>r\t%0,%2 |
6697 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6698 | [(set_attr "op_type" "RRE,RXY") |
6699 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6700 | |
43a09b63 | 6701 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6702 | (define_insn "*sub<mode>3_slb" |
6703 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6704 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6705 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6706 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6707 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6708 | "" |
e69166de | 6709 | "@ |
9a91a21f AS |
6710 | slb<g>r\t%0,%2 |
6711 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6712 | [(set_attr "op_type" "RRE,RXY") |
6713 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6714 | |
9a91a21f AS |
6715 | (define_expand "add<mode>cc" |
6716 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6717 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6718 | (match_operand:GPR 2 "register_operand" "") |
6719 | (match_operand:GPR 3 "const_int_operand" "")] | |
8cc6307c | 6720 | "" |
9381e3f1 | 6721 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6722 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6723 | operands[0], operands[2], |
5d880bd2 UW |
6724 | operands[3])) FAIL; DONE;") |
6725 | ||
6726 | ; | |
6727 | ; scond instruction pattern(s). | |
6728 | ; | |
6729 | ||
9a91a21f AS |
6730 | (define_insn_and_split "*scond<mode>" |
6731 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6732 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6733 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6734 | "" |
5d880bd2 UW |
6735 | "#" |
6736 | "&& reload_completed" | |
6737 | [(set (match_dup 0) (const_int 0)) | |
6738 | (parallel | |
a94a76a7 UW |
6739 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6740 | (match_dup 0))) | |
ae156f85 | 6741 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6742 | "") |
5d880bd2 | 6743 | |
9a91a21f AS |
6744 | (define_insn_and_split "*scond<mode>_neg" |
6745 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6746 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6747 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6748 | "" |
5d880bd2 UW |
6749 | "#" |
6750 | "&& reload_completed" | |
6751 | [(set (match_dup 0) (const_int 0)) | |
6752 | (parallel | |
9a91a21f AS |
6753 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6754 | (match_dup 1))) | |
ae156f85 | 6755 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6756 | (parallel |
9a91a21f | 6757 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6758 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6759 | "") |
5d880bd2 | 6760 | |
5d880bd2 | 6761 | |
f90b7a5a | 6762 | (define_expand "cstore<mode>4" |
9a91a21f | 6763 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6764 | (match_operator:SI 1 "s390_scond_operator" |
6765 | [(match_operand:GPR 2 "register_operand" "") | |
6766 | (match_operand:GPR 3 "general_operand" "")]))] | |
8cc6307c | 6767 | "" |
f90b7a5a | 6768 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6769 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6770 | ||
f90b7a5a | 6771 | (define_expand "cstorecc4" |
69950452 | 6772 | [(parallel |
f90b7a5a PB |
6773 | [(set (match_operand:SI 0 "register_operand" "") |
6774 | (match_operator:SI 1 "s390_eqne_operator" | |
3ea685e7 | 6775 | [(match_operand 2 "cc_reg_operand") |
f90b7a5a | 6776 | (match_operand 3 "const0_operand")])) |
69950452 AS |
6777 | (clobber (reg:CC CC_REGNUM))])] |
6778 | "" | |
3ea685e7 DV |
6779 | "machine_mode mode = GET_MODE (operands[2]); |
6780 | if (TARGET_Z196) | |
6781 | { | |
6782 | rtx cond, ite; | |
6783 | ||
6784 | if (GET_CODE (operands[1]) == NE) | |
6785 | cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); | |
6786 | else | |
6787 | cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); | |
6788 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); | |
6789 | emit_insn (gen_rtx_SET (operands[0], ite)); | |
6790 | } | |
6791 | else | |
6792 | { | |
6793 | if (mode != CCZ1mode) | |
6794 | FAIL; | |
6795 | emit_insn (gen_sne (operands[0], operands[2])); | |
6796 | if (GET_CODE (operands[1]) == EQ) | |
6797 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6798 | } | |
f90b7a5a | 6799 | DONE;") |
69950452 | 6800 | |
f90b7a5a | 6801 | (define_insn_and_split "sne" |
69950452 | 6802 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6803 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6804 | (const_int 0))) |
6805 | (clobber (reg:CC CC_REGNUM))] | |
6806 | "" | |
6807 | "#" | |
6808 | "reload_completed" | |
6809 | [(parallel | |
6810 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6811 | (clobber (reg:CC CC_REGNUM))])]) | |
6812 | ||
163f23d2 AK |
6813 | ; Such patterns get directly emitted by noce_emit_store_flag. |
6814 | (define_insn_and_split "*cstorecc<mode>_z13" | |
6815 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6816 | (match_operator:GPR 1 "s390_comparison" | |
6817 | [(match_operand 2 "cc_reg_operand" "c") | |
6818 | (match_operand 3 "const_int_operand" "")]))] | |
6819 | "TARGET_Z13" | |
6820 | "#" | |
6821 | "reload_completed" | |
6822 | [(set (match_dup 0) (const_int 0)) | |
6823 | (set (match_dup 0) | |
6824 | (if_then_else:GPR | |
6825 | (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
6826 | (const_int 1) | |
6827 | (match_dup 0)))]) | |
e69166de | 6828 | |
65b1d8ea AK |
6829 | ;; |
6830 | ;; - Conditional move instructions (introduced with z196) | |
6831 | ;; | |
6832 | ||
6833 | (define_expand "mov<mode>cc" | |
6834 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6835 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
88e845c0 RD |
6836 | (match_operand:GPR 2 "loc_operand" "") |
6837 | (match_operand:GPR 3 "loc_operand" "")))] | |
65b1d8ea | 6838 | "TARGET_Z196" |
7477de01 | 6839 | { |
88e845c0 RD |
6840 | if (!TARGET_Z13 && CONSTANT_P (operands[2])) |
6841 | operands[2] = force_reg (<MODE>mode, operands[2]); | |
6842 | ||
6843 | if (!TARGET_Z13 && CONSTANT_P (operands[3])) | |
6844 | operands[3] = force_reg (<MODE>mode, operands[3]); | |
6845 | ||
7477de01 AK |
6846 | /* Emit the comparison insn in case we do not already have a comparison result. */ |
6847 | if (!s390_comparison (operands[1], VOIDmode)) | |
6848 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6849 | XEXP (operands[1], 0), | |
6850 | XEXP (operands[1], 1)); | |
6851 | }) | |
65b1d8ea | 6852 | |
d8928886 RD |
6853 | ;; |
6854 | ;; - We do not have instructions for QImode or HImode but still | |
6855 | ;; enable load on condition/if conversion for them. | |
6856 | (define_expand "mov<mode>cc" | |
6857 | [(set (match_operand:HQI 0 "nonimmediate_operand" "") | |
6858 | (if_then_else:HQI (match_operand 1 "comparison_operator" "") | |
6859 | (match_operand:HQI 2 "loc_operand" "") | |
6860 | (match_operand:HQI 3 "loc_operand" "")))] | |
6861 | "TARGET_Z196" | |
6862 | { | |
6863 | /* Emit the comparison insn in case we do not already have a comparison | |
6864 | result. */ | |
6865 | if (!s390_comparison (operands[1], VOIDmode)) | |
6866 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6867 | XEXP (operands[1], 0), | |
6868 | XEXP (operands[1], 1)); | |
6869 | ||
6870 | rtx then = operands[2]; | |
6871 | rtx els = operands[3]; | |
6872 | ||
6873 | if ((!TARGET_Z13 && CONSTANT_P (then)) || MEM_P (then)) | |
6874 | then = force_reg (<MODE>mode, then); | |
6875 | if ((!TARGET_Z13 && CONSTANT_P (els)) || MEM_P (els)) | |
6876 | els = force_reg (<MODE>mode, els); | |
6877 | ||
6878 | if (!CONSTANT_P (then)) | |
6879 | then = simplify_gen_subreg (E_SImode, then, <MODE>mode, 0); | |
6880 | if (!CONSTANT_P (els)) | |
6881 | els = simplify_gen_subreg (E_SImode, els, <MODE>mode, 0); | |
6882 | ||
6883 | rtx tmp_target = gen_reg_rtx (E_SImode); | |
6884 | emit_insn (gen_movsicc (tmp_target, operands[1], then, els)); | |
6885 | emit_move_insn (operands[0], gen_lowpart (<MODE>mode, tmp_target)); | |
6886 | DONE; | |
6887 | }) | |
6888 | ||
6889 | ||
6890 | ||
618eef38 | 6891 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi, selr, selgr |
561f6312 | 6892 | (define_insn "*mov<mode>cc" |
618eef38 | 6893 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,S,S") |
65b1d8ea AK |
6894 | (if_then_else:GPR |
6895 | (match_operator 1 "s390_comparison" | |
618eef38 AK |
6896 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c") |
6897 | (match_operand 5 "const_int_operand" "")]) | |
6898 | (match_operand:GPR 3 "loc_operand" " d,0,d,S,0,K,0,d,0") | |
6899 | (match_operand:GPR 4 "loc_operand" " 0,d,d,0,S,0,K,0,d")))] | |
65b1d8ea AK |
6900 | "TARGET_Z196" |
6901 | "@ | |
6902 | loc<g>r%C1\t%0,%3 | |
6903 | loc<g>r%D1\t%0,%4 | |
618eef38 | 6904 | sel<g>r%C1\t%0,%3,%4 |
a6510374 AK |
6905 | loc<g>%C1\t%0,%3 |
6906 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6907 | loc<g>hi%C1\t%0,%h3 |
6908 | loc<g>hi%D1\t%0,%h4 | |
a6510374 | 6909 | stoc<g>%C1\t%3,%0 |
561f6312 | 6910 | stoc<g>%D1\t%4,%0" |
618eef38 | 6911 | [(set_attr "op_type" "RRF,RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") |
80f8cd77 | 6912 | (set_attr "cpu_facility" "*,*,z15,*,*,z13,z13,*,*")]) |
65b1d8ea | 6913 | |
9db1d521 HP |
6914 | ;; |
6915 | ;;- Multiply instructions. | |
6916 | ;; | |
6917 | ||
4023fb28 UW |
6918 | ; |
6919 | ; muldi3 instruction pattern(s). | |
6920 | ; | |
9db1d521 | 6921 | |
7d2fd075 AK |
6922 | (define_expand "muldi3" |
6923 | [(parallel | |
6924 | [(set (match_operand:DI 0 "register_operand") | |
6925 | (mult:DI (match_operand:DI 1 "nonimmediate_operand") | |
6926 | (match_operand:DI 2 "general_operand"))) | |
6927 | (clobber (reg:CC CC_REGNUM))])] | |
6928 | "TARGET_ZARCH") | |
6929 | ||
07893d4f UW |
6930 | (define_insn "*muldi3_sign" |
6931 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6932 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6933 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6934 | "TARGET_ZARCH" |
07893d4f | 6935 | "@ |
d40c829f UW |
6936 | msgfr\t%0,%2 |
6937 | msgf\t%0,%2" | |
963fc8d0 AK |
6938 | [(set_attr "op_type" "RRE,RXY") |
6939 | (set_attr "type" "imuldi")]) | |
07893d4f | 6940 | |
7d2fd075 AK |
6941 | (define_insn "*muldi3" |
6942 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") | |
6943 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") | |
6944 | (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) | |
6945 | (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] | |
9602b6a1 | 6946 | "TARGET_ZARCH" |
9db1d521 | 6947 | "@ |
d40c829f | 6948 | msgr\t%0,%2 |
7d2fd075 | 6949 | msgrkc\t%0,%1,%2 |
d40c829f | 6950 | mghi\t%0,%h2 |
963fc8d0 AK |
6951 | msg\t%0,%2 |
6952 | msgfi\t%0,%2" | |
7d2fd075 | 6953 | [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") |
963fc8d0 | 6954 | (set_attr "type" "imuldi") |
e9e8efc9 | 6955 | (set_attr "cpu_facility" "*,z14,*,*,z10")]) |
7d2fd075 AK |
6956 | |
6957 | (define_insn "mulditi3" | |
6958 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6959 | (mult:TI (sign_extend:TI | |
6960 | (match_operand:DI 1 "register_operand" "%d,0")) | |
6961 | (sign_extend:TI | |
6962 | (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] | |
e9e8efc9 | 6963 | "TARGET_Z14" |
7d2fd075 AK |
6964 | "@ |
6965 | mgrk\t%0,%1,%2 | |
6966 | mg\t%0,%2" | |
6967 | [(set_attr "op_type" "RRF,RXY")]) | |
6968 | ||
6969 | ; Combine likes op1 and op2 to be swapped sometimes. | |
6970 | (define_insn "mulditi3_2" | |
6971 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6972 | (mult:TI (sign_extend:TI | |
6973 | (match_operand:DI 1 "nonimmediate_operand" "%d,T")) | |
6974 | (sign_extend:TI | |
6975 | (match_operand:DI 2 "register_operand" " d,0"))))] | |
e9e8efc9 | 6976 | "TARGET_Z14" |
7d2fd075 AK |
6977 | "@ |
6978 | mgrk\t%0,%1,%2 | |
6979 | mg\t%0,%1" | |
6980 | [(set_attr "op_type" "RRF,RXY")]) | |
6981 | ||
6982 | (define_insn "*muldi3_sign" | |
6983 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6984 | (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
6985 | (match_operand:DI 1 "register_operand" "0")))] | |
e9e8efc9 | 6986 | "TARGET_Z14" |
7d2fd075 AK |
6987 | "mgh\t%0,%2" |
6988 | [(set_attr "op_type" "RXY")]) | |
6989 | ||
f2d3c02a | 6990 | |
9db1d521 HP |
6991 | ; |
6992 | ; mulsi3 instruction pattern(s). | |
6993 | ; | |
6994 | ||
7d2fd075 AK |
6995 | (define_expand "mulsi3" |
6996 | [(parallel | |
6997 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6998 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6999 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
7000 | (clobber (reg:CC CC_REGNUM))])] | |
7001 | "") | |
7002 | ||
f1e77d83 | 7003 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
7004 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7005 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
7006 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 7007 | "" |
963fc8d0 AK |
7008 | "@ |
7009 | mh\t%0,%2 | |
7010 | mhy\t%0,%2" | |
7011 | [(set_attr "op_type" "RX,RXY") | |
7012 | (set_attr "type" "imulhi") | |
7013 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 7014 | |
7d2fd075 AK |
7015 | (define_insn "*mulsi3" |
7016 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
7017 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7018 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
7019 | (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] | |
9db1d521 HP |
7020 | "" |
7021 | "@ | |
d40c829f | 7022 | msr\t%0,%2 |
7d2fd075 | 7023 | msrkc\t%0,%1,%2 |
d40c829f UW |
7024 | mhi\t%0,%h2 |
7025 | ms\t%0,%2 | |
963fc8d0 AK |
7026 | msy\t%0,%2 |
7027 | msfi\t%0,%2" | |
7d2fd075 AK |
7028 | [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") |
7029 | (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") | |
e9e8efc9 | 7030 | (set_attr "cpu_facility" "*,z14,*,*,longdisp,z10")]) |
9db1d521 | 7031 | |
4023fb28 UW |
7032 | ; |
7033 | ; mulsidi3 instruction pattern(s). | |
7034 | ; | |
7035 | ||
f1e77d83 | 7036 | (define_insn "mulsidi3" |
963fc8d0 | 7037 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 7038 | (mult:DI (sign_extend:DI |
963fc8d0 | 7039 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 7040 | (sign_extend:DI |
963fc8d0 | 7041 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 7042 | "!TARGET_ZARCH" |
f1e77d83 UW |
7043 | "@ |
7044 | mr\t%0,%2 | |
963fc8d0 AK |
7045 | m\t%0,%2 |
7046 | mfy\t%0,%2" | |
7047 | [(set_attr "op_type" "RR,RX,RXY") | |
7048 | (set_attr "type" "imulsi") | |
7049 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 7050 | |
4caa6bab AK |
7051 | ; Jump to label OP3 if OP1 * OP2 results in a signed overflow |
7052 | (define_expand "mulv<mode>4" | |
7053 | [(parallel | |
7054 | [(set (reg:CCO CC_REGNUM) | |
7055 | (compare:CCO (mult:<DBL> | |
7056 | (sign_extend:<DBL> (match_operand:GPR 1 "register_operand")) | |
7057 | (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand"))) | |
7058 | (sign_extend:<DBL> (mult:GPR (match_dup 1) (match_dup 2))))) | |
7059 | (set (match_operand:GPR 0 "register_operand") | |
7060 | (mult:GPR (match_dup 1) (match_dup 2)))]) | |
7061 | (set (pc) | |
7062 | (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) | |
7063 | (label_ref (match_operand 3)) | |
7064 | (pc)))] | |
7065 | "TARGET_Z14") | |
7066 | ||
7067 | ; msrkc, msc, msgrkc, msgc | |
7068 | (define_insn "*mulv<mode>3_ccoverflow" | |
7069 | [(set (reg CC_REGNUM) | |
7070 | (compare (mult:<DBL> | |
7071 | (sign_extend:<DBL> (match_operand:GPR 1 "register_operand" "%d,0")) | |
7072 | (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand" " d,T"))) | |
7073 | (sign_extend:<DBL> (mult:GPR (match_dup 1) (match_dup 2))))) | |
7074 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
7075 | (mult:GPR (match_dup 1) (match_dup 2)))] | |
7076 | "s390_match_ccmode (insn, CCOmode) && TARGET_Z14" | |
7077 | "@ | |
7078 | ms<g>rkc\t%0,%1,%2 | |
7079 | ms<g>c\t%0,%2" | |
7080 | [(set_attr "op_type" "RRF,RXY")]) | |
7081 | ||
7082 | ||
f1e77d83 | 7083 | ; |
6e0d70c9 | 7084 | ; umul instruction pattern(s). |
f1e77d83 | 7085 | ; |
c7453384 | 7086 | |
6e0d70c9 AK |
7087 | ; mlr, ml, mlgr, mlg |
7088 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 7089 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 7090 | (mult:DW (zero_extend:DW |
3e4be43f | 7091 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 7092 | (zero_extend:DW |
3e4be43f | 7093 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
8cc6307c | 7094 | "" |
f1e77d83 | 7095 | "@ |
6e0d70c9 AK |
7096 | ml<tg>r\t%0,%2 |
7097 | ml<tg>\t%0,%2" | |
f1e77d83 | 7098 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 7099 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 7100 | |
9db1d521 | 7101 | ; |
609e7e80 | 7102 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
7103 | ; |
7104 | ||
9381e3f1 | 7105 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 7106 | (define_insn "mul<mode>3" |
2de2b3f9 AK |
7107 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7108 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
7109 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7110 | "TARGET_HARD_FLOAT" |
9db1d521 | 7111 | "@ |
62d3f261 AK |
7112 | m<xdee>tr\t%0,%1,%2 |
7113 | m<xdee>br\t%0,%2 | |
6e5b5de8 | 7114 | m<xdee>b\t%0,%2 |
2de2b3f9 AK |
7115 | wfmdb\t%v0,%v1,%v2 |
7116 | wfmsb\t%v0,%v1,%v2" | |
7117 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7118 | (set_attr "type" "fmul<mode>") |
2de2b3f9 AK |
7119 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7120 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7121 | |
9381e3f1 | 7122 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 7123 | (define_insn "fma<mode>4" |
2de2b3f9 AK |
7124 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
7125 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
7126 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
7127 | (match_operand:DSF 3 "register_operand" "0,0,v,v")))] | |
d7ecb504 | 7128 | "TARGET_HARD_FLOAT" |
a1b892b5 | 7129 | "@ |
f61a2c7d | 7130 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 | 7131 | ma<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
7132 | wfmadb\t%v0,%v1,%v2,%v3 |
7133 | wfmasb\t%v0,%v1,%v2,%v3" | |
7134 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7135 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
7136 | (set_attr "cpu_facility" "*,*,vx,vxe") |
7137 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
a1b892b5 | 7138 | |
43a09b63 | 7139 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 7140 | (define_insn "fms<mode>4" |
2de2b3f9 AK |
7141 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
7142 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
7143 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
7144 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] | |
d7ecb504 | 7145 | "TARGET_HARD_FLOAT" |
a1b892b5 | 7146 | "@ |
f61a2c7d | 7147 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 | 7148 | ms<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
7149 | wfmsdb\t%v0,%v1,%v2,%v3 |
7150 | wfmssb\t%v0,%v1,%v2,%v3" | |
7151 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7152 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
7153 | (set_attr "cpu_facility" "*,*,vx,vxe") |
7154 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
9db1d521 HP |
7155 | |
7156 | ;; | |
7157 | ;;- Divide and modulo instructions. | |
7158 | ;; | |
7159 | ||
7160 | ; | |
4023fb28 | 7161 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
7162 | ; |
7163 | ||
4023fb28 UW |
7164 | (define_expand "divmoddi4" |
7165 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 7166 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
7167 | (match_operand:DI 2 "general_operand" ""))) |
7168 | (set (match_operand:DI 3 "general_operand" "") | |
7169 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
7170 | (clobber (match_dup 4))] | |
9602b6a1 | 7171 | "TARGET_ZARCH" |
9db1d521 | 7172 | { |
d8485bdb TS |
7173 | rtx div_equal, mod_equal; |
7174 | rtx_insn *insn; | |
4023fb28 UW |
7175 | |
7176 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
7177 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
7178 | |
7179 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 7180 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
7181 | |
7182 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 7183 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7184 | |
7185 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 7186 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7187 | |
9db1d521 | 7188 | DONE; |
10bbf137 | 7189 | }) |
9db1d521 HP |
7190 | |
7191 | (define_insn "divmodtidi3" | |
4023fb28 UW |
7192 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
7193 | (ior:TI | |
4023fb28 UW |
7194 | (ashift:TI |
7195 | (zero_extend:TI | |
5665e398 | 7196 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 7197 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
7198 | (const_int 64)) |
7199 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 7200 | "TARGET_ZARCH" |
9db1d521 | 7201 | "@ |
d40c829f UW |
7202 | dsgr\t%0,%2 |
7203 | dsg\t%0,%2" | |
d3632d41 | 7204 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7205 | (set_attr "type" "idiv")]) |
9db1d521 | 7206 | |
4023fb28 UW |
7207 | (define_insn "divmodtisi3" |
7208 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
7209 | (ior:TI | |
4023fb28 UW |
7210 | (ashift:TI |
7211 | (zero_extend:TI | |
5665e398 | 7212 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 7213 | (sign_extend:DI |
3e4be43f | 7214 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
7215 | (const_int 64)) |
7216 | (zero_extend:TI | |
7217 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 7218 | "TARGET_ZARCH" |
4023fb28 | 7219 | "@ |
d40c829f UW |
7220 | dsgfr\t%0,%2 |
7221 | dsgf\t%0,%2" | |
d3632d41 | 7222 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7223 | (set_attr "type" "idiv")]) |
9db1d521 | 7224 | |
4023fb28 UW |
7225 | ; |
7226 | ; udivmoddi4 instruction pattern(s). | |
7227 | ; | |
9db1d521 | 7228 | |
4023fb28 UW |
7229 | (define_expand "udivmoddi4" |
7230 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
7231 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
7232 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
7233 | (set (match_operand:DI 3 "general_operand" "") | |
7234 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
7235 | (clobber (match_dup 4))] | |
9602b6a1 | 7236 | "TARGET_ZARCH" |
9db1d521 | 7237 | { |
d8485bdb TS |
7238 | rtx div_equal, mod_equal, equal; |
7239 | rtx_insn *insn; | |
4023fb28 UW |
7240 | |
7241 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
7242 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
7243 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
7244 | gen_rtx_ASHIFT (TImode, |
7245 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
7246 | GEN_INT (64)), |
7247 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
7248 | |
7249 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 7250 | emit_clobber (operands[4]); |
4023fb28 UW |
7251 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
7252 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 7253 | |
4023fb28 | 7254 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7255 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7256 | |
7257 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 7258 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7259 | |
7260 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 7261 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7262 | |
9db1d521 | 7263 | DONE; |
10bbf137 | 7264 | }) |
9db1d521 HP |
7265 | |
7266 | (define_insn "udivmodtidi3" | |
4023fb28 | 7267 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 7268 | (ior:TI |
5665e398 UW |
7269 | (ashift:TI |
7270 | (zero_extend:TI | |
7271 | (truncate:DI | |
2f7e5a0d EC |
7272 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
7273 | (zero_extend:TI | |
3e4be43f | 7274 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7275 | (const_int 64)) |
7276 | (zero_extend:TI | |
7277 | (truncate:DI | |
7278 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 7279 | "TARGET_ZARCH" |
9db1d521 | 7280 | "@ |
d40c829f UW |
7281 | dlgr\t%0,%2 |
7282 | dlg\t%0,%2" | |
d3632d41 | 7283 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7284 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7285 | |
7286 | ; | |
4023fb28 | 7287 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
7288 | ; |
7289 | ||
4023fb28 UW |
7290 | (define_expand "divmodsi4" |
7291 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7292 | (div:SI (match_operand:SI 1 "general_operand" "") | |
7293 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7294 | (set (match_operand:SI 3 "general_operand" "") | |
7295 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
7296 | (clobber (match_dup 4))] | |
9602b6a1 | 7297 | "!TARGET_ZARCH" |
9db1d521 | 7298 | { |
d8485bdb TS |
7299 | rtx div_equal, mod_equal, equal; |
7300 | rtx_insn *insn; | |
4023fb28 UW |
7301 | |
7302 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
7303 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
7304 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7305 | gen_rtx_ASHIFT (DImode, |
7306 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7307 | GEN_INT (32)), |
7308 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
7309 | |
7310 | operands[4] = gen_reg_rtx(DImode); | |
7311 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 7312 | |
4023fb28 | 7313 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7314 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7315 | |
7316 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7317 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7318 | |
7319 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7320 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7321 | |
9db1d521 | 7322 | DONE; |
10bbf137 | 7323 | }) |
9db1d521 HP |
7324 | |
7325 | (define_insn "divmoddisi3" | |
4023fb28 | 7326 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 7327 | (ior:DI |
5665e398 UW |
7328 | (ashift:DI |
7329 | (zero_extend:DI | |
7330 | (truncate:SI | |
2f7e5a0d EC |
7331 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
7332 | (sign_extend:DI | |
5665e398 UW |
7333 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
7334 | (const_int 32)) | |
7335 | (zero_extend:DI | |
7336 | (truncate:SI | |
7337 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7338 | "!TARGET_ZARCH" |
9db1d521 | 7339 | "@ |
d40c829f UW |
7340 | dr\t%0,%2 |
7341 | d\t%0,%2" | |
9db1d521 | 7342 | [(set_attr "op_type" "RR,RX") |
077dab3b | 7343 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7344 | |
7345 | ; | |
7346 | ; udivsi3 and umodsi3 instruction pattern(s). | |
7347 | ; | |
7348 | ||
f1e77d83 UW |
7349 | (define_expand "udivmodsi4" |
7350 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7351 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
7352 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7353 | (set (match_operand:SI 3 "general_operand" "") | |
7354 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
7355 | (clobber (match_dup 4))] | |
8cc6307c | 7356 | "!TARGET_ZARCH" |
f1e77d83 | 7357 | { |
d8485bdb TS |
7358 | rtx div_equal, mod_equal, equal; |
7359 | rtx_insn *insn; | |
f1e77d83 UW |
7360 | |
7361 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7362 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7363 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
7364 | gen_rtx_ASHIFT (DImode, |
7365 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7366 | GEN_INT (32)), |
7367 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
7368 | |
7369 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 7370 | emit_clobber (operands[4]); |
f1e77d83 UW |
7371 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
7372 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 7373 | |
f1e77d83 | 7374 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7375 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
7376 | |
7377 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7378 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
7379 | |
7380 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7381 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
7382 | |
7383 | DONE; | |
7384 | }) | |
7385 | ||
7386 | (define_insn "udivmoddisi3" | |
7387 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 7388 | (ior:DI |
5665e398 UW |
7389 | (ashift:DI |
7390 | (zero_extend:DI | |
7391 | (truncate:SI | |
2f7e5a0d EC |
7392 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
7393 | (zero_extend:DI | |
3e4be43f | 7394 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7395 | (const_int 32)) |
7396 | (zero_extend:DI | |
7397 | (truncate:SI | |
7398 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
8cc6307c | 7399 | "!TARGET_ZARCH" |
f1e77d83 UW |
7400 | "@ |
7401 | dlr\t%0,%2 | |
7402 | dl\t%0,%2" | |
7403 | [(set_attr "op_type" "RRE,RXY") | |
7404 | (set_attr "type" "idiv")]) | |
4023fb28 | 7405 | |
9db1d521 | 7406 | ; |
f5905b37 | 7407 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7408 | ; |
7409 | ||
609e7e80 | 7410 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7411 | (define_insn "div<mode>3" |
2de2b3f9 AK |
7412 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7413 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
7414 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7415 | "TARGET_HARD_FLOAT" |
9db1d521 | 7416 | "@ |
62d3f261 AK |
7417 | d<xde>tr\t%0,%1,%2 |
7418 | d<xde>br\t%0,%2 | |
6e5b5de8 | 7419 | d<xde>b\t%0,%2 |
2de2b3f9 AK |
7420 | wfddb\t%v0,%v1,%v2 |
7421 | wfdsb\t%v0,%v1,%v2" | |
7422 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7423 | (set_attr "type" "fdiv<mode>") |
2de2b3f9 AK |
7424 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7425 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7426 | |
9db1d521 HP |
7427 | |
7428 | ;; | |
7429 | ;;- And instructions. | |
7430 | ;; | |
7431 | ||
047d35ed AS |
7432 | (define_expand "and<mode>3" |
7433 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7434 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7435 | (match_operand:INT 2 "general_operand" ""))) | |
7436 | (clobber (reg:CC CC_REGNUM))] | |
7437 | "" | |
7438 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7439 | ||
9db1d521 HP |
7440 | ; |
7441 | ; anddi3 instruction pattern(s). | |
7442 | ; | |
7443 | ||
7444 | (define_insn "*anddi3_cc" | |
ae156f85 | 7445 | [(set (reg CC_REGNUM) |
e3140518 | 7446 | (compare |
3e4be43f | 7447 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7448 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7449 | (const_int 0))) |
3e4be43f | 7450 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7451 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7452 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7453 | "@ |
d40c829f | 7454 | ngr\t%0,%2 |
65b1d8ea | 7455 | ngrk\t%0,%1,%2 |
e3140518 RH |
7456 | ng\t%0,%2 |
7457 | risbg\t%0,%1,%s2,128+%e2,0" | |
7458 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7459 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7460 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7461 | |
7462 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7463 | [(set (reg CC_REGNUM) |
e3140518 | 7464 | (compare |
3e4be43f | 7465 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7466 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7467 | (const_int 0))) |
3e4be43f | 7468 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7469 | "TARGET_ZARCH |
7470 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7471 | /* Do not steal TM patterns. */ |
7472 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7473 | "@ |
d40c829f | 7474 | ngr\t%0,%2 |
65b1d8ea | 7475 | ngrk\t%0,%1,%2 |
e3140518 RH |
7476 | ng\t%0,%2 |
7477 | risbg\t%0,%1,%s2,128+%e2,0" | |
7478 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7479 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7480 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7481 | |
3af8e996 | 7482 | (define_insn "*anddi3" |
65b1d8ea | 7483 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7484 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7485 | (and:DI |
7486 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7487 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7488 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7489 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7490 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7491 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7492 | "@ |
7493 | # | |
7494 | # | |
7495 | nihh\t%0,%j2 | |
7496 | nihl\t%0,%j2 | |
7497 | nilh\t%0,%j2 | |
7498 | nill\t%0,%j2 | |
7499 | nihf\t%0,%m2 | |
7500 | nilf\t%0,%m2 | |
7501 | ngr\t%0,%2 | |
65b1d8ea | 7502 | ngrk\t%0,%1,%2 |
ec24698e | 7503 | ng\t%0,%2 |
e3140518 | 7504 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7505 | # |
7506 | #" | |
e3140518 RH |
7507 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7508 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7509 | (set_attr "z10prop" "*, |
7510 | *, | |
7511 | z10_super_E1, | |
7512 | z10_super_E1, | |
7513 | z10_super_E1, | |
7514 | z10_super_E1, | |
7515 | z10_super_E1, | |
7516 | z10_super_E1, | |
7517 | z10_super_E1, | |
65b1d8ea | 7518 | *, |
9381e3f1 | 7519 | z10_super_E1, |
e3140518 | 7520 | z10_super_E1, |
9381e3f1 WG |
7521 | *, |
7522 | *")]) | |
0dfa6c5e UW |
7523 | |
7524 | (define_split | |
7525 | [(set (match_operand:DI 0 "s_operand" "") | |
7526 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7527 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7528 | "reload_completed" |
7529 | [(parallel | |
7530 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7531 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7532 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7533 | |
1a2e356e | 7534 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7535 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7536 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7537 | (and:GPR (lshiftrt:GPR | |
7538 | (match_operand:GPR 1 "register_operand" "d") | |
7539 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7540 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7541 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7542 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7543 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7544 | INTVAL (operands[3]))" | |
64c744b9 | 7545 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7546 | [(set_attr "op_type" "RIE") |
7547 | (set_attr "z10prop" "z10_super_E1")]) | |
7548 | ||
64c744b9 | 7549 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7550 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7551 | (and:GPR (ashift:GPR | |
7552 | (match_operand:GPR 1 "register_operand" "d") | |
7553 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7554 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7555 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7556 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7557 | INTVAL (operands[3]))" | |
64c744b9 | 7558 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7559 | [(set_attr "op_type" "RIE") |
7560 | (set_attr "z10prop" "z10_super_E1")]) | |
7561 | ||
9db1d521 HP |
7562 | |
7563 | ; | |
7564 | ; andsi3 instruction pattern(s). | |
7565 | ; | |
7566 | ||
7567 | (define_insn "*andsi3_cc" | |
ae156f85 | 7568 | [(set (reg CC_REGNUM) |
e3140518 RH |
7569 | (compare |
7570 | (and:SI | |
7571 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7572 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7573 | (const_int 0))) | |
7574 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7575 | (and:SI (match_dup 1) (match_dup 2)))] |
7576 | "s390_match_ccmode(insn, CCTmode)" | |
7577 | "@ | |
ec24698e | 7578 | nilf\t%0,%o2 |
d40c829f | 7579 | nr\t%0,%2 |
65b1d8ea | 7580 | nrk\t%0,%1,%2 |
d40c829f | 7581 | n\t%0,%2 |
e3140518 RH |
7582 | ny\t%0,%2 |
7583 | risbg\t%0,%1,%t2,128+%f2,0" | |
7584 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7585 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7586 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7587 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7588 | |
7589 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7590 | [(set (reg CC_REGNUM) |
e3140518 RH |
7591 | (compare |
7592 | (and:SI | |
7593 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7594 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7595 | (const_int 0))) | |
7596 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7597 | "s390_match_ccmode(insn, CCTmode) |
7598 | /* Do not steal TM patterns. */ | |
7599 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7600 | "@ |
ec24698e | 7601 | nilf\t%0,%o2 |
d40c829f | 7602 | nr\t%0,%2 |
65b1d8ea | 7603 | nrk\t%0,%1,%2 |
d40c829f | 7604 | n\t%0,%2 |
e3140518 RH |
7605 | ny\t%0,%2 |
7606 | risbg\t%0,%1,%t2,128+%f2,0" | |
7607 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7608 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7609 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7610 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7611 | |
f19a9af7 | 7612 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7613 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7614 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7615 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7616 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7617 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7618 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7619 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7620 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7621 | "@ |
f19a9af7 AK |
7622 | # |
7623 | # | |
7624 | nilh\t%0,%j2 | |
2f7e5a0d | 7625 | nill\t%0,%j2 |
ec24698e | 7626 | nilf\t%0,%o2 |
d40c829f | 7627 | nr\t%0,%2 |
65b1d8ea | 7628 | nrk\t%0,%1,%2 |
d40c829f | 7629 | n\t%0,%2 |
8cb66696 | 7630 | ny\t%0,%2 |
e3140518 | 7631 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7632 | # |
19b63d8e | 7633 | #" |
e3140518 | 7634 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7635 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7636 | (set_attr "z10prop" "*, |
7637 | *, | |
7638 | z10_super_E1, | |
7639 | z10_super_E1, | |
7640 | z10_super_E1, | |
7641 | z10_super_E1, | |
65b1d8ea | 7642 | *, |
9381e3f1 WG |
7643 | z10_super_E1, |
7644 | z10_super_E1, | |
e3140518 | 7645 | z10_super_E1, |
9381e3f1 WG |
7646 | *, |
7647 | *")]) | |
f19a9af7 AK |
7648 | |
7649 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7650 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7651 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7652 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7653 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7654 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7655 | "@ |
7656 | nr\t%0,%2 | |
8cb66696 | 7657 | n\t%0,%2 |
0dfa6c5e | 7658 | # |
19b63d8e | 7659 | #" |
9381e3f1 WG |
7660 | [(set_attr "op_type" "RR,RX,SI,SS") |
7661 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7662 | ||
0dfa6c5e UW |
7663 | |
7664 | (define_split | |
7665 | [(set (match_operand:SI 0 "s_operand" "") | |
7666 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7667 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7668 | "reload_completed" |
7669 | [(parallel | |
7670 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7671 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7672 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7673 | |
9db1d521 HP |
7674 | ; |
7675 | ; andhi3 instruction pattern(s). | |
7676 | ; | |
7677 | ||
8cb66696 | 7678 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7679 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7680 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7681 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7682 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7683 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7684 | "@ |
d40c829f | 7685 | nr\t%0,%2 |
65b1d8ea | 7686 | nrk\t%0,%1,%2 |
8cb66696 | 7687 | nill\t%0,%x2 |
0dfa6c5e | 7688 | # |
19b63d8e | 7689 | #" |
65b1d8ea AK |
7690 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7691 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7692 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7693 | ]) |
8cb66696 UW |
7694 | |
7695 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7696 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7697 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7698 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7699 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7700 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7701 | "@ | |
7702 | nr\t%0,%2 | |
0dfa6c5e | 7703 | # |
19b63d8e | 7704 | #" |
9381e3f1 WG |
7705 | [(set_attr "op_type" "RR,SI,SS") |
7706 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7707 | ]) | |
0dfa6c5e UW |
7708 | |
7709 | (define_split | |
7710 | [(set (match_operand:HI 0 "s_operand" "") | |
7711 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7712 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7713 | "reload_completed" |
7714 | [(parallel | |
7715 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7716 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7717 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7718 | |
9db1d521 HP |
7719 | ; |
7720 | ; andqi3 instruction pattern(s). | |
7721 | ; | |
7722 | ||
8cb66696 | 7723 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7724 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7725 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7726 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7727 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7728 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7729 | "@ |
d40c829f | 7730 | nr\t%0,%2 |
65b1d8ea | 7731 | nrk\t%0,%1,%2 |
8cb66696 | 7732 | nill\t%0,%b2 |
fc0ea003 UW |
7733 | ni\t%S0,%b2 |
7734 | niy\t%S0,%b2 | |
19b63d8e | 7735 | #" |
65b1d8ea | 7736 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7737 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7738 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7739 | |
7740 | (define_insn "*andqi3_esa" | |
7741 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7742 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7743 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7744 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7745 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7746 | "@ |
8cb66696 | 7747 | nr\t%0,%2 |
fc0ea003 | 7748 | ni\t%S0,%b2 |
19b63d8e | 7749 | #" |
9381e3f1 WG |
7750 | [(set_attr "op_type" "RR,SI,SS") |
7751 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7752 | |
deb9351f DV |
7753 | ; |
7754 | ; And with complement | |
7755 | ; | |
7756 | ; c = ~b & a = (b & a) ^ a | |
7757 | ||
7758 | (define_insn_and_split "*andc_split_<mode>" | |
7759 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7760 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7761 | (match_operand:GPR 2 "general_operand" ""))) | |
7762 | (clobber (reg:CC CC_REGNUM))] | |
80f8cd77 | 7763 | "!TARGET_Z15 |
4a9733f3 | 7764 | && ! reload_completed |
ad7ab32e DV |
7765 | && (GET_CODE (operands[0]) != MEM |
7766 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7767 | on the split xor if (b & a) is stored into a pseudo. */ | |
7768 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7769 | "#" |
7770 | "&& 1" | |
7771 | [ | |
7772 | (parallel | |
7773 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7774 | (clobber (reg:CC CC_REGNUM))]) | |
7775 | (parallel | |
7776 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7777 | (clobber (reg:CC CC_REGNUM))])] | |
7778 | { | |
7779 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7780 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7781 | else | |
7782 | operands[3] = operands[0]; | |
7783 | }) | |
7784 | ||
19b63d8e UW |
7785 | ; |
7786 | ; Block and (NC) patterns. | |
7787 | ; | |
7788 | ||
7789 | (define_insn "*nc" | |
7790 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7791 | (and:BLK (match_dup 0) | |
7792 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7793 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7794 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7795 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7796 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7797 | [(set_attr "op_type" "SS") |
7798 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7799 | |
7800 | (define_split | |
7801 | [(set (match_operand 0 "memory_operand" "") | |
7802 | (and (match_dup 0) | |
7803 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7804 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7805 | "reload_completed |
7806 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7807 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7808 | [(parallel | |
7809 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7810 | (use (match_dup 2)) | |
ae156f85 | 7811 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7812 | { |
7813 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7814 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7815 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7816 | }) | |
7817 | ||
7818 | (define_peephole2 | |
7819 | [(parallel | |
7820 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7821 | (and:BLK (match_dup 0) | |
7822 | (match_operand:BLK 1 "memory_operand" ""))) | |
7823 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7824 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7825 | (parallel |
7826 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7827 | (and:BLK (match_dup 3) | |
7828 | (match_operand:BLK 4 "memory_operand" ""))) | |
7829 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7830 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7831 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7832 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7833 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7834 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7835 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7836 | [(parallel | |
7837 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7838 | (use (match_dup 8)) | |
ae156f85 | 7839 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7840 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7841 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7842 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7843 | ||
9db1d521 HP |
7844 | |
7845 | ;; | |
7846 | ;;- Bit set (inclusive or) instructions. | |
7847 | ;; | |
7848 | ||
047d35ed AS |
7849 | (define_expand "ior<mode>3" |
7850 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7851 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7852 | (match_operand:INT 2 "general_operand" ""))) | |
7853 | (clobber (reg:CC CC_REGNUM))] | |
7854 | "" | |
7855 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7856 | ||
9db1d521 HP |
7857 | ; |
7858 | ; iordi3 instruction pattern(s). | |
7859 | ; | |
7860 | ||
4023fb28 | 7861 | (define_insn "*iordi3_cc" |
ae156f85 | 7862 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7863 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7864 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7865 | (const_int 0))) |
3e4be43f | 7866 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7867 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7868 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7869 | "@ |
d40c829f | 7870 | ogr\t%0,%2 |
65b1d8ea | 7871 | ogrk\t%0,%1,%2 |
d40c829f | 7872 | og\t%0,%2" |
65b1d8ea AK |
7873 | [(set_attr "op_type" "RRE,RRF,RXY") |
7874 | (set_attr "cpu_facility" "*,z196,*") | |
7875 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7876 | |
7877 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7878 | [(set (reg CC_REGNUM) |
65b1d8ea | 7879 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7880 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7881 | (const_int 0))) |
65b1d8ea | 7882 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7883 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7884 | "@ |
d40c829f | 7885 | ogr\t%0,%2 |
65b1d8ea | 7886 | ogrk\t%0,%1,%2 |
d40c829f | 7887 | og\t%0,%2" |
65b1d8ea AK |
7888 | [(set_attr "op_type" "RRE,RRF,RXY") |
7889 | (set_attr "cpu_facility" "*,z196,*") | |
7890 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7891 | |
3af8e996 | 7892 | (define_insn "*iordi3" |
65b1d8ea | 7893 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7894 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7895 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7896 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7897 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7898 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7899 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7900 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7901 | "@ |
7902 | oihh\t%0,%i2 | |
7903 | oihl\t%0,%i2 | |
7904 | oilh\t%0,%i2 | |
7905 | oill\t%0,%i2 | |
7906 | oihf\t%0,%k2 | |
7907 | oilf\t%0,%k2 | |
7908 | ogr\t%0,%2 | |
65b1d8ea | 7909 | ogrk\t%0,%1,%2 |
ec24698e UW |
7910 | og\t%0,%2 |
7911 | # | |
7912 | #" | |
65b1d8ea AK |
7913 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7914 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7915 | (set_attr "z10prop" "z10_super_E1, |
7916 | z10_super_E1, | |
7917 | z10_super_E1, | |
7918 | z10_super_E1, | |
7919 | z10_super_E1, | |
7920 | z10_super_E1, | |
7921 | z10_super_E1, | |
65b1d8ea | 7922 | *, |
9381e3f1 WG |
7923 | z10_super_E1, |
7924 | *, | |
7925 | *")]) | |
0dfa6c5e UW |
7926 | |
7927 | (define_split | |
7928 | [(set (match_operand:DI 0 "s_operand" "") | |
7929 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7930 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7931 | "reload_completed" |
7932 | [(parallel | |
7933 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7934 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7935 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7936 | |
9db1d521 HP |
7937 | ; |
7938 | ; iorsi3 instruction pattern(s). | |
7939 | ; | |
7940 | ||
4023fb28 | 7941 | (define_insn "*iorsi3_cc" |
ae156f85 | 7942 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7943 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7944 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7945 | (const_int 0))) |
65b1d8ea | 7946 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7947 | (ior:SI (match_dup 1) (match_dup 2)))] |
7948 | "s390_match_ccmode(insn, CCTmode)" | |
7949 | "@ | |
ec24698e | 7950 | oilf\t%0,%o2 |
d40c829f | 7951 | or\t%0,%2 |
65b1d8ea | 7952 | ork\t%0,%1,%2 |
d40c829f UW |
7953 | o\t%0,%2 |
7954 | oy\t%0,%2" | |
65b1d8ea | 7955 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7956 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7957 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7958 | |
7959 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7960 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7961 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7962 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7963 | (const_int 0))) |
65b1d8ea | 7964 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7965 | "s390_match_ccmode(insn, CCTmode)" |
7966 | "@ | |
ec24698e | 7967 | oilf\t%0,%o2 |
d40c829f | 7968 | or\t%0,%2 |
65b1d8ea | 7969 | ork\t%0,%1,%2 |
d40c829f UW |
7970 | o\t%0,%2 |
7971 | oy\t%0,%2" | |
65b1d8ea | 7972 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7973 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7974 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7975 | |
8cb66696 | 7976 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7977 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7978 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7979 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7980 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7981 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7982 | "@ |
f19a9af7 AK |
7983 | oilh\t%0,%i2 |
7984 | oill\t%0,%i2 | |
ec24698e | 7985 | oilf\t%0,%o2 |
d40c829f | 7986 | or\t%0,%2 |
65b1d8ea | 7987 | ork\t%0,%1,%2 |
d40c829f | 7988 | o\t%0,%2 |
8cb66696 | 7989 | oy\t%0,%2 |
0dfa6c5e | 7990 | # |
19b63d8e | 7991 | #" |
65b1d8ea | 7992 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7993 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7994 | (set_attr "z10prop" "z10_super_E1, |
7995 | z10_super_E1, | |
7996 | z10_super_E1, | |
7997 | z10_super_E1, | |
65b1d8ea | 7998 | *, |
9381e3f1 WG |
7999 | z10_super_E1, |
8000 | z10_super_E1, | |
8001 | *, | |
8002 | *")]) | |
8cb66696 UW |
8003 | |
8004 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 8005 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 8006 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 8007 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 8008 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8009 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
8010 | "@ |
8011 | or\t%0,%2 | |
8cb66696 | 8012 | o\t%0,%2 |
0dfa6c5e | 8013 | # |
19b63d8e | 8014 | #" |
9381e3f1 WG |
8015 | [(set_attr "op_type" "RR,RX,SI,SS") |
8016 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8017 | |
8018 | (define_split | |
8019 | [(set (match_operand:SI 0 "s_operand" "") | |
8020 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8021 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8022 | "reload_completed" |
8023 | [(parallel | |
8024 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8025 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8026 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 8027 | |
4023fb28 UW |
8028 | ; |
8029 | ; iorhi3 instruction pattern(s). | |
8030 | ; | |
8031 | ||
8cb66696 | 8032 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
8033 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8034 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
8035 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 8036 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8037 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 8038 | "@ |
d40c829f | 8039 | or\t%0,%2 |
65b1d8ea | 8040 | ork\t%0,%1,%2 |
8cb66696 | 8041 | oill\t%0,%x2 |
0dfa6c5e | 8042 | # |
19b63d8e | 8043 | #" |
65b1d8ea AK |
8044 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
8045 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
8046 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
8047 | |
8048 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
8049 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
8050 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
8051 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 8052 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8053 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
8054 | "@ | |
8055 | or\t%0,%2 | |
0dfa6c5e | 8056 | # |
19b63d8e | 8057 | #" |
9381e3f1 WG |
8058 | [(set_attr "op_type" "RR,SI,SS") |
8059 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8060 | |
8061 | (define_split | |
8062 | [(set (match_operand:HI 0 "s_operand" "") | |
8063 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8064 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8065 | "reload_completed" |
8066 | [(parallel | |
8067 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8068 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8069 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 8070 | |
9db1d521 | 8071 | ; |
4023fb28 | 8072 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
8073 | ; |
8074 | ||
8cb66696 | 8075 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
8076 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8077 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
8078 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 8079 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8080 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 8081 | "@ |
d40c829f | 8082 | or\t%0,%2 |
65b1d8ea | 8083 | ork\t%0,%1,%2 |
8cb66696 | 8084 | oill\t%0,%b2 |
fc0ea003 UW |
8085 | oi\t%S0,%b2 |
8086 | oiy\t%S0,%b2 | |
19b63d8e | 8087 | #" |
65b1d8ea | 8088 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 8089 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
8090 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
8091 | z10_super,z10_super,*")]) | |
8cb66696 UW |
8092 | |
8093 | (define_insn "*iorqi3_esa" | |
8094 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
8095 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
8096 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 8097 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8098 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 8099 | "@ |
8cb66696 | 8100 | or\t%0,%2 |
fc0ea003 | 8101 | oi\t%S0,%b2 |
19b63d8e | 8102 | #" |
9381e3f1 WG |
8103 | [(set_attr "op_type" "RR,SI,SS") |
8104 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 8105 | |
4a9733f3 AK |
8106 | ; |
8107 | ; And/Or with complement | |
8108 | ; | |
8109 | ||
8110 | ; ncrk, ncgrk, ocrk, ocgrk | |
8111 | (define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cc" | |
8112 | [(set (reg CC_REGNUM) | |
8113 | (compare | |
8114 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8115 | (match_operand:GPR 2 "register_operand" "d")) | |
8116 | (const_int 0))) | |
8117 | (set (match_operand:GPR 0 "register_operand" "=d") | |
8118 | (ANDOR:GPR (not:GPR (match_dup 1)) | |
8119 | (match_dup 2)))] | |
80f8cd77 | 8120 | "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" |
4a9733f3 AK |
8121 | "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" |
8122 | [(set_attr "op_type" "RRF")]) | |
8123 | ||
8124 | ; ncrk, ncgrk, ocrk, ocgrk | |
8125 | (define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cconly" | |
8126 | [(set (reg CC_REGNUM) | |
8127 | (compare | |
8128 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8129 | (match_operand:GPR 2 "register_operand" "d")) | |
8130 | (const_int 0))) | |
8131 | (clobber (match_scratch:GPR 0 "=d"))] | |
80f8cd77 | 8132 | "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" |
4a9733f3 AK |
8133 | "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" |
8134 | [(set_attr "op_type" "RRF")]) | |
8135 | ||
8136 | ; ncrk, ncgrk, ocrk, ocgrk | |
8137 | (define_insn "*<ANDOR:bitops_name>c<GPR:mode>" | |
8138 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8139 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8140 | (match_operand:GPR 2 "register_operand" "d"))) | |
8141 | (clobber (reg:CC CC_REGNUM))] | |
80f8cd77 | 8142 | "TARGET_Z15" |
4a9733f3 AK |
8143 | "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" |
8144 | [(set_attr "op_type" "RRF")]) | |
8145 | ||
8146 | ; | |
8147 | ;- Nand/Nor instructions. | |
8148 | ; | |
8149 | ||
8150 | ; nnrk, nngrk, nork, nogrk | |
8151 | (define_insn "*n<ANDOR:inv_bitops_name><GPR:mode>_cc" | |
8152 | [(set (reg CC_REGNUM) | |
8153 | (compare | |
8154 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8155 | (not:GPR (match_operand:GPR 2 "register_operand" "d"))) | |
8156 | (const_int 0))) | |
8157 | (set (match_operand:GPR 0 "register_operand" "=d") | |
8158 | (ANDOR:GPR (not:GPR (match_dup 1)) | |
8159 | (not:GPR (match_dup 2))))] | |
80f8cd77 | 8160 | "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" |
4a9733f3 AK |
8161 | "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" |
8162 | [(set_attr "op_type" "RRF")]) | |
8163 | ||
8164 | ; nnrk, nngrk, nork, nogrk | |
8165 | (define_insn "*n<ANDOR:inv_bitops_name><mode>_cconly" | |
8166 | [(set (reg CC_REGNUM) | |
8167 | (compare | |
8168 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8169 | (not:GPR (match_operand:GPR 2 "register_operand" "d"))) | |
8170 | (const_int 0))) | |
8171 | (clobber (match_scratch:GPR 0 "=d"))] | |
80f8cd77 | 8172 | "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" |
4a9733f3 AK |
8173 | "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" |
8174 | [(set_attr "op_type" "RRF")]) | |
8175 | ||
8176 | ; nnrk, nngrk, nork, nogrk | |
8177 | (define_insn "*n<ANDOR:inv_bitops_name><mode>" | |
8178 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8179 | (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) | |
8180 | (not:GPR (match_operand:GPR 2 "register_operand" "d")))) | |
8181 | (clobber (reg:CC CC_REGNUM))] | |
80f8cd77 | 8182 | "TARGET_Z15" |
4a9733f3 AK |
8183 | "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" |
8184 | [(set_attr "op_type" "RRF")]) | |
8185 | ||
8186 | ||
19b63d8e UW |
8187 | ; |
8188 | ; Block inclusive or (OC) patterns. | |
8189 | ; | |
8190 | ||
8191 | (define_insn "*oc" | |
8192 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8193 | (ior:BLK (match_dup 0) | |
8194 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8195 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8196 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8197 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8198 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
8199 | [(set_attr "op_type" "SS") |
8200 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8201 | |
8202 | (define_split | |
8203 | [(set (match_operand 0 "memory_operand" "") | |
8204 | (ior (match_dup 0) | |
8205 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8206 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8207 | "reload_completed |
8208 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8209 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8210 | [(parallel | |
8211 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
8212 | (use (match_dup 2)) | |
ae156f85 | 8213 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8214 | { |
8215 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8216 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8217 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8218 | }) | |
8219 | ||
8220 | (define_peephole2 | |
8221 | [(parallel | |
8222 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8223 | (ior:BLK (match_dup 0) | |
8224 | (match_operand:BLK 1 "memory_operand" ""))) | |
8225 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8226 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8227 | (parallel |
8228 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8229 | (ior:BLK (match_dup 3) | |
8230 | (match_operand:BLK 4 "memory_operand" ""))) | |
8231 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8232 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8233 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8234 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8235 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8236 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8237 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8238 | [(parallel | |
8239 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
8240 | (use (match_dup 8)) | |
ae156f85 | 8241 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8242 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8243 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8244 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8245 | ||
9db1d521 HP |
8246 | |
8247 | ;; | |
8248 | ;;- Xor instructions. | |
8249 | ;; | |
8250 | ||
047d35ed AS |
8251 | (define_expand "xor<mode>3" |
8252 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
8253 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
8254 | (match_operand:INT 2 "general_operand" ""))) | |
8255 | (clobber (reg:CC CC_REGNUM))] | |
8256 | "" | |
8257 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
8258 | ||
3c91f126 AK |
8259 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
8260 | ; simplifications. So its better to have something matching. | |
8261 | (define_split | |
8262 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
8263 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
8264 | "" | |
8265 | [(parallel | |
8266 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
8267 | (clobber (reg:CC CC_REGNUM))])] | |
8268 | { | |
8269 | operands[2] = constm1_rtx; | |
8270 | if (!s390_logical_operator_ok_p (operands)) | |
8271 | FAIL; | |
8272 | }) | |
8273 | ||
9db1d521 HP |
8274 | ; |
8275 | ; xordi3 instruction pattern(s). | |
8276 | ; | |
8277 | ||
4023fb28 | 8278 | (define_insn "*xordi3_cc" |
ae156f85 | 8279 | [(set (reg CC_REGNUM) |
3e4be43f UW |
8280 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
8281 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 8282 | (const_int 0))) |
3e4be43f | 8283 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 8284 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 8285 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 8286 | "@ |
d40c829f | 8287 | xgr\t%0,%2 |
65b1d8ea | 8288 | xgrk\t%0,%1,%2 |
d40c829f | 8289 | xg\t%0,%2" |
65b1d8ea | 8290 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 8291 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 8292 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
8293 | |
8294 | (define_insn "*xordi3_cconly" | |
ae156f85 | 8295 | [(set (reg CC_REGNUM) |
3e4be43f UW |
8296 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
8297 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 8298 | (const_int 0))) |
3e4be43f | 8299 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 8300 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 8301 | "@ |
d40c829f | 8302 | xgr\t%0,%2 |
65b1d8ea | 8303 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 8304 | xg\t%0,%2" |
65b1d8ea AK |
8305 | [(set_attr "op_type" "RRE,RRF,RXY") |
8306 | (set_attr "cpu_facility" "*,z196,*") | |
8307 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 8308 | |
3af8e996 | 8309 | (define_insn "*xordi3" |
3e4be43f UW |
8310 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
8311 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
8312 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 8313 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8314 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
8315 | "@ |
8316 | xihf\t%0,%k2 | |
8317 | xilf\t%0,%k2 | |
8318 | xgr\t%0,%2 | |
65b1d8ea | 8319 | xgrk\t%0,%1,%2 |
ec24698e UW |
8320 | xg\t%0,%2 |
8321 | # | |
8322 | #" | |
65b1d8ea AK |
8323 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
8324 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
8325 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
8326 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8327 | |
8328 | (define_split | |
8329 | [(set (match_operand:DI 0 "s_operand" "") | |
8330 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 8331 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8332 | "reload_completed" |
8333 | [(parallel | |
8334 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8335 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8336 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 8337 | |
9db1d521 HP |
8338 | ; |
8339 | ; xorsi3 instruction pattern(s). | |
8340 | ; | |
8341 | ||
4023fb28 | 8342 | (define_insn "*xorsi3_cc" |
ae156f85 | 8343 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8344 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8345 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8346 | (const_int 0))) |
65b1d8ea | 8347 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
8348 | (xor:SI (match_dup 1) (match_dup 2)))] |
8349 | "s390_match_ccmode(insn, CCTmode)" | |
8350 | "@ | |
ec24698e | 8351 | xilf\t%0,%o2 |
d40c829f | 8352 | xr\t%0,%2 |
65b1d8ea | 8353 | xrk\t%0,%1,%2 |
d40c829f UW |
8354 | x\t%0,%2 |
8355 | xy\t%0,%2" | |
65b1d8ea | 8356 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8357 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8358 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8359 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
8360 | |
8361 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 8362 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8363 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8364 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8365 | (const_int 0))) |
65b1d8ea | 8366 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
8367 | "s390_match_ccmode(insn, CCTmode)" |
8368 | "@ | |
ec24698e | 8369 | xilf\t%0,%o2 |
d40c829f | 8370 | xr\t%0,%2 |
65b1d8ea | 8371 | xrk\t%0,%1,%2 |
d40c829f UW |
8372 | x\t%0,%2 |
8373 | xy\t%0,%2" | |
65b1d8ea | 8374 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8375 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8376 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8377 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 8378 | |
8cb66696 | 8379 | (define_insn "*xorsi3" |
65b1d8ea AK |
8380 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
8381 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
8382 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 8383 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8384 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8385 | "@ |
ec24698e | 8386 | xilf\t%0,%o2 |
d40c829f | 8387 | xr\t%0,%2 |
65b1d8ea | 8388 | xrk\t%0,%1,%2 |
d40c829f | 8389 | x\t%0,%2 |
8cb66696 | 8390 | xy\t%0,%2 |
0dfa6c5e | 8391 | # |
19b63d8e | 8392 | #" |
65b1d8ea | 8393 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8394 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8395 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8396 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8397 | |
8398 | (define_split | |
8399 | [(set (match_operand:SI 0 "s_operand" "") | |
8400 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8401 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8402 | "reload_completed" |
8403 | [(parallel | |
8404 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8405 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8406 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8407 | |
9db1d521 HP |
8408 | ; |
8409 | ; xorhi3 instruction pattern(s). | |
8410 | ; | |
8411 | ||
8cb66696 | 8412 | (define_insn "*xorhi3" |
65b1d8ea AK |
8413 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8414 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8415 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8416 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8417 | "s390_logical_operator_ok_p (operands)" |
8418 | "@ | |
ec24698e | 8419 | xilf\t%0,%x2 |
8cb66696 | 8420 | xr\t%0,%2 |
65b1d8ea | 8421 | xrk\t%0,%1,%2 |
0dfa6c5e | 8422 | # |
19b63d8e | 8423 | #" |
65b1d8ea AK |
8424 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8425 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8426 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8427 | |
8428 | (define_split | |
8429 | [(set (match_operand:HI 0 "s_operand" "") | |
8430 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8431 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8432 | "reload_completed" |
8433 | [(parallel | |
8434 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8435 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8436 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8437 | |
9db1d521 HP |
8438 | ; |
8439 | ; xorqi3 instruction pattern(s). | |
8440 | ; | |
8441 | ||
8cb66696 | 8442 | (define_insn "*xorqi3" |
65b1d8ea AK |
8443 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8444 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8445 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8446 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8447 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8448 | "@ |
ec24698e | 8449 | xilf\t%0,%b2 |
8cb66696 | 8450 | xr\t%0,%2 |
65b1d8ea | 8451 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8452 | xi\t%S0,%b2 |
8453 | xiy\t%S0,%b2 | |
19b63d8e | 8454 | #" |
65b1d8ea | 8455 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8456 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8457 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8458 | |
4023fb28 | 8459 | |
19b63d8e UW |
8460 | ; |
8461 | ; Block exclusive or (XC) patterns. | |
8462 | ; | |
8463 | ||
8464 | (define_insn "*xc" | |
8465 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8466 | (xor:BLK (match_dup 0) | |
8467 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8468 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8469 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8470 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8471 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8472 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8473 | |
8474 | (define_split | |
8475 | [(set (match_operand 0 "memory_operand" "") | |
8476 | (xor (match_dup 0) | |
8477 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8478 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8479 | "reload_completed |
8480 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8481 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8482 | [(parallel | |
8483 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8484 | (use (match_dup 2)) | |
ae156f85 | 8485 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8486 | { |
8487 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8488 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8489 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8490 | }) | |
8491 | ||
8492 | (define_peephole2 | |
8493 | [(parallel | |
8494 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8495 | (xor:BLK (match_dup 0) | |
8496 | (match_operand:BLK 1 "memory_operand" ""))) | |
8497 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8498 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8499 | (parallel |
8500 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8501 | (xor:BLK (match_dup 3) | |
8502 | (match_operand:BLK 4 "memory_operand" ""))) | |
8503 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8504 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8505 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8506 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8507 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8508 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8509 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8510 | [(parallel | |
8511 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8512 | (use (match_dup 8)) | |
ae156f85 | 8513 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8514 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8515 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8516 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8517 | ||
8518 | ; | |
8519 | ; Block xor (XC) patterns with src == dest. | |
8520 | ; | |
8521 | ||
8522 | (define_insn "*xc_zero" | |
8523 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8524 | (const_int 0)) | |
8525 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8526 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8527 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8528 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8529 | [(set_attr "op_type" "SS") |
8530 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8531 | |
8532 | (define_peephole2 | |
8533 | [(parallel | |
8534 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8535 | (const_int 0)) | |
8536 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8537 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8538 | (parallel |
8539 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8540 | (const_int 0)) | |
8541 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8542 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8543 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8544 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8545 | [(parallel | |
8546 | [(set (match_dup 4) (const_int 0)) | |
8547 | (use (match_dup 5)) | |
ae156f85 | 8548 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8549 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8550 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8551 | ||
4a9733f3 AK |
8552 | ; |
8553 | ;- Nxor instructions. | |
8554 | ; | |
8555 | ||
8556 | ; nxrk, nxgrk | |
8557 | (define_insn "*nxor<GPR:mode>_cc" | |
8558 | [(set (reg CC_REGNUM) | |
8559 | (compare | |
8560 | (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") | |
8561 | (match_operand:GPR 2 "register_operand" "d"))) | |
8562 | (const_int 0))) | |
8563 | (set (match_operand:GPR 0 "register_operand" "=d") | |
8564 | (xor:GPR (not:GPR (match_dup 1)) | |
8565 | (match_dup 2)))] | |
80f8cd77 | 8566 | "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" |
4a9733f3 AK |
8567 | "nx<GPR:g>rk\t%0,%1,%2" |
8568 | [(set_attr "op_type" "RRF")]) | |
8569 | ||
8570 | ; nxrk, nxgrk | |
8571 | (define_insn "*nxor<mode>_cconly" | |
8572 | [(set (reg CC_REGNUM) | |
8573 | (compare | |
8574 | (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") | |
8575 | (match_operand:GPR 2 "register_operand" "d"))) | |
8576 | (const_int 0))) | |
8577 | (clobber (match_scratch:GPR 0 "=d"))] | |
80f8cd77 | 8578 | "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" |
4a9733f3 AK |
8579 | "nx<GPR:g>rk\t%0,%1,%2" |
8580 | [(set_attr "op_type" "RRF")]) | |
8581 | ||
8582 | ; nxrk, nxgrk | |
8583 | (define_insn "*nxor<mode>" | |
8584 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8585 | (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") | |
8586 | (match_operand:GPR 2 "register_operand" "d")))) | |
8587 | (clobber (reg:CC CC_REGNUM))] | |
80f8cd77 | 8588 | "TARGET_Z15" |
4a9733f3 AK |
8589 | "nx<GPR:g>rk\t%0,%1,%2" |
8590 | [(set_attr "op_type" "RRF")]) | |
9db1d521 HP |
8591 | |
8592 | ;; | |
8593 | ;;- Negate instructions. | |
8594 | ;; | |
8595 | ||
8596 | ; | |
9a91a21f | 8597 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8598 | ; |
8599 | ||
9a91a21f | 8600 | (define_expand "neg<mode>2" |
9db1d521 | 8601 | [(parallel |
9a91a21f AS |
8602 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8603 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8604 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8605 | "" |
8606 | "") | |
8607 | ||
26a89301 | 8608 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8609 | [(set (reg CC_REGNUM) |
26a89301 UW |
8610 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8611 | (match_operand:SI 1 "register_operand" "d") 0) | |
8612 | (const_int 32)) (const_int 32))) | |
8613 | (const_int 0))) | |
8614 | (set (match_operand:DI 0 "register_operand" "=d") | |
8615 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8616 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8617 | "lcgfr\t%0,%1" |
729e750f WG |
8618 | [(set_attr "op_type" "RRE") |
8619 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8620 | |
26a89301 UW |
8621 | (define_insn "*negdi2_sign" |
8622 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8623 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8624 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8625 | "TARGET_ZARCH" |
26a89301 | 8626 | "lcgfr\t%0,%1" |
729e750f WG |
8627 | [(set_attr "op_type" "RRE") |
8628 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8629 | |
43a09b63 | 8630 | ; lcr, lcgr |
9a91a21f | 8631 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8632 | [(set (reg CC_REGNUM) |
9a91a21f | 8633 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8634 | (const_int 0))) |
9a91a21f AS |
8635 | (set (match_operand:GPR 0 "register_operand" "=d") |
8636 | (neg:GPR (match_dup 1)))] | |
8637 | "s390_match_ccmode (insn, CCAmode)" | |
8638 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8639 | [(set_attr "op_type" "RR<E>") |
8640 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8641 | |
8642 | ; lcr, lcgr | |
9a91a21f | 8643 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8644 | [(set (reg CC_REGNUM) |
9a91a21f | 8645 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8646 | (const_int 0))) |
9a91a21f AS |
8647 | (clobber (match_scratch:GPR 0 "=d"))] |
8648 | "s390_match_ccmode (insn, CCAmode)" | |
8649 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8650 | [(set_attr "op_type" "RR<E>") |
8651 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8652 | |
8653 | ; lcr, lcgr | |
9a91a21f AS |
8654 | (define_insn "*neg<mode>2" |
8655 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8656 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8657 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8658 | "" |
8659 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8660 | [(set_attr "op_type" "RR<E>") |
8661 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8662 | |
b7d19263 | 8663 | (define_insn "*negdi2_31" |
9db1d521 HP |
8664 | [(set (match_operand:DI 0 "register_operand" "=d") |
8665 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8666 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8667 | "!TARGET_ZARCH" |
b7d19263 AK |
8668 | "#") |
8669 | ||
8670 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8671 | ||
8672 | ; Doing the twos complement separately on the SImode parts does an | |
8673 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8674 | ; ... unless the +1 on the low part created an overflow. | |
8675 | ||
8676 | (define_split | |
8677 | [(set (match_operand:DI 0 "register_operand" "") | |
8678 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8679 | (clobber (reg:CC CC_REGNUM))] | |
8680 | "!TARGET_ZARCH | |
8681 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8682 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8683 | && reload_completed" | |
26a89301 UW |
8684 | [(parallel |
8685 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8686 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8687 | (parallel |
ae156f85 | 8688 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8689 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8690 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8691 | (set (pc) | |
ae156f85 | 8692 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8693 | (pc) |
8694 | (label_ref (match_dup 6)))) | |
8695 | (parallel | |
8696 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8697 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8698 | (match_dup 6)] |
8699 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8700 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8701 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8702 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8703 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8704 | |
b7d19263 AK |
8705 | ; Like above but first make a copy of the low part of the src operand |
8706 | ; since it might overlap with the high part of the destination. | |
8707 | ||
8708 | (define_split | |
8709 | [(set (match_operand:DI 0 "register_operand" "") | |
8710 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8711 | (clobber (reg:CC CC_REGNUM))] | |
8712 | "!TARGET_ZARCH | |
8713 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8714 | && reload_completed" | |
8715 | [; Make a backup of op5 first | |
8716 | (set (match_dup 4) (match_dup 5)) | |
8717 | ; Setting op2 here might clobber op5 | |
8718 | (parallel | |
8719 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8720 | (clobber (reg:CC CC_REGNUM))]) | |
8721 | (parallel | |
8722 | [(set (reg:CCAP CC_REGNUM) | |
8723 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8724 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8725 | (set (pc) | |
8726 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8727 | (pc) | |
8728 | (label_ref (match_dup 6)))) | |
8729 | (parallel | |
8730 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8731 | (clobber (reg:CC CC_REGNUM))]) | |
8732 | (match_dup 6)] | |
8733 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8734 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8735 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8736 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8737 | operands[6] = gen_label_rtx ();") | |
8738 | ||
9db1d521 | 8739 | ; |
f5905b37 | 8740 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8741 | ; |
8742 | ||
f5905b37 | 8743 | (define_expand "neg<mode>2" |
9db1d521 | 8744 | [(parallel |
2de2b3f9 AK |
8745 | [(set (match_operand:BFP 0 "register_operand") |
8746 | (neg:BFP (match_operand:BFP 1 "register_operand"))) | |
ae156f85 | 8747 | (clobber (reg:CC CC_REGNUM))])] |
2de2b3f9 | 8748 | "TARGET_HARD_FLOAT") |
9db1d521 | 8749 | |
43a09b63 | 8750 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8751 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8752 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8753 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8754 | (match_operand:BFP 2 "const0_operand" ""))) | |
8755 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8756 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8757 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8758 | "lc<xde>br\t%0,%1" |
26a89301 | 8759 | [(set_attr "op_type" "RRE") |
f5905b37 | 8760 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8761 | |
8762 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8763 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8764 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8765 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8766 | (match_operand:BFP 2 "const0_operand" ""))) | |
8767 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8768 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8769 | "lc<xde>br\t%0,%1" |
26a89301 | 8770 | [(set_attr "op_type" "RRE") |
f5905b37 | 8771 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8772 | |
85dae55a AK |
8773 | ; lcdfr |
8774 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8775 | [(set (match_operand:FP 0 "register_operand" "=f") |
8776 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8777 | "TARGET_DFP" |
85dae55a AK |
8778 | "lcdfr\t%0,%1" |
8779 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8780 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8781 | |
43a09b63 | 8782 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8783 | ; FIXME: wflcdb does not clobber cc |
2de2b3f9 | 8784 | ; FIXME: Does wflcdb ever match here? |
f5905b37 | 8785 | (define_insn "*neg<mode>2" |
2de2b3f9 AK |
8786 | [(set (match_operand:BFP 0 "register_operand" "=f,v,v") |
8787 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) | |
ae156f85 | 8788 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8789 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8790 | "@ |
8791 | lc<xde>br\t%0,%1 | |
2de2b3f9 AK |
8792 | wflcdb\t%0,%1 |
8793 | wflcsb\t%0,%1" | |
8794 | [(set_attr "op_type" "RRE,VRR,VRR") | |
8795 | (set_attr "cpu_facility" "*,vx,vxe") | |
8796 | (set_attr "type" "fsimp<mode>,*,*") | |
8797 | (set_attr "enabled" "*,<DF>,<SF>")]) | |
9db1d521 | 8798 | |
9db1d521 HP |
8799 | |
8800 | ;; | |
8801 | ;;- Absolute value instructions. | |
8802 | ;; | |
8803 | ||
8804 | ; | |
9a91a21f | 8805 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8806 | ; |
8807 | ||
26a89301 | 8808 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8809 | [(set (reg CC_REGNUM) |
26a89301 UW |
8810 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8811 | (match_operand:SI 1 "register_operand" "d") 0) | |
8812 | (const_int 32)) (const_int 32))) | |
8813 | (const_int 0))) | |
8814 | (set (match_operand:DI 0 "register_operand" "=d") | |
8815 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8816 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8817 | "lpgfr\t%0,%1" |
729e750f WG |
8818 | [(set_attr "op_type" "RRE") |
8819 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8820 | |
8821 | (define_insn "*absdi2_sign" | |
8822 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8823 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8824 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8825 | "TARGET_ZARCH" |
26a89301 | 8826 | "lpgfr\t%0,%1" |
729e750f WG |
8827 | [(set_attr "op_type" "RRE") |
8828 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8829 | |
43a09b63 | 8830 | ; lpr, lpgr |
9a91a21f | 8831 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8832 | [(set (reg CC_REGNUM) |
9a91a21f | 8833 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8834 | (const_int 0))) |
9a91a21f AS |
8835 | (set (match_operand:GPR 0 "register_operand" "=d") |
8836 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8837 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8838 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8839 | [(set_attr "op_type" "RR<E>") |
8840 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8841 | |
9381e3f1 | 8842 | ; lpr, lpgr |
9a91a21f | 8843 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8844 | [(set (reg CC_REGNUM) |
9a91a21f | 8845 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8846 | (const_int 0))) |
9a91a21f | 8847 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8848 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8849 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8850 | [(set_attr "op_type" "RR<E>") |
8851 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8852 | |
8853 | ; lpr, lpgr | |
9a91a21f AS |
8854 | (define_insn "abs<mode>2" |
8855 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8856 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8857 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8858 | "" |
9a91a21f | 8859 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8860 | [(set_attr "op_type" "RR<E>") |
8861 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8862 | |
9db1d521 | 8863 | ; |
f5905b37 | 8864 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8865 | ; |
8866 | ||
f5905b37 | 8867 | (define_expand "abs<mode>2" |
9db1d521 | 8868 | [(parallel |
7b6baae1 AK |
8869 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8870 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8871 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8872 | "TARGET_HARD_FLOAT" |
8873 | "") | |
8874 | ||
43a09b63 | 8875 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8876 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8877 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8878 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8879 | (match_operand:BFP 2 "const0_operand" ""))) | |
8880 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8881 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8882 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8883 | "lp<xde>br\t%0,%1" |
26a89301 | 8884 | [(set_attr "op_type" "RRE") |
f5905b37 | 8885 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8886 | |
8887 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8888 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8889 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8890 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8891 | (match_operand:BFP 2 "const0_operand" ""))) | |
8892 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8893 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8894 | "lp<xde>br\t%0,%1" |
26a89301 | 8895 | [(set_attr "op_type" "RRE") |
f5905b37 | 8896 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8897 | |
85dae55a AK |
8898 | ; lpdfr |
8899 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8900 | [(set (match_operand:FP 0 "register_operand" "=f") |
8901 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8902 | "TARGET_DFP" |
85dae55a AK |
8903 | "lpdfr\t%0,%1" |
8904 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8905 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8906 | |
43a09b63 | 8907 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8908 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8909 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8910 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8911 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8912 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8913 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8914 | "@ |
8915 | lp<xde>br\t%0,%1 | |
8916 | wflpdb\t%0,%1" | |
8917 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8918 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8919 | (set_attr "type" "fsimp<mode>,*") |
8920 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8921 | |
9db1d521 | 8922 | |
3ef093a8 AK |
8923 | ;; |
8924 | ;;- Negated absolute value instructions | |
8925 | ;; | |
8926 | ||
8927 | ; | |
8928 | ; Integer | |
8929 | ; | |
8930 | ||
26a89301 | 8931 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8932 | [(set (reg CC_REGNUM) |
26a89301 UW |
8933 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8934 | (match_operand:SI 1 "register_operand" "d") 0) | |
8935 | (const_int 32)) (const_int 32)))) | |
8936 | (const_int 0))) | |
8937 | (set (match_operand:DI 0 "register_operand" "=d") | |
8938 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8939 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8940 | "lngfr\t%0,%1" |
729e750f WG |
8941 | [(set_attr "op_type" "RRE") |
8942 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8943 | |
26a89301 UW |
8944 | (define_insn "*negabsdi2_sign" |
8945 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8946 | (neg:DI (abs:DI (sign_extend:DI | |
8947 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8948 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8949 | "TARGET_ZARCH" |
26a89301 | 8950 | "lngfr\t%0,%1" |
729e750f WG |
8951 | [(set_attr "op_type" "RRE") |
8952 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8953 | |
43a09b63 | 8954 | ; lnr, lngr |
9a91a21f | 8955 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8956 | [(set (reg CC_REGNUM) |
9a91a21f | 8957 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8958 | (const_int 0))) |
9a91a21f AS |
8959 | (set (match_operand:GPR 0 "register_operand" "=d") |
8960 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8961 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8962 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8963 | [(set_attr "op_type" "RR<E>") |
8964 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8965 | |
8966 | ; lnr, lngr | |
9a91a21f | 8967 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8968 | [(set (reg CC_REGNUM) |
9a91a21f | 8969 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8970 | (const_int 0))) |
9a91a21f | 8971 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8972 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8973 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8974 | [(set_attr "op_type" "RR<E>") |
8975 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8976 | |
8977 | ; lnr, lngr | |
9a91a21f AS |
8978 | (define_insn "*negabs<mode>2" |
8979 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8980 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8981 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8982 | "" |
9a91a21f | 8983 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8984 | [(set_attr "op_type" "RR<E>") |
8985 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8986 | |
3ef093a8 AK |
8987 | ; |
8988 | ; Floating point | |
8989 | ; | |
8990 | ||
43a09b63 | 8991 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8992 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8993 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8994 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8995 | (match_operand:BFP 2 "const0_operand" ""))) | |
8996 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8997 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8998 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8999 | "ln<xde>br\t%0,%1" |
26a89301 | 9000 | [(set_attr "op_type" "RRE") |
f5905b37 | 9001 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
9002 | |
9003 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 9004 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 9005 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
9006 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
9007 | (match_operand:BFP 2 "const0_operand" ""))) | |
9008 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 9009 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 9010 | "ln<xde>br\t%0,%1" |
26a89301 | 9011 | [(set_attr "op_type" "RRE") |
f5905b37 | 9012 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 9013 | |
85dae55a AK |
9014 | ; lndfr |
9015 | (define_insn "*negabs<mode>2_nocc" | |
ef2df516 RS |
9016 | [(set (match_operand:FP 0 "register_operand" "=f") |
9017 | (neg:FP (abs:FP (match_operand:FP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 9018 | "TARGET_DFP" |
85dae55a AK |
9019 | "lndfr\t%0,%1" |
9020 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 9021 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 9022 | |
43a09b63 | 9023 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 9024 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 9025 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
9026 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
9027 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 9028 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 9029 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
9030 | "@ |
9031 | ln<xde>br\t%0,%1 | |
9032 | wflndb\t%0,%1" | |
9033 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 9034 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
9035 | (set_attr "type" "fsimp<mode>,*") |
9036 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 9037 | |
4023fb28 UW |
9038 | ;; |
9039 | ;;- Square root instructions. | |
9040 | ;; | |
9041 | ||
9042 | ; | |
f5905b37 | 9043 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
9044 | ; |
9045 | ||
9381e3f1 | 9046 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 9047 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
9048 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
9049 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 9050 | "TARGET_HARD_FLOAT" |
4023fb28 | 9051 | "@ |
f61a2c7d | 9052 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
9053 | sq<xde>b\t%0,%1 |
9054 | wfsqdb\t%v0,%v1" | |
9055 | [(set_attr "op_type" "RRE,RXE,VRR") | |
9056 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 9057 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 9058 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 9059 | |
9db1d521 HP |
9060 | |
9061 | ;; | |
9062 | ;;- One complement instructions. | |
9063 | ;; | |
9064 | ||
9065 | ; | |
342cf42b | 9066 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 9067 | ; |
c7453384 | 9068 | |
342cf42b | 9069 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 9070 | [(parallel |
342cf42b AS |
9071 | [(set (match_operand:INT 0 "register_operand" "") |
9072 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
9073 | (const_int -1))) | |
ae156f85 | 9074 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 9075 | "" |
4023fb28 | 9076 | "") |
9db1d521 HP |
9077 | |
9078 | ||
ec24698e UW |
9079 | ;; |
9080 | ;; Find leftmost bit instructions. | |
9081 | ;; | |
9082 | ||
9083 | (define_expand "clzdi2" | |
9084 | [(set (match_operand:DI 0 "register_operand" "=d") | |
9085 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 9086 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 9087 | { |
d8485bdb TS |
9088 | rtx_insn *insn; |
9089 | rtx clz_equal; | |
ec24698e | 9090 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 9091 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
9092 | |
9093 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
9094 | ||
9095 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
9096 | ||
9381e3f1 | 9097 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 9098 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
9099 | |
9100 | DONE; | |
9101 | }) | |
9102 | ||
33f3393a AK |
9103 | ; CLZ result is in hard reg op0 - this is the high part of the target operand |
9104 | ; The source with the left-most one bit cleared is in hard reg op0 + 1 - the low part | |
ec24698e UW |
9105 | (define_insn "clztidi2" |
9106 | [(set (match_operand:TI 0 "register_operand" "=d") | |
9107 | (ior:TI | |
33f3393a AK |
9108 | (ashift:TI (zero_extend:TI (clz:DI (match_operand:DI 1 "register_operand" "d"))) |
9109 | (const_int 64)) | |
9110 | (zero_extend:TI | |
9111 | (xor:DI (match_dup 1) | |
9112 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
9113 | (subreg:SI (clz:DI (match_dup 1)) 4)))))) | |
ec24698e | 9114 | (clobber (reg:CC CC_REGNUM))] |
406fde6e | 9115 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 9116 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
9117 | "flogr\t%0,%1" |
9118 | [(set_attr "op_type" "RRE")]) | |
9119 | ||
9120 | ||
9db1d521 HP |
9121 | ;; |
9122 | ;;- Rotate instructions. | |
9123 | ;; | |
9124 | ||
9125 | ; | |
9a91a21f | 9126 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
9127 | ; |
9128 | ||
191eb16d AK |
9129 | (define_expand "rotl<mode>3" |
9130 | [(set (match_operand:GPR 0 "register_operand" "") | |
9131 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
e2839e47 | 9132 | (match_operand:QI 2 "shift_count_operand" "")))] |
8cc6307c | 9133 | "" |
191eb16d | 9134 | "") |
9db1d521 | 9135 | |
43a09b63 | 9136 | ; rll, rllg |
e2839e47 | 9137 | (define_insn "*rotl<mode>3" |
191eb16d AK |
9138 | [(set (match_operand:GPR 0 "register_operand" "=d") |
9139 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
e2839e47 | 9140 | (match_operand:QI 2 "shift_count_operand" "jsc")))] |
8cc6307c | 9141 | "" |
e2839e47 | 9142 | "rll<g>\t%0,%1,%Y2" |
4989e88a | 9143 | [(set_attr "op_type" "RSE") |
9381e3f1 | 9144 | (set_attr "atype" "reg") |
191eb16d | 9145 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 9146 | |
9db1d521 HP |
9147 | |
9148 | ;; | |
f337b930 | 9149 | ;;- Shift instructions. |
9db1d521 | 9150 | ;; |
9db1d521 HP |
9151 | |
9152 | ; | |
1b48c8cc | 9153 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 9154 | ; Left shifts and logical right shifts |
9db1d521 | 9155 | |
1b48c8cc AS |
9156 | (define_expand "<shift><mode>3" |
9157 | [(set (match_operand:DSI 0 "register_operand" "") | |
9158 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
e2839e47 | 9159 | (match_operand:QI 2 "shift_count_operand" "")))] |
9db1d521 HP |
9160 | "" |
9161 | "") | |
9162 | ||
adf22b3f | 9163 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 9164 | ; sldl, srdl |
e2839e47 | 9165 | (define_insn "*<shift>di3_31" |
adf22b3f AK |
9166 | [(set (match_operand:DI 0 "register_operand" "=d") |
9167 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
e2839e47 | 9168 | (match_operand:QI 2 "shift_count_operand" "jsc")))] |
9602b6a1 | 9169 | "!TARGET_ZARCH" |
e2839e47 | 9170 | "s<lr>dl\t%0,%Y2" |
077dab3b | 9171 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
9172 | (set_attr "atype" "reg") |
9173 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9174 | |
adf22b3f AK |
9175 | |
9176 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 9177 | ; sll, srl, sllg, srlg, sllk, srlk |
e2839e47 | 9178 | (define_insn "*<shift><mode>3" |
adf22b3f AK |
9179 | [(set (match_operand:GPR 0 "register_operand" "=d, d") |
9180 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
e2839e47 | 9181 | (match_operand:QI 2 "shift_count_operand" "jsc,jsc")))] |
1b48c8cc | 9182 | "" |
65b1d8ea | 9183 | "@ |
e2839e47 RD |
9184 | s<lr>l<g>\t%0,<1>%Y2 |
9185 | s<lr>l<gk>\t%0,%1,%Y2" | |
65b1d8ea AK |
9186 | [(set_attr "op_type" "RS<E>,RSY") |
9187 | (set_attr "atype" "reg,reg") | |
9188 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 9189 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 9190 | |
e2839e47 | 9191 | |
9db1d521 | 9192 | ; |
1b48c8cc | 9193 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 9194 | ; Arithmetic right shifts |
9db1d521 | 9195 | |
1b48c8cc | 9196 | (define_expand "ashr<mode>3" |
9db1d521 | 9197 | [(parallel |
1b48c8cc AS |
9198 | [(set (match_operand:DSI 0 "register_operand" "") |
9199 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
e2839e47 | 9200 | (match_operand:QI 2 "shift_count_operand" ""))) |
ae156f85 | 9201 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
9202 | "" |
9203 | "") | |
9204 | ||
a9fcf821 AK |
9205 | ; FIXME: The number of alternatives is doubled here to match the fix |
9206 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
9207 | ; The right fix should be to support match_scratch in the output | |
9208 | ; pattern of a define_subst. | |
e2839e47 | 9209 | (define_insn "*ashrdi3_31<setcc><cconly>" |
a9fcf821 AK |
9210 | [(set (match_operand:DI 0 "register_operand" "=d, d") |
9211 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
e2839e47 | 9212 | (match_operand:QI 2 "shift_count_operand" "jsc,jsc"))) |
ae156f85 | 9213 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9214 | "!TARGET_ZARCH" |
65b1d8ea | 9215 | "@ |
e2839e47 RD |
9216 | srda\t%0,%Y2 |
9217 | srda\t%0,%Y2" | |
a9fcf821 AK |
9218 | [(set_attr "op_type" "RS") |
9219 | (set_attr "atype" "reg")]) | |
ecbe845e | 9220 | |
ecbe845e | 9221 | |
43a09b63 | 9222 | ; sra, srag |
e2839e47 | 9223 | (define_insn "*ashr<mode>3<setcc><cconly>" |
a9fcf821 AK |
9224 | [(set (match_operand:GPR 0 "register_operand" "=d, d") |
9225 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
e2839e47 | 9226 | (match_operand:QI 2 "shift_count_operand" "jsc,jsc"))) |
ae156f85 | 9227 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 9228 | "" |
65b1d8ea | 9229 | "@ |
e2839e47 RD |
9230 | sra<g>\t%0,<1>%Y2 |
9231 | sra<gk>\t%0,%1,%Y2" | |
65b1d8ea | 9232 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 9233 | (set_attr "atype" "reg") |
01496eca | 9234 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 9235 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 9236 | |
9db1d521 | 9237 | |
9db1d521 HP |
9238 | ;; |
9239 | ;; Branch instruction patterns. | |
9240 | ;; | |
9241 | ||
f90b7a5a | 9242 | (define_expand "cbranch<mode>4" |
fa77b251 | 9243 | [(set (pc) |
f90b7a5a PB |
9244 | (if_then_else (match_operator 0 "comparison_operator" |
9245 | [(match_operand:GPR 1 "register_operand" "") | |
9246 | (match_operand:GPR 2 "general_operand" "")]) | |
9247 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 9248 | (pc)))] |
ba956982 | 9249 | "" |
f90b7a5a PB |
9250 | "s390_emit_jump (operands[3], |
9251 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
9252 | DONE;") | |
9253 | ||
9254 | (define_expand "cbranch<mode>4" | |
9255 | [(set (pc) | |
9256 | (if_then_else (match_operator 0 "comparison_operator" | |
9257 | [(match_operand:FP 1 "register_operand" "") | |
9258 | (match_operand:FP 2 "general_operand" "")]) | |
9259 | (label_ref (match_operand 3 "" "")) | |
9260 | (pc)))] | |
9261 | "TARGET_HARD_FLOAT" | |
9262 | "s390_emit_jump (operands[3], | |
9263 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
9264 | DONE;") | |
9265 | ||
9266 | (define_expand "cbranchcc4" | |
9267 | [(set (pc) | |
de6fba39 | 9268 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 9269 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 9270 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
9271 | (label_ref (match_operand 3 "" "")) |
9272 | (pc)))] | |
de6fba39 UW |
9273 | "" |
9274 | "") | |
ba956982 | 9275 | |
9db1d521 HP |
9276 | |
9277 | ;; | |
9278 | ;;- Conditional jump instructions. | |
9279 | ;; | |
9280 | ||
6590e19a UW |
9281 | (define_insn "*cjump_64" |
9282 | [(set (pc) | |
9283 | (if_then_else | |
5a3fe9b6 AK |
9284 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
9285 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
9286 | (label_ref (match_operand 0 "" "")) |
9287 | (pc)))] | |
8cc6307c | 9288 | "" |
9db1d521 | 9289 | { |
13e58269 | 9290 | if (get_attr_length (insn) == 4) |
d40c829f | 9291 | return "j%C1\t%l0"; |
6590e19a | 9292 | else |
d40c829f | 9293 | return "jg%C1\t%l0"; |
6590e19a UW |
9294 | } |
9295 | [(set_attr "op_type" "RI") | |
9296 | (set_attr "type" "branch") | |
9297 | (set (attr "length") | |
9298 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9299 | (const_int 4) (const_int 6)))]) | |
9300 | ||
f314b9b1 | 9301 | (define_insn "*cjump_long" |
6590e19a UW |
9302 | [(set (pc) |
9303 | (if_then_else | |
ae156f85 | 9304 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 9305 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 9306 | (pc)))] |
84b4c7b5 | 9307 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9308 | { |
9309 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9310 | return "b%C1r\t%0"; |
f314b9b1 | 9311 | else |
d40c829f | 9312 | return "b%C1\t%a0"; |
10bbf137 | 9313 | } |
c7453384 | 9314 | [(set (attr "op_type") |
f314b9b1 UW |
9315 | (if_then_else (match_operand 0 "register_operand" "") |
9316 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9317 | (set (attr "mnemonic") |
9318 | (if_then_else (match_operand 0 "register_operand" "") | |
9319 | (const_string "bcr") (const_string "bc"))) | |
6590e19a | 9320 | (set_attr "type" "branch") |
077dab3b | 9321 | (set_attr "atype" "agen")]) |
9db1d521 | 9322 | |
177bc204 RS |
9323 | ;; A conditional return instruction. |
9324 | (define_insn "*c<code>" | |
9325 | [(set (pc) | |
9326 | (if_then_else | |
9327 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
9328 | (ANY_RETURN) | |
9329 | (pc)))] | |
9330 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
9331 | { |
9332 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
9333 | { | |
9334 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
9335 | INVALID_REGNUM, | |
9336 | operands[0], | |
9337 | s390_indirect_branch_type_return); | |
9338 | return ""; | |
9339 | } | |
9340 | else | |
9341 | return "b%C0r\t%%r14"; | |
9342 | } | |
9343 | [(set (attr "op_type") | |
9344 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9345 | (const_string "RIL") | |
9346 | (const_string "RR"))) | |
9347 | (set (attr "mnemonic") | |
9348 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
9349 | (const_string "brcl") | |
9350 | (const_string "bcr"))) | |
177bc204 RS |
9351 | (set_attr "type" "jsr") |
9352 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
9353 | |
9354 | ;; | |
9355 | ;;- Negated conditional jump instructions. | |
9356 | ;; | |
9357 | ||
6590e19a UW |
9358 | (define_insn "*icjump_64" |
9359 | [(set (pc) | |
9360 | (if_then_else | |
ae156f85 | 9361 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9362 | (pc) |
9363 | (label_ref (match_operand 0 "" ""))))] | |
8cc6307c | 9364 | "" |
c7453384 | 9365 | { |
13e58269 | 9366 | if (get_attr_length (insn) == 4) |
d40c829f | 9367 | return "j%D1\t%l0"; |
6590e19a | 9368 | else |
d40c829f | 9369 | return "jg%D1\t%l0"; |
6590e19a UW |
9370 | } |
9371 | [(set_attr "op_type" "RI") | |
9372 | (set_attr "type" "branch") | |
9373 | (set (attr "length") | |
9374 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9375 | (const_int 4) (const_int 6)))]) | |
9376 | ||
f314b9b1 | 9377 | (define_insn "*icjump_long" |
6590e19a UW |
9378 | [(set (pc) |
9379 | (if_then_else | |
ae156f85 | 9380 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 9381 | (pc) |
4fe6dea8 | 9382 | (match_operand 0 "address_operand" "ZQZR")))] |
84b4c7b5 | 9383 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9384 | { |
9385 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9386 | return "b%D1r\t%0"; |
f314b9b1 | 9387 | else |
d40c829f | 9388 | return "b%D1\t%a0"; |
10bbf137 | 9389 | } |
c7453384 | 9390 | [(set (attr "op_type") |
f314b9b1 UW |
9391 | (if_then_else (match_operand 0 "register_operand" "") |
9392 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9393 | (set (attr "mnemonic") |
9394 | (if_then_else (match_operand 0 "register_operand" "") | |
9395 | (const_string "bcr") (const_string "bc"))) | |
077dab3b HP |
9396 | (set_attr "type" "branch") |
9397 | (set_attr "atype" "agen")]) | |
9db1d521 | 9398 | |
4456530d HP |
9399 | ;; |
9400 | ;;- Trap instructions. | |
9401 | ;; | |
9402 | ||
9403 | (define_insn "trap" | |
9404 | [(trap_if (const_int 1) (const_int 0))] | |
9405 | "" | |
d40c829f | 9406 | "j\t.+2" |
6590e19a | 9407 | [(set_attr "op_type" "RI") |
077dab3b | 9408 | (set_attr "type" "branch")]) |
4456530d | 9409 | |
f90b7a5a PB |
9410 | (define_expand "ctrap<mode>4" |
9411 | [(trap_if (match_operator 0 "comparison_operator" | |
9412 | [(match_operand:GPR 1 "register_operand" "") | |
9413 | (match_operand:GPR 2 "general_operand" "")]) | |
9414 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 9415 | "" |
f90b7a5a PB |
9416 | { |
9417 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9418 | operands[1], operands[2]); | |
9419 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9420 | DONE; | |
9421 | }) | |
9422 | ||
9423 | (define_expand "ctrap<mode>4" | |
9424 | [(trap_if (match_operator 0 "comparison_operator" | |
9425 | [(match_operand:FP 1 "register_operand" "") | |
9426 | (match_operand:FP 2 "general_operand" "")]) | |
9427 | (match_operand 3 "const0_operand" ""))] | |
9428 | "" | |
9429 | { | |
9430 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9431 | operands[1], operands[2]); | |
9432 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9433 | DONE; | |
9434 | }) | |
4456530d | 9435 | |
f90b7a5a PB |
9436 | (define_insn "condtrap" |
9437 | [(trap_if (match_operator 0 "s390_comparison" | |
9438 | [(match_operand 1 "cc_reg_operand" "c") | |
9439 | (const_int 0)]) | |
4456530d HP |
9440 | (const_int 0))] |
9441 | "" | |
d40c829f | 9442 | "j%C0\t.+2"; |
077dab3b HP |
9443 | [(set_attr "op_type" "RI") |
9444 | (set_attr "type" "branch")]) | |
9db1d521 | 9445 | |
963fc8d0 AK |
9446 | ; crt, cgrt, cit, cgit |
9447 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9448 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9449 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9450 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9451 | (const_int 0))] | |
9452 | "TARGET_Z10" | |
9453 | "@ | |
9454 | c<g>rt%C0\t%1,%2 | |
9455 | c<g>it%C0\t%1,%h2" | |
9456 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9457 | (set_attr "type" "branch") |
729e750f | 9458 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9459 | |
22ac2c2f | 9460 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9461 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9462 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9463 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9464 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9465 | (const_int 0))] |
9466 | "TARGET_Z10" | |
9467 | "@ | |
9468 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9469 | cl<gf>it%C0\t%1,%x2 |
9470 | cl<g>t%C0\t%1,%2" | |
9471 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9472 | (set_attr "type" "branch") | |
9473 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9474 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9475 | ||
9476 | ; lat, lgat | |
9477 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9478 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9479 | (const_int 0)) |
9480 | (const_int 0)) | |
9481 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9482 | (match_dup 0))] | |
9483 | "TARGET_ZEC12" | |
9484 | "l<g>at\t%1,%0" | |
9485 | [(set_attr "op_type" "RXY")]) | |
9486 | ||
963fc8d0 | 9487 | |
9db1d521 | 9488 | ;; |
0a3bdf9d | 9489 | ;;- Loop instructions. |
9db1d521 | 9490 | ;; |
0a3bdf9d UW |
9491 | ;; This is all complicated by the fact that since this is a jump insn |
9492 | ;; we must handle our own output reloads. | |
c7453384 | 9493 | |
f1149235 AK |
9494 | ;; branch on index |
9495 | ||
9496 | ; This splitter will be matched by combine and has to add the 2 moves | |
9497 | ; necessary to load the compare and the increment values into a | |
9498 | ; register pair as needed by brxle. | |
9499 | ||
9500 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9501 | [(set (pc) | |
9502 | (if_then_else | |
9503 | (match_operator 6 "s390_brx_operator" | |
9504 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9505 | (match_operand:GPR 2 "general_operand" "")) | |
9506 | (match_operand:GPR 3 "register_operand" "")]) | |
9507 | (label_ref (match_operand 0 "" "")) | |
9508 | (pc))) | |
9509 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9510 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9511 | (clobber (match_scratch:GPR 5 ""))] | |
8cc6307c | 9512 | "" |
f1149235 AK |
9513 | "#" |
9514 | "!reload_completed && !reload_in_progress" | |
9515 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9516 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9517 | (parallel [(set (pc) | |
9518 | (if_then_else | |
9519 | (match_op_dup 6 | |
9520 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9521 | (match_dup 8)]) | |
9522 | (label_ref (match_dup 0)) | |
9523 | (pc))) | |
9524 | (set (match_dup 4) | |
9525 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9526 | (clobber (match_dup 5)) | |
9527 | (clobber (reg:CC CC_REGNUM))])] | |
9528 | { | |
9529 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9530 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9531 | gen_highpart (word_mode, dreg)); | |
9532 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9533 | gen_lowpart (word_mode, dreg)); | |
9534 | }) | |
9535 | ||
9536 | ; brxlg, brxhg | |
9537 | ||
9538 | (define_insn_and_split "*brxg_64bit" | |
9539 | [(set (pc) | |
9540 | (if_then_else | |
9541 | (match_operator 5 "s390_brx_operator" | |
9542 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9543 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9544 | (subreg:DI (match_dup 2) 8)]) | |
9545 | (label_ref (match_operand 0 "" "")) | |
9546 | (pc))) | |
9547 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9548 | (plus:DI (match_dup 1) | |
9549 | (subreg:DI (match_dup 2) 0))) | |
9550 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9551 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9552 | "TARGET_ZARCH" |
f1149235 AK |
9553 | { |
9554 | if (which_alternative != 0) | |
9555 | return "#"; | |
9556 | else if (get_attr_length (insn) == 6) | |
9557 | return "brx%E5g\t%1,%2,%l0"; | |
9558 | else | |
9559 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9560 | } | |
9561 | "&& reload_completed | |
9562 | && (!REG_P (operands[3]) | |
9563 | || !rtx_equal_p (operands[1], operands[3]))" | |
9564 | [(set (match_dup 4) (match_dup 1)) | |
9565 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9566 | (clobber (reg:CC CC_REGNUM))]) | |
9567 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9568 | (set (match_dup 3) (match_dup 4)) | |
9569 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9570 | (label_ref (match_dup 0)) | |
9571 | (pc)))] | |
9572 | "" | |
9573 | [(set_attr "op_type" "RIE") | |
9574 | (set_attr "type" "branch") | |
9575 | (set (attr "length") | |
9576 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9577 | (const_int 6) (const_int 16)))]) | |
9578 | ||
9579 | ; brxle, brxh | |
9580 | ||
9581 | (define_insn_and_split "*brx_64bit" | |
9582 | [(set (pc) | |
9583 | (if_then_else | |
9584 | (match_operator 5 "s390_brx_operator" | |
9585 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9586 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9587 | (subreg:SI (match_dup 2) 12)]) | |
9588 | (label_ref (match_operand 0 "" "")) | |
9589 | (pc))) | |
9590 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9591 | (plus:SI (match_dup 1) | |
9592 | (subreg:SI (match_dup 2) 4))) | |
9593 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9594 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9595 | "TARGET_ZARCH" |
f1149235 AK |
9596 | { |
9597 | if (which_alternative != 0) | |
9598 | return "#"; | |
9599 | else if (get_attr_length (insn) == 6) | |
9600 | return "brx%C5\t%1,%2,%l0"; | |
9601 | else | |
9602 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9603 | } | |
9604 | "&& reload_completed | |
9605 | && (!REG_P (operands[3]) | |
9606 | || !rtx_equal_p (operands[1], operands[3]))" | |
9607 | [(set (match_dup 4) (match_dup 1)) | |
9608 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9609 | (clobber (reg:CC CC_REGNUM))]) | |
9610 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9611 | (set (match_dup 3) (match_dup 4)) | |
9612 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9613 | (label_ref (match_dup 0)) | |
9614 | (pc)))] | |
9615 | "" | |
9616 | [(set_attr "op_type" "RSI") | |
9617 | (set_attr "type" "branch") | |
9618 | (set (attr "length") | |
9619 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9620 | (const_int 6) (const_int 14)))]) | |
9621 | ||
9622 | ; brxle, brxh | |
9623 | ||
9624 | (define_insn_and_split "*brx_31bit" | |
9625 | [(set (pc) | |
9626 | (if_then_else | |
9627 | (match_operator 5 "s390_brx_operator" | |
9628 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9629 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9630 | (subreg:SI (match_dup 2) 4)]) | |
9631 | (label_ref (match_operand 0 "" "")) | |
9632 | (pc))) | |
9633 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9634 | (plus:SI (match_dup 1) | |
9635 | (subreg:SI (match_dup 2) 0))) | |
9636 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9637 | (clobber (reg:CC CC_REGNUM))] | |
8cc6307c | 9638 | "!TARGET_ZARCH" |
f1149235 AK |
9639 | { |
9640 | if (which_alternative != 0) | |
9641 | return "#"; | |
9642 | else if (get_attr_length (insn) == 6) | |
9643 | return "brx%C5\t%1,%2,%l0"; | |
9644 | else | |
9645 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9646 | } | |
9647 | "&& reload_completed | |
9648 | && (!REG_P (operands[3]) | |
9649 | || !rtx_equal_p (operands[1], operands[3]))" | |
9650 | [(set (match_dup 4) (match_dup 1)) | |
9651 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9652 | (clobber (reg:CC CC_REGNUM))]) | |
9653 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9654 | (set (match_dup 3) (match_dup 4)) | |
9655 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9656 | (label_ref (match_dup 0)) | |
9657 | (pc)))] | |
9658 | "" | |
9659 | [(set_attr "op_type" "RSI") | |
9660 | (set_attr "type" "branch") | |
9661 | (set (attr "length") | |
9662 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9663 | (const_int 6) (const_int 14)))]) | |
9664 | ||
9665 | ||
9666 | ;; branch on count | |
9667 | ||
0a3bdf9d UW |
9668 | (define_expand "doloop_end" |
9669 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9670 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9671 | "" |
0a3bdf9d | 9672 | { |
8cc6307c | 9673 | if (GET_MODE (operands[0]) == SImode) |
1d0216c8 | 9674 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9675 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9676 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9677 | else |
9678 | FAIL; | |
9679 | ||
9680 | DONE; | |
10bbf137 | 9681 | }) |
0a3bdf9d | 9682 | |
6590e19a | 9683 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9684 | [(set (pc) |
9685 | (if_then_else | |
7e665d18 | 9686 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9687 | (const_int 1)) |
9688 | (label_ref (match_operand 0 "" "")) | |
9689 | (pc))) | |
7e665d18 | 9690 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9691 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9692 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9693 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 9694 | "" |
0a3bdf9d UW |
9695 | { |
9696 | if (which_alternative != 0) | |
10bbf137 | 9697 | return "#"; |
0a3bdf9d | 9698 | else if (get_attr_length (insn) == 4) |
d40c829f | 9699 | return "brct\t%1,%l0"; |
6590e19a | 9700 | else |
545d16ff | 9701 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9702 | } |
9703 | "&& reload_completed | |
9704 | && (! REG_P (operands[2]) | |
9705 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9706 | [(set (match_dup 3) (match_dup 1)) |
9707 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9708 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9709 | (const_int 0))) | |
9710 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9711 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9712 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9713 | (label_ref (match_dup 0)) |
9714 | (pc)))] | |
9715 | "" | |
9716 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9717 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9718 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9719 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9720 | (set_attr "type" "branch") |
9721 | (set (attr "length") | |
9722 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9723 | (const_int 4) (const_int 10)))]) | |
9724 | ||
6590e19a | 9725 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9726 | [(set (pc) |
9727 | (if_then_else | |
7e665d18 | 9728 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9729 | (const_int 1)) |
9730 | (label_ref (match_operand 0 "" "")) | |
9731 | (pc))) | |
7e665d18 | 9732 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9733 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9734 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9735 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9736 | "TARGET_ZARCH" |
0a3bdf9d UW |
9737 | { |
9738 | if (which_alternative != 0) | |
10bbf137 | 9739 | return "#"; |
0a3bdf9d | 9740 | else if (get_attr_length (insn) == 4) |
d40c829f | 9741 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9742 | else |
545d16ff | 9743 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9744 | } |
6590e19a | 9745 | "&& reload_completed |
0a3bdf9d UW |
9746 | && (! REG_P (operands[2]) |
9747 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9748 | [(set (match_dup 3) (match_dup 1)) |
9749 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9750 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9751 | (const_int 0))) | |
9752 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9753 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9754 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9755 | (label_ref (match_dup 0)) |
0a3bdf9d | 9756 | (pc)))] |
6590e19a UW |
9757 | "" |
9758 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9759 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9760 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9761 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9762 | (set_attr "type" "branch") |
9763 | (set (attr "length") | |
9764 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9765 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9766 | |
9767 | ;; | |
9768 | ;;- Unconditional jump instructions. | |
9769 | ;; | |
9770 | ||
9771 | ; | |
9772 | ; jump instruction pattern(s). | |
9773 | ; | |
9774 | ||
6590e19a UW |
9775 | (define_expand "jump" |
9776 | [(match_operand 0 "" "")] | |
9db1d521 | 9777 | "" |
6590e19a UW |
9778 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9779 | ||
9780 | (define_insn "*jump64" | |
9781 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8cc6307c | 9782 | "" |
9db1d521 | 9783 | { |
13e58269 | 9784 | if (get_attr_length (insn) == 4) |
d40c829f | 9785 | return "j\t%l0"; |
6590e19a | 9786 | else |
d40c829f | 9787 | return "jg\t%l0"; |
6590e19a UW |
9788 | } |
9789 | [(set_attr "op_type" "RI") | |
9790 | (set_attr "type" "branch") | |
9791 | (set (attr "length") | |
9792 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9793 | (const_int 4) (const_int 6)))]) | |
9794 | ||
9db1d521 HP |
9795 | ; |
9796 | ; indirect-jump instruction pattern(s). | |
9797 | ; | |
9798 | ||
2841f550 AK |
9799 | (define_expand "indirect_jump" |
9800 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9801 | "" |
f314b9b1 | 9802 | { |
2841f550 AK |
9803 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9804 | ; | |
e9e8efc9 | 9805 | else if (TARGET_Z14 |
2841f550 AK |
9806 | && GET_MODE (operands[0]) == Pmode |
9807 | && memory_operand (operands[0], Pmode)) | |
9808 | ; | |
f314b9b1 | 9809 | else |
2841f550 | 9810 | operands[0] = force_reg (Pmode, operands[0]); |
84b4c7b5 AK |
9811 | |
9812 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9813 | { | |
9814 | operands[0] = force_reg (Pmode, operands[0]); | |
9815 | if (TARGET_CPU_Z10) | |
9816 | { | |
9817 | if (TARGET_64BIT) | |
9818 | emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); | |
9819 | else | |
9820 | emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); | |
9821 | } | |
9822 | else | |
9823 | { | |
9824 | if (TARGET_64BIT) | |
9825 | emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); | |
9826 | else | |
9827 | emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); | |
9828 | } | |
9829 | DONE; | |
9830 | } | |
9831 | ||
9832 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9833 | { | |
9834 | operands[0] = force_reg (Pmode, operands[0]); | |
9835 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9836 | if (TARGET_CPU_Z10) | |
9837 | { | |
9838 | if (TARGET_64BIT) | |
9839 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], | |
9840 | label_ref)); | |
9841 | else | |
9842 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], | |
9843 | label_ref)); | |
9844 | } | |
9845 | else | |
9846 | { | |
9847 | if (TARGET_64BIT) | |
9848 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], | |
9849 | label_ref, | |
9850 | force_reg (Pmode, label_ref))); | |
9851 | else | |
9852 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], | |
9853 | label_ref, | |
9854 | force_reg (Pmode, label_ref))); | |
9855 | } | |
9856 | DONE; | |
9857 | } | |
2841f550 AK |
9858 | }) |
9859 | ||
9860 | (define_insn "*indirect_jump" | |
9861 | [(set (pc) | |
84b4c7b5 AK |
9862 | (match_operand 0 "address_operand" "ZR"))] |
9863 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9864 | { | |
9865 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9866 | return "br\t%0"; | |
9867 | else | |
9868 | return "b\t%a0"; | |
9869 | } | |
9870 | [(set (attr "op_type") | |
9871 | (if_then_else (match_operand 0 "register_operand" "") | |
9872 | (const_string "RR") (const_string "RX"))) | |
9873 | (set (attr "mnemonic") | |
9874 | (if_then_else (match_operand 0 "register_operand" "") | |
9875 | (const_string "br") (const_string "b"))) | |
2841f550 | 9876 | (set_attr "type" "branch") |
84b4c7b5 AK |
9877 | (set_attr "atype" "agen")]) |
9878 | ||
9879 | (define_insn "indirect_jump_via_thunk<mode>_z10" | |
9880 | [(set (pc) | |
9881 | (match_operand:P 0 "register_operand" "a"))] | |
9882 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9883 | && TARGET_CPU_Z10" | |
9884 | { | |
9885 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9886 | INVALID_REGNUM, | |
9887 | NULL_RTX, | |
9888 | s390_indirect_branch_type_jump); | |
9889 | return ""; | |
9890 | } | |
9891 | [(set_attr "op_type" "RIL") | |
9892 | (set_attr "mnemonic" "jg") | |
9893 | (set_attr "type" "branch") | |
9894 | (set_attr "atype" "agen")]) | |
9895 | ||
9896 | (define_insn "indirect_jump_via_thunk<mode>" | |
9897 | [(set (pc) | |
9898 | (match_operand:P 0 "register_operand" " a")) | |
9899 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9900 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9901 | && !TARGET_CPU_Z10" | |
9902 | { | |
9903 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9904 | INVALID_REGNUM, | |
9905 | NULL_RTX, | |
9906 | s390_indirect_branch_type_jump); | |
9907 | return ""; | |
9908 | } | |
9909 | [(set_attr "op_type" "RIL") | |
9910 | (set_attr "mnemonic" "jg") | |
9911 | (set_attr "type" "branch") | |
9912 | (set_attr "atype" "agen")]) | |
9913 | ||
9914 | ||
9915 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9916 | ; from mark_jump_label. Without this the label_ref would become the | |
9917 | ; ONLY jump target of that jump breaking the control flow graph. | |
9918 | (define_insn "indirect_jump_via_inlinethunk<mode>_z10" | |
9919 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9920 | (const_int 0) | |
9921 | (const_int 0)) | |
9922 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9923 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9924 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9925 | && TARGET_CPU_Z10" | |
9926 | { | |
9927 | s390_indirect_branch_via_inline_thunk (operands[1]); | |
9928 | return ""; | |
9929 | } | |
9930 | [(set_attr "op_type" "RIL") | |
9931 | (set_attr "type" "branch") | |
9932 | (set_attr "length" "10")]) | |
9933 | ||
9934 | (define_insn "indirect_jump_via_inlinethunk<mode>" | |
9935 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9936 | (const_int 0) | |
9937 | (const_int 0)) | |
9938 | (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9939 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9940 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9941 | && !TARGET_CPU_Z10" | |
9942 | { | |
9943 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9944 | return ""; | |
9945 | } | |
9946 | [(set_attr "op_type" "RX") | |
9947 | (set_attr "type" "branch") | |
9948 | (set_attr "length" "8")]) | |
2841f550 AK |
9949 | |
9950 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9951 | ; checked against address constraints like ZR above. So make this a | |
9952 | ; separate pattern for now. | |
9953 | (define_insn "*indirect2_jump" | |
9954 | [(set (pc) | |
9955 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
84b4c7b5 | 9956 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
2841f550 AK |
9957 | "@ |
9958 | br\t%0 | |
9959 | bi\t%0" | |
9960 | [(set_attr "op_type" "RR,RXY") | |
9961 | (set_attr "type" "branch") | |
9962 | (set_attr "atype" "agen") | |
e9e8efc9 | 9963 | (set_attr "cpu_facility" "*,z14")]) |
9db1d521 HP |
9964 | |
9965 | ; | |
f314b9b1 | 9966 | ; casesi instruction pattern(s). |
9db1d521 HP |
9967 | ; |
9968 | ||
84b4c7b5 AK |
9969 | (define_expand "casesi_jump" |
9970 | [(parallel | |
9971 | [(set (pc) (match_operand 0 "address_operand")) | |
9972 | (use (label_ref (match_operand 1 "")))])] | |
9db1d521 | 9973 | "" |
84b4c7b5 AK |
9974 | { |
9975 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9976 | { | |
9977 | operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); | |
9978 | ||
9979 | if (TARGET_CPU_Z10) | |
9980 | { | |
9981 | if (TARGET_64BIT) | |
9982 | emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], | |
9983 | operands[1])); | |
9984 | else | |
9985 | emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], | |
9986 | operands[1])); | |
9987 | } | |
9988 | else | |
9989 | { | |
9990 | if (TARGET_64BIT) | |
9991 | emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], | |
9992 | operands[1])); | |
9993 | else | |
9994 | emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], | |
9995 | operands[1])); | |
9996 | } | |
9997 | DONE; | |
9998 | } | |
9999 | ||
10000 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
10001 | { | |
10002 | operands[0] = force_reg (Pmode, operands[0]); | |
10003 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
10004 | if (TARGET_CPU_Z10) | |
10005 | { | |
10006 | if (TARGET_64BIT) | |
10007 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], | |
10008 | operands[1], | |
10009 | label_ref)); | |
10010 | else | |
10011 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], | |
10012 | operands[1], | |
10013 | label_ref)); | |
10014 | } | |
10015 | else | |
10016 | { | |
10017 | if (TARGET_64BIT) | |
10018 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], | |
10019 | operands[1], | |
10020 | label_ref, | |
10021 | force_reg (Pmode, label_ref))); | |
10022 | else | |
10023 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], | |
10024 | operands[1], | |
10025 | label_ref, | |
10026 | force_reg (Pmode, label_ref))); | |
10027 | } | |
10028 | DONE; | |
10029 | } | |
10030 | }) | |
10031 | ||
10032 | (define_insn "*casesi_jump" | |
10033 | [(set (pc) (match_operand 0 "address_operand" "ZR")) | |
10034 | (use (label_ref (match_operand 1 "" "")))] | |
10035 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9db1d521 | 10036 | { |
f314b9b1 | 10037 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 10038 | return "br\t%0"; |
f314b9b1 | 10039 | else |
d40c829f | 10040 | return "b\t%a0"; |
10bbf137 | 10041 | } |
c7453384 | 10042 | [(set (attr "op_type") |
f314b9b1 UW |
10043 | (if_then_else (match_operand 0 "register_operand" "") |
10044 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10045 | (set (attr "mnemonic") |
10046 | (if_then_else (match_operand 0 "register_operand" "") | |
10047 | (const_string "br") (const_string "b"))) | |
10048 | (set_attr "type" "branch") | |
10049 | (set_attr "atype" "agen")]) | |
10050 | ||
10051 | (define_insn "casesi_jump_via_thunk<mode>_z10" | |
10052 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
10053 | (use (label_ref (match_operand 1 "" "")))] | |
10054 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
10055 | && TARGET_CPU_Z10" | |
10056 | { | |
10057 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10058 | INVALID_REGNUM, | |
10059 | NULL_RTX, | |
10060 | s390_indirect_branch_type_jump); | |
10061 | return ""; | |
10062 | } | |
10063 | [(set_attr "op_type" "RIL") | |
10064 | (set_attr "mnemonic" "jg") | |
10065 | (set_attr "type" "branch") | |
10066 | (set_attr "atype" "agen")]) | |
10067 | ||
10068 | (define_insn "casesi_jump_via_thunk<mode>" | |
10069 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
10070 | (use (label_ref (match_operand 1 "" ""))) | |
10071 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10072 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
10073 | && !TARGET_CPU_Z10" | |
10074 | { | |
10075 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10076 | INVALID_REGNUM, | |
10077 | NULL_RTX, | |
10078 | s390_indirect_branch_type_jump); | |
10079 | return ""; | |
10080 | } | |
10081 | [(set_attr "op_type" "RIL") | |
10082 | (set_attr "mnemonic" "jg") | |
077dab3b HP |
10083 | (set_attr "type" "branch") |
10084 | (set_attr "atype" "agen")]) | |
9db1d521 | 10085 | |
84b4c7b5 AK |
10086 | |
10087 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
10088 | ; from mark_jump_label. Without this the label_ref would become the | |
10089 | ; ONLY jump target of that jump breaking the control flow graph. | |
10090 | (define_insn "casesi_jump_via_inlinethunk<mode>_z10" | |
10091 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
10092 | (const_int 0) | |
10093 | (const_int 0)) | |
10094 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
10095 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
10096 | (use (label_ref (match_operand 1 "" "")))] | |
10097 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
10098 | && TARGET_CPU_Z10" | |
10099 | { | |
10100 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
10101 | return ""; | |
10102 | } | |
10103 | [(set_attr "op_type" "RIL") | |
10104 | (set_attr "type" "cs") | |
10105 | (set_attr "length" "10")]) | |
10106 | ||
10107 | (define_insn "casesi_jump_via_inlinethunk<mode>" | |
10108 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
10109 | (const_int 0) | |
10110 | (const_int 0)) | |
10111 | (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
10112 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
10113 | (use (label_ref (match_operand 1 "" "")))] | |
10114 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
10115 | && !TARGET_CPU_Z10" | |
10116 | { | |
10117 | s390_indirect_branch_via_inline_thunk (operands[3]); | |
10118 | return ""; | |
10119 | } | |
10120 | [(set_attr "op_type" "RX") | |
10121 | (set_attr "type" "cs") | |
10122 | (set_attr "length" "8")]) | |
10123 | ||
f314b9b1 UW |
10124 | (define_expand "casesi" |
10125 | [(match_operand:SI 0 "general_operand" "") | |
10126 | (match_operand:SI 1 "general_operand" "") | |
10127 | (match_operand:SI 2 "general_operand" "") | |
10128 | (label_ref (match_operand 3 "" "")) | |
10129 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 10130 | "" |
f314b9b1 UW |
10131 | { |
10132 | rtx index = gen_reg_rtx (SImode); | |
10133 | rtx base = gen_reg_rtx (Pmode); | |
10134 | rtx target = gen_reg_rtx (Pmode); | |
10135 | ||
10136 | emit_move_insn (index, operands[0]); | |
10137 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
10138 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 10139 | operands[4]); |
f314b9b1 UW |
10140 | |
10141 | if (Pmode != SImode) | |
10142 | index = convert_to_mode (Pmode, index, 1); | |
10143 | if (GET_CODE (index) != REG) | |
10144 | index = copy_to_mode_reg (Pmode, index); | |
10145 | ||
10146 | if (TARGET_64BIT) | |
10147 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
10148 | else | |
a556fd39 | 10149 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 10150 | |
f314b9b1 UW |
10151 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
10152 | ||
542a8afa | 10153 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
10154 | emit_move_insn (target, index); |
10155 | ||
10156 | if (flag_pic) | |
10157 | target = gen_rtx_PLUS (Pmode, base, target); | |
10158 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
10159 | ||
10160 | DONE; | |
10bbf137 | 10161 | }) |
9db1d521 HP |
10162 | |
10163 | ||
10164 | ;; | |
10165 | ;;- Jump to subroutine. | |
10166 | ;; | |
10167 | ;; | |
10168 | ||
10169 | ; | |
10170 | ; untyped call instruction pattern(s). | |
10171 | ; | |
10172 | ||
10173 | ;; Call subroutine returning any type. | |
10174 | (define_expand "untyped_call" | |
10175 | [(parallel [(call (match_operand 0 "" "") | |
10176 | (const_int 0)) | |
10177 | (match_operand 1 "" "") | |
10178 | (match_operand 2 "" "")])] | |
10179 | "" | |
9db1d521 HP |
10180 | { |
10181 | int i; | |
10182 | ||
10183 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
10184 | ||
10185 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10186 | { | |
10187 | rtx set = XVECEXP (operands[2], 0, i); | |
10188 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10189 | } | |
10190 | ||
10191 | /* The optimizer does not know that the call sets the function value | |
10192 | registers we stored in the result block. We avoid problems by | |
10193 | claiming that all hard registers are used and clobbered at this | |
10194 | point. */ | |
10195 | emit_insn (gen_blockage ()); | |
10196 | ||
10197 | DONE; | |
10bbf137 | 10198 | }) |
9db1d521 HP |
10199 | |
10200 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
10201 | ;; all of memory. This blocks insns from being moved across this point. | |
10202 | ||
10203 | (define_insn "blockage" | |
10bbf137 | 10204 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 10205 | "" |
4023fb28 | 10206 | "" |
d5869ca0 UW |
10207 | [(set_attr "type" "none") |
10208 | (set_attr "length" "0")]) | |
4023fb28 | 10209 | |
9db1d521 | 10210 | ; |
ed9676cf | 10211 | ; sibcall patterns |
9db1d521 HP |
10212 | ; |
10213 | ||
ed9676cf | 10214 | (define_expand "sibcall" |
44b8152b | 10215 | [(call (match_operand 0 "" "") |
ed9676cf | 10216 | (match_operand 1 "" ""))] |
9db1d521 | 10217 | "" |
9db1d521 | 10218 | { |
ed9676cf AK |
10219 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
10220 | DONE; | |
10221 | }) | |
9db1d521 | 10222 | |
ed9676cf | 10223 | (define_insn "*sibcall_br" |
ae156f85 | 10224 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 10225 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 10226 | "SIBLING_CALL_P (insn) |
ed9676cf | 10227 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
84b4c7b5 AK |
10228 | { |
10229 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
10230 | { | |
10231 | gcc_assert (TARGET_CPU_Z10); | |
10232 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
10233 | INVALID_REGNUM, | |
10234 | NULL_RTX, | |
10235 | s390_indirect_branch_type_call); | |
10236 | return ""; | |
10237 | } | |
10238 | else | |
10239 | return "br\t%%r1"; | |
10240 | } | |
10241 | [(set (attr "op_type") | |
10242 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10243 | (const_string "RIL") | |
10244 | (const_string "RR"))) | |
10245 | (set (attr "mnemonic") | |
10246 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10247 | (const_string "jg") | |
10248 | (const_string "br"))) | |
ed9676cf AK |
10249 | (set_attr "type" "branch") |
10250 | (set_attr "atype" "agen")]) | |
9db1d521 | 10251 | |
ed9676cf AK |
10252 | (define_insn "*sibcall_brc" |
10253 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10254 | (match_operand 1 "const_int_operand" "n"))] | |
10255 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
10256 | "j\t%0" | |
10257 | [(set_attr "op_type" "RI") | |
10258 | (set_attr "type" "branch")]) | |
9db1d521 | 10259 | |
ed9676cf AK |
10260 | (define_insn "*sibcall_brcl" |
10261 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10262 | (match_operand 1 "const_int_operand" "n"))] | |
8cc6307c | 10263 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
10264 | "jg\t%0" |
10265 | [(set_attr "op_type" "RIL") | |
10266 | (set_attr "type" "branch")]) | |
44b8152b | 10267 | |
ed9676cf AK |
10268 | ; |
10269 | ; sibcall_value patterns | |
10270 | ; | |
9e8327e3 | 10271 | |
ed9676cf AK |
10272 | (define_expand "sibcall_value" |
10273 | [(set (match_operand 0 "" "") | |
10274 | (call (match_operand 1 "" "") | |
10275 | (match_operand 2 "" "")))] | |
10276 | "" | |
10277 | { | |
10278 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 10279 | DONE; |
10bbf137 | 10280 | }) |
9db1d521 | 10281 | |
ed9676cf AK |
10282 | (define_insn "*sibcall_value_br" |
10283 | [(set (match_operand 0 "" "") | |
ae156f85 | 10284 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 10285 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 10286 | "SIBLING_CALL_P (insn) |
ed9676cf | 10287 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
84b4c7b5 AK |
10288 | { |
10289 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
10290 | { | |
10291 | gcc_assert (TARGET_CPU_Z10); | |
10292 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
10293 | INVALID_REGNUM, | |
10294 | NULL_RTX, | |
10295 | s390_indirect_branch_type_call); | |
10296 | return ""; | |
10297 | } | |
10298 | else | |
10299 | return "br\t%%r1"; | |
10300 | } | |
10301 | [(set (attr "op_type") | |
10302 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10303 | (const_string "RIL") | |
10304 | (const_string "RR"))) | |
10305 | (set (attr "mnemonic") | |
10306 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
10307 | (const_string "jg") | |
10308 | (const_string "br"))) | |
ed9676cf AK |
10309 | (set_attr "type" "branch") |
10310 | (set_attr "atype" "agen")]) | |
10311 | ||
10312 | (define_insn "*sibcall_value_brc" | |
10313 | [(set (match_operand 0 "" "") | |
10314 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
10315 | (match_operand 2 "const_int_operand" "n")))] | |
10316 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
10317 | "j\t%1" | |
10318 | [(set_attr "op_type" "RI") | |
10319 | (set_attr "type" "branch")]) | |
10320 | ||
10321 | (define_insn "*sibcall_value_brcl" | |
10322 | [(set (match_operand 0 "" "") | |
10323 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
10324 | (match_operand 2 "const_int_operand" "n")))] | |
8cc6307c | 10325 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
10326 | "jg\t%1" |
10327 | [(set_attr "op_type" "RIL") | |
10328 | (set_attr "type" "branch")]) | |
10329 | ||
10330 | ||
10331 | ; | |
10332 | ; call instruction pattern(s). | |
10333 | ; | |
10334 | ||
10335 | (define_expand "call" | |
10336 | [(call (match_operand 0 "" "") | |
10337 | (match_operand 1 "" "")) | |
10338 | (use (match_operand 2 "" ""))] | |
44b8152b | 10339 | "" |
ed9676cf | 10340 | { |
2f7e5a0d | 10341 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
10342 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
10343 | DONE; | |
10344 | }) | |
44b8152b | 10345 | |
9e8327e3 UW |
10346 | (define_insn "*bras" |
10347 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10348 | (match_operand 1 "const_int_operand" "n")) | |
10349 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
10350 | "!SIBLING_CALL_P (insn) |
10351 | && TARGET_SMALL_EXEC | |
ed9676cf | 10352 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 10353 | "bras\t%2,%0" |
9db1d521 | 10354 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10355 | (set_attr "type" "jsr") |
10356 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10357 | |
9e8327e3 UW |
10358 | (define_insn "*brasl" |
10359 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10360 | (match_operand 1 "const_int_operand" "n")) | |
10361 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d | 10362 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10363 | |
ed9676cf | 10364 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
10365 | "brasl\t%2,%0" |
10366 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10367 | (set_attr "type" "jsr") |
14cfceb7 IL |
10368 | (set_attr "z196prop" "z196_cracked") |
10369 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10370 | |
9e8327e3 | 10371 | (define_insn "*basr" |
3e4be43f | 10372 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
10373 | (match_operand 1 "const_int_operand" "n")) |
10374 | (clobber (match_operand 2 "register_operand" "=r"))] | |
84b4c7b5 AK |
10375 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10376 | && !SIBLING_CALL_P (insn) | |
10377 | && GET_MODE (operands[2]) == Pmode" | |
9e8327e3 UW |
10378 | { |
10379 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10380 | return "basr\t%2,%0"; | |
10381 | else | |
10382 | return "bas\t%2,%a0"; | |
10383 | } | |
10384 | [(set (attr "op_type") | |
10385 | (if_then_else (match_operand 0 "register_operand" "") | |
10386 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10387 | (set (attr "mnemonic") |
10388 | (if_then_else (match_operand 0 "register_operand" "") | |
10389 | (const_string "basr") (const_string "bas"))) | |
10390 | (set_attr "type" "jsr") | |
10391 | (set_attr "atype" "agen") | |
10392 | (set_attr "z196prop" "z196_cracked")]) | |
10393 | ||
10394 | (define_insn "*basr_via_thunk<mode>_z10" | |
10395 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10396 | (match_operand 1 "const_int_operand" "n")) | |
10397 | (clobber (match_operand:P 2 "register_operand" "=&r"))] | |
10398 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10399 | && TARGET_CPU_Z10 | |
10400 | && !SIBLING_CALL_P (insn)" | |
10401 | { | |
10402 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10403 | REGNO (operands[2]), | |
10404 | NULL_RTX, | |
10405 | s390_indirect_branch_type_call); | |
10406 | return ""; | |
10407 | } | |
10408 | [(set_attr "op_type" "RIL") | |
10409 | (set_attr "mnemonic" "brasl") | |
10410 | (set_attr "type" "jsr") | |
10411 | (set_attr "atype" "agen") | |
10412 | (set_attr "z196prop" "z196_cracked")]) | |
10413 | ||
10414 | (define_insn "*basr_via_thunk<mode>" | |
10415 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10416 | (match_operand 1 "const_int_operand" "n")) | |
10417 | (clobber (match_operand:P 2 "register_operand" "=&r")) | |
10418 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10419 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10420 | && !TARGET_CPU_Z10 | |
10421 | && !SIBLING_CALL_P (insn)" | |
10422 | { | |
10423 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10424 | REGNO (operands[2]), | |
10425 | NULL_RTX, | |
10426 | s390_indirect_branch_type_call); | |
10427 | return ""; | |
10428 | } | |
10429 | [(set_attr "op_type" "RIL") | |
10430 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10431 | (set_attr "type" "jsr") |
65b1d8ea AK |
10432 | (set_attr "atype" "agen") |
10433 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
10434 | |
10435 | ; | |
10436 | ; call_value instruction pattern(s). | |
10437 | ; | |
10438 | ||
10439 | (define_expand "call_value" | |
44b8152b UW |
10440 | [(set (match_operand 0 "" "") |
10441 | (call (match_operand 1 "" "") | |
10442 | (match_operand 2 "" ""))) | |
10443 | (use (match_operand 3 "" ""))] | |
9db1d521 | 10444 | "" |
9db1d521 | 10445 | { |
2f7e5a0d | 10446 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 10447 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 10448 | DONE; |
10bbf137 | 10449 | }) |
9db1d521 | 10450 | |
9e8327e3 | 10451 | (define_insn "*bras_r" |
c19ec8f9 | 10452 | [(set (match_operand 0 "" "") |
9e8327e3 | 10453 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 10454 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 10455 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
10456 | "!SIBLING_CALL_P (insn) |
10457 | && TARGET_SMALL_EXEC | |
ed9676cf | 10458 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10459 | "bras\t%3,%1" |
9db1d521 | 10460 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10461 | (set_attr "type" "jsr") |
10462 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10463 | |
9e8327e3 | 10464 | (define_insn "*brasl_r" |
c19ec8f9 | 10465 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10466 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10467 | (match_operand 2 "const_int_operand" "n"))) | |
10468 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d | 10469 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10470 | |
ed9676cf | 10471 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10472 | "brasl\t%3,%1" |
10473 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10474 | (set_attr "type" "jsr") |
14cfceb7 IL |
10475 | (set_attr "z196prop" "z196_cracked") |
10476 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10477 | |
9e8327e3 | 10478 | (define_insn "*basr_r" |
c19ec8f9 | 10479 | [(set (match_operand 0 "" "") |
3e4be43f | 10480 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10481 | (match_operand 2 "const_int_operand" "n"))) |
10482 | (clobber (match_operand 3 "register_operand" "=r"))] | |
84b4c7b5 AK |
10483 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10484 | && !SIBLING_CALL_P (insn) | |
10485 | && GET_MODE (operands[3]) == Pmode" | |
9e8327e3 UW |
10486 | { |
10487 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10488 | return "basr\t%3,%1"; | |
10489 | else | |
10490 | return "bas\t%3,%a1"; | |
10491 | } | |
10492 | [(set (attr "op_type") | |
10493 | (if_then_else (match_operand 1 "register_operand" "") | |
10494 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10495 | (set (attr "mnemonic") |
10496 | (if_then_else (match_operand 1 "register_operand" "") | |
10497 | (const_string "basr") (const_string "bas"))) | |
10498 | (set_attr "type" "jsr") | |
10499 | (set_attr "atype" "agen") | |
10500 | (set_attr "z196prop" "z196_cracked")]) | |
10501 | ||
10502 | (define_insn "*basr_r_via_thunk_z10" | |
10503 | [(set (match_operand 0 "" "") | |
10504 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10505 | (match_operand 2 "const_int_operand" "n"))) | |
10506 | (clobber (match_operand 3 "register_operand" "=&r"))] | |
10507 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10508 | && TARGET_CPU_Z10 | |
10509 | && !SIBLING_CALL_P (insn) | |
10510 | && GET_MODE (operands[3]) == Pmode" | |
10511 | { | |
10512 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10513 | REGNO (operands[3]), | |
10514 | NULL_RTX, | |
10515 | s390_indirect_branch_type_call); | |
10516 | return ""; | |
10517 | } | |
10518 | [(set_attr "op_type" "RIL") | |
10519 | (set_attr "mnemonic" "brasl") | |
10520 | (set_attr "type" "jsr") | |
10521 | (set_attr "atype" "agen") | |
10522 | (set_attr "z196prop" "z196_cracked")]) | |
10523 | ||
10524 | (define_insn "*basr_r_via_thunk" | |
10525 | [(set (match_operand 0 "" "") | |
10526 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10527 | (match_operand 2 "const_int_operand" "n"))) | |
10528 | (clobber (match_operand 3 "register_operand" "=&r")) | |
10529 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10530 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10531 | && !TARGET_CPU_Z10 | |
10532 | && !SIBLING_CALL_P (insn) | |
10533 | && GET_MODE (operands[3]) == Pmode" | |
10534 | { | |
10535 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10536 | REGNO (operands[3]), | |
10537 | NULL_RTX, | |
10538 | s390_indirect_branch_type_call); | |
10539 | return ""; | |
10540 | } | |
10541 | [(set_attr "op_type" "RIL") | |
10542 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10543 | (set_attr "type" "jsr") |
65b1d8ea AK |
10544 | (set_attr "atype" "agen") |
10545 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10546 | |
fd3cd001 UW |
10547 | ;; |
10548 | ;;- Thread-local storage support. | |
10549 | ;; | |
10550 | ||
8f4f98f6 IL |
10551 | (define_expand "@get_thread_pointer<mode>" |
10552 | [(set (match_operand:P 0 "nonimmediate_operand" "") | |
10553 | (unspec:P [(reg:P TP_REGNUM)] UNSPEC_GET_TP))] | |
f959607b | 10554 | "" |
c5aa1d12 | 10555 | "") |
fd3cd001 | 10556 | |
f959607b CLT |
10557 | (define_expand "set_thread_pointer<mode>" |
10558 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
10559 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
10560 | "" | |
c5aa1d12 UW |
10561 | "") |
10562 | ||
10563 | (define_insn "*set_tp" | |
ae156f85 | 10564 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
10565 | "" |
10566 | "" | |
10567 | [(set_attr "type" "none") | |
10568 | (set_attr "length" "0")]) | |
c7453384 | 10569 | |
fd3cd001 UW |
10570 | (define_insn "*tls_load_64" |
10571 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 10572 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
10573 | (match_operand:DI 2 "" "")] |
10574 | UNSPEC_TLS_LOAD))] | |
10575 | "TARGET_64BIT" | |
d40c829f | 10576 | "lg\t%0,%1%J2" |
9381e3f1 WG |
10577 | [(set_attr "op_type" "RXE") |
10578 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
10579 | |
10580 | (define_insn "*tls_load_31" | |
d3632d41 UW |
10581 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10582 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
10583 | (match_operand:SI 2 "" "")] |
10584 | UNSPEC_TLS_LOAD))] | |
10585 | "!TARGET_64BIT" | |
d3632d41 | 10586 | "@ |
d40c829f UW |
10587 | l\t%0,%1%J2 |
10588 | ly\t%0,%1%J2" | |
9381e3f1 | 10589 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 10590 | (set_attr "type" "load") |
3e4be43f | 10591 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 10592 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 10593 | |
9e8327e3 | 10594 | (define_insn "*bras_tls" |
c19ec8f9 | 10595 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10596 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10597 | (match_operand 2 "const_int_operand" "n"))) | |
10598 | (clobber (match_operand 3 "register_operand" "=r")) | |
10599 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10600 | "!SIBLING_CALL_P (insn) |
10601 | && TARGET_SMALL_EXEC | |
ed9676cf | 10602 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10603 | "bras\t%3,%1%J4" |
fd3cd001 | 10604 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10605 | (set_attr "type" "jsr") |
10606 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10607 | |
9e8327e3 | 10608 | (define_insn "*brasl_tls" |
c19ec8f9 | 10609 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10610 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10611 | (match_operand 2 "const_int_operand" "n"))) | |
10612 | (clobber (match_operand 3 "register_operand" "=r")) | |
10613 | (use (match_operand 4 "" ""))] | |
2f7e5a0d | 10614 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10615 | |
ed9676cf | 10616 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10617 | "brasl\t%3,%1%J4" |
10618 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10619 | (set_attr "type" "jsr") |
14cfceb7 IL |
10620 | (set_attr "z196prop" "z196_cracked") |
10621 | (set_attr "relative_long" "yes")]) | |
fd3cd001 | 10622 | |
9e8327e3 | 10623 | (define_insn "*basr_tls" |
c19ec8f9 | 10624 | [(set (match_operand 0 "" "") |
3e4be43f | 10625 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10626 | (match_operand 2 "const_int_operand" "n"))) |
10627 | (clobber (match_operand 3 "register_operand" "=r")) | |
10628 | (use (match_operand 4 "" ""))] | |
ed9676cf | 10629 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10630 | { |
10631 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10632 | return "basr\t%3,%1%J4"; | |
10633 | else | |
10634 | return "bas\t%3,%a1%J4"; | |
10635 | } | |
10636 | [(set (attr "op_type") | |
10637 | (if_then_else (match_operand 1 "register_operand" "") | |
10638 | (const_string "RR") (const_string "RX"))) | |
10639 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10640 | (set_attr "atype" "agen") |
10641 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10642 | |
e0374221 AS |
10643 | ;; |
10644 | ;;- Atomic operations | |
10645 | ;; | |
10646 | ||
10647 | ; | |
78ce265b | 10648 | ; memory barrier patterns. |
e0374221 AS |
10649 | ; |
10650 | ||
78ce265b RH |
10651 | (define_expand "mem_thread_fence" |
10652 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
10653 | "" | |
10654 | { | |
10655 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
10656 | enough not to require barriers of any kind. */ | |
46b35980 | 10657 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
10658 | { |
10659 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
10660 | MEM_VOLATILE_P (mem) = 1; | |
10661 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
10662 | } | |
10663 | DONE; | |
e0374221 AS |
10664 | }) |
10665 | ||
78ce265b RH |
10666 | ; Although bcr is superscalar on Z10, this variant will never |
10667 | ; become part of an execution group. | |
a9cc3f58 AK |
10668 | ; With z196 we can make use of the fast-BCR-serialization facility. |
10669 | ; This allows for a slightly faster sync which is sufficient for our | |
10670 | ; purposes. | |
78ce265b | 10671 | (define_insn "mem_thread_fence_1" |
e0374221 | 10672 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 10673 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 10674 | "" |
a9cc3f58 AK |
10675 | { |
10676 | if (TARGET_Z196) | |
10677 | return "bcr\t14,0"; | |
10678 | else | |
10679 | return "bcr\t15,0"; | |
10680 | } | |
10681 | [(set_attr "op_type" "RR") | |
10682 | (set_attr "mnemonic" "bcr_flush") | |
10683 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10684 | |
78ce265b RH |
10685 | ; |
10686 | ; atomic load/store operations | |
10687 | ; | |
10688 | ||
10689 | ; Atomic loads need not examine the memory model at all. | |
10690 | (define_expand "atomic_load<mode>" | |
10691 | [(match_operand:DINT 0 "register_operand") ;; output | |
10692 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10693 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10694 | "" | |
10695 | { | |
75cc21e2 AK |
10696 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10697 | FAIL; | |
10698 | ||
78ce265b RH |
10699 | if (<MODE>mode == TImode) |
10700 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10701 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10702 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10703 | else | |
10704 | emit_move_insn (operands[0], operands[1]); | |
10705 | DONE; | |
10706 | }) | |
10707 | ||
10708 | ; Different from movdi_31 in that we want no splitters. | |
10709 | (define_insn "atomic_loaddi_1" | |
10710 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10711 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10712 | UNSPEC_MOVA))] | |
10713 | "!TARGET_ZARCH" | |
10714 | "@ | |
10715 | lm\t%0,%M0,%S1 | |
10716 | lmy\t%0,%M0,%S1 | |
10717 | ld\t%0,%1 | |
10718 | ldy\t%0,%1" | |
10719 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10720 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10721 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10722 | ||
10723 | (define_insn "atomic_loadti_1" | |
10724 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10725 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10726 | UNSPEC_MOVA))] |
10727 | "TARGET_ZARCH" | |
10728 | "lpq\t%0,%1" | |
10729 | [(set_attr "op_type" "RXY") | |
10730 | (set_attr "type" "other")]) | |
10731 | ||
10732 | ; Atomic stores must(?) enforce sequential consistency. | |
10733 | (define_expand "atomic_store<mode>" | |
10734 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10735 | (match_operand:DINT 1 "register_operand") ;; input | |
10736 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10737 | "" | |
10738 | { | |
46b35980 | 10739 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10740 | |
75cc21e2 AK |
10741 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10742 | FAIL; | |
10743 | ||
78ce265b RH |
10744 | if (<MODE>mode == TImode) |
10745 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10746 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10747 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10748 | else | |
10749 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10750 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10751 | emit_insn (gen_mem_thread_fence (operands[2])); |
10752 | DONE; | |
10753 | }) | |
10754 | ||
10755 | ; Different from movdi_31 in that we want no splitters. | |
10756 | (define_insn "atomic_storedi_1" | |
10757 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10758 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10759 | UNSPEC_MOVA))] | |
10760 | "!TARGET_ZARCH" | |
10761 | "@ | |
10762 | stm\t%1,%N1,%S0 | |
10763 | stmy\t%1,%N1,%S0 | |
10764 | std %1,%0 | |
10765 | stdy %1,%0" | |
10766 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10767 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10768 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10769 | ||
10770 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10771 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10772 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10773 | UNSPEC_MOVA))] | |
10774 | "TARGET_ZARCH" | |
10775 | "stpq\t%1,%0" | |
10776 | [(set_attr "op_type" "RXY") | |
10777 | (set_attr "type" "other")]) | |
e0374221 AS |
10778 | |
10779 | ; | |
10780 | ; compare and swap patterns. | |
10781 | ; | |
10782 | ||
78ce265b RH |
10783 | (define_expand "atomic_compare_and_swap<mode>" |
10784 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
03db9ab5 DV |
10785 | (match_operand:DINT 1 "nonimmediate_operand");; oldval output |
10786 | (match_operand:DINT 2 "s_operand") ;; memory | |
10787 | (match_operand:DINT 3 "general_operand") ;; expected intput | |
10788 | (match_operand:DINT 4 "general_operand") ;; newval intput | |
78ce265b RH |
10789 | (match_operand:SI 5 "const_int_operand") ;; is_weak |
10790 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10791 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10792 | "" | |
10793 | { | |
03db9ab5 DV |
10794 | if (GET_MODE_BITSIZE (<MODE>mode) >= 16 |
10795 | && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) | |
75cc21e2 AK |
10796 | FAIL; |
10797 | ||
03db9ab5 DV |
10798 | s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], |
10799 | operands[3], operands[4], INTVAL (operands[5])); | |
10800 | DONE;}) | |
3093f076 | 10801 | |
78ce265b RH |
10802 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10803 | [(parallel | |
10804 | [(set (match_operand:DGPR 0 "register_operand") | |
03db9ab5 | 10805 | (match_operand:DGPR 1 "s_operand")) |
78ce265b RH |
10806 | (set (match_dup 1) |
10807 | (unspec_volatile:DGPR | |
10808 | [(match_dup 1) | |
10809 | (match_operand:DGPR 2 "register_operand") | |
10810 | (match_operand:DGPR 3 "register_operand")] | |
10811 | UNSPECV_CAS)) | |
03db9ab5 DV |
10812 | (set (match_operand 4 "cc_reg_operand") |
10813 | (match_dup 5))])] | |
10814 | "GET_MODE (operands[4]) == CCZmode | |
10815 | || GET_MODE (operands[4]) == CCZ1mode" | |
10816 | { | |
10817 | operands[5] | |
10818 | = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); | |
10819 | }) | |
78ce265b RH |
10820 | |
10821 | ; cdsg, csg | |
10822 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10823 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
bdb57bcb | 10824 | (match_operand:TDI 1 "nonsym_memory_operand" "+S")) |
8006eaa6 | 10825 | (set (match_dup 1) |
78ce265b | 10826 | (unspec_volatile:TDI |
8006eaa6 | 10827 | [(match_dup 1) |
78ce265b RH |
10828 | (match_operand:TDI 2 "register_operand" "0") |
10829 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 | 10830 | UNSPECV_CAS)) |
03db9ab5 DV |
10831 | (set (reg CC_REGNUM) |
10832 | (compare (match_dup 1) (match_dup 2)))] | |
10833 | "TARGET_ZARCH | |
10834 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10835 | "c<td>sg\t%0,%3,%S1" |
10836 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10837 | (set_attr "type" "sem")]) |
10838 | ||
78ce265b RH |
10839 | ; cds, cdsy |
10840 | (define_insn "*atomic_compare_and_swapdi_2" | |
10841 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
bdb57bcb | 10842 | (match_operand:DI 1 "nonsym_memory_operand" "+Q,S")) |
e0374221 | 10843 | (set (match_dup 1) |
78ce265b RH |
10844 | (unspec_volatile:DI |
10845 | [(match_dup 1) | |
10846 | (match_operand:DI 2 "register_operand" "0,0") | |
10847 | (match_operand:DI 3 "register_operand" "r,r")] | |
10848 | UNSPECV_CAS)) | |
03db9ab5 DV |
10849 | (set (reg CC_REGNUM) |
10850 | (compare (match_dup 1) (match_dup 2)))] | |
10851 | "!TARGET_ZARCH | |
10852 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10853 | "@ |
10854 | cds\t%0,%3,%S1 | |
10855 | cdsy\t%0,%3,%S1" | |
10856 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10857 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10858 | (set_attr "type" "sem")]) |
10859 | ||
10860 | ; cs, csy | |
10861 | (define_insn "*atomic_compare_and_swapsi_3" | |
10862 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
bdb57bcb | 10863 | (match_operand:SI 1 "nonsym_memory_operand" "+Q,S")) |
78ce265b RH |
10864 | (set (match_dup 1) |
10865 | (unspec_volatile:SI | |
e0374221 | 10866 | [(match_dup 1) |
78ce265b RH |
10867 | (match_operand:SI 2 "register_operand" "0,0") |
10868 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10869 | UNSPECV_CAS)) |
03db9ab5 DV |
10870 | (set (reg CC_REGNUM) |
10871 | (compare (match_dup 1) (match_dup 2)))] | |
10872 | "s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10873 | "@ |
10874 | cs\t%0,%3,%S1 | |
10875 | csy\t%0,%3,%S1" | |
10876 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10877 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10878 | (set_attr "type" "sem")]) |
10879 | ||
45d18331 AS |
10880 | ; |
10881 | ; Other atomic instruction patterns. | |
10882 | ; | |
10883 | ||
65b1d8ea AK |
10884 | ; z196 load and add, xor, or and and instructions |
10885 | ||
78ce265b RH |
10886 | (define_expand "atomic_fetch_<atomic><mode>" |
10887 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10888 | (ATOMIC_Z196:GPR | |
10889 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10890 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10891 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10892 | "TARGET_Z196" |
78ce265b | 10893 | { |
75cc21e2 AK |
10894 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10895 | FAIL; | |
10896 | ||
78ce265b RH |
10897 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10898 | (operands[0], operands[1], operands[2])); | |
10899 | DONE; | |
10900 | }) | |
65b1d8ea AK |
10901 | |
10902 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10903 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10904 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10905 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10906 | (set (match_dup 1) |
10907 | (unspec_volatile:GPR | |
10908 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10909 | (match_operand:GPR 2 "general_operand" "d"))] | |
10910 | UNSPECV_ATOMIC_OP)) | |
10911 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10912 | "TARGET_Z196" |
78ce265b RH |
10913 | "la<noxa><g>\t%0,%2,%1" |
10914 | [(set_attr "op_type" "RSY") | |
10915 | (set_attr "type" "sem")]) | |
65b1d8ea | 10916 | |
78ce265b RH |
10917 | ;; For SImode and larger, the optabs.c code will do just fine in |
10918 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10919 | ;; better by expanding our own loop. | |
65b1d8ea | 10920 | |
78ce265b RH |
10921 | (define_expand "atomic_<atomic><mode>" |
10922 | [(ATOMIC:HQI | |
10923 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10924 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10925 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10926 | "" |
78ce265b RH |
10927 | { |
10928 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10929 | operands[1], false); | |
10930 | DONE; | |
10931 | }) | |
45d18331 | 10932 | |
78ce265b RH |
10933 | (define_expand "atomic_fetch_<atomic><mode>" |
10934 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10935 | (ATOMIC:HQI | |
10936 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10937 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10938 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10939 | "" |
78ce265b RH |
10940 | { |
10941 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10942 | operands[2], false); | |
10943 | DONE; | |
10944 | }) | |
10945 | ||
10946 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10947 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10948 | (ATOMIC:HQI | |
10949 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10950 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10951 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10952 | "" | |
10953 | { | |
10954 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10955 | operands[2], true); | |
10956 | DONE; | |
10957 | }) | |
10958 | ||
03db9ab5 DV |
10959 | ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code |
10960 | ;; generated by the middleend is not good. | |
78ce265b | 10961 | (define_expand "atomic_exchange<mode>" |
03db9ab5 DV |
10962 | [(match_operand:DINT 0 "register_operand") ;; val out |
10963 | (match_operand:DINT 1 "s_operand") ;; memory | |
10964 | (match_operand:DINT 2 "general_operand") ;; val in | |
78ce265b | 10965 | (match_operand:SI 3 "const_int_operand")] ;; model |
45d18331 | 10966 | "" |
78ce265b | 10967 | { |
03db9ab5 DV |
10968 | if (<MODE>mode != QImode |
10969 | && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) | |
10970 | FAIL; | |
10971 | if (<MODE>mode == HImode || <MODE>mode == QImode) | |
10972 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], | |
10973 | false); | |
10974 | else if (<MODE>mode == SImode || TARGET_ZARCH) | |
10975 | s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); | |
10976 | else | |
10977 | FAIL; | |
78ce265b RH |
10978 | DONE; |
10979 | }) | |
45d18331 | 10980 | |
9db1d521 HP |
10981 | ;; |
10982 | ;;- Miscellaneous instructions. | |
10983 | ;; | |
10984 | ||
10985 | ; | |
10986 | ; allocate stack instruction pattern(s). | |
10987 | ; | |
10988 | ||
10989 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10990 | [(match_operand 0 "general_operand" "") |
10991 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10992 | "TARGET_BACKCHAIN" |
9db1d521 | 10993 | { |
ef44a6ff | 10994 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10995 | |
ef44a6ff UW |
10996 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10997 | anti_adjust_stack (operands[1]); | |
10998 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10999 | |
ef44a6ff UW |
11000 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
11001 | DONE; | |
10bbf137 | 11002 | }) |
9db1d521 HP |
11003 | |
11004 | ||
11005 | ; | |
43ab026f | 11006 | ; setjmp instruction pattern. |
9db1d521 HP |
11007 | ; |
11008 | ||
9db1d521 | 11009 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 11010 | [(match_operand 0 "" "")] |
f314b9b1 | 11011 | "flag_pic" |
9db1d521 | 11012 | { |
585539a1 | 11013 | emit_insn (s390_load_got ()); |
c41c1387 | 11014 | emit_use (pic_offset_table_rtx); |
9db1d521 | 11015 | DONE; |
fd7643fb | 11016 | }) |
9db1d521 | 11017 | |
9db1d521 HP |
11018 | ;; These patterns say how to save and restore the stack pointer. We need not |
11019 | ;; save the stack pointer at function level since we are careful to | |
11020 | ;; preserve the backchain. At block level, we have to restore the backchain | |
11021 | ;; when we restore the stack pointer. | |
11022 | ;; | |
11023 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
11024 | ;; backchain and restore both. Note that in the nonlocal case, the | |
11025 | ;; save area is a memory location. | |
11026 | ||
11027 | (define_expand "save_stack_function" | |
11028 | [(match_operand 0 "general_operand" "") | |
11029 | (match_operand 1 "general_operand" "")] | |
11030 | "" | |
11031 | "DONE;") | |
11032 | ||
11033 | (define_expand "restore_stack_function" | |
11034 | [(match_operand 0 "general_operand" "") | |
11035 | (match_operand 1 "general_operand" "")] | |
11036 | "" | |
11037 | "DONE;") | |
11038 | ||
11039 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
11040 | [(match_operand 0 "register_operand" "") |
11041 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 11042 | "TARGET_BACKCHAIN" |
9db1d521 | 11043 | { |
ef44a6ff UW |
11044 | rtx temp = gen_reg_rtx (Pmode); |
11045 | ||
11046 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
11047 | emit_move_insn (operands[0], operands[1]); | |
11048 | emit_move_insn (s390_back_chain_rtx (), temp); | |
11049 | ||
11050 | DONE; | |
10bbf137 | 11051 | }) |
9db1d521 HP |
11052 | |
11053 | (define_expand "save_stack_nonlocal" | |
11054 | [(match_operand 0 "memory_operand" "") | |
11055 | (match_operand 1 "register_operand" "")] | |
11056 | "" | |
9db1d521 | 11057 | { |
ef44a6ff UW |
11058 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
11059 | ||
11060 | /* Copy the backchain to the first word, sp to the second and the | |
11061 | literal pool base to the third. */ | |
11062 | ||
9602b6a1 AK |
11063 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
11064 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
11065 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
11066 | ||
b3d31392 | 11067 | if (TARGET_BACKCHAIN) |
9602b6a1 | 11068 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 11069 | |
9602b6a1 AK |
11070 | emit_move_insn (save_sp, operands[1]); |
11071 | emit_move_insn (save_bp, base); | |
9db1d521 | 11072 | |
9db1d521 | 11073 | DONE; |
10bbf137 | 11074 | }) |
9db1d521 HP |
11075 | |
11076 | (define_expand "restore_stack_nonlocal" | |
11077 | [(match_operand 0 "register_operand" "") | |
11078 | (match_operand 1 "memory_operand" "")] | |
11079 | "" | |
9db1d521 | 11080 | { |
490ceeb4 | 11081 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 11082 | rtx temp = NULL_RTX; |
9db1d521 | 11083 | |
43ab026f | 11084 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 11085 | literal pool base from the third. */ |
43ab026f | 11086 | |
9602b6a1 AK |
11087 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
11088 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
11089 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
11090 | ||
b3d31392 | 11091 | if (TARGET_BACKCHAIN) |
9602b6a1 | 11092 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 11093 | |
9602b6a1 AK |
11094 | emit_move_insn (base, save_bp); |
11095 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
11096 | |
11097 | if (temp) | |
11098 | emit_move_insn (s390_back_chain_rtx (), temp); | |
11099 | ||
c41c1387 | 11100 | emit_use (base); |
9db1d521 | 11101 | DONE; |
10bbf137 | 11102 | }) |
9db1d521 | 11103 | |
7bcebb25 AK |
11104 | (define_expand "exception_receiver" |
11105 | [(const_int 0)] | |
11106 | "" | |
11107 | { | |
11108 | s390_set_has_landing_pad_p (true); | |
11109 | DONE; | |
11110 | }) | |
9db1d521 HP |
11111 | |
11112 | ; | |
11113 | ; nop instruction pattern(s). | |
11114 | ; | |
11115 | ||
11116 | (define_insn "nop" | |
11117 | [(const_int 0)] | |
11118 | "" | |
aad98a61 AK |
11119 | "nopr\t%%r0" |
11120 | [(set_attr "op_type" "RR")]) | |
11121 | ||
11122 | ; non-branch NOPs required for optimizing compare-and-branch patterns | |
11123 | ; on z10 | |
11124 | ||
11125 | (define_insn "nop_lr0" | |
11126 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] | |
11127 | "" | |
d40c829f | 11128 | "lr\t0,0" |
729e750f WG |
11129 | [(set_attr "op_type" "RR") |
11130 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 11131 | |
aad98a61 AK |
11132 | (define_insn "nop_lr1" |
11133 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] | |
d277db6b WG |
11134 | "" |
11135 | "lr\t1,1" | |
11136 | [(set_attr "op_type" "RR")]) | |
11137 | ||
f8af0e30 DV |
11138 | ;;- Undeletable nops (used for hotpatching) |
11139 | ||
11140 | (define_insn "nop_2_byte" | |
11141 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
11142 | "" | |
4bbc8970 | 11143 | "nopr\t%%r0" |
f8af0e30 DV |
11144 | [(set_attr "op_type" "RR")]) |
11145 | ||
11146 | (define_insn "nop_4_byte" | |
11147 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
11148 | "" | |
11149 | "nop\t0" | |
11150 | [(set_attr "op_type" "RX")]) | |
11151 | ||
11152 | (define_insn "nop_6_byte" | |
11153 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
8cc6307c | 11154 | "" |
f8af0e30 | 11155 | "brcl\t0, 0" |
14cfceb7 IL |
11156 | [(set_attr "op_type" "RIL") |
11157 | (set_attr "relative_long" "yes")]) | |
f8af0e30 | 11158 | |
9db1d521 HP |
11159 | |
11160 | ; | |
11161 | ; Special literal pool access instruction pattern(s). | |
11162 | ; | |
11163 | ||
416cf582 UW |
11164 | (define_insn "*pool_entry" |
11165 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
11166 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 11167 | "" |
9db1d521 | 11168 | { |
ef4bddc2 | 11169 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 11170 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 11171 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
11172 | return ""; |
11173 | } | |
b628bd8e | 11174 | [(set (attr "length") |
416cf582 | 11175 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 11176 | |
9bb86f41 UW |
11177 | (define_insn "pool_align" |
11178 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
11179 | UNSPECV_POOL_ALIGN)] | |
11180 | "" | |
11181 | ".align\t%0" | |
b628bd8e | 11182 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 11183 | |
9bb86f41 UW |
11184 | (define_insn "pool_section_start" |
11185 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
11186 | "" | |
b929b470 MK |
11187 | { |
11188 | switch_to_section (targetm.asm_out.function_rodata_section | |
11189 | (current_function_decl)); | |
11190 | return ""; | |
11191 | } | |
b628bd8e | 11192 | [(set_attr "length" "0")]) |
b2ccb744 | 11193 | |
9bb86f41 UW |
11194 | (define_insn "pool_section_end" |
11195 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
11196 | "" | |
b929b470 MK |
11197 | { |
11198 | switch_to_section (current_function_section ()); | |
11199 | return ""; | |
11200 | } | |
b628bd8e | 11201 | [(set_attr "length" "0")]) |
b2ccb744 | 11202 | |
5af2f3d3 | 11203 | (define_insn "main_base_64" |
9e8327e3 UW |
11204 | [(set (match_operand 0 "register_operand" "=a") |
11205 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8cc6307c | 11206 | "GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
11207 | "larl\t%0,%1" |
11208 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 11209 | (set_attr "type" "larl") |
14cfceb7 IL |
11210 | (set_attr "z10prop" "z10_fwd_A1") |
11211 | (set_attr "relative_long" "yes")]) | |
5af2f3d3 UW |
11212 | |
11213 | (define_insn "main_pool" | |
585539a1 UW |
11214 | [(set (match_operand 0 "register_operand" "=a") |
11215 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
11216 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
11217 | { |
11218 | gcc_unreachable (); | |
11219 | } | |
9381e3f1 | 11220 | [(set (attr "type") |
8cc6307c | 11221 | (const_string "larl"))]) |
b2ccb744 | 11222 | |
aee4e0db | 11223 | (define_insn "reload_base_64" |
9e8327e3 UW |
11224 | [(set (match_operand 0 "register_operand" "=a") |
11225 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8cc6307c | 11226 | "GET_MODE (operands[0]) == Pmode" |
d40c829f | 11227 | "larl\t%0,%1" |
aee4e0db | 11228 | [(set_attr "op_type" "RIL") |
9381e3f1 | 11229 | (set_attr "type" "larl") |
729e750f | 11230 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 11231 | |
aee4e0db | 11232 | (define_insn "pool" |
fd7643fb | 11233 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 11234 | "" |
8d933e31 AS |
11235 | { |
11236 | gcc_unreachable (); | |
11237 | } | |
b628bd8e | 11238 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 11239 | |
4023fb28 UW |
11240 | ;; |
11241 | ;; Insns related to generating the function prologue and epilogue. | |
11242 | ;; | |
11243 | ||
11244 | ||
11245 | (define_expand "prologue" | |
11246 | [(use (const_int 0))] | |
11247 | "" | |
10bbf137 | 11248 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
11249 | |
11250 | (define_expand "epilogue" | |
11251 | [(use (const_int 1))] | |
11252 | "" | |
ed9676cf AK |
11253 | "s390_emit_epilogue (false); DONE;") |
11254 | ||
11255 | (define_expand "sibcall_epilogue" | |
11256 | [(use (const_int 0))] | |
11257 | "" | |
11258 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 11259 | |
177bc204 RS |
11260 | ;; A direct return instruction, without using an epilogue. |
11261 | (define_insn "<code>" | |
11262 | [(ANY_RETURN)] | |
11263 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
11264 | { |
11265 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11266 | { | |
11267 | /* The target is always r14 so there is no clobber | |
11268 | of r1 needed for pre z10 targets. */ | |
11269 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
11270 | INVALID_REGNUM, | |
11271 | NULL_RTX, | |
11272 | s390_indirect_branch_type_return); | |
11273 | return ""; | |
11274 | } | |
11275 | else | |
11276 | return "br\t%%r14"; | |
11277 | } | |
11278 | [(set (attr "op_type") | |
11279 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11280 | (const_string "RIL") | |
11281 | (const_string "RR"))) | |
11282 | (set (attr "mnemonic") | |
11283 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11284 | (const_string "jg") | |
11285 | (const_string "br"))) | |
177bc204 RS |
11286 | (set_attr "type" "jsr") |
11287 | (set_attr "atype" "agen")]) | |
11288 | ||
84b4c7b5 AK |
11289 | |
11290 | (define_expand "return_use" | |
11291 | [(parallel | |
11292 | [(return) | |
11293 | (use (match_operand 0 "register_operand" "a"))])] | |
11294 | "" | |
11295 | { | |
11296 | if (!TARGET_CPU_Z10 | |
11297 | && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) | |
11298 | { | |
11299 | if (TARGET_64BIT) | |
11300 | emit_jump_insn (gen_returndi_prez10 (operands[0])); | |
11301 | else | |
11302 | emit_jump_insn (gen_returnsi_prez10 (operands[0])); | |
11303 | DONE; | |
11304 | } | |
11305 | }) | |
11306 | ||
11307 | (define_insn "*return<mode>" | |
4023fb28 | 11308 | [(return) |
84b4c7b5 AK |
11309 | (use (match_operand:P 0 "register_operand" "a"))] |
11310 | "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
11311 | { | |
11312 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11313 | { | |
11314 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
11315 | INVALID_REGNUM, | |
11316 | NULL_RTX, | |
11317 | s390_indirect_branch_type_return); | |
11318 | return ""; | |
11319 | } | |
11320 | else | |
11321 | return "br\t%0"; | |
11322 | } | |
11323 | [(set (attr "op_type") | |
11324 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11325 | (const_string "RIL") | |
11326 | (const_string "RR"))) | |
11327 | (set (attr "mnemonic") | |
11328 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11329 | (const_string "jg") | |
11330 | (const_string "br"))) | |
11331 | (set_attr "type" "jsr") | |
11332 | (set_attr "atype" "agen")]) | |
11333 | ||
11334 | (define_insn "return<mode>_prez10" | |
11335 | [(return) | |
11336 | (use (match_operand:P 0 "register_operand" "a")) | |
11337 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
11338 | "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
11339 | { | |
11340 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
11341 | { | |
11342 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
11343 | INVALID_REGNUM, | |
11344 | NULL_RTX, | |
11345 | s390_indirect_branch_type_return); | |
11346 | return ""; | |
11347 | } | |
11348 | else | |
11349 | return "br\t%0"; | |
11350 | } | |
11351 | [(set (attr "op_type") | |
11352 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11353 | (const_string "RIL") | |
11354 | (const_string "RR"))) | |
11355 | (set (attr "mnemonic") | |
11356 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
11357 | (const_string "jg") | |
11358 | (const_string "br"))) | |
c7453384 | 11359 | (set_attr "type" "jsr") |
077dab3b | 11360 | (set_attr "atype" "agen")]) |
4023fb28 | 11361 | |
4023fb28 | 11362 | |
c7453384 | 11363 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 11364 | ;; pointer. This is used for compatibility. |
c7453384 EC |
11365 | |
11366 | (define_expand "ptr_extend" | |
11367 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11368 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 11369 | "TARGET_64BIT" |
c7453384 | 11370 | { |
c7453384 EC |
11371 | emit_insn (gen_anddi3 (operands[0], |
11372 | gen_lowpart (DImode, operands[1]), | |
11373 | GEN_INT (0x7fffffff))); | |
c7453384 | 11374 | DONE; |
10bbf137 | 11375 | }) |
4798630c D |
11376 | |
11377 | ;; Instruction definition to expand eh_return macro to support | |
11378 | ;; swapping in special linkage return addresses. | |
11379 | ||
11380 | (define_expand "eh_return" | |
11381 | [(use (match_operand 0 "register_operand" ""))] | |
11382 | "TARGET_TPF" | |
11383 | { | |
11384 | s390_emit_tpf_eh_return (operands[0]); | |
11385 | DONE; | |
11386 | }) | |
11387 | ||
7b8acc34 AK |
11388 | ; |
11389 | ; Stack Protector Patterns | |
11390 | ; | |
11391 | ||
11392 | (define_expand "stack_protect_set" | |
11393 | [(set (match_operand 0 "memory_operand" "") | |
11394 | (match_operand 1 "memory_operand" ""))] | |
11395 | "" | |
11396 | { | |
11397 | #ifdef TARGET_THREAD_SSP_OFFSET | |
11398 | operands[1] | |
11399 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11400 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11401 | #endif | |
11402 | if (TARGET_64BIT) | |
11403 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
11404 | else | |
11405 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
11406 | ||
11407 | DONE; | |
11408 | }) | |
11409 | ||
11410 | (define_insn "stack_protect_set<mode>" | |
11411 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
11412 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
11413 | "" | |
11414 | "mvc\t%O0(%G0,%R0),%S1" | |
11415 | [(set_attr "op_type" "SS")]) | |
11416 | ||
11417 | (define_expand "stack_protect_test" | |
11418 | [(set (reg:CC CC_REGNUM) | |
11419 | (compare (match_operand 0 "memory_operand" "") | |
11420 | (match_operand 1 "memory_operand" ""))) | |
11421 | (match_operand 2 "" "")] | |
11422 | "" | |
11423 | { | |
f90b7a5a | 11424 | rtx cc_reg, test; |
7b8acc34 AK |
11425 | #ifdef TARGET_THREAD_SSP_OFFSET |
11426 | operands[1] | |
11427 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11428 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11429 | #endif | |
7b8acc34 AK |
11430 | if (TARGET_64BIT) |
11431 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
11432 | else | |
11433 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
11434 | ||
f90b7a5a PB |
11435 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
11436 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
11437 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
11438 | DONE; |
11439 | }) | |
11440 | ||
11441 | (define_insn "stack_protect_test<mode>" | |
11442 | [(set (reg:CCZ CC_REGNUM) | |
11443 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
11444 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
11445 | "" | |
11446 | "clc\t%O0(%G0,%R0),%S1" | |
11447 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
11448 | |
11449 | ; This is used in s390_emit_prologue in order to prevent insns | |
11450 | ; adjusting the stack pointer to be moved over insns writing stack | |
11451 | ; slots using a copy of the stack pointer in a different register. | |
11452 | (define_insn "stack_tie" | |
11453 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
11454 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
11455 | "" | |
11456 | "" | |
11457 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
11458 | |
11459 | ||
82c6f58a AK |
11460 | (define_insn "stack_restore_from_fpr" |
11461 | [(set (reg:DI STACK_REGNUM) | |
11462 | (match_operand:DI 0 "register_operand" "f")) | |
11463 | (clobber (mem:BLK (scratch)))] | |
11464 | "TARGET_Z10" | |
11465 | "lgdr\t%%r15,%0" | |
11466 | [(set_attr "op_type" "RRE")]) | |
11467 | ||
963fc8d0 AK |
11468 | ; |
11469 | ; Data prefetch patterns | |
11470 | ; | |
11471 | ||
11472 | (define_insn "prefetch" | |
3e4be43f UW |
11473 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
11474 | (match_operand:SI 1 "const_int_operand" " n,n") | |
11475 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 11476 | "TARGET_Z10" |
963fc8d0 | 11477 | { |
4fe6dea8 AK |
11478 | switch (which_alternative) |
11479 | { | |
11480 | case 0: | |
4fe6dea8 | 11481 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 11482 | case 1: |
4fe6dea8 AK |
11483 | if (larl_operand (operands[0], Pmode)) |
11484 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 11485 | /* fallthrough */ |
4fe6dea8 AK |
11486 | default: |
11487 | ||
11488 | /* This might be reached for symbolic operands with an odd | |
11489 | addend. We simply omit the prefetch for such rare cases. */ | |
11490 | ||
11491 | return ""; | |
11492 | } | |
9381e3f1 | 11493 | } |
22d72dbc AK |
11494 | [(set_attr "type" "load,larl") |
11495 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea | 11496 | (set_attr "z10prop" "z10_super") |
14cfceb7 IL |
11497 | (set_attr "z196prop" "z196_alone") |
11498 | (set_attr "relative_long" "yes")]) | |
07da44ab AK |
11499 | |
11500 | ||
11501 | ; | |
11502 | ; Byte swap instructions | |
11503 | ; | |
11504 | ||
511f5bb1 AK |
11505 | ; FIXME: There is also mvcin but we cannot use it since src and target |
11506 | ; may overlap. | |
50dc4eed | 11507 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 11508 | (define_insn "bswap<mode>2" |
3e4be43f UW |
11509 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
11510 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11511 | "" |
07da44ab AK |
11512 | "@ |
11513 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
11514 | lrv<g>\t%0,%1 |
11515 | strv<g>\t%1,%0" | |
11516 | [(set_attr "type" "*,load,store") | |
11517 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 11518 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11519 | |
511f5bb1 | 11520 | (define_insn "bswaphi2" |
3e4be43f UW |
11521 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
11522 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11523 | "" |
6f5a59d1 AK |
11524 | "@ |
11525 | # | |
11526 | lrvh\t%0,%1 | |
11527 | strvh\t%1,%0" | |
11528 | [(set_attr "type" "*,load,store") | |
11529 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 11530 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11531 | |
6f5a59d1 AK |
11532 | (define_split |
11533 | [(set (match_operand:HI 0 "register_operand" "") | |
11534 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
8cc6307c | 11535 | "" |
6f5a59d1 | 11536 | [(set (match_dup 2) (bswap:SI (match_dup 3))) |
9060e335 | 11537 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 11538 | { |
9060e335 | 11539 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
11540 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
11541 | }) | |
11542 | ||
11543 | ||
65b1d8ea AK |
11544 | ; |
11545 | ; Population count instruction | |
11546 | ; | |
11547 | ||
80f8cd77 | 11548 | (define_insn "*popcountdi_z15_cc" |
25cb5165 AK |
11549 | [(set (reg CC_REGNUM) |
11550 | (compare (popcount:DI (match_operand:DI 1 "register_operand" "d")) | |
11551 | (const_int 0))) | |
11552 | (set (match_operand:DI 0 "register_operand" "=d") | |
11553 | (match_dup 1))] | |
80f8cd77 | 11554 | "TARGET_Z15 && s390_match_ccmode (insn, CCTmode)" |
25cb5165 AK |
11555 | "popcnt\t%0,%1,8" |
11556 | [(set_attr "op_type" "RRF")]) | |
11557 | ||
80f8cd77 | 11558 | (define_insn "*popcountdi_z15_cconly" |
25cb5165 AK |
11559 | [(set (reg CC_REGNUM) |
11560 | (compare (popcount:DI (match_operand:DI 1 "register_operand" "d")) | |
11561 | (const_int 0))) | |
11562 | (clobber (match_scratch:DI 0 "=d"))] | |
80f8cd77 | 11563 | "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" |
25cb5165 AK |
11564 | "popcnt\t%0,%1,8" |
11565 | [(set_attr "op_type" "RRF")]) | |
11566 | ||
80f8cd77 | 11567 | (define_insn "*popcountdi_z15" |
25cb5165 AK |
11568 | [(set (match_operand:DI 0 "register_operand" "=d") |
11569 | (popcount:DI (match_operand:DI 1 "register_operand" "d"))) | |
11570 | (clobber (reg:CC CC_REGNUM))] | |
80f8cd77 | 11571 | "TARGET_Z15" |
25cb5165 AK |
11572 | "popcnt\t%0,%1,8" |
11573 | [(set_attr "op_type" "RRF")]) | |
11574 | ||
80f8cd77 | 11575 | ; The pre-z15 popcount instruction counts the bits of op1 in 8 byte |
65b1d8ea | 11576 | ; portions and stores the result in the corresponding bytes in op0. |
25cb5165 | 11577 | (define_insn "*popcount<mode>_z196" |
65b1d8ea AK |
11578 | [(set (match_operand:INT 0 "register_operand" "=d") |
11579 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
11580 | (clobber (reg:CC CC_REGNUM))] | |
11581 | "TARGET_Z196" | |
11582 | "popcnt\t%0,%1" | |
11583 | [(set_attr "op_type" "RRE")]) | |
11584 | ||
25cb5165 | 11585 | (define_expand "popcountdi2_z196" |
65b1d8ea AK |
11586 | [; popcnt op0, op1 |
11587 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
11588 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
11589 | UNSPEC_POPCNT)) | |
11590 | (clobber (reg:CC CC_REGNUM))]) | |
11591 | ; sllg op2, op0, 32 | |
11592 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
11593 | ; agr op0, op2 | |
11594 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11595 | (clobber (reg:CC CC_REGNUM))]) | |
11596 | ; sllg op2, op0, 16 | |
17465c6e | 11597 | (set (match_dup 2) |
65b1d8ea AK |
11598 | (ashift:DI (match_dup 0) (const_int 16))) |
11599 | ; agr op0, op2 | |
11600 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11601 | (clobber (reg:CC CC_REGNUM))]) | |
11602 | ; sllg op2, op0, 8 | |
11603 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
11604 | ; agr op0, op2 | |
11605 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11606 | (clobber (reg:CC CC_REGNUM))]) | |
11607 | ; srlg op0, op0, 56 | |
11608 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
25cb5165 | 11609 | "TARGET_Z196" |
65b1d8ea AK |
11610 | "operands[2] = gen_reg_rtx (DImode);") |
11611 | ||
25cb5165 AK |
11612 | (define_expand "popcountdi2" |
11613 | [(parallel | |
11614 | [(set (match_operand:DI 0 "register_operand" "") | |
11615 | (popcount:DI (match_operand:DI 1 "register_operand"))) | |
11616 | (clobber (reg:CC CC_REGNUM))])] | |
11617 | "TARGET_Z196" | |
11618 | { | |
80f8cd77 | 11619 | if (!TARGET_Z15) |
25cb5165 AK |
11620 | { |
11621 | emit_insn (gen_popcountdi2_z196 (operands[0], operands[1])); | |
11622 | DONE; | |
11623 | } | |
11624 | }) | |
11625 | ||
11626 | (define_expand "popcountsi2_z196" | |
65b1d8ea AK |
11627 | [; popcnt op0, op1 |
11628 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
11629 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
11630 | UNSPEC_POPCNT)) | |
11631 | (clobber (reg:CC CC_REGNUM))]) | |
11632 | ; sllk op2, op0, 16 | |
17465c6e | 11633 | (set (match_dup 2) |
65b1d8ea AK |
11634 | (ashift:SI (match_dup 0) (const_int 16))) |
11635 | ; ar op0, op2 | |
11636 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11637 | (clobber (reg:CC CC_REGNUM))]) | |
11638 | ; sllk op2, op0, 8 | |
11639 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
11640 | ; ar op0, op2 | |
11641 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11642 | (clobber (reg:CC CC_REGNUM))]) | |
11643 | ; srl op0, op0, 24 | |
11644 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
11645 | "TARGET_Z196" | |
11646 | "operands[2] = gen_reg_rtx (SImode);") | |
11647 | ||
25cb5165 AK |
11648 | ; popcount always counts on the full 64 bit. With the z196 version |
11649 | ; counting bits per byte we just ignore the upper 4 bytes. With the | |
80f8cd77 | 11650 | ; z15 version we have to zero out the upper 32 bits first. |
25cb5165 AK |
11651 | (define_expand "popcountsi2" |
11652 | [(set (match_dup 2) | |
11653 | (zero_extend:DI (match_operand:SI 1 "register_operand"))) | |
11654 | (parallel [(set (match_dup 3) (popcount:DI (match_dup 2))) | |
11655 | (clobber (reg:CC CC_REGNUM))]) | |
11656 | (set (match_operand:SI 0 "register_operand") | |
11657 | (subreg:SI (match_dup 3) 4))] | |
11658 | "TARGET_Z196" | |
11659 | { | |
80f8cd77 | 11660 | if (!TARGET_Z15) |
25cb5165 AK |
11661 | { |
11662 | emit_insn (gen_popcountsi2_z196 (operands[0], operands[1])); | |
11663 | DONE; | |
11664 | } | |
11665 | else | |
11666 | { | |
11667 | operands[2] = gen_reg_rtx (DImode); | |
11668 | operands[3] = gen_reg_rtx (DImode); | |
11669 | } | |
11670 | }) | |
11671 | ||
11672 | (define_expand "popcounthi2_z196" | |
65b1d8ea AK |
11673 | [; popcnt op0, op1 |
11674 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
11675 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
11676 | UNSPEC_POPCNT)) | |
11677 | (clobber (reg:CC CC_REGNUM))]) | |
11678 | ; sllk op2, op0, 8 | |
17465c6e | 11679 | (set (match_dup 2) |
65b1d8ea AK |
11680 | (ashift:SI (match_dup 0) (const_int 8))) |
11681 | ; ar op0, op2 | |
11682 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11683 | (clobber (reg:CC CC_REGNUM))]) | |
11684 | ; srl op0, op0, 8 | |
11685 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
11686 | "TARGET_Z196" | |
11687 | "operands[2] = gen_reg_rtx (SImode);") | |
11688 | ||
25cb5165 AK |
11689 | (define_expand "popcounthi2" |
11690 | [(set (match_dup 2) | |
11691 | (zero_extend:DI (match_operand:HI 1 "register_operand"))) | |
11692 | (parallel [(set (match_dup 3) (popcount:DI (match_dup 2))) | |
11693 | (clobber (reg:CC CC_REGNUM))]) | |
11694 | (set (match_operand:HI 0 "register_operand") | |
11695 | (subreg:HI (match_dup 3) 6))] | |
11696 | "TARGET_Z196" | |
11697 | { | |
80f8cd77 | 11698 | if (!TARGET_Z15) |
25cb5165 AK |
11699 | { |
11700 | emit_insn (gen_popcounthi2_z196 (operands[0], operands[1])); | |
11701 | DONE; | |
11702 | } | |
11703 | else | |
11704 | { | |
11705 | operands[2] = gen_reg_rtx (DImode); | |
11706 | operands[3] = gen_reg_rtx (DImode); | |
11707 | } | |
11708 | }) | |
11709 | ||
11710 | ; For popcount on a single byte the old z196 style popcount | |
11711 | ; instruction is ideal. Since it anyway does a byte-wise popcount we | |
11712 | ; just use it instead of zero extending the QImode input to DImode and | |
80f8cd77 | 11713 | ; using the z15 popcount variant. |
65b1d8ea AK |
11714 | (define_expand "popcountqi2" |
11715 | [; popcnt op0, op1 | |
11716 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
11717 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
11718 | UNSPEC_POPCNT)) | |
11719 | (clobber (reg:CC CC_REGNUM))])] | |
11720 | "TARGET_Z196" | |
11721 | "") | |
11722 | ||
11723 | ;; | |
11724 | ;;- Copy sign instructions | |
11725 | ;; | |
11726 | ||
11727 | (define_insn "copysign<mode>3" | |
11728 | [(set (match_operand:FP 0 "register_operand" "=f") | |
11729 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
11730 | (match_operand:FP 2 "register_operand" "f")] | |
11731 | UNSPEC_COPYSIGN))] | |
11732 | "TARGET_Z196" | |
11733 | "cpsdr\t%0,%2,%1" | |
11734 | [(set_attr "op_type" "RRF") | |
11735 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
11736 | |
11737 | ||
11738 | ;; | |
11739 | ;;- Transactional execution instructions | |
11740 | ;; | |
11741 | ||
11742 | ; This splitter helps combine to make use of CC directly when | |
11743 | ; comparing the integer result of a tbegin builtin with a constant. | |
11744 | ; The unspec is already removed by canonicalize_comparison. So this | |
11745 | ; splitters only job is to turn the PARALLEL into separate insns | |
11746 | ; again. Unfortunately this only works with the very first cc/int | |
11747 | ; compare since combine is not able to deal with data flow across | |
11748 | ; basic block boundaries. | |
11749 | ||
11750 | ; It needs to be an insn pattern as well since combine does not apply | |
11751 | ; the splitter directly. Combine would only use it if it actually | |
11752 | ; would reduce the number of instructions. | |
11753 | (define_insn_and_split "*ccraw_to_int" | |
11754 | [(set (pc) | |
11755 | (if_then_else | |
11756 | (match_operator 0 "s390_eqne_operator" | |
11757 | [(reg:CCRAW CC_REGNUM) | |
11758 | (match_operand 1 "const_int_operand" "")]) | |
11759 | (label_ref (match_operand 2 "" "")) | |
11760 | (pc))) | |
11761 | (set (match_operand:SI 3 "register_operand" "=d") | |
11762 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
11763 | "" | |
11764 | "#" | |
11765 | "" | |
11766 | [(set (match_dup 3) | |
11767 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
11768 | (set (pc) | |
11769 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
11770 | (label_ref (match_dup 2)) | |
11771 | (pc)))] | |
11772 | "") | |
11773 | ||
11774 | ; Non-constrained transaction begin | |
11775 | ||
11776 | (define_expand "tbegin" | |
ee163e72 AK |
11777 | [(match_operand:SI 0 "register_operand" "") |
11778 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11779 | "TARGET_HTM" |
11780 | { | |
11781 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
11782 | DONE; | |
11783 | }) | |
11784 | ||
11785 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
11786 | [(match_operand:SI 0 "register_operand" "") |
11787 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11788 | "TARGET_HTM" |
11789 | { | |
11790 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
11791 | DONE; | |
11792 | }) | |
11793 | ||
11794 | (define_expand "tbegin_retry" | |
ee163e72 AK |
11795 | [(match_operand:SI 0 "register_operand" "") |
11796 | (match_operand:BLK 1 "memory_operand" "") | |
11797 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11798 | "TARGET_HTM" |
11799 | { | |
11800 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
11801 | DONE; | |
11802 | }) | |
11803 | ||
11804 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
11805 | [(match_operand:SI 0 "register_operand" "") |
11806 | (match_operand:BLK 1 "memory_operand" "") | |
11807 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11808 | "TARGET_HTM" |
11809 | { | |
11810 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
11811 | DONE; | |
11812 | }) | |
11813 | ||
c914ac45 AK |
11814 | ; Clobber VRs since they don't get restored |
11815 | (define_insn "tbegin_1_z13" | |
11816 | [(set (reg:CCRAW CC_REGNUM) | |
11817 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
11818 | UNSPECV_TBEGIN)) | |
11819 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11820 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
11821 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11822 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11823 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11824 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11825 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11826 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11827 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11828 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11829 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11830 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11831 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11832 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11833 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11834 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11835 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11836 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11837 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11838 | ; not supposed to be used for immediates (see genpreds.c). | |
11839 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11840 | "tbegin\t%1,%x0" | |
11841 | [(set_attr "op_type" "SIL")]) | |
11842 | ||
5a3fe9b6 AK |
11843 | (define_insn "tbegin_1" |
11844 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11845 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11846 | UNSPECV_TBEGIN)) |
2561451d AK |
11847 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11848 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11849 | (clobber (reg:DF 16)) |
11850 | (clobber (reg:DF 17)) | |
11851 | (clobber (reg:DF 18)) | |
11852 | (clobber (reg:DF 19)) | |
11853 | (clobber (reg:DF 20)) | |
11854 | (clobber (reg:DF 21)) | |
11855 | (clobber (reg:DF 22)) | |
11856 | (clobber (reg:DF 23)) | |
11857 | (clobber (reg:DF 24)) | |
11858 | (clobber (reg:DF 25)) | |
11859 | (clobber (reg:DF 26)) | |
11860 | (clobber (reg:DF 27)) | |
11861 | (clobber (reg:DF 28)) | |
11862 | (clobber (reg:DF 29)) | |
11863 | (clobber (reg:DF 30)) | |
11864 | (clobber (reg:DF 31))] | |
11865 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11866 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11867 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11868 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11869 | [(set_attr "op_type" "SIL")]) |
11870 | ||
11871 | ; Same as above but without the FPR clobbers | |
11872 | (define_insn "tbegin_nofloat_1" | |
11873 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11874 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11875 | UNSPECV_TBEGIN)) | |
11876 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11877 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11878 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11879 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11880 | [(set_attr "op_type" "SIL")]) |
11881 | ||
11882 | ||
11883 | ; Constrained transaction begin | |
11884 | ||
11885 | (define_expand "tbeginc" | |
11886 | [(set (reg:CCRAW CC_REGNUM) | |
11887 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11888 | UNSPECV_TBEGINC))] | |
11889 | "TARGET_HTM" | |
11890 | "") | |
11891 | ||
11892 | (define_insn "*tbeginc_1" | |
11893 | [(set (reg:CCRAW CC_REGNUM) | |
11894 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11895 | UNSPECV_TBEGINC))] | |
11896 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11897 | "tbeginc\t0,%x0" | |
11898 | [(set_attr "op_type" "SIL")]) | |
11899 | ||
11900 | ; Transaction end | |
11901 | ||
11902 | (define_expand "tend" | |
11903 | [(set (reg:CCRAW CC_REGNUM) | |
11904 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11905 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11906 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11907 | "TARGET_HTM" | |
11908 | "") | |
11909 | ||
11910 | (define_insn "*tend_1" | |
11911 | [(set (reg:CCRAW CC_REGNUM) | |
11912 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11913 | "TARGET_HTM" | |
11914 | "tend" | |
11915 | [(set_attr "op_type" "S")]) | |
11916 | ||
11917 | ; Transaction abort | |
11918 | ||
11919 | (define_expand "tabort" | |
eae48192 | 11920 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11921 | UNSPECV_TABORT)] |
11922 | "TARGET_HTM && operands != NULL" | |
11923 | { | |
11924 | if (CONST_INT_P (operands[0]) | |
11925 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11926 | { | |
63c79a75 JJ |
11927 | error ("invalid transaction abort code: %wd; values in range 0 " |
11928 | "through 255 are reserved", INTVAL (operands[0])); | |
5a3fe9b6 AK |
11929 | FAIL; |
11930 | } | |
11931 | }) | |
11932 | ||
11933 | (define_insn "*tabort_1" | |
eae48192 | 11934 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11935 | UNSPECV_TABORT)] |
11936 | "TARGET_HTM && operands != NULL" | |
11937 | "tabort\t%Y0" | |
11938 | [(set_attr "op_type" "S")]) | |
11939 | ||
eae48192 AK |
11940 | (define_insn "*tabort_1_plus" |
11941 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11942 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11943 | UNSPECV_TABORT)] | |
11944 | "TARGET_HTM && operands != NULL | |
11945 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11946 | "tabort\t%1(%0)" | |
11947 | [(set_attr "op_type" "S")]) | |
11948 | ||
5a3fe9b6 AK |
11949 | ; Transaction extract nesting depth |
11950 | ||
11951 | (define_insn "etnd" | |
11952 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11953 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11954 | "TARGET_HTM" | |
11955 | "etnd\t%0" | |
11956 | [(set_attr "op_type" "RRE")]) | |
11957 | ||
11958 | ; Non-transactional store | |
11959 | ||
11960 | (define_insn "ntstg" | |
3e4be43f | 11961 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11962 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11963 | UNSPECV_NTSTG))] | |
11964 | "TARGET_HTM" | |
11965 | "ntstg\t%1,%0" | |
11966 | [(set_attr "op_type" "RXY")]) | |
11967 | ||
11968 | ; Transaction perform processor assist | |
11969 | ||
11970 | (define_expand "tx_assist" | |
2561451d AK |
11971 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11972 | (reg:SI GPR0_REGNUM) | |
291a9e98 | 11973 | (const_int PPA_TX_ABORT)] |
5a3fe9b6 AK |
11974 | UNSPECV_PPA)] |
11975 | "TARGET_HTM" | |
2561451d | 11976 | "") |
5a3fe9b6 AK |
11977 | |
11978 | (define_insn "*ppa" | |
11979 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11980 | (match_operand:SI 1 "register_operand" "d") | |
11981 | (match_operand 2 "const_int_operand" "I")] | |
11982 | UNSPECV_PPA)] | |
291a9e98 | 11983 | "(TARGET_ZEC12 || TARGET_HTM) && INTVAL (operands[2]) < 16" |
2561451d | 11984 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11985 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11986 | |
11987 | ||
11988 | ; Set and get floating point control register | |
11989 | ||
3af82a61 | 11990 | (define_insn "sfpc" |
004f64e1 AK |
11991 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11992 | UNSPECV_SFPC)] | |
11993 | "TARGET_HARD_FLOAT" | |
11994 | "sfpc\t%0") | |
11995 | ||
3af82a61 | 11996 | (define_insn "efpc" |
004f64e1 AK |
11997 | [(set (match_operand:SI 0 "register_operand" "=d") |
11998 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11999 | "TARGET_HARD_FLOAT" | |
12000 | "efpc\t%0") | |
3af82a61 AK |
12001 | |
12002 | ||
12003 | ; Load count to block boundary | |
12004 | ||
12005 | (define_insn "lcbb" | |
12006 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 12007 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
12008 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
12009 | (clobber (reg:CC CC_REGNUM))] | |
12010 | "TARGET_Z13" | |
9a36359e | 12011 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 12012 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
12013 | |
12014 | ; Handle -fsplit-stack. | |
12015 | ||
12016 | (define_expand "split_stack_prologue" | |
12017 | [(const_int 0)] | |
12018 | "" | |
12019 | { | |
12020 | s390_expand_split_stack_prologue (); | |
12021 | DONE; | |
12022 | }) | |
12023 | ||
12024 | ;; If there are operand 0 bytes available on the stack, jump to | |
12025 | ;; operand 1. | |
12026 | ||
12027 | (define_expand "split_stack_space_check" | |
12028 | [(set (pc) (if_then_else | |
12029 | (ltu (minus (reg 15) | |
12030 | (match_operand 0 "register_operand")) | |
12031 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
12032 | (label_ref (match_operand 1)) | |
12033 | (pc)))] | |
12034 | "" | |
12035 | { | |
12036 | /* Offset from thread pointer to __private_ss. */ | |
12037 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
12038 | rtx tp = s390_get_thread_pointer (); | |
12039 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
12040 | rtx reg = gen_reg_rtx (Pmode); | |
12041 | rtx cc; | |
12042 | if (TARGET_64BIT) | |
12043 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
12044 | else | |
12045 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
12046 | cc = s390_emit_compare (GT, reg, guard); | |
12047 | s390_emit_jump (operands[1], cc); | |
12048 | ||
12049 | DONE; | |
12050 | }) | |
12051 | ||
051fb43f | 12052 | ;; Call to __morestack used by the split stack support |
4cb4721f | 12053 | |
051fb43f AK |
12054 | ; The insn has 3 parts: |
12055 | ; 1. A jump to the call done label. The jump will be done as part of | |
12056 | ; __morestack and will not be explicitly emitted to the insn stream. | |
12057 | ; 2. The call of __morestack including a use for r1 which is supposed to | |
12058 | ; point to the parameter block for __morestack. | |
12059 | ; 3. 3 USES whose values together with the call done label will be | |
12060 | ; used to emit the parameter block to the .rodata section. This | |
12061 | ; needs to be tied into the same insn as 1. since the call done | |
12062 | ; label is emitted also as part of the parm block. In order to | |
12063 | ; allow the edge to the BB with the call done label to be | |
12064 | ; redirected both need to make use of the same label_ref. | |
4cb4721f | 12065 | |
051fb43f AK |
12066 | (define_insn "@split_stack_call<mode>" |
12067 | [(set (pc) (label_ref (match_operand 2 "" ""))) ; call done label | |
4cb4721f MK |
12068 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") |
12069 | (reg:P 1)] | |
051fb43f AK |
12070 | UNSPECV_SPLIT_STACK_CALL)) |
12071 | (use (label_ref (match_operand 1 "" "X"))) ; parm block label | |
12072 | (use (match_operand 3 "const_int_operand" "X")) ; frame size | |
12073 | (use (match_operand 4 "const_int_operand" "X"))] ; arg size | |
8cc6307c | 12074 | "" |
051fb43f AK |
12075 | { |
12076 | s390_output_split_stack_data (operands[1], operands[2], operands[3], operands[4]); | |
12077 | return "jg\t%0"; | |
12078 | } | |
4cb4721f MK |
12079 | [(set_attr "op_type" "RIL") |
12080 | (set_attr "type" "branch")]) | |
12081 | ||
051fb43f | 12082 | ; As above but with a conditional jump |
4cb4721f | 12083 | |
051fb43f | 12084 | (define_insn "@split_stack_cond_call<mode>" |
4cb4721f MK |
12085 | [(set (pc) |
12086 | (if_then_else | |
051fb43f AK |
12087 | (match_operand 5 "" "") ; condition |
12088 | (label_ref (match_operand 2 "" "")) ; call done label | |
4cb4721f MK |
12089 | (pc))) |
12090 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
12091 | (reg:P 1)] | |
051fb43f AK |
12092 | UNSPECV_SPLIT_STACK_CALL)) |
12093 | (use (label_ref (match_operand 1 "" "X"))) ; parm block label | |
12094 | (use (match_operand 3 "const_int_operand" "X")) ; frame size | |
12095 | (use (match_operand 4 "const_int_operand" "X"))] ; arg size | |
8cc6307c | 12096 | "" |
051fb43f AK |
12097 | { |
12098 | s390_output_split_stack_data (operands[1], operands[2], operands[3], operands[4]); | |
12099 | return "jg%C5\t%0"; | |
12100 | } | |
4cb4721f MK |
12101 | [(set_attr "op_type" "RIL") |
12102 | (set_attr "type" "branch")]) | |
539405d5 | 12103 | |
051fb43f | 12104 | |
539405d5 AK |
12105 | (define_insn "osc_break" |
12106 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
12107 | "" | |
12108 | "bcr\t7,%%r0" | |
12109 | [(set_attr "op_type" "RR")]) | |
291a9e98 AK |
12110 | |
12111 | (define_expand "speculation_barrier" | |
12112 | [(unspec_volatile [(reg:SI GPR0_REGNUM) | |
12113 | (reg:SI GPR0_REGNUM) | |
12114 | (const_int PPA_OOO_BARRIER)] | |
12115 | UNSPECV_PPA)] | |
12116 | "TARGET_ZEC12" | |
12117 | "") |