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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
c161ecf7 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 4 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 5 | |
58add37a UW |
6 | ;; This file is part of GCC. |
7 | ||
8 | ;; GCC is free software; you can redistribute it and/or modify it under | |
9 | ;; the terms of the GNU General Public License as published by the Free | |
10 | ;; Software Foundation; either version 2, or (at your option) any later | |
11 | ;; version. | |
12 | ||
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | ;; for more details. | |
9db1d521 HP |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
58add37a UW |
19 | ;; along with GCC; see the file COPYING. If not, write to the Free |
20 | ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | ;; 02111-1307, USA. | |
9db1d521 HP |
22 | |
23 | ;; | |
24 | ;; Special constraints for s/390 machine description: | |
25 | ;; | |
26 | ;; a -- Any address register from 1 to 15. | |
27 | ;; d -- Any register from 0 to 15. | |
28 | ;; I -- An 8-bit constant (0..255). | |
29 | ;; J -- A 12-bit constant (0..4095). | |
30 | ;; K -- A 16-bit constant (-32768..32767). | |
31 | ;; Q -- A memory reference without index-register. | |
32 | ;; S -- Valid operand for the LARL instruction. | |
33 | ;; | |
34 | ;; Special formats used for outputting 390 instructions. | |
35 | ;; | |
36 | ;; %b -- Print a constant byte integer. xy | |
37 | ;; %h -- Print a signed 16-bit. wxyz | |
38 | ;; %N -- Print next register (second word of a DImode reg) or next word. | |
39 | ;; %M -- Print next register (second word of a TImode reg) or next word. | |
40 | ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)). | |
41 | ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). | |
42 | ;; | |
43 | ;; We have a special constraint for pattern matching. | |
44 | ;; | |
45 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
46 | ;; | |
9db1d521 | 47 | |
fd3cd001 UW |
48 | ;; |
49 | ;; UNSPEC usage | |
50 | ;; | |
51 | ||
52 | (define_constants | |
10bbf137 UW |
53 | [; Miscellaneous |
54 | (UNSPEC_ROUND 1) | |
55 | (UNSPEC_SETHIGH 10) | |
56 | ||
57 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
58 | (UNSPEC_LTREL_OFFSET 100) |
59 | (UNSPEC_LTREL_BASE 101) | |
60 | (UNSPEC_GOTENT 110) | |
61 | (UNSPEC_GOT 111) | |
62 | (UNSPEC_GOTOFF 112) | |
63 | (UNSPEC_PLT 113) | |
64 | (UNSPEC_PLTOFF 114) | |
65 | ||
66 | ; Literal pool | |
67 | (UNSPEC_RELOAD_BASE 210) | |
68 | ||
69 | ; TLS relocation specifiers | |
fd3cd001 UW |
70 | (UNSPEC_TLSGD 500) |
71 | (UNSPEC_TLSLDM 501) | |
72 | (UNSPEC_NTPOFF 502) | |
73 | (UNSPEC_DTPOFF 503) | |
74 | (UNSPEC_GOTNTPOFF 504) | |
75 | (UNSPEC_INDNTPOFF 505) | |
76 | ||
77 | ; TLS support | |
78 | (UNSPEC_TP 510) | |
79 | (UNSPEC_TLSLDM_NTPOFF 511) | |
80 | (UNSPEC_TLS_LOAD 512) | |
81 | ]) | |
82 | ||
83 | ;; | |
84 | ;; UNSPEC_VOLATILE usage | |
85 | ;; | |
86 | ||
87 | (define_constants | |
10bbf137 UW |
88 | [; Blockage |
89 | (UNSPECV_BLOCKAGE 0) | |
90 | ||
91 | ; Literal pool | |
fd7643fb UW |
92 | (UNSPECV_POOL 200) |
93 | (UNSPECV_POOL_START 201) | |
94 | (UNSPECV_POOL_END 202) | |
416cf582 | 95 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
96 | (UNSPECV_MAIN_POOL 300) |
97 | ||
98 | ; TLS support | |
fd3cd001 UW |
99 | (UNSPECV_SET_TP 500) |
100 | ]) | |
101 | ||
102 | ||
1fec52be HP |
103 | ;; Processor type. This attribute must exactly match the processor_type |
104 | ;; enumeration in s390.h. | |
105 | ||
f13e0d4e UW |
106 | (define_attr "cpu" "g5,g6,z900,z990" |
107 | (const (symbol_ref "s390_tune"))) | |
9db1d521 | 108 | |
f2d3c02a HP |
109 | ;; Define an insn type attribute. This is used in function unit delay |
110 | ;; computations. | |
9db1d521 | 111 | |
077dab3b HP |
112 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
113 | cs,vs,store,imul,idiv, | |
114 | branch,jsr,fsimpd,fsimps, | |
115 | floadd,floads,fstored, fstores, | |
116 | fmuld,fmuls,fdivd,fdivs, | |
117 | ftoi,itof,fsqrtd,fsqrts, | |
118 | other,o2,o3" | |
c7453384 | 119 | (const_string "integer")) |
9db1d521 | 120 | |
077dab3b | 121 | ;; Operand type. Used to default length attribute values |
9db1d521 | 122 | |
077dab3b | 123 | (define_attr "op_type" |
d3632d41 | 124 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" |
077dab3b HP |
125 | (const_string "RX")) |
126 | ||
127 | ;; Insn are devide in two classes: | |
128 | ;; agen: Insn using agen | |
129 | ;; reg: Insn not using agen | |
130 | ||
131 | (define_attr "atype" "agen,reg" | |
132 | (cond [ (eq_attr "op_type" "E") (const_string "reg") | |
133 | (eq_attr "op_type" "RR") (const_string "reg") | |
134 | (eq_attr "op_type" "RX") (const_string "agen") | |
135 | (eq_attr "op_type" "RI") (const_string "reg") | |
136 | (eq_attr "op_type" "RRE") (const_string "reg") | |
137 | (eq_attr "op_type" "RS") (const_string "agen") | |
138 | (eq_attr "op_type" "RSI") (const_string "agen") | |
139 | (eq_attr "op_type" "S") (const_string "agen") | |
140 | (eq_attr "op_type" "SI") (const_string "agen") | |
141 | (eq_attr "op_type" "SS") (const_string "agen") | |
142 | (eq_attr "op_type" "SSE") (const_string "agen") | |
143 | (eq_attr "op_type" "RXE") (const_string "agen") | |
144 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
145 | (eq_attr "op_type" "RIL") (const_string "agen") |
146 | (eq_attr "op_type" "RXY") (const_string "agen") | |
147 | (eq_attr "op_type" "RSY") (const_string "agen") | |
148 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
077dab3b | 149 | (const_string "reg"))) |
9db1d521 | 150 | |
c7453384 | 151 | ;; Generic pipeline function unit. |
9db1d521 | 152 | |
4023fb28 UW |
153 | (define_function_unit "integer" 1 0 |
154 | (eq_attr "type" "none") 0 0) | |
155 | ||
f2d3c02a HP |
156 | (define_function_unit "integer" 1 0 |
157 | (eq_attr "type" "integer") 1 1) | |
9db1d521 | 158 | |
077dab3b HP |
159 | (define_function_unit "integer" 1 0 |
160 | (eq_attr "type" "fsimpd") 1 1) | |
161 | ||
162 | (define_function_unit "integer" 1 0 | |
163 | (eq_attr "type" "fsimps") 1 1) | |
164 | ||
f2d3c02a HP |
165 | (define_function_unit "integer" 1 0 |
166 | (eq_attr "type" "load") 1 1) | |
9db1d521 | 167 | |
077dab3b HP |
168 | (define_function_unit "integer" 1 0 |
169 | (eq_attr "type" "floadd") 1 1) | |
170 | ||
171 | (define_function_unit "integer" 1 0 | |
172 | (eq_attr "type" "floads") 1 1) | |
173 | ||
f2d3c02a HP |
174 | (define_function_unit "integer" 1 0 |
175 | (eq_attr "type" "la") 1 1) | |
9db1d521 | 176 | |
077dab3b HP |
177 | (define_function_unit "integer" 1 0 |
178 | (eq_attr "type" "larl") 1 1) | |
179 | ||
f2d3c02a HP |
180 | (define_function_unit "integer" 1 0 |
181 | (eq_attr "type" "lr") 1 1) | |
9db1d521 | 182 | |
077dab3b HP |
183 | (define_function_unit "integer" 1 0 |
184 | (eq_attr "type" "branch") 1 1) | |
185 | ||
f2d3c02a HP |
186 | (define_function_unit "integer" 1 0 |
187 | (eq_attr "type" "store") 1 1) | |
9db1d521 | 188 | |
077dab3b HP |
189 | (define_function_unit "integer" 1 0 |
190 | (eq_attr "type" "fstored") 1 1) | |
191 | ||
192 | (define_function_unit "integer" 1 0 | |
193 | (eq_attr "type" "fstores") 1 1) | |
194 | ||
4023fb28 UW |
195 | (define_function_unit "integer" 1 0 |
196 | (eq_attr "type" "lm") 2 2) | |
197 | ||
198 | (define_function_unit "integer" 1 0 | |
199 | (eq_attr "type" "stm") 2 2) | |
200 | ||
201 | (define_function_unit "integer" 1 0 | |
202 | (eq_attr "type" "cs") 5 5) | |
203 | ||
204 | (define_function_unit "integer" 1 0 | |
205 | (eq_attr "type" "vs") 30 30) | |
206 | ||
f2d3c02a HP |
207 | (define_function_unit "integer" 1 0 |
208 | (eq_attr "type" "jsr") 5 5) | |
9db1d521 | 209 | |
f2d3c02a HP |
210 | (define_function_unit "integer" 1 0 |
211 | (eq_attr "type" "imul") 7 7) | |
212 | ||
213 | (define_function_unit "integer" 1 0 | |
077dab3b HP |
214 | (eq_attr "type" "fmuld") 6 6) |
215 | ||
216 | (define_function_unit "integer" 1 0 | |
217 | (eq_attr "type" "fmuls") 6 6) | |
9db1d521 | 218 | |
f2d3c02a HP |
219 | (define_function_unit "integer" 1 0 |
220 | (eq_attr "type" "idiv") 33 33) | |
9db1d521 | 221 | |
f2d3c02a | 222 | (define_function_unit "integer" 1 0 |
077dab3b HP |
223 | (eq_attr "type" "fdivd") 33 33) |
224 | ||
225 | (define_function_unit "integer" 1 0 | |
226 | (eq_attr "type" "fdivs") 33 33) | |
227 | ||
228 | (define_function_unit "integer" 1 0 | |
229 | (eq_attr "type" "fsqrtd") 30 30) | |
230 | ||
231 | (define_function_unit "integer" 1 0 | |
232 | (eq_attr "type" "fsqrts") 30 30) | |
233 | ||
234 | (define_function_unit "integer" 1 0 | |
235 | (eq_attr "type" "ftoi") 2 2) | |
236 | ||
237 | (define_function_unit "integer" 1 0 | |
238 | (eq_attr "type" "itof") 2 2) | |
9db1d521 | 239 | |
f2d3c02a HP |
240 | (define_function_unit "integer" 1 0 |
241 | (eq_attr "type" "o2") 2 2) | |
9db1d521 | 242 | |
f2d3c02a HP |
243 | (define_function_unit "integer" 1 0 |
244 | (eq_attr "type" "o3") 3 3) | |
9db1d521 | 245 | |
f2d3c02a HP |
246 | (define_function_unit "integer" 1 0 |
247 | (eq_attr "type" "other") 5 5) | |
248 | ||
077dab3b | 249 | ;; Pipeline description for z900 |
9db1d521 | 250 | |
077dab3b | 251 | (include "2064.md") |
52609473 | 252 | (include "2084.md") |
9db1d521 HP |
253 | |
254 | ;; Length in bytes. | |
255 | ||
256 | (define_attr "length" "" | |
257 | (cond [ (eq_attr "op_type" "E") (const_int 2) | |
258 | (eq_attr "op_type" "RR") (const_int 2) | |
259 | (eq_attr "op_type" "RX") (const_int 4) | |
260 | (eq_attr "op_type" "RI") (const_int 4) | |
261 | (eq_attr "op_type" "RRE") (const_int 4) | |
262 | (eq_attr "op_type" "RS") (const_int 4) | |
263 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
264 | (eq_attr "op_type" "S") (const_int 4) |
265 | (eq_attr "op_type" "SI") (const_int 4) | |
266 | (eq_attr "op_type" "SS") (const_int 6) | |
267 | (eq_attr "op_type" "SSE") (const_int 6) | |
268 | (eq_attr "op_type" "RXE") (const_int 6) | |
269 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
270 | (eq_attr "op_type" "RIL") (const_int 6) |
271 | (eq_attr "op_type" "RXY") (const_int 6) | |
272 | (eq_attr "op_type" "RSY") (const_int 6) | |
273 | (eq_attr "op_type" "SIY") (const_int 6)] | |
9db1d521 HP |
274 | (const_int 4))) |
275 | ||
276 | ;; Define attributes for `asm' insns. | |
277 | ||
f2d3c02a | 278 | (define_asm_attributes [(set_attr "type" "other") |
9db1d521 HP |
279 | (set_attr "op_type" "NN")]) |
280 | ||
281 | ;; | |
282 | ;; Condition Codes | |
283 | ;; | |
284 | ; | |
285 | ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) | |
286 | ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) | |
287 | ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) | |
288 | ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) | |
289 | ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) | |
c7453384 | 290 | |
9db1d521 HP |
291 | ; CCZ -> CCL / CCZ1 |
292 | ; CCZ1 -> CCA/CCU/CCS/CCT | |
293 | ; CCS -> CCA | |
c7453384 | 294 | |
9db1d521 HP |
295 | ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST |
296 | ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT | |
297 | ||
298 | ||
299 | ;; | |
300 | ;;- Compare instructions. | |
301 | ;; | |
302 | ||
303 | (define_expand "cmpdi" | |
304 | [(set (reg:CC 33) | |
305 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
306 | (match_operand:DI 1 "general_operand" "")))] | |
307 | "TARGET_64BIT" | |
9db1d521 HP |
308 | { |
309 | s390_compare_op0 = operands[0]; | |
310 | s390_compare_op1 = operands[1]; | |
311 | DONE; | |
10bbf137 | 312 | }) |
9db1d521 HP |
313 | |
314 | (define_expand "cmpsi" | |
315 | [(set (reg:CC 33) | |
316 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
317 | (match_operand:SI 1 "general_operand" "")))] | |
318 | "" | |
9db1d521 HP |
319 | { |
320 | s390_compare_op0 = operands[0]; | |
321 | s390_compare_op1 = operands[1]; | |
322 | DONE; | |
10bbf137 | 323 | }) |
9db1d521 | 324 | |
9db1d521 HP |
325 | (define_expand "cmpdf" |
326 | [(set (reg:CC 33) | |
327 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
328 | (match_operand:DF 1 "general_operand" "")))] | |
329 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
330 | { |
331 | s390_compare_op0 = operands[0]; | |
332 | s390_compare_op1 = operands[1]; | |
333 | DONE; | |
10bbf137 | 334 | }) |
9db1d521 HP |
335 | |
336 | (define_expand "cmpsf" | |
337 | [(set (reg:CC 33) | |
338 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
339 | (match_operand:SF 1 "general_operand" "")))] | |
340 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
341 | { |
342 | s390_compare_op0 = operands[0]; | |
343 | s390_compare_op1 = operands[1]; | |
344 | DONE; | |
10bbf137 | 345 | }) |
9db1d521 HP |
346 | |
347 | ||
07893d4f | 348 | ; Test-under-Mask (zero_extract) instructions |
9db1d521 | 349 | |
07893d4f | 350 | (define_insn "*tmdi_ext" |
9db1d521 HP |
351 | [(set (reg 33) |
352 | (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d") | |
4023fb28 UW |
353 | (match_operand:DI 1 "const_int_operand" "n") |
354 | (match_operand:DI 2 "const_int_operand" "n")) | |
9db1d521 | 355 | (const_int 0)))] |
4023fb28 | 356 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
c7453384 | 357 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
4023fb28 UW |
358 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 |
359 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
360 | == INTVAL (operands[2]) >> 4" | |
9db1d521 | 361 | { |
4023fb28 UW |
362 | int part = INTVAL (operands[2]) >> 4; |
363 | int block = (1 << INTVAL (operands[1])) - 1; | |
364 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
9db1d521 | 365 | |
4023fb28 | 366 | operands[2] = GEN_INT (block << shift); |
9db1d521 | 367 | |
4023fb28 UW |
368 | switch (part) |
369 | { | |
d40c829f UW |
370 | case 0: return "tmhh\t%0,%x2"; |
371 | case 1: return "tmhl\t%0,%x2"; | |
372 | case 2: return "tmlh\t%0,%x2"; | |
373 | case 3: return "tmll\t%0,%x2"; | |
4023fb28 UW |
374 | default: abort (); |
375 | } | |
10bbf137 | 376 | } |
4023fb28 UW |
377 | [(set_attr "op_type" "RI")]) |
378 | ||
07893d4f | 379 | (define_insn "*tmsi_ext" |
9db1d521 | 380 | [(set (reg 33) |
07893d4f UW |
381 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") |
382 | (match_operand:SI 1 "const_int_operand" "n") | |
383 | (match_operand:SI 2 "const_int_operand" "n")) | |
9db1d521 | 384 | (const_int 0)))] |
07893d4f | 385 | "s390_match_ccmode(insn, CCTmode) |
c7453384 | 386 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
07893d4f UW |
387 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 |
388 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
389 | == INTVAL (operands[2]) >> 4" | |
9db1d521 | 390 | { |
07893d4f UW |
391 | int part = INTVAL (operands[2]) >> 4; |
392 | int block = (1 << INTVAL (operands[1])) - 1; | |
393 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
394 | ||
395 | operands[2] = GEN_INT (block << shift); | |
9db1d521 | 396 | |
4023fb28 | 397 | switch (part) |
9db1d521 | 398 | { |
d40c829f UW |
399 | case 0: return "tmh\t%0,%x2"; |
400 | case 1: return "tml\t%0,%x2"; | |
4023fb28 | 401 | default: abort (); |
9db1d521 | 402 | } |
10bbf137 | 403 | } |
4023fb28 UW |
404 | [(set_attr "op_type" "RI")]) |
405 | ||
07893d4f | 406 | (define_insn "*tmqi_ext" |
4023fb28 | 407 | [(set (reg 33) |
d3632d41 UW |
408 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S") |
409 | (match_operand:SI 1 "const_int_operand" "n,n") | |
410 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
4023fb28 | 411 | (const_int 0)))] |
07893d4f | 412 | "s390_match_ccmode(insn, CCTmode) |
c7453384 | 413 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
07893d4f | 414 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" |
4023fb28 | 415 | { |
07893d4f UW |
416 | int block = (1 << INTVAL (operands[1])) - 1; |
417 | int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); | |
9db1d521 | 418 | |
07893d4f | 419 | operands[2] = GEN_INT (block << shift); |
d40c829f | 420 | return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; |
10bbf137 | 421 | } |
d3632d41 | 422 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 423 | |
07893d4f | 424 | ; Test-under-Mask instructions |
9db1d521 | 425 | |
07893d4f UW |
426 | (define_insn "*tmdi_mem" |
427 | [(set (reg 33) | |
d3632d41 UW |
428 | (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S") |
429 | (match_operand:DI 1 "immediate_operand" "n,n")) | |
430 | (match_operand:DI 2 "immediate_operand" "n,n")))] | |
07893d4f UW |
431 | "TARGET_64BIT |
432 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) | |
433 | && s390_single_qi (operands[1], DImode, 0) >= 0" | |
07893d4f UW |
434 | { |
435 | int part = s390_single_qi (operands[1], DImode, 0); | |
436 | operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part)); | |
437 | ||
c7453384 | 438 | operands[0] = gen_rtx_MEM (QImode, |
07893d4f | 439 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 440 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 441 | } |
d3632d41 | 442 | [(set_attr "op_type" "SI,SIY")]) |
07893d4f UW |
443 | |
444 | (define_insn "*tmsi_mem" | |
4023fb28 | 445 | [(set (reg 33) |
d3632d41 UW |
446 | (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S") |
447 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
448 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 449 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
4023fb28 | 450 | && s390_single_qi (operands[1], SImode, 0) >= 0" |
4023fb28 UW |
451 | { |
452 | int part = s390_single_qi (operands[1], SImode, 0); | |
453 | operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part)); | |
454 | ||
c7453384 | 455 | operands[0] = gen_rtx_MEM (QImode, |
4023fb28 | 456 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 457 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 458 | } |
077dab3b | 459 | [(set_attr "op_type" "SI")]) |
9db1d521 | 460 | |
07893d4f | 461 | (define_insn "*tmhi_mem" |
9db1d521 | 462 | [(set (reg 33) |
d3632d41 UW |
463 | (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0) |
464 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
465 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f UW |
466 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
467 | && s390_single_qi (operands[1], HImode, 0) >= 0" | |
07893d4f UW |
468 | { |
469 | int part = s390_single_qi (operands[1], HImode, 0); | |
470 | operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part)); | |
9db1d521 | 471 | |
c7453384 | 472 | operands[0] = gen_rtx_MEM (QImode, |
07893d4f | 473 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 474 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 475 | } |
077dab3b | 476 | [(set_attr "op_type" "SI")]) |
9db1d521 | 477 | |
07893d4f | 478 | (define_insn "*tmqi_mem" |
9db1d521 | 479 | [(set (reg 33) |
d3632d41 UW |
480 | (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0) |
481 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
482 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 483 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" |
d3632d41 | 484 | "@ |
d40c829f UW |
485 | tm\t%0,%b1 |
486 | tmy\t%0,%b1" | |
d3632d41 | 487 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 488 | |
05b9aaaa UW |
489 | (define_insn "*tmdi_reg" |
490 | [(set (reg 33) | |
491 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d") | |
492 | (match_operand:DI 1 "immediate_operand" "n")) | |
493 | (match_operand:DI 2 "immediate_operand" "n")))] | |
494 | "TARGET_64BIT | |
495 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
496 | && s390_single_hi (operands[1], DImode, 0) >= 0" | |
05b9aaaa UW |
497 | { |
498 | int part = s390_single_hi (operands[1], DImode, 0); | |
499 | operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); | |
500 | ||
501 | switch (part) | |
502 | { | |
d40c829f UW |
503 | case 0: return "tmhh\t%0,%x1"; |
504 | case 1: return "tmhl\t%0,%x1"; | |
505 | case 2: return "tmlh\t%0,%x1"; | |
506 | case 3: return "tmll\t%0,%x1"; | |
05b9aaaa UW |
507 | default: abort (); |
508 | } | |
10bbf137 | 509 | } |
05b9aaaa UW |
510 | [(set_attr "op_type" "RI")]) |
511 | ||
512 | (define_insn "*tmsi_reg" | |
513 | [(set (reg 33) | |
514 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d") | |
515 | (match_operand:SI 1 "immediate_operand" "n")) | |
516 | (match_operand:SI 2 "immediate_operand" "n")))] | |
517 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
518 | && s390_single_hi (operands[1], SImode, 0) >= 0" | |
05b9aaaa UW |
519 | { |
520 | int part = s390_single_hi (operands[1], SImode, 0); | |
521 | operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); | |
522 | ||
523 | switch (part) | |
524 | { | |
d40c829f UW |
525 | case 0: return "tmh\t%0,%x1"; |
526 | case 1: return "tml\t%0,%x1"; | |
05b9aaaa UW |
527 | default: abort (); |
528 | } | |
10bbf137 | 529 | } |
05b9aaaa UW |
530 | [(set_attr "op_type" "RI")]) |
531 | ||
07893d4f | 532 | (define_insn "*tmhi_full" |
9db1d521 | 533 | [(set (reg 33) |
07893d4f UW |
534 | (compare (match_operand:HI 0 "register_operand" "d") |
535 | (match_operand:HI 1 "immediate_operand" "n")))] | |
536 | "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" | |
d40c829f | 537 | "tml\t%0,65535" |
07893d4f | 538 | [(set_attr "op_type" "RX")]) |
9db1d521 | 539 | |
07893d4f | 540 | (define_insn "*tmqi_full" |
9db1d521 | 541 | [(set (reg 33) |
07893d4f UW |
542 | (compare (match_operand:QI 0 "register_operand" "d") |
543 | (match_operand:QI 1 "immediate_operand" "n")))] | |
544 | "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" | |
d40c829f | 545 | "tml\t%0,255" |
07893d4f | 546 | [(set_attr "op_type" "RI")]) |
9db1d521 | 547 | |
07893d4f UW |
548 | |
549 | ; Load-and-Test instructions | |
550 | ||
551 | (define_insn "*tstdi_sign" | |
9db1d521 | 552 | [(set (reg 33) |
07893d4f UW |
553 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
554 | (const_int 32)) (const_int 32)) | |
555 | (match_operand:DI 1 "const0_operand" ""))) | |
556 | (set (match_operand:DI 2 "register_operand" "=d") | |
557 | (sign_extend:DI (match_dup 0)))] | |
558 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 559 | "ltgfr\t%2,%0" |
07893d4f UW |
560 | [(set_attr "op_type" "RRE")]) |
561 | ||
562 | (define_insn "*tstdi" | |
9db1d521 | 563 | [(set (reg 33) |
07893d4f UW |
564 | (compare (match_operand:DI 0 "register_operand" "d") |
565 | (match_operand:DI 1 "const0_operand" ""))) | |
566 | (set (match_operand:DI 2 "register_operand" "=d") | |
567 | (match_dup 0))] | |
568 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 569 | "ltgr\t%2,%0" |
07893d4f | 570 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 571 | |
07893d4f | 572 | (define_insn "*tstdi_cconly" |
9db1d521 | 573 | [(set (reg 33) |
07893d4f UW |
574 | (compare (match_operand:DI 0 "register_operand" "d") |
575 | (match_operand:DI 1 "const0_operand" "")))] | |
576 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 577 | "ltgr\t%0,%0" |
07893d4f | 578 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 579 | |
07893d4f UW |
580 | (define_insn "*tstdi_cconly_31" |
581 | [(set (reg 33) | |
582 | (compare (match_operand:DI 0 "register_operand" "d") | |
583 | (match_operand:DI 1 "const0_operand" "")))] | |
584 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 585 | "srda\t%0,0" |
077dab3b HP |
586 | [(set_attr "op_type" "RS") |
587 | (set_attr "atype" "reg")]) | |
588 | ||
4023fb28 | 589 | |
07893d4f UW |
590 | (define_insn "*tstsi" |
591 | [(set (reg 33) | |
d3632d41 | 592 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 593 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 594 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f UW |
595 | (match_dup 0))] |
596 | "s390_match_ccmode(insn, CCSmode)" | |
597 | "@ | |
d40c829f UW |
598 | ltr\t%2,%0 |
599 | icm\t%2,15,%0 | |
600 | icmy\t%2,15,%0" | |
d3632d41 | 601 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 602 | |
07893d4f | 603 | (define_insn "*tstsi_cconly" |
4023fb28 | 604 | [(set (reg 33) |
d3632d41 | 605 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 606 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 607 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
608 | "s390_match_ccmode(insn, CCSmode)" |
609 | "@ | |
d40c829f UW |
610 | ltr\t%0,%0 |
611 | icm\t%2,15,%0 | |
612 | icmy\t%2,15,%0" | |
d3632d41 | 613 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 614 | |
07893d4f UW |
615 | (define_insn "*tstsi_cconly2" |
616 | [(set (reg 33) | |
617 | (compare (match_operand:SI 0 "register_operand" "d") | |
618 | (match_operand:SI 1 "const0_operand" "")))] | |
619 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 620 | "ltr\t%0,%0" |
07893d4f | 621 | [(set_attr "op_type" "RR")]) |
4023fb28 | 622 | |
3af97654 UW |
623 | (define_insn "*tsthiCCT" |
624 | [(set (reg 33) | |
d3632d41 | 625 | (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 626 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 627 | (set (match_operand:HI 2 "register_operand" "=d,d,0") |
3af97654 UW |
628 | (match_dup 0))] |
629 | "s390_match_ccmode(insn, CCTmode)" | |
630 | "@ | |
d40c829f UW |
631 | icm\t%2,3,%0 |
632 | icmy\t%2,3,%0 | |
633 | tml\t%0,65535" | |
d3632d41 | 634 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
635 | |
636 | (define_insn "*tsthiCCT_cconly" | |
637 | [(set (reg 33) | |
d3632d41 | 638 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 639 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 640 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
641 | "s390_match_ccmode(insn, CCTmode)" |
642 | "@ | |
d40c829f UW |
643 | icm\t%2,3,%0 |
644 | icmy\t%2,3,%0 | |
645 | tml\t%0,65535" | |
d3632d41 | 646 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 647 | |
07893d4f | 648 | (define_insn "*tsthi" |
9db1d521 | 649 | [(set (reg 33) |
d3632d41 | 650 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 651 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 652 | (set (match_operand:HI 2 "register_operand" "=d,d") |
9db1d521 HP |
653 | (match_dup 0))] |
654 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 655 | "@ |
d40c829f UW |
656 | icm\t%2,3,%0 |
657 | icmy\t%2,3,%0" | |
d3632d41 | 658 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 659 | |
07893d4f | 660 | (define_insn "*tsthi_cconly" |
9db1d521 | 661 | [(set (reg 33) |
d3632d41 | 662 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 663 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 664 | (clobber (match_scratch:HI 2 "=d,d"))] |
9db1d521 | 665 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 666 | "@ |
d40c829f UW |
667 | icm\t%2,3,%0 |
668 | icmy\t%2,3,%0" | |
d3632d41 | 669 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 670 | |
3af97654 UW |
671 | (define_insn "*tstqiCCT" |
672 | [(set (reg 33) | |
d3632d41 | 673 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 674 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 675 | (set (match_operand:QI 2 "register_operand" "=d,d,0") |
3af97654 UW |
676 | (match_dup 0))] |
677 | "s390_match_ccmode(insn, CCTmode)" | |
678 | "@ | |
d40c829f UW |
679 | icm\t%2,1,%0 |
680 | icmy\t%2,1,%0 | |
681 | tml\t%0,255" | |
d3632d41 | 682 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
683 | |
684 | (define_insn "*tstqiCCT_cconly" | |
685 | [(set (reg 33) | |
d3632d41 | 686 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
687 | (match_operand:QI 1 "const0_operand" "")))] |
688 | "s390_match_ccmode(insn, CCTmode)" | |
689 | "@ | |
d40c829f UW |
690 | cli\t%0,0 |
691 | cliy\t%0,0 | |
692 | tml\t%0,255" | |
d3632d41 | 693 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 694 | |
07893d4f | 695 | (define_insn "*tstqi" |
9db1d521 | 696 | [(set (reg 33) |
d3632d41 | 697 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 698 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 699 | (set (match_operand:QI 2 "register_operand" "=d,d") |
07893d4f UW |
700 | (match_dup 0))] |
701 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 702 | "@ |
d40c829f UW |
703 | icm\t%2,1,%0 |
704 | icmy\t%2,1,%0" | |
d3632d41 | 705 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 706 | |
07893d4f | 707 | (define_insn "*tstqi_cconly" |
9db1d521 | 708 | [(set (reg 33) |
d3632d41 | 709 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 710 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 711 | (clobber (match_scratch:QI 2 "=d,d"))] |
07893d4f | 712 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 713 | "@ |
d40c829f UW |
714 | icm\t%2,1,%0 |
715 | icmy\t%2,1,%0" | |
d3632d41 UW |
716 | [(set_attr "op_type" "RS,RSY")]) |
717 | ||
9db1d521 | 718 | |
07893d4f | 719 | ; Compare (signed) instructions |
4023fb28 | 720 | |
07893d4f | 721 | (define_insn "*cmpdi_ccs_sign" |
4023fb28 | 722 | [(set (reg 33) |
07893d4f UW |
723 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
724 | (match_operand:DI 0 "register_operand" "d,d")))] | |
725 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 726 | "@ |
d40c829f UW |
727 | cgfr\t%0,%1 |
728 | cgf\t%0,%1" | |
d3632d41 | 729 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 730 | |
07893d4f | 731 | (define_insn "*cmpdi_ccs" |
4023fb28 | 732 | [(set (reg 33) |
07893d4f UW |
733 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
734 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
735 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
736 | "@ | |
d40c829f UW |
737 | cgr\t%0,%1 |
738 | cghi\t%0,%c1 | |
739 | cg\t%0,%1" | |
d3632d41 | 740 | [(set_attr "op_type" "RRE,RI,RXY")]) |
c7453384 | 741 | |
07893d4f UW |
742 | (define_insn "*cmpsi_ccs_sign" |
743 | [(set (reg 33) | |
d3632d41 UW |
744 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
745 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 746 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 747 | "@ |
d40c829f UW |
748 | ch\t%0,%1 |
749 | chy\t%0,%1" | |
d3632d41 | 750 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 751 | |
07893d4f | 752 | (define_insn "*cmpsi_ccs" |
9db1d521 | 753 | [(set (reg 33) |
d3632d41 UW |
754 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
755 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
9db1d521 | 756 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 757 | "@ |
d40c829f UW |
758 | cr\t%0,%1 |
759 | chi\t%0,%c1 | |
760 | c\t%0,%1 | |
761 | cy\t%0,%1" | |
d3632d41 | 762 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
c7453384 | 763 | |
07893d4f UW |
764 | |
765 | ; Compare (unsigned) instructions | |
9db1d521 | 766 | |
07893d4f | 767 | (define_insn "*cmpdi_ccu_zero" |
9db1d521 | 768 | [(set (reg 33) |
07893d4f UW |
769 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
770 | (match_operand:DI 0 "register_operand" "d,d")))] | |
771 | "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT" | |
772 | "@ | |
d40c829f UW |
773 | clgfr\t%0,%1 |
774 | clgf\t%0,%1" | |
d3632d41 | 775 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 776 | |
07893d4f | 777 | (define_insn "*cmpdi_ccu" |
9db1d521 | 778 | [(set (reg 33) |
07893d4f UW |
779 | (compare (match_operand:DI 0 "register_operand" "d,d") |
780 | (match_operand:DI 1 "general_operand" "d,m")))] | |
781 | "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" | |
782 | "@ | |
d40c829f UW |
783 | clgr\t%0,%1 |
784 | clg\t%0,%1" | |
d3632d41 | 785 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 786 | |
07893d4f | 787 | (define_insn "*cmpsi_ccu" |
9db1d521 | 788 | [(set (reg 33) |
d3632d41 UW |
789 | (compare (match_operand:SI 0 "register_operand" "d,d,d") |
790 | (match_operand:SI 1 "general_operand" "d,R,T")))] | |
07893d4f UW |
791 | "s390_match_ccmode(insn, CCUmode)" |
792 | "@ | |
d40c829f UW |
793 | clr\t%0,%1 |
794 | cl\t%0,%1 | |
795 | cly\t%0,%1" | |
d3632d41 | 796 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 797 | |
07893d4f | 798 | (define_insn "*cmphi_ccu" |
9db1d521 | 799 | [(set (reg 33) |
d3632d41 UW |
800 | (compare (match_operand:HI 0 "register_operand" "d,d") |
801 | (match_operand:HI 1 "s_imm_operand" "Q,S")))] | |
9db1d521 | 802 | "s390_match_ccmode(insn, CCUmode)" |
d3632d41 | 803 | "@ |
d40c829f UW |
804 | clm\t%0,3,%1 |
805 | clmy\t%0,3,%1" | |
d3632d41 | 806 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
807 | |
808 | (define_insn "*cmpqi_ccu" | |
809 | [(set (reg 33) | |
d3632d41 UW |
810 | (compare (match_operand:QI 0 "register_operand" "d,d") |
811 | (match_operand:QI 1 "s_imm_operand" "Q,S")))] | |
9db1d521 | 812 | "s390_match_ccmode(insn, CCUmode)" |
d3632d41 | 813 | "@ |
d40c829f UW |
814 | clm\t%0,1,%1 |
815 | clmy\t%0,1,%1" | |
d3632d41 | 816 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 817 | |
07893d4f | 818 | (define_insn "*cli" |
9db1d521 | 819 | [(set (reg 33) |
d3632d41 UW |
820 | (compare (match_operand:QI 0 "memory_operand" "Q,S") |
821 | (match_operand:QI 1 "immediate_operand" "n,n")))] | |
07893d4f | 822 | "s390_match_ccmode (insn, CCUmode)" |
d3632d41 | 823 | "@ |
d40c829f UW |
824 | cli\t%0,%b1 |
825 | cliy\t%0,%b1" | |
d3632d41 | 826 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 827 | |
07893d4f UW |
828 | (define_insn "*cmpdi_ccu_mem" |
829 | [(set (reg 33) | |
ccfc6cc8 UW |
830 | (compare (match_operand:DI 0 "s_operand" "Q") |
831 | (match_operand:DI 1 "s_imm_operand" "Q")))] | |
07893d4f | 832 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 833 | "clc\t%O0(8,%R0),%1" |
077dab3b | 834 | [(set_attr "op_type" "SS")]) |
07893d4f UW |
835 | |
836 | (define_insn "*cmpsi_ccu_mem" | |
837 | [(set (reg 33) | |
ccfc6cc8 UW |
838 | (compare (match_operand:SI 0 "s_operand" "Q") |
839 | (match_operand:SI 1 "s_imm_operand" "Q")))] | |
07893d4f | 840 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 841 | "clc\t%O0(4,%R0),%1" |
077dab3b | 842 | [(set_attr "op_type" "SS")]) |
07893d4f UW |
843 | |
844 | (define_insn "*cmphi_ccu_mem" | |
845 | [(set (reg 33) | |
ccfc6cc8 UW |
846 | (compare (match_operand:HI 0 "s_operand" "Q") |
847 | (match_operand:HI 1 "s_imm_operand" "Q")))] | |
07893d4f | 848 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 849 | "clc\t%O0(2,%R0),%1" |
077dab3b | 850 | [(set_attr "op_type" "SS")]) |
07893d4f | 851 | |
9db1d521 HP |
852 | (define_insn "*cmpqi_ccu_mem" |
853 | [(set (reg 33) | |
ccfc6cc8 UW |
854 | (compare (match_operand:QI 0 "s_operand" "Q") |
855 | (match_operand:QI 1 "s_imm_operand" "Q")))] | |
9db1d521 | 856 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 857 | "clc\t%O0(1,%R0),%1" |
077dab3b | 858 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
859 | |
860 | ||
861 | ; DF instructions | |
862 | ||
863 | (define_insn "*cmpdf_ccs_0" | |
864 | [(set (reg 33) | |
865 | (compare (match_operand:DF 0 "register_operand" "f") | |
866 | (match_operand:DF 1 "const0_operand" "")))] | |
867 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 868 | "ltdbr\t%0,%0" |
077dab3b HP |
869 | [(set_attr "op_type" "RRE") |
870 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
871 | |
872 | (define_insn "*cmpdf_ccs_0_ibm" | |
873 | [(set (reg 33) | |
874 | (compare (match_operand:DF 0 "register_operand" "f") | |
875 | (match_operand:DF 1 "const0_operand" "")))] | |
876 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 877 | "ltdr\t%0,%0" |
077dab3b HP |
878 | [(set_attr "op_type" "RR") |
879 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
880 | |
881 | (define_insn "*cmpdf_ccs" | |
882 | [(set (reg 33) | |
883 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 884 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
885 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
886 | "@ | |
d40c829f UW |
887 | cdbr\t%0,%1 |
888 | cdb\t%0,%1" | |
ce50cae8 | 889 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 890 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
891 | |
892 | (define_insn "*cmpdf_ccs_ibm" | |
893 | [(set (reg 33) | |
894 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 895 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
896 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
897 | "@ | |
d40c829f UW |
898 | cdr\t%0,%1 |
899 | cd\t%0,%1" | |
9db1d521 | 900 | [(set_attr "op_type" "RR,RX") |
077dab3b | 901 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
902 | |
903 | ||
904 | ; SF instructions | |
905 | ||
906 | (define_insn "*cmpsf_ccs_0" | |
907 | [(set (reg 33) | |
908 | (compare (match_operand:SF 0 "register_operand" "f") | |
909 | (match_operand:SF 1 "const0_operand" "")))] | |
910 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 911 | "ltebr\t%0,%0" |
077dab3b HP |
912 | [(set_attr "op_type" "RRE") |
913 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
914 | |
915 | (define_insn "*cmpsf_ccs_0_ibm" | |
916 | [(set (reg 33) | |
917 | (compare (match_operand:SF 0 "register_operand" "f") | |
918 | (match_operand:SF 1 "const0_operand" "")))] | |
919 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 920 | "lter\t%0,%0" |
077dab3b HP |
921 | [(set_attr "op_type" "RR") |
922 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
923 | |
924 | (define_insn "*cmpsf_ccs" | |
925 | [(set (reg 33) | |
926 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 927 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
928 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
929 | "@ | |
d40c829f UW |
930 | cebr\t%0,%1 |
931 | ceb\t%0,%1" | |
077dab3b HP |
932 | [(set_attr "op_type" "RRE,RXE") |
933 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
934 | |
935 | (define_insn "*cmpsf_ccs" | |
936 | [(set (reg 33) | |
937 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 938 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
939 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
940 | "@ | |
d40c829f UW |
941 | cer\t%0,%1 |
942 | ce\t%0,%1" | |
077dab3b HP |
943 | [(set_attr "op_type" "RR,RX") |
944 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
945 | |
946 | ||
947 | ;; | |
948 | ;;- Move instructions. | |
949 | ;; | |
950 | ||
951 | ; | |
952 | ; movti instruction pattern(s). | |
953 | ; | |
954 | ||
955 | (define_insn "movti" | |
d3632d41 UW |
956 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
957 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
9db1d521 | 958 | "TARGET_64BIT" |
4023fb28 | 959 | "@ |
d40c829f UW |
960 | lmg\t%0,%N0,%1 |
961 | stmg\t%1,%N1,%0 | |
4023fb28 | 962 | # |
9b7c75b9 | 963 | # |
d40c829f | 964 | mvc\t%O0(16,%R0),%1" |
d3632d41 | 965 | [(set_attr "op_type" "RSY,RSY,NN,NN,SS") |
fe03d631 | 966 | (set_attr "type" "lm,stm,*,*,cs")]) |
4023fb28 UW |
967 | |
968 | (define_split | |
969 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
970 | (match_operand:TI 1 "general_operand" ""))] | |
971 | "TARGET_64BIT && reload_completed | |
dc65c307 | 972 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
973 | [(set (match_dup 2) (match_dup 4)) |
974 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 975 | { |
dc65c307 UW |
976 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
977 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
978 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
979 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
980 | }) | |
981 | ||
982 | (define_split | |
983 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
984 | (match_operand:TI 1 "general_operand" ""))] | |
985 | "TARGET_64BIT && reload_completed | |
986 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
987 | [(set (match_dup 2) (match_dup 4)) | |
988 | (set (match_dup 3) (match_dup 5))] | |
989 | { | |
990 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
991 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
992 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
993 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
994 | }) | |
4023fb28 UW |
995 | |
996 | (define_split | |
997 | [(set (match_operand:TI 0 "register_operand" "") | |
998 | (match_operand:TI 1 "memory_operand" ""))] | |
999 | "TARGET_64BIT && reload_completed | |
1000 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 1001 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1002 | { |
1003 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
1004 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1005 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1006 | }) |
1007 | ||
1008 | (define_expand "reload_outti" | |
1009 | [(parallel [(match_operand:TI 0 "memory_operand" "") | |
1010 | (match_operand:TI 1 "register_operand" "d") | |
1011 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1012 | "TARGET_64BIT" | |
1013 | { | |
1014 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1015 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1016 | emit_move_insn (operands[0], operands[1]); | |
1017 | DONE; | |
1018 | }) | |
9db1d521 HP |
1019 | |
1020 | ; | |
1021 | ; movdi instruction pattern(s). | |
1022 | ; | |
1023 | ||
9db1d521 HP |
1024 | (define_expand "movdi" |
1025 | [(set (match_operand:DI 0 "general_operand" "") | |
1026 | (match_operand:DI 1 "general_operand" ""))] | |
1027 | "" | |
9db1d521 | 1028 | { |
fd3cd001 UW |
1029 | /* Handle symbolic constants. */ |
1030 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1031 | emit_symbolic_move (operands); | |
4023fb28 UW |
1032 | |
1033 | /* During and after reload, we need to force constants | |
1034 | to the literal pool ourselves, if necessary. */ | |
1035 | if ((reload_in_progress || reload_completed) | |
c7453384 | 1036 | && CONSTANT_P (operands[1]) |
4023fb28 | 1037 | && (!legitimate_reload_constant_p (operands[1]) |
8e509cf9 | 1038 | || FP_REG_P (operands[0]))) |
4023fb28 | 1039 | operands[1] = force_const_mem (DImode, operands[1]); |
10bbf137 | 1040 | }) |
9db1d521 | 1041 | |
4023fb28 UW |
1042 | (define_insn "*movdi_lhi" |
1043 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1044 | (match_operand:DI 1 "immediate_operand" "K"))] | |
1045 | "TARGET_64BIT | |
1046 | && GET_CODE (operands[1]) == CONST_INT | |
1047 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') | |
8e509cf9 | 1048 | && !FP_REG_P (operands[0])" |
d40c829f | 1049 | "lghi\t%0,%h1" |
077dab3b | 1050 | [(set_attr "op_type" "RI")]) |
4023fb28 UW |
1051 | |
1052 | (define_insn "*movdi_lli" | |
1053 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1054 | (match_operand:DI 1 "immediate_operand" "n"))] | |
1055 | "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0 | |
8e509cf9 | 1056 | && !FP_REG_P (operands[0])" |
4023fb28 UW |
1057 | { |
1058 | int part = s390_single_hi (operands[1], DImode, 0); | |
1059 | operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); | |
1060 | ||
1061 | switch (part) | |
1062 | { | |
d40c829f UW |
1063 | case 0: return "llihh\t%0,%x1"; |
1064 | case 1: return "llihl\t%0,%x1"; | |
1065 | case 2: return "llilh\t%0,%x1"; | |
1066 | case 3: return "llill\t%0,%x1"; | |
4023fb28 UW |
1067 | default: abort (); |
1068 | } | |
10bbf137 | 1069 | } |
077dab3b | 1070 | [(set_attr "op_type" "RI")]) |
4023fb28 | 1071 | |
d3632d41 UW |
1072 | (define_insn "*movdi_lay" |
1073 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1074 | (match_operand:DI 1 "address_operand" "p"))] | |
c7453384 | 1075 | "TARGET_64BIT |
d3632d41 UW |
1076 | && TARGET_LONG_DISPLACEMENT |
1077 | && GET_CODE (operands[1]) == CONST_INT | |
1078 | && !FP_REG_P (operands[0])" | |
d40c829f | 1079 | "lay\t%0,%a1" |
d3632d41 UW |
1080 | [(set_attr "op_type" "RXY") |
1081 | (set_attr "type" "la")]) | |
1082 | ||
4023fb28 UW |
1083 | (define_insn "*movdi_larl" |
1084 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1085 | (match_operand:DI 1 "larl_operand" "X"))] | |
1086 | "TARGET_64BIT | |
8e509cf9 | 1087 | && !FP_REG_P (operands[0])" |
d40c829f | 1088 | "larl\t%0,%1" |
4023fb28 | 1089 | [(set_attr "op_type" "RIL") |
077dab3b | 1090 | (set_attr "type" "larl")]) |
4023fb28 | 1091 | |
9db1d521 | 1092 | (define_insn "*movdi_64" |
d3632d41 UW |
1093 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!*f,!R,!T,?Q") |
1094 | (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))] | |
9db1d521 HP |
1095 | "TARGET_64BIT" |
1096 | "@ | |
d40c829f UW |
1097 | lgr\t%0,%1 |
1098 | lg\t%0,%1 | |
1099 | stg\t%1,%0 | |
1100 | ldr\t%0,%1 | |
1101 | ld\t%0,%1 | |
1102 | ldy\t%0,%1 | |
1103 | std\t%1,%0 | |
1104 | stdy\t%1,%0 | |
1105 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1106 | [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS") |
1107 | (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")]) | |
9db1d521 HP |
1108 | |
1109 | (define_insn "*movdi_31" | |
d3632d41 UW |
1110 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
1111 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
9db1d521 | 1112 | "!TARGET_64BIT" |
4023fb28 | 1113 | "@ |
d40c829f UW |
1114 | lm\t%0,%N0,%1 |
1115 | stm\t%1,%N1,%0 | |
4023fb28 UW |
1116 | # |
1117 | # | |
d40c829f UW |
1118 | ldr\t%0,%1 |
1119 | ld\t%0,%1 | |
1120 | ldy\t%0,%1 | |
1121 | std\t%1,%0 | |
1122 | stdy\t%1,%0 | |
1123 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1124 | [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS") |
1125 | (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")]) | |
4023fb28 UW |
1126 | |
1127 | (define_split | |
1128 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1129 | (match_operand:DI 1 "general_operand" ""))] | |
1130 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1131 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1132 | [(set (match_dup 2) (match_dup 4)) |
1133 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1134 | { |
dc65c307 UW |
1135 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1136 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1137 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1138 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1139 | }) | |
1140 | ||
1141 | (define_split | |
1142 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1143 | (match_operand:DI 1 "general_operand" ""))] | |
1144 | "!TARGET_64BIT && reload_completed | |
1145 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1146 | [(set (match_dup 2) (match_dup 4)) | |
1147 | (set (match_dup 3) (match_dup 5))] | |
1148 | { | |
1149 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1150 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1151 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1152 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1153 | }) | |
9db1d521 | 1154 | |
4023fb28 UW |
1155 | (define_split |
1156 | [(set (match_operand:DI 0 "register_operand" "") | |
1157 | (match_operand:DI 1 "memory_operand" ""))] | |
1158 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1159 | && !FP_REG_P (operands[0]) |
4023fb28 | 1160 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1161 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1162 | { |
1163 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1164 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1165 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1166 | }) |
1167 | ||
1168 | (define_expand "reload_outdi" | |
1169 | [(parallel [(match_operand:DI 0 "memory_operand" "") | |
1170 | (match_operand:DI 1 "register_operand" "d") | |
1171 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1172 | "!TARGET_64BIT" | |
1173 | { | |
1174 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1175 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1176 | emit_move_insn (operands[0], operands[1]); | |
1177 | DONE; | |
1178 | }) | |
9db1d521 | 1179 | |
84817c5d UW |
1180 | (define_peephole2 |
1181 | [(set (match_operand:DI 0 "register_operand" "") | |
1182 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1183 | "TARGET_64BIT | |
1184 | && !FP_REG_P (operands[0]) | |
1185 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1186 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1187 | && get_pool_mode (operands[1]) == DImode | |
1188 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1189 | [(set (match_dup 0) (match_dup 2))] | |
1190 | "operands[2] = get_pool_constant (operands[1]);") | |
1191 | ||
9db1d521 HP |
1192 | ; |
1193 | ; movsi instruction pattern(s). | |
1194 | ; | |
1195 | ||
9db1d521 HP |
1196 | (define_expand "movsi" |
1197 | [(set (match_operand:SI 0 "general_operand" "") | |
1198 | (match_operand:SI 1 "general_operand" ""))] | |
1199 | "" | |
9db1d521 | 1200 | { |
fd3cd001 UW |
1201 | /* Handle symbolic constants. */ |
1202 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1203 | emit_symbolic_move (operands); | |
ba956982 | 1204 | |
c7453384 EC |
1205 | /* expr.c tries to load an effective address using |
1206 | force_reg. This fails because we don't have a | |
ba956982 UW |
1207 | generic load_address pattern. Convert the move |
1208 | to a proper arithmetic operation instead, unless | |
1209 | it is guaranteed to be OK. */ | |
1210 | if (GET_CODE (operands[1]) == PLUS | |
1211 | && !legitimate_la_operand_p (operands[1])) | |
1212 | { | |
1213 | operands[1] = force_operand (operands[1], operands[0]); | |
1214 | if (operands[1] == operands[0]) | |
1215 | DONE; | |
1216 | } | |
4023fb28 UW |
1217 | |
1218 | /* During and after reload, we need to force constants | |
1219 | to the literal pool ourselves, if necessary. */ | |
1220 | if ((reload_in_progress || reload_completed) | |
c7453384 | 1221 | && CONSTANT_P (operands[1]) |
4023fb28 | 1222 | && (!legitimate_reload_constant_p (operands[1]) |
8e509cf9 | 1223 | || FP_REG_P (operands[0]))) |
4023fb28 | 1224 | operands[1] = force_const_mem (SImode, operands[1]); |
10bbf137 | 1225 | }) |
9db1d521 | 1226 | |
4023fb28 UW |
1227 | (define_insn "*movsi_lhi" |
1228 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1229 | (match_operand:SI 1 "immediate_operand" "K"))] | |
1230 | "GET_CODE (operands[1]) == CONST_INT | |
1231 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') | |
8e509cf9 | 1232 | && !FP_REG_P (operands[0])" |
d40c829f | 1233 | "lhi\t%0,%h1" |
4023fb28 UW |
1234 | [(set_attr "op_type" "RI")]) |
1235 | ||
1236 | (define_insn "*movsi_lli" | |
1237 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1238 | (match_operand:SI 1 "immediate_operand" "n"))] | |
1239 | "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0 | |
8e509cf9 | 1240 | && !FP_REG_P (operands[0])" |
4023fb28 UW |
1241 | { |
1242 | int part = s390_single_hi (operands[1], SImode, 0); | |
1243 | operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); | |
1244 | ||
1245 | switch (part) | |
1246 | { | |
d40c829f UW |
1247 | case 0: return "llilh\t%0,%x1"; |
1248 | case 1: return "llill\t%0,%x1"; | |
4023fb28 UW |
1249 | default: abort (); |
1250 | } | |
10bbf137 | 1251 | } |
4023fb28 UW |
1252 | [(set_attr "op_type" "RI")]) |
1253 | ||
d3632d41 UW |
1254 | (define_insn "*movsi_lay" |
1255 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1256 | (match_operand:SI 1 "address_operand" "p"))] | |
1257 | "TARGET_LONG_DISPLACEMENT | |
1258 | && GET_CODE (operands[1]) == CONST_INT | |
1259 | && !FP_REG_P (operands[0])" | |
d40c829f | 1260 | "lay\t%0,%a1" |
d3632d41 UW |
1261 | [(set_attr "op_type" "RXY") |
1262 | (set_attr "type" "la")]) | |
1263 | ||
9db1d521 | 1264 | (define_insn "*movsi" |
d3632d41 UW |
1265 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") |
1266 | (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))] | |
9db1d521 HP |
1267 | "" |
1268 | "@ | |
d40c829f UW |
1269 | lr\t%0,%1 |
1270 | l\t%0,%1 | |
1271 | ly\t%0,%1 | |
1272 | st\t%1,%0 | |
1273 | sty\t%1,%0 | |
1274 | ler\t%0,%1 | |
1275 | le\t%0,%1 | |
1276 | ley\t%0,%1 | |
1277 | ste\t%1,%0 | |
1278 | stey\t%1,%0 | |
1279 | mvc\t%O0(4,%R0),%1" | |
d3632d41 UW |
1280 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1281 | (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")]) | |
9db1d521 | 1282 | |
84817c5d UW |
1283 | (define_peephole2 |
1284 | [(set (match_operand:SI 0 "register_operand" "") | |
1285 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1286 | "!FP_REG_P (operands[0]) | |
1287 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1288 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1289 | && get_pool_mode (operands[1]) == SImode | |
1290 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1291 | [(set (match_dup 0) (match_dup 2))] | |
1292 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 HP |
1293 | |
1294 | ; | |
1295 | ; movhi instruction pattern(s). | |
1296 | ; | |
1297 | ||
1298 | (define_insn "movhi" | |
d3632d41 UW |
1299 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1300 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1301 | "" |
1302 | "@ | |
d40c829f UW |
1303 | lr\t%0,%1 |
1304 | lhi\t%0,%h1 | |
1305 | lh\t%0,%1 | |
1306 | lhy\t%0,%1 | |
1307 | sth\t%1,%0 | |
1308 | sthy\t%1,%0 | |
1309 | mvc\t%O0(2,%R0),%1" | |
d3632d41 UW |
1310 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
1311 | (set_attr "type" "lr,*,*,*,store,store,cs")]) | |
9db1d521 | 1312 | |
84817c5d UW |
1313 | (define_peephole2 |
1314 | [(set (match_operand:HI 0 "register_operand" "") | |
1315 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1316 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1317 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1318 | && get_pool_mode (operands[1]) == HImode | |
1319 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1320 | [(set (match_dup 0) (match_dup 2))] | |
1321 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1322 | |
9db1d521 HP |
1323 | ; |
1324 | ; movqi instruction pattern(s). | |
1325 | ; | |
1326 | ||
1327 | (define_insn "movqi_64" | |
d3632d41 UW |
1328 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q") |
1329 | (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))] | |
9db1d521 HP |
1330 | "TARGET_64BIT" |
1331 | "@ | |
d40c829f UW |
1332 | lr\t%0,%1 |
1333 | lhi\t%0,%b1 | |
1334 | llgc\t%0,%1 | |
1335 | stc\t%1,%0 | |
1336 | stcy\t%1,%0 | |
1337 | mvi\t%0,%b1 | |
1338 | mviy\t%0,%b1 | |
1339 | mvc\t%O0(1,%R0),%1" | |
d3632d41 UW |
1340 | [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS") |
1341 | (set_attr "type" "lr,*,*,store,store,store,store,cs")]) | |
4023fb28 | 1342 | |
9db1d521 | 1343 | (define_insn "movqi" |
d3632d41 UW |
1344 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1345 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1346 | "" |
1347 | "@ | |
d40c829f UW |
1348 | lr\t%0,%1 |
1349 | lhi\t%0,%b1 | |
1350 | ic\t%0,%1 | |
1351 | icy\t%0,%1 | |
1352 | stc\t%1,%0 | |
1353 | stcy\t%1,%0 | |
1354 | mvi\t%0,%b1 | |
1355 | mviy\t%0,%b1 | |
1356 | mvc\t%O0(1,%R0),%1" | |
d3632d41 UW |
1357 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1358 | (set_attr "type" "lr,*,*,*,store,store,store,store,cs")]) | |
9db1d521 | 1359 | |
84817c5d UW |
1360 | (define_peephole2 |
1361 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1362 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1363 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1364 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1365 | && get_pool_mode (operands[1]) == QImode | |
1366 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1367 | [(set (match_dup 0) (match_dup 2))] | |
1368 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1369 | |
9db1d521 | 1370 | ; |
05b9aaaa | 1371 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1372 | ; |
1373 | ||
1374 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1375 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1376 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1377 | "" |
d3632d41 | 1378 | "@ |
d40c829f UW |
1379 | ic\t%0,%1 |
1380 | icy\t%0,%1" | |
d3632d41 | 1381 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1382 | |
1383 | ; | |
1384 | ; movstricthi instruction pattern(s). | |
1385 | ; | |
1386 | ||
1387 | (define_insn "*movstricthi" | |
d3632d41 UW |
1388 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
1389 | (match_operand:HI 1 "s_imm_operand" "Q,S")) | |
9db1d521 HP |
1390 | (clobber (reg:CC 33))] |
1391 | "" | |
d3632d41 | 1392 | "@ |
d40c829f UW |
1393 | icm\t%0,3,%1 |
1394 | icmy\t%0,3,%1" | |
d3632d41 | 1395 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1396 | |
1397 | ; | |
1398 | ; movstrictsi instruction pattern(s). | |
1399 | ; | |
1400 | ||
05b9aaaa | 1401 | (define_insn "movstrictsi" |
d3632d41 UW |
1402 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d")) |
1403 | (match_operand:SI 1 "general_operand" "d,R,T"))] | |
9db1d521 HP |
1404 | "TARGET_64BIT" |
1405 | "@ | |
d40c829f UW |
1406 | lr\t%0,%1 |
1407 | l\t%0,%1 | |
1408 | ly\t%0,%1" | |
d3632d41 UW |
1409 | [(set_attr "op_type" "RR,RX,RXY") |
1410 | (set_attr "type" "lr,load,load")]) | |
9db1d521 HP |
1411 | |
1412 | ; | |
1413 | ; movdf instruction pattern(s). | |
1414 | ; | |
1415 | ||
1416 | (define_expand "movdf" | |
1417 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1418 | (match_operand:DF 1 "general_operand" ""))] | |
1419 | "" | |
9db1d521 | 1420 | { |
4023fb28 UW |
1421 | /* During and after reload, we need to force constants |
1422 | to the literal pool ourselves, if necessary. */ | |
1423 | if ((reload_in_progress || reload_completed) | |
1424 | && CONSTANT_P (operands[1])) | |
1425 | operands[1] = force_const_mem (DFmode, operands[1]); | |
10bbf137 | 1426 | }) |
9db1d521 HP |
1427 | |
1428 | (define_insn "*movdf_64" | |
d3632d41 UW |
1429 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") |
1430 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1431 | "TARGET_64BIT" |
9db1d521 | 1432 | "@ |
d40c829f UW |
1433 | ldr\t%0,%1 |
1434 | ld\t%0,%1 | |
1435 | ldy\t%0,%1 | |
1436 | std\t%1,%0 | |
1437 | stdy\t%1,%0 | |
1438 | lgr\t%0,%1 | |
1439 | lg\t%0,%1 | |
1440 | stg\t%1,%0 | |
1441 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1442 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
1443 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")]) | |
9db1d521 HP |
1444 | |
1445 | (define_insn "*movdf_31" | |
d3632d41 UW |
1446 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") |
1447 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] | |
4023fb28 | 1448 | "!TARGET_64BIT" |
9db1d521 | 1449 | "@ |
d40c829f UW |
1450 | ldr\t%0,%1 |
1451 | ld\t%0,%1 | |
1452 | ldy\t%0,%1 | |
1453 | std\t%1,%0 | |
1454 | stdy\t%1,%0 | |
1455 | lm\t%0,%N0,%1 | |
1456 | stm\t%1,%N1,%0 | |
4023fb28 | 1457 | # |
9b7c75b9 | 1458 | # |
d40c829f | 1459 | mvc\t%O0(8,%R0),%1" |
d3632d41 UW |
1460 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS") |
1461 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")]) | |
4023fb28 UW |
1462 | |
1463 | (define_split | |
1464 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1465 | (match_operand:DF 1 "general_operand" ""))] | |
1466 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1467 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1468 | [(set (match_dup 2) (match_dup 4)) |
1469 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1470 | { |
dc65c307 UW |
1471 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1472 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1473 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1474 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1475 | }) | |
1476 | ||
1477 | (define_split | |
1478 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1479 | (match_operand:DF 1 "general_operand" ""))] | |
1480 | "!TARGET_64BIT && reload_completed | |
1481 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1482 | [(set (match_dup 2) (match_dup 4)) | |
1483 | (set (match_dup 3) (match_dup 5))] | |
1484 | { | |
1485 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1486 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1487 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1488 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1489 | }) | |
9db1d521 | 1490 | |
4023fb28 UW |
1491 | (define_split |
1492 | [(set (match_operand:DF 0 "register_operand" "") | |
1493 | (match_operand:DF 1 "memory_operand" ""))] | |
1494 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1495 | && !FP_REG_P (operands[0]) |
4023fb28 | 1496 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1497 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1498 | { |
1499 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1500 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1501 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1502 | }) |
1503 | ||
1504 | (define_expand "reload_outdf" | |
1505 | [(parallel [(match_operand:DF 0 "memory_operand" "") | |
1506 | (match_operand:DF 1 "register_operand" "d") | |
1507 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1508 | "!TARGET_64BIT" | |
1509 | { | |
1510 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1511 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1512 | emit_move_insn (operands[0], operands[1]); | |
1513 | DONE; | |
1514 | }) | |
9db1d521 HP |
1515 | |
1516 | ; | |
1517 | ; movsf instruction pattern(s). | |
1518 | ; | |
1519 | ||
1520 | (define_expand "movsf" | |
1521 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
1522 | (match_operand:SF 1 "general_operand" ""))] | |
1523 | "" | |
9db1d521 | 1524 | { |
4023fb28 UW |
1525 | /* During and after reload, we need to force constants |
1526 | to the literal pool ourselves, if necessary. */ | |
1527 | if ((reload_in_progress || reload_completed) | |
1528 | && CONSTANT_P (operands[1])) | |
1529 | operands[1] = force_const_mem (SFmode, operands[1]); | |
10bbf137 | 1530 | }) |
9db1d521 | 1531 | |
4023fb28 | 1532 | (define_insn "*movsf" |
d3632d41 UW |
1533 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") |
1534 | (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1535 | "" |
9db1d521 | 1536 | "@ |
d40c829f UW |
1537 | ler\t%0,%1 |
1538 | le\t%0,%1 | |
1539 | ley\t%0,%1 | |
1540 | ste\t%1,%0 | |
1541 | stey\t%1,%0 | |
1542 | lr\t%0,%1 | |
1543 | l\t%0,%1 | |
1544 | ly\t%0,%1 | |
1545 | st\t%1,%0 | |
1546 | sty\t%1,%0 | |
1547 | mvc\t%O0(4,%R0),%1" | |
d3632d41 UW |
1548 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1549 | (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")]) | |
4023fb28 | 1550 | |
9db1d521 HP |
1551 | ; |
1552 | ; load_multiple pattern(s). | |
1553 | ; | |
1554 | ||
1555 | (define_expand "load_multiple" | |
1556 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1557 | (match_operand 1 "" "")) | |
1558 | (use (match_operand 2 "" ""))])] | |
1559 | "" | |
9db1d521 HP |
1560 | { |
1561 | int regno; | |
1562 | int count; | |
1563 | rtx from; | |
4023fb28 | 1564 | int i, off; |
9db1d521 HP |
1565 | |
1566 | /* Support only loading a constant number of fixed-point registers from | |
1567 | memory and only bother with this if more than two */ | |
1568 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1569 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1570 | || INTVAL (operands[2]) > 16 |
1571 | || GET_CODE (operands[1]) != MEM | |
1572 | || GET_CODE (operands[0]) != REG | |
1573 | || REGNO (operands[0]) >= 16) | |
1574 | FAIL; | |
1575 | ||
1576 | count = INTVAL (operands[2]); | |
1577 | regno = REGNO (operands[0]); | |
1578 | ||
1579 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1580 | if (no_new_pseudos) |
1581 | { | |
1582 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1583 | { | |
1584 | from = XEXP (operands[1], 0); | |
1585 | off = 0; | |
1586 | } | |
1587 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1588 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1589 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1590 | { | |
1591 | from = XEXP (XEXP (operands[1], 0), 0); | |
1592 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1593 | } | |
1594 | else | |
1595 | FAIL; | |
1596 | ||
1597 | if (from == frame_pointer_rtx || from == arg_pointer_rtx) | |
1598 | FAIL; | |
1599 | } | |
1600 | else | |
1601 | { | |
1602 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1603 | off = 0; | |
1604 | } | |
9db1d521 HP |
1605 | |
1606 | for (i = 0; i < count; i++) | |
1607 | XVECEXP (operands[3], 0, i) | |
1608 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i), | |
1609 | change_address (operands[1], Pmode, | |
4023fb28 UW |
1610 | plus_constant (from, |
1611 | off + i * UNITS_PER_WORD))); | |
10bbf137 | 1612 | }) |
9db1d521 HP |
1613 | |
1614 | (define_insn "*load_multiple_di" | |
1615 | [(match_parallel 0 "load_multiple_operation" | |
1616 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1617 | (match_operand:DI 2 "s_operand" "QS"))])] |
9db1d521 | 1618 | "" |
9db1d521 HP |
1619 | { |
1620 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1621 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
d40c829f | 1622 | return "lmg\t%1,%0,%2"; |
10bbf137 | 1623 | } |
d3632d41 | 1624 | [(set_attr "op_type" "RSY") |
4023fb28 | 1625 | (set_attr "type" "lm")]) |
9db1d521 HP |
1626 | |
1627 | (define_insn "*load_multiple_si" | |
1628 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1629 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1630 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
9db1d521 | 1631 | "" |
9db1d521 HP |
1632 | { |
1633 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1634 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
d40c829f | 1635 | return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2"; |
10bbf137 | 1636 | } |
d3632d41 | 1637 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1638 | (set_attr "type" "lm")]) |
9db1d521 HP |
1639 | |
1640 | ; | |
c7453384 | 1641 | ; store multiple pattern(s). |
9db1d521 HP |
1642 | ; |
1643 | ||
1644 | (define_expand "store_multiple" | |
1645 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1646 | (match_operand 1 "" "")) | |
1647 | (use (match_operand 2 "" ""))])] | |
1648 | "" | |
9db1d521 HP |
1649 | { |
1650 | int regno; | |
1651 | int count; | |
1652 | rtx to; | |
4023fb28 | 1653 | int i, off; |
9db1d521 HP |
1654 | |
1655 | /* Support only storing a constant number of fixed-point registers to | |
1656 | memory and only bother with this if more than two. */ | |
1657 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1658 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1659 | || INTVAL (operands[2]) > 16 |
1660 | || GET_CODE (operands[0]) != MEM | |
1661 | || GET_CODE (operands[1]) != REG | |
1662 | || REGNO (operands[1]) >= 16) | |
1663 | FAIL; | |
1664 | ||
1665 | count = INTVAL (operands[2]); | |
1666 | regno = REGNO (operands[1]); | |
1667 | ||
1668 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1669 | |
1670 | if (no_new_pseudos) | |
1671 | { | |
1672 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1673 | { | |
1674 | to = XEXP (operands[0], 0); | |
1675 | off = 0; | |
1676 | } | |
1677 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1678 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1679 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1680 | { | |
1681 | to = XEXP (XEXP (operands[0], 0), 0); | |
1682 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1683 | } | |
1684 | else | |
1685 | FAIL; | |
1686 | ||
1687 | if (to == frame_pointer_rtx || to == arg_pointer_rtx) | |
1688 | FAIL; | |
1689 | } | |
c7453384 | 1690 | else |
4023fb28 UW |
1691 | { |
1692 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1693 | off = 0; | |
1694 | } | |
9db1d521 HP |
1695 | |
1696 | for (i = 0; i < count; i++) | |
1697 | XVECEXP (operands[3], 0, i) | |
1698 | = gen_rtx_SET (VOIDmode, | |
1699 | change_address (operands[0], Pmode, | |
4023fb28 UW |
1700 | plus_constant (to, |
1701 | off + i * UNITS_PER_WORD)), | |
9db1d521 | 1702 | gen_rtx_REG (Pmode, regno + i)); |
10bbf137 | 1703 | }) |
9db1d521 HP |
1704 | |
1705 | (define_insn "*store_multiple_di" | |
1706 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1707 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 HP |
1708 | (match_operand:DI 2 "register_operand" "r"))])] |
1709 | "" | |
9db1d521 HP |
1710 | { |
1711 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1712 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
d40c829f | 1713 | return "stmg\t%2,%0,%1"; |
10bbf137 | 1714 | } |
d3632d41 | 1715 | [(set_attr "op_type" "RSY") |
4023fb28 | 1716 | (set_attr "type" "stm")]) |
9db1d521 HP |
1717 | |
1718 | ||
1719 | (define_insn "*store_multiple_si" | |
1720 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1721 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1722 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
9db1d521 | 1723 | "" |
9db1d521 HP |
1724 | { |
1725 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1726 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
d40c829f | 1727 | return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1"; |
10bbf137 | 1728 | } |
d3632d41 | 1729 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1730 | (set_attr "type" "stm")]) |
9db1d521 HP |
1731 | |
1732 | ;; | |
1733 | ;; String instructions. | |
1734 | ;; | |
1735 | ||
1736 | ; | |
a41c6c53 | 1737 | ; movstrM instruction pattern(s). |
9db1d521 HP |
1738 | ; |
1739 | ||
1740 | (define_expand "movstrdi" | |
a41c6c53 UW |
1741 | [(set (match_operand:BLK 0 "memory_operand" "") |
1742 | (match_operand:BLK 1 "memory_operand" "")) | |
1743 | (use (match_operand:DI 2 "general_operand" "")) | |
1744 | (match_operand 3 "" "")] | |
1745 | "TARGET_64BIT" | |
1746 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
9db1d521 HP |
1747 | |
1748 | (define_expand "movstrsi" | |
a41c6c53 UW |
1749 | [(set (match_operand:BLK 0 "memory_operand" "") |
1750 | (match_operand:BLK 1 "memory_operand" "")) | |
1751 | (use (match_operand:SI 2 "general_operand" "")) | |
1752 | (match_operand 3 "" "")] | |
1753 | "" | |
1754 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
9db1d521 | 1755 | |
ecbe845e UW |
1756 | ; Move a block that is up to 256 bytes in length. |
1757 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1758 | |
a41c6c53 UW |
1759 | (define_insn "movstr_short_64" |
1760 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1761 | (match_operand:BLK 1 "memory_operand" "Q,Q")) | |
ecbe845e UW |
1762 | (use (match_operand:DI 2 "nonmemory_operand" "n,a")) |
1763 | (clobber (match_scratch:DI 3 "=X,&a"))] | |
1764 | "TARGET_64BIT" | |
ecbe845e UW |
1765 | { |
1766 | switch (which_alternative) | |
1767 | { | |
1768 | case 0: | |
d40c829f | 1769 | return "mvc\t%O0(%b2+1,%R0),%1"; |
ecbe845e UW |
1770 | |
1771 | case 1: | |
d40c829f UW |
1772 | output_asm_insn ("bras\t%3,.+10", operands); |
1773 | output_asm_insn ("mvc\t%O0(1,%R0),%1", operands); | |
1774 | return "ex\t%2,0(%3)"; | |
ecbe845e UW |
1775 | |
1776 | default: | |
1777 | abort (); | |
1778 | } | |
10bbf137 | 1779 | } |
ecbe845e | 1780 | [(set_attr "op_type" "SS,NN") |
a41c6c53 | 1781 | (set_attr "type" "cs,cs") |
077dab3b | 1782 | (set_attr "atype" "*,agen") |
ecbe845e UW |
1783 | (set_attr "length" "*,14")]) |
1784 | ||
a41c6c53 UW |
1785 | (define_insn "movstr_short_31" |
1786 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1787 | (match_operand:BLK 1 "memory_operand" "Q,Q")) | |
ecbe845e UW |
1788 | (use (match_operand:SI 2 "nonmemory_operand" "n,a")) |
1789 | (clobber (match_scratch:SI 3 "=X,&a"))] | |
1790 | "!TARGET_64BIT" | |
ecbe845e UW |
1791 | { |
1792 | switch (which_alternative) | |
1793 | { | |
1794 | case 0: | |
d40c829f | 1795 | return "mvc\t%O0(%b2+1,%R0),%1"; |
ecbe845e UW |
1796 | |
1797 | case 1: | |
d40c829f UW |
1798 | output_asm_insn ("bras\t%3,.+10", operands); |
1799 | output_asm_insn ("mvc\t%O0(1,%R0),%1", operands); | |
1800 | return "ex\t%2,0(%3)"; | |
9db1d521 | 1801 | |
ecbe845e UW |
1802 | default: |
1803 | abort (); | |
1804 | } | |
10bbf137 | 1805 | } |
ecbe845e | 1806 | [(set_attr "op_type" "SS,NN") |
a41c6c53 | 1807 | (set_attr "type" "cs,cs") |
077dab3b | 1808 | (set_attr "atype" "*,agen") |
ecbe845e | 1809 | (set_attr "length" "*,14")]) |
9db1d521 | 1810 | |
a41c6c53 | 1811 | ; Move a block of arbitrary length. |
9db1d521 | 1812 | |
a41c6c53 | 1813 | (define_insn "movstr_long_64" |
9f37ccb1 UW |
1814 | [(set (match_operand:TI 0 "register_operand" "=d") |
1815 | (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0") | |
1816 | (lshiftrt:TI (match_dup 2) (const_int 64))) | |
1817 | (const_int 64))) | |
1818 | (set (match_operand:TI 1 "register_operand" "=d") | |
1819 | (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1") | |
1820 | (lshiftrt:TI (match_dup 3) (const_int 64))) | |
1821 | (const_int 64))) | |
1822 | (set (mem:BLK (subreg:DI (match_dup 2) 0)) | |
1823 | (mem:BLK (subreg:DI (match_dup 3) 0))) | |
9db1d521 | 1824 | (clobber (reg:CC 33))] |
9f37ccb1 | 1825 | "TARGET_64BIT" |
d40c829f | 1826 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 1827 | [(set_attr "op_type" "NN") |
a41c6c53 | 1828 | (set_attr "type" "vs") |
9db1d521 HP |
1829 | (set_attr "length" "8")]) |
1830 | ||
a41c6c53 | 1831 | (define_insn "movstr_long_31" |
9f37ccb1 UW |
1832 | [(set (match_operand:DI 0 "register_operand" "=d") |
1833 | (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0") | |
1834 | (lshiftrt:DI (match_dup 2) (const_int 32))) | |
1835 | (const_int 32))) | |
1836 | (set (match_operand:DI 1 "register_operand" "=d") | |
1837 | (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1") | |
1838 | (lshiftrt:DI (match_dup 3) (const_int 32))) | |
1839 | (const_int 32))) | |
1840 | (set (mem:BLK (subreg:SI (match_dup 2) 0)) | |
1841 | (mem:BLK (subreg:SI (match_dup 3) 0))) | |
9db1d521 | 1842 | (clobber (reg:CC 33))] |
9f37ccb1 | 1843 | "!TARGET_64BIT" |
d40c829f | 1844 | "mvcle\t%0,%1,0\;jo\t.-4" |
a41c6c53 UW |
1845 | [(set_attr "op_type" "NN") |
1846 | (set_attr "type" "vs") | |
a41c6c53 | 1847 | (set_attr "length" "8")]) |
9db1d521 HP |
1848 | |
1849 | ; | |
a41c6c53 | 1850 | ; clrstrM instruction pattern(s). |
9db1d521 HP |
1851 | ; |
1852 | ||
1853 | (define_expand "clrstrdi" | |
a41c6c53 | 1854 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
1855 | (const_int 0)) |
1856 | (use (match_operand:DI 1 "general_operand" "")) | |
1857 | (match_operand 2 "" "")] | |
1858 | "TARGET_64BIT" | |
a41c6c53 | 1859 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") |
9db1d521 HP |
1860 | |
1861 | (define_expand "clrstrsi" | |
a41c6c53 | 1862 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
1863 | (const_int 0)) |
1864 | (use (match_operand:SI 1 "general_operand" "")) | |
1865 | (match_operand 2 "" "")] | |
a41c6c53 UW |
1866 | "" |
1867 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") | |
9db1d521 | 1868 | |
a41c6c53 UW |
1869 | ; Clear a block that is up to 256 bytes in length. |
1870 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1871 | |
a41c6c53 UW |
1872 | (define_insn "clrstr_short_64" |
1873 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1874 | (const_int 0)) | |
1875 | (use (match_operand:DI 1 "nonmemory_operand" "n,a")) | |
1876 | (clobber (match_scratch:DI 2 "=X,&a")) | |
1877 | (clobber (reg:CC 33))] | |
1878 | "TARGET_64BIT" | |
a41c6c53 UW |
1879 | { |
1880 | switch (which_alternative) | |
1881 | { | |
1882 | case 0: | |
d40c829f | 1883 | return "xc\t%O0(%b1+1,%R0),%0"; |
9db1d521 | 1884 | |
a41c6c53 | 1885 | case 1: |
d40c829f UW |
1886 | output_asm_insn ("bras\t%2,.+10", operands); |
1887 | output_asm_insn ("xc\t%O0(1,%R0),%0", operands); | |
1888 | return "ex\t%1,0(%2)"; | |
9db1d521 | 1889 | |
a41c6c53 UW |
1890 | default: |
1891 | abort (); | |
1892 | } | |
10bbf137 | 1893 | } |
a41c6c53 UW |
1894 | [(set_attr "op_type" "SS,NN") |
1895 | (set_attr "type" "cs,cs") | |
077dab3b | 1896 | (set_attr "atype" "*,agen") |
a41c6c53 | 1897 | (set_attr "length" "*,14")]) |
9db1d521 | 1898 | |
a41c6c53 UW |
1899 | (define_insn "clrstr_short_31" |
1900 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
9db1d521 | 1901 | (const_int 0)) |
a41c6c53 UW |
1902 | (use (match_operand:SI 1 "nonmemory_operand" "n,a")) |
1903 | (clobber (match_scratch:SI 2 "=X,&a")) | |
9db1d521 | 1904 | (clobber (reg:CC 33))] |
a41c6c53 | 1905 | "!TARGET_64BIT" |
a41c6c53 UW |
1906 | { |
1907 | switch (which_alternative) | |
1908 | { | |
1909 | case 0: | |
d40c829f | 1910 | return "xc\t%O0(%b1+1,%R0),%0"; |
9db1d521 | 1911 | |
a41c6c53 | 1912 | case 1: |
d40c829f UW |
1913 | output_asm_insn ("bras\t%2,.+10", operands); |
1914 | output_asm_insn ("xc\t%O0(1,%R0),%0", operands); | |
1915 | return "ex\t%1,0(%2)"; | |
9db1d521 | 1916 | |
a41c6c53 UW |
1917 | default: |
1918 | abort (); | |
1919 | } | |
10bbf137 | 1920 | } |
a41c6c53 UW |
1921 | [(set_attr "op_type" "SS,NN") |
1922 | (set_attr "type" "cs,cs") | |
077dab3b | 1923 | (set_attr "atype" "*,agen") |
a41c6c53 UW |
1924 | (set_attr "length" "*,14")]) |
1925 | ||
1926 | ; Clear a block of arbitrary length. | |
1927 | ||
1928 | (define_insn "clrstr_long_64" | |
9f37ccb1 UW |
1929 | [(set (match_operand:TI 0 "register_operand" "=d") |
1930 | (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0") | |
1931 | (lshiftrt:TI (match_dup 2) (const_int 64))) | |
1932 | (const_int 64))) | |
1933 | (set (mem:BLK (subreg:DI (match_dup 2) 0)) | |
9db1d521 | 1934 | (const_int 0)) |
9f37ccb1 | 1935 | (use (match_operand:TI 1 "register_operand" "d")) |
9db1d521 HP |
1936 | (clobber (reg:CC 33))] |
1937 | "TARGET_64BIT" | |
d40c829f | 1938 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 1939 | [(set_attr "op_type" "NN") |
4023fb28 | 1940 | (set_attr "type" "vs") |
9db1d521 HP |
1941 | (set_attr "length" "8")]) |
1942 | ||
a41c6c53 | 1943 | (define_insn "clrstr_long_31" |
9f37ccb1 UW |
1944 | [(set (match_operand:DI 0 "register_operand" "=d") |
1945 | (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0") | |
1946 | (lshiftrt:DI (match_dup 2) (const_int 32))) | |
1947 | (const_int 32))) | |
1948 | (set (mem:BLK (subreg:SI (match_dup 2) 0)) | |
9db1d521 | 1949 | (const_int 0)) |
9f37ccb1 | 1950 | (use (match_operand:DI 1 "register_operand" "d")) |
9db1d521 HP |
1951 | (clobber (reg:CC 33))] |
1952 | "!TARGET_64BIT" | |
d40c829f | 1953 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 1954 | [(set_attr "op_type" "NN") |
4023fb28 | 1955 | (set_attr "type" "vs") |
9db1d521 HP |
1956 | (set_attr "length" "8")]) |
1957 | ||
1958 | ; | |
358b8f01 | 1959 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
1960 | ; |
1961 | ||
358b8f01 | 1962 | (define_expand "cmpmemdi" |
a41c6c53 UW |
1963 | [(set (match_operand:DI 0 "register_operand" "") |
1964 | (compare:DI (match_operand:BLK 1 "memory_operand" "") | |
1965 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
1966 | (use (match_operand:DI 3 "general_operand" "")) | |
1967 | (use (match_operand:DI 4 "" ""))] | |
1968 | "TARGET_64BIT" | |
c7453384 | 1969 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 1970 | operands[2], operands[3]); DONE;") |
9db1d521 | 1971 | |
358b8f01 | 1972 | (define_expand "cmpmemsi" |
a41c6c53 UW |
1973 | [(set (match_operand:SI 0 "register_operand" "") |
1974 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
1975 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
1976 | (use (match_operand:SI 3 "general_operand" "")) | |
1977 | (use (match_operand:SI 4 "" ""))] | |
1978 | "" | |
c7453384 | 1979 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 1980 | operands[2], operands[3]); DONE;") |
9db1d521 | 1981 | |
a41c6c53 UW |
1982 | ; Compare a block that is up to 256 bytes in length. |
1983 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1984 | |
358b8f01 | 1985 | (define_insn "cmpmem_short_64" |
a41c6c53 UW |
1986 | [(set (reg:CCS 33) |
1987 | (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
1988 | (match_operand:BLK 1 "memory_operand" "Q,Q"))) | |
1989 | (use (match_operand:DI 2 "nonmemory_operand" "n,a")) | |
1990 | (clobber (match_scratch:DI 3 "=X,&a"))] | |
1991 | "TARGET_64BIT" | |
a41c6c53 UW |
1992 | { |
1993 | switch (which_alternative) | |
9db1d521 | 1994 | { |
a41c6c53 | 1995 | case 0: |
d40c829f | 1996 | return "clc\t%O0(%b2+1,%R0),%1"; |
9db1d521 | 1997 | |
a41c6c53 | 1998 | case 1: |
d40c829f UW |
1999 | output_asm_insn ("bras\t%3,.+10", operands); |
2000 | output_asm_insn ("clc\t%O0(1,%R0),%1", operands); | |
2001 | return "ex\t%2,0(%3)"; | |
9db1d521 | 2002 | |
a41c6c53 UW |
2003 | default: |
2004 | abort (); | |
9db1d521 | 2005 | } |
10bbf137 | 2006 | } |
a41c6c53 UW |
2007 | [(set_attr "op_type" "SS,NN") |
2008 | (set_attr "type" "cs,cs") | |
077dab3b | 2009 | (set_attr "atype" "*,agen") |
a41c6c53 | 2010 | (set_attr "length" "*,14")]) |
9db1d521 | 2011 | |
358b8f01 | 2012 | (define_insn "cmpmem_short_31" |
a41c6c53 UW |
2013 | [(set (reg:CCS 33) |
2014 | (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
2015 | (match_operand:BLK 1 "memory_operand" "Q,Q"))) | |
2016 | (use (match_operand:SI 2 "nonmemory_operand" "n,a")) | |
2017 | (clobber (match_scratch:SI 3 "=X,&a"))] | |
2018 | "!TARGET_64BIT" | |
9db1d521 | 2019 | { |
a41c6c53 | 2020 | switch (which_alternative) |
9db1d521 | 2021 | { |
a41c6c53 | 2022 | case 0: |
d40c829f | 2023 | return "clc\t%O0(%b2+1,%R0),%1"; |
9db1d521 | 2024 | |
a41c6c53 | 2025 | case 1: |
d40c829f UW |
2026 | output_asm_insn ("bras\t%3,.+10", operands); |
2027 | output_asm_insn ("clc\t%O0(1,%R0),%1", operands); | |
2028 | return "ex\t%2,0(%3)"; | |
9db1d521 | 2029 | |
a41c6c53 UW |
2030 | default: |
2031 | abort (); | |
9db1d521 | 2032 | } |
10bbf137 | 2033 | } |
a41c6c53 UW |
2034 | [(set_attr "op_type" "SS,NN") |
2035 | (set_attr "type" "cs,cs") | |
077dab3b | 2036 | (set_attr "atype" "*,agen") |
a41c6c53 | 2037 | (set_attr "length" "*,14")]) |
9db1d521 | 2038 | |
a41c6c53 | 2039 | ; Compare a block of arbitrary length. |
9db1d521 | 2040 | |
358b8f01 | 2041 | (define_insn "cmpmem_long_64" |
4023fb28 UW |
2042 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2043 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2044 | (set (reg:CCS 33) | |
2045 | (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2046 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
2047 | (use (match_dup 2)) | |
2048 | (use (match_dup 3))] | |
9db1d521 | 2049 | "TARGET_64BIT" |
d40c829f | 2050 | "clcl\t%0,%1" |
9db1d521 | 2051 | [(set_attr "op_type" "RR") |
4023fb28 | 2052 | (set_attr "type" "vs")]) |
9db1d521 | 2053 | |
358b8f01 | 2054 | (define_insn "cmpmem_long_31" |
4023fb28 UW |
2055 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2056 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
2057 | (set (reg:CCS 33) | |
2058 | (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2059 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
2060 | (use (match_dup 2)) | |
2061 | (use (match_dup 3))] | |
9db1d521 | 2062 | "!TARGET_64BIT" |
d40c829f | 2063 | "clcl\t%0,%1" |
9db1d521 | 2064 | [(set_attr "op_type" "RR") |
4023fb28 | 2065 | (set_attr "type" "vs")]) |
9db1d521 HP |
2066 | |
2067 | ; Convert condition code to integer in range (-1, 0, 1) | |
2068 | ||
2069 | (define_insn "cmpint_si" | |
2070 | [(set (match_operand:SI 0 "register_operand" "=d") | |
ba956982 | 2071 | (compare:SI (reg:CCS 33) (const_int 0)))] |
9db1d521 | 2072 | "" |
9db1d521 | 2073 | { |
d40c829f UW |
2074 | output_asm_insn ("lhi\t%0,1", operands); |
2075 | output_asm_insn ("jh\t.+12", operands); | |
2076 | output_asm_insn ("jl\t.+6", operands); | |
2077 | output_asm_insn ("sr\t%0,%0", operands); | |
2078 | return "lcr\t%0,%0"; | |
10bbf137 | 2079 | } |
9db1d521 HP |
2080 | [(set_attr "op_type" "NN") |
2081 | (set_attr "length" "16") | |
f2d3c02a | 2082 | (set_attr "type" "other")]) |
9db1d521 HP |
2083 | |
2084 | (define_insn "cmpint_di" | |
2085 | [(set (match_operand:DI 0 "register_operand" "=d") | |
ba956982 | 2086 | (compare:DI (reg:CCS 33) (const_int 0)))] |
9db1d521 | 2087 | "TARGET_64BIT" |
9db1d521 | 2088 | { |
d40c829f UW |
2089 | output_asm_insn ("lghi\t%0,1", operands); |
2090 | output_asm_insn ("jh\t.+12", operands); | |
2091 | output_asm_insn ("jl\t.+6", operands); | |
2092 | output_asm_insn ("sgr\t%0,%0", operands); | |
2093 | return "lcgr\t%0,%0"; | |
10bbf137 | 2094 | } |
9db1d521 HP |
2095 | [(set_attr "op_type" "NN") |
2096 | (set_attr "length" "22") | |
f2d3c02a | 2097 | (set_attr "type" "other")]) |
9db1d521 | 2098 | |
4023fb28 | 2099 | |
9db1d521 HP |
2100 | ;; |
2101 | ;;- Conversion instructions. | |
2102 | ;; | |
2103 | ||
4023fb28 | 2104 | (define_insn "*sethighqisi" |
d3632d41 | 2105 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2106 | (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2107 | (clobber (reg:CC 33))] |
2108 | "" | |
d3632d41 | 2109 | "@ |
d40c829f UW |
2110 | icm\t%0,8,%1 |
2111 | icmy\t%0,8,%1" | |
d3632d41 | 2112 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2113 | |
2114 | (define_insn "*sethighhisi" | |
d3632d41 | 2115 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2116 | (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2117 | (clobber (reg:CC 33))] |
2118 | "" | |
d3632d41 | 2119 | "@ |
d40c829f UW |
2120 | icm\t%0,12,%1 |
2121 | icmy\t%0,12,%1" | |
d3632d41 | 2122 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2123 | |
2124 | (define_insn "*sethighqidi_64" | |
2125 | [(set (match_operand:DI 0 "register_operand" "=d") | |
10bbf137 | 2126 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2127 | (clobber (reg:CC 33))] |
2128 | "TARGET_64BIT" | |
d40c829f | 2129 | "icmh\t%0,8,%1" |
d3632d41 | 2130 | [(set_attr "op_type" "RSY")]) |
4023fb28 UW |
2131 | |
2132 | (define_insn "*sethighqidi_31" | |
d3632d41 | 2133 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
10bbf137 | 2134 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2135 | (clobber (reg:CC 33))] |
2136 | "!TARGET_64BIT" | |
d3632d41 | 2137 | "@ |
d40c829f UW |
2138 | icm\t%0,8,%1 |
2139 | icmy\t%0,8,%1" | |
d3632d41 | 2140 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2141 | |
cc7ab9b7 UW |
2142 | (define_insn_and_split "*extractqi" |
2143 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2144 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2145 | (match_operand 2 "const_int_operand" "n") | |
2146 | (const_int 0))) | |
2147 | (clobber (reg:CC 33))] | |
2148 | "!TARGET_64BIT | |
4023fb28 | 2149 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
cc7ab9b7 UW |
2150 | "#" |
2151 | "&& reload_completed" | |
4023fb28 | 2152 | [(parallel |
10bbf137 | 2153 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2154 | (clobber (reg:CC 33))]) |
2155 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2156 | { |
2157 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2158 | operands[1] = change_address (operands[1], QImode, 0); | |
10bbf137 | 2159 | } |
0796c16a | 2160 | [(set_attr "atype" "agen")]) |
4023fb28 | 2161 | |
cc7ab9b7 UW |
2162 | (define_insn_and_split "*extracthi" |
2163 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2164 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2165 | (match_operand 2 "const_int_operand" "n") | |
2166 | (const_int 0))) | |
2167 | (clobber (reg:CC 33))] | |
2168 | "!TARGET_64BIT | |
4023fb28 | 2169 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
cc7ab9b7 UW |
2170 | "#" |
2171 | "&& reload_completed" | |
4023fb28 | 2172 | [(parallel |
10bbf137 | 2173 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2174 | (clobber (reg:CC 33))]) |
2175 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2176 | { |
2177 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2178 | operands[1] = change_address (operands[1], HImode, 0); | |
10bbf137 | 2179 | } |
0796c16a | 2180 | [(set_attr "atype" "agen")]) |
4023fb28 | 2181 | |
9db1d521 HP |
2182 | ; |
2183 | ; extendsidi2 instruction pattern(s). | |
2184 | ; | |
2185 | ||
4023fb28 UW |
2186 | (define_expand "extendsidi2" |
2187 | [(set (match_operand:DI 0 "register_operand" "") | |
2188 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2189 | "" | |
2190 | " | |
2191 | { | |
2192 | if (!TARGET_64BIT) | |
2193 | { | |
9f37ccb1 UW |
2194 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2195 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2196 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2197 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2198 | DONE; |
2199 | } | |
2200 | } | |
2201 | ") | |
2202 | ||
2203 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2204 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2205 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2206 | "TARGET_64BIT" | |
2207 | "@ | |
d40c829f UW |
2208 | lgfr\t%0,%1 |
2209 | lgf\t%0,%1" | |
d3632d41 | 2210 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2211 | |
9db1d521 HP |
2212 | ; |
2213 | ; extendhidi2 instruction pattern(s). | |
2214 | ; | |
2215 | ||
4023fb28 UW |
2216 | (define_expand "extendhidi2" |
2217 | [(set (match_operand:DI 0 "register_operand" "") | |
2218 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2219 | "" | |
2220 | " | |
2221 | { | |
2222 | if (!TARGET_64BIT) | |
2223 | { | |
2224 | rtx tmp = gen_reg_rtx (SImode); | |
2225 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
2226 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2227 | DONE; | |
2228 | } | |
2229 | else | |
2230 | { | |
2231 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2232 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2233 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2234 | DONE; |
2235 | } | |
2236 | } | |
2237 | ") | |
2238 | ||
2239 | (define_insn "*extendhidi2" | |
9db1d521 | 2240 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2241 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2242 | "TARGET_64BIT" |
d40c829f | 2243 | "lgh\t%0,%1" |
d3632d41 | 2244 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2245 | |
2246 | ; | |
2247 | ; extendqidi2 instruction pattern(s). | |
2248 | ; | |
2249 | ||
4023fb28 UW |
2250 | (define_expand "extendqidi2" |
2251 | [(set (match_operand:DI 0 "register_operand" "") | |
2252 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
2253 | "" | |
2254 | " | |
2255 | { | |
2256 | if (!TARGET_64BIT) | |
2257 | { | |
2258 | rtx tmp = gen_reg_rtx (SImode); | |
2259 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
2260 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2261 | DONE; | |
2262 | } | |
2263 | else | |
2264 | { | |
2265 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2266 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2267 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2268 | DONE; |
2269 | } | |
2270 | } | |
2271 | ") | |
2272 | ||
d3632d41 UW |
2273 | (define_insn "*extendqidi2" |
2274 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2275 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2276 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2277 | "lgb\t%0,%1" |
d3632d41 UW |
2278 | [(set_attr "op_type" "RXY")]) |
2279 | ||
4023fb28 UW |
2280 | (define_split |
2281 | [(set (match_operand:DI 0 "register_operand" "") | |
2282 | (sign_extend:DI (match_operand:QI 1 "s_operand" "")))] | |
d3632d41 | 2283 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed" |
4023fb28 | 2284 | [(parallel |
10bbf137 | 2285 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2286 | (clobber (reg:CC 33))]) |
2287 | (parallel | |
2288 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
2289 | (clobber (reg:CC 33))])] | |
2290 | "") | |
9db1d521 HP |
2291 | |
2292 | ; | |
2293 | ; extendhisi2 instruction pattern(s). | |
2294 | ; | |
2295 | ||
4023fb28 UW |
2296 | (define_expand "extendhisi2" |
2297 | [(set (match_operand:SI 0 "register_operand" "") | |
2298 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2299 | "" |
4023fb28 UW |
2300 | " |
2301 | { | |
2302 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2303 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
c7453384 | 2304 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); |
4023fb28 UW |
2305 | DONE; |
2306 | } | |
2307 | ") | |
9db1d521 | 2308 | |
4023fb28 | 2309 | (define_insn "*extendhisi2" |
d3632d41 UW |
2310 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2311 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
4023fb28 | 2312 | "" |
d3632d41 | 2313 | "@ |
d40c829f UW |
2314 | lh\t%0,%1 |
2315 | lhy\t%0,%1" | |
d3632d41 | 2316 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
2317 | |
2318 | ; | |
2319 | ; extendqisi2 instruction pattern(s). | |
2320 | ; | |
2321 | ||
4023fb28 UW |
2322 | (define_expand "extendqisi2" |
2323 | [(set (match_operand:SI 0 "register_operand" "") | |
2324 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 | 2325 | "" |
4023fb28 UW |
2326 | " |
2327 | { | |
2328 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2329 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
c7453384 | 2330 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); |
4023fb28 UW |
2331 | DONE; |
2332 | } | |
2333 | ") | |
9db1d521 | 2334 | |
d3632d41 UW |
2335 | (define_insn "*extendqisi2" |
2336 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2337 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
2338 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2339 | "lb\t%0,%1" |
d3632d41 UW |
2340 | [(set_attr "op_type" "RXY")]) |
2341 | ||
4023fb28 UW |
2342 | (define_split |
2343 | [(set (match_operand:SI 0 "register_operand" "") | |
2344 | (sign_extend:SI (match_operand:QI 1 "s_operand" "")))] | |
d3632d41 | 2345 | "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed" |
4023fb28 | 2346 | [(parallel |
10bbf137 | 2347 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2348 | (clobber (reg:CC 33))]) |
2349 | (parallel | |
2350 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
2351 | (clobber (reg:CC 33))])] | |
2352 | "") | |
9db1d521 HP |
2353 | |
2354 | ; | |
2355 | ; extendqihi2 instruction pattern(s). | |
2356 | ; | |
2357 | ||
9db1d521 HP |
2358 | |
2359 | ; | |
2360 | ; zero_extendsidi2 instruction pattern(s). | |
2361 | ; | |
2362 | ||
4023fb28 UW |
2363 | (define_expand "zero_extendsidi2" |
2364 | [(set (match_operand:DI 0 "register_operand" "") | |
2365 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2366 | "" | |
2367 | " | |
2368 | { | |
2369 | if (!TARGET_64BIT) | |
2370 | { | |
9f37ccb1 UW |
2371 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2372 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2373 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2374 | DONE; |
2375 | } | |
2376 | } | |
2377 | ") | |
2378 | ||
2379 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2380 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2381 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2382 | "TARGET_64BIT" | |
2383 | "@ | |
d40c829f UW |
2384 | llgfr\t%0,%1 |
2385 | llgf\t%0,%1" | |
d3632d41 | 2386 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2387 | |
9db1d521 HP |
2388 | ; |
2389 | ; zero_extendhidi2 instruction pattern(s). | |
2390 | ; | |
2391 | ||
4023fb28 UW |
2392 | (define_expand "zero_extendhidi2" |
2393 | [(set (match_operand:DI 0 "register_operand" "") | |
2394 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2395 | "" | |
2396 | " | |
2397 | { | |
2398 | if (!TARGET_64BIT) | |
2399 | { | |
2400 | rtx tmp = gen_reg_rtx (SImode); | |
2401 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
2402 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
2403 | DONE; | |
2404 | } | |
2405 | else | |
2406 | { | |
2407 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2408 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2409 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2410 | DONE; |
2411 | } | |
2412 | } | |
2413 | ") | |
9db1d521 | 2414 | |
4023fb28 UW |
2415 | (define_insn "*zero_extendhidi2" |
2416 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2417 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
9db1d521 | 2418 | "TARGET_64BIT" |
d40c829f | 2419 | "llgh\t%0,%1" |
d3632d41 | 2420 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2421 | |
2422 | ; | |
4023fb28 | 2423 | ; zero_extendqidi2 instruction pattern(s) |
9db1d521 HP |
2424 | ; |
2425 | ||
4023fb28 UW |
2426 | (define_expand "zero_extendqidi2" |
2427 | [(set (match_operand:DI 0 "register_operand" "") | |
2428 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 HP |
2429 | "" |
2430 | " | |
2431 | { | |
2432 | if (!TARGET_64BIT) | |
2433 | { | |
4023fb28 UW |
2434 | rtx tmp = gen_reg_rtx (SImode); |
2435 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
2436 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
9db1d521 HP |
2437 | DONE; |
2438 | } | |
4023fb28 UW |
2439 | else |
2440 | { | |
2441 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2442 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2443 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2444 | DONE; |
2445 | } | |
2446 | } | |
2447 | ") | |
9db1d521 | 2448 | |
4023fb28 UW |
2449 | (define_insn "*zero_extendqidi2" |
2450 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2451 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
9db1d521 | 2452 | "TARGET_64BIT" |
d40c829f | 2453 | "llgc\t%0,%1" |
d3632d41 | 2454 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2455 | |
2456 | ; | |
4023fb28 | 2457 | ; zero_extendhisi2 instruction pattern(s). |
9db1d521 HP |
2458 | ; |
2459 | ||
4023fb28 UW |
2460 | (define_expand "zero_extendhisi2" |
2461 | [(set (match_operand:SI 0 "register_operand" "") | |
2462 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2463 | "" |
4023fb28 UW |
2464 | " |
2465 | { | |
2466 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2467 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
2468 | DONE; | |
2469 | } | |
2470 | ") | |
9db1d521 | 2471 | |
4023fb28 | 2472 | (define_insn "*zero_extendhisi2_64" |
9db1d521 | 2473 | [(set (match_operand:SI 0 "register_operand" "=d") |
4023fb28 | 2474 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2475 | "TARGET_64BIT" |
d40c829f | 2476 | "llgh\t%0,%1" |
d3632d41 | 2477 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2478 | |
2479 | (define_insn_and_split "*zero_extendhisi2_31" | |
2480 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
d3632d41 | 2481 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS"))) |
cc7ab9b7 UW |
2482 | (clobber (reg:CC 33))] |
2483 | "!TARGET_64BIT" | |
2484 | "#" | |
2485 | "&& reload_completed" | |
2486 | [(set (match_dup 0) (const_int 0)) | |
2487 | (parallel | |
2488 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
2489 | (clobber (reg:CC 33))])] | |
2490 | "operands[2] = gen_lowpart (HImode, operands[0]);" | |
0796c16a | 2491 | [(set_attr "atype" "agen")]) |
c7453384 | 2492 | |
4023fb28 UW |
2493 | ; |
2494 | ; zero_extendqisi2 instruction pattern(s). | |
2495 | ; | |
9db1d521 HP |
2496 | |
2497 | (define_expand "zero_extendqisi2" | |
2498 | [(set (match_operand:SI 0 "register_operand" "") | |
4023fb28 | 2499 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
9db1d521 HP |
2500 | "" |
2501 | " | |
2502 | { | |
4023fb28 UW |
2503 | operands[1] = gen_lowpart (SImode, operands[1]); |
2504 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2505 | DONE; | |
2506 | } | |
2507 | ") | |
9db1d521 | 2508 | |
4023fb28 UW |
2509 | (define_insn "*zero_extendqisi2_64" |
2510 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2511 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
2512 | "TARGET_64BIT" | |
d40c829f | 2513 | "llgc\t%0,%1" |
d3632d41 | 2514 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2515 | |
2516 | (define_insn_and_split "*zero_extendqisi2_31" | |
2517 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2518 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
2519 | "!TARGET_64BIT" | |
2520 | "#" | |
2521 | "&& reload_completed" | |
2522 | [(set (match_dup 0) (const_int 0)) | |
2523 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2524 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
0796c16a | 2525 | [(set_attr "atype" "agen")]) |
c7453384 | 2526 | |
9db1d521 HP |
2527 | ; |
2528 | ; zero_extendqihi2 instruction pattern(s). | |
2529 | ; | |
2530 | ||
9db1d521 HP |
2531 | (define_expand "zero_extendqihi2" |
2532 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2533 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
9db1d521 | 2534 | "TARGET_64BIT" |
9db1d521 HP |
2535 | " |
2536 | { | |
4023fb28 UW |
2537 | operands[1] = gen_lowpart (HImode, operands[1]); |
2538 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2539 | DONE; | |
2540 | } | |
2541 | ") | |
9db1d521 | 2542 | |
4023fb28 | 2543 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2544 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2545 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
9db1d521 | 2546 | "TARGET_64BIT" |
d40c829f | 2547 | "llgc\t%0,%1" |
d3632d41 | 2548 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2549 | |
cc7ab9b7 UW |
2550 | (define_insn_and_split "*zero_extendqihi2_31" |
2551 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2552 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
2553 | "!TARGET_64BIT" | |
2554 | "#" | |
2555 | "&& reload_completed" | |
2556 | [(set (match_dup 0) (const_int 0)) | |
2557 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2558 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
0796c16a | 2559 | [(set_attr "atype" "agen")]) |
cc7ab9b7 UW |
2560 | |
2561 | ||
9db1d521 HP |
2562 | ; |
2563 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
2564 | ; | |
2565 | ||
2566 | (define_expand "fixuns_truncdfdi2" | |
2567 | [(set (match_operand:DI 0 "register_operand" "") | |
2568 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
2569 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2570 | { |
2571 | rtx label1 = gen_label_rtx (); | |
2572 | rtx label2 = gen_label_rtx (); | |
2573 | rtx temp = gen_reg_rtx (DFmode); | |
2574 | operands[1] = force_reg (DFmode, operands[1]); | |
2575 | ||
c7453384 | 2576 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2577 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2578 | REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); |
9db1d521 | 2579 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2580 | emit_insn (gen_subdf3 (temp, operands[1], |
2581 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2582 | REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); |
9db1d521 | 2583 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2584 | emit_jump (label2); |
9db1d521 HP |
2585 | |
2586 | emit_label (label1); | |
2587 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2588 | emit_label (label2); | |
2589 | DONE; | |
10bbf137 | 2590 | }) |
9db1d521 HP |
2591 | |
2592 | (define_expand "fix_truncdfdi2" | |
2593 | [(set (match_operand:DI 0 "register_operand" "") | |
2594 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2595 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2596 | { |
2597 | operands[1] = force_reg (DFmode, operands[1]); | |
2598 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2599 | DONE; | |
10bbf137 | 2600 | }) |
9db1d521 HP |
2601 | |
2602 | (define_insn "fix_truncdfdi2_ieee" | |
2603 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2604 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2605 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2606 | (clobber (reg:CC 33))] |
2607 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2608 | "cgdbr\t%0,%h2,%1" |
9db1d521 | 2609 | [(set_attr "op_type" "RRE") |
077dab3b | 2610 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2611 | |
2612 | ; | |
2613 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
2614 | ; | |
2615 | ||
2616 | (define_expand "fixuns_truncdfsi2" | |
2617 | [(set (match_operand:SI 0 "register_operand" "") | |
2618 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
2619 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2620 | { |
2621 | rtx label1 = gen_label_rtx (); | |
2622 | rtx label2 = gen_label_rtx (); | |
2623 | rtx temp = gen_reg_rtx (DFmode); | |
2624 | ||
2625 | operands[1] = force_reg (DFmode,operands[1]); | |
c7453384 | 2626 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2627 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2628 | REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); |
9db1d521 | 2629 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2630 | emit_insn (gen_subdf3 (temp, operands[1], |
2631 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2632 | REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); |
9db1d521 | 2633 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2634 | emit_jump (label2); |
9db1d521 HP |
2635 | |
2636 | emit_label (label1); | |
2637 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2638 | emit_label (label2); | |
2639 | DONE; | |
10bbf137 | 2640 | }) |
9db1d521 HP |
2641 | |
2642 | (define_expand "fix_truncdfsi2" | |
2643 | [(set (match_operand:SI 0 "register_operand" "") | |
2644 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2645 | "TARGET_HARD_FLOAT" | |
9db1d521 | 2646 | { |
c7453384 | 2647 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2648 | { |
2649 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2650 | ||
2651 | rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); | |
4023fb28 UW |
2652 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2653 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
2654 | |
2655 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 2656 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 2657 | two31r, two32, temp)); |
c7453384 EC |
2658 | } |
2659 | else | |
9db1d521 HP |
2660 | { |
2661 | operands[1] = force_reg (DFmode, operands[1]); | |
2662 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2663 | } | |
2664 | ||
2665 | DONE; | |
10bbf137 | 2666 | }) |
9db1d521 HP |
2667 | |
2668 | (define_insn "fix_truncdfsi2_ieee" | |
2669 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2670 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2671 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2672 | (clobber (reg:CC 33))] |
2673 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2674 | "cfdbr\t%0,%h2,%1" |
9db1d521 | 2675 | [(set_attr "op_type" "RRE") |
4023fb28 | 2676 | (set_attr "type" "other" )]) |
9db1d521 HP |
2677 | |
2678 | (define_insn "fix_truncdfsi2_ibm" | |
2679 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2680 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
2681 | (use (match_operand:DI 2 "immediate_operand" "m")) |
2682 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 HP |
2683 | (use (match_operand:BLK 4 "memory_operand" "m")) |
2684 | (clobber (reg:CC 33))] | |
2685 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 2686 | { |
d40c829f UW |
2687 | output_asm_insn ("sd\t%1,%2", operands); |
2688 | output_asm_insn ("aw\t%1,%3", operands); | |
2689 | output_asm_insn ("std\t%1,%4", operands); | |
2690 | output_asm_insn ("xi\t%N4,128", operands); | |
2691 | return "l\t%0,%N4"; | |
10bbf137 | 2692 | } |
9db1d521 | 2693 | [(set_attr "op_type" "NN") |
077dab3b HP |
2694 | (set_attr "type" "ftoi") |
2695 | (set_attr "atype" "agen") | |
9db1d521 HP |
2696 | (set_attr "length" "20")]) |
2697 | ||
2698 | ; | |
2699 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
2700 | ; | |
2701 | ||
2702 | (define_expand "fixuns_truncsfdi2" | |
2703 | [(set (match_operand:DI 0 "register_operand" "") | |
2704 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
2705 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2706 | { |
2707 | rtx label1 = gen_label_rtx (); | |
2708 | rtx label2 = gen_label_rtx (); | |
2709 | rtx temp = gen_reg_rtx (SFmode); | |
2710 | ||
2711 | operands[1] = force_reg (SFmode, operands[1]); | |
c7453384 | 2712 | emit_insn (gen_cmpsf (operands[1], |
4023fb28 | 2713 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2714 | REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); |
9db1d521 HP |
2715 | emit_jump_insn (gen_blt (label1)); |
2716 | ||
4023fb28 UW |
2717 | emit_insn (gen_subsf3 (temp, operands[1], |
2718 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2719 | REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); |
9db1d521 | 2720 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2721 | emit_jump (label2); |
9db1d521 HP |
2722 | |
2723 | emit_label (label1); | |
2724 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2725 | emit_label (label2); | |
2726 | DONE; | |
10bbf137 | 2727 | }) |
9db1d521 HP |
2728 | |
2729 | (define_expand "fix_truncsfdi2" | |
2730 | [(set (match_operand:DI 0 "register_operand" "") | |
2731 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2732 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2733 | { |
2734 | operands[1] = force_reg (SFmode, operands[1]); | |
2735 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2736 | DONE; | |
10bbf137 | 2737 | }) |
9db1d521 HP |
2738 | |
2739 | (define_insn "fix_truncsfdi2_ieee" | |
2740 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2741 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 2742 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2743 | (clobber (reg:CC 33))] |
2744 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2745 | "cgebr\t%0,%h2,%1" |
9db1d521 | 2746 | [(set_attr "op_type" "RRE") |
077dab3b | 2747 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2748 | |
2749 | ; | |
2750 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
2751 | ; | |
2752 | ||
2753 | (define_expand "fixuns_truncsfsi2" | |
2754 | [(set (match_operand:SI 0 "register_operand" "") | |
2755 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
2756 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2757 | { |
2758 | rtx label1 = gen_label_rtx (); | |
2759 | rtx label2 = gen_label_rtx (); | |
2760 | rtx temp = gen_reg_rtx (SFmode); | |
2761 | ||
2762 | operands[1] = force_reg (SFmode, operands[1]); | |
4023fb28 UW |
2763 | emit_insn (gen_cmpsf (operands[1], |
2764 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2765 | REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); |
9db1d521 | 2766 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2767 | emit_insn (gen_subsf3 (temp, operands[1], |
2768 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2769 | REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); |
9db1d521 | 2770 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2771 | emit_jump (label2); |
9db1d521 HP |
2772 | |
2773 | emit_label (label1); | |
2774 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2775 | emit_label (label2); | |
2776 | DONE; | |
10bbf137 | 2777 | }) |
9db1d521 HP |
2778 | |
2779 | (define_expand "fix_truncsfsi2" | |
2780 | [(set (match_operand:SI 0 "register_operand" "") | |
2781 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2782 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
2783 | { |
2784 | if (TARGET_IBM_FLOAT) | |
2785 | { | |
2786 | /* Convert to DFmode and then use the POP algorithm. */ | |
2787 | rtx temp = gen_reg_rtx (DFmode); | |
2788 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
2789 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
2790 | } | |
2791 | else | |
2792 | { | |
2793 | operands[1] = force_reg (SFmode, operands[1]); | |
2794 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2795 | } | |
2796 | ||
2797 | DONE; | |
10bbf137 | 2798 | }) |
9db1d521 HP |
2799 | |
2800 | (define_insn "fix_truncsfsi2_ieee" | |
2801 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2802 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 2803 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2804 | (clobber (reg:CC 33))] |
2805 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2806 | "cfebr\t%0,%h2,%1" |
9db1d521 | 2807 | [(set_attr "op_type" "RRE") |
077dab3b | 2808 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2809 | |
2810 | ; | |
2811 | ; floatdidf2 instruction pattern(s). | |
2812 | ; | |
2813 | ||
2814 | (define_insn "floatdidf2" | |
2815 | [(set (match_operand:DF 0 "register_operand" "=f") | |
4023fb28 UW |
2816 | (float:DF (match_operand:DI 1 "register_operand" "d"))) |
2817 | (clobber (reg:CC 33))] | |
9db1d521 | 2818 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2819 | "cdgbr\t%0,%1" |
9db1d521 | 2820 | [(set_attr "op_type" "RRE") |
f0bf1270 | 2821 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2822 | |
2823 | ; | |
2824 | ; floatdisf2 instruction pattern(s). | |
2825 | ; | |
2826 | ||
2827 | (define_insn "floatdisf2" | |
2828 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 UW |
2829 | (float:SF (match_operand:DI 1 "register_operand" "d"))) |
2830 | (clobber (reg:CC 33))] | |
9db1d521 | 2831 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2832 | "cegbr\t%0,%1" |
9db1d521 | 2833 | [(set_attr "op_type" "RRE") |
077dab3b | 2834 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2835 | |
2836 | ; | |
2837 | ; floatsidf2 instruction pattern(s). | |
2838 | ; | |
2839 | ||
2840 | (define_expand "floatsidf2" | |
4023fb28 UW |
2841 | [(parallel |
2842 | [(set (match_operand:DF 0 "register_operand" "") | |
2843 | (float:DF (match_operand:SI 1 "register_operand" ""))) | |
2844 | (clobber (reg:CC 33))])] | |
9db1d521 | 2845 | "TARGET_HARD_FLOAT" |
9db1d521 | 2846 | { |
c7453384 | 2847 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2848 | { |
2849 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
2850 | ||
2851 | rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); | |
c7453384 | 2852 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
2853 | |
2854 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
2855 | DONE; | |
2856 | } | |
10bbf137 | 2857 | }) |
9db1d521 HP |
2858 | |
2859 | (define_insn "floatsidf2_ieee" | |
2860 | [(set (match_operand:DF 0 "register_operand" "=f") | |
4023fb28 UW |
2861 | (float:DF (match_operand:SI 1 "register_operand" "d"))) |
2862 | (clobber (reg:CC 33))] | |
9db1d521 | 2863 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2864 | "cdfbr\t%0,%1" |
9db1d521 | 2865 | [(set_attr "op_type" "RRE") |
077dab3b | 2866 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2867 | |
2868 | (define_insn "floatsidf2_ibm" | |
2869 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2870 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 2871 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 HP |
2872 | (use (match_operand:BLK 3 "memory_operand" "m")) |
2873 | (clobber (reg:CC 33))] | |
2874 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 2875 | { |
d40c829f UW |
2876 | output_asm_insn ("st\t%1,%N3", operands); |
2877 | output_asm_insn ("xi\t%N3,128", operands); | |
2878 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
2879 | output_asm_insn ("ld\t%0,%3", operands); | |
2880 | return "sd\t%0,%2"; | |
10bbf137 | 2881 | } |
9db1d521 | 2882 | [(set_attr "op_type" "NN") |
4023fb28 | 2883 | (set_attr "type" "other" ) |
077dab3b | 2884 | (set_attr "atype" "agen") |
9db1d521 HP |
2885 | (set_attr "length" "20")]) |
2886 | ||
2887 | ; | |
2888 | ; floatsisf2 instruction pattern(s). | |
2889 | ; | |
2890 | ||
2891 | (define_expand "floatsisf2" | |
4023fb28 UW |
2892 | [(parallel |
2893 | [(set (match_operand:SF 0 "register_operand" "") | |
2894 | (float:SF (match_operand:SI 1 "register_operand" ""))) | |
2895 | (clobber (reg:CC 33))])] | |
9db1d521 | 2896 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
2897 | { |
2898 | if (TARGET_IBM_FLOAT) | |
2899 | { | |
2900 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
2901 | rtx temp = gen_reg_rtx (DFmode); | |
2902 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
2903 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
2904 | DONE; | |
2905 | } | |
10bbf137 | 2906 | }) |
9db1d521 HP |
2907 | |
2908 | (define_insn "floatsisf2_ieee" | |
2909 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 UW |
2910 | (float:SF (match_operand:SI 1 "register_operand" "d"))) |
2911 | (clobber (reg:CC 33))] | |
9db1d521 | 2912 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2913 | "cefbr\t%0,%1" |
9db1d521 | 2914 | [(set_attr "op_type" "RRE") |
077dab3b | 2915 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2916 | |
2917 | ; | |
2918 | ; truncdfsf2 instruction pattern(s). | |
2919 | ; | |
2920 | ||
2921 | (define_expand "truncdfsf2" | |
2922 | [(set (match_operand:SF 0 "register_operand" "") | |
2923 | (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] | |
2924 | "TARGET_HARD_FLOAT" | |
4023fb28 | 2925 | "") |
9db1d521 HP |
2926 | |
2927 | (define_insn "truncdfsf2_ieee" | |
2928 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 | 2929 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] |
9db1d521 | 2930 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2931 | "ledbr\t%0,%1" |
ce50cae8 | 2932 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
2933 | |
2934 | (define_insn "truncdfsf2_ibm" | |
2935 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 2936 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
2937 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
2938 | "@ | |
d40c829f UW |
2939 | lrer\t%0,%1 |
2940 | le\t%0,%1" | |
4023fb28 | 2941 | [(set_attr "op_type" "RR,RX") |
077dab3b | 2942 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
2943 | |
2944 | ; | |
2945 | ; extendsfdf2 instruction pattern(s). | |
2946 | ; | |
2947 | ||
2948 | (define_expand "extendsfdf2" | |
2949 | [(set (match_operand:DF 0 "register_operand" "") | |
2950 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2951 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
2952 | { |
2953 | if (TARGET_IBM_FLOAT) | |
2954 | { | |
2955 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
2956 | DONE; | |
2957 | } | |
10bbf137 | 2958 | }) |
9db1d521 HP |
2959 | |
2960 | (define_insn "extendsfdf2_ieee" | |
2961 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 2962 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
2963 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
2964 | "@ | |
d40c829f UW |
2965 | ldebr\t%0,%1 |
2966 | ldeb\t%0,%1" | |
077dab3b HP |
2967 | [(set_attr "op_type" "RRE,RXE") |
2968 | (set_attr "type" "floads,floads")]) | |
9db1d521 HP |
2969 | |
2970 | (define_insn "extendsfdf2_ibm" | |
2971 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 2972 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
9db1d521 HP |
2973 | (clobber (reg:CC 33))] |
2974 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
2975 | "@ | |
d40c829f UW |
2976 | sdr\t%0,%0\;ler\t%0,%1 |
2977 | sdr\t%0,%0\;le\t%0,%1" | |
077dab3b HP |
2978 | [(set_attr "op_type" "NN,NN") |
2979 | (set_attr "atype" "reg,agen") | |
2980 | (set_attr "length" "4,6") | |
c7453384 | 2981 | (set_attr "type" "o2,o2")]) |
9db1d521 HP |
2982 | |
2983 | ||
2984 | ;; | |
fae778eb | 2985 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 2986 | ;; |
fae778eb | 2987 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
2988 | ; because of unpredictable Bits in Register for Halfword and Byte |
2989 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
2990 | ||
07893d4f UW |
2991 | ;; |
2992 | ;;- Add instructions. | |
2993 | ;; | |
2994 | ||
2995 | ; | |
2996 | ; adddi3 instruction pattern(s). | |
2997 | ; | |
2998 | ||
07893d4f UW |
2999 | (define_insn "*adddi3_sign" |
3000 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3001 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3002 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3003 | (clobber (reg:CC 33))] | |
3004 | "TARGET_64BIT" | |
3005 | "@ | |
d40c829f UW |
3006 | agfr\t%0,%2 |
3007 | agf\t%0,%2" | |
d3632d41 | 3008 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3009 | |
3010 | (define_insn "*adddi3_zero_cc" | |
c7453384 | 3011 | [(set (reg 33) |
07893d4f UW |
3012 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3013 | (match_operand:DI 1 "register_operand" "0,0")) | |
3014 | (const_int 0))) | |
3015 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3016 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3017 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3018 | "@ | |
d40c829f UW |
3019 | algfr\t%0,%2 |
3020 | algf\t%0,%2" | |
d3632d41 | 3021 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3022 | |
3023 | (define_insn "*adddi3_zero_cconly" | |
c7453384 | 3024 | [(set (reg 33) |
07893d4f UW |
3025 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3026 | (match_operand:DI 1 "register_operand" "0,0")) | |
3027 | (const_int 0))) | |
3028 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3029 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3030 | "@ | |
d40c829f UW |
3031 | algfr\t%0,%2 |
3032 | algf\t%0,%2" | |
d3632d41 | 3033 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3034 | |
3035 | (define_insn "*adddi3_zero" | |
3036 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3037 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3038 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3039 | (clobber (reg:CC 33))] | |
3040 | "TARGET_64BIT" | |
3041 | "@ | |
d40c829f UW |
3042 | algfr\t%0,%2 |
3043 | algf\t%0,%2" | |
d3632d41 | 3044 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3045 | |
0a3bdf9d | 3046 | (define_insn "*adddi3_imm_cc" |
c7453384 | 3047 | [(set (reg 33) |
0a3bdf9d UW |
3048 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
3049 | (match_operand:DI 2 "const_int_operand" "K")) | |
3050 | (const_int 0))) | |
3051 | (set (match_operand:DI 0 "register_operand" "=d") | |
3052 | (plus:DI (match_dup 1) (match_dup 2)))] | |
c7453384 EC |
3053 | "TARGET_64BIT |
3054 | && s390_match_ccmode (insn, CCAmode) | |
0a3bdf9d | 3055 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" |
d40c829f | 3056 | "aghi\t%0,%h2" |
077dab3b | 3057 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3058 | |
07893d4f | 3059 | (define_insn "*adddi3_cc" |
c7453384 | 3060 | [(set (reg 33) |
96fd3851 | 3061 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3062 | (match_operand:DI 2 "general_operand" "d,m")) |
3063 | (const_int 0))) | |
3064 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3065 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3066 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3067 | "@ | |
d40c829f UW |
3068 | algr\t%0,%2 |
3069 | alg\t%0,%2" | |
d3632d41 | 3070 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3071 | |
07893d4f | 3072 | (define_insn "*adddi3_cconly" |
c7453384 | 3073 | [(set (reg 33) |
96fd3851 | 3074 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3075 | (match_operand:DI 2 "general_operand" "d,m")) |
3076 | (const_int 0))) | |
3077 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3078 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3079 | "@ | |
d40c829f UW |
3080 | algr\t%0,%2 |
3081 | alg\t%0,%2" | |
d3632d41 | 3082 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3083 | |
07893d4f | 3084 | (define_insn "*adddi3_cconly2" |
c7453384 | 3085 | [(set (reg 33) |
96fd3851 | 3086 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3087 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3088 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3089 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3090 | "@ |
d40c829f UW |
3091 | algr\t%0,%2 |
3092 | alg\t%0,%2" | |
d3632d41 | 3093 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3094 | |
07893d4f | 3095 | (define_insn "*adddi3_64" |
9db1d521 | 3096 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3097 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
9db1d521 HP |
3098 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
3099 | (clobber (reg:CC 33))] | |
3100 | "TARGET_64BIT" | |
3101 | "@ | |
d40c829f UW |
3102 | agr\t%0,%2 |
3103 | aghi\t%0,%h2 | |
3104 | ag\t%0,%2" | |
d3632d41 | 3105 | [(set_attr "op_type" "RRE,RI,RXY")]) |
9db1d521 | 3106 | |
07893d4f UW |
3107 | (define_insn_and_split "*adddi3_31" |
3108 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3109 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3110 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 HP |
3111 | (clobber (reg:CC 33))] |
3112 | "!TARGET_64BIT" | |
07893d4f UW |
3113 | "#" |
3114 | "&& reload_completed" | |
3115 | [(parallel | |
3116 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
3117 | (clobber (reg:CC 33))]) | |
3118 | (parallel | |
3119 | [(set (reg:CCL1 33) | |
3120 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3121 | (match_dup 7))) | |
3122 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3123 | (set (pc) | |
3124 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
3125 | (pc) | |
3126 | (label_ref (match_dup 9)))) | |
3127 | (parallel | |
3128 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
3129 | (clobber (reg:CC 33))]) | |
3130 | (match_dup 9)] | |
97c6f7ad UW |
3131 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3132 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3133 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3134 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3135 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3136 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
07893d4f | 3137 | operands[9] = gen_label_rtx ();" |
0796c16a | 3138 | [(set_attr "op_type" "NN")]) |
9db1d521 HP |
3139 | |
3140 | (define_expand "adddi3" | |
07893d4f UW |
3141 | [(parallel |
3142 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3143 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f UW |
3144 | (match_operand:DI 2 "general_operand" ""))) |
3145 | (clobber (reg:CC 33))])] | |
9db1d521 | 3146 | "" |
07893d4f | 3147 | "") |
9db1d521 | 3148 | |
f3e9edff | 3149 | (define_insn "*la_64" |
d3632d41 UW |
3150 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
3151 | (match_operand:QI 1 "address_operand" "U,W"))] | |
9db1d521 | 3152 | "TARGET_64BIT" |
d3632d41 | 3153 | "@ |
d40c829f UW |
3154 | la\t%0,%a1 |
3155 | lay\t%0,%a1" | |
d3632d41 | 3156 | [(set_attr "op_type" "RX,RXY") |
9db1d521 HP |
3157 | (set_attr "type" "la")]) |
3158 | ||
4888ec5d UW |
3159 | (define_peephole2 |
3160 | [(parallel | |
3161 | [(set (match_operand:DI 0 "register_operand" "") | |
3162 | (match_operand:QI 1 "address_operand" "")) | |
3163 | (clobber (reg:CC 33))])] | |
3164 | "TARGET_64BIT | |
3165 | && strict_memory_address_p (VOIDmode, operands[1]) | |
3166 | && preferred_la_operand_p (operands[1])" | |
3167 | [(set (match_dup 0) (match_dup 1))] | |
3168 | "") | |
3169 | ||
3170 | (define_peephole2 | |
3171 | [(set (match_operand:DI 0 "register_operand" "") | |
3172 | (match_operand:DI 1 "register_operand" "")) | |
3173 | (parallel | |
3174 | [(set (match_dup 0) | |
3175 | (plus:DI (match_dup 0) | |
3176 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
3177 | (clobber (reg:CC 33))])] | |
3178 | "TARGET_64BIT | |
3179 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
3180 | && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2])) | |
3181 | && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))" | |
3182 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] | |
3183 | "") | |
3184 | ||
f3e9edff UW |
3185 | (define_expand "reload_indi" |
3186 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
3187 | (match_operand:DI 1 "s390_plus_operand" "") | |
7974fe63 | 3188 | (match_operand:DI 2 "register_operand" "=&a")])] |
9db1d521 | 3189 | "TARGET_64BIT" |
4023fb28 | 3190 | { |
f3e9edff UW |
3191 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); |
3192 | DONE; | |
10bbf137 | 3193 | }) |
4023fb28 | 3194 | |
c7453384 | 3195 | |
9db1d521 HP |
3196 | ; |
3197 | ; addsi3 instruction pattern(s). | |
3198 | ; | |
9db1d521 | 3199 | |
0a3bdf9d | 3200 | (define_insn "*addsi3_imm_cc" |
c7453384 | 3201 | [(set (reg 33) |
0a3bdf9d UW |
3202 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3203 | (match_operand:SI 2 "const_int_operand" "K")) | |
3204 | (const_int 0))) | |
3205 | (set (match_operand:SI 0 "register_operand" "=d") | |
3206 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3207 | "s390_match_ccmode (insn, CCAmode) | |
3208 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" | |
d40c829f | 3209 | "ahi\t%0,%h2" |
077dab3b | 3210 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3211 | |
07893d4f | 3212 | (define_insn "*addsi3_carry1_cc" |
c7453384 | 3213 | [(set (reg 33) |
d3632d41 UW |
3214 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3215 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3216 | (match_dup 1))) |
d3632d41 | 3217 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3218 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3219 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3220 | "@ |
d40c829f UW |
3221 | alr\t%0,%2 |
3222 | al\t%0,%2 | |
3223 | aly\t%0,%2" | |
d3632d41 | 3224 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3225 | |
3226 | (define_insn "*addsi3_carry1_cconly" | |
c7453384 | 3227 | [(set (reg 33) |
d3632d41 UW |
3228 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3229 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3230 | (match_dup 1))) |
d3632d41 | 3231 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3232 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3233 | "@ |
d40c829f UW |
3234 | alr\t%0,%2 |
3235 | al\t%0,%2 | |
3236 | aly\t%0,%2" | |
d3632d41 | 3237 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3238 | |
3239 | (define_insn "*addsi3_carry2_cc" | |
c7453384 | 3240 | [(set (reg 33) |
d3632d41 UW |
3241 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3242 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3243 | (match_dup 2))) |
d3632d41 | 3244 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3245 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3246 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3247 | "@ |
d40c829f UW |
3248 | alr\t%0,%2 |
3249 | al\t%0,%2 | |
3250 | aly\t%0,%2" | |
d3632d41 | 3251 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3252 | |
3253 | (define_insn "*addsi3_carry2_cconly" | |
c7453384 | 3254 | [(set (reg 33) |
d3632d41 UW |
3255 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3256 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3257 | (match_dup 2))) |
d3632d41 | 3258 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3259 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3260 | "@ |
d40c829f UW |
3261 | alr\t%0,%2 |
3262 | al\t%0,%2 | |
3263 | aly\t%0,%2" | |
d3632d41 | 3264 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3265 | |
9db1d521 | 3266 | (define_insn "*addsi3_cc" |
c7453384 | 3267 | [(set (reg 33) |
d3632d41 UW |
3268 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3269 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3270 | (const_int 0))) |
d3632d41 | 3271 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3272 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3273 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3274 | "@ |
d40c829f UW |
3275 | alr\t%0,%2 |
3276 | al\t%0,%2 | |
3277 | aly\t%0,%2" | |
d3632d41 | 3278 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3279 | |
3280 | (define_insn "*addsi3_cconly" | |
c7453384 | 3281 | [(set (reg 33) |
d3632d41 UW |
3282 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3283 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3284 | (const_int 0))) |
d3632d41 | 3285 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3286 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3287 | "@ |
d40c829f UW |
3288 | alr\t%0,%2 |
3289 | al\t%0,%2 | |
3290 | aly\t%0,%2" | |
d3632d41 | 3291 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3292 | |
3293 | (define_insn "*addsi3_cconly2" | |
c7453384 | 3294 | [(set (reg 33) |
d3632d41 UW |
3295 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3296 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3297 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
ba956982 | 3298 | "s390_match_ccmode(insn, CCLmode)" |
9db1d521 | 3299 | "@ |
d40c829f UW |
3300 | alr\t%0,%2 |
3301 | al\t%0,%2 | |
3302 | aly\t%0,%2" | |
d3632d41 | 3303 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3304 | |
07893d4f | 3305 | (define_insn "*addsi3_sign" |
d3632d41 UW |
3306 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3307 | (plus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3308 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
3309 | (clobber (reg:CC 33))] |
3310 | "" | |
d3632d41 | 3311 | "@ |
d40c829f UW |
3312 | ah\t%0,%2 |
3313 | ahy\t%0,%2" | |
d3632d41 | 3314 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f UW |
3315 | |
3316 | (define_insn "*addsi3_sub" | |
d3632d41 UW |
3317 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3318 | (plus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3319 | (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0))) | |
07893d4f UW |
3320 | (clobber (reg:CC 33))] |
3321 | "" | |
d3632d41 | 3322 | "@ |
d40c829f UW |
3323 | ah\t%0,%2 |
3324 | ahy\t%0,%2" | |
d3632d41 | 3325 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3326 | |
9db1d521 | 3327 | (define_insn "addsi3" |
d3632d41 UW |
3328 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3329 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3330 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
9db1d521 HP |
3331 | (clobber (reg:CC 33))] |
3332 | "" | |
3333 | "@ | |
d40c829f UW |
3334 | ar\t%0,%2 |
3335 | ahi\t%0,%h2 | |
3336 | a\t%0,%2 | |
3337 | ay\t%0,%2" | |
d3632d41 | 3338 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
9db1d521 | 3339 | |
f3e9edff | 3340 | (define_insn "*la_31" |
d3632d41 UW |
3341 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3342 | (match_operand:QI 1 "address_operand" "U,W"))] | |
100c7420 | 3343 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
d3632d41 | 3344 | "@ |
d40c829f UW |
3345 | la\t%0,%a1 |
3346 | lay\t%0,%a1" | |
d3632d41 | 3347 | [(set_attr "op_type" "RX,RXY") |
100c7420 UW |
3348 | (set_attr "type" "la")]) |
3349 | ||
4888ec5d UW |
3350 | (define_peephole2 |
3351 | [(parallel | |
3352 | [(set (match_operand:SI 0 "register_operand" "") | |
3353 | (match_operand:QI 1 "address_operand" "")) | |
3354 | (clobber (reg:CC 33))])] | |
3355 | "!TARGET_64BIT | |
3356 | && strict_memory_address_p (VOIDmode, operands[1]) | |
3357 | && preferred_la_operand_p (operands[1])" | |
3358 | [(set (match_dup 0) (match_dup 1))] | |
3359 | "") | |
3360 | ||
3361 | (define_peephole2 | |
3362 | [(set (match_operand:SI 0 "register_operand" "") | |
3363 | (match_operand:SI 1 "register_operand" "")) | |
3364 | (parallel | |
3365 | [(set (match_dup 0) | |
3366 | (plus:SI (match_dup 0) | |
3367 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
3368 | (clobber (reg:CC 33))])] | |
3369 | "!TARGET_64BIT | |
3370 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
3371 | && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2])) | |
3372 | && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))" | |
3373 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] | |
3374 | "") | |
3375 | ||
100c7420 | 3376 | (define_insn "*la_31_and" |
d3632d41 UW |
3377 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3378 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
100c7420 UW |
3379 | (const_int 2147483647)))] |
3380 | "!TARGET_64BIT" | |
d3632d41 | 3381 | "@ |
d40c829f UW |
3382 | la\t%0,%a1 |
3383 | lay\t%0,%a1" | |
d3632d41 | 3384 | [(set_attr "op_type" "RX,RXY") |
9db1d521 | 3385 | (set_attr "type" "la")]) |
100c7420 UW |
3386 | |
3387 | (define_insn_and_split "*la_31_and_cc" | |
3388 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3389 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
3390 | (const_int 2147483647))) | |
3391 | (clobber (reg:CC 33))] | |
3392 | "!TARGET_64BIT" | |
3393 | "#" | |
3394 | "&& reload_completed" | |
c7453384 | 3395 | [(set (match_dup 0) |
100c7420 UW |
3396 | (and:SI (match_dup 1) (const_int 2147483647)))] |
3397 | "" | |
3398 | [(set_attr "op_type" "RX") | |
100c7420 | 3399 | (set_attr "type" "la")]) |
9db1d521 | 3400 | |
a41c6c53 | 3401 | (define_insn "force_la_31" |
d3632d41 UW |
3402 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3403 | (match_operand:QI 1 "address_operand" "U,W")) | |
a41c6c53 UW |
3404 | (use (const_int 0))] |
3405 | "!TARGET_64BIT" | |
d3632d41 | 3406 | "@ |
d40c829f UW |
3407 | la\t%0,%a1 |
3408 | lay\t%0,%a1" | |
a41c6c53 | 3409 | [(set_attr "op_type" "RX") |
a41c6c53 UW |
3410 | (set_attr "type" "la")]) |
3411 | ||
f3e9edff UW |
3412 | (define_expand "reload_insi" |
3413 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
3414 | (match_operand:SI 1 "s390_plus_operand" "") | |
7974fe63 | 3415 | (match_operand:SI 2 "register_operand" "=&a")])] |
f3e9edff | 3416 | "!TARGET_64BIT" |
4023fb28 | 3417 | { |
f3e9edff UW |
3418 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); |
3419 | DONE; | |
10bbf137 | 3420 | }) |
bc1fa59c | 3421 | |
9db1d521 | 3422 | |
9db1d521 HP |
3423 | ; |
3424 | ; adddf3 instruction pattern(s). | |
3425 | ; | |
3426 | ||
3427 | (define_expand "adddf3" | |
3428 | [(parallel | |
3429 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3430 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3431 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3432 | (clobber (reg:CC 33))])] |
3433 | "TARGET_HARD_FLOAT" | |
3434 | "") | |
3435 | ||
3436 | (define_insn "*adddf3" | |
3437 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3438 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3439 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3440 | (clobber (reg:CC 33))] |
3441 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3442 | "@ | |
d40c829f UW |
3443 | adbr\t%0,%2 |
3444 | adb\t%0,%2" | |
ce50cae8 | 3445 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3446 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3447 | |
3ef093a8 AK |
3448 | (define_insn "*adddf3_cc" |
3449 | [(set (reg 33) | |
3450 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3451 | (match_operand:DF 2 "general_operand" "f,R")) | |
3452 | (match_operand:DF 3 "const0_operand" ""))) | |
3453 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
3454 | (plus:DF (match_dup 1) (match_dup 2)))] | |
3455 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3456 | "@ | |
d40c829f UW |
3457 | adbr\t%0,%2 |
3458 | adb\t%0,%2" | |
3ef093a8 AK |
3459 | [(set_attr "op_type" "RRE,RXE") |
3460 | (set_attr "type" "fsimpd,fsimpd")]) | |
3461 | ||
3462 | (define_insn "*adddf3_cconly" | |
3463 | [(set (reg 33) | |
3464 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3465 | (match_operand:DF 2 "general_operand" "f,R")) | |
3466 | (match_operand:DF 3 "const0_operand" ""))) | |
3467 | (clobber (match_scratch:DF 0 "=f,f"))] | |
3468 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3469 | "@ | |
d40c829f UW |
3470 | adbr\t%0,%2 |
3471 | adb\t%0,%2" | |
3ef093a8 AK |
3472 | [(set_attr "op_type" "RRE,RXE") |
3473 | (set_attr "type" "fsimpd,fsimpd")]) | |
3474 | ||
9db1d521 HP |
3475 | (define_insn "*adddf3_ibm" |
3476 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3477 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3478 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3479 | (clobber (reg:CC 33))] |
3480 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3481 | "@ | |
d40c829f UW |
3482 | adr\t%0,%2 |
3483 | ad\t%0,%2" | |
9db1d521 | 3484 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3485 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
3486 | |
3487 | ; | |
3488 | ; addsf3 instruction pattern(s). | |
3489 | ; | |
3490 | ||
3491 | (define_expand "addsf3" | |
3492 | [(parallel | |
3493 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3494 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3495 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3496 | (clobber (reg:CC 33))])] |
3497 | "TARGET_HARD_FLOAT" | |
3498 | "") | |
3499 | ||
3500 | (define_insn "*addsf3" | |
3501 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3502 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3503 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3504 | (clobber (reg:CC 33))] |
3505 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3506 | "@ | |
d40c829f UW |
3507 | aebr\t%0,%2 |
3508 | aeb\t%0,%2" | |
ce50cae8 | 3509 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3510 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 3511 | |
3ef093a8 AK |
3512 | (define_insn "*addsf3_cc" |
3513 | [(set (reg 33) | |
3514 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3515 | (match_operand:SF 2 "general_operand" "f,R")) | |
3516 | (match_operand:SF 3 "const0_operand" ""))) | |
3517 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
3518 | (plus:SF (match_dup 1) (match_dup 2)))] | |
3519 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3520 | "@ | |
d40c829f UW |
3521 | aebr\t%0,%2 |
3522 | aeb\t%0,%2" | |
3ef093a8 AK |
3523 | [(set_attr "op_type" "RRE,RXE") |
3524 | (set_attr "type" "fsimps,fsimps")]) | |
3525 | ||
3526 | (define_insn "*addsf3_cconly" | |
3527 | [(set (reg 33) | |
3528 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3529 | (match_operand:SF 2 "general_operand" "f,R")) | |
3530 | (match_operand:SF 3 "const0_operand" ""))) | |
3531 | (clobber (match_scratch:SF 0 "=f,f"))] | |
3532 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3533 | "@ | |
d40c829f UW |
3534 | aebr\t%0,%2 |
3535 | aeb\t%0,%2" | |
3ef093a8 AK |
3536 | [(set_attr "op_type" "RRE,RXE") |
3537 | (set_attr "type" "fsimps,fsimps")]) | |
3538 | ||
9db1d521 HP |
3539 | (define_insn "*addsf3" |
3540 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3541 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3542 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3543 | (clobber (reg:CC 33))] |
3544 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3545 | "@ | |
d40c829f UW |
3546 | aer\t%0,%2 |
3547 | ae\t%0,%2" | |
9db1d521 | 3548 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3549 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
3550 | |
3551 | ||
3552 | ;; | |
3553 | ;;- Subtract instructions. | |
3554 | ;; | |
3555 | ||
3556 | ; | |
3557 | ; subdi3 instruction pattern(s). | |
3558 | ; | |
3559 | ||
07893d4f UW |
3560 | (define_insn "*subdi3_sign" |
3561 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3562 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3563 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3564 | (clobber (reg:CC 33))] | |
3565 | "TARGET_64BIT" | |
3566 | "@ | |
d40c829f UW |
3567 | sgfr\t%0,%2 |
3568 | sgf\t%0,%2" | |
d3632d41 | 3569 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3570 | |
3571 | (define_insn "*subdi3_zero_cc" | |
c7453384 | 3572 | [(set (reg 33) |
07893d4f UW |
3573 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3574 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3575 | (const_int 0))) | |
3576 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3577 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3578 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3579 | "@ | |
d40c829f UW |
3580 | slgfr\t%0,%2 |
3581 | slgf\t%0,%2" | |
d3632d41 | 3582 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3583 | |
3584 | (define_insn "*subdi3_zero_cconly" | |
c7453384 | 3585 | [(set (reg 33) |
07893d4f UW |
3586 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3587 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3588 | (const_int 0))) | |
3589 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3590 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3591 | "@ | |
d40c829f UW |
3592 | slgfr\t%0,%2 |
3593 | slgf\t%0,%2" | |
d3632d41 | 3594 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3595 | |
3596 | (define_insn "*subdi3_zero" | |
3597 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3598 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3599 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3600 | (clobber (reg:CC 33))] | |
3601 | "TARGET_64BIT" | |
3602 | "@ | |
d40c829f UW |
3603 | slgfr\t%0,%2 |
3604 | slgf\t%0,%2" | |
d3632d41 | 3605 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3606 | |
3607 | (define_insn "*subdi3_cc" | |
3608 | [(set (reg 33) | |
3609 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3610 | (match_operand:DI 2 "general_operand" "d,m")) | |
3611 | (const_int 0))) | |
3612 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3613 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3614 | "s390_match_ccmode (insn, CCLmode)" | |
3615 | "@ | |
d40c829f UW |
3616 | slgr\t%0,%2 |
3617 | slg\t%0,%2" | |
d3632d41 | 3618 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3619 | |
3620 | (define_insn "*subdi3_cconly" | |
3621 | [(set (reg 33) | |
3622 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3623 | (match_operand:DI 2 "general_operand" "d,m")) | |
3624 | (const_int 0))) | |
3625 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3626 | "s390_match_ccmode (insn, CCLmode)" | |
3627 | "@ | |
d40c829f UW |
3628 | slgr\t%0,%2 |
3629 | slg\t%0,%2" | |
d3632d41 | 3630 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3631 | |
9db1d521 HP |
3632 | (define_insn "*subdi3_64" |
3633 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3634 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3635 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
3636 | (clobber (reg:CC 33))] | |
3637 | "TARGET_64BIT" | |
3638 | "@ | |
d40c829f UW |
3639 | sgr\t%0,%2 |
3640 | sg\t%0,%2" | |
077dab3b | 3641 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3642 | |
07893d4f UW |
3643 | (define_insn_and_split "*subdi3_31" |
3644 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3645 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3646 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3647 | (clobber (reg:CC 33))] |
07893d4f UW |
3648 | "!TARGET_64BIT" |
3649 | "#" | |
3650 | "&& reload_completed" | |
3651 | [(parallel | |
3652 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
3653 | (clobber (reg:CC 33))]) | |
3654 | (parallel | |
3655 | [(set (reg:CCL2 33) | |
3656 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3657 | (match_dup 7))) | |
3658 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3659 | (set (pc) | |
3660 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
3661 | (pc) | |
3662 | (label_ref (match_dup 9)))) | |
3663 | (parallel | |
3664 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
3665 | (clobber (reg:CC 33))]) | |
3666 | (match_dup 9)] | |
97c6f7ad UW |
3667 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3668 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3669 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3670 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3671 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3672 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
07893d4f | 3673 | operands[9] = gen_label_rtx ();" |
0796c16a | 3674 | [(set_attr "op_type" "NN")]) |
07893d4f UW |
3675 | |
3676 | (define_expand "subdi3" | |
3677 | [(parallel | |
3678 | [(set (match_operand:DI 0 "register_operand" "") | |
3679 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3680 | (match_operand:DI 2 "general_operand" ""))) | |
3681 | (clobber (reg:CC 33))])] | |
9db1d521 | 3682 | "" |
07893d4f | 3683 | "") |
9db1d521 HP |
3684 | |
3685 | ; | |
3686 | ; subsi3 instruction pattern(s). | |
3687 | ; | |
3688 | ||
07893d4f UW |
3689 | (define_insn "*subsi3_borrow_cc" |
3690 | [(set (reg 33) | |
d3632d41 UW |
3691 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3692 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3693 | (match_dup 1))) |
d3632d41 | 3694 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f UW |
3695 | (minus:SI (match_dup 1) (match_dup 2)))] |
3696 | "s390_match_ccmode(insn, CCL2mode)" | |
3697 | "@ | |
d40c829f UW |
3698 | slr\t%0,%2 |
3699 | sl\t%0,%2 | |
3700 | sly\t%0,%2" | |
d3632d41 | 3701 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3702 | |
3703 | (define_insn "*subsi3_borrow_cconly" | |
3704 | [(set (reg 33) | |
d3632d41 UW |
3705 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3706 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3707 | (match_dup 1))) |
d3632d41 | 3708 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
07893d4f UW |
3709 | "s390_match_ccmode(insn, CCL2mode)" |
3710 | "@ | |
d40c829f UW |
3711 | slr\t%0,%2 |
3712 | sl\t%0,%2 | |
3713 | sly\t%0,%2" | |
d3632d41 | 3714 | [(set_attr "op_type" "RR,RX,RXE")]) |
07893d4f | 3715 | |
9db1d521 HP |
3716 | (define_insn "*subsi3_cc" |
3717 | [(set (reg 33) | |
d3632d41 UW |
3718 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3719 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3720 | (const_int 0))) |
d3632d41 | 3721 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3722 | (minus:SI (match_dup 1) (match_dup 2)))] |
ba956982 | 3723 | "s390_match_ccmode(insn, CCLmode)" |
9db1d521 | 3724 | "@ |
d40c829f UW |
3725 | slr\t%0,%2 |
3726 | sl\t%0,%2 | |
3727 | sly\t%0,%2" | |
d3632d41 | 3728 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3729 | |
3730 | (define_insn "*subsi3_cconly" | |
3731 | [(set (reg 33) | |
d3632d41 UW |
3732 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3733 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3734 | (const_int 0))) |
d3632d41 | 3735 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
ba956982 | 3736 | "s390_match_ccmode(insn, CCLmode)" |
9db1d521 | 3737 | "@ |
d40c829f UW |
3738 | slr\t%0,%2 |
3739 | sl\t%0,%2 | |
3740 | sly\t%0,%2" | |
d3632d41 | 3741 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3742 | |
07893d4f | 3743 | (define_insn "*subsi3_sign" |
d3632d41 UW |
3744 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3745 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3746 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
3747 | (clobber (reg:CC 33))] |
3748 | "" | |
d3632d41 | 3749 | "@ |
d40c829f UW |
3750 | sh\t%0,%2 |
3751 | shy\t%0,%2" | |
d3632d41 | 3752 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f UW |
3753 | |
3754 | (define_insn "*subsi3_sub" | |
d3632d41 UW |
3755 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3756 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3757 | (subreg:SI (match_operand:HI 2 "memory_operand" "R,T") 0))) | |
07893d4f UW |
3758 | (clobber (reg:CC 33))] |
3759 | "" | |
d3632d41 | 3760 | "@ |
d40c829f UW |
3761 | sh\t%0,%2 |
3762 | shy\t%0,%2" | |
d3632d41 | 3763 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3764 | |
9db1d521 | 3765 | (define_insn "subsi3" |
d3632d41 UW |
3766 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
3767 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
3768 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
3769 | (clobber (reg:CC 33))] |
3770 | "" | |
3771 | "@ | |
d40c829f UW |
3772 | sr\t%0,%2 |
3773 | s\t%0,%2 | |
3774 | sy\t%0,%2" | |
d3632d41 | 3775 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3776 | |
9db1d521 HP |
3777 | |
3778 | ; | |
3779 | ; subdf3 instruction pattern(s). | |
3780 | ; | |
3781 | ||
3782 | (define_expand "subdf3" | |
3783 | [(parallel | |
3784 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
3785 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 3786 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3787 | (clobber (reg:CC 33))])] |
3788 | "TARGET_HARD_FLOAT" | |
3789 | "") | |
3790 | ||
3791 | (define_insn "*subdf3" | |
3792 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
3793 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 3794 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3795 | (clobber (reg:CC 33))] |
3796 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3797 | "@ | |
d40c829f UW |
3798 | sdbr\t%0,%2 |
3799 | sdb\t%0,%2" | |
ce50cae8 | 3800 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3801 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3802 | |
3ef093a8 AK |
3803 | (define_insn "*subdf3_cc" |
3804 | [(set (reg 33) | |
3805 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3806 | (match_operand:DF 2 "general_operand" "f,R")) | |
3807 | (match_operand:DF 3 "const0_operand" ""))) | |
3808 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
3809 | (plus:DF (match_dup 1) (match_dup 2)))] | |
3810 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3811 | "@ | |
d40c829f UW |
3812 | sdbr\t%0,%2 |
3813 | sdb\t%0,%2" | |
3ef093a8 AK |
3814 | [(set_attr "op_type" "RRE,RXE") |
3815 | (set_attr "type" "fsimpd,fsimpd")]) | |
3816 | ||
3817 | (define_insn "*subdf3_cconly" | |
3818 | [(set (reg 33) | |
3819 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3820 | (match_operand:DF 2 "general_operand" "f,R")) | |
3821 | (match_operand:DF 3 "const0_operand" ""))) | |
3822 | (clobber (match_scratch:DF 0 "=f,f"))] | |
3823 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3824 | "@ | |
d40c829f UW |
3825 | sdbr\t%0,%2 |
3826 | sdb\t%0,%2" | |
3ef093a8 AK |
3827 | [(set_attr "op_type" "RRE,RXE") |
3828 | (set_attr "type" "fsimpd,fsimpd")]) | |
3829 | ||
9db1d521 HP |
3830 | (define_insn "*subdf3_ibm" |
3831 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
3832 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 3833 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3834 | (clobber (reg:CC 33))] |
3835 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3836 | "@ | |
d40c829f UW |
3837 | sdr\t%0,%2 |
3838 | sd\t%0,%2" | |
9db1d521 | 3839 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3840 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
3841 | |
3842 | ; | |
3843 | ; subsf3 instruction pattern(s). | |
3844 | ; | |
3845 | ||
3846 | (define_expand "subsf3" | |
3847 | [(parallel | |
3848 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
3849 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 3850 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3851 | (clobber (reg:CC 33))])] |
3852 | "TARGET_HARD_FLOAT" | |
3853 | "") | |
3854 | ||
3855 | (define_insn "*subsf3" | |
3856 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
3857 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 3858 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3859 | (clobber (reg:CC 33))] |
3860 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3861 | "@ | |
d40c829f UW |
3862 | sebr\t%0,%2 |
3863 | seb\t%0,%2" | |
ce50cae8 | 3864 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3865 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 3866 | |
3ef093a8 AK |
3867 | (define_insn "*subsf3_cc" |
3868 | [(set (reg 33) | |
3869 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3870 | (match_operand:SF 2 "general_operand" "f,R")) | |
3871 | (match_operand:SF 3 "const0_operand" ""))) | |
3872 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
3873 | (minus:SF (match_dup 1) (match_dup 2)))] | |
3874 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3875 | "@ | |
d40c829f UW |
3876 | sebr\t%0,%2 |
3877 | seb\t%0,%2" | |
3ef093a8 AK |
3878 | [(set_attr "op_type" "RRE,RXE") |
3879 | (set_attr "type" "fsimps,fsimps")]) | |
3880 | ||
3881 | (define_insn "*subsf3_cconly" | |
3882 | [(set (reg 33) | |
3883 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3884 | (match_operand:SF 2 "general_operand" "f,R")) | |
3885 | (match_operand:SF 3 "const0_operand" ""))) | |
3886 | (clobber (match_scratch:SF 0 "=f,f"))] | |
3887 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3888 | "@ | |
d40c829f UW |
3889 | sebr\t%0,%2 |
3890 | seb\t%0,%2" | |
3ef093a8 AK |
3891 | [(set_attr "op_type" "RRE,RXE") |
3892 | (set_attr "type" "fsimps,fsimps")]) | |
3893 | ||
9db1d521 HP |
3894 | (define_insn "*subsf3_ibm" |
3895 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
3896 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 3897 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3898 | (clobber (reg:CC 33))] |
3899 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3900 | "@ | |
d40c829f UW |
3901 | ser\t%0,%2 |
3902 | se\t%0,%2" | |
9db1d521 | 3903 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3904 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
3905 | |
3906 | ||
3907 | ;; | |
3908 | ;;- Multiply instructions. | |
3909 | ;; | |
3910 | ||
4023fb28 UW |
3911 | ; |
3912 | ; muldi3 instruction pattern(s). | |
3913 | ; | |
9db1d521 | 3914 | |
07893d4f UW |
3915 | (define_insn "*muldi3_sign" |
3916 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3917 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
3918 | (match_operand:DI 1 "register_operand" "0,0")))] | |
3919 | "TARGET_64BIT" | |
3920 | "@ | |
d40c829f UW |
3921 | msgfr\t%0,%2 |
3922 | msgf\t%0,%2" | |
d3632d41 | 3923 | [(set_attr "op_type" "RRE,RXY") |
07893d4f UW |
3924 | (set_attr "type" "imul")]) |
3925 | ||
3926 | ||
4023fb28 | 3927 | (define_insn "muldi3" |
9db1d521 | 3928 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3929 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 3930 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
3931 | "TARGET_64BIT" |
3932 | "@ | |
d40c829f UW |
3933 | msgr\t%0,%2 |
3934 | mghi\t%0,%h2 | |
3935 | msg\t%0,%2" | |
d3632d41 | 3936 | [(set_attr "op_type" "RRE,RI,RXY") |
f2d3c02a HP |
3937 | (set_attr "type" "imul")]) |
3938 | ||
9db1d521 HP |
3939 | ; |
3940 | ; mulsi3 instruction pattern(s). | |
3941 | ; | |
3942 | ||
3943 | (define_insn "mulsi3" | |
d3632d41 UW |
3944 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3945 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3946 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
3947 | "" |
3948 | "@ | |
d40c829f UW |
3949 | msr\t%0,%2 |
3950 | mhi\t%0,%h2 | |
3951 | ms\t%0,%2 | |
3952 | msy\t%0,%2" | |
d3632d41 | 3953 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
f2d3c02a | 3954 | (set_attr "type" "imul")]) |
9db1d521 | 3955 | |
4023fb28 UW |
3956 | ; |
3957 | ; mulsidi3 instruction pattern(s). | |
3958 | ; | |
3959 | ||
3960 | (define_expand "mulsidi3" | |
3961 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3962 | (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")) |
4023fb28 UW |
3963 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))] |
3964 | "!TARGET_64BIT" | |
4023fb28 UW |
3965 | { |
3966 | rtx insn; | |
3967 | ||
014cb9b6 | 3968 | emit_insn (gen_zero_extendsidi2 (operands[0], operands[1])); |
4023fb28 UW |
3969 | insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2])); |
3970 | ||
3971 | REG_NOTES (insn) = | |
c7453384 EC |
3972 | gen_rtx_EXPR_LIST (REG_EQUAL, |
3973 | gen_rtx_MULT (DImode, | |
4023fb28 UW |
3974 | gen_rtx_SIGN_EXTEND (DImode, operands[1]), |
3975 | gen_rtx_SIGN_EXTEND (DImode, operands[2])), | |
3976 | REG_NOTES (insn)); | |
3977 | DONE; | |
10bbf137 | 3978 | }) |
c7453384 | 3979 | |
9db1d521 HP |
3980 | (define_insn "mulsi_6432" |
3981 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
c7453384 | 3982 | (mult:DI (sign_extend:DI |
4023fb28 | 3983 | (truncate:SI (match_operand:DI 1 "register_operand" "0,0"))) |
9db1d521 | 3984 | (sign_extend:DI |
d3632d41 | 3985 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] |
9db1d521 HP |
3986 | "!TARGET_64BIT" |
3987 | "@ | |
d40c829f UW |
3988 | mr\t%0,%2 |
3989 | m\t%0,%2" | |
9db1d521 | 3990 | [(set_attr "op_type" "RR,RX") |
f2d3c02a | 3991 | (set_attr "type" "imul")]) |
c7453384 | 3992 | |
9db1d521 HP |
3993 | ; |
3994 | ; muldf3 instruction pattern(s). | |
3995 | ; | |
3996 | ||
3997 | (define_expand "muldf3" | |
3998 | [(parallel | |
3999 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4000 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 4001 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4002 | (clobber (reg:CC 33))])] |
4003 | "TARGET_HARD_FLOAT" | |
4004 | "") | |
4005 | ||
4006 | (define_insn "*muldf3" | |
4007 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4008 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 4009 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4010 | (clobber (reg:CC 33))] |
4011 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4012 | "@ | |
d40c829f UW |
4013 | mdbr\t%0,%2 |
4014 | mdb\t%0,%2" | |
ce50cae8 | 4015 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4016 | (set_attr "type" "fmuld")]) |
9db1d521 HP |
4017 | |
4018 | (define_insn "*muldf3_ibm" | |
4019 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4020 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 4021 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4022 | (clobber (reg:CC 33))] |
4023 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4024 | "@ | |
d40c829f UW |
4025 | mdr\t%0,%2 |
4026 | md\t%0,%2" | |
9db1d521 | 4027 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4028 | (set_attr "type" "fmuld")]) |
9db1d521 HP |
4029 | |
4030 | ; | |
4031 | ; mulsf3 instruction pattern(s). | |
4032 | ; | |
4033 | ||
4034 | (define_expand "mulsf3" | |
4035 | [(parallel | |
4036 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4037 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 4038 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4039 | (clobber (reg:CC 33))])] |
4040 | "TARGET_HARD_FLOAT" | |
4041 | "") | |
4042 | ||
4043 | (define_insn "*mulsf3" | |
4044 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4045 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 4046 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4047 | (clobber (reg:CC 33))] |
4048 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4049 | "@ | |
d40c829f UW |
4050 | meebr\t%0,%2 |
4051 | meeb\t%0,%2" | |
ce50cae8 | 4052 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4053 | (set_attr "type" "fmuls")]) |
9db1d521 HP |
4054 | |
4055 | (define_insn "*mulsf3_ibm" | |
4056 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4057 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 4058 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4059 | (clobber (reg:CC 33))] |
4060 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4061 | "@ | |
d40c829f UW |
4062 | mer\t%0,%2 |
4063 | me\t%0,%2" | |
9db1d521 | 4064 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4065 | (set_attr "type" "fmuls")]) |
9db1d521 HP |
4066 | |
4067 | ||
4068 | ;; | |
4069 | ;;- Divide and modulo instructions. | |
4070 | ;; | |
4071 | ||
4072 | ; | |
4023fb28 | 4073 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4074 | ; |
4075 | ||
4023fb28 UW |
4076 | (define_expand "divmoddi4" |
4077 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4078 | (div:DI (match_operand:DI 1 "general_operand" "") | |
4079 | (match_operand:DI 2 "general_operand" ""))) | |
4080 | (set (match_operand:DI 3 "general_operand" "") | |
4081 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4082 | (clobber (match_dup 4))] | |
9db1d521 | 4083 | "TARGET_64BIT" |
9db1d521 | 4084 | { |
4023fb28 UW |
4085 | rtx insn, div_equal, mod_equal, equal; |
4086 | ||
4087 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4088 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4089 | equal = gen_rtx_IOR (TImode, | |
4090 | gen_rtx_ZERO_EXTEND (TImode, div_equal), | |
4091 | gen_rtx_ASHIFT (TImode, | |
4092 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
4093 | GEN_INT (64))); | |
4094 | ||
4095 | operands[4] = gen_reg_rtx(TImode); | |
4096 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4097 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
ecbe845e | 4098 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); |
4023fb28 UW |
4099 | insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2])); |
4100 | REG_NOTES (insn) = | |
4101 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4102 | ||
4103 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4104 | REG_NOTES (insn) = | |
4105 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4106 | ||
4107 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4108 | REG_NOTES (insn) = | |
4109 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4110 | |
9db1d521 | 4111 | DONE; |
10bbf137 | 4112 | }) |
9db1d521 HP |
4113 | |
4114 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4115 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4116 | (ior:TI | |
4117 | (zero_extend:TI | |
4118 | (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) | |
4119 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4120 | (ashift:TI | |
4121 | (zero_extend:TI | |
c7453384 | 4122 | (mod:DI (truncate:DI (match_dup 1)) |
4023fb28 UW |
4123 | (match_dup 2))) |
4124 | (const_int 64))))] | |
9db1d521 HP |
4125 | "TARGET_64BIT" |
4126 | "@ | |
d40c829f UW |
4127 | dsgr\t%0,%2 |
4128 | dsg\t%0,%2" | |
d3632d41 | 4129 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4130 | (set_attr "type" "idiv")]) |
9db1d521 | 4131 | |
4023fb28 UW |
4132 | (define_insn "divmodtisi3" |
4133 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4134 | (ior:TI | |
4135 | (zero_extend:TI | |
4136 | (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) | |
4137 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) | |
4138 | (ashift:TI | |
4139 | (zero_extend:TI | |
c7453384 | 4140 | (mod:DI (truncate:DI (match_dup 1)) |
4023fb28 UW |
4141 | (sign_extend:DI (match_dup 2)))) |
4142 | (const_int 64))))] | |
9db1d521 | 4143 | "TARGET_64BIT" |
4023fb28 | 4144 | "@ |
d40c829f UW |
4145 | dsgfr\t%0,%2 |
4146 | dsgf\t%0,%2" | |
d3632d41 | 4147 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4148 | (set_attr "type" "idiv")]) |
9db1d521 | 4149 | |
4023fb28 UW |
4150 | ; |
4151 | ; udivmoddi4 instruction pattern(s). | |
4152 | ; | |
9db1d521 | 4153 | |
4023fb28 UW |
4154 | (define_expand "udivmoddi4" |
4155 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4156 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4157 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4158 | (set (match_operand:DI 3 "general_operand" "") | |
4159 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4160 | (clobber (match_dup 4))] | |
9db1d521 | 4161 | "TARGET_64BIT" |
9db1d521 | 4162 | { |
4023fb28 UW |
4163 | rtx insn, div_equal, mod_equal, equal; |
4164 | ||
4165 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4166 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4167 | equal = gen_rtx_IOR (TImode, | |
4168 | gen_rtx_ZERO_EXTEND (TImode, div_equal), | |
4169 | gen_rtx_ASHIFT (TImode, | |
4170 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
4171 | GEN_INT (64))); | |
4172 | ||
4173 | operands[4] = gen_reg_rtx(TImode); | |
4174 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4175 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4176 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4177 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4178 | REG_NOTES (insn) = | |
4179 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4180 | ||
4181 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4182 | REG_NOTES (insn) = | |
4183 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4184 | ||
4185 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4186 | REG_NOTES (insn) = | |
4187 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4188 | |
9db1d521 | 4189 | DONE; |
10bbf137 | 4190 | }) |
9db1d521 HP |
4191 | |
4192 | (define_insn "udivmodtidi3" | |
4023fb28 | 4193 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
c7453384 | 4194 | (ior:TI (zero_extend:TI |
4023fb28 UW |
4195 | (truncate:DI |
4196 | (udiv:TI (match_operand:TI 1 "register_operand" "0,0") | |
4197 | (zero_extend:TI | |
4198 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) | |
4199 | (ashift:TI | |
4200 | (zero_extend:TI | |
4201 | (truncate:DI | |
4202 | (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2))))) | |
4203 | (const_int 64))))] | |
9db1d521 HP |
4204 | "TARGET_64BIT" |
4205 | "@ | |
d40c829f UW |
4206 | dlgr\t%0,%2 |
4207 | dlg\t%0,%2" | |
d3632d41 | 4208 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4209 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4210 | |
4211 | ; | |
4023fb28 | 4212 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4213 | ; |
4214 | ||
4023fb28 UW |
4215 | (define_expand "divmodsi4" |
4216 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4217 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4218 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4219 | (set (match_operand:SI 3 "general_operand" "") | |
4220 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4221 | (clobber (match_dup 4))] | |
9db1d521 | 4222 | "!TARGET_64BIT" |
9db1d521 | 4223 | { |
4023fb28 UW |
4224 | rtx insn, div_equal, mod_equal, equal; |
4225 | ||
4226 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4227 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4228 | equal = gen_rtx_IOR (DImode, | |
4229 | gen_rtx_ZERO_EXTEND (DImode, div_equal), | |
4230 | gen_rtx_ASHIFT (DImode, | |
4231 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
4232 | GEN_INT (32))); | |
4233 | ||
4234 | operands[4] = gen_reg_rtx(DImode); | |
4235 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4236 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4237 | REG_NOTES (insn) = | |
4238 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4239 | ||
4240 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4241 | REG_NOTES (insn) = | |
4242 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4243 | ||
4244 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4245 | REG_NOTES (insn) = | |
4246 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4247 | |
9db1d521 | 4248 | DONE; |
10bbf137 | 4249 | }) |
9db1d521 HP |
4250 | |
4251 | (define_insn "divmoddisi3" | |
4023fb28 UW |
4252 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
4253 | (ior:DI (zero_extend:DI | |
4254 | (truncate:SI | |
4255 | (div:DI (match_operand:DI 1 "register_operand" "0,0") | |
c7453384 | 4256 | (sign_extend:DI |
d3632d41 | 4257 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4023fb28 UW |
4258 | (ashift:DI |
4259 | (zero_extend:DI | |
4260 | (truncate:SI | |
4261 | (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2))))) | |
4262 | (const_int 32))))] | |
9db1d521 HP |
4263 | "!TARGET_64BIT" |
4264 | "@ | |
d40c829f UW |
4265 | dr\t%0,%2 |
4266 | d\t%0,%2" | |
9db1d521 | 4267 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4268 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4269 | |
4270 | ; | |
4271 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4272 | ; | |
4273 | ||
4023fb28 | 4274 | |
9db1d521 HP |
4275 | (define_expand "udivsi3" |
4276 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4277 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4278 | (match_operand:SI 2 "general_operand" ""))) |
4279 | (clobber (match_dup 3))] | |
9db1d521 | 4280 | "!TARGET_64BIT" |
9db1d521 | 4281 | { |
4023fb28 UW |
4282 | rtx insn, udiv_equal, umod_equal, equal; |
4283 | ||
4284 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4285 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4286 | equal = gen_rtx_IOR (DImode, | |
4287 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal), | |
4288 | gen_rtx_ASHIFT (DImode, | |
4289 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
4290 | GEN_INT (32))); | |
9db1d521 | 4291 | |
4023fb28 | 4292 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4293 | |
4294 | if (CONSTANT_P (operands[2])) | |
4295 | { | |
4296 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4297 | { | |
4298 | rtx label1 = gen_label_rtx (); | |
4299 | ||
4023fb28 UW |
4300 | operands[1] = make_safe_from (operands[1], operands[0]); |
4301 | emit_move_insn (operands[0], const0_rtx); | |
4302 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4303 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4304 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4305 | emit_label (label1); |
4306 | } | |
4307 | else | |
4308 | { | |
c7453384 EC |
4309 | operands[2] = force_reg (SImode, operands[2]); |
4310 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4311 | |
4312 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4313 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4314 | operands[2])); | |
4315 | REG_NOTES (insn) = | |
4316 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4317 | |
4318 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4319 | gen_lowpart (SImode, operands[3])); |
4320 | REG_NOTES (insn) = | |
c7453384 | 4321 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4322 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4323 | } |
4324 | } | |
4325 | else | |
c7453384 | 4326 | { |
9db1d521 HP |
4327 | rtx label1 = gen_label_rtx (); |
4328 | rtx label2 = gen_label_rtx (); | |
4329 | rtx label3 = gen_label_rtx (); | |
4330 | ||
c7453384 EC |
4331 | operands[1] = force_reg (SImode, operands[1]); |
4332 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4333 | operands[2] = force_reg (SImode, operands[2]); | |
4334 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4335 | |
4336 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4337 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4338 | emit_jump_insn (gen_bgtu (label3)); | |
4339 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4340 | emit_jump_insn (gen_blt (label2)); | |
4341 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4342 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4343 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4344 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4345 | operands[2])); | |
4346 | REG_NOTES (insn) = | |
4347 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4348 | |
4349 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4350 | gen_lowpart (SImode, operands[3])); |
4351 | REG_NOTES (insn) = | |
c7453384 | 4352 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4353 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4354 | emit_jump (label3); |
9db1d521 | 4355 | emit_label (label1); |
4023fb28 | 4356 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4357 | emit_jump (label3); |
9db1d521 | 4358 | emit_label (label2); |
4023fb28 | 4359 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4360 | emit_label (label3); |
4361 | } | |
c7453384 | 4362 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4363 | DONE; |
10bbf137 | 4364 | }) |
9db1d521 HP |
4365 | |
4366 | (define_expand "umodsi3" | |
4367 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4368 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4369 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4370 | (clobber (match_dup 3))] | |
9db1d521 | 4371 | "!TARGET_64BIT" |
9db1d521 | 4372 | { |
4023fb28 UW |
4373 | rtx insn, udiv_equal, umod_equal, equal; |
4374 | ||
4375 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4376 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4377 | equal = gen_rtx_IOR (DImode, | |
4378 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal), | |
4379 | gen_rtx_ASHIFT (DImode, | |
4380 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
4381 | GEN_INT (32))); | |
9db1d521 | 4382 | |
4023fb28 | 4383 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4384 | |
4385 | if (CONSTANT_P (operands[2])) | |
4386 | { | |
4387 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4388 | { | |
4389 | rtx label1 = gen_label_rtx (); | |
4390 | ||
4023fb28 UW |
4391 | operands[1] = make_safe_from (operands[1], operands[0]); |
4392 | emit_move_insn (operands[0], operands[1]); | |
4393 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 4394 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
4395 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4396 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
4397 | emit_label (label1); |
4398 | } | |
4399 | else | |
4400 | { | |
c7453384 EC |
4401 | operands[2] = force_reg (SImode, operands[2]); |
4402 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4403 | |
4404 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4405 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4406 | operands[2])); | |
4407 | REG_NOTES (insn) = | |
4408 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4409 | |
4410 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4411 | gen_highpart (SImode, operands[3])); |
4412 | REG_NOTES (insn) = | |
c7453384 | 4413 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4414 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
4415 | } |
4416 | } | |
4417 | else | |
4418 | { | |
4419 | rtx label1 = gen_label_rtx (); | |
4420 | rtx label2 = gen_label_rtx (); | |
4421 | rtx label3 = gen_label_rtx (); | |
4422 | ||
c7453384 EC |
4423 | operands[1] = force_reg (SImode, operands[1]); |
4424 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4425 | operands[2] = force_reg (SImode, operands[2]); | |
4426 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 4427 | |
c7453384 | 4428 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 4429 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 HP |
4430 | emit_jump_insn (gen_bgtu (label3)); |
4431 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4432 | emit_jump_insn (gen_blt (label2)); | |
4433 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4434 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4435 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4436 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4437 | operands[2])); | |
4438 | REG_NOTES (insn) = | |
4439 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4440 | |
4441 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4442 | gen_highpart (SImode, operands[3])); |
4443 | REG_NOTES (insn) = | |
c7453384 | 4444 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4445 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 4446 | emit_jump (label3); |
9db1d521 | 4447 | emit_label (label1); |
4023fb28 | 4448 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 4449 | emit_jump (label3); |
9db1d521 | 4450 | emit_label (label2); |
4023fb28 | 4451 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
4452 | emit_label (label3); |
4453 | } | |
9db1d521 | 4454 | DONE; |
10bbf137 | 4455 | }) |
9db1d521 HP |
4456 | |
4457 | ; | |
4458 | ; divdf3 instruction pattern(s). | |
4459 | ; | |
4460 | ||
4461 | (define_expand "divdf3" | |
4462 | [(parallel | |
4023fb28 UW |
4463 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4464 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4465 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4466 | (clobber (reg:CC 33))])] |
4467 | "TARGET_HARD_FLOAT" | |
4468 | "") | |
4469 | ||
4470 | (define_insn "*divdf3" | |
4023fb28 UW |
4471 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4472 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4473 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4474 | (clobber (reg:CC 33))] |
4475 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4476 | "@ | |
d40c829f UW |
4477 | ddbr\t%0,%2 |
4478 | ddb\t%0,%2" | |
ce50cae8 | 4479 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4480 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
4481 | |
4482 | (define_insn "*divdf3_ibm" | |
4023fb28 UW |
4483 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4484 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4485 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4486 | (clobber (reg:CC 33))] |
4487 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4488 | "@ | |
d40c829f UW |
4489 | ddr\t%0,%2 |
4490 | dd\t%0,%2" | |
9db1d521 | 4491 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4492 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
4493 | |
4494 | ; | |
4495 | ; divsf3 instruction pattern(s). | |
4496 | ; | |
4497 | ||
4498 | (define_expand "divsf3" | |
4499 | [(parallel | |
4023fb28 UW |
4500 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4501 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4502 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4503 | (clobber (reg:CC 33))])] |
4504 | "TARGET_HARD_FLOAT" | |
4505 | "") | |
4506 | ||
4507 | (define_insn "*divsf3" | |
4023fb28 UW |
4508 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4509 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4510 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4511 | (clobber (reg:CC 33))] |
4512 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4513 | "@ | |
d40c829f UW |
4514 | debr\t%0,%2 |
4515 | deb\t%0,%2" | |
ce50cae8 | 4516 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4517 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
4518 | |
4519 | (define_insn "*divsf3" | |
4023fb28 UW |
4520 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4521 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4522 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4523 | (clobber (reg:CC 33))] |
4524 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4525 | "@ | |
d40c829f UW |
4526 | der\t%0,%2 |
4527 | de\t%0,%2" | |
9db1d521 | 4528 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4529 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
4530 | |
4531 | ||
4532 | ;; | |
4533 | ;;- And instructions. | |
4534 | ;; | |
4535 | ||
4536 | ; | |
4537 | ; anddi3 instruction pattern(s). | |
4538 | ; | |
4539 | ||
4540 | (define_insn "*anddi3_cc" | |
4541 | [(set (reg 33) | |
96fd3851 | 4542 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4543 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 4544 | (const_int 0))) |
4023fb28 | 4545 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
4546 | (and:DI (match_dup 1) (match_dup 2)))] |
4547 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4548 | "@ | |
d40c829f UW |
4549 | ngr\t%0,%2 |
4550 | ng\t%0,%2" | |
d3632d41 | 4551 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
4552 | |
4553 | (define_insn "*anddi3_cconly" | |
4554 | [(set (reg 33) | |
96fd3851 | 4555 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4556 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
4557 | (const_int 0))) |
4558 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4559 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4560 | "@ | |
d40c829f UW |
4561 | ngr\t%0,%2 |
4562 | ng\t%0,%2" | |
d3632d41 | 4563 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 4564 | |
4023fb28 UW |
4565 | (define_insn "*anddi3_ni" |
4566 | [(set (match_operand:DI 0 "register_operand" "=d") | |
05b9aaaa | 4567 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
4023fb28 UW |
4568 | (match_operand:DI 2 "immediate_operand" "n"))) |
4569 | (clobber (reg:CC 33))] | |
4570 | "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0" | |
4023fb28 UW |
4571 | { |
4572 | int part = s390_single_hi (operands[2], DImode, -1); | |
4573 | operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); | |
4574 | ||
4575 | switch (part) | |
4576 | { | |
d40c829f UW |
4577 | case 0: return "nihh\t%0,%x2"; |
4578 | case 1: return "nihl\t%0,%x2"; | |
4579 | case 2: return "nilh\t%0,%x2"; | |
4580 | case 3: return "nill\t%0,%x2"; | |
4023fb28 UW |
4581 | default: abort (); |
4582 | } | |
10bbf137 | 4583 | } |
077dab3b | 4584 | [(set_attr "op_type" "RI")]) |
4023fb28 | 4585 | |
9db1d521 | 4586 | (define_insn "anddi3" |
4023fb28 | 4587 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
96fd3851 | 4588 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4589 | (match_operand:DI 2 "general_operand" "d,m"))) |
9db1d521 HP |
4590 | (clobber (reg:CC 33))] |
4591 | "TARGET_64BIT" | |
4592 | "@ | |
d40c829f UW |
4593 | ngr\t%0,%2 |
4594 | ng\t%0,%2" | |
d3632d41 | 4595 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
4596 | |
4597 | (define_insn "*anddi3_ss" | |
ccfc6cc8 | 4598 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 4599 | (and:DI (match_dup 0) |
ccfc6cc8 | 4600 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
4601 | (clobber (reg:CC 33))] |
4602 | "" | |
d40c829f | 4603 | "nc\t%O0(8,%R0),%1" |
077dab3b | 4604 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
4605 | |
4606 | (define_insn "*anddi3_ss_inv" | |
ccfc6cc8 UW |
4607 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4608 | (and:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
4609 | (match_dup 0))) |
4610 | (clobber (reg:CC 33))] | |
4611 | "" | |
d40c829f | 4612 | "nc\t%O0(8,%R0),%1" |
077dab3b | 4613 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
4614 | |
4615 | ; | |
4616 | ; andsi3 instruction pattern(s). | |
4617 | ; | |
4618 | ||
4619 | (define_insn "*andsi3_cc" | |
4620 | [(set (reg 33) | |
d3632d41 UW |
4621 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4622 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4623 | (const_int 0))) |
d3632d41 | 4624 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 HP |
4625 | (and:SI (match_dup 1) (match_dup 2)))] |
4626 | "s390_match_ccmode(insn, CCTmode)" | |
4627 | "@ | |
d40c829f UW |
4628 | nr\t%0,%2 |
4629 | n\t%0,%2 | |
4630 | ny\t%0,%2" | |
d3632d41 | 4631 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
4632 | |
4633 | (define_insn "*andsi3_cconly" | |
4634 | [(set (reg 33) | |
d3632d41 UW |
4635 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4636 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4637 | (const_int 0))) |
d3632d41 | 4638 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
9db1d521 HP |
4639 | "s390_match_ccmode(insn, CCTmode)" |
4640 | "@ | |
d40c829f UW |
4641 | nr\t%0,%2 |
4642 | n\t%0,%2 | |
4643 | ny\t%0,%2" | |
d3632d41 | 4644 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4645 | |
4023fb28 UW |
4646 | (define_insn "*andsi3_ni" |
4647 | [(set (match_operand:SI 0 "register_operand" "=d") | |
05b9aaaa | 4648 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
4023fb28 UW |
4649 | (match_operand:SI 2 "immediate_operand" "n"))) |
4650 | (clobber (reg:CC 33))] | |
4651 | "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0" | |
4023fb28 UW |
4652 | { |
4653 | int part = s390_single_hi (operands[2], SImode, -1); | |
4654 | operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); | |
4655 | ||
4656 | switch (part) | |
4657 | { | |
d40c829f UW |
4658 | case 0: return "nilh\t%0,%x2"; |
4659 | case 1: return "nill\t%0,%x2"; | |
4023fb28 UW |
4660 | default: abort (); |
4661 | } | |
10bbf137 | 4662 | } |
077dab3b | 4663 | [(set_attr "op_type" "RI")]) |
4023fb28 | 4664 | |
9db1d521 | 4665 | (define_insn "andsi3" |
d3632d41 UW |
4666 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4667 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
4668 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
4669 | (clobber (reg:CC 33))] |
4670 | "" | |
4671 | "@ | |
d40c829f UW |
4672 | nr\t%0,%2 |
4673 | n\t%0,%2 | |
4674 | ny\t%0,%2" | |
d3632d41 | 4675 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
4676 | |
4677 | (define_insn "*andsi3_ss" | |
ccfc6cc8 | 4678 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 4679 | (and:SI (match_dup 0) |
ccfc6cc8 | 4680 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
4681 | (clobber (reg:CC 33))] |
4682 | "" | |
d40c829f | 4683 | "nc\t%O0(4,%R0),%1" |
077dab3b | 4684 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
4685 | |
4686 | (define_insn "*andsi3_ss_inv" | |
ccfc6cc8 UW |
4687 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4688 | (and:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
4689 | (match_dup 0))) |
4690 | (clobber (reg:CC 33))] | |
4691 | "" | |
d40c829f | 4692 | "nc\t%O0(4,%R0),%1" |
077dab3b | 4693 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
4694 | |
4695 | ; | |
4696 | ; andhi3 instruction pattern(s). | |
4697 | ; | |
4698 | ||
4023fb28 UW |
4699 | (define_insn "*andhi3_ni" |
4700 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
4701 | (and:HI (match_operand:HI 1 "register_operand" "%0,0") | |
4702 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
4703 | (clobber (reg:CC 33))] | |
4704 | "TARGET_64BIT" | |
4705 | "@ | |
d40c829f UW |
4706 | nr\t%0,%2 |
4707 | nill\t%0,%x2" | |
077dab3b | 4708 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 UW |
4709 | |
4710 | (define_insn "andhi3" | |
4711 | [(set (match_operand:HI 0 "register_operand" "=d") | |
4712 | (and:HI (match_operand:HI 1 "register_operand" "%0") | |
4713 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
4714 | (clobber (reg:CC 33))] | |
9db1d521 | 4715 | "" |
d40c829f | 4716 | "nr\t%0,%2" |
077dab3b | 4717 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
4718 | |
4719 | (define_insn "*andhi3_ss" | |
ccfc6cc8 | 4720 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 4721 | (and:HI (match_dup 0) |
ccfc6cc8 | 4722 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
4723 | (clobber (reg:CC 33))] |
4724 | "" | |
d40c829f | 4725 | "nc\t%O0(2,%R0),%1" |
077dab3b | 4726 | [(set_attr "op_type" "SS")]) |
9db1d521 | 4727 | |
4023fb28 | 4728 | (define_insn "*andhi3_ss_inv" |
ccfc6cc8 UW |
4729 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4730 | (and:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 4731 | (match_dup 0))) |
9db1d521 HP |
4732 | (clobber (reg:CC 33))] |
4733 | "" | |
d40c829f | 4734 | "nc\t%O0(2,%R0),%1" |
077dab3b | 4735 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
4736 | |
4737 | ; | |
4738 | ; andqi3 instruction pattern(s). | |
4739 | ; | |
4740 | ||
4023fb28 UW |
4741 | (define_insn "*andqi3_ni" |
4742 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
4743 | (and:QI (match_operand:QI 1 "register_operand" "%0,0") | |
4744 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
4745 | (clobber (reg:CC 33))] | |
4746 | "TARGET_64BIT" | |
4747 | "@ | |
d40c829f UW |
4748 | nr\t%0,%2 |
4749 | nill\t%0,%b2" | |
077dab3b | 4750 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 | 4751 | |
9db1d521 | 4752 | (define_insn "andqi3" |
4023fb28 UW |
4753 | [(set (match_operand:QI 0 "register_operand" "=d") |
4754 | (and:QI (match_operand:QI 1 "register_operand" "%0") | |
4755 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
4756 | (clobber (reg:CC 33))] | |
4757 | "" | |
d40c829f | 4758 | "nr\t%0,%2" |
077dab3b | 4759 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
4760 | |
4761 | (define_insn "*andqi3_ss" | |
d3632d41 | 4762 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 4763 | (and:QI (match_dup 0) |
d3632d41 | 4764 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
4765 | (clobber (reg:CC 33))] |
4766 | "" | |
4767 | "@ | |
d40c829f UW |
4768 | ni\t%0,%b1 |
4769 | niy\t%0,%b1 | |
4770 | nc\t%O0(1,%R0),%1" | |
d3632d41 | 4771 | [(set_attr "op_type" "SI,SIY,SS")]) |
4023fb28 UW |
4772 | |
4773 | (define_insn "*andqi3_ss_inv" | |
d3632d41 UW |
4774 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4775 | (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 UW |
4776 | (match_dup 0))) |
4777 | (clobber (reg:CC 33))] | |
4778 | "" | |
4779 | "@ | |
d40c829f UW |
4780 | ni\t%0,%b1 |
4781 | niy\t%0,%b1 | |
4782 | nc\t%O0(1,%R0),%1" | |
d3632d41 | 4783 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
4784 | |
4785 | ||
4786 | ;; | |
4787 | ;;- Bit set (inclusive or) instructions. | |
4788 | ;; | |
4789 | ||
4790 | ; | |
4791 | ; iordi3 instruction pattern(s). | |
4792 | ; | |
4793 | ||
4023fb28 UW |
4794 | (define_insn "*iordi3_cc" |
4795 | [(set (reg 33) | |
96fd3851 | 4796 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
4797 | (match_operand:DI 2 "general_operand" "d,m")) |
4798 | (const_int 0))) | |
4799 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4800 | (ior:DI (match_dup 1) (match_dup 2)))] | |
4801 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4802 | "@ | |
d40c829f UW |
4803 | ogr\t%0,%2 |
4804 | og\t%0,%2" | |
d3632d41 | 4805 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
4806 | |
4807 | (define_insn "*iordi3_cconly" | |
4808 | [(set (reg 33) | |
96fd3851 | 4809 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
4810 | (match_operand:DI 2 "general_operand" "d,m")) |
4811 | (const_int 0))) | |
4812 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4813 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4814 | "@ | |
d40c829f UW |
4815 | ogr\t%0,%2 |
4816 | og\t%0,%2" | |
d3632d41 | 4817 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
4818 | |
4819 | (define_insn "*iordi3_oi" | |
4820 | [(set (match_operand:DI 0 "register_operand" "=d") | |
c707d0b0 | 4821 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
4023fb28 UW |
4822 | (match_operand:DI 2 "immediate_operand" "n"))) |
4823 | (clobber (reg:CC 33))] | |
4824 | "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0" | |
4023fb28 UW |
4825 | { |
4826 | int part = s390_single_hi (operands[2], DImode, 0); | |
4827 | operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); | |
4828 | ||
4829 | switch (part) | |
4830 | { | |
d40c829f UW |
4831 | case 0: return "oihh\t%0,%x2"; |
4832 | case 1: return "oihl\t%0,%x2"; | |
4833 | case 2: return "oilh\t%0,%x2"; | |
4834 | case 3: return "oill\t%0,%x2"; | |
4023fb28 UW |
4835 | default: abort (); |
4836 | } | |
10bbf137 | 4837 | } |
077dab3b | 4838 | [(set_attr "op_type" "RI")]) |
4023fb28 | 4839 | |
9db1d521 | 4840 | (define_insn "iordi3" |
4023fb28 | 4841 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
96fd3851 | 4842 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4843 | (match_operand:DI 2 "general_operand" "d,m"))) |
9db1d521 HP |
4844 | (clobber (reg:CC 33))] |
4845 | "TARGET_64BIT" | |
4846 | "@ | |
d40c829f UW |
4847 | ogr\t%0,%2 |
4848 | og\t%0,%2" | |
d3632d41 | 4849 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
4850 | |
4851 | (define_insn "*iordi3_ss" | |
ccfc6cc8 | 4852 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 4853 | (ior:DI (match_dup 0) |
ccfc6cc8 | 4854 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
4855 | (clobber (reg:CC 33))] |
4856 | "" | |
d40c829f | 4857 | "oc\t%O0(8,%R0),%1" |
077dab3b | 4858 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
4859 | |
4860 | (define_insn "*iordi3_ss_inv" | |
ccfc6cc8 UW |
4861 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4862 | (ior:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
4863 | (match_dup 0))) |
4864 | (clobber (reg:CC 33))] | |
4865 | "" | |
d40c829f | 4866 | "oc\t%O0(8,%R0),%1" |
077dab3b | 4867 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
4868 | |
4869 | ; | |
4870 | ; iorsi3 instruction pattern(s). | |
4871 | ; | |
4872 | ||
4023fb28 UW |
4873 | (define_insn "*iorsi3_cc" |
4874 | [(set (reg 33) | |
d3632d41 UW |
4875 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4876 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 4877 | (const_int 0))) |
d3632d41 | 4878 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
4879 | (ior:SI (match_dup 1) (match_dup 2)))] |
4880 | "s390_match_ccmode(insn, CCTmode)" | |
4881 | "@ | |
d40c829f UW |
4882 | or\t%0,%2 |
4883 | o\t%0,%2 | |
4884 | oy\t%0,%2" | |
d3632d41 | 4885 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
4886 | |
4887 | (define_insn "*iorsi3_cconly" | |
4888 | [(set (reg 33) | |
d3632d41 UW |
4889 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4890 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 4891 | (const_int 0))) |
d3632d41 | 4892 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
4893 | "s390_match_ccmode(insn, CCTmode)" |
4894 | "@ | |
d40c829f UW |
4895 | or\t%0,%2 |
4896 | o\t%0,%2 | |
4897 | oy\t%0,%2" | |
d3632d41 | 4898 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
4899 | |
4900 | (define_insn "*iorsi3_oi" | |
4901 | [(set (match_operand:SI 0 "register_operand" "=d") | |
c707d0b0 | 4902 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
4023fb28 UW |
4903 | (match_operand:SI 2 "immediate_operand" "n"))) |
4904 | (clobber (reg:CC 33))] | |
4905 | "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0" | |
4023fb28 UW |
4906 | { |
4907 | int part = s390_single_hi (operands[2], SImode, 0); | |
4908 | operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); | |
4909 | ||
4910 | switch (part) | |
4911 | { | |
d40c829f UW |
4912 | case 0: return "oilh\t%0,%x2"; |
4913 | case 1: return "oill\t%0,%x2"; | |
4023fb28 UW |
4914 | default: abort (); |
4915 | } | |
10bbf137 | 4916 | } |
077dab3b | 4917 | [(set_attr "op_type" "RI")]) |
4023fb28 UW |
4918 | |
4919 | (define_insn "iorsi3" | |
d3632d41 UW |
4920 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4921 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
4922 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4023fb28 UW |
4923 | (clobber (reg:CC 33))] |
4924 | "" | |
4925 | "@ | |
d40c829f UW |
4926 | or\t%0,%2 |
4927 | o\t%0,%2 | |
4928 | oy\t%0,%2" | |
d3632d41 | 4929 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
4930 | |
4931 | (define_insn "*iorsi3_ss" | |
ccfc6cc8 | 4932 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 4933 | (ior:SI (match_dup 0) |
ccfc6cc8 | 4934 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
4935 | (clobber (reg:CC 33))] |
4936 | "" | |
d40c829f | 4937 | "oc\t%O0(4,%R0),%1" |
077dab3b | 4938 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
4939 | |
4940 | (define_insn "*iorsi3_ss_inv" | |
ccfc6cc8 UW |
4941 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4942 | (ior:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
4943 | (match_dup 0))) |
4944 | (clobber (reg:CC 33))] | |
4945 | "" | |
d40c829f | 4946 | "oc\t%O0(4,%R0),%1" |
077dab3b | 4947 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
4948 | |
4949 | ; | |
4950 | ; iorhi3 instruction pattern(s). | |
4951 | ; | |
4952 | ||
4953 | (define_insn "*iorhi3_oi" | |
4954 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
4955 | (ior:HI (match_operand:HI 1 "register_operand" "%0,0") | |
4956 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
4957 | (clobber (reg:CC 33))] | |
4958 | "TARGET_64BIT" | |
4959 | "@ | |
d40c829f UW |
4960 | or\t%0,%2 |
4961 | oill\t%0,%x2" | |
077dab3b | 4962 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 UW |
4963 | |
4964 | (define_insn "iorhi3" | |
4965 | [(set (match_operand:HI 0 "register_operand" "=d") | |
4966 | (ior:HI (match_operand:HI 1 "register_operand" "%0") | |
4967 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
4968 | (clobber (reg:CC 33))] | |
9db1d521 | 4969 | "" |
d40c829f | 4970 | "or\t%0,%2" |
077dab3b | 4971 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
4972 | |
4973 | (define_insn "*iorhi3_ss" | |
ccfc6cc8 | 4974 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 4975 | (ior:HI (match_dup 0) |
ccfc6cc8 | 4976 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
4977 | (clobber (reg:CC 33))] |
4978 | "" | |
d40c829f | 4979 | "oc\t%O0(2,%R0),%1" |
077dab3b | 4980 | [(set_attr "op_type" "SS")]) |
9db1d521 | 4981 | |
4023fb28 | 4982 | (define_insn "*iorhi3_ss_inv" |
ccfc6cc8 UW |
4983 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4984 | (ior:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 4985 | (match_dup 0))) |
9db1d521 HP |
4986 | (clobber (reg:CC 33))] |
4987 | "" | |
d40c829f | 4988 | "oc\t%O0(2,%R0),%1" |
077dab3b | 4989 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
4990 | |
4991 | ; | |
4023fb28 | 4992 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
4993 | ; |
4994 | ||
4023fb28 UW |
4995 | (define_insn "*iorqi3_oi" |
4996 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
4997 | (ior:QI (match_operand:QI 1 "register_operand" "%0,0") | |
4998 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
4999 | (clobber (reg:CC 33))] | |
5000 | "TARGET_64BIT" | |
5001 | "@ | |
d40c829f UW |
5002 | or\t%0,%2 |
5003 | oill\t%0,%b2" | |
077dab3b | 5004 | [(set_attr "op_type" "RR,RI")]) |
9db1d521 | 5005 | |
4023fb28 UW |
5006 | (define_insn "iorqi3" |
5007 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5008 | (ior:QI (match_operand:QI 1 "register_operand" "%0") | |
5009 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5010 | (clobber (reg:CC 33))] | |
5011 | "" | |
d40c829f | 5012 | "or\t%0,%2" |
077dab3b | 5013 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5014 | |
5015 | (define_insn "*iorqi3_ss" | |
d3632d41 | 5016 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5017 | (ior:QI (match_dup 0) |
d3632d41 | 5018 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5019 | (clobber (reg:CC 33))] |
5020 | "" | |
5021 | "@ | |
d40c829f UW |
5022 | oi\t%0,%b1 |
5023 | oiy\t%0,%b1 | |
5024 | oc\t%O0(1,%R0),%1" | |
d3632d41 | 5025 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 | 5026 | |
4023fb28 | 5027 | (define_insn "*iorqi3_ss_inv" |
d3632d41 UW |
5028 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5029 | (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 | 5030 | (match_dup 0))) |
9db1d521 HP |
5031 | (clobber (reg:CC 33))] |
5032 | "" | |
5033 | "@ | |
d40c829f UW |
5034 | oi\t%0,%b1 |
5035 | oiy\t%0,%b1 | |
5036 | oc\t%O0(1,%R0),%1" | |
d3632d41 | 5037 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5038 | |
5039 | ||
5040 | ;; | |
5041 | ;;- Xor instructions. | |
5042 | ;; | |
5043 | ||
5044 | ; | |
5045 | ; xordi3 instruction pattern(s). | |
5046 | ; | |
5047 | ||
4023fb28 UW |
5048 | (define_insn "*xordi3_cc" |
5049 | [(set (reg 33) | |
96fd3851 | 5050 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5051 | (match_operand:DI 2 "general_operand" "d,m")) |
5052 | (const_int 0))) | |
5053 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5054 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5055 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5056 | "@ | |
d40c829f UW |
5057 | xgr\t%0,%2 |
5058 | xg\t%0,%2" | |
d3632d41 | 5059 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5060 | |
5061 | (define_insn "*xordi3_cconly" | |
5062 | [(set (reg 33) | |
96fd3851 | 5063 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5064 | (match_operand:DI 2 "general_operand" "d,m")) |
5065 | (const_int 0))) | |
5066 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5067 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5068 | "@ | |
d40c829f UW |
5069 | xgr\t%0,%2 |
5070 | xr\t%0,%2" | |
d3632d41 | 5071 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5072 | |
9db1d521 | 5073 | (define_insn "xordi3" |
4023fb28 | 5074 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
96fd3851 | 5075 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5076 | (match_operand:DI 2 "general_operand" "d,m"))) |
9db1d521 HP |
5077 | (clobber (reg:CC 33))] |
5078 | "TARGET_64BIT" | |
5079 | "@ | |
d40c829f UW |
5080 | xgr\t%0,%2 |
5081 | xg\t%0,%2" | |
d3632d41 | 5082 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5083 | |
5084 | (define_insn "*xordi3_ss" | |
ccfc6cc8 | 5085 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5086 | (xor:DI (match_dup 0) |
ccfc6cc8 | 5087 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5088 | (clobber (reg:CC 33))] |
5089 | "" | |
d40c829f | 5090 | "xc\t%O0(8,%R0),%1" |
077dab3b | 5091 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5092 | |
5093 | (define_insn "*xordi3_ss_inv" | |
ccfc6cc8 UW |
5094 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5095 | (xor:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5096 | (match_dup 0))) |
5097 | (clobber (reg:CC 33))] | |
5098 | "" | |
d40c829f | 5099 | "xc\t%O0(8,%R0),%1" |
077dab3b | 5100 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5101 | |
5102 | ; | |
5103 | ; xorsi3 instruction pattern(s). | |
5104 | ; | |
5105 | ||
4023fb28 UW |
5106 | (define_insn "*xorsi3_cc" |
5107 | [(set (reg 33) | |
d3632d41 UW |
5108 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5109 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5110 | (const_int 0))) |
d3632d41 | 5111 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5112 | (xor:SI (match_dup 1) (match_dup 2)))] |
5113 | "s390_match_ccmode(insn, CCTmode)" | |
5114 | "@ | |
d40c829f UW |
5115 | xr\t%0,%2 |
5116 | x\t%0,%2 | |
5117 | xy\t%0,%2" | |
d3632d41 | 5118 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5119 | |
5120 | (define_insn "*xorsi3_cconly" | |
5121 | [(set (reg 33) | |
d3632d41 UW |
5122 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5123 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5124 | (const_int 0))) |
d3632d41 | 5125 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5126 | "s390_match_ccmode(insn, CCTmode)" |
5127 | "@ | |
d40c829f UW |
5128 | xr\t%0,%2 |
5129 | x\t%0,%2 | |
5130 | xy\t%0,%2" | |
d3632d41 | 5131 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5132 | |
4023fb28 | 5133 | (define_insn "xorsi3" |
d3632d41 UW |
5134 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
5135 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
5136 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
5137 | (clobber (reg:CC 33))] |
5138 | "" | |
5139 | "@ | |
d40c829f UW |
5140 | xr\t%0,%2 |
5141 | x\t%0,%2 | |
5142 | xy\t%0,%2" | |
d3632d41 | 5143 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5144 | |
5145 | (define_insn "*xorsi3_ss" | |
ccfc6cc8 | 5146 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5147 | (xor:SI (match_dup 0) |
ccfc6cc8 | 5148 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5149 | (clobber (reg:CC 33))] |
5150 | "" | |
d40c829f | 5151 | "xc\t%O0(4,%R0),%1" |
077dab3b | 5152 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5153 | |
5154 | (define_insn "*xorsi3_ss_inv" | |
ccfc6cc8 UW |
5155 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5156 | (xor:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5157 | (match_dup 0))) |
5158 | (clobber (reg:CC 33))] | |
5159 | "" | |
d40c829f | 5160 | "xc\t%O0(4,%R0),%1" |
077dab3b | 5161 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5162 | |
5163 | ; | |
5164 | ; xorhi3 instruction pattern(s). | |
5165 | ; | |
5166 | ||
4023fb28 UW |
5167 | (define_insn "xorhi3" |
5168 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5169 | (xor:HI (match_operand:HI 1 "register_operand" "%0") | |
5170 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5171 | (clobber (reg:CC 33))] | |
9db1d521 | 5172 | "" |
d40c829f | 5173 | "xr\t%0,%2" |
d3632d41 | 5174 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5175 | |
5176 | (define_insn "*xorhi3_ss" | |
ccfc6cc8 | 5177 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5178 | (xor:HI (match_dup 0) |
ccfc6cc8 | 5179 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5180 | (clobber (reg:CC 33))] |
5181 | "" | |
d40c829f | 5182 | "xc\t%O0(2,%R0),%1" |
077dab3b | 5183 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5184 | |
4023fb28 | 5185 | (define_insn "*xorhi3_ss_inv" |
ccfc6cc8 UW |
5186 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5187 | (xor:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5188 | (match_dup 0))) |
9db1d521 HP |
5189 | (clobber (reg:CC 33))] |
5190 | "" | |
d40c829f | 5191 | "xc\t%O0(2,%R0),%1" |
077dab3b | 5192 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5193 | |
5194 | ; | |
5195 | ; xorqi3 instruction pattern(s). | |
5196 | ; | |
5197 | ||
5198 | (define_insn "xorqi3" | |
4023fb28 UW |
5199 | [(set (match_operand:QI 0 "register_operand" "=d") |
5200 | (xor:QI (match_operand:QI 1 "register_operand" "%0") | |
5201 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5202 | (clobber (reg:CC 33))] | |
5203 | "" | |
d40c829f | 5204 | "xr\t%0,%2" |
077dab3b | 5205 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5206 | |
5207 | (define_insn "*xorqi3_ss" | |
d3632d41 | 5208 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5209 | (xor:QI (match_dup 0) |
d3632d41 | 5210 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5211 | (clobber (reg:CC 33))] |
5212 | "" | |
5213 | "@ | |
d40c829f UW |
5214 | xi\t%0,%b1 |
5215 | xiy\t%0,%b1 | |
5216 | xc\t%O0(1,%R0),%1" | |
d3632d41 | 5217 | [(set_attr "op_type" "SI,SIY,SS")]) |
4023fb28 UW |
5218 | |
5219 | (define_insn "*xorqi3_ss_inv" | |
d3632d41 UW |
5220 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5221 | (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 UW |
5222 | (match_dup 0))) |
5223 | (clobber (reg:CC 33))] | |
5224 | "" | |
5225 | "@ | |
d40c829f UW |
5226 | xi\t%0,%b1 |
5227 | xiy\t%0,%b1 | |
5228 | xc\t%O0(1,%R0),%1" | |
d3632d41 | 5229 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5230 | |
5231 | ||
5232 | ;; | |
5233 | ;;- Negate instructions. | |
5234 | ;; | |
5235 | ||
5236 | ; | |
5237 | ; negdi2 instruction pattern(s). | |
5238 | ; | |
5239 | ||
5240 | (define_expand "negdi2" | |
5241 | [(parallel | |
5242 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5243 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5244 | (clobber (reg:CC 33))])] | |
5245 | "" | |
5246 | "") | |
5247 | ||
5248 | (define_insn "*negdi2_64" | |
5249 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5250 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5251 | (clobber (reg:CC 33))] | |
5252 | "TARGET_64BIT" | |
d40c829f | 5253 | "lcgr\t%0,%1" |
f2d3c02a | 5254 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
5255 | |
5256 | (define_insn "*negdi2_31" | |
5257 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5258 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5259 | (clobber (reg:CC 33))] | |
5260 | "!TARGET_64BIT" | |
9db1d521 HP |
5261 | { |
5262 | rtx xop[1]; | |
5263 | xop[0] = gen_label_rtx (); | |
d40c829f UW |
5264 | output_asm_insn ("lcr\t%0,%1", operands); |
5265 | output_asm_insn ("lcr\t%N0,%N1", operands); | |
5266 | output_asm_insn ("je\t%l0", xop); | |
5267 | output_asm_insn ("bctr\t%0,0", operands); | |
47798692 | 5268 | targetm.asm_out.internal_label (asm_out_file, "L", |
9db1d521 | 5269 | CODE_LABEL_NUMBER (xop[0])); |
10bbf137 UW |
5270 | return ""; |
5271 | } | |
9db1d521 | 5272 | [(set_attr "op_type" "NN") |
4023fb28 UW |
5273 | (set_attr "type" "other") |
5274 | (set_attr "length" "10")]) | |
9db1d521 HP |
5275 | |
5276 | ; | |
5277 | ; negsi2 instruction pattern(s). | |
5278 | ; | |
5279 | ||
5280 | (define_insn "negsi2" | |
5281 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5282 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
5283 | (clobber (reg:CC 33))] | |
5284 | "" | |
d40c829f | 5285 | "lcr\t%0,%1" |
f2d3c02a | 5286 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
5287 | |
5288 | ; | |
5289 | ; negdf2 instruction pattern(s). | |
5290 | ; | |
5291 | ||
5292 | (define_expand "negdf2" | |
5293 | [(parallel | |
5294 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5295 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5296 | (clobber (reg:CC 33))])] | |
5297 | "TARGET_HARD_FLOAT" | |
5298 | "") | |
5299 | ||
5300 | (define_insn "*negdf2" | |
5301 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5302 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5303 | (clobber (reg:CC 33))] | |
5304 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5305 | "lcdbr\t%0,%1" |
077dab3b HP |
5306 | [(set_attr "op_type" "RRE") |
5307 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5308 | |
5309 | (define_insn "*negdf2_ibm" | |
5310 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5311 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5312 | (clobber (reg:CC 33))] | |
5313 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5314 | "lcdr\t%0,%1" |
077dab3b HP |
5315 | [(set_attr "op_type" "RR") |
5316 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5317 | |
5318 | ; | |
5319 | ; negsf2 instruction pattern(s). | |
5320 | ; | |
5321 | ||
5322 | (define_expand "negsf2" | |
5323 | [(parallel | |
5324 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5325 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5326 | (clobber (reg:CC 33))])] | |
5327 | "TARGET_HARD_FLOAT" | |
5328 | "") | |
5329 | ||
5330 | (define_insn "*negsf2" | |
5331 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5332 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5333 | (clobber (reg:CC 33))] | |
5334 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5335 | "lcebr\t%0,%1" |
077dab3b HP |
5336 | [(set_attr "op_type" "RRE") |
5337 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5338 | |
5339 | (define_insn "*negsf2" | |
5340 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5341 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5342 | (clobber (reg:CC 33))] | |
5343 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5344 | "lcer\t%0,%1" |
077dab3b HP |
5345 | [(set_attr "op_type" "RR") |
5346 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5347 | |
5348 | ||
5349 | ;; | |
5350 | ;;- Absolute value instructions. | |
5351 | ;; | |
5352 | ||
5353 | ; | |
5354 | ; absdi2 instruction pattern(s). | |
5355 | ; | |
5356 | ||
5357 | (define_insn "absdi2" | |
5358 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5359 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
5360 | (clobber (reg:CC 33))] | |
5361 | "TARGET_64BIT" | |
d40c829f | 5362 | "lpgr\t%0,%1" |
f2d3c02a | 5363 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
5364 | |
5365 | ; | |
5366 | ; abssi2 instruction pattern(s). | |
5367 | ; | |
5368 | ||
5369 | (define_insn "abssi2" | |
5370 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5371 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
5372 | (clobber (reg:CC 33))] | |
5373 | "" | |
d40c829f | 5374 | "lpr\t%0,%1" |
f2d3c02a | 5375 | [(set_attr "op_type" "RR")]) |
9db1d521 | 5376 | |
9db1d521 HP |
5377 | ; |
5378 | ; absdf2 instruction pattern(s). | |
5379 | ; | |
5380 | ||
5381 | (define_expand "absdf2" | |
5382 | [(parallel | |
5383 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5384 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5385 | (clobber (reg:CC 33))])] | |
5386 | "TARGET_HARD_FLOAT" | |
5387 | "") | |
5388 | ||
5389 | (define_insn "*absdf2" | |
5390 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5391 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5392 | (clobber (reg:CC 33))] | |
5393 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5394 | "lpdbr\t%0,%1" |
077dab3b HP |
5395 | [(set_attr "op_type" "RRE") |
5396 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5397 | |
5398 | (define_insn "*absdf2_ibm" | |
5399 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5400 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5401 | (clobber (reg:CC 33))] | |
5402 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5403 | "lpdr\t%0,%1" |
077dab3b HP |
5404 | [(set_attr "op_type" "RR") |
5405 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5406 | |
5407 | ; | |
5408 | ; abssf2 instruction pattern(s). | |
5409 | ; | |
5410 | ||
5411 | (define_expand "abssf2" | |
5412 | [(parallel | |
5413 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5414 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5415 | (clobber (reg:CC 33))])] | |
5416 | "TARGET_HARD_FLOAT" | |
5417 | "") | |
5418 | ||
5419 | (define_insn "*abssf2" | |
5420 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5421 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5422 | (clobber (reg:CC 33))] | |
5423 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5424 | "lpebr\t%0,%1" |
077dab3b HP |
5425 | [(set_attr "op_type" "RRE") |
5426 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5427 | |
5428 | (define_insn "*abssf2_ibm" | |
5429 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5430 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5431 | (clobber (reg:CC 33))] | |
5432 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5433 | "lper\t%0,%1" |
077dab3b HP |
5434 | [(set_attr "op_type" "RR") |
5435 | (set_attr "type" "fsimps")]) | |
9db1d521 | 5436 | |
3ef093a8 AK |
5437 | ;; |
5438 | ;;- Negated absolute value instructions | |
5439 | ;; | |
5440 | ||
5441 | ; | |
5442 | ; Integer | |
5443 | ; | |
5444 | ||
5445 | (define_insn "*negabssi2" | |
5446 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5447 | (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) | |
5448 | (clobber (reg:CC 33))] | |
5449 | "" | |
d40c829f | 5450 | "lnr\t%0,%1" |
3ef093a8 AK |
5451 | [(set_attr "op_type" "RR")]) |
5452 | ||
5453 | (define_insn "*negabsdi2" | |
5454 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5455 | (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) | |
5456 | (clobber (reg:CC 33))] | |
5457 | "TARGET_64BIT" | |
d40c829f | 5458 | "lngr\t%0,%1" |
3ef093a8 AK |
5459 | [(set_attr "op_type" "RRE")]) |
5460 | ||
5461 | ; | |
5462 | ; Floating point | |
5463 | ; | |
5464 | ||
5465 | (define_insn "*negabssf2" | |
5466 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5467 | (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) | |
5468 | (clobber (reg:CC 33))] | |
5469 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5470 | "lnebr\t%0,%1" |
3ef093a8 AK |
5471 | [(set_attr "op_type" "RRE") |
5472 | (set_attr "type" "fsimps")]) | |
5473 | ||
5474 | (define_insn "*negabsdf2" | |
5475 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5476 | (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) | |
5477 | (clobber (reg:CC 33))] | |
5478 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5479 | "lndbr\t%0,%1" |
3ef093a8 AK |
5480 | [(set_attr "op_type" "RRE") |
5481 | (set_attr "type" "fsimpd")]) | |
5482 | ||
4023fb28 UW |
5483 | ;; |
5484 | ;;- Square root instructions. | |
5485 | ;; | |
5486 | ||
5487 | ; | |
5488 | ; sqrtdf2 instruction pattern(s). | |
5489 | ; | |
5490 | ||
5491 | (define_insn "sqrtdf2" | |
5492 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 5493 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] |
4023fb28 UW |
5494 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5495 | "@ | |
d40c829f UW |
5496 | sqdbr\t%0,%1 |
5497 | sqdb\t%0,%1" | |
d3632d41 | 5498 | [(set_attr "op_type" "RRE,RXE")]) |
4023fb28 UW |
5499 | |
5500 | ; | |
5501 | ; sqrtsf2 instruction pattern(s). | |
5502 | ; | |
5503 | ||
5504 | (define_insn "sqrtsf2" | |
5505 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 5506 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] |
4023fb28 UW |
5507 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5508 | "@ | |
d40c829f UW |
5509 | sqebr\t%0,%1 |
5510 | sqeb\t%0,%1" | |
d3632d41 | 5511 | [(set_attr "op_type" "RRE,RXE")]) |
9db1d521 HP |
5512 | |
5513 | ;; | |
5514 | ;;- One complement instructions. | |
5515 | ;; | |
5516 | ||
5517 | ; | |
5518 | ; one_cmpldi2 instruction pattern(s). | |
5519 | ; | |
c7453384 | 5520 | |
9db1d521 HP |
5521 | (define_expand "one_cmpldi2" |
5522 | [(parallel | |
4023fb28 UW |
5523 | [(set (match_operand:DI 0 "register_operand" "") |
5524 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
5525 | (const_int -1))) | |
9db1d521 HP |
5526 | (clobber (reg:CC 33))])] |
5527 | "TARGET_64BIT" | |
4023fb28 | 5528 | "") |
c7453384 | 5529 | |
9db1d521 HP |
5530 | ; |
5531 | ; one_cmplsi2 instruction pattern(s). | |
5532 | ; | |
c7453384 | 5533 | |
9db1d521 HP |
5534 | (define_expand "one_cmplsi2" |
5535 | [(parallel | |
4023fb28 UW |
5536 | [(set (match_operand:SI 0 "register_operand" "") |
5537 | (xor:SI (match_operand:SI 1 "register_operand" "") | |
5538 | (const_int -1))) | |
9db1d521 HP |
5539 | (clobber (reg:CC 33))])] |
5540 | "" | |
4023fb28 | 5541 | "") |
c7453384 | 5542 | |
9db1d521 HP |
5543 | ; |
5544 | ; one_cmplhi2 instruction pattern(s). | |
5545 | ; | |
c7453384 | 5546 | |
9db1d521 HP |
5547 | (define_expand "one_cmplhi2" |
5548 | [(parallel | |
4023fb28 UW |
5549 | [(set (match_operand:HI 0 "register_operand" "") |
5550 | (xor:HI (match_operand:HI 1 "register_operand" "") | |
5551 | (const_int -1))) | |
9db1d521 HP |
5552 | (clobber (reg:CC 33))])] |
5553 | "" | |
4023fb28 | 5554 | "") |
c7453384 | 5555 | |
9db1d521 HP |
5556 | ; |
5557 | ; one_cmplqi2 instruction pattern(s). | |
5558 | ; | |
c7453384 | 5559 | |
4023fb28 UW |
5560 | (define_expand "one_cmplqi2" |
5561 | [(parallel | |
5562 | [(set (match_operand:QI 0 "register_operand" "") | |
5563 | (xor:QI (match_operand:QI 1 "register_operand" "") | |
5564 | (const_int -1))) | |
5565 | (clobber (reg:CC 33))])] | |
9db1d521 | 5566 | "" |
4023fb28 | 5567 | "") |
9db1d521 HP |
5568 | |
5569 | ||
5570 | ;; | |
5571 | ;;- Rotate instructions. | |
5572 | ;; | |
5573 | ||
5574 | ; | |
5575 | ; rotldi3 instruction pattern(s). | |
5576 | ; | |
5577 | ||
5578 | (define_insn "rotldi3" | |
5579 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5580 | (rotate:DI (match_operand:DI 1 "register_operand" "d,d") | |
ecbe845e | 5581 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
9db1d521 HP |
5582 | "TARGET_64BIT" |
5583 | "@ | |
d40c829f UW |
5584 | rllg\t%0,%1,%c2 |
5585 | rllg\t%0,%1,0(%2)" | |
077dab3b HP |
5586 | [(set_attr "op_type" "RSE") |
5587 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5588 | |
5589 | ; | |
5590 | ; rotlsi3 instruction pattern(s). | |
5591 | ; | |
5592 | ||
5593 | (define_insn "rotlsi3" | |
5594 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5595 | (rotate:SI (match_operand:SI 1 "register_operand" "d,d") | |
ecbe845e | 5596 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
9db1d521 HP |
5597 | "TARGET_64BIT" |
5598 | "@ | |
d40c829f UW |
5599 | rll\t%0,%1,%c2 |
5600 | rll\t%0,%1,0(%2)" | |
077dab3b HP |
5601 | [(set_attr "op_type" "RSE") |
5602 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5603 | |
5604 | ||
5605 | ;; | |
5606 | ;;- Arithmetic shift instructions. | |
5607 | ;; | |
9db1d521 HP |
5608 | |
5609 | ; | |
5610 | ; ashldi3 instruction pattern(s). | |
5611 | ; | |
5612 | ||
5613 | (define_expand "ashldi3" | |
ecbe845e UW |
5614 | [(set (match_operand:DI 0 "register_operand" "") |
5615 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
5616 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
9db1d521 HP |
5617 | "" |
5618 | "") | |
5619 | ||
5620 | (define_insn "*ashldi3_31" | |
5621 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5622 | (ashift:DI (match_operand:DI 1 "register_operand" "0,0") | |
ecbe845e | 5623 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
9db1d521 HP |
5624 | "!TARGET_64BIT" |
5625 | "@ | |
d40c829f UW |
5626 | sldl\t%0,%c2 |
5627 | sldl\t%0,0(%2)" | |
077dab3b HP |
5628 | [(set_attr "op_type" "RS") |
5629 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5630 | |
5631 | (define_insn "*ashldi3_64" | |
ecbe845e | 5632 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 | 5633 | (ashift:DI (match_operand:DI 1 "register_operand" "d,d") |
ecbe845e | 5634 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
9db1d521 HP |
5635 | "TARGET_64BIT" |
5636 | "@ | |
d40c829f UW |
5637 | sllg\t%0,%1,%2 |
5638 | sllg\t%0,%1,0(%2)" | |
077dab3b HP |
5639 | [(set_attr "op_type" "RSE") |
5640 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5641 | |
5642 | ; | |
5643 | ; ashrdi3 instruction pattern(s). | |
5644 | ; | |
5645 | ||
5646 | (define_expand "ashrdi3" | |
5647 | [(parallel | |
5648 | [(set (match_operand:DI 0 "register_operand" "") | |
5649 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
5650 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5651 | (clobber (reg:CC 33))])] | |
5652 | "" | |
5653 | "") | |
5654 | ||
ecbe845e UW |
5655 | (define_insn "*ashrdi3_cc_31" |
5656 | [(set (reg 33) | |
5657 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
5658 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5659 | (const_int 0))) | |
5660 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5661 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
5662 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
5663 | "@ | |
d40c829f UW |
5664 | srda\t%0,%c2 |
5665 | srda\t%0,0(%2)" | |
077dab3b HP |
5666 | [(set_attr "op_type" "RS") |
5667 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
5668 | |
5669 | (define_insn "*ashrdi3_cconly_31" | |
5670 | [(set (reg 33) | |
5671 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
5672 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5673 | (const_int 0))) | |
5674 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5675 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
5676 | "@ | |
d40c829f UW |
5677 | srda\t%0,%c2 |
5678 | srda\t%0,0(%2)" | |
077dab3b HP |
5679 | [(set_attr "op_type" "RS") |
5680 | (set_attr "atype" "reg")]) | |
ecbe845e | 5681 | |
9db1d521 HP |
5682 | (define_insn "*ashrdi3_31" |
5683 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5684 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
5685 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
5686 | (clobber (reg:CC 33))] | |
5687 | "!TARGET_64BIT" | |
5688 | "@ | |
d40c829f UW |
5689 | srda\t%0,%c2 |
5690 | srda\t%0,0(%2)" | |
077dab3b HP |
5691 | [(set_attr "op_type" "RS") |
5692 | (set_attr "atype" "reg")]) | |
c7453384 | 5693 | |
ecbe845e UW |
5694 | (define_insn "*ashrdi3_cc_64" |
5695 | [(set (reg 33) | |
5696 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
5697 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5698 | (const_int 0))) | |
5699 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5700 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
5701 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
5702 | "@ | |
d40c829f UW |
5703 | srag\t%0,%1,%c2 |
5704 | srag\t%0,%1,0(%2)" | |
077dab3b HP |
5705 | [(set_attr "op_type" "RSE") |
5706 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
5707 | |
5708 | (define_insn "*ashrdi3_cconly_64" | |
5709 | [(set (reg 33) | |
5710 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
5711 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5712 | (const_int 0))) | |
5713 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5714 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
5715 | "@ | |
d40c829f UW |
5716 | srag\t%0,%1,%c2 |
5717 | srag\t%0,%1,0(%2)" | |
077dab3b HP |
5718 | [(set_attr "op_type" "RSE") |
5719 | (set_attr "atype" "reg")]) | |
ecbe845e | 5720 | |
9db1d521 HP |
5721 | (define_insn "*ashrdi3_64" |
5722 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5723 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
5724 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
5725 | (clobber (reg:CC 33))] | |
5726 | "TARGET_64BIT" | |
5727 | "@ | |
d40c829f UW |
5728 | srag\t%0,%1,%c2 |
5729 | srag\t%0,%1,0(%2)" | |
077dab3b HP |
5730 | [(set_attr "op_type" "RSE") |
5731 | (set_attr "atype" "reg")]) | |
5732 | ||
9db1d521 HP |
5733 | |
5734 | ; | |
5735 | ; ashlsi3 instruction pattern(s). | |
5736 | ; | |
9db1d521 HP |
5737 | |
5738 | (define_insn "ashlsi3" | |
5739 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5740 | (ashift:SI (match_operand:SI 1 "register_operand" "0,0") | |
ecbe845e | 5741 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
9db1d521 HP |
5742 | "" |
5743 | "@ | |
d40c829f UW |
5744 | sll\t%0,%c2 |
5745 | sll\t%0,0(%2)" | |
077dab3b HP |
5746 | [(set_attr "op_type" "RS") |
5747 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5748 | |
5749 | ; | |
5750 | ; ashrsi3 instruction pattern(s). | |
5751 | ; | |
5752 | ||
ecbe845e UW |
5753 | (define_insn "*ashrsi3_cc" |
5754 | [(set (reg 33) | |
5755 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
5756 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5757 | (const_int 0))) | |
5758 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
5759 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
5760 | "s390_match_ccmode(insn, CCSmode)" | |
5761 | "@ | |
d40c829f UW |
5762 | sra\t%0,%c2 |
5763 | sra\t%0,0(%2)" | |
077dab3b HP |
5764 | [(set_attr "op_type" "RS") |
5765 | (set_attr "atype" "reg")]) | |
5766 | ||
ecbe845e UW |
5767 | |
5768 | (define_insn "*ashrsi3_cconly" | |
5769 | [(set (reg 33) | |
5770 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
5771 | (match_operand:SI 2 "nonmemory_operand" "J,a")) | |
5772 | (const_int 0))) | |
5773 | (clobber (match_scratch:SI 0 "=d,d"))] | |
5774 | "s390_match_ccmode(insn, CCSmode)" | |
5775 | "@ | |
d40c829f UW |
5776 | sra\t%0,%c2 |
5777 | sra\t%0,0(%2)" | |
077dab3b HP |
5778 | [(set_attr "op_type" "RS") |
5779 | (set_attr "atype" "reg")]) | |
ecbe845e | 5780 | |
9db1d521 HP |
5781 | (define_insn "ashrsi3" |
5782 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5783 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
4023fb28 | 5784 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) |
9db1d521 HP |
5785 | (clobber (reg:CC 33))] |
5786 | "" | |
5787 | "@ | |
d40c829f UW |
5788 | sra\t%0,%c2 |
5789 | sra\t%0,0(%2)" | |
077dab3b HP |
5790 | [(set_attr "op_type" "RS") |
5791 | (set_attr "atype" "reg")]) | |
9db1d521 | 5792 | |
9db1d521 HP |
5793 | |
5794 | ;; | |
5795 | ;;- logical shift instructions. | |
5796 | ;; | |
5797 | ||
5798 | ; | |
5799 | ; lshrdi3 instruction pattern(s). | |
5800 | ; | |
5801 | ||
5802 | (define_expand "lshrdi3" | |
ecbe845e UW |
5803 | [(set (match_operand:DI 0 "register_operand" "") |
5804 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
5805 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
9db1d521 HP |
5806 | "" |
5807 | "") | |
5808 | ||
5809 | (define_insn "*lshrdi3_31" | |
5810 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5811 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
ecbe845e | 5812 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
9db1d521 HP |
5813 | "!TARGET_64BIT" |
5814 | "@ | |
d40c829f UW |
5815 | srdl\t%0,%c2 |
5816 | srdl\t%0,0(%2)" | |
077dab3b HP |
5817 | [(set_attr "op_type" "RS,RS") |
5818 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5819 | |
5820 | (define_insn "*lshrdi3_64" | |
5821 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5822 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
ecbe845e | 5823 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
9db1d521 HP |
5824 | "TARGET_64BIT" |
5825 | "@ | |
d40c829f UW |
5826 | srlg\t%0,%1,%c2 |
5827 | srlg\t%0,%1,0(%2)" | |
077dab3b HP |
5828 | [(set_attr "op_type" "RSE,RSE") |
5829 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5830 | |
5831 | ; | |
5832 | ; lshrsi3 instruction pattern(s). | |
5833 | ; | |
5834 | ||
5835 | (define_insn "lshrsi3" | |
5836 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5837 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
ecbe845e | 5838 | (match_operand:SI 2 "nonmemory_operand" "J,a")))] |
9db1d521 HP |
5839 | "" |
5840 | "@ | |
d40c829f UW |
5841 | srl\t%0,%c2 |
5842 | srl\t%0,0(%2)" | |
077dab3b HP |
5843 | [(set_attr "op_type" "RS") |
5844 | (set_attr "atype" "reg")]) | |
9db1d521 | 5845 | |
9db1d521 HP |
5846 | |
5847 | ;; | |
5848 | ;; Branch instruction patterns. | |
5849 | ;; | |
5850 | ||
5851 | (define_expand "beq" | |
5852 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
5853 | (set (pc) | |
5854 | (if_then_else (eq (reg:CCZ 33) (const_int 0)) | |
5855 | (label_ref (match_operand 0 "" "")) | |
5856 | (pc)))] | |
5857 | "" | |
10bbf137 | 5858 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5859 | |
5860 | (define_expand "bne" | |
5861 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
5862 | (set (pc) | |
5863 | (if_then_else (ne (reg:CCZ 33) (const_int 0)) | |
5864 | (label_ref (match_operand 0 "" "")) | |
5865 | (pc)))] | |
5866 | "" | |
10bbf137 | 5867 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5868 | |
5869 | (define_expand "bgt" | |
5870 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5871 | (set (pc) | |
5872 | (if_then_else (gt (reg:CCS 33) (const_int 0)) | |
5873 | (label_ref (match_operand 0 "" "")) | |
5874 | (pc)))] | |
5875 | "" | |
10bbf137 | 5876 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5877 | |
5878 | (define_expand "bgtu" | |
5879 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
5880 | (set (pc) | |
5881 | (if_then_else (gtu (reg:CCU 33) (const_int 0)) | |
5882 | (label_ref (match_operand 0 "" "")) | |
5883 | (pc)))] | |
5884 | "" | |
10bbf137 | 5885 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5886 | |
5887 | (define_expand "blt" | |
5888 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5889 | (set (pc) | |
5890 | (if_then_else (lt (reg:CCS 33) (const_int 0)) | |
5891 | (label_ref (match_operand 0 "" "")) | |
5892 | (pc)))] | |
5893 | "" | |
10bbf137 | 5894 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5895 | |
5896 | (define_expand "bltu" | |
5897 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
5898 | (set (pc) | |
5899 | (if_then_else (ltu (reg:CCU 33) (const_int 0)) | |
5900 | (label_ref (match_operand 0 "" "")) | |
5901 | (pc)))] | |
5902 | "" | |
10bbf137 | 5903 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5904 | |
5905 | (define_expand "bge" | |
5906 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5907 | (set (pc) | |
5908 | (if_then_else (ge (reg:CCS 33) (const_int 0)) | |
5909 | (label_ref (match_operand 0 "" "")) | |
5910 | (pc)))] | |
5911 | "" | |
10bbf137 | 5912 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5913 | |
5914 | (define_expand "bgeu" | |
5915 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
5916 | (set (pc) | |
5917 | (if_then_else (geu (reg:CCU 33) (const_int 0)) | |
5918 | (label_ref (match_operand 0 "" "")) | |
5919 | (pc)))] | |
5920 | "" | |
10bbf137 | 5921 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5922 | |
5923 | (define_expand "ble" | |
5924 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5925 | (set (pc) | |
5926 | (if_then_else (le (reg:CCS 33) (const_int 0)) | |
5927 | (label_ref (match_operand 0 "" "")) | |
5928 | (pc)))] | |
5929 | "" | |
10bbf137 | 5930 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
5931 | |
5932 | (define_expand "bleu" | |
5933 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
5934 | (set (pc) | |
5935 | (if_then_else (leu (reg:CCU 33) (const_int 0)) | |
5936 | (label_ref (match_operand 0 "" "")) | |
5937 | (pc)))] | |
5938 | "" | |
10bbf137 | 5939 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 | 5940 | |
ba956982 UW |
5941 | (define_expand "bunordered" |
5942 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5943 | (set (pc) | |
5944 | (if_then_else (unordered (reg:CCS 33) (const_int 0)) | |
5945 | (label_ref (match_operand 0 "" "")) | |
5946 | (pc)))] | |
5947 | "" | |
10bbf137 | 5948 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
5949 | |
5950 | (define_expand "bordered" | |
5951 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5952 | (set (pc) | |
5953 | (if_then_else (ordered (reg:CCS 33) (const_int 0)) | |
5954 | (label_ref (match_operand 0 "" "")) | |
5955 | (pc)))] | |
5956 | "" | |
10bbf137 | 5957 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
5958 | |
5959 | (define_expand "buneq" | |
5960 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5961 | (set (pc) | |
5962 | (if_then_else (uneq (reg:CCS 33) (const_int 0)) | |
5963 | (label_ref (match_operand 0 "" "")) | |
5964 | (pc)))] | |
5965 | "" | |
10bbf137 | 5966 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
5967 | |
5968 | (define_expand "bungt" | |
5969 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5970 | (set (pc) | |
5971 | (if_then_else (ungt (reg:CCS 33) (const_int 0)) | |
5972 | (label_ref (match_operand 0 "" "")) | |
5973 | (pc)))] | |
5974 | "" | |
10bbf137 | 5975 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
5976 | |
5977 | (define_expand "bunlt" | |
5978 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5979 | (set (pc) | |
5980 | (if_then_else (unlt (reg:CCS 33) (const_int 0)) | |
5981 | (label_ref (match_operand 0 "" "")) | |
5982 | (pc)))] | |
5983 | "" | |
10bbf137 | 5984 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
5985 | |
5986 | (define_expand "bunge" | |
5987 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5988 | (set (pc) | |
5989 | (if_then_else (unge (reg:CCS 33) (const_int 0)) | |
5990 | (label_ref (match_operand 0 "" "")) | |
5991 | (pc)))] | |
5992 | "" | |
10bbf137 | 5993 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
5994 | |
5995 | (define_expand "bunle" | |
5996 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
5997 | (set (pc) | |
5998 | (if_then_else (unle (reg:CCS 33) (const_int 0)) | |
5999 | (label_ref (match_operand 0 "" "")) | |
6000 | (pc)))] | |
6001 | "" | |
10bbf137 | 6002 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6003 | |
6004 | (define_expand "bltgt" | |
6005 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6006 | (set (pc) | |
6007 | (if_then_else (ltgt (reg:CCS 33) (const_int 0)) | |
6008 | (label_ref (match_operand 0 "" "")) | |
6009 | (pc)))] | |
6010 | "" | |
10bbf137 | 6011 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 | 6012 | |
9db1d521 HP |
6013 | |
6014 | ;; | |
6015 | ;;- Conditional jump instructions. | |
6016 | ;; | |
6017 | ||
6018 | (define_insn "cjump" | |
6019 | [(set (pc) | |
c7453384 | 6020 | (if_then_else |
9db1d521 HP |
6021 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) |
6022 | (label_ref (match_operand 0 "" "")) | |
6023 | (pc)))] | |
6024 | "" | |
9db1d521 | 6025 | { |
13e58269 | 6026 | if (get_attr_length (insn) == 4) |
d40c829f | 6027 | return "j%C1\t%l0"; |
13e58269 | 6028 | else if (TARGET_64BIT) |
d40c829f | 6029 | return "jg%C1\t%l0"; |
9db1d521 | 6030 | else |
13e58269 | 6031 | abort (); |
10bbf137 | 6032 | } |
9db1d521 | 6033 | [(set_attr "op_type" "RI") |
077dab3b | 6034 | (set_attr "type" "branch") |
13e58269 UW |
6035 | (set (attr "length") |
6036 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6037 | (const_int 4) | |
6038 | (ne (symbol_ref "TARGET_64BIT") (const_int 0)) | |
6039 | (const_int 6) | |
6040 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6041 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6042 | |
f314b9b1 | 6043 | (define_insn "*cjump_long" |
9db1d521 HP |
6044 | [(set (pc) |
6045 | (if_then_else | |
6046 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
d3632d41 | 6047 | (match_operand 0 "address_operand" "U") |
9db1d521 HP |
6048 | (pc)))] |
6049 | "" | |
f314b9b1 UW |
6050 | { |
6051 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6052 | return "b%C1r\t%0"; |
f314b9b1 | 6053 | else |
d40c829f | 6054 | return "b%C1\t%a0"; |
10bbf137 | 6055 | } |
c7453384 | 6056 | [(set (attr "op_type") |
f314b9b1 UW |
6057 | (if_then_else (match_operand 0 "register_operand" "") |
6058 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6059 | (set_attr "type" "branch") |
6060 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6061 | |
6062 | ||
6063 | ;; | |
6064 | ;;- Negated conditional jump instructions. | |
6065 | ;; | |
6066 | ||
6067 | (define_insn "icjump" | |
6068 | [(set (pc) | |
6069 | (if_then_else | |
6070 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
c7453384 | 6071 | (pc) |
9db1d521 HP |
6072 | (label_ref (match_operand 0 "" ""))))] |
6073 | "" | |
c7453384 | 6074 | { |
13e58269 | 6075 | if (get_attr_length (insn) == 4) |
d40c829f | 6076 | return "j%D1\t%l0"; |
13e58269 | 6077 | else if (TARGET_64BIT) |
d40c829f | 6078 | return "jg%D1\t%l0"; |
9db1d521 | 6079 | else |
13e58269 | 6080 | abort (); |
10bbf137 | 6081 | } |
9db1d521 | 6082 | [(set_attr "op_type" "RI") |
077dab3b | 6083 | (set_attr "type" "branch") |
13e58269 UW |
6084 | (set (attr "length") |
6085 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6086 | (const_int 4) | |
6087 | (ne (symbol_ref "TARGET_64BIT") (const_int 0)) | |
6088 | (const_int 6) | |
6089 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6090 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6091 | |
f314b9b1 | 6092 | (define_insn "*icjump_long" |
9db1d521 HP |
6093 | [(set (pc) |
6094 | (if_then_else | |
6095 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
f314b9b1 | 6096 | (pc) |
d3632d41 | 6097 | (match_operand 0 "address_operand" "U")))] |
9db1d521 | 6098 | "" |
f314b9b1 UW |
6099 | { |
6100 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6101 | return "b%D1r\t%0"; |
f314b9b1 | 6102 | else |
d40c829f | 6103 | return "b%D1\t%a0"; |
10bbf137 | 6104 | } |
c7453384 | 6105 | [(set (attr "op_type") |
f314b9b1 UW |
6106 | (if_then_else (match_operand 0 "register_operand" "") |
6107 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6108 | (set_attr "type" "branch") |
6109 | (set_attr "atype" "agen")]) | |
9db1d521 | 6110 | |
4456530d HP |
6111 | ;; |
6112 | ;;- Trap instructions. | |
6113 | ;; | |
6114 | ||
6115 | (define_insn "trap" | |
6116 | [(trap_if (const_int 1) (const_int 0))] | |
6117 | "" | |
d40c829f | 6118 | "j\t.+2" |
077dab3b HP |
6119 | [(set_attr "op_type" "RX") |
6120 | (set_attr "type" "branch")]) | |
4456530d HP |
6121 | |
6122 | (define_expand "conditional_trap" | |
6123 | [(set (match_dup 2) (match_dup 3)) | |
6124 | (trap_if (match_operator 0 "comparison_operator" | |
6125 | [(match_dup 2) (const_int 0)]) | |
6126 | (match_operand:SI 1 "general_operand" ""))] | |
6127 | "" | |
4456530d HP |
6128 | { |
6129 | enum machine_mode ccmode; | |
6130 | ||
c7453384 | 6131 | if (operands[1] != const0_rtx) FAIL; |
4456530d | 6132 | |
c7453384 EC |
6133 | ccmode = s390_select_ccmode (GET_CODE (operands[0]), |
6134 | s390_compare_op0, s390_compare_op1); | |
4456530d HP |
6135 | operands[2] = gen_rtx_REG (ccmode, 33); |
6136 | operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6137 | }) |
4456530d HP |
6138 | |
6139 | (define_insn "*trap" | |
6140 | [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)]) | |
6141 | (const_int 0))] | |
6142 | "" | |
d40c829f | 6143 | "j%C0\t.+2"; |
077dab3b HP |
6144 | [(set_attr "op_type" "RI") |
6145 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6146 | |
6147 | ;; | |
0a3bdf9d | 6148 | ;;- Loop instructions. |
9db1d521 | 6149 | ;; |
0a3bdf9d UW |
6150 | ;; This is all complicated by the fact that since this is a jump insn |
6151 | ;; we must handle our own output reloads. | |
c7453384 | 6152 | |
0a3bdf9d UW |
6153 | (define_expand "doloop_end" |
6154 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6155 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6156 | (use (match_operand 2 "" "")) ; max iterations | |
6157 | (use (match_operand 3 "" "")) ; loop level | |
6158 | (use (match_operand 4 "" ""))] ; label | |
6159 | "" | |
0a3bdf9d UW |
6160 | { |
6161 | if (GET_MODE (operands[0]) == SImode) | |
6162 | emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0])); | |
6163 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) | |
6164 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6165 | else | |
6166 | FAIL; | |
6167 | ||
6168 | DONE; | |
10bbf137 | 6169 | }) |
0a3bdf9d UW |
6170 | |
6171 | (define_insn "doloop_si" | |
6172 | [(set (pc) | |
6173 | (if_then_else | |
6174 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6175 | (const_int 1)) | |
6176 | (label_ref (match_operand 0 "" "")) | |
6177 | (pc))) | |
6178 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6179 | (plus:SI (match_dup 1) (const_int -1))) | |
6180 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6181 | (clobber (reg:CC 33))] | |
6182 | "" | |
0a3bdf9d UW |
6183 | { |
6184 | if (which_alternative != 0) | |
10bbf137 | 6185 | return "#"; |
0a3bdf9d | 6186 | else if (get_attr_length (insn) == 4) |
d40c829f | 6187 | return "brct\t%1,%l0"; |
0a3bdf9d UW |
6188 | else |
6189 | abort (); | |
10bbf137 | 6190 | } |
0a3bdf9d | 6191 | [(set_attr "op_type" "RI") |
077dab3b | 6192 | (set_attr "type" "branch") |
0a3bdf9d UW |
6193 | (set (attr "length") |
6194 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6195 | (const_int 4) | |
6196 | (ne (symbol_ref "TARGET_64BIT") (const_int 0)) | |
6197 | (const_int 10) | |
0a3bdf9d UW |
6198 | (eq (symbol_ref "flag_pic") (const_int 0)) |
6199 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6200 | |
0a3bdf9d UW |
6201 | (define_insn "*doloop_si_long" |
6202 | [(set (pc) | |
6203 | (if_then_else | |
6204 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6205 | (const_int 1)) | |
d3632d41 | 6206 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6207 | (pc))) |
6208 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6209 | (plus:SI (match_dup 1) (const_int -1))) | |
6210 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6211 | (clobber (reg:CC 33))] | |
6212 | "" | |
0a3bdf9d UW |
6213 | { |
6214 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6215 | return "bctr\t%1,%0"; |
0a3bdf9d | 6216 | else |
d40c829f | 6217 | return "bct\t%1,%a0"; |
10bbf137 | 6218 | } |
c7453384 | 6219 | [(set (attr "op_type") |
0a3bdf9d UW |
6220 | (if_then_else (match_operand 0 "register_operand" "") |
6221 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6222 | (set_attr "type" "branch") |
6223 | (set_attr "atype" "agen")]) | |
0a3bdf9d UW |
6224 | |
6225 | (define_split | |
6226 | [(set (pc) | |
6227 | (if_then_else (ne (match_operand:SI 1 "register_operand" "") | |
6228 | (const_int 1)) | |
6229 | (match_operand 0 "" "") | |
6230 | (pc))) | |
6231 | (set (match_operand:SI 2 "nonimmediate_operand" "") | |
6232 | (plus:SI (match_dup 1) (const_int -1))) | |
6233 | (clobber (match_scratch:SI 3 "")) | |
6234 | (clobber (reg:CC 33))] | |
6235 | "reload_completed | |
6236 | && (! REG_P (operands[2]) | |
6237 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6238 | [(set (match_dup 3) (match_dup 1)) | |
6239 | (parallel [(set (reg:CCAN 33) | |
6240 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
6241 | (const_int 0))) | |
6242 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6243 | (set (match_dup 2) (match_dup 3)) | |
6244 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6245 | (match_dup 0) | |
6246 | (pc)))] | |
6247 | "") | |
9db1d521 | 6248 | |
0a3bdf9d UW |
6249 | (define_insn "doloop_di" |
6250 | [(set (pc) | |
6251 | (if_then_else | |
6252 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6253 | (const_int 1)) | |
6254 | (label_ref (match_operand 0 "" "")) | |
6255 | (pc))) | |
6256 | (set (match_operand:DI 2 "register_operand" "=1,?*m*r") | |
6257 | (plus:DI (match_dup 1) (const_int -1))) | |
6258 | (clobber (match_scratch:DI 3 "=X,&d")) | |
6259 | (clobber (reg:CC 33))] | |
6260 | "TARGET_64BIT" | |
0a3bdf9d UW |
6261 | { |
6262 | if (which_alternative != 0) | |
10bbf137 | 6263 | return "#"; |
0a3bdf9d | 6264 | else if (get_attr_length (insn) == 4) |
d40c829f | 6265 | return "brctg\t%1,%l0"; |
0a3bdf9d UW |
6266 | else |
6267 | abort (); | |
10bbf137 | 6268 | } |
0a3bdf9d | 6269 | [(set_attr "op_type" "RI") |
077dab3b | 6270 | (set_attr "type" "branch") |
0a3bdf9d UW |
6271 | (set (attr "length") |
6272 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6273 | (const_int 4) (const_int 12)))]) | |
6274 | ||
6275 | (define_insn "*doloop_di_long" | |
6276 | [(set (pc) | |
6277 | (if_then_else | |
6278 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6279 | (const_int 1)) | |
d3632d41 | 6280 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6281 | (pc))) |
6282 | (set (match_operand:DI 2 "register_operand" "=1,?*m*d") | |
6283 | (plus:DI (match_dup 1) (const_int -1))) | |
6284 | (clobber (match_scratch:DI 3 "=X,&d")) | |
6285 | (clobber (reg:CC 33))] | |
6286 | "" | |
0a3bdf9d UW |
6287 | { |
6288 | if (get_attr_op_type (insn) == OP_TYPE_RRE) | |
d40c829f | 6289 | return "bctgr\t%1,%0"; |
0a3bdf9d | 6290 | else |
d40c829f | 6291 | return "bctg\t%1,%a0"; |
10bbf137 | 6292 | } |
c7453384 | 6293 | [(set (attr "op_type") |
0a3bdf9d UW |
6294 | (if_then_else (match_operand 0 "register_operand" "") |
6295 | (const_string "RRE") (const_string "RXE"))) | |
077dab3b HP |
6296 | (set_attr "type" "branch") |
6297 | (set_attr "atype" "agen")]) | |
0a3bdf9d UW |
6298 | |
6299 | (define_split | |
6300 | [(set (pc) | |
6301 | (if_then_else (ne (match_operand:DI 1 "register_operand" "") | |
6302 | (const_int 1)) | |
6303 | (match_operand 0 "" "") | |
6304 | (pc))) | |
6305 | (set (match_operand:DI 2 "nonimmediate_operand" "") | |
6306 | (plus:DI (match_dup 1) (const_int -1))) | |
6307 | (clobber (match_scratch:DI 3 "")) | |
6308 | (clobber (reg:CC 33))] | |
6309 | "reload_completed | |
6310 | && (! REG_P (operands[2]) | |
6311 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6312 | [(set (match_dup 3) (match_dup 1)) | |
6313 | (parallel [(set (reg:CCAN 33) | |
6314 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) | |
6315 | (const_int 0))) | |
6316 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6317 | (set (match_dup 2) (match_dup 3)) | |
6318 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6319 | (match_dup 0) | |
6320 | (pc)))] | |
6321 | "") | |
9db1d521 HP |
6322 | |
6323 | ;; | |
6324 | ;;- Unconditional jump instructions. | |
6325 | ;; | |
6326 | ||
6327 | ; | |
6328 | ; jump instruction pattern(s). | |
6329 | ; | |
6330 | ||
6331 | (define_insn "jump" | |
6332 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6333 | "" | |
9db1d521 | 6334 | { |
13e58269 | 6335 | if (get_attr_length (insn) == 4) |
d40c829f | 6336 | return "j\t%l0"; |
13e58269 | 6337 | else if (TARGET_64BIT) |
d40c829f | 6338 | return "jg\t%l0"; |
9db1d521 | 6339 | else |
13e58269 | 6340 | abort (); |
10bbf137 | 6341 | } |
9db1d521 | 6342 | [(set_attr "op_type" "RI") |
077dab3b | 6343 | (set_attr "type" "branch") |
13e58269 UW |
6344 | (set (attr "length") |
6345 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6346 | (const_int 4) | |
6347 | (ne (symbol_ref "TARGET_64BIT") (const_int 0)) | |
6348 | (const_int 6) | |
6349 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6350 | (const_int 6)] (const_int 8)))]) | |
9db1d521 HP |
6351 | |
6352 | ; | |
6353 | ; indirect-jump instruction pattern(s). | |
6354 | ; | |
6355 | ||
6356 | (define_insn "indirect_jump" | |
d3632d41 | 6357 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6358 | "" |
f314b9b1 UW |
6359 | { |
6360 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6361 | return "br\t%0"; |
f314b9b1 | 6362 | else |
d40c829f | 6363 | return "b\t%a0"; |
10bbf137 | 6364 | } |
c7453384 | 6365 | [(set (attr "op_type") |
f314b9b1 UW |
6366 | (if_then_else (match_operand 0 "register_operand" "") |
6367 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6368 | (set_attr "type" "branch") |
6369 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6370 | |
6371 | ; | |
f314b9b1 | 6372 | ; casesi instruction pattern(s). |
9db1d521 HP |
6373 | ; |
6374 | ||
f314b9b1 | 6375 | (define_insn "casesi_jump" |
d3632d41 | 6376 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 6377 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 6378 | "" |
9db1d521 | 6379 | { |
f314b9b1 | 6380 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 6381 | return "br\t%0"; |
f314b9b1 | 6382 | else |
d40c829f | 6383 | return "b\t%a0"; |
10bbf137 | 6384 | } |
c7453384 | 6385 | [(set (attr "op_type") |
f314b9b1 UW |
6386 | (if_then_else (match_operand 0 "register_operand" "") |
6387 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6388 | (set_attr "type" "branch") |
6389 | (set_attr "atype" "agen")]) | |
9db1d521 | 6390 | |
f314b9b1 UW |
6391 | (define_expand "casesi" |
6392 | [(match_operand:SI 0 "general_operand" "") | |
6393 | (match_operand:SI 1 "general_operand" "") | |
6394 | (match_operand:SI 2 "general_operand" "") | |
6395 | (label_ref (match_operand 3 "" "")) | |
6396 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 6397 | "" |
f314b9b1 UW |
6398 | { |
6399 | rtx index = gen_reg_rtx (SImode); | |
6400 | rtx base = gen_reg_rtx (Pmode); | |
6401 | rtx target = gen_reg_rtx (Pmode); | |
6402 | ||
6403 | emit_move_insn (index, operands[0]); | |
6404 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6405 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 6406 | operands[4]); |
f314b9b1 UW |
6407 | |
6408 | if (Pmode != SImode) | |
6409 | index = convert_to_mode (Pmode, index, 1); | |
6410 | if (GET_CODE (index) != REG) | |
6411 | index = copy_to_mode_reg (Pmode, index); | |
6412 | ||
6413 | if (TARGET_64BIT) | |
6414 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6415 | else | |
6416 | emit_insn (gen_ashlsi3 (index, index, GEN_INT (2))); | |
9db1d521 | 6417 | |
f314b9b1 UW |
6418 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6419 | ||
6420 | index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index)); | |
6421 | emit_move_insn (target, index); | |
6422 | ||
6423 | if (flag_pic) | |
6424 | target = gen_rtx_PLUS (Pmode, base, target); | |
6425 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
6426 | ||
6427 | DONE; | |
10bbf137 | 6428 | }) |
9db1d521 HP |
6429 | |
6430 | ||
6431 | ;; | |
6432 | ;;- Jump to subroutine. | |
6433 | ;; | |
6434 | ;; | |
6435 | ||
6436 | ; | |
6437 | ; untyped call instruction pattern(s). | |
6438 | ; | |
6439 | ||
6440 | ;; Call subroutine returning any type. | |
6441 | (define_expand "untyped_call" | |
6442 | [(parallel [(call (match_operand 0 "" "") | |
6443 | (const_int 0)) | |
6444 | (match_operand 1 "" "") | |
6445 | (match_operand 2 "" "")])] | |
6446 | "" | |
9db1d521 HP |
6447 | { |
6448 | int i; | |
6449 | ||
6450 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
6451 | ||
6452 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
6453 | { | |
6454 | rtx set = XVECEXP (operands[2], 0, i); | |
6455 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
6456 | } | |
6457 | ||
6458 | /* The optimizer does not know that the call sets the function value | |
6459 | registers we stored in the result block. We avoid problems by | |
6460 | claiming that all hard registers are used and clobbered at this | |
6461 | point. */ | |
6462 | emit_insn (gen_blockage ()); | |
6463 | ||
6464 | DONE; | |
10bbf137 | 6465 | }) |
9db1d521 HP |
6466 | |
6467 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
6468 | ;; all of memory. This blocks insns from being moved across this point. | |
6469 | ||
6470 | (define_insn "blockage" | |
10bbf137 | 6471 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 6472 | "" |
4023fb28 | 6473 | "" |
d5869ca0 UW |
6474 | [(set_attr "type" "none") |
6475 | (set_attr "length" "0")]) | |
4023fb28 | 6476 | |
9db1d521 HP |
6477 | |
6478 | ||
6479 | ; | |
6480 | ; call instruction pattern(s). | |
6481 | ; | |
6482 | ||
6483 | (define_expand "call" | |
44b8152b UW |
6484 | [(call (match_operand 0 "" "") |
6485 | (match_operand 1 "" "")) | |
6486 | (use (match_operand 2 "" ""))] | |
9db1d521 | 6487 | "" |
9db1d521 | 6488 | { |
44b8152b | 6489 | rtx insn; |
9db1d521 HP |
6490 | |
6491 | /* Direct function calls need special treatment. */ | |
6492 | if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) | |
6493 | { | |
6494 | rtx sym = XEXP (operands[0], 0); | |
6495 | ||
6496 | /* When calling a global routine in PIC mode, we must | |
6497 | replace the symbol itself with the PLT stub. */ | |
114278e7 | 6498 | if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) |
9db1d521 | 6499 | { |
fd7643fb | 6500 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
9db1d521 HP |
6501 | sym = gen_rtx_CONST (Pmode, sym); |
6502 | } | |
6503 | ||
c7453384 | 6504 | /* Unless we can use the bras(l) insn, force the |
9db1d521 HP |
6505 | routine address into a register. */ |
6506 | if (!TARGET_SMALL_EXEC && !TARGET_64BIT) | |
fd7643fb UW |
6507 | { |
6508 | if (flag_pic) | |
6509 | sym = legitimize_pic_address (sym, 0); | |
6510 | else | |
6511 | sym = force_reg (Pmode, sym); | |
6512 | } | |
9db1d521 HP |
6513 | |
6514 | operands[0] = gen_rtx_MEM (QImode, sym); | |
6515 | } | |
44b8152b UW |
6516 | |
6517 | /* Emit insn. */ | |
6518 | insn = emit_call_insn (gen_call_exp (operands[0], operands[1], | |
6519 | gen_rtx_REG (Pmode, RETURN_REGNUM))); | |
44b8152b | 6520 | DONE; |
10bbf137 | 6521 | }) |
9db1d521 | 6522 | |
44b8152b UW |
6523 | (define_expand "call_exp" |
6524 | [(parallel [(call (match_operand 0 "" "") | |
6525 | (match_operand 1 "" "")) | |
6526 | (clobber (match_operand 2 "" ""))])] | |
6527 | "" | |
6528 | "") | |
6529 | ||
9db1d521 HP |
6530 | (define_insn "brasl" |
6531 | [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X")) | |
6532 | (match_operand:SI 1 "const_int_operand" "n")) | |
6533 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
6534 | "TARGET_64BIT" | |
d40c829f | 6535 | "brasl\t%2,%0" |
9db1d521 | 6536 | [(set_attr "op_type" "RIL") |
4023fb28 | 6537 | (set_attr "type" "jsr")]) |
9db1d521 HP |
6538 | |
6539 | (define_insn "bras" | |
6540 | [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X")) | |
6541 | (match_operand:SI 1 "const_int_operand" "n")) | |
6542 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
6543 | "TARGET_SMALL_EXEC" | |
d40c829f | 6544 | "bras\t%2,%0" |
9db1d521 | 6545 | [(set_attr "op_type" "RI") |
4023fb28 | 6546 | (set_attr "type" "jsr")]) |
9db1d521 HP |
6547 | |
6548 | (define_insn "basr_64" | |
6549 | [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) | |
6550 | (match_operand:SI 1 "const_int_operand" "n")) | |
6551 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
6552 | "TARGET_64BIT" | |
d40c829f | 6553 | "basr\t%2,%0" |
9db1d521 | 6554 | [(set_attr "op_type" "RR") |
f2d3c02a | 6555 | (set_attr "type" "jsr") |
077dab3b | 6556 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6557 | |
6558 | (define_insn "basr_31" | |
6559 | [(call (mem:QI (match_operand:SI 0 "register_operand" "a")) | |
6560 | (match_operand:SI 1 "const_int_operand" "n")) | |
6561 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
6562 | "!TARGET_64BIT" | |
d40c829f | 6563 | "basr\t%2,%0" |
9db1d521 | 6564 | [(set_attr "op_type" "RR") |
f2d3c02a | 6565 | (set_attr "type" "jsr") |
077dab3b | 6566 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6567 | |
6568 | (define_insn "bas_64" | |
d3632d41 | 6569 | [(call (mem:QI (match_operand:QI 0 "address_operand" "U")) |
9db1d521 HP |
6570 | (match_operand:SI 1 "const_int_operand" "n")) |
6571 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
6572 | "TARGET_64BIT" | |
d40c829f | 6573 | "bas\t%2,%a0" |
9db1d521 | 6574 | [(set_attr "op_type" "RX") |
077dab3b | 6575 | (set_attr "type" "jsr")]) |
9db1d521 HP |
6576 | |
6577 | (define_insn "bas_31" | |
d3632d41 | 6578 | [(call (mem:QI (match_operand:QI 0 "address_operand" "U")) |
9db1d521 HP |
6579 | (match_operand:SI 1 "const_int_operand" "n")) |
6580 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
6581 | "!TARGET_64BIT" | |
d40c829f | 6582 | "bas\t%2,%a0" |
9db1d521 | 6583 | [(set_attr "op_type" "RX") |
077dab3b | 6584 | (set_attr "type" "jsr")]) |
9db1d521 HP |
6585 | |
6586 | ||
6587 | ; | |
6588 | ; call_value instruction pattern(s). | |
6589 | ; | |
6590 | ||
6591 | (define_expand "call_value" | |
44b8152b UW |
6592 | [(set (match_operand 0 "" "") |
6593 | (call (match_operand 1 "" "") | |
6594 | (match_operand 2 "" ""))) | |
6595 | (use (match_operand 3 "" ""))] | |
9db1d521 | 6596 | "" |
9db1d521 | 6597 | { |
44b8152b | 6598 | rtx insn; |
9db1d521 HP |
6599 | |
6600 | /* Direct function calls need special treatment. */ | |
6601 | if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) | |
6602 | { | |
6603 | rtx sym = XEXP (operands[1], 0); | |
6604 | ||
6605 | /* When calling a global routine in PIC mode, we must | |
6606 | replace the symbol itself with the PLT stub. */ | |
114278e7 | 6607 | if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) |
9db1d521 | 6608 | { |
fd7643fb | 6609 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
9db1d521 HP |
6610 | sym = gen_rtx_CONST (Pmode, sym); |
6611 | } | |
6612 | ||
c7453384 | 6613 | /* Unless we can use the bras(l) insn, force the |
9db1d521 HP |
6614 | routine address into a register. */ |
6615 | if (!TARGET_SMALL_EXEC && !TARGET_64BIT) | |
6616 | { | |
fd7643fb UW |
6617 | if (flag_pic) |
6618 | sym = legitimize_pic_address (sym, 0); | |
6619 | else | |
6620 | sym = force_reg (Pmode, sym); | |
9db1d521 HP |
6621 | } |
6622 | ||
6623 | operands[1] = gen_rtx_MEM (QImode, sym); | |
6624 | } | |
44b8152b UW |
6625 | |
6626 | /* Emit insn. */ | |
6627 | insn = emit_call_insn ( | |
6628 | gen_call_value_exp (operands[0], operands[1], operands[2], | |
6629 | gen_rtx_REG (Pmode, RETURN_REGNUM))); | |
44b8152b | 6630 | DONE; |
10bbf137 | 6631 | }) |
9db1d521 | 6632 | |
44b8152b UW |
6633 | (define_expand "call_value_exp" |
6634 | [(parallel [(set (match_operand 0 "" "") | |
6635 | (call (match_operand 1 "" "") | |
6636 | (match_operand 2 "" ""))) | |
6637 | (clobber (match_operand 3 "" ""))])] | |
6638 | "" | |
6639 | "") | |
6640 | ||
9db1d521 HP |
6641 | (define_insn "brasl_r" |
6642 | [(set (match_operand 0 "register_operand" "=df") | |
6643 | (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) | |
6644 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6645 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
6646 | "TARGET_64BIT" | |
d40c829f | 6647 | "brasl\t%3,%1" |
9db1d521 | 6648 | [(set_attr "op_type" "RIL") |
f2d3c02a | 6649 | (set_attr "type" "jsr")]) |
9db1d521 HP |
6650 | |
6651 | (define_insn "bras_r" | |
6652 | [(set (match_operand 0 "register_operand" "=df") | |
6653 | (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) | |
6654 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6655 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
6656 | "TARGET_SMALL_EXEC" | |
d40c829f | 6657 | "bras\t%3,%1" |
9db1d521 | 6658 | [(set_attr "op_type" "RI") |
f2d3c02a | 6659 | (set_attr "type" "jsr")]) |
9db1d521 HP |
6660 | |
6661 | (define_insn "basr_r_64" | |
6662 | [(set (match_operand 0 "register_operand" "=df") | |
6663 | (call (mem:QI (match_operand:DI 1 "register_operand" "a")) | |
6664 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6665 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
6666 | "TARGET_64BIT" | |
d40c829f | 6667 | "basr\t%3,%1" |
9db1d521 | 6668 | [(set_attr "op_type" "RR") |
077dab3b HP |
6669 | (set_attr "type" "jsr") |
6670 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6671 | |
6672 | (define_insn "basr_r_31" | |
6673 | [(set (match_operand 0 "register_operand" "=df") | |
6674 | (call (mem:QI (match_operand:SI 1 "register_operand" "a")) | |
6675 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6676 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
6677 | "!TARGET_64BIT" | |
d40c829f | 6678 | "basr\t%3,%1" |
9db1d521 | 6679 | [(set_attr "op_type" "RR") |
f2d3c02a | 6680 | (set_attr "type" "jsr") |
077dab3b | 6681 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6682 | |
6683 | (define_insn "bas_r_64" | |
6684 | [(set (match_operand 0 "register_operand" "=df") | |
d3632d41 | 6685 | (call (mem:QI (match_operand:QI 1 "address_operand" "U")) |
9db1d521 HP |
6686 | (match_operand:SI 2 "const_int_operand" "n"))) |
6687 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
6688 | "TARGET_64BIT" | |
d40c829f | 6689 | "bas\t%3,%a1" |
9db1d521 | 6690 | [(set_attr "op_type" "RX") |
077dab3b | 6691 | (set_attr "type" "jsr")]) |
9db1d521 HP |
6692 | |
6693 | (define_insn "bas_r_31" | |
6694 | [(set (match_operand 0 "register_operand" "=df") | |
d3632d41 | 6695 | (call (mem:QI (match_operand:QI 1 "address_operand" "U")) |
9db1d521 HP |
6696 | (match_operand:SI 2 "const_int_operand" "n"))) |
6697 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
6698 | "!TARGET_64BIT" | |
d40c829f | 6699 | "bas\t%3,%a1" |
9db1d521 | 6700 | [(set_attr "op_type" "RX") |
077dab3b | 6701 | (set_attr "type" "jsr")]) |
9db1d521 HP |
6702 | |
6703 | ||
fd3cd001 UW |
6704 | ;; |
6705 | ;;- Thread-local storage support. | |
6706 | ;; | |
6707 | ||
6708 | (define_insn "get_tp_64" | |
6709 | [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q") | |
6710 | (unspec:DI [(const_int 0)] UNSPEC_TP))] | |
6711 | "TARGET_64BIT" | |
6712 | "@ | |
d40c829f UW |
6713 | ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1 |
6714 | stam\t%%a0,%%a1,%0" | |
fd3cd001 UW |
6715 | [(set_attr "op_type" "NN,RS") |
6716 | (set_attr "atype" "reg,*") | |
6717 | (set_attr "type" "o3,*") | |
6718 | (set_attr "length" "14,*")]) | |
6719 | ||
6720 | (define_insn "get_tp_31" | |
6721 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q") | |
6722 | (unspec:SI [(const_int 0)] UNSPEC_TP))] | |
6723 | "!TARGET_64BIT" | |
6724 | "@ | |
d40c829f UW |
6725 | ear\t%0,%%a0 |
6726 | stam\t%%a0,%%a0,%0" | |
fd3cd001 UW |
6727 | [(set_attr "op_type" "RRE,RS")]) |
6728 | ||
6729 | (define_insn "set_tp_64" | |
6730 | [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP) | |
6731 | (clobber (match_scratch:SI 1 "=d,X"))] | |
6732 | "TARGET_64BIT" | |
6733 | "@ | |
d40c829f UW |
6734 | sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1 |
6735 | lam\t%%a0,%%a1,%0" | |
fd3cd001 UW |
6736 | [(set_attr "op_type" "NN,RS") |
6737 | (set_attr "atype" "reg,*") | |
6738 | (set_attr "type" "o3,*") | |
6739 | (set_attr "length" "14,*")]) | |
6740 | ||
6741 | (define_insn "set_tp_31" | |
6742 | [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)] | |
6743 | "!TARGET_64BIT" | |
6744 | "@ | |
d40c829f UW |
6745 | sar\t%%a0,%0 |
6746 | lam\t%%a0,%%a0,%0" | |
fd3cd001 | 6747 | [(set_attr "op_type" "RRE,RS")]) |
c7453384 | 6748 | |
fd3cd001 UW |
6749 | (define_insn "*tls_load_64" |
6750 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6751 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
6752 | (match_operand:DI 2 "" "")] | |
6753 | UNSPEC_TLS_LOAD))] | |
6754 | "TARGET_64BIT" | |
d40c829f | 6755 | "lg\t%0,%1%J2" |
fd3cd001 UW |
6756 | [(set_attr "op_type" "RXE")]) |
6757 | ||
6758 | (define_insn "*tls_load_31" | |
d3632d41 UW |
6759 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6760 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
6761 | (match_operand:SI 2 "" "")] |
6762 | UNSPEC_TLS_LOAD))] | |
6763 | "!TARGET_64BIT" | |
d3632d41 | 6764 | "@ |
d40c829f UW |
6765 | l\t%0,%1%J2 |
6766 | ly\t%0,%1%J2" | |
d3632d41 | 6767 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 UW |
6768 | |
6769 | (define_expand "call_value_tls" | |
6770 | [(set (match_operand 0 "" "") | |
6771 | (call (const_int 0) (const_int 0))) | |
6772 | (use (match_operand 1 "" ""))] | |
6773 | "" | |
fd3cd001 UW |
6774 | { |
6775 | rtx insn, sym; | |
6776 | ||
6777 | if (!flag_pic) | |
6778 | abort (); | |
6779 | ||
6780 | sym = s390_tls_get_offset (); | |
fd7643fb | 6781 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
fd3cd001 UW |
6782 | sym = gen_rtx_CONST (Pmode, sym); |
6783 | ||
c7453384 | 6784 | /* Unless we can use the bras(l) insn, force the |
fd3cd001 UW |
6785 | routine address into a register. */ |
6786 | if (!TARGET_SMALL_EXEC && !TARGET_64BIT) | |
6787 | { | |
fd7643fb UW |
6788 | if (flag_pic) |
6789 | sym = legitimize_pic_address (sym, 0); | |
6790 | else | |
6791 | sym = force_reg (Pmode, sym); | |
fd3cd001 UW |
6792 | } |
6793 | ||
6794 | sym = gen_rtx_MEM (QImode, sym); | |
6795 | ||
6796 | /* Emit insn. */ | |
6797 | insn = emit_call_insn ( | |
6798 | gen_call_value_tls_exp (operands[0], sym, const0_rtx, | |
6799 | gen_rtx_REG (Pmode, RETURN_REGNUM), | |
6800 | operands[1])); | |
6801 | ||
6802 | /* The calling convention of __tls_get_offset uses the | |
6803 | GOT register implicitly. */ | |
6804 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
6805 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]); | |
6806 | CONST_OR_PURE_CALL_P (insn) = 1; | |
6807 | ||
6808 | DONE; | |
10bbf137 | 6809 | }) |
fd3cd001 UW |
6810 | |
6811 | (define_expand "call_value_tls_exp" | |
6812 | [(parallel [(set (match_operand 0 "" "") | |
6813 | (call (match_operand 1 "" "") | |
6814 | (match_operand 2 "" ""))) | |
6815 | (clobber (match_operand 3 "" "")) | |
6816 | (use (match_operand 4 "" ""))])] | |
6817 | "" | |
6818 | "") | |
6819 | ||
6820 | (define_insn "brasl_tls" | |
6821 | [(set (match_operand 0 "register_operand" "=df") | |
6822 | (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) | |
6823 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6824 | (clobber (match_operand:DI 3 "register_operand" "=r")) | |
6825 | (use (match_operand:DI 4 "" ""))] | |
6826 | "TARGET_64BIT" | |
d40c829f | 6827 | "brasl\t%3,%1%J4" |
fd3cd001 UW |
6828 | [(set_attr "op_type" "RIL") |
6829 | (set_attr "type" "jsr")]) | |
6830 | ||
6831 | (define_insn "bras_tls" | |
6832 | [(set (match_operand 0 "register_operand" "=df") | |
6833 | (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) | |
6834 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6835 | (clobber (match_operand:SI 3 "register_operand" "=r")) | |
6836 | (use (match_operand:SI 4 "" ""))] | |
6837 | "TARGET_SMALL_EXEC" | |
d40c829f | 6838 | "bras\t%3,%1%J4" |
fd3cd001 UW |
6839 | [(set_attr "op_type" "RI") |
6840 | (set_attr "type" "jsr")]) | |
6841 | ||
6842 | (define_insn "basr_tls_64" | |
6843 | [(set (match_operand 0 "register_operand" "=df") | |
6844 | (call (mem:QI (match_operand:DI 1 "register_operand" "a")) | |
6845 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6846 | (clobber (match_operand:DI 3 "register_operand" "=r")) | |
6847 | (use (match_operand:DI 4 "" ""))] | |
6848 | "TARGET_64BIT" | |
d40c829f | 6849 | "basr\t%3,%1%J4" |
fd3cd001 UW |
6850 | [(set_attr "op_type" "RR") |
6851 | (set_attr "type" "jsr")]) | |
6852 | ||
6853 | (define_insn "basr_tls_31" | |
6854 | [(set (match_operand 0 "register_operand" "=df") | |
6855 | (call (mem:QI (match_operand:SI 1 "register_operand" "a")) | |
6856 | (match_operand:SI 2 "const_int_operand" "n"))) | |
6857 | (clobber (match_operand:SI 3 "register_operand" "=r")) | |
6858 | (use (match_operand:SI 4 "" ""))] | |
6859 | "!TARGET_64BIT" | |
d40c829f | 6860 | "basr\t%3,%1%J4" |
fd3cd001 UW |
6861 | [(set_attr "op_type" "RR") |
6862 | (set_attr "type" "jsr") | |
6863 | (set_attr "atype" "agen")]) | |
6864 | ||
6865 | (define_insn "bas_tls_64" | |
6866 | [(set (match_operand 0 "register_operand" "=df") | |
d3632d41 | 6867 | (call (mem:QI (match_operand:QI 1 "address_operand" "U")) |
fd3cd001 UW |
6868 | (match_operand:SI 2 "const_int_operand" "n"))) |
6869 | (clobber (match_operand:DI 3 "register_operand" "=r")) | |
6870 | (use (match_operand:DI 4 "" ""))] | |
6871 | "TARGET_64BIT" | |
d40c829f | 6872 | "bas\t%3,%a1%J4" |
fd3cd001 UW |
6873 | [(set_attr "op_type" "RX") |
6874 | (set_attr "type" "jsr") | |
6875 | (set_attr "atype" "agen")]) | |
6876 | ||
6877 | (define_insn "bas_tls_31" | |
6878 | [(set (match_operand 0 "register_operand" "=df") | |
d3632d41 | 6879 | (call (mem:QI (match_operand:QI 1 "address_operand" "U")) |
fd3cd001 UW |
6880 | (match_operand:SI 2 "const_int_operand" "n"))) |
6881 | (clobber (match_operand:SI 3 "register_operand" "=r")) | |
6882 | (use (match_operand:SI 4 "" ""))] | |
6883 | "!TARGET_64BIT" | |
d40c829f | 6884 | "bas\t%3,%a1%J4" |
fd3cd001 UW |
6885 | [(set_attr "op_type" "RX") |
6886 | (set_attr "type" "jsr") | |
6887 | (set_attr "atype" "agen")]) | |
6888 | ||
9db1d521 HP |
6889 | ;; |
6890 | ;;- Miscellaneous instructions. | |
6891 | ;; | |
6892 | ||
6893 | ; | |
6894 | ; allocate stack instruction pattern(s). | |
6895 | ; | |
6896 | ||
6897 | (define_expand "allocate_stack" | |
6898 | [(set (reg 15) | |
6899 | (plus (reg 15) (match_operand 1 "general_operand" ""))) | |
6900 | (set (match_operand 0 "general_operand" "") | |
6901 | (reg 15))] | |
6902 | "" | |
9db1d521 HP |
6903 | { |
6904 | rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); | |
6905 | rtx chain = gen_rtx (MEM, Pmode, stack); | |
6906 | rtx temp = gen_reg_rtx (Pmode); | |
c7453384 | 6907 | |
9db1d521 HP |
6908 | emit_move_insn (temp, chain); |
6909 | ||
6910 | if (TARGET_64BIT) | |
6911 | emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
6912 | else | |
6913 | emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
6914 | ||
6915 | emit_move_insn (chain, temp); | |
6916 | ||
c7453384 | 6917 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
9db1d521 | 6918 | DONE; |
10bbf137 | 6919 | }) |
9db1d521 HP |
6920 | |
6921 | ||
6922 | ; | |
6923 | ; setjmp/longjmp instruction pattern(s). | |
6924 | ; | |
6925 | ||
6926 | (define_expand "builtin_setjmp_setup" | |
fd7643fb | 6927 | [(match_operand 0 "register_operand" "")] |
9db1d521 | 6928 | "" |
9db1d521 | 6929 | { |
f314b9b1 UW |
6930 | rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); |
6931 | rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); | |
6932 | ||
6933 | emit_move_insn (base, basereg); | |
9db1d521 | 6934 | DONE; |
fd7643fb | 6935 | }) |
9db1d521 HP |
6936 | |
6937 | (define_expand "builtin_setjmp_receiver" | |
fd7643fb | 6938 | [(match_operand 0 "" "")] |
f314b9b1 | 6939 | "flag_pic" |
9db1d521 | 6940 | { |
fd7643fb UW |
6941 | s390_load_got (false); |
6942 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
9db1d521 | 6943 | DONE; |
fd7643fb | 6944 | }) |
9db1d521 | 6945 | |
9db1d521 | 6946 | (define_expand "builtin_longjmp" |
fd7643fb | 6947 | [(match_operand 0 "register_operand" "")] |
9db1d521 | 6948 | "" |
9db1d521 HP |
6949 | { |
6950 | /* The elements of the buffer are, in order: */ | |
6951 | rtx fp = gen_rtx_MEM (Pmode, operands[0]); | |
f314b9b1 UW |
6952 | rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode))); |
6953 | rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode))); | |
6954 | rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); | |
6955 | rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); | |
fd7643fb | 6956 | rtx jmp = gen_reg_rtx (Pmode); |
9db1d521 HP |
6957 | |
6958 | emit_move_insn (jmp, lab); | |
f314b9b1 | 6959 | emit_move_insn (basereg, base); |
9db1d521 HP |
6960 | emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); |
6961 | emit_move_insn (hard_frame_pointer_rtx, fp); | |
6962 | ||
6963 | emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx)); | |
6964 | emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); | |
f314b9b1 | 6965 | emit_insn (gen_rtx_USE (VOIDmode, basereg)); |
9db1d521 HP |
6966 | emit_indirect_jump (jmp); |
6967 | DONE; | |
fd7643fb | 6968 | }) |
9db1d521 HP |
6969 | |
6970 | ||
6971 | ;; These patterns say how to save and restore the stack pointer. We need not | |
6972 | ;; save the stack pointer at function level since we are careful to | |
6973 | ;; preserve the backchain. At block level, we have to restore the backchain | |
6974 | ;; when we restore the stack pointer. | |
6975 | ;; | |
6976 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
6977 | ;; backchain and restore both. Note that in the nonlocal case, the | |
6978 | ;; save area is a memory location. | |
6979 | ||
6980 | (define_expand "save_stack_function" | |
6981 | [(match_operand 0 "general_operand" "") | |
6982 | (match_operand 1 "general_operand" "")] | |
6983 | "" | |
6984 | "DONE;") | |
6985 | ||
6986 | (define_expand "restore_stack_function" | |
6987 | [(match_operand 0 "general_operand" "") | |
6988 | (match_operand 1 "general_operand" "")] | |
6989 | "" | |
6990 | "DONE;") | |
6991 | ||
6992 | (define_expand "restore_stack_block" | |
6993 | [(use (match_operand 0 "register_operand" "")) | |
6994 | (set (match_dup 2) (match_dup 3)) | |
6995 | (set (match_dup 0) (match_operand 1 "register_operand" "")) | |
6996 | (set (match_dup 3) (match_dup 2))] | |
6997 | "" | |
9db1d521 HP |
6998 | { |
6999 | operands[2] = gen_reg_rtx (Pmode); | |
7000 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); | |
10bbf137 | 7001 | }) |
9db1d521 HP |
7002 | |
7003 | (define_expand "save_stack_nonlocal" | |
7004 | [(match_operand 0 "memory_operand" "") | |
7005 | (match_operand 1 "register_operand" "")] | |
7006 | "" | |
9db1d521 HP |
7007 | { |
7008 | rtx temp = gen_reg_rtx (Pmode); | |
7009 | ||
7010 | /* Copy the backchain to the first word, sp to the second. */ | |
7011 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); | |
7012 | emit_move_insn (operand_subword (operands[0], 0, 0, | |
7013 | TARGET_64BIT ? TImode : DImode), | |
7014 | temp); | |
7015 | emit_move_insn (operand_subword (operands[0], 1, 0, | |
7016 | TARGET_64BIT ? TImode : DImode), | |
7017 | operands[1]); | |
7018 | DONE; | |
10bbf137 | 7019 | }) |
9db1d521 HP |
7020 | |
7021 | (define_expand "restore_stack_nonlocal" | |
7022 | [(match_operand 0 "register_operand" "") | |
7023 | (match_operand 1 "memory_operand" "")] | |
7024 | "" | |
9db1d521 HP |
7025 | { |
7026 | rtx temp = gen_reg_rtx (Pmode); | |
7027 | ||
7028 | /* Restore the backchain from the first word, sp from the second. */ | |
7029 | emit_move_insn (temp, | |
7030 | operand_subword (operands[1], 0, 0, | |
7031 | TARGET_64BIT ? TImode : DImode)); | |
7032 | emit_move_insn (operands[0], | |
7033 | operand_subword (operands[1], 1, 0, | |
7034 | TARGET_64BIT ? TImode : DImode)); | |
7035 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); | |
7036 | DONE; | |
10bbf137 | 7037 | }) |
9db1d521 HP |
7038 | |
7039 | ||
7040 | ; | |
7041 | ; nop instruction pattern(s). | |
7042 | ; | |
7043 | ||
7044 | (define_insn "nop" | |
7045 | [(const_int 0)] | |
7046 | "" | |
d40c829f | 7047 | "lr\t0,0" |
9db1d521 HP |
7048 | [(set_attr "op_type" "RR")]) |
7049 | ||
7050 | ||
7051 | ; | |
7052 | ; Special literal pool access instruction pattern(s). | |
7053 | ; | |
7054 | ||
416cf582 UW |
7055 | (define_insn "*pool_entry" |
7056 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7057 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7058 | "" |
9db1d521 | 7059 | { |
416cf582 UW |
7060 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7061 | unsigned int align = GET_MODE_BITSIZE (mode); | |
7062 | s390_output_pool_entry (asm_out_file, operands[0], mode, align); | |
fd7643fb UW |
7063 | return ""; |
7064 | } | |
416cf582 UW |
7065 | [(set_attr "op_type" "NN") |
7066 | (set (attr "length") | |
7067 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) | |
b2ccb744 UW |
7068 | |
7069 | (define_insn "pool_start_31" | |
fd7643fb | 7070 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] |
b2ccb744 | 7071 | "!TARGET_64BIT" |
d40c829f | 7072 | ".align\t4" |
b2ccb744 UW |
7073 | [(set_attr "op_type" "NN") |
7074 | (set_attr "length" "2")]) | |
7075 | ||
7076 | (define_insn "pool_end_31" | |
fd7643fb | 7077 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] |
b2ccb744 | 7078 | "!TARGET_64BIT" |
d40c829f | 7079 | ".align\t2" |
b2ccb744 UW |
7080 | [(set_attr "op_type" "NN") |
7081 | (set_attr "length" "2")]) | |
7082 | ||
7083 | (define_insn "pool_start_64" | |
fd7643fb | 7084 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] |
b2ccb744 | 7085 | "TARGET_64BIT" |
d40c829f | 7086 | ".section\t.rodata\;.align\t8" |
b2ccb744 UW |
7087 | [(set_attr "op_type" "NN") |
7088 | (set_attr "length" "0")]) | |
7089 | ||
7090 | (define_insn "pool_end_64" | |
fd7643fb | 7091 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] |
b2ccb744 UW |
7092 | "TARGET_64BIT" |
7093 | ".previous" | |
7094 | [(set_attr "op_type" "NN") | |
7095 | (set_attr "length" "0")]) | |
7096 | ||
aee4e0db | 7097 | (define_insn "reload_base_31" |
b2ccb744 | 7098 | [(set (match_operand:SI 0 "register_operand" "=a") |
fd7643fb | 7099 | (unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] |
b2ccb744 | 7100 | "!TARGET_64BIT" |
d40c829f | 7101 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
9db1d521 | 7102 | [(set_attr "op_type" "NN") |
b2ccb744 UW |
7103 | (set_attr "type" "la") |
7104 | (set_attr "length" "6")]) | |
7105 | ||
aee4e0db UW |
7106 | (define_insn "reload_base_64" |
7107 | [(set (match_operand:DI 0 "register_operand" "=a") | |
fd7643fb | 7108 | (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] |
aee4e0db | 7109 | "TARGET_64BIT" |
d40c829f | 7110 | "larl\t%0,%1" |
aee4e0db | 7111 | [(set_attr "op_type" "RIL") |
077dab3b | 7112 | (set_attr "type" "larl")]) |
aee4e0db | 7113 | |
aee4e0db | 7114 | (define_insn "pool" |
fd7643fb | 7115 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db UW |
7116 | "" |
7117 | "* abort ();" | |
7118 | [(set_attr "op_type" "NN") | |
7119 | (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
9db1d521 | 7120 | |
4023fb28 UW |
7121 | ;; |
7122 | ;; Insns related to generating the function prologue and epilogue. | |
7123 | ;; | |
7124 | ||
7125 | ||
7126 | (define_expand "prologue" | |
7127 | [(use (const_int 0))] | |
7128 | "" | |
10bbf137 | 7129 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
7130 | |
7131 | (define_expand "epilogue" | |
7132 | [(use (const_int 1))] | |
7133 | "" | |
10bbf137 | 7134 | "s390_emit_epilogue (); DONE;") |
4023fb28 UW |
7135 | |
7136 | ||
7137 | (define_insn "*return_si" | |
7138 | [(return) | |
7139 | (use (match_operand:SI 0 "register_operand" "a"))] | |
7140 | "!TARGET_64BIT" | |
d40c829f | 7141 | "br\t%0" |
4023fb28 | 7142 | [(set_attr "op_type" "RR") |
c7453384 | 7143 | (set_attr "type" "jsr") |
077dab3b | 7144 | (set_attr "atype" "agen")]) |
4023fb28 UW |
7145 | |
7146 | (define_insn "*return_di" | |
7147 | [(return) | |
7148 | (use (match_operand:DI 0 "register_operand" "a"))] | |
7149 | "TARGET_64BIT" | |
d40c829f | 7150 | "br\t%0" |
4023fb28 | 7151 | [(set_attr "op_type" "RR") |
c7453384 | 7152 | (set_attr "type" "jsr") |
077dab3b | 7153 | (set_attr "atype" "agen")]) |
4023fb28 | 7154 | |
29742ba4 | 7155 | (define_insn "literal_pool_31" |
fd7643fb | 7156 | [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL) |
c7453384 EC |
7157 | (set (match_operand:SI 0 "register_operand" "=a") |
7158 | (label_ref (match_operand 1 "" ""))) | |
29742ba4 | 7159 | (use (label_ref (match_operand 2 "" "")))] |
4023fb28 | 7160 | "" |
4023fb28 | 7161 | { |
c7453384 | 7162 | if (s390_nr_constants) |
5c033b9f | 7163 | { |
d40c829f | 7164 | output_asm_insn ("bras\t%0,%2", operands); |
5c033b9f | 7165 | s390_output_constant_pool (operands[1], operands[2]); |
c7453384 | 7166 | } |
5c033b9f | 7167 | |
c7453384 | 7168 | return ""; |
5c033b9f | 7169 | } |
4023fb28 | 7170 | [(set_attr "op_type" "NN") |
077dab3b | 7171 | (set_attr "type" "larl")]) |
4023fb28 | 7172 | |
29742ba4 | 7173 | (define_insn "literal_pool_64" |
fd7643fb | 7174 | [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL) |
c7453384 EC |
7175 | (set (match_operand:DI 0 "register_operand" "=a") |
7176 | (label_ref (match_operand 1 "" ""))) | |
29742ba4 HP |
7177 | (use (label_ref (match_operand 2 "" "")))] |
7178 | "" | |
29742ba4 | 7179 | { |
c7453384 | 7180 | if (s390_nr_constants) |
5c033b9f | 7181 | { |
d40c829f | 7182 | output_asm_insn ("larl\t%0,%1", operands); |
5c033b9f UW |
7183 | s390_output_constant_pool (operands[1], operands[2]); |
7184 | } | |
7185 | ||
c7453384 | 7186 | return ""; |
5c033b9f | 7187 | } |
29742ba4 | 7188 | [(set_attr "op_type" "NN") |
077dab3b | 7189 | (set_attr "type" "larl")]) |
c7453384 EC |
7190 | |
7191 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit | |
7192 | ;; pointer. This is used for compatability. | |
7193 | ||
7194 | (define_expand "ptr_extend" | |
7195 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7196 | (match_operand:SI 1 "register_operand" "r"))] | |
7197 | "" | |
c7453384 | 7198 | { |
c7453384 EC |
7199 | emit_insn (gen_anddi3 (operands[0], |
7200 | gen_lowpart (DImode, operands[1]), | |
7201 | GEN_INT (0x7fffffff))); | |
c7453384 | 7202 | DONE; |
10bbf137 | 7203 | }) |