]>
Commit | Line | Data |
---|---|---|
9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
23a5b65a | 2 | ;; Copyright (C) 1999-2014 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
10bbf137 | 73 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
74 | UNSPEC_LTREL_OFFSET |
75 | UNSPEC_LTREL_BASE | |
76 | UNSPEC_POOL_OFFSET | |
77 | UNSPEC_GOTENT | |
78 | UNSPEC_GOT | |
79 | UNSPEC_GOTOFF | |
80 | UNSPEC_PLT | |
81 | UNSPEC_PLTOFF | |
fd7643fb UW |
82 | |
83 | ; Literal pool | |
30a49b23 AK |
84 | UNSPEC_RELOAD_BASE |
85 | UNSPEC_MAIN_BASE | |
86 | UNSPEC_LTREF | |
87 | UNSPEC_INSN | |
88 | UNSPEC_EXECUTE | |
fd7643fb | 89 | |
1a8c13b3 | 90 | ; Atomic Support |
30a49b23 | 91 | UNSPEC_MB |
78ce265b | 92 | UNSPEC_MOVA |
1a8c13b3 | 93 | |
fd7643fb | 94 | ; TLS relocation specifiers |
30a49b23 AK |
95 | UNSPEC_TLSGD |
96 | UNSPEC_TLSLDM | |
97 | UNSPEC_NTPOFF | |
98 | UNSPEC_DTPOFF | |
99 | UNSPEC_GOTNTPOFF | |
100 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
101 | |
102 | ; TLS support | |
30a49b23 AK |
103 | UNSPEC_TLSLDM_NTPOFF |
104 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
105 | |
106 | ; String Functions | |
30a49b23 AK |
107 | UNSPEC_SRST |
108 | UNSPEC_MVST | |
638e37c2 | 109 | |
7b8acc34 | 110 | ; Stack Smashing Protector |
30a49b23 AK |
111 | UNSPEC_SP_SET |
112 | UNSPEC_SP_TEST | |
85dae55a | 113 | |
638e37c2 | 114 | ; Test Data Class (TDC) |
30a49b23 | 115 | UNSPEC_TDC_INSN |
65b1d8ea AK |
116 | |
117 | ; Population Count | |
30a49b23 AK |
118 | UNSPEC_POPCNT |
119 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
120 | |
121 | ; Load FP Integer | |
122 | UNSPEC_FPINT_FLOOR | |
123 | UNSPEC_FPINT_BTRUNC | |
124 | UNSPEC_FPINT_ROUND | |
125 | UNSPEC_FPINT_CEIL | |
126 | UNSPEC_FPINT_NEARBYINT | |
127 | UNSPEC_FPINT_RINT | |
fd3cd001 UW |
128 | ]) |
129 | ||
130 | ;; | |
131 | ;; UNSPEC_VOLATILE usage | |
132 | ;; | |
133 | ||
30a49b23 AK |
134 | (define_c_enum "unspecv" [ |
135 | ; Blockage | |
136 | UNSPECV_BLOCKAGE | |
10bbf137 | 137 | |
2f7e5a0d | 138 | ; TPF Support |
30a49b23 AK |
139 | UNSPECV_TPF_PROLOGUE |
140 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 141 | |
10bbf137 | 142 | ; Literal pool |
30a49b23 AK |
143 | UNSPECV_POOL |
144 | UNSPECV_POOL_SECTION | |
145 | UNSPECV_POOL_ALIGN | |
146 | UNSPECV_POOL_ENTRY | |
147 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
148 | |
149 | ; TLS support | |
30a49b23 | 150 | UNSPECV_SET_TP |
e0374221 AS |
151 | |
152 | ; Atomic Support | |
30a49b23 AK |
153 | UNSPECV_CAS |
154 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 AK |
155 | |
156 | ; Transactional Execution support | |
157 | UNSPECV_TBEGIN | |
2561451d | 158 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
159 | UNSPECV_TBEGINC |
160 | UNSPECV_TEND | |
161 | UNSPECV_TABORT | |
162 | UNSPECV_ETND | |
163 | UNSPECV_NTSTG | |
164 | UNSPECV_PPA | |
fd3cd001 UW |
165 | ]) |
166 | ||
ae156f85 AS |
167 | ;; |
168 | ;; Registers | |
169 | ;; | |
170 | ||
35dd9a0e AK |
171 | ; Registers with special meaning |
172 | ||
ae156f85 AS |
173 | (define_constants |
174 | [ | |
175 | ; Sibling call register. | |
176 | (SIBCALL_REGNUM 1) | |
177 | ; Literal pool base register. | |
178 | (BASE_REGNUM 13) | |
179 | ; Return address register. | |
180 | (RETURN_REGNUM 14) | |
181 | ; Condition code register. | |
182 | (CC_REGNUM 33) | |
f4aa3848 | 183 | ; Thread local storage pointer register. |
ae156f85 AS |
184 | (TP_REGNUM 36) |
185 | ]) | |
186 | ||
35dd9a0e AK |
187 | ; Hardware register names |
188 | ||
189 | (define_constants | |
190 | [ | |
191 | ; General purpose registers | |
192 | (GPR0_REGNUM 0) | |
193 | ; Floating point registers. | |
194 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
195 | (FPR1_REGNUM 20) |
196 | (FPR2_REGNUM 17) | |
197 | (FPR3_REGNUM 21) | |
198 | (FPR4_REGNUM 18) | |
199 | (FPR5_REGNUM 22) | |
200 | (FPR6_REGNUM 19) | |
201 | (FPR7_REGNUM 23) | |
202 | (FPR8_REGNUM 24) | |
203 | (FPR9_REGNUM 28) | |
204 | (FPR10_REGNUM 25) | |
205 | (FPR11_REGNUM 29) | |
206 | (FPR12_REGNUM 26) | |
207 | (FPR13_REGNUM 30) | |
208 | (FPR14_REGNUM 27) | |
209 | (FPR15_REGNUM 31) | |
35dd9a0e AK |
210 | ]) |
211 | ||
212 | ;; | |
213 | ;; PFPO GPR0 argument format | |
214 | ;; | |
215 | ||
216 | (define_constants | |
217 | [ | |
218 | ; PFPO operation type | |
219 | (PFPO_CONVERT 0x1000000) | |
220 | ; PFPO operand types | |
221 | (PFPO_OP_TYPE_SF 0x5) | |
222 | (PFPO_OP_TYPE_DF 0x6) | |
223 | (PFPO_OP_TYPE_TF 0x7) | |
224 | (PFPO_OP_TYPE_SD 0x8) | |
225 | (PFPO_OP_TYPE_DD 0x9) | |
226 | (PFPO_OP_TYPE_TD 0xa) | |
227 | ; Bitposition of operand types | |
228 | (PFPO_OP0_TYPE_SHIFT 16) | |
229 | (PFPO_OP1_TYPE_SHIFT 8) | |
230 | ]) | |
231 | ||
5a3fe9b6 AK |
232 | ; Immediate operands for tbegin and tbeginc |
233 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
234 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 235 | |
29a74354 UW |
236 | ;; Instruction operand type as used in the Principles of Operation. |
237 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 238 | |
29a74354 | 239 | (define_attr "op_type" |
963fc8d0 | 240 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS" |
b628bd8e | 241 | (const_string "NN")) |
9db1d521 | 242 | |
29a74354 | 243 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 244 | |
077dab3b | 245 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 246 | cs,vs,store,sem,idiv, |
ed0e512a | 247 | imulhi,imulsi,imuldi, |
2cdece44 | 248 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
249 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
250 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 251 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 252 | fmadddf,fmaddsf, |
9381e3f1 WG |
253 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
254 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
255 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
256 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
257 | ftoidfp, other" | |
29a74354 UW |
258 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
259 | (eq_attr "op_type" "SS") (const_string "cs")] | |
260 | (const_string "integer"))) | |
9db1d521 | 261 | |
29a74354 UW |
262 | ;; Another attribute used for scheduling purposes: |
263 | ;; agen: Instruction uses the address generation unit | |
264 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
265 | |
266 | (define_attr "atype" "agen,reg" | |
c68e7b86 | 267 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") |
0101708c AS |
268 | (const_string "reg") |
269 | (const_string "agen"))) | |
9db1d521 | 270 | |
9381e3f1 WG |
271 | ;; Properties concerning Z10 execution grouping and value forwarding. |
272 | ;; z10_super: instruction is superscalar. | |
273 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
274 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
275 | ;; target register. It can forward this value to a second instruction that reads | |
276 | ;; the same register if that second instruction is issued in the same group. | |
277 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
278 | ;; instruction in the S pipe writes to the register, then the T instruction | |
279 | ;; can immediately read the new value. | |
280 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
281 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
282 | ;; |
283 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
284 | ||
285 | ||
286 | (define_attr "z10prop" "none, | |
287 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
288 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
289 | z10_rec, | |
290 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 291 | z10_c" |
9381e3f1 WG |
292 | (const_string "none")) |
293 | ||
65b1d8ea AK |
294 | ;; Properties concerning Z196 decoding |
295 | ;; z196_alone: must group alone | |
296 | ;; z196_end: ends a group | |
297 | ;; z196_cracked: instruction is cracked or expanded | |
298 | (define_attr "z196prop" "none, | |
299 | z196_alone, z196_ends, | |
300 | z196_cracked" | |
301 | (const_string "none")) | |
9381e3f1 | 302 | |
a9cc3f58 | 303 | (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 304 | |
9db1d521 HP |
305 | ;; Length in bytes. |
306 | ||
307 | (define_attr "length" "" | |
963fc8d0 AK |
308 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
309 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 310 | (const_int 6))) |
9db1d521 | 311 | |
29a74354 UW |
312 | |
313 | ;; Processor type. This attribute must exactly match the processor_type | |
314 | ;; enumeration in s390.h. The current machine description does not | |
315 | ;; distinguish between g5 and g6, but there are differences between the two | |
316 | ;; CPUs could in theory be modeled. | |
317 | ||
22ac2c2f | 318 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12" |
90c6fd8a | 319 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 320 | |
b5e0425c AK |
321 | (define_attr "cpu_facility" |
322 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12" | |
3af8e996 AK |
323 | (const_string "standard")) |
324 | ||
325 | (define_attr "enabled" "" | |
326 | (cond [(eq_attr "cpu_facility" "standard") | |
327 | (const_int 1) | |
328 | ||
329 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 330 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
331 | (const_int 1) |
332 | ||
333 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 334 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
335 | (const_int 1) |
336 | ||
337 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 338 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
339 | (const_int 1) |
340 | ||
341 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 342 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
343 | (const_int 1) |
344 | ||
345 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 346 | (match_test "TARGET_DFP")) |
93538e8e AK |
347 | (const_int 1) |
348 | ||
b5e0425c AK |
349 | (and (eq_attr "cpu_facility" "cpu_zarch") |
350 | (match_test "TARGET_CPU_ZARCH")) | |
351 | (const_int 1) | |
352 | ||
93538e8e | 353 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 354 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
355 | (const_int 1) |
356 | ||
357 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 358 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
359 | (const_int 1) |
360 | ||
361 | (and (eq_attr "cpu_facility" "zEC12") | |
362 | (match_test "TARGET_ZEC12")) | |
3af8e996 AK |
363 | (const_int 1)] |
364 | (const_int 0))) | |
365 | ||
29a74354 UW |
366 | ;; Pipeline description for z900. For lack of anything better, |
367 | ;; this description is also used for the g5 and g6. | |
368 | (include "2064.md") | |
369 | ||
3443392a | 370 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
371 | (include "2084.md") |
372 | ||
9381e3f1 WG |
373 | ;; Pipeline description for z10 |
374 | (include "2097.md") | |
375 | ||
65b1d8ea AK |
376 | ;; Pipeline description for z196 |
377 | (include "2817.md") | |
378 | ||
22ac2c2f AK |
379 | ;; Pipeline description for zEC12 |
380 | (include "2827.md") | |
381 | ||
0bfc3f69 AS |
382 | ;; Predicates |
383 | (include "predicates.md") | |
384 | ||
cd8dc1f9 WG |
385 | ;; Constraint definitions |
386 | (include "constraints.md") | |
387 | ||
a8ba31f2 EC |
388 | ;; Other includes |
389 | (include "tpf.md") | |
f52c81dd | 390 | |
3abcb3a7 | 391 | ;; Iterators |
f52c81dd | 392 | |
3abcb3a7 | 393 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 394 | ;; same template. |
f4aa3848 | 395 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 396 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 | 397 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
963fc8d0 | 398 | (define_mode_iterator FPALL [TF DF SF TD DD SD]) |
3abcb3a7 HPN |
399 | (define_mode_iterator BFP [TF DF SF]) |
400 | (define_mode_iterator DFP [TD DD]) | |
401 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
402 | (define_mode_iterator DSF [DF SF]) | |
403 | (define_mode_iterator SD_SF [SF SD]) | |
404 | (define_mode_iterator DD_DF [DF DD]) | |
405 | (define_mode_iterator TD_TF [TF TD]) | |
406 | ||
3abcb3a7 | 407 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 408 | ;; from the same template. |
9602b6a1 | 409 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 410 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 411 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 412 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 413 | |
3abcb3a7 | 414 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 415 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 416 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 417 | |
78ce265b RH |
418 | ;; These macros refer to the actual word_mode of the configuration. |
419 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
420 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
421 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
422 | ||
6e0d70c9 AK |
423 | ;; Used by the umul pattern to express modes having half the size. |
424 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
425 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
426 | ||
3abcb3a7 | 427 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 428 | ;; the same template. |
3abcb3a7 | 429 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 430 | |
3abcb3a7 | 431 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 432 | ;; same template. |
9602b6a1 | 433 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
963fc8d0 | 434 | (define_mode_iterator INTALL [TI DI SI HI QI]) |
78ce265b | 435 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
342cf42b | 436 | |
3abcb3a7 | 437 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 438 | ;; the same template. |
3abcb3a7 | 439 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 440 | |
d12a76f3 | 441 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
442 | (define_code_iterator IXOR [ior xor]) |
443 | ||
d12a76f3 AK |
444 | ;; This iterator is used to expand the patterns for the nearest |
445 | ;; integer functions. | |
446 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
447 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
448 | UNSPEC_FPINT_NEARBYINT]) | |
449 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
450 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
451 | (UNSPEC_FPINT_ROUND "round") | |
452 | (UNSPEC_FPINT_CEIL "ceil") | |
453 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
454 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
455 | (UNSPEC_FPINT_BTRUNC "5") | |
456 | (UNSPEC_FPINT_ROUND "1") | |
457 | (UNSPEC_FPINT_CEIL "6") | |
458 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
459 | ||
3abcb3a7 HPN |
460 | ;; This iterator and attribute allow to combine most atomic operations. |
461 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 462 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
f4aa3848 | 463 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") |
45d18331 | 464 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 465 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 466 | |
f4aa3848 | 467 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
468 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
469 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 470 | |
f4aa3848 AK |
471 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
472 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
473 | ;; SDmode. |
474 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 475 | |
609e7e80 | 476 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
477 | ;; Likewise for "<RXe>". |
478 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
479 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
480 | ||
609e7e80 | 481 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 482 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
483 | ;; dfp variants in a single insn definition. |
484 | ||
3abcb3a7 | 485 | ;; This attribute is used to set op_type accordingly. |
f4aa3848 | 486 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
609e7e80 AK |
487 | (DD "RRR") (SD "RRR")]) |
488 | ||
f4aa3848 | 489 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
490 | ;; first and the second operand match for bfp modes. |
491 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
492 | ||
f4aa3848 | 493 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
494 | ;; additional operand for the dfp instructions. |
495 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
496 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
497 | ||
f5905b37 | 498 | |
85dae55a AK |
499 | ;; This attribute is used in the operand constraint list |
500 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
501 | ;; TFmode values are represented by a fp register pair. Since the | |
502 | ;; sign bit instructions only handle single source and target fp registers | |
503 | ;; these instructions can only be used for TFmode values if the source and | |
504 | ;; target operand uses the same fp register. | |
505 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
506 | ||
609e7e80 AK |
507 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
508 | ;; This is used to disable the memory alternative in TFmode patterns. | |
509 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
510 | ||
3abcb3a7 | 511 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
512 | ;; within instruction mnemonics. |
513 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
514 | ||
0387c142 WG |
515 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
516 | ;; modes and to an empty string for bfp modes. | |
517 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
518 | ||
1b48c8cc AS |
519 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
520 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
521 | ;; version only operates on one register. | |
522 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
523 | ||
524 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
525 | ;; version only operates on one register. The DImode version needs an additional | |
526 | ;; register for the assembler output. | |
527 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
528 | |
529 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
530 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
531 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
532 | ||
533 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 534 | ;; pattern itself and the corresponding function calls. |
f337b930 | 535 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
536 | |
537 | ;; This attribute handles differences in the instruction 'type' and will result | |
538 | ;; in "RRE" for DImode and "RR" for SImode. | |
539 | (define_mode_attr E [(DI "E") (SI "")]) | |
540 | ||
3298c037 AK |
541 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
542 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
543 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
544 | ||
8006eaa6 AS |
545 | ;; This attribute handles differences in the instruction 'type' and will result |
546 | ;; in "RSE" for TImode and "RS" for DImode. | |
547 | (define_mode_attr TE [(TI "E") (DI "")]) | |
548 | ||
9a91a21f AS |
549 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
550 | ;; and "lcr" in SImode. | |
551 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 552 | |
3298c037 AK |
553 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
554 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
555 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
556 | ;; variant for long displacements. | |
557 | (define_mode_attr y [(DI "g") (SI "y")]) | |
558 | ||
9602b6a1 | 559 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
560 | ;; and "cds" in DImode. |
561 | (define_mode_attr tg [(TI "g") (DI "")]) | |
562 | ||
78ce265b RH |
563 | ;; In TDI templates, a string like "c<d>sg". |
564 | (define_mode_attr td [(TI "d") (DI "")]) | |
565 | ||
2f8f8434 AS |
566 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
567 | ;; and "cfdbr" in SImode. | |
568 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
569 | ||
65b1d8ea AK |
570 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
571 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
572 | ;; 3 operands shift instructions into the existing patterns. | |
573 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
574 | ||
f52c81dd AS |
575 | ;; ICM mask required to load MODE value into the lowest subreg |
576 | ;; of a SImode register. | |
577 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
578 | ||
f6ee577c AS |
579 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
580 | ;; HImode and "llgc" in QImode. | |
581 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
582 | ||
a1aed706 AS |
583 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
584 | ;; in SImode. | |
585 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
586 | ||
609e7e80 AK |
587 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
588 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
589 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
590 | ||
f52c81dd AS |
591 | ;; Maximum unsigned integer that fits in MODE. |
592 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
593 | ||
75ca1b39 RH |
594 | ;; Start and end field computations for RISBG et al. |
595 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
596 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
597 | ||
2542ef05 RH |
598 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
599 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
600 | ||
9db1d521 HP |
601 | ;; |
602 | ;;- Compare instructions. | |
603 | ;; | |
604 | ||
07893d4f | 605 | ; Test-under-Mask instructions |
9db1d521 | 606 | |
07893d4f | 607 | (define_insn "*tmqi_mem" |
ae156f85 | 608 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
609 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
610 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
611 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 612 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 613 | "@ |
fc0ea003 UW |
614 | tm\t%S0,%b1 |
615 | tmy\t%S0,%b1" | |
9381e3f1 WG |
616 | [(set_attr "op_type" "SI,SIY") |
617 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 618 | |
05b9aaaa | 619 | (define_insn "*tmdi_reg" |
ae156f85 | 620 | [(set (reg CC_REGNUM) |
f19a9af7 | 621 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 622 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
623 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
624 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 625 | "TARGET_ZARCH |
3ed99cc9 | 626 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
627 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
628 | "@ | |
629 | tmhh\t%0,%i1 | |
630 | tmhl\t%0,%i1 | |
631 | tmlh\t%0,%i1 | |
632 | tmll\t%0,%i1" | |
9381e3f1 WG |
633 | [(set_attr "op_type" "RI") |
634 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
635 | |
636 | (define_insn "*tmsi_reg" | |
ae156f85 | 637 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
638 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
639 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
640 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 641 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
642 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
643 | "@ | |
644 | tmh\t%0,%i1 | |
645 | tml\t%0,%i1" | |
729e750f WG |
646 | [(set_attr "op_type" "RI") |
647 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 648 | |
f52c81dd | 649 | (define_insn "*tm<mode>_full" |
ae156f85 | 650 | [(set (reg CC_REGNUM) |
f52c81dd AS |
651 | (compare (match_operand:HQI 0 "register_operand" "d") |
652 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 653 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 654 | "tml\t%0,<max_uint>" |
729e750f WG |
655 | [(set_attr "op_type" "RI") |
656 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 657 | |
07893d4f | 658 | |
08a5aaa2 | 659 | ; |
07893d4f | 660 | ; Load-and-Test instructions |
08a5aaa2 AS |
661 | ; |
662 | ||
c0220ea4 | 663 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
664 | |
665 | (define_insn "*tstdi_sign" | |
ae156f85 | 666 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
667 | (compare |
668 | (ashiftrt:DI | |
669 | (ashift:DI | |
670 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
671 | (const_int 32)) (const_int 32)) | |
672 | (match_operand:DI 1 "const0_operand" ""))) | |
673 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 674 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 675 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
676 | "ltgfr\t%2,%0 |
677 | ltgf\t%2,%0" | |
678 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
679 | (set_attr "cpu_facility" "*,z10") |
680 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 681 | |
43a09b63 | 682 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 683 | (define_insn "*tst<mode>_extimm" |
ec24698e | 684 | [(set (reg CC_REGNUM) |
fb492564 | 685 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
686 | (match_operand:GPR 1 "const0_operand" ""))) |
687 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 688 | (match_dup 0))] |
08a5aaa2 | 689 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 690 | "@ |
08a5aaa2 AS |
691 | lt<g>r\t%2,%0 |
692 | lt<g>\t%2,%0" | |
9381e3f1 | 693 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 694 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 695 | |
43a09b63 | 696 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 697 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 698 | [(set (reg CC_REGNUM) |
fb492564 | 699 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
700 | (match_operand:GPR 1 "const0_operand" ""))) |
701 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
702 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 703 | "@ |
08a5aaa2 AS |
704 | lt<g>r\t%0,%0 |
705 | lt<g>\t%2,%0" | |
9381e3f1 | 706 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 707 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 708 | |
07893d4f | 709 | (define_insn "*tstdi" |
ae156f85 | 710 | [(set (reg CC_REGNUM) |
07893d4f UW |
711 | (compare (match_operand:DI 0 "register_operand" "d") |
712 | (match_operand:DI 1 "const0_operand" ""))) | |
713 | (set (match_operand:DI 2 "register_operand" "=d") | |
714 | (match_dup 0))] | |
9602b6a1 | 715 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 716 | "ltgr\t%2,%0" |
9381e3f1 WG |
717 | [(set_attr "op_type" "RRE") |
718 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 719 | |
07893d4f | 720 | (define_insn "*tstsi" |
ae156f85 | 721 | [(set (reg CC_REGNUM) |
d3632d41 | 722 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 723 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 724 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 725 | (match_dup 0))] |
ec24698e | 726 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 727 | "@ |
d40c829f | 728 | ltr\t%2,%0 |
fc0ea003 UW |
729 | icm\t%2,15,%S0 |
730 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
731 | [(set_attr "op_type" "RR,RS,RSY") |
732 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 733 | |
07893d4f | 734 | (define_insn "*tstsi_cconly" |
ae156f85 | 735 | [(set (reg CC_REGNUM) |
d3632d41 | 736 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 737 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 738 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
739 | "s390_match_ccmode(insn, CCSmode)" |
740 | "@ | |
d40c829f | 741 | ltr\t%0,%0 |
fc0ea003 UW |
742 | icm\t%2,15,%S0 |
743 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
744 | [(set_attr "op_type" "RR,RS,RSY") |
745 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 746 | |
08a5aaa2 AS |
747 | (define_insn "*tstdi_cconly_31" |
748 | [(set (reg CC_REGNUM) | |
749 | (compare (match_operand:DI 0 "register_operand" "d") | |
750 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 751 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
752 | "srda\t%0,0" |
753 | [(set_attr "op_type" "RS") | |
754 | (set_attr "atype" "reg")]) | |
755 | ||
43a09b63 | 756 | ; ltr, ltgr |
08a5aaa2 | 757 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 758 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
759 | (compare (match_operand:GPR 0 "register_operand" "d") |
760 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 761 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 762 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
763 | [(set_attr "op_type" "RR<E>") |
764 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 765 | |
c0220ea4 | 766 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 767 | |
f52c81dd | 768 | (define_insn "*tst<mode>CCT" |
ae156f85 | 769 | [(set (reg CC_REGNUM) |
f52c81dd AS |
770 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
771 | (match_operand:HQI 1 "const0_operand" ""))) | |
772 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
773 | (match_dup 0))] |
774 | "s390_match_ccmode(insn, CCTmode)" | |
775 | "@ | |
f52c81dd AS |
776 | icm\t%2,<icm_lo>,%S0 |
777 | icmy\t%2,<icm_lo>,%S0 | |
778 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
779 | [(set_attr "op_type" "RS,RSY,RI") |
780 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
781 | |
782 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 783 | [(set (reg CC_REGNUM) |
d3632d41 | 784 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 785 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 786 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
787 | "s390_match_ccmode(insn, CCTmode)" |
788 | "@ | |
fc0ea003 UW |
789 | icm\t%2,3,%S0 |
790 | icmy\t%2,3,%S0 | |
d40c829f | 791 | tml\t%0,65535" |
9381e3f1 WG |
792 | [(set_attr "op_type" "RS,RSY,RI") |
793 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 794 | |
3af97654 | 795 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 796 | [(set (reg CC_REGNUM) |
d3632d41 | 797 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
798 | (match_operand:QI 1 "const0_operand" "")))] |
799 | "s390_match_ccmode(insn, CCTmode)" | |
800 | "@ | |
fc0ea003 UW |
801 | cli\t%S0,0 |
802 | cliy\t%S0,0 | |
d40c829f | 803 | tml\t%0,255" |
9381e3f1 | 804 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 805 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 806 | |
f52c81dd | 807 | (define_insn "*tst<mode>" |
ae156f85 | 808 | [(set (reg CC_REGNUM) |
f52c81dd AS |
809 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
810 | (match_operand:HQI 1 "const0_operand" ""))) | |
811 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
812 | (match_dup 0))] |
813 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 814 | "@ |
f52c81dd AS |
815 | icm\t%2,<icm_lo>,%S0 |
816 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
817 | [(set_attr "op_type" "RS,RSY") |
818 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 819 | |
f52c81dd | 820 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 821 | [(set (reg CC_REGNUM) |
f52c81dd AS |
822 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
823 | (match_operand:HQI 1 "const0_operand" ""))) | |
824 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 825 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 826 | "@ |
f52c81dd AS |
827 | icm\t%2,<icm_lo>,%S0 |
828 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
829 | [(set_attr "op_type" "RS,RSY") |
830 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 831 | |
9db1d521 | 832 | |
575f7c2b UW |
833 | ; Compare (equality) instructions |
834 | ||
835 | (define_insn "*cmpdi_cct" | |
ae156f85 | 836 | [(set (reg CC_REGNUM) |
ec24698e | 837 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 838 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 839 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
840 | "@ |
841 | cgr\t%0,%1 | |
f4f41b4e | 842 | cghi\t%0,%h1 |
ec24698e | 843 | cgfi\t%0,%1 |
575f7c2b | 844 | cg\t%0,%1 |
19b63d8e | 845 | #" |
9381e3f1 WG |
846 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
847 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
848 | |
849 | (define_insn "*cmpsi_cct" | |
ae156f85 | 850 | [(set (reg CC_REGNUM) |
ec24698e UW |
851 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
852 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 853 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
854 | "@ |
855 | cr\t%0,%1 | |
f4f41b4e | 856 | chi\t%0,%h1 |
ec24698e | 857 | cfi\t%0,%1 |
575f7c2b UW |
858 | c\t%0,%1 |
859 | cy\t%0,%1 | |
19b63d8e | 860 | #" |
9381e3f1 | 861 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 862 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 863 | |
07893d4f | 864 | ; Compare (signed) instructions |
4023fb28 | 865 | |
07893d4f | 866 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 867 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
868 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
869 | "d,RT,b")) | |
870 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 871 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 872 | "@ |
d40c829f | 873 | cgfr\t%0,%1 |
963fc8d0 AK |
874 | cgf\t%0,%1 |
875 | cgfrl\t%0,%1" | |
876 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 877 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 878 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 879 | |
9381e3f1 WG |
880 | |
881 | ||
07893d4f | 882 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 883 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
884 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
885 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 886 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 887 | "@ |
d40c829f | 888 | ch\t%0,%1 |
963fc8d0 AK |
889 | chy\t%0,%1 |
890 | chrl\t%0,%1" | |
891 | [(set_attr "op_type" "RX,RXY,RIL") | |
892 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
893 | (set_attr "type" "*,*,larl") |
894 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
895 | |
896 | (define_insn "*cmphi_ccs_z10" | |
897 | [(set (reg CC_REGNUM) | |
898 | (compare (match_operand:HI 0 "s_operand" "Q") | |
899 | (match_operand:HI 1 "immediate_operand" "K")))] | |
900 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
901 | "chhsi\t%0,%1" | |
65b1d8ea AK |
902 | [(set_attr "op_type" "SIL") |
903 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
904 | |
905 | (define_insn "*cmpdi_ccs_signhi_rl" | |
906 | [(set (reg CC_REGNUM) | |
907 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
908 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
909 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
910 | "@ | |
911 | cgh\t%0,%1 | |
912 | cghrl\t%0,%1" | |
913 | [(set_attr "op_type" "RXY,RIL") | |
914 | (set_attr "type" "*,larl")]) | |
4023fb28 | 915 | |
963fc8d0 | 916 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 917 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 918 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
919 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
920 | "d,d,Q, d,d,d,d") | |
921 | (match_operand:GPR 1 "general_operand" | |
922 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 923 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 924 | "@ |
3298c037 AK |
925 | c<g>r\t%0,%1 |
926 | c<g>hi\t%0,%h1 | |
963fc8d0 | 927 | c<g>hsi\t%0,%h1 |
3298c037 AK |
928 | c<g>fi\t%0,%1 |
929 | c<g>\t%0,%1 | |
963fc8d0 AK |
930 | c<y>\t%0,%1 |
931 | c<g>rl\t%0,%1" | |
932 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
933 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
934 | (set_attr "type" "*,*,*,*,*,*,larl") |
935 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 936 | |
07893d4f UW |
937 | |
938 | ; Compare (unsigned) instructions | |
9db1d521 | 939 | |
963fc8d0 AK |
940 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
941 | [(set (reg CC_REGNUM) | |
942 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
943 | "larl_operand" "X"))) | |
944 | (match_operand:SI 0 "register_operand" "d")))] | |
945 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
946 | "clhrl\t%0,%1" | |
947 | [(set_attr "op_type" "RIL") | |
729e750f WG |
948 | (set_attr "type" "larl") |
949 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
950 | |
951 | ; clhrl, clghrl | |
952 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
953 | [(set (reg CC_REGNUM) | |
954 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
955 | "larl_operand" "X"))) | |
956 | (match_operand:GPR 0 "register_operand" "d")))] | |
957 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
958 | "cl<g>hrl\t%0,%1" | |
959 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
960 | (set_attr "type" "larl") |
961 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 962 | |
07893d4f | 963 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 964 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
965 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
966 | "d,RT,b")) | |
967 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 968 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 969 | "@ |
d40c829f | 970 | clgfr\t%0,%1 |
963fc8d0 AK |
971 | clgf\t%0,%1 |
972 | clgfrl\t%0,%1" | |
973 | [(set_attr "op_type" "RRE,RXY,RIL") | |
974 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
975 | (set_attr "type" "*,*,larl") |
976 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 977 | |
07893d4f | 978 | (define_insn "*cmpdi_ccu" |
ae156f85 | 979 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
980 | (compare (match_operand:DI 0 "nonimmediate_operand" |
981 | "d, d,d,Q, d, Q,BQ") | |
982 | (match_operand:DI 1 "general_operand" | |
983 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 984 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 985 | "@ |
d40c829f | 986 | clgr\t%0,%1 |
ec24698e | 987 | clgfi\t%0,%1 |
963fc8d0 AK |
988 | clgrl\t%0,%1 |
989 | clghsi\t%0,%x1 | |
575f7c2b | 990 | clg\t%0,%1 |
e221ef54 | 991 | # |
19b63d8e | 992 | #" |
963fc8d0 AK |
993 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
994 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
995 | (set_attr "type" "*,*,larl,*,*,*,*") |
996 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 997 | |
07893d4f | 998 | (define_insn "*cmpsi_ccu" |
ae156f85 | 999 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1000 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1001 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1002 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1003 | "@ |
d40c829f | 1004 | clr\t%0,%1 |
ec24698e | 1005 | clfi\t%0,%o1 |
963fc8d0 AK |
1006 | clrl\t%0,%1 |
1007 | clfhsi\t%0,%x1 | |
d40c829f | 1008 | cl\t%0,%1 |
575f7c2b | 1009 | cly\t%0,%1 |
e221ef54 | 1010 | # |
19b63d8e | 1011 | #" |
963fc8d0 AK |
1012 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
1013 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
1014 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1015 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1016 | |
07893d4f | 1017 | (define_insn "*cmphi_ccu" |
ae156f85 | 1018 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1019 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1020 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1021 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1022 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1023 | "@ |
fc0ea003 UW |
1024 | clm\t%0,3,%S1 |
1025 | clmy\t%0,3,%S1 | |
963fc8d0 | 1026 | clhhsi\t%0,%1 |
e221ef54 | 1027 | # |
19b63d8e | 1028 | #" |
963fc8d0 | 1029 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
1030 | (set_attr "cpu_facility" "*,*,z10,*,*") |
1031 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
1032 | |
1033 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1034 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1035 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1036 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1037 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1038 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1039 | "@ |
fc0ea003 UW |
1040 | clm\t%0,1,%S1 |
1041 | clmy\t%0,1,%S1 | |
1042 | cli\t%S0,%b1 | |
1043 | cliy\t%S0,%b1 | |
e221ef54 | 1044 | # |
19b63d8e | 1045 | #" |
9381e3f1 WG |
1046 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
1047 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
1048 | |
1049 | ||
19b63d8e UW |
1050 | ; Block compare (CLC) instruction patterns. |
1051 | ||
1052 | (define_insn "*clc" | |
ae156f85 | 1053 | [(set (reg CC_REGNUM) |
d4f52f0e | 1054 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1055 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1056 | (use (match_operand 2 "const_int_operand" "n"))] | |
1057 | "s390_match_ccmode (insn, CCUmode) | |
1058 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1059 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1060 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1061 | |
1062 | (define_split | |
ae156f85 | 1063 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1064 | (compare (match_operand 0 "memory_operand" "") |
1065 | (match_operand 1 "memory_operand" "")))] | |
1066 | "reload_completed | |
1067 | && s390_match_ccmode (insn, CCUmode) | |
1068 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1069 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1070 | [(parallel | |
1071 | [(set (match_dup 0) (match_dup 1)) | |
1072 | (use (match_dup 2))])] | |
1073 | { | |
1074 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1075 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1076 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1077 | ||
1078 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1079 | operands[0], operands[1]); | |
1080 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1081 | }) | |
1082 | ||
1083 | ||
609e7e80 | 1084 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1085 | |
609e7e80 | 1086 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1087 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1088 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1089 | (compare (match_operand:FP 0 "register_operand" "f") |
1090 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1091 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1092 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1093 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1094 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1095 | |
be5de7a1 | 1096 | ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb |
f5905b37 | 1097 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1098 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1099 | (compare (match_operand:FP 0 "register_operand" "f,f") |
1100 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 1101 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1102 | "@ |
609e7e80 | 1103 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1104 | c<xde>b\t%0,%1" |
077dab3b | 1105 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 1106 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1107 | |
963fc8d0 AK |
1108 | |
1109 | ; Compare and Branch instructions | |
1110 | ||
1111 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1112 | ; The following instructions do a complementary access of their second |
1113 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1114 | (define_insn "*cmp_and_br_signed_<mode>" |
1115 | [(set (pc) | |
1116 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1117 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1118 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1119 | (label_ref (match_operand 3 "" "")) | |
1120 | (pc))) | |
1121 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1122 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1123 | { |
1124 | if (get_attr_length (insn) == 6) | |
1125 | return which_alternative ? | |
1126 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1127 | else | |
1128 | return which_alternative ? | |
1129 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1130 | } | |
1131 | [(set_attr "op_type" "RIE") | |
1132 | (set_attr "type" "branch") | |
e3cba5e5 | 1133 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1134 | (set (attr "length") |
1135 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1136 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1137 | ; 10 byte for cgr/jg | |
1138 | ||
1139 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1140 | ; The following instructions do a complementary access of their second |
1141 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1142 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1143 | [(set (pc) | |
1144 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1145 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1146 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1147 | (label_ref (match_operand 3 "" "")) | |
1148 | (pc))) | |
1149 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1150 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1151 | { |
1152 | if (get_attr_length (insn) == 6) | |
1153 | return which_alternative ? | |
1154 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1155 | else | |
1156 | return which_alternative ? | |
1157 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1158 | } | |
1159 | [(set_attr "op_type" "RIE") | |
1160 | (set_attr "type" "branch") | |
e3cba5e5 | 1161 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1162 | (set (attr "length") |
1163 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1164 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1165 | ; 10 byte for clgr/jg | |
1166 | ||
b0f86a7e AK |
1167 | ; And now the same two patterns as above but with a negated CC mask. |
1168 | ||
1169 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1170 | ; The following instructions do a complementary access of their second | |
1171 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1172 | (define_insn "*icmp_and_br_signed_<mode>" | |
1173 | [(set (pc) | |
1174 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1175 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1176 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1177 | (pc) | |
1178 | (label_ref (match_operand 3 "" "")))) | |
1179 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1180 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1181 | { |
1182 | if (get_attr_length (insn) == 6) | |
1183 | return which_alternative ? | |
1184 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1185 | else | |
1186 | return which_alternative ? | |
1187 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1188 | } | |
1189 | [(set_attr "op_type" "RIE") | |
1190 | (set_attr "type" "branch") | |
1191 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1192 | (set (attr "length") | |
1193 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1194 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1195 | ; 10 byte for cgr/jg | |
1196 | ||
1197 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1198 | ; The following instructions do a complementary access of their second | |
1199 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1200 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1201 | [(set (pc) | |
1202 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1203 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1204 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1205 | (pc) | |
1206 | (label_ref (match_operand 3 "" "")))) | |
1207 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1208 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1209 | { |
1210 | if (get_attr_length (insn) == 6) | |
1211 | return which_alternative ? | |
1212 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1213 | else | |
1214 | return which_alternative ? | |
1215 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1216 | } | |
1217 | [(set_attr "op_type" "RIE") | |
1218 | (set_attr "type" "branch") | |
1219 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1220 | (set (attr "length") | |
1221 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1222 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1223 | ; 10 byte for clgr/jg | |
1224 | ||
9db1d521 HP |
1225 | ;; |
1226 | ;;- Move instructions. | |
1227 | ;; | |
1228 | ||
1229 | ; | |
1230 | ; movti instruction pattern(s). | |
1231 | ; | |
1232 | ||
1233 | (define_insn "movti" | |
f2dc2f86 AK |
1234 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o") |
1235 | (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))] | |
9602b6a1 | 1236 | "TARGET_ZARCH" |
4023fb28 | 1237 | "@ |
fc0ea003 UW |
1238 | lmg\t%0,%N0,%S1 |
1239 | stmg\t%1,%N1,%S0 | |
4023fb28 | 1240 | # |
19b63d8e | 1241 | #" |
f2dc2f86 AK |
1242 | [(set_attr "op_type" "RSY,RSY,*,*") |
1243 | (set_attr "type" "lm,stm,*,*")]) | |
4023fb28 UW |
1244 | |
1245 | (define_split | |
1246 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1247 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1248 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1249 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1250 | [(set (match_dup 2) (match_dup 4)) |
1251 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1252 | { |
dc65c307 UW |
1253 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1254 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1255 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1256 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1257 | }) | |
1258 | ||
1259 | (define_split | |
1260 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1261 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1262 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1263 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1264 | [(set (match_dup 2) (match_dup 4)) | |
1265 | (set (match_dup 3) (match_dup 5))] | |
1266 | { | |
1267 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1268 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1269 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1270 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1271 | }) | |
4023fb28 UW |
1272 | |
1273 | (define_split | |
1274 | [(set (match_operand:TI 0 "register_operand" "") | |
1275 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1276 | "TARGET_ZARCH && reload_completed |
4023fb28 | 1277 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1278 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1279 | { |
1280 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1281 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1282 | s390_load_address (addr, XEXP (operands[1], 0)); |
1283 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1284 | }) |
1285 | ||
833cd70a AK |
1286 | |
1287 | ; | |
1288 | ; Patterns used for secondary reloads | |
1289 | ; | |
1290 | ||
963fc8d0 AK |
1291 | ; z10 provides move instructions accepting larl memory operands. |
1292 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1293 | ; These patterns are also used for unaligned SI and DI accesses. | |
1294 | ||
1295 | (define_expand "reload<INTALL:mode><P:mode>_tomem_z10" | |
1296 | [(parallel [(match_operand:INTALL 0 "memory_operand" "") | |
1297 | (match_operand:INTALL 1 "register_operand" "=d") | |
1298 | (match_operand:P 2 "register_operand" "=&a")])] | |
1299 | "TARGET_Z10" | |
1300 | { | |
1301 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1302 | DONE; | |
1303 | }) | |
1304 | ||
1305 | (define_expand "reload<INTALL:mode><P:mode>_toreg_z10" | |
1306 | [(parallel [(match_operand:INTALL 0 "register_operand" "=d") | |
1307 | (match_operand:INTALL 1 "memory_operand" "") | |
1308 | (match_operand:P 2 "register_operand" "=a")])] | |
1309 | "TARGET_Z10" | |
1310 | { | |
1311 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1312 | DONE; | |
1313 | }) | |
1314 | ||
1315 | (define_expand "reload<FPALL:mode><P:mode>_tomem_z10" | |
1316 | [(parallel [(match_operand:FPALL 0 "memory_operand" "") | |
1317 | (match_operand:FPALL 1 "register_operand" "=d") | |
1318 | (match_operand:P 2 "register_operand" "=&a")])] | |
1319 | "TARGET_Z10" | |
1320 | { | |
1321 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1322 | DONE; | |
1323 | }) | |
1324 | ||
1325 | (define_expand "reload<FPALL:mode><P:mode>_toreg_z10" | |
1326 | [(parallel [(match_operand:FPALL 0 "register_operand" "=d") | |
1327 | (match_operand:FPALL 1 "memory_operand" "") | |
1328 | (match_operand:P 2 "register_operand" "=a")])] | |
1329 | "TARGET_Z10" | |
1330 | { | |
1331 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1332 | DONE; | |
1333 | }) | |
1334 | ||
1335 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1336 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1337 | (match_operand:P 1 "larl_operand" "") | |
1338 | (match_operand:P 2 "register_operand" "=a")])] | |
1339 | "TARGET_Z10" | |
1340 | { | |
1341 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1342 | DONE; | |
1343 | }) | |
1344 | ||
833cd70a AK |
1345 | ; Handles loading a PLUS (load address) expression |
1346 | ||
1347 | (define_expand "reload<mode>_plus" | |
1348 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1349 | (match_operand:P 1 "s390_plus_operand" "") | |
1350 | (match_operand:P 2 "register_operand" "=&a")])] | |
1351 | "" | |
1352 | { | |
1353 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1354 | DONE; | |
1355 | }) | |
1356 | ||
1357 | ; Handles assessing a non-offsetable memory address | |
1358 | ||
1359 | (define_expand "reload<mode>_nonoffmem_in" | |
1360 | [(parallel [(match_operand 0 "register_operand" "") | |
1361 | (match_operand 1 "" "") | |
1362 | (match_operand:P 2 "register_operand" "=&a")])] | |
1363 | "" | |
1364 | { | |
1365 | gcc_assert (MEM_P (operands[1])); | |
1366 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1367 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1368 | emit_move_insn (operands[0], operands[1]); | |
1369 | DONE; | |
1370 | }) | |
1371 | ||
1372 | (define_expand "reload<mode>_nonoffmem_out" | |
1373 | [(parallel [(match_operand 0 "" "") | |
1374 | (match_operand 1 "register_operand" "") | |
1375 | (match_operand:P 2 "register_operand" "=&a")])] | |
1376 | "" | |
dc65c307 | 1377 | { |
9c3c3dcc | 1378 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1379 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1380 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1381 | emit_move_insn (operands[0], operands[1]); | |
1382 | DONE; | |
1383 | }) | |
9db1d521 | 1384 | |
1f9e1fc6 AK |
1385 | (define_expand "reload<mode>_PIC_addr" |
1386 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1387 | (match_operand 1 "larl_operand" "") | |
1388 | (match_operand:P 2 "register_operand" "=a")])] | |
1389 | "" | |
1390 | { | |
0a2aaacc KG |
1391 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1392 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1393 | }) |
1394 | ||
9db1d521 HP |
1395 | ; |
1396 | ; movdi instruction pattern(s). | |
1397 | ; | |
1398 | ||
9db1d521 HP |
1399 | (define_expand "movdi" |
1400 | [(set (match_operand:DI 0 "general_operand" "") | |
1401 | (match_operand:DI 1 "general_operand" ""))] | |
1402 | "" | |
9db1d521 | 1403 | { |
fd3cd001 | 1404 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1405 | if (TARGET_64BIT |
1406 | && (SYMBOLIC_CONST (operands[1]) | |
1407 | || (GET_CODE (operands[1]) == PLUS | |
1408 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1409 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1410 | emit_symbolic_move (operands); |
10bbf137 | 1411 | }) |
9db1d521 | 1412 | |
4023fb28 UW |
1413 | (define_insn "*movdi_larl" |
1414 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1415 | (match_operand:DI 1 "larl_operand" "X"))] | |
1416 | "TARGET_64BIT | |
8e509cf9 | 1417 | && !FP_REG_P (operands[0])" |
d40c829f | 1418 | "larl\t%0,%1" |
4023fb28 | 1419 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1420 | (set_attr "type" "larl") |
1421 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1422 | |
3af8e996 | 1423 | (define_insn "*movdi_64" |
85dae55a | 1424 | [(set (match_operand:DI 0 "nonimmediate_operand" |
963fc8d0 | 1425 | "=d,d,d,d,d,d,d,d,f,d,d,d,d,d, |
f2dc2f86 | 1426 | RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t") |
85dae55a | 1427 | (match_operand:DI 1 "general_operand" |
963fc8d0 | 1428 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, |
f2dc2f86 | 1429 | d,*f,R,T,*f,*f,d,K,t,d,t,Q"))] |
9602b6a1 | 1430 | "TARGET_ZARCH" |
85dae55a AK |
1431 | "@ |
1432 | lghi\t%0,%h1 | |
1433 | llihh\t%0,%i1 | |
1434 | llihl\t%0,%i1 | |
1435 | llilh\t%0,%i1 | |
1436 | llill\t%0,%i1 | |
1437 | lgfi\t%0,%1 | |
1438 | llihf\t%0,%k1 | |
1439 | llilf\t%0,%k1 | |
1440 | ldgr\t%0,%1 | |
1441 | lgdr\t%0,%1 | |
1442 | lay\t%0,%a1 | |
963fc8d0 | 1443 | lgrl\t%0,%1 |
85dae55a AK |
1444 | lgr\t%0,%1 |
1445 | lg\t%0,%1 | |
1446 | stg\t%1,%0 | |
1447 | ldr\t%0,%1 | |
1448 | ld\t%0,%1 | |
1449 | ldy\t%0,%1 | |
1450 | std\t%1,%0 | |
1451 | stdy\t%1,%0 | |
963fc8d0 AK |
1452 | stgrl\t%1,%0 |
1453 | mvghi\t%0,%1 | |
85dae55a AK |
1454 | # |
1455 | # | |
1456 | stam\t%1,%N1,%S0 | |
f2dc2f86 | 1457 | lam\t%0,%N0,%S1" |
963fc8d0 | 1458 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
f2dc2f86 | 1459 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS") |
963fc8d0 AK |
1460 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
1461 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*, | |
f2dc2f86 | 1462 | *,*") |
3af8e996 | 1463 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1464 | z10,*,*,*,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1465 | z10,z10,*,*,*,*") |
9381e3f1 WG |
1466 | (set_attr "z10prop" "z10_fwd_A1, |
1467 | z10_fwd_E1, | |
1468 | z10_fwd_E1, | |
1469 | z10_fwd_E1, | |
1470 | z10_fwd_E1, | |
1471 | z10_fwd_A1, | |
1472 | z10_fwd_E1, | |
1473 | z10_fwd_E1, | |
1474 | *, | |
1475 | *, | |
1476 | z10_fwd_A1, | |
1477 | z10_fwd_A3, | |
1478 | z10_fr_E1, | |
1479 | z10_fwd_A3, | |
1480 | z10_rec, | |
1481 | *, | |
1482 | *, | |
1483 | *, | |
1484 | *, | |
1485 | *, | |
1486 | z10_rec, | |
1487 | z10_super, | |
1488 | *, | |
1489 | *, | |
1490 | *, | |
9381e3f1 WG |
1491 | *") |
1492 | ]) | |
c5aa1d12 UW |
1493 | |
1494 | (define_split | |
1495 | [(set (match_operand:DI 0 "register_operand" "") | |
1496 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1497 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1498 | [(set (match_dup 2) (match_dup 3)) |
1499 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1500 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1501 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1502 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1503 | ||
1504 | (define_split | |
1505 | [(set (match_operand:DI 0 "register_operand" "") | |
1506 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1507 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1508 | && dead_or_set_p (insn, operands[1])" |
1509 | [(set (match_dup 3) (match_dup 2)) | |
1510 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1511 | (set (match_dup 4) (match_dup 2))] | |
1512 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1513 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1514 | ||
1515 | (define_split | |
1516 | [(set (match_operand:DI 0 "register_operand" "") | |
1517 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1518 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1519 | && !dead_or_set_p (insn, operands[1])" |
1520 | [(set (match_dup 3) (match_dup 2)) | |
1521 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1522 | (set (match_dup 4) (match_dup 2)) | |
1523 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1524 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1525 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1526 | |
1527 | (define_insn "*movdi_31" | |
963fc8d0 | 1528 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1529 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1530 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1531 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1532 | "!TARGET_ZARCH" |
4023fb28 | 1533 | "@ |
fc0ea003 | 1534 | lm\t%0,%N0,%S1 |
c4d50129 | 1535 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1536 | stm\t%1,%N1,%S0 |
c4d50129 | 1537 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1538 | # |
1539 | # | |
d40c829f UW |
1540 | ldr\t%0,%1 |
1541 | ld\t%0,%1 | |
1542 | ldy\t%0,%1 | |
1543 | std\t%1,%0 | |
1544 | stdy\t%1,%0 | |
19b63d8e | 1545 | #" |
f2dc2f86 AK |
1546 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1547 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1548 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1549 | |
1550 | ; For a load from a symbol ref we can use one of the target registers | |
1551 | ; together with larl to load the address. | |
1552 | (define_split | |
1553 | [(set (match_operand:DI 0 "register_operand" "") | |
1554 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1555 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1556 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1557 | [(set (match_dup 2) (match_dup 3)) | |
1558 | (set (match_dup 0) (match_dup 1))] | |
1559 | { | |
1560 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1561 | operands[3] = XEXP (operands[1], 0); | |
1562 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1563 | }) | |
4023fb28 UW |
1564 | |
1565 | (define_split | |
1566 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1567 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1568 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1569 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1570 | [(set (match_dup 2) (match_dup 4)) |
1571 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1572 | { |
dc65c307 UW |
1573 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1574 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1575 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1576 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1577 | }) | |
1578 | ||
1579 | (define_split | |
1580 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1581 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1582 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1583 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1584 | [(set (match_dup 2) (match_dup 4)) | |
1585 | (set (match_dup 3) (match_dup 5))] | |
1586 | { | |
1587 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1588 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1589 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1590 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1591 | }) | |
9db1d521 | 1592 | |
4023fb28 UW |
1593 | (define_split |
1594 | [(set (match_operand:DI 0 "register_operand" "") | |
1595 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1596 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1597 | && !FP_REG_P (operands[0]) |
4023fb28 | 1598 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1599 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1600 | { |
1601 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1602 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1603 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1604 | }) |
1605 | ||
84817c5d UW |
1606 | (define_peephole2 |
1607 | [(set (match_operand:DI 0 "register_operand" "") | |
1608 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1609 | "TARGET_ZARCH |
84817c5d UW |
1610 | && !FP_REG_P (operands[0]) |
1611 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1612 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1613 | && get_pool_mode (operands[1]) == DImode | |
1614 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1615 | [(set (match_dup 0) (match_dup 2))] | |
1616 | "operands[2] = get_pool_constant (operands[1]);") | |
1617 | ||
7bdff56f UW |
1618 | (define_insn "*la_64" |
1619 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1620 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1621 | "TARGET_64BIT" |
1622 | "@ | |
1623 | la\t%0,%a1 | |
1624 | lay\t%0,%a1" | |
1625 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1626 | (set_attr "type" "la") |
1627 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1628 | |
1629 | (define_peephole2 | |
1630 | [(parallel | |
1631 | [(set (match_operand:DI 0 "register_operand" "") | |
1632 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1633 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1634 | "TARGET_64BIT |
e1d5ee28 | 1635 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1636 | [(set (match_dup 0) (match_dup 1))] |
1637 | "") | |
1638 | ||
1639 | (define_peephole2 | |
1640 | [(set (match_operand:DI 0 "register_operand" "") | |
1641 | (match_operand:DI 1 "register_operand" "")) | |
1642 | (parallel | |
1643 | [(set (match_dup 0) | |
1644 | (plus:DI (match_dup 0) | |
1645 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1646 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1647 | "TARGET_64BIT |
1648 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1649 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1650 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1651 | "") | |
1652 | ||
9db1d521 HP |
1653 | ; |
1654 | ; movsi instruction pattern(s). | |
1655 | ; | |
1656 | ||
9db1d521 HP |
1657 | (define_expand "movsi" |
1658 | [(set (match_operand:SI 0 "general_operand" "") | |
1659 | (match_operand:SI 1 "general_operand" ""))] | |
1660 | "" | |
9db1d521 | 1661 | { |
fd3cd001 | 1662 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1663 | if (!TARGET_64BIT |
1664 | && (SYMBOLIC_CONST (operands[1]) | |
1665 | || (GET_CODE (operands[1]) == PLUS | |
1666 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1667 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1668 | emit_symbolic_move (operands); |
10bbf137 | 1669 | }) |
9db1d521 | 1670 | |
9e8327e3 UW |
1671 | (define_insn "*movsi_larl" |
1672 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1673 | (match_operand:SI 1 "larl_operand" "X"))] | |
1674 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1675 | && !FP_REG_P (operands[0])" | |
1676 | "larl\t%0,%1" | |
1677 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1678 | (set_attr "type" "larl") |
729e750f | 1679 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1680 | |
f19a9af7 | 1681 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1682 | [(set (match_operand:SI 0 "nonimmediate_operand" |
f2dc2f86 | 1683 | "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t") |
2f7e5a0d | 1684 | (match_operand:SI 1 "general_operand" |
f2dc2f86 | 1685 | "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))] |
f19a9af7 | 1686 | "TARGET_ZARCH" |
9db1d521 | 1687 | "@ |
f19a9af7 AK |
1688 | lhi\t%0,%h1 |
1689 | llilh\t%0,%i1 | |
1690 | llill\t%0,%i1 | |
ec24698e | 1691 | iilf\t%0,%o1 |
f19a9af7 | 1692 | lay\t%0,%a1 |
963fc8d0 | 1693 | lrl\t%0,%1 |
d40c829f UW |
1694 | lr\t%0,%1 |
1695 | l\t%0,%1 | |
1696 | ly\t%0,%1 | |
1697 | st\t%1,%0 | |
1698 | sty\t%1,%0 | |
1699 | ler\t%0,%1 | |
1700 | le\t%0,%1 | |
1701 | ley\t%0,%1 | |
1702 | ste\t%1,%0 | |
1703 | stey\t%1,%0 | |
c5aa1d12 UW |
1704 | ear\t%0,%1 |
1705 | sar\t%0,%1 | |
1706 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1707 | strl\t%1,%0 |
1708 | mvhi\t%0,%1 | |
f2dc2f86 | 1709 | lam\t%0,%0,%S1" |
963fc8d0 | 1710 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
f2dc2f86 | 1711 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS") |
9381e3f1 WG |
1712 | (set_attr "type" "*, |
1713 | *, | |
1714 | *, | |
1715 | *, | |
1716 | la, | |
1717 | larl, | |
1718 | lr, | |
1719 | load, | |
1720 | load, | |
1721 | store, | |
1722 | store, | |
1723 | floadsf, | |
1724 | floadsf, | |
1725 | floadsf, | |
1726 | fstoresf, | |
1727 | fstoresf, | |
1728 | *, | |
1729 | *, | |
1730 | *, | |
1731 | larl, | |
1732 | *, | |
9381e3f1 | 1733 | *") |
963fc8d0 | 1734 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
f2dc2f86 | 1735 | *,*,longdisp,*,longdisp,*,*,*,z10,z10,*") |
9381e3f1 WG |
1736 | (set_attr "z10prop" "z10_fwd_A1, |
1737 | z10_fwd_E1, | |
1738 | z10_fwd_E1, | |
1739 | z10_fwd_A1, | |
1740 | z10_fwd_A1, | |
1741 | z10_fwd_A3, | |
1742 | z10_fr_E1, | |
1743 | z10_fwd_A3, | |
1744 | z10_fwd_A3, | |
729e750f | 1745 | z10_rec, |
9381e3f1 WG |
1746 | z10_rec, |
1747 | *, | |
1748 | *, | |
1749 | *, | |
1750 | *, | |
1751 | *, | |
1752 | z10_super_E1, | |
1753 | z10_super, | |
1754 | *, | |
1755 | z10_rec, | |
1756 | z10_super, | |
9381e3f1 | 1757 | *")]) |
f19a9af7 AK |
1758 | |
1759 | (define_insn "*movsi_esa" | |
f2dc2f86 AK |
1760 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t") |
1761 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1762 | "!TARGET_ZARCH" |
1763 | "@ | |
1764 | lhi\t%0,%h1 | |
1765 | lr\t%0,%1 | |
1766 | l\t%0,%1 | |
1767 | st\t%1,%0 | |
1768 | ler\t%0,%1 | |
1769 | le\t%0,%1 | |
1770 | ste\t%1,%0 | |
c5aa1d12 UW |
1771 | ear\t%0,%1 |
1772 | sar\t%0,%1 | |
1773 | stam\t%1,%1,%S0 | |
f2dc2f86 AK |
1774 | lam\t%0,%0,%S1" |
1775 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS") | |
1776 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*") | |
9381e3f1 WG |
1777 | (set_attr "z10prop" "z10_fwd_A1, |
1778 | z10_fr_E1, | |
1779 | z10_fwd_A3, | |
729e750f | 1780 | z10_rec, |
9381e3f1 WG |
1781 | *, |
1782 | *, | |
1783 | *, | |
1784 | z10_super_E1, | |
1785 | z10_super, | |
1786 | *, | |
9381e3f1 WG |
1787 | *") |
1788 | ]) | |
9db1d521 | 1789 | |
84817c5d UW |
1790 | (define_peephole2 |
1791 | [(set (match_operand:SI 0 "register_operand" "") | |
1792 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1793 | "!FP_REG_P (operands[0]) | |
1794 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1795 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1796 | && get_pool_mode (operands[1]) == SImode | |
1797 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1798 | [(set (match_dup 0) (match_dup 2))] | |
1799 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1800 | |
7bdff56f UW |
1801 | (define_insn "*la_31" |
1802 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1803 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1804 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1805 | "@ | |
1806 | la\t%0,%a1 | |
1807 | lay\t%0,%a1" | |
1808 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1809 | (set_attr "type" "la") |
1810 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1811 | |
1812 | (define_peephole2 | |
1813 | [(parallel | |
1814 | [(set (match_operand:SI 0 "register_operand" "") | |
1815 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1816 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1817 | "!TARGET_64BIT |
e1d5ee28 | 1818 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1819 | [(set (match_dup 0) (match_dup 1))] |
1820 | "") | |
1821 | ||
1822 | (define_peephole2 | |
1823 | [(set (match_operand:SI 0 "register_operand" "") | |
1824 | (match_operand:SI 1 "register_operand" "")) | |
1825 | (parallel | |
1826 | [(set (match_dup 0) | |
1827 | (plus:SI (match_dup 0) | |
1828 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1829 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1830 | "!TARGET_64BIT |
1831 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1832 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1833 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1834 | "") | |
1835 | ||
1836 | (define_insn "*la_31_and" | |
1837 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1838 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
1839 | (const_int 2147483647)))] |
1840 | "!TARGET_64BIT" | |
1841 | "@ | |
1842 | la\t%0,%a1 | |
1843 | lay\t%0,%a1" | |
1844 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1845 | (set_attr "type" "la") |
1846 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1847 | |
1848 | (define_insn_and_split "*la_31_and_cc" | |
1849 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1850 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1851 | (const_int 2147483647))) | |
ae156f85 | 1852 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1853 | "!TARGET_64BIT" |
1854 | "#" | |
1855 | "&& reload_completed" | |
1856 | [(set (match_dup 0) | |
1857 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1858 | "" | |
1859 | [(set_attr "op_type" "RX") | |
1860 | (set_attr "type" "la")]) | |
1861 | ||
1862 | (define_insn "force_la_31" | |
1863 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1864 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
1865 | (use (const_int 0))] |
1866 | "!TARGET_64BIT" | |
1867 | "@ | |
1868 | la\t%0,%a1 | |
1869 | lay\t%0,%a1" | |
1870 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
1871 | (set_attr "type" "la") |
1872 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 1873 | |
9db1d521 HP |
1874 | ; |
1875 | ; movhi instruction pattern(s). | |
1876 | ; | |
1877 | ||
02ed3c5e UW |
1878 | (define_expand "movhi" |
1879 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1880 | (match_operand:HI 1 "general_operand" ""))] | |
1881 | "" | |
1882 | { | |
2f7e5a0d | 1883 | /* Make it explicit that loading a register from memory |
02ed3c5e | 1884 | always sign-extends (at least) to SImode. */ |
b3a13419 | 1885 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 1886 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1887 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1888 | { |
1889 | rtx tmp = gen_reg_rtx (SImode); | |
1890 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1891 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1892 | operands[1] = gen_lowpart (HImode, tmp); | |
1893 | } | |
1894 | }) | |
1895 | ||
1896 | (define_insn "*movhi" | |
f2dc2f86 AK |
1897 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q") |
1898 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))] | |
9db1d521 HP |
1899 | "" |
1900 | "@ | |
d40c829f UW |
1901 | lr\t%0,%1 |
1902 | lhi\t%0,%h1 | |
1903 | lh\t%0,%1 | |
1904 | lhy\t%0,%1 | |
963fc8d0 | 1905 | lhrl\t%0,%1 |
d40c829f UW |
1906 | sth\t%1,%0 |
1907 | sthy\t%1,%0 | |
963fc8d0 | 1908 | sthrl\t%1,%0 |
f2dc2f86 AK |
1909 | mvhhi\t%0,%1" |
1910 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL") | |
1911 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*") | |
1912 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10") | |
9381e3f1 WG |
1913 | (set_attr "z10prop" "z10_fr_E1, |
1914 | z10_fwd_A1, | |
1915 | z10_super_E1, | |
1916 | z10_super_E1, | |
1917 | z10_super_E1, | |
729e750f | 1918 | z10_rec, |
9381e3f1 WG |
1919 | z10_rec, |
1920 | z10_rec, | |
f2dc2f86 | 1921 | z10_super")]) |
9db1d521 | 1922 | |
84817c5d UW |
1923 | (define_peephole2 |
1924 | [(set (match_operand:HI 0 "register_operand" "") | |
1925 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1926 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1927 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1928 | && get_pool_mode (operands[1]) == HImode | |
1929 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1930 | [(set (match_dup 0) (match_dup 2))] | |
1931 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1932 | |
9db1d521 HP |
1933 | ; |
1934 | ; movqi instruction pattern(s). | |
1935 | ; | |
1936 | ||
02ed3c5e UW |
1937 | (define_expand "movqi" |
1938 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1939 | (match_operand:QI 1 "general_operand" ""))] | |
1940 | "" | |
1941 | { | |
c19ec8f9 | 1942 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1943 | is just as fast as a QImode load. */ |
b3a13419 | 1944 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 1945 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1946 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1947 | { |
9602b6a1 AK |
1948 | rtx tmp = gen_reg_rtx (DImode); |
1949 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
02ed3c5e UW |
1950 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1951 | operands[1] = gen_lowpart (QImode, tmp); | |
1952 | } | |
1953 | }) | |
4023fb28 | 1954 | |
02ed3c5e | 1955 | (define_insn "*movqi" |
0a88561f AK |
1956 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1957 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1958 | "" |
1959 | "@ | |
d40c829f UW |
1960 | lr\t%0,%1 |
1961 | lhi\t%0,%b1 | |
1962 | ic\t%0,%1 | |
1963 | icy\t%0,%1 | |
1964 | stc\t%1,%0 | |
1965 | stcy\t%1,%0 | |
fc0ea003 | 1966 | mvi\t%S0,%b1 |
0a88561f | 1967 | mviy\t%S0,%b1 |
b247e88a | 1968 | #" |
0a88561f AK |
1969 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1970 | (set_attr "type" "lr,*,*,*,store,store,store,store,*") | |
9381e3f1 WG |
1971 | (set_attr "z10prop" "z10_fr_E1, |
1972 | z10_fwd_A1, | |
1973 | z10_super_E1, | |
1974 | z10_super_E1, | |
729e750f | 1975 | z10_rec, |
9381e3f1 WG |
1976 | z10_rec, |
1977 | z10_super, | |
0a88561f AK |
1978 | z10_super, |
1979 | *")]) | |
9db1d521 | 1980 | |
84817c5d UW |
1981 | (define_peephole2 |
1982 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1983 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1984 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1985 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1986 | && get_pool_mode (operands[1]) == QImode | |
1987 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1988 | [(set (match_dup 0) (match_dup 2))] | |
1989 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1990 | |
9db1d521 | 1991 | ; |
05b9aaaa | 1992 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1993 | ; |
1994 | ||
1995 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1996 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1997 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1998 | "" |
d3632d41 | 1999 | "@ |
d40c829f UW |
2000 | ic\t%0,%1 |
2001 | icy\t%0,%1" | |
9381e3f1 | 2002 | [(set_attr "op_type" "RX,RXY") |
729e750f | 2003 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2004 | |
2005 | ; | |
2006 | ; movstricthi instruction pattern(s). | |
2007 | ; | |
2008 | ||
2009 | (define_insn "*movstricthi" | |
d3632d41 | 2010 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2011 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2012 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2013 | "" |
d3632d41 | 2014 | "@ |
fc0ea003 UW |
2015 | icm\t%0,3,%S1 |
2016 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
2017 | [(set_attr "op_type" "RS,RSY") |
2018 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
2019 | |
2020 | ; | |
2021 | ; movstrictsi instruction pattern(s). | |
2022 | ; | |
2023 | ||
05b9aaaa | 2024 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2025 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2026 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2027 | "TARGET_ZARCH" |
9db1d521 | 2028 | "@ |
d40c829f UW |
2029 | lr\t%0,%1 |
2030 | l\t%0,%1 | |
c5aa1d12 UW |
2031 | ly\t%0,%1 |
2032 | ear\t%0,%1" | |
2033 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
2034 | (set_attr "type" "lr,load,load,*") |
2035 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 2036 | |
f61a2c7d | 2037 | ; |
609e7e80 | 2038 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2039 | ; |
2040 | ||
609e7e80 AK |
2041 | (define_expand "mov<mode>" |
2042 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2043 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2044 | "" |
2045 | "") | |
2046 | ||
609e7e80 | 2047 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2048 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
2049 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 2050 | "TARGET_ZARCH" |
f61a2c7d | 2051 | "@ |
65b1d8ea | 2052 | lzxr\t%0 |
f61a2c7d AK |
2053 | lxr\t%0,%1 |
2054 | # | |
2055 | # | |
2056 | lmg\t%0,%N0,%S1 | |
2057 | stmg\t%1,%N1,%S0 | |
2058 | # | |
f61a2c7d | 2059 | #" |
65b1d8ea AK |
2060 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2061 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2062 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2063 | |
609e7e80 | 2064 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2065 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2066 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2067 | "!TARGET_ZARCH" |
f61a2c7d | 2068 | "@ |
65b1d8ea | 2069 | lzxr\t%0 |
f61a2c7d AK |
2070 | lxr\t%0,%1 |
2071 | # | |
f61a2c7d | 2072 | #" |
65b1d8ea AK |
2073 | [(set_attr "op_type" "RRE,RRE,*,*") |
2074 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2075 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2076 | |
2077 | ; TFmode in GPRs splitters | |
2078 | ||
2079 | (define_split | |
609e7e80 AK |
2080 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2081 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2082 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2083 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2084 | [(set (match_dup 2) (match_dup 4)) |
2085 | (set (match_dup 3) (match_dup 5))] | |
2086 | { | |
609e7e80 AK |
2087 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2088 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2089 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2090 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2091 | }) |
2092 | ||
2093 | (define_split | |
609e7e80 AK |
2094 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2095 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2096 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2097 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2098 | [(set (match_dup 2) (match_dup 4)) |
2099 | (set (match_dup 3) (match_dup 5))] | |
2100 | { | |
609e7e80 AK |
2101 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2102 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2103 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2104 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2105 | }) |
2106 | ||
2107 | (define_split | |
609e7e80 AK |
2108 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2109 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2110 | "TARGET_ZARCH && reload_completed |
f61a2c7d AK |
2111 | && !FP_REG_P (operands[0]) |
2112 | && !s_operand (operands[1], VOIDmode)" | |
2113 | [(set (match_dup 0) (match_dup 1))] | |
2114 | { | |
609e7e80 | 2115 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2116 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2117 | s390_load_address (addr, XEXP (operands[1], 0)); |
2118 | operands[1] = replace_equiv_address (operands[1], addr); | |
2119 | }) | |
2120 | ||
7b6baae1 | 2121 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2122 | |
2123 | (define_split | |
609e7e80 AK |
2124 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2125 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2126 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2127 | && FP_REG_P (operands[0])" |
2128 | [(set (match_dup 2) (match_dup 4)) | |
2129 | (set (match_dup 3) (match_dup 5))] | |
2130 | { | |
609e7e80 AK |
2131 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2132 | <MODE>mode, 0); | |
2133 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2134 | <MODE>mode, 8); | |
2135 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2136 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2137 | }) |
2138 | ||
2139 | (define_split | |
609e7e80 AK |
2140 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2141 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2142 | "reload_completed && offsettable_memref_p (operands[0]) |
2143 | && FP_REG_P (operands[1])" | |
2144 | [(set (match_dup 2) (match_dup 4)) | |
2145 | (set (match_dup 3) (match_dup 5))] | |
2146 | { | |
609e7e80 AK |
2147 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2148 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2149 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2150 | <MODE>mode, 0); | |
2151 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2152 | <MODE>mode, 8); | |
f61a2c7d AK |
2153 | }) |
2154 | ||
9db1d521 | 2155 | ; |
609e7e80 | 2156 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2157 | ; |
2158 | ||
609e7e80 AK |
2159 | (define_expand "mov<mode>" |
2160 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2161 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2162 | "" |
13c025c1 | 2163 | "") |
9db1d521 | 2164 | |
609e7e80 AK |
2165 | (define_insn "*mov<mode>_64dfp" |
2166 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2167 | "=f,f,f,d,f,f,R,T,d,d, d,RT") |
609e7e80 | 2168 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2169 | " G,f,d,f,R,T,f,f,G,d,RT, d"))] |
9602b6a1 | 2170 | "TARGET_DFP" |
85dae55a | 2171 | "@ |
65b1d8ea | 2172 | lzdr\t%0 |
85dae55a AK |
2173 | ldr\t%0,%1 |
2174 | ldgr\t%0,%1 | |
2175 | lgdr\t%0,%1 | |
2176 | ld\t%0,%1 | |
2177 | ldy\t%0,%1 | |
2178 | std\t%1,%0 | |
2179 | stdy\t%1,%0 | |
45e5214c | 2180 | lghi\t%0,0 |
85dae55a AK |
2181 | lgr\t%0,%1 |
2182 | lg\t%0,%1 | |
f2dc2f86 | 2183 | stg\t%1,%0" |
65b1d8ea AK |
2184 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2185 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, | |
45e5214c | 2186 | fstoredf,fstoredf,*,lr,load,store") |
65b1d8ea AK |
2187 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") |
2188 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
85dae55a | 2189 | |
609e7e80 | 2190 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2191 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT") |
2192 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))] | |
9602b6a1 | 2193 | "TARGET_ZARCH" |
9db1d521 | 2194 | "@ |
65b1d8ea | 2195 | lzdr\t%0 |
d40c829f UW |
2196 | ldr\t%0,%1 |
2197 | ld\t%0,%1 | |
2198 | ldy\t%0,%1 | |
2199 | std\t%1,%0 | |
2200 | stdy\t%1,%0 | |
45e5214c | 2201 | lghi\t%0,0 |
d40c829f UW |
2202 | lgr\t%0,%1 |
2203 | lg\t%0,%1 | |
f2dc2f86 | 2204 | stg\t%1,%0" |
65b1d8ea AK |
2205 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY") |
2206 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2207 | fstore<mode>,fstore<mode>,*,lr,load,store") | |
2208 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec") | |
2209 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")]) | |
609e7e80 AK |
2210 | |
2211 | (define_insn "*mov<mode>_31" | |
2212 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2213 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2214 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2215 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2216 | "!TARGET_ZARCH" |
9db1d521 | 2217 | "@ |
65b1d8ea | 2218 | lzdr\t%0 |
d40c829f UW |
2219 | ldr\t%0,%1 |
2220 | ld\t%0,%1 | |
2221 | ldy\t%0,%1 | |
2222 | std\t%1,%0 | |
2223 | stdy\t%1,%0 | |
fc0ea003 | 2224 | lm\t%0,%N0,%S1 |
c4d50129 | 2225 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2226 | stm\t%1,%N1,%S0 |
c4d50129 | 2227 | stmy\t%1,%N1,%S0 |
4023fb28 | 2228 | # |
19b63d8e | 2229 | #" |
65b1d8ea AK |
2230 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2231 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2232 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2233 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2234 | |
2235 | (define_split | |
609e7e80 AK |
2236 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2237 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2238 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2239 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2240 | [(set (match_dup 2) (match_dup 4)) |
2241 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2242 | { |
609e7e80 AK |
2243 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2244 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2245 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2246 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2247 | }) |
2248 | ||
2249 | (define_split | |
609e7e80 AK |
2250 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2251 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2252 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2253 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2254 | [(set (match_dup 2) (match_dup 4)) |
2255 | (set (match_dup 3) (match_dup 5))] | |
2256 | { | |
609e7e80 AK |
2257 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2258 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2259 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2260 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2261 | }) |
9db1d521 | 2262 | |
4023fb28 | 2263 | (define_split |
609e7e80 AK |
2264 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2265 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2266 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2267 | && !FP_REG_P (operands[0]) |
4023fb28 | 2268 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2269 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2270 | { |
609e7e80 | 2271 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2272 | s390_load_address (addr, XEXP (operands[1], 0)); |
2273 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2274 | }) |
2275 | ||
9db1d521 | 2276 | ; |
609e7e80 | 2277 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2278 | ; |
2279 | ||
609e7e80 AK |
2280 | (define_insn "mov<mode>" |
2281 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
65b1d8ea | 2282 | "=f,f,f,f,R,T,d,d,d,d,R,T") |
609e7e80 | 2283 | (match_operand:SD_SF 1 "general_operand" |
65b1d8ea | 2284 | " G,f,R,T,f,f,G,d,R,T,d,d"))] |
4023fb28 | 2285 | "" |
9db1d521 | 2286 | "@ |
65b1d8ea | 2287 | lzer\t%0 |
d40c829f UW |
2288 | ler\t%0,%1 |
2289 | le\t%0,%1 | |
2290 | ley\t%0,%1 | |
2291 | ste\t%1,%0 | |
2292 | stey\t%1,%0 | |
45e5214c | 2293 | lhi\t%0,0 |
d40c829f UW |
2294 | lr\t%0,%1 |
2295 | l\t%0,%1 | |
2296 | ly\t%0,%1 | |
2297 | st\t%1,%0 | |
f2dc2f86 | 2298 | sty\t%1,%0" |
65b1d8ea AK |
2299 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY") |
2300 | (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>, | |
2301 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") | |
2302 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2303 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2304 | |
9dc62c00 AK |
2305 | ; |
2306 | ; movcc instruction pattern | |
2307 | ; | |
2308 | ||
2309 | (define_insn "movcc" | |
2310 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2311 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2312 | "" |
2313 | "@ | |
2314 | lr\t%0,%1 | |
2315 | tmh\t%1,12288 | |
2316 | ipm\t%0 | |
a71f0749 DV |
2317 | l\t%0,%1 |
2318 | ly\t%0,%1 | |
2319 | st\t%1,%0 | |
2320 | sty\t%1,%0" | |
8dd3b235 | 2321 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 DV |
2322 | (set_attr "type" "lr,*,*,load,load,store,store") |
2323 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
65b1d8ea | 2324 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2325 | |
19b63d8e UW |
2326 | ; |
2327 | ; Block move (MVC) patterns. | |
2328 | ; | |
2329 | ||
2330 | (define_insn "*mvc" | |
2331 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2332 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2333 | (use (match_operand 2 "const_int_operand" "n"))] | |
2334 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2335 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2336 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2337 | |
0a88561f AK |
2338 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2339 | ; order to have it implemented with mvc. | |
2340 | ||
2341 | (define_split | |
2342 | [(set (match_operand:QI 0 "memory_operand" "") | |
2343 | (match_operand:QI 1 "memory_operand" ""))] | |
2344 | "reload_completed" | |
2345 | [(parallel | |
2346 | [(set (match_dup 0) (match_dup 1)) | |
2347 | (use (const_int 1))])] | |
2348 | { | |
2349 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2350 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2351 | }) | |
2352 | ||
2353 | ||
19b63d8e UW |
2354 | (define_peephole2 |
2355 | [(parallel | |
2356 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2357 | (match_operand:BLK 1 "memory_operand" "")) | |
2358 | (use (match_operand 2 "const_int_operand" ""))]) | |
2359 | (parallel | |
2360 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2361 | (match_operand:BLK 4 "memory_operand" "")) | |
2362 | (use (match_operand 5 "const_int_operand" ""))])] | |
2363 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2364 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2365 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2366 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2367 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2368 | [(parallel | |
2369 | [(set (match_dup 6) (match_dup 7)) | |
2370 | (use (match_dup 8))])] | |
2371 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2372 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2373 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2374 | ||
2375 | ||
9db1d521 HP |
2376 | ; |
2377 | ; load_multiple pattern(s). | |
2378 | ; | |
22ea6b4f UW |
2379 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2380 | ; we currently support load_multiple/store_multiple only after reload. | |
2381 | ; | |
9db1d521 HP |
2382 | |
2383 | (define_expand "load_multiple" | |
2384 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2385 | (match_operand 1 "" "")) | |
2386 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2387 | "reload_completed" |
9db1d521 | 2388 | { |
c19ec8f9 | 2389 | enum machine_mode mode; |
9db1d521 HP |
2390 | int regno; |
2391 | int count; | |
2392 | rtx from; | |
4023fb28 | 2393 | int i, off; |
9db1d521 HP |
2394 | |
2395 | /* Support only loading a constant number of fixed-point registers from | |
2396 | memory and only bother with this if more than two */ | |
2397 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2398 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2399 | || INTVAL (operands[2]) > 16 |
2400 | || GET_CODE (operands[1]) != MEM | |
2401 | || GET_CODE (operands[0]) != REG | |
2402 | || REGNO (operands[0]) >= 16) | |
2403 | FAIL; | |
2404 | ||
2405 | count = INTVAL (operands[2]); | |
2406 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2407 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2408 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2409 | FAIL; |
9db1d521 HP |
2410 | |
2411 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2412 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2413 | { |
2414 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2415 | { | |
2416 | from = XEXP (operands[1], 0); | |
2417 | off = 0; | |
2418 | } | |
2419 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2420 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2421 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2422 | { | |
2423 | from = XEXP (XEXP (operands[1], 0), 0); | |
2424 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2425 | } | |
2426 | else | |
2427 | FAIL; | |
4023fb28 UW |
2428 | } |
2429 | else | |
2430 | { | |
2431 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2432 | off = 0; | |
2433 | } | |
9db1d521 HP |
2434 | |
2435 | for (i = 0; i < count; i++) | |
2436 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
2437 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
2438 | change_address (operands[1], mode, | |
0a81f074 RS |
2439 | plus_constant (Pmode, from, |
2440 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2441 | }) |
9db1d521 HP |
2442 | |
2443 | (define_insn "*load_multiple_di" | |
2444 | [(match_parallel 0 "load_multiple_operation" | |
2445 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2446 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2447 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2448 | { |
2449 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2450 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2451 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2452 | } |
d3632d41 | 2453 | [(set_attr "op_type" "RSY") |
4023fb28 | 2454 | (set_attr "type" "lm")]) |
9db1d521 HP |
2455 | |
2456 | (define_insn "*load_multiple_si" | |
2457 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2458 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2459 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2460 | "reload_completed" |
9db1d521 HP |
2461 | { |
2462 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2463 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2464 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2465 | } |
d3632d41 | 2466 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2467 | (set_attr "type" "lm")]) |
9db1d521 HP |
2468 | |
2469 | ; | |
c7453384 | 2470 | ; store multiple pattern(s). |
9db1d521 HP |
2471 | ; |
2472 | ||
2473 | (define_expand "store_multiple" | |
2474 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2475 | (match_operand 1 "" "")) | |
2476 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2477 | "reload_completed" |
9db1d521 | 2478 | { |
c19ec8f9 | 2479 | enum machine_mode mode; |
9db1d521 HP |
2480 | int regno; |
2481 | int count; | |
2482 | rtx to; | |
4023fb28 | 2483 | int i, off; |
9db1d521 HP |
2484 | |
2485 | /* Support only storing a constant number of fixed-point registers to | |
2486 | memory and only bother with this if more than two. */ | |
2487 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2488 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2489 | || INTVAL (operands[2]) > 16 |
2490 | || GET_CODE (operands[0]) != MEM | |
2491 | || GET_CODE (operands[1]) != REG | |
2492 | || REGNO (operands[1]) >= 16) | |
2493 | FAIL; | |
2494 | ||
2495 | count = INTVAL (operands[2]); | |
2496 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2497 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2498 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2499 | FAIL; |
9db1d521 HP |
2500 | |
2501 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2502 | |
b3a13419 | 2503 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2504 | { |
2505 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2506 | { | |
2507 | to = XEXP (operands[0], 0); | |
2508 | off = 0; | |
2509 | } | |
2510 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2511 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2512 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2513 | { | |
2514 | to = XEXP (XEXP (operands[0], 0), 0); | |
2515 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2516 | } | |
2517 | else | |
2518 | FAIL; | |
4023fb28 | 2519 | } |
c7453384 | 2520 | else |
4023fb28 UW |
2521 | { |
2522 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2523 | off = 0; | |
2524 | } | |
9db1d521 HP |
2525 | |
2526 | for (i = 0; i < count; i++) | |
2527 | XVECEXP (operands[3], 0, i) | |
2528 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 | 2529 | change_address (operands[0], mode, |
0a81f074 RS |
2530 | plus_constant (Pmode, to, |
2531 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2532 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2533 | }) |
9db1d521 HP |
2534 | |
2535 | (define_insn "*store_multiple_di" | |
2536 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2537 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2538 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2539 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2540 | { |
2541 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2542 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2543 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2544 | } |
d3632d41 | 2545 | [(set_attr "op_type" "RSY") |
4023fb28 | 2546 | (set_attr "type" "stm")]) |
9db1d521 HP |
2547 | |
2548 | ||
2549 | (define_insn "*store_multiple_si" | |
2550 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2551 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2552 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2553 | "reload_completed" |
9db1d521 HP |
2554 | { |
2555 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2556 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2557 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2558 | } |
d3632d41 | 2559 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2560 | (set_attr "type" "stm")]) |
9db1d521 HP |
2561 | |
2562 | ;; | |
2563 | ;; String instructions. | |
2564 | ;; | |
2565 | ||
963fc8d0 | 2566 | (define_insn "*execute_rl" |
2771c2f9 | 2567 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2568 | [(unspec [(match_operand 1 "register_operand" "a") |
2569 | (match_operand 2 "" "") | |
2570 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2571 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2572 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2573 | "exrl\t%1,%3" | |
2574 | [(set_attr "op_type" "RIL") | |
2575 | (set_attr "type" "cs")]) | |
2576 | ||
9bb86f41 | 2577 | (define_insn "*execute" |
2771c2f9 | 2578 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2579 | [(unspec [(match_operand 1 "register_operand" "a") |
2580 | (match_operand:BLK 2 "memory_operand" "R") | |
2581 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2582 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2583 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2584 | "ex\t%1,%2" | |
29a74354 UW |
2585 | [(set_attr "op_type" "RX") |
2586 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2587 | |
2588 | ||
91d39d71 UW |
2589 | ; |
2590 | ; strlenM instruction pattern(s). | |
2591 | ; | |
2592 | ||
9db2f16d | 2593 | (define_expand "strlen<mode>" |
ccbdc0d4 | 2594 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2595 | (parallel |
91d39d71 | 2596 | [(set (match_dup 4) |
9db2f16d | 2597 | (unspec:P [(const_int 0) |
91d39d71 | 2598 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2599 | (reg:SI 0) |
91d39d71 | 2600 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2601 | (clobber (scratch:P)) |
ae156f85 | 2602 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2603 | (parallel |
9db2f16d AS |
2604 | [(set (match_operand:P 0 "register_operand" "") |
2605 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2606 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2607 | "" |
91d39d71 | 2608 | { |
9db2f16d AS |
2609 | operands[4] = gen_reg_rtx (Pmode); |
2610 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2611 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2612 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2613 | }) | |
2614 | ||
9db2f16d AS |
2615 | (define_insn "*strlen<mode>" |
2616 | [(set (match_operand:P 0 "register_operand" "=a") | |
2617 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2618 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2619 | (reg:SI 0) |
91d39d71 | 2620 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2621 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2622 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2623 | "" |
91d39d71 | 2624 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2625 | [(set_attr "length" "8") |
2626 | (set_attr "type" "vs")]) | |
91d39d71 | 2627 | |
ccbdc0d4 AS |
2628 | ; |
2629 | ; cmpstrM instruction pattern(s). | |
2630 | ; | |
2631 | ||
2632 | (define_expand "cmpstrsi" | |
2633 | [(set (reg:SI 0) (const_int 0)) | |
2634 | (parallel | |
2635 | [(clobber (match_operand 3 "" "")) | |
2636 | (clobber (match_dup 4)) | |
2637 | (set (reg:CCU CC_REGNUM) | |
2638 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2639 | (match_operand:BLK 2 "memory_operand" ""))) | |
2640 | (use (reg:SI 0))]) | |
2641 | (parallel | |
2642 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2643 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
2644 | (clobber (reg:CC CC_REGNUM))])] |
2645 | "" | |
2646 | { | |
2647 | /* As the result of CMPINT is inverted compared to what we need, | |
2648 | we have to swap the operands. */ | |
2649 | rtx op1 = operands[2]; | |
2650 | rtx op2 = operands[1]; | |
2651 | rtx addr1 = gen_reg_rtx (Pmode); | |
2652 | rtx addr2 = gen_reg_rtx (Pmode); | |
2653 | ||
2654 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2655 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2656 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2657 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2658 | operands[3] = addr1; | |
2659 | operands[4] = addr2; | |
2660 | }) | |
2661 | ||
2662 | (define_insn "*cmpstr<mode>" | |
2663 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2664 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2665 | (set (reg:CCU CC_REGNUM) | |
2666 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2667 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2668 | (use (reg:SI 0))] | |
2669 | "" | |
2670 | "clst\t%0,%1\;jo\t.-4" | |
2671 | [(set_attr "length" "8") | |
2672 | (set_attr "type" "vs")]) | |
9381e3f1 | 2673 | |
742090fc AS |
2674 | ; |
2675 | ; movstr instruction pattern. | |
2676 | ; | |
2677 | ||
2678 | (define_expand "movstr" | |
2679 | [(set (reg:SI 0) (const_int 0)) | |
9381e3f1 | 2680 | (parallel |
742090fc AS |
2681 | [(clobber (match_dup 3)) |
2682 | (set (match_operand:BLK 1 "memory_operand" "") | |
2683 | (match_operand:BLK 2 "memory_operand" "")) | |
2684 | (set (match_operand 0 "register_operand" "") | |
9381e3f1 | 2685 | (unspec [(match_dup 1) |
742090fc AS |
2686 | (match_dup 2) |
2687 | (reg:SI 0)] UNSPEC_MVST)) | |
2688 | (clobber (reg:CC CC_REGNUM))])] | |
2689 | "" | |
2690 | { | |
2691 | rtx addr1 = gen_reg_rtx (Pmode); | |
2692 | rtx addr2 = gen_reg_rtx (Pmode); | |
2693 | ||
2694 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2695 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2696 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2697 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2698 | operands[3] = addr2; | |
2699 | }) | |
2700 | ||
2701 | (define_insn "*movstr" | |
2702 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2703 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2704 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2705 | (set (match_operand:P 0 "register_operand" "=d") | |
9381e3f1 | 2706 | (unspec [(mem:BLK (match_dup 1)) |
742090fc AS |
2707 | (mem:BLK (match_dup 3)) |
2708 | (reg:SI 0)] UNSPEC_MVST)) | |
2709 | (clobber (reg:CC CC_REGNUM))] | |
2710 | "" | |
2711 | "mvst\t%1,%2\;jo\t.-4" | |
2712 | [(set_attr "length" "8") | |
2713 | (set_attr "type" "vs")]) | |
9381e3f1 | 2714 | |
742090fc | 2715 | |
9db1d521 | 2716 | ; |
70128ad9 | 2717 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2718 | ; |
2719 | ||
9db2f16d | 2720 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2721 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2722 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2723 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2724 | (match_operand 3 "" "")] |
2725 | "" | |
367d32f3 AK |
2726 | { |
2727 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
2728 | DONE; | |
2729 | else | |
2730 | FAIL; | |
2731 | }) | |
9db1d521 | 2732 | |
ecbe845e UW |
2733 | ; Move a block that is up to 256 bytes in length. |
2734 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2735 | |
70128ad9 | 2736 | (define_expand "movmem_short" |
b9404c99 UW |
2737 | [(parallel |
2738 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2739 | (match_operand:BLK 1 "memory_operand" "")) | |
2740 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2741 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2742 | (clobber (match_dup 3))])] |
2743 | "" | |
2744 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2745 | |
70128ad9 | 2746 | (define_insn "*movmem_short" |
963fc8d0 AK |
2747 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
2748 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2749 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2750 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
2751 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
2752 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 2753 | "#" |
963fc8d0 | 2754 | [(set_attr "type" "cs") |
b5e0425c | 2755 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 2756 | |
9bb86f41 UW |
2757 | (define_split |
2758 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2759 | (match_operand:BLK 1 "memory_operand" "")) | |
2760 | (use (match_operand 2 "const_int_operand" "")) | |
2761 | (use (match_operand 3 "immediate_operand" "")) | |
2762 | (clobber (scratch))] | |
2763 | "reload_completed" | |
2764 | [(parallel | |
2765 | [(set (match_dup 0) (match_dup 1)) | |
2766 | (use (match_dup 2))])] | |
2767 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2768 | |
9bb86f41 UW |
2769 | (define_split |
2770 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2771 | (match_operand:BLK 1 "memory_operand" "")) | |
2772 | (use (match_operand 2 "register_operand" "")) | |
2773 | (use (match_operand 3 "memory_operand" "")) | |
2774 | (clobber (scratch))] | |
2775 | "reload_completed" | |
2776 | [(parallel | |
2777 | [(unspec [(match_dup 2) (match_dup 3) | |
2778 | (const_int 0)] UNSPEC_EXECUTE) | |
2779 | (set (match_dup 0) (match_dup 1)) | |
2780 | (use (const_int 1))])] | |
2781 | "") | |
2782 | ||
963fc8d0 AK |
2783 | (define_split |
2784 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2785 | (match_operand:BLK 1 "memory_operand" "")) | |
2786 | (use (match_operand 2 "register_operand" "")) | |
2787 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2788 | (clobber (scratch))] | |
2789 | "TARGET_Z10 && reload_completed" | |
2790 | [(parallel | |
2791 | [(unspec [(match_dup 2) (const_int 0) | |
2792 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2793 | (set (match_dup 0) (match_dup 1)) | |
2794 | (use (const_int 1))])] | |
2795 | "operands[3] = gen_label_rtx ();") | |
2796 | ||
9bb86f41 UW |
2797 | (define_split |
2798 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2799 | (match_operand:BLK 1 "memory_operand" "")) | |
2800 | (use (match_operand 2 "register_operand" "")) | |
2801 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2802 | (clobber (match_operand 3 "register_operand" ""))] | |
2803 | "reload_completed && TARGET_CPU_ZARCH" | |
2804 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2805 | (parallel | |
9381e3f1 | 2806 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
2807 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
2808 | (set (match_dup 0) (match_dup 1)) | |
2809 | (use (const_int 1))])] | |
2810 | "operands[4] = gen_label_rtx ();") | |
2811 | ||
a41c6c53 | 2812 | ; Move a block of arbitrary length. |
9db1d521 | 2813 | |
70128ad9 | 2814 | (define_expand "movmem_long" |
b9404c99 UW |
2815 | [(parallel |
2816 | [(clobber (match_dup 2)) | |
2817 | (clobber (match_dup 3)) | |
2818 | (set (match_operand:BLK 0 "memory_operand" "") | |
2819 | (match_operand:BLK 1 "memory_operand" "")) | |
2820 | (use (match_operand 2 "general_operand" "")) | |
2821 | (use (match_dup 3)) | |
ae156f85 | 2822 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2823 | "" |
2824 | { | |
9602b6a1 AK |
2825 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
2826 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
2827 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
2828 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
2829 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
2830 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
2831 | rtx len0 = gen_lowpart (Pmode, reg0); |
2832 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2833 | ||
c41c1387 | 2834 | emit_clobber (reg0); |
b9404c99 UW |
2835 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
2836 | emit_move_insn (len0, operands[2]); | |
2837 | ||
c41c1387 | 2838 | emit_clobber (reg1); |
b9404c99 UW |
2839 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2840 | emit_move_insn (len1, operands[2]); | |
2841 | ||
2842 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2843 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2844 | operands[2] = reg0; | |
2845 | operands[3] = reg1; | |
2846 | }) | |
2847 | ||
a1aed706 AS |
2848 | (define_insn "*movmem_long" |
2849 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2850 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2851 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2852 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2853 | (use (match_dup 2)) |
2854 | (use (match_dup 3)) | |
ae156f85 | 2855 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
2856 | "TARGET_64BIT || !TARGET_ZARCH" |
2857 | "mvcle\t%0,%1,0\;jo\t.-4" | |
2858 | [(set_attr "length" "8") | |
2859 | (set_attr "type" "vs")]) | |
2860 | ||
2861 | (define_insn "*movmem_long_31z" | |
2862 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2863 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2864 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
2865 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
2866 | (use (match_dup 2)) | |
2867 | (use (match_dup 3)) | |
2868 | (clobber (reg:CC CC_REGNUM))] | |
2869 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 2870 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2871 | [(set_attr "length" "8") |
2872 | (set_attr "type" "vs")]) | |
9db1d521 | 2873 | |
638e37c2 WG |
2874 | |
2875 | ; | |
2876 | ; Test data class. | |
2877 | ; | |
2878 | ||
0f67fa83 WG |
2879 | (define_expand "signbit<mode>2" |
2880 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2881 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2882 | (match_dup 2)] | |
0f67fa83 WG |
2883 | UNSPEC_TDC_INSN)) |
2884 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2885 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
2886 | "TARGET_HARD_FLOAT" |
2887 | { | |
2888 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
2889 | }) | |
2890 | ||
638e37c2 WG |
2891 | (define_expand "isinf<mode>2" |
2892 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
2893 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
2894 | (match_dup 2)] | |
638e37c2 WG |
2895 | UNSPEC_TDC_INSN)) |
2896 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2897 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 2898 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
2899 | { |
2900 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
2901 | }) | |
2902 | ||
5a3fe9b6 AK |
2903 | (define_insn_and_split "*cc_to_int" |
2904 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2905 | (unspec:SI [(match_operand 1 "register_operand" "0")] | |
2906 | UNSPEC_CC_TO_INT))] | |
2907 | "operands != NULL" | |
2908 | "#" | |
2909 | "reload_completed" | |
2910 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
2911 | ||
638e37c2 WG |
2912 | ; This insn is used to generate all variants of the Test Data Class |
2913 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
2914 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 2915 | ; specifying the required test(s). |
638e37c2 | 2916 | ; |
be5de7a1 | 2917 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
2918 | (define_insn "*TDC_insn_<mode>" |
2919 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 2920 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 2921 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 2922 | "TARGET_HARD_FLOAT" |
0387c142 | 2923 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 2924 | [(set_attr "op_type" "RXE") |
9381e3f1 | 2925 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 2926 | |
638e37c2 WG |
2927 | |
2928 | ||
9db1d521 | 2929 | ; |
57e84f18 | 2930 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2931 | ; |
2932 | ||
57e84f18 | 2933 | (define_expand "setmem<mode>" |
a41c6c53 | 2934 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2935 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2936 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2937 | (match_operand 3 "" "")] |
a41c6c53 | 2938 | "" |
6d057022 | 2939 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2940 | |
a41c6c53 | 2941 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2942 | ; The block length is taken as (operands[1] % 256) + 1. |
2943 | ||
70128ad9 | 2944 | (define_expand "clrmem_short" |
b9404c99 UW |
2945 | [(parallel |
2946 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2947 | (const_int 0)) | |
2948 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2949 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2950 | (clobber (match_dup 2)) |
ae156f85 | 2951 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2952 | "" |
2953 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2954 | |
70128ad9 | 2955 | (define_insn "*clrmem_short" |
963fc8d0 | 2956 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 2957 | (const_int 0)) |
963fc8d0 AK |
2958 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
2959 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 2960 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 2961 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 2962 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 2963 | "#" |
963fc8d0 | 2964 | [(set_attr "type" "cs") |
b5e0425c | 2965 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
2966 | |
2967 | (define_split | |
2968 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2969 | (const_int 0)) | |
2970 | (use (match_operand 1 "const_int_operand" "")) | |
2971 | (use (match_operand 2 "immediate_operand" "")) | |
2972 | (clobber (scratch)) | |
ae156f85 | 2973 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2974 | "reload_completed" |
2975 | [(parallel | |
2976 | [(set (match_dup 0) (const_int 0)) | |
2977 | (use (match_dup 1)) | |
ae156f85 | 2978 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2979 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2980 | |
9bb86f41 UW |
2981 | (define_split |
2982 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2983 | (const_int 0)) | |
2984 | (use (match_operand 1 "register_operand" "")) | |
2985 | (use (match_operand 2 "memory_operand" "")) | |
2986 | (clobber (scratch)) | |
ae156f85 | 2987 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2988 | "reload_completed" |
2989 | [(parallel | |
2990 | [(unspec [(match_dup 1) (match_dup 2) | |
2991 | (const_int 0)] UNSPEC_EXECUTE) | |
2992 | (set (match_dup 0) (const_int 0)) | |
2993 | (use (const_int 1)) | |
ae156f85 | 2994 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2995 | "") |
9db1d521 | 2996 | |
963fc8d0 AK |
2997 | (define_split |
2998 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2999 | (const_int 0)) | |
3000 | (use (match_operand 1 "register_operand" "")) | |
3001 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3002 | (clobber (scratch)) | |
3003 | (clobber (reg:CC CC_REGNUM))] | |
3004 | "TARGET_Z10 && reload_completed" | |
3005 | [(parallel | |
3006 | [(unspec [(match_dup 1) (const_int 0) | |
3007 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3008 | (set (match_dup 0) (const_int 0)) | |
3009 | (use (const_int 1)) | |
3010 | (clobber (reg:CC CC_REGNUM))])] | |
3011 | "operands[3] = gen_label_rtx ();") | |
3012 | ||
9bb86f41 UW |
3013 | (define_split |
3014 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3015 | (const_int 0)) | |
3016 | (use (match_operand 1 "register_operand" "")) | |
3017 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3018 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3019 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3020 | "reload_completed && TARGET_CPU_ZARCH" |
3021 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3022 | (parallel | |
9381e3f1 | 3023 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3024 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3025 | (set (match_dup 0) (const_int 0)) | |
3026 | (use (const_int 1)) | |
ae156f85 | 3027 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3028 | "operands[3] = gen_label_rtx ();") |
3029 | ||
9381e3f1 | 3030 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3031 | |
6d057022 | 3032 | (define_expand "setmem_long" |
b9404c99 UW |
3033 | [(parallel |
3034 | [(clobber (match_dup 1)) | |
3035 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 3036 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 3037 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 3038 | (use (match_dup 3)) |
ae156f85 | 3039 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3040 | "" |
a41c6c53 | 3041 | { |
9602b6a1 AK |
3042 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3043 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
3044 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
3045 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3046 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3047 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3048 | |
c41c1387 | 3049 | emit_clobber (reg0); |
b9404c99 UW |
3050 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3051 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3052 | |
b9404c99 | 3053 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3054 | |
b9404c99 UW |
3055 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3056 | operands[1] = reg0; | |
6d057022 | 3057 | operands[3] = reg1; |
b9404c99 | 3058 | }) |
a41c6c53 | 3059 | |
6d057022 | 3060 | (define_insn "*setmem_long" |
a1aed706 | 3061 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3062 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 3063 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 3064 | (use (match_dup 3)) |
a1aed706 | 3065 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3066 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3067 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3068 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3069 | [(set_attr "length" "8") |
3070 | (set_attr "type" "vs")]) | |
9db1d521 | 3071 | |
4989e88a AK |
3072 | (define_insn "*setmem_long_and" |
3073 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3074 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
3075 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
3076 | (match_operand 4 "const_int_operand" "n"))) | |
3077 | (use (match_dup 3)) | |
3078 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3079 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 AK |
3080 | "(TARGET_64BIT || !TARGET_ZARCH) && |
3081 | (INTVAL (operands[4]) & 255) == 255" | |
3082 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3083 | [(set_attr "length" "8") | |
3084 | (set_attr "type" "vs")]) | |
3085 | ||
3086 | (define_insn "*setmem_long_31z" | |
3087 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3088 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
3089 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) | |
3090 | (use (match_dup 3)) | |
3091 | (use (match_operand:TI 1 "register_operand" "d")) | |
3092 | (clobber (reg:CC CC_REGNUM))] | |
3093 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3094 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3095 | [(set_attr "length" "8") | |
3096 | (set_attr "type" "vs")]) | |
9602b6a1 | 3097 | |
9db1d521 | 3098 | ; |
358b8f01 | 3099 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3100 | ; |
3101 | ||
358b8f01 | 3102 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3103 | [(set (match_operand:SI 0 "register_operand" "") |
3104 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3105 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3106 | (use (match_operand:SI 3 "general_operand" "")) | |
3107 | (use (match_operand:SI 4 "" ""))] | |
3108 | "" | |
367d32f3 AK |
3109 | { |
3110 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3111 | operands[2], operands[3])) | |
3112 | DONE; | |
3113 | else | |
3114 | FAIL; | |
3115 | }) | |
9db1d521 | 3116 | |
a41c6c53 UW |
3117 | ; Compare a block that is up to 256 bytes in length. |
3118 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3119 | |
b9404c99 UW |
3120 | (define_expand "cmpmem_short" |
3121 | [(parallel | |
ae156f85 | 3122 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3123 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3124 | (match_operand:BLK 1 "memory_operand" ""))) |
3125 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3126 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3127 | (clobber (match_dup 3))])] |
3128 | "" | |
3129 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3130 | |
b9404c99 | 3131 | (define_insn "*cmpmem_short" |
ae156f85 | 3132 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3133 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3134 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3135 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3136 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3137 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3138 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3139 | "#" |
963fc8d0 | 3140 | [(set_attr "type" "cs") |
b5e0425c | 3141 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3142 | |
9bb86f41 | 3143 | (define_split |
ae156f85 | 3144 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3145 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3146 | (match_operand:BLK 1 "memory_operand" ""))) | |
3147 | (use (match_operand 2 "const_int_operand" "")) | |
3148 | (use (match_operand 3 "immediate_operand" "")) | |
3149 | (clobber (scratch))] | |
3150 | "reload_completed" | |
3151 | [(parallel | |
ae156f85 | 3152 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3153 | (use (match_dup 2))])] |
3154 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3155 | |
9bb86f41 | 3156 | (define_split |
ae156f85 | 3157 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3158 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3159 | (match_operand:BLK 1 "memory_operand" ""))) | |
3160 | (use (match_operand 2 "register_operand" "")) | |
3161 | (use (match_operand 3 "memory_operand" "")) | |
3162 | (clobber (scratch))] | |
3163 | "reload_completed" | |
3164 | [(parallel | |
3165 | [(unspec [(match_dup 2) (match_dup 3) | |
3166 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3167 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3168 | (use (const_int 1))])] |
3169 | "") | |
3170 | ||
963fc8d0 AK |
3171 | (define_split |
3172 | [(set (reg:CCU CC_REGNUM) | |
3173 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3174 | (match_operand:BLK 1 "memory_operand" ""))) | |
3175 | (use (match_operand 2 "register_operand" "")) | |
3176 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3177 | (clobber (scratch))] | |
3178 | "TARGET_Z10 && reload_completed" | |
3179 | [(parallel | |
3180 | [(unspec [(match_dup 2) (const_int 0) | |
3181 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3182 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3183 | (use (const_int 1))])] | |
3184 | "operands[4] = gen_label_rtx ();") | |
3185 | ||
9bb86f41 | 3186 | (define_split |
ae156f85 | 3187 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3188 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3189 | (match_operand:BLK 1 "memory_operand" ""))) | |
3190 | (use (match_operand 2 "register_operand" "")) | |
3191 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3192 | (clobber (match_operand 3 "register_operand" ""))] | |
3193 | "reload_completed && TARGET_CPU_ZARCH" | |
3194 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3195 | (parallel | |
9381e3f1 | 3196 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3197 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3198 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3199 | (use (const_int 1))])] |
3200 | "operands[4] = gen_label_rtx ();") | |
3201 | ||
a41c6c53 | 3202 | ; Compare a block of arbitrary length. |
9db1d521 | 3203 | |
b9404c99 UW |
3204 | (define_expand "cmpmem_long" |
3205 | [(parallel | |
3206 | [(clobber (match_dup 2)) | |
3207 | (clobber (match_dup 3)) | |
ae156f85 | 3208 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3209 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3210 | (match_operand:BLK 1 "memory_operand" ""))) |
3211 | (use (match_operand 2 "general_operand" "")) | |
3212 | (use (match_dup 3))])] | |
3213 | "" | |
3214 | { | |
9602b6a1 AK |
3215 | enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3216 | enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
3217 | rtx reg0 = gen_reg_rtx (dreg_mode); | |
3218 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3219 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3220 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3221 | rtx len0 = gen_lowpart (Pmode, reg0); |
3222 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3223 | ||
c41c1387 | 3224 | emit_clobber (reg0); |
b9404c99 UW |
3225 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3226 | emit_move_insn (len0, operands[2]); | |
3227 | ||
c41c1387 | 3228 | emit_clobber (reg1); |
b9404c99 UW |
3229 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3230 | emit_move_insn (len1, operands[2]); | |
3231 | ||
3232 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3233 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3234 | operands[2] = reg0; | |
3235 | operands[3] = reg1; | |
3236 | }) | |
3237 | ||
a1aed706 AS |
3238 | (define_insn "*cmpmem_long" |
3239 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3240 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3241 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3242 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3243 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3244 | (use (match_dup 2)) |
3245 | (use (match_dup 3))] | |
9602b6a1 | 3246 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3247 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3248 | [(set_attr "length" "8") |
3249 | (set_attr "type" "vs")]) | |
9db1d521 | 3250 | |
9602b6a1 AK |
3251 | (define_insn "*cmpmem_long_31z" |
3252 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3253 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3254 | (set (reg:CCU CC_REGNUM) | |
3255 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3256 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3257 | (use (match_dup 2)) | |
3258 | (use (match_dup 3))] | |
3259 | "!TARGET_64BIT && TARGET_ZARCH" | |
3260 | "clcle\t%0,%1,0\;jo\t.-4" | |
3261 | [(set_attr "op_type" "NN") | |
3262 | (set_attr "type" "vs") | |
3263 | (set_attr "length" "8")]) | |
3264 | ||
02887425 UW |
3265 | ; Convert CCUmode condition code to integer. |
3266 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3267 | |
02887425 | 3268 | (define_insn_and_split "cmpint" |
9db1d521 | 3269 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3270 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3271 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3272 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3273 | "" |
02887425 UW |
3274 | "#" |
3275 | "reload_completed" | |
3276 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3277 | (parallel | |
3278 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3279 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3280 | |
3281 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3282 | [(set (reg CC_REGNUM) |
02887425 | 3283 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3284 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3285 | (const_int 0))) |
3286 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3287 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3288 | "s390_match_ccmode (insn, CCSmode)" |
3289 | "#" | |
3290 | "&& reload_completed" | |
3291 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3292 | (parallel | |
3293 | [(set (match_dup 2) (match_dup 3)) | |
3294 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3295 | { |
02887425 UW |
3296 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3297 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3298 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3299 | }) | |
9db1d521 | 3300 | |
02887425 | 3301 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3302 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3303 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3304 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3305 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3306 | "TARGET_ZARCH" |
02887425 UW |
3307 | "#" |
3308 | "&& reload_completed" | |
3309 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3310 | (parallel | |
3311 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3312 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3313 | |
3314 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3315 | [(set (reg CC_REGNUM) |
9381e3f1 | 3316 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3317 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3318 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3319 | (const_int 32)) (const_int 32)) |
3320 | (const_int 0))) | |
3321 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3322 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3323 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3324 | "#" |
3325 | "&& reload_completed" | |
3326 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3327 | (parallel | |
3328 | [(set (match_dup 2) (match_dup 3)) | |
3329 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3330 | { |
02887425 UW |
3331 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3332 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3333 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3334 | }) | |
9db1d521 | 3335 | |
4023fb28 | 3336 | |
9db1d521 HP |
3337 | ;; |
3338 | ;;- Conversion instructions. | |
3339 | ;; | |
3340 | ||
6fa05db6 | 3341 | (define_insn "*sethighpartsi" |
d3632d41 | 3342 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3343 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3344 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3345 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3346 | "" |
d3632d41 | 3347 | "@ |
6fa05db6 AS |
3348 | icm\t%0,%2,%S1 |
3349 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3350 | [(set_attr "op_type" "RS,RSY") |
3351 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3352 | |
6fa05db6 | 3353 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3354 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3355 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3356 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3357 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3358 | "TARGET_ZARCH" |
6fa05db6 | 3359 | "icmh\t%0,%2,%S1" |
729e750f WG |
3360 | [(set_attr "op_type" "RSY") |
3361 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3362 | |
6fa05db6 | 3363 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3364 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3365 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3366 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3367 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3368 | "!TARGET_ZARCH" |
d3632d41 | 3369 | "@ |
6fa05db6 AS |
3370 | icm\t%0,%2,%S1 |
3371 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3372 | [(set_attr "op_type" "RS,RSY") |
3373 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3374 | ||
1a2e356e RH |
3375 | ; |
3376 | ; extv instruction patterns | |
3377 | ; | |
3378 | ||
3379 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3380 | ; after resolving some issues with it. | |
3381 | ||
3382 | (define_expand "extzv" | |
3383 | [(parallel | |
3384 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3385 | (zero_extract:DI | |
3386 | (match_operand:DI 1 "register_operand" "d") | |
3387 | (match_operand 2 "const_int_operand" "") ; size | |
3388 | (match_operand 3 "const_int_operand" ""))) ; start | |
3389 | (clobber (reg:CC CC_REGNUM))])] | |
3390 | "TARGET_Z10" | |
3391 | { | |
3392 | /* Starting with zEC12 there is risbgn not clobbering CC. */ | |
3393 | if (TARGET_ZEC12) | |
3394 | { | |
3395 | emit_move_insn (operands[0], | |
3396 | gen_rtx_ZERO_EXTRACT (DImode, | |
3397 | operands[1], | |
3398 | operands[2], | |
3399 | operands[3])); | |
3400 | DONE; | |
3401 | } | |
3402 | }) | |
3403 | ||
3404 | (define_insn "*extzv<mode>_zEC12" | |
3405 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3406 | (zero_extract:GPR | |
3407 | (match_operand:GPR 1 "register_operand" "d") | |
3408 | (match_operand 2 "const_int_operand" "") ; size | |
3409 | (match_operand 3 "const_int_operand" "")))] ; start] | |
3410 | "TARGET_ZEC12" | |
3411 | "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3412 | [(set_attr "op_type" "RIE")]) | |
3413 | ||
3414 | (define_insn "*extzv<mode>_z10" | |
3415 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3416 | (zero_extract:GPR | |
3417 | (match_operand:GPR 1 "register_operand" "d") | |
3418 | (match_operand 2 "const_int_operand" "") ; size | |
3419 | (match_operand 3 "const_int_operand" ""))) ; start | |
3420 | (clobber (reg:CC CC_REGNUM))] | |
3421 | "TARGET_Z10" | |
3422 | "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3423 | [(set_attr "op_type" "RIE") | |
3424 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3425 | |
1a2e356e | 3426 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 AS |
3427 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3428 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3429 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3430 | (const_int 0))) |
ae156f85 | 3431 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3432 | "!TARGET_Z10" |
cc7ab9b7 UW |
3433 | "#" |
3434 | "&& reload_completed" | |
4023fb28 | 3435 | [(parallel |
6fa05db6 | 3436 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3437 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3438 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3439 | { |
6fa05db6 AS |
3440 | int bitsize = INTVAL (operands[2]); |
3441 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3442 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3443 | ||
3444 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3445 | set_mem_size (operands[1], size); |
2542ef05 | 3446 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3447 | operands[3] = GEN_INT (mask); |
b628bd8e | 3448 | }) |
4023fb28 | 3449 | |
1a2e356e | 3450 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 AS |
3451 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3452 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3453 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3454 | (const_int 0))) |
ae156f85 | 3455 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3456 | "" |
cc7ab9b7 UW |
3457 | "#" |
3458 | "&& reload_completed" | |
4023fb28 | 3459 | [(parallel |
6fa05db6 | 3460 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3461 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3462 | (parallel |
3463 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3464 | (clobber (reg:CC CC_REGNUM))])] | |
3465 | { | |
3466 | int bitsize = INTVAL (operands[2]); | |
3467 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3468 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3469 | ||
3470 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3471 | set_mem_size (operands[1], size); |
2542ef05 | 3472 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3473 | operands[3] = GEN_INT (mask); |
3474 | }) | |
3475 | ||
3476 | ; | |
3477 | ; insv instruction patterns | |
3478 | ; | |
3479 | ||
3480 | (define_expand "insv" | |
3481 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3482 | (match_operand 1 "const_int_operand" "") | |
3483 | (match_operand 2 "const_int_operand" "")) | |
3484 | (match_operand 3 "general_operand" ""))] | |
3485 | "" | |
4023fb28 | 3486 | { |
6fa05db6 AS |
3487 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3488 | DONE; | |
3489 | FAIL; | |
b628bd8e | 3490 | }) |
4023fb28 | 3491 | |
2542ef05 RH |
3492 | |
3493 | ; The normal RTL expansion will never generate a zero_extract where | |
3494 | ; the location operand isn't word mode. However, we do this in the | |
3495 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
22ac2c2f AK |
3496 | (define_insn "*insv<mode>_zEC12" |
3497 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3498 | (match_operand 1 "const_int_operand" "I") ; size |
3499 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f AK |
3500 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
3501 | "TARGET_ZEC12 | |
2542ef05 RH |
3502 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3503 | "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
22ac2c2f AK |
3504 | [(set_attr "op_type" "RIE")]) |
3505 | ||
963fc8d0 AK |
3506 | (define_insn "*insv<mode>_z10" |
3507 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3508 | (match_operand 1 "const_int_operand" "I") ; size |
3509 | (match_operand 2 "const_int_operand" "I")) ; pos | |
963fc8d0 AK |
3510 | (match_operand:GPR 3 "nonimmediate_operand" "d")) |
3511 | (clobber (reg:CC CC_REGNUM))] | |
3512 | "TARGET_Z10 | |
2542ef05 RH |
3513 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3514 | "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
9381e3f1 WG |
3515 | [(set_attr "op_type" "RIE") |
3516 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3517 | |
22ac2c2f AK |
3518 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3519 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3520 | (define_insn "*insv<mode>_zEC12_noshift" | |
3521 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3522 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3523 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
22ac2c2f | 3524 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 RH |
3525 | (match_operand:GPR 4 "const_int_operand" ""))))] |
3526 | "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3527 | "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
22ac2c2f AK |
3528 | [(set_attr "op_type" "RIE")]) |
3529 | ||
963fc8d0 AK |
3530 | (define_insn "*insv<mode>_z10_noshift" |
3531 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3532 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3533 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
963fc8d0 | 3534 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 | 3535 | (match_operand:GPR 4 "const_int_operand" "")))) |
963fc8d0 | 3536 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 RH |
3537 | "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3538 | "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
9381e3f1 WG |
3539 | [(set_attr "op_type" "RIE") |
3540 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3541 | |
571e408a | 3542 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 3543 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
3544 | (IXOR:GPR |
3545 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3546 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3547 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 3548 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 3549 | "TARGET_Z10" |
571e408a RH |
3550 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
3551 | [(set_attr "op_type" "RIE")]) | |
3552 | ||
3553 | (define_insn "*r<noxa>sbg_di_rotl" | |
3554 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
3555 | (IXOR:DI | |
3556 | (and:DI | |
3557 | (rotate:DI | |
3558 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
3559 | (match_operand:DI 3 "const_int_operand" "")) | |
3560 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
3561 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
3562 | (clobber (reg:CC CC_REGNUM))] | |
3563 | "TARGET_Z10" | |
3564 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
3565 | [(set_attr "op_type" "RIE")]) | |
3566 | ||
3567 | (define_insn "*r<noxa>sbg_<mode>_srl" | |
3568 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3569 | (IXOR:GPR | |
3570 | (and:GPR | |
3571 | (lshiftrt:GPR | |
3572 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3573 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3574 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3575 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3576 | (clobber (reg:CC CC_REGNUM))] | |
3577 | "TARGET_Z10 | |
3578 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
3579 | INTVAL (operands[2]))" | |
3580 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
3581 | [(set_attr "op_type" "RIE")]) | |
3582 | ||
3583 | (define_insn "*r<noxa>sbg_<mode>_sll" | |
3584 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3585 | (IXOR:GPR | |
3586 | (and:GPR | |
3587 | (ashift:GPR | |
3588 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3589 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3590 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3591 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3592 | (clobber (reg:CC CC_REGNUM))] | |
3593 | "TARGET_Z10 | |
3594 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
3595 | INTVAL (operands[2]))" | |
3596 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
3597 | [(set_attr "op_type" "RIE")]) |
3598 | ||
5bb33936 RH |
3599 | ;; These two are generated by combine for s.bf &= val. |
3600 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
3601 | ;; shifts and ands, which results in some truly awful patterns | |
3602 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
3603 | ;; Instead of | |
3604 | ;; | |
3605 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3606 | ;; (const_int 24 [0x18]) | |
3607 | ;; (const_int 0 [0])) | |
3608 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3609 | ;; (const_int 40 [0x28])) 4) | |
3610 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
3611 | ;; | |
3612 | ;; we should instead generate | |
3613 | ;; | |
3614 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3615 | ;; (const_int 24 [0x18]) | |
3616 | ;; (const_int 0 [0])) | |
3617 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3618 | ;; (const_int 40 [0x28])) | |
3619 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
3620 | ;; | |
3621 | ;; by noticing that we can push down the outer paradoxical subreg | |
3622 | ;; into the operation. | |
3623 | ||
3624 | (define_insn "*insv_rnsbg_noshift" | |
3625 | [(set (zero_extract:DI | |
3626 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3627 | (match_operand 1 "const_int_operand" "") | |
3628 | (match_operand 2 "const_int_operand" "")) | |
3629 | (and:DI | |
3630 | (match_dup 0) | |
3631 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
3632 | (clobber (reg:CC CC_REGNUM))] | |
3633 | "TARGET_Z10 | |
3634 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" | |
3635 | "rnsbg\t%0,%3,%2,63,0" | |
3636 | [(set_attr "op_type" "RIE")]) | |
3637 | ||
3638 | (define_insn "*insv_rnsbg_srl" | |
3639 | [(set (zero_extract:DI | |
3640 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3641 | (match_operand 1 "const_int_operand" "") | |
3642 | (match_operand 2 "const_int_operand" "")) | |
3643 | (and:DI | |
3644 | (lshiftrt:DI | |
3645 | (match_dup 0) | |
3646 | (match_operand 3 "const_int_operand" "")) | |
3647 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
3648 | (clobber (reg:CC CC_REGNUM))] | |
3649 | "TARGET_Z10 | |
3650 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" | |
3651 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
3652 | [(set_attr "op_type" "RIE")]) | |
3653 | ||
6fa05db6 | 3654 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 3655 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
3656 | (match_operand 1 "const_int_operand" "n,n") |
3657 | (const_int 0)) | |
9602b6a1 | 3658 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
3659 | "INTVAL (operands[1]) > 0 |
3660 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3661 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3662 | { | |
3663 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3664 | ||
3665 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 3666 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
3667 | : "stcmy\t%2,%1,%S0"; |
3668 | } | |
9381e3f1 WG |
3669 | [(set_attr "op_type" "RS,RSY") |
3670 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
3671 | |
3672 | (define_insn "*insvdi_mem_reghigh" | |
3673 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3674 | (match_operand 1 "const_int_operand" "n") | |
3675 | (const_int 0)) | |
3676 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3677 | (const_int 32)))] | |
9602b6a1 | 3678 | "TARGET_ZARCH |
6fa05db6 AS |
3679 | && INTVAL (operands[1]) > 0 |
3680 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3681 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3682 | { | |
3683 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3684 | ||
3685 | operands[1] = GEN_INT ((1ul << size) - 1); | |
3686 | return "stcmh\t%2,%1,%S0"; | |
3687 | } | |
9381e3f1 WG |
3688 | [(set_attr "op_type" "RSY") |
3689 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 3690 | |
9602b6a1 AK |
3691 | (define_insn "*insvdi_reg_imm" |
3692 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3693 | (const_int 16) | |
3694 | (match_operand 1 "const_int_operand" "n")) | |
3695 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
3696 | "TARGET_ZARCH |
3697 | && INTVAL (operands[1]) >= 0 | |
3698 | && INTVAL (operands[1]) < BITS_PER_WORD | |
3699 | && INTVAL (operands[1]) % 16 == 0" | |
3700 | { | |
3701 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
3702 | { | |
3703 | case 64: return "iihh\t%0,%x2"; break; | |
3704 | case 48: return "iihl\t%0,%x2"; break; | |
3705 | case 32: return "iilh\t%0,%x2"; break; | |
3706 | case 16: return "iill\t%0,%x2"; break; | |
3707 | default: gcc_unreachable(); | |
3708 | } | |
3709 | } | |
9381e3f1 WG |
3710 | [(set_attr "op_type" "RI") |
3711 | (set_attr "z10prop" "z10_super_E1")]) | |
3712 | ||
9fec758d WG |
3713 | ; Update the left-most 32 bit of a DI. |
3714 | (define_insn "*insv_h_di_reg_extimm" | |
3715 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3716 | (const_int 32) | |
3717 | (const_int 0)) | |
3718 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3719 | "TARGET_EXTIMM" | |
3720 | "iihf\t%0,%o1" | |
3721 | [(set_attr "op_type" "RIL") | |
3722 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 3723 | |
d378b983 RH |
3724 | ; Update the right-most 32 bit of a DI. |
3725 | (define_insn "*insv_l_di_reg_extimm" | |
3726 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3727 | (const_int 32) | |
3728 | (const_int 32)) | |
3729 | (match_operand:DI 1 "const_int_operand" "n"))] | |
3730 | "TARGET_EXTIMM" | |
3731 | "iilf\t%0,%o1" | |
9381e3f1 | 3732 | [(set_attr "op_type" "RIL") |
9fec758d | 3733 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 3734 | |
9db1d521 HP |
3735 | ; |
3736 | ; extendsidi2 instruction pattern(s). | |
3737 | ; | |
3738 | ||
4023fb28 UW |
3739 | (define_expand "extendsidi2" |
3740 | [(set (match_operand:DI 0 "register_operand" "") | |
3741 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3742 | "" | |
4023fb28 | 3743 | { |
9602b6a1 | 3744 | if (!TARGET_ZARCH) |
4023fb28 | 3745 | { |
c41c1387 | 3746 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3747 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
3748 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
3749 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
3750 | DONE; |
3751 | } | |
ec24698e | 3752 | }) |
4023fb28 UW |
3753 | |
3754 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
3755 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3756 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3757 | "TARGET_ZARCH" |
9db1d521 | 3758 | "@ |
d40c829f | 3759 | lgfr\t%0,%1 |
963fc8d0 AK |
3760 | lgf\t%0,%1 |
3761 | lgfrl\t%0,%1" | |
3762 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3763 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3764 | (set_attr "cpu_facility" "*,*,z10") |
3765 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3766 | |
9db1d521 | 3767 | ; |
56477c21 | 3768 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3769 | ; |
3770 | ||
56477c21 AS |
3771 | (define_expand "extend<HQI:mode><DSI:mode>2" |
3772 | [(set (match_operand:DSI 0 "register_operand" "") | |
3773 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 3774 | "" |
4023fb28 | 3775 | { |
9602b6a1 | 3776 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
3777 | { |
3778 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 3779 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
3780 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
3781 | DONE; | |
3782 | } | |
ec24698e | 3783 | else if (!TARGET_EXTIMM) |
4023fb28 | 3784 | { |
2542ef05 | 3785 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
3786 | |
3787 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
3788 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
3789 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
3790 | DONE; |
3791 | } | |
ec24698e UW |
3792 | }) |
3793 | ||
56477c21 AS |
3794 | ; |
3795 | ; extendhidi2 instruction pattern(s). | |
3796 | ; | |
3797 | ||
ec24698e | 3798 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
3799 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3800 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 3801 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
3802 | "@ |
3803 | lghr\t%0,%1 | |
963fc8d0 AK |
3804 | lgh\t%0,%1 |
3805 | lghrl\t%0,%1" | |
3806 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3807 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3808 | (set_attr "cpu_facility" "extimm,extimm,z10") |
3809 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
3810 | |
3811 | (define_insn "*extendhidi2" | |
9db1d521 | 3812 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 3813 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 3814 | "TARGET_ZARCH" |
d40c829f | 3815 | "lgh\t%0,%1" |
9381e3f1 WG |
3816 | [(set_attr "op_type" "RXY") |
3817 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 3818 | |
9db1d521 | 3819 | ; |
56477c21 | 3820 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
3821 | ; |
3822 | ||
ec24698e | 3823 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
3824 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3825 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
3826 | "TARGET_EXTIMM" |
3827 | "@ | |
3828 | lhr\t%0,%1 | |
3829 | lh\t%0,%1 | |
963fc8d0 AK |
3830 | lhy\t%0,%1 |
3831 | lhrl\t%0,%1" | |
3832 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
3833 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
3834 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
3835 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3836 | |
4023fb28 | 3837 | (define_insn "*extendhisi2" |
d3632d41 UW |
3838 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3839 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 3840 | "!TARGET_EXTIMM" |
d3632d41 | 3841 | "@ |
d40c829f UW |
3842 | lh\t%0,%1 |
3843 | lhy\t%0,%1" | |
9381e3f1 WG |
3844 | [(set_attr "op_type" "RX,RXY") |
3845 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 3846 | |
56477c21 AS |
3847 | ; |
3848 | ; extendqi(si|di)2 instruction pattern(s). | |
3849 | ; | |
3850 | ||
43a09b63 | 3851 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
3852 | (define_insn "*extendqi<mode>2_extimm" |
3853 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 3854 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
3855 | "TARGET_EXTIMM" |
3856 | "@ | |
56477c21 AS |
3857 | l<g>br\t%0,%1 |
3858 | l<g>b\t%0,%1" | |
9381e3f1 WG |
3859 | [(set_attr "op_type" "RRE,RXY") |
3860 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 3861 | |
43a09b63 | 3862 | ; lb, lgb |
56477c21 AS |
3863 | (define_insn "*extendqi<mode>2" |
3864 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 3865 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
3866 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
3867 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
3868 | [(set_attr "op_type" "RXY") |
3869 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 3870 | |
56477c21 AS |
3871 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
3872 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3873 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 3874 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 3875 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
3876 | "#" |
3877 | "&& reload_completed" | |
4023fb28 | 3878 | [(parallel |
56477c21 | 3879 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 3880 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 3881 | (parallel |
56477c21 | 3882 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 3883 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
3884 | { |
3885 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3886 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 3887 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 3888 | }) |
9db1d521 | 3889 | |
9db1d521 HP |
3890 | ; |
3891 | ; zero_extendsidi2 instruction pattern(s). | |
3892 | ; | |
3893 | ||
4023fb28 UW |
3894 | (define_expand "zero_extendsidi2" |
3895 | [(set (match_operand:DI 0 "register_operand" "") | |
3896 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
3897 | "" | |
4023fb28 | 3898 | { |
9602b6a1 | 3899 | if (!TARGET_ZARCH) |
4023fb28 | 3900 | { |
c41c1387 | 3901 | emit_clobber (operands[0]); |
9f37ccb1 UW |
3902 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
3903 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
3904 | DONE; |
3905 | } | |
ec24698e | 3906 | }) |
4023fb28 UW |
3907 | |
3908 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
3909 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3910 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 3911 | "TARGET_ZARCH" |
9db1d521 | 3912 | "@ |
d40c829f | 3913 | llgfr\t%0,%1 |
963fc8d0 AK |
3914 | llgf\t%0,%1 |
3915 | llgfrl\t%0,%1" | |
3916 | [(set_attr "op_type" "RRE,RXY,RIL") | |
3917 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
3918 | (set_attr "cpu_facility" "*,*,z10") |
3919 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 3920 | |
288e517f AK |
3921 | ; |
3922 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
3923 | ; | |
3924 | ||
d6083c7d UW |
3925 | (define_insn "*llgt_sidi" |
3926 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3927 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3928 | (const_int 2147483647)))] |
9602b6a1 | 3929 | "TARGET_ZARCH" |
d6083c7d | 3930 | "llgt\t%0,%1" |
9381e3f1 WG |
3931 | [(set_attr "op_type" "RXE") |
3932 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
3933 | |
3934 | (define_insn_and_split "*llgt_sidi_split" | |
3935 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 3936 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 3937 | (const_int 2147483647))) |
ae156f85 | 3938 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3939 | "TARGET_ZARCH" |
d6083c7d UW |
3940 | "#" |
3941 | "&& reload_completed" | |
3942 | [(set (match_dup 0) | |
3943 | (and:DI (subreg:DI (match_dup 1) 0) | |
3944 | (const_int 2147483647)))] | |
3945 | "") | |
3946 | ||
288e517f AK |
3947 | (define_insn "*llgt_sisi" |
3948 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 3949 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 3950 | (const_int 2147483647)))] |
c4d50129 | 3951 | "TARGET_ZARCH" |
288e517f AK |
3952 | "@ |
3953 | llgtr\t%0,%1 | |
3954 | llgt\t%0,%1" | |
9381e3f1 WG |
3955 | [(set_attr "op_type" "RRE,RXE") |
3956 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3957 | |
288e517f AK |
3958 | (define_insn "*llgt_didi" |
3959 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3960 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
3961 | (const_int 2147483647)))] | |
9602b6a1 | 3962 | "TARGET_ZARCH" |
288e517f AK |
3963 | "@ |
3964 | llgtr\t%0,%1 | |
3965 | llgt\t%0,%N1" | |
9381e3f1 WG |
3966 | [(set_attr "op_type" "RRE,RXE") |
3967 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 3968 | |
f19a9af7 | 3969 | (define_split |
9602b6a1 AK |
3970 | [(set (match_operand:DSI 0 "register_operand" "") |
3971 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 3972 | (const_int 2147483647))) |
ae156f85 | 3973 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 3974 | "TARGET_ZARCH && reload_completed" |
288e517f | 3975 | [(set (match_dup 0) |
9602b6a1 | 3976 | (and:DSI (match_dup 1) |
f6ee577c | 3977 | (const_int 2147483647)))] |
288e517f AK |
3978 | "") |
3979 | ||
9db1d521 | 3980 | ; |
56477c21 | 3981 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
3982 | ; |
3983 | ||
56477c21 AS |
3984 | (define_expand "zero_extend<mode>di2" |
3985 | [(set (match_operand:DI 0 "register_operand" "") | |
3986 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
3987 | "" | |
3988 | { | |
9602b6a1 | 3989 | if (!TARGET_ZARCH) |
56477c21 AS |
3990 | { |
3991 | rtx tmp = gen_reg_rtx (SImode); | |
3992 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
3993 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
3994 | DONE; | |
3995 | } | |
3996 | else if (!TARGET_EXTIMM) | |
3997 | { | |
2542ef05 | 3998 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
3999 | operands[1] = gen_lowpart (DImode, operands[1]); |
4000 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4001 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4002 | DONE; | |
4003 | } | |
4004 | }) | |
4005 | ||
f6ee577c | 4006 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4007 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4008 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4009 | "" |
4023fb28 | 4010 | { |
ec24698e UW |
4011 | if (!TARGET_EXTIMM) |
4012 | { | |
4013 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4014 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4015 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4016 | DONE; |
56477c21 | 4017 | } |
ec24698e UW |
4018 | }) |
4019 | ||
963fc8d0 AK |
4020 | ; llhrl, llghrl |
4021 | (define_insn "*zero_extendhi<mode>2_z10" | |
4022 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4023 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
4024 | "TARGET_Z10" | |
4025 | "@ | |
4026 | ll<g>hr\t%0,%1 | |
4027 | ll<g>h\t%0,%1 | |
4028 | ll<g>hrl\t%0,%1" | |
4029 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4030 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4031 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4032 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4033 | |
43a09b63 | 4034 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4035 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4036 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4037 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4038 | "TARGET_EXTIMM" |
4039 | "@ | |
56477c21 AS |
4040 | ll<g><hc>r\t%0,%1 |
4041 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4042 | [(set_attr "op_type" "RRE,RXY") |
4043 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4044 | |
43a09b63 | 4045 | ; llgh, llgc |
56477c21 AS |
4046 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4047 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4048 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 4049 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4050 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4051 | [(set_attr "op_type" "RXY") |
4052 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4053 | |
4054 | (define_insn_and_split "*zero_extendhisi2_31" | |
4055 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 4056 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 4057 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4058 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4059 | "#" |
4060 | "&& reload_completed" | |
4061 | [(set (match_dup 0) (const_int 0)) | |
4062 | (parallel | |
4063 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4064 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4065 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4066 | |
cc7ab9b7 UW |
4067 | (define_insn_and_split "*zero_extendqisi2_31" |
4068 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 4069 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4070 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4071 | "#" |
4072 | "&& reload_completed" | |
4073 | [(set (match_dup 0) (const_int 0)) | |
4074 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4075 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4076 | |
9db1d521 HP |
4077 | ; |
4078 | ; zero_extendqihi2 instruction pattern(s). | |
4079 | ; | |
4080 | ||
9db1d521 HP |
4081 | (define_expand "zero_extendqihi2" |
4082 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4083 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4084 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4085 | { |
4023fb28 UW |
4086 | operands[1] = gen_lowpart (HImode, operands[1]); |
4087 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4088 | DONE; | |
ec24698e | 4089 | }) |
9db1d521 | 4090 | |
4023fb28 | 4091 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4092 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 4093 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 4094 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4095 | "llgc\t%0,%1" |
9381e3f1 WG |
4096 | [(set_attr "op_type" "RXY") |
4097 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4098 | |
cc7ab9b7 UW |
4099 | (define_insn_and_split "*zero_extendqihi2_31" |
4100 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 4101 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4102 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4103 | "#" |
4104 | "&& reload_completed" | |
4105 | [(set (match_dup 0) (const_int 0)) | |
4106 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4107 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4108 | |
609e7e80 AK |
4109 | ; |
4110 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
4111 | ; | |
4112 | ||
4113 | (define_expand "fixuns_truncdddi2" | |
4114 | [(parallel | |
4115 | [(set (match_operand:DI 0 "register_operand" "") | |
4116 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
65b1d8ea AK |
4117 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) |
4118 | (clobber (reg:CC CC_REGNUM))])] | |
9381e3f1 | 4119 | |
fb068247 | 4120 | "TARGET_HARD_DFP" |
609e7e80 | 4121 | { |
65b1d8ea AK |
4122 | if (!TARGET_Z196) |
4123 | { | |
4124 | rtx label1 = gen_label_rtx (); | |
4125 | rtx label2 = gen_label_rtx (); | |
4126 | rtx temp = gen_reg_rtx (TDmode); | |
4127 | REAL_VALUE_TYPE cmp, sub; | |
4128 | ||
4129 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4130 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4131 | ||
4132 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4133 | solution is doing the check and the subtraction in TD mode and using a | |
4134 | TD -> DI convert afterwards. */ | |
4135 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4136 | temp = force_reg (TDmode, temp); | |
4137 | emit_cmp_and_jump_insns (temp, | |
4138 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
4139 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4140 | emit_insn (gen_subtd3 (temp, temp, | |
4141 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
4142 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
4143 | emit_jump (label2); | |
4144 | ||
4145 | emit_label (label1); | |
4146 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4147 | emit_label (label2); | |
4148 | DONE; | |
4149 | } | |
609e7e80 AK |
4150 | }) |
4151 | ||
4152 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
4153 | [(parallel |
4154 | [(set (match_operand:DI 0 "register_operand" "") | |
4155 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4156 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) | |
4157 | (clobber (reg:CC CC_REGNUM))])] | |
4158 | ||
fb068247 | 4159 | "TARGET_HARD_DFP" |
609e7e80 | 4160 | { |
65b1d8ea AK |
4161 | if (!TARGET_Z196) |
4162 | { | |
4163 | rtx label1 = gen_label_rtx (); | |
4164 | rtx label2 = gen_label_rtx (); | |
4165 | rtx temp = gen_reg_rtx (TDmode); | |
4166 | REAL_VALUE_TYPE cmp, sub; | |
4167 | ||
4168 | operands[1] = force_reg (TDmode, operands[1]); | |
4169 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4170 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4171 | ||
4172 | emit_cmp_and_jump_insns (operands[1], | |
4173 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), | |
4174 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4175 | emit_insn (gen_subtd3 (temp, operands[1], | |
4176 | CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); | |
4177 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); | |
4178 | emit_jump (label2); | |
4179 | ||
4180 | emit_label (label1); | |
4181 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4182 | emit_label (label2); | |
4183 | DONE; | |
4184 | } | |
609e7e80 | 4185 | }) |
cc7ab9b7 | 4186 | |
9db1d521 | 4187 | ; |
65b1d8ea | 4188 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 4189 | ; instruction pattern(s). |
9db1d521 HP |
4190 | ; |
4191 | ||
7b6baae1 | 4192 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
4193 | [(parallel |
4194 | [(set (match_operand:GPR 0 "register_operand" "") | |
4195 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4196 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4197 | (clobber (reg:CC CC_REGNUM))])] | |
142cd70f | 4198 | "TARGET_HARD_FLOAT" |
9db1d521 | 4199 | { |
65b1d8ea AK |
4200 | if (!TARGET_Z196) |
4201 | { | |
4202 | rtx label1 = gen_label_rtx (); | |
4203 | rtx label2 = gen_label_rtx (); | |
4204 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4205 | REAL_VALUE_TYPE cmp, sub; | |
4206 | ||
4207 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
2542ef05 RH |
4208 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); |
4209 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
65b1d8ea AK |
4210 | |
4211 | emit_cmp_and_jump_insns (operands[1], | |
4212 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), | |
4213 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4214 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4215 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); | |
4216 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4217 | GEN_INT (7))); | |
4218 | emit_jump (label2); | |
4219 | ||
4220 | emit_label (label1); | |
4221 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4222 | operands[1], GEN_INT (5))); | |
4223 | emit_label (label2); | |
4224 | DONE; | |
4225 | } | |
10bbf137 | 4226 | }) |
9db1d521 | 4227 | |
65b1d8ea AK |
4228 | ; fixuns_trunc(td|dd)si2 expander |
4229 | (define_expand "fixuns_trunc<mode>si2" | |
4230 | [(parallel | |
4231 | [(set (match_operand:SI 0 "register_operand" "") | |
4232 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
4233 | (unspec:SI [(const_int 5)] UNSPEC_ROUND) | |
4234 | (clobber (reg:CC CC_REGNUM))])] | |
8540e6e8 | 4235 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4236 | "") |
4237 | ||
4238 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4239 | ||
4240 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr | |
4241 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4242 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
4243 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
4244 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4245 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4246 | (clobber (reg:CC CC_REGNUM))] | |
4247 | "TARGET_Z196" | |
4248 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" | |
4249 | [(set_attr "op_type" "RRF") | |
4250 | (set_attr "type" "ftoi")]) | |
4251 | ||
b60cb710 AK |
4252 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4253 | [(set (match_operand:GPR 0 "register_operand" "") | |
4254 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4255 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4256 | { |
b60cb710 AK |
4257 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
4258 | GEN_INT (5))); | |
9db1d521 | 4259 | DONE; |
10bbf137 | 4260 | }) |
9db1d521 | 4261 | |
43a09b63 | 4262 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
142cd70f | 4263 | (define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
2f8f8434 | 4264 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7b6baae1 | 4265 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) |
2f8f8434 | 4266 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) |
ae156f85 | 4267 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4268 | "TARGET_HARD_FLOAT" |
7b6baae1 | 4269 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4270 | [(set_attr "op_type" "RRE") |
077dab3b | 4271 | (set_attr "type" "ftoi")]) |
9db1d521 | 4272 | |
609e7e80 AK |
4273 | |
4274 | ; | |
4275 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4276 | ; | |
4277 | ||
99cd7dd0 AK |
4278 | (define_expand "fix_trunc<mode>di2" |
4279 | [(set (match_operand:DI 0 "register_operand" "") | |
4280 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4281 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4282 | { |
4283 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4284 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
4285 | GEN_INT (9))); | |
4286 | DONE; | |
4287 | }) | |
4288 | ||
609e7e80 | 4289 | ; cgxtr, cgdtr |
99cd7dd0 | 4290 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4291 | [(set (match_operand:DI 0 "register_operand" "=d") |
4292 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4293 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4294 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4295 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4296 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4297 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4298 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4299 | |
4300 | ||
f61a2c7d AK |
4301 | ; |
4302 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4303 | ; | |
4304 | ||
4305 | (define_expand "fix_trunctf<mode>2" | |
4306 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4307 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
4308 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4309 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 4310 | "TARGET_HARD_FLOAT" |
142cd70f | 4311 | "") |
9db1d521 | 4312 | |
9db1d521 | 4313 | |
9db1d521 | 4314 | ; |
142cd70f | 4315 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4316 | ; |
4317 | ||
609e7e80 | 4318 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4319 | (define_insn "floatdi<mode>2" |
609e7e80 AK |
4320 | [(set (match_operand:FP 0 "register_operand" "=f") |
4321 | (float:FP (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 4322 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
609e7e80 | 4323 | "c<xde>g<bt>r\t%0,%1" |
9db1d521 | 4324 | [(set_attr "op_type" "RRE") |
9381e3f1 | 4325 | (set_attr "type" "itof<mode>" )]) |
9db1d521 | 4326 | |
43a09b63 | 4327 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4328 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4329 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4330 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4331 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4332 | "c<xde>fbr\t%0,%1" |
4333 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4334 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4335 | |
65b1d8ea AK |
4336 | ; cxftr, cdftr |
4337 | (define_insn "floatsi<mode>2" | |
4338 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4339 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4340 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4341 | "c<xde>ftr\t%0,0,%1,0" | |
4342 | [(set_attr "op_type" "RRE") | |
4343 | (set_attr "type" "itof<mode>" )]) | |
4344 | ||
4345 | ; | |
4346 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4347 | ; | |
4348 | ||
4349 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr | |
4350 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
4351 | (define_insn "floatuns<GPR:mode><FP:mode>2" | |
4352 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4353 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4354 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4355 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" | |
4356 | [(set_attr "op_type" "RRE") | |
4357 | (set_attr "type" "itof<FP:mode>" )]) | |
f61a2c7d | 4358 | |
9db1d521 HP |
4359 | ; |
4360 | ; truncdfsf2 instruction pattern(s). | |
4361 | ; | |
4362 | ||
142cd70f | 4363 | (define_insn "truncdfsf2" |
9db1d521 | 4364 | [(set (match_operand:SF 0 "register_operand" "=f") |
a036c6f7 | 4365 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
142cd70f | 4366 | "TARGET_HARD_FLOAT" |
d40c829f | 4367 | "ledbr\t%0,%1" |
f61a2c7d AK |
4368 | [(set_attr "op_type" "RRE") |
4369 | (set_attr "type" "ftruncdf")]) | |
9db1d521 | 4370 | |
f61a2c7d | 4371 | ; |
142cd70f | 4372 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4373 | ; |
4374 | ||
142cd70f AK |
4375 | ; ldxbr, lexbr |
4376 | (define_insn "trunctf<mode>2" | |
4377 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4378 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4379 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4380 | "TARGET_HARD_FLOAT" |
4381 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4382 | [(set_attr "length" "6") |
9381e3f1 | 4383 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4384 | |
609e7e80 AK |
4385 | ; |
4386 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4387 | ; | |
4388 | ||
4389 | (define_insn "trunctddd2" | |
4390 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
4391 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4392 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4393 | "TARGET_HARD_DFP" |
bf259a77 AK |
4394 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4395 | [(set_attr "length" "6") | |
9381e3f1 | 4396 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4397 | |
4398 | (define_insn "truncddsd2" | |
4399 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4400 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4401 | "TARGET_HARD_DFP" |
609e7e80 AK |
4402 | "ledtr\t%0,0,%1,0" |
4403 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4404 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4405 | |
9db1d521 | 4406 | ; |
142cd70f | 4407 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4408 | ; |
4409 | ||
142cd70f AK |
4410 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
4411 | (define_insn "extend<DSF:mode><BFP:mode>2" | |
4412 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
4413 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] | |
4414 | "TARGET_HARD_FLOAT | |
4415 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)" | |
f61a2c7d | 4416 | "@ |
142cd70f AK |
4417 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4418 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
f61a2c7d | 4419 | [(set_attr "op_type" "RRE,RXE") |
142cd70f | 4420 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) |
f61a2c7d | 4421 | |
609e7e80 AK |
4422 | ; |
4423 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4424 | ; | |
4425 | ||
4426 | (define_insn "extendddtd2" | |
4427 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4428 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4429 | "TARGET_HARD_DFP" |
609e7e80 AK |
4430 | "lxdtr\t%0,%1,0" |
4431 | [(set_attr "op_type" "RRF") | |
4432 | (set_attr "type" "fsimptf")]) | |
4433 | ||
4434 | (define_insn "extendsddd2" | |
4435 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4436 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4437 | "TARGET_HARD_DFP" |
609e7e80 AK |
4438 | "ldetr\t%0,%1,0" |
4439 | [(set_attr "op_type" "RRF") | |
4440 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4441 | |
d12a76f3 AK |
4442 | ; Binary Floating Point - load fp integer |
4443 | ||
4444 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
4445 | ; For all of them the inexact exceptions are suppressed. | |
4446 | ||
4447 | ; fiebra, fidbra, fixbra | |
4448 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
4449 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4450 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4451 | FPINT))] | |
4452 | "TARGET_Z196" | |
4453 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4454 | [(set_attr "op_type" "RRF") | |
4455 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4456 | ||
4457 | ; rint is supposed to raise an inexact exception so we can use the | |
4458 | ; older instructions. | |
4459 | ||
4460 | ; fiebr, fidbr, fixbr | |
4461 | (define_insn "rint<BFP:mode>2" | |
4462 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4463 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4464 | UNSPEC_FPINT_RINT))] | |
4465 | "" | |
4466 | "fi<BFP:xde>br\t%0,0,%1" | |
4467 | [(set_attr "op_type" "RRF") | |
4468 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4469 | ||
4470 | ||
4471 | ; Decimal Floating Point - load fp integer | |
4472 | ||
4473 | ; fidtr, fixtr | |
4474 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
4475 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4476 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4477 | FPINT))] | |
4478 | "TARGET_HARD_DFP" | |
4479 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4480 | [(set_attr "op_type" "RRF") | |
4481 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4482 | ||
4483 | ; fidtr, fixtr | |
4484 | (define_insn "rint<DFP:mode>2" | |
4485 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4486 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4487 | UNSPEC_FPINT_RINT))] | |
4488 | "TARGET_HARD_DFP" | |
4489 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
4490 | [(set_attr "op_type" "RRF") | |
4491 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4492 | ||
4493 | ; | |
35dd9a0e AK |
4494 | ; Binary <-> Decimal floating point trunc patterns |
4495 | ; | |
4496 | ||
4497 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4498 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4499 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e AK |
4500 | (use (reg:SI GPR0_REGNUM)) |
4501 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4502 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4503 | "pfpo") |
4504 | ||
4505 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4506 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 4507 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e AK |
4508 | (use (reg:SI GPR0_REGNUM)) |
4509 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4510 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4511 | "pfpo") |
4512 | ||
4513 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 4514 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
4515 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
4516 | (parallel | |
4517 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4518 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e AK |
4519 | (use (reg:SI GPR0_REGNUM)) |
4520 | (clobber (reg:CC CC_REGNUM))]) | |
4521 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4522 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4523 | "TARGET_HARD_DFP |
35dd9a0e AK |
4524 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4525 | { | |
4526 | HOST_WIDE_INT flags; | |
4527 | ||
4528 | flags = (PFPO_CONVERT | | |
4529 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4530 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4531 | ||
4532 | operands[2] = GEN_INT (flags); | |
4533 | }) | |
4534 | ||
4535 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 4536 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
4537 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
4538 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4539 | (parallel | |
2cf4c39e | 4540 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e AK |
4541 | (use (reg:SI GPR0_REGNUM)) |
4542 | (clobber (reg:CC CC_REGNUM))]) | |
4543 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4544 | "TARGET_HARD_DFP |
35dd9a0e AK |
4545 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
4546 | { | |
4547 | HOST_WIDE_INT flags; | |
4548 | ||
4549 | flags = (PFPO_CONVERT | | |
4550 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4551 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4552 | ||
4553 | operands[2] = GEN_INT (flags); | |
4554 | }) | |
4555 | ||
4556 | ; | |
4557 | ; Binary <-> Decimal floating point extend patterns | |
4558 | ; | |
4559 | ||
4560 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 4561 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e AK |
4562 | (use (reg:SI GPR0_REGNUM)) |
4563 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4564 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4565 | "pfpo") |
4566 | ||
4567 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 4568 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e AK |
4569 | (use (reg:SI GPR0_REGNUM)) |
4570 | (clobber (reg:CC CC_REGNUM))] | |
fb068247 | 4571 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4572 | "pfpo") |
4573 | ||
4574 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 4575 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
4576 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
4577 | (parallel | |
4578 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4579 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e AK |
4580 | (use (reg:SI GPR0_REGNUM)) |
4581 | (clobber (reg:CC CC_REGNUM))]) | |
4582 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") | |
4583 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4584 | "TARGET_HARD_DFP |
35dd9a0e AK |
4585 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4586 | { | |
4587 | HOST_WIDE_INT flags; | |
4588 | ||
4589 | flags = (PFPO_CONVERT | | |
4590 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4591 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4592 | ||
4593 | operands[2] = GEN_INT (flags); | |
4594 | }) | |
4595 | ||
4596 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 4597 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
4598 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
4599 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4600 | (parallel | |
2cf4c39e | 4601 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e AK |
4602 | (use (reg:SI GPR0_REGNUM)) |
4603 | (clobber (reg:CC CC_REGNUM))]) | |
4604 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] | |
fb068247 | 4605 | "TARGET_HARD_DFP |
35dd9a0e AK |
4606 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
4607 | { | |
4608 | HOST_WIDE_INT flags; | |
4609 | ||
4610 | flags = (PFPO_CONVERT | | |
4611 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4612 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4613 | ||
4614 | operands[2] = GEN_INT (flags); | |
4615 | }) | |
4616 | ||
4617 | ||
9db1d521 | 4618 | ;; |
fae778eb | 4619 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 4620 | ;; |
fae778eb | 4621 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
4622 | ; because of unpredictable Bits in Register for Halfword and Byte |
4623 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
4624 | ||
07893d4f UW |
4625 | ;; |
4626 | ;;- Add instructions. | |
4627 | ;; | |
4628 | ||
1c7b1b7e UW |
4629 | ; |
4630 | ; addti3 instruction pattern(s). | |
4631 | ; | |
4632 | ||
4633 | (define_insn_and_split "addti3" | |
4634 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
4635 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
4636 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 4637 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4638 | "TARGET_ZARCH" |
1c7b1b7e UW |
4639 | "#" |
4640 | "&& reload_completed" | |
4641 | [(parallel | |
ae156f85 | 4642 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
4643 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
4644 | (match_dup 7))) | |
4645 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
4646 | (parallel | |
a94a76a7 UW |
4647 | [(set (match_dup 3) (plus:DI |
4648 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4649 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4650 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
4651 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
4652 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
4653 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
4654 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
4655 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 4656 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 4657 | |
07893d4f UW |
4658 | ; |
4659 | ; adddi3 instruction pattern(s). | |
4660 | ; | |
4661 | ||
3298c037 AK |
4662 | (define_expand "adddi3" |
4663 | [(parallel | |
963fc8d0 | 4664 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
4665 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
4666 | (match_operand:DI 2 "general_operand" ""))) | |
4667 | (clobber (reg:CC CC_REGNUM))])] | |
4668 | "" | |
4669 | "") | |
4670 | ||
07893d4f UW |
4671 | (define_insn "*adddi3_sign" |
4672 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4673 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4674 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4675 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4676 | "TARGET_ZARCH" |
07893d4f | 4677 | "@ |
d40c829f UW |
4678 | agfr\t%0,%2 |
4679 | agf\t%0,%2" | |
65b1d8ea AK |
4680 | [(set_attr "op_type" "RRE,RXY") |
4681 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
4682 | |
4683 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 4684 | [(set (reg CC_REGNUM) |
fb492564 | 4685 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4686 | (match_operand:DI 1 "register_operand" "0,0")) |
4687 | (const_int 0))) | |
4688 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4689 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 4690 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4691 | "@ |
d40c829f UW |
4692 | algfr\t%0,%2 |
4693 | algf\t%0,%2" | |
9381e3f1 WG |
4694 | [(set_attr "op_type" "RRE,RXY") |
4695 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4696 | |
4697 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 4698 | [(set (reg CC_REGNUM) |
fb492564 | 4699 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
4700 | (match_operand:DI 1 "register_operand" "0,0")) |
4701 | (const_int 0))) | |
4702 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 4703 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 4704 | "@ |
d40c829f UW |
4705 | algfr\t%0,%2 |
4706 | algf\t%0,%2" | |
9381e3f1 WG |
4707 | [(set_attr "op_type" "RRE,RXY") |
4708 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
4709 | |
4710 | (define_insn "*adddi3_zero" | |
4711 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 4712 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 4713 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 4714 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4715 | "TARGET_ZARCH" |
07893d4f | 4716 | "@ |
d40c829f UW |
4717 | algfr\t%0,%2 |
4718 | algf\t%0,%2" | |
9381e3f1 WG |
4719 | [(set_attr "op_type" "RRE,RXY") |
4720 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 4721 | |
e69166de | 4722 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 4723 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
4724 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
4725 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 4726 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4727 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
4728 | "#" |
4729 | "&& reload_completed" | |
4730 | [(parallel | |
ae156f85 | 4731 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
4732 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4733 | (match_dup 7))) | |
4734 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4735 | (parallel | |
a94a76a7 UW |
4736 | [(set (match_dup 3) (plus:SI |
4737 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
4738 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 4739 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
4740 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4741 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4742 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4743 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4744 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 4745 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 4746 | |
07893d4f | 4747 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 4748 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 4749 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 4750 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 4751 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 4752 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4753 | "#" |
4754 | "&& reload_completed" | |
4755 | [(parallel | |
4756 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 4757 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4758 | (parallel |
ae156f85 | 4759 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
4760 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
4761 | (match_dup 7))) | |
4762 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
4763 | (set (pc) | |
ae156f85 | 4764 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
4765 | (pc) |
4766 | (label_ref (match_dup 9)))) | |
4767 | (parallel | |
4768 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 4769 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 4770 | (match_dup 9)] |
97c6f7ad UW |
4771 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4772 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4773 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4774 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4775 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4776 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4777 | operands[9] = gen_label_rtx ();") |
9db1d521 | 4778 | |
3298c037 AK |
4779 | ; |
4780 | ; addsi3 instruction pattern(s). | |
4781 | ; | |
4782 | ||
4783 | (define_expand "addsi3" | |
07893d4f | 4784 | [(parallel |
963fc8d0 | 4785 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
4786 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
4787 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 4788 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 4789 | "" |
07893d4f | 4790 | "") |
9db1d521 | 4791 | |
3298c037 AK |
4792 | (define_insn "*addsi3_sign" |
4793 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4794 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
4795 | (match_operand:SI 1 "register_operand" "0,0"))) | |
4796 | (clobber (reg:CC CC_REGNUM))] | |
4797 | "" | |
4798 | "@ | |
4799 | ah\t%0,%2 | |
4800 | ahy\t%0,%2" | |
65b1d8ea AK |
4801 | [(set_attr "op_type" "RX,RXY") |
4802 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 4803 | |
9db1d521 | 4804 | ; |
3298c037 | 4805 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 4806 | ; |
9db1d521 | 4807 | |
65b1d8ea | 4808 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 4809 | (define_insn "*add<mode>3" |
65b1d8ea AK |
4810 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
4811 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
4812 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
4813 | (clobber (reg:CC CC_REGNUM))] |
4814 | "" | |
ec24698e | 4815 | "@ |
3298c037 | 4816 | a<g>r\t%0,%2 |
65b1d8ea | 4817 | a<g>rk\t%0,%1,%2 |
3298c037 | 4818 | a<g>hi\t%0,%h2 |
65b1d8ea | 4819 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
4820 | al<g>fi\t%0,%2 |
4821 | sl<g>fi\t%0,%n2 | |
4822 | a<g>\t%0,%2 | |
963fc8d0 AK |
4823 | a<y>\t%0,%2 |
4824 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4825 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
4826 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
4827 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4828 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 4829 | |
65b1d8ea | 4830 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 4831 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 4832 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4833 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
4834 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 4835 | (match_dup 1))) |
65b1d8ea | 4836 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 4837 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4838 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4839 | "@ |
3298c037 | 4840 | al<g>r\t%0,%2 |
65b1d8ea | 4841 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4842 | al<g>fi\t%0,%2 |
4843 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4844 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4845 | al<g>\t%0,%2 |
963fc8d0 AK |
4846 | al<y>\t%0,%2 |
4847 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4848 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4849 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4850 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4851 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4852 | |
65b1d8ea | 4853 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4854 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 4855 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4856 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4857 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4858 | (match_dup 1))) |
65b1d8ea | 4859 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4860 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4861 | "@ |
3298c037 | 4862 | al<g>r\t%0,%2 |
65b1d8ea | 4863 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4864 | al<g>\t%0,%2 |
4865 | al<y>\t%0,%2" | |
65b1d8ea AK |
4866 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4867 | (set_attr "cpu_facility" "*,z196,*,*") | |
4868 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4869 | |
65b1d8ea | 4870 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4871 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 4872 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4873 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4874 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 4875 | (match_dup 2))) |
65b1d8ea | 4876 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4877 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4878 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4879 | "@ |
3298c037 | 4880 | al<g>r\t%0,%2 |
65b1d8ea | 4881 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4882 | al<g>fi\t%0,%2 |
4883 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4884 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4885 | al<g>\t%0,%2 |
963fc8d0 AK |
4886 | al<y>\t%0,%2 |
4887 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4888 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4889 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4890 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
4891 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4892 | |
65b1d8ea | 4893 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4894 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 4895 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4896 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4897 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 4898 | (match_dup 2))) |
65b1d8ea | 4899 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4900 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 4901 | "@ |
3298c037 | 4902 | al<g>r\t%0,%2 |
65b1d8ea | 4903 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4904 | al<g>\t%0,%2 |
4905 | al<y>\t%0,%2" | |
65b1d8ea AK |
4906 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4907 | (set_attr "cpu_facility" "*,z196,*,*") | |
4908 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4909 | |
65b1d8ea | 4910 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 4911 | (define_insn "*add<mode>3_cc" |
ae156f85 | 4912 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4913 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
4914 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 4915 | (const_int 0))) |
65b1d8ea | 4916 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 4917 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 4918 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4919 | "@ |
3298c037 | 4920 | al<g>r\t%0,%2 |
65b1d8ea | 4921 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4922 | al<g>fi\t%0,%2 |
4923 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 4924 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 4925 | al<g>\t%0,%2 |
963fc8d0 AK |
4926 | al<y>\t%0,%2 |
4927 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
4928 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
4929 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
4930 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
4931 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4932 | |
65b1d8ea | 4933 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4934 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 4935 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4936 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4937 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 4938 | (const_int 0))) |
65b1d8ea | 4939 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 4940 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4941 | "@ |
3298c037 | 4942 | al<g>r\t%0,%2 |
65b1d8ea | 4943 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4944 | al<g>\t%0,%2 |
4945 | al<y>\t%0,%2" | |
65b1d8ea AK |
4946 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4947 | (set_attr "cpu_facility" "*,z196,*,*") | |
4948 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4949 | |
65b1d8ea | 4950 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 4951 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 4952 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
4953 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
4954 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
4955 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 4956 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 4957 | "@ |
3298c037 | 4958 | al<g>r\t%0,%2 |
65b1d8ea | 4959 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
4960 | al<g>\t%0,%2 |
4961 | al<y>\t%0,%2" | |
65b1d8ea AK |
4962 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
4963 | (set_attr "cpu_facility" "*,z196,*,*") | |
4964 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 4965 | |
963fc8d0 | 4966 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
4967 | (define_insn "*add<mode>3_imm_cc" |
4968 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
4969 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
4970 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 4971 | (const_int 0))) |
65b1d8ea | 4972 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
4973 | (plus:GPR (match_dup 1) (match_dup 2)))] |
4974 | "s390_match_ccmode (insn, CCAmode) | |
4975 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
4976 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
4977 | /* Avoid INT32_MIN on 32 bit. */ | |
4978 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 4979 | "@ |
3298c037 | 4980 | a<g>hi\t%0,%h2 |
65b1d8ea | 4981 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
4982 | a<g>fi\t%0,%2 |
4983 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
4984 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
4985 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
4986 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4987 | |
9db1d521 | 4988 | ; |
609e7e80 | 4989 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
4990 | ; |
4991 | ||
609e7e80 | 4992 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
142cd70f | 4993 | (define_insn "add<mode>3" |
609e7e80 AK |
4994 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
4995 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
4996 | (match_operand:FP 2 "general_operand" " f,<Rf>"))) | |
ae156f85 | 4997 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 4998 | "TARGET_HARD_FLOAT" |
9db1d521 | 4999 | "@ |
609e7e80 | 5000 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5001 | a<xde>b\t%0,%2" |
609e7e80 | 5002 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5003 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5004 | |
609e7e80 | 5005 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5006 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5007 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5008 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
5009 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
5010 | (match_operand:FP 3 "const0_operand" ""))) | |
5011 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5012 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5013 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5014 | "@ |
609e7e80 | 5015 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5016 | a<xde>b\t%0,%2" |
609e7e80 | 5017 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5018 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5019 | |
609e7e80 | 5020 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5021 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5022 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5023 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
5024 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
5025 | (match_operand:FP 3 "const0_operand" ""))) | |
5026 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5027 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5028 | "@ |
609e7e80 | 5029 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5030 | a<xde>b\t%0,%2" |
609e7e80 | 5031 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5032 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5033 | |
9db1d521 HP |
5034 | |
5035 | ;; | |
5036 | ;;- Subtract instructions. | |
5037 | ;; | |
5038 | ||
1c7b1b7e UW |
5039 | ; |
5040 | ; subti3 instruction pattern(s). | |
5041 | ; | |
5042 | ||
5043 | (define_insn_and_split "subti3" | |
5044 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
5045 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
5046 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 5047 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5048 | "TARGET_ZARCH" |
1c7b1b7e UW |
5049 | "#" |
5050 | "&& reload_completed" | |
5051 | [(parallel | |
ae156f85 | 5052 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
5053 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
5054 | (match_dup 7))) | |
5055 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
5056 | (parallel | |
5057 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5058 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5059 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
5060 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5061 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5062 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5063 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5064 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 5065 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 5066 | |
9db1d521 HP |
5067 | ; |
5068 | ; subdi3 instruction pattern(s). | |
5069 | ; | |
5070 | ||
3298c037 AK |
5071 | (define_expand "subdi3" |
5072 | [(parallel | |
5073 | [(set (match_operand:DI 0 "register_operand" "") | |
5074 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
5075 | (match_operand:DI 2 "general_operand" ""))) | |
5076 | (clobber (reg:CC CC_REGNUM))])] | |
5077 | "" | |
5078 | "") | |
5079 | ||
07893d4f UW |
5080 | (define_insn "*subdi3_sign" |
5081 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5082 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5083 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5084 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5085 | "TARGET_ZARCH" |
07893d4f | 5086 | "@ |
d40c829f UW |
5087 | sgfr\t%0,%2 |
5088 | sgf\t%0,%2" | |
9381e3f1 | 5089 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
5090 | (set_attr "z10prop" "z10_c,*") |
5091 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
5092 | |
5093 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 5094 | [(set (reg CC_REGNUM) |
07893d4f | 5095 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5096 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5097 | (const_int 0))) |
5098 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5099 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 5100 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5101 | "@ |
d40c829f UW |
5102 | slgfr\t%0,%2 |
5103 | slgf\t%0,%2" | |
9381e3f1 WG |
5104 | [(set_attr "op_type" "RRE,RXY") |
5105 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5106 | |
5107 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 5108 | [(set (reg CC_REGNUM) |
07893d4f | 5109 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5110 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5111 | (const_int 0))) |
5112 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5113 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5114 | "@ |
d40c829f UW |
5115 | slgfr\t%0,%2 |
5116 | slgf\t%0,%2" | |
9381e3f1 WG |
5117 | [(set_attr "op_type" "RRE,RXY") |
5118 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5119 | |
5120 | (define_insn "*subdi3_zero" | |
5121 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5122 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5123 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5124 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5125 | "TARGET_ZARCH" |
07893d4f | 5126 | "@ |
d40c829f UW |
5127 | slgfr\t%0,%2 |
5128 | slgf\t%0,%2" | |
9381e3f1 WG |
5129 | [(set_attr "op_type" "RRE,RXY") |
5130 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 5131 | |
e69166de UW |
5132 | (define_insn_and_split "*subdi3_31z" |
5133 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5134 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
5135 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5136 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5137 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5138 | "#" |
5139 | "&& reload_completed" | |
5140 | [(parallel | |
ae156f85 | 5141 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
5142 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5143 | (match_dup 7))) | |
5144 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5145 | (parallel | |
5146 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5147 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5148 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
5149 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5150 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5151 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5152 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5153 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5154 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5155 | |
07893d4f UW |
5156 | (define_insn_and_split "*subdi3_31" |
5157 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5158 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 5159 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5160 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5161 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5162 | "#" |
5163 | "&& reload_completed" | |
5164 | [(parallel | |
5165 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5166 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5167 | (parallel |
ae156f85 | 5168 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
5169 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5170 | (match_dup 7))) | |
5171 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5172 | (set (pc) | |
ae156f85 | 5173 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5174 | (pc) |
5175 | (label_ref (match_dup 9)))) | |
5176 | (parallel | |
5177 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 5178 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5179 | (match_dup 9)] |
97c6f7ad UW |
5180 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5181 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5182 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5183 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5184 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5185 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5186 | operands[9] = gen_label_rtx ();") |
07893d4f | 5187 | |
3298c037 AK |
5188 | ; |
5189 | ; subsi3 instruction pattern(s). | |
5190 | ; | |
5191 | ||
5192 | (define_expand "subsi3" | |
07893d4f | 5193 | [(parallel |
3298c037 AK |
5194 | [(set (match_operand:SI 0 "register_operand" "") |
5195 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
5196 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5197 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5198 | "" |
07893d4f | 5199 | "") |
9db1d521 | 5200 | |
3298c037 AK |
5201 | (define_insn "*subsi3_sign" |
5202 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5203 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
5204 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
5205 | (clobber (reg:CC CC_REGNUM))] | |
5206 | "" | |
5207 | "@ | |
5208 | sh\t%0,%2 | |
5209 | shy\t%0,%2" | |
65b1d8ea AK |
5210 | [(set_attr "op_type" "RX,RXY") |
5211 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5212 | |
9db1d521 | 5213 | ; |
3298c037 | 5214 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
5215 | ; |
5216 | ||
65b1d8ea | 5217 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 5218 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
5219 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
5220 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
5221 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
5222 | (clobber (reg:CC CC_REGNUM))] |
5223 | "" | |
5224 | "@ | |
5225 | s<g>r\t%0,%2 | |
65b1d8ea | 5226 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
5227 | s<g>\t%0,%2 |
5228 | s<y>\t%0,%2" | |
65b1d8ea AK |
5229 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5230 | (set_attr "cpu_facility" "*,z196,*,*") | |
5231 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 5232 | |
65b1d8ea | 5233 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5234 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 5235 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5236 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5237 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5238 | (match_dup 1))) |
65b1d8ea | 5239 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5240 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5241 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5242 | "@ |
3298c037 | 5243 | sl<g>r\t%0,%2 |
65b1d8ea | 5244 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5245 | sl<g>\t%0,%2 |
5246 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5247 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5248 | (set_attr "cpu_facility" "*,z196,*,*") | |
5249 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5250 | |
65b1d8ea | 5251 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5252 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 5253 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5254 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5255 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5256 | (match_dup 1))) |
65b1d8ea | 5257 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5258 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5259 | "@ |
3298c037 | 5260 | sl<g>r\t%0,%2 |
65b1d8ea | 5261 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5262 | sl<g>\t%0,%2 |
5263 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5264 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5265 | (set_attr "cpu_facility" "*,z196,*,*") | |
5266 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5267 | |
65b1d8ea | 5268 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5269 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5270 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5271 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5272 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5273 | (const_int 0))) |
65b1d8ea | 5274 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5275 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5276 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5277 | "@ |
3298c037 | 5278 | sl<g>r\t%0,%2 |
65b1d8ea | 5279 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5280 | sl<g>\t%0,%2 |
5281 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5282 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5283 | (set_attr "cpu_facility" "*,z196,*,*") | |
5284 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5285 | |
65b1d8ea | 5286 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5287 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5288 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5289 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5290 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5291 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5292 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5293 | "s390_match_ccmode (insn, CCL3mode)" |
5294 | "@ | |
3298c037 | 5295 | sl<g>r\t%0,%2 |
65b1d8ea | 5296 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5297 | sl<g>\t%0,%2 |
5298 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5299 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5300 | (set_attr "cpu_facility" "*,z196,*,*") | |
5301 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5302 | |
65b1d8ea | 5303 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5304 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5305 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5306 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5307 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5308 | (const_int 0))) |
65b1d8ea | 5309 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5310 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5311 | "@ |
3298c037 | 5312 | sl<g>r\t%0,%2 |
65b1d8ea | 5313 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5314 | sl<g>\t%0,%2 |
5315 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5316 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5317 | (set_attr "cpu_facility" "*,z196,*,*") | |
5318 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5319 | |
9db1d521 | 5320 | |
65b1d8ea | 5321 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5322 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5323 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5324 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5325 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5326 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5327 | "s390_match_ccmode (insn, CCL3mode)" |
5328 | "@ | |
3298c037 | 5329 | sl<g>r\t%0,%2 |
65b1d8ea | 5330 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5331 | sl<g>\t%0,%2 |
5332 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5333 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5334 | (set_attr "cpu_facility" "*,z196,*,*") | |
5335 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5336 | |
9db1d521 HP |
5337 | |
5338 | ; | |
609e7e80 | 5339 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5340 | ; |
5341 | ||
d46f24b6 | 5342 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5343 | (define_insn "sub<mode>3" |
609e7e80 AK |
5344 | [(set (match_operand:FP 0 "register_operand" "=f, f") |
5345 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
142cd70f | 5346 | (match_operand:FP 2 "general_operand" "f,<Rf>"))) |
ae156f85 | 5347 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5348 | "TARGET_HARD_FLOAT" |
9db1d521 | 5349 | "@ |
609e7e80 | 5350 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5351 | s<xde>b\t%0,%2" |
609e7e80 | 5352 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5353 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5354 | |
d46f24b6 | 5355 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5356 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5357 | [(set (reg CC_REGNUM) |
609e7e80 | 5358 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 5359 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
5360 | (match_operand:FP 3 "const0_operand" ""))) |
5361 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5362 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5363 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5364 | "@ |
609e7e80 | 5365 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5366 | s<xde>b\t%0,%2" |
609e7e80 | 5367 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5368 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5369 | |
d46f24b6 | 5370 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5371 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5372 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5373 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
5374 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
5375 | (match_operand:FP 3 "const0_operand" ""))) | |
5376 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5377 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5378 | "@ |
609e7e80 | 5379 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5380 | s<xde>b\t%0,%2" |
609e7e80 | 5381 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5382 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5383 | |
9db1d521 | 5384 | |
e69166de UW |
5385 | ;; |
5386 | ;;- Conditional add/subtract instructions. | |
5387 | ;; | |
5388 | ||
5389 | ; | |
9a91a21f | 5390 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
5391 | ; |
5392 | ||
a996720c UW |
5393 | ; the following 4 patterns are used when the result of an add with |
5394 | ; carry is checked for an overflow condition | |
5395 | ||
5396 | ; op1 + op2 + c < op1 | |
5397 | ||
5398 | ; alcr, alc, alcgr, alcg | |
5399 | (define_insn "*add<mode>3_alc_carry1_cc" | |
5400 | [(set (reg CC_REGNUM) | |
5401 | (compare | |
5402 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5403 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5404 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5405 | (match_dup 1))) |
5406 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5407 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5408 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5409 | "@ | |
5410 | alc<g>r\t%0,%2 | |
5411 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5412 | [(set_attr "op_type" "RRE,RXY") |
5413 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5414 | |
5415 | ; alcr, alc, alcgr, alcg | |
5416 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
5417 | [(set (reg CC_REGNUM) | |
5418 | (compare | |
5419 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5420 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5421 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5422 | (match_dup 1))) |
5423 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5424 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5425 | "@ | |
5426 | alc<g>r\t%0,%2 | |
5427 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5428 | [(set_attr "op_type" "RRE,RXY") |
5429 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5430 | |
5431 | ; op1 + op2 + c < op2 | |
5432 | ||
5433 | ; alcr, alc, alcgr, alcg | |
5434 | (define_insn "*add<mode>3_alc_carry2_cc" | |
5435 | [(set (reg CC_REGNUM) | |
5436 | (compare | |
5437 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5438 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5439 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5440 | (match_dup 2))) |
5441 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5442 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5443 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5444 | "@ | |
5445 | alc<g>r\t%0,%2 | |
5446 | alc<g>\t%0,%2" | |
5447 | [(set_attr "op_type" "RRE,RXY")]) | |
5448 | ||
5449 | ; alcr, alc, alcgr, alcg | |
5450 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
5451 | [(set (reg CC_REGNUM) | |
5452 | (compare | |
5453 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5454 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5455 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5456 | (match_dup 2))) |
5457 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5458 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5459 | "@ | |
5460 | alc<g>r\t%0,%2 | |
5461 | alc<g>\t%0,%2" | |
5462 | [(set_attr "op_type" "RRE,RXY")]) | |
5463 | ||
43a09b63 | 5464 | ; alcr, alc, alcgr, alcg |
9a91a21f | 5465 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 5466 | [(set (reg CC_REGNUM) |
e69166de | 5467 | (compare |
a94a76a7 UW |
5468 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5469 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5470 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 5471 | (const_int 0))) |
9a91a21f | 5472 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 5473 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 5474 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5475 | "@ |
9a91a21f AS |
5476 | alc<g>r\t%0,%2 |
5477 | alc<g>\t%0,%2" | |
e69166de UW |
5478 | [(set_attr "op_type" "RRE,RXY")]) |
5479 | ||
43a09b63 | 5480 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
5481 | (define_insn "*add<mode>3_alc" |
5482 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
5483 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5484 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5485 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 5486 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5487 | "TARGET_CPU_ZARCH" |
e69166de | 5488 | "@ |
9a91a21f AS |
5489 | alc<g>r\t%0,%2 |
5490 | alc<g>\t%0,%2" | |
e69166de UW |
5491 | [(set_attr "op_type" "RRE,RXY")]) |
5492 | ||
43a09b63 | 5493 | ; slbr, slb, slbgr, slbg |
9a91a21f | 5494 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 5495 | [(set (reg CC_REGNUM) |
e69166de | 5496 | (compare |
9a91a21f | 5497 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 5498 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5499 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 5500 | (const_int 0))) |
9a91a21f AS |
5501 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
5502 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 5503 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5504 | "@ |
9a91a21f AS |
5505 | slb<g>r\t%0,%2 |
5506 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5507 | [(set_attr "op_type" "RRE,RXY") |
5508 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5509 | |
43a09b63 | 5510 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
5511 | (define_insn "*sub<mode>3_slb" |
5512 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
5513 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 5514 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 5515 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 5516 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5517 | "TARGET_CPU_ZARCH" |
e69166de | 5518 | "@ |
9a91a21f AS |
5519 | slb<g>r\t%0,%2 |
5520 | slb<g>\t%0,%2" | |
9381e3f1 WG |
5521 | [(set_attr "op_type" "RRE,RXY") |
5522 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 5523 | |
9a91a21f AS |
5524 | (define_expand "add<mode>cc" |
5525 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 5526 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
5527 | (match_operand:GPR 2 "register_operand" "") |
5528 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 5529 | "TARGET_CPU_ZARCH" |
9381e3f1 | 5530 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 5531 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 5532 | operands[0], operands[2], |
5d880bd2 UW |
5533 | operands[3])) FAIL; DONE;") |
5534 | ||
5535 | ; | |
5536 | ; scond instruction pattern(s). | |
5537 | ; | |
5538 | ||
9a91a21f AS |
5539 | (define_insn_and_split "*scond<mode>" |
5540 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5541 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 5542 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5543 | "TARGET_CPU_ZARCH" |
5544 | "#" | |
5545 | "&& reload_completed" | |
5546 | [(set (match_dup 0) (const_int 0)) | |
5547 | (parallel | |
a94a76a7 UW |
5548 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
5549 | (match_dup 0))) | |
ae156f85 | 5550 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5551 | "") |
5d880bd2 | 5552 | |
9a91a21f AS |
5553 | (define_insn_and_split "*scond<mode>_neg" |
5554 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
5555 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 5556 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
5557 | "TARGET_CPU_ZARCH" |
5558 | "#" | |
5559 | "&& reload_completed" | |
5560 | [(set (match_dup 0) (const_int 0)) | |
5561 | (parallel | |
9a91a21f AS |
5562 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
5563 | (match_dup 1))) | |
ae156f85 | 5564 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 5565 | (parallel |
9a91a21f | 5566 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 5567 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 5568 | "") |
5d880bd2 | 5569 | |
5d880bd2 | 5570 | |
f90b7a5a | 5571 | (define_expand "cstore<mode>4" |
9a91a21f | 5572 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
5573 | (match_operator:SI 1 "s390_scond_operator" |
5574 | [(match_operand:GPR 2 "register_operand" "") | |
5575 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 5576 | "TARGET_CPU_ZARCH" |
f90b7a5a | 5577 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
5578 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
5579 | ||
f90b7a5a | 5580 | (define_expand "cstorecc4" |
69950452 | 5581 | [(parallel |
f90b7a5a PB |
5582 | [(set (match_operand:SI 0 "register_operand" "") |
5583 | (match_operator:SI 1 "s390_eqne_operator" | |
5584 | [(match_operand:CCZ1 2 "register_operand") | |
5585 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
5586 | (clobber (reg:CC CC_REGNUM))])] |
5587 | "" | |
f90b7a5a PB |
5588 | "emit_insn (gen_sne (operands[0], operands[2])); |
5589 | if (GET_CODE (operands[1]) == EQ) | |
5590 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
5591 | DONE;") | |
69950452 | 5592 | |
f90b7a5a | 5593 | (define_insn_and_split "sne" |
69950452 | 5594 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 5595 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
5596 | (const_int 0))) |
5597 | (clobber (reg:CC CC_REGNUM))] | |
5598 | "" | |
5599 | "#" | |
5600 | "reload_completed" | |
5601 | [(parallel | |
5602 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
5603 | (clobber (reg:CC CC_REGNUM))])]) | |
5604 | ||
e69166de | 5605 | |
65b1d8ea AK |
5606 | ;; |
5607 | ;; - Conditional move instructions (introduced with z196) | |
5608 | ;; | |
5609 | ||
5610 | (define_expand "mov<mode>cc" | |
5611 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
5612 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
5613 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
5614 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
5615 | "TARGET_Z196" | |
5616 | "operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
5617 | XEXP (operands[1], 0), XEXP (operands[1], 1));") | |
5618 | ||
27037b5f | 5619 | ; locr, loc, stoc, locgr, locg, stocg |
65b1d8ea AK |
5620 | (define_insn_and_split "*mov<mode>cc" |
5621 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
5622 | (if_then_else:GPR | |
5623 | (match_operator 1 "s390_comparison" | |
5624 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5a3fe9b6 | 5625 | (match_operand 5 "const_int_operand" "")]) |
65b1d8ea AK |
5626 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") |
5627 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
5628 | "TARGET_Z196" | |
5629 | "@ | |
5630 | loc<g>r%C1\t%0,%3 | |
5631 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
5632 | loc<g>%C1\t%0,%3 |
5633 | loc<g>%D1\t%0,%4 | |
5634 | stoc<g>%C1\t%3,%0 | |
5635 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
5636 | #" |
5637 | "&& reload_completed | |
5638 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
5639 | [(set (match_dup 0) | |
5640 | (if_then_else:GPR | |
5641 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5642 | (match_dup 3) | |
5643 | (match_dup 0))) | |
5644 | (set (match_dup 0) | |
5645 | (if_then_else:GPR | |
5646 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
5647 | (match_dup 0) | |
5648 | (match_dup 4)))] | |
5649 | "" | |
5650 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
5651 | ||
9db1d521 HP |
5652 | ;; |
5653 | ;;- Multiply instructions. | |
5654 | ;; | |
5655 | ||
4023fb28 UW |
5656 | ; |
5657 | ; muldi3 instruction pattern(s). | |
5658 | ; | |
9db1d521 | 5659 | |
07893d4f UW |
5660 | (define_insn "*muldi3_sign" |
5661 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 5662 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5663 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 5664 | "TARGET_ZARCH" |
07893d4f | 5665 | "@ |
d40c829f UW |
5666 | msgfr\t%0,%2 |
5667 | msgf\t%0,%2" | |
963fc8d0 AK |
5668 | [(set_attr "op_type" "RRE,RXY") |
5669 | (set_attr "type" "imuldi")]) | |
07893d4f | 5670 | |
4023fb28 | 5671 | (define_insn "muldi3" |
963fc8d0 AK |
5672 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
5673 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5674 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 5675 | "TARGET_ZARCH" |
9db1d521 | 5676 | "@ |
d40c829f UW |
5677 | msgr\t%0,%2 |
5678 | mghi\t%0,%h2 | |
963fc8d0 AK |
5679 | msg\t%0,%2 |
5680 | msgfi\t%0,%2" | |
5681 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
5682 | (set_attr "type" "imuldi") | |
5683 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 5684 | |
9db1d521 HP |
5685 | ; |
5686 | ; mulsi3 instruction pattern(s). | |
5687 | ; | |
5688 | ||
f1e77d83 | 5689 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
5690 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
5691 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5692 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 5693 | "" |
963fc8d0 AK |
5694 | "@ |
5695 | mh\t%0,%2 | |
5696 | mhy\t%0,%2" | |
5697 | [(set_attr "op_type" "RX,RXY") | |
5698 | (set_attr "type" "imulhi") | |
5699 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 5700 | |
9db1d521 | 5701 | (define_insn "mulsi3" |
963fc8d0 AK |
5702 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
5703 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5704 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
5705 | "" |
5706 | "@ | |
d40c829f UW |
5707 | msr\t%0,%2 |
5708 | mhi\t%0,%h2 | |
5709 | ms\t%0,%2 | |
963fc8d0 AK |
5710 | msy\t%0,%2 |
5711 | msfi\t%0,%2" | |
5712 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
5713 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
5714 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 5715 | |
4023fb28 UW |
5716 | ; |
5717 | ; mulsidi3 instruction pattern(s). | |
5718 | ; | |
5719 | ||
f1e77d83 | 5720 | (define_insn "mulsidi3" |
963fc8d0 | 5721 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 5722 | (mult:DI (sign_extend:DI |
963fc8d0 | 5723 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 5724 | (sign_extend:DI |
963fc8d0 | 5725 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 5726 | "!TARGET_ZARCH" |
f1e77d83 UW |
5727 | "@ |
5728 | mr\t%0,%2 | |
963fc8d0 AK |
5729 | m\t%0,%2 |
5730 | mfy\t%0,%2" | |
5731 | [(set_attr "op_type" "RR,RX,RXY") | |
5732 | (set_attr "type" "imulsi") | |
5733 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 5734 | |
f1e77d83 | 5735 | ; |
6e0d70c9 | 5736 | ; umul instruction pattern(s). |
f1e77d83 | 5737 | ; |
c7453384 | 5738 | |
6e0d70c9 AK |
5739 | ; mlr, ml, mlgr, mlg |
5740 | (define_insn "umul<dwh><mode>3" | |
5741 | [(set (match_operand:DW 0 "register_operand" "=d, d") | |
5742 | (mult:DW (zero_extend:DW | |
5743 | (match_operand:<DWH> 1 "register_operand" "%0, 0")) | |
5744 | (zero_extend:DW | |
5745 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] | |
5746 | "TARGET_CPU_ZARCH" | |
f1e77d83 | 5747 | "@ |
6e0d70c9 AK |
5748 | ml<tg>r\t%0,%2 |
5749 | ml<tg>\t%0,%2" | |
f1e77d83 | 5750 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 5751 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 5752 | |
9db1d521 | 5753 | ; |
609e7e80 | 5754 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5755 | ; |
5756 | ||
9381e3f1 | 5757 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 5758 | (define_insn "mul<mode>3" |
609e7e80 AK |
5759 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
5760 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") | |
5761 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 5762 | "TARGET_HARD_FLOAT" |
9db1d521 | 5763 | "@ |
609e7e80 | 5764 | m<xdee><bt>r\t%0,<op1>%2 |
f61a2c7d | 5765 | m<xdee>b\t%0,%2" |
609e7e80 | 5766 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5767 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 5768 | |
9381e3f1 | 5769 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 5770 | (define_insn "fma<mode>4" |
f61a2c7d | 5771 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
d7ecb504 RH |
5772 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5773 | (match_operand:DSF 2 "nonimmediate_operand" "f,R") | |
f61a2c7d | 5774 | (match_operand:DSF 3 "register_operand" "0,0")))] |
d7ecb504 | 5775 | "TARGET_HARD_FLOAT" |
a1b892b5 | 5776 | "@ |
f61a2c7d AK |
5777 | ma<xde>br\t%0,%1,%2 |
5778 | ma<xde>b\t%0,%1,%2" | |
a1b892b5 | 5779 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5780 | (set_attr "type" "fmadd<mode>")]) |
a1b892b5 | 5781 | |
43a09b63 | 5782 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 5783 | (define_insn "fms<mode>4" |
f61a2c7d | 5784 | [(set (match_operand:DSF 0 "register_operand" "=f,f") |
d7ecb504 RH |
5785 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f") |
5786 | (match_operand:DSF 2 "nonimmediate_operand" "f,R") | |
5787 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))] | |
5788 | "TARGET_HARD_FLOAT" | |
a1b892b5 | 5789 | "@ |
f61a2c7d AK |
5790 | ms<xde>br\t%0,%1,%2 |
5791 | ms<xde>b\t%0,%1,%2" | |
ce50cae8 | 5792 | [(set_attr "op_type" "RRE,RXE") |
65b1d8ea | 5793 | (set_attr "type" "fmadd<mode>")]) |
9db1d521 HP |
5794 | |
5795 | ;; | |
5796 | ;;- Divide and modulo instructions. | |
5797 | ;; | |
5798 | ||
5799 | ; | |
4023fb28 | 5800 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
5801 | ; |
5802 | ||
4023fb28 UW |
5803 | (define_expand "divmoddi4" |
5804 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 5805 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
5806 | (match_operand:DI 2 "general_operand" ""))) |
5807 | (set (match_operand:DI 3 "general_operand" "") | |
5808 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
5809 | (clobber (match_dup 4))] | |
9602b6a1 | 5810 | "TARGET_ZARCH" |
9db1d521 | 5811 | { |
f1e77d83 | 5812 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
5813 | |
5814 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
5815 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
5816 | |
5817 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 5818 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
5819 | |
5820 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5821 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5822 | |
5823 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5824 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5825 | |
9db1d521 | 5826 | DONE; |
10bbf137 | 5827 | }) |
9db1d521 HP |
5828 | |
5829 | (define_insn "divmodtidi3" | |
4023fb28 UW |
5830 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
5831 | (ior:TI | |
4023fb28 UW |
5832 | (ashift:TI |
5833 | (zero_extend:TI | |
5665e398 | 5834 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5835 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
5836 | (const_int 64)) |
5837 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 5838 | "TARGET_ZARCH" |
9db1d521 | 5839 | "@ |
d40c829f UW |
5840 | dsgr\t%0,%2 |
5841 | dsg\t%0,%2" | |
d3632d41 | 5842 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5843 | (set_attr "type" "idiv")]) |
9db1d521 | 5844 | |
4023fb28 UW |
5845 | (define_insn "divmodtisi3" |
5846 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
5847 | (ior:TI | |
4023fb28 UW |
5848 | (ashift:TI |
5849 | (zero_extend:TI | |
5665e398 | 5850 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 5851 | (sign_extend:DI |
fb492564 | 5852 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
5853 | (const_int 64)) |
5854 | (zero_extend:TI | |
5855 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 5856 | "TARGET_ZARCH" |
4023fb28 | 5857 | "@ |
d40c829f UW |
5858 | dsgfr\t%0,%2 |
5859 | dsgf\t%0,%2" | |
d3632d41 | 5860 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5861 | (set_attr "type" "idiv")]) |
9db1d521 | 5862 | |
4023fb28 UW |
5863 | ; |
5864 | ; udivmoddi4 instruction pattern(s). | |
5865 | ; | |
9db1d521 | 5866 | |
4023fb28 UW |
5867 | (define_expand "udivmoddi4" |
5868 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
5869 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
5870 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
5871 | (set (match_operand:DI 3 "general_operand" "") | |
5872 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
5873 | (clobber (match_dup 4))] | |
9602b6a1 | 5874 | "TARGET_ZARCH" |
9db1d521 | 5875 | { |
4023fb28 UW |
5876 | rtx insn, div_equal, mod_equal, equal; |
5877 | ||
5878 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
5879 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
5880 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
5881 | gen_rtx_ASHIFT (TImode, |
5882 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
5883 | GEN_INT (64)), |
5884 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
5885 | |
5886 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 5887 | emit_clobber (operands[4]); |
4023fb28 UW |
5888 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
5889 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 5890 | |
4023fb28 | 5891 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5892 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5893 | |
5894 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 5895 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5896 | |
5897 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 5898 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5899 | |
9db1d521 | 5900 | DONE; |
10bbf137 | 5901 | }) |
9db1d521 HP |
5902 | |
5903 | (define_insn "udivmodtidi3" | |
4023fb28 | 5904 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 5905 | (ior:TI |
5665e398 UW |
5906 | (ashift:TI |
5907 | (zero_extend:TI | |
5908 | (truncate:DI | |
2f7e5a0d EC |
5909 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
5910 | (zero_extend:TI | |
fb492564 | 5911 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
5912 | (const_int 64)) |
5913 | (zero_extend:TI | |
5914 | (truncate:DI | |
5915 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 5916 | "TARGET_ZARCH" |
9db1d521 | 5917 | "@ |
d40c829f UW |
5918 | dlgr\t%0,%2 |
5919 | dlg\t%0,%2" | |
d3632d41 | 5920 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 5921 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5922 | |
5923 | ; | |
4023fb28 | 5924 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
5925 | ; |
5926 | ||
4023fb28 UW |
5927 | (define_expand "divmodsi4" |
5928 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5929 | (div:SI (match_operand:SI 1 "general_operand" "") | |
5930 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5931 | (set (match_operand:SI 3 "general_operand" "") | |
5932 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
5933 | (clobber (match_dup 4))] | |
9602b6a1 | 5934 | "!TARGET_ZARCH" |
9db1d521 | 5935 | { |
4023fb28 UW |
5936 | rtx insn, div_equal, mod_equal, equal; |
5937 | ||
5938 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
5939 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
5940 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5941 | gen_rtx_ASHIFT (DImode, |
5942 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
5943 | GEN_INT (32)), |
5944 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
5945 | |
5946 | operands[4] = gen_reg_rtx(DImode); | |
5947 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 5948 | |
4023fb28 | 5949 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 5950 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
5951 | |
5952 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 5953 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
5954 | |
5955 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 5956 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 5957 | |
9db1d521 | 5958 | DONE; |
10bbf137 | 5959 | }) |
9db1d521 HP |
5960 | |
5961 | (define_insn "divmoddisi3" | |
4023fb28 | 5962 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 5963 | (ior:DI |
5665e398 UW |
5964 | (ashift:DI |
5965 | (zero_extend:DI | |
5966 | (truncate:SI | |
2f7e5a0d EC |
5967 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
5968 | (sign_extend:DI | |
5665e398 UW |
5969 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
5970 | (const_int 32)) | |
5971 | (zero_extend:DI | |
5972 | (truncate:SI | |
5973 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 5974 | "!TARGET_ZARCH" |
9db1d521 | 5975 | "@ |
d40c829f UW |
5976 | dr\t%0,%2 |
5977 | d\t%0,%2" | |
9db1d521 | 5978 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5979 | (set_attr "type" "idiv")]) |
9db1d521 HP |
5980 | |
5981 | ; | |
5982 | ; udivsi3 and umodsi3 instruction pattern(s). | |
5983 | ; | |
5984 | ||
f1e77d83 UW |
5985 | (define_expand "udivmodsi4" |
5986 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
5987 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
5988 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
5989 | (set (match_operand:SI 3 "general_operand" "") | |
5990 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
5991 | (clobber (match_dup 4))] | |
9602b6a1 | 5992 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
5993 | { |
5994 | rtx insn, div_equal, mod_equal, equal; | |
5995 | ||
5996 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5997 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5998 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
5999 | gen_rtx_ASHIFT (DImode, |
6000 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6001 | GEN_INT (32)), |
6002 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
6003 | |
6004 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 6005 | emit_clobber (operands[4]); |
f1e77d83 UW |
6006 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
6007 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 6008 | |
f1e77d83 | 6009 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6010 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
6011 | |
6012 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6013 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
6014 | |
6015 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6016 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
6017 | |
6018 | DONE; | |
6019 | }) | |
6020 | ||
6021 | (define_insn "udivmoddisi3" | |
6022 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 6023 | (ior:DI |
5665e398 UW |
6024 | (ashift:DI |
6025 | (zero_extend:DI | |
6026 | (truncate:SI | |
2f7e5a0d EC |
6027 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
6028 | (zero_extend:DI | |
fb492564 | 6029 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6030 | (const_int 32)) |
6031 | (zero_extend:DI | |
6032 | (truncate:SI | |
6033 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6034 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6035 | "@ |
6036 | dlr\t%0,%2 | |
6037 | dl\t%0,%2" | |
6038 | [(set_attr "op_type" "RRE,RXY") | |
6039 | (set_attr "type" "idiv")]) | |
4023fb28 | 6040 | |
9db1d521 HP |
6041 | (define_expand "udivsi3" |
6042 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6043 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
6044 | (match_operand:SI 2 "general_operand" ""))) |
6045 | (clobber (match_dup 3))] | |
9602b6a1 | 6046 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6047 | { |
4023fb28 UW |
6048 | rtx insn, udiv_equal, umod_equal, equal; |
6049 | ||
6050 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6051 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6052 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6053 | gen_rtx_ASHIFT (DImode, |
6054 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6055 | GEN_INT (32)), |
6056 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6057 | |
4023fb28 | 6058 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6059 | |
6060 | if (CONSTANT_P (operands[2])) | |
6061 | { | |
6062 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
6063 | { | |
6064 | rtx label1 = gen_label_rtx (); | |
6065 | ||
4023fb28 UW |
6066 | operands[1] = make_safe_from (operands[1], operands[0]); |
6067 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6068 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
6069 | SImode, 1, label1); | |
4023fb28 | 6070 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6071 | emit_label (label1); |
6072 | } | |
6073 | else | |
6074 | { | |
c7453384 EC |
6075 | operands[2] = force_reg (SImode, operands[2]); |
6076 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6077 | |
6078 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6079 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6080 | operands[2])); | |
bd94cb6e | 6081 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6082 | |
6083 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6084 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 6085 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
6086 | } |
6087 | } | |
6088 | else | |
c7453384 | 6089 | { |
9db1d521 HP |
6090 | rtx label1 = gen_label_rtx (); |
6091 | rtx label2 = gen_label_rtx (); | |
6092 | rtx label3 = gen_label_rtx (); | |
6093 | ||
c7453384 EC |
6094 | operands[1] = force_reg (SImode, operands[1]); |
6095 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6096 | operands[2] = force_reg (SImode, operands[2]); | |
6097 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6098 | |
6099 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6100 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6101 | SImode, 1, label3); | |
6102 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6103 | SImode, 0, label2); | |
6104 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6105 | SImode, 0, label1); | |
4023fb28 UW |
6106 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6107 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6108 | operands[2])); | |
bd94cb6e | 6109 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6110 | |
6111 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6112 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
6113 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
6114 | ||
f314b9b1 | 6115 | emit_jump (label3); |
9db1d521 | 6116 | emit_label (label1); |
4023fb28 | 6117 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 6118 | emit_jump (label3); |
9db1d521 | 6119 | emit_label (label2); |
4023fb28 | 6120 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6121 | emit_label (label3); |
6122 | } | |
c7453384 | 6123 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 6124 | DONE; |
10bbf137 | 6125 | }) |
9db1d521 HP |
6126 | |
6127 | (define_expand "umodsi3" | |
6128 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6129 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
6130 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
6131 | (clobber (match_dup 3))] | |
9602b6a1 | 6132 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6133 | { |
4023fb28 UW |
6134 | rtx insn, udiv_equal, umod_equal, equal; |
6135 | ||
6136 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6137 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6138 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6139 | gen_rtx_ASHIFT (DImode, |
6140 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6141 | GEN_INT (32)), |
6142 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6143 | |
4023fb28 | 6144 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6145 | |
6146 | if (CONSTANT_P (operands[2])) | |
6147 | { | |
6148 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
6149 | { | |
6150 | rtx label1 = gen_label_rtx (); | |
6151 | ||
4023fb28 UW |
6152 | operands[1] = make_safe_from (operands[1], operands[0]); |
6153 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
6154 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
6155 | SImode, 1, label1); | |
4023fb28 UW |
6156 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
6157 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
6158 | emit_label (label1); |
6159 | } | |
6160 | else | |
6161 | { | |
c7453384 EC |
6162 | operands[2] = force_reg (SImode, operands[2]); |
6163 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6164 | |
6165 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6166 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6167 | operands[2])); | |
bd94cb6e | 6168 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6169 | |
6170 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6171 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 6172 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
6173 | } |
6174 | } | |
6175 | else | |
6176 | { | |
6177 | rtx label1 = gen_label_rtx (); | |
6178 | rtx label2 = gen_label_rtx (); | |
6179 | rtx label3 = gen_label_rtx (); | |
6180 | ||
c7453384 EC |
6181 | operands[1] = force_reg (SImode, operands[1]); |
6182 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6183 | operands[2] = force_reg (SImode, operands[2]); | |
6184 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 6185 | |
c7453384 | 6186 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
6187 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6188 | SImode, 1, label3); | |
6189 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6190 | SImode, 0, label2); | |
6191 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6192 | SImode, 0, label1); | |
4023fb28 UW |
6193 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6194 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6195 | operands[2])); | |
bd94cb6e | 6196 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6197 | |
6198 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6199 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
6200 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
6201 | ||
f314b9b1 | 6202 | emit_jump (label3); |
9db1d521 | 6203 | emit_label (label1); |
4023fb28 | 6204 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 6205 | emit_jump (label3); |
9db1d521 | 6206 | emit_label (label2); |
4023fb28 | 6207 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
6208 | emit_label (label3); |
6209 | } | |
9db1d521 | 6210 | DONE; |
10bbf137 | 6211 | }) |
9db1d521 HP |
6212 | |
6213 | ; | |
f5905b37 | 6214 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
6215 | ; |
6216 | ||
609e7e80 | 6217 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 6218 | (define_insn "div<mode>3" |
609e7e80 AK |
6219 | [(set (match_operand:FP 0 "register_operand" "=f,f") |
6220 | (div:FP (match_operand:FP 1 "register_operand" "<f0>,0") | |
6221 | (match_operand:FP 2 "general_operand" "f,<Rf>")))] | |
142cd70f | 6222 | "TARGET_HARD_FLOAT" |
9db1d521 | 6223 | "@ |
609e7e80 | 6224 | d<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 6225 | d<xde>b\t%0,%2" |
609e7e80 | 6226 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 6227 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 6228 | |
9db1d521 HP |
6229 | |
6230 | ;; | |
6231 | ;;- And instructions. | |
6232 | ;; | |
6233 | ||
047d35ed AS |
6234 | (define_expand "and<mode>3" |
6235 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6236 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6237 | (match_operand:INT 2 "general_operand" ""))) | |
6238 | (clobber (reg:CC CC_REGNUM))] | |
6239 | "" | |
6240 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
6241 | ||
9db1d521 HP |
6242 | ; |
6243 | ; anddi3 instruction pattern(s). | |
6244 | ; | |
6245 | ||
6246 | (define_insn "*anddi3_cc" | |
ae156f85 | 6247 | [(set (reg CC_REGNUM) |
e3140518 RH |
6248 | (compare |
6249 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6250 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
6251 | (const_int 0))) | |
6252 | (set (match_operand:DI 0 "register_operand" "=d,d, d, d") | |
9db1d521 | 6253 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 6254 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 6255 | "@ |
d40c829f | 6256 | ngr\t%0,%2 |
65b1d8ea | 6257 | ngrk\t%0,%1,%2 |
e3140518 RH |
6258 | ng\t%0,%2 |
6259 | risbg\t%0,%1,%s2,128+%e2,0" | |
6260 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6261 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6262 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6263 | |
6264 | (define_insn "*anddi3_cconly" | |
ae156f85 | 6265 | [(set (reg CC_REGNUM) |
e3140518 RH |
6266 | (compare |
6267 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6268 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
9db1d521 | 6269 | (const_int 0))) |
e3140518 RH |
6270 | (clobber (match_scratch:DI 0 "=d,d, d, d"))] |
6271 | "TARGET_ZARCH | |
6272 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
6273 | /* Do not steal TM patterns. */ |
6274 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 6275 | "@ |
d40c829f | 6276 | ngr\t%0,%2 |
65b1d8ea | 6277 | ngrk\t%0,%1,%2 |
e3140518 RH |
6278 | ng\t%0,%2 |
6279 | risbg\t%0,%1,%s2,128+%e2,0" | |
6280 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6281 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6282 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6283 | |
3af8e996 | 6284 | (define_insn "*anddi3" |
65b1d8ea | 6285 | [(set (match_operand:DI 0 "nonimmediate_operand" |
e3140518 RH |
6286 | "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") |
6287 | (and:DI | |
6288 | (match_operand:DI 1 "nonimmediate_operand" | |
6289 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") | |
6290 | (match_operand:DI 2 "general_operand" | |
6291 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) | |
ec24698e | 6292 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6293 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6294 | "@ |
6295 | # | |
6296 | # | |
6297 | nihh\t%0,%j2 | |
6298 | nihl\t%0,%j2 | |
6299 | nilh\t%0,%j2 | |
6300 | nill\t%0,%j2 | |
6301 | nihf\t%0,%m2 | |
6302 | nilf\t%0,%m2 | |
6303 | ngr\t%0,%2 | |
65b1d8ea | 6304 | ngrk\t%0,%1,%2 |
ec24698e | 6305 | ng\t%0,%2 |
e3140518 | 6306 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
6307 | # |
6308 | #" | |
e3140518 RH |
6309 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
6310 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
6311 | (set_attr "z10prop" "*, |
6312 | *, | |
6313 | z10_super_E1, | |
6314 | z10_super_E1, | |
6315 | z10_super_E1, | |
6316 | z10_super_E1, | |
6317 | z10_super_E1, | |
6318 | z10_super_E1, | |
6319 | z10_super_E1, | |
65b1d8ea | 6320 | *, |
9381e3f1 | 6321 | z10_super_E1, |
e3140518 | 6322 | z10_super_E1, |
9381e3f1 WG |
6323 | *, |
6324 | *")]) | |
0dfa6c5e UW |
6325 | |
6326 | (define_split | |
6327 | [(set (match_operand:DI 0 "s_operand" "") | |
6328 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6329 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6330 | "reload_completed" |
6331 | [(parallel | |
6332 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6333 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6334 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6335 | |
1a2e356e RH |
6336 | ;; These two are what combine generates for (ashift (zero_extract)). |
6337 | (define_insn "*extzv_<mode>_srl" | |
6338 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6339 | (and:GPR (lshiftrt:GPR | |
6340 | (match_operand:GPR 1 "register_operand" "d") | |
6341 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6342 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6343 | (clobber (reg:CC CC_REGNUM))] | |
6344 | "TARGET_Z10 | |
6345 | /* Note that even for the SImode pattern, the rotate is always DImode. */ | |
6346 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
6347 | INTVAL (operands[3]))" | |
6348 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" | |
6349 | [(set_attr "op_type" "RIE") | |
6350 | (set_attr "z10prop" "z10_super_E1")]) | |
6351 | ||
6352 | (define_insn "*extzv_<mode>_sll" | |
6353 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6354 | (and:GPR (ashift:GPR | |
6355 | (match_operand:GPR 1 "register_operand" "d") | |
6356 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6357 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6358 | (clobber (reg:CC CC_REGNUM))] | |
6359 | "TARGET_Z10 | |
6360 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), | |
6361 | INTVAL (operands[3]))" | |
6362 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" | |
6363 | [(set_attr "op_type" "RIE") | |
6364 | (set_attr "z10prop" "z10_super_E1")]) | |
6365 | ||
9db1d521 HP |
6366 | |
6367 | ; | |
6368 | ; andsi3 instruction pattern(s). | |
6369 | ; | |
6370 | ||
6371 | (define_insn "*andsi3_cc" | |
ae156f85 | 6372 | [(set (reg CC_REGNUM) |
e3140518 RH |
6373 | (compare |
6374 | (and:SI | |
6375 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6376 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6377 | (const_int 0))) | |
6378 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
6379 | (and:SI (match_dup 1) (match_dup 2)))] |
6380 | "s390_match_ccmode(insn, CCTmode)" | |
6381 | "@ | |
ec24698e | 6382 | nilf\t%0,%o2 |
d40c829f | 6383 | nr\t%0,%2 |
65b1d8ea | 6384 | nrk\t%0,%1,%2 |
d40c829f | 6385 | n\t%0,%2 |
e3140518 RH |
6386 | ny\t%0,%2 |
6387 | risbg\t%0,%1,%t2,128+%f2,0" | |
6388 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6389 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
6390 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6391 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6392 | |
6393 | (define_insn "*andsi3_cconly" | |
ae156f85 | 6394 | [(set (reg CC_REGNUM) |
e3140518 RH |
6395 | (compare |
6396 | (and:SI | |
6397 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6398 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6399 | (const_int 0))) | |
6400 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
6401 | "s390_match_ccmode(insn, CCTmode) |
6402 | /* Do not steal TM patterns. */ | |
6403 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 6404 | "@ |
ec24698e | 6405 | nilf\t%0,%o2 |
d40c829f | 6406 | nr\t%0,%2 |
65b1d8ea | 6407 | nrk\t%0,%1,%2 |
d40c829f | 6408 | n\t%0,%2 |
e3140518 RH |
6409 | ny\t%0,%2 |
6410 | risbg\t%0,%1,%t2,128+%f2,0" | |
6411 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6412 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
65b1d8ea | 6413 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 6414 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6415 | |
f19a9af7 | 6416 | (define_insn "*andsi3_zarch" |
65b1d8ea | 6417 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 6418 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 6419 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 6420 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 6421 | (match_operand:SI 2 "general_operand" |
e3140518 | 6422 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q"))) |
ae156f85 | 6423 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6424 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6425 | "@ |
f19a9af7 AK |
6426 | # |
6427 | # | |
6428 | nilh\t%0,%j2 | |
2f7e5a0d | 6429 | nill\t%0,%j2 |
ec24698e | 6430 | nilf\t%0,%o2 |
d40c829f | 6431 | nr\t%0,%2 |
65b1d8ea | 6432 | nrk\t%0,%1,%2 |
d40c829f | 6433 | n\t%0,%2 |
8cb66696 | 6434 | ny\t%0,%2 |
e3140518 | 6435 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 6436 | # |
19b63d8e | 6437 | #" |
e3140518 RH |
6438 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
6439 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") | |
9381e3f1 WG |
6440 | (set_attr "z10prop" "*, |
6441 | *, | |
6442 | z10_super_E1, | |
6443 | z10_super_E1, | |
6444 | z10_super_E1, | |
6445 | z10_super_E1, | |
65b1d8ea | 6446 | *, |
9381e3f1 WG |
6447 | z10_super_E1, |
6448 | z10_super_E1, | |
e3140518 | 6449 | z10_super_E1, |
9381e3f1 WG |
6450 | *, |
6451 | *")]) | |
f19a9af7 AK |
6452 | |
6453 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
6454 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
6455 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
6456 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 6457 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6458 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6459 | "@ |
6460 | nr\t%0,%2 | |
8cb66696 | 6461 | n\t%0,%2 |
0dfa6c5e | 6462 | # |
19b63d8e | 6463 | #" |
9381e3f1 WG |
6464 | [(set_attr "op_type" "RR,RX,SI,SS") |
6465 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6466 | ||
0dfa6c5e UW |
6467 | |
6468 | (define_split | |
6469 | [(set (match_operand:SI 0 "s_operand" "") | |
6470 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6471 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6472 | "reload_completed" |
6473 | [(parallel | |
6474 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6475 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6476 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6477 | |
9db1d521 HP |
6478 | ; |
6479 | ; andhi3 instruction pattern(s). | |
6480 | ; | |
6481 | ||
8cb66696 | 6482 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
6483 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6484 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6485 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 6486 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6487 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6488 | "@ |
d40c829f | 6489 | nr\t%0,%2 |
65b1d8ea | 6490 | nrk\t%0,%1,%2 |
8cb66696 | 6491 | nill\t%0,%x2 |
0dfa6c5e | 6492 | # |
19b63d8e | 6493 | #" |
65b1d8ea AK |
6494 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6495 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6496 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 6497 | ]) |
8cb66696 UW |
6498 | |
6499 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
6500 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6501 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6502 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 6503 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6504 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6505 | "@ | |
6506 | nr\t%0,%2 | |
0dfa6c5e | 6507 | # |
19b63d8e | 6508 | #" |
9381e3f1 WG |
6509 | [(set_attr "op_type" "RR,SI,SS") |
6510 | (set_attr "z10prop" "z10_super_E1,*,*") | |
6511 | ]) | |
0dfa6c5e UW |
6512 | |
6513 | (define_split | |
6514 | [(set (match_operand:HI 0 "s_operand" "") | |
6515 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6516 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6517 | "reload_completed" |
6518 | [(parallel | |
6519 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6520 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6521 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 6522 | |
9db1d521 HP |
6523 | ; |
6524 | ; andqi3 instruction pattern(s). | |
6525 | ; | |
6526 | ||
8cb66696 | 6527 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
6528 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6529 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6530 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6531 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6532 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6533 | "@ |
d40c829f | 6534 | nr\t%0,%2 |
65b1d8ea | 6535 | nrk\t%0,%1,%2 |
8cb66696 | 6536 | nill\t%0,%b2 |
fc0ea003 UW |
6537 | ni\t%S0,%b2 |
6538 | niy\t%S0,%b2 | |
19b63d8e | 6539 | #" |
65b1d8ea AK |
6540 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6541 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6542 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
6543 | |
6544 | (define_insn "*andqi3_esa" | |
6545 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6546 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6547 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6548 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6549 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6550 | "@ |
8cb66696 | 6551 | nr\t%0,%2 |
fc0ea003 | 6552 | ni\t%S0,%b2 |
19b63d8e | 6553 | #" |
9381e3f1 WG |
6554 | [(set_attr "op_type" "RR,SI,SS") |
6555 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 6556 | |
19b63d8e UW |
6557 | ; |
6558 | ; Block and (NC) patterns. | |
6559 | ; | |
6560 | ||
6561 | (define_insn "*nc" | |
6562 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6563 | (and:BLK (match_dup 0) | |
6564 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6565 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6566 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6567 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6568 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6569 | [(set_attr "op_type" "SS") |
6570 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6571 | |
6572 | (define_split | |
6573 | [(set (match_operand 0 "memory_operand" "") | |
6574 | (and (match_dup 0) | |
6575 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6576 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6577 | "reload_completed |
6578 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6579 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6580 | [(parallel | |
6581 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
6582 | (use (match_dup 2)) | |
ae156f85 | 6583 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6584 | { |
6585 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6586 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6587 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6588 | }) | |
6589 | ||
6590 | (define_peephole2 | |
6591 | [(parallel | |
6592 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6593 | (and:BLK (match_dup 0) | |
6594 | (match_operand:BLK 1 "memory_operand" ""))) | |
6595 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6596 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6597 | (parallel |
6598 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6599 | (and:BLK (match_dup 3) | |
6600 | (match_operand:BLK 4 "memory_operand" ""))) | |
6601 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6602 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6603 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6604 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6605 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6606 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6607 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6608 | [(parallel | |
6609 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
6610 | (use (match_dup 8)) | |
ae156f85 | 6611 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6612 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6613 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6614 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6615 | ||
9db1d521 HP |
6616 | |
6617 | ;; | |
6618 | ;;- Bit set (inclusive or) instructions. | |
6619 | ;; | |
6620 | ||
047d35ed AS |
6621 | (define_expand "ior<mode>3" |
6622 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6623 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6624 | (match_operand:INT 2 "general_operand" ""))) | |
6625 | (clobber (reg:CC CC_REGNUM))] | |
6626 | "" | |
6627 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
6628 | ||
9db1d521 HP |
6629 | ; |
6630 | ; iordi3 instruction pattern(s). | |
6631 | ; | |
6632 | ||
4023fb28 | 6633 | (define_insn "*iordi3_cc" |
ae156f85 | 6634 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6635 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6636 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6637 | (const_int 0))) |
65b1d8ea | 6638 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6639 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6640 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6641 | "@ |
d40c829f | 6642 | ogr\t%0,%2 |
65b1d8ea | 6643 | ogrk\t%0,%1,%2 |
d40c829f | 6644 | og\t%0,%2" |
65b1d8ea AK |
6645 | [(set_attr "op_type" "RRE,RRF,RXY") |
6646 | (set_attr "cpu_facility" "*,z196,*") | |
6647 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
6648 | |
6649 | (define_insn "*iordi3_cconly" | |
ae156f85 | 6650 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6651 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
6652 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6653 | (const_int 0))) |
65b1d8ea | 6654 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 6655 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6656 | "@ |
d40c829f | 6657 | ogr\t%0,%2 |
65b1d8ea | 6658 | ogrk\t%0,%1,%2 |
d40c829f | 6659 | og\t%0,%2" |
65b1d8ea AK |
6660 | [(set_attr "op_type" "RRE,RRF,RXY") |
6661 | (set_attr "cpu_facility" "*,z196,*") | |
6662 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6663 | |
3af8e996 | 6664 | (define_insn "*iordi3" |
65b1d8ea AK |
6665 | [(set (match_operand:DI 0 "nonimmediate_operand" |
6666 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
6667 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
6668 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 6669 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 6670 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 6671 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6672 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6673 | "@ |
6674 | oihh\t%0,%i2 | |
6675 | oihl\t%0,%i2 | |
6676 | oilh\t%0,%i2 | |
6677 | oill\t%0,%i2 | |
6678 | oihf\t%0,%k2 | |
6679 | oilf\t%0,%k2 | |
6680 | ogr\t%0,%2 | |
65b1d8ea | 6681 | ogrk\t%0,%1,%2 |
ec24698e UW |
6682 | og\t%0,%2 |
6683 | # | |
6684 | #" | |
65b1d8ea AK |
6685 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
6686 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
6687 | (set_attr "z10prop" "z10_super_E1, |
6688 | z10_super_E1, | |
6689 | z10_super_E1, | |
6690 | z10_super_E1, | |
6691 | z10_super_E1, | |
6692 | z10_super_E1, | |
6693 | z10_super_E1, | |
65b1d8ea | 6694 | *, |
9381e3f1 WG |
6695 | z10_super_E1, |
6696 | *, | |
6697 | *")]) | |
0dfa6c5e UW |
6698 | |
6699 | (define_split | |
6700 | [(set (match_operand:DI 0 "s_operand" "") | |
6701 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6702 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6703 | "reload_completed" |
6704 | [(parallel | |
6705 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6706 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6707 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6708 | |
9db1d521 HP |
6709 | ; |
6710 | ; iorsi3 instruction pattern(s). | |
6711 | ; | |
6712 | ||
4023fb28 | 6713 | (define_insn "*iorsi3_cc" |
ae156f85 | 6714 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6715 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6716 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6717 | (const_int 0))) |
65b1d8ea | 6718 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
6719 | (ior:SI (match_dup 1) (match_dup 2)))] |
6720 | "s390_match_ccmode(insn, CCTmode)" | |
6721 | "@ | |
ec24698e | 6722 | oilf\t%0,%o2 |
d40c829f | 6723 | or\t%0,%2 |
65b1d8ea | 6724 | ork\t%0,%1,%2 |
d40c829f UW |
6725 | o\t%0,%2 |
6726 | oy\t%0,%2" | |
65b1d8ea AK |
6727 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6728 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6729 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
6730 | |
6731 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 6732 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6733 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
6734 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 6735 | (const_int 0))) |
65b1d8ea | 6736 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
6737 | "s390_match_ccmode(insn, CCTmode)" |
6738 | "@ | |
ec24698e | 6739 | oilf\t%0,%o2 |
d40c829f | 6740 | or\t%0,%2 |
65b1d8ea | 6741 | ork\t%0,%1,%2 |
d40c829f UW |
6742 | o\t%0,%2 |
6743 | oy\t%0,%2" | |
65b1d8ea AK |
6744 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
6745 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
6746 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 6747 | |
8cb66696 | 6748 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
6749 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
6750 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
6751 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 6752 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6753 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6754 | "@ |
f19a9af7 AK |
6755 | oilh\t%0,%i2 |
6756 | oill\t%0,%i2 | |
ec24698e | 6757 | oilf\t%0,%o2 |
d40c829f | 6758 | or\t%0,%2 |
65b1d8ea | 6759 | ork\t%0,%1,%2 |
d40c829f | 6760 | o\t%0,%2 |
8cb66696 | 6761 | oy\t%0,%2 |
0dfa6c5e | 6762 | # |
19b63d8e | 6763 | #" |
65b1d8ea AK |
6764 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
6765 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
6766 | (set_attr "z10prop" "z10_super_E1, |
6767 | z10_super_E1, | |
6768 | z10_super_E1, | |
6769 | z10_super_E1, | |
65b1d8ea | 6770 | *, |
9381e3f1 WG |
6771 | z10_super_E1, |
6772 | z10_super_E1, | |
6773 | *, | |
6774 | *")]) | |
8cb66696 UW |
6775 | |
6776 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 6777 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 6778 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 6779 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 6780 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6781 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6782 | "@ |
6783 | or\t%0,%2 | |
8cb66696 | 6784 | o\t%0,%2 |
0dfa6c5e | 6785 | # |
19b63d8e | 6786 | #" |
9381e3f1 WG |
6787 | [(set_attr "op_type" "RR,RX,SI,SS") |
6788 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6789 | |
6790 | (define_split | |
6791 | [(set (match_operand:SI 0 "s_operand" "") | |
6792 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6793 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6794 | "reload_completed" |
6795 | [(parallel | |
6796 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6797 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6798 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 6799 | |
4023fb28 UW |
6800 | ; |
6801 | ; iorhi3 instruction pattern(s). | |
6802 | ; | |
6803 | ||
8cb66696 | 6804 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
6805 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
6806 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
6807 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 6808 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6809 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6810 | "@ |
d40c829f | 6811 | or\t%0,%2 |
65b1d8ea | 6812 | ork\t%0,%1,%2 |
8cb66696 | 6813 | oill\t%0,%x2 |
0dfa6c5e | 6814 | # |
19b63d8e | 6815 | #" |
65b1d8ea AK |
6816 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
6817 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
6818 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
6819 | |
6820 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
6821 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
6822 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
6823 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 6824 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
6825 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
6826 | "@ | |
6827 | or\t%0,%2 | |
0dfa6c5e | 6828 | # |
19b63d8e | 6829 | #" |
9381e3f1 WG |
6830 | [(set_attr "op_type" "RR,SI,SS") |
6831 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
6832 | |
6833 | (define_split | |
6834 | [(set (match_operand:HI 0 "s_operand" "") | |
6835 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 6836 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6837 | "reload_completed" |
6838 | [(parallel | |
6839 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6840 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6841 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 6842 | |
9db1d521 | 6843 | ; |
4023fb28 | 6844 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
6845 | ; |
6846 | ||
8cb66696 | 6847 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
6848 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
6849 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6850 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 6851 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6852 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 6853 | "@ |
d40c829f | 6854 | or\t%0,%2 |
65b1d8ea | 6855 | ork\t%0,%1,%2 |
8cb66696 | 6856 | oill\t%0,%b2 |
fc0ea003 UW |
6857 | oi\t%S0,%b2 |
6858 | oiy\t%S0,%b2 | |
19b63d8e | 6859 | #" |
65b1d8ea AK |
6860 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
6861 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
6862 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
6863 | z10_super,z10_super,*")]) | |
8cb66696 UW |
6864 | |
6865 | (define_insn "*iorqi3_esa" | |
6866 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
6867 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
6868 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 6869 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6870 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6871 | "@ |
8cb66696 | 6872 | or\t%0,%2 |
fc0ea003 | 6873 | oi\t%S0,%b2 |
19b63d8e | 6874 | #" |
9381e3f1 WG |
6875 | [(set_attr "op_type" "RR,SI,SS") |
6876 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 6877 | |
19b63d8e UW |
6878 | ; |
6879 | ; Block inclusive or (OC) patterns. | |
6880 | ; | |
6881 | ||
6882 | (define_insn "*oc" | |
6883 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6884 | (ior:BLK (match_dup 0) | |
6885 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
6886 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 6887 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 6888 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 6889 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
6890 | [(set_attr "op_type" "SS") |
6891 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
6892 | |
6893 | (define_split | |
6894 | [(set (match_operand 0 "memory_operand" "") | |
6895 | (ior (match_dup 0) | |
6896 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 6897 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
6898 | "reload_completed |
6899 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6900 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6901 | [(parallel | |
6902 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
6903 | (use (match_dup 2)) | |
ae156f85 | 6904 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6905 | { |
6906 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6907 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6908 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6909 | }) | |
6910 | ||
6911 | (define_peephole2 | |
6912 | [(parallel | |
6913 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6914 | (ior:BLK (match_dup 0) | |
6915 | (match_operand:BLK 1 "memory_operand" ""))) | |
6916 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 6917 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
6918 | (parallel |
6919 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6920 | (ior:BLK (match_dup 3) | |
6921 | (match_operand:BLK 4 "memory_operand" ""))) | |
6922 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 6923 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6924 | "s390_offset_p (operands[0], operands[3], operands[2]) |
6925 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 6926 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 6927 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
6928 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
6929 | [(parallel | |
6930 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
6931 | (use (match_dup 8)) | |
ae156f85 | 6932 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
6933 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
6934 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6935 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6936 | ||
9db1d521 HP |
6937 | |
6938 | ;; | |
6939 | ;;- Xor instructions. | |
6940 | ;; | |
6941 | ||
047d35ed AS |
6942 | (define_expand "xor<mode>3" |
6943 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6944 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6945 | (match_operand:INT 2 "general_operand" ""))) | |
6946 | (clobber (reg:CC CC_REGNUM))] | |
6947 | "" | |
6948 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
6949 | ||
9db1d521 HP |
6950 | ; |
6951 | ; xordi3 instruction pattern(s). | |
6952 | ; | |
6953 | ||
4023fb28 | 6954 | (define_insn "*xordi3_cc" |
ae156f85 | 6955 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6956 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6957 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6958 | (const_int 0))) |
65b1d8ea | 6959 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 6960 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 6961 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6962 | "@ |
d40c829f | 6963 | xgr\t%0,%2 |
65b1d8ea | 6964 | xgrk\t%0,%1,%2 |
d40c829f | 6965 | xg\t%0,%2" |
65b1d8ea | 6966 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 6967 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 6968 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
6969 | |
6970 | (define_insn "*xordi3_cconly" | |
ae156f85 | 6971 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6972 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
6973 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 6974 | (const_int 0))) |
65b1d8ea | 6975 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 6976 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 6977 | "@ |
d40c829f | 6978 | xgr\t%0,%2 |
65b1d8ea | 6979 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 6980 | xg\t%0,%2" |
65b1d8ea AK |
6981 | [(set_attr "op_type" "RRE,RRF,RXY") |
6982 | (set_attr "cpu_facility" "*,z196,*") | |
6983 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 6984 | |
3af8e996 | 6985 | (define_insn "*xordi3" |
65b1d8ea AK |
6986 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
6987 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
6988 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 6989 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6990 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6991 | "@ |
6992 | xihf\t%0,%k2 | |
6993 | xilf\t%0,%k2 | |
6994 | xgr\t%0,%2 | |
65b1d8ea | 6995 | xgrk\t%0,%1,%2 |
ec24698e UW |
6996 | xg\t%0,%2 |
6997 | # | |
6998 | #" | |
65b1d8ea AK |
6999 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
7000 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
7001 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
7002 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7003 | |
7004 | (define_split | |
7005 | [(set (match_operand:DI 0 "s_operand" "") | |
7006 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7007 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7008 | "reload_completed" |
7009 | [(parallel | |
7010 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7011 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7012 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 7013 | |
9db1d521 HP |
7014 | ; |
7015 | ; xorsi3 instruction pattern(s). | |
7016 | ; | |
7017 | ||
4023fb28 | 7018 | (define_insn "*xorsi3_cc" |
ae156f85 | 7019 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7020 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7021 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7022 | (const_int 0))) |
65b1d8ea | 7023 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7024 | (xor:SI (match_dup 1) (match_dup 2)))] |
7025 | "s390_match_ccmode(insn, CCTmode)" | |
7026 | "@ | |
ec24698e | 7027 | xilf\t%0,%o2 |
d40c829f | 7028 | xr\t%0,%2 |
65b1d8ea | 7029 | xrk\t%0,%1,%2 |
d40c829f UW |
7030 | x\t%0,%2 |
7031 | xy\t%0,%2" | |
65b1d8ea AK |
7032 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7033 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7034 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7035 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7036 | |
7037 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 7038 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7039 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7040 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7041 | (const_int 0))) |
65b1d8ea | 7042 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7043 | "s390_match_ccmode(insn, CCTmode)" |
7044 | "@ | |
ec24698e | 7045 | xilf\t%0,%o2 |
d40c829f | 7046 | xr\t%0,%2 |
65b1d8ea | 7047 | xrk\t%0,%1,%2 |
d40c829f UW |
7048 | x\t%0,%2 |
7049 | xy\t%0,%2" | |
65b1d8ea AK |
7050 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7051 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7052 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7053 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7054 | |
8cb66696 | 7055 | (define_insn "*xorsi3" |
65b1d8ea AK |
7056 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
7057 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
7058 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7059 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7060 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7061 | "@ |
ec24698e | 7062 | xilf\t%0,%o2 |
d40c829f | 7063 | xr\t%0,%2 |
65b1d8ea | 7064 | xrk\t%0,%1,%2 |
d40c829f | 7065 | x\t%0,%2 |
8cb66696 | 7066 | xy\t%0,%2 |
0dfa6c5e | 7067 | # |
19b63d8e | 7068 | #" |
65b1d8ea AK |
7069 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
7070 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
7071 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7072 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7073 | |
7074 | (define_split | |
7075 | [(set (match_operand:SI 0 "s_operand" "") | |
7076 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7077 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7078 | "reload_completed" |
7079 | [(parallel | |
7080 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7081 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7082 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 7083 | |
9db1d521 HP |
7084 | ; |
7085 | ; xorhi3 instruction pattern(s). | |
7086 | ; | |
7087 | ||
8cb66696 | 7088 | (define_insn "*xorhi3" |
65b1d8ea AK |
7089 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7090 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
7091 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 7092 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7093 | "s390_logical_operator_ok_p (operands)" |
7094 | "@ | |
ec24698e | 7095 | xilf\t%0,%x2 |
8cb66696 | 7096 | xr\t%0,%2 |
65b1d8ea | 7097 | xrk\t%0,%1,%2 |
0dfa6c5e | 7098 | # |
19b63d8e | 7099 | #" |
65b1d8ea AK |
7100 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
7101 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7102 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
7103 | |
7104 | (define_split | |
7105 | [(set (match_operand:HI 0 "s_operand" "") | |
7106 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7107 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7108 | "reload_completed" |
7109 | [(parallel | |
7110 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7111 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7112 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 7113 | |
9db1d521 HP |
7114 | ; |
7115 | ; xorqi3 instruction pattern(s). | |
7116 | ; | |
7117 | ||
8cb66696 | 7118 | (define_insn "*xorqi3" |
65b1d8ea AK |
7119 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7120 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
7121 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 7122 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7123 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7124 | "@ |
ec24698e | 7125 | xilf\t%0,%b2 |
8cb66696 | 7126 | xr\t%0,%2 |
65b1d8ea | 7127 | xrk\t%0,%1,%2 |
fc0ea003 UW |
7128 | xi\t%S0,%b2 |
7129 | xiy\t%S0,%b2 | |
19b63d8e | 7130 | #" |
65b1d8ea AK |
7131 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
7132 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
7133 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 7134 | |
4023fb28 | 7135 | |
19b63d8e UW |
7136 | ; |
7137 | ; Block exclusive or (XC) patterns. | |
7138 | ; | |
7139 | ||
7140 | (define_insn "*xc" | |
7141 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7142 | (xor:BLK (match_dup 0) | |
7143 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7144 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7145 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7146 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7147 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 7148 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
7149 | |
7150 | (define_split | |
7151 | [(set (match_operand 0 "memory_operand" "") | |
7152 | (xor (match_dup 0) | |
7153 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7154 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7155 | "reload_completed |
7156 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7157 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7158 | [(parallel | |
7159 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
7160 | (use (match_dup 2)) | |
ae156f85 | 7161 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7162 | { |
7163 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7164 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7165 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7166 | }) | |
7167 | ||
7168 | (define_peephole2 | |
7169 | [(parallel | |
7170 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7171 | (xor:BLK (match_dup 0) | |
7172 | (match_operand:BLK 1 "memory_operand" ""))) | |
7173 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7174 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7175 | (parallel |
7176 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7177 | (xor:BLK (match_dup 3) | |
7178 | (match_operand:BLK 4 "memory_operand" ""))) | |
7179 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7180 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7181 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7182 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7183 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7184 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7185 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7186 | [(parallel | |
7187 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
7188 | (use (match_dup 8)) | |
ae156f85 | 7189 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7190 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7191 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7192 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7193 | ||
7194 | ; | |
7195 | ; Block xor (XC) patterns with src == dest. | |
7196 | ; | |
7197 | ||
7198 | (define_insn "*xc_zero" | |
7199 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7200 | (const_int 0)) | |
7201 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 7202 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7203 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 7204 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
7205 | [(set_attr "op_type" "SS") |
7206 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7207 | |
7208 | (define_peephole2 | |
7209 | [(parallel | |
7210 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7211 | (const_int 0)) | |
7212 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 7213 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7214 | (parallel |
7215 | [(set (match_operand:BLK 2 "memory_operand" "") | |
7216 | (const_int 0)) | |
7217 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 7218 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7219 | "s390_offset_p (operands[0], operands[2], operands[1]) |
7220 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
7221 | [(parallel | |
7222 | [(set (match_dup 4) (const_int 0)) | |
7223 | (use (match_dup 5)) | |
ae156f85 | 7224 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7225 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7226 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
7227 | ||
9db1d521 HP |
7228 | |
7229 | ;; | |
7230 | ;;- Negate instructions. | |
7231 | ;; | |
7232 | ||
7233 | ; | |
9a91a21f | 7234 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
7235 | ; |
7236 | ||
9a91a21f | 7237 | (define_expand "neg<mode>2" |
9db1d521 | 7238 | [(parallel |
9a91a21f AS |
7239 | [(set (match_operand:DSI 0 "register_operand" "=d") |
7240 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 7241 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7242 | "" |
7243 | "") | |
7244 | ||
26a89301 | 7245 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 7246 | [(set (reg CC_REGNUM) |
26a89301 UW |
7247 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7248 | (match_operand:SI 1 "register_operand" "d") 0) | |
7249 | (const_int 32)) (const_int 32))) | |
7250 | (const_int 0))) | |
7251 | (set (match_operand:DI 0 "register_operand" "=d") | |
7252 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7253 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7254 | "lcgfr\t%0,%1" |
729e750f WG |
7255 | [(set_attr "op_type" "RRE") |
7256 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7257 | |
26a89301 UW |
7258 | (define_insn "*negdi2_sign" |
7259 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7260 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7261 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7262 | "TARGET_ZARCH" |
26a89301 | 7263 | "lcgfr\t%0,%1" |
729e750f WG |
7264 | [(set_attr "op_type" "RRE") |
7265 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7266 | |
43a09b63 | 7267 | ; lcr, lcgr |
9a91a21f | 7268 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7269 | [(set (reg CC_REGNUM) |
9a91a21f | 7270 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7271 | (const_int 0))) |
9a91a21f AS |
7272 | (set (match_operand:GPR 0 "register_operand" "=d") |
7273 | (neg:GPR (match_dup 1)))] | |
7274 | "s390_match_ccmode (insn, CCAmode)" | |
7275 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7276 | [(set_attr "op_type" "RR<E>") |
7277 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7278 | |
7279 | ; lcr, lcgr | |
9a91a21f | 7280 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7281 | [(set (reg CC_REGNUM) |
9a91a21f | 7282 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7283 | (const_int 0))) |
9a91a21f AS |
7284 | (clobber (match_scratch:GPR 0 "=d"))] |
7285 | "s390_match_ccmode (insn, CCAmode)" | |
7286 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7287 | [(set_attr "op_type" "RR<E>") |
7288 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7289 | |
7290 | ; lcr, lcgr | |
9a91a21f AS |
7291 | (define_insn "*neg<mode>2" |
7292 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7293 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7294 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
7295 | "" |
7296 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7297 | [(set_attr "op_type" "RR<E>") |
7298 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 7299 | |
26a89301 | 7300 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
7301 | [(set (match_operand:DI 0 "register_operand" "=d") |
7302 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 7303 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7304 | "!TARGET_ZARCH" |
26a89301 UW |
7305 | "#" |
7306 | "&& reload_completed" | |
7307 | [(parallel | |
7308 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 7309 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 7310 | (parallel |
ae156f85 | 7311 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
7312 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
7313 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
7314 | (set (pc) | |
ae156f85 | 7315 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
7316 | (pc) |
7317 | (label_ref (match_dup 6)))) | |
7318 | (parallel | |
7319 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 7320 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
7321 | (match_dup 6)] |
7322 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7323 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7324 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7325 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7326 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 7327 | |
9db1d521 | 7328 | ; |
f5905b37 | 7329 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7330 | ; |
7331 | ||
f5905b37 | 7332 | (define_expand "neg<mode>2" |
9db1d521 | 7333 | [(parallel |
7b6baae1 AK |
7334 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7335 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7336 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7337 | "TARGET_HARD_FLOAT" |
7338 | "") | |
7339 | ||
43a09b63 | 7340 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7341 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7342 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7343 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7344 | (match_operand:BFP 2 "const0_operand" ""))) | |
7345 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7346 | (neg:BFP (match_dup 1)))] | |
142cd70f | 7347 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7348 | "lc<xde>br\t%0,%1" |
26a89301 | 7349 | [(set_attr "op_type" "RRE") |
f5905b37 | 7350 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7351 | |
7352 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 7353 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7354 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7355 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7356 | (match_operand:BFP 2 "const0_operand" ""))) | |
7357 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7358 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7359 | "lc<xde>br\t%0,%1" |
26a89301 | 7360 | [(set_attr "op_type" "RRE") |
f5905b37 | 7361 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7362 | |
85dae55a AK |
7363 | ; lcdfr |
7364 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
7365 | [(set (match_operand:FP 0 "register_operand" "=f") |
7366 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7367 | "TARGET_DFP" |
85dae55a AK |
7368 | "lcdfr\t%0,%1" |
7369 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7370 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7371 | |
43a09b63 | 7372 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7373 | (define_insn "*neg<mode>2" |
7b6baae1 AK |
7374 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7375 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7376 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7377 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7378 | "lc<xde>br\t%0,%1" |
077dab3b | 7379 | [(set_attr "op_type" "RRE") |
f5905b37 | 7380 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7381 | |
9db1d521 HP |
7382 | |
7383 | ;; | |
7384 | ;;- Absolute value instructions. | |
7385 | ;; | |
7386 | ||
7387 | ; | |
9a91a21f | 7388 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
7389 | ; |
7390 | ||
26a89301 | 7391 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 7392 | [(set (reg CC_REGNUM) |
26a89301 UW |
7393 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7394 | (match_operand:SI 1 "register_operand" "d") 0) | |
7395 | (const_int 32)) (const_int 32))) | |
7396 | (const_int 0))) | |
7397 | (set (match_operand:DI 0 "register_operand" "=d") | |
7398 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7399 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7400 | "lpgfr\t%0,%1" |
729e750f WG |
7401 | [(set_attr "op_type" "RRE") |
7402 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
7403 | |
7404 | (define_insn "*absdi2_sign" | |
7405 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7406 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7407 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7408 | "TARGET_ZARCH" |
26a89301 | 7409 | "lpgfr\t%0,%1" |
729e750f WG |
7410 | [(set_attr "op_type" "RRE") |
7411 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7412 | |
43a09b63 | 7413 | ; lpr, lpgr |
9a91a21f | 7414 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7415 | [(set (reg CC_REGNUM) |
9a91a21f | 7416 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 7417 | (const_int 0))) |
9a91a21f AS |
7418 | (set (match_operand:GPR 0 "register_operand" "=d") |
7419 | (abs:GPR (match_dup 1)))] | |
26a89301 | 7420 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7421 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7422 | [(set_attr "op_type" "RR<E>") |
7423 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 7424 | |
9381e3f1 | 7425 | ; lpr, lpgr |
9a91a21f | 7426 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7427 | [(set (reg CC_REGNUM) |
9a91a21f | 7428 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7429 | (const_int 0))) |
9a91a21f | 7430 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7431 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7432 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7433 | [(set_attr "op_type" "RR<E>") |
7434 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7435 | |
7436 | ; lpr, lpgr | |
9a91a21f AS |
7437 | (define_insn "abs<mode>2" |
7438 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7439 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7440 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 7441 | "" |
9a91a21f | 7442 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
7443 | [(set_attr "op_type" "RR<E>") |
7444 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 7445 | |
9db1d521 | 7446 | ; |
f5905b37 | 7447 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7448 | ; |
7449 | ||
f5905b37 | 7450 | (define_expand "abs<mode>2" |
9db1d521 | 7451 | [(parallel |
7b6baae1 AK |
7452 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7453 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7454 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7455 | "TARGET_HARD_FLOAT" |
7456 | "") | |
7457 | ||
43a09b63 | 7458 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7459 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7460 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7461 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7462 | (match_operand:BFP 2 "const0_operand" ""))) | |
7463 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7464 | (abs:BFP (match_dup 1)))] | |
142cd70f | 7465 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7466 | "lp<xde>br\t%0,%1" |
26a89301 | 7467 | [(set_attr "op_type" "RRE") |
f5905b37 | 7468 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7469 | |
7470 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 7471 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 7472 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7473 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
7474 | (match_operand:BFP 2 "const0_operand" ""))) | |
7475 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7476 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7477 | "lp<xde>br\t%0,%1" |
26a89301 | 7478 | [(set_attr "op_type" "RRE") |
f5905b37 | 7479 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7480 | |
85dae55a AK |
7481 | ; lpdfr |
7482 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
7483 | [(set (match_operand:FP 0 "register_operand" "=f") |
7484 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7485 | "TARGET_DFP" |
85dae55a AK |
7486 | "lpdfr\t%0,%1" |
7487 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7488 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7489 | |
43a09b63 | 7490 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 7491 | (define_insn "*abs<mode>2" |
7b6baae1 AK |
7492 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7493 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7494 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7495 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7496 | "lp<xde>br\t%0,%1" |
077dab3b | 7497 | [(set_attr "op_type" "RRE") |
f5905b37 | 7498 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 7499 | |
9db1d521 | 7500 | |
3ef093a8 AK |
7501 | ;; |
7502 | ;;- Negated absolute value instructions | |
7503 | ;; | |
7504 | ||
7505 | ; | |
7506 | ; Integer | |
7507 | ; | |
7508 | ||
26a89301 | 7509 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 7510 | [(set (reg CC_REGNUM) |
26a89301 UW |
7511 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7512 | (match_operand:SI 1 "register_operand" "d") 0) | |
7513 | (const_int 32)) (const_int 32)))) | |
7514 | (const_int 0))) | |
7515 | (set (match_operand:DI 0 "register_operand" "=d") | |
7516 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 7517 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7518 | "lngfr\t%0,%1" |
729e750f WG |
7519 | [(set_attr "op_type" "RRE") |
7520 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7521 | |
26a89301 UW |
7522 | (define_insn "*negabsdi2_sign" |
7523 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7524 | (neg:DI (abs:DI (sign_extend:DI | |
7525 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 7526 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7527 | "TARGET_ZARCH" |
26a89301 | 7528 | "lngfr\t%0,%1" |
729e750f WG |
7529 | [(set_attr "op_type" "RRE") |
7530 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 7531 | |
43a09b63 | 7532 | ; lnr, lngr |
9a91a21f | 7533 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7534 | [(set (reg CC_REGNUM) |
9a91a21f | 7535 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7536 | (const_int 0))) |
9a91a21f AS |
7537 | (set (match_operand:GPR 0 "register_operand" "=d") |
7538 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 7539 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7540 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7541 | [(set_attr "op_type" "RR<E>") |
7542 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7543 | |
7544 | ; lnr, lngr | |
9a91a21f | 7545 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7546 | [(set (reg CC_REGNUM) |
9a91a21f | 7547 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 7548 | (const_int 0))) |
9a91a21f | 7549 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 7550 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 7551 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7552 | [(set_attr "op_type" "RR<E>") |
7553 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
7554 | |
7555 | ; lnr, lngr | |
9a91a21f AS |
7556 | (define_insn "*negabs<mode>2" |
7557 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7558 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 7559 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 7560 | "" |
9a91a21f | 7561 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
7562 | [(set_attr "op_type" "RR<E>") |
7563 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7564 | |
3ef093a8 AK |
7565 | ; |
7566 | ; Floating point | |
7567 | ; | |
7568 | ||
43a09b63 | 7569 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7570 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 7571 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7572 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7573 | (match_operand:BFP 2 "const0_operand" ""))) | |
7574 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7575 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 7576 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7577 | "ln<xde>br\t%0,%1" |
26a89301 | 7578 | [(set_attr "op_type" "RRE") |
f5905b37 | 7579 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7580 | |
7581 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 7582 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 7583 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7584 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
7585 | (match_operand:BFP 2 "const0_operand" ""))) | |
7586 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7587 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7588 | "ln<xde>br\t%0,%1" |
26a89301 | 7589 | [(set_attr "op_type" "RRE") |
f5905b37 | 7590 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7591 | |
85dae55a AK |
7592 | ; lndfr |
7593 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
7594 | [(set (match_operand:FP 0 "register_operand" "=f") |
7595 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 7596 | "TARGET_DFP" |
85dae55a AK |
7597 | "lndfr\t%0,%1" |
7598 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7599 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7600 | |
43a09b63 | 7601 | ; lnxbr, lndbr, lnebr |
f5905b37 | 7602 | (define_insn "*negabs<mode>2" |
7b6baae1 AK |
7603 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7604 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f")))) | |
ae156f85 | 7605 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7606 | "TARGET_HARD_FLOAT" |
f61a2c7d | 7607 | "ln<xde>br\t%0,%1" |
26a89301 | 7608 | [(set_attr "op_type" "RRE") |
f5905b37 | 7609 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 7610 | |
4023fb28 UW |
7611 | ;; |
7612 | ;;- Square root instructions. | |
7613 | ;; | |
7614 | ||
7615 | ; | |
f5905b37 | 7616 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
7617 | ; |
7618 | ||
9381e3f1 | 7619 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 7620 | (define_insn "sqrt<mode>2" |
7b6baae1 AK |
7621 | [(set (match_operand:BFP 0 "register_operand" "=f,f") |
7622 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 7623 | "TARGET_HARD_FLOAT" |
4023fb28 | 7624 | "@ |
f61a2c7d AK |
7625 | sq<xde>br\t%0,%1 |
7626 | sq<xde>b\t%0,%1" | |
a036c6f7 | 7627 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 7628 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 7629 | |
9db1d521 HP |
7630 | |
7631 | ;; | |
7632 | ;;- One complement instructions. | |
7633 | ;; | |
7634 | ||
7635 | ; | |
342cf42b | 7636 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 7637 | ; |
c7453384 | 7638 | |
342cf42b | 7639 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 7640 | [(parallel |
342cf42b AS |
7641 | [(set (match_operand:INT 0 "register_operand" "") |
7642 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
7643 | (const_int -1))) | |
ae156f85 | 7644 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 7645 | "" |
4023fb28 | 7646 | "") |
9db1d521 HP |
7647 | |
7648 | ||
ec24698e UW |
7649 | ;; |
7650 | ;; Find leftmost bit instructions. | |
7651 | ;; | |
7652 | ||
7653 | (define_expand "clzdi2" | |
7654 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7655 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 7656 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7657 | { |
7658 | rtx insn, clz_equal; | |
7659 | rtx wide_reg = gen_reg_rtx (TImode); | |
7660 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
7661 | ||
7662 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
7663 | ||
7664 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
7665 | ||
9381e3f1 | 7666 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 7667 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
7668 | |
7669 | DONE; | |
7670 | }) | |
7671 | ||
7672 | (define_insn "clztidi2" | |
7673 | [(set (match_operand:TI 0 "register_operand" "=d") | |
7674 | (ior:TI | |
9381e3f1 WG |
7675 | (ashift:TI |
7676 | (zero_extend:TI | |
ec24698e UW |
7677 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
7678 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
7679 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 7680 | |
ec24698e UW |
7681 | (const_int 64)) |
7682 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
7683 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 7684 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 7685 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 7686 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
7687 | "flogr\t%0,%1" |
7688 | [(set_attr "op_type" "RRE")]) | |
7689 | ||
7690 | ||
9db1d521 HP |
7691 | ;; |
7692 | ;;- Rotate instructions. | |
7693 | ;; | |
7694 | ||
7695 | ; | |
9a91a21f | 7696 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
7697 | ; |
7698 | ||
43a09b63 | 7699 | ; rll, rllg |
9a91a21f AS |
7700 | (define_insn "rotl<mode>3" |
7701 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7702 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 7703 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 7704 | "TARGET_CPU_ZARCH" |
9a91a21f | 7705 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 7706 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
7707 | (set_attr "atype" "reg") |
7708 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 7709 | |
43a09b63 | 7710 | ; rll, rllg |
4989e88a AK |
7711 | (define_insn "*rotl<mode>3_and" |
7712 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7713 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
7714 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7715 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
7716 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
7717 | "rll<g>\t%0,%1,%Y2" | |
7718 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
7719 | (set_attr "atype" "reg") |
7720 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 7721 | |
9db1d521 HP |
7722 | |
7723 | ;; | |
f337b930 | 7724 | ;;- Shift instructions. |
9db1d521 | 7725 | ;; |
9db1d521 HP |
7726 | |
7727 | ; | |
1b48c8cc | 7728 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 7729 | ; Left shifts and logical right shifts |
9db1d521 | 7730 | |
1b48c8cc AS |
7731 | (define_expand "<shift><mode>3" |
7732 | [(set (match_operand:DSI 0 "register_operand" "") | |
7733 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
7734 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
7735 | "" |
7736 | "") | |
7737 | ||
43a09b63 | 7738 | ; sldl, srdl |
f337b930 | 7739 | (define_insn "*<shift>di3_31" |
ac32b25e | 7740 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 7741 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7742 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9602b6a1 | 7743 | "!TARGET_ZARCH" |
f337b930 | 7744 | "s<lr>dl\t%0,%Y2" |
077dab3b | 7745 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
7746 | (set_attr "atype" "reg") |
7747 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 7748 | |
65b1d8ea | 7749 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7750 | (define_insn "*<shift><mode>3" |
65b1d8ea AK |
7751 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7752 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7753 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] | |
1b48c8cc | 7754 | "" |
65b1d8ea AK |
7755 | "@ |
7756 | s<lr>l<g>\t%0,<1>%Y2 | |
7757 | s<lr>l<gk>\t%0,%1,%Y2" | |
7758 | [(set_attr "op_type" "RS<E>,RSY") | |
7759 | (set_attr "atype" "reg,reg") | |
7760 | (set_attr "cpu_facility" "*,z196") | |
7761 | (set_attr "z10prop" "z10_super_E1,*")]) | |
9db1d521 | 7762 | |
43a09b63 | 7763 | ; sldl, srdl |
4989e88a AK |
7764 | (define_insn "*<shift>di3_31_and" |
7765 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7766 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
7767 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7768 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
9602b6a1 | 7769 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7770 | "s<lr>dl\t%0,%Y2" |
7771 | [(set_attr "op_type" "RS") | |
7772 | (set_attr "atype" "reg")]) | |
7773 | ||
65b1d8ea | 7774 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 7775 | (define_insn "*<shift><mode>3_and" |
65b1d8ea AK |
7776 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7777 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7778 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7779 | (match_operand:SI 3 "const_int_operand" "n,n"))))] | |
1b48c8cc | 7780 | "(INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7781 | "@ |
7782 | s<lr>l<g>\t%0,<1>%Y2 | |
7783 | s<lr>l<gk>\t%0,%1,%Y2" | |
7784 | [(set_attr "op_type" "RS<E>,RSY") | |
7785 | (set_attr "atype" "reg,reg") | |
7786 | (set_attr "cpu_facility" "*,z196") | |
7787 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7788 | |
9db1d521 | 7789 | ; |
1b48c8cc | 7790 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 7791 | ; Arithmetic right shifts |
9db1d521 | 7792 | |
1b48c8cc | 7793 | (define_expand "ashr<mode>3" |
9db1d521 | 7794 | [(parallel |
1b48c8cc AS |
7795 | [(set (match_operand:DSI 0 "register_operand" "") |
7796 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
7797 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 7798 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7799 | "" |
7800 | "") | |
7801 | ||
ecbe845e | 7802 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 7803 | [(set (reg CC_REGNUM) |
ac32b25e | 7804 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7805 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7806 | (const_int 0))) |
ac32b25e | 7807 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e | 7808 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7809 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7810 | "srda\t%0,%Y2" |
077dab3b HP |
7811 | [(set_attr "op_type" "RS") |
7812 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
7813 | |
7814 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 7815 | [(set (reg CC_REGNUM) |
ac32b25e | 7816 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 7817 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 7818 | (const_int 0))) |
ac32b25e | 7819 | (clobber (match_scratch:DI 0 "=d"))] |
9602b6a1 | 7820 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 7821 | "srda\t%0,%Y2" |
077dab3b HP |
7822 | [(set_attr "op_type" "RS") |
7823 | (set_attr "atype" "reg")]) | |
ecbe845e | 7824 | |
9db1d521 | 7825 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
7826 | [(set (match_operand:DI 0 "register_operand" "=d") |
7827 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 7828 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 7829 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7830 | "!TARGET_ZARCH" |
ac32b25e | 7831 | "srda\t%0,%Y2" |
077dab3b HP |
7832 | [(set_attr "op_type" "RS") |
7833 | (set_attr "atype" "reg")]) | |
c7453384 | 7834 | |
65b1d8ea | 7835 | ; sra, srag, srak |
1b48c8cc | 7836 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 7837 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7838 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7839 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7840 | (const_int 0))) |
65b1d8ea | 7841 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc AS |
7842 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] |
7843 | "s390_match_ccmode(insn, CCSmode)" | |
65b1d8ea AK |
7844 | "@ |
7845 | sra<g>\t%0,<1>%Y2 | |
7846 | sra<gk>\t%0,%1,%Y2" | |
7847 | [(set_attr "op_type" "RS<E>,RSY") | |
7848 | (set_attr "atype" "reg,reg") | |
7849 | (set_attr "cpu_facility" "*,z196") | |
7850 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7851 | |
65b1d8ea | 7852 | ; sra, srag, srak |
1b48c8cc | 7853 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 7854 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7855 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7856 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 7857 | (const_int 0))) |
65b1d8ea | 7858 | (clobber (match_scratch:GPR 0 "=d,d"))] |
1b48c8cc | 7859 | "s390_match_ccmode(insn, CCSmode)" |
65b1d8ea AK |
7860 | "@ |
7861 | sra<g>\t%0,<1>%Y2 | |
7862 | sra<gk>\t%0,%1,%Y2" | |
7863 | [(set_attr "op_type" "RS<E>,RSY") | |
7864 | (set_attr "atype" "reg,reg") | |
7865 | (set_attr "cpu_facility" "*,z196") | |
7866 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 7867 | |
43a09b63 | 7868 | ; sra, srag |
1b48c8cc | 7869 | (define_insn "*ashr<mode>3" |
65b1d8ea AK |
7870 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7871 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7872 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) | |
ae156f85 | 7873 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 7874 | "" |
65b1d8ea AK |
7875 | "@ |
7876 | sra<g>\t%0,<1>%Y2 | |
7877 | sra<gk>\t%0,%1,%Y2" | |
7878 | [(set_attr "op_type" "RS<E>,RSY") | |
7879 | (set_attr "atype" "reg,reg") | |
7880 | (set_attr "cpu_facility" "*,z196") | |
7881 | (set_attr "z10prop" "z10_super_E1,*")]) | |
077dab3b | 7882 | |
9db1d521 | 7883 | |
4989e88a AK |
7884 | ; shift pattern with implicit ANDs |
7885 | ||
7886 | (define_insn "*ashrdi3_cc_31_and" | |
7887 | [(set (reg CC_REGNUM) | |
7888 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7889 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7890 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7891 | (const_int 0))) | |
7892 | (set (match_operand:DI 0 "register_operand" "=d") | |
7893 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
9602b6a1 | 7894 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7895 | && (INTVAL (operands[3]) & 63) == 63" |
7896 | "srda\t%0,%Y2" | |
7897 | [(set_attr "op_type" "RS") | |
7898 | (set_attr "atype" "reg")]) | |
7899 | ||
7900 | (define_insn "*ashrdi3_cconly_31_and" | |
7901 | [(set (reg CC_REGNUM) | |
7902 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7903 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7904 | (match_operand:SI 3 "const_int_operand" "n"))) | |
7905 | (const_int 0))) | |
7906 | (clobber (match_scratch:DI 0 "=d"))] | |
9602b6a1 | 7907 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
7908 | && (INTVAL (operands[3]) & 63) == 63" |
7909 | "srda\t%0,%Y2" | |
7910 | [(set_attr "op_type" "RS") | |
7911 | (set_attr "atype" "reg")]) | |
7912 | ||
7913 | (define_insn "*ashrdi3_31_and" | |
7914 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7915 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
7916 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
7917 | (match_operand:SI 3 "const_int_operand" "n")))) | |
7918 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 7919 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
7920 | "srda\t%0,%Y2" |
7921 | [(set_attr "op_type" "RS") | |
7922 | (set_attr "atype" "reg")]) | |
7923 | ||
65b1d8ea | 7924 | ; sra, srag, srak |
1b48c8cc | 7925 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 7926 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7927 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7928 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7929 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7930 | (const_int 0))) |
65b1d8ea | 7931 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc | 7932 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] |
4989e88a | 7933 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7934 | "@ |
7935 | sra<g>\t%0,<1>%Y2 | |
7936 | sra<gk>\t%0,%1,%Y2" | |
7937 | [(set_attr "op_type" "RS<E>,RSY") | |
7938 | (set_attr "atype" "reg,reg") | |
7939 | (set_attr "cpu_facility" "*,z196") | |
7940 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7941 | |
65b1d8ea | 7942 | ; sra, srag, srak |
1b48c8cc | 7943 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 7944 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7945 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
7946 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7947 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 7948 | (const_int 0))) |
65b1d8ea | 7949 | (clobber (match_scratch:GPR 0 "=d,d"))] |
4989e88a | 7950 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
7951 | "@ |
7952 | sra<g>\t%0,<1>%Y2 | |
7953 | sra<gk>\t%0,%1,%Y2" | |
7954 | [(set_attr "op_type" "RS<E>,RSY") | |
7955 | (set_attr "atype" "reg,reg") | |
7956 | (set_attr "cpu_facility" "*,z196") | |
7957 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 7958 | |
65b1d8ea | 7959 | ; sra, srag, srak |
1b48c8cc | 7960 | (define_insn "*ashr<mode>3_and" |
65b1d8ea AK |
7961 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
7962 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
7963 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
7964 | (match_operand:SI 3 "const_int_operand" "n,n")))) | |
4989e88a AK |
7965 | (clobber (reg:CC CC_REGNUM))] |
7966 | "(INTVAL (operands[3]) & 63) == 63" | |
65b1d8ea AK |
7967 | "@ |
7968 | sra<g>\t%0,<1>%Y2 | |
7969 | sra<gk>\t%0,%1,%Y2" | |
7970 | [(set_attr "op_type" "RS<E>,RSY") | |
7971 | (set_attr "atype" "reg,reg") | |
01496eca | 7972 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 7973 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 7974 | |
9db1d521 | 7975 | |
9db1d521 HP |
7976 | ;; |
7977 | ;; Branch instruction patterns. | |
7978 | ;; | |
7979 | ||
f90b7a5a | 7980 | (define_expand "cbranch<mode>4" |
fa77b251 | 7981 | [(set (pc) |
f90b7a5a PB |
7982 | (if_then_else (match_operator 0 "comparison_operator" |
7983 | [(match_operand:GPR 1 "register_operand" "") | |
7984 | (match_operand:GPR 2 "general_operand" "")]) | |
7985 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 7986 | (pc)))] |
ba956982 | 7987 | "" |
f90b7a5a PB |
7988 | "s390_emit_jump (operands[3], |
7989 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
7990 | DONE;") | |
7991 | ||
7992 | (define_expand "cbranch<mode>4" | |
7993 | [(set (pc) | |
7994 | (if_then_else (match_operator 0 "comparison_operator" | |
7995 | [(match_operand:FP 1 "register_operand" "") | |
7996 | (match_operand:FP 2 "general_operand" "")]) | |
7997 | (label_ref (match_operand 3 "" "")) | |
7998 | (pc)))] | |
7999 | "TARGET_HARD_FLOAT" | |
8000 | "s390_emit_jump (operands[3], | |
8001 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8002 | DONE;") | |
8003 | ||
8004 | (define_expand "cbranchcc4" | |
8005 | [(set (pc) | |
8006 | (if_then_else (match_operator 0 "s390_eqne_operator" | |
8007 | [(match_operand 1 "cc_reg_operand" "") | |
8008 | (match_operand 2 "const0_operand" "")]) | |
8009 | (label_ref (match_operand 3 "" "")) | |
8010 | (pc)))] | |
8011 | "TARGET_HARD_FLOAT" | |
8012 | "s390_emit_jump (operands[3], | |
8013 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8014 | DONE;") | |
8015 | ||
ba956982 | 8016 | |
9db1d521 HP |
8017 | |
8018 | ;; | |
8019 | ;;- Conditional jump instructions. | |
8020 | ;; | |
8021 | ||
6590e19a UW |
8022 | (define_insn "*cjump_64" |
8023 | [(set (pc) | |
8024 | (if_then_else | |
5a3fe9b6 AK |
8025 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8026 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8027 | (label_ref (match_operand 0 "" "")) |
8028 | (pc)))] | |
8029 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8030 | { |
13e58269 | 8031 | if (get_attr_length (insn) == 4) |
d40c829f | 8032 | return "j%C1\t%l0"; |
6590e19a | 8033 | else |
d40c829f | 8034 | return "jg%C1\t%l0"; |
6590e19a UW |
8035 | } |
8036 | [(set_attr "op_type" "RI") | |
8037 | (set_attr "type" "branch") | |
8038 | (set (attr "length") | |
8039 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8040 | (const_int 4) (const_int 6)))]) | |
8041 | ||
8042 | (define_insn "*cjump_31" | |
8043 | [(set (pc) | |
8044 | (if_then_else | |
5a3fe9b6 AK |
8045 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8046 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8047 | (label_ref (match_operand 0 "" "")) |
8048 | (pc)))] | |
8049 | "!TARGET_CPU_ZARCH" | |
8050 | { | |
8d933e31 AS |
8051 | gcc_assert (get_attr_length (insn) == 4); |
8052 | return "j%C1\t%l0"; | |
10bbf137 | 8053 | } |
9db1d521 | 8054 | [(set_attr "op_type" "RI") |
077dab3b | 8055 | (set_attr "type" "branch") |
13e58269 | 8056 | (set (attr "length") |
d7f99b2c | 8057 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8058 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8059 | (const_int 4) (const_int 6)) | |
8060 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8061 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8062 | |
f314b9b1 | 8063 | (define_insn "*cjump_long" |
6590e19a UW |
8064 | [(set (pc) |
8065 | (if_then_else | |
ae156f85 | 8066 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8067 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8068 | (pc)))] |
9db1d521 | 8069 | "" |
f314b9b1 UW |
8070 | { |
8071 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8072 | return "b%C1r\t%0"; |
f314b9b1 | 8073 | else |
d40c829f | 8074 | return "b%C1\t%a0"; |
10bbf137 | 8075 | } |
c7453384 | 8076 | [(set (attr "op_type") |
f314b9b1 UW |
8077 | (if_then_else (match_operand 0 "register_operand" "") |
8078 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 8079 | (set_attr "type" "branch") |
077dab3b | 8080 | (set_attr "atype" "agen")]) |
9db1d521 HP |
8081 | |
8082 | ||
8083 | ;; | |
8084 | ;;- Negated conditional jump instructions. | |
8085 | ;; | |
8086 | ||
6590e19a UW |
8087 | (define_insn "*icjump_64" |
8088 | [(set (pc) | |
8089 | (if_then_else | |
ae156f85 | 8090 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8091 | (pc) |
8092 | (label_ref (match_operand 0 "" ""))))] | |
8093 | "TARGET_CPU_ZARCH" | |
c7453384 | 8094 | { |
13e58269 | 8095 | if (get_attr_length (insn) == 4) |
d40c829f | 8096 | return "j%D1\t%l0"; |
6590e19a | 8097 | else |
d40c829f | 8098 | return "jg%D1\t%l0"; |
6590e19a UW |
8099 | } |
8100 | [(set_attr "op_type" "RI") | |
8101 | (set_attr "type" "branch") | |
8102 | (set (attr "length") | |
8103 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8104 | (const_int 4) (const_int 6)))]) | |
8105 | ||
8106 | (define_insn "*icjump_31" | |
8107 | [(set (pc) | |
8108 | (if_then_else | |
ae156f85 | 8109 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8110 | (pc) |
8111 | (label_ref (match_operand 0 "" ""))))] | |
8112 | "!TARGET_CPU_ZARCH" | |
8113 | { | |
8d933e31 AS |
8114 | gcc_assert (get_attr_length (insn) == 4); |
8115 | return "j%D1\t%l0"; | |
10bbf137 | 8116 | } |
9db1d521 | 8117 | [(set_attr "op_type" "RI") |
077dab3b | 8118 | (set_attr "type" "branch") |
13e58269 | 8119 | (set (attr "length") |
d7f99b2c | 8120 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8121 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8122 | (const_int 4) (const_int 6)) | |
8123 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8124 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8125 | |
f314b9b1 | 8126 | (define_insn "*icjump_long" |
6590e19a UW |
8127 | [(set (pc) |
8128 | (if_then_else | |
ae156f85 | 8129 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 8130 | (pc) |
4fe6dea8 | 8131 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 8132 | "" |
f314b9b1 UW |
8133 | { |
8134 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8135 | return "b%D1r\t%0"; |
f314b9b1 | 8136 | else |
d40c829f | 8137 | return "b%D1\t%a0"; |
10bbf137 | 8138 | } |
c7453384 | 8139 | [(set (attr "op_type") |
f314b9b1 UW |
8140 | (if_then_else (match_operand 0 "register_operand" "") |
8141 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8142 | (set_attr "type" "branch") |
8143 | (set_attr "atype" "agen")]) | |
9db1d521 | 8144 | |
4456530d HP |
8145 | ;; |
8146 | ;;- Trap instructions. | |
8147 | ;; | |
8148 | ||
8149 | (define_insn "trap" | |
8150 | [(trap_if (const_int 1) (const_int 0))] | |
8151 | "" | |
d40c829f | 8152 | "j\t.+2" |
6590e19a | 8153 | [(set_attr "op_type" "RI") |
077dab3b | 8154 | (set_attr "type" "branch")]) |
4456530d | 8155 | |
f90b7a5a PB |
8156 | (define_expand "ctrap<mode>4" |
8157 | [(trap_if (match_operator 0 "comparison_operator" | |
8158 | [(match_operand:GPR 1 "register_operand" "") | |
8159 | (match_operand:GPR 2 "general_operand" "")]) | |
8160 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 8161 | "" |
f90b7a5a PB |
8162 | { |
8163 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8164 | operands[1], operands[2]); | |
8165 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8166 | DONE; | |
8167 | }) | |
8168 | ||
8169 | (define_expand "ctrap<mode>4" | |
8170 | [(trap_if (match_operator 0 "comparison_operator" | |
8171 | [(match_operand:FP 1 "register_operand" "") | |
8172 | (match_operand:FP 2 "general_operand" "")]) | |
8173 | (match_operand 3 "const0_operand" ""))] | |
8174 | "" | |
8175 | { | |
8176 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8177 | operands[1], operands[2]); | |
8178 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8179 | DONE; | |
8180 | }) | |
4456530d | 8181 | |
f90b7a5a PB |
8182 | (define_insn "condtrap" |
8183 | [(trap_if (match_operator 0 "s390_comparison" | |
8184 | [(match_operand 1 "cc_reg_operand" "c") | |
8185 | (const_int 0)]) | |
4456530d HP |
8186 | (const_int 0))] |
8187 | "" | |
d40c829f | 8188 | "j%C0\t.+2"; |
077dab3b HP |
8189 | [(set_attr "op_type" "RI") |
8190 | (set_attr "type" "branch")]) | |
9db1d521 | 8191 | |
963fc8d0 AK |
8192 | ; crt, cgrt, cit, cgit |
8193 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
8194 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
8195 | [(match_operand:GPR 1 "register_operand" "d,d") | |
8196 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
8197 | (const_int 0))] | |
8198 | "TARGET_Z10" | |
8199 | "@ | |
8200 | c<g>rt%C0\t%1,%2 | |
8201 | c<g>it%C0\t%1,%h2" | |
8202 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 8203 | (set_attr "type" "branch") |
729e750f | 8204 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 8205 | |
22ac2c2f | 8206 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
8207 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
8208 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
22ac2c2f AK |
8209 | [(match_operand:GPR 1 "register_operand" "d,d, d") |
8210 | (match_operand:GPR 2 "general_operand" "d,D,RT")]) | |
963fc8d0 AK |
8211 | (const_int 0))] |
8212 | "TARGET_Z10" | |
8213 | "@ | |
8214 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
8215 | cl<gf>it%C0\t%1,%x2 |
8216 | cl<g>t%C0\t%1,%2" | |
8217 | [(set_attr "op_type" "RRF,RIE,RSY") | |
8218 | (set_attr "type" "branch") | |
8219 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
8220 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
8221 | ||
8222 | ; lat, lgat | |
8223 | (define_insn "*load_and_trap<mode>" | |
8224 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") | |
8225 | (const_int 0)) | |
8226 | (const_int 0)) | |
8227 | (set (match_operand:GPR 1 "register_operand" "=d") | |
8228 | (match_dup 0))] | |
8229 | "TARGET_ZEC12" | |
8230 | "l<g>at\t%1,%0" | |
8231 | [(set_attr "op_type" "RXY")]) | |
8232 | ||
963fc8d0 | 8233 | |
9db1d521 | 8234 | ;; |
0a3bdf9d | 8235 | ;;- Loop instructions. |
9db1d521 | 8236 | ;; |
0a3bdf9d UW |
8237 | ;; This is all complicated by the fact that since this is a jump insn |
8238 | ;; we must handle our own output reloads. | |
c7453384 | 8239 | |
f1149235 AK |
8240 | ;; branch on index |
8241 | ||
8242 | ; This splitter will be matched by combine and has to add the 2 moves | |
8243 | ; necessary to load the compare and the increment values into a | |
8244 | ; register pair as needed by brxle. | |
8245 | ||
8246 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
8247 | [(set (pc) | |
8248 | (if_then_else | |
8249 | (match_operator 6 "s390_brx_operator" | |
8250 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
8251 | (match_operand:GPR 2 "general_operand" "")) | |
8252 | (match_operand:GPR 3 "register_operand" "")]) | |
8253 | (label_ref (match_operand 0 "" "")) | |
8254 | (pc))) | |
8255 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
8256 | (plus:GPR (match_dup 1) (match_dup 2))) | |
8257 | (clobber (match_scratch:GPR 5 ""))] | |
8258 | "TARGET_CPU_ZARCH" | |
8259 | "#" | |
8260 | "!reload_completed && !reload_in_progress" | |
8261 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
8262 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
8263 | (parallel [(set (pc) | |
8264 | (if_then_else | |
8265 | (match_op_dup 6 | |
8266 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
8267 | (match_dup 8)]) | |
8268 | (label_ref (match_dup 0)) | |
8269 | (pc))) | |
8270 | (set (match_dup 4) | |
8271 | (plus:GPR (match_dup 1) (match_dup 7))) | |
8272 | (clobber (match_dup 5)) | |
8273 | (clobber (reg:CC CC_REGNUM))])] | |
8274 | { | |
8275 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
8276 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
8277 | gen_highpart (word_mode, dreg)); | |
8278 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
8279 | gen_lowpart (word_mode, dreg)); | |
8280 | }) | |
8281 | ||
8282 | ; brxlg, brxhg | |
8283 | ||
8284 | (define_insn_and_split "*brxg_64bit" | |
8285 | [(set (pc) | |
8286 | (if_then_else | |
8287 | (match_operator 5 "s390_brx_operator" | |
8288 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
8289 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
8290 | (subreg:DI (match_dup 2) 8)]) | |
8291 | (label_ref (match_operand 0 "" "")) | |
8292 | (pc))) | |
8293 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
8294 | (plus:DI (match_dup 1) | |
8295 | (subreg:DI (match_dup 2) 0))) | |
8296 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
8297 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8298 | "TARGET_ZARCH" |
f1149235 AK |
8299 | { |
8300 | if (which_alternative != 0) | |
8301 | return "#"; | |
8302 | else if (get_attr_length (insn) == 6) | |
8303 | return "brx%E5g\t%1,%2,%l0"; | |
8304 | else | |
8305 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
8306 | } | |
8307 | "&& reload_completed | |
8308 | && (!REG_P (operands[3]) | |
8309 | || !rtx_equal_p (operands[1], operands[3]))" | |
8310 | [(set (match_dup 4) (match_dup 1)) | |
8311 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
8312 | (clobber (reg:CC CC_REGNUM))]) | |
8313 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
8314 | (set (match_dup 3) (match_dup 4)) | |
8315 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8316 | (label_ref (match_dup 0)) | |
8317 | (pc)))] | |
8318 | "" | |
8319 | [(set_attr "op_type" "RIE") | |
8320 | (set_attr "type" "branch") | |
8321 | (set (attr "length") | |
8322 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8323 | (const_int 6) (const_int 16)))]) | |
8324 | ||
8325 | ; brxle, brxh | |
8326 | ||
8327 | (define_insn_and_split "*brx_64bit" | |
8328 | [(set (pc) | |
8329 | (if_then_else | |
8330 | (match_operator 5 "s390_brx_operator" | |
8331 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8332 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
8333 | (subreg:SI (match_dup 2) 12)]) | |
8334 | (label_ref (match_operand 0 "" "")) | |
8335 | (pc))) | |
8336 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8337 | (plus:SI (match_dup 1) | |
8338 | (subreg:SI (match_dup 2) 4))) | |
8339 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8340 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8341 | "TARGET_ZARCH" |
f1149235 AK |
8342 | { |
8343 | if (which_alternative != 0) | |
8344 | return "#"; | |
8345 | else if (get_attr_length (insn) == 6) | |
8346 | return "brx%C5\t%1,%2,%l0"; | |
8347 | else | |
8348 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8349 | } | |
8350 | "&& reload_completed | |
8351 | && (!REG_P (operands[3]) | |
8352 | || !rtx_equal_p (operands[1], operands[3]))" | |
8353 | [(set (match_dup 4) (match_dup 1)) | |
8354 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8355 | (clobber (reg:CC CC_REGNUM))]) | |
8356 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
8357 | (set (match_dup 3) (match_dup 4)) | |
8358 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8359 | (label_ref (match_dup 0)) | |
8360 | (pc)))] | |
8361 | "" | |
8362 | [(set_attr "op_type" "RSI") | |
8363 | (set_attr "type" "branch") | |
8364 | (set (attr "length") | |
8365 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8366 | (const_int 6) (const_int 14)))]) | |
8367 | ||
8368 | ; brxle, brxh | |
8369 | ||
8370 | (define_insn_and_split "*brx_31bit" | |
8371 | [(set (pc) | |
8372 | (if_then_else | |
8373 | (match_operator 5 "s390_brx_operator" | |
8374 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8375 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
8376 | (subreg:SI (match_dup 2) 4)]) | |
8377 | (label_ref (match_operand 0 "" "")) | |
8378 | (pc))) | |
8379 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8380 | (plus:SI (match_dup 1) | |
8381 | (subreg:SI (match_dup 2) 0))) | |
8382 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8383 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8384 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
8385 | { |
8386 | if (which_alternative != 0) | |
8387 | return "#"; | |
8388 | else if (get_attr_length (insn) == 6) | |
8389 | return "brx%C5\t%1,%2,%l0"; | |
8390 | else | |
8391 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8392 | } | |
8393 | "&& reload_completed | |
8394 | && (!REG_P (operands[3]) | |
8395 | || !rtx_equal_p (operands[1], operands[3]))" | |
8396 | [(set (match_dup 4) (match_dup 1)) | |
8397 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
8398 | (clobber (reg:CC CC_REGNUM))]) | |
8399 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8400 | (set (match_dup 3) (match_dup 4)) | |
8401 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8402 | (label_ref (match_dup 0)) | |
8403 | (pc)))] | |
8404 | "" | |
8405 | [(set_attr "op_type" "RSI") | |
8406 | (set_attr "type" "branch") | |
8407 | (set (attr "length") | |
8408 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8409 | (const_int 6) (const_int 14)))]) | |
8410 | ||
8411 | ||
8412 | ;; branch on count | |
8413 | ||
0a3bdf9d UW |
8414 | (define_expand "doloop_end" |
8415 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 8416 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 8417 | "" |
0a3bdf9d | 8418 | { |
6590e19a | 8419 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 8420 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 8421 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 8422 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 8423 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 8424 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
8425 | else |
8426 | FAIL; | |
8427 | ||
8428 | DONE; | |
10bbf137 | 8429 | }) |
0a3bdf9d | 8430 | |
6590e19a | 8431 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
8432 | [(set (pc) |
8433 | (if_then_else | |
7e665d18 | 8434 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8435 | (const_int 1)) |
8436 | (label_ref (match_operand 0 "" "")) | |
8437 | (pc))) | |
7e665d18 | 8438 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8439 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8440 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8441 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8442 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8443 | { |
8444 | if (which_alternative != 0) | |
10bbf137 | 8445 | return "#"; |
0a3bdf9d | 8446 | else if (get_attr_length (insn) == 4) |
d40c829f | 8447 | return "brct\t%1,%l0"; |
6590e19a | 8448 | else |
545d16ff | 8449 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
8450 | } |
8451 | "&& reload_completed | |
8452 | && (! REG_P (operands[2]) | |
8453 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8454 | [(set (match_dup 3) (match_dup 1)) |
8455 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8456 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8457 | (const_int 0))) | |
8458 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8459 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8460 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8461 | (label_ref (match_dup 0)) |
8462 | (pc)))] | |
8463 | "" | |
8464 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8465 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8466 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8467 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8468 | (set_attr "type" "branch") |
8469 | (set (attr "length") | |
8470 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8471 | (const_int 4) (const_int 10)))]) | |
8472 | ||
8473 | (define_insn_and_split "doloop_si31" | |
8474 | [(set (pc) | |
8475 | (if_then_else | |
7e665d18 | 8476 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
8477 | (const_int 1)) |
8478 | (label_ref (match_operand 0 "" "")) | |
8479 | (pc))) | |
7e665d18 | 8480 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 8481 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8482 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 8483 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
8484 | "!TARGET_CPU_ZARCH" |
8485 | { | |
8486 | if (which_alternative != 0) | |
8487 | return "#"; | |
8488 | else if (get_attr_length (insn) == 4) | |
8489 | return "brct\t%1,%l0"; | |
0a3bdf9d | 8490 | else |
8d933e31 | 8491 | gcc_unreachable (); |
10bbf137 | 8492 | } |
6590e19a UW |
8493 | "&& reload_completed |
8494 | && (! REG_P (operands[2]) | |
8495 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8496 | [(set (match_dup 3) (match_dup 1)) |
8497 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
8498 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
8499 | (const_int 0))) | |
8500 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
8501 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8502 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
8503 | (label_ref (match_dup 0)) |
8504 | (pc)))] | |
8505 | "" | |
0a3bdf9d | 8506 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
8507 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8508 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8509 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 8510 | (set_attr "type" "branch") |
0a3bdf9d | 8511 | (set (attr "length") |
d7f99b2c | 8512 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8513 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8514 | (const_int 4) (const_int 6)) | |
8515 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8516 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8517 | |
0a3bdf9d UW |
8518 | (define_insn "*doloop_si_long" |
8519 | [(set (pc) | |
8520 | (if_then_else | |
7e665d18 | 8521 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 8522 | (const_int 1)) |
4fe6dea8 | 8523 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 8524 | (pc))) |
7e665d18 | 8525 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 8526 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 8527 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 8528 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 8529 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
8530 | { |
8531 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8532 | return "bctr\t%1,%0"; |
0a3bdf9d | 8533 | else |
d40c829f | 8534 | return "bct\t%1,%a0"; |
10bbf137 | 8535 | } |
c7453384 | 8536 | [(set (attr "op_type") |
0a3bdf9d UW |
8537 | (if_then_else (match_operand 0 "register_operand" "") |
8538 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8539 | (set_attr "type" "branch") |
729e750f | 8540 | (set_attr "atype" "agen") |
65b1d8ea AK |
8541 | (set_attr "z10prop" "z10_c") |
8542 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 8543 | |
6590e19a | 8544 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
8545 | [(set (pc) |
8546 | (if_then_else | |
7e665d18 | 8547 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
8548 | (const_int 1)) |
8549 | (label_ref (match_operand 0 "" "")) | |
8550 | (pc))) | |
7e665d18 | 8551 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 8552 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 8553 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 8554 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8555 | "TARGET_ZARCH" |
0a3bdf9d UW |
8556 | { |
8557 | if (which_alternative != 0) | |
10bbf137 | 8558 | return "#"; |
0a3bdf9d | 8559 | else if (get_attr_length (insn) == 4) |
d40c829f | 8560 | return "brctg\t%1,%l0"; |
0a3bdf9d | 8561 | else |
545d16ff | 8562 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 8563 | } |
6590e19a | 8564 | "&& reload_completed |
0a3bdf9d UW |
8565 | && (! REG_P (operands[2]) |
8566 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
8567 | [(set (match_dup 3) (match_dup 1)) |
8568 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
8569 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
8570 | (const_int 0))) | |
8571 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
8572 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 8573 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 8574 | (label_ref (match_dup 0)) |
0a3bdf9d | 8575 | (pc)))] |
6590e19a UW |
8576 | "" |
8577 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
8578 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
8579 | ; hurt us in the (rare) case of ahi. | |
729e750f | 8580 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
8581 | (set_attr "type" "branch") |
8582 | (set (attr "length") | |
8583 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8584 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
8585 | |
8586 | ;; | |
8587 | ;;- Unconditional jump instructions. | |
8588 | ;; | |
8589 | ||
8590 | ; | |
8591 | ; jump instruction pattern(s). | |
8592 | ; | |
8593 | ||
6590e19a UW |
8594 | (define_expand "jump" |
8595 | [(match_operand 0 "" "")] | |
9db1d521 | 8596 | "" |
6590e19a UW |
8597 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
8598 | ||
8599 | (define_insn "*jump64" | |
8600 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8601 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8602 | { |
13e58269 | 8603 | if (get_attr_length (insn) == 4) |
d40c829f | 8604 | return "j\t%l0"; |
6590e19a | 8605 | else |
d40c829f | 8606 | return "jg\t%l0"; |
6590e19a UW |
8607 | } |
8608 | [(set_attr "op_type" "RI") | |
8609 | (set_attr "type" "branch") | |
8610 | (set (attr "length") | |
8611 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8612 | (const_int 4) (const_int 6)))]) | |
8613 | ||
8614 | (define_insn "*jump31" | |
8615 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8616 | "!TARGET_CPU_ZARCH" | |
8617 | { | |
8d933e31 AS |
8618 | gcc_assert (get_attr_length (insn) == 4); |
8619 | return "j\t%l0"; | |
10bbf137 | 8620 | } |
9db1d521 | 8621 | [(set_attr "op_type" "RI") |
077dab3b | 8622 | (set_attr "type" "branch") |
13e58269 | 8623 | (set (attr "length") |
d7f99b2c | 8624 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8625 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8626 | (const_int 4) (const_int 6)) | |
8627 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8628 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
8629 | |
8630 | ; | |
8631 | ; indirect-jump instruction pattern(s). | |
8632 | ; | |
8633 | ||
8634 | (define_insn "indirect_jump" | |
4fe6dea8 | 8635 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 8636 | "" |
f314b9b1 UW |
8637 | { |
8638 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8639 | return "br\t%0"; |
f314b9b1 | 8640 | else |
d40c829f | 8641 | return "b\t%a0"; |
10bbf137 | 8642 | } |
c7453384 | 8643 | [(set (attr "op_type") |
f314b9b1 UW |
8644 | (if_then_else (match_operand 0 "register_operand" "") |
8645 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 8646 | (set_attr "type" "branch") |
729e750f | 8647 | (set_attr "atype" "agen")]) |
9db1d521 HP |
8648 | |
8649 | ; | |
f314b9b1 | 8650 | ; casesi instruction pattern(s). |
9db1d521 HP |
8651 | ; |
8652 | ||
f314b9b1 | 8653 | (define_insn "casesi_jump" |
4fe6dea8 | 8654 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 8655 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 8656 | "" |
9db1d521 | 8657 | { |
f314b9b1 | 8658 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 8659 | return "br\t%0"; |
f314b9b1 | 8660 | else |
d40c829f | 8661 | return "b\t%a0"; |
10bbf137 | 8662 | } |
c7453384 | 8663 | [(set (attr "op_type") |
f314b9b1 UW |
8664 | (if_then_else (match_operand 0 "register_operand" "") |
8665 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8666 | (set_attr "type" "branch") |
8667 | (set_attr "atype" "agen")]) | |
9db1d521 | 8668 | |
f314b9b1 UW |
8669 | (define_expand "casesi" |
8670 | [(match_operand:SI 0 "general_operand" "") | |
8671 | (match_operand:SI 1 "general_operand" "") | |
8672 | (match_operand:SI 2 "general_operand" "") | |
8673 | (label_ref (match_operand 3 "" "")) | |
8674 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 8675 | "" |
f314b9b1 UW |
8676 | { |
8677 | rtx index = gen_reg_rtx (SImode); | |
8678 | rtx base = gen_reg_rtx (Pmode); | |
8679 | rtx target = gen_reg_rtx (Pmode); | |
8680 | ||
8681 | emit_move_insn (index, operands[0]); | |
8682 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
8683 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 8684 | operands[4]); |
f314b9b1 UW |
8685 | |
8686 | if (Pmode != SImode) | |
8687 | index = convert_to_mode (Pmode, index, 1); | |
8688 | if (GET_CODE (index) != REG) | |
8689 | index = copy_to_mode_reg (Pmode, index); | |
8690 | ||
8691 | if (TARGET_64BIT) | |
8692 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
8693 | else | |
a556fd39 | 8694 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 8695 | |
f314b9b1 UW |
8696 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
8697 | ||
542a8afa | 8698 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
8699 | emit_move_insn (target, index); |
8700 | ||
8701 | if (flag_pic) | |
8702 | target = gen_rtx_PLUS (Pmode, base, target); | |
8703 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
8704 | ||
8705 | DONE; | |
10bbf137 | 8706 | }) |
9db1d521 HP |
8707 | |
8708 | ||
8709 | ;; | |
8710 | ;;- Jump to subroutine. | |
8711 | ;; | |
8712 | ;; | |
8713 | ||
8714 | ; | |
8715 | ; untyped call instruction pattern(s). | |
8716 | ; | |
8717 | ||
8718 | ;; Call subroutine returning any type. | |
8719 | (define_expand "untyped_call" | |
8720 | [(parallel [(call (match_operand 0 "" "") | |
8721 | (const_int 0)) | |
8722 | (match_operand 1 "" "") | |
8723 | (match_operand 2 "" "")])] | |
8724 | "" | |
9db1d521 HP |
8725 | { |
8726 | int i; | |
8727 | ||
8728 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
8729 | ||
8730 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
8731 | { | |
8732 | rtx set = XVECEXP (operands[2], 0, i); | |
8733 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
8734 | } | |
8735 | ||
8736 | /* The optimizer does not know that the call sets the function value | |
8737 | registers we stored in the result block. We avoid problems by | |
8738 | claiming that all hard registers are used and clobbered at this | |
8739 | point. */ | |
8740 | emit_insn (gen_blockage ()); | |
8741 | ||
8742 | DONE; | |
10bbf137 | 8743 | }) |
9db1d521 HP |
8744 | |
8745 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
8746 | ;; all of memory. This blocks insns from being moved across this point. | |
8747 | ||
8748 | (define_insn "blockage" | |
10bbf137 | 8749 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 8750 | "" |
4023fb28 | 8751 | "" |
d5869ca0 UW |
8752 | [(set_attr "type" "none") |
8753 | (set_attr "length" "0")]) | |
4023fb28 | 8754 | |
9db1d521 | 8755 | ; |
ed9676cf | 8756 | ; sibcall patterns |
9db1d521 HP |
8757 | ; |
8758 | ||
ed9676cf | 8759 | (define_expand "sibcall" |
44b8152b | 8760 | [(call (match_operand 0 "" "") |
ed9676cf | 8761 | (match_operand 1 "" ""))] |
9db1d521 | 8762 | "" |
9db1d521 | 8763 | { |
ed9676cf AK |
8764 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
8765 | DONE; | |
8766 | }) | |
9db1d521 | 8767 | |
ed9676cf | 8768 | (define_insn "*sibcall_br" |
ae156f85 | 8769 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8770 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 8771 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8772 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
8773 | "br\t%%r1" | |
8774 | [(set_attr "op_type" "RR") | |
8775 | (set_attr "type" "branch") | |
8776 | (set_attr "atype" "agen")]) | |
9db1d521 | 8777 | |
ed9676cf AK |
8778 | (define_insn "*sibcall_brc" |
8779 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8780 | (match_operand 1 "const_int_operand" "n"))] | |
8781 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8782 | "j\t%0" | |
8783 | [(set_attr "op_type" "RI") | |
8784 | (set_attr "type" "branch")]) | |
9db1d521 | 8785 | |
ed9676cf AK |
8786 | (define_insn "*sibcall_brcl" |
8787 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8788 | (match_operand 1 "const_int_operand" "n"))] | |
8789 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8790 | "jg\t%0" | |
8791 | [(set_attr "op_type" "RIL") | |
8792 | (set_attr "type" "branch")]) | |
44b8152b | 8793 | |
ed9676cf AK |
8794 | ; |
8795 | ; sibcall_value patterns | |
8796 | ; | |
9e8327e3 | 8797 | |
ed9676cf AK |
8798 | (define_expand "sibcall_value" |
8799 | [(set (match_operand 0 "" "") | |
8800 | (call (match_operand 1 "" "") | |
8801 | (match_operand 2 "" "")))] | |
8802 | "" | |
8803 | { | |
8804 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 8805 | DONE; |
10bbf137 | 8806 | }) |
9db1d521 | 8807 | |
ed9676cf AK |
8808 | (define_insn "*sibcall_value_br" |
8809 | [(set (match_operand 0 "" "") | |
ae156f85 | 8810 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 8811 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 8812 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
8813 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
8814 | "br\t%%r1" | |
8815 | [(set_attr "op_type" "RR") | |
8816 | (set_attr "type" "branch") | |
8817 | (set_attr "atype" "agen")]) | |
8818 | ||
8819 | (define_insn "*sibcall_value_brc" | |
8820 | [(set (match_operand 0 "" "") | |
8821 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8822 | (match_operand 2 "const_int_operand" "n")))] | |
8823 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
8824 | "j\t%1" | |
8825 | [(set_attr "op_type" "RI") | |
8826 | (set_attr "type" "branch")]) | |
8827 | ||
8828 | (define_insn "*sibcall_value_brcl" | |
8829 | [(set (match_operand 0 "" "") | |
8830 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
8831 | (match_operand 2 "const_int_operand" "n")))] | |
8832 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
8833 | "jg\t%1" | |
8834 | [(set_attr "op_type" "RIL") | |
8835 | (set_attr "type" "branch")]) | |
8836 | ||
8837 | ||
8838 | ; | |
8839 | ; call instruction pattern(s). | |
8840 | ; | |
8841 | ||
8842 | (define_expand "call" | |
8843 | [(call (match_operand 0 "" "") | |
8844 | (match_operand 1 "" "")) | |
8845 | (use (match_operand 2 "" ""))] | |
44b8152b | 8846 | "" |
ed9676cf | 8847 | { |
2f7e5a0d | 8848 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
8849 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
8850 | DONE; | |
8851 | }) | |
44b8152b | 8852 | |
9e8327e3 UW |
8853 | (define_insn "*bras" |
8854 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8855 | (match_operand 1 "const_int_operand" "n")) | |
8856 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8857 | "!SIBLING_CALL_P (insn) |
8858 | && TARGET_SMALL_EXEC | |
ed9676cf | 8859 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 8860 | "bras\t%2,%0" |
9db1d521 | 8861 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8862 | (set_attr "type" "jsr") |
8863 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8864 | |
9e8327e3 UW |
8865 | (define_insn "*brasl" |
8866 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
8867 | (match_operand 1 "const_int_operand" "n")) | |
8868 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
8869 | "!SIBLING_CALL_P (insn) |
8870 | && TARGET_CPU_ZARCH | |
ed9676cf | 8871 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8872 | "brasl\t%2,%0" |
8873 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8874 | (set_attr "type" "jsr") |
8875 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8876 | |
9e8327e3 | 8877 | (define_insn "*basr" |
4fe6dea8 | 8878 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
8879 | (match_operand 1 "const_int_operand" "n")) |
8880 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 8881 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
8882 | { |
8883 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8884 | return "basr\t%2,%0"; | |
8885 | else | |
8886 | return "bas\t%2,%a0"; | |
8887 | } | |
8888 | [(set (attr "op_type") | |
8889 | (if_then_else (match_operand 0 "register_operand" "") | |
8890 | (const_string "RR") (const_string "RX"))) | |
8891 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8892 | (set_attr "atype" "agen") |
8893 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
8894 | |
8895 | ; | |
8896 | ; call_value instruction pattern(s). | |
8897 | ; | |
8898 | ||
8899 | (define_expand "call_value" | |
44b8152b UW |
8900 | [(set (match_operand 0 "" "") |
8901 | (call (match_operand 1 "" "") | |
8902 | (match_operand 2 "" ""))) | |
8903 | (use (match_operand 3 "" ""))] | |
9db1d521 | 8904 | "" |
9db1d521 | 8905 | { |
2f7e5a0d | 8906 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 8907 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 8908 | DONE; |
10bbf137 | 8909 | }) |
9db1d521 | 8910 | |
9e8327e3 | 8911 | (define_insn "*bras_r" |
c19ec8f9 | 8912 | [(set (match_operand 0 "" "") |
9e8327e3 | 8913 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 8914 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 8915 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
8916 | "!SIBLING_CALL_P (insn) |
8917 | && TARGET_SMALL_EXEC | |
ed9676cf | 8918 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 8919 | "bras\t%3,%1" |
9db1d521 | 8920 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
8921 | (set_attr "type" "jsr") |
8922 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8923 | |
9e8327e3 | 8924 | (define_insn "*brasl_r" |
c19ec8f9 | 8925 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
8926 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
8927 | (match_operand 2 "const_int_operand" "n"))) | |
8928 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
8929 | "!SIBLING_CALL_P (insn) |
8930 | && TARGET_CPU_ZARCH | |
ed9676cf | 8931 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8932 | "brasl\t%3,%1" |
8933 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
8934 | (set_attr "type" "jsr") |
8935 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8936 | |
9e8327e3 | 8937 | (define_insn "*basr_r" |
c19ec8f9 | 8938 | [(set (match_operand 0 "" "") |
4fe6dea8 | 8939 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
8940 | (match_operand 2 "const_int_operand" "n"))) |
8941 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 8942 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
8943 | { |
8944 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
8945 | return "basr\t%3,%1"; | |
8946 | else | |
8947 | return "bas\t%3,%a1"; | |
8948 | } | |
8949 | [(set (attr "op_type") | |
8950 | (if_then_else (match_operand 1 "register_operand" "") | |
8951 | (const_string "RR") (const_string "RX"))) | |
8952 | (set_attr "type" "jsr") | |
65b1d8ea AK |
8953 | (set_attr "atype" "agen") |
8954 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8955 | |
fd3cd001 UW |
8956 | ;; |
8957 | ;;- Thread-local storage support. | |
8958 | ;; | |
8959 | ||
f959607b CLT |
8960 | (define_expand "get_thread_pointer<mode>" |
8961 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
8962 | "" | |
c5aa1d12 | 8963 | "") |
fd3cd001 | 8964 | |
f959607b CLT |
8965 | (define_expand "set_thread_pointer<mode>" |
8966 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
8967 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
8968 | "" | |
c5aa1d12 UW |
8969 | "") |
8970 | ||
8971 | (define_insn "*set_tp" | |
ae156f85 | 8972 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
8973 | "" |
8974 | "" | |
8975 | [(set_attr "type" "none") | |
8976 | (set_attr "length" "0")]) | |
c7453384 | 8977 | |
fd3cd001 UW |
8978 | (define_insn "*tls_load_64" |
8979 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 8980 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
8981 | (match_operand:DI 2 "" "")] |
8982 | UNSPEC_TLS_LOAD))] | |
8983 | "TARGET_64BIT" | |
d40c829f | 8984 | "lg\t%0,%1%J2" |
9381e3f1 WG |
8985 | [(set_attr "op_type" "RXE") |
8986 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
8987 | |
8988 | (define_insn "*tls_load_31" | |
d3632d41 UW |
8989 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
8990 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
8991 | (match_operand:SI 2 "" "")] |
8992 | UNSPEC_TLS_LOAD))] | |
8993 | "!TARGET_64BIT" | |
d3632d41 | 8994 | "@ |
d40c829f UW |
8995 | l\t%0,%1%J2 |
8996 | ly\t%0,%1%J2" | |
9381e3f1 | 8997 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 8998 | (set_attr "type" "load") |
9381e3f1 | 8999 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 9000 | |
9e8327e3 | 9001 | (define_insn "*bras_tls" |
c19ec8f9 | 9002 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9003 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9004 | (match_operand 2 "const_int_operand" "n"))) | |
9005 | (clobber (match_operand 3 "register_operand" "=r")) | |
9006 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9007 | "!SIBLING_CALL_P (insn) |
9008 | && TARGET_SMALL_EXEC | |
ed9676cf | 9009 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9010 | "bras\t%3,%1%J4" |
fd3cd001 | 9011 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9012 | (set_attr "type" "jsr") |
9013 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9014 | |
9e8327e3 | 9015 | (define_insn "*brasl_tls" |
c19ec8f9 | 9016 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9017 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9018 | (match_operand 2 "const_int_operand" "n"))) | |
9019 | (clobber (match_operand 3 "register_operand" "=r")) | |
9020 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9021 | "!SIBLING_CALL_P (insn) |
9022 | && TARGET_CPU_ZARCH | |
ed9676cf | 9023 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9024 | "brasl\t%3,%1%J4" |
9025 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9026 | (set_attr "type" "jsr") |
9027 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9028 | |
9e8327e3 | 9029 | (define_insn "*basr_tls" |
c19ec8f9 | 9030 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9031 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9032 | (match_operand 2 "const_int_operand" "n"))) |
9033 | (clobber (match_operand 3 "register_operand" "=r")) | |
9034 | (use (match_operand 4 "" ""))] | |
ed9676cf | 9035 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9036 | { |
9037 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9038 | return "basr\t%3,%1%J4"; | |
9039 | else | |
9040 | return "bas\t%3,%a1%J4"; | |
9041 | } | |
9042 | [(set (attr "op_type") | |
9043 | (if_then_else (match_operand 1 "register_operand" "") | |
9044 | (const_string "RR") (const_string "RX"))) | |
9045 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9046 | (set_attr "atype" "agen") |
9047 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9048 | |
e0374221 AS |
9049 | ;; |
9050 | ;;- Atomic operations | |
9051 | ;; | |
9052 | ||
9053 | ; | |
78ce265b | 9054 | ; memory barrier patterns. |
e0374221 AS |
9055 | ; |
9056 | ||
78ce265b RH |
9057 | (define_expand "mem_signal_fence" |
9058 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
9059 | "" |
9060 | { | |
78ce265b RH |
9061 | /* The s390 memory model is strong enough not to require any |
9062 | barrier in order to synchronize a thread with itself. */ | |
9063 | DONE; | |
9064 | }) | |
9065 | ||
9066 | (define_expand "mem_thread_fence" | |
9067 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
9068 | "" | |
9069 | { | |
9070 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
9071 | enough not to require barriers of any kind. */ | |
9072 | if (INTVAL (operands[0]) == MEMMODEL_SEQ_CST) | |
9073 | { | |
9074 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
9075 | MEM_VOLATILE_P (mem) = 1; | |
9076 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
9077 | } | |
9078 | DONE; | |
e0374221 AS |
9079 | }) |
9080 | ||
78ce265b RH |
9081 | ; Although bcr is superscalar on Z10, this variant will never |
9082 | ; become part of an execution group. | |
a9cc3f58 AK |
9083 | ; With z196 we can make use of the fast-BCR-serialization facility. |
9084 | ; This allows for a slightly faster sync which is sufficient for our | |
9085 | ; purposes. | |
78ce265b | 9086 | (define_insn "mem_thread_fence_1" |
e0374221 | 9087 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 9088 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 9089 | "" |
a9cc3f58 AK |
9090 | { |
9091 | if (TARGET_Z196) | |
9092 | return "bcr\t14,0"; | |
9093 | else | |
9094 | return "bcr\t15,0"; | |
9095 | } | |
9096 | [(set_attr "op_type" "RR") | |
9097 | (set_attr "mnemonic" "bcr_flush") | |
9098 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 9099 | |
78ce265b RH |
9100 | ; |
9101 | ; atomic load/store operations | |
9102 | ; | |
9103 | ||
9104 | ; Atomic loads need not examine the memory model at all. | |
9105 | (define_expand "atomic_load<mode>" | |
9106 | [(match_operand:DINT 0 "register_operand") ;; output | |
9107 | (match_operand:DINT 1 "memory_operand") ;; memory | |
9108 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9109 | "" | |
9110 | { | |
9111 | if (<MODE>mode == TImode) | |
9112 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
9113 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9114 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
9115 | else | |
9116 | emit_move_insn (operands[0], operands[1]); | |
9117 | DONE; | |
9118 | }) | |
9119 | ||
9120 | ; Different from movdi_31 in that we want no splitters. | |
9121 | (define_insn "atomic_loaddi_1" | |
9122 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
9123 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
9124 | UNSPEC_MOVA))] | |
9125 | "!TARGET_ZARCH" | |
9126 | "@ | |
9127 | lm\t%0,%M0,%S1 | |
9128 | lmy\t%0,%M0,%S1 | |
9129 | ld\t%0,%1 | |
9130 | ldy\t%0,%1" | |
9131 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9132 | (set_attr "type" "lm,lm,floaddf,floaddf")]) | |
9133 | ||
9134 | (define_insn "atomic_loadti_1" | |
9135 | [(set (match_operand:TI 0 "register_operand" "=r") | |
9136 | (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] | |
9137 | UNSPEC_MOVA))] | |
9138 | "TARGET_ZARCH" | |
9139 | "lpq\t%0,%1" | |
9140 | [(set_attr "op_type" "RXY") | |
9141 | (set_attr "type" "other")]) | |
9142 | ||
9143 | ; Atomic stores must(?) enforce sequential consistency. | |
9144 | (define_expand "atomic_store<mode>" | |
9145 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
9146 | (match_operand:DINT 1 "register_operand") ;; input | |
9147 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9148 | "" | |
9149 | { | |
9150 | enum memmodel model = (enum memmodel) INTVAL (operands[2]); | |
9151 | ||
9152 | if (<MODE>mode == TImode) | |
9153 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
9154 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9155 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
9156 | else | |
9157 | emit_move_insn (operands[0], operands[1]); | |
9158 | if (model == MEMMODEL_SEQ_CST) | |
9159 | emit_insn (gen_mem_thread_fence (operands[2])); | |
9160 | DONE; | |
9161 | }) | |
9162 | ||
9163 | ; Different from movdi_31 in that we want no splitters. | |
9164 | (define_insn "atomic_storedi_1" | |
9165 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
9166 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
9167 | UNSPEC_MOVA))] | |
9168 | "!TARGET_ZARCH" | |
9169 | "@ | |
9170 | stm\t%1,%N1,%S0 | |
9171 | stmy\t%1,%N1,%S0 | |
9172 | std %1,%0 | |
9173 | stdy %1,%0" | |
9174 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9175 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) | |
9176 | ||
9177 | (define_insn "atomic_storeti_1" | |
9178 | [(set (match_operand:TI 0 "memory_operand" "=RT") | |
9179 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] | |
9180 | UNSPEC_MOVA))] | |
9181 | "TARGET_ZARCH" | |
9182 | "stpq\t%1,%0" | |
9183 | [(set_attr "op_type" "RXY") | |
9184 | (set_attr "type" "other")]) | |
e0374221 AS |
9185 | |
9186 | ; | |
9187 | ; compare and swap patterns. | |
9188 | ; | |
9189 | ||
78ce265b RH |
9190 | (define_expand "atomic_compare_and_swap<mode>" |
9191 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9192 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
9193 | (match_operand:DGPR 2 "memory_operand") ;; memory |
9194 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
9195 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
9196 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9197 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9198 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
9199 | "" | |
9200 | { | |
215770ad UW |
9201 | rtx cc, cmp, output = operands[1]; |
9202 | ||
9203 | if (!register_operand (output, <MODE>mode)) | |
9204 | output = gen_reg_rtx (<MODE>mode); | |
9205 | ||
78ce265b | 9206 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
9207 | (output, operands[2], operands[3], operands[4])); |
9208 | ||
9209 | /* We deliberately accept non-register operands in the predicate | |
9210 | to ensure the write back to the output operand happens *before* | |
9211 | the store-flags code below. This makes it easier for combine | |
9212 | to merge the store-flags code with a potential test-and-branch | |
9213 | pattern following (immediately!) afterwards. */ | |
9214 | if (output != operands[1]) | |
9215 | emit_move_insn (operands[1], output); | |
9216 | ||
78ce265b RH |
9217 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
9218 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
9219 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
9220 | DONE; | |
9221 | }) | |
e0374221 | 9222 | |
78ce265b RH |
9223 | (define_expand "atomic_compare_and_swap<mode>" |
9224 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9225 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
9226 | (match_operand:HQI 2 "memory_operand") ;; memory |
9227 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
9228 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
9229 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9230 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9231 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 9232 | "" |
78ce265b RH |
9233 | { |
9234 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
9235 | operands[3], operands[4], INTVAL (operands[5])); | |
9236 | DONE; | |
9237 | }) | |
3093f076 | 9238 | |
78ce265b RH |
9239 | (define_expand "atomic_compare_and_swap<mode>_internal" |
9240 | [(parallel | |
9241 | [(set (match_operand:DGPR 0 "register_operand") | |
9242 | (match_operand:DGPR 1 "memory_operand")) | |
9243 | (set (match_dup 1) | |
9244 | (unspec_volatile:DGPR | |
9245 | [(match_dup 1) | |
9246 | (match_operand:DGPR 2 "register_operand") | |
9247 | (match_operand:DGPR 3 "register_operand")] | |
9248 | UNSPECV_CAS)) | |
9249 | (set (reg:CCZ1 CC_REGNUM) | |
9250 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
9251 | "") | |
9252 | ||
9253 | ; cdsg, csg | |
9254 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
9255 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
9256 | (match_operand:TDI 1 "memory_operand" "+QS")) | |
8006eaa6 | 9257 | (set (match_dup 1) |
78ce265b | 9258 | (unspec_volatile:TDI |
8006eaa6 | 9259 | [(match_dup 1) |
78ce265b RH |
9260 | (match_operand:TDI 2 "register_operand" "0") |
9261 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
9262 | UNSPECV_CAS)) |
9263 | (set (reg:CCZ1 CC_REGNUM) | |
9264 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
9265 | "TARGET_ZARCH" |
9266 | "c<td>sg\t%0,%3,%S1" | |
9267 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
9268 | (set_attr "type" "sem")]) |
9269 | ||
78ce265b RH |
9270 | ; cds, cdsy |
9271 | (define_insn "*atomic_compare_and_swapdi_2" | |
9272 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
9273 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 9274 | (set (match_dup 1) |
78ce265b RH |
9275 | (unspec_volatile:DI |
9276 | [(match_dup 1) | |
9277 | (match_operand:DI 2 "register_operand" "0,0") | |
9278 | (match_operand:DI 3 "register_operand" "r,r")] | |
9279 | UNSPECV_CAS)) | |
9280 | (set (reg:CCZ1 CC_REGNUM) | |
9281 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9282 | "!TARGET_ZARCH" | |
9283 | "@ | |
9284 | cds\t%0,%3,%S1 | |
9285 | cdsy\t%0,%3,%S1" | |
9286 | [(set_attr "op_type" "RS,RSY") | |
9287 | (set_attr "type" "sem")]) | |
9288 | ||
9289 | ; cs, csy | |
9290 | (define_insn "*atomic_compare_and_swapsi_3" | |
9291 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
9292 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
9293 | (set (match_dup 1) | |
9294 | (unspec_volatile:SI | |
e0374221 | 9295 | [(match_dup 1) |
78ce265b RH |
9296 | (match_operand:SI 2 "register_operand" "0,0") |
9297 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 9298 | UNSPECV_CAS)) |
69950452 AS |
9299 | (set (reg:CCZ1 CC_REGNUM) |
9300 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 9301 | "" |
78ce265b RH |
9302 | "@ |
9303 | cs\t%0,%3,%S1 | |
9304 | csy\t%0,%3,%S1" | |
9305 | [(set_attr "op_type" "RS,RSY") | |
e0374221 AS |
9306 | (set_attr "type" "sem")]) |
9307 | ||
45d18331 AS |
9308 | ; |
9309 | ; Other atomic instruction patterns. | |
9310 | ; | |
9311 | ||
65b1d8ea AK |
9312 | ; z196 load and add, xor, or and and instructions |
9313 | ||
78ce265b RH |
9314 | (define_expand "atomic_fetch_<atomic><mode>" |
9315 | [(match_operand:GPR 0 "register_operand") ;; val out | |
9316 | (ATOMIC_Z196:GPR | |
9317 | (match_operand:GPR 1 "memory_operand") ;; memory | |
9318 | (match_operand:GPR 2 "register_operand")) ;; val in | |
9319 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 9320 | "TARGET_Z196" |
78ce265b RH |
9321 | { |
9322 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf | |
9323 | (operands[0], operands[1], operands[2])); | |
9324 | DONE; | |
9325 | }) | |
65b1d8ea AK |
9326 | |
9327 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
9328 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
9329 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
9330 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
9331 | (set (match_dup 1) | |
9332 | (unspec_volatile:GPR | |
9333 | [(ATOMIC_Z196:GPR (match_dup 1) | |
9334 | (match_operand:GPR 2 "general_operand" "d"))] | |
9335 | UNSPECV_ATOMIC_OP)) | |
9336 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 9337 | "TARGET_Z196" |
78ce265b RH |
9338 | "la<noxa><g>\t%0,%2,%1" |
9339 | [(set_attr "op_type" "RSY") | |
9340 | (set_attr "type" "sem")]) | |
65b1d8ea | 9341 | |
78ce265b RH |
9342 | ;; For SImode and larger, the optabs.c code will do just fine in |
9343 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
9344 | ;; better by expanding our own loop. | |
65b1d8ea | 9345 | |
78ce265b RH |
9346 | (define_expand "atomic_<atomic><mode>" |
9347 | [(ATOMIC:HQI | |
9348 | (match_operand:HQI 0 "memory_operand") ;; memory | |
9349 | (match_operand:HQI 1 "general_operand")) ;; val in | |
9350 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 9351 | "" |
78ce265b RH |
9352 | { |
9353 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
9354 | operands[1], false); | |
9355 | DONE; | |
9356 | }) | |
45d18331 | 9357 | |
78ce265b RH |
9358 | (define_expand "atomic_fetch_<atomic><mode>" |
9359 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9360 | (ATOMIC:HQI | |
9361 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9362 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9363 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9364 | "" |
78ce265b RH |
9365 | { |
9366 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9367 | operands[2], false); | |
9368 | DONE; | |
9369 | }) | |
9370 | ||
9371 | (define_expand "atomic_<atomic>_fetch<mode>" | |
9372 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9373 | (ATOMIC:HQI | |
9374 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9375 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9376 | (match_operand:SI 3 "const_int_operand")] ;; model | |
9377 | "" | |
9378 | { | |
9379 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9380 | operands[2], true); | |
9381 | DONE; | |
9382 | }) | |
9383 | ||
9384 | (define_expand "atomic_exchange<mode>" | |
9385 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9386 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9387 | (match_operand:HQI 2 "general_operand") ;; val in | |
9388 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9389 | "" |
78ce265b RH |
9390 | { |
9391 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
9392 | operands[2], false); | |
9393 | DONE; | |
9394 | }) | |
45d18331 | 9395 | |
9db1d521 HP |
9396 | ;; |
9397 | ;;- Miscellaneous instructions. | |
9398 | ;; | |
9399 | ||
9400 | ; | |
9401 | ; allocate stack instruction pattern(s). | |
9402 | ; | |
9403 | ||
9404 | (define_expand "allocate_stack" | |
ef44a6ff UW |
9405 | [(match_operand 0 "general_operand" "") |
9406 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 9407 | "TARGET_BACKCHAIN" |
9db1d521 | 9408 | { |
ef44a6ff | 9409 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 9410 | |
ef44a6ff UW |
9411 | emit_move_insn (temp, s390_back_chain_rtx ()); |
9412 | anti_adjust_stack (operands[1]); | |
9413 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 9414 | |
ef44a6ff UW |
9415 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
9416 | DONE; | |
10bbf137 | 9417 | }) |
9db1d521 HP |
9418 | |
9419 | ||
9420 | ; | |
43ab026f | 9421 | ; setjmp instruction pattern. |
9db1d521 HP |
9422 | ; |
9423 | ||
9db1d521 | 9424 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 9425 | [(match_operand 0 "" "")] |
f314b9b1 | 9426 | "flag_pic" |
9db1d521 | 9427 | { |
585539a1 | 9428 | emit_insn (s390_load_got ()); |
c41c1387 | 9429 | emit_use (pic_offset_table_rtx); |
9db1d521 | 9430 | DONE; |
fd7643fb | 9431 | }) |
9db1d521 | 9432 | |
9db1d521 HP |
9433 | ;; These patterns say how to save and restore the stack pointer. We need not |
9434 | ;; save the stack pointer at function level since we are careful to | |
9435 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9436 | ;; when we restore the stack pointer. | |
9437 | ;; | |
9438 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9439 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9440 | ;; save area is a memory location. | |
9441 | ||
9442 | (define_expand "save_stack_function" | |
9443 | [(match_operand 0 "general_operand" "") | |
9444 | (match_operand 1 "general_operand" "")] | |
9445 | "" | |
9446 | "DONE;") | |
9447 | ||
9448 | (define_expand "restore_stack_function" | |
9449 | [(match_operand 0 "general_operand" "") | |
9450 | (match_operand 1 "general_operand" "")] | |
9451 | "" | |
9452 | "DONE;") | |
9453 | ||
9454 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
9455 | [(match_operand 0 "register_operand" "") |
9456 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 9457 | "TARGET_BACKCHAIN" |
9db1d521 | 9458 | { |
ef44a6ff UW |
9459 | rtx temp = gen_reg_rtx (Pmode); |
9460 | ||
9461 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
9462 | emit_move_insn (operands[0], operands[1]); | |
9463 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9464 | ||
9465 | DONE; | |
10bbf137 | 9466 | }) |
9db1d521 HP |
9467 | |
9468 | (define_expand "save_stack_nonlocal" | |
9469 | [(match_operand 0 "memory_operand" "") | |
9470 | (match_operand 1 "register_operand" "")] | |
9471 | "" | |
9db1d521 | 9472 | { |
ef44a6ff UW |
9473 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
9474 | ||
9475 | /* Copy the backchain to the first word, sp to the second and the | |
9476 | literal pool base to the third. */ | |
9477 | ||
9602b6a1 AK |
9478 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
9479 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
9480 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
9481 | ||
b3d31392 | 9482 | if (TARGET_BACKCHAIN) |
9602b6a1 | 9483 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 9484 | |
9602b6a1 AK |
9485 | emit_move_insn (save_sp, operands[1]); |
9486 | emit_move_insn (save_bp, base); | |
9db1d521 | 9487 | |
9db1d521 | 9488 | DONE; |
10bbf137 | 9489 | }) |
9db1d521 HP |
9490 | |
9491 | (define_expand "restore_stack_nonlocal" | |
9492 | [(match_operand 0 "register_operand" "") | |
9493 | (match_operand 1 "memory_operand" "")] | |
9494 | "" | |
9db1d521 | 9495 | { |
490ceeb4 | 9496 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 9497 | rtx temp = NULL_RTX; |
9db1d521 | 9498 | |
43ab026f | 9499 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 9500 | literal pool base from the third. */ |
43ab026f | 9501 | |
9602b6a1 AK |
9502 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
9503 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
9504 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
9505 | ||
b3d31392 | 9506 | if (TARGET_BACKCHAIN) |
9602b6a1 | 9507 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 9508 | |
9602b6a1 AK |
9509 | emit_move_insn (base, save_bp); |
9510 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
9511 | |
9512 | if (temp) | |
9513 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9514 | ||
c41c1387 | 9515 | emit_use (base); |
9db1d521 | 9516 | DONE; |
10bbf137 | 9517 | }) |
9db1d521 | 9518 | |
7bcebb25 AK |
9519 | (define_expand "exception_receiver" |
9520 | [(const_int 0)] | |
9521 | "" | |
9522 | { | |
9523 | s390_set_has_landing_pad_p (true); | |
9524 | DONE; | |
9525 | }) | |
9db1d521 HP |
9526 | |
9527 | ; | |
9528 | ; nop instruction pattern(s). | |
9529 | ; | |
9530 | ||
9531 | (define_insn "nop" | |
9532 | [(const_int 0)] | |
9533 | "" | |
d40c829f | 9534 | "lr\t0,0" |
729e750f WG |
9535 | [(set_attr "op_type" "RR") |
9536 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 9537 | |
d277db6b WG |
9538 | (define_insn "nop1" |
9539 | [(const_int 1)] | |
9540 | "" | |
9541 | "lr\t1,1" | |
9542 | [(set_attr "op_type" "RR")]) | |
9543 | ||
9db1d521 HP |
9544 | |
9545 | ; | |
9546 | ; Special literal pool access instruction pattern(s). | |
9547 | ; | |
9548 | ||
416cf582 UW |
9549 | (define_insn "*pool_entry" |
9550 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
9551 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 9552 | "" |
9db1d521 | 9553 | { |
416cf582 UW |
9554 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
9555 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 9556 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
9557 | return ""; |
9558 | } | |
b628bd8e | 9559 | [(set (attr "length") |
416cf582 | 9560 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 9561 | |
9bb86f41 UW |
9562 | (define_insn "pool_align" |
9563 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
9564 | UNSPECV_POOL_ALIGN)] | |
9565 | "" | |
9566 | ".align\t%0" | |
b628bd8e | 9567 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 9568 | |
9bb86f41 UW |
9569 | (define_insn "pool_section_start" |
9570 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
9571 | "" | |
9572 | ".section\t.rodata" | |
b628bd8e | 9573 | [(set_attr "length" "0")]) |
b2ccb744 | 9574 | |
9bb86f41 UW |
9575 | (define_insn "pool_section_end" |
9576 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
9577 | "" | |
b2ccb744 | 9578 | ".previous" |
b628bd8e | 9579 | [(set_attr "length" "0")]) |
b2ccb744 | 9580 | |
5af2f3d3 | 9581 | (define_insn "main_base_31_small" |
9e8327e3 UW |
9582 | [(set (match_operand 0 "register_operand" "=a") |
9583 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9584 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9585 | "basr\t%0,0" |
9586 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
9587 | (set_attr "type" "la") |
9588 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9589 | |
9590 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
9591 | [(set (match_operand 0 "register_operand" "=a") |
9592 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 9593 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 9594 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 9595 | "bras\t%0,%2" |
65b1d8ea AK |
9596 | [(set_attr "op_type" "RI") |
9597 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
9598 | |
9599 | (define_insn "main_base_64" | |
9e8327e3 UW |
9600 | [(set (match_operand 0 "register_operand" "=a") |
9601 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
9602 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
9603 | "larl\t%0,%1" |
9604 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 9605 | (set_attr "type" "larl") |
729e750f | 9606 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
9607 | |
9608 | (define_insn "main_pool" | |
585539a1 UW |
9609 | [(set (match_operand 0 "register_operand" "=a") |
9610 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
9611 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
9612 | { |
9613 | gcc_unreachable (); | |
9614 | } | |
9381e3f1 | 9615 | [(set (attr "type") |
d7f99b2c | 9616 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 9617 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 9618 | |
aee4e0db | 9619 | (define_insn "reload_base_31" |
9e8327e3 UW |
9620 | [(set (match_operand 0 "register_operand" "=a") |
9621 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9622 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9623 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 9624 | [(set_attr "length" "6") |
65b1d8ea AK |
9625 | (set_attr "type" "la") |
9626 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 9627 | |
aee4e0db | 9628 | (define_insn "reload_base_64" |
9e8327e3 UW |
9629 | [(set (match_operand 0 "register_operand" "=a") |
9630 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
9631 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9632 | "larl\t%0,%1" |
aee4e0db | 9633 | [(set_attr "op_type" "RIL") |
9381e3f1 | 9634 | (set_attr "type" "larl") |
729e750f | 9635 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 9636 | |
aee4e0db | 9637 | (define_insn "pool" |
fd7643fb | 9638 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 9639 | "" |
8d933e31 AS |
9640 | { |
9641 | gcc_unreachable (); | |
9642 | } | |
b628bd8e | 9643 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 9644 | |
4023fb28 UW |
9645 | ;; |
9646 | ;; Insns related to generating the function prologue and epilogue. | |
9647 | ;; | |
9648 | ||
9649 | ||
9650 | (define_expand "prologue" | |
9651 | [(use (const_int 0))] | |
9652 | "" | |
10bbf137 | 9653 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
9654 | |
9655 | (define_expand "epilogue" | |
9656 | [(use (const_int 1))] | |
9657 | "" | |
ed9676cf AK |
9658 | "s390_emit_epilogue (false); DONE;") |
9659 | ||
9660 | (define_expand "sibcall_epilogue" | |
9661 | [(use (const_int 0))] | |
9662 | "" | |
9663 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 9664 | |
9e8327e3 | 9665 | (define_insn "*return" |
4023fb28 | 9666 | [(return) |
9e8327e3 UW |
9667 | (use (match_operand 0 "register_operand" "a"))] |
9668 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 9669 | "br\t%0" |
4023fb28 | 9670 | [(set_attr "op_type" "RR") |
c7453384 | 9671 | (set_attr "type" "jsr") |
077dab3b | 9672 | (set_attr "atype" "agen")]) |
4023fb28 | 9673 | |
4023fb28 | 9674 | |
c7453384 | 9675 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 9676 | ;; pointer. This is used for compatibility. |
c7453384 EC |
9677 | |
9678 | (define_expand "ptr_extend" | |
9679 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9680 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 9681 | "TARGET_64BIT" |
c7453384 | 9682 | { |
c7453384 EC |
9683 | emit_insn (gen_anddi3 (operands[0], |
9684 | gen_lowpart (DImode, operands[1]), | |
9685 | GEN_INT (0x7fffffff))); | |
c7453384 | 9686 | DONE; |
10bbf137 | 9687 | }) |
4798630c D |
9688 | |
9689 | ;; Instruction definition to expand eh_return macro to support | |
9690 | ;; swapping in special linkage return addresses. | |
9691 | ||
9692 | (define_expand "eh_return" | |
9693 | [(use (match_operand 0 "register_operand" ""))] | |
9694 | "TARGET_TPF" | |
9695 | { | |
9696 | s390_emit_tpf_eh_return (operands[0]); | |
9697 | DONE; | |
9698 | }) | |
9699 | ||
7b8acc34 AK |
9700 | ; |
9701 | ; Stack Protector Patterns | |
9702 | ; | |
9703 | ||
9704 | (define_expand "stack_protect_set" | |
9705 | [(set (match_operand 0 "memory_operand" "") | |
9706 | (match_operand 1 "memory_operand" ""))] | |
9707 | "" | |
9708 | { | |
9709 | #ifdef TARGET_THREAD_SSP_OFFSET | |
9710 | operands[1] | |
9711 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9712 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9713 | #endif | |
9714 | if (TARGET_64BIT) | |
9715 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
9716 | else | |
9717 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
9718 | ||
9719 | DONE; | |
9720 | }) | |
9721 | ||
9722 | (define_insn "stack_protect_set<mode>" | |
9723 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
9724 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
9725 | "" | |
9726 | "mvc\t%O0(%G0,%R0),%S1" | |
9727 | [(set_attr "op_type" "SS")]) | |
9728 | ||
9729 | (define_expand "stack_protect_test" | |
9730 | [(set (reg:CC CC_REGNUM) | |
9731 | (compare (match_operand 0 "memory_operand" "") | |
9732 | (match_operand 1 "memory_operand" ""))) | |
9733 | (match_operand 2 "" "")] | |
9734 | "" | |
9735 | { | |
f90b7a5a | 9736 | rtx cc_reg, test; |
7b8acc34 AK |
9737 | #ifdef TARGET_THREAD_SSP_OFFSET |
9738 | operands[1] | |
9739 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
9740 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
9741 | #endif | |
7b8acc34 AK |
9742 | if (TARGET_64BIT) |
9743 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
9744 | else | |
9745 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
9746 | ||
f90b7a5a PB |
9747 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
9748 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
9749 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
9750 | DONE; |
9751 | }) | |
9752 | ||
9753 | (define_insn "stack_protect_test<mode>" | |
9754 | [(set (reg:CCZ CC_REGNUM) | |
9755 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
9756 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
9757 | "" | |
9758 | "clc\t%O0(%G0,%R0),%S1" | |
9759 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
9760 | |
9761 | ; This is used in s390_emit_prologue in order to prevent insns | |
9762 | ; adjusting the stack pointer to be moved over insns writing stack | |
9763 | ; slots using a copy of the stack pointer in a different register. | |
9764 | (define_insn "stack_tie" | |
9765 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
9766 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
9767 | "" | |
9768 | "" | |
9769 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
9770 | |
9771 | ||
9772 | ; | |
9773 | ; Data prefetch patterns | |
9774 | ; | |
9775 | ||
9776 | (define_insn "prefetch" | |
22d72dbc AK |
9777 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
9778 | (match_operand:SI 1 "const_int_operand" " n,n") | |
9779 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
9780 | "TARGET_Z10" | |
963fc8d0 | 9781 | { |
4fe6dea8 AK |
9782 | switch (which_alternative) |
9783 | { | |
9784 | case 0: | |
4fe6dea8 | 9785 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 9786 | case 1: |
4fe6dea8 AK |
9787 | if (larl_operand (operands[0], Pmode)) |
9788 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
9789 | default: | |
9790 | ||
9791 | /* This might be reached for symbolic operands with an odd | |
9792 | addend. We simply omit the prefetch for such rare cases. */ | |
9793 | ||
9794 | return ""; | |
9795 | } | |
9381e3f1 | 9796 | } |
22d72dbc AK |
9797 | [(set_attr "type" "load,larl") |
9798 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
9799 | (set_attr "z10prop" "z10_super") |
9800 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
9801 | |
9802 | ||
9803 | ; | |
9804 | ; Byte swap instructions | |
9805 | ; | |
9806 | ||
9807 | (define_insn "bswap<mode>2" | |
9808 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
9809 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] | |
677fbff4 | 9810 | "TARGET_CPU_ZARCH" |
07da44ab AK |
9811 | "@ |
9812 | lrv<g>r\t%0,%1 | |
9813 | lrv<g>\t%0,%1" | |
9814 | [(set_attr "type" "*,load") | |
9815 | (set_attr "op_type" "RRE,RXY") | |
9816 | (set_attr "z10prop" "z10_super")]) | |
65b1d8ea AK |
9817 | |
9818 | ||
9819 | ; | |
9820 | ; Population count instruction | |
9821 | ; | |
9822 | ||
9823 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
9824 | ; portions and stores the result in the corresponding bytes in op0. | |
9825 | (define_insn "*popcount<mode>" | |
9826 | [(set (match_operand:INT 0 "register_operand" "=d") | |
9827 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
9828 | (clobber (reg:CC CC_REGNUM))] | |
9829 | "TARGET_Z196" | |
9830 | "popcnt\t%0,%1" | |
9831 | [(set_attr "op_type" "RRE")]) | |
9832 | ||
9833 | (define_expand "popcountdi2" | |
9834 | [; popcnt op0, op1 | |
9835 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
9836 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
9837 | UNSPEC_POPCNT)) | |
9838 | (clobber (reg:CC CC_REGNUM))]) | |
9839 | ; sllg op2, op0, 32 | |
9840 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
9841 | ; agr op0, op2 | |
9842 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9843 | (clobber (reg:CC CC_REGNUM))]) | |
9844 | ; sllg op2, op0, 16 | |
17465c6e | 9845 | (set (match_dup 2) |
65b1d8ea AK |
9846 | (ashift:DI (match_dup 0) (const_int 16))) |
9847 | ; agr op0, op2 | |
9848 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9849 | (clobber (reg:CC CC_REGNUM))]) | |
9850 | ; sllg op2, op0, 8 | |
9851 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
9852 | ; agr op0, op2 | |
9853 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
9854 | (clobber (reg:CC CC_REGNUM))]) | |
9855 | ; srlg op0, op0, 56 | |
9856 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
9857 | "TARGET_Z196 && TARGET_64BIT" | |
9858 | "operands[2] = gen_reg_rtx (DImode);") | |
9859 | ||
9860 | (define_expand "popcountsi2" | |
9861 | [; popcnt op0, op1 | |
9862 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
9863 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
9864 | UNSPEC_POPCNT)) | |
9865 | (clobber (reg:CC CC_REGNUM))]) | |
9866 | ; sllk op2, op0, 16 | |
17465c6e | 9867 | (set (match_dup 2) |
65b1d8ea AK |
9868 | (ashift:SI (match_dup 0) (const_int 16))) |
9869 | ; ar op0, op2 | |
9870 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9871 | (clobber (reg:CC CC_REGNUM))]) | |
9872 | ; sllk op2, op0, 8 | |
9873 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
9874 | ; ar op0, op2 | |
9875 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9876 | (clobber (reg:CC CC_REGNUM))]) | |
9877 | ; srl op0, op0, 24 | |
9878 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
9879 | "TARGET_Z196" | |
9880 | "operands[2] = gen_reg_rtx (SImode);") | |
9881 | ||
9882 | (define_expand "popcounthi2" | |
9883 | [; popcnt op0, op1 | |
9884 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
9885 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
9886 | UNSPEC_POPCNT)) | |
9887 | (clobber (reg:CC CC_REGNUM))]) | |
9888 | ; sllk op2, op0, 8 | |
17465c6e | 9889 | (set (match_dup 2) |
65b1d8ea AK |
9890 | (ashift:SI (match_dup 0) (const_int 8))) |
9891 | ; ar op0, op2 | |
9892 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
9893 | (clobber (reg:CC CC_REGNUM))]) | |
9894 | ; srl op0, op0, 8 | |
9895 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
9896 | "TARGET_Z196" | |
9897 | "operands[2] = gen_reg_rtx (SImode);") | |
9898 | ||
9899 | (define_expand "popcountqi2" | |
9900 | [; popcnt op0, op1 | |
9901 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
9902 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
9903 | UNSPEC_POPCNT)) | |
9904 | (clobber (reg:CC CC_REGNUM))])] | |
9905 | "TARGET_Z196" | |
9906 | "") | |
9907 | ||
9908 | ;; | |
9909 | ;;- Copy sign instructions | |
9910 | ;; | |
9911 | ||
9912 | (define_insn "copysign<mode>3" | |
9913 | [(set (match_operand:FP 0 "register_operand" "=f") | |
9914 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
9915 | (match_operand:FP 2 "register_operand" "f")] | |
9916 | UNSPEC_COPYSIGN))] | |
9917 | "TARGET_Z196" | |
9918 | "cpsdr\t%0,%2,%1" | |
9919 | [(set_attr "op_type" "RRF") | |
9920 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
9921 | |
9922 | ||
9923 | ;; | |
9924 | ;;- Transactional execution instructions | |
9925 | ;; | |
9926 | ||
9927 | ; This splitter helps combine to make use of CC directly when | |
9928 | ; comparing the integer result of a tbegin builtin with a constant. | |
9929 | ; The unspec is already removed by canonicalize_comparison. So this | |
9930 | ; splitters only job is to turn the PARALLEL into separate insns | |
9931 | ; again. Unfortunately this only works with the very first cc/int | |
9932 | ; compare since combine is not able to deal with data flow across | |
9933 | ; basic block boundaries. | |
9934 | ||
9935 | ; It needs to be an insn pattern as well since combine does not apply | |
9936 | ; the splitter directly. Combine would only use it if it actually | |
9937 | ; would reduce the number of instructions. | |
9938 | (define_insn_and_split "*ccraw_to_int" | |
9939 | [(set (pc) | |
9940 | (if_then_else | |
9941 | (match_operator 0 "s390_eqne_operator" | |
9942 | [(reg:CCRAW CC_REGNUM) | |
9943 | (match_operand 1 "const_int_operand" "")]) | |
9944 | (label_ref (match_operand 2 "" "")) | |
9945 | (pc))) | |
9946 | (set (match_operand:SI 3 "register_operand" "=d") | |
9947 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
9948 | "" | |
9949 | "#" | |
9950 | "" | |
9951 | [(set (match_dup 3) | |
9952 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
9953 | (set (pc) | |
9954 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
9955 | (label_ref (match_dup 2)) | |
9956 | (pc)))] | |
9957 | "") | |
9958 | ||
9959 | ; Non-constrained transaction begin | |
9960 | ||
9961 | (define_expand "tbegin" | |
ee163e72 AK |
9962 | [(match_operand:SI 0 "register_operand" "") |
9963 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
9964 | "TARGET_HTM" |
9965 | { | |
9966 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
9967 | DONE; | |
9968 | }) | |
9969 | ||
9970 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
9971 | [(match_operand:SI 0 "register_operand" "") |
9972 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
9973 | "TARGET_HTM" |
9974 | { | |
9975 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
9976 | DONE; | |
9977 | }) | |
9978 | ||
9979 | (define_expand "tbegin_retry" | |
ee163e72 AK |
9980 | [(match_operand:SI 0 "register_operand" "") |
9981 | (match_operand:BLK 1 "memory_operand" "") | |
9982 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
9983 | "TARGET_HTM" |
9984 | { | |
9985 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
9986 | DONE; | |
9987 | }) | |
9988 | ||
9989 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
9990 | [(match_operand:SI 0 "register_operand" "") |
9991 | (match_operand:BLK 1 "memory_operand" "") | |
9992 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
9993 | "TARGET_HTM" |
9994 | { | |
9995 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
9996 | DONE; | |
9997 | }) | |
9998 | ||
9999 | (define_insn "tbegin_1" | |
10000 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 10001 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 10002 | UNSPECV_TBEGIN)) |
2561451d AK |
10003 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
10004 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
10005 | (clobber (reg:DF 16)) |
10006 | (clobber (reg:DF 17)) | |
10007 | (clobber (reg:DF 18)) | |
10008 | (clobber (reg:DF 19)) | |
10009 | (clobber (reg:DF 20)) | |
10010 | (clobber (reg:DF 21)) | |
10011 | (clobber (reg:DF 22)) | |
10012 | (clobber (reg:DF 23)) | |
10013 | (clobber (reg:DF 24)) | |
10014 | (clobber (reg:DF 25)) | |
10015 | (clobber (reg:DF 26)) | |
10016 | (clobber (reg:DF 27)) | |
10017 | (clobber (reg:DF 28)) | |
10018 | (clobber (reg:DF 29)) | |
10019 | (clobber (reg:DF 30)) | |
10020 | (clobber (reg:DF 31))] | |
10021 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10022 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
10023 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
10024 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10025 | [(set_attr "op_type" "SIL")]) |
10026 | ||
10027 | ; Same as above but without the FPR clobbers | |
10028 | (define_insn "tbegin_nofloat_1" | |
10029 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
10030 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
10031 | UNSPECV_TBEGIN)) | |
10032 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10033 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
10034 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10035 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10036 | [(set_attr "op_type" "SIL")]) |
10037 | ||
10038 | ||
10039 | ; Constrained transaction begin | |
10040 | ||
10041 | (define_expand "tbeginc" | |
10042 | [(set (reg:CCRAW CC_REGNUM) | |
10043 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
10044 | UNSPECV_TBEGINC))] | |
10045 | "TARGET_HTM" | |
10046 | "") | |
10047 | ||
10048 | (define_insn "*tbeginc_1" | |
10049 | [(set (reg:CCRAW CC_REGNUM) | |
10050 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
10051 | UNSPECV_TBEGINC))] | |
10052 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10053 | "tbeginc\t0,%x0" | |
10054 | [(set_attr "op_type" "SIL")]) | |
10055 | ||
10056 | ; Transaction end | |
10057 | ||
10058 | (define_expand "tend" | |
10059 | [(set (reg:CCRAW CC_REGNUM) | |
10060 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 10061 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
10062 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
10063 | "TARGET_HTM" | |
10064 | "") | |
10065 | ||
10066 | (define_insn "*tend_1" | |
10067 | [(set (reg:CCRAW CC_REGNUM) | |
10068 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
10069 | "TARGET_HTM" | |
10070 | "tend" | |
10071 | [(set_attr "op_type" "S")]) | |
10072 | ||
10073 | ; Transaction abort | |
10074 | ||
10075 | (define_expand "tabort" | |
ee163e72 | 10076 | [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")] |
5a3fe9b6 AK |
10077 | UNSPECV_TABORT)] |
10078 | "TARGET_HTM && operands != NULL" | |
10079 | { | |
10080 | if (CONST_INT_P (operands[0]) | |
10081 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
10082 | { | |
10083 | error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC | |
10084 | ". Values in range 0 through 255 are reserved.", | |
10085 | INTVAL (operands[0])); | |
10086 | FAIL; | |
10087 | } | |
10088 | }) | |
10089 | ||
10090 | (define_insn "*tabort_1" | |
ee163e72 | 10091 | [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")] |
5a3fe9b6 AK |
10092 | UNSPECV_TABORT)] |
10093 | "TARGET_HTM && operands != NULL" | |
10094 | "tabort\t%Y0" | |
10095 | [(set_attr "op_type" "S")]) | |
10096 | ||
10097 | ; Transaction extract nesting depth | |
10098 | ||
10099 | (define_insn "etnd" | |
10100 | [(set (match_operand:SI 0 "register_operand" "=d") | |
10101 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
10102 | "TARGET_HTM" | |
10103 | "etnd\t%0" | |
10104 | [(set_attr "op_type" "RRE")]) | |
10105 | ||
10106 | ; Non-transactional store | |
10107 | ||
10108 | (define_insn "ntstg" | |
10109 | [(set (match_operand:DI 0 "memory_operand" "=RT") | |
10110 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] | |
10111 | UNSPECV_NTSTG))] | |
10112 | "TARGET_HTM" | |
10113 | "ntstg\t%1,%0" | |
10114 | [(set_attr "op_type" "RXY")]) | |
10115 | ||
10116 | ; Transaction perform processor assist | |
10117 | ||
10118 | (define_expand "tx_assist" | |
2561451d AK |
10119 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
10120 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
10121 | (const_int 1)] |
10122 | UNSPECV_PPA)] | |
10123 | "TARGET_HTM" | |
2561451d | 10124 | "") |
5a3fe9b6 AK |
10125 | |
10126 | (define_insn "*ppa" | |
10127 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
10128 | (match_operand:SI 1 "register_operand" "d") | |
10129 | (match_operand 2 "const_int_operand" "I")] | |
10130 | UNSPECV_PPA)] | |
10131 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 10132 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 10133 | [(set_attr "op_type" "RRF")]) |