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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
9c3c3dcc | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a UW |
20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
21 | ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | ;; 02111-1307, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
9dc62c00 | 28 | ;; c -- Condition code register 33. |
9db1d521 HP |
29 | ;; d -- Any register from 0 to 15. |
30 | ;; I -- An 8-bit constant (0..255). | |
31 | ;; J -- A 12-bit constant (0..4095). | |
32 | ;; K -- A 16-bit constant (-32768..32767). | |
2f7e5a0d | 33 | ;; L -- Value appropriate as displacement. |
f19a9af7 AK |
34 | ;; (0..4095) for short displacement |
35 | ;; (-524288..524287) for long displacement | |
36 | ;; M -- Constant integer with a value of 0x7fffffff. | |
37 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
0dfa6c5e UW |
38 | ;; 0..9,x: number of the part counting from most to least significant |
39 | ;; H,Q: mode of the part | |
40 | ;; D,S,H: mode of the containing operand | |
41 | ;; 0,F: value of the other parts (F - all bits set) | |
2f7e5a0d | 42 | ;; |
f19a9af7 | 43 | ;; The constraint matches if the specified part of a constant |
0dfa6c5e UW |
44 | ;; has a value different from its other parts. If the letter x |
45 | ;; is specified instead of a part number, the constraint matches | |
46 | ;; if there is any single part with non-default value. | |
f19a9af7 AK |
47 | ;; Q -- Memory reference without index register and with short displacement. |
48 | ;; R -- Memory reference with index register and short displacement. | |
49 | ;; S -- Memory reference without index register but with long displacement. | |
50 | ;; T -- Memory reference with index register and long displacement. | |
0dfa6c5e UW |
51 | ;; A -- Multiple letter constraint followed by Q, R, S, or T: |
52 | ;; Offsettable memory reference of type specified by second letter. | |
e221ef54 UW |
53 | ;; B -- Multiple letter constraint followed by Q, R, S, or T: |
54 | ;; Memory reference of the type specified by second letter that | |
55 | ;; does *not* refer to a literal pool entry. | |
f19a9af7 AK |
56 | ;; U -- Pointer with short displacement. |
57 | ;; W -- Pointer with long displacement. | |
58 | ;; Y -- Shift count operand. | |
9db1d521 HP |
59 | ;; |
60 | ;; Special formats used for outputting 390 instructions. | |
61 | ;; | |
f19a9af7 AK |
62 | ;; %C: print opcode suffix for branch condition. |
63 | ;; %D: print opcode suffix for inverse branch condition. | |
64 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
65 | ;; %O: print only the displacement of a memory reference. | |
66 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 67 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
68 | ;; %N: print the second word of a DImode operand. |
69 | ;; %M: print the second word of a TImode operand. | |
70 | ||
71 | ;; %b: print integer X as if it's an unsigned byte. | |
72 | ;; %x: print integer X as if it's an unsigned word. | |
73 | ;; %h: print integer X as if it's a signed word. | |
74 | ;; %i: print the first nonzero HImode part of X | |
75 | ;; %j: print the first HImode part unequal to 0xffff of X | |
76 | ||
9db1d521 HP |
77 | ;; |
78 | ;; We have a special constraint for pattern matching. | |
79 | ;; | |
80 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
81 | ;; | |
9db1d521 | 82 | |
fd3cd001 UW |
83 | ;; |
84 | ;; UNSPEC usage | |
85 | ;; | |
86 | ||
87 | (define_constants | |
10bbf137 UW |
88 | [; Miscellaneous |
89 | (UNSPEC_ROUND 1) | |
5b022de5 | 90 | (UNSPEC_CMPINT 2) |
10bbf137 UW |
91 | (UNSPEC_SETHIGH 10) |
92 | ||
93 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
94 | (UNSPEC_LTREL_OFFSET 100) |
95 | (UNSPEC_LTREL_BASE 101) | |
96 | (UNSPEC_GOTENT 110) | |
97 | (UNSPEC_GOT 111) | |
98 | (UNSPEC_GOTOFF 112) | |
99 | (UNSPEC_PLT 113) | |
100 | (UNSPEC_PLTOFF 114) | |
101 | ||
102 | ; Literal pool | |
103 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 104 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 105 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
106 | (UNSPEC_INSN 213) |
107 | (UNSPEC_EXECUTE 214) | |
fd7643fb UW |
108 | |
109 | ; TLS relocation specifiers | |
fd3cd001 UW |
110 | (UNSPEC_TLSGD 500) |
111 | (UNSPEC_TLSLDM 501) | |
112 | (UNSPEC_NTPOFF 502) | |
113 | (UNSPEC_DTPOFF 503) | |
114 | (UNSPEC_GOTNTPOFF 504) | |
115 | (UNSPEC_INDNTPOFF 505) | |
116 | ||
117 | ; TLS support | |
fd3cd001 UW |
118 | (UNSPEC_TLSLDM_NTPOFF 511) |
119 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
120 | |
121 | ; String Functions | |
122 | (UNSPEC_SRST 600) | |
fd3cd001 UW |
123 | ]) |
124 | ||
125 | ;; | |
126 | ;; UNSPEC_VOLATILE usage | |
127 | ;; | |
128 | ||
129 | (define_constants | |
10bbf137 UW |
130 | [; Blockage |
131 | (UNSPECV_BLOCKAGE 0) | |
132 | ||
2f7e5a0d EC |
133 | ; TPF Support |
134 | (UNSPECV_TPF_PROLOGUE 20) | |
135 | (UNSPECV_TPF_EPILOGUE 21) | |
136 | ||
10bbf137 | 137 | ; Literal pool |
fd7643fb | 138 | (UNSPECV_POOL 200) |
9bb86f41 UW |
139 | (UNSPECV_POOL_SECTION 201) |
140 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 141 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
142 | (UNSPECV_MAIN_POOL 300) |
143 | ||
144 | ; TLS support | |
fd3cd001 UW |
145 | (UNSPECV_SET_TP 500) |
146 | ]) | |
147 | ||
148 | ||
29a74354 UW |
149 | ;; Instruction operand type as used in the Principles of Operation. |
150 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 151 | |
29a74354 UW |
152 | (define_attr "op_type" |
153 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" | |
b628bd8e | 154 | (const_string "NN")) |
9db1d521 | 155 | |
29a74354 | 156 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 157 | |
077dab3b | 158 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
ed0e512a AK |
159 | cs,vs,store,idiv, |
160 | imulhi,imulsi,imuldi, | |
077dab3b HP |
161 | branch,jsr,fsimpd,fsimps, |
162 | floadd,floads,fstored, fstores, | |
163 | fmuld,fmuls,fdivd,fdivs, | |
164 | ftoi,itof,fsqrtd,fsqrts, | |
a036c6f7 | 165 | other" |
29a74354 UW |
166 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
167 | (eq_attr "op_type" "SS") (const_string "cs")] | |
168 | (const_string "integer"))) | |
9db1d521 | 169 | |
29a74354 UW |
170 | ;; Another attribute used for scheduling purposes: |
171 | ;; agen: Instruction uses the address generation unit | |
172 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
173 | |
174 | (define_attr "atype" "agen,reg" | |
b628bd8e | 175 | (cond [(eq_attr "op_type" "E") (const_string "reg") |
077dab3b HP |
176 | (eq_attr "op_type" "RR") (const_string "reg") |
177 | (eq_attr "op_type" "RX") (const_string "agen") | |
178 | (eq_attr "op_type" "RI") (const_string "reg") | |
179 | (eq_attr "op_type" "RRE") (const_string "reg") | |
180 | (eq_attr "op_type" "RS") (const_string "agen") | |
181 | (eq_attr "op_type" "RSI") (const_string "agen") | |
182 | (eq_attr "op_type" "S") (const_string "agen") | |
183 | (eq_attr "op_type" "SI") (const_string "agen") | |
184 | (eq_attr "op_type" "SS") (const_string "agen") | |
185 | (eq_attr "op_type" "SSE") (const_string "agen") | |
186 | (eq_attr "op_type" "RXE") (const_string "agen") | |
187 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
188 | (eq_attr "op_type" "RIL") (const_string "agen") |
189 | (eq_attr "op_type" "RXY") (const_string "agen") | |
190 | (eq_attr "op_type" "RSY") (const_string "agen") | |
191 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
b628bd8e | 192 | (const_string "agen"))) |
9db1d521 | 193 | |
9db1d521 HP |
194 | ;; Length in bytes. |
195 | ||
196 | (define_attr "length" "" | |
b628bd8e | 197 | (cond [(eq_attr "op_type" "E") (const_int 2) |
9db1d521 HP |
198 | (eq_attr "op_type" "RR") (const_int 2) |
199 | (eq_attr "op_type" "RX") (const_int 4) | |
200 | (eq_attr "op_type" "RI") (const_int 4) | |
201 | (eq_attr "op_type" "RRE") (const_int 4) | |
202 | (eq_attr "op_type" "RS") (const_int 4) | |
203 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
204 | (eq_attr "op_type" "S") (const_int 4) |
205 | (eq_attr "op_type" "SI") (const_int 4) | |
206 | (eq_attr "op_type" "SS") (const_int 6) | |
207 | (eq_attr "op_type" "SSE") (const_int 6) | |
208 | (eq_attr "op_type" "RXE") (const_int 6) | |
209 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
210 | (eq_attr "op_type" "RIL") (const_int 6) |
211 | (eq_attr "op_type" "RXY") (const_int 6) | |
212 | (eq_attr "op_type" "RSY") (const_int 6) | |
213 | (eq_attr "op_type" "SIY") (const_int 6)] | |
b628bd8e | 214 | (const_int 6))) |
9db1d521 | 215 | |
29a74354 UW |
216 | |
217 | ;; Processor type. This attribute must exactly match the processor_type | |
218 | ;; enumeration in s390.h. The current machine description does not | |
219 | ;; distinguish between g5 and g6, but there are differences between the two | |
220 | ;; CPUs could in theory be modeled. | |
221 | ||
222 | (define_attr "cpu" "g5,g6,z900,z990" | |
223 | (const (symbol_ref "s390_tune"))) | |
224 | ||
225 | ;; Pipeline description for z900. For lack of anything better, | |
226 | ;; this description is also used for the g5 and g6. | |
227 | (include "2064.md") | |
228 | ||
229 | ;; Pipeline description for z990. | |
230 | (include "2084.md") | |
231 | ||
0bfc3f69 AS |
232 | ;; Predicates |
233 | (include "predicates.md") | |
234 | ||
f52c81dd AS |
235 | |
236 | ;; Macros | |
237 | ||
9db2f16d AS |
238 | ;; This mode macro allows 31-bit and 64-bit GPR patterns to be generated |
239 | ;; from the same template. | |
240 | (define_mode_macro GPR [(DI "TARGET_64BIT") SI]) | |
241 | ||
242 | ;; This mode macro allows :P to be used for patterns that operate on | |
243 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
244 | (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) | |
245 | ||
f52c81dd AS |
246 | ;; This mode macro allows the QI and HI patterns to be defined from |
247 | ;; the same template. | |
248 | (define_mode_macro HQI [HI QI]) | |
249 | ||
342cf42b AS |
250 | ;; This mode macro allows the integer patterns to be defined from the |
251 | ;; same template. | |
252 | (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI]) | |
253 | ||
fa77b251 AS |
254 | ;; This macro allows to unify all 'bCOND' expander patterns. |
255 | (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered | |
256 | ordered uneq unlt ungt unle unge ltgt]) | |
257 | ||
f52c81dd AS |
258 | |
259 | ;; ICM mask required to load MODE value into the highest subreg | |
260 | ;; of a SImode register. | |
261 | (define_mode_attr icm_hi [(HI "12") (QI "8")]) | |
262 | ||
263 | ;; ICM mask required to load MODE value into the lowest subreg | |
264 | ;; of a SImode register. | |
265 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
266 | ||
267 | ;; Maximum unsigned integer that fits in MODE. | |
268 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
269 | ||
270 | ||
9db1d521 HP |
271 | ;; |
272 | ;;- Compare instructions. | |
273 | ;; | |
274 | ||
9db2f16d | 275 | (define_expand "cmp<mode>" |
9db1d521 | 276 | [(set (reg:CC 33) |
9db2f16d AS |
277 | (compare:CC (match_operand:GPR 0 "register_operand" "") |
278 | (match_operand:GPR 1 "general_operand" "")))] | |
9db1d521 | 279 | "" |
9db1d521 HP |
280 | { |
281 | s390_compare_op0 = operands[0]; | |
282 | s390_compare_op1 = operands[1]; | |
283 | DONE; | |
10bbf137 | 284 | }) |
9db1d521 | 285 | |
9db1d521 HP |
286 | (define_expand "cmpdf" |
287 | [(set (reg:CC 33) | |
288 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
289 | (match_operand:DF 1 "general_operand" "")))] | |
290 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
291 | { |
292 | s390_compare_op0 = operands[0]; | |
293 | s390_compare_op1 = operands[1]; | |
294 | DONE; | |
10bbf137 | 295 | }) |
9db1d521 HP |
296 | |
297 | (define_expand "cmpsf" | |
298 | [(set (reg:CC 33) | |
299 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
300 | (match_operand:SF 1 "general_operand" "")))] | |
301 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
302 | { |
303 | s390_compare_op0 = operands[0]; | |
304 | s390_compare_op1 = operands[1]; | |
305 | DONE; | |
10bbf137 | 306 | }) |
9db1d521 HP |
307 | |
308 | ||
07893d4f | 309 | ; Test-under-Mask instructions |
9db1d521 | 310 | |
07893d4f | 311 | (define_insn "*tmqi_mem" |
9db1d521 | 312 | [(set (reg 33) |
68f9c5e2 UW |
313 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
314 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
315 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
07893d4f | 316 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" |
d3632d41 | 317 | "@ |
fc0ea003 UW |
318 | tm\t%S0,%b1 |
319 | tmy\t%S0,%b1" | |
d3632d41 | 320 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 321 | |
05b9aaaa UW |
322 | (define_insn "*tmdi_reg" |
323 | [(set (reg 33) | |
f19a9af7 | 324 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 325 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
326 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
327 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa UW |
328 | "TARGET_64BIT |
329 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
f19a9af7 AK |
330 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
331 | "@ | |
332 | tmhh\t%0,%i1 | |
333 | tmhl\t%0,%i1 | |
334 | tmlh\t%0,%i1 | |
335 | tmll\t%0,%i1" | |
05b9aaaa UW |
336 | [(set_attr "op_type" "RI")]) |
337 | ||
338 | (define_insn "*tmsi_reg" | |
339 | [(set (reg 33) | |
f19a9af7 AK |
340 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
341 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
342 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
05b9aaaa | 343 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) |
f19a9af7 AK |
344 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
345 | "@ | |
346 | tmh\t%0,%i1 | |
347 | tml\t%0,%i1" | |
05b9aaaa UW |
348 | [(set_attr "op_type" "RI")]) |
349 | ||
f52c81dd | 350 | (define_insn "*tm<mode>_full" |
9db1d521 | 351 | [(set (reg 33) |
f52c81dd AS |
352 | (compare (match_operand:HQI 0 "register_operand" "d") |
353 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
a556fd39 | 354 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
f52c81dd | 355 | "tml\t%0,<max_uint>" |
07893d4f | 356 | [(set_attr "op_type" "RI")]) |
9db1d521 | 357 | |
07893d4f UW |
358 | |
359 | ; Load-and-Test instructions | |
360 | ||
361 | (define_insn "*tstdi_sign" | |
9db1d521 | 362 | [(set (reg 33) |
07893d4f UW |
363 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
364 | (const_int 32)) (const_int 32)) | |
365 | (match_operand:DI 1 "const0_operand" ""))) | |
366 | (set (match_operand:DI 2 "register_operand" "=d") | |
367 | (sign_extend:DI (match_dup 0)))] | |
368 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 369 | "ltgfr\t%2,%0" |
07893d4f UW |
370 | [(set_attr "op_type" "RRE")]) |
371 | ||
372 | (define_insn "*tstdi" | |
9db1d521 | 373 | [(set (reg 33) |
07893d4f UW |
374 | (compare (match_operand:DI 0 "register_operand" "d") |
375 | (match_operand:DI 1 "const0_operand" ""))) | |
376 | (set (match_operand:DI 2 "register_operand" "=d") | |
377 | (match_dup 0))] | |
378 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 379 | "ltgr\t%2,%0" |
07893d4f | 380 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 381 | |
07893d4f | 382 | (define_insn "*tstdi_cconly" |
9db1d521 | 383 | [(set (reg 33) |
07893d4f UW |
384 | (compare (match_operand:DI 0 "register_operand" "d") |
385 | (match_operand:DI 1 "const0_operand" "")))] | |
386 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 387 | "ltgr\t%0,%0" |
07893d4f | 388 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 389 | |
07893d4f UW |
390 | (define_insn "*tstdi_cconly_31" |
391 | [(set (reg 33) | |
392 | (compare (match_operand:DI 0 "register_operand" "d") | |
393 | (match_operand:DI 1 "const0_operand" "")))] | |
394 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 395 | "srda\t%0,0" |
077dab3b HP |
396 | [(set_attr "op_type" "RS") |
397 | (set_attr "atype" "reg")]) | |
398 | ||
4023fb28 | 399 | |
07893d4f UW |
400 | (define_insn "*tstsi" |
401 | [(set (reg 33) | |
d3632d41 | 402 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 403 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 404 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f UW |
405 | (match_dup 0))] |
406 | "s390_match_ccmode(insn, CCSmode)" | |
407 | "@ | |
d40c829f | 408 | ltr\t%2,%0 |
fc0ea003 UW |
409 | icm\t%2,15,%S0 |
410 | icmy\t%2,15,%S0" | |
d3632d41 | 411 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 412 | |
07893d4f | 413 | (define_insn "*tstsi_cconly" |
4023fb28 | 414 | [(set (reg 33) |
d3632d41 | 415 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 416 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 417 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
418 | "s390_match_ccmode(insn, CCSmode)" |
419 | "@ | |
d40c829f | 420 | ltr\t%0,%0 |
fc0ea003 UW |
421 | icm\t%2,15,%S0 |
422 | icmy\t%2,15,%S0" | |
d3632d41 | 423 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 424 | |
07893d4f UW |
425 | (define_insn "*tstsi_cconly2" |
426 | [(set (reg 33) | |
427 | (compare (match_operand:SI 0 "register_operand" "d") | |
428 | (match_operand:SI 1 "const0_operand" "")))] | |
429 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 430 | "ltr\t%0,%0" |
07893d4f | 431 | [(set_attr "op_type" "RR")]) |
4023fb28 | 432 | |
f52c81dd | 433 | (define_insn "*tst<mode>CCT" |
3af97654 | 434 | [(set (reg 33) |
f52c81dd AS |
435 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
436 | (match_operand:HQI 1 "const0_operand" ""))) | |
437 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
438 | (match_dup 0))] |
439 | "s390_match_ccmode(insn, CCTmode)" | |
440 | "@ | |
f52c81dd AS |
441 | icm\t%2,<icm_lo>,%S0 |
442 | icmy\t%2,<icm_lo>,%S0 | |
443 | tml\t%0,<max_uint>" | |
d3632d41 | 444 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
445 | |
446 | (define_insn "*tsthiCCT_cconly" | |
447 | [(set (reg 33) | |
d3632d41 | 448 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 449 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 450 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
451 | "s390_match_ccmode(insn, CCTmode)" |
452 | "@ | |
fc0ea003 UW |
453 | icm\t%2,3,%S0 |
454 | icmy\t%2,3,%S0 | |
d40c829f | 455 | tml\t%0,65535" |
d3632d41 | 456 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 457 | |
3af97654 UW |
458 | (define_insn "*tstqiCCT_cconly" |
459 | [(set (reg 33) | |
d3632d41 | 460 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
461 | (match_operand:QI 1 "const0_operand" "")))] |
462 | "s390_match_ccmode(insn, CCTmode)" | |
463 | "@ | |
fc0ea003 UW |
464 | cli\t%S0,0 |
465 | cliy\t%S0,0 | |
d40c829f | 466 | tml\t%0,255" |
d3632d41 | 467 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 468 | |
f52c81dd | 469 | (define_insn "*tst<mode>" |
9db1d521 | 470 | [(set (reg 33) |
f52c81dd AS |
471 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
472 | (match_operand:HQI 1 "const0_operand" ""))) | |
473 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
474 | (match_dup 0))] |
475 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 476 | "@ |
f52c81dd AS |
477 | icm\t%2,<icm_lo>,%S0 |
478 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 | 479 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 480 | |
f52c81dd | 481 | (define_insn "*tst<mode>_cconly" |
9db1d521 | 482 | [(set (reg 33) |
f52c81dd AS |
483 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
484 | (match_operand:HQI 1 "const0_operand" ""))) | |
485 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 486 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 487 | "@ |
f52c81dd AS |
488 | icm\t%2,<icm_lo>,%S0 |
489 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 UW |
490 | [(set_attr "op_type" "RS,RSY")]) |
491 | ||
9db1d521 | 492 | |
575f7c2b UW |
493 | ; Compare (equality) instructions |
494 | ||
495 | (define_insn "*cmpdi_cct" | |
496 | [(set (reg 33) | |
e221ef54 UW |
497 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q") |
498 | (match_operand:DI 1 "general_operand" "d,K,m,BQ")))] | |
499 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" | |
575f7c2b UW |
500 | "@ |
501 | cgr\t%0,%1 | |
f4f41b4e | 502 | cghi\t%0,%h1 |
575f7c2b | 503 | cg\t%0,%1 |
19b63d8e | 504 | #" |
e221ef54 | 505 | [(set_attr "op_type" "RRE,RI,RXY,SS")]) |
575f7c2b UW |
506 | |
507 | (define_insn "*cmpsi_cct" | |
508 | [(set (reg 33) | |
e221ef54 UW |
509 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
510 | (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))] | |
511 | "s390_match_ccmode (insn, CCTmode)" | |
575f7c2b UW |
512 | "@ |
513 | cr\t%0,%1 | |
f4f41b4e | 514 | chi\t%0,%h1 |
575f7c2b UW |
515 | c\t%0,%1 |
516 | cy\t%0,%1 | |
19b63d8e | 517 | #" |
e221ef54 | 518 | [(set_attr "op_type" "RR,RI,RX,RXY,SS")]) |
575f7c2b UW |
519 | |
520 | ||
07893d4f | 521 | ; Compare (signed) instructions |
4023fb28 | 522 | |
07893d4f | 523 | (define_insn "*cmpdi_ccs_sign" |
4023fb28 | 524 | [(set (reg 33) |
07893d4f UW |
525 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
526 | (match_operand:DI 0 "register_operand" "d,d")))] | |
527 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 528 | "@ |
d40c829f UW |
529 | cgfr\t%0,%1 |
530 | cgf\t%0,%1" | |
d3632d41 | 531 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 532 | |
07893d4f | 533 | (define_insn "*cmpdi_ccs" |
4023fb28 | 534 | [(set (reg 33) |
07893d4f UW |
535 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
536 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
537 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
538 | "@ | |
d40c829f | 539 | cgr\t%0,%1 |
f4f41b4e | 540 | cghi\t%0,%h1 |
d40c829f | 541 | cg\t%0,%1" |
d3632d41 | 542 | [(set_attr "op_type" "RRE,RI,RXY")]) |
c7453384 | 543 | |
07893d4f UW |
544 | (define_insn "*cmpsi_ccs_sign" |
545 | [(set (reg 33) | |
d3632d41 UW |
546 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
547 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 548 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 549 | "@ |
d40c829f UW |
550 | ch\t%0,%1 |
551 | chy\t%0,%1" | |
d3632d41 | 552 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 553 | |
07893d4f | 554 | (define_insn "*cmpsi_ccs" |
9db1d521 | 555 | [(set (reg 33) |
d3632d41 UW |
556 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
557 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
9db1d521 | 558 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 559 | "@ |
d40c829f | 560 | cr\t%0,%1 |
f4f41b4e | 561 | chi\t%0,%h1 |
d40c829f UW |
562 | c\t%0,%1 |
563 | cy\t%0,%1" | |
d3632d41 | 564 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
c7453384 | 565 | |
07893d4f UW |
566 | |
567 | ; Compare (unsigned) instructions | |
9db1d521 | 568 | |
07893d4f | 569 | (define_insn "*cmpdi_ccu_zero" |
9db1d521 | 570 | [(set (reg 33) |
07893d4f UW |
571 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
572 | (match_operand:DI 0 "register_operand" "d,d")))] | |
575f7c2b | 573 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 574 | "@ |
d40c829f UW |
575 | clgfr\t%0,%1 |
576 | clgf\t%0,%1" | |
d3632d41 | 577 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 578 | |
07893d4f | 579 | (define_insn "*cmpdi_ccu" |
9db1d521 | 580 | [(set (reg 33) |
e221ef54 UW |
581 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ") |
582 | (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))] | |
583 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" | |
07893d4f | 584 | "@ |
d40c829f | 585 | clgr\t%0,%1 |
575f7c2b | 586 | clg\t%0,%1 |
e221ef54 | 587 | # |
19b63d8e | 588 | #" |
e221ef54 | 589 | [(set_attr "op_type" "RRE,RXY,SS,SS")]) |
9db1d521 | 590 | |
07893d4f | 591 | (define_insn "*cmpsi_ccu" |
9db1d521 | 592 | [(set (reg 33) |
e221ef54 UW |
593 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ") |
594 | (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))] | |
595 | "s390_match_ccmode (insn, CCUmode)" | |
07893d4f | 596 | "@ |
d40c829f UW |
597 | clr\t%0,%1 |
598 | cl\t%0,%1 | |
575f7c2b | 599 | cly\t%0,%1 |
e221ef54 | 600 | # |
19b63d8e | 601 | #" |
e221ef54 | 602 | [(set_attr "op_type" "RR,RX,RXY,SS,SS")]) |
9db1d521 | 603 | |
07893d4f | 604 | (define_insn "*cmphi_ccu" |
9db1d521 | 605 | [(set (reg 33) |
e221ef54 UW |
606 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") |
607 | (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] | |
575f7c2b | 608 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 609 | && !register_operand (operands[1], HImode)" |
d3632d41 | 610 | "@ |
fc0ea003 UW |
611 | clm\t%0,3,%S1 |
612 | clmy\t%0,3,%S1 | |
e221ef54 | 613 | # |
19b63d8e | 614 | #" |
e221ef54 | 615 | [(set_attr "op_type" "RS,RSY,SS,SS")]) |
9db1d521 HP |
616 | |
617 | (define_insn "*cmpqi_ccu" | |
618 | [(set (reg 33) | |
e221ef54 UW |
619 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
620 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 621 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 622 | && !register_operand (operands[1], QImode)" |
d3632d41 | 623 | "@ |
fc0ea003 UW |
624 | clm\t%0,1,%S1 |
625 | clmy\t%0,1,%S1 | |
626 | cli\t%S0,%b1 | |
627 | cliy\t%S0,%b1 | |
e221ef54 | 628 | # |
19b63d8e | 629 | #" |
e221ef54 | 630 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) |
9db1d521 HP |
631 | |
632 | ||
19b63d8e UW |
633 | ; Block compare (CLC) instruction patterns. |
634 | ||
635 | (define_insn "*clc" | |
636 | [(set (reg 33) | |
d4f52f0e | 637 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
638 | (match_operand:BLK 1 "memory_operand" "Q"))) |
639 | (use (match_operand 2 "const_int_operand" "n"))] | |
640 | "s390_match_ccmode (insn, CCUmode) | |
641 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 642 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 643 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
644 | |
645 | (define_split | |
646 | [(set (reg 33) | |
647 | (compare (match_operand 0 "memory_operand" "") | |
648 | (match_operand 1 "memory_operand" "")))] | |
649 | "reload_completed | |
650 | && s390_match_ccmode (insn, CCUmode) | |
651 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
652 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
653 | [(parallel | |
654 | [(set (match_dup 0) (match_dup 1)) | |
655 | (use (match_dup 2))])] | |
656 | { | |
657 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
658 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
659 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
660 | ||
661 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
662 | operands[0], operands[1]); | |
663 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
664 | }) | |
665 | ||
666 | ||
9db1d521 HP |
667 | ; DF instructions |
668 | ||
669 | (define_insn "*cmpdf_ccs_0" | |
670 | [(set (reg 33) | |
671 | (compare (match_operand:DF 0 "register_operand" "f") | |
672 | (match_operand:DF 1 "const0_operand" "")))] | |
673 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 674 | "ltdbr\t%0,%0" |
077dab3b HP |
675 | [(set_attr "op_type" "RRE") |
676 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
677 | |
678 | (define_insn "*cmpdf_ccs_0_ibm" | |
679 | [(set (reg 33) | |
680 | (compare (match_operand:DF 0 "register_operand" "f") | |
681 | (match_operand:DF 1 "const0_operand" "")))] | |
682 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 683 | "ltdr\t%0,%0" |
077dab3b HP |
684 | [(set_attr "op_type" "RR") |
685 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
686 | |
687 | (define_insn "*cmpdf_ccs" | |
688 | [(set (reg 33) | |
689 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 690 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
691 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
692 | "@ | |
d40c829f UW |
693 | cdbr\t%0,%1 |
694 | cdb\t%0,%1" | |
ce50cae8 | 695 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 696 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
697 | |
698 | (define_insn "*cmpdf_ccs_ibm" | |
699 | [(set (reg 33) | |
700 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 701 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
702 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
703 | "@ | |
d40c829f UW |
704 | cdr\t%0,%1 |
705 | cd\t%0,%1" | |
9db1d521 | 706 | [(set_attr "op_type" "RR,RX") |
077dab3b | 707 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
708 | |
709 | ||
710 | ; SF instructions | |
711 | ||
712 | (define_insn "*cmpsf_ccs_0" | |
713 | [(set (reg 33) | |
714 | (compare (match_operand:SF 0 "register_operand" "f") | |
715 | (match_operand:SF 1 "const0_operand" "")))] | |
716 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 717 | "ltebr\t%0,%0" |
077dab3b HP |
718 | [(set_attr "op_type" "RRE") |
719 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
720 | |
721 | (define_insn "*cmpsf_ccs_0_ibm" | |
722 | [(set (reg 33) | |
723 | (compare (match_operand:SF 0 "register_operand" "f") | |
724 | (match_operand:SF 1 "const0_operand" "")))] | |
725 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 726 | "lter\t%0,%0" |
077dab3b HP |
727 | [(set_attr "op_type" "RR") |
728 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
729 | |
730 | (define_insn "*cmpsf_ccs" | |
731 | [(set (reg 33) | |
732 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 733 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
734 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
735 | "@ | |
d40c829f UW |
736 | cebr\t%0,%1 |
737 | ceb\t%0,%1" | |
077dab3b HP |
738 | [(set_attr "op_type" "RRE,RXE") |
739 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
740 | |
741 | (define_insn "*cmpsf_ccs" | |
742 | [(set (reg 33) | |
743 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 744 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
745 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
746 | "@ | |
d40c829f UW |
747 | cer\t%0,%1 |
748 | ce\t%0,%1" | |
077dab3b HP |
749 | [(set_attr "op_type" "RR,RX") |
750 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
751 | |
752 | ||
753 | ;; | |
754 | ;;- Move instructions. | |
755 | ;; | |
756 | ||
757 | ; | |
758 | ; movti instruction pattern(s). | |
759 | ; | |
760 | ||
761 | (define_insn "movti" | |
d3632d41 UW |
762 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
763 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
9db1d521 | 764 | "TARGET_64BIT" |
4023fb28 | 765 | "@ |
fc0ea003 UW |
766 | lmg\t%0,%N0,%S1 |
767 | stmg\t%1,%N1,%S0 | |
4023fb28 | 768 | # |
9b7c75b9 | 769 | # |
19b63d8e | 770 | #" |
b628bd8e UW |
771 | [(set_attr "op_type" "RSY,RSY,*,*,SS") |
772 | (set_attr "type" "lm,stm,*,*,*")]) | |
4023fb28 UW |
773 | |
774 | (define_split | |
775 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
776 | (match_operand:TI 1 "general_operand" ""))] | |
777 | "TARGET_64BIT && reload_completed | |
dc65c307 | 778 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
779 | [(set (match_dup 2) (match_dup 4)) |
780 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 781 | { |
dc65c307 UW |
782 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
783 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
784 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
785 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
786 | }) | |
787 | ||
788 | (define_split | |
789 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
790 | (match_operand:TI 1 "general_operand" ""))] | |
791 | "TARGET_64BIT && reload_completed | |
792 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
793 | [(set (match_dup 2) (match_dup 4)) | |
794 | (set (match_dup 3) (match_dup 5))] | |
795 | { | |
796 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
797 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
798 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
799 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
800 | }) | |
4023fb28 UW |
801 | |
802 | (define_split | |
803 | [(set (match_operand:TI 0 "register_operand" "") | |
804 | (match_operand:TI 1 "memory_operand" ""))] | |
805 | "TARGET_64BIT && reload_completed | |
806 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 807 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
808 | { |
809 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
810 | s390_load_address (addr, XEXP (operands[1], 0)); | |
811 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
812 | }) |
813 | ||
814 | (define_expand "reload_outti" | |
9c3c3dcc | 815 | [(parallel [(match_operand:TI 0 "" "") |
dc65c307 UW |
816 | (match_operand:TI 1 "register_operand" "d") |
817 | (match_operand:DI 2 "register_operand" "=&a")])] | |
818 | "TARGET_64BIT" | |
819 | { | |
9c3c3dcc | 820 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 821 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
822 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
823 | emit_move_insn (operands[0], operands[1]); | |
824 | DONE; | |
825 | }) | |
9db1d521 HP |
826 | |
827 | ; | |
828 | ; movdi instruction pattern(s). | |
829 | ; | |
830 | ||
9db1d521 HP |
831 | (define_expand "movdi" |
832 | [(set (match_operand:DI 0 "general_operand" "") | |
833 | (match_operand:DI 1 "general_operand" ""))] | |
834 | "" | |
9db1d521 | 835 | { |
fd3cd001 UW |
836 | /* Handle symbolic constants. */ |
837 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
838 | emit_symbolic_move (operands); | |
10bbf137 | 839 | }) |
9db1d521 | 840 | |
4023fb28 UW |
841 | (define_insn "*movdi_larl" |
842 | [(set (match_operand:DI 0 "register_operand" "=d") | |
843 | (match_operand:DI 1 "larl_operand" "X"))] | |
844 | "TARGET_64BIT | |
8e509cf9 | 845 | && !FP_REG_P (operands[0])" |
d40c829f | 846 | "larl\t%0,%1" |
4023fb28 | 847 | [(set_attr "op_type" "RIL") |
077dab3b | 848 | (set_attr "type" "larl")]) |
4023fb28 | 849 | |
9db1d521 | 850 | (define_insn "*movdi_64" |
2f7e5a0d | 851 | [(set (match_operand:DI 0 "nonimmediate_operand" |
c5aa1d12 | 852 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 853 | (match_operand:DI 1 "general_operand" |
c5aa1d12 | 854 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
9db1d521 HP |
855 | "TARGET_64BIT" |
856 | "@ | |
f19a9af7 AK |
857 | lghi\t%0,%h1 |
858 | llihh\t%0,%i1 | |
859 | llihl\t%0,%i1 | |
860 | llilh\t%0,%i1 | |
861 | llill\t%0,%i1 | |
862 | lay\t%0,%a1 | |
d40c829f UW |
863 | lgr\t%0,%1 |
864 | lg\t%0,%1 | |
865 | stg\t%1,%0 | |
866 | ldr\t%0,%1 | |
867 | ld\t%0,%1 | |
868 | ldy\t%0,%1 | |
869 | std\t%1,%0 | |
870 | stdy\t%1,%0 | |
c5aa1d12 UW |
871 | # |
872 | # | |
873 | stam\t%1,%N1,%S0 | |
874 | lam\t%0,%N0,%S1 | |
19b63d8e | 875 | #" |
b628bd8e UW |
876 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, |
877 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
878 | (set_attr "type" "*,*,*,*,*,la,lr,load,store, | |
879 | floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")]) | |
c5aa1d12 UW |
880 | |
881 | (define_split | |
882 | [(set (match_operand:DI 0 "register_operand" "") | |
883 | (match_operand:DI 1 "register_operand" ""))] | |
884 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
885 | [(set (match_dup 2) (match_dup 3)) | |
886 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
887 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
888 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
889 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
890 | ||
891 | (define_split | |
892 | [(set (match_operand:DI 0 "register_operand" "") | |
893 | (match_operand:DI 1 "register_operand" ""))] | |
894 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
895 | && dead_or_set_p (insn, operands[1])" | |
896 | [(set (match_dup 3) (match_dup 2)) | |
897 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
898 | (set (match_dup 4) (match_dup 2))] | |
899 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
900 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
901 | ||
902 | (define_split | |
903 | [(set (match_operand:DI 0 "register_operand" "") | |
904 | (match_operand:DI 1 "register_operand" ""))] | |
905 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
906 | && !dead_or_set_p (insn, operands[1])" | |
907 | [(set (match_dup 3) (match_dup 2)) | |
908 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
909 | (set (match_dup 4) (match_dup 2)) | |
910 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
911 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
912 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
913 | |
914 | (define_insn "*movdi_31" | |
d3632d41 UW |
915 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
916 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
9db1d521 | 917 | "!TARGET_64BIT" |
4023fb28 | 918 | "@ |
fc0ea003 UW |
919 | lm\t%0,%N0,%S1 |
920 | stm\t%1,%N1,%S0 | |
4023fb28 UW |
921 | # |
922 | # | |
d40c829f UW |
923 | ldr\t%0,%1 |
924 | ld\t%0,%1 | |
925 | ldy\t%0,%1 | |
926 | std\t%1,%0 | |
927 | stdy\t%1,%0 | |
19b63d8e | 928 | #" |
b628bd8e UW |
929 | [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS") |
930 | (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")]) | |
4023fb28 UW |
931 | |
932 | (define_split | |
933 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
934 | (match_operand:DI 1 "general_operand" ""))] | |
935 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 936 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
937 | [(set (match_dup 2) (match_dup 4)) |
938 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 939 | { |
dc65c307 UW |
940 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
941 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
942 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
943 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
944 | }) | |
945 | ||
946 | (define_split | |
947 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
948 | (match_operand:DI 1 "general_operand" ""))] | |
949 | "!TARGET_64BIT && reload_completed | |
950 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
951 | [(set (match_dup 2) (match_dup 4)) | |
952 | (set (match_dup 3) (match_dup 5))] | |
953 | { | |
954 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
955 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
956 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
957 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
958 | }) | |
9db1d521 | 959 | |
4023fb28 UW |
960 | (define_split |
961 | [(set (match_operand:DI 0 "register_operand" "") | |
962 | (match_operand:DI 1 "memory_operand" ""))] | |
963 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 964 | && !FP_REG_P (operands[0]) |
4023fb28 | 965 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 966 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
967 | { |
968 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
969 | s390_load_address (addr, XEXP (operands[1], 0)); | |
970 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
971 | }) |
972 | ||
973 | (define_expand "reload_outdi" | |
9c3c3dcc | 974 | [(parallel [(match_operand:DI 0 "" "") |
dc65c307 UW |
975 | (match_operand:DI 1 "register_operand" "d") |
976 | (match_operand:SI 2 "register_operand" "=&a")])] | |
977 | "!TARGET_64BIT" | |
978 | { | |
9c3c3dcc | 979 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 980 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
981 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
982 | emit_move_insn (operands[0], operands[1]); | |
983 | DONE; | |
984 | }) | |
9db1d521 | 985 | |
84817c5d UW |
986 | (define_peephole2 |
987 | [(set (match_operand:DI 0 "register_operand" "") | |
988 | (mem:DI (match_operand 1 "address_operand" "")))] | |
989 | "TARGET_64BIT | |
990 | && !FP_REG_P (operands[0]) | |
991 | && GET_CODE (operands[1]) == SYMBOL_REF | |
992 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
993 | && get_pool_mode (operands[1]) == DImode | |
994 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
995 | [(set (match_dup 0) (match_dup 2))] | |
996 | "operands[2] = get_pool_constant (operands[1]);") | |
997 | ||
7bdff56f UW |
998 | (define_insn "*la_64" |
999 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1000 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1001 | "TARGET_64BIT" | |
1002 | "@ | |
1003 | la\t%0,%a1 | |
1004 | lay\t%0,%a1" | |
1005 | [(set_attr "op_type" "RX,RXY") | |
1006 | (set_attr "type" "la")]) | |
1007 | ||
1008 | (define_peephole2 | |
1009 | [(parallel | |
1010 | [(set (match_operand:DI 0 "register_operand" "") | |
1011 | (match_operand:QI 1 "address_operand" "")) | |
1012 | (clobber (reg:CC 33))])] | |
1013 | "TARGET_64BIT | |
e1d5ee28 | 1014 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1015 | [(set (match_dup 0) (match_dup 1))] |
1016 | "") | |
1017 | ||
1018 | (define_peephole2 | |
1019 | [(set (match_operand:DI 0 "register_operand" "") | |
1020 | (match_operand:DI 1 "register_operand" "")) | |
1021 | (parallel | |
1022 | [(set (match_dup 0) | |
1023 | (plus:DI (match_dup 0) | |
1024 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
1025 | (clobber (reg:CC 33))])] | |
1026 | "TARGET_64BIT | |
1027 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1028 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1029 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1030 | "") | |
1031 | ||
1032 | (define_expand "reload_indi" | |
1033 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1034 | (match_operand:DI 1 "s390_plus_operand" "") | |
1035 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1036 | "TARGET_64BIT" | |
1037 | { | |
1038 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1039 | DONE; | |
1040 | }) | |
1041 | ||
9db1d521 HP |
1042 | ; |
1043 | ; movsi instruction pattern(s). | |
1044 | ; | |
1045 | ||
9db1d521 HP |
1046 | (define_expand "movsi" |
1047 | [(set (match_operand:SI 0 "general_operand" "") | |
1048 | (match_operand:SI 1 "general_operand" ""))] | |
1049 | "" | |
9db1d521 | 1050 | { |
fd3cd001 UW |
1051 | /* Handle symbolic constants. */ |
1052 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1053 | emit_symbolic_move (operands); | |
10bbf137 | 1054 | }) |
9db1d521 | 1055 | |
9e8327e3 UW |
1056 | (define_insn "*movsi_larl" |
1057 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1058 | (match_operand:SI 1 "larl_operand" "X"))] | |
1059 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1060 | && !FP_REG_P (operands[0])" | |
1061 | "larl\t%0,%1" | |
1062 | [(set_attr "op_type" "RIL") | |
1063 | (set_attr "type" "larl")]) | |
1064 | ||
f19a9af7 | 1065 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1066 | [(set (match_operand:SI 0 "nonimmediate_operand" |
c5aa1d12 | 1067 | "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 1068 | (match_operand:SI 1 "general_operand" |
c5aa1d12 | 1069 | "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
f19a9af7 | 1070 | "TARGET_ZARCH" |
9db1d521 | 1071 | "@ |
f19a9af7 AK |
1072 | lhi\t%0,%h1 |
1073 | llilh\t%0,%i1 | |
1074 | llill\t%0,%i1 | |
1075 | lay\t%0,%a1 | |
d40c829f UW |
1076 | lr\t%0,%1 |
1077 | l\t%0,%1 | |
1078 | ly\t%0,%1 | |
1079 | st\t%1,%0 | |
1080 | sty\t%1,%0 | |
1081 | ler\t%0,%1 | |
1082 | le\t%0,%1 | |
1083 | ley\t%0,%1 | |
1084 | ste\t%1,%0 | |
1085 | stey\t%1,%0 | |
c5aa1d12 UW |
1086 | ear\t%0,%1 |
1087 | sar\t%0,%1 | |
1088 | stam\t%1,%1,%S0 | |
1089 | lam\t%0,%0,%S1 | |
19b63d8e | 1090 | #" |
b628bd8e UW |
1091 | [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY, |
1092 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") | |
1093 | (set_attr "type" "*,*,*,la,lr,load,load,store,store, | |
1094 | floads,floads,floads,fstores,fstores,*,*,*,*,*")]) | |
f19a9af7 AK |
1095 | |
1096 | (define_insn "*movsi_esa" | |
c5aa1d12 UW |
1097 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") |
1098 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))] | |
f19a9af7 AK |
1099 | "!TARGET_ZARCH" |
1100 | "@ | |
1101 | lhi\t%0,%h1 | |
1102 | lr\t%0,%1 | |
1103 | l\t%0,%1 | |
1104 | st\t%1,%0 | |
1105 | ler\t%0,%1 | |
1106 | le\t%0,%1 | |
1107 | ste\t%1,%0 | |
c5aa1d12 UW |
1108 | ear\t%0,%1 |
1109 | sar\t%0,%1 | |
1110 | stam\t%1,%1,%S0 | |
1111 | lam\t%0,%0,%S1 | |
19b63d8e | 1112 | #" |
c5aa1d12 | 1113 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") |
b628bd8e | 1114 | (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")]) |
9db1d521 | 1115 | |
84817c5d UW |
1116 | (define_peephole2 |
1117 | [(set (match_operand:SI 0 "register_operand" "") | |
1118 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1119 | "!FP_REG_P (operands[0]) | |
1120 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1121 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1122 | && get_pool_mode (operands[1]) == SImode | |
1123 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1124 | [(set (match_dup 0) (match_dup 2))] | |
1125 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1126 | |
7bdff56f UW |
1127 | (define_insn "*la_31" |
1128 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1129 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1130 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1131 | "@ | |
1132 | la\t%0,%a1 | |
1133 | lay\t%0,%a1" | |
1134 | [(set_attr "op_type" "RX,RXY") | |
1135 | (set_attr "type" "la")]) | |
1136 | ||
1137 | (define_peephole2 | |
1138 | [(parallel | |
1139 | [(set (match_operand:SI 0 "register_operand" "") | |
1140 | (match_operand:QI 1 "address_operand" "")) | |
1141 | (clobber (reg:CC 33))])] | |
1142 | "!TARGET_64BIT | |
e1d5ee28 | 1143 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1144 | [(set (match_dup 0) (match_dup 1))] |
1145 | "") | |
1146 | ||
1147 | (define_peephole2 | |
1148 | [(set (match_operand:SI 0 "register_operand" "") | |
1149 | (match_operand:SI 1 "register_operand" "")) | |
1150 | (parallel | |
1151 | [(set (match_dup 0) | |
1152 | (plus:SI (match_dup 0) | |
1153 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
1154 | (clobber (reg:CC 33))])] | |
1155 | "!TARGET_64BIT | |
1156 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1157 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1158 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1159 | "") | |
1160 | ||
1161 | (define_insn "*la_31_and" | |
1162 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1163 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1164 | (const_int 2147483647)))] | |
1165 | "!TARGET_64BIT" | |
1166 | "@ | |
1167 | la\t%0,%a1 | |
1168 | lay\t%0,%a1" | |
1169 | [(set_attr "op_type" "RX,RXY") | |
1170 | (set_attr "type" "la")]) | |
1171 | ||
1172 | (define_insn_and_split "*la_31_and_cc" | |
1173 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1174 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1175 | (const_int 2147483647))) | |
1176 | (clobber (reg:CC 33))] | |
1177 | "!TARGET_64BIT" | |
1178 | "#" | |
1179 | "&& reload_completed" | |
1180 | [(set (match_dup 0) | |
1181 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1182 | "" | |
1183 | [(set_attr "op_type" "RX") | |
1184 | (set_attr "type" "la")]) | |
1185 | ||
1186 | (define_insn "force_la_31" | |
1187 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1188 | (match_operand:QI 1 "address_operand" "U,W")) | |
1189 | (use (const_int 0))] | |
1190 | "!TARGET_64BIT" | |
1191 | "@ | |
1192 | la\t%0,%a1 | |
1193 | lay\t%0,%a1" | |
1194 | [(set_attr "op_type" "RX") | |
1195 | (set_attr "type" "la")]) | |
1196 | ||
1197 | (define_expand "reload_insi" | |
1198 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1199 | (match_operand:SI 1 "s390_plus_operand" "") | |
1200 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1201 | "!TARGET_64BIT" | |
1202 | { | |
1203 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1204 | DONE; | |
1205 | }) | |
1206 | ||
9db1d521 HP |
1207 | ; |
1208 | ; movhi instruction pattern(s). | |
1209 | ; | |
1210 | ||
02ed3c5e UW |
1211 | (define_expand "movhi" |
1212 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1213 | (match_operand:HI 1 "general_operand" ""))] | |
1214 | "" | |
1215 | { | |
2f7e5a0d | 1216 | /* Make it explicit that loading a register from memory |
02ed3c5e UW |
1217 | always sign-extends (at least) to SImode. */ |
1218 | if (optimize && !no_new_pseudos | |
1219 | && register_operand (operands[0], VOIDmode) | |
8fff4fc1 | 1220 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1221 | { |
1222 | rtx tmp = gen_reg_rtx (SImode); | |
1223 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1224 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1225 | operands[1] = gen_lowpart (HImode, tmp); | |
1226 | } | |
1227 | }) | |
1228 | ||
1229 | (define_insn "*movhi" | |
d3632d41 UW |
1230 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1231 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1232 | "" |
1233 | "@ | |
d40c829f UW |
1234 | lr\t%0,%1 |
1235 | lhi\t%0,%h1 | |
1236 | lh\t%0,%1 | |
1237 | lhy\t%0,%1 | |
1238 | sth\t%1,%0 | |
1239 | sthy\t%1,%0 | |
19b63d8e | 1240 | #" |
d3632d41 | 1241 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
b628bd8e | 1242 | (set_attr "type" "lr,*,*,*,store,store,*")]) |
9db1d521 | 1243 | |
84817c5d UW |
1244 | (define_peephole2 |
1245 | [(set (match_operand:HI 0 "register_operand" "") | |
1246 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1247 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1248 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1249 | && get_pool_mode (operands[1]) == HImode | |
1250 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1251 | [(set (match_dup 0) (match_dup 2))] | |
1252 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1253 | |
9db1d521 HP |
1254 | ; |
1255 | ; movqi instruction pattern(s). | |
1256 | ; | |
1257 | ||
02ed3c5e UW |
1258 | (define_expand "movqi" |
1259 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1260 | (match_operand:QI 1 "general_operand" ""))] | |
1261 | "" | |
1262 | { | |
c19ec8f9 | 1263 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1264 | is just as fast as a QImode load. */ |
c19ec8f9 | 1265 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1266 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1267 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1268 | { |
c19ec8f9 UW |
1269 | rtx tmp = gen_reg_rtx (word_mode); |
1270 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1271 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1272 | operands[1] = gen_lowpart (QImode, tmp); | |
1273 | } | |
1274 | }) | |
4023fb28 | 1275 | |
02ed3c5e | 1276 | (define_insn "*movqi" |
d3632d41 UW |
1277 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1278 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1279 | "" |
1280 | "@ | |
d40c829f UW |
1281 | lr\t%0,%1 |
1282 | lhi\t%0,%b1 | |
1283 | ic\t%0,%1 | |
1284 | icy\t%0,%1 | |
1285 | stc\t%1,%0 | |
1286 | stcy\t%1,%0 | |
fc0ea003 UW |
1287 | mvi\t%S0,%b1 |
1288 | mviy\t%S0,%b1 | |
19b63d8e | 1289 | #" |
d3632d41 | 1290 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
b628bd8e | 1291 | (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) |
9db1d521 | 1292 | |
84817c5d UW |
1293 | (define_peephole2 |
1294 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1295 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1296 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1297 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1298 | && get_pool_mode (operands[1]) == QImode | |
1299 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1300 | [(set (match_dup 0) (match_dup 2))] | |
1301 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1302 | |
9db1d521 | 1303 | ; |
05b9aaaa | 1304 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1305 | ; |
1306 | ||
1307 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1308 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1309 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1310 | "" |
d3632d41 | 1311 | "@ |
d40c829f UW |
1312 | ic\t%0,%1 |
1313 | icy\t%0,%1" | |
d3632d41 | 1314 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1315 | |
1316 | ; | |
1317 | ; movstricthi instruction pattern(s). | |
1318 | ; | |
1319 | ||
1320 | (define_insn "*movstricthi" | |
d3632d41 | 1321 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1322 | (match_operand:HI 1 "memory_operand" "Q,S")) |
9db1d521 HP |
1323 | (clobber (reg:CC 33))] |
1324 | "" | |
d3632d41 | 1325 | "@ |
fc0ea003 UW |
1326 | icm\t%0,3,%S1 |
1327 | icmy\t%0,3,%S1" | |
d3632d41 | 1328 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1329 | |
1330 | ; | |
1331 | ; movstrictsi instruction pattern(s). | |
1332 | ; | |
1333 | ||
05b9aaaa | 1334 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1335 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1336 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1337 | "TARGET_64BIT" |
1338 | "@ | |
d40c829f UW |
1339 | lr\t%0,%1 |
1340 | l\t%0,%1 | |
c5aa1d12 UW |
1341 | ly\t%0,%1 |
1342 | ear\t%0,%1" | |
1343 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
1344 | (set_attr "type" "lr,load,load,*")]) | |
9db1d521 HP |
1345 | |
1346 | ; | |
1347 | ; movdf instruction pattern(s). | |
1348 | ; | |
1349 | ||
1350 | (define_expand "movdf" | |
1351 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1352 | (match_operand:DF 1 "general_operand" ""))] | |
1353 | "" | |
13c025c1 | 1354 | "") |
9db1d521 HP |
1355 | |
1356 | (define_insn "*movdf_64" | |
d3632d41 UW |
1357 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") |
1358 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1359 | "TARGET_64BIT" |
9db1d521 | 1360 | "@ |
d40c829f UW |
1361 | ldr\t%0,%1 |
1362 | ld\t%0,%1 | |
1363 | ldy\t%0,%1 | |
1364 | std\t%1,%0 | |
1365 | stdy\t%1,%0 | |
1366 | lgr\t%0,%1 | |
1367 | lg\t%0,%1 | |
1368 | stg\t%1,%0 | |
19b63d8e | 1369 | #" |
d3632d41 | 1370 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
b628bd8e | 1371 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")]) |
9db1d521 HP |
1372 | |
1373 | (define_insn "*movdf_31" | |
d3632d41 UW |
1374 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") |
1375 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] | |
4023fb28 | 1376 | "!TARGET_64BIT" |
9db1d521 | 1377 | "@ |
d40c829f UW |
1378 | ldr\t%0,%1 |
1379 | ld\t%0,%1 | |
1380 | ldy\t%0,%1 | |
1381 | std\t%1,%0 | |
1382 | stdy\t%1,%0 | |
fc0ea003 UW |
1383 | lm\t%0,%N0,%S1 |
1384 | stm\t%1,%N1,%S0 | |
4023fb28 | 1385 | # |
9b7c75b9 | 1386 | # |
19b63d8e | 1387 | #" |
b628bd8e UW |
1388 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS") |
1389 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")]) | |
4023fb28 UW |
1390 | |
1391 | (define_split | |
1392 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1393 | (match_operand:DF 1 "general_operand" ""))] | |
1394 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1395 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1396 | [(set (match_dup 2) (match_dup 4)) |
1397 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1398 | { |
dc65c307 UW |
1399 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1400 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1401 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1402 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1403 | }) | |
1404 | ||
1405 | (define_split | |
1406 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1407 | (match_operand:DF 1 "general_operand" ""))] | |
1408 | "!TARGET_64BIT && reload_completed | |
1409 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1410 | [(set (match_dup 2) (match_dup 4)) | |
1411 | (set (match_dup 3) (match_dup 5))] | |
1412 | { | |
1413 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1414 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1415 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1416 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1417 | }) | |
9db1d521 | 1418 | |
4023fb28 UW |
1419 | (define_split |
1420 | [(set (match_operand:DF 0 "register_operand" "") | |
1421 | (match_operand:DF 1 "memory_operand" ""))] | |
1422 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1423 | && !FP_REG_P (operands[0]) |
4023fb28 | 1424 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1425 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1426 | { |
1427 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1428 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1429 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1430 | }) |
1431 | ||
1432 | (define_expand "reload_outdf" | |
9c3c3dcc | 1433 | [(parallel [(match_operand:DF 0 "" "") |
dc65c307 UW |
1434 | (match_operand:DF 1 "register_operand" "d") |
1435 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1436 | "!TARGET_64BIT" | |
1437 | { | |
9c3c3dcc | 1438 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1439 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1440 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1441 | emit_move_insn (operands[0], operands[1]); | |
1442 | DONE; | |
1443 | }) | |
9db1d521 HP |
1444 | |
1445 | ; | |
1446 | ; movsf instruction pattern(s). | |
1447 | ; | |
1448 | ||
13c025c1 | 1449 | (define_insn "movsf" |
d3632d41 UW |
1450 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") |
1451 | (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1452 | "" |
9db1d521 | 1453 | "@ |
d40c829f UW |
1454 | ler\t%0,%1 |
1455 | le\t%0,%1 | |
1456 | ley\t%0,%1 | |
1457 | ste\t%1,%0 | |
1458 | stey\t%1,%0 | |
1459 | lr\t%0,%1 | |
1460 | l\t%0,%1 | |
1461 | ly\t%0,%1 | |
1462 | st\t%1,%0 | |
1463 | sty\t%1,%0 | |
19b63d8e | 1464 | #" |
d3632d41 | 1465 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
b628bd8e UW |
1466 | (set_attr "type" "floads,floads,floads,fstores,fstores, |
1467 | lr,load,load,store,store,*")]) | |
4023fb28 | 1468 | |
9dc62c00 AK |
1469 | ; |
1470 | ; movcc instruction pattern | |
1471 | ; | |
1472 | ||
1473 | (define_insn "movcc" | |
1474 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
1475 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
1476 | "" | |
1477 | "@ | |
1478 | lr\t%0,%1 | |
1479 | tmh\t%1,12288 | |
1480 | ipm\t%0 | |
1481 | st\t%0,%1 | |
1482 | sty\t%0,%1 | |
1483 | l\t%1,%0 | |
1484 | ly\t%1,%0" | |
8dd3b235 AK |
1485 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
1486 | (set_attr "type" "lr,*,*,store,store,load,load")]) | |
9dc62c00 | 1487 | |
19b63d8e UW |
1488 | ; |
1489 | ; Block move (MVC) patterns. | |
1490 | ; | |
1491 | ||
1492 | (define_insn "*mvc" | |
1493 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
1494 | (match_operand:BLK 1 "memory_operand" "Q")) | |
1495 | (use (match_operand 2 "const_int_operand" "n"))] | |
1496 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1497 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 1498 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1499 | |
1500 | (define_split | |
1501 | [(set (match_operand 0 "memory_operand" "") | |
1502 | (match_operand 1 "memory_operand" ""))] | |
1503 | "reload_completed | |
1504 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1505 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1506 | [(parallel | |
1507 | [(set (match_dup 0) (match_dup 1)) | |
1508 | (use (match_dup 2))])] | |
1509 | { | |
1510 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1511 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1512 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1513 | }) | |
1514 | ||
1515 | (define_peephole2 | |
1516 | [(parallel | |
1517 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1518 | (match_operand:BLK 1 "memory_operand" "")) | |
1519 | (use (match_operand 2 "const_int_operand" ""))]) | |
1520 | (parallel | |
1521 | [(set (match_operand:BLK 3 "memory_operand" "") | |
1522 | (match_operand:BLK 4 "memory_operand" "")) | |
1523 | (use (match_operand 5 "const_int_operand" ""))])] | |
1524 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
1525 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
1526 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
1527 | [(parallel | |
1528 | [(set (match_dup 6) (match_dup 7)) | |
1529 | (use (match_dup 8))])] | |
1530 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
1531 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
1532 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
1533 | ||
1534 | ||
9db1d521 HP |
1535 | ; |
1536 | ; load_multiple pattern(s). | |
1537 | ; | |
22ea6b4f UW |
1538 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1539 | ; we currently support load_multiple/store_multiple only after reload. | |
1540 | ; | |
9db1d521 HP |
1541 | |
1542 | (define_expand "load_multiple" | |
1543 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1544 | (match_operand 1 "" "")) | |
1545 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1546 | "reload_completed" |
9db1d521 | 1547 | { |
c19ec8f9 | 1548 | enum machine_mode mode; |
9db1d521 HP |
1549 | int regno; |
1550 | int count; | |
1551 | rtx from; | |
4023fb28 | 1552 | int i, off; |
9db1d521 HP |
1553 | |
1554 | /* Support only loading a constant number of fixed-point registers from | |
1555 | memory and only bother with this if more than two */ | |
1556 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1557 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1558 | || INTVAL (operands[2]) > 16 |
1559 | || GET_CODE (operands[1]) != MEM | |
1560 | || GET_CODE (operands[0]) != REG | |
1561 | || REGNO (operands[0]) >= 16) | |
1562 | FAIL; | |
1563 | ||
1564 | count = INTVAL (operands[2]); | |
1565 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1566 | mode = GET_MODE (operands[0]); |
1567 | if (mode != SImode && mode != word_mode) | |
1568 | FAIL; | |
9db1d521 HP |
1569 | |
1570 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1571 | if (no_new_pseudos) |
1572 | { | |
1573 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1574 | { | |
1575 | from = XEXP (operands[1], 0); | |
1576 | off = 0; | |
1577 | } | |
1578 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1579 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1580 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1581 | { | |
1582 | from = XEXP (XEXP (operands[1], 0), 0); | |
1583 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1584 | } | |
1585 | else | |
1586 | FAIL; | |
4023fb28 UW |
1587 | } |
1588 | else | |
1589 | { | |
1590 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1591 | off = 0; | |
1592 | } | |
9db1d521 HP |
1593 | |
1594 | for (i = 0; i < count; i++) | |
1595 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1596 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1597 | change_address (operands[1], mode, | |
1598 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1599 | }) |
9db1d521 HP |
1600 | |
1601 | (define_insn "*load_multiple_di" | |
1602 | [(match_parallel 0 "load_multiple_operation" | |
1603 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1604 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1605 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1606 | { |
1607 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1608 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1609 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 1610 | } |
d3632d41 | 1611 | [(set_attr "op_type" "RSY") |
4023fb28 | 1612 | (set_attr "type" "lm")]) |
9db1d521 HP |
1613 | |
1614 | (define_insn "*load_multiple_si" | |
1615 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1616 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1617 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1618 | "reload_completed" |
9db1d521 HP |
1619 | { |
1620 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1621 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1622 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 1623 | } |
d3632d41 | 1624 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1625 | (set_attr "type" "lm")]) |
9db1d521 HP |
1626 | |
1627 | ; | |
c7453384 | 1628 | ; store multiple pattern(s). |
9db1d521 HP |
1629 | ; |
1630 | ||
1631 | (define_expand "store_multiple" | |
1632 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1633 | (match_operand 1 "" "")) | |
1634 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1635 | "reload_completed" |
9db1d521 | 1636 | { |
c19ec8f9 | 1637 | enum machine_mode mode; |
9db1d521 HP |
1638 | int regno; |
1639 | int count; | |
1640 | rtx to; | |
4023fb28 | 1641 | int i, off; |
9db1d521 HP |
1642 | |
1643 | /* Support only storing a constant number of fixed-point registers to | |
1644 | memory and only bother with this if more than two. */ | |
1645 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1646 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1647 | || INTVAL (operands[2]) > 16 |
1648 | || GET_CODE (operands[0]) != MEM | |
1649 | || GET_CODE (operands[1]) != REG | |
1650 | || REGNO (operands[1]) >= 16) | |
1651 | FAIL; | |
1652 | ||
1653 | count = INTVAL (operands[2]); | |
1654 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1655 | mode = GET_MODE (operands[1]); |
1656 | if (mode != SImode && mode != word_mode) | |
1657 | FAIL; | |
9db1d521 HP |
1658 | |
1659 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1660 | |
1661 | if (no_new_pseudos) | |
1662 | { | |
1663 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1664 | { | |
1665 | to = XEXP (operands[0], 0); | |
1666 | off = 0; | |
1667 | } | |
1668 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1669 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1670 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1671 | { | |
1672 | to = XEXP (XEXP (operands[0], 0), 0); | |
1673 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1674 | } | |
1675 | else | |
1676 | FAIL; | |
4023fb28 | 1677 | } |
c7453384 | 1678 | else |
4023fb28 UW |
1679 | { |
1680 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1681 | off = 0; | |
1682 | } | |
9db1d521 HP |
1683 | |
1684 | for (i = 0; i < count; i++) | |
1685 | XVECEXP (operands[3], 0, i) | |
1686 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1687 | change_address (operands[0], mode, |
1688 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1689 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1690 | }) |
9db1d521 HP |
1691 | |
1692 | (define_insn "*store_multiple_di" | |
1693 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1694 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1695 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1696 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1697 | { |
1698 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1699 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1700 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 1701 | } |
d3632d41 | 1702 | [(set_attr "op_type" "RSY") |
4023fb28 | 1703 | (set_attr "type" "stm")]) |
9db1d521 HP |
1704 | |
1705 | ||
1706 | (define_insn "*store_multiple_si" | |
1707 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1708 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1709 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1710 | "reload_completed" |
9db1d521 HP |
1711 | { |
1712 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1713 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1714 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 1715 | } |
d3632d41 | 1716 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1717 | (set_attr "type" "stm")]) |
9db1d521 HP |
1718 | |
1719 | ;; | |
1720 | ;; String instructions. | |
1721 | ;; | |
1722 | ||
9bb86f41 UW |
1723 | (define_insn "*execute" |
1724 | [(match_parallel 0 "" | |
1725 | [(unspec [(match_operand 1 "register_operand" "a") | |
1726 | (match_operand:BLK 2 "memory_operand" "R") | |
1727 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
1728 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
1729 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
1730 | "ex\t%1,%2" | |
29a74354 UW |
1731 | [(set_attr "op_type" "RX") |
1732 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
1733 | |
1734 | ||
91d39d71 UW |
1735 | ; |
1736 | ; strlenM instruction pattern(s). | |
1737 | ; | |
1738 | ||
9db2f16d | 1739 | (define_expand "strlen<mode>" |
91d39d71 | 1740 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) |
2f7e5a0d | 1741 | (parallel |
91d39d71 | 1742 | [(set (match_dup 4) |
9db2f16d | 1743 | (unspec:P [(const_int 0) |
91d39d71 UW |
1744 | (match_operand:BLK 1 "memory_operand" "") |
1745 | (reg:QI 0) | |
1746 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
9db2f16d | 1747 | (clobber (scratch:P)) |
91d39d71 UW |
1748 | (clobber (reg:CC 33))]) |
1749 | (parallel | |
9db2f16d AS |
1750 | [(set (match_operand:P 0 "register_operand" "") |
1751 | (minus:P (match_dup 4) (match_dup 5))) | |
91d39d71 | 1752 | (clobber (reg:CC 33))])] |
9db2f16d | 1753 | "" |
91d39d71 | 1754 | { |
9db2f16d AS |
1755 | operands[4] = gen_reg_rtx (Pmode); |
1756 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
1757 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
1758 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1759 | }) | |
1760 | ||
9db2f16d AS |
1761 | (define_insn "*strlen<mode>" |
1762 | [(set (match_operand:P 0 "register_operand" "=a") | |
1763 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
1764 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
91d39d71 UW |
1765 | (reg:QI 0) |
1766 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
9db2f16d | 1767 | (clobber (match_scratch:P 1 "=a")) |
2f7e5a0d | 1768 | (clobber (reg:CC 33))] |
9db2f16d | 1769 | "" |
91d39d71 | 1770 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
1771 | [(set_attr "length" "8") |
1772 | (set_attr "type" "vs")]) | |
91d39d71 | 1773 | |
9db1d521 | 1774 | ; |
70128ad9 | 1775 | ; movmemM instruction pattern(s). |
9db1d521 HP |
1776 | ; |
1777 | ||
9db2f16d | 1778 | (define_expand "movmem<mode>" |
a41c6c53 UW |
1779 | [(set (match_operand:BLK 0 "memory_operand" "") |
1780 | (match_operand:BLK 1 "memory_operand" "")) | |
9db2f16d | 1781 | (use (match_operand:GPR 2 "general_operand" "")) |
a41c6c53 UW |
1782 | (match_operand 3 "" "")] |
1783 | "" | |
70128ad9 | 1784 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 1785 | |
ecbe845e UW |
1786 | ; Move a block that is up to 256 bytes in length. |
1787 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1788 | |
70128ad9 | 1789 | (define_expand "movmem_short" |
b9404c99 UW |
1790 | [(parallel |
1791 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1792 | (match_operand:BLK 1 "memory_operand" "")) | |
1793 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 1794 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
1795 | (clobber (match_dup 3))])] |
1796 | "" | |
1797 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 1798 | |
70128ad9 | 1799 | (define_insn "*movmem_short" |
9bb86f41 UW |
1800 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
1801 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) | |
1802 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
1803 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
1804 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 1805 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
1806 | && GET_MODE (operands[4]) == Pmode" |
1807 | "#" | |
b628bd8e | 1808 | [(set_attr "type" "cs")]) |
ecbe845e | 1809 | |
9bb86f41 UW |
1810 | (define_split |
1811 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1812 | (match_operand:BLK 1 "memory_operand" "")) | |
1813 | (use (match_operand 2 "const_int_operand" "")) | |
1814 | (use (match_operand 3 "immediate_operand" "")) | |
1815 | (clobber (scratch))] | |
1816 | "reload_completed" | |
1817 | [(parallel | |
1818 | [(set (match_dup 0) (match_dup 1)) | |
1819 | (use (match_dup 2))])] | |
1820 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 1821 | |
9bb86f41 UW |
1822 | (define_split |
1823 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1824 | (match_operand:BLK 1 "memory_operand" "")) | |
1825 | (use (match_operand 2 "register_operand" "")) | |
1826 | (use (match_operand 3 "memory_operand" "")) | |
1827 | (clobber (scratch))] | |
1828 | "reload_completed" | |
1829 | [(parallel | |
1830 | [(unspec [(match_dup 2) (match_dup 3) | |
1831 | (const_int 0)] UNSPEC_EXECUTE) | |
1832 | (set (match_dup 0) (match_dup 1)) | |
1833 | (use (const_int 1))])] | |
1834 | "") | |
1835 | ||
1836 | (define_split | |
1837 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1838 | (match_operand:BLK 1 "memory_operand" "")) | |
1839 | (use (match_operand 2 "register_operand" "")) | |
1840 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
1841 | (clobber (match_operand 3 "register_operand" ""))] | |
1842 | "reload_completed && TARGET_CPU_ZARCH" | |
1843 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
1844 | (parallel | |
1845 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
1846 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
1847 | (set (match_dup 0) (match_dup 1)) | |
1848 | (use (const_int 1))])] | |
1849 | "operands[4] = gen_label_rtx ();") | |
1850 | ||
a41c6c53 | 1851 | ; Move a block of arbitrary length. |
9db1d521 | 1852 | |
70128ad9 | 1853 | (define_expand "movmem_long" |
b9404c99 UW |
1854 | [(parallel |
1855 | [(clobber (match_dup 2)) | |
1856 | (clobber (match_dup 3)) | |
1857 | (set (match_operand:BLK 0 "memory_operand" "") | |
1858 | (match_operand:BLK 1 "memory_operand" "")) | |
1859 | (use (match_operand 2 "general_operand" "")) | |
1860 | (use (match_dup 3)) | |
1861 | (clobber (reg:CC 33))])] | |
1862 | "" | |
1863 | { | |
1864 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
1865 | rtx reg0 = gen_reg_rtx (dword_mode); | |
1866 | rtx reg1 = gen_reg_rtx (dword_mode); | |
1867 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
1868 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
1869 | rtx len0 = gen_lowpart (Pmode, reg0); | |
1870 | rtx len1 = gen_lowpart (Pmode, reg1); | |
1871 | ||
1872 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
1873 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
1874 | emit_move_insn (len0, operands[2]); | |
1875 | ||
1876 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
1877 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1878 | emit_move_insn (len1, operands[2]); | |
1879 | ||
1880 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
1881 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
1882 | operands[2] = reg0; | |
1883 | operands[3] = reg1; | |
1884 | }) | |
1885 | ||
70128ad9 | 1886 | (define_insn "*movmem_long_64" |
b9404c99 UW |
1887 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
1888 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
1889 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
1890 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) | |
1891 | (use (match_dup 2)) | |
1892 | (use (match_dup 3)) | |
9db1d521 | 1893 | (clobber (reg:CC 33))] |
9f37ccb1 | 1894 | "TARGET_64BIT" |
d40c829f | 1895 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
1896 | [(set_attr "length" "8") |
1897 | (set_attr "type" "vs")]) | |
9db1d521 | 1898 | |
70128ad9 | 1899 | (define_insn "*movmem_long_31" |
b9404c99 UW |
1900 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
1901 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
1902 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
1903 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) | |
1904 | (use (match_dup 2)) | |
1905 | (use (match_dup 3)) | |
9db1d521 | 1906 | (clobber (reg:CC 33))] |
9f37ccb1 | 1907 | "!TARGET_64BIT" |
d40c829f | 1908 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
1909 | [(set_attr "length" "8") |
1910 | (set_attr "type" "vs")]) | |
9db1d521 HP |
1911 | |
1912 | ; | |
70128ad9 | 1913 | ; clrmemM instruction pattern(s). |
9db1d521 HP |
1914 | ; |
1915 | ||
9db2f16d | 1916 | (define_expand "clrmem<mode>" |
a41c6c53 | 1917 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 | 1918 | (const_int 0)) |
9db2f16d | 1919 | (use (match_operand:GPR 1 "general_operand" "")) |
9db1d521 | 1920 | (match_operand 2 "" "")] |
a41c6c53 | 1921 | "" |
70128ad9 | 1922 | "s390_expand_clrmem (operands[0], operands[1]); DONE;") |
9db1d521 | 1923 | |
a41c6c53 | 1924 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
1925 | ; The block length is taken as (operands[1] % 256) + 1. |
1926 | ||
70128ad9 | 1927 | (define_expand "clrmem_short" |
b9404c99 UW |
1928 | [(parallel |
1929 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1930 | (const_int 0)) | |
1931 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 1932 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
1933 | (clobber (match_dup 2)) |
1934 | (clobber (reg:CC 33))])] | |
1935 | "" | |
1936 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 1937 | |
70128ad9 | 1938 | (define_insn "*clrmem_short" |
9bb86f41 | 1939 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
a41c6c53 | 1940 | (const_int 0)) |
9bb86f41 UW |
1941 | (use (match_operand 1 "nonmemory_operand" "n,a,a")) |
1942 | (use (match_operand 2 "immediate_operand" "X,R,X")) | |
1943 | (clobber (match_scratch 3 "=X,X,&a")) | |
a41c6c53 | 1944 | (clobber (reg:CC 33))] |
b9404c99 | 1945 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
1946 | && GET_MODE (operands[3]) == Pmode" |
1947 | "#" | |
b628bd8e | 1948 | [(set_attr "type" "cs")]) |
9bb86f41 UW |
1949 | |
1950 | (define_split | |
1951 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1952 | (const_int 0)) | |
1953 | (use (match_operand 1 "const_int_operand" "")) | |
1954 | (use (match_operand 2 "immediate_operand" "")) | |
1955 | (clobber (scratch)) | |
1956 | (clobber (reg:CC 33))] | |
1957 | "reload_completed" | |
1958 | [(parallel | |
1959 | [(set (match_dup 0) (const_int 0)) | |
1960 | (use (match_dup 1)) | |
1961 | (clobber (reg:CC 33))])] | |
1962 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") | |
9db1d521 | 1963 | |
9bb86f41 UW |
1964 | (define_split |
1965 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1966 | (const_int 0)) | |
1967 | (use (match_operand 1 "register_operand" "")) | |
1968 | (use (match_operand 2 "memory_operand" "")) | |
1969 | (clobber (scratch)) | |
1970 | (clobber (reg:CC 33))] | |
1971 | "reload_completed" | |
1972 | [(parallel | |
1973 | [(unspec [(match_dup 1) (match_dup 2) | |
1974 | (const_int 0)] UNSPEC_EXECUTE) | |
1975 | (set (match_dup 0) (const_int 0)) | |
1976 | (use (const_int 1)) | |
1977 | (clobber (reg:CC 33))])] | |
1978 | "") | |
9db1d521 | 1979 | |
9bb86f41 UW |
1980 | (define_split |
1981 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1982 | (const_int 0)) | |
1983 | (use (match_operand 1 "register_operand" "")) | |
1984 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
1985 | (clobber (match_operand 2 "register_operand" "")) | |
1986 | (clobber (reg:CC 33))] | |
1987 | "reload_completed && TARGET_CPU_ZARCH" | |
1988 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
1989 | (parallel | |
1990 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
1991 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
1992 | (set (match_dup 0) (const_int 0)) | |
1993 | (use (const_int 1)) | |
1994 | (clobber (reg:CC 33))])] | |
1995 | "operands[3] = gen_label_rtx ();") | |
1996 | ||
b9404c99 UW |
1997 | ; Clear a block of arbitrary length. |
1998 | ||
70128ad9 | 1999 | (define_expand "clrmem_long" |
b9404c99 UW |
2000 | [(parallel |
2001 | [(clobber (match_dup 1)) | |
2002 | (set (match_operand:BLK 0 "memory_operand" "") | |
2003 | (const_int 0)) | |
2004 | (use (match_operand 1 "general_operand" "")) | |
2005 | (use (match_dup 2)) | |
2006 | (clobber (reg:CC 33))])] | |
2007 | "" | |
a41c6c53 | 2008 | { |
b9404c99 UW |
2009 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2010 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2011 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2012 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2013 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2014 | |
b9404c99 UW |
2015 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2016 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2017 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2018 | |
b9404c99 | 2019 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2020 | |
b9404c99 UW |
2021 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2022 | operands[1] = reg0; | |
2023 | operands[2] = reg1; | |
2024 | }) | |
a41c6c53 | 2025 | |
70128ad9 | 2026 | (define_insn "*clrmem_long_64" |
b9404c99 UW |
2027 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2028 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
9db1d521 | 2029 | (const_int 0)) |
b9404c99 | 2030 | (use (match_dup 2)) |
9f37ccb1 | 2031 | (use (match_operand:TI 1 "register_operand" "d")) |
9db1d521 HP |
2032 | (clobber (reg:CC 33))] |
2033 | "TARGET_64BIT" | |
d40c829f | 2034 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2035 | [(set_attr "length" "8") |
2036 | (set_attr "type" "vs")]) | |
9db1d521 | 2037 | |
70128ad9 | 2038 | (define_insn "*clrmem_long_31" |
b9404c99 UW |
2039 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2040 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
9db1d521 | 2041 | (const_int 0)) |
b9404c99 | 2042 | (use (match_dup 2)) |
9f37ccb1 | 2043 | (use (match_operand:DI 1 "register_operand" "d")) |
9db1d521 HP |
2044 | (clobber (reg:CC 33))] |
2045 | "!TARGET_64BIT" | |
d40c829f | 2046 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2047 | [(set_attr "length" "8") |
2048 | (set_attr "type" "vs")]) | |
9db1d521 HP |
2049 | |
2050 | ; | |
358b8f01 | 2051 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2052 | ; |
2053 | ||
358b8f01 | 2054 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2055 | [(set (match_operand:SI 0 "register_operand" "") |
2056 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2057 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2058 | (use (match_operand:SI 3 "general_operand" "")) | |
2059 | (use (match_operand:SI 4 "" ""))] | |
2060 | "" | |
c7453384 | 2061 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2062 | operands[2], operands[3]); DONE;") |
9db1d521 | 2063 | |
a41c6c53 UW |
2064 | ; Compare a block that is up to 256 bytes in length. |
2065 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2066 | |
b9404c99 UW |
2067 | (define_expand "cmpmem_short" |
2068 | [(parallel | |
5b022de5 UW |
2069 | [(set (reg:CCU 33) |
2070 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
b9404c99 UW |
2071 | (match_operand:BLK 1 "memory_operand" ""))) |
2072 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2073 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2074 | (clobber (match_dup 3))])] |
2075 | "" | |
2076 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2077 | |
b9404c99 | 2078 | (define_insn "*cmpmem_short" |
5b022de5 | 2079 | [(set (reg:CCU 33) |
d4f52f0e | 2080 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") |
9bb86f41 UW |
2081 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) |
2082 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2083 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2084 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2085 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2086 | && GET_MODE (operands[4]) == Pmode" |
2087 | "#" | |
b628bd8e | 2088 | [(set_attr "type" "cs")]) |
9db1d521 | 2089 | |
9bb86f41 UW |
2090 | (define_split |
2091 | [(set (reg:CCU 33) | |
2092 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2093 | (match_operand:BLK 1 "memory_operand" ""))) | |
2094 | (use (match_operand 2 "const_int_operand" "")) | |
2095 | (use (match_operand 3 "immediate_operand" "")) | |
2096 | (clobber (scratch))] | |
2097 | "reload_completed" | |
2098 | [(parallel | |
2099 | [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2100 | (use (match_dup 2))])] | |
2101 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2102 | |
9bb86f41 UW |
2103 | (define_split |
2104 | [(set (reg:CCU 33) | |
2105 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2106 | (match_operand:BLK 1 "memory_operand" ""))) | |
2107 | (use (match_operand 2 "register_operand" "")) | |
2108 | (use (match_operand 3 "memory_operand" "")) | |
2109 | (clobber (scratch))] | |
2110 | "reload_completed" | |
2111 | [(parallel | |
2112 | [(unspec [(match_dup 2) (match_dup 3) | |
2113 | (const_int 0)] UNSPEC_EXECUTE) | |
2114 | (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2115 | (use (const_int 1))])] | |
2116 | "") | |
2117 | ||
2118 | (define_split | |
2119 | [(set (reg:CCU 33) | |
2120 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2121 | (match_operand:BLK 1 "memory_operand" ""))) | |
2122 | (use (match_operand 2 "register_operand" "")) | |
2123 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2124 | (clobber (match_operand 3 "register_operand" ""))] | |
2125 | "reload_completed && TARGET_CPU_ZARCH" | |
2126 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2127 | (parallel | |
2128 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2129 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2130 | (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2131 | (use (const_int 1))])] | |
2132 | "operands[4] = gen_label_rtx ();") | |
2133 | ||
a41c6c53 | 2134 | ; Compare a block of arbitrary length. |
9db1d521 | 2135 | |
b9404c99 UW |
2136 | (define_expand "cmpmem_long" |
2137 | [(parallel | |
2138 | [(clobber (match_dup 2)) | |
2139 | (clobber (match_dup 3)) | |
5b022de5 UW |
2140 | (set (reg:CCU 33) |
2141 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
b9404c99 UW |
2142 | (match_operand:BLK 1 "memory_operand" ""))) |
2143 | (use (match_operand 2 "general_operand" "")) | |
2144 | (use (match_dup 3))])] | |
2145 | "" | |
2146 | { | |
2147 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2148 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2149 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2150 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2151 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2152 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2153 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2154 | ||
2155 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2156 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2157 | emit_move_insn (len0, operands[2]); | |
2158 | ||
2159 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2160 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2161 | emit_move_insn (len1, operands[2]); | |
2162 | ||
2163 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2164 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2165 | operands[2] = reg0; | |
2166 | operands[3] = reg1; | |
2167 | }) | |
2168 | ||
2169 | (define_insn "*cmpmem_long_64" | |
4023fb28 UW |
2170 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2171 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
5b022de5 UW |
2172 | (set (reg:CCU 33) |
2173 | (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2174 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
2175 | (use (match_dup 2)) | |
2176 | (use (match_dup 3))] | |
9db1d521 | 2177 | "TARGET_64BIT" |
287ff198 | 2178 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2179 | [(set_attr "length" "8") |
2180 | (set_attr "type" "vs")]) | |
9db1d521 | 2181 | |
b9404c99 | 2182 | (define_insn "*cmpmem_long_31" |
4023fb28 UW |
2183 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2184 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
5b022de5 UW |
2185 | (set (reg:CCU 33) |
2186 | (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2187 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
2188 | (use (match_dup 2)) | |
2189 | (use (match_dup 3))] | |
9db1d521 | 2190 | "!TARGET_64BIT" |
287ff198 | 2191 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2192 | [(set_attr "length" "8") |
2193 | (set_attr "type" "vs")]) | |
9db1d521 | 2194 | |
02887425 UW |
2195 | ; Convert CCUmode condition code to integer. |
2196 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 2197 | |
02887425 | 2198 | (define_insn_and_split "cmpint" |
9db1d521 | 2199 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 UW |
2200 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2201 | UNSPEC_CMPINT)) | |
2202 | (clobber (reg:CC 33))] | |
9db1d521 | 2203 | "" |
02887425 UW |
2204 | "#" |
2205 | "reload_completed" | |
2206 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2207 | (parallel | |
2208 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
2209 | (clobber (reg:CC 33))])]) | |
2210 | ||
2211 | (define_insn_and_split "*cmpint_cc" | |
2212 | [(set (reg 33) | |
2213 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2214 | UNSPEC_CMPINT) | |
2215 | (const_int 0))) | |
2216 | (set (match_operand:SI 0 "register_operand" "=d") | |
2217 | (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))] | |
2218 | "s390_match_ccmode (insn, CCSmode)" | |
2219 | "#" | |
2220 | "&& reload_completed" | |
2221 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2222 | (parallel | |
2223 | [(set (match_dup 2) (match_dup 3)) | |
2224 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 2225 | { |
02887425 UW |
2226 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
2227 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2228 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2229 | }) | |
9db1d521 | 2230 | |
02887425 | 2231 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 2232 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 UW |
2233 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2234 | UNSPEC_CMPINT))) | |
2235 | (clobber (reg:CC 33))] | |
9db1d521 | 2236 | "TARGET_64BIT" |
02887425 UW |
2237 | "#" |
2238 | "&& reload_completed" | |
2239 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2240 | (parallel | |
2241 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
2242 | (clobber (reg:CC 33))])]) | |
2243 | ||
2244 | (define_insn_and_split "*cmpint_sign_cc" | |
2245 | [(set (reg 33) | |
2246 | (compare (ashiftrt:DI (ashift:DI (subreg:DI | |
2247 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2248 | UNSPEC_CMPINT) 0) | |
2249 | (const_int 32)) (const_int 32)) | |
2250 | (const_int 0))) | |
2251 | (set (match_operand:DI 0 "register_operand" "=d") | |
2252 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))] | |
2253 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" | |
2254 | "#" | |
2255 | "&& reload_completed" | |
2256 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2257 | (parallel | |
2258 | [(set (match_dup 2) (match_dup 3)) | |
2259 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 2260 | { |
02887425 UW |
2261 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
2262 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2263 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2264 | }) | |
9db1d521 | 2265 | |
4023fb28 | 2266 | |
9db1d521 HP |
2267 | ;; |
2268 | ;;- Conversion instructions. | |
2269 | ;; | |
2270 | ||
4023fb28 | 2271 | |
f52c81dd | 2272 | (define_insn "*sethigh<mode>si" |
d3632d41 | 2273 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f52c81dd | 2274 | (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2275 | (clobber (reg:CC 33))] |
2276 | "" | |
d3632d41 | 2277 | "@ |
f52c81dd AS |
2278 | icm\t%0,<icm_hi>,%S1 |
2279 | icmy\t%0,<icm_hi>,%S1" | |
d3632d41 | 2280 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2281 | |
2282 | (define_insn "*sethighqidi_64" | |
2283 | [(set (match_operand:DI 0 "register_operand" "=d") | |
10bbf137 | 2284 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2285 | (clobber (reg:CC 33))] |
2286 | "TARGET_64BIT" | |
fc0ea003 | 2287 | "icmh\t%0,8,%S1" |
d3632d41 | 2288 | [(set_attr "op_type" "RSY")]) |
4023fb28 UW |
2289 | |
2290 | (define_insn "*sethighqidi_31" | |
d3632d41 | 2291 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
10bbf137 | 2292 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2293 | (clobber (reg:CC 33))] |
2294 | "!TARGET_64BIT" | |
d3632d41 | 2295 | "@ |
fc0ea003 UW |
2296 | icm\t%0,8,%S1 |
2297 | icmy\t%0,8,%S1" | |
d3632d41 | 2298 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2299 | |
cc7ab9b7 UW |
2300 | (define_insn_and_split "*extractqi" |
2301 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2302 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2303 | (match_operand 2 "const_int_operand" "n") | |
2304 | (const_int 0))) | |
2305 | (clobber (reg:CC 33))] | |
2306 | "!TARGET_64BIT | |
4023fb28 | 2307 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
cc7ab9b7 UW |
2308 | "#" |
2309 | "&& reload_completed" | |
4023fb28 | 2310 | [(parallel |
10bbf137 | 2311 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2312 | (clobber (reg:CC 33))]) |
2313 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2314 | { |
2315 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2316 | operands[1] = change_address (operands[1], QImode, 0); | |
b628bd8e | 2317 | }) |
4023fb28 | 2318 | |
cc7ab9b7 UW |
2319 | (define_insn_and_split "*extracthi" |
2320 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2321 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2322 | (match_operand 2 "const_int_operand" "n") | |
2323 | (const_int 0))) | |
2324 | (clobber (reg:CC 33))] | |
2325 | "!TARGET_64BIT | |
4023fb28 | 2326 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
cc7ab9b7 UW |
2327 | "#" |
2328 | "&& reload_completed" | |
4023fb28 | 2329 | [(parallel |
10bbf137 | 2330 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2331 | (clobber (reg:CC 33))]) |
2332 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2333 | { |
2334 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2335 | operands[1] = change_address (operands[1], HImode, 0); | |
b628bd8e | 2336 | }) |
4023fb28 | 2337 | |
9db1d521 HP |
2338 | ; |
2339 | ; extendsidi2 instruction pattern(s). | |
2340 | ; | |
2341 | ||
4023fb28 UW |
2342 | (define_expand "extendsidi2" |
2343 | [(set (match_operand:DI 0 "register_operand" "") | |
2344 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2345 | "" | |
2346 | " | |
2347 | { | |
2348 | if (!TARGET_64BIT) | |
2349 | { | |
9f37ccb1 UW |
2350 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2351 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2352 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2353 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2354 | DONE; |
2355 | } | |
2356 | } | |
2357 | ") | |
2358 | ||
2359 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2360 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2361 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2362 | "TARGET_64BIT" | |
2363 | "@ | |
d40c829f UW |
2364 | lgfr\t%0,%1 |
2365 | lgf\t%0,%1" | |
d3632d41 | 2366 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2367 | |
9db1d521 HP |
2368 | ; |
2369 | ; extendhidi2 instruction pattern(s). | |
2370 | ; | |
2371 | ||
4023fb28 UW |
2372 | (define_expand "extendhidi2" |
2373 | [(set (match_operand:DI 0 "register_operand" "") | |
2374 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2375 | "" | |
2376 | " | |
2377 | { | |
2378 | if (!TARGET_64BIT) | |
2379 | { | |
2380 | rtx tmp = gen_reg_rtx (SImode); | |
2381 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
2382 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2383 | DONE; | |
2384 | } | |
2385 | else | |
2386 | { | |
2387 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2388 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2389 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2390 | DONE; |
2391 | } | |
2392 | } | |
2393 | ") | |
2394 | ||
2395 | (define_insn "*extendhidi2" | |
9db1d521 | 2396 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2397 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2398 | "TARGET_64BIT" |
d40c829f | 2399 | "lgh\t%0,%1" |
d3632d41 | 2400 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2401 | |
2402 | ; | |
2403 | ; extendqidi2 instruction pattern(s). | |
2404 | ; | |
2405 | ||
4023fb28 UW |
2406 | (define_expand "extendqidi2" |
2407 | [(set (match_operand:DI 0 "register_operand" "") | |
2408 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
2409 | "" | |
2410 | " | |
2411 | { | |
2412 | if (!TARGET_64BIT) | |
2413 | { | |
2414 | rtx tmp = gen_reg_rtx (SImode); | |
2415 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
2416 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2417 | DONE; | |
2418 | } | |
2419 | else | |
2420 | { | |
2421 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2422 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2423 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2424 | DONE; |
2425 | } | |
2426 | } | |
2427 | ") | |
2428 | ||
d3632d41 UW |
2429 | (define_insn "*extendqidi2" |
2430 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2431 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2432 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2433 | "lgb\t%0,%1" |
d3632d41 UW |
2434 | [(set_attr "op_type" "RXY")]) |
2435 | ||
19796784 AK |
2436 | (define_insn_and_split "*extendqidi2_short_displ" |
2437 | [(set (match_operand:DI 0 "register_operand" "=d") | |
59f8a8be UW |
2438 | (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) |
2439 | (clobber (reg:CC 33))] | |
19796784 AK |
2440 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" |
2441 | "#" | |
2442 | "&& reload_completed" | |
4023fb28 | 2443 | [(parallel |
10bbf137 | 2444 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2445 | (clobber (reg:CC 33))]) |
2446 | (parallel | |
2447 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
2448 | (clobber (reg:CC 33))])] | |
2449 | "") | |
9db1d521 HP |
2450 | |
2451 | ; | |
2452 | ; extendhisi2 instruction pattern(s). | |
2453 | ; | |
2454 | ||
4023fb28 UW |
2455 | (define_expand "extendhisi2" |
2456 | [(set (match_operand:SI 0 "register_operand" "") | |
2457 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2458 | "" |
4023fb28 UW |
2459 | " |
2460 | { | |
2461 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2462 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
c7453384 | 2463 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); |
4023fb28 UW |
2464 | DONE; |
2465 | } | |
2466 | ") | |
9db1d521 | 2467 | |
4023fb28 | 2468 | (define_insn "*extendhisi2" |
d3632d41 UW |
2469 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2470 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
4023fb28 | 2471 | "" |
d3632d41 | 2472 | "@ |
d40c829f UW |
2473 | lh\t%0,%1 |
2474 | lhy\t%0,%1" | |
d3632d41 | 2475 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
2476 | |
2477 | ; | |
2478 | ; extendqisi2 instruction pattern(s). | |
2479 | ; | |
2480 | ||
4023fb28 UW |
2481 | (define_expand "extendqisi2" |
2482 | [(set (match_operand:SI 0 "register_operand" "") | |
2483 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 | 2484 | "" |
4023fb28 UW |
2485 | " |
2486 | { | |
2487 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2488 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
c7453384 | 2489 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); |
4023fb28 UW |
2490 | DONE; |
2491 | } | |
2492 | ") | |
9db1d521 | 2493 | |
d3632d41 UW |
2494 | (define_insn "*extendqisi2" |
2495 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2496 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2497 | "TARGET_LONG_DISPLACEMENT" |
d40c829f | 2498 | "lb\t%0,%1" |
d3632d41 UW |
2499 | [(set_attr "op_type" "RXY")]) |
2500 | ||
eb457a7a | 2501 | (define_insn_and_split "*extendqisi2_short_displ" |
19796784 | 2502 | [(set (match_operand:SI 0 "register_operand" "=d") |
59f8a8be UW |
2503 | (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) |
2504 | (clobber (reg:CC 33))] | |
19796784 AK |
2505 | "!TARGET_LONG_DISPLACEMENT" |
2506 | "#" | |
2507 | "&& reload_completed" | |
4023fb28 | 2508 | [(parallel |
10bbf137 | 2509 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2510 | (clobber (reg:CC 33))]) |
2511 | (parallel | |
2512 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
2513 | (clobber (reg:CC 33))])] | |
2514 | "") | |
9db1d521 HP |
2515 | |
2516 | ; | |
2517 | ; extendqihi2 instruction pattern(s). | |
2518 | ; | |
2519 | ||
9db1d521 HP |
2520 | |
2521 | ; | |
2522 | ; zero_extendsidi2 instruction pattern(s). | |
2523 | ; | |
2524 | ||
4023fb28 UW |
2525 | (define_expand "zero_extendsidi2" |
2526 | [(set (match_operand:DI 0 "register_operand" "") | |
2527 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2528 | "" | |
2529 | " | |
2530 | { | |
2531 | if (!TARGET_64BIT) | |
2532 | { | |
9f37ccb1 UW |
2533 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2534 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2535 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2536 | DONE; |
2537 | } | |
2538 | } | |
2539 | ") | |
2540 | ||
2541 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2542 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2543 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2544 | "TARGET_64BIT" | |
2545 | "@ | |
d40c829f UW |
2546 | llgfr\t%0,%1 |
2547 | llgf\t%0,%1" | |
d3632d41 | 2548 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2549 | |
9db1d521 HP |
2550 | ; |
2551 | ; zero_extendhidi2 instruction pattern(s). | |
2552 | ; | |
2553 | ||
4023fb28 UW |
2554 | (define_expand "zero_extendhidi2" |
2555 | [(set (match_operand:DI 0 "register_operand" "") | |
2556 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2557 | "" | |
2558 | " | |
2559 | { | |
2560 | if (!TARGET_64BIT) | |
2561 | { | |
2562 | rtx tmp = gen_reg_rtx (SImode); | |
2563 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
2564 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
2565 | DONE; | |
2566 | } | |
2567 | else | |
2568 | { | |
2569 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2570 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2571 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2572 | DONE; |
2573 | } | |
2574 | } | |
2575 | ") | |
9db1d521 | 2576 | |
4023fb28 UW |
2577 | (define_insn "*zero_extendhidi2" |
2578 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2579 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
9db1d521 | 2580 | "TARGET_64BIT" |
d40c829f | 2581 | "llgh\t%0,%1" |
d3632d41 | 2582 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2583 | |
288e517f AK |
2584 | ; |
2585 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2586 | ; | |
2587 | ||
d6083c7d UW |
2588 | (define_insn "*llgt_sidi" |
2589 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2590 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2591 | (const_int 2147483647)))] | |
2592 | "TARGET_64BIT" | |
2593 | "llgt\t%0,%1" | |
2594 | [(set_attr "op_type" "RXE")]) | |
2595 | ||
2596 | (define_insn_and_split "*llgt_sidi_split" | |
2597 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2598 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2599 | (const_int 2147483647))) | |
2600 | (clobber (reg:CC 33))] | |
2601 | "TARGET_64BIT" | |
2602 | "#" | |
2603 | "&& reload_completed" | |
2604 | [(set (match_dup 0) | |
2605 | (and:DI (subreg:DI (match_dup 1) 0) | |
2606 | (const_int 2147483647)))] | |
2607 | "") | |
2608 | ||
288e517f AK |
2609 | (define_insn "*llgt_sisi" |
2610 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2611 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2612 | (const_int 2147483647)))] | |
2613 | "TARGET_64BIT" | |
2614 | "@ | |
2615 | llgtr\t%0,%1 | |
2616 | llgt\t%0,%1" | |
2617 | [(set_attr "op_type" "RRE,RXE")]) | |
2618 | ||
f19a9af7 AK |
2619 | (define_split |
2620 | [(set (match_operand:SI 0 "register_operand" "") | |
2621 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
288e517f AK |
2622 | (const_int 2147483647))) |
2623 | (clobber (reg:CC 33))] | |
f19a9af7 | 2624 | "TARGET_64BIT && reload_completed" |
288e517f AK |
2625 | [(set (match_dup 0) |
2626 | (and:SI (match_dup 1) | |
2627 | (const_int 2147483647)))] | |
2628 | "") | |
2629 | ||
2630 | (define_insn "*llgt_didi" | |
2631 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2632 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2633 | (const_int 2147483647)))] | |
2634 | "TARGET_64BIT" | |
2635 | "@ | |
2636 | llgtr\t%0,%1 | |
2637 | llgt\t%0,%N1" | |
2638 | [(set_attr "op_type" "RRE,RXE")]) | |
2639 | ||
f19a9af7 AK |
2640 | (define_split |
2641 | [(set (match_operand:DI 0 "register_operand" "") | |
2642 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
288e517f AK |
2643 | (const_int 2147483647))) |
2644 | (clobber (reg:CC 33))] | |
f19a9af7 | 2645 | "TARGET_64BIT && reload_completed" |
288e517f AK |
2646 | [(set (match_dup 0) |
2647 | (and:DI (match_dup 1) | |
2648 | (const_int 2147483647)))] | |
2649 | "") | |
2650 | ||
9db1d521 | 2651 | ; |
4023fb28 | 2652 | ; zero_extendqidi2 instruction pattern(s) |
9db1d521 HP |
2653 | ; |
2654 | ||
4023fb28 UW |
2655 | (define_expand "zero_extendqidi2" |
2656 | [(set (match_operand:DI 0 "register_operand" "") | |
2657 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 HP |
2658 | "" |
2659 | " | |
2660 | { | |
2661 | if (!TARGET_64BIT) | |
2662 | { | |
4023fb28 UW |
2663 | rtx tmp = gen_reg_rtx (SImode); |
2664 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
2665 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
9db1d521 HP |
2666 | DONE; |
2667 | } | |
4023fb28 UW |
2668 | else |
2669 | { | |
2670 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2671 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2672 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2673 | DONE; |
2674 | } | |
2675 | } | |
2676 | ") | |
9db1d521 | 2677 | |
4023fb28 UW |
2678 | (define_insn "*zero_extendqidi2" |
2679 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2680 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
9db1d521 | 2681 | "TARGET_64BIT" |
d40c829f | 2682 | "llgc\t%0,%1" |
d3632d41 | 2683 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2684 | |
2685 | ; | |
4023fb28 | 2686 | ; zero_extendhisi2 instruction pattern(s). |
9db1d521 HP |
2687 | ; |
2688 | ||
4023fb28 UW |
2689 | (define_expand "zero_extendhisi2" |
2690 | [(set (match_operand:SI 0 "register_operand" "") | |
2691 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2692 | "" |
4023fb28 UW |
2693 | " |
2694 | { | |
2695 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2696 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
2697 | DONE; | |
2698 | } | |
2699 | ") | |
9db1d521 | 2700 | |
4023fb28 | 2701 | (define_insn "*zero_extendhisi2_64" |
9db1d521 | 2702 | [(set (match_operand:SI 0 "register_operand" "=d") |
4023fb28 | 2703 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
f4f41b4e | 2704 | "TARGET_ZARCH" |
d40c829f | 2705 | "llgh\t%0,%1" |
d3632d41 | 2706 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2707 | |
2708 | (define_insn_and_split "*zero_extendhisi2_31" | |
2709 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2710 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
cc7ab9b7 | 2711 | (clobber (reg:CC 33))] |
f4f41b4e | 2712 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2713 | "#" |
2714 | "&& reload_completed" | |
2715 | [(set (match_dup 0) (const_int 0)) | |
2716 | (parallel | |
2717 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
2718 | (clobber (reg:CC 33))])] | |
b628bd8e | 2719 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 2720 | |
4023fb28 UW |
2721 | ; |
2722 | ; zero_extendqisi2 instruction pattern(s). | |
2723 | ; | |
9db1d521 HP |
2724 | |
2725 | (define_expand "zero_extendqisi2" | |
2726 | [(set (match_operand:SI 0 "register_operand" "") | |
4023fb28 | 2727 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
9db1d521 HP |
2728 | "" |
2729 | " | |
2730 | { | |
4023fb28 UW |
2731 | operands[1] = gen_lowpart (SImode, operands[1]); |
2732 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2733 | DONE; | |
2734 | } | |
2735 | ") | |
9db1d521 | 2736 | |
4023fb28 UW |
2737 | (define_insn "*zero_extendqisi2_64" |
2738 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2739 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2740 | "TARGET_ZARCH" |
d40c829f | 2741 | "llgc\t%0,%1" |
d3632d41 | 2742 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2743 | |
2744 | (define_insn_and_split "*zero_extendqisi2_31" | |
2745 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2746 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2747 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2748 | "#" |
2749 | "&& reload_completed" | |
2750 | [(set (match_dup 0) (const_int 0)) | |
2751 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2752 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 2753 | |
9db1d521 HP |
2754 | ; |
2755 | ; zero_extendqihi2 instruction pattern(s). | |
2756 | ; | |
2757 | ||
9db1d521 HP |
2758 | (define_expand "zero_extendqihi2" |
2759 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2760 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
9e8327e3 | 2761 | "TARGET_ZARCH" |
9db1d521 HP |
2762 | " |
2763 | { | |
4023fb28 UW |
2764 | operands[1] = gen_lowpart (HImode, operands[1]); |
2765 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2766 | DONE; | |
2767 | } | |
2768 | ") | |
9db1d521 | 2769 | |
4023fb28 | 2770 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2771 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2772 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
9e8327e3 | 2773 | "TARGET_ZARCH" |
d40c829f | 2774 | "llgc\t%0,%1" |
d3632d41 | 2775 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2776 | |
cc7ab9b7 UW |
2777 | (define_insn_and_split "*zero_extendqihi2_31" |
2778 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2779 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2780 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2781 | "#" |
2782 | "&& reload_completed" | |
2783 | [(set (match_dup 0) (const_int 0)) | |
2784 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2785 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 UW |
2786 | |
2787 | ||
9db1d521 HP |
2788 | ; |
2789 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
2790 | ; | |
2791 | ||
2792 | (define_expand "fixuns_truncdfdi2" | |
2793 | [(set (match_operand:DI 0 "register_operand" "") | |
2794 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
2795 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2796 | { |
2797 | rtx label1 = gen_label_rtx (); | |
2798 | rtx label2 = gen_label_rtx (); | |
2799 | rtx temp = gen_reg_rtx (DFmode); | |
2800 | operands[1] = force_reg (DFmode, operands[1]); | |
2801 | ||
c7453384 | 2802 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2803 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2804 | REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); |
9db1d521 | 2805 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2806 | emit_insn (gen_subdf3 (temp, operands[1], |
2807 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2808 | REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); |
9db1d521 | 2809 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2810 | emit_jump (label2); |
9db1d521 HP |
2811 | |
2812 | emit_label (label1); | |
2813 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2814 | emit_label (label2); | |
2815 | DONE; | |
10bbf137 | 2816 | }) |
9db1d521 HP |
2817 | |
2818 | (define_expand "fix_truncdfdi2" | |
2819 | [(set (match_operand:DI 0 "register_operand" "") | |
2820 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2821 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2822 | { |
2823 | operands[1] = force_reg (DFmode, operands[1]); | |
2824 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2825 | DONE; | |
10bbf137 | 2826 | }) |
9db1d521 HP |
2827 | |
2828 | (define_insn "fix_truncdfdi2_ieee" | |
2829 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2830 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2831 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2832 | (clobber (reg:CC 33))] |
2833 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2834 | "cgdbr\t%0,%h2,%1" |
9db1d521 | 2835 | [(set_attr "op_type" "RRE") |
077dab3b | 2836 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2837 | |
2838 | ; | |
2839 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
2840 | ; | |
2841 | ||
2842 | (define_expand "fixuns_truncdfsi2" | |
2843 | [(set (match_operand:SI 0 "register_operand" "") | |
2844 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
2845 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2846 | { |
2847 | rtx label1 = gen_label_rtx (); | |
2848 | rtx label2 = gen_label_rtx (); | |
2849 | rtx temp = gen_reg_rtx (DFmode); | |
2850 | ||
2851 | operands[1] = force_reg (DFmode,operands[1]); | |
c7453384 | 2852 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2853 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2854 | REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); |
9db1d521 | 2855 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2856 | emit_insn (gen_subdf3 (temp, operands[1], |
2857 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2858 | REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); |
9db1d521 | 2859 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2860 | emit_jump (label2); |
9db1d521 HP |
2861 | |
2862 | emit_label (label1); | |
2863 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2864 | emit_label (label2); | |
2865 | DONE; | |
10bbf137 | 2866 | }) |
9db1d521 HP |
2867 | |
2868 | (define_expand "fix_truncdfsi2" | |
2869 | [(set (match_operand:SI 0 "register_operand" "") | |
2870 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2871 | "TARGET_HARD_FLOAT" | |
9db1d521 | 2872 | { |
c7453384 | 2873 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2874 | { |
2875 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2876 | ||
c19ec8f9 | 2877 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
2878 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2879 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
2880 | |
2881 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 2882 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 2883 | two31r, two32, temp)); |
c7453384 EC |
2884 | } |
2885 | else | |
9db1d521 HP |
2886 | { |
2887 | operands[1] = force_reg (DFmode, operands[1]); | |
2888 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2889 | } | |
2890 | ||
2891 | DONE; | |
10bbf137 | 2892 | }) |
9db1d521 HP |
2893 | |
2894 | (define_insn "fix_truncdfsi2_ieee" | |
2895 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2896 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2897 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2898 | (clobber (reg:CC 33))] |
2899 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2900 | "cfdbr\t%0,%h2,%1" |
9db1d521 | 2901 | [(set_attr "op_type" "RRE") |
a036c6f7 | 2902 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2903 | |
2904 | (define_insn "fix_truncdfsi2_ibm" | |
2905 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2906 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
2907 | (use (match_operand:DI 2 "immediate_operand" "m")) |
2908 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 HP |
2909 | (use (match_operand:BLK 4 "memory_operand" "m")) |
2910 | (clobber (reg:CC 33))] | |
2911 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 2912 | { |
d40c829f UW |
2913 | output_asm_insn ("sd\t%1,%2", operands); |
2914 | output_asm_insn ("aw\t%1,%3", operands); | |
2915 | output_asm_insn ("std\t%1,%4", operands); | |
2916 | output_asm_insn ("xi\t%N4,128", operands); | |
2917 | return "l\t%0,%N4"; | |
10bbf137 | 2918 | } |
b628bd8e | 2919 | [(set_attr "length" "20")]) |
9db1d521 HP |
2920 | |
2921 | ; | |
2922 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
2923 | ; | |
2924 | ||
2925 | (define_expand "fixuns_truncsfdi2" | |
2926 | [(set (match_operand:DI 0 "register_operand" "") | |
2927 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
2928 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2929 | { |
2930 | rtx label1 = gen_label_rtx (); | |
2931 | rtx label2 = gen_label_rtx (); | |
2932 | rtx temp = gen_reg_rtx (SFmode); | |
2933 | ||
2934 | operands[1] = force_reg (SFmode, operands[1]); | |
c7453384 | 2935 | emit_insn (gen_cmpsf (operands[1], |
4023fb28 | 2936 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2937 | REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); |
9db1d521 HP |
2938 | emit_jump_insn (gen_blt (label1)); |
2939 | ||
4023fb28 UW |
2940 | emit_insn (gen_subsf3 (temp, operands[1], |
2941 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2942 | REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); |
9db1d521 | 2943 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2944 | emit_jump (label2); |
9db1d521 HP |
2945 | |
2946 | emit_label (label1); | |
2947 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2948 | emit_label (label2); | |
2949 | DONE; | |
10bbf137 | 2950 | }) |
9db1d521 HP |
2951 | |
2952 | (define_expand "fix_truncsfdi2" | |
2953 | [(set (match_operand:DI 0 "register_operand" "") | |
2954 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2955 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2956 | { |
2957 | operands[1] = force_reg (SFmode, operands[1]); | |
2958 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2959 | DONE; | |
10bbf137 | 2960 | }) |
9db1d521 HP |
2961 | |
2962 | (define_insn "fix_truncsfdi2_ieee" | |
2963 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2964 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 2965 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2966 | (clobber (reg:CC 33))] |
2967 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2968 | "cgebr\t%0,%h2,%1" |
9db1d521 | 2969 | [(set_attr "op_type" "RRE") |
077dab3b | 2970 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2971 | |
2972 | ; | |
2973 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
2974 | ; | |
2975 | ||
2976 | (define_expand "fixuns_truncsfsi2" | |
2977 | [(set (match_operand:SI 0 "register_operand" "") | |
2978 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
2979 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2980 | { |
2981 | rtx label1 = gen_label_rtx (); | |
2982 | rtx label2 = gen_label_rtx (); | |
2983 | rtx temp = gen_reg_rtx (SFmode); | |
2984 | ||
2985 | operands[1] = force_reg (SFmode, operands[1]); | |
4023fb28 UW |
2986 | emit_insn (gen_cmpsf (operands[1], |
2987 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2988 | REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); |
9db1d521 | 2989 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2990 | emit_insn (gen_subsf3 (temp, operands[1], |
2991 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2992 | REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); |
9db1d521 | 2993 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2994 | emit_jump (label2); |
9db1d521 HP |
2995 | |
2996 | emit_label (label1); | |
2997 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2998 | emit_label (label2); | |
2999 | DONE; | |
10bbf137 | 3000 | }) |
9db1d521 HP |
3001 | |
3002 | (define_expand "fix_truncsfsi2" | |
3003 | [(set (match_operand:SI 0 "register_operand" "") | |
3004 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3005 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3006 | { |
3007 | if (TARGET_IBM_FLOAT) | |
3008 | { | |
3009 | /* Convert to DFmode and then use the POP algorithm. */ | |
3010 | rtx temp = gen_reg_rtx (DFmode); | |
3011 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
3012 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
3013 | } | |
3014 | else | |
3015 | { | |
3016 | operands[1] = force_reg (SFmode, operands[1]); | |
3017 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3018 | } | |
3019 | ||
3020 | DONE; | |
10bbf137 | 3021 | }) |
9db1d521 HP |
3022 | |
3023 | (define_insn "fix_truncsfsi2_ieee" | |
3024 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3025 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 3026 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
3027 | (clobber (reg:CC 33))] |
3028 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 3029 | "cfebr\t%0,%h2,%1" |
9db1d521 | 3030 | [(set_attr "op_type" "RRE") |
077dab3b | 3031 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
3032 | |
3033 | ; | |
3034 | ; floatdidf2 instruction pattern(s). | |
3035 | ; | |
3036 | ||
3037 | (define_insn "floatdidf2" | |
3038 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 3039 | (float:DF (match_operand:DI 1 "register_operand" "d")))] |
9db1d521 | 3040 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3041 | "cdgbr\t%0,%1" |
9db1d521 | 3042 | [(set_attr "op_type" "RRE") |
f0bf1270 | 3043 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3044 | |
3045 | ; | |
3046 | ; floatdisf2 instruction pattern(s). | |
3047 | ; | |
3048 | ||
3049 | (define_insn "floatdisf2" | |
3050 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3051 | (float:SF (match_operand:DI 1 "register_operand" "d")))] |
9db1d521 | 3052 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3053 | "cegbr\t%0,%1" |
9db1d521 | 3054 | [(set_attr "op_type" "RRE") |
077dab3b | 3055 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3056 | |
3057 | ; | |
3058 | ; floatsidf2 instruction pattern(s). | |
3059 | ; | |
3060 | ||
3061 | (define_expand "floatsidf2" | |
a036c6f7 UW |
3062 | [(set (match_operand:DF 0 "register_operand" "") |
3063 | (float:DF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3064 | "TARGET_HARD_FLOAT" |
9db1d521 | 3065 | { |
c7453384 | 3066 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3067 | { |
3068 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
3069 | ||
c19ec8f9 | 3070 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 3071 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
3072 | |
3073 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
3074 | DONE; | |
3075 | } | |
10bbf137 | 3076 | }) |
9db1d521 HP |
3077 | |
3078 | (define_insn "floatsidf2_ieee" | |
3079 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 3080 | (float:DF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3081 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3082 | "cdfbr\t%0,%1" |
9db1d521 | 3083 | [(set_attr "op_type" "RRE") |
077dab3b | 3084 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3085 | |
3086 | (define_insn "floatsidf2_ibm" | |
3087 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3088 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3089 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 HP |
3090 | (use (match_operand:BLK 3 "memory_operand" "m")) |
3091 | (clobber (reg:CC 33))] | |
3092 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 3093 | { |
d40c829f UW |
3094 | output_asm_insn ("st\t%1,%N3", operands); |
3095 | output_asm_insn ("xi\t%N3,128", operands); | |
3096 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3097 | output_asm_insn ("ld\t%0,%3", operands); | |
3098 | return "sd\t%0,%2"; | |
10bbf137 | 3099 | } |
b628bd8e | 3100 | [(set_attr "length" "20")]) |
9db1d521 HP |
3101 | |
3102 | ; | |
3103 | ; floatsisf2 instruction pattern(s). | |
3104 | ; | |
3105 | ||
3106 | (define_expand "floatsisf2" | |
a036c6f7 UW |
3107 | [(set (match_operand:SF 0 "register_operand" "") |
3108 | (float:SF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3109 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3110 | { |
3111 | if (TARGET_IBM_FLOAT) | |
3112 | { | |
3113 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3114 | rtx temp = gen_reg_rtx (DFmode); | |
3115 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3116 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3117 | DONE; | |
3118 | } | |
10bbf137 | 3119 | }) |
9db1d521 HP |
3120 | |
3121 | (define_insn "floatsisf2_ieee" | |
3122 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3123 | (float:SF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3124 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3125 | "cefbr\t%0,%1" |
9db1d521 | 3126 | [(set_attr "op_type" "RRE") |
077dab3b | 3127 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3128 | |
3129 | ; | |
3130 | ; truncdfsf2 instruction pattern(s). | |
3131 | ; | |
3132 | ||
3133 | (define_expand "truncdfsf2" | |
3134 | [(set (match_operand:SF 0 "register_operand" "") | |
a036c6f7 | 3135 | (float_truncate:SF (match_operand:DF 1 "register_operand" "")))] |
9db1d521 | 3136 | "TARGET_HARD_FLOAT" |
4023fb28 | 3137 | "") |
9db1d521 HP |
3138 | |
3139 | (define_insn "truncdfsf2_ieee" | |
3140 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3141 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
9db1d521 | 3142 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3143 | "ledbr\t%0,%1" |
ce50cae8 | 3144 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
3145 | |
3146 | (define_insn "truncdfsf2_ibm" | |
3147 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
a036c6f7 | 3148 | (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3149 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3150 | "@ | |
a036c6f7 | 3151 | ler\t%0,%1 |
d40c829f | 3152 | le\t%0,%1" |
4023fb28 | 3153 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3154 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3155 | |
3156 | ; | |
3157 | ; extendsfdf2 instruction pattern(s). | |
3158 | ; | |
3159 | ||
3160 | (define_expand "extendsfdf2" | |
3161 | [(set (match_operand:DF 0 "register_operand" "") | |
3162 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3163 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3164 | { |
3165 | if (TARGET_IBM_FLOAT) | |
3166 | { | |
3167 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3168 | DONE; | |
3169 | } | |
10bbf137 | 3170 | }) |
9db1d521 HP |
3171 | |
3172 | (define_insn "extendsfdf2_ieee" | |
3173 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3174 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3175 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3176 | "@ | |
d40c829f UW |
3177 | ldebr\t%0,%1 |
3178 | ldeb\t%0,%1" | |
077dab3b HP |
3179 | [(set_attr "op_type" "RRE,RXE") |
3180 | (set_attr "type" "floads,floads")]) | |
9db1d521 HP |
3181 | |
3182 | (define_insn "extendsfdf2_ibm" | |
3183 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3184 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
9db1d521 HP |
3185 | (clobber (reg:CC 33))] |
3186 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3187 | "@ | |
d40c829f UW |
3188 | sdr\t%0,%0\;ler\t%0,%1 |
3189 | sdr\t%0,%0\;le\t%0,%1" | |
b628bd8e | 3190 | [(set_attr "length" "4,6") |
a036c6f7 | 3191 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3192 | |
3193 | ||
3194 | ;; | |
fae778eb | 3195 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3196 | ;; |
fae778eb | 3197 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3198 | ; because of unpredictable Bits in Register for Halfword and Byte |
3199 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3200 | ||
07893d4f UW |
3201 | ;; |
3202 | ;;- Add instructions. | |
3203 | ;; | |
3204 | ||
1c7b1b7e UW |
3205 | ; |
3206 | ; addti3 instruction pattern(s). | |
3207 | ; | |
3208 | ||
3209 | (define_insn_and_split "addti3" | |
3210 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3211 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
3212 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3213 | (clobber (reg:CC 33))] | |
3214 | "TARGET_64BIT" | |
3215 | "#" | |
3216 | "&& reload_completed" | |
3217 | [(parallel | |
3218 | [(set (reg:CCL1 33) | |
3219 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) | |
3220 | (match_dup 7))) | |
3221 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
3222 | (parallel | |
3223 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
3224 | (ltu:DI (reg:CCL1 33) (const_int 0)))) | |
3225 | (clobber (reg:CC 33))])] | |
3226 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3227 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3228 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3229 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3230 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3231 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3232 | |
07893d4f UW |
3233 | ; |
3234 | ; adddi3 instruction pattern(s). | |
3235 | ; | |
3236 | ||
07893d4f UW |
3237 | (define_insn "*adddi3_sign" |
3238 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3239 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3240 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3241 | (clobber (reg:CC 33))] | |
3242 | "TARGET_64BIT" | |
3243 | "@ | |
d40c829f UW |
3244 | agfr\t%0,%2 |
3245 | agf\t%0,%2" | |
d3632d41 | 3246 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3247 | |
3248 | (define_insn "*adddi3_zero_cc" | |
c7453384 | 3249 | [(set (reg 33) |
07893d4f UW |
3250 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3251 | (match_operand:DI 1 "register_operand" "0,0")) | |
3252 | (const_int 0))) | |
3253 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3254 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3255 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3256 | "@ | |
d40c829f UW |
3257 | algfr\t%0,%2 |
3258 | algf\t%0,%2" | |
d3632d41 | 3259 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3260 | |
3261 | (define_insn "*adddi3_zero_cconly" | |
c7453384 | 3262 | [(set (reg 33) |
07893d4f UW |
3263 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3264 | (match_operand:DI 1 "register_operand" "0,0")) | |
3265 | (const_int 0))) | |
3266 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3267 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3268 | "@ | |
d40c829f UW |
3269 | algfr\t%0,%2 |
3270 | algf\t%0,%2" | |
d3632d41 | 3271 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3272 | |
3273 | (define_insn "*adddi3_zero" | |
3274 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3275 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3276 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3277 | (clobber (reg:CC 33))] | |
3278 | "TARGET_64BIT" | |
3279 | "@ | |
d40c829f UW |
3280 | algfr\t%0,%2 |
3281 | algf\t%0,%2" | |
d3632d41 | 3282 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3283 | |
0a3bdf9d | 3284 | (define_insn "*adddi3_imm_cc" |
c7453384 | 3285 | [(set (reg 33) |
0a3bdf9d UW |
3286 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
3287 | (match_operand:DI 2 "const_int_operand" "K")) | |
3288 | (const_int 0))) | |
3289 | (set (match_operand:DI 0 "register_operand" "=d") | |
3290 | (plus:DI (match_dup 1) (match_dup 2)))] | |
c7453384 EC |
3291 | "TARGET_64BIT |
3292 | && s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3293 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3294 | "aghi\t%0,%h2" |
077dab3b | 3295 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3296 | |
b2ba71ca UW |
3297 | (define_insn "*adddi3_carry1_cc" |
3298 | [(set (reg 33) | |
3299 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3300 | (match_operand:DI 2 "general_operand" "d,m")) | |
3301 | (match_dup 1))) | |
3302 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3303 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3304 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3305 | "@ | |
3306 | algr\t%0,%2 | |
3307 | alg\t%0,%2" | |
3308 | [(set_attr "op_type" "RRE,RXY")]) | |
3309 | ||
3310 | (define_insn "*adddi3_carry1_cconly" | |
3311 | [(set (reg 33) | |
3312 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3313 | (match_operand:DI 2 "general_operand" "d,m")) | |
3314 | (match_dup 1))) | |
3315 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3316 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3317 | "@ | |
3318 | algr\t%0,%2 | |
3319 | alg\t%0,%2" | |
3320 | [(set_attr "op_type" "RRE,RXY")]) | |
3321 | ||
3322 | (define_insn "*adddi3_carry2_cc" | |
3323 | [(set (reg 33) | |
3324 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3325 | (match_operand:DI 2 "general_operand" "d,m")) | |
3326 | (match_dup 2))) | |
3327 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3328 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3329 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3330 | "@ | |
3331 | algr\t%0,%2 | |
3332 | alg\t%0,%2" | |
3333 | [(set_attr "op_type" "RRE,RXY")]) | |
3334 | ||
3335 | (define_insn "*adddi3_carry2_cconly" | |
3336 | [(set (reg 33) | |
3337 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3338 | (match_operand:DI 2 "general_operand" "d,m")) | |
3339 | (match_dup 2))) | |
3340 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3341 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3342 | "@ | |
3343 | algr\t%0,%2 | |
3344 | alg\t%0,%2" | |
3345 | [(set_attr "op_type" "RRE,RXY")]) | |
3346 | ||
07893d4f | 3347 | (define_insn "*adddi3_cc" |
c7453384 | 3348 | [(set (reg 33) |
96fd3851 | 3349 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3350 | (match_operand:DI 2 "general_operand" "d,m")) |
3351 | (const_int 0))) | |
3352 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3353 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3354 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3355 | "@ | |
d40c829f UW |
3356 | algr\t%0,%2 |
3357 | alg\t%0,%2" | |
d3632d41 | 3358 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3359 | |
07893d4f | 3360 | (define_insn "*adddi3_cconly" |
c7453384 | 3361 | [(set (reg 33) |
96fd3851 | 3362 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3363 | (match_operand:DI 2 "general_operand" "d,m")) |
3364 | (const_int 0))) | |
3365 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3366 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3367 | "@ | |
d40c829f UW |
3368 | algr\t%0,%2 |
3369 | alg\t%0,%2" | |
d3632d41 | 3370 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3371 | |
07893d4f | 3372 | (define_insn "*adddi3_cconly2" |
c7453384 | 3373 | [(set (reg 33) |
96fd3851 | 3374 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3375 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3376 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3377 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3378 | "@ |
d40c829f UW |
3379 | algr\t%0,%2 |
3380 | alg\t%0,%2" | |
d3632d41 | 3381 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3382 | |
07893d4f | 3383 | (define_insn "*adddi3_64" |
9db1d521 | 3384 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3385 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
9db1d521 HP |
3386 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
3387 | (clobber (reg:CC 33))] | |
3388 | "TARGET_64BIT" | |
3389 | "@ | |
d40c829f UW |
3390 | agr\t%0,%2 |
3391 | aghi\t%0,%h2 | |
3392 | ag\t%0,%2" | |
d3632d41 | 3393 | [(set_attr "op_type" "RRE,RI,RXY")]) |
9db1d521 | 3394 | |
e69166de UW |
3395 | (define_insn_and_split "*adddi3_31z" |
3396 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3397 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3398 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3399 | (clobber (reg:CC 33))] | |
3400 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3401 | "#" | |
3402 | "&& reload_completed" | |
3403 | [(parallel | |
3404 | [(set (reg:CCL1 33) | |
3405 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3406 | (match_dup 7))) | |
3407 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3408 | (parallel | |
3409 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
3410 | (ltu:SI (reg:CCL1 33) (const_int 0)))) | |
3411 | (clobber (reg:CC 33))])] | |
3412 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3413 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3414 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3415 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3416 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3417 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3418 | |
07893d4f UW |
3419 | (define_insn_and_split "*adddi3_31" |
3420 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3421 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3422 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3423 | (clobber (reg:CC 33))] |
e69166de | 3424 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3425 | "#" |
3426 | "&& reload_completed" | |
3427 | [(parallel | |
3428 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
3429 | (clobber (reg:CC 33))]) | |
3430 | (parallel | |
3431 | [(set (reg:CCL1 33) | |
3432 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3433 | (match_dup 7))) | |
3434 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3435 | (set (pc) | |
3436 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
3437 | (pc) | |
3438 | (label_ref (match_dup 9)))) | |
3439 | (parallel | |
3440 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
3441 | (clobber (reg:CC 33))]) | |
3442 | (match_dup 9)] | |
97c6f7ad UW |
3443 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3444 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3445 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3446 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3447 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3448 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3449 | operands[9] = gen_label_rtx ();") |
9db1d521 HP |
3450 | |
3451 | (define_expand "adddi3" | |
07893d4f UW |
3452 | [(parallel |
3453 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3454 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f UW |
3455 | (match_operand:DI 2 "general_operand" ""))) |
3456 | (clobber (reg:CC 33))])] | |
9db1d521 | 3457 | "" |
07893d4f | 3458 | "") |
9db1d521 | 3459 | |
9db1d521 HP |
3460 | ; |
3461 | ; addsi3 instruction pattern(s). | |
3462 | ; | |
9db1d521 | 3463 | |
0a3bdf9d | 3464 | (define_insn "*addsi3_imm_cc" |
c7453384 | 3465 | [(set (reg 33) |
0a3bdf9d UW |
3466 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3467 | (match_operand:SI 2 "const_int_operand" "K")) | |
3468 | (const_int 0))) | |
3469 | (set (match_operand:SI 0 "register_operand" "=d") | |
3470 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3471 | "s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3472 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3473 | "ahi\t%0,%h2" |
077dab3b | 3474 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3475 | |
07893d4f | 3476 | (define_insn "*addsi3_carry1_cc" |
c7453384 | 3477 | [(set (reg 33) |
d3632d41 UW |
3478 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3479 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3480 | (match_dup 1))) |
d3632d41 | 3481 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3482 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3483 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3484 | "@ |
d40c829f UW |
3485 | alr\t%0,%2 |
3486 | al\t%0,%2 | |
3487 | aly\t%0,%2" | |
d3632d41 | 3488 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3489 | |
3490 | (define_insn "*addsi3_carry1_cconly" | |
c7453384 | 3491 | [(set (reg 33) |
d3632d41 UW |
3492 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3493 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3494 | (match_dup 1))) |
d3632d41 | 3495 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3496 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3497 | "@ |
d40c829f UW |
3498 | alr\t%0,%2 |
3499 | al\t%0,%2 | |
3500 | aly\t%0,%2" | |
d3632d41 | 3501 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3502 | |
3503 | (define_insn "*addsi3_carry2_cc" | |
c7453384 | 3504 | [(set (reg 33) |
d3632d41 UW |
3505 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3506 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3507 | (match_dup 2))) |
d3632d41 | 3508 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3509 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3510 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3511 | "@ |
d40c829f UW |
3512 | alr\t%0,%2 |
3513 | al\t%0,%2 | |
3514 | aly\t%0,%2" | |
d3632d41 | 3515 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3516 | |
3517 | (define_insn "*addsi3_carry2_cconly" | |
c7453384 | 3518 | [(set (reg 33) |
d3632d41 UW |
3519 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3520 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3521 | (match_dup 2))) |
d3632d41 | 3522 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3523 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3524 | "@ |
d40c829f UW |
3525 | alr\t%0,%2 |
3526 | al\t%0,%2 | |
3527 | aly\t%0,%2" | |
d3632d41 | 3528 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3529 | |
9db1d521 | 3530 | (define_insn "*addsi3_cc" |
c7453384 | 3531 | [(set (reg 33) |
d3632d41 UW |
3532 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3533 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3534 | (const_int 0))) |
d3632d41 | 3535 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3536 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3537 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3538 | "@ |
d40c829f UW |
3539 | alr\t%0,%2 |
3540 | al\t%0,%2 | |
3541 | aly\t%0,%2" | |
d3632d41 | 3542 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3543 | |
3544 | (define_insn "*addsi3_cconly" | |
c7453384 | 3545 | [(set (reg 33) |
d3632d41 UW |
3546 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3547 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3548 | (const_int 0))) |
d3632d41 | 3549 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3550 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3551 | "@ |
d40c829f UW |
3552 | alr\t%0,%2 |
3553 | al\t%0,%2 | |
3554 | aly\t%0,%2" | |
d3632d41 | 3555 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3556 | |
3557 | (define_insn "*addsi3_cconly2" | |
c7453384 | 3558 | [(set (reg 33) |
d3632d41 UW |
3559 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3560 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3561 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3562 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3563 | "@ |
d40c829f UW |
3564 | alr\t%0,%2 |
3565 | al\t%0,%2 | |
3566 | aly\t%0,%2" | |
d3632d41 | 3567 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3568 | |
07893d4f | 3569 | (define_insn "*addsi3_sign" |
d3632d41 | 3570 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f0ad121f UW |
3571 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) |
3572 | (match_operand:SI 1 "register_operand" "0,0"))) | |
07893d4f UW |
3573 | (clobber (reg:CC 33))] |
3574 | "" | |
d3632d41 | 3575 | "@ |
d40c829f UW |
3576 | ah\t%0,%2 |
3577 | ahy\t%0,%2" | |
d3632d41 | 3578 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3579 | |
9db1d521 | 3580 | (define_insn "addsi3" |
d3632d41 UW |
3581 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3582 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3583 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
9db1d521 HP |
3584 | (clobber (reg:CC 33))] |
3585 | "" | |
3586 | "@ | |
d40c829f UW |
3587 | ar\t%0,%2 |
3588 | ahi\t%0,%h2 | |
3589 | a\t%0,%2 | |
3590 | ay\t%0,%2" | |
d3632d41 | 3591 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
9db1d521 | 3592 | |
9db1d521 HP |
3593 | ; |
3594 | ; adddf3 instruction pattern(s). | |
3595 | ; | |
3596 | ||
3597 | (define_expand "adddf3" | |
3598 | [(parallel | |
3599 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3600 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3601 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3602 | (clobber (reg:CC 33))])] |
3603 | "TARGET_HARD_FLOAT" | |
3604 | "") | |
3605 | ||
3606 | (define_insn "*adddf3" | |
3607 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3608 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3609 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3610 | (clobber (reg:CC 33))] |
3611 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3612 | "@ | |
d40c829f UW |
3613 | adbr\t%0,%2 |
3614 | adb\t%0,%2" | |
ce50cae8 | 3615 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3616 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3617 | |
3ef093a8 AK |
3618 | (define_insn "*adddf3_cc" |
3619 | [(set (reg 33) | |
3620 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3621 | (match_operand:DF 2 "general_operand" "f,R")) | |
3622 | (match_operand:DF 3 "const0_operand" ""))) | |
3623 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
3624 | (plus:DF (match_dup 1) (match_dup 2)))] | |
3625 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3626 | "@ | |
d40c829f UW |
3627 | adbr\t%0,%2 |
3628 | adb\t%0,%2" | |
3ef093a8 AK |
3629 | [(set_attr "op_type" "RRE,RXE") |
3630 | (set_attr "type" "fsimpd,fsimpd")]) | |
3631 | ||
3632 | (define_insn "*adddf3_cconly" | |
3633 | [(set (reg 33) | |
3634 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3635 | (match_operand:DF 2 "general_operand" "f,R")) | |
3636 | (match_operand:DF 3 "const0_operand" ""))) | |
3637 | (clobber (match_scratch:DF 0 "=f,f"))] | |
3638 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3639 | "@ | |
d40c829f UW |
3640 | adbr\t%0,%2 |
3641 | adb\t%0,%2" | |
3ef093a8 AK |
3642 | [(set_attr "op_type" "RRE,RXE") |
3643 | (set_attr "type" "fsimpd,fsimpd")]) | |
3644 | ||
9db1d521 HP |
3645 | (define_insn "*adddf3_ibm" |
3646 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3647 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3648 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3649 | (clobber (reg:CC 33))] |
3650 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3651 | "@ | |
d40c829f UW |
3652 | adr\t%0,%2 |
3653 | ad\t%0,%2" | |
9db1d521 | 3654 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3655 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
3656 | |
3657 | ; | |
3658 | ; addsf3 instruction pattern(s). | |
3659 | ; | |
3660 | ||
3661 | (define_expand "addsf3" | |
3662 | [(parallel | |
3663 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3664 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3665 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3666 | (clobber (reg:CC 33))])] |
3667 | "TARGET_HARD_FLOAT" | |
3668 | "") | |
3669 | ||
3670 | (define_insn "*addsf3" | |
3671 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3672 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3673 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3674 | (clobber (reg:CC 33))] |
3675 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3676 | "@ | |
d40c829f UW |
3677 | aebr\t%0,%2 |
3678 | aeb\t%0,%2" | |
ce50cae8 | 3679 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3680 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 3681 | |
3ef093a8 AK |
3682 | (define_insn "*addsf3_cc" |
3683 | [(set (reg 33) | |
3684 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3685 | (match_operand:SF 2 "general_operand" "f,R")) | |
3686 | (match_operand:SF 3 "const0_operand" ""))) | |
3687 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
3688 | (plus:SF (match_dup 1) (match_dup 2)))] | |
3689 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3690 | "@ | |
d40c829f UW |
3691 | aebr\t%0,%2 |
3692 | aeb\t%0,%2" | |
3ef093a8 AK |
3693 | [(set_attr "op_type" "RRE,RXE") |
3694 | (set_attr "type" "fsimps,fsimps")]) | |
3695 | ||
3696 | (define_insn "*addsf3_cconly" | |
3697 | [(set (reg 33) | |
3698 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3699 | (match_operand:SF 2 "general_operand" "f,R")) | |
3700 | (match_operand:SF 3 "const0_operand" ""))) | |
3701 | (clobber (match_scratch:SF 0 "=f,f"))] | |
3702 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3703 | "@ | |
d40c829f UW |
3704 | aebr\t%0,%2 |
3705 | aeb\t%0,%2" | |
3ef093a8 AK |
3706 | [(set_attr "op_type" "RRE,RXE") |
3707 | (set_attr "type" "fsimps,fsimps")]) | |
3708 | ||
9db1d521 HP |
3709 | (define_insn "*addsf3" |
3710 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3711 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3712 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3713 | (clobber (reg:CC 33))] |
3714 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3715 | "@ | |
d40c829f UW |
3716 | aer\t%0,%2 |
3717 | ae\t%0,%2" | |
9db1d521 | 3718 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3719 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
3720 | |
3721 | ||
3722 | ;; | |
3723 | ;;- Subtract instructions. | |
3724 | ;; | |
3725 | ||
1c7b1b7e UW |
3726 | ; |
3727 | ; subti3 instruction pattern(s). | |
3728 | ; | |
3729 | ||
3730 | (define_insn_and_split "subti3" | |
3731 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3732 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3733 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3734 | (clobber (reg:CC 33))] | |
3735 | "TARGET_64BIT" | |
3736 | "#" | |
3737 | "&& reload_completed" | |
3738 | [(parallel | |
3739 | [(set (reg:CCL2 33) | |
3740 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) | |
3741 | (match_dup 7))) | |
3742 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3743 | (parallel | |
3744 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
3745 | (gtu:DI (reg:CCL2 33) (const_int 0)))) | |
3746 | (clobber (reg:CC 33))])] | |
3747 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3748 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3749 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3750 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3751 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3752 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3753 | |
9db1d521 HP |
3754 | ; |
3755 | ; subdi3 instruction pattern(s). | |
3756 | ; | |
3757 | ||
07893d4f UW |
3758 | (define_insn "*subdi3_sign" |
3759 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3760 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3761 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3762 | (clobber (reg:CC 33))] | |
3763 | "TARGET_64BIT" | |
3764 | "@ | |
d40c829f UW |
3765 | sgfr\t%0,%2 |
3766 | sgf\t%0,%2" | |
d3632d41 | 3767 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3768 | |
3769 | (define_insn "*subdi3_zero_cc" | |
c7453384 | 3770 | [(set (reg 33) |
07893d4f UW |
3771 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3772 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3773 | (const_int 0))) | |
3774 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3775 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3776 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3777 | "@ | |
d40c829f UW |
3778 | slgfr\t%0,%2 |
3779 | slgf\t%0,%2" | |
d3632d41 | 3780 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3781 | |
3782 | (define_insn "*subdi3_zero_cconly" | |
c7453384 | 3783 | [(set (reg 33) |
07893d4f UW |
3784 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3785 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3786 | (const_int 0))) | |
3787 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3788 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3789 | "@ | |
d40c829f UW |
3790 | slgfr\t%0,%2 |
3791 | slgf\t%0,%2" | |
d3632d41 | 3792 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3793 | |
3794 | (define_insn "*subdi3_zero" | |
3795 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3796 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3797 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3798 | (clobber (reg:CC 33))] | |
3799 | "TARGET_64BIT" | |
3800 | "@ | |
d40c829f UW |
3801 | slgfr\t%0,%2 |
3802 | slgf\t%0,%2" | |
d3632d41 | 3803 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3804 | |
b2ba71ca UW |
3805 | (define_insn "*subdi3_borrow_cc" |
3806 | [(set (reg 33) | |
3807 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3808 | (match_operand:DI 2 "general_operand" "d,m")) | |
3809 | (match_dup 1))) | |
3810 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3811 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3812 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3813 | "@ | |
3814 | slgr\t%0,%2 | |
3815 | slg\t%0,%2" | |
3816 | [(set_attr "op_type" "RRE,RXY")]) | |
3817 | ||
3818 | (define_insn "*subdi3_borrow_cconly" | |
3819 | [(set (reg 33) | |
3820 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3821 | (match_operand:DI 2 "general_operand" "d,m")) | |
3822 | (match_dup 1))) | |
3823 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3824 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3825 | "@ | |
3826 | slgr\t%0,%2 | |
3827 | slg\t%0,%2" | |
3828 | [(set_attr "op_type" "RRE,RXY")]) | |
3829 | ||
07893d4f UW |
3830 | (define_insn "*subdi3_cc" |
3831 | [(set (reg 33) | |
3832 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3833 | (match_operand:DI 2 "general_operand" "d,m")) | |
3834 | (const_int 0))) | |
3835 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3836 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3837 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3838 | "@ |
d40c829f UW |
3839 | slgr\t%0,%2 |
3840 | slg\t%0,%2" | |
d3632d41 | 3841 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3842 | |
5d880bd2 UW |
3843 | (define_insn "*subdi3_cc2" |
3844 | [(set (reg 33) | |
3845 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
3846 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3847 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3848 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3849 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3850 | "@ | |
3851 | slgr\t%0,%2 | |
3852 | slg\t%0,%2" | |
3853 | [(set_attr "op_type" "RRE,RXY")]) | |
3854 | ||
07893d4f UW |
3855 | (define_insn "*subdi3_cconly" |
3856 | [(set (reg 33) | |
3857 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3858 | (match_operand:DI 2 "general_operand" "d,m")) | |
3859 | (const_int 0))) | |
3860 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3861 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3862 | "@ |
d40c829f UW |
3863 | slgr\t%0,%2 |
3864 | slg\t%0,%2" | |
d3632d41 | 3865 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3866 | |
5d880bd2 UW |
3867 | (define_insn "*subdi3_cconly2" |
3868 | [(set (reg 33) | |
3869 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
3870 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3871 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3872 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3873 | "@ | |
3874 | slgr\t%0,%2 | |
3875 | slg\t%0,%2" | |
3876 | [(set_attr "op_type" "RRE,RXY")]) | |
3877 | ||
9db1d521 HP |
3878 | (define_insn "*subdi3_64" |
3879 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3880 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3881 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
3882 | (clobber (reg:CC 33))] | |
3883 | "TARGET_64BIT" | |
3884 | "@ | |
d40c829f UW |
3885 | sgr\t%0,%2 |
3886 | sg\t%0,%2" | |
077dab3b | 3887 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3888 | |
e69166de UW |
3889 | (define_insn_and_split "*subdi3_31z" |
3890 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3891 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3892 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3893 | (clobber (reg:CC 33))] | |
3894 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3895 | "#" | |
3896 | "&& reload_completed" | |
3897 | [(parallel | |
3898 | [(set (reg:CCL2 33) | |
3899 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3900 | (match_dup 7))) | |
3901 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3902 | (parallel | |
3903 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
3904 | (gtu:SI (reg:CCL2 33) (const_int 0)))) | |
3905 | (clobber (reg:CC 33))])] | |
3906 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3907 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3908 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3909 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3910 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3911 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3912 | |
07893d4f UW |
3913 | (define_insn_and_split "*subdi3_31" |
3914 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3915 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3916 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3917 | (clobber (reg:CC 33))] |
e69166de | 3918 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3919 | "#" |
3920 | "&& reload_completed" | |
3921 | [(parallel | |
3922 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
3923 | (clobber (reg:CC 33))]) | |
3924 | (parallel | |
3925 | [(set (reg:CCL2 33) | |
3926 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3927 | (match_dup 7))) | |
3928 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3929 | (set (pc) | |
3930 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
3931 | (pc) | |
3932 | (label_ref (match_dup 9)))) | |
3933 | (parallel | |
3934 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
3935 | (clobber (reg:CC 33))]) | |
3936 | (match_dup 9)] | |
97c6f7ad UW |
3937 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3938 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3939 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3940 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3941 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3942 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3943 | operands[9] = gen_label_rtx ();") |
07893d4f UW |
3944 | |
3945 | (define_expand "subdi3" | |
3946 | [(parallel | |
3947 | [(set (match_operand:DI 0 "register_operand" "") | |
3948 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3949 | (match_operand:DI 2 "general_operand" ""))) | |
3950 | (clobber (reg:CC 33))])] | |
9db1d521 | 3951 | "" |
07893d4f | 3952 | "") |
9db1d521 HP |
3953 | |
3954 | ; | |
3955 | ; subsi3 instruction pattern(s). | |
3956 | ; | |
3957 | ||
07893d4f UW |
3958 | (define_insn "*subsi3_borrow_cc" |
3959 | [(set (reg 33) | |
d3632d41 UW |
3960 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3961 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3962 | (match_dup 1))) |
d3632d41 | 3963 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3964 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3965 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3966 | "@ |
d40c829f UW |
3967 | slr\t%0,%2 |
3968 | sl\t%0,%2 | |
3969 | sly\t%0,%2" | |
d3632d41 | 3970 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3971 | |
3972 | (define_insn "*subsi3_borrow_cconly" | |
3973 | [(set (reg 33) | |
d3632d41 UW |
3974 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3975 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3976 | (match_dup 1))) |
d3632d41 | 3977 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 3978 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3979 | "@ |
d40c829f UW |
3980 | slr\t%0,%2 |
3981 | sl\t%0,%2 | |
3982 | sly\t%0,%2" | |
b2ba71ca | 3983 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3984 | |
9db1d521 HP |
3985 | (define_insn "*subsi3_cc" |
3986 | [(set (reg 33) | |
d3632d41 UW |
3987 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3988 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3989 | (const_int 0))) |
d3632d41 | 3990 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3991 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3992 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3993 | "@ |
d40c829f UW |
3994 | slr\t%0,%2 |
3995 | sl\t%0,%2 | |
3996 | sly\t%0,%2" | |
d3632d41 | 3997 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3998 | |
5d880bd2 UW |
3999 | (define_insn "*subsi3_cc2" |
4000 | [(set (reg 33) | |
4001 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
4002 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4003 | (set (match_operand:SI 0 "register_operand" "=d,d,d") | |
4004 | (minus:SI (match_dup 1) (match_dup 2)))] | |
4005 | "s390_match_ccmode (insn, CCL3mode)" | |
4006 | "@ | |
4007 | slr\t%0,%2 | |
4008 | sl\t%0,%2 | |
4009 | sly\t%0,%2" | |
4010 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4011 | ||
9db1d521 HP |
4012 | (define_insn "*subsi3_cconly" |
4013 | [(set (reg 33) | |
d3632d41 UW |
4014 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4015 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4016 | (const_int 0))) |
d3632d41 | 4017 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4018 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4019 | "@ |
d40c829f UW |
4020 | slr\t%0,%2 |
4021 | sl\t%0,%2 | |
4022 | sly\t%0,%2" | |
d3632d41 | 4023 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4024 | |
5d880bd2 UW |
4025 | (define_insn "*subsi3_cconly2" |
4026 | [(set (reg 33) | |
4027 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
4028 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4029 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
4030 | "s390_match_ccmode (insn, CCL3mode)" | |
4031 | "@ | |
4032 | slr\t%0,%2 | |
4033 | sl\t%0,%2 | |
4034 | sly\t%0,%2" | |
4035 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4036 | ||
07893d4f | 4037 | (define_insn "*subsi3_sign" |
d3632d41 UW |
4038 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4039 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4040 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
4041 | (clobber (reg:CC 33))] |
4042 | "" | |
d3632d41 | 4043 | "@ |
d40c829f UW |
4044 | sh\t%0,%2 |
4045 | shy\t%0,%2" | |
d3632d41 | 4046 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 4047 | |
9db1d521 | 4048 | (define_insn "subsi3" |
d3632d41 UW |
4049 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4050 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
4051 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
4052 | (clobber (reg:CC 33))] |
4053 | "" | |
4054 | "@ | |
d40c829f UW |
4055 | sr\t%0,%2 |
4056 | s\t%0,%2 | |
4057 | sy\t%0,%2" | |
d3632d41 | 4058 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4059 | |
9db1d521 HP |
4060 | |
4061 | ; | |
4062 | ; subdf3 instruction pattern(s). | |
4063 | ; | |
4064 | ||
4065 | (define_expand "subdf3" | |
4066 | [(parallel | |
4067 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4068 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4069 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4070 | (clobber (reg:CC 33))])] |
4071 | "TARGET_HARD_FLOAT" | |
4072 | "") | |
4073 | ||
4074 | (define_insn "*subdf3" | |
4075 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4076 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4077 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4078 | (clobber (reg:CC 33))] |
4079 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4080 | "@ | |
d40c829f UW |
4081 | sdbr\t%0,%2 |
4082 | sdb\t%0,%2" | |
ce50cae8 | 4083 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4084 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 4085 | |
3ef093a8 AK |
4086 | (define_insn "*subdf3_cc" |
4087 | [(set (reg 33) | |
4dbb5970 | 4088 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4089 | (match_operand:DF 2 "general_operand" "f,R")) |
4090 | (match_operand:DF 3 "const0_operand" ""))) | |
4091 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
db09b5b6 | 4092 | (minus:DF (match_dup 1) (match_dup 2)))] |
3ef093a8 AK |
4093 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4094 | "@ | |
d40c829f UW |
4095 | sdbr\t%0,%2 |
4096 | sdb\t%0,%2" | |
3ef093a8 AK |
4097 | [(set_attr "op_type" "RRE,RXE") |
4098 | (set_attr "type" "fsimpd,fsimpd")]) | |
4099 | ||
4100 | (define_insn "*subdf3_cconly" | |
4101 | [(set (reg 33) | |
4dbb5970 | 4102 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4103 | (match_operand:DF 2 "general_operand" "f,R")) |
4104 | (match_operand:DF 3 "const0_operand" ""))) | |
4105 | (clobber (match_scratch:DF 0 "=f,f"))] | |
4106 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4107 | "@ | |
d40c829f UW |
4108 | sdbr\t%0,%2 |
4109 | sdb\t%0,%2" | |
3ef093a8 AK |
4110 | [(set_attr "op_type" "RRE,RXE") |
4111 | (set_attr "type" "fsimpd,fsimpd")]) | |
4112 | ||
9db1d521 HP |
4113 | (define_insn "*subdf3_ibm" |
4114 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4115 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4116 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4117 | (clobber (reg:CC 33))] |
4118 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4119 | "@ | |
d40c829f UW |
4120 | sdr\t%0,%2 |
4121 | sd\t%0,%2" | |
9db1d521 | 4122 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4123 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
4124 | |
4125 | ; | |
4126 | ; subsf3 instruction pattern(s). | |
4127 | ; | |
4128 | ||
4129 | (define_expand "subsf3" | |
4130 | [(parallel | |
4131 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4132 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4133 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4134 | (clobber (reg:CC 33))])] |
4135 | "TARGET_HARD_FLOAT" | |
4136 | "") | |
4137 | ||
4138 | (define_insn "*subsf3" | |
4139 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4140 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4141 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4142 | (clobber (reg:CC 33))] |
4143 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4144 | "@ | |
d40c829f UW |
4145 | sebr\t%0,%2 |
4146 | seb\t%0,%2" | |
ce50cae8 | 4147 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4148 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 4149 | |
3ef093a8 AK |
4150 | (define_insn "*subsf3_cc" |
4151 | [(set (reg 33) | |
4dbb5970 | 4152 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4153 | (match_operand:SF 2 "general_operand" "f,R")) |
4154 | (match_operand:SF 3 "const0_operand" ""))) | |
4155 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
4156 | (minus:SF (match_dup 1) (match_dup 2)))] | |
4157 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4158 | "@ | |
d40c829f UW |
4159 | sebr\t%0,%2 |
4160 | seb\t%0,%2" | |
3ef093a8 AK |
4161 | [(set_attr "op_type" "RRE,RXE") |
4162 | (set_attr "type" "fsimps,fsimps")]) | |
4163 | ||
4164 | (define_insn "*subsf3_cconly" | |
4165 | [(set (reg 33) | |
4dbb5970 | 4166 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4167 | (match_operand:SF 2 "general_operand" "f,R")) |
4168 | (match_operand:SF 3 "const0_operand" ""))) | |
4169 | (clobber (match_scratch:SF 0 "=f,f"))] | |
4170 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4171 | "@ | |
d40c829f UW |
4172 | sebr\t%0,%2 |
4173 | seb\t%0,%2" | |
3ef093a8 AK |
4174 | [(set_attr "op_type" "RRE,RXE") |
4175 | (set_attr "type" "fsimps,fsimps")]) | |
4176 | ||
9db1d521 HP |
4177 | (define_insn "*subsf3_ibm" |
4178 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4179 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4180 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4181 | (clobber (reg:CC 33))] |
4182 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4183 | "@ | |
d40c829f UW |
4184 | ser\t%0,%2 |
4185 | se\t%0,%2" | |
9db1d521 | 4186 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4187 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
4188 | |
4189 | ||
e69166de UW |
4190 | ;; |
4191 | ;;- Conditional add/subtract instructions. | |
4192 | ;; | |
4193 | ||
4194 | ; | |
4195 | ; adddicc instruction pattern(s). | |
4196 | ; | |
4197 | ||
4198 | (define_insn "*adddi3_alc_cc" | |
2f7e5a0d | 4199 | [(set (reg 33) |
e69166de UW |
4200 | (compare |
4201 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4202 | (match_operand:DI 2 "general_operand" "d,m")) | |
4203 | (match_operand:DI 3 "s390_alc_comparison" "")) | |
4204 | (const_int 0))) | |
4205 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4206 | (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4207 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
e69166de | 4208 | "@ |
fc0ea003 UW |
4209 | alcgr\t%0,%2 |
4210 | alcg\t%0,%2" | |
e69166de UW |
4211 | [(set_attr "op_type" "RRE,RXY")]) |
4212 | ||
4213 | (define_insn "*adddi3_alc" | |
4214 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4215 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4216 | (match_operand:DI 2 "general_operand" "d,m")) | |
4217 | (match_operand:DI 3 "s390_alc_comparison" ""))) | |
2f7e5a0d EC |
4218 | (clobber (reg:CC 33))] |
4219 | "TARGET_64BIT" | |
e69166de | 4220 | "@ |
fc0ea003 UW |
4221 | alcgr\t%0,%2 |
4222 | alcg\t%0,%2" | |
e69166de UW |
4223 | [(set_attr "op_type" "RRE,RXY")]) |
4224 | ||
4225 | (define_insn "*subdi3_slb_cc" | |
2f7e5a0d | 4226 | [(set (reg 33) |
e69166de UW |
4227 | (compare |
4228 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4229 | (match_operand:DI 2 "general_operand" "d,m")) | |
4230 | (match_operand:DI 3 "s390_slb_comparison" "")) | |
4231 | (const_int 0))) | |
4232 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4233 | (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4234 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
e69166de | 4235 | "@ |
fc0ea003 UW |
4236 | slbgr\t%0,%2 |
4237 | slbg\t%0,%2" | |
e69166de UW |
4238 | [(set_attr "op_type" "RRE,RXY")]) |
4239 | ||
4240 | (define_insn "*subdi3_slb" | |
4241 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4242 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4243 | (match_operand:DI 2 "general_operand" "d,m")) | |
4244 | (match_operand:DI 3 "s390_slb_comparison" ""))) | |
2f7e5a0d EC |
4245 | (clobber (reg:CC 33))] |
4246 | "TARGET_64BIT" | |
e69166de | 4247 | "@ |
fc0ea003 UW |
4248 | slbgr\t%0,%2 |
4249 | slbg\t%0,%2" | |
e69166de UW |
4250 | [(set_attr "op_type" "RRE,RXY")]) |
4251 | ||
5d880bd2 UW |
4252 | (define_expand "adddicc" |
4253 | [(match_operand:DI 0 "register_operand" "") | |
4254 | (match_operand 1 "comparison_operator" "") | |
4255 | (match_operand:DI 2 "register_operand" "") | |
4256 | (match_operand:DI 3 "const_int_operand" "")] | |
4257 | "TARGET_64BIT" | |
4258 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4259 | s390_compare_op0, s390_compare_op1, | |
4260 | operands[0], operands[2], | |
4261 | operands[3])) FAIL; DONE;") | |
4262 | ||
e69166de UW |
4263 | ; |
4264 | ; addsicc instruction pattern(s). | |
4265 | ; | |
4266 | ||
4267 | (define_insn "*addsi3_alc_cc" | |
2f7e5a0d | 4268 | [(set (reg 33) |
e69166de UW |
4269 | (compare |
4270 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4271 | (match_operand:SI 2 "general_operand" "d,m")) | |
4272 | (match_operand:SI 3 "s390_alc_comparison" "")) | |
4273 | (const_int 0))) | |
4274 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4275 | (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4276 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4277 | "@ |
fc0ea003 UW |
4278 | alcr\t%0,%2 |
4279 | alc\t%0,%2" | |
e69166de UW |
4280 | [(set_attr "op_type" "RRE,RXY")]) |
4281 | ||
4282 | (define_insn "*addsi3_alc" | |
4283 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4284 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4285 | (match_operand:SI 2 "general_operand" "d,m")) | |
4286 | (match_operand:SI 3 "s390_alc_comparison" ""))) | |
4287 | (clobber (reg:CC 33))] | |
2f7e5a0d | 4288 | "TARGET_CPU_ZARCH" |
e69166de | 4289 | "@ |
fc0ea003 UW |
4290 | alcr\t%0,%2 |
4291 | alc\t%0,%2" | |
e69166de UW |
4292 | [(set_attr "op_type" "RRE,RXY")]) |
4293 | ||
4294 | (define_insn "*subsi3_slb_cc" | |
2f7e5a0d | 4295 | [(set (reg 33) |
e69166de UW |
4296 | (compare |
4297 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4298 | (match_operand:SI 2 "general_operand" "d,m")) | |
4299 | (match_operand:SI 3 "s390_slb_comparison" "")) | |
4300 | (const_int 0))) | |
4301 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4302 | (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4303 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4304 | "@ |
fc0ea003 UW |
4305 | slbr\t%0,%2 |
4306 | slb\t%0,%2" | |
e69166de UW |
4307 | [(set_attr "op_type" "RRE,RXY")]) |
4308 | ||
4309 | (define_insn "*subsi3_slb" | |
4310 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4311 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4312 | (match_operand:SI 2 "general_operand" "d,m")) | |
4313 | (match_operand:SI 3 "s390_slb_comparison" ""))) | |
2f7e5a0d EC |
4314 | (clobber (reg:CC 33))] |
4315 | "TARGET_CPU_ZARCH" | |
e69166de | 4316 | "@ |
fc0ea003 UW |
4317 | slbr\t%0,%2 |
4318 | slb\t%0,%2" | |
e69166de UW |
4319 | [(set_attr "op_type" "RRE,RXY")]) |
4320 | ||
5d880bd2 UW |
4321 | (define_expand "addsicc" |
4322 | [(match_operand:SI 0 "register_operand" "") | |
4323 | (match_operand 1 "comparison_operator" "") | |
4324 | (match_operand:SI 2 "register_operand" "") | |
4325 | (match_operand:SI 3 "const_int_operand" "")] | |
4326 | "TARGET_CPU_ZARCH" | |
4327 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4328 | s390_compare_op0, s390_compare_op1, | |
4329 | operands[0], operands[2], | |
4330 | operands[3])) FAIL; DONE;") | |
4331 | ||
4332 | ; | |
4333 | ; scond instruction pattern(s). | |
4334 | ; | |
4335 | ||
4336 | (define_insn_and_split "*sconddi" | |
4337 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4338 | (match_operand:DI 1 "s390_alc_comparison" "")) | |
4339 | (clobber (reg:CC 33))] | |
4340 | "TARGET_64BIT" | |
4341 | "#" | |
4342 | "&& reload_completed" | |
4343 | [(set (match_dup 0) (const_int 0)) | |
4344 | (parallel | |
4345 | [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0)) | |
4346 | (match_dup 1))) | |
4347 | (clobber (reg:CC 33))])] | |
b628bd8e | 4348 | "") |
5d880bd2 UW |
4349 | |
4350 | (define_insn_and_split "*scondsi" | |
4351 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
4352 | (match_operand:SI 1 "s390_alc_comparison" "")) | |
4353 | (clobber (reg:CC 33))] | |
4354 | "TARGET_CPU_ZARCH" | |
4355 | "#" | |
4356 | "&& reload_completed" | |
4357 | [(set (match_dup 0) (const_int 0)) | |
4358 | (parallel | |
4359 | [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0)) | |
4360 | (match_dup 1))) | |
4361 | (clobber (reg:CC 33))])] | |
b628bd8e | 4362 | "") |
5d880bd2 UW |
4363 | |
4364 | (define_insn_and_split "*sconddi_neg" | |
4365 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4366 | (match_operand:DI 1 "s390_slb_comparison" "")) | |
4367 | (clobber (reg:CC 33))] | |
4368 | "TARGET_64BIT" | |
4369 | "#" | |
4370 | "&& reload_completed" | |
4371 | [(set (match_dup 0) (const_int 0)) | |
4372 | (parallel | |
4373 | [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0)) | |
4374 | (match_dup 1))) | |
4375 | (clobber (reg:CC 33))]) | |
4376 | (parallel | |
4377 | [(set (match_dup 0) (neg:DI (match_dup 0))) | |
4378 | (clobber (reg:CC 33))])] | |
b628bd8e | 4379 | "") |
5d880bd2 UW |
4380 | |
4381 | (define_insn_and_split "*scondsi_neg" | |
4382 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
4383 | (match_operand:SI 1 "s390_slb_comparison" "")) | |
4384 | (clobber (reg:CC 33))] | |
4385 | "TARGET_CPU_ZARCH" | |
4386 | "#" | |
4387 | "&& reload_completed" | |
4388 | [(set (match_dup 0) (const_int 0)) | |
4389 | (parallel | |
4390 | [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0)) | |
4391 | (match_dup 1))) | |
4392 | (clobber (reg:CC 33))]) | |
4393 | (parallel | |
4394 | [(set (match_dup 0) (neg:SI (match_dup 0))) | |
4395 | (clobber (reg:CC 33))])] | |
b628bd8e | 4396 | "") |
5d880bd2 UW |
4397 | |
4398 | (define_expand "sltu" | |
4399 | [(match_operand:SI 0 "register_operand" "")] | |
4400 | "TARGET_CPU_ZARCH" | |
4401 | "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1, | |
4402 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4403 | ||
4404 | (define_expand "sgtu" | |
4405 | [(match_operand:SI 0 "register_operand" "")] | |
4406 | "TARGET_CPU_ZARCH" | |
4407 | "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1, | |
4408 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4409 | ||
4410 | (define_expand "sleu" | |
4411 | [(match_operand:SI 0 "register_operand" "")] | |
4412 | "TARGET_CPU_ZARCH" | |
4413 | "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1, | |
4414 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4415 | ||
4416 | (define_expand "sgeu" | |
4417 | [(match_operand:SI 0 "register_operand" "")] | |
4418 | "TARGET_CPU_ZARCH" | |
4419 | "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1, | |
4420 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4421 | ||
e69166de | 4422 | |
9db1d521 HP |
4423 | ;; |
4424 | ;;- Multiply instructions. | |
4425 | ;; | |
4426 | ||
4023fb28 UW |
4427 | ; |
4428 | ; muldi3 instruction pattern(s). | |
4429 | ; | |
9db1d521 | 4430 | |
07893d4f UW |
4431 | (define_insn "*muldi3_sign" |
4432 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4433 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4434 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4435 | "TARGET_64BIT" | |
4436 | "@ | |
d40c829f UW |
4437 | msgfr\t%0,%2 |
4438 | msgf\t%0,%2" | |
d3632d41 | 4439 | [(set_attr "op_type" "RRE,RXY") |
ed0e512a | 4440 | (set_attr "type" "imuldi")]) |
07893d4f | 4441 | |
4023fb28 | 4442 | (define_insn "muldi3" |
9db1d521 | 4443 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4444 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4445 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4446 | "TARGET_64BIT" |
4447 | "@ | |
d40c829f UW |
4448 | msgr\t%0,%2 |
4449 | mghi\t%0,%h2 | |
4450 | msg\t%0,%2" | |
d3632d41 | 4451 | [(set_attr "op_type" "RRE,RI,RXY") |
ed0e512a | 4452 | (set_attr "type" "imuldi")]) |
f2d3c02a | 4453 | |
9db1d521 HP |
4454 | ; |
4455 | ; mulsi3 instruction pattern(s). | |
4456 | ; | |
4457 | ||
f1e77d83 UW |
4458 | (define_insn "*mulsi3_sign" |
4459 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4460 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4461 | (match_operand:SI 1 "register_operand" "0")))] | |
4462 | "" | |
4463 | "mh\t%0,%2" | |
4464 | [(set_attr "op_type" "RX") | |
ed0e512a | 4465 | (set_attr "type" "imulhi")]) |
f1e77d83 | 4466 | |
9db1d521 | 4467 | (define_insn "mulsi3" |
d3632d41 UW |
4468 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4469 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4470 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4471 | "" |
4472 | "@ | |
d40c829f UW |
4473 | msr\t%0,%2 |
4474 | mhi\t%0,%h2 | |
4475 | ms\t%0,%2 | |
4476 | msy\t%0,%2" | |
d3632d41 | 4477 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
ed0e512a | 4478 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi")]) |
9db1d521 | 4479 | |
4023fb28 UW |
4480 | ; |
4481 | ; mulsidi3 instruction pattern(s). | |
4482 | ; | |
4483 | ||
f1e77d83 UW |
4484 | (define_insn "mulsidi3" |
4485 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4486 | (mult:DI (sign_extend:DI | |
4487 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4488 | (sign_extend:DI | |
4489 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4490 | "!TARGET_64BIT" |
f1e77d83 UW |
4491 | "@ |
4492 | mr\t%0,%2 | |
4493 | m\t%0,%2" | |
4494 | [(set_attr "op_type" "RR,RX") | |
ed0e512a | 4495 | (set_attr "type" "imulsi")]) |
4023fb28 | 4496 | |
f1e77d83 UW |
4497 | ; |
4498 | ; umulsidi3 instruction pattern(s). | |
4499 | ; | |
c7453384 | 4500 | |
f1e77d83 UW |
4501 | (define_insn "umulsidi3" |
4502 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4503 | (mult:DI (zero_extend:DI | |
4504 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4505 | (zero_extend:DI | |
4506 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4507 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4508 | "@ | |
4509 | mlr\t%0,%2 | |
4510 | ml\t%0,%2" | |
4511 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 4512 | (set_attr "type" "imulsi")]) |
c7453384 | 4513 | |
9db1d521 HP |
4514 | ; |
4515 | ; muldf3 instruction pattern(s). | |
4516 | ; | |
4517 | ||
4518 | (define_expand "muldf3" | |
553e5ce9 UW |
4519 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4520 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
4521 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4522 | "TARGET_HARD_FLOAT" |
4523 | "") | |
4524 | ||
4525 | (define_insn "*muldf3" | |
4526 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4527 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4528 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4529 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4530 | "@ | |
d40c829f UW |
4531 | mdbr\t%0,%2 |
4532 | mdb\t%0,%2" | |
ce50cae8 | 4533 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4534 | (set_attr "type" "fmuld")]) |
9db1d521 HP |
4535 | |
4536 | (define_insn "*muldf3_ibm" | |
4537 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4538 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4539 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4540 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4541 | "@ | |
d40c829f UW |
4542 | mdr\t%0,%2 |
4543 | md\t%0,%2" | |
9db1d521 | 4544 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4545 | (set_attr "type" "fmuld")]) |
9db1d521 | 4546 | |
a1b892b5 AK |
4547 | (define_insn "*fmadddf" |
4548 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4549 | (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") | |
4550 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4551 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4552 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4553 | "@ |
4554 | madbr\t%0,%1,%2 | |
4555 | madb\t%0,%1,%2" | |
4556 | [(set_attr "op_type" "RRE,RXE") | |
4557 | (set_attr "type" "fmuld")]) | |
4558 | ||
4559 | (define_insn "*fmsubdf" | |
4560 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4561 | (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") | |
4562 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4563 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4564 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4565 | "@ |
4566 | msdbr\t%0,%1,%2 | |
4567 | msdb\t%0,%1,%2" | |
4568 | [(set_attr "op_type" "RRE,RXE") | |
4569 | (set_attr "type" "fmuld")]) | |
4570 | ||
9db1d521 HP |
4571 | ; |
4572 | ; mulsf3 instruction pattern(s). | |
4573 | ; | |
4574 | ||
4575 | (define_expand "mulsf3" | |
553e5ce9 UW |
4576 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4577 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
4578 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4579 | "TARGET_HARD_FLOAT" |
4580 | "") | |
4581 | ||
4582 | (define_insn "*mulsf3" | |
4583 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4584 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4585 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4586 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4587 | "@ | |
d40c829f UW |
4588 | meebr\t%0,%2 |
4589 | meeb\t%0,%2" | |
ce50cae8 | 4590 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4591 | (set_attr "type" "fmuls")]) |
9db1d521 HP |
4592 | |
4593 | (define_insn "*mulsf3_ibm" | |
4594 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4595 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4596 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4597 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4598 | "@ | |
d40c829f UW |
4599 | mer\t%0,%2 |
4600 | me\t%0,%2" | |
9db1d521 | 4601 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4602 | (set_attr "type" "fmuls")]) |
9db1d521 | 4603 | |
a1b892b5 AK |
4604 | (define_insn "*fmaddsf" |
4605 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4606 | (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") | |
4607 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4608 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4609 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4610 | "@ |
4611 | maebr\t%0,%1,%2 | |
4612 | maeb\t%0,%1,%2" | |
4613 | [(set_attr "op_type" "RRE,RXE") | |
4614 | (set_attr "type" "fmuls")]) | |
4615 | ||
4616 | (define_insn "*fmsubsf" | |
4617 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4618 | (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") | |
4619 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4620 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4621 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4622 | "@ |
4623 | msebr\t%0,%1,%2 | |
4624 | mseb\t%0,%1,%2" | |
4625 | [(set_attr "op_type" "RRE,RXE") | |
4626 | (set_attr "type" "fmuls")]) | |
9db1d521 HP |
4627 | |
4628 | ;; | |
4629 | ;;- Divide and modulo instructions. | |
4630 | ;; | |
4631 | ||
4632 | ; | |
4023fb28 | 4633 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4634 | ; |
4635 | ||
4023fb28 UW |
4636 | (define_expand "divmoddi4" |
4637 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4638 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4639 | (match_operand:DI 2 "general_operand" ""))) |
4640 | (set (match_operand:DI 3 "general_operand" "") | |
4641 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4642 | (clobber (match_dup 4))] | |
9db1d521 | 4643 | "TARGET_64BIT" |
9db1d521 | 4644 | { |
f1e77d83 | 4645 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4646 | |
4647 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4648 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4649 | |
4650 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4651 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4652 | |
4653 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4654 | REG_NOTES (insn) = | |
4655 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4656 | ||
4657 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4658 | REG_NOTES (insn) = | |
4659 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4660 | |
9db1d521 | 4661 | DONE; |
10bbf137 | 4662 | }) |
9db1d521 HP |
4663 | |
4664 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4665 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4666 | (ior:TI | |
4023fb28 UW |
4667 | (ashift:TI |
4668 | (zero_extend:TI | |
5665e398 UW |
4669 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4670 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4671 | (const_int 64)) | |
4672 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4673 | "TARGET_64BIT" |
4674 | "@ | |
d40c829f UW |
4675 | dsgr\t%0,%2 |
4676 | dsg\t%0,%2" | |
d3632d41 | 4677 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4678 | (set_attr "type" "idiv")]) |
9db1d521 | 4679 | |
4023fb28 UW |
4680 | (define_insn "divmodtisi3" |
4681 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4682 | (ior:TI | |
4023fb28 UW |
4683 | (ashift:TI |
4684 | (zero_extend:TI | |
5665e398 | 4685 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 4686 | (sign_extend:DI |
5665e398 UW |
4687 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4688 | (const_int 64)) | |
4689 | (zero_extend:TI | |
4690 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4691 | "TARGET_64BIT" |
4023fb28 | 4692 | "@ |
d40c829f UW |
4693 | dsgfr\t%0,%2 |
4694 | dsgf\t%0,%2" | |
d3632d41 | 4695 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4696 | (set_attr "type" "idiv")]) |
9db1d521 | 4697 | |
4023fb28 UW |
4698 | ; |
4699 | ; udivmoddi4 instruction pattern(s). | |
4700 | ; | |
9db1d521 | 4701 | |
4023fb28 UW |
4702 | (define_expand "udivmoddi4" |
4703 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4704 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4705 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4706 | (set (match_operand:DI 3 "general_operand" "") | |
4707 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4708 | (clobber (match_dup 4))] | |
9db1d521 | 4709 | "TARGET_64BIT" |
9db1d521 | 4710 | { |
4023fb28 UW |
4711 | rtx insn, div_equal, mod_equal, equal; |
4712 | ||
4713 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4714 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4715 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4716 | gen_rtx_ASHIFT (TImode, |
4717 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4718 | GEN_INT (64)), |
4719 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4720 | |
4721 | operands[4] = gen_reg_rtx(TImode); | |
4722 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4723 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4724 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4725 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4726 | REG_NOTES (insn) = | |
4727 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4728 | ||
4729 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4730 | REG_NOTES (insn) = | |
4731 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4732 | ||
4733 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4734 | REG_NOTES (insn) = | |
4735 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4736 | |
9db1d521 | 4737 | DONE; |
10bbf137 | 4738 | }) |
9db1d521 HP |
4739 | |
4740 | (define_insn "udivmodtidi3" | |
4023fb28 | 4741 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 4742 | (ior:TI |
5665e398 UW |
4743 | (ashift:TI |
4744 | (zero_extend:TI | |
4745 | (truncate:DI | |
2f7e5a0d EC |
4746 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
4747 | (zero_extend:TI | |
5665e398 UW |
4748 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
4749 | (const_int 64)) | |
4750 | (zero_extend:TI | |
4751 | (truncate:DI | |
4752 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4753 | "TARGET_64BIT" |
4754 | "@ | |
d40c829f UW |
4755 | dlgr\t%0,%2 |
4756 | dlg\t%0,%2" | |
d3632d41 | 4757 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4758 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4759 | |
4760 | ; | |
4023fb28 | 4761 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4762 | ; |
4763 | ||
4023fb28 UW |
4764 | (define_expand "divmodsi4" |
4765 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4766 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4767 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4768 | (set (match_operand:SI 3 "general_operand" "") | |
4769 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4770 | (clobber (match_dup 4))] | |
9db1d521 | 4771 | "!TARGET_64BIT" |
9db1d521 | 4772 | { |
4023fb28 UW |
4773 | rtx insn, div_equal, mod_equal, equal; |
4774 | ||
4775 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4776 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4777 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4778 | gen_rtx_ASHIFT (DImode, |
4779 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4780 | GEN_INT (32)), |
4781 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4782 | |
4783 | operands[4] = gen_reg_rtx(DImode); | |
4784 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4785 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4786 | REG_NOTES (insn) = | |
4787 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4788 | ||
4789 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4790 | REG_NOTES (insn) = | |
4791 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4792 | ||
4793 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4794 | REG_NOTES (insn) = | |
4795 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4796 | |
9db1d521 | 4797 | DONE; |
10bbf137 | 4798 | }) |
9db1d521 HP |
4799 | |
4800 | (define_insn "divmoddisi3" | |
4023fb28 | 4801 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 4802 | (ior:DI |
5665e398 UW |
4803 | (ashift:DI |
4804 | (zero_extend:DI | |
4805 | (truncate:SI | |
2f7e5a0d EC |
4806 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4807 | (sign_extend:DI | |
5665e398 UW |
4808 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4809 | (const_int 32)) | |
4810 | (zero_extend:DI | |
4811 | (truncate:SI | |
4812 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4813 | "!TARGET_64BIT" |
4814 | "@ | |
d40c829f UW |
4815 | dr\t%0,%2 |
4816 | d\t%0,%2" | |
9db1d521 | 4817 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4818 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4819 | |
4820 | ; | |
4821 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4822 | ; | |
4823 | ||
f1e77d83 UW |
4824 | (define_expand "udivmodsi4" |
4825 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4826 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4827 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4828 | (set (match_operand:SI 3 "general_operand" "") | |
4829 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4830 | (clobber (match_dup 4))] | |
4831 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4832 | { | |
4833 | rtx insn, div_equal, mod_equal, equal; | |
4834 | ||
4835 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4836 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4837 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4838 | gen_rtx_ASHIFT (DImode, |
4839 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4840 | GEN_INT (32)), |
4841 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4842 | |
4843 | operands[4] = gen_reg_rtx(DImode); | |
4844 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4845 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4846 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4847 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4848 | REG_NOTES (insn) = | |
4849 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4850 | ||
4851 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4852 | REG_NOTES (insn) = | |
4853 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4854 | ||
4855 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4856 | REG_NOTES (insn) = | |
4857 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4858 | ||
4859 | DONE; | |
4860 | }) | |
4861 | ||
4862 | (define_insn "udivmoddisi3" | |
4863 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 4864 | (ior:DI |
5665e398 UW |
4865 | (ashift:DI |
4866 | (zero_extend:DI | |
4867 | (truncate:SI | |
2f7e5a0d EC |
4868 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
4869 | (zero_extend:DI | |
5665e398 UW |
4870 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
4871 | (const_int 32)) | |
4872 | (zero_extend:DI | |
4873 | (truncate:SI | |
4874 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4875 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4876 | "@ | |
4877 | dlr\t%0,%2 | |
4878 | dl\t%0,%2" | |
4879 | [(set_attr "op_type" "RRE,RXY") | |
4880 | (set_attr "type" "idiv")]) | |
4023fb28 | 4881 | |
9db1d521 HP |
4882 | (define_expand "udivsi3" |
4883 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4884 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4885 | (match_operand:SI 2 "general_operand" ""))) |
4886 | (clobber (match_dup 3))] | |
f1e77d83 | 4887 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4888 | { |
4023fb28 UW |
4889 | rtx insn, udiv_equal, umod_equal, equal; |
4890 | ||
4891 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4892 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4893 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4894 | gen_rtx_ASHIFT (DImode, |
4895 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4896 | GEN_INT (32)), |
4897 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4898 | |
4023fb28 | 4899 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4900 | |
4901 | if (CONSTANT_P (operands[2])) | |
4902 | { | |
4903 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4904 | { | |
4905 | rtx label1 = gen_label_rtx (); | |
4906 | ||
4023fb28 UW |
4907 | operands[1] = make_safe_from (operands[1], operands[0]); |
4908 | emit_move_insn (operands[0], const0_rtx); | |
4909 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4910 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4911 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4912 | emit_label (label1); |
4913 | } | |
4914 | else | |
4915 | { | |
c7453384 EC |
4916 | operands[2] = force_reg (SImode, operands[2]); |
4917 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4918 | |
4919 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4920 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4921 | operands[2])); | |
4922 | REG_NOTES (insn) = | |
4923 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4924 | |
4925 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4926 | gen_lowpart (SImode, operands[3])); |
4927 | REG_NOTES (insn) = | |
c7453384 | 4928 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4929 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4930 | } |
4931 | } | |
4932 | else | |
c7453384 | 4933 | { |
9db1d521 HP |
4934 | rtx label1 = gen_label_rtx (); |
4935 | rtx label2 = gen_label_rtx (); | |
4936 | rtx label3 = gen_label_rtx (); | |
4937 | ||
c7453384 EC |
4938 | operands[1] = force_reg (SImode, operands[1]); |
4939 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4940 | operands[2] = force_reg (SImode, operands[2]); | |
4941 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4942 | |
4943 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4944 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4945 | emit_jump_insn (gen_bgtu (label3)); | |
220a826e | 4946 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4947 | emit_jump_insn (gen_blt (label2)); |
4948 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4949 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4950 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4951 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4952 | operands[2])); | |
4953 | REG_NOTES (insn) = | |
4954 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4955 | |
4956 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4957 | gen_lowpart (SImode, operands[3])); |
4958 | REG_NOTES (insn) = | |
c7453384 | 4959 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4960 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4961 | emit_jump (label3); |
9db1d521 | 4962 | emit_label (label1); |
4023fb28 | 4963 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4964 | emit_jump (label3); |
9db1d521 | 4965 | emit_label (label2); |
4023fb28 | 4966 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4967 | emit_label (label3); |
4968 | } | |
c7453384 | 4969 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4970 | DONE; |
10bbf137 | 4971 | }) |
9db1d521 HP |
4972 | |
4973 | (define_expand "umodsi3" | |
4974 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4975 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4976 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4977 | (clobber (match_dup 3))] | |
f1e77d83 | 4978 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4979 | { |
4023fb28 UW |
4980 | rtx insn, udiv_equal, umod_equal, equal; |
4981 | ||
4982 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4983 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4984 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4985 | gen_rtx_ASHIFT (DImode, |
4986 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4987 | GEN_INT (32)), |
4988 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4989 | |
4023fb28 | 4990 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4991 | |
4992 | if (CONSTANT_P (operands[2])) | |
4993 | { | |
4994 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4995 | { | |
4996 | rtx label1 = gen_label_rtx (); | |
4997 | ||
4023fb28 UW |
4998 | operands[1] = make_safe_from (operands[1], operands[0]); |
4999 | emit_move_insn (operands[0], operands[1]); | |
5000 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 5001 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
5002 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
5003 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
5004 | emit_label (label1); |
5005 | } | |
5006 | else | |
5007 | { | |
c7453384 EC |
5008 | operands[2] = force_reg (SImode, operands[2]); |
5009 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5010 | |
5011 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5012 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5013 | operands[2])); | |
5014 | REG_NOTES (insn) = | |
5015 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5016 | |
5017 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5018 | gen_highpart (SImode, operands[3])); |
5019 | REG_NOTES (insn) = | |
c7453384 | 5020 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5021 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
5022 | } |
5023 | } | |
5024 | else | |
5025 | { | |
5026 | rtx label1 = gen_label_rtx (); | |
5027 | rtx label2 = gen_label_rtx (); | |
5028 | rtx label3 = gen_label_rtx (); | |
5029 | ||
c7453384 EC |
5030 | operands[1] = force_reg (SImode, operands[1]); |
5031 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5032 | operands[2] = force_reg (SImode, operands[2]); | |
5033 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5034 | |
c7453384 | 5035 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 5036 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 | 5037 | emit_jump_insn (gen_bgtu (label3)); |
220a826e | 5038 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
5039 | emit_jump_insn (gen_blt (label2)); |
5040 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5041 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
5042 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5043 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5044 | operands[2])); | |
5045 | REG_NOTES (insn) = | |
5046 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5047 | |
5048 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5049 | gen_highpart (SImode, operands[3])); |
5050 | REG_NOTES (insn) = | |
c7453384 | 5051 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5052 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 5053 | emit_jump (label3); |
9db1d521 | 5054 | emit_label (label1); |
4023fb28 | 5055 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5056 | emit_jump (label3); |
9db1d521 | 5057 | emit_label (label2); |
4023fb28 | 5058 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5059 | emit_label (label3); |
5060 | } | |
9db1d521 | 5061 | DONE; |
10bbf137 | 5062 | }) |
9db1d521 HP |
5063 | |
5064 | ; | |
5065 | ; divdf3 instruction pattern(s). | |
5066 | ; | |
5067 | ||
5068 | (define_expand "divdf3" | |
553e5ce9 UW |
5069 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5070 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
5071 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
5072 | "TARGET_HARD_FLOAT" |
5073 | "") | |
5074 | ||
5075 | (define_insn "*divdf3" | |
4023fb28 UW |
5076 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5077 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 5078 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5079 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5080 | "@ | |
d40c829f UW |
5081 | ddbr\t%0,%2 |
5082 | ddb\t%0,%2" | |
ce50cae8 | 5083 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 5084 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
5085 | |
5086 | (define_insn "*divdf3_ibm" | |
4023fb28 UW |
5087 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5088 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 5089 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5090 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5091 | "@ | |
d40c829f UW |
5092 | ddr\t%0,%2 |
5093 | dd\t%0,%2" | |
9db1d521 | 5094 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5095 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
5096 | |
5097 | ; | |
5098 | ; divsf3 instruction pattern(s). | |
5099 | ; | |
5100 | ||
5101 | (define_expand "divsf3" | |
553e5ce9 UW |
5102 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5103 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
5104 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
5105 | "TARGET_HARD_FLOAT" |
5106 | "") | |
5107 | ||
5108 | (define_insn "*divsf3" | |
4023fb28 UW |
5109 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5110 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 5111 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5112 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5113 | "@ | |
d40c829f UW |
5114 | debr\t%0,%2 |
5115 | deb\t%0,%2" | |
ce50cae8 | 5116 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 5117 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
5118 | |
5119 | (define_insn "*divsf3" | |
4023fb28 UW |
5120 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5121 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 5122 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5123 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5124 | "@ | |
d40c829f UW |
5125 | der\t%0,%2 |
5126 | de\t%0,%2" | |
9db1d521 | 5127 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5128 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
5129 | |
5130 | ||
5131 | ;; | |
5132 | ;;- And instructions. | |
5133 | ;; | |
5134 | ||
5135 | ; | |
5136 | ; anddi3 instruction pattern(s). | |
5137 | ; | |
5138 | ||
5139 | (define_insn "*anddi3_cc" | |
5140 | [(set (reg 33) | |
96fd3851 | 5141 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5142 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 5143 | (const_int 0))) |
4023fb28 | 5144 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
5145 | (and:DI (match_dup 1) (match_dup 2)))] |
5146 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5147 | "@ | |
d40c829f UW |
5148 | ngr\t%0,%2 |
5149 | ng\t%0,%2" | |
d3632d41 | 5150 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
5151 | |
5152 | (define_insn "*anddi3_cconly" | |
5153 | [(set (reg 33) | |
96fd3851 | 5154 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5155 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
5156 | (const_int 0))) |
5157 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
5158 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
5159 | /* Do not steal TM patterns. */ | |
5160 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 5161 | "@ |
d40c829f UW |
5162 | ngr\t%0,%2 |
5163 | ng\t%0,%2" | |
d3632d41 | 5164 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 5165 | |
8cb66696 | 5166 | (define_insn "*anddi3" |
0dfa6c5e | 5167 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
8cb66696 | 5168 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
0dfa6c5e | 5169 | "%d,o,0,0,0,0,0,0,0,0") |
8cb66696 | 5170 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5171 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) |
4023fb28 | 5172 | (clobber (reg:CC 33))] |
8cb66696 UW |
5173 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
5174 | "@ | |
5175 | # | |
5176 | # | |
5177 | nihh\t%0,%j2 | |
5178 | nihl\t%0,%j2 | |
5179 | nilh\t%0,%j2 | |
5180 | nill\t%0,%j2 | |
5181 | ngr\t%0,%2 | |
5182 | ng\t%0,%2 | |
0dfa6c5e | 5183 | # |
19b63d8e | 5184 | #" |
0dfa6c5e UW |
5185 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5186 | ||
5187 | (define_split | |
5188 | [(set (match_operand:DI 0 "s_operand" "") | |
5189 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5190 | (clobber (reg:CC 33))] | |
5191 | "reload_completed" | |
5192 | [(parallel | |
5193 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5194 | (clobber (reg:CC 33))])] | |
5195 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
4023fb28 | 5196 | |
8cb66696 UW |
5197 | (define_expand "anddi3" |
5198 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5199 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5200 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 5201 | (clobber (reg:CC 33))] |
8cb66696 UW |
5202 | "TARGET_64BIT" |
5203 | "s390_expand_logical_operator (AND, DImode, operands); DONE;") | |
9db1d521 HP |
5204 | |
5205 | ; | |
5206 | ; andsi3 instruction pattern(s). | |
5207 | ; | |
5208 | ||
5209 | (define_insn "*andsi3_cc" | |
5210 | [(set (reg 33) | |
d3632d41 UW |
5211 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5212 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5213 | (const_int 0))) |
d3632d41 | 5214 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 HP |
5215 | (and:SI (match_dup 1) (match_dup 2)))] |
5216 | "s390_match_ccmode(insn, CCTmode)" | |
5217 | "@ | |
d40c829f UW |
5218 | nr\t%0,%2 |
5219 | n\t%0,%2 | |
5220 | ny\t%0,%2" | |
d3632d41 | 5221 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
5222 | |
5223 | (define_insn "*andsi3_cconly" | |
5224 | [(set (reg 33) | |
d3632d41 UW |
5225 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5226 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5227 | (const_int 0))) |
d3632d41 | 5228 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
68f9c5e2 UW |
5229 | "s390_match_ccmode(insn, CCTmode) |
5230 | /* Do not steal TM patterns. */ | |
5231 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 5232 | "@ |
d40c829f UW |
5233 | nr\t%0,%2 |
5234 | n\t%0,%2 | |
5235 | ny\t%0,%2" | |
d3632d41 | 5236 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5237 | |
f19a9af7 | 5238 | (define_insn "*andsi3_zarch" |
0dfa6c5e UW |
5239 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q") |
5240 | (and:SI (match_operand:SI 1 "nonimmediate_operand" | |
5241 | "%d,o,0,0,0,0,0,0,0") | |
5242 | (match_operand:SI 2 "general_operand" | |
5243 | "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q"))) | |
9db1d521 | 5244 | (clobber (reg:CC 33))] |
8cb66696 | 5245 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5246 | "@ |
f19a9af7 AK |
5247 | # |
5248 | # | |
5249 | nilh\t%0,%j2 | |
2f7e5a0d | 5250 | nill\t%0,%j2 |
d40c829f UW |
5251 | nr\t%0,%2 |
5252 | n\t%0,%2 | |
8cb66696 | 5253 | ny\t%0,%2 |
0dfa6c5e | 5254 | # |
19b63d8e | 5255 | #" |
0dfa6c5e | 5256 | [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")]) |
f19a9af7 AK |
5257 | |
5258 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
5259 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5260 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5261 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
f19a9af7 | 5262 | (clobber (reg:CC 33))] |
8cb66696 | 5263 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5264 | "@ |
5265 | nr\t%0,%2 | |
8cb66696 | 5266 | n\t%0,%2 |
0dfa6c5e | 5267 | # |
19b63d8e | 5268 | #" |
0dfa6c5e UW |
5269 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5270 | ||
5271 | (define_split | |
5272 | [(set (match_operand:SI 0 "s_operand" "") | |
5273 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5274 | (clobber (reg:CC 33))] | |
5275 | "reload_completed" | |
5276 | [(parallel | |
5277 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5278 | (clobber (reg:CC 33))])] | |
5279 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
4023fb28 | 5280 | |
8cb66696 UW |
5281 | (define_expand "andsi3" |
5282 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5283 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5284 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5285 | (clobber (reg:CC 33))] |
5286 | "" | |
8cb66696 | 5287 | "s390_expand_logical_operator (AND, SImode, operands); DONE;") |
9db1d521 HP |
5288 | |
5289 | ; | |
5290 | ; andhi3 instruction pattern(s). | |
5291 | ; | |
5292 | ||
8cb66696 | 5293 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
5294 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5295 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5296 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
4023fb28 | 5297 | (clobber (reg:CC 33))] |
8cb66696 | 5298 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5299 | "@ |
d40c829f | 5300 | nr\t%0,%2 |
8cb66696 | 5301 | nill\t%0,%x2 |
0dfa6c5e | 5302 | # |
19b63d8e | 5303 | #" |
0dfa6c5e | 5304 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5305 | |
5306 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
5307 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5308 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5309 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
4023fb28 | 5310 | (clobber (reg:CC 33))] |
8cb66696 UW |
5311 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5312 | "@ | |
5313 | nr\t%0,%2 | |
0dfa6c5e | 5314 | # |
19b63d8e | 5315 | #" |
0dfa6c5e UW |
5316 | [(set_attr "op_type" "RR,SI,SS")]) |
5317 | ||
5318 | (define_split | |
5319 | [(set (match_operand:HI 0 "s_operand" "") | |
5320 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5321 | (clobber (reg:CC 33))] | |
5322 | "reload_completed" | |
5323 | [(parallel | |
5324 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5325 | (clobber (reg:CC 33))])] | |
5326 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
9db1d521 | 5327 | |
8cb66696 UW |
5328 | (define_expand "andhi3" |
5329 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5330 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5331 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5332 | (clobber (reg:CC 33))] |
5333 | "" | |
8cb66696 | 5334 | "s390_expand_logical_operator (AND, HImode, operands); DONE;") |
9db1d521 HP |
5335 | |
5336 | ; | |
5337 | ; andqi3 instruction pattern(s). | |
5338 | ; | |
5339 | ||
8cb66696 UW |
5340 | (define_insn "*andqi3_zarch" |
5341 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5342 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5343 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
4023fb28 | 5344 | (clobber (reg:CC 33))] |
8cb66696 | 5345 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5346 | "@ |
d40c829f | 5347 | nr\t%0,%2 |
8cb66696 | 5348 | nill\t%0,%b2 |
fc0ea003 UW |
5349 | ni\t%S0,%b2 |
5350 | niy\t%S0,%b2 | |
19b63d8e | 5351 | #" |
8cb66696 UW |
5352 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5353 | ||
5354 | (define_insn "*andqi3_esa" | |
5355 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5356 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5357 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
9db1d521 | 5358 | (clobber (reg:CC 33))] |
8cb66696 | 5359 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5360 | "@ |
8cb66696 | 5361 | nr\t%0,%2 |
fc0ea003 | 5362 | ni\t%S0,%b2 |
19b63d8e | 5363 | #" |
8cb66696 | 5364 | [(set_attr "op_type" "RR,SI,SS")]) |
4023fb28 | 5365 | |
8cb66696 UW |
5366 | (define_expand "andqi3" |
5367 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5368 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5369 | (match_operand:QI 2 "general_operand" ""))) | |
4023fb28 UW |
5370 | (clobber (reg:CC 33))] |
5371 | "" | |
8cb66696 | 5372 | "s390_expand_logical_operator (AND, QImode, operands); DONE;") |
9db1d521 | 5373 | |
19b63d8e UW |
5374 | ; |
5375 | ; Block and (NC) patterns. | |
5376 | ; | |
5377 | ||
5378 | (define_insn "*nc" | |
5379 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5380 | (and:BLK (match_dup 0) | |
5381 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5382 | (use (match_operand 2 "const_int_operand" "n")) | |
5383 | (clobber (reg:CC 33))] | |
5384 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5385 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 5386 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5387 | |
5388 | (define_split | |
5389 | [(set (match_operand 0 "memory_operand" "") | |
5390 | (and (match_dup 0) | |
5391 | (match_operand 1 "memory_operand" ""))) | |
5392 | (clobber (reg:CC 33))] | |
5393 | "reload_completed | |
5394 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5395 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5396 | [(parallel | |
5397 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
5398 | (use (match_dup 2)) | |
5399 | (clobber (reg:CC 33))])] | |
5400 | { | |
5401 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5402 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5403 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5404 | }) | |
5405 | ||
5406 | (define_peephole2 | |
5407 | [(parallel | |
5408 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5409 | (and:BLK (match_dup 0) | |
5410 | (match_operand:BLK 1 "memory_operand" ""))) | |
5411 | (use (match_operand 2 "const_int_operand" "")) | |
5412 | (clobber (reg:CC 33))]) | |
5413 | (parallel | |
5414 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5415 | (and:BLK (match_dup 3) | |
5416 | (match_operand:BLK 4 "memory_operand" ""))) | |
5417 | (use (match_operand 5 "const_int_operand" "")) | |
5418 | (clobber (reg:CC 33))])] | |
5419 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
5420 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5421 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5422 | [(parallel | |
5423 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
5424 | (use (match_dup 8)) | |
5425 | (clobber (reg:CC 33))])] | |
5426 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5427 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5428 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5429 | ||
9db1d521 HP |
5430 | |
5431 | ;; | |
5432 | ;;- Bit set (inclusive or) instructions. | |
5433 | ;; | |
5434 | ||
5435 | ; | |
5436 | ; iordi3 instruction pattern(s). | |
5437 | ; | |
5438 | ||
4023fb28 UW |
5439 | (define_insn "*iordi3_cc" |
5440 | [(set (reg 33) | |
96fd3851 | 5441 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5442 | (match_operand:DI 2 "general_operand" "d,m")) |
5443 | (const_int 0))) | |
5444 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5445 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5446 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5447 | "@ | |
d40c829f UW |
5448 | ogr\t%0,%2 |
5449 | og\t%0,%2" | |
d3632d41 | 5450 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5451 | |
5452 | (define_insn "*iordi3_cconly" | |
5453 | [(set (reg 33) | |
96fd3851 | 5454 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5455 | (match_operand:DI 2 "general_operand" "d,m")) |
5456 | (const_int 0))) | |
5457 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5458 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5459 | "@ | |
d40c829f UW |
5460 | ogr\t%0,%2 |
5461 | og\t%0,%2" | |
d3632d41 | 5462 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5463 | |
8cb66696 | 5464 | (define_insn "*iordi3" |
0dfa6c5e | 5465 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
bad82153 | 5466 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") |
8cb66696 | 5467 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5468 | "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) |
9db1d521 | 5469 | (clobber (reg:CC 33))] |
8cb66696 | 5470 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5471 | "@ |
f19a9af7 AK |
5472 | oihh\t%0,%i2 |
5473 | oihl\t%0,%i2 | |
5474 | oilh\t%0,%i2 | |
5475 | oill\t%0,%i2 | |
d40c829f | 5476 | ogr\t%0,%2 |
8cb66696 | 5477 | og\t%0,%2 |
0dfa6c5e | 5478 | # |
19b63d8e | 5479 | #" |
0dfa6c5e UW |
5480 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5481 | ||
5482 | (define_split | |
5483 | [(set (match_operand:DI 0 "s_operand" "") | |
5484 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5485 | (clobber (reg:CC 33))] | |
5486 | "reload_completed" | |
5487 | [(parallel | |
5488 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5489 | (clobber (reg:CC 33))])] | |
5490 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
4023fb28 | 5491 | |
8cb66696 UW |
5492 | (define_expand "iordi3" |
5493 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5494 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5495 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 5496 | (clobber (reg:CC 33))] |
8cb66696 UW |
5497 | "TARGET_64BIT" |
5498 | "s390_expand_logical_operator (IOR, DImode, operands); DONE;") | |
9db1d521 HP |
5499 | |
5500 | ; | |
5501 | ; iorsi3 instruction pattern(s). | |
5502 | ; | |
5503 | ||
4023fb28 UW |
5504 | (define_insn "*iorsi3_cc" |
5505 | [(set (reg 33) | |
d3632d41 UW |
5506 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5507 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5508 | (const_int 0))) |
d3632d41 | 5509 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5510 | (ior:SI (match_dup 1) (match_dup 2)))] |
5511 | "s390_match_ccmode(insn, CCTmode)" | |
5512 | "@ | |
d40c829f UW |
5513 | or\t%0,%2 |
5514 | o\t%0,%2 | |
5515 | oy\t%0,%2" | |
d3632d41 | 5516 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5517 | |
5518 | (define_insn "*iorsi3_cconly" | |
5519 | [(set (reg 33) | |
d3632d41 UW |
5520 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5521 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5522 | (const_int 0))) |
d3632d41 | 5523 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5524 | "s390_match_ccmode(insn, CCTmode)" |
5525 | "@ | |
d40c829f UW |
5526 | or\t%0,%2 |
5527 | o\t%0,%2 | |
5528 | oy\t%0,%2" | |
d3632d41 | 5529 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 | 5530 | |
8cb66696 | 5531 | (define_insn "*iorsi3_zarch" |
0dfa6c5e | 5532 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q") |
bad82153 | 5533 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") |
0dfa6c5e | 5534 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q"))) |
4023fb28 | 5535 | (clobber (reg:CC 33))] |
8cb66696 | 5536 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5537 | "@ |
f19a9af7 AK |
5538 | oilh\t%0,%i2 |
5539 | oill\t%0,%i2 | |
d40c829f UW |
5540 | or\t%0,%2 |
5541 | o\t%0,%2 | |
8cb66696 | 5542 | oy\t%0,%2 |
0dfa6c5e | 5543 | # |
19b63d8e | 5544 | #" |
0dfa6c5e | 5545 | [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")]) |
8cb66696 UW |
5546 | |
5547 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 5548 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 5549 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 5550 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
f19a9af7 | 5551 | (clobber (reg:CC 33))] |
8cb66696 | 5552 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5553 | "@ |
5554 | or\t%0,%2 | |
8cb66696 | 5555 | o\t%0,%2 |
0dfa6c5e | 5556 | # |
19b63d8e | 5557 | #" |
0dfa6c5e UW |
5558 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5559 | ||
5560 | (define_split | |
5561 | [(set (match_operand:SI 0 "s_operand" "") | |
5562 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5563 | (clobber (reg:CC 33))] | |
5564 | "reload_completed" | |
5565 | [(parallel | |
5566 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5567 | (clobber (reg:CC 33))])] | |
5568 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
4023fb28 | 5569 | |
8cb66696 UW |
5570 | (define_expand "iorsi3" |
5571 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5572 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5573 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5574 | (clobber (reg:CC 33))] |
5575 | "" | |
8cb66696 | 5576 | "s390_expand_logical_operator (IOR, SImode, operands); DONE;") |
4023fb28 UW |
5577 | |
5578 | ; | |
5579 | ; iorhi3 instruction pattern(s). | |
5580 | ; | |
5581 | ||
8cb66696 | 5582 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
5583 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5584 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5585 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
4023fb28 | 5586 | (clobber (reg:CC 33))] |
8cb66696 | 5587 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5588 | "@ |
d40c829f | 5589 | or\t%0,%2 |
8cb66696 | 5590 | oill\t%0,%x2 |
0dfa6c5e | 5591 | # |
19b63d8e | 5592 | #" |
0dfa6c5e | 5593 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5594 | |
5595 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
5596 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5597 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5598 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
4023fb28 | 5599 | (clobber (reg:CC 33))] |
8cb66696 UW |
5600 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5601 | "@ | |
5602 | or\t%0,%2 | |
0dfa6c5e | 5603 | # |
19b63d8e | 5604 | #" |
0dfa6c5e UW |
5605 | [(set_attr "op_type" "RR,SI,SS")]) |
5606 | ||
5607 | (define_split | |
5608 | [(set (match_operand:HI 0 "s_operand" "") | |
5609 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5610 | (clobber (reg:CC 33))] | |
5611 | "reload_completed" | |
5612 | [(parallel | |
5613 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5614 | (clobber (reg:CC 33))])] | |
5615 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
9db1d521 | 5616 | |
8cb66696 UW |
5617 | (define_expand "iorhi3" |
5618 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5619 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5620 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5621 | (clobber (reg:CC 33))] |
5622 | "" | |
8cb66696 | 5623 | "s390_expand_logical_operator (IOR, HImode, operands); DONE;") |
9db1d521 HP |
5624 | |
5625 | ; | |
4023fb28 | 5626 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5627 | ; |
5628 | ||
8cb66696 UW |
5629 | (define_insn "*iorqi3_zarch" |
5630 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5631 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5632 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
4023fb28 | 5633 | (clobber (reg:CC 33))] |
8cb66696 | 5634 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5635 | "@ |
d40c829f | 5636 | or\t%0,%2 |
8cb66696 | 5637 | oill\t%0,%b2 |
fc0ea003 UW |
5638 | oi\t%S0,%b2 |
5639 | oiy\t%S0,%b2 | |
19b63d8e | 5640 | #" |
8cb66696 UW |
5641 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5642 | ||
5643 | (define_insn "*iorqi3_esa" | |
5644 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5645 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5646 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
4023fb28 | 5647 | (clobber (reg:CC 33))] |
8cb66696 | 5648 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5649 | "@ |
8cb66696 | 5650 | or\t%0,%2 |
fc0ea003 | 5651 | oi\t%S0,%b2 |
19b63d8e | 5652 | #" |
8cb66696 | 5653 | [(set_attr "op_type" "RR,SI,SS")]) |
9db1d521 | 5654 | |
8cb66696 UW |
5655 | (define_expand "iorqi3" |
5656 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5657 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5658 | (match_operand:QI 2 "general_operand" ""))) | |
9db1d521 HP |
5659 | (clobber (reg:CC 33))] |
5660 | "" | |
8cb66696 | 5661 | "s390_expand_logical_operator (IOR, QImode, operands); DONE;") |
9db1d521 | 5662 | |
19b63d8e UW |
5663 | ; |
5664 | ; Block inclusive or (OC) patterns. | |
5665 | ; | |
5666 | ||
5667 | (define_insn "*oc" | |
5668 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5669 | (ior:BLK (match_dup 0) | |
5670 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5671 | (use (match_operand 2 "const_int_operand" "n")) | |
5672 | (clobber (reg:CC 33))] | |
5673 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5674 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 5675 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5676 | |
5677 | (define_split | |
5678 | [(set (match_operand 0 "memory_operand" "") | |
5679 | (ior (match_dup 0) | |
5680 | (match_operand 1 "memory_operand" ""))) | |
5681 | (clobber (reg:CC 33))] | |
5682 | "reload_completed | |
5683 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5684 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5685 | [(parallel | |
5686 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
5687 | (use (match_dup 2)) | |
5688 | (clobber (reg:CC 33))])] | |
5689 | { | |
5690 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5691 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5692 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5693 | }) | |
5694 | ||
5695 | (define_peephole2 | |
5696 | [(parallel | |
5697 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5698 | (ior:BLK (match_dup 0) | |
5699 | (match_operand:BLK 1 "memory_operand" ""))) | |
5700 | (use (match_operand 2 "const_int_operand" "")) | |
5701 | (clobber (reg:CC 33))]) | |
5702 | (parallel | |
5703 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5704 | (ior:BLK (match_dup 3) | |
5705 | (match_operand:BLK 4 "memory_operand" ""))) | |
5706 | (use (match_operand 5 "const_int_operand" "")) | |
5707 | (clobber (reg:CC 33))])] | |
5708 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
5709 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5710 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5711 | [(parallel | |
5712 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
5713 | (use (match_dup 8)) | |
5714 | (clobber (reg:CC 33))])] | |
5715 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5716 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5717 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5718 | ||
9db1d521 HP |
5719 | |
5720 | ;; | |
5721 | ;;- Xor instructions. | |
5722 | ;; | |
5723 | ||
5724 | ; | |
5725 | ; xordi3 instruction pattern(s). | |
5726 | ; | |
5727 | ||
4023fb28 UW |
5728 | (define_insn "*xordi3_cc" |
5729 | [(set (reg 33) | |
96fd3851 | 5730 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5731 | (match_operand:DI 2 "general_operand" "d,m")) |
5732 | (const_int 0))) | |
5733 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5734 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5735 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5736 | "@ | |
d40c829f UW |
5737 | xgr\t%0,%2 |
5738 | xg\t%0,%2" | |
d3632d41 | 5739 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5740 | |
5741 | (define_insn "*xordi3_cconly" | |
5742 | [(set (reg 33) | |
96fd3851 | 5743 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5744 | (match_operand:DI 2 "general_operand" "d,m")) |
5745 | (const_int 0))) | |
5746 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5747 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5748 | "@ | |
d40c829f UW |
5749 | xgr\t%0,%2 |
5750 | xr\t%0,%2" | |
d3632d41 | 5751 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5752 | |
8cb66696 | 5753 | (define_insn "*xordi3" |
0dfa6c5e UW |
5754 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5755 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5756 | (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) | |
9db1d521 | 5757 | (clobber (reg:CC 33))] |
8cb66696 | 5758 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5759 | "@ |
d40c829f | 5760 | xgr\t%0,%2 |
8cb66696 | 5761 | xg\t%0,%2 |
0dfa6c5e | 5762 | # |
19b63d8e | 5763 | #" |
0dfa6c5e UW |
5764 | [(set_attr "op_type" "RRE,RXY,SI,SS")]) |
5765 | ||
5766 | (define_split | |
5767 | [(set (match_operand:DI 0 "s_operand" "") | |
5768 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5769 | (clobber (reg:CC 33))] | |
5770 | "reload_completed" | |
5771 | [(parallel | |
5772 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5773 | (clobber (reg:CC 33))])] | |
5774 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
4023fb28 | 5775 | |
8cb66696 UW |
5776 | (define_expand "xordi3" |
5777 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5778 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5779 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 5780 | (clobber (reg:CC 33))] |
8cb66696 UW |
5781 | "TARGET_64BIT" |
5782 | "s390_expand_logical_operator (XOR, DImode, operands); DONE;") | |
9db1d521 HP |
5783 | |
5784 | ; | |
5785 | ; xorsi3 instruction pattern(s). | |
5786 | ; | |
5787 | ||
4023fb28 UW |
5788 | (define_insn "*xorsi3_cc" |
5789 | [(set (reg 33) | |
d3632d41 UW |
5790 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5791 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5792 | (const_int 0))) |
d3632d41 | 5793 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5794 | (xor:SI (match_dup 1) (match_dup 2)))] |
5795 | "s390_match_ccmode(insn, CCTmode)" | |
5796 | "@ | |
d40c829f UW |
5797 | xr\t%0,%2 |
5798 | x\t%0,%2 | |
5799 | xy\t%0,%2" | |
d3632d41 | 5800 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5801 | |
5802 | (define_insn "*xorsi3_cconly" | |
5803 | [(set (reg 33) | |
d3632d41 UW |
5804 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5805 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5806 | (const_int 0))) |
d3632d41 | 5807 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5808 | "s390_match_ccmode(insn, CCTmode)" |
5809 | "@ | |
d40c829f UW |
5810 | xr\t%0,%2 |
5811 | x\t%0,%2 | |
5812 | xy\t%0,%2" | |
d3632d41 | 5813 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5814 | |
8cb66696 | 5815 | (define_insn "*xorsi3" |
0dfa6c5e UW |
5816 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q") |
5817 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5818 | (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q"))) | |
9db1d521 | 5819 | (clobber (reg:CC 33))] |
8cb66696 | 5820 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5821 | "@ |
d40c829f UW |
5822 | xr\t%0,%2 |
5823 | x\t%0,%2 | |
8cb66696 | 5824 | xy\t%0,%2 |
0dfa6c5e | 5825 | # |
19b63d8e | 5826 | #" |
0dfa6c5e UW |
5827 | [(set_attr "op_type" "RR,RX,RXY,SI,SS")]) |
5828 | ||
5829 | (define_split | |
5830 | [(set (match_operand:SI 0 "s_operand" "") | |
5831 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5832 | (clobber (reg:CC 33))] | |
5833 | "reload_completed" | |
5834 | [(parallel | |
5835 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5836 | (clobber (reg:CC 33))])] | |
5837 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
8cb66696 UW |
5838 | |
5839 | (define_expand "xorsi3" | |
5840 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5841 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5842 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5843 | (clobber (reg:CC 33))] |
5844 | "" | |
8cb66696 | 5845 | "s390_expand_logical_operator (XOR, SImode, operands); DONE;") |
9db1d521 HP |
5846 | |
5847 | ; | |
5848 | ; xorhi3 instruction pattern(s). | |
5849 | ; | |
5850 | ||
8cb66696 | 5851 | (define_insn "*xorhi3" |
0dfa6c5e UW |
5852 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5853 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5854 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
4023fb28 | 5855 | (clobber (reg:CC 33))] |
8cb66696 UW |
5856 | "s390_logical_operator_ok_p (operands)" |
5857 | "@ | |
5858 | xr\t%0,%2 | |
0dfa6c5e | 5859 | # |
19b63d8e | 5860 | #" |
0dfa6c5e UW |
5861 | [(set_attr "op_type" "RR,SI,SS")]) |
5862 | ||
5863 | (define_split | |
5864 | [(set (match_operand:HI 0 "s_operand" "") | |
5865 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5866 | (clobber (reg:CC 33))] | |
5867 | "reload_completed" | |
5868 | [(parallel | |
5869 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5870 | (clobber (reg:CC 33))])] | |
5871 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
9db1d521 | 5872 | |
8cb66696 UW |
5873 | (define_expand "xorhi3" |
5874 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5875 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5876 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5877 | (clobber (reg:CC 33))] |
5878 | "" | |
8cb66696 | 5879 | "s390_expand_logical_operator (XOR, HImode, operands); DONE;") |
9db1d521 HP |
5880 | |
5881 | ; | |
5882 | ; xorqi3 instruction pattern(s). | |
5883 | ; | |
5884 | ||
8cb66696 UW |
5885 | (define_insn "*xorqi3" |
5886 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q") | |
5887 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0") | |
5888 | (match_operand:QI 2 "general_operand" "d,n,n,Q"))) | |
4023fb28 | 5889 | (clobber (reg:CC 33))] |
8cb66696 | 5890 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5891 | "@ |
8cb66696 | 5892 | xr\t%0,%2 |
fc0ea003 UW |
5893 | xi\t%S0,%b2 |
5894 | xiy\t%S0,%b2 | |
19b63d8e | 5895 | #" |
8cb66696 | 5896 | [(set_attr "op_type" "RR,SI,SIY,SS")]) |
4023fb28 | 5897 | |
8cb66696 UW |
5898 | (define_expand "xorqi3" |
5899 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5900 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5901 | (match_operand:QI 2 "general_operand" ""))) | |
4023fb28 UW |
5902 | (clobber (reg:CC 33))] |
5903 | "" | |
8cb66696 | 5904 | "s390_expand_logical_operator (XOR, QImode, operands); DONE;") |
9db1d521 | 5905 | |
19b63d8e UW |
5906 | ; |
5907 | ; Block exclusive or (XC) patterns. | |
5908 | ; | |
5909 | ||
5910 | (define_insn "*xc" | |
5911 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5912 | (xor:BLK (match_dup 0) | |
5913 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5914 | (use (match_operand 2 "const_int_operand" "n")) | |
5915 | (clobber (reg:CC 33))] | |
5916 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5917 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 5918 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5919 | |
5920 | (define_split | |
5921 | [(set (match_operand 0 "memory_operand" "") | |
5922 | (xor (match_dup 0) | |
5923 | (match_operand 1 "memory_operand" ""))) | |
5924 | (clobber (reg:CC 33))] | |
5925 | "reload_completed | |
5926 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5927 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5928 | [(parallel | |
5929 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
5930 | (use (match_dup 2)) | |
5931 | (clobber (reg:CC 33))])] | |
5932 | { | |
5933 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5934 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5935 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5936 | }) | |
5937 | ||
5938 | (define_peephole2 | |
5939 | [(parallel | |
5940 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5941 | (xor:BLK (match_dup 0) | |
5942 | (match_operand:BLK 1 "memory_operand" ""))) | |
5943 | (use (match_operand 2 "const_int_operand" "")) | |
5944 | (clobber (reg:CC 33))]) | |
5945 | (parallel | |
5946 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5947 | (xor:BLK (match_dup 3) | |
5948 | (match_operand:BLK 4 "memory_operand" ""))) | |
5949 | (use (match_operand 5 "const_int_operand" "")) | |
5950 | (clobber (reg:CC 33))])] | |
5951 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
5952 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5953 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5954 | [(parallel | |
5955 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
5956 | (use (match_dup 8)) | |
5957 | (clobber (reg:CC 33))])] | |
5958 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5959 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5960 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5961 | ||
5962 | ; | |
5963 | ; Block xor (XC) patterns with src == dest. | |
5964 | ; | |
5965 | ||
5966 | (define_insn "*xc_zero" | |
5967 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5968 | (const_int 0)) | |
5969 | (use (match_operand 1 "const_int_operand" "n")) | |
5970 | (clobber (reg:CC 33))] | |
5971 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" | |
fc0ea003 | 5972 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 5973 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5974 | |
5975 | (define_peephole2 | |
5976 | [(parallel | |
5977 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5978 | (const_int 0)) | |
5979 | (use (match_operand 1 "const_int_operand" "")) | |
5980 | (clobber (reg:CC 33))]) | |
5981 | (parallel | |
5982 | [(set (match_operand:BLK 2 "memory_operand" "") | |
5983 | (const_int 0)) | |
5984 | (use (match_operand 3 "const_int_operand" "")) | |
5985 | (clobber (reg:CC 33))])] | |
5986 | "s390_offset_p (operands[0], operands[2], operands[1]) | |
5987 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
5988 | [(parallel | |
5989 | [(set (match_dup 4) (const_int 0)) | |
5990 | (use (match_dup 5)) | |
5991 | (clobber (reg:CC 33))])] | |
5992 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5993 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
5994 | ||
9db1d521 HP |
5995 | |
5996 | ;; | |
5997 | ;;- Negate instructions. | |
5998 | ;; | |
5999 | ||
6000 | ; | |
6001 | ; negdi2 instruction pattern(s). | |
6002 | ; | |
6003 | ||
6004 | (define_expand "negdi2" | |
6005 | [(parallel | |
6006 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6007 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
6008 | (clobber (reg:CC 33))])] | |
6009 | "" | |
6010 | "") | |
6011 | ||
26a89301 UW |
6012 | (define_insn "*negdi2_sign_cc" |
6013 | [(set (reg 33) | |
6014 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6015 | (match_operand:SI 1 "register_operand" "d") 0) | |
6016 | (const_int 32)) (const_int 32))) | |
6017 | (const_int 0))) | |
6018 | (set (match_operand:DI 0 "register_operand" "=d") | |
6019 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
6020 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6021 | "lcgfr\t%0,%1" | |
6022 | [(set_attr "op_type" "RRE")]) | |
6023 | ||
6024 | (define_insn "*negdi2_sign" | |
6025 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6026 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
6027 | (clobber (reg:CC 33))] | |
6028 | "TARGET_64BIT" | |
6029 | "lcgfr\t%0,%1" | |
6030 | [(set_attr "op_type" "RRE")]) | |
6031 | ||
6032 | (define_insn "*negdi2_cc" | |
6033 | [(set (reg 33) | |
6034 | (compare (neg:DI (match_operand:DI 1 "register_operand" "d")) | |
6035 | (const_int 0))) | |
6036 | (set (match_operand:DI 0 "register_operand" "=d") | |
6037 | (neg:DI (match_dup 1)))] | |
6038 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6039 | "lcgr\t%0,%1" | |
6040 | [(set_attr "op_type" "RRE")]) | |
6041 | ||
6042 | (define_insn "*negdi2_cconly" | |
6043 | [(set (reg 33) | |
6044 | (compare (neg:DI (match_operand:DI 1 "register_operand" "d")) | |
6045 | (const_int 0))) | |
6046 | (clobber (match_scratch:DI 0 "=d"))] | |
6047 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6048 | "lcgr\t%0,%1" | |
6049 | [(set_attr "op_type" "RRE")]) | |
6050 | ||
9db1d521 HP |
6051 | (define_insn "*negdi2_64" |
6052 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6053 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
6054 | (clobber (reg:CC 33))] | |
6055 | "TARGET_64BIT" | |
d40c829f | 6056 | "lcgr\t%0,%1" |
26a89301 | 6057 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 6058 | |
26a89301 | 6059 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
6060 | [(set (match_operand:DI 0 "register_operand" "=d") |
6061 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
6062 | (clobber (reg:CC 33))] | |
6063 | "!TARGET_64BIT" | |
26a89301 UW |
6064 | "#" |
6065 | "&& reload_completed" | |
6066 | [(parallel | |
6067 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
6068 | (clobber (reg:CC 33))]) | |
6069 | (parallel | |
6070 | [(set (reg:CCAP 33) | |
6071 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) | |
6072 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
6073 | (set (pc) | |
6074 | (if_then_else (ne (reg:CCAP 33) (const_int 0)) | |
6075 | (pc) | |
6076 | (label_ref (match_dup 6)))) | |
6077 | (parallel | |
6078 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
6079 | (clobber (reg:CC 33))]) | |
6080 | (match_dup 6)] | |
6081 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
6082 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
6083 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
6084 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
6085 | operands[6] = gen_label_rtx ();") | |
9db1d521 HP |
6086 | |
6087 | ; | |
6088 | ; negsi2 instruction pattern(s). | |
6089 | ; | |
6090 | ||
26a89301 UW |
6091 | (define_insn "*negsi2_cc" |
6092 | [(set (reg 33) | |
6093 | (compare (neg:SI (match_operand:SI 1 "register_operand" "d")) | |
6094 | (const_int 0))) | |
6095 | (set (match_operand:SI 0 "register_operand" "=d") | |
6096 | (neg:SI (match_dup 1)))] | |
6097 | "s390_match_ccmode (insn, CCAmode)" | |
6098 | "lcr\t%0,%1" | |
6099 | [(set_attr "op_type" "RR")]) | |
6100 | ||
6101 | (define_insn "*negsi2_cconly" | |
6102 | [(set (reg 33) | |
6103 | (compare (neg:SI (match_operand:SI 1 "register_operand" "d")) | |
6104 | (const_int 0))) | |
6105 | (clobber (match_scratch:SI 0 "=d"))] | |
6106 | "s390_match_ccmode (insn, CCAmode)" | |
6107 | "lcr\t%0,%1" | |
6108 | [(set_attr "op_type" "RR")]) | |
6109 | ||
9db1d521 HP |
6110 | (define_insn "negsi2" |
6111 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6112 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
6113 | (clobber (reg:CC 33))] | |
6114 | "" | |
d40c829f | 6115 | "lcr\t%0,%1" |
f2d3c02a | 6116 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
6117 | |
6118 | ; | |
6119 | ; negdf2 instruction pattern(s). | |
6120 | ; | |
6121 | ||
6122 | (define_expand "negdf2" | |
6123 | [(parallel | |
6124 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6125 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
6126 | (clobber (reg:CC 33))])] | |
6127 | "TARGET_HARD_FLOAT" | |
6128 | "") | |
6129 | ||
26a89301 UW |
6130 | (define_insn "*negdf2_cc" |
6131 | [(set (reg 33) | |
6132 | (compare (neg:DF (match_operand:DF 1 "register_operand" "f")) | |
6133 | (match_operand:DF 2 "const0_operand" ""))) | |
6134 | (set (match_operand:DF 0 "register_operand" "=f") | |
6135 | (neg:DF (match_dup 1)))] | |
6136 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6137 | "lcdbr\t%0,%1" | |
6138 | [(set_attr "op_type" "RRE") | |
6139 | (set_attr "type" "fsimpd")]) | |
6140 | ||
6141 | (define_insn "*negdf2_cconly" | |
6142 | [(set (reg 33) | |
6143 | (compare (neg:DF (match_operand:DF 1 "register_operand" "f")) | |
6144 | (match_operand:DF 2 "const0_operand" ""))) | |
6145 | (clobber (match_scratch:DF 0 "=f"))] | |
6146 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6147 | "lcdbr\t%0,%1" | |
6148 | [(set_attr "op_type" "RRE") | |
6149 | (set_attr "type" "fsimpd")]) | |
6150 | ||
9db1d521 HP |
6151 | (define_insn "*negdf2" |
6152 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6153 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
6154 | (clobber (reg:CC 33))] | |
6155 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6156 | "lcdbr\t%0,%1" |
077dab3b HP |
6157 | [(set_attr "op_type" "RRE") |
6158 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6159 | |
6160 | (define_insn "*negdf2_ibm" | |
6161 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6162 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
6163 | (clobber (reg:CC 33))] | |
6164 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6165 | "lcdr\t%0,%1" |
077dab3b HP |
6166 | [(set_attr "op_type" "RR") |
6167 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6168 | |
6169 | ; | |
6170 | ; negsf2 instruction pattern(s). | |
6171 | ; | |
6172 | ||
6173 | (define_expand "negsf2" | |
6174 | [(parallel | |
6175 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6176 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
6177 | (clobber (reg:CC 33))])] | |
6178 | "TARGET_HARD_FLOAT" | |
6179 | "") | |
6180 | ||
26a89301 UW |
6181 | (define_insn "*negsf2_cc" |
6182 | [(set (reg 33) | |
6183 | (compare (neg:SF (match_operand:SF 1 "register_operand" "f")) | |
6184 | (match_operand:SF 2 "const0_operand" ""))) | |
6185 | (set (match_operand:SF 0 "register_operand" "=f") | |
6186 | (neg:SF (match_dup 1)))] | |
6187 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6188 | "lcebr\t%0,%1" | |
6189 | [(set_attr "op_type" "RRE") | |
6190 | (set_attr "type" "fsimps")]) | |
6191 | ||
6192 | (define_insn "*negsf2_cconly" | |
6193 | [(set (reg 33) | |
6194 | (compare (neg:SF (match_operand:SF 1 "register_operand" "f")) | |
6195 | (match_operand:SF 2 "const0_operand" ""))) | |
6196 | (clobber (match_scratch:SF 0 "=f"))] | |
6197 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6198 | "lcebr\t%0,%1" | |
6199 | [(set_attr "op_type" "RRE") | |
6200 | (set_attr "type" "fsimps")]) | |
6201 | ||
9db1d521 HP |
6202 | (define_insn "*negsf2" |
6203 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6204 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
6205 | (clobber (reg:CC 33))] | |
6206 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6207 | "lcebr\t%0,%1" |
077dab3b HP |
6208 | [(set_attr "op_type" "RRE") |
6209 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
6210 | |
6211 | (define_insn "*negsf2" | |
6212 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6213 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
6214 | (clobber (reg:CC 33))] | |
6215 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6216 | "lcer\t%0,%1" |
077dab3b HP |
6217 | [(set_attr "op_type" "RR") |
6218 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
6219 | |
6220 | ||
6221 | ;; | |
6222 | ;;- Absolute value instructions. | |
6223 | ;; | |
6224 | ||
6225 | ; | |
6226 | ; absdi2 instruction pattern(s). | |
6227 | ; | |
6228 | ||
26a89301 UW |
6229 | (define_insn "*absdi2_sign_cc" |
6230 | [(set (reg 33) | |
6231 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6232 | (match_operand:SI 1 "register_operand" "d") 0) | |
6233 | (const_int 32)) (const_int 32))) | |
6234 | (const_int 0))) | |
6235 | (set (match_operand:DI 0 "register_operand" "=d") | |
6236 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
6237 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6238 | "lpgfr\t%0,%1" | |
6239 | [(set_attr "op_type" "RRE")]) | |
6240 | ||
6241 | (define_insn "*absdi2_sign" | |
6242 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6243 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
6244 | (clobber (reg:CC 33))] | |
6245 | "TARGET_64BIT" | |
6246 | "lpgfr\t%0,%1" | |
6247 | [(set_attr "op_type" "RRE")]) | |
6248 | ||
6249 | (define_insn "*absdi2_cc" | |
6250 | [(set (reg 33) | |
6251 | (compare (abs:DI (match_operand:DI 1 "register_operand" "d")) | |
6252 | (const_int 0))) | |
6253 | (set (match_operand:DI 0 "register_operand" "=d") | |
6254 | (abs:DI (match_dup 1)))] | |
6255 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6256 | "lpgr\t%0,%1" | |
6257 | [(set_attr "op_type" "RRE")]) | |
6258 | ||
6259 | (define_insn "*absdi2_cconly" | |
6260 | [(set (reg 33) | |
6261 | (compare (abs:DI (match_operand:DI 1 "register_operand" "d")) | |
6262 | (const_int 0))) | |
6263 | (clobber (match_scratch:DI 0 "=d"))] | |
6264 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6265 | "lpgr\t%0,%1" | |
6266 | [(set_attr "op_type" "RRE")]) | |
6267 | ||
9db1d521 HP |
6268 | (define_insn "absdi2" |
6269 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6270 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
6271 | (clobber (reg:CC 33))] | |
6272 | "TARGET_64BIT" | |
d40c829f | 6273 | "lpgr\t%0,%1" |
f2d3c02a | 6274 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
6275 | |
6276 | ; | |
6277 | ; abssi2 instruction pattern(s). | |
6278 | ; | |
6279 | ||
26a89301 UW |
6280 | (define_insn "*abssi2_cc" |
6281 | [(set (reg 33) | |
6282 | (compare (abs:SI (match_operand:SI 1 "register_operand" "d")) | |
6283 | (const_int 0))) | |
6284 | (set (match_operand:SI 0 "register_operand" "=d") | |
6285 | (abs:SI (match_dup 1)))] | |
6286 | "s390_match_ccmode (insn, CCAmode)" | |
6287 | "lpr\t%0,%1" | |
6288 | [(set_attr "op_type" "RR")]) | |
6289 | ||
6290 | (define_insn "*abssi2_cconly" | |
6291 | [(set (reg 33) | |
6292 | (compare (abs:SI (match_operand:SI 1 "register_operand" "d")) | |
6293 | (const_int 0))) | |
6294 | (clobber (match_scratch:SI 0 "=d"))] | |
6295 | "s390_match_ccmode (insn, CCAmode)" | |
6296 | "lpr\t%0,%1" | |
6297 | [(set_attr "op_type" "RR")]) | |
6298 | ||
9db1d521 HP |
6299 | (define_insn "abssi2" |
6300 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6301 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
6302 | (clobber (reg:CC 33))] | |
6303 | "" | |
d40c829f | 6304 | "lpr\t%0,%1" |
f2d3c02a | 6305 | [(set_attr "op_type" "RR")]) |
9db1d521 | 6306 | |
9db1d521 HP |
6307 | ; |
6308 | ; absdf2 instruction pattern(s). | |
6309 | ; | |
6310 | ||
6311 | (define_expand "absdf2" | |
6312 | [(parallel | |
6313 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6314 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6315 | (clobber (reg:CC 33))])] | |
6316 | "TARGET_HARD_FLOAT" | |
6317 | "") | |
6318 | ||
26a89301 UW |
6319 | (define_insn "*absdf2_cc" |
6320 | [(set (reg 33) | |
6321 | (compare (abs:DF (match_operand:DF 1 "register_operand" "f")) | |
6322 | (match_operand:DF 2 "const0_operand" ""))) | |
6323 | (set (match_operand:DF 0 "register_operand" "=f") | |
6324 | (abs:DF (match_dup 1)))] | |
6325 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6326 | "lpdbr\t%0,%1" | |
6327 | [(set_attr "op_type" "RRE") | |
6328 | (set_attr "type" "fsimpd")]) | |
6329 | ||
6330 | (define_insn "*absdf2_cconly" | |
6331 | [(set (reg 33) | |
6332 | (compare (abs:DF (match_operand:DF 1 "register_operand" "f")) | |
6333 | (match_operand:DF 2 "const0_operand" ""))) | |
6334 | (clobber (match_scratch:DF 0 "=f"))] | |
6335 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6336 | "lpdbr\t%0,%1" | |
6337 | [(set_attr "op_type" "RRE") | |
6338 | (set_attr "type" "fsimpd")]) | |
6339 | ||
9db1d521 HP |
6340 | (define_insn "*absdf2" |
6341 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6342 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6343 | (clobber (reg:CC 33))] | |
6344 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6345 | "lpdbr\t%0,%1" |
077dab3b HP |
6346 | [(set_attr "op_type" "RRE") |
6347 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6348 | |
6349 | (define_insn "*absdf2_ibm" | |
6350 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6351 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6352 | (clobber (reg:CC 33))] | |
6353 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6354 | "lpdr\t%0,%1" |
077dab3b HP |
6355 | [(set_attr "op_type" "RR") |
6356 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6357 | |
6358 | ; | |
6359 | ; abssf2 instruction pattern(s). | |
6360 | ; | |
6361 | ||
6362 | (define_expand "abssf2" | |
6363 | [(parallel | |
6364 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6365 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6366 | (clobber (reg:CC 33))])] | |
6367 | "TARGET_HARD_FLOAT" | |
6368 | "") | |
6369 | ||
26a89301 UW |
6370 | (define_insn "*abssf2_cc" |
6371 | [(set (reg 33) | |
6372 | (compare (abs:SF (match_operand:SF 1 "register_operand" "f")) | |
6373 | (match_operand:SF 2 "const0_operand" ""))) | |
6374 | (set (match_operand:SF 0 "register_operand" "=f") | |
6375 | (abs:SF (match_dup 1)))] | |
6376 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6377 | "lpebr\t%0,%1" | |
6378 | [(set_attr "op_type" "RRE") | |
6379 | (set_attr "type" "fsimps")]) | |
6380 | ||
6381 | (define_insn "*abssf2_cconly" | |
6382 | [(set (reg 33) | |
6383 | (compare (abs:SF (match_operand:SF 1 "register_operand" "f")) | |
6384 | (match_operand:SF 2 "const0_operand" ""))) | |
6385 | (clobber (match_scratch:SF 0 "=f"))] | |
6386 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6387 | "lpebr\t%0,%1" | |
6388 | [(set_attr "op_type" "RRE") | |
6389 | (set_attr "type" "fsimps")]) | |
6390 | ||
9db1d521 HP |
6391 | (define_insn "*abssf2" |
6392 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6393 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6394 | (clobber (reg:CC 33))] | |
6395 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6396 | "lpebr\t%0,%1" |
077dab3b HP |
6397 | [(set_attr "op_type" "RRE") |
6398 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
6399 | |
6400 | (define_insn "*abssf2_ibm" | |
6401 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6402 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6403 | (clobber (reg:CC 33))] | |
6404 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6405 | "lper\t%0,%1" |
077dab3b HP |
6406 | [(set_attr "op_type" "RR") |
6407 | (set_attr "type" "fsimps")]) | |
9db1d521 | 6408 | |
3ef093a8 AK |
6409 | ;; |
6410 | ;;- Negated absolute value instructions | |
6411 | ;; | |
6412 | ||
6413 | ; | |
6414 | ; Integer | |
6415 | ; | |
6416 | ||
26a89301 UW |
6417 | (define_insn "*negabsdi2_sign_cc" |
6418 | [(set (reg 33) | |
6419 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6420 | (match_operand:SI 1 "register_operand" "d") 0) | |
6421 | (const_int 32)) (const_int 32)))) | |
6422 | (const_int 0))) | |
6423 | (set (match_operand:DI 0 "register_operand" "=d") | |
6424 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6425 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6426 | "lngfr\t%0,%1" | |
6427 | [(set_attr "op_type" "RRE")]) | |
6428 | ||
6429 | (define_insn "*negabsdi2_sign" | |
6430 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6431 | (neg:DI (abs:DI (sign_extend:DI | |
6432 | (match_operand:SI 1 "register_operand" "d"))))) | |
3ef093a8 | 6433 | (clobber (reg:CC 33))] |
26a89301 UW |
6434 | "TARGET_64BIT" |
6435 | "lngfr\t%0,%1" | |
6436 | [(set_attr "op_type" "RRE")]) | |
3ef093a8 | 6437 | |
26a89301 UW |
6438 | (define_insn "*negabsdi2_cc" |
6439 | [(set (reg 33) | |
6440 | (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
6441 | (const_int 0))) | |
6442 | (set (match_operand:DI 0 "register_operand" "=d") | |
6443 | (neg:DI (abs:DI (match_dup 1))))] | |
6444 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6445 | "lngr\t%0,%1" | |
6446 | [(set_attr "op_type" "RRE")]) | |
6447 | ||
6448 | (define_insn "*negabsdi2_cconly" | |
6449 | [(set (reg 33) | |
6450 | (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
6451 | (const_int 0))) | |
6452 | (clobber (match_scratch:DI 0 "=d"))] | |
6453 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6454 | "lngr\t%0,%1" | |
6455 | [(set_attr "op_type" "RRE")]) | |
6456 | ||
3ef093a8 AK |
6457 | (define_insn "*negabsdi2" |
6458 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6459 | (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) | |
6460 | (clobber (reg:CC 33))] | |
6461 | "TARGET_64BIT" | |
d40c829f | 6462 | "lngr\t%0,%1" |
3ef093a8 AK |
6463 | [(set_attr "op_type" "RRE")]) |
6464 | ||
26a89301 UW |
6465 | (define_insn "*negabssi2_cc" |
6466 | [(set (reg 33) | |
6467 | (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
6468 | (const_int 0))) | |
6469 | (set (match_operand:SI 0 "register_operand" "=d") | |
6470 | (neg:SI (abs:SI (match_dup 1))))] | |
6471 | "s390_match_ccmode (insn, CCAmode)" | |
6472 | "lnr\t%0,%1" | |
6473 | [(set_attr "op_type" "RR")]) | |
6474 | ||
6475 | (define_insn "*negabssi2_cconly" | |
6476 | [(set (reg 33) | |
6477 | (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
6478 | (const_int 0))) | |
6479 | (clobber (match_scratch:SI 0 "=d"))] | |
6480 | "s390_match_ccmode (insn, CCAmode)" | |
6481 | "lnr\t%0,%1" | |
6482 | [(set_attr "op_type" "RR")]) | |
6483 | ||
6484 | (define_insn "*negabssi2" | |
6485 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6486 | (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) | |
6487 | (clobber (reg:CC 33))] | |
6488 | "" | |
6489 | "lnr\t%0,%1" | |
6490 | [(set_attr "op_type" "RR")]) | |
6491 | ||
3ef093a8 AK |
6492 | ; |
6493 | ; Floating point | |
6494 | ; | |
6495 | ||
26a89301 UW |
6496 | (define_insn "*negabsdf2_cc" |
6497 | [(set (reg 33) | |
6498 | (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6499 | (match_operand:DF 2 "const0_operand" ""))) | |
6500 | (set (match_operand:DF 0 "register_operand" "=f") | |
6501 | (neg:DF (abs:DF (match_dup 1))))] | |
6502 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6503 | "lndbr\t%0,%1" | |
3ef093a8 | 6504 | [(set_attr "op_type" "RRE") |
26a89301 UW |
6505 | (set_attr "type" "fsimpd")]) |
6506 | ||
6507 | (define_insn "*negabsdf2_cconly" | |
6508 | [(set (reg 33) | |
6509 | (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6510 | (match_operand:DF 2 "const0_operand" ""))) | |
6511 | (clobber (match_scratch:DF 0 "=f"))] | |
6512 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6513 | "lndbr\t%0,%1" | |
6514 | [(set_attr "op_type" "RRE") | |
6515 | (set_attr "type" "fsimpd")]) | |
6516 | ||
3ef093a8 AK |
6517 | (define_insn "*negabsdf2" |
6518 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6519 | (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) | |
6520 | (clobber (reg:CC 33))] | |
6521 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6522 | "lndbr\t%0,%1" |
3ef093a8 AK |
6523 | [(set_attr "op_type" "RRE") |
6524 | (set_attr "type" "fsimpd")]) | |
6525 | ||
26a89301 UW |
6526 | (define_insn "*negabssf2_cc" |
6527 | [(set (reg 33) | |
6528 | (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6529 | (match_operand:SF 2 "const0_operand" ""))) | |
6530 | (set (match_operand:SF 0 "register_operand" "=f") | |
6531 | (neg:SF (abs:SF (match_dup 1))))] | |
6532 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6533 | "lnebr\t%0,%1" | |
6534 | [(set_attr "op_type" "RRE") | |
6535 | (set_attr "type" "fsimps")]) | |
6536 | ||
6537 | (define_insn "*negabssf2_cconly" | |
6538 | [(set (reg 33) | |
6539 | (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6540 | (match_operand:SF 2 "const0_operand" ""))) | |
6541 | (clobber (match_scratch:SF 0 "=f"))] | |
6542 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6543 | "lnebr\t%0,%1" | |
6544 | [(set_attr "op_type" "RRE") | |
6545 | (set_attr "type" "fsimps")]) | |
6546 | ||
6547 | (define_insn "*negabssf2" | |
6548 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6549 | (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) | |
6550 | (clobber (reg:CC 33))] | |
6551 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6552 | "lnebr\t%0,%1" | |
6553 | [(set_attr "op_type" "RRE") | |
6554 | (set_attr "type" "fsimps")]) | |
6555 | ||
4023fb28 UW |
6556 | ;; |
6557 | ;;- Square root instructions. | |
6558 | ;; | |
6559 | ||
6560 | ; | |
6561 | ; sqrtdf2 instruction pattern(s). | |
6562 | ; | |
6563 | ||
6564 | (define_insn "sqrtdf2" | |
6565 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 6566 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6567 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6568 | "@ | |
d40c829f UW |
6569 | sqdbr\t%0,%1 |
6570 | sqdb\t%0,%1" | |
a036c6f7 UW |
6571 | [(set_attr "op_type" "RRE,RXE") |
6572 | (set_attr "type" "fsqrtd")]) | |
4023fb28 UW |
6573 | |
6574 | ; | |
6575 | ; sqrtsf2 instruction pattern(s). | |
6576 | ; | |
6577 | ||
6578 | (define_insn "sqrtsf2" | |
6579 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 6580 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6581 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6582 | "@ | |
d40c829f UW |
6583 | sqebr\t%0,%1 |
6584 | sqeb\t%0,%1" | |
a036c6f7 UW |
6585 | [(set_attr "op_type" "RRE,RXE") |
6586 | (set_attr "type" "fsqrts")]) | |
9db1d521 HP |
6587 | |
6588 | ;; | |
6589 | ;;- One complement instructions. | |
6590 | ;; | |
6591 | ||
6592 | ; | |
342cf42b | 6593 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 6594 | ; |
c7453384 | 6595 | |
342cf42b | 6596 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 6597 | [(parallel |
342cf42b AS |
6598 | [(set (match_operand:INT 0 "register_operand" "") |
6599 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
6600 | (const_int -1))) | |
4023fb28 | 6601 | (clobber (reg:CC 33))])] |
9db1d521 | 6602 | "" |
4023fb28 | 6603 | "") |
9db1d521 HP |
6604 | |
6605 | ||
6606 | ;; | |
6607 | ;;- Rotate instructions. | |
6608 | ;; | |
6609 | ||
6610 | ; | |
6611 | ; rotldi3 instruction pattern(s). | |
6612 | ; | |
6613 | ||
6614 | (define_insn "rotldi3" | |
ac32b25e UW |
6615 | [(set (match_operand:DI 0 "register_operand" "=d") |
6616 | (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
6617 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6618 | "TARGET_64BIT" |
ac32b25e | 6619 | "rllg\t%0,%1,%Y2" |
077dab3b HP |
6620 | [(set_attr "op_type" "RSE") |
6621 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6622 | |
6623 | ; | |
6624 | ; rotlsi3 instruction pattern(s). | |
6625 | ; | |
6626 | ||
6627 | (define_insn "rotlsi3" | |
ac32b25e UW |
6628 | [(set (match_operand:SI 0 "register_operand" "=d") |
6629 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
6630 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9e8327e3 | 6631 | "TARGET_CPU_ZARCH" |
ac32b25e | 6632 | "rll\t%0,%1,%Y2" |
077dab3b HP |
6633 | [(set_attr "op_type" "RSE") |
6634 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6635 | |
6636 | ||
6637 | ;; | |
6638 | ;;- Arithmetic shift instructions. | |
6639 | ;; | |
9db1d521 HP |
6640 | |
6641 | ; | |
6642 | ; ashldi3 instruction pattern(s). | |
6643 | ; | |
6644 | ||
6645 | (define_expand "ashldi3" | |
ecbe845e UW |
6646 | [(set (match_operand:DI 0 "register_operand" "") |
6647 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6648 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6649 | "" |
6650 | "") | |
6651 | ||
6652 | (define_insn "*ashldi3_31" | |
ac32b25e UW |
6653 | [(set (match_operand:DI 0 "register_operand" "=d") |
6654 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
6655 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6656 | "!TARGET_64BIT" |
ac32b25e | 6657 | "sldl\t%0,%Y2" |
077dab3b HP |
6658 | [(set_attr "op_type" "RS") |
6659 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6660 | |
6661 | (define_insn "*ashldi3_64" | |
ac32b25e UW |
6662 | [(set (match_operand:DI 0 "register_operand" "=d") |
6663 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
6664 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6665 | "TARGET_64BIT" |
ac32b25e | 6666 | "sllg\t%0,%1,%Y2" |
077dab3b HP |
6667 | [(set_attr "op_type" "RSE") |
6668 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6669 | |
6670 | ; | |
6671 | ; ashrdi3 instruction pattern(s). | |
6672 | ; | |
6673 | ||
6674 | (define_expand "ashrdi3" | |
6675 | [(parallel | |
6676 | [(set (match_operand:DI 0 "register_operand" "") | |
6677 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6678 | (match_operand:SI 2 "shift_count_operand" ""))) |
9db1d521 HP |
6679 | (clobber (reg:CC 33))])] |
6680 | "" | |
6681 | "") | |
6682 | ||
ecbe845e UW |
6683 | (define_insn "*ashrdi3_cc_31" |
6684 | [(set (reg 33) | |
ac32b25e UW |
6685 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6686 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6687 | (const_int 0))) |
ac32b25e | 6688 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6689 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6690 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6691 | "srda\t%0,%Y2" |
077dab3b HP |
6692 | [(set_attr "op_type" "RS") |
6693 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6694 | |
6695 | (define_insn "*ashrdi3_cconly_31" | |
6696 | [(set (reg 33) | |
ac32b25e UW |
6697 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6698 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6699 | (const_int 0))) |
ac32b25e | 6700 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6701 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6702 | "srda\t%0,%Y2" |
077dab3b HP |
6703 | [(set_attr "op_type" "RS") |
6704 | (set_attr "atype" "reg")]) | |
ecbe845e | 6705 | |
9db1d521 | 6706 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6707 | [(set (match_operand:DI 0 "register_operand" "=d") |
6708 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6709 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6710 | (clobber (reg:CC 33))] |
6711 | "!TARGET_64BIT" | |
ac32b25e | 6712 | "srda\t%0,%Y2" |
077dab3b HP |
6713 | [(set_attr "op_type" "RS") |
6714 | (set_attr "atype" "reg")]) | |
c7453384 | 6715 | |
ecbe845e UW |
6716 | (define_insn "*ashrdi3_cc_64" |
6717 | [(set (reg 33) | |
ac32b25e UW |
6718 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6719 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6720 | (const_int 0))) |
ac32b25e | 6721 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6722 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6723 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
ac32b25e | 6724 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6725 | [(set_attr "op_type" "RSE") |
6726 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6727 | |
6728 | (define_insn "*ashrdi3_cconly_64" | |
6729 | [(set (reg 33) | |
ac32b25e UW |
6730 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6731 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6732 | (const_int 0))) |
ac32b25e | 6733 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6734 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
ac32b25e | 6735 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6736 | [(set_attr "op_type" "RSE") |
6737 | (set_attr "atype" "reg")]) | |
ecbe845e | 6738 | |
9db1d521 | 6739 | (define_insn "*ashrdi3_64" |
ac32b25e UW |
6740 | [(set (match_operand:DI 0 "register_operand" "=d") |
6741 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6742 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6743 | (clobber (reg:CC 33))] |
6744 | "TARGET_64BIT" | |
ac32b25e | 6745 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6746 | [(set_attr "op_type" "RSE") |
6747 | (set_attr "atype" "reg")]) | |
6748 | ||
9db1d521 HP |
6749 | |
6750 | ; | |
6751 | ; ashlsi3 instruction pattern(s). | |
6752 | ; | |
9db1d521 HP |
6753 | |
6754 | (define_insn "ashlsi3" | |
ac32b25e UW |
6755 | [(set (match_operand:SI 0 "register_operand" "=d") |
6756 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
6757 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6758 | "" |
ac32b25e | 6759 | "sll\t%0,%Y2" |
077dab3b HP |
6760 | [(set_attr "op_type" "RS") |
6761 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6762 | |
6763 | ; | |
6764 | ; ashrsi3 instruction pattern(s). | |
6765 | ; | |
6766 | ||
ecbe845e UW |
6767 | (define_insn "*ashrsi3_cc" |
6768 | [(set (reg 33) | |
ac32b25e UW |
6769 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6770 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6771 | (const_int 0))) |
ac32b25e | 6772 | (set (match_operand:SI 0 "register_operand" "=d") |
ecbe845e UW |
6773 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
6774 | "s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6775 | "sra\t%0,%Y2" |
077dab3b HP |
6776 | [(set_attr "op_type" "RS") |
6777 | (set_attr "atype" "reg")]) | |
6778 | ||
ecbe845e UW |
6779 | |
6780 | (define_insn "*ashrsi3_cconly" | |
6781 | [(set (reg 33) | |
ac32b25e UW |
6782 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6783 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6784 | (const_int 0))) |
ac32b25e | 6785 | (clobber (match_scratch:SI 0 "=d"))] |
ecbe845e | 6786 | "s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6787 | "sra\t%0,%Y2" |
077dab3b HP |
6788 | [(set_attr "op_type" "RS") |
6789 | (set_attr "atype" "reg")]) | |
ecbe845e | 6790 | |
9db1d521 | 6791 | (define_insn "ashrsi3" |
ac32b25e UW |
6792 | [(set (match_operand:SI 0 "register_operand" "=d") |
6793 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6794 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6795 | (clobber (reg:CC 33))] |
6796 | "" | |
ac32b25e | 6797 | "sra\t%0,%Y2" |
077dab3b HP |
6798 | [(set_attr "op_type" "RS") |
6799 | (set_attr "atype" "reg")]) | |
9db1d521 | 6800 | |
9db1d521 HP |
6801 | |
6802 | ;; | |
6803 | ;;- logical shift instructions. | |
6804 | ;; | |
6805 | ||
6806 | ; | |
6807 | ; lshrdi3 instruction pattern(s). | |
6808 | ; | |
6809 | ||
6810 | (define_expand "lshrdi3" | |
ecbe845e UW |
6811 | [(set (match_operand:DI 0 "register_operand" "") |
6812 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6813 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6814 | "" |
6815 | "") | |
6816 | ||
6817 | (define_insn "*lshrdi3_31" | |
ac32b25e UW |
6818 | [(set (match_operand:DI 0 "register_operand" "=d") |
6819 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6820 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6821 | "!TARGET_64BIT" |
ac32b25e UW |
6822 | "srdl\t%0,%Y2" |
6823 | [(set_attr "op_type" "RS") | |
077dab3b | 6824 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6825 | |
6826 | (define_insn "*lshrdi3_64" | |
ac32b25e UW |
6827 | [(set (match_operand:DI 0 "register_operand" "=d") |
6828 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6829 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6830 | "TARGET_64BIT" |
ac32b25e UW |
6831 | "srlg\t%0,%1,%Y2" |
6832 | [(set_attr "op_type" "RSE") | |
077dab3b | 6833 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6834 | |
6835 | ; | |
6836 | ; lshrsi3 instruction pattern(s). | |
6837 | ; | |
6838 | ||
6839 | (define_insn "lshrsi3" | |
ac32b25e UW |
6840 | [(set (match_operand:SI 0 "register_operand" "=d") |
6841 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6842 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6843 | "" |
ac32b25e | 6844 | "srl\t%0,%Y2" |
077dab3b HP |
6845 | [(set_attr "op_type" "RS") |
6846 | (set_attr "atype" "reg")]) | |
9db1d521 | 6847 | |
9db1d521 HP |
6848 | |
6849 | ;; | |
6850 | ;; Branch instruction patterns. | |
6851 | ;; | |
6852 | ||
fa77b251 AS |
6853 | (define_expand "b<code>" |
6854 | [(set (pc) | |
6855 | (if_then_else (COMPARE (match_operand 0 "" "") | |
6856 | (const_int 0)) | |
6857 | (match_dup 0) | |
6858 | (pc)))] | |
ba956982 | 6859 | "" |
6590e19a | 6860 | "s390_emit_jump (operands[0], |
fa77b251 | 6861 | s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;") |
ba956982 | 6862 | |
9db1d521 HP |
6863 | |
6864 | ;; | |
6865 | ;;- Conditional jump instructions. | |
6866 | ;; | |
6867 | ||
6590e19a UW |
6868 | (define_insn "*cjump_64" |
6869 | [(set (pc) | |
6870 | (if_then_else | |
5b022de5 | 6871 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6872 | (label_ref (match_operand 0 "" "")) |
6873 | (pc)))] | |
6874 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6875 | { |
13e58269 | 6876 | if (get_attr_length (insn) == 4) |
d40c829f | 6877 | return "j%C1\t%l0"; |
6590e19a | 6878 | else |
d40c829f | 6879 | return "jg%C1\t%l0"; |
6590e19a UW |
6880 | } |
6881 | [(set_attr "op_type" "RI") | |
6882 | (set_attr "type" "branch") | |
6883 | (set (attr "length") | |
6884 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6885 | (const_int 4) (const_int 6)))]) | |
6886 | ||
6887 | (define_insn "*cjump_31" | |
6888 | [(set (pc) | |
6889 | (if_then_else | |
5b022de5 | 6890 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6891 | (label_ref (match_operand 0 "" "")) |
6892 | (pc)))] | |
6893 | "!TARGET_CPU_ZARCH" | |
6894 | { | |
6895 | if (get_attr_length (insn) == 4) | |
6896 | return "j%C1\t%l0"; | |
9db1d521 | 6897 | else |
13e58269 | 6898 | abort (); |
10bbf137 | 6899 | } |
9db1d521 | 6900 | [(set_attr "op_type" "RI") |
077dab3b | 6901 | (set_attr "type" "branch") |
13e58269 | 6902 | (set (attr "length") |
6590e19a UW |
6903 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6904 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6905 | (const_int 4) (const_int 6)) | |
6906 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6907 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6908 | |
f314b9b1 | 6909 | (define_insn "*cjump_long" |
6590e19a UW |
6910 | [(set (pc) |
6911 | (if_then_else | |
5b022de5 | 6912 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6913 | (match_operand 0 "address_operand" "U") |
6914 | (pc)))] | |
9db1d521 | 6915 | "" |
f314b9b1 UW |
6916 | { |
6917 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6918 | return "b%C1r\t%0"; |
f314b9b1 | 6919 | else |
d40c829f | 6920 | return "b%C1\t%a0"; |
10bbf137 | 6921 | } |
c7453384 | 6922 | [(set (attr "op_type") |
f314b9b1 UW |
6923 | (if_then_else (match_operand 0 "register_operand" "") |
6924 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 6925 | (set_attr "type" "branch") |
077dab3b | 6926 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6927 | |
6928 | ||
6929 | ;; | |
6930 | ;;- Negated conditional jump instructions. | |
6931 | ;; | |
6932 | ||
6590e19a UW |
6933 | (define_insn "*icjump_64" |
6934 | [(set (pc) | |
6935 | (if_then_else | |
5b022de5 | 6936 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6937 | (pc) |
6938 | (label_ref (match_operand 0 "" ""))))] | |
6939 | "TARGET_CPU_ZARCH" | |
c7453384 | 6940 | { |
13e58269 | 6941 | if (get_attr_length (insn) == 4) |
d40c829f | 6942 | return "j%D1\t%l0"; |
6590e19a | 6943 | else |
d40c829f | 6944 | return "jg%D1\t%l0"; |
6590e19a UW |
6945 | } |
6946 | [(set_attr "op_type" "RI") | |
6947 | (set_attr "type" "branch") | |
6948 | (set (attr "length") | |
6949 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6950 | (const_int 4) (const_int 6)))]) | |
6951 | ||
6952 | (define_insn "*icjump_31" | |
6953 | [(set (pc) | |
6954 | (if_then_else | |
5b022de5 | 6955 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6956 | (pc) |
6957 | (label_ref (match_operand 0 "" ""))))] | |
6958 | "!TARGET_CPU_ZARCH" | |
6959 | { | |
6960 | if (get_attr_length (insn) == 4) | |
6961 | return "j%D1\t%l0"; | |
9db1d521 | 6962 | else |
13e58269 | 6963 | abort (); |
10bbf137 | 6964 | } |
9db1d521 | 6965 | [(set_attr "op_type" "RI") |
077dab3b | 6966 | (set_attr "type" "branch") |
13e58269 | 6967 | (set (attr "length") |
6590e19a UW |
6968 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6969 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6970 | (const_int 4) (const_int 6)) | |
6971 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6972 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6973 | |
f314b9b1 | 6974 | (define_insn "*icjump_long" |
6590e19a UW |
6975 | [(set (pc) |
6976 | (if_then_else | |
5b022de5 | 6977 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
6978 | (pc) |
6979 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 6980 | "" |
f314b9b1 UW |
6981 | { |
6982 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6983 | return "b%D1r\t%0"; |
f314b9b1 | 6984 | else |
d40c829f | 6985 | return "b%D1\t%a0"; |
10bbf137 | 6986 | } |
c7453384 | 6987 | [(set (attr "op_type") |
f314b9b1 UW |
6988 | (if_then_else (match_operand 0 "register_operand" "") |
6989 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6990 | (set_attr "type" "branch") |
6991 | (set_attr "atype" "agen")]) | |
9db1d521 | 6992 | |
4456530d HP |
6993 | ;; |
6994 | ;;- Trap instructions. | |
6995 | ;; | |
6996 | ||
6997 | (define_insn "trap" | |
6998 | [(trap_if (const_int 1) (const_int 0))] | |
6999 | "" | |
d40c829f | 7000 | "j\t.+2" |
6590e19a | 7001 | [(set_attr "op_type" "RI") |
077dab3b | 7002 | (set_attr "type" "branch")]) |
4456530d HP |
7003 | |
7004 | (define_expand "conditional_trap" | |
6590e19a UW |
7005 | [(trap_if (match_operand 0 "comparison_operator" "") |
7006 | (match_operand 1 "general_operand" ""))] | |
4456530d | 7007 | "" |
4456530d | 7008 | { |
6590e19a UW |
7009 | if (operands[1] != const0_rtx) FAIL; |
7010 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
7011 | s390_compare_op0, s390_compare_op1); | |
10bbf137 | 7012 | }) |
4456530d HP |
7013 | |
7014 | (define_insn "*trap" | |
5b022de5 | 7015 | [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)]) |
4456530d HP |
7016 | (const_int 0))] |
7017 | "" | |
d40c829f | 7018 | "j%C0\t.+2"; |
077dab3b HP |
7019 | [(set_attr "op_type" "RI") |
7020 | (set_attr "type" "branch")]) | |
9db1d521 HP |
7021 | |
7022 | ;; | |
0a3bdf9d | 7023 | ;;- Loop instructions. |
9db1d521 | 7024 | ;; |
0a3bdf9d UW |
7025 | ;; This is all complicated by the fact that since this is a jump insn |
7026 | ;; we must handle our own output reloads. | |
c7453384 | 7027 | |
0a3bdf9d UW |
7028 | (define_expand "doloop_end" |
7029 | [(use (match_operand 0 "" "")) ; loop pseudo | |
7030 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
7031 | (use (match_operand 2 "" "")) ; max iterations | |
7032 | (use (match_operand 3 "" "")) ; loop level | |
7033 | (use (match_operand 4 "" ""))] ; label | |
7034 | "" | |
0a3bdf9d | 7035 | { |
6590e19a UW |
7036 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
7037 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
7038 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
7039 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
7040 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
7041 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
7042 | else | |
7043 | FAIL; | |
7044 | ||
7045 | DONE; | |
10bbf137 | 7046 | }) |
0a3bdf9d | 7047 | |
6590e19a | 7048 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
7049 | [(set (pc) |
7050 | (if_then_else | |
7051 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
7052 | (const_int 1)) | |
7053 | (label_ref (match_operand 0 "" "")) | |
7054 | (pc))) | |
bd446804 | 7055 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 7056 | (plus:SI (match_dup 1) (const_int -1))) |
eb862a88 | 7057 | (clobber (match_scratch:SI 3 "=X,&1")) |
0a3bdf9d | 7058 | (clobber (reg:CC 33))] |
6590e19a | 7059 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
7060 | { |
7061 | if (which_alternative != 0) | |
10bbf137 | 7062 | return "#"; |
0a3bdf9d | 7063 | else if (get_attr_length (insn) == 4) |
d40c829f | 7064 | return "brct\t%1,%l0"; |
6590e19a | 7065 | else |
545d16ff | 7066 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
7067 | } |
7068 | "&& reload_completed | |
7069 | && (! REG_P (operands[2]) | |
7070 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 7071 | [(parallel [(set (reg:CCAN 33) |
6590e19a UW |
7072 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
7073 | (const_int 0))) | |
7074 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7075 | (set (match_dup 2) (match_dup 3)) | |
7076 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
7077 | (label_ref (match_dup 0)) | |
7078 | (pc)))] | |
7079 | "" | |
7080 | [(set_attr "op_type" "RI") | |
7081 | (set_attr "type" "branch") | |
7082 | (set (attr "length") | |
7083 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7084 | (const_int 4) (const_int 10)))]) | |
7085 | ||
7086 | (define_insn_and_split "doloop_si31" | |
7087 | [(set (pc) | |
7088 | (if_then_else | |
7089 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
7090 | (const_int 1)) | |
7091 | (label_ref (match_operand 0 "" "")) | |
7092 | (pc))) | |
7093 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") | |
7094 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 7095 | (clobber (match_scratch:SI 3 "=X,&1")) |
6590e19a UW |
7096 | (clobber (reg:CC 33))] |
7097 | "!TARGET_CPU_ZARCH" | |
7098 | { | |
7099 | if (which_alternative != 0) | |
7100 | return "#"; | |
7101 | else if (get_attr_length (insn) == 4) | |
7102 | return "brct\t%1,%l0"; | |
0a3bdf9d UW |
7103 | else |
7104 | abort (); | |
10bbf137 | 7105 | } |
6590e19a UW |
7106 | "&& reload_completed |
7107 | && (! REG_P (operands[2]) | |
7108 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 7109 | [(parallel [(set (reg:CCAN 33) |
6590e19a UW |
7110 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
7111 | (const_int 0))) | |
7112 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7113 | (set (match_dup 2) (match_dup 3)) | |
7114 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
7115 | (label_ref (match_dup 0)) | |
7116 | (pc)))] | |
7117 | "" | |
0a3bdf9d | 7118 | [(set_attr "op_type" "RI") |
077dab3b | 7119 | (set_attr "type" "branch") |
0a3bdf9d | 7120 | (set (attr "length") |
6590e19a UW |
7121 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7122 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7123 | (const_int 4) (const_int 6)) | |
7124 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7125 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7126 | |
0a3bdf9d UW |
7127 | (define_insn "*doloop_si_long" |
7128 | [(set (pc) | |
7129 | (if_then_else | |
7130 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
7131 | (const_int 1)) | |
d3632d41 | 7132 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
7133 | (pc))) |
7134 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
7135 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 7136 | (clobber (match_scratch:SI 3 "=X,&1")) |
0a3bdf9d | 7137 | (clobber (reg:CC 33))] |
6590e19a | 7138 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
7139 | { |
7140 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7141 | return "bctr\t%1,%0"; |
0a3bdf9d | 7142 | else |
d40c829f | 7143 | return "bct\t%1,%a0"; |
10bbf137 | 7144 | } |
c7453384 | 7145 | [(set (attr "op_type") |
0a3bdf9d UW |
7146 | (if_then_else (match_operand 0 "register_operand" "") |
7147 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7148 | (set_attr "type" "branch") |
7149 | (set_attr "atype" "agen")]) | |
0a3bdf9d | 7150 | |
6590e19a | 7151 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
7152 | [(set (pc) |
7153 | (if_then_else | |
7154 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
7155 | (const_int 1)) | |
7156 | (label_ref (match_operand 0 "" "")) | |
7157 | (pc))) | |
eb862a88 | 7158 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 7159 | (plus:DI (match_dup 1) (const_int -1))) |
eb862a88 | 7160 | (clobber (match_scratch:DI 3 "=X,&1")) |
0a3bdf9d UW |
7161 | (clobber (reg:CC 33))] |
7162 | "TARGET_64BIT" | |
0a3bdf9d UW |
7163 | { |
7164 | if (which_alternative != 0) | |
10bbf137 | 7165 | return "#"; |
0a3bdf9d | 7166 | else if (get_attr_length (insn) == 4) |
d40c829f | 7167 | return "brctg\t%1,%l0"; |
0a3bdf9d | 7168 | else |
545d16ff | 7169 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 7170 | } |
6590e19a | 7171 | "&& reload_completed |
0a3bdf9d UW |
7172 | && (! REG_P (operands[2]) |
7173 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 7174 | [(parallel [(set (reg:CCAN 33) |
0a3bdf9d UW |
7175 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
7176 | (const_int 0))) | |
7177 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
7178 | (set (match_dup 2) (match_dup 3)) | |
7179 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6590e19a | 7180 | (label_ref (match_dup 0)) |
0a3bdf9d | 7181 | (pc)))] |
6590e19a UW |
7182 | "" |
7183 | [(set_attr "op_type" "RI") | |
7184 | (set_attr "type" "branch") | |
7185 | (set (attr "length") | |
7186 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7187 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
7188 | |
7189 | ;; | |
7190 | ;;- Unconditional jump instructions. | |
7191 | ;; | |
7192 | ||
7193 | ; | |
7194 | ; jump instruction pattern(s). | |
7195 | ; | |
7196 | ||
6590e19a UW |
7197 | (define_expand "jump" |
7198 | [(match_operand 0 "" "")] | |
9db1d521 | 7199 | "" |
6590e19a UW |
7200 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
7201 | ||
7202 | (define_insn "*jump64" | |
7203 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7204 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7205 | { |
13e58269 | 7206 | if (get_attr_length (insn) == 4) |
d40c829f | 7207 | return "j\t%l0"; |
6590e19a | 7208 | else |
d40c829f | 7209 | return "jg\t%l0"; |
6590e19a UW |
7210 | } |
7211 | [(set_attr "op_type" "RI") | |
7212 | (set_attr "type" "branch") | |
7213 | (set (attr "length") | |
7214 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7215 | (const_int 4) (const_int 6)))]) | |
7216 | ||
7217 | (define_insn "*jump31" | |
7218 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7219 | "!TARGET_CPU_ZARCH" | |
7220 | { | |
7221 | if (get_attr_length (insn) == 4) | |
7222 | return "j\t%l0"; | |
9db1d521 | 7223 | else |
13e58269 | 7224 | abort (); |
10bbf137 | 7225 | } |
9db1d521 | 7226 | [(set_attr "op_type" "RI") |
077dab3b | 7227 | (set_attr "type" "branch") |
13e58269 | 7228 | (set (attr "length") |
6590e19a UW |
7229 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7230 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7231 | (const_int 4) (const_int 6)) | |
7232 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7233 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
7234 | |
7235 | ; | |
7236 | ; indirect-jump instruction pattern(s). | |
7237 | ; | |
7238 | ||
7239 | (define_insn "indirect_jump" | |
d3632d41 | 7240 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 7241 | "" |
f314b9b1 UW |
7242 | { |
7243 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7244 | return "br\t%0"; |
f314b9b1 | 7245 | else |
d40c829f | 7246 | return "b\t%a0"; |
10bbf137 | 7247 | } |
c7453384 | 7248 | [(set (attr "op_type") |
f314b9b1 UW |
7249 | (if_then_else (match_operand 0 "register_operand" "") |
7250 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7251 | (set_attr "type" "branch") |
7252 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7253 | |
7254 | ; | |
f314b9b1 | 7255 | ; casesi instruction pattern(s). |
9db1d521 HP |
7256 | ; |
7257 | ||
f314b9b1 | 7258 | (define_insn "casesi_jump" |
d3632d41 | 7259 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 7260 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 7261 | "" |
9db1d521 | 7262 | { |
f314b9b1 | 7263 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 7264 | return "br\t%0"; |
f314b9b1 | 7265 | else |
d40c829f | 7266 | return "b\t%a0"; |
10bbf137 | 7267 | } |
c7453384 | 7268 | [(set (attr "op_type") |
f314b9b1 UW |
7269 | (if_then_else (match_operand 0 "register_operand" "") |
7270 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7271 | (set_attr "type" "branch") |
7272 | (set_attr "atype" "agen")]) | |
9db1d521 | 7273 | |
f314b9b1 UW |
7274 | (define_expand "casesi" |
7275 | [(match_operand:SI 0 "general_operand" "") | |
7276 | (match_operand:SI 1 "general_operand" "") | |
7277 | (match_operand:SI 2 "general_operand" "") | |
7278 | (label_ref (match_operand 3 "" "")) | |
7279 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 7280 | "" |
f314b9b1 UW |
7281 | { |
7282 | rtx index = gen_reg_rtx (SImode); | |
7283 | rtx base = gen_reg_rtx (Pmode); | |
7284 | rtx target = gen_reg_rtx (Pmode); | |
7285 | ||
7286 | emit_move_insn (index, operands[0]); | |
7287 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
7288 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 7289 | operands[4]); |
f314b9b1 UW |
7290 | |
7291 | if (Pmode != SImode) | |
7292 | index = convert_to_mode (Pmode, index, 1); | |
7293 | if (GET_CODE (index) != REG) | |
7294 | index = copy_to_mode_reg (Pmode, index); | |
7295 | ||
7296 | if (TARGET_64BIT) | |
7297 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
7298 | else | |
a556fd39 | 7299 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 7300 | |
f314b9b1 UW |
7301 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
7302 | ||
542a8afa | 7303 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
7304 | emit_move_insn (target, index); |
7305 | ||
7306 | if (flag_pic) | |
7307 | target = gen_rtx_PLUS (Pmode, base, target); | |
7308 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
7309 | ||
7310 | DONE; | |
10bbf137 | 7311 | }) |
9db1d521 HP |
7312 | |
7313 | ||
7314 | ;; | |
7315 | ;;- Jump to subroutine. | |
7316 | ;; | |
7317 | ;; | |
7318 | ||
7319 | ; | |
7320 | ; untyped call instruction pattern(s). | |
7321 | ; | |
7322 | ||
7323 | ;; Call subroutine returning any type. | |
7324 | (define_expand "untyped_call" | |
7325 | [(parallel [(call (match_operand 0 "" "") | |
7326 | (const_int 0)) | |
7327 | (match_operand 1 "" "") | |
7328 | (match_operand 2 "" "")])] | |
7329 | "" | |
9db1d521 HP |
7330 | { |
7331 | int i; | |
7332 | ||
7333 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
7334 | ||
7335 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7336 | { | |
7337 | rtx set = XVECEXP (operands[2], 0, i); | |
7338 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7339 | } | |
7340 | ||
7341 | /* The optimizer does not know that the call sets the function value | |
7342 | registers we stored in the result block. We avoid problems by | |
7343 | claiming that all hard registers are used and clobbered at this | |
7344 | point. */ | |
7345 | emit_insn (gen_blockage ()); | |
7346 | ||
7347 | DONE; | |
10bbf137 | 7348 | }) |
9db1d521 HP |
7349 | |
7350 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7351 | ;; all of memory. This blocks insns from being moved across this point. | |
7352 | ||
7353 | (define_insn "blockage" | |
10bbf137 | 7354 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 7355 | "" |
4023fb28 | 7356 | "" |
d5869ca0 UW |
7357 | [(set_attr "type" "none") |
7358 | (set_attr "length" "0")]) | |
4023fb28 | 7359 | |
9db1d521 | 7360 | ; |
ed9676cf | 7361 | ; sibcall patterns |
9db1d521 HP |
7362 | ; |
7363 | ||
ed9676cf | 7364 | (define_expand "sibcall" |
44b8152b | 7365 | [(call (match_operand 0 "" "") |
ed9676cf | 7366 | (match_operand 1 "" ""))] |
9db1d521 | 7367 | "" |
9db1d521 | 7368 | { |
ed9676cf AK |
7369 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
7370 | DONE; | |
7371 | }) | |
9db1d521 | 7372 | |
ed9676cf AK |
7373 | (define_insn "*sibcall_br" |
7374 | [(call (mem:QI (reg 1)) | |
7375 | (match_operand 0 "const_int_operand" "n"))] | |
2f7e5a0d | 7376 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7377 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
7378 | "br\t%%r1" | |
7379 | [(set_attr "op_type" "RR") | |
7380 | (set_attr "type" "branch") | |
7381 | (set_attr "atype" "agen")]) | |
9db1d521 | 7382 | |
ed9676cf AK |
7383 | (define_insn "*sibcall_brc" |
7384 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7385 | (match_operand 1 "const_int_operand" "n"))] | |
7386 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7387 | "j\t%0" | |
7388 | [(set_attr "op_type" "RI") | |
7389 | (set_attr "type" "branch")]) | |
9db1d521 | 7390 | |
ed9676cf AK |
7391 | (define_insn "*sibcall_brcl" |
7392 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7393 | (match_operand 1 "const_int_operand" "n"))] | |
7394 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7395 | "jg\t%0" | |
7396 | [(set_attr "op_type" "RIL") | |
7397 | (set_attr "type" "branch")]) | |
44b8152b | 7398 | |
ed9676cf AK |
7399 | ; |
7400 | ; sibcall_value patterns | |
7401 | ; | |
9e8327e3 | 7402 | |
ed9676cf AK |
7403 | (define_expand "sibcall_value" |
7404 | [(set (match_operand 0 "" "") | |
7405 | (call (match_operand 1 "" "") | |
7406 | (match_operand 2 "" "")))] | |
7407 | "" | |
7408 | { | |
7409 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 7410 | DONE; |
10bbf137 | 7411 | }) |
9db1d521 | 7412 | |
ed9676cf AK |
7413 | (define_insn "*sibcall_value_br" |
7414 | [(set (match_operand 0 "" "") | |
7415 | (call (mem:QI (reg 1)) | |
7416 | (match_operand 1 "const_int_operand" "n")))] | |
2f7e5a0d | 7417 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7418 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
7419 | "br\t%%r1" | |
7420 | [(set_attr "op_type" "RR") | |
7421 | (set_attr "type" "branch") | |
7422 | (set_attr "atype" "agen")]) | |
7423 | ||
7424 | (define_insn "*sibcall_value_brc" | |
7425 | [(set (match_operand 0 "" "") | |
7426 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7427 | (match_operand 2 "const_int_operand" "n")))] | |
7428 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7429 | "j\t%1" | |
7430 | [(set_attr "op_type" "RI") | |
7431 | (set_attr "type" "branch")]) | |
7432 | ||
7433 | (define_insn "*sibcall_value_brcl" | |
7434 | [(set (match_operand 0 "" "") | |
7435 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7436 | (match_operand 2 "const_int_operand" "n")))] | |
7437 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7438 | "jg\t%1" | |
7439 | [(set_attr "op_type" "RIL") | |
7440 | (set_attr "type" "branch")]) | |
7441 | ||
7442 | ||
7443 | ; | |
7444 | ; call instruction pattern(s). | |
7445 | ; | |
7446 | ||
7447 | (define_expand "call" | |
7448 | [(call (match_operand 0 "" "") | |
7449 | (match_operand 1 "" "")) | |
7450 | (use (match_operand 2 "" ""))] | |
44b8152b | 7451 | "" |
ed9676cf | 7452 | { |
2f7e5a0d | 7453 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
7454 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
7455 | DONE; | |
7456 | }) | |
44b8152b | 7457 | |
9e8327e3 UW |
7458 | (define_insn "*bras" |
7459 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7460 | (match_operand 1 "const_int_operand" "n")) | |
7461 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7462 | "!SIBLING_CALL_P (insn) |
7463 | && TARGET_SMALL_EXEC | |
ed9676cf | 7464 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 7465 | "bras\t%2,%0" |
9db1d521 | 7466 | [(set_attr "op_type" "RI") |
4023fb28 | 7467 | (set_attr "type" "jsr")]) |
9db1d521 | 7468 | |
9e8327e3 UW |
7469 | (define_insn "*brasl" |
7470 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7471 | (match_operand 1 "const_int_operand" "n")) | |
7472 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7473 | "!SIBLING_CALL_P (insn) |
7474 | && TARGET_CPU_ZARCH | |
ed9676cf | 7475 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7476 | "brasl\t%2,%0" |
7477 | [(set_attr "op_type" "RIL") | |
077dab3b | 7478 | (set_attr "type" "jsr")]) |
9db1d521 | 7479 | |
9e8327e3 UW |
7480 | (define_insn "*basr" |
7481 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
7482 | (match_operand 1 "const_int_operand" "n")) | |
7483 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 7484 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7485 | { |
7486 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7487 | return "basr\t%2,%0"; | |
7488 | else | |
7489 | return "bas\t%2,%a0"; | |
7490 | } | |
7491 | [(set (attr "op_type") | |
7492 | (if_then_else (match_operand 0 "register_operand" "") | |
7493 | (const_string "RR") (const_string "RX"))) | |
7494 | (set_attr "type" "jsr") | |
7495 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7496 | |
7497 | ; | |
7498 | ; call_value instruction pattern(s). | |
7499 | ; | |
7500 | ||
7501 | (define_expand "call_value" | |
44b8152b UW |
7502 | [(set (match_operand 0 "" "") |
7503 | (call (match_operand 1 "" "") | |
7504 | (match_operand 2 "" ""))) | |
7505 | (use (match_operand 3 "" ""))] | |
9db1d521 | 7506 | "" |
9db1d521 | 7507 | { |
2f7e5a0d | 7508 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 7509 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 7510 | DONE; |
10bbf137 | 7511 | }) |
9db1d521 | 7512 | |
9e8327e3 | 7513 | (define_insn "*bras_r" |
c19ec8f9 | 7514 | [(set (match_operand 0 "" "") |
9e8327e3 | 7515 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7516 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 7517 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
7518 | "!SIBLING_CALL_P (insn) |
7519 | && TARGET_SMALL_EXEC | |
ed9676cf | 7520 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7521 | "bras\t%3,%1" |
9db1d521 | 7522 | [(set_attr "op_type" "RI") |
f2d3c02a | 7523 | (set_attr "type" "jsr")]) |
9db1d521 | 7524 | |
9e8327e3 | 7525 | (define_insn "*brasl_r" |
c19ec8f9 | 7526 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7527 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7528 | (match_operand 2 "const_int_operand" "n"))) | |
7529 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
7530 | "!SIBLING_CALL_P (insn) |
7531 | && TARGET_CPU_ZARCH | |
ed9676cf | 7532 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7533 | "brasl\t%3,%1" |
7534 | [(set_attr "op_type" "RIL") | |
077dab3b | 7535 | (set_attr "type" "jsr")]) |
9db1d521 | 7536 | |
9e8327e3 | 7537 | (define_insn "*basr_r" |
c19ec8f9 | 7538 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7539 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7540 | (match_operand 2 "const_int_operand" "n"))) | |
7541 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 7542 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7543 | { |
7544 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7545 | return "basr\t%3,%1"; | |
7546 | else | |
7547 | return "bas\t%3,%a1"; | |
7548 | } | |
7549 | [(set (attr "op_type") | |
7550 | (if_then_else (match_operand 1 "register_operand" "") | |
7551 | (const_string "RR") (const_string "RX"))) | |
7552 | (set_attr "type" "jsr") | |
7553 | (set_attr "atype" "agen")]) | |
9db1d521 | 7554 | |
fd3cd001 UW |
7555 | ;; |
7556 | ;;- Thread-local storage support. | |
7557 | ;; | |
7558 | ||
c5aa1d12 UW |
7559 | (define_expand "get_tp_64" |
7560 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))] | |
fd3cd001 | 7561 | "TARGET_64BIT" |
c5aa1d12 | 7562 | "") |
fd3cd001 | 7563 | |
c5aa1d12 UW |
7564 | (define_expand "get_tp_31" |
7565 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))] | |
fd3cd001 | 7566 | "!TARGET_64BIT" |
c5aa1d12 | 7567 | "") |
fd3cd001 | 7568 | |
c5aa1d12 UW |
7569 | (define_expand "set_tp_64" |
7570 | [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" "")) | |
ca11b3fb | 7571 | (set (reg:DI 36) (unspec_volatile:DI [(reg:DI 36)] UNSPECV_SET_TP))] |
fd3cd001 | 7572 | "TARGET_64BIT" |
c5aa1d12 | 7573 | "") |
fd3cd001 | 7574 | |
c5aa1d12 UW |
7575 | (define_expand "set_tp_31" |
7576 | [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" "")) | |
ca11b3fb | 7577 | (set (reg:SI 36) (unspec_volatile:SI [(reg:SI 36)] UNSPECV_SET_TP))] |
fd3cd001 | 7578 | "!TARGET_64BIT" |
c5aa1d12 UW |
7579 | "") |
7580 | ||
7581 | (define_insn "*set_tp" | |
ca11b3fb | 7582 | [(set (reg 36) (unspec_volatile [(reg 36)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
7583 | "" |
7584 | "" | |
7585 | [(set_attr "type" "none") | |
7586 | (set_attr "length" "0")]) | |
c7453384 | 7587 | |
fd3cd001 UW |
7588 | (define_insn "*tls_load_64" |
7589 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7590 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7591 | (match_operand:DI 2 "" "")] | |
7592 | UNSPEC_TLS_LOAD))] | |
7593 | "TARGET_64BIT" | |
d40c829f | 7594 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7595 | [(set_attr "op_type" "RXE")]) |
7596 | ||
7597 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7598 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7599 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7600 | (match_operand:SI 2 "" "")] |
7601 | UNSPEC_TLS_LOAD))] | |
7602 | "!TARGET_64BIT" | |
d3632d41 | 7603 | "@ |
d40c829f UW |
7604 | l\t%0,%1%J2 |
7605 | ly\t%0,%1%J2" | |
d3632d41 | 7606 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 | 7607 | |
9e8327e3 | 7608 | (define_insn "*bras_tls" |
c19ec8f9 | 7609 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7610 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7611 | (match_operand 2 "const_int_operand" "n"))) | |
7612 | (clobber (match_operand 3 "register_operand" "=r")) | |
7613 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7614 | "!SIBLING_CALL_P (insn) |
7615 | && TARGET_SMALL_EXEC | |
ed9676cf | 7616 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7617 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7618 | [(set_attr "op_type" "RI") |
7619 | (set_attr "type" "jsr")]) | |
7620 | ||
9e8327e3 | 7621 | (define_insn "*brasl_tls" |
c19ec8f9 | 7622 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7623 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7624 | (match_operand 2 "const_int_operand" "n"))) | |
7625 | (clobber (match_operand 3 "register_operand" "=r")) | |
7626 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7627 | "!SIBLING_CALL_P (insn) |
7628 | && TARGET_CPU_ZARCH | |
ed9676cf | 7629 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7630 | "brasl\t%3,%1%J4" |
7631 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7632 | (set_attr "type" "jsr")]) |
7633 | ||
9e8327e3 | 7634 | (define_insn "*basr_tls" |
c19ec8f9 | 7635 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7636 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7637 | (match_operand 2 "const_int_operand" "n"))) | |
7638 | (clobber (match_operand 3 "register_operand" "=r")) | |
7639 | (use (match_operand 4 "" ""))] | |
ed9676cf | 7640 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7641 | { |
7642 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7643 | return "basr\t%3,%1%J4"; | |
7644 | else | |
7645 | return "bas\t%3,%a1%J4"; | |
7646 | } | |
7647 | [(set (attr "op_type") | |
7648 | (if_then_else (match_operand 1 "register_operand" "") | |
7649 | (const_string "RR") (const_string "RX"))) | |
7650 | (set_attr "type" "jsr") | |
7651 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7652 | |
9db1d521 HP |
7653 | ;; |
7654 | ;;- Miscellaneous instructions. | |
7655 | ;; | |
7656 | ||
7657 | ; | |
7658 | ; allocate stack instruction pattern(s). | |
7659 | ; | |
7660 | ||
7661 | (define_expand "allocate_stack" | |
ef44a6ff UW |
7662 | [(match_operand 0 "general_operand" "") |
7663 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 7664 | "TARGET_BACKCHAIN" |
9db1d521 | 7665 | { |
ef44a6ff | 7666 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 7667 | |
ef44a6ff UW |
7668 | emit_move_insn (temp, s390_back_chain_rtx ()); |
7669 | anti_adjust_stack (operands[1]); | |
7670 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 7671 | |
ef44a6ff UW |
7672 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
7673 | DONE; | |
10bbf137 | 7674 | }) |
9db1d521 HP |
7675 | |
7676 | ||
7677 | ; | |
43ab026f | 7678 | ; setjmp instruction pattern. |
9db1d521 HP |
7679 | ; |
7680 | ||
9db1d521 | 7681 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7682 | [(match_operand 0 "" "")] |
f314b9b1 | 7683 | "flag_pic" |
9db1d521 | 7684 | { |
585539a1 | 7685 | emit_insn (s390_load_got ()); |
fd7643fb | 7686 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
9db1d521 | 7687 | DONE; |
fd7643fb | 7688 | }) |
9db1d521 | 7689 | |
9db1d521 HP |
7690 | ;; These patterns say how to save and restore the stack pointer. We need not |
7691 | ;; save the stack pointer at function level since we are careful to | |
7692 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7693 | ;; when we restore the stack pointer. | |
7694 | ;; | |
7695 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7696 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7697 | ;; save area is a memory location. | |
7698 | ||
7699 | (define_expand "save_stack_function" | |
7700 | [(match_operand 0 "general_operand" "") | |
7701 | (match_operand 1 "general_operand" "")] | |
7702 | "" | |
7703 | "DONE;") | |
7704 | ||
7705 | (define_expand "restore_stack_function" | |
7706 | [(match_operand 0 "general_operand" "") | |
7707 | (match_operand 1 "general_operand" "")] | |
7708 | "" | |
7709 | "DONE;") | |
7710 | ||
7711 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
7712 | [(match_operand 0 "register_operand" "") |
7713 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 7714 | "TARGET_BACKCHAIN" |
9db1d521 | 7715 | { |
ef44a6ff UW |
7716 | rtx temp = gen_reg_rtx (Pmode); |
7717 | ||
7718 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
7719 | emit_move_insn (operands[0], operands[1]); | |
7720 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7721 | ||
7722 | DONE; | |
10bbf137 | 7723 | }) |
9db1d521 HP |
7724 | |
7725 | (define_expand "save_stack_nonlocal" | |
7726 | [(match_operand 0 "memory_operand" "") | |
7727 | (match_operand 1 "register_operand" "")] | |
7728 | "" | |
9db1d521 | 7729 | { |
ef44a6ff UW |
7730 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
7731 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
7732 | ||
7733 | /* Copy the backchain to the first word, sp to the second and the | |
7734 | literal pool base to the third. */ | |
7735 | ||
b3d31392 | 7736 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7737 | { |
7738 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
7739 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
7740 | } | |
7741 | ||
7742 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
7743 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 7744 | |
9db1d521 | 7745 | DONE; |
10bbf137 | 7746 | }) |
9db1d521 HP |
7747 | |
7748 | (define_expand "restore_stack_nonlocal" | |
7749 | [(match_operand 0 "register_operand" "") | |
7750 | (match_operand 1 "memory_operand" "")] | |
7751 | "" | |
9db1d521 | 7752 | { |
ef44a6ff | 7753 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 7754 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 7755 | rtx temp = NULL_RTX; |
9db1d521 | 7756 | |
43ab026f | 7757 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 7758 | literal pool base from the third. */ |
43ab026f | 7759 | |
b3d31392 | 7760 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7761 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
7762 | ||
7763 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
7764 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
7765 | ||
7766 | if (temp) | |
7767 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7768 | ||
7769 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
9db1d521 | 7770 | DONE; |
10bbf137 | 7771 | }) |
9db1d521 HP |
7772 | |
7773 | ||
7774 | ; | |
7775 | ; nop instruction pattern(s). | |
7776 | ; | |
7777 | ||
7778 | (define_insn "nop" | |
7779 | [(const_int 0)] | |
7780 | "" | |
d40c829f | 7781 | "lr\t0,0" |
9db1d521 HP |
7782 | [(set_attr "op_type" "RR")]) |
7783 | ||
7784 | ||
7785 | ; | |
7786 | ; Special literal pool access instruction pattern(s). | |
7787 | ; | |
7788 | ||
416cf582 UW |
7789 | (define_insn "*pool_entry" |
7790 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7791 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7792 | "" |
9db1d521 | 7793 | { |
416cf582 UW |
7794 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7795 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 7796 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
7797 | return ""; |
7798 | } | |
b628bd8e | 7799 | [(set (attr "length") |
416cf582 | 7800 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 7801 | |
9bb86f41 UW |
7802 | (define_insn "pool_align" |
7803 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
7804 | UNSPECV_POOL_ALIGN)] | |
7805 | "" | |
7806 | ".align\t%0" | |
b628bd8e | 7807 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 7808 | |
9bb86f41 UW |
7809 | (define_insn "pool_section_start" |
7810 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
7811 | "" | |
7812 | ".section\t.rodata" | |
b628bd8e | 7813 | [(set_attr "length" "0")]) |
b2ccb744 | 7814 | |
9bb86f41 UW |
7815 | (define_insn "pool_section_end" |
7816 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
7817 | "" | |
b2ccb744 | 7818 | ".previous" |
b628bd8e | 7819 | [(set_attr "length" "0")]) |
b2ccb744 | 7820 | |
5af2f3d3 | 7821 | (define_insn "main_base_31_small" |
9e8327e3 UW |
7822 | [(set (match_operand 0 "register_operand" "=a") |
7823 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7824 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7825 | "basr\t%0,0" |
7826 | [(set_attr "op_type" "RR") | |
7827 | (set_attr "type" "la")]) | |
7828 | ||
7829 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
7830 | [(set (match_operand 0 "register_operand" "=a") |
7831 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 7832 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 7833 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
7834 | "bras\t%0,%2" |
7835 | [(set_attr "op_type" "RI")]) | |
7836 | ||
7837 | (define_insn "main_base_64" | |
9e8327e3 UW |
7838 | [(set (match_operand 0 "register_operand" "=a") |
7839 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7840 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7841 | "larl\t%0,%1" |
7842 | [(set_attr "op_type" "RIL") | |
7843 | (set_attr "type" "larl")]) | |
7844 | ||
7845 | (define_insn "main_pool" | |
585539a1 UW |
7846 | [(set (match_operand 0 "register_operand" "=a") |
7847 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
7848 | "GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 | 7849 | "* abort ();" |
b628bd8e | 7850 | [(set (attr "type") |
ea77e738 UW |
7851 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
7852 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 7853 | |
aee4e0db | 7854 | (define_insn "reload_base_31" |
9e8327e3 UW |
7855 | [(set (match_operand 0 "register_operand" "=a") |
7856 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7857 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7858 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
7859 | [(set_attr "length" "6") |
7860 | (set_attr "type" "la")]) | |
b2ccb744 | 7861 | |
aee4e0db | 7862 | (define_insn "reload_base_64" |
9e8327e3 UW |
7863 | [(set (match_operand 0 "register_operand" "=a") |
7864 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7865 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7866 | "larl\t%0,%1" |
aee4e0db | 7867 | [(set_attr "op_type" "RIL") |
077dab3b | 7868 | (set_attr "type" "larl")]) |
aee4e0db | 7869 | |
aee4e0db | 7870 | (define_insn "pool" |
fd7643fb | 7871 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db UW |
7872 | "" |
7873 | "* abort ();" | |
b628bd8e | 7874 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 7875 | |
4023fb28 UW |
7876 | ;; |
7877 | ;; Insns related to generating the function prologue and epilogue. | |
7878 | ;; | |
7879 | ||
7880 | ||
7881 | (define_expand "prologue" | |
7882 | [(use (const_int 0))] | |
7883 | "" | |
10bbf137 | 7884 | "s390_emit_prologue (); DONE;") |
4023fb28 | 7885 | |
2f7e5a0d EC |
7886 | (define_insn "prologue_tpf" |
7887 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE) | |
7888 | (clobber (reg:DI 1))] | |
3839e36a | 7889 | "TARGET_TPF_PROFILING" |
9e811ecd JT |
7890 | "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064" |
7891 | [(set_attr "length" "14")]) | |
2f7e5a0d | 7892 | |
4023fb28 UW |
7893 | (define_expand "epilogue" |
7894 | [(use (const_int 1))] | |
7895 | "" | |
ed9676cf AK |
7896 | "s390_emit_epilogue (false); DONE;") |
7897 | ||
2f7e5a0d EC |
7898 | (define_insn "epilogue_tpf" |
7899 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE) | |
7900 | (clobber (reg:DI 1))] | |
3839e36a | 7901 | "TARGET_TPF_PROFILING" |
9e811ecd JT |
7902 | "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070" |
7903 | [(set_attr "length" "14")]) | |
2f7e5a0d | 7904 | |
ed9676cf AK |
7905 | (define_expand "sibcall_epilogue" |
7906 | [(use (const_int 0))] | |
7907 | "" | |
7908 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 7909 | |
9e8327e3 | 7910 | (define_insn "*return" |
4023fb28 | 7911 | [(return) |
9e8327e3 UW |
7912 | (use (match_operand 0 "register_operand" "a"))] |
7913 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7914 | "br\t%0" |
4023fb28 | 7915 | [(set_attr "op_type" "RR") |
c7453384 | 7916 | (set_attr "type" "jsr") |
077dab3b | 7917 | (set_attr "atype" "agen")]) |
4023fb28 | 7918 | |
4023fb28 | 7919 | |
c7453384 | 7920 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 7921 | ;; pointer. This is used for compatibility. |
c7453384 EC |
7922 | |
7923 | (define_expand "ptr_extend" | |
7924 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7925 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7926 | "TARGET_64BIT" |
c7453384 | 7927 | { |
c7453384 EC |
7928 | emit_insn (gen_anddi3 (operands[0], |
7929 | gen_lowpart (DImode, operands[1]), | |
7930 | GEN_INT (0x7fffffff))); | |
c7453384 | 7931 | DONE; |
10bbf137 | 7932 | }) |
4798630c D |
7933 | |
7934 | ;; Instruction definition to expand eh_return macro to support | |
7935 | ;; swapping in special linkage return addresses. | |
7936 | ||
7937 | (define_expand "eh_return" | |
7938 | [(use (match_operand 0 "register_operand" ""))] | |
7939 | "TARGET_TPF" | |
7940 | { | |
7941 | s390_emit_tpf_eh_return (operands[0]); | |
7942 | DONE; | |
7943 | }) | |
7944 |